Apple A1181, K36C Schematics

TABLE_TABLEOFCONTENTS_ITEM

APPLE INC.

6

DESIGNER

DESCRIPTION OF CHANGE

REV.

A

D

C

B

A

D

C

B

8 7

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

TITLE

DRAWING NUMBER

SHT

OF

METRIC

DRAFTER

ENG APPD

QA APPD

RELEASE

DESIGN CK

MFG APPD

SCALE

NONE

MATERIAL/FINISH

NOTED AS

APPLICABLE

SIZE

D

THIRD ANGLE PROJECTION

DIMENSIONS ARE IN MILLIMETERS

XX

X.XX

X.XXX

DO NOT SCALE DRAWING

REV

ZONE

ECN

CK APPD

DATE

ENG APPD

DATE

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

ANGLES

TABLE_TABLEOFCONTENTS_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

Schematic / PCB #’s

K36C MLB SCHEMATIC

APR/10/2009

051-8089

SCHEM,MLB,K36C

109

?

02 691395

04/09/09

1

02

ENGINEERING RELEASED

K36B_MLB

39

08/17/2008

46

External USB Connectors

SCHEM,MLB,K36C

051-8089 CRITICAL

1 SCH

820-2496

PCBF,MLB,K36B

CRITICAL

PCB1

24

08/17/2008

25

K36B_MLB

MCP Standard Decoupling

23

08/17/2008

24

K36B_MLB

MCP79 A01 Silicon Support

3

08/17/2008

3

K36B_MLB

Power Block Diagram

7

08/17/2008

7

K36B_MLB

FUNC TEST

8

K36B_MLB

Power Aliases

2

08/17/2008

2

K36B_MLB

System Block Diagram

4

08/17/2008

4

K36B_MLB

CONFIGURATION OPTIONS

37

(MASTER)

43

K36B_MLB

FireWire Ports

36

08/17/2008

42

K36B_MLB

FireWire Port Power

35

08/17/2008

41

K36B_MLB

FireWire LLC/PHY(FW643E)

34

04/04/2008

39

SUMA

ETHERNET CONNECTOR

33

04/04/2008

38

SUMA

Ethernet & AirPort Support

32

03/20/2008

37

SUMA

Ethernet PHY (RTL8211CL)

31

08/17/2008

34

K36B_MLB

Right Clutch Connector

30

08/17/2008

33

K36B_MLB

Memory Active Termination

29

08/17/2008

32

K36B_MLB

DDR2 SO-DIMM Connector B

28

08/17/2008

31

K36B_MLB

DDR2 SO-DIMM Connector A

27

08/17/2008

29

K36B_MLB

FSB/DDR2 VREF MARGINING

26

08/17/2008

28

K36B_MLB

SB Misc

25

08/17/2008

26

K36B_MLB

MCP Graphics Support

22

08/17/2008

22

K36B_MLB

MCP Power & Ground

21

08/17/2008

21

K36B_MLB

MCP HDA & MISC

20

08/17/2008

20

K36B_MLB

MCP SATA & USB

19

08/17/2008

19

K36B_MLB

MCP PCI & LPC

18

08/17/2008

18

K36B_MLB

MCP Ethernet & Graphics

17

08/17/2008

17

K36B_MLB

MCP PCIe Interfaces

16

08/17/2008

16

K36B_MLB

MCP Memory Misc

15

08/17/2008

15

K36B_MLB

MCP Memory Interface

14

08/17/2008

14

K36B_MLB

MCP CPU Interface

13

01/08/2008

13

M99_MLB

eXtended Debug Port(MiniXDP)

12

08/17/2008

12

K36B_MLB

CPU Decoupling

11

08/17/2008

11

K36B_MLB

CPU Power & Ground

10

08/18/2008

10

K36B_MLB

CPU FSB

9

K36B_MLB

SIGNAL ALIAS

6

08/17//2008

6

K36B_MLB

JTAG Scan Chain

5

K36B_MLB

Revision History

K36B_MLB

76

08/17/2008

109

K36B RULE DEFINITIONS

K36B_MLB

75

08/17/2008

106

SMC Constraints

K36B_MLB

74

08/17/2008

105

FireWire Constraints

K36B_MLB

73

08/17/2008

104

Ethernet Constraints

K36B_MLB

72

08/17/2008

103

MCP Constraints 2

K36B_MLB

71

08/17/2008

102

MCP Constraints 1

K36B_MLB

70

08/17/2008

101

Memory Constraints

K36B_MLB

69

08/17/2008

100

CPU/FSB Constraints

K36B_MLB

68

08/17/2008

94

MINI-DVI CONNECTOR

K36B_MLB

67

08/17/2008

93

TMDS ALIASES

K36B_MLB

66

08/17/2008

90

INVERTER,LVDS

K36B_MLB

65

08/17/2008

79

POWER FETS

K36B_MLB

64

08/17/2008

78

POWER SEQUENCING

K36B_MLB

63

08/17/2008

77

MISC POWER SUPPLIES

K36B_MLB

62

08/17/2008

76

CPU VTT(1.05V) SUPPLY

K36B_MLB

61

08/17/2008

75

MCP VCORE REGULATOR

K36B_MLB

60

08/17/2008

74

IMVP6 CPU VCore Regulator

K36B_MLB

59

08/17/2008

73

1.8V/0.9V DDR2 SUPPLY

K36B_MLB

58

08/17/2008

72

5V/3.3V SUPPLY

K36B_MLB

57

08/17/2008

70

PBUS Supply/Battery Charger

RAYMOND

56

08/17/2008

69

DC-In & Battery Connectors

K36A_MLB

55

08/29/2008

68

AUDIO: JACK TRANSLATORS

K36A_MLB

54

08/29/2008

67

AUDIO: JACK

K36A_MLB

53

08/29/2008

66

AUDI0: SPEAKER AMP

K36A_MLB

52

08/29/2008

62

AUDIO: CODEC

K36B_MLB

51

081/17/2008

61

SPI ROM

K36B_MLB

50

08/17/2008

59

SMS

K36B_MLB

49

08/17/2008

58

GEYSER

K36B_MLB

48

08/17/2008

56

Fan

K36B_MLB

47

08/17/2008

55

Thermal Sensors

K36B_MLB

46

08/17/2008

54

Current Sensing

K36B_MLB

45

08/17/2008

53

VOLTAGE SENSING

K36B_MLB

44

08/17/2008

52

SMBUS CONNECTIONS

K36B_MLB

43

08/17/2008

51

LPC+SPI Debug Connector

K36B_MLB

42

08/17/2008

50

SMC Support

K36B_MLB

41

08/17/2008

49

SMC

K36B_MLB

40

07/17/2008

48

Front Flex Support

Date

(.csa)

Page

Contents

Page

Date

(.csa)

Contents

K36B_MLB

38

08/17/2008

45

SATA Connectors

1

08/22/2007

1

K36BH_MLB

Table of Contents

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

FW643E

LVDS OUT

HDMI OUT

SYNTH

CLK

CONN

PG 71

J9401

MINI DVI

U4100

PCI-E

FIREWIRE

DIMM’s

Boot ROM

SPI

J3100,3200

J5520

J5601

U4900

J4600,4601J9001J4501J5800J4810

U6610,6620,6630U6801

Speaker

PG 57

Amps

J3900

U3700

J9001

J4500

J4501

2.X OR 3.X GHZ

J1300

XDP CONN

INTEL CPU

PG 25,26

EXTERNAL

USB

Connectors

PG 39

SMB

CONN

88E1116

AirPort

SMB

1 2

PG 40

KEYBOARD

TRACKPAD/

CAMERA

IR

MINI PCI-E

J4300

FW PORT

Conn

J3400

3GHZ.

PG 38

ODD

Conn

800/1067/1333 MHz

PG 14

DIMM

PG 37

E-NET

PG 33

Conn

PG 28

PG 16

UP TO 20 LANES3

30

PG 20

NVIDIA

Bluetooth

(UP TO 12 DEVICES)

FSB INTERFACE

MEMORY

PG 52

CONN

DP OUT

LVDS

PG 71

DVI OUT

TMDS OUT

PG 17

PG 18

(UP TO FOUR PORTS)

PCI

PCI-E

4

CTRL

SATA

Conns

PG 41

MCP79

PG 19

LPC

8 9

PG 40

SATA

PG 59

Audio

FSB

64-Bit

POWER SUPPLY

PG 31

GB

J6950

PG 12

U1000

PG 40

HD

E-NET

Conn

U6100

PG 40

USB

PG 45

POWER SENSE

PG 48,49

DC/BATT

PENRYN

SPI

PG 18

MAIN

TEMP SENSOR

FAN CONN AND CONTROL

J5100

PG 43

Ser

FanADC

SMC

B,0

Prt

BSB

PWR

Misc

Port80,serial

LPC Conn

GPIOs

SATA

RGB OUT

PG 38

PG 13

PG 24

PG 20

HDA

PG 41

PG 44

5 6 7

U1400

PG 17

RGMII

PG 60

PG 9

PG 20

PG 35

Amp

PG 56

Line Out

Codec

Audio

PG 53

Amp

U6200

J6800,6801,6802,6803

HEADPHONE

PG 55

U6801

2 UDIMMs

DDR2-800MHZ

SYNC_MASTER=K36B_MLB SYNC_DATE=08/17/2008

02

2

109

System Block Diagram

051-8089

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

PP1V5_S0_FET

P1V5_S0_PGOOD

16-3

P1V5S0_EN

EN

PVIN

1.5V (S0)

TPS62510

U7740

VOUT

19-1

05

(4A MAX CURRENT)

PP3V3_S5_REG

(4A MAX

VOUT1

ENTRIP2

SMC_PM_G2_EN

2418

17 06

13

01

02

07

02

09

08

28

PPVCORE_S0_CPU_REG

PP1V05_S5_REG

5V

(RT)

EN1

VOUT2

Q7910

Q3810

P3V3S0_EN

PG

U7750

(44A MAX CURRENT)

PP1V05_S0_FET

03

PBUS SUPPLY/

PM_RSMRST_L

PM_PWRBTN_L SMC_RESET_L

SLP_S4_L(P94)

CPUVTTS0_PGOOD

TPS51116

U7300

=DDRVTT_EN

=DDRREG_EN

04-1

SMC

VREG3

CPUVTTS0_PGOOD

PP4V6_AUDIO_ANALOG

ENTRIP1

P1V05_S5_EN

U7400

VR_ON

IMVP_VR_ON

LT3470

VOUT

PP3V42_G3H_REG

U1400

P5VLTS3_EN

S3

0.9V

VOUT1

PP3V3_S0

16-3

RC

AP_PWR_EN

PP1V05_S0

LTC2909

VIN

SMC_ADAPTER_EN

S0PGOOD_PWROK

U7870

Q7930

PP3V3_S0_FET

11-2

PPVCORE_S0_MCP

12

PP0V9_S0_REG

02

MCPCORES0_EN

MCP_CORE

11-2

PPVCORE_S0_MCP_REG_R

16-4

16-2

16-3

16-1

16-2

RC

DELAY

15

16

11-1

11

PM_SLP_S4_L

11-3

PCI_RESET0#

MCP79

RC

(S0)

BATT_POS_F

DDRREG_EN

J6950

P3V3S3_EN

DELAY

SMC_CPU_VSENSE

PPCPUVTT_S0_REG

RC

CPU VCORE

11-1

VIN

VOUT

A

P3V3S3_EN

09-1

25

CPU_PWRGD

PWRGD(P12)

RSMRST_PWRGD

10

PWRBTN*

U6201

ALL_SYS_PWRGD

V

4.6V AUDIO

U5403

32

SMC

RSMRST_OUT(P15)

IMVP_VR_ON(P16)

IMVP_VR_ON

30

29

PPVBAT_G3H_CHGR_OUT

MCP79

RSMRST*

PWRGOOD

RESET*

MAX8902A

99ms DLY

U1000

CPU

VOUT

PPBUS_G3H

26

U7000

ISL6258A

SMC PWRGD

SMC_RESET_L

RN5VD30A-F

CPUVTT

MCP_PS_PWRGD

U1400

U2850

PPBUS_G3H

CHGR_BGATE

04

PS_PWRGD

DCIN(16.5V)

U5000

EN_PSV

02

(9 TO 12.6V)

BATTERY CHARGER

RC

SMC_BATT_ISENSE

PBUS_VSENSE

U6990

CPUVTTS0_EN

(S5)

ENABLES

VIN

A

02

PPVIN_G3H_P3V42G3H

(S0)

01

TPS51117

Q7050

SMC_DCIN_ISENSE

(1.05V)

6A FUSE

R7955

U7600

PGOOD

D6905

U4900

SLP_S3_L

RST*

SLP_S5_L SLP_S4_L

EN

EN2

PP5VLT_S3_REG

VOUT2

U7500

5V (LT)

VOUT

A

1.8V

EN2

VIN

EN1

P5VLTS3_EN

PBUSVSENS_EN

RC

DELAY

3S2P

DELAY

RC

DELAY

RC

DELAY

SLP_S5_L(P95)

RSMRST_IN(P13)

3.3V

TPS51125

DELAY

(1A MAX CURRENT)

16-2

20

02

VOUT2

S5

(S0)

P1V05S0_EN

U4900

P60

(S5)

P3V3S0_EN

P5VRTS0_EN_L

(S0)

SLP_S3#

DELAY

16-2

U7200

PM_SLP_S3_L

PP3V3_S5

PP3V3_S3_FET

P5V3V3_PGOOD

PM_SLP_S3_L

MCPCORES0_EN

CPUVTTS0_EN

MCPDDR_EN

P1V5S0_EN

RST*

1.8V S0

CHGR_EN

AC

ADAPTER

IN

PPVBAT_G3H_CHGR_REG

SHDN*

3.425V G3HOT

VIN

Q5315

V

D6905

VIN

22

LPC_RESET0*

(8A MAX CURRENT)

CPUPWRGD

LPC_RESET_L

29-1

09-1

CPU_RESET#

7A FUSE

31

Q3805

PM_WLAN_EN_L

Q3805

P16

Q7800

PGOOD

IN

PP5VLT_S3_REG

SMC_LRESET_L

SEL ADJ1 ADJ2

PP1V8_S0

(23A MAX CURRENT)

(4.5A MAX CURRENT)

SN0802043

PP5V_LT_S3_PGOOD MCPCORES0_PGOOD

PP5VLT_S3

MCPCORES0_PGOOD

P5V_LT_S3_PGOOD

P1V5_S0_PGOOD

P5V3V3_PGOOD

04-1

EN

VOUT1

PGOOD1

PGOOD2

SLP_S3_L(P93)

SMC_ONOFF_L

OVT

PWR_BUTTON(P90)

P17(BTN_OUT)

K36B POWER SYSTEM ARCHITECTURE

25

PVIN

TPS62510

1.05V (S5)

PP1V8_S3_REG

14

(12A MAX CURRENT)

(Q7901 & Q7971)

FETS

R5490

S3 TO S0

21

P3V3_ENET_FET

PP1V8_S0_REG

P3V3ENET_EN_L

FL7700

21

R5490

PP1V5_S0PP1V5_S0_FET

PP1V8_S0_FET

CURRENT)

PP5VRT_S0_REG

P1V05_S5_PGOOD

VOUT

VR_PWRGOOD_DELAY

SMC_CPU_ISENSE

PGOOD

ISL9504B

VIN

109

3

SYNC_DATE=08/17/2008

02

SYNC_MASTER=K36B_MLB

Power Block Diagram

051-8089

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

TABLE_ALT_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

TABLE_ALT_ITEM

TABLE_5_ITEM

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

ALTERNATES OPTION

BOM OPTION

BOARD STACK-UP AND CONSTRUCTION

(NONE)

BOTTOM

11

10

9

8

7

6

5

4

3

2

SIGNAL(High Speed)

POWER

SIGNAL(High Speed)

POWER

GROUND

SIGNAL

SIGNAL(High Speed)

SIGNAL

GROUND

(NONE)

BOM options provided by this page:

Top

Signal aliases required by this page:

Power aliases required by this page:

Page Notes

ALL

ALTERNATE PER CYNDI

152S0516152S0874

ALTERNATE PER CYNDI

ALL

152S0586152S0847

ALTERNATE PER CYNDI

ALL

152S0694 152S0138

ALL

ALTERNATE PER CYNDI

152S0685152S0796

CRITICAL

J6700

1

514-0667

CONN,RCPT,3.5MM AUDIO OUT,R/A

J3900

CONN,RCPT,RJ45,NO FILTER,8P1

CRITICAL

514-0668

CONN,RCPT,USB,4P,MIDPLANE

514-0669

1

J4601

CRITICAL

J6750

CRITICAL

CONN,RCPT,3.5MM AUDIO IN,R/A

1

514-0666

ALL

ALTERNATE PER CYNDI

157S0055157S0058

ALTERNATE PER CYNDI

152S0693152S0778

ALL

514-0665

J9401

CRITICAL

1

CONN,RCPT,MINI-DVI,32P,R/A

U3700

IC,RTL8251CA-VB-GR,GIGE TRANSCEIVER,48P

CRITICAL

1

338S0694

341S2420

CRITICAL1SMC_PROG

IC,SMC,HS8/2117,9X9MM,TLP,HF,BLANK

U4900

341S2418

1

CRITICAL

BOOTROM_PROG

IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP

U6100

341S2093

CRITICAL

1

IC, CYPRESS, CY7C63833

U4800

338S0654

1

CRITICAL

IC,FW643E,1394B PHY/OHCI LINK/PCI-E,127

U4100

LBL,P/N LABEL,PCB,28MMX6MM

1

CRITICAL

826-4393

[EEE:3TN]

337S3769

PDC,SLGVT,2.26,25W,1066,R0,3M,BGA,P7750

U1000

CRITICAL

1

CRITICAL

U1400

IC,GMCP,MCP79,35X35MM,BGA1437,B031

338S0702

J4600

CONN,RCPT,USB,4P,MIDPLANE

1

514-0669

CRITICAL

128S0093

ALTERNATE PER CYNDI

ALL

128S0218

051-8089

CONFIGURATION OPTIONS

SYNC_DATE=08/17/2008

109

02

4

SYNC_MASTER=K36B_MLB

PAGE_BORDER=TRUE

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

- CHANGE R1440 TO 150_5% AND NO STUFF

- RTC FOLLOW M97 DESIGN AND USE SUPERCAP SOLUTION

- MCP S0 PWRGD FOLLOW M97 DESIGN

- R2872 CHANGE TO 0OHM

- J6700 CHANGE FROM 514-0521 TO 514-0667

- DELETE L4502, NET SATA_HDD_D2R_UF_P / SATA_HDD_D2R_UF_N

- J3900 CHANGE FROM 514-0523 TO 514-0668

- J9401 CHANGE FROM 514-0517 TO 514-0665

- J6950 CHANGE FROM 516S0620 TO 516S0735

*****2008/11/06*****

- U5413 CHANGE FROM 353S1432 TO 353S2220

- R7417 CHANGE FROM 5.36K(114S0289) TO 4.42K(114S0280)

*****2008/11/12*****

- U1000 CHANGE FROM 373S3646 TO 373S3702

- NETNAME ENET_INTR_L CHANGE TO TP_ENET_INTR_L.

- DELETE R1987,R1988,R1995,R1970,R1971,R1972,R1973,R1996,R1997,R1998,R1999,R1978,R1979

- NET LVDSMUX_SEL_IG_L SYNC M97 NETNAME

- REMOVE NET DIMM_OVERTEMPA_L

- REMOVE NET DIMM_OVERTEMPA_L PAGE 42:

- ADD SMC_EXCARD_PWR_EN TO TP_SMC_EXCARD_PWR_EN

- ADD SMC_RSTGATE_L TO TP_SMC_RSTGATE_L

- ADD ALS_GAIN TO NC_ALS_GAIN

- PULL R3240 DOWN TO GND. PULL R3241 HIGH

- C6832, C6833 CHANGE FROM 127S0062 TO 127S0108

- L4501 / Fl4520 / FL4525 CHANGE FROM 155S0303 TO 155S0371

- DELETE PHYSICAL/SPACING SETTING OF SATA_HDD_D2R_UF_P / SATA_HDD_D2R_UF_N

PAGE 4:

PAGE 68:

PAGE 62:

*****2008/10/31*****

PAGE 41:

*****2008/08/25***** CHANGE CSA BASE ON WILL’S SUGGESTION.

- NET DPMUX_SEL_IG_L SYNC M97 NETNAME

- NET DPMUX_LOWPWR_L SYNC M97 NETNAME AUD_IPHS_SWITCH_EN

- ENET_PWRDWN_L CHANGE TO TP_ENET_PWRDWN_L

(FOLLOW M97 DESIGN).

*****2008/10/30*****

- J6950 516S0735 CHANGE TO 516S0620

PAGE 69:

- C7321 FROM 128S0111(POLY) CHANGE TO 128S0218 (POLY,CASE-D2E-SM)

- XDP FOLLOW M97 DESIGN. CONNECTOR FROM 998-1571 CHANGE TO 516S0625.

- C7040/C7041/C7047 CHANGE TO 138S0614

- L9002 CHANGE TO 116S0004(0ohm,5%,0402)

- C9003 CHANGE TO 116S0004(0ohm,5%,0402)

NOTE: All page numbers are .csa, not PDF. See page 1 for .csa -> PDF mapping.

- STUFF C5250/C5251/C5270/C5271/C5260/C5261/C5280/C5281

- J6700 514-0604 CHANGE TO HF APN 514-0521

- I2C_ALS_SDA CHANGE TO I2C_MINI_PCIE_SDA

- I2C_ALS_SCL CHANGE TO I2C_MINI_PCIE_SCL

- ADD C5250/C5251/C5270/C5271/C5260/C5261/C5280/C5281 131S1104 (22pF,5%,0402) NO STUFF

- J3400 516S0635 CHANGE TO HF APN 516S0729

- R2825/R2826 CHANGE TO 116s0004 (0 OHM,5%,0402)

- R1950/R1951/R1952/1953 CHANGE TO 116s0004 (0 OHM,5%,0402)

- TEXT "ALS" CHANGE TO "MINI-PCIE"

- J6750 514-0603 CHANGE TO HF APN 514-0519

- J6950 516S0620 CHANGE TO HF APN 516S0735

*****2008/10/25*****

PAGE 52:

- TP_RTL8211_CLK125 CHANGE TO RTL8211_CLK125

- ADD R3731 (116s0026 22 ohm 5% 0402) FOR EMI 125MHZ NOISE

- C6830/C6831 CHANGE TO APN 128S0220, and REMOVE BOMOPTION OMIT

- C6605 CHANGE TO APN 128s0148, HF APN 128s0221, and REMOVE BOMOPTION OMIT

- C6601/C6603 CHANGE TO APN 128S0135, and REMOVE BOMOPTION OMIT

PAGE 67:

PAGE 69:

- C7281, C7241, C7272 FROM 138S0555(603) CHANGE TO 138S0615(603-1)

- C7291, C7292, C7252, C7251 FROM 128S0115(POLY,CASE-B2) CHANGE TO

- Q7400, Q7402 FROM 376S0472 CHANGE TO 376S0617.

- C7280, C7240 FROM 128S0092(POLY) CHANGE TO 128S0128(POLY-TANT)

PAGE 9:

- ADD ESTARLDO_EN TO NC_ESTARLDO_EN

PAGE 29:

PAGE 28:

Revision History

PLAGE 23:

- CHANGE XDP_TDO_CONN TO XDP_TDO

PAGE 29:

PAGE 14:

- R7859 CHANGE TO 100 OHM.

PAGE 64:

PAGE 61:

PAGE 39:

PAGE 32,33,34

PAGE 44:

PAGE 68:

*****2008/08/23*****

PAGE 6:

- REMOVE ETHERNET CIRCUIT.

PAGE 9:

- REMOVE R3400, R3401

- L3401 FROM NO STUFF CHANGE TO STUFF. PAGE 39

PAGE 41:

PAGE 46:

- SMC_NB_CORE_ISENSE CHANGE TO SMC_MCP_CORE_ISENSE

- R5417 ADD BOM OPTION FOR NO STUFF

PAGE 50:

- ADD C5926 (10UF,20%.0603) TO =PP3V3_S3_SMS PAGE 63:

PAGE 66:

- REMOVE R9010, R9011 *****2008/08/24***** PAGE 6:

PAGE 13:

- =P3V3ENET_EN_L LINK TO PM_SLP_RMGT_L

- ADD =RTL8211_ENSWRE LINK TO GND.

- DELETE R4699.

PAGE 8:

- REMOVE USB_PWR_EN_S3

PAGE 31:

PAGE 13:

- =P1V05ENET_EN LINK TO PM_SLP_RMGT_L

- DELETE R2400~R2413 FOR MCP A01 VERSION.

- SMC_NB_CORE_ISENSE CHANGE TO SMC_MCP_CORE_ISENSE

- SMC_NB_DDR_ISENSE CHANGE TO SMC_MCP_DDR_ISENSE

- R4690 FROM NO STUFF CHANGE TO STUFF.

- R5416 ADD BOM OPTION FOR NO STUFF

- SMC_NB_DDR_ISENSE CHANGE TO SMC_MCP_DDR_ISENSE

PAGE 10:

- ADD =RTL8211_REGOUT LINK TO NC_RTL8211_REGOUT.

- C7601 FROM 138S0578 CHANGE TO 138S0614.

- Q7620 FROM 376S0512 CHANGE TO 376S0652.

PAGE 62:

- C7560 FROM 128S0092 CHANGE TO 128S0218.

- Q7500 FROM 376S0512 CHANGE TO 376S0652.

- L7500 FROM 152S0869 CHANGE TO 152S0685.

PAGE 61:

- XW7400 ADD BOMOPTION OMIT.

PAGE 60:

- C7343 FROM 128S0073 CHANGE TO 128S0233.

PAGE 59:

PAGE 18:

PAGE 25:

PAG3 35:

PAGE 58:

- Q7260, Q7261 FROM 376S0512 CHANGE TO 376S0652 (H-F)

128S0222(POLY,CASE-B2-SM)

PAGE 57:

PAGE 65:

*****2008/08/22*****

- R1410 CHANGE TO 49.9 OHM

- ADD =PP3V42_G3H_RTC_D LINK TO =PP3V42_G3H_REG

PAGE 8:

PAGE 7:

- R7011 CHANGE TO 9.31K OHM, 1%

*****2008/08/21*****

- R7879 CHANGE TO 100K OHM.

- ADD SMC_EXCARD_PWR_EN TEST_POINT

PAGE 43:

- ADD SMC_ANALOG_ID TO NC_SMC_ANALOG_ID

- ADD SMC_SYS_KBDLED TO NC_SMC_SYS_KBDLED

- ADD R5054 10KOHM LINK SMC_GPU_ISENSE PULL DOWN TO GND.

- R5142 CHANGE TO NO STUFF. PAGE 46:

- ADD =PP1V05_ENET_PHY LINK TO PP1V2R1V05_ENET.

- ADD =PP3V3_S5_P3V3ENETFET LINK TO PP3V3_S5

MODIFY ALL NOSTUFF TO NO STUFF.

- ADD R5055 10KOHM LINK SMC_NB_MISC_ISENSE PULL DOWN TO GND.

PAGE 19:

PAGE 18:

- DELETE 1.05V S0 FET CIRCUIT.

- U7500 PIN TONSEL LINK TO GND DIRECTLY.

- U7500 PIN V5DRV1 LINK TO PP5V_S0_MCPREG_VCC.

- ADD =PP3V3_ENET_PHY_VDDREG LINK TO TP_PP3V3_ENET_PHY_VDDREG.

- FOLLOW M97 DESIGN

PAGE 26:

PAGE :

PAGE 57:

- R5417 CHANGE TO 4.53K AND DELETE BOM OPTION.

- R5416 CHANGE TO 4.53K AND DELETE BOM OPTION.

*****2008/09/02*****

PAGE 66:

- REMOVE R7884 AND C7884

- XDP FOLLOW M98 DESIGN. CONNECTOR FROM 516S0625 CHANGE TO 998-1571.

PAGE 66:

PAGE 29:

- ADD STANDOFF 860-0749 X 1

- ADD STANDOFF 860-0723 X 1

- ADD STANDOFF 860-0964 X 4

PAGE 45:

- R1860 AND R1861 CHANGE TO PAGE 68.

- C2504-C2507 FROM 138S0578(402) CHANGE TO 138S0614(402-1)

- C2516-C2517 FROM 138S0578(402) CHANGE TO 138S0614(402-1)

- R4150 FROM 118S0343 (0201) CHANGE TO 116S0056(0402)

- R0602 BOMOPTION FROM JTAG_1DEV CHANGE TO NO STUFF.

- Q7320 FROM 376S0512 CHANGE TO 376S0652 (H-F)

- REMOVE ALT TABLE

- REMOVE ALT TABLE PAGE 94:

PAGE 74:

PAGE 50:

PAGE 29:

*****2008/10/20*****

*****2008/10/22*****

PAGE 37:

PAGE 90:

PAGE 48:

- C4803 CHANGE TO 138S0614

- C6605 CHANGE TO HF APN 128S0221

PAGE 66:

PAGE 70:

PAGE 52:

PAGE 28:

PAGE 12:

PAGE 72:

PAGE 68:

PAGE 9:

*****2008/09/27*****

- CHANGE ODD CONNECTOR FROM 516S0720 TO 516S0719

- REMOVE J9001 PIN 20 AND PIN21 NET.

- R5418 CHANGE TO 4.53K AND DELETE BOM OPTION.

- REMOVE BOMOPTION TABLE OF R2903/R2905/R2909/R2911

- REMOVE K36 BOM OPTION TABLE AND ALT TABLE

- C2870 CHANGE TO 138S0614

- C1200 ~ C1219 CHANGE TO 138S0580

- R7272 CHANGE FROM 57.6K 1%(114s0389) TO 75K 1%(114s0399)

- ADD R2903/R2905 BOMOTION AND CHANGE VALUE TO 200 OHM

*****2008/10/24*****

PAGE 19:

PAGE 34:

- Q7321 FROM 376S0511 CHANGE TO 376S0651 (H-F)

PAGE 34:

- J3400 516S0729 CHANGE TO 516S0635

*****2008/10/28*****

*****2008/11/01*****

- U4100 CHANGE FROM 338S0523 TO 338S0654

PAGE 45:

*****2008/11/05*****

- ADD GMUX_JTAG_TMS AND GMUX_JTAG_TDI IN MISC NC MCP79 ALIASES.

- BOM change U1400 CHANGE FROM 338S0678 TO 338S0702

- C6210 CHANGE FROM 127S0062 TO 127S0108

PAGE 102:

- NETNAME FROM CHGR LOWCURRENT GATE CHANGE TO CHGR_LOWCURRENT_GATE

- NETNAME FROM CHGR LOWCURRENT REF CHANGE TO CHGR_LOWCURRENT_REF

- CHANG C9442 AND C9443 TO 47PF

- CHANGE R9460,R9461 TO 0OHM,

- ADD C9480 0.1UF_16V_0402 FROM GND_CHASSIS_TMDS_DOWN TO GND

- CHANGE R9462, R9463 TO 2.7KOHM

- CHANGE C9411, C9412 TO 220PF

- R5280/R5281 = 1K (FOLLOW M97D)

- R5270/R5271 = 1K (FOLLOW M97D)

- D4600/D4601/PIN-6 CONNECT TO USB VBUS (FOLLOW M97D)

- J6750 CHANGE FROM 514-0519 TO 514-0666

*****2008/11/19*****

- J4600, J4601 CHANGE FROM 514-0527 TO 514-0669

- U3700 CHANGE FROM 338S0570 TO 338S0694

*****2008/11/26*****

- PAGE 61 NOTE : CORRECT REFERENCE TO R5164 AND R5144

- J3400 CHANGE TO 516S0729

- R5156, R5157, R5158 change from 0 to 33 ohm, 5%, 0402(116s0030)

*****2008/12/20*****

- U4900 symbol update

*****2008/12/17*****

- R5144 and R5164 changed to 10K 5% 0402 (116S0090)

*****2008/12/12*****

051-8089

02

SYNC_MASTER=K36B_MLB

109

5

02

IN

B1

OE*

VCCB

B2 B3 B4

GND

A4

A3

A2

A1

VCCA

OUT

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

1.05V TO 3.3V LEVEL TRANSLATOR (K36B: ON ICT FIXTURE)

XDP connector

and/or level translator

U1000

U1400

From XDP connector

or via level translator

MCP

From XDP connector

To XDP connector

CPU

69 13 10

7 6

JTAG_ALLDEV

UQFN

NLSV4T244

U0600

2 3 4 5

10 9 8 7

6

12

1

11

10V 402

JTAG_ALLDEV

CERM

20%

0.1UF

C0601

1

2

10V CERM 402

0.1UF

JTAG_ALLDEV

20%

C0602

1

2

JTAG_ALLDEV

10K

5%

402

MF-LF

1/16W

R0601

1

2

402

MF-LF

1/16W

0

5%

NO STUFF

R0602

1

2

13

7

69 13 10

7 6

69 13 10

7

69 13 10

7 6

MF-LF

XDP

402

0

5%

1/16W

R0603

1 2

1/16W

5%

402

0

MF-LF

XDP

R0604

1 2

13

7

6

02

109

SYNC_DATE=08/17//2008

SYNC_MASTER=K36B_MLB

JTAG Scan Chain

051-8089

=PP3V3_S0_XDP

XDP_TRST_L

XDP_TMS

XDP_TCK XDP_TDI

XDP_TRST_L

JTAG_MCP_TDO_CONN

XDP_TCK

JTAG_MCP_TDO

XDP_TDO_CONN

XDP_TMS

MAKE_BASE=TRUE

JTAG_MCP_TCK

MAKE_BASE=TRUE

JTAG_MCP_TDI

MAKE_BASE=TRUE

JTAG_MCP_TMS

MAKE_BASE=TRUE

JTAG_MCP_TRST_L

XDP_TDO

=PP1V05_S0_CPU

JTAG_LVL_TRANS_EN_L

8

13

6 7

10 13 69

6 7

10 13 69

6 7

10 13 69

21

7

13 21

7

13 21

7

13 21

7

13 21

10 69

8

10 11 12 13

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

#J3400 Airport

Need 6 TP

# Other Func Test Points

#J4810 BLUETOOTH

Functional Test Points

Need 2 TP

Need 6 TP

Need 4 TP

Need 3 TP

Need 4 TP

Need 6 TP

Need 4 TP

Need 2 TP

#J4500 SATA ODD

#J6703 Right SUB SPEAKER CONNECTOR

#J6702 Left SPEAKER CONNECTOR

# J6701 MIC CONNECTOR

#J9001 LCD + CAMERA CONNECTOR

#J9000 INVERTER Connector

#J6900 MagSafe DC Power Jack

Need 2 TP

#J1300 XDP

Need 8 TP

# J5800 GEYSER AND DIMM0 REMOTE TEMP SENSORS

#J5520 CPU/MCP Thermal Sensor

# J5100 LPC+SPI Connector

# J4501 SATA HD System LED and IR

#J5601 Fan Connectors

#J6950 Battery/Lid Connector

I12 I15

I157

I158

I159

I16

I160

I161

I162

I163 I164

I165 I166

I167

I168

I169

I170

I171

I172

I173

I174

I175

I176

I177

I178

I179

I180

I181

I182

I183 I184

I185

I186

I187

I188

I189

I190

I191

I192

I193

I194

I195

I196 I197

I198

I199

I200

I201

I202

I203

I204 I205

I206

I207

I208

I209 I210

I211

I212

I213

I214

I215

I216

I217

I218

I219 I220

I221

I222

I223

I224

I225

I226

I227

I228

I229

I230

I231

I232

I233

I234

I235 I236

I237

I238

I239

I240 I241

I242

I243

I244

I245

I246

I247

I248 I249

I250

I251

I252

I253

I254

I255

I256

I257

I258

I259

I260

I261

I262

I263

I264

I265

I266

I267

I268

I269 I270

I271

I272

I273

I274

I275

I276

I277

I278

I279

I280

I281

I282

I283

I284

I285

I286

I287

I288

I289

I290

I291

I292

I293

I294

I295

I296

I297

I298 I299

I300

I301

I302

I303

I304

I305

I306

I307 I308 I309

I310 I311

I312

I313

I314

I315

I316

I317

I318

I319

I320

I321

I322 I323

I324

I325

I326

I327

I328

I329 I330

I331

I332

I333

I334

I335

I336

I337 I338

I339

I340

I341

I342

I343

I344

I345

109

02

7

051-8089

FUNC TEST

I2C_MINI_PCIE_SDA

TRUE

PCIE_WAKE_L

TRUE

MINI_CLKREQ_L

TRUE

PCIE_CLK100M_MINI_N

TRUE

PCIE_CLK100M_MINI_P

PP3V3_S3_AIRPORT_CONN

TRUE

I2C_MINI_PCIE_SCL

TRUE

GND

TRUE

ALL_SYS_PWRGD

TRUE

PPVCORE_S0_CPU

TRUE

PPCPUVTT_S0

PCIE_MINI_R2D_P

TRUE

PP3V3_WLAN

TRUE

PP1V5_S0_R

TRUE

MINI_RESET

TRUE

PCIE_MINI_D2R_P

TRUE

PCIE_MINI_R2D_N

TRUE

GND

TRUE

PP5V_S3_IR_CONN

TRUE

IR_RX_OUT

TRUE

SYS_LED_ANODE_L

TRUE

PP5V_S0_HDD_FLT

TRUE

SATA_HDD_D2R_C_P

TRUE

SATA_HDD_D2R_C_N

TRUE

GND_SMC_LID_F

TRUE

SMC_LID_F

TRUE

GND

TRUE

LPCPLUS_GPIO

TRUE

SMC_RX_L

TRUE

SMC_NMI

TRUE

JTAG_MCP_TDI

TRUE

MCP_DEBUG<1>

TRUE

PP3V3_S0

TRUE

SMBUS_MCP_0_CLK

TRUE

PM_LATRIGGER_L

TRUE

TP_XDP_OBSDATA_B3

TRUE

TP_XDP_OBSDATA_B1

TRUE

XDP_BPM_L<2>

TRUE

TP_XDP_OBSDATA_B2

TRUE

TP_XDP_OBSDATA_B0

TRUE

TP_XDP_OBSFN_B0

TRUE

XDP_BPM_L<0>

TRUE

PP5VRT_S0

TRUE

LPC_AD<1>

TRUE

SPI_ALT_MOSI

TRUE

LPC_FRAME_L

TRUE

PM_CLKRUN_L

TRUE

SMC_TMS

TRUE

DEBUG_RESET_L

TRUE

SMC_TDO

TRUE

SMC_TRST_L

TRUE

SMC_MD1

TRUE

SMC_TX_L

TRUE

SPI_ALT_MISO

TRUE

LPC_AD<0>

TRUE

LPC_CLK33M_LPCPLUS

TRUE

SPI_ALT_CS_L

TRUE

LPC_SERIRQ

TRUE

PP5V_S3_TPAD_F

TRUE

CPUTHMSNS_D2_P

TRUE

CPUTHMSNS_D2_N

TRUE

MCPTHMSNS_D2_P

TRUE

SMC_LID_LC

TRUE

CONN_TPAD_USB_N

TRUE

CONN_TPAD_USB_P

TRUE

CONN_TPAD_ONOFF_FLTR_L

TRUE

TPAD_GND_F

TRUE

SPKRCONN_R_N_OUT

TRUE

SPKRCONN_R_P_OUT

TRUE

PP3V42_G3H

TRUE

PP3V3_S5

TRUE

PPVTT_S3_DDR_BUF

TRUE

PP5VLT_S3

TRUE

PP3V3_S3

TRUE

PP1V8_S3

TRUE

PP1V0_FW

TRUE

PP5VRT_S0

TRUE

PP1V05_S0

TRUE

PP1V05_S0_MCP_SATA_AVDD

TRUE

PP1V05_S0

TRUE

PP1V05_S0_MCP_PEX_AVDD

TRUE

PP1V8_S0_R

TRUE

PP1V8_S0

TRUE

PP1V05_S0

TRUE

PPVCORE_S0_MCP_R

USB2_AIRPORT_P

TRUE

USB2_AIRPORT_N

TRUE

PCIE_MINI_D2R_N

TRUE

PP0V9_S0

TRUE

PPVCORE_S0_MCP

TRUE

PP1V5_S0_R

TRUE

PP3V3_S0

TRUE

PP1V05_S5_REG

TRUE

GND_BT_F_CONN

TRUE

USB2_BT_F_P_CONN

TRUE

MCPTHMSNS_D2_N

TRUE

SPKRCONN_SUB_P_OUT

TRUE

SPKRCONN_SUB_N_OUT

TRUE

SPKRCONN_L_P_OUT

TRUE

SPKRCONN_L_N_OUT

TRUE

MIC_LO_CONN

TRUE

MIC_HI_CONN

TRUE

MIC_SHLD_CONN

TRUE

PP5V_S3_CAMERA_F

TRUE

GND

TRUE

USB2_CAMERA_CONN_N

TRUE

LVDS_IG_A_CLK_F_N

TRUE

LVDS_IG_A_CLK_F_P

TRUE

LVDS_IG_A_DATA_P<2>

TRUE

USB2_CAMERA_CONN_P

TRUE

LVDS_IG_A_DATA_N<2>

TRUE

LVDS_IG_DDC_CLK

TRUE

LVDS_IG_A_DATA_N<0>

TRUE

LVDS_IG_DDC_DATA

TRUE

LVDS_IG_A_DATA_P<0>

TRUE

LVDS_IG_A_DATA_P<1>

TRUE

PP18V5_DCIN_FUSE

TRUE

PP3V3_LCDVDD_SW_F

TRUE

INV_GND

TRUE

PPBUS_ALL_INV_CONN

TRUE

GND

TRUE

GND

TRUE

PP3V42_G3H_LIDSWITCH_F

TRUE

PPVBAT_G3H_CONN_F

TRUE

SMBUS_BATT_SCL_F

TRUE

LVDS_IG_A_DATA_N<1>

TRUE

PP3V3_S0_LCD_F

TRUE

INV_BKLIGHT_PWM_L

TRUE

PP5V_INV_F

TRUE

ADAPTER_SENSE

TRUE

PPVP_FW

TRUE

PP1V2R1V05_ENET

TRUE

PP3V3_ENET_PHY

TRUE

PPBUS_G3H_CPU_ISNS

TRUE

PPBUS_G3H

TRUE

PP18V5_G3H

TRUE

LPC_AD<2>

TRUE

SPIROM_USE_MLB

TRUE

LPC_AD<3>

TRUE

SPI_ALT_CLK

TRUE

LPC_PWRDWN_L

TRUE

SMC_TDI

TRUE

SMC_TCK

TRUE

SMC_RESET_L

TRUE

XDP_BPM_L<4>

TRUE

XDP_BPM_L<5>

TRUE

XDP_BPM_L<3>

TRUE

JTAG_MCP_TCK

TRUE

XDP_TCK

TRUE

PPCPUVTT_S0

TRUE

JTAG_MCP_TDO_CONN

TRUE

MCP_DEBUG<2>

TRUE

MCP_DEBUG<3>

TRUE

MCP_DEBUG<4>

TRUE

MCP_DEBUG<6>

TRUE

MCP_DEBUG<5>

TRUE

MCP_DEBUG<7>

TRUE

FSB_CLK_ITP_P

TRUE

FSB_CLK_ITP_N

TRUE

XDP_CPURST_L

TRUE

XDP_TDO_CONN

TRUE

XDP_TDI

TRUE

XDP_TRST_L

TRUE

XDP_BPM_L<1>

TRUE

JTAG_MCP_TRST_L

SATA_HDD_R2D_P

TRUE

SATA_HDD_R2D_N

TRUE

SMBUS_BATT_SDA_F

TRUE

PP3V42_G3H

TRUE

XDP_PWRGD

TRUE

SMBUS_MCP_0_DATA

TRUE

MCP_DEBUG<0>

TRUE

JTAG_MCP_TMS

TRUE

XDP_TMS

TRUE

GND

TRUE

XDP_DBRESET_L

TRUE

XDP_OBS20

TRUE

TP_XDP_OBSFN_B1

TRUE

SATA_ODD_D2R_C_N

TRUE

SATA_ODD_D2R_C_P

TRUE

PP3V3_S0

TRUE

SMC_ODD_DETECT

TRUE

GND

TRUE

SATA_ODD_R2D_UF_P

TRUE

SATA_ODD_R2D_UF_N

PP3V3_S3_BT_F_CONN

TRUE TRUE

USB2_BT_F_N_CONN

TRUE

GND

TRUE

FAN_RT_TACH

TRUE

FAN_RT_PWM

TRUE

PP5VRT_S0

SMC_BS_ALRT_L_F

TRUE

31 44

17 31

17 31 71

31

31 44

26 41 64

8

7 8

31 71

31

7 8

31

17 31 71

31 71

38

38 40

38

38 71

56

18 43

39 41 42 43

41 43

6

13 21

13 19 72

7 8

13 21 44 72

13 19

13

10 13 69

13

10 13 69

7 8

19 41 43 72

43

19 41 43 72

19 41 43

41 42 43

26 43

41 42 43

41 43

39 41 42 43

43

19 41 43 72

26 43 72

43

19 41 43

49

47

49

49 72

49

53 54

7 8

8

7 8

8

24

7 8

8

24

8

7 8

8

31 72

17 31 71

8

7 8

8

40

40 72

47

53 54

54

54 55

66

66 72

66

18 66 71

66 72

18 66 71

18 66

18 66 71

18 66

18 66 71

56

66

56

18 66 71

66

56

8

19 41 43 72

43

19 41 43 72

43

19 41 43

41 42 43

10 13 69

6

13 21

6

10 13 69

7 8

6

13

13 19 72

13 14 69

13 69

6

13

6

10 13 69

6

10 13 69

6

13 21

38 71

56

7 8

13

13 21 44 72

13 19 72

6

13 21

6

10 13 69

10 13 26

13

38 71

7 8

38 41

38 71

40

40 72

48

7 8

56

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

"S5" RAILS

"FW" RAILS

"S0,S0M" RAILS

"ENET" RAILS

206 mA (A01)

PEX & SATA AVDD/DVDD aliases

57 mA (A01)

"S3" RAILS

206 mA (A01)

127 mA (A01)

43 mA (A01)

127 mA (A01)

206 mA (A01)

127 mA (A01)

(CPU VCORE PWR)

(MCP VCORE REG. OUTPUT)

"G3H" RAILS

(DDR PWR REG. OUTPUT)

(DDR PWR AFTER SENSE RES.)

(MCP VCORE AFTER SENSE RES)

051-8089

Power Aliases

109

8

02

SYNC_MASTER=K36B_MLB

PP3V3_S3

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm VOLTAGE=3.3V

PP1V8_S3

MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.8V

MIN_LINE_WIDTH=1.5 mm

MAKE_BASE=TRUE

=PP1V8_S3_REG

=PP3V3_S3_BT

=PPVCORE_S0_CPU_VSENSE

PPVCORE_S0_CPU

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.3 MM

MAKE_BASE=TRUE

VOLTAGE=0.9V

=PP1V05_S0_MCP_FSB

=PP1V05_S0_CPU

=PP1V8_S3_MEM

=PP3V3_S3_FET

=PP5V_S0_LCD

PP5VRT_S0

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.30 MM

MAKE_BASE=TRUE

VOLTAGE=5V

=PP1V05_S0_SMC_LS

PPVCORE_S0_MCP_R

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE

=PP1V05_S0_FET

PPVTT_S3_DDR_BUF

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

VOLTAGE=0.9V

=PPBUS_S5_FW_FET

=PPVTT_S3_DDR_BUF

PP5VLT_S3

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM VOLTAGE=5V

MAKE_BASE=TRUE

=PP5V_S3_AUDIO

=PP5V_S3_1V8S3_0V9S0

=PP5V_S3_TPAD

=PP5V_S3_SYSLED

=PP5V_S3_VTTCLAMP

=PP5V_S3_IR

=PP5V_S3_EXTUSB

PP1V8_S0_R

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.5MM

MAKE_BASE=TRUE

PP1V0_FW

MAKE_BASE=TRUE

VOLTAGE=1.0V

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.5MM

PP3V3_S0

MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V MAKE_BASE=TRUE

PPBUS_G3H_CPU_ISNS

VOLTAGE=12.6V

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.3MM

MAKE_BASE=TRUE

PPBUS_G3H

MIN_NECK_WIDTH=0.25MM MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5MM VOLTAGE=12.6V

PP3V42_G3H

MAKE_BASE=TRUE

VOLTAGE=3.42V

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

PP1V05_S0_MCP_PEX_AVDD

MAKE_BASE=TRUE

PP1V05_S0_MCP_SATA_AVDD

MAKE_BASE=TRUE

PP1V5_S0_R

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.5V MAKE_BASE=TRUE

PP18V5_G3H

MAKE_BASE=TRUE

VOLTAGE=18.5V

MIN_NECK_WIDTH=0.3 MM

MIN_LINE_WIDTH=0.6 MM

PPCPUVTT_S0

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

VOLTAGE=1.05V

PP3V3_ENET_PHY

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE

PP1V2R1V05_ENET

MAKE_BASE=TRUE

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 MM

PP1V05_S0

MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM

PP0V9_S0

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm VOLTAGE=0.9V

MAKE_BASE=TRUE

PPVCORE_S0_MCP

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE

PP1V05_S5_REG

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

MIN_LINE_WIDTH=0.6 MM

PP3V3_S5

VOLTAGE=3.3V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=1.5 mm

=PP3V3_FW_LATEVG

=PP3V3_S5_MCPPWRGD =PP3V3_S5_AIRPORT_AUX

=PP3V3_S5_P3V3ENETFET

=PP3V3_S5_P3V3S0FET =PP3V3_S5_P1V05S5

=PP1V05_ENET_P1V05ENETFET

=PP1V05_S5_MCP_VDD_AUXC

=PP5V_S3_AUDIO_AMP

=PP5V_S3_MCPDDRFET

=PP5V_S3_CAMERA

=PP3V3_S3_SMS

=PP3V3_S0_XDP

=PP3V3_S0_MCP_DAC_UF

=PP3V3_S0_MCP

=PP3V3_S0_FAN_RT

=PP3V3_S0_TMDS

=PP1V05_S5_REG

=PP3V3_S3_AIRPORT_AUX

=PP3V3_S3_PDCISENS

=PP3V3_S3_SMBUS_SMC_A_S3

=PP1V05_S0_MCP_PEX_DVDD

=PPVCORE_S0_MCP

=PP1V8_S0

=PP1V8_S0_FET

=PPMCPCORE_S0_REG

=PP1V8_S0_FET_R

=PP3V3R1V8_S0_MCP_IFP_VDD

=PP1V8_S0_VMON

=PP1V05_ENET_MCP_RMGT

=PP1V05_ENET_PHY

=PP1V05_ENET_FET

=PP1V05_ENET_MCP_PLL_MAC

=PPVP_FW_PHY_CPS_FET

=PPVP_FW_PORT1

=PP3V3_ENET_FET

=PP3V3_ENET_MCP_RMGT =PP3V3_ENET_PHY

=PP1V5_S0_FET

=PPBUS_G3H_CPU_ISNS

=PP3V42_G3H_BMON_ISNS

=PPVIN_S5_SMCVREF =PP3V42_G3H_SMBUS_SMC_BSA =PP3V42_G3H_PWRCTL =PP3V42_G3H_CHGR =PP3V42_G3H_SMCUSBMUX =PP3V42_G3H_LIDSWITCH

=PP3V3_S5_SMC

=PPBUS_S5_INV

=PP1V0_FW_FWPHY

=PPVIN_S3_5VLTS3

=PP0V9_S0_REG

=PP3V3_S5_REG

=PP1V8_S3_P1V8S0FET

=PPSPD_S0_MEM

=PP5VR3V3_S0_MCPCOREISNS

=PP3V3_S0_CPUTHMSNS

=PP3V3_S0_MCPTHMSNS

=PP3V3R1V5_S0_MCP_HDA

=PP3V3_S0_MCP_PLL_UF

=PP3V3_S0_HDCPROM

=PP18V5_DCIN_CONN

=PPCPUVTT_S0_REG

=PP1V0_FW_REG

=PP3V3_S0_SMC

=PP3V3_S3_SMBUS_SMC_MGMT

=PP3V3_S5_LPCPLUS

=PP3V42_G3H_RTC_D

=PP18V5_G3H_CHGR

=PP3V42_G3H_REG

=PP1V05_S0_MCP_SATA_DVDD0

=PP1V05_S0_MCP_PEX_AVDD1

=PPVCORE_S0_CPU_REG

=PPVCORE_S0_MCP_REG_R

=PP3V3_S0_MCP_GPIO

=PP3V3_S0_SMBUS_MCP_0

=PP3V3_S0_SMBUS_SMC_B_S0

=PP3V3_S5_PWRCTL =PP3V3_S5_P1V05ENETFET

=PP3V3_S5_P3V3S3FET

=PP1V05_S0_MCP_SATA_AVDD0

=PP3V3_S5_LCD =PP3V3_S5_MCP

=PP1V05_S0_MCP_SATA_DVDD

=PP1V05_S0_MCP_PEX_DVDD1

=PP1V05_S0_MCP_SATA_DVDD1

=PP1V05_S0_MCP_SATA_AVDD1

=PP1V05_S0_MCP_PEX_DVDD0

=PP1V05_S0_MCP_PEX_AVDD0

=PP1V05_S0_MCP_PEX_DVDD

=PPVIN_S5_CPU_IMVP

=PPVIN_S0_CPUVTTS0

=PP3V3_S5_ROM

=PP3V3_S5_MCP_GPIO

=PP3V3_S3_VREFMRGN =PP3V3_S3_WLAN

=PPVIN_S0_MCPCORES0 =PPVIN_S0_MCPREG_VIN

=PPVIN_S5_3V3S5

=PPVIN_S5_1V8S3_0V9S0

=PPBUS_S5_FWPWRSW

=PPBUS_G3HRS5

=PPVIN_S0_5VRTS0

=PPBUS_G3H

=PPBUS_G3H_CPU_ISNS_R

=PP3V3_S0_LCD

=PPVCORE_S0_CPU

=PP5V_S0_HDD

=PP5V_S0_ODD

=PP5VRT_S0_REG

=PP3V3_S0_FET

=PP5VLT_S3_REG

=PP3V3_S0_MCP_VPLL_UF =PP3V3_S0_ODD =PP3V3_S0_LPCPLUS =PP3V3_S0_SMBUS_SMC_0_S0

=PP3V3_S0_AUDIO

=PP3V3_S0_IMVP

=PP1V8R1V5_S0_MCP_MEM

=PP1V5_S0_CPU

=PP1V5_S0_AIRPORT

=PP1V05_S0_VMON

=PP1V05_S0_MCP_HDMI_VDD

=PP1V05_S0_MCP_SATA_DVDD

=PP1V05_S0_MCP_PLL_UF

=PP1V05_S0_MCP_AVDD_UF

=PP0V9_S3M_MEM_TERM

=PPVTT_S0_VTTCLAMP

=PPVCORE_S0_MCP_VSENSE

=PP5V_S0_CPUVTTS0

=PP5V_S0_TMDS

=PP5V_S0_CPU_IMVP

=PP5V_S0_FAN_RT

=PP5V_S0_LPCPLUS

=PP5V_S0_AUDIO =PP5V_S0_AUDIO_AMP

=PP3V3_S0_PWRCTL =PP3V3_S0_VMON =PP3V3_S0_MCPDDRISNS =PP3V3_S0_CPUVTTISNS =PP3V3_FW_P1V0FW =PP3V3_FW_PHY =PP3V3_FW_FWPHY

PP1V8_S0

MIN_NECK_WIDTH=0.2MM VOLTAGE=1.8V

MIN_LINE_WIDTH=0.5MM

MAKE_BASE=TRUE

PPVP_FW

MAKE_BASE=TRUE

VOLTAGE=12.6V

MIN_LINK_WIDTH=0.4 MM

MIN_NECK_WIDTH=0.2 MM

7

59

40

45

7

14 22 24

6

10 11 12 13

28 29

21 65

66

7

42

7

65

7

36

27 59

7

59

49

42

65

38 40

39

7

24

7

24

7

36 37

26

33

65

63

33

22 24

65

66

50

6

13

25

21 22 24

48

68

63

31

59

44

8

24

22 24 46 61

46

65

61

46

18 25

64

18 24

32

33

24

37

33

18 24

32

63

46

42

44

64

57

39

56

41 42 50

66

35

61

59

58

65

28 29

46

47

21 24

24

25

56

62 65

63

42

44

43

26

57

56

20

17

60

46

18 19 21

44

64

33

65

20

66

22 24

8

24

17

20

17

8

24

60

62

43 51

18 20

27

31

61

58

59

36

45

58

57

46

66

11 12

38

58

63 65

61

25

38

44

52 54 55

60

16 24

11 12

31

64

18 25

8

24

30

65

45

62

68

60

48

43

52 55

53

64

46

63

37

35 37

7

OUT

IN

TABLE_5_ITEM

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

MISC NC MCP79 ALIASES

UNUSED EXPRESS CARD LANE

BLUETOOTH

CPU HEATSINK STANDOFF SCREW HOLE

BUT, NEED CHANGE TO HIGH STANDOFF SYMBOL

FOR LAYOUT PLACEMENT

PCI-E ALIASES

ETHERNET ALIASES

UNUSED GPU LANES

SO-DIMM ALIASES

(EMI PAD FOR INVERTER GONNECTOR)

HDA PULL-DOWN

LAN ALIASES

TRACKPAD(WELLSPRING)

FSB MHZ

0 1 0

CPU FSB FREQUENCY STRAPS

1 0 0

0 1 1

1 1 1

1 1 0

1 0 1

0 0 1

(RSVD)

(400)

200

100

133

333

(166)

266

BSEL<2..0>

0 0 0

UNUSED ADDRESS PINS

UNUSED USB PORTS

Screw Holes

BATTERY,AUDIO,DIP DIMM CONNECTOR CHASSIS GND

DCIN CONNECTOR CHASSIS GND

DP HOTPLUG PULL-DOWN

ROM FAILURE OVERRIDE

Z0903 USE SAME Z0913 NON SHAPE OF A HOOF SYMBOL

MCP_SAFE_MODE SIGNAL TO SUPPORT

FW PULL-DOWN

USB ALIASES

UNUSED LVDS SIGNALS

LVDS ALIASES

DIP DIMM CONNECTOR CHASSIS GND

SATA,LVDS CONNECTOR CHASSIS GND

DIP DIMM CONNECTOR CHASSIS GND

I/O CONNECTOR CHASSIS GND

5%

47K

1/16W MF-LF 402

R0930

1

2

14 69 10

20K

1/16W

5% MF-LF

402

R0940

1

2

OMIT

STDOFF-4.5OD3.95H-1.1-3.2-TH

Z0905

1

OMIT

STDOFF-4.2OD3.95H-5.52R3.37-6B

Z0903

1

5R2P3-7SQBNP

OMIT

Z0901

1

OMIT

STDOFF-4.5OD3.95H-1.1-3.2-TH

Z0921

1

STDOFF-4.2OD3.95H-5.52R3.37-7SQB

OMIT

Z0904

1

OMIT

5R2P3-7B

Z0911

1

5R2P3-7SQB

OMIT

Z0909

1

5R2P3-7SQB

OMIT

Z0910

1

OMIT

5P0R2P3-7BLB

Z0908

1

7X7R2P3-5B

OMIT

Z0902

1

6P5R2P6-7SQB

OMIT

Z0907

1

CLIP-SM-M42

EMI-SPRING

ZS0920

1

5R2P3-7SQBNP

OMIT

Z0906

1

OMIT

STDOFF-4.2OD2.15H-1.2-3.2-TH

Z0912

1

OMIT

STDOFF-4.2OD3.95H-5.52R3.37-6B

Z0913

1

47K

1/16W 402

MF-LF

5%

R0931

1

2

5%

402

47K

1/16W MF-LF

R0932

1

2

1/16W

5%

0

MF-LF 402

R0955

1

2

0

5%

MF-LF

1/16W

402

R0920

1 2

41

20K

402

MF-LF

1/16W

5%

R0977

1

2

1%

124

1/16W MF-LF

402

R0941

1

2

0.01UF

16V CERM 402

10%

C0940

1

2

SM

XW0902

1 2

SM

XW0901

1 2

?

860-0749

STANDOFF W/THRU HOLES,WIRELESS

Z0913

1

STANDOFF

051-8089

109

02

9

SYNC_MASTER=K36B_MLB

SIGNAL ALIAS

?

Z0903,Z0904,Z0905,Z0921

STANDOFF860-0964

4

THERMAL STANDOFF

Z0912

STANDOFF WIRELESS

1

860-0723

?

STANDOFF

=GND_CHASSIS_DIPDIMM_RIGHT =GND_CHASSIS_RJ45

=GND_CHASSIS_LVDS =GND_CHASSIS_DIPDIMM_CENTER

=GND_CHASSIS_FW_DOWN

=GND_CHASSIS_TMDS_DOWN

=GND_CHASSIS_FW_UPPER

=GND_CHASSIS_TMDS_UPPER

=GND_BATT_CHGND =GND_CHASSIS_AUDIO_JACK

=GND_CHASSIS_AUDIO_MIC

=GND_CHASSIS_DIPDIMM_LEFT

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_IG_A_DATA_N3

MCP_TV_DAC_RSET

MCP_SPKR

PCIE_FW_PRSNT_L

DP_HOTPLUG_DET

PEG_PRSNT_L PEG_CLKREQ_L

=PEG_R2D_C_N<15:0> =PEG_R2D_C_P<15:0>

CPU_PECI_MCP

=GND_AUDIO_AMP

=GND_AUDIO_CODEC

USB_EXCARD_N

USB_EXTD_N

INVT_CHGND

MCP_MII_COL

PCIE_EXCARD_D2R_P

SMC_MCP_SAFE_MODE

MCP_MII_RXER

AUD_IPHS_SWITCH_EN

=MCP_BSEL<0:2>

MCP_MII_CRS

LVDS_IG_A_DATA_P<3> LVDS_IG_A_DATA_N<3>

GMUX_JTAG_TMS MCP_MEM_RESET_L

MEM_A_A<15> MEM_B_A<15>

GMUX_JTAG_TDI

USB_EXTD_P

USB_EXCARD_P

MCP_TV_DAC_VREF

=USB2_BT_P

=USB2_TPAD_N

=USB2_TPAD_P

USB_EXTC_P

PEG_CLK100M_P

EXTGPU_RESET_L

EXTGPU_PWR_EN

PEG_CLK100M_N

=P3V3ENET_EN

=PP3V3_ENET_PHY_VDDREG

MAKE_BASE=TRUE

USB_TPAD_P

TP_USB_EXTDP

MAKE_BASE=TRUE

USB_TPAD_N

MAKE_BASE=TRUE

TP_PEG_CLK100MP

MAKE_BASE=TRUE

TP_USB_EXCARDP

TP_USB_EXTCP

MAKE_BASE=TRUE

TP_EXTGPU_PWR_EN

MAKE_BASE=TRUE

TP_EXTGPU_RESET_L

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PEG_R2D_C_N<15:0>

CPU_BSEL<0:2>

MAKE_BASE=TRUE

TP_PEG_CLK100MN

NC_LVDS_IG_A_DATA_P3

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_IG_B_DATA_P<3:0>

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_GMUX_JTAG_TMS

MAKE_BASE=TRUE

TP_GMUX_JTAG_TDI

MAKE_BASE=TRUE

TP_MCP_MEM_RESET_L

MAKE_BASE=TRUE

TP_CPU_PECI_MCP

TP_MEM_A_A15

MAKE_BASE=TRUE MAKE_BASE=TRUE

TP_MEM_B_A15

MAKE_BASE=TRUE

USB_BT_P

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_IG_B_CLKP

MAKE_BASE=TRUE

GND_AUDIO_CODEC

MAKE_BASE=TRUE

GND_AUDIO_AMP

MAKE_BASE=TRUE

TP_PEG_PRSNT_L

NC_LVDS_IG_B_CLKN

MAKE_BASE=TRUE

NO_TEST=TRUE

PP3V3_ENET_PHY_VDDREG

MAKE_BASE=TRUE

NC_PEG_R2D_C_P<15:0>

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_PEG_CLKREQ_L

PM_SLP_RMGT_L

MAKE_BASE=TRUE

NC_PEG_D2R_N<15:0>

MAKE_BASE=TRUE

NO_TEST=TRUE

=PEG_D2R_N<15:0> =PEG_D2R_P<15:0>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PEG_D2R_P<15:0>

LVDS_IG_B_CLK_P LVDS_IG_B_CLK_N LVDS_IG_B_DATA_P<3:0>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_IG_B_DATA_N<3:0>

USB_EXTC_N

MAKE_BASE=TRUE

NC_RTL8211_REGOUT

=P1V05ENET_EN

=RTL8211_ENSWREG

=RTL8211_REGOUT

TP_USB_EXCARDN

MAKE_BASE=TRUE

TP_USB_EXTDN

MAKE_BASE=TRUE

TP_PCIE_EXCARD_D2RP

LVDS_IG_B_DATA_N<3:0>

=USB2_BT_N

MAKE_BASE=TRUE

USB_BT_N

TP_USB_EXTCN

MAKE_BASE=TRUE

USB_MINI_P

MAKE_BASE=TRUE

=USB_MINI_P

USB_MINI_N

MAKE_BASE=TRUE

=USB_MINI_N

TP_PCIE_EXCARD_D2RN

MAKE_BASE=TRUE

PCIE_EXCARD_D2R_N

MAKE_BASE=TRUE

TP_PCIE_EXCARD_R2D_CP

PCIE_EXCARD_R2D_C_P

TP_PCIE_CLK100M_EXCARDP

MAKE_BASE=TRUE

PCIE_CLK100M_EXCARD_P

TP_EXCARD_CLKREQ_L

MAKE_BASE=TRUE

EXCARD_CLKREQ_L

MAKE_BASE=TRUE

TP_PCIE_CLK100M_EXCARDN

PCIE_CLK100M_EXCARD_N

TP_PCIE_EXCARD_PRSNT_L

MAKE_BASE=TRUE

PCIE_EXCARD_PRSNT_L

TP_PCIE_EXCARD_R2D_CN

MAKE_BASE=TRUE

PCIE_EXCARD_R2D_C_N

29

34

66

28 29

37

68

37

68

56

54

55

28

18 71

21

17

18

17

14

53

52 53 54 55

20 72

66

18

17 71

18

19

18

18 71

19

16

28

29

19

20 72

18 71

40

49

20 72

17 71

17

17 71

33

32

20 72

21

17

18 71

20 72

33

32

18 71

40 20 72

20 72 31

17 71

17

17 71

17

17 71

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

IN IN IN

IN

OUT

IN

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

OUT OUT

OUT

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI BI BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI

BI BI BI

BI

BI BI

BI BI BI BI BI

BI

OUT

IN

IN IN IN IN IN

IN IN

OUT

IN IN

IN

IN IN

IN

OUT

BI BI BI BI

TEST7

TEST6

DSTBP1* DINV1*

D31*

D30*

D25*

D11* D12* D13* D14*

DSTBP0* DINV0*

D9*

D8*

D7*

D6*

D19*

D18*

D0*

D32* D1* D2*

D5*

D16*

D20* D21* D22* D23* D24*

D26* D27* D28* D29*

DSTBN1*

GTLREF

TEST3 TEST4 TEST5

BSEL0 BSEL1 BSEL2

D33*

D34*

D35*

D36*

D37*

D38*

D39*

D40*

D41*

D42*

D43*

D44*

D45*

D46*

D47*

DSTBN2* DSTBP2*

DINV2*

D48*

D49*

D50*

D51*

D52*

D53*

D54*

D55*

D56*

D57*

D58*

D59*

D60*

D61*

D62*

D63*

DSTBN3* DSTBP3*

DINV3*

COMP0 COMP1 COMP2 COMP3

DPRSTP*

DPSLP*

DPWR*

PWRGOOD

SLP*

PSI*

D17*

D4*

D3*

DSTBN0*

D15*

D10*

TEST2

TEST1

2 OF 4

DATA GRP 3 DATA GRP 2

MISC

DATA GRP 0DATA GRP 1

LOCK*

INIT*

A20M*

A6*

A3* A4*

A14*

A16*

REQ0* REQ1* REQ2* REQ3* REQ4*

BCLK1

BCLK0

THERMTRIP*

THERMDA

PROCHOT*

DBR*

TRST*

TMS

TDO

TDI

TCK

PREQ*

PRDY*

BPM3*

BPM2*

BPM1*

BPM0*

HITM*

HIT*

TRDY*

RS2*

RS1*

RS0*

RESET*

IERR*

BR0*

DBSY*

DRDY*

DEFER*

BNR*

RSVD4

RSVD3

RSVD2

RSVD1

RSVD0

SMI*

LINT1

LINT0

STPCLK*

FERR*

ADSTB1*

A35*

A34*

A33*

A32*

A31*

A30*

A29*

A28*

A19*

A18*

A17*

ADSTB0*

A13*

A12*

BPRI*

A20* A21* A22* A23* A24*

A26* A27*

A9*

A8*

A7*

A11*

A25*

THERMDC

IGNNE*

ADS*

A10*

A15*

A5*

RSVD5 RSVD6 RSVD7 RSVD8

1 OF 4

CONTROL

THERMAL

XDP/ITP SIGNALS

H CLK

ADDR GROUP1

ICH

RESERVED

ADDR GROUP0

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

CHANGE CPU FROM SOCKET TO BGA SYMBOL

SYNC FROM T18

PLACEMENT_NOTE (all 4 resistors):

CPU JTAG Support

402

MF-LF

54.9

1/16W

1%

R1000

1

2

402

MF-LF

1/16W

5%

68

R1002

1

2

PLACEMENT_NOTE=Place R1005 within 12.7mm of CPU.

1/16W

1%

MF-LF

1K

402

R1005

1

2

PLACEMENT_NOTE=Place R1006 within 12.7mm of CPU.

2.0K

402

1/16W MF-LF

1%

R1006

1

2

54.9

1% 1/16W MF-LF

402

Place within 12.7mm of CPU

R1023

1

2

402

MF-LF

1/16W

1%

27.4

Place within 12.7mm of CPU

R1022

1

2

54.9

1% 1/16W MF-LF

402

Place within 12.7mm of CPU

R1021

1

2

27.4

402

MF-LF

1/16W

1%

Place within 12.7mm of CPU

R1020

1

2

69 14

69 60 14

69 14

60

69 14 13

69 14

69

9

69

9

69

9

69 14

69 13

7

69 13

7

69 13

7

69 13

7

69 13

7

69 13

7

69 10

6

26 13

7

69 60 42 14

47

69 42 14

69 14

69 14 13

69 14

69 13 10

7 6

69 13 10

7 6

69 13 10

7 6

69 13 10

7 6

47

69 14

402

0

1/16W MF-LF

5%

NO STUFF

R1010

1 2

402

1K

MF-LF

5%

1/16W

NO STUFF

R1011

1

2

1% 1/16W MF-LF

402

54.9

R1001

1

2

54.9

1/16W MF-LF

402

1%

R1090

1 2

402

54.9

MF-LF

1%

1/16W

R1091

1 2

402

54.9

1/16W MF-LF

1%

R1093

1 2

69 14

402

649

1/16W MF-LF

1%

R1094

1 2

1/16W

5%

1K

MF-LF 402

NO STUFF

R1012

1

2

402

16V

10%

0.1uF

X5R

PLACEMENT_NOTE=Place C1014 within 12.7mm of CPU.

NO STUFF

C1014

1

2

OMIT

PENRYN

FCBGA

U1000

B22

B23 C21

R26 U26

AA1 Y1

E22

F24

J24 J23

H22

F26 K22

H23

N22

K25

P26 R23

E26

L23

M24 L22

M23 P25

P23

P22 T24

R24

L25

G22

T25

N25

Y22

AB24 V24

V26

V23 T22

U25 U23

F23

Y25

W22 Y23

W24

W25 AA23

AA24

AB25

AE24

AD24

G25

AA21 AB22

AB21

AC26 AD20

AE22 AF23

AC25

AE21 AD21

E25

AC22

AD23 AF22

AC23

E23

K24 G24

H25

N24

U22

AC20

E5 B5

D24

J26

L26

Y26

AE25

H26

M26

AA26

AF24

AD26

AE6

D6 D7

C23 D25

C24

AF26

AF1

A26

C3

402

1%

MF-LF

1/16W

54.9

PLACEMENT_NOTE=Place R1092 near ITP connector (if present)

R1092

1 2

OMIT

PENRYN

FCBGA

U1000

N3

P5 P2

L2

P4 P1

R1

Y2

U5

R3 W6

A6

U4

Y5 U1

R4 T5

T3

W2 W5

Y4

J4

U2 V4

W3

AA4 AB2

AA3

L5

L4

K5 M3

N2

J1

H1

M1

V1

A22 A21

E2

AD4 AD3

AD1

AC4

G5

F1

C20

E1

H5

F21

A5

G6 E4

D20

C4

B3

C6

B4

H4

AC2

AC1

D21

K3

H2 K2

J3

L1

C1 F3

F4 G3

M4

N5

T2 V3

B2

F6 D2

D22

D3

A3

D5

AC5

AA6

AB3

A24

B25

C7

AB5

G2

AB6

SYNC_MASTER=K36B_MLB SYNC_DATE=08/18/2008

10

109

02

CPU FSB

051-8089

FSB_D_L<14>

FSB_D_L<20>

XDP_TDO

FSB_A_L<24> FSB_A_L<25> FSB_A_L<26> FSB_A_L<27>

FSB_CLK_CPU_N

XDP_TMS

XDP_TDO

XDP_TDI

XDP_DBRESET_L

XDP_TRST_L

XDP_TMS

CPU_THERMD_N

CPU_STPCLK_L

FSB_DINV_L<3>

FSB_D_L<63>

FSB_DINV_L<0>

FSB_DSTB_L_N<0>

FSB_D_L<10>

FSB_D_L<9>

FSB_D_L<7>

FSB_D_L<2>

FSB_D_L<1>

FSB_D_L<0>

TP_CPU_RSVD_T2

XDP_BPM_L<1>

FSB_D_L<3> FSB_D_L<4> FSB_D_L<5> FSB_D_L<6>

FSB_D_L<8>

FSB_D_L<11> FSB_D_L<12>

FSB_DSTB_L_P<0>

FSB_D_L<16> FSB_D_L<17>

FSB_D_L<21> FSB_D_L<22> FSB_D_L<23> FSB_D_L<24>

FSB_D_L<26>

FSB_D_L<29> FSB_D_L<30> FSB_D_L<31>

CPU_DPSLP_L

CPU_DPRSTP_L

FSB_DSTB_L_N<3> FSB_DSTB_L_P<3>

FSB_D_L<62>

FSB_D_L<61>

FSB_D_L<60>

FSB_D_L<59>

FSB_D_L<58>

FSB_D_L<56>

FSB_D_L<54>

FSB_D_L<53>

FSB_D_L<52>

FSB_D_L<51>

FSB_D_L<50>

FSB_D_L<49>

FSB_D_L<48>

FSB_DINV_L<2>

FSB_DSTB_L_P<2>

FSB_DSTB_L_N<2>

FSB_D_L<47>

FSB_D_L<46>

FSB_D_L<45>

FSB_D_L<44>

FSB_D_L<43>

FSB_D_L<42>

FSB_D_L<41>

FSB_D_L<40>

FSB_D_L<39>

FSB_D_L<38>

FSB_D_L<37>

FSB_D_L<36>

FSB_D_L<35>

FSB_D_L<34>

FSB_D_L<33>

FSB_D_L<32>

XDP_TRST_L

XDP_TCK

CPU_INIT_L

XDP_TCK

XDP_BPM_L<4>

FSB_BPRI_L

FSB_RS_L<2>

FSB_RS_L<0>

FSB_ADS_L FSB_BNR_L

FSB_DEFER_L FSB_DRDY_L FSB_DBSY_L

FSB_A_L<7> FSB_A_L<8>

FSB_A_L<11>

FSB_A_L<13> FSB_A_L<14> FSB_A_L<15> FSB_A_L<16> FSB_ADSTB_L<0>

FSB_REQ_L<0> FSB_REQ_L<1> FSB_REQ_L<2> FSB_REQ_L<3> FSB_REQ_L<4>

FSB_A_L<17> FSB_A_L<18>

FSB_A_L<23>

FSB_A_L<22>

FSB_A_L<20>

FSB_A_L<19>

FSB_A_L<21>

CPU_SMI_L

TP_CPU_RSVD_N5

TP_CPU_RSVD_F6

TP_CPU_RSVD_B2

TP_CPU_RSVD_D3

TP_CPU_RSVD_D22

TP_CPU_RSVD_D2

TP_CPU_RSVD_V3

TP_CPU_RSVD_M4

CPU_NMI

CPU_INTR

CPU_IGNNE_L

FSB_A_L<29>

FSB_A_L<28>

FSB_A_L<30> FSB_A_L<31> FSB_A_L<32> FSB_A_L<33> FSB_A_L<34> FSB_A_L<35> FSB_ADSTB_L<1>

CPU_FERR_L

CPU_A20M_L

CPU_THERMD_P

FSB_D_L<13>

FSB_D_L<15>

FSB_D_L<55>

FSB_D_L<57>

CPU_COMP<0>

CPU_COMP<2>

FSB_DSTB_L_P<1>

FSB_DSTB_L_N<1>

XDP_BPM_L<0>

FSB_HITM_L

FSB_D_L<18> FSB_D_L<19>

FSB_DPWR_L

CPU_BSEL<1>

CPU_PWRGD

FSB_DINV_L<1>

CPU_BSEL<2>

TP_CPU_TEST3

CPU_GTLREF

TP_CPU_TEST5 TP_CPU_TEST6

TP_CPU_TEST7

CPU_TEST4

CPU_TEST2

CPU_BSEL<0>

XDP_TDI

XDP_BPM_L<3>

XDP_BPM_L<2>

FSB_A_L<12>

FSB_CLK_CPU_P

PM_THRMTRIP_L

CPU_TEST1

CPU_COMP<3>

CPU_PROCHOT_L

FSB_A_L<10>

FSB_A_L<9>

FSB_A_L<6>

FSB_A_L<5>

FSB_LOCK_L

FSB_CPURST_L

FSB_RS_L<1>

FSB_TRDY_L

XDP_BPM_L<5>

CPU_PSI_L

FSB_CPUSLP_L

FSB_HIT_L

CPU_IERR_L

FSB_BREQ0_L

FSB_A_L<4>

FSB_A_L<3>

FSB_D_L<25>

FSB_D_L<27> FSB_D_L<28>

CPU_COMP<1>

=PP1V05_S0_CPU

6

10 69

6 7

10 13 69

6 7

10 13 69

6 7

10 13 69

6 7

10 13 69

69

27 69

69

6 8

11 12 13

OUT OUT OUT OUT OUT OUT OUT

OUT

VCC

VCCP

VCCA

VID0 VID1 VID2 VID3 VID4 VID5 VID6

VCCSENSE

VSSSENSE

VCC

3 OF 4

VSS VSS

4 OF 4

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

23 A (LV Design Target)

Current numbers from Merom for Santa Rosa EMTS, doc #20905.

(BR1#)

CHANGE CPU FROM SOCKET TO BGA SYMBOL

SYNC FROM T18

41 A (SV HFM)

30.4 A (SV LFM)

44 A (SV Design Target)

(CPU CORE POWER)

130 mA

NEED 1.5V POWER SOURCE

(CPU INTERNAL PLL POWER 1.5V)

(CPU IO POWER 1.05V)

4500 mA (before VCC stable) 2500 mA (after VCC stable)

(Socket-P KEY)

69 60

PLACEMENT_NOTE=Place R1101 within 25.4mm of CPU, no stubs.

1/16W

1%

100

402

MF-LF

R1101

1

2

69 60

OMIT

PENRYN

FCBGA

U1000

A7

A9

B9 B10

B12

B14 B15

B17

B18 B20

C9 C10

A10

C12

C13 C15

C17

C18

D9

D10

D12 D14

D15

A12

D17

D18

E7

E9

E10

E12 E13

E15

E17 E18

A13

E20

F7

F9

F10 F12

F14

F15 F17

F18

F20

A15

AA7

AA9

AA10

AA12

AA13 AA15

AA17

AA18 AA20

AB9

A17

AC10 AB10

AB12 AB14

AB15

AB17 AB18

AB20

AB7

AC7

A18

AC9

AC12

AC13 AC15

AC17 AC18

AD7

AD9 AD10

AD12

A20

AD14 AD15

AD17

AD18 AE9

AE10 AE12

AE13

AE15 AE17

B7

AE18

AE20 AF9

AF10 AF12

AF14 AF15

AF17

AF18 AF20

B26 C26

G21 V6

R21

R6

T21 T6

V21

W21

J6

K6 M6

J21 K21

M21

N21 N6

AF7

AD6 AF5

AE5

AF4 AE3

AF3

AE2

AE7

OMIT

PENRYN

FCBGA

U1000

A4 A8

B11

W1

W4 W23

W26 Y3

Y6 Y21

Y24

AA2 AA5

B13

AA8

AA11 AA14

AA16

AA19 AA22

AA25 AB1

AB4

AB8

B16

AB11

AB13

AB16 AB19

AB23

AB26 AC3

AC6

AC8

AC11

B19

AC14

AC16 AC19

AC21

AC24 AD2 AD5 AD8

AD11 AD13

B21

AD16

AD19 AD22

AD25

AE1

AE4 AE8

AE11

AE14 AE16

B24

AE19

AE23 AE26

A2 AF6

AF8

AF11 AF13

AF16

AF19

C5

AF21

A25

AF25

B1

C8

C11

C14

A11

C16

C19

C2 C22

C25

D1

D4

D8 D11

D13

A14

D16 D19

D23

D26

E3

E6

E8

E11 E14

E16

A16

E19

E21 E24

F5

F8 F11

F13 F16

F19

F2

A19

F22

F25

G4

G1

G23

G26

H3

H6 H21

H24

A23

J2

J5

J22

J25

K1

K4

K23 K26

L3

L6

AF2

L21

L24

M2

M5

M22 M25

N1

N4 N23

N26

B6

P3

P6

P21 P24

R2

R5 R22

R25 T1

T4

B8

T23 T26

U3 U6

U21 U24

V2

V5

V22 V25

PLACEMENT_NOTE=Place R1100 within 25.4mm of CPU, no stubs.

100

1% 1/16W

402

MF-LF

R1100

1

2

02

11

109

SYNC_DATE=08/17/2008SYNC_MASTER=K36B_MLB

CPU Power & Ground

051-8089

=PP1V05_S0_CPU

=PPVCORE_S0_CPU

CPU_VCCSENSE_P

CPU_VID<6>

CPU_VID<5>

CPU_VID<3>

CPU_VID<2>

CPU_VID<1>

CPU_VID<0>

=PP1V5_S0_CPU

CPU_VID<4>

CPU_VCCSENSE_N

=PPVCORE_S0_CPU

6 8

10 12 13

8

11 12

8

12

8

11 12

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

CPU VCore HF and Bulk Decoupling

6x 330uF. 32x 22uF 0805 (20 stuffed)

PLACEMENT_NOTE (C1200-C1219):

PLACEMENT_NOTE (C1240-C1243):

1x 330uF, 6x 0.1uF 0402

SYNC FROM T18

VCCP (CPU I/O) DECOUPLING

VCCA (CPU AVdd) DECOUPLING

1x 10uF, 1x 0.01uF

CERM 805

6.3V

20%

22UF

Place inside socket cavity on secondary side.

CRITICAL

C1206

1

2

PLACEMENT_NOTE=PLACE C1260 BETWEEN CPU & MCP79.

330UF

2.0V

20%

CRITICAL

D2T-SM2

POLY-TANT

C1260

1

2 3

CERM

Place inside socket cavity on secondary side.

6.3V

20%

22UF

805

CRITICAL

C1204

1

2

CERM

Place inside socket cavity on secondary side.

6.3V

20%

22UF

805

CRITICAL

C1216

1

2

CERM

6.3V

20%

Place inside socket cavity on secondary side.

22UF

805

CRITICAL

C1214

1

2

CERM

CRITICAL

Place inside socket cavity on secondary side.

6.3V

20%

22UF

805

C1208

1

2

CERM

6.3V

20%

805

Place inside socket cavity on secondary side.

22UF

CRITICAL

C1203

1

2

CERM

Place inside socket cavity on secondary side.

805

22UF

20%

6.3V

CRITICAL

C1207

1

2

CERM

Place inside socket cavity on secondary side.

6.3V

20%

805

22UF

CRITICAL

C1202

1

2

CERM

CRITICAL

22UF

Place inside socket cavity on secondary side.

805

20%

6.3V

C1201

1

2

CERM

20%

805

Place inside socket cavity on secondary side.

22UF

6.3V

CRITICAL

C1213

1

2

CERM 805

Place inside socket cavity on secondary side.

6.3V

20%

22UF

CRITICAL

C1212

1

2

CERM

Place inside socket cavity on secondary side.

805

22UF

20%

6.3V

CRITICAL

C1211

1

2

CERM

Place inside socket cavity on secondary side.

805

22UF

20%

6.3V

CRITICAL

C1219

1

2

CERM

CRITICAL

22UF

Place inside socket cavity on secondary side.

6.3V

20%

805

C1200

1

2

22UF

CERM

Place inside socket cavity on secondary side.

6.3V

20%

805

CRITICAL

C1210

1

2

20%

402

CERM

10V

0.1UF

C1261

1

2

CERM

CRITICAL

805

Place inside socket cavity on secondary side.

22UF

20%

6.3V

C1205

1

2

CERM

Place inside socket cavity on secondary side.

805

22UF

20%

6.3V

CRITICAL

C1209

1

2

CERM

Place inside socket cavity on secondary side.

805

22UF

20%

6.3V

CRITICAL

C1215

1

2

CERM

Place inside socket cavity on secondary side.

805

22UF

20%

6.3V

CRITICAL

C1217

1

2

20%

402

CERM

10V

0.1UF

C1262

1

2

20%

402

CERM

0.1UF

10V

C1263

1

2

20%

402

CERM

10V

0.1UF

C1264

1

2

20%

402

CERM

10V

0.1UF

C1265

1

2

20% CERM

10V

0.1UF

402

C1266

1

2

CERM

6.3V

20%

22UF

805

Place inside socket cavity on secondary side.

CRITICAL

C1218

1

2

PLACEMENT_NOTE=PLACE C1250 C1251 NEAR CPU PIN B26.

402

CERM

10% 16V

0.01UF

C1251

1

2

20%

6.3V X5R 603

10uF

C1250

1

2

Place on secondary side.

D2T-SM2

POLY-TANT

2.0V

20%

330UF

CRITICAL

C1240

1

23

330UF

20%

CRITICAL

2.0V POLY-TANT D2T-SM2

Place on secondary side.

C1241

1

23

Place on secondary side.

330UF

20%

2.0V POLY-TANT D2T-SM2

CRITICAL

C1242

1

23

CRITICAL

330UF

2.0V

D2T-SM2

Place on secondary side.

20%

POLY-TANT

C1243

1

23

SYNC_MASTER=K36B_MLB SYNC_DATE=08/17/2008

109

12

02

CPU Decoupling

051-8089

=PP1V5_S0_CPU

=PP1V05_S0_CPU

=PPVCORE_S0_CPU

8

11

6 8

10 11 13

8

11

IN

BI

BI BI

OUT

IN

BI

IN

IN IN

OUT

OUT OUT

BI BI

OUT

IN

IN IN

IN OUT OUT OUT

OUT

NC

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

PWRGD/HOOK0

516S0625

OBSFN_B1

OBSDATA_D1

OBSDATA_D2

MCP79-specific pinout

OBSFN_A0 OBSFN_A1

VCC_OBS_CD

DBR#/HOOK7 NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.

Direction of XDP module

XDP_PRESENT#

TDI

OBSFN_C1

OBSDATA_C0

OBSFN_D1

ITPCLK/HOOK4

RESET#/HOOK6

OBSDATA_C2

TCK0

OBSDATA_A3

OBSDATA_A1

OBSFN_C0

OBSDATA_C3

Mini-XDP Connector

Please avoid any obstructions

NOTE: This is not the standard XDP pinout.

VCC_OBS_AB

TDO

OBSFN_D0

SCL

SDA

TRSTn

HOOK3

HOOK2

HOOK1

TMS

OBSDATA_D0

TCK1

OBSDATA_B2 OBSDATA_B3

OBSFN_B0

ITPCLK#/HOOK5

OBSDATA_D3

OBSDATA_B1

OBSDATA_B0

OBSDATA_A2

OBSDATA_A0

OBSDATA_C1

Use with 920-0620 adapter board to support CPU, MCP debugging.

on even-numbered side of J1300

69 14 10

1/16W

5%

XDP

MF-LF

402

1K

R1399

1 2

72 44 21

7

72 44 21

7

XDP

402

1% 1/16W MF-LF

54.9

R1315

1

2

X5R

10% 16V

XDP

0.1uF

402

C1300

1

2

XDP

402

16V

0.1uF

10%

X5R

C1301

1

2

69 10

7

69 10

7

69 10

7 6

69 14 10

PLACEMENT_NOTE=Place close to CPU to minimize stub.

1K

5% 1/16W MF-LF

402

XDP

R1303

1 2

69 10

7

69 10

7

69 10

7

69 10

7

21

7 6

21

7 6

21

7 6

72 19

7

72 19

7

72 19

7

72 19

7

72 19

7

72 19

7

72 19

7

72 19

7

21

7 6

69 14

7

69 14

7

7 6

69 10

7 6

69 10

7 6

69 10

7 6

26 10

7

19

7

CRITICAL

6-1747769-0

XDP_CONN

F-ST-SM

J1300

61

62

63

64

1

10 11 12 13 14 15 16 17 18 19

2

20 21 22 23 24 25 26 27 28 29

3

30 31 32 33 34 35 36 37 38 39

4

40 41 42 43 44 45 46 47 48 49

5

50 51 52 53 54 55 56 57 58 59

6

60

7 8 9

109

02

SYNC_MASTER=M99_MLB

SYNC_DATE=01/08/2008

13

eXtended Debug Port(MiniXDP)

051-8089

FSB_CPURST_L

CPU_PWRGD

XDP_BPM_L<0>

XDP_BPM_L<4>

XDP_BPM_L<3> XDP_BPM_L<2>

XDP_BPM_L<1>

TP_XDP_OBSFN_B1

TP_XDP_OBSFN_B0

TP_XDP_OBSDATA_B0

TP_XDP_OBSDATA_B2 TP_XDP_OBSDATA_B3

XDP_OBS20

PM_LATRIGGER_L JTAG_MCP_TCK

MCP_DEBUG<3>

XDP_TRST_L

MCP_DEBUG<1>

MCP_DEBUG<2>

JTAG_MCP_TMS

MCP_DEBUG<0>

JTAG_MCP_TDI

JTAG_MCP_TRST_L

JTAG_MCP_TDO_CONN

XDP_BPM_L<5>

XDP_TCK

FSB_CLK_ITP_P

MCP_DEBUG<7>

MCP_DEBUG<6>

MCP_DEBUG<5>

MCP_DEBUG<4>

XDP_TMS

XDP_TDI

XDP_DBRESET_L

XDP_CPURST_L

FSB_CLK_ITP_N

TP_XDP_OBSDATA_B1

=PP3V3_S0_XDP

XDP_TDO_CONN

XDP_PWRGD

SMBUS_MCP_0_CLK

=PP1V05_S0_CPU

SMBUS_MCP_0_DATA

7

69

7

6 8

7

6 8

10 11 12

IN IN IN

IN

OUT

BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI

BI BI

BI

BI BI BI

BI

IN

BI

OUT

OUT OUT OUT

OUT OUT

OUT OUT OUT OUT OUT OUT

OUT

OUT OUT OUT OUT OUT

OUT OUT

IN

BI BI

CPU_BR0#

CPU_BNR#

BCLK_OUT_NB_N

CPU_BR1#

CPU_REQ4#

CPU_ADS#

CPU_A27#

CPU_A26#

CPU_A25#

CPU_A34#

CPU_D62#

CPU_D61#

CPU_D60#

CPU_A28# CPU_A29# CPU_A30# CPU_A31# CPU_A32#

CPU_A22# CPU_A23# CPU_A24#

CPU_REQ3#

CPU_REQ2#

CPU_DBI3#

CPU_D14#

CPU_D13#

CPU_D12#

CPU_D11#

CPU_D10#

CPU_DPWR#

CPU_RS1#

BCLK_VML_COMP_GND

CPU_COMP_VCC

CPU_TRDY#

CPU_PROCHOT#

CPU_BSEL0

CPU_RS2#

CPU_BSEL1

BCLK_IN_P

BCLK_OUT_CPU_N

CPU_PWRGD

CPU_DSTBP0#

CPU_DSTBP1#

CPU_DBI1#

CPU_DBI0#

CPU_DSTBN1#

CPU_DSTBN0#

CPU_DBI2#

CPU_DSTBP2# CPU_DSTBN2#

CPU_DSTBP3#

CPU_A4#

CPU_DSTBN3#

CPU_A3#

CPU_A5#

CPU_A9#

CPU_A8#

CPU_A6# CPU_A7#

CPU_A12#

CPU_A14#

CPU_A13#

CPU_A11#

CPU_A15# CPU_A16#

CPU_A19#

CPU_A17# CPU_A18#

CPU_A20# CPU_A21#

CPU_A35#

CPU_A33#

CPU_ADSTB0#

CPU_REQ0#

CPU_LOCK#

CPU_HIT# CPU_HITM#

CPU_FERR#

CPU_THERMTRIP#

CPU_PECI

CPU_COMP_GND

CPU_D0# CPU_D1#

CPU_D3#

CPU_D2#

CPU_D4# CPU_D5# CPU_D6#

CPU_D8#

CPU_D7#

CPU_D9#

CPU_D15#

CPU_D17# CPU_D18#

CPU_D16#

CPU_D19# CPU_D20# CPU_D21#

CPU_D23#

CPU_D22#

CPU_D24# CPU_D25# CPU_D26# CPU_D27# CPU_D28# CPU_D29# CPU_D30# CPU_D31# CPU_D32# CPU_D33# CPU_D34# CPU_D35# CPU_D36#

CPU_D38#

CPU_D37#

CPU_D39# CPU_D40# CPU_D41#

CPU_D43#

CPU_D42#

CPU_D44# CPU_D45# CPU_D46# CPU_D47#

CPU_D52# CPU_D53# CPU_D54# CPU_D55# CPU_D56# CPU_D57# CPU_D58# CPU_D59#

CPU_D63#

CPU_BPRI#

CPU_DEFER#

BCLK_OUT_CPU_P

BCLK_OUT_ITP_P BCLK_OUT_ITP_N

BCLK_OUT_NB_P

BCLK_IN_N

CPU_A20M#

CPU_NMI

CPU_INTR

CPU_SMI#

CPU_RESET#

CPU_SLP#

CPU_DPSLP#

CPU_STPCLK# CPU_DPRSTP#

CPU_D51#

CPU_D50#

CPU_D49#

CPU_D48#

CPU_ADSTB1#

CPU_IGNNE#

CPU_INIT#

BCLK_VML_COMP_VDD

CPU_RS0#

+V_DLL_DLCELL_AVDD +V_PLL_MCLK +V_PLL_FSB +V_PLL_CPU

CPU_A10#

CPU_BSEL2

CPU_DBSY# CPU_DRDY#

CPU_REQ1#

FSB

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

270 mA (A01)

Loop-back clock for delay matching.

20 mA

206 mA

15 mA

(MCP_BSEL<0>)

(MCP_BSEL<1>)

(MCP_BSEL<2>)

29 mA

9

69 10

69 13 10

69 10

69 13

7

69 13

7

69 10

69 13 10

69 10

69 60 10

9

69 60 42 10

69 42 10

69 10

49.9

1/16W

1%

402

MF-LF

R1436

1

2

1/16W

1%

402

MF-LF

49.9

R1431

1

2

49.9

MF-LF

402

1%

1/16W

R1430

1

2

402

49.9

1/16W

1%

MF-LF

R1435

1

2

NO STUFF

402

5%

1K

1/16W MF-LF

R1422

1

2

NO STUFF

1K

402

MF-LF

1/16W

5%

R1421

1

2

NO STUFF

1K

5%

402

MF-LF

1/16W

R1420

1

2

402

1/16W

62

5%

MF-LF

R1415

1

2

MF-LF

1/16W

402

1%

54.9

R1410

1

2

5% 1/16W

150

NO STUFF

402

MF-LF

R1440

1

2

OMIT

MCP79-TOPO-B

(1 OF 11)

BGA

U1400

AK41

AJ40

G41

G42

AL42

AL43

AK42

AL41

AM40

AM39

AF35

AG35

AG39 AE33

AG37 AG38

AG34

AN38 AL39

AG33

AL33

AF41

AJ33

AN36

AJ35 AJ37

AJ36 AJ38

AL37

AL34 AN37

AC34

AJ34

AL38 AL35

AN34

AR39 AN35

AE38

AE34

AC37 AE37

AE35

AB35

AD42

AE36

AK35

AD43

AA41

AE40

AL32

F41

D42

F42

AM42

AM43

Y43

W42

R42 T39

T42 T41

R41

T43 W35

AA37

W33 W34

Y40

AA36

AA34 AA38

AA35 U38

U36

U35 U33

U34

W38

W41

R33

U37

N34 N33

R34 R35

P35

R39 R37

R38

Y39

L37 L39

L38

N36 N38

J39 J38

J37

L42 M42

V42

P41

N41 N40

M40

H40 K42

H41 L41

H43

H42

Y41

K41

J40

H39 M43

Y42 P42

U41

V41

V35

N35

J41

AD39

AA40

AN32

AN33 AM32

AD41

U40

W37

L36

M41

T40

W39

N37

M39

AH40

AB42 AD40

AH39

AH42 AF42

AC43

AG41

E41

AJ41

AH43

AC38

AA33 AC39

AC33

AC35

H38

AC41 AB41

AC42

AM33

AH41

AG42

AG43

AE41

AG27

AH28

AG28

AH27

62

MF-LF

5%

402

1/16W

R1416

1

2

02

14

109

SYNC_DATE=08/17/2008SYNC_MASTER=K36B_MLB

MCP CPU Interface

051-8089

FSB_DSTB_L_P<2>

FSB_DSTB_L_P<3>

FSB_DINV_L<3>

FSB_A_L<3>

FSB_A_L<12>

FSB_A_L<23>

FSB_CLK_MCP_N

FSB_CLK_MCP_P

CPU_PROCHOT_L

FSB_RS_L<2>

FSB_RS_L<1>

FSB_RS_L<0>

MCP_BCLK_VML_COMP_GND

MCP_CPU_COMP_VCC MCP_CPU_COMP_GND

CPU_PECI_MCP

=PP1V05_S0_MCP_FSB

FSB_TRDY_L

FSB_HITM_L

FSB_HIT_L

FSB_DRDY_L

FSB_DBSY_L

FSB_BREQ0_L

FSB_BNR_L

FSB_ADS_L

FSB_A_L<21>

FSB_A_L<14>

FSB_A_L<16>

FSB_A_L<15>

FSB_A_L<33>

FSB_A_L<25>

FSB_DINV_L<0>

FSB_DINV_L<2>

FSB_DSTB_L_N<3>

FSB_A_L<4>

FSB_A_L<6> FSB_A_L<7> FSB_A_L<8> FSB_A_L<9>

FSB_A_L<17> FSB_A_L<18>

FSB_A_L<24>

FSB_A_L<26> FSB_A_L<27>

FSB_A_L<30>

FSB_A_L<35>

FSB_ADSTB_L<1>

FSB_REQ_L<0> FSB_REQ_L<1> FSB_REQ_L<2> FSB_REQ_L<3> FSB_REQ_L<4>

FSB_LOCK_L

FSB_D_L<0> FSB_D_L<1> FSB_D_L<2> FSB_D_L<3>

FSB_D_L<20>

CPU_INTR

CPU_DPRSTP_L

FSB_DSTB_L_N<2>

FSB_A_L<32>

FSB_ADSTB_L<0>

FSB_A_L<31>

FSB_A_L<28>

FSB_A_L<22>

FSB_A_L<20>

FSB_A_L<10> FSB_A_L<11>

FSB_A_L<13>

FSB_DINV_L<1>

FSB_DSTB_L_N<1>

FSB_DSTB_L_P<1>

FSB_DSTB_L_N<0>

FSB_DSTB_L_P<0>

FSB_BREQ1_L

FSB_D_L<47>

FSB_D_L<33>

FSB_D_L<31>

FSB_D_L<25>

FSB_D_L<14>

FSB_D_L<11>

FSB_D_L<4> FSB_D_L<5> FSB_D_L<6> FSB_D_L<7> FSB_D_L<8> FSB_D_L<9> FSB_D_L<10>

FSB_D_L<12> FSB_D_L<13>

FSB_D_L<15> FSB_D_L<16> FSB_D_L<17> FSB_D_L<18> FSB_D_L<19>

FSB_D_L<21> FSB_D_L<22> FSB_D_L<23> FSB_D_L<24>

FSB_D_L<26> FSB_D_L<27> FSB_D_L<28> FSB_D_L<29> FSB_D_L<30>

FSB_D_L<32>

FSB_D_L<34> FSB_D_L<35> FSB_D_L<36> FSB_D_L<37> FSB_D_L<38> FSB_D_L<39> FSB_D_L<40> FSB_D_L<41> FSB_D_L<42> FSB_D_L<43> FSB_D_L<44> FSB_D_L<45> FSB_D_L<46>

FSB_D_L<48> FSB_D_L<49>

FSB_D_L<51> FSB_D_L<52>

FSB_D_L<60>

FSB_D_L<53>

FSB_D_L<55>

FSB_D_L<57> FSB_D_L<58> FSB_D_L<59>

FSB_D_L<56>

FSB_D_L<54>

FSB_D_L<50>

FSB_BPRI_L FSB_DEFER_L

FSB_CLK_CPU_P FSB_CLK_CPU_N

FSB_CLK_ITP_P FSB_CLK_ITP_N

CPU_A20M_L

CPU_STPCLK_L

FSB_DPWR_L

CPU_DPSLP_L

FSB_CPURST_L

FSB_A_L<29>

FSB_A_L<34>

FSB_D_L<63>

FSB_D_L<62>

FSB_D_L<61>

PM_THRMTRIP_L

CPU_IGNNE_L CPU_INIT_L

=MCP_BSEL<0>

=MCP_BSEL<1>

CPU_NMI

PP1V05_S0_MCP_PLL_FSB

CPU_SMI_L

CPU_PWRGD

FSB_CPUSLP_L

MCP_BCLK_VML_COMP_VDD

=MCP_BSEL<2>

CPU_FERR_L

=PP1V05_S0_MCP_FSB

FSB_A_L<5>

FSB_A_L<19>

69

8

14 22 24

69

24

69

8

14 22 24

0A

MEMORY

MEMORY PARTITION 0

CONTROL

MCKE0A_1 MCKE0A_0

MODT0A_1 MODT0A_0

MCS0A_0#

MCS0A_1#

MCLK0A_0_N

MCLK0A_0_P

MCLK0A_1_N

MCLK0A_2_N

MCLK0A_1_P

MCLK0A_2_P

MA0_0

MA0_1

MA0_2

MA0_3

MA0_4

MA0_5

MA0_6

MA0_8 MA0_7

MA0_9

MA0_10

MA0_11

MA0_13 MA0_12

MA0_14

MBA0_2

MBA0_0

MBA0_1

MWE0#

MCAS0#

MRAS0#

MDQS0_0_P MDQS0_0_N

MDQS0_1_P

MDQS0_2_N

MDQS0_1_N

MDQS0_2_P

MDQS0_3_N

MDQS0_4_P

MDQS0_3_P

MDQS0_4_N

MDQS0_5_N

MDQS0_5_P

MDQS0_6_N

MDQS0_6_P

MDQS0_7_N

MDQS0_7_P

MDQM0_2 MDQM0_1 MDQM0_0

MDQM0_3

MDQM0_4

MDQ0_0

MDQM0_7

MDQM0_5

MDQM0_6

MDQ0_1

MDQ0_4 MDQ0_3 MDQ0_2

MDQ0_5

MDQ0_6

MDQ0_9 MDQ0_8 MDQ0_7

MDQ0_10

MDQ0_11

MDQ0_15 MDQ0_14 MDQ0_13 MDQ0_12

MDQ0_16

MDQ0_21 MDQ0_20

MDQ0_18

MDQ0_19

MDQ0_17

MDQ0_25 MDQ0_24 MDQ0_23 MDQ0_22

MDQ0_26

MDQ0_29 MDQ0_28 MDQ0_27

MDQ0_30

MDQ0_31

MDQ0_35 MDQ0_34

MDQ0_32

MDQ0_36

MDQ0_33

MDQ0_41

MDQ0_37

MDQ0_38

MDQ0_40 MDQ0_39

MDQ0_42

MDQ0_47 MDQ0_46

MDQ0_43

MDQ0_45 MDQ0_44

MDQ0_51 MDQ0_50 MDQ0_49

MDQ0_52

MDQ0_48

MDQ0_55 MDQ0_54 MDQ0_53

MDQ0_56

MDQ0_57

MDQ0_61 MDQ0_60

MDQ0_58

MDQ0_59

MDQ0_62

MDQ0_63

OUT

OUT OUT OUT OUT OUT OUT

BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

OUT OUT OUT

OUT OUT

BI BI

BI

BI BI

BI

BI BI BI BI

BI BI

BI

BI BI BI

BI

BI BI BI BI BI BI

BI

OUT OUT OUT

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

OUT OUT

MEMORY

CONTROL

1A

MEMORY PARTITION 1

MDQ1_63

MDQ1_60 MDQ1_59

MDQ1_62

MDQ1_58

MDQ1_61

MDQ1_57

MDQ1_53

MDQ1_56 MDQ1_55 MDQ1_54

MDQ1_52

MDQ1_49

MDQ1_51 MDQ1_50

MDQ1_48 MDQ1_47 MDQ1_46

MDQ1_43

MDQ1_44

MDQ1_45

MDQ1_42 MDQ1_41

MDQ1_37

MDQ1_38

MDQ1_39

MDQ1_36 MDQ1_35

MDQ1_32

MDQ1_33

MDQ1_34

MDQ1_31 MDQ1_30

MDQ1_27

MDQ1_28

MDQ1_29

MDQ1_22

MDQ1_26 MDQ1_25 MDQ1_24 MDQ1_23

MDQ1_17

MDQ1_19

MDQ1_20

MDQ1_18

MDQ1_21

MDQ1_16

MDQ1_12

MDQ1_13

MDQ1_14

MDQ1_15

MDQ1_11 MDQ1_10

MDQ1_7

MDQ1_8

MDQ1_9

MDQ1_3

MDQ1_6

MDQ1_2

MDQ1_4

MDQ1_5

MDQ1_1

MDQM1_6 MDQM1_5

MDQ1_0

MDQM1_7

MDQM1_4 MDQM1_3

MDQM1_0

MDQM1_1

MDQM1_2

MDQ1_40

MDQS1_7_P

MDQS1_6_N

MDQS1_6_P

MDQS1_7_N

MDQS1_5_N

MDQS1_5_P

MDQS1_4_P

MDQS1_3_P

MDQS1_4_N

MDQS1_2_P

MDQS1_3_N

MDQS1_1_P

MDQS1_2_N

MDQS1_1_N MDQS1_0_P MDQS1_0_N

MRAS1# MCAS1#

MWE1#

MBA1_2 MBA1_1 MBA1_0

MA1_14 MA1_13 MA1_12 MA1_11 MA1_10

MA1_9 MA1_8 MA1_7 MA1_6 MA1_5 MA1_4 MA1_3 MA1_2 MA1_1 MA1_0

MCLK1A_2_P

MCLK1A_1_P

MCLK1A_2_N

MCLK1A_0_P

MCLK1A_1_N

MCS1A_1# MCS1A_0#

MCLK1A_0_N

MODT1A_1 MODT1A_0

MCKE1A_0

MCKE1A_1

BI BI BI

BI

BI BI BI

BI

BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI

BI

BI BI BI

BI

BI BI BI

BI

BI BI BI BI BI BI

BI

OUT

BI

OUT OUT OUT OUT OUT OUT OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

OMIT

BGA

MCP79-TOPO-B

(2 OF 11)

U1400

AR19

AT19

AN19

AW21

AN23

AU15

AR23

AU19

AV19

AN21

AR21

AP21

AU21

AR22

AV21

AW17

AP19

AP23

AP17

AT23

AU23

BC20

BB20

AY24

BA24

AV33

AW33

AR18

AT15

AP35

AR35

AV31

AT31

AW37

AV37

AR33

AU31

AN31

AV29

AN29

AV27

AW38

AR31

AP31

AR29

AP29

AR27

AP27

AR25

AP25

AU27

AT27

AV38

AU25

AR26

AU13

AR14

AT11

AR11

AW13

AV13

AV11

AU11

AR38

AV9

AU9

AY5

AW6

AP11

AW9

AU8

AU7

AV5

AU6

AR37

AR5

AN10

AW5

AV6

AR7

AR6

AN7

AN6

AL7

AL6

AV39

AN9

AP9

AL9

AL8

AW39

AU37

AT37

AR34

AV35

AW29

AN27

AN13

AR10

AU5

AN5

AT39

AU39

AU35

AT35

AU29

AU30

AW25

AV25

AR13

AP13

AW8

AW7

AR9

AR8

AL11

AL10

AV15

AP15

AV17

AR17

70 28

70 30 28

70 28

70 30 28

70 28

70 29

70 30 29

70 29

70 30 29

OMIT

(3 OF 11)

MCP79-TOPO-B

BGA

U1400

BA18

BB25

BA17

BC28

AW28

BA14

BA29

BA25

BB26

BA26

BA27

AY27

BA28

AY28

BB28

BB17

BB18

BB29

BA15

BB30

AY31

AY19

BA19

BA22

BB22

BB42

BA42

BB16

BB14

AP42

AR41

BC40

BA40

AV41

AV42

AW40

BB40

AY39

BA38

BB36

BA36

AU41

AY40

BA39

AW36

BC36

AY35

BA34

BB32

BA32

AY36

BA35

AU40

AW32

BC32

BA12

AY12

BB9

BB8

AW12

BB12

BB10

BA9

AN40

AY8

BA7

BC4

BB4

BC8

BA8

BA5

BB5

BB2

BA3

AP41

AW3

AW4

BC3

BB3

AY3

AY4

AU3

AU2

AR3

AR4

AT41

AV3

AV2

AT3

AT4

AT40

AW41

AW42

AR42

AY43

BB38

BB34

BA11

AY7

BA2

AT5

AT43

AT42

AY42

BA43

BA37

BB37

BA33

BB33

AY11

BA10

BA6

BB6

AY1

AY2

AT1

AT2

AY15

BB13

AW16

BA16

70 29

109

02

15

SYNC_DATE=08/17/2008SYNC_MASTER=K36B_MLB

MCP Memory Interface

051-8089

MEM_A_DQ<36>

MEM_B_DM<5>

MEM_A_DQ<47>

MEM_B_DQS_P<7> MEM_B_DQS_N<7> MEM_B_DQS_P<6> MEM_B_DQS_N<6> MEM_B_DQS_P<5> MEM_B_DQS_N<5> MEM_B_DQS_P<4> MEM_B_DQS_N<4> MEM_B_DQS_P<3> MEM_B_DQS_N<3> MEM_B_DQS_P<2> MEM_B_DQS_N<2> MEM_B_DQS_P<1> MEM_B_DQS_N<1> MEM_B_DQS_P<0> MEM_B_DQS_N<0>

MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L

MEM_B_BA<2> MEM_B_BA<1>

MEM_B_A<14> MEM_B_A<13> MEM_B_A<12> MEM_B_A<11> MEM_B_A<10> MEM_B_A<9> MEM_B_A<8> MEM_B_A<7>

MEM_B_A<5> MEM_B_A<4>

MEM_B_A<2> MEM_B_A<1> MEM_B_A<0>

MEM_B_DQ<63> MEM_B_DQ<62> MEM_B_DQ<61> MEM_B_DQ<60> MEM_B_DQ<59> MEM_B_DQ<58> MEM_B_DQ<57> MEM_B_DQ<56> MEM_B_DQ<55> MEM_B_DQ<54> MEM_B_DQ<53> MEM_B_DQ<52> MEM_B_DQ<51> MEM_B_DQ<50> MEM_B_DQ<49> MEM_B_DQ<48> MEM_B_DQ<47> MEM_B_DQ<46> MEM_B_DQ<45> MEM_B_DQ<44> MEM_B_DQ<43> MEM_B_DQ<42> MEM_B_DQ<41> MEM_B_DQ<40> MEM_B_DQ<39> MEM_B_DQ<38> MEM_B_DQ<37> MEM_B_DQ<36> MEM_B_DQ<35> MEM_B_DQ<34> MEM_B_DQ<33> MEM_B_DQ<32> MEM_B_DQ<31> MEM_B_DQ<30> MEM_B_DQ<29> MEM_B_DQ<28> MEM_B_DQ<27> MEM_B_DQ<26> MEM_B_DQ<25> MEM_B_DQ<24> MEM_B_DQ<23> MEM_B_DQ<22> MEM_B_DQ<21> MEM_B_DQ<20> MEM_B_DQ<19> MEM_B_DQ<18> MEM_B_DQ<17> MEM_B_DQ<16> MEM_B_DQ<15> MEM_B_DQ<14> MEM_B_DQ<13> MEM_B_DQ<12> MEM_B_DQ<11> MEM_B_DQ<10> MEM_B_DQ<9>

MEM_B_DQ<2> MEM_B_DQ<1> MEM_B_DQ<0>

MEM_B_DM<6>

MEM_B_DM<4>

MEM_B_DM<1>

MEM_B_DQ<3>

MEM_B_DQ<4>

MEM_B_DQ<5>

MEM_B_DQ<7> MEM_B_DQ<6>

MEM_A_DQ<61>

MEM_A_DQ<59>

MEM_A_DQ<60>

MEM_A_DQ<57> MEM_A_DQ<56>

MEM_A_DQ<48>

MEM_A_DQ<51>

MEM_A_DQ<44>

MEM_A_DQ<45>

MEM_A_DQ<43>

MEM_A_DQ<46>

MEM_A_DQ<42>

MEM_A_DQ<39>

MEM_A_DQ<40>

MEM_A_DQ<38> MEM_A_DQ<37>

MEM_A_DQ<41>

MEM_A_DQ<33> MEM_A_DQ<32>

MEM_A_DQ<34>

MEM_A_DQ<35>

MEM_A_DQ<31> MEM_A_DQ<30>

MEM_A_DQ<27>

MEM_A_DQ<28>

MEM_A_DQ<29>

MEM_A_DQ<26>

MEM_A_DQ<22>

MEM_A_DQ<23>

MEM_A_DQ<24>

MEM_A_DQ<25>

MEM_A_DQ<17>

MEM_A_DQ<19> MEM_A_DQ<18>

MEM_A_DQ<20>

MEM_A_DQ<21>

MEM_A_DQ<16>

MEM_A_DQ<12>

MEM_A_DQ<13>

MEM_A_DQ<14>

MEM_A_DQ<15>

MEM_A_DQ<11> MEM_A_DQ<10>

MEM_A_DQ<7>

MEM_A_DQ<8>

MEM_A_DQ<9>

MEM_A_DQ<6> MEM_A_DQ<5>

MEM_A_DQ<2>

MEM_A_DQ<3>

MEM_A_DQ<4>

MEM_A_DQ<1>

MEM_A_DM<6> MEM_A_DM<5>

MEM_A_DM<7>

MEM_A_DQ<0>

MEM_A_DM<4> MEM_A_DM<3>

MEM_A_DM<0>

MEM_A_DM<1>

MEM_A_DM<2>

MEM_A_DQS_P<7>

MEM_A_DQS_N<6> MEM_A_DQS_P<5> MEM_A_DQS_N<5>

MEM_A_DQS_N<4> MEM_A_DQS_P<3>

MEM_A_DQS_P<4>

MEM_A_DQS_N<3> MEM_A_DQS_P<2>

MEM_A_DQS_N<1>

MEM_A_DQS_P<1>

MEM_A_DQS_N<0>

MEM_A_DQS_P<0>

MEM_A_RAS_L

MEM_A_BA<1> MEM_A_BA<0>

MEM_A_BA<2>

MEM_A_A<14>

MEM_A_A<12>

MEM_A_A<13>

MEM_A_A<11> MEM_A_A<10> MEM_A_A<9>

MEM_A_A<7>

MEM_A_A<8>

MEM_A_A<6>

MEM_A_A<2>

MEM_A_WE_L

MEM_A_CAS_L

MEM_A_ODT<1>

MEM_A_CKE<1> MEM_A_CKE<0> MEM_B_CKE<0>

MEM_B_DM<7>

MEM_A_A<0>

MEM_A_A<1>

MEM_A_A<4>

MEM_A_A<5>

MEM_A_CLK_P<0>

MEM_A_CS_L<1>

MEM_A_CLK_N<0>

TP_MEM_A_CLK2P

MEM_A_CS_L<0>

TP_MEM_B_CLK2P TP_MEM_B_CLK2N

MEM_B_CS_L<1> MEM_B_CS_L<0>

MEM_A_ODT<0>

MEM_A_CLK_N<1>

TP_MEM_A_CLK2N

MEM_A_CLK_P<1>

MEM_B_DM<3>

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_CLK_N<1>

MEM_B_CLK_P<1>

MEM_A_DQ<58>

MEM_B_DM<0>

MEM_B_DM<2>

MEM_B_CKE<1>

MEM_B_ODT<0>

MEM_B_ODT<1>

MEM_A_DQS_N<2>

MEM_A_DQ<62>

MEM_B_BA<0>

MEM_B_A<6>

MEM_B_A<3>

MEM_B_DQ<8>

MEM_A_DQ<53>

MEM_A_A<3>

MEM_A_DQS_P<6>

MEM_A_DQS_N<7>

MEM_A_DQ<63>

MEM_A_DQ<52>

MEM_A_DQ<54>

MEM_A_DQ<55>

MEM_A_DQ<50> MEM_A_DQ<49>

MCLK1B_2_P

MCLK1B_1_N

MCLK1B_0_P

MCLK1B_1_P

MCLK1B_2_N

MCS1B_1#

MCS1B_0#

MCLK1B_0_N

MODT1B_0

MCKE1B_1

MCKE1B_0

MODT1B_1

MRESET0#

GND55 GND56 GND57 GND58

GND60

GND59

GND61 GND62 GND63 GND64

GND52 GND53 GND54

GND51

GND49 GND50

GND48

GND47

GND46

GND44 GND45

GND43

GND42

GND41

GND39 GND40

GND38

GND37

GND36

GND35

GND33 GND34

GND32

GND31

GND30

GND28 GND29

GND27

GND26

GND25

GND24

GND18 GND19

GND17

GND16

GND15

GND13 GND14

GND10

GND12

GND11

GND8 GND9

GND7

GND6

GND5

GND2 GND3 GND4

GND1

MEM_COMP_VDD MEM_COMP_GND

MODT0B_0 MODT0B_1

MCKE0B_1

MCKE0B_0

MCLK0B_0_N

MCS0B_0# MCS0B_1#

MCLK0B_2_N

MCLK0B_1_P

MCLK0B_0_P

MCLK0B_1_N

MCLK0B_2_P

+V_PLL_XREF_XS

+V_PLL_CORE +V_VPLL

+VDD_MEM1 +VDD_MEM2 +VDD_MEM3 +VDD_MEM4 +VDD_MEM5 +VDD_MEM6 +VDD_MEM7 +VDD_MEM8

+VDD_MEM9 +VDD_MEM10 +VDD_MEM11

+VDD_MEM14 +VDD_MEM15 +VDD_MEM16 +VDD_MEM17 +VDD_MEM18 +VDD_MEM19 +VDD_MEM20

+VDD_MEM22

+VDD_MEM21

+VDD_MEM23 +VDD_MEM24 +VDD_MEM25 +VDD_MEM26

+VDD_MEM30

+VDD_MEM27

+VDD_MEM29

+VDD_MEM31 +VDD_MEM32 +VDD_MEM33 +VDD_MEM34

+VDD_MEM38 +VDD_MEM39 +VDD_MEM40 +VDD_MEM41

+VDD_MEM43 +VDD_MEM44 +VDD_MEM45

+VDD_MEM42

+V_PLL_DP

+VDD_MEM13

+VDD_MEM12

+VDD_MEM28

+VDD_MEM37

+VDD_MEM36

+VDD_MEM35

GND21

GND20

GND22 GND23

MEMORY CONTROL 0B

MEMORY CONTROL 1B

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

87 mA (A01)

19 mA

17 mA 12 mA

39 mA

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

TP or NC for DDR2.

4771 MA (A01, DDR2)

MF-LF

402

1/16W

40.2

1%

R1610

1

2

40.2

1/16W

1%

MF-LF

402

R1611

1

2

OMIT

BGA

MCP79-TOPO-B

(4 OF 11)

U1400

AA22

AA39

AB22

AB7

AD22

AE20 AF24

AG24 AH35

AK7

AM28

AP12

AT25

AP30

AR36 AU10

F28

BC21

AY9

BC9 D34

F24

G30

G32 H31

K7

M38

M5

M6

M7 M9

N39

N8

P10

P33

P34 P37

P4

P40

P7

R36

R40 R43

R5

T10

T18

T20

AK11

T24

T26

T33

T34

T35 T37

T38

T6

T7

T9

U18 U20

U22

V10

V34

W5

AV23

AN25

BA30

BA31

BB21

BA21

BC24

BB24

AU34

AU33

AY20

BA20

BA23

AY23

BB41

BA41

AU17 AR15

BC16 BA13

AM41

AN41

AN17

AN15

AY16

BC13

AY32

U27

U28

T27

T28

AM17

AN20 AN24

AT17

AP16 AN22

AP20

AP24 AV16

AR16 AR20

AM19

AR24

AW15 AP22

AP18

AU16 AN18

AU24

AT21 AY29

AV24

AM21

AU20

AU22

AW27 BC17

AV20

AY17 AY18

AM15

AU18 AY25

AM23

AY26 AW19

AW24

BC25 AL30

AM31

AM25 AM27

AM29 AN16

BC29

109

16

02

SYNC_DATE=08/17/2008SYNC_MASTER=K36B_MLB

MCP Memory Misc

051-8089

MCP_MEM_RESET_L

TP_MEM_A_ODT<2>

PP1V05_S0_MCP_PLL_CORE

TP_MEM_A_CKE<2>

TP_MEM_B_CS_L<2>

MCP_MEM_COMP_GND

TP_MEM_A_CLK4N

TP_MEM_A_CLK5P TP_MEM_A_CLK5N

TP_MEM_B_CLK5P TP_MEM_B_CLK5N

TP_MEM_B_CLK4P TP_MEM_B_CLK4N

TP_MEM_B_CLK3P TP_MEM_B_CLK3N

TP_MEM_B_CS_L<3>

TP_MEM_B_ODT<2>

=PP1V8R1V5_S0_MCP_MEM

MCP_MEM_COMP_VDD

TP_MEM_A_ODT<3>

TP_MEM_A_CKE<3>

=PP1V8R1V5_S0_MCP_MEM

TP_MEM_A_CLK3N

TP_MEM_A_CLK3P

TP_MEM_A_CLK4P

TP_MEM_B_CKE<2> TP_MEM_B_CKE<3>

TP_MEM_A_CS_L<3>

TP_MEM_B_ODT<3>

TP_MEM_A_CS_L<2>

9

24

70

8

16 24

70

8

16 24

PE0_RX0_P

PE0_RX2_N

+AVDD0_PEX11

+AVDD0_PEX7 +AVDD0_PEX8

+AVDD1_PEX3

+AVDD1_PEX2

+AVDD1_PEX1

+AVDD0_PEX13

+AVDD0_PEX12

+AVDD0_PEX10

+AVDD0_PEX9

+AVDD0_PEX6

+AVDD0_PEX5

+AVDD0_PEX4

+AVDD0_PEX3

+AVDD0_PEX2

+AVDD0_PEX1

+V_PLL_PEX

+DVDD1_PEX2

+DVDD1_PEX1

+DVDD0_PEX8

+DVDD0_PEX7

+DVDD0_PEX6

+DVDD0_PEX5

+DVDD0_PEX4

+DVDD0_PEX3

+DVDD0_PEX2

+DVDD0_PEX1

PE0_RX0_N

PE0_RX2_P

PE0_RX4_P

PE0_RX6_P

PEB_PRSNT#

PE1_TX3_N

PE1_TX3_P

PE1_TX2_N

PE1_TX1_N

PE1_TX2_P

PE1_TX0_N

PE1_TX1_P

PE6_REFCLK_N

PEX_RST0#

PE1_TX0_P

PE5_REFCLK_N

PE5_REFCLK_P

PE6_REFCLK_P

PE4_REFCLK_N

PE4_REFCLK_P

PE3_REFCLK_N

PE2_REFCLK_N

PE1_REFCLK_N

PE2_REFCLK_P

PE0_REFCLK_N

PE0_REFCLK_P

PE1_REFCLK_P

PE0_TX15_N

PE0_TX14_N PE0_TX15_P

PE0_TX13_N PE0_TX14_P

PE0_TX12_N

PE0_TX12_P

PE0_TX13_P

PE0_TX11_N

PE0_TX11_P

PE0_TX10_N

PE0_TX9_N PE0_TX10_P

PE0_TX8_N

PE0_TX8_P

PE0_TX9_P

PE0_TX7_N

PE0_TX7_P

PE0_TX6_N

PE0_TX5_N

PE0_TX6_P

PE0_TX4_N

PE0_TX5_P

PE0_TX3_N

PE0_TX3_P

PE0_TX4_P

PE0_TX2_N

PE0_TX2_P

PE0_TX0_N

PE0_TX1_N

PE0_TX1_P

PE0_TX0_P

PEX_CLK_COMP

PE1_RX3_N

PE1_RX3_P

PE1_RX2_N

PE1_RX0_N

PE1_RX1_P

PE1_RX2_P

PE1_RX1_N

PE_WAKE#

PE1_RX0_P

PE0_PRSNT_16#

PE0_RX13_N PE0_RX14_P

PE0_RX15_P

PE0_RX14_N

PE0_RX15_N

PE0_RX12_P

PE0_RX11_P

PE0_RX13_P

PE0_RX11_N

PE0_RX12_N

PE0_RX10_N

PE0_RX8_P

PE0_RX9_P

PE0_RX10_P

PE0_RX8_N

PE0_RX9_N

PE0_RX5_N

PE0_RX7_P

PE0_RX6_N

PE0_RX7_N

PE0_RX3_P

PE0_RX5_P

PE0_RX3_N

PE0_RX4_N

PE0_RX1_P PE0_RX1_N

PEC_PRSNT#

PEC_CLKREQ#/GPIO_50

PE3_REFCLK_P

PED_CLKREQ#/GPIO_51

PED_PRSNT#

PEB_CLKREQ#/GPIO_49

PEE_CLKREQ#/GPIO_16 PEE_PRSNT#/GPIO_46

PEF_CLKREQ#/GPIO_17 PEF_PRSNT#/GPIO_47

PEG_CLKREQ#/GPIO_18 PEG_PRSNT#/GPIO_48

PCI EXPRESS

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

OUT OUT

OUT

OUT OUT

OUT

IN IN

IN

IN IN

OUT

OUT OUT

OUT

IN

OUT

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Int PU

84 mA (A01)

Int PU

Int PU (S5)

IF PE1 INTERFACE IS NOT USED, GROUND DVDD1_PEX AND AVDD1_PEX

IF PE0 INTERFACE IS NOT USED, GROUND DVDD0_PEX AND AVDD0_PEX.

OMIT

BGA

(5 OF 11)

MCP79-TOPO-B

U1400

Y12

AC12 AD12

V12

W12

AA12 AB12

M12 P12

R12

N12 T12

U12

M13 N13

P13

T17

W19 U17

V19 W16

W17

W18 U16

T19 U19

T16

C9

D11

E11

E7

F7

L8

L9

L6

L7

N10

N11

P9

N9

N6

N7

N4

N5

C7

D7

F6

E6

F5

E5

E3

E4

D3

C3

H5

G5

J6

J7

J4

J5

L10

L11

D4

C5

J1

H1

J3

J2

K3

K2

L3

L4

M3

M4

M1

M2

B4

C4

A3

A4

B2

B3

D1

C1

E1

D2

F2

E2

F4

F3

H4

G3

H2

H3

F11

G11

J9

K9

G9

H9

E9

F9

G7

H7

C8

D8

A8

B8

B7

A7

C6

B6

J10

J11

F13

G13

H13

J13

K14

L14

M14

N14

F17

D5 D9

E8

C10

M15 B10

L16 L18

M16

M18

M17

M19

A11

K11

9

71

9

71

9

71 31

7

71 31

7

9

35

31

7

71 35

71

9

71

9

31

7

31

9

71 31

7

71 31

7

71 35

71

9

71

9

71 31

71

9

71

9

NO STUFF

2.37K

1/16W MF-LF 402

PLACEMENT_NOTE=Place within 12.7mm of U1400

1%

R1710

1

2

26

9

109

02

17

SYNC_DATE=08/17/2008SYNC_MASTER=K36B_MLB

MCP PCIe Interfaces

051-8089

=PEG_R2D_C_P<3>

=PEG_D2R_P<6>

=PEG_D2R_N<5>

=PEG_D2R_P<5>

=PP1V05_S0_MCP_PEX_AVDD0

=PP1V05_S0_MCP_PEX_AVDD1

=PP1V05_S0_MCP_PEX_DVDD0

PCIE_EXCARD_D2R_P PCIE_EXCARD_D2R_N

TP_PCIE_PE4_D2RP TP_PCIE_PE4_D2RN

PCIE_EXCARD_PRSNT_L

EXCARD_CLKREQ_L

FW_CLKREQ_L

PCIE_MINI_PRSNT_L

TP_PE4_CLKREQ_L TP_PE4_PRSNT_L

TP_MCP_GPIO_17

PCIE_WAKE_L

PCIE_MINI_D2R_P PCIE_MINI_D2R_N

PCIE_FW_D2R_P PCIE_FW_D2R_N

=PP1V05_S0_MCP_PEX_DVDD1

PEG_CLKREQ_L EXTGPU_RESET_L

PEG_PRSNT_L

TP_PCIE_PE4_R2D_CN

PCIE_FW_R2D_C_N

PCIE_EXCARD_R2D_C_P

TP_PCIE_CLK100M_PE6N

PP1V05_S0_MCP_PLL_PEX

TP_PCIE_CLK100M_PE4N

TP_PCIE_CLK100M_PE5N

PCIE_RESET_L

PCIE_MINI_R2D_C_P

PCIE_FW_R2D_C_P

=PEG_D2R_N<15>

=PEG_D2R_N<7>

=PEG_D2R_P<0>

=PEG_D2R_N<2>

=PEG_D2R_N<0>

=PEG_D2R_P<2>

=PEG_D2R_P<4>

PCIE_EXCARD_R2D_C_N

PCIE_MINI_R2D_C_N

TP_PCIE_CLK100M_PE5P

TP_PCIE_CLK100M_PE6P

TP_PCIE_CLK100M_PE4P

PCIE_CLK100M_EXCARD_N

PCIE_CLK100M_FW_N

PCIE_CLK100M_MINI_N

PCIE_CLK100M_FW_P

PEG_CLK100M_N

PEG_CLK100M_P

PCIE_CLK100M_MINI_P

=PEG_R2D_C_N<15>

=PEG_R2D_C_N<14> =PEG_R2D_C_P<15>

=PEG_R2D_C_N<13> =PEG_R2D_C_P<14>

=PEG_R2D_C_N<12>

=PEG_R2D_C_P<12>

=PEG_R2D_C_P<13>

=PEG_R2D_C_N<11>

=PEG_R2D_C_P<11>

=PEG_R2D_C_N<10>

=PEG_R2D_C_N<9> =PEG_R2D_C_P<10>

=PEG_R2D_C_N<8>

=PEG_R2D_C_P<8>

=PEG_R2D_C_P<9>

=PEG_R2D_C_N<7>

=PEG_R2D_C_P<7>

=PEG_R2D_C_N<6>

=PEG_R2D_C_N<5> =PEG_R2D_C_P<6>

=PEG_R2D_C_N<4> =PEG_R2D_C_P<5>

=PEG_R2D_C_N<3> =PEG_R2D_C_P<4>

=PEG_R2D_C_N<2>

=PEG_R2D_C_P<2>

=PEG_R2D_C_N<0>

=PEG_R2D_C_N<1>

=PEG_R2D_C_P<1>

=PEG_R2D_C_P<0>

=PEG_D2R_N<13> =PEG_D2R_P<14>

=PEG_D2R_P<15>

=PEG_D2R_N<14>

=PEG_D2R_P<12>

=PEG_D2R_P<11>

=PEG_D2R_P<13>

=PEG_D2R_N<11>

=PEG_D2R_N<12>

=PEG_D2R_N<10>

=PEG_D2R_P<8>

=PEG_D2R_P<9>

=PEG_D2R_N<8>

=PEG_D2R_N<9>

=PEG_D2R_P<7>

=PEG_D2R_N<6>

=PEG_D2R_P<3> =PEG_D2R_N<3>

=PEG_D2R_N<4>

=PEG_D2R_P<1> =PEG_D2R_N<1>

PCIE_CLK100M_EXCARD_P

EXTGPU_PWR_EN

MINI_CLKREQ_L

MCP_PEX_CLK_COMP

PCIE_FW_PRSNT_L

TP_PCIE_PE4_R2D_CP

=PEG_D2R_P<10>

8

24

71

IN

BI

OUT

IN IN IN IN

IN IN

OUT

OUT OUT OUT OUT OUT OUT

OUT OUT

IN IN

OUT OUT

OUT OUT OUT

OUT OUT

IN

IN OUT

IN IN IN

GPIO_7/NFERR*/IGPU_GPIO_7

+V_DUAL_MACPLL

+VDD_HDMI

+V_PLL_HDMI

+V_PLL_IFPAB

+VDD_IFPB

+VDD_IFPA

+V_TV_DAC

+V_RGB_DAC

+V_DUAL_RMGT2

MII_COMP_GND

MII_COMP_VDD

LCD_PANEL_PWR/GPIO_58

LCD_BKL_ON/GPIO_59

LCD_BKL_CTL/GPIO_57

XTALOUT_TV

GPIO_6/FERR*/IGPU_GPIO_6

HDMI_TXC_P/ML0_LANE3_P HDMI_TXC_N/ML0_LANE3_N

HDMI_TXD0_P/ML0_LANE2_P HDMI_TXD0_N/ML0_LANE2_N HDMI_TXD1_P/ML0_LANE1_P HDMI_TXD1_N/ML0_LANE1_N HDMI_TXD2_P/ML0_LANE0_P HDMI_TXD2_N/ML0_LANE0_N

HPLUG_DET2/GPIO_22

IFPA_TXC_N

XTALIN_TV

DDC_DATA2/GPIO_24

DDC_CLK2/GPIO_23

RGB_DAC_RSET RGB_DAC_VREF

TV_DAC_VREF

DP_AUX_CH0_P DP_AUX_CH0_N

HPLUG_DET3

HDMI_RSET HDMI_VPROBE

RGMII_MDIO

BUF_25MHZ

DDC_DATA0

DDC_CLK0

RGB_DAC_RED

RGB_DAC_GREEN

RGB_DAC_BLUE

RGB_DAC_HSYNC RGB_DAC_VSYNC

TV_DAC_RED

TV_DAC_GREEN

IFPA_TXC_P

IFPA_TXD0_P IFPA_TXD0_N

IFPA_TXD2_P

IFPA_TXD1_P IFPA_TXD1_N

IFPA_TXD3_P

IFPA_TXD2_N

IFPB_TXC_P IFPB_TXC_N

IFPB_TXD5_P

IFPB_TXD4_P IFPB_TXD4_N

IFPB_TXD6_P

IFPB_TXD5_N

IFPB_TXD6_N IFPB_TXD7_P IFPB_TXD7_N

DDC_DATA3

DDC_CLK3

IFPAB_RSET

IFPAB_VPROBE

TV_DAC_RSET

RGMII_RXD0

RGMII_INTR/GPIO_35

RGMII_RXD3

RGMII_RXCTL/MII_RXDV

RGMII_RXC/MII_RXCLK

RGMII_RXD2

RGMII_RXD1

MII_RESET#

RGMII_MDC

RGMII_PWRDWN/GPIO_37

MII_RXER/GPIO_36 MII_COL/GPIO_20/MSMB_DATA MII_CRS/GPIO_21/MSMB_CLK

TV_DAC_BLUE

TV_DAC_HSYNC/GPIO_44 TV_DAC_VSYNC/GPIO_45

+V_DUAL_RMGT1

MII_VREF

RGMII_TXCTL/MII_TXEN

RGMII_TXC/MII_TXCLK

RGMII_TXD3

RGMII_TXD2

RGMII_TXD1

RGMII_TXD0

+3.3V_DUAL_RMGT1 +3.3V_DUAL_RMGT2

IFPA_TXD3_N

LAN

DACS

FLAT PANEL

BI

OUT

OUT OUT

OUT OUT OUT

OUT

OUT OUT OUT OUT OUT

OUT OUT

OUT OUT OUT

OUT

OUT OUT OUT OUT OUT

OUT

BI

OUT

BI

OUT

OUT OUT

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

=MCP_HDMI_DDC_CLK

Comp / Pb

131 mA (A01)

MCP79 requires a S5 pull-up.

feature via software. This

MII, RGMII products will enable

Network Interface Select

Interface

RGMII

MII 0

1

83 mA (A01)

TV DAC Disable:

NOTE: All Apple products set strap to

Y / Y

ENET_TXD<0>

DDC_CLK0/DDC_DATA0 pull-ups still required.

Okay to float XTALIN_TV and XTALOUT_TV.

95 mA (A01)

8 mA

BY DEFAULT, PULL DOWN(1K OR SRONGER) MUST BE USED

(~10K TO 3.3V). TO ENSURE PINS ARE LOW

IN MCP79 THESE PINS HAVE UNDOCUMENTED PULL HIGH

level-shifters.

=MCP_HDMI_DDC_DATA =MCP_HDMI_HPD

DP_IG_DDC_CLK

TV / Component

Okay to float all TV_DAC signals.

avoids a leakage issue since

103 mA

206 mA (A01)

RGB ONLY

C / Pr

8 mA

16 mA (A01)

DP_IG_HPD

190 mA (A01, 1.8V)

TMDS_IG_TXC_P/N

GPIO 57-59 ( IF LCD PANEL IS USED):

WF: IFP is capable of LVDS (1.8V) or TMDS (3.3V), need aliases

DP_IG_AUX_CH_P/N

=MCP_HDMI_TXD_P/N<2>

DP_IG_ML_P/N<0>

DP_IG_ML_P/N<1>

DP_IG_ML_P/N<2>

DP_IG_ML_P/N<3>

=MCP_HDMI_TXD_P/N<1>

=MCP_HDMI_TXD_P/N<0>

=MCP_HDMI_TXC_P/N

MCP Signal

DisplayPort

5 mA (A01)

TMDS/HDMI

DP_IG_AUX_CH_P/N

DP_IG_DDC_DATA

be used to provide HDMI or dual-channel TMDS without

NOTE: HDMI port requires level-shifting. IFP interface can

NOTE: 20K pull-down required on DP_HOTPLUG_DET.

NOTE: 1M pull-down required on DP_IG_CA_DET if DP not used.

TP_DP_IG_AUX_CHP/N

TMDS_IG_HPD

TMDS_IG_DDC_DATA

TMDS_IG_DDC_CLK

TMDS_IG_TXD_P/N<2>

TMDS_IG_TXD_P/N<1>

TMDS_IG_TXD_P/N<0>

Interface Mode

24

73 32

73 33

32

73 32

66

67

9

67

71 25

71 68

49.9

1/16W

402

1%

MF-LF

R1810

1

2

49.9

1%

402

1/16W MF-LF

R1811

1

2

67

26

9

BGA

MCP79-TOPO-B

(6 OF 11)

OMIT

U1400

E23

B31

C30

D31

A31

B30

E31

C43

D43

E16

B15

J31

E35

D35

F35

G35

G33

F33

H33

J33

J30

C31 F31

C35

B35

A32

B32

C32

D32

C33

D33

C34

B34

E32

G31

K31

L31

H29

J29

K29

L29

K30

L30

M30

N30

G39

E37 F40

B26

B27

C27

B22

J23

F23

E28

J24

K24

T23

U23

V23

M29

M28

J32

K32

T25

M27 M26

B40

A39

A40

B39

C39

B38

A41

J22

D21

C21

G23

A23

C22

C23

B23

E24 A24

D24 C26

B24

C24 C25

D25

C36

B36

D36

A36

E36 A35

C37

C38

D38

1/16W MF-LF

5%

402

10K

R1850

1

2

43

7

47K

5%

1/16W

402

MF-LF

R1820

1

2

1/16W

402

MF-LF

5%

100K

R1861

12

73 32

100K

5%

MF-LF

402

1/16W

R1860

12

71

9

71

9

71 66

7

71 66

7

71 66

7

73 32

71 66

7

71 66

7

71 66

7

71

9

71

9

71

9

71

9

71

9

71

9

71

9

73 32

71

9

71

9

71

9

71

9

71

9

66

7

66

7

67

71 25

73 32

71 25

73 32

051-8089

SYNC_DATE=08/17/2008

MCP Ethernet & Graphics

02

18

109

SYNC_MASTER=K36B_MLB

ENET_TXD<3>

ENET_TXD<2>

ENET_CLK125M_RXCLK

NO_TEST=TRUE

NC_MCP_RGB_VSYNC

NC_MCP_RGB_BLUE

NO_TEST=TRUE

NC_MCP_RGB_RED

NO_TEST=TRUE

ENET_TXD<0>

=PP3V3_S5_MCP_GPIO

LPCPLUS_GPIO DP_IG_CA_DET

MCP_CLK27M_XTALIN MCP_CLK27M_XTALOUT

MCP_HDMI_TXD_P<1>

ENET_RXD<1>

LVDS_IG_PANEL_PWR

MCP_HDMI_TXC_P MCP_HDMI_TXC_N

MCP_HDMI_TXD_P<0>

MCP_HDMI_TXD_N<1>

TP_DP_IG_AUX_CHN

TP_DP_IG_AUX_CHP

MCP_HDMI_TXD_N<2>

MCP_HDMI_TXD_P<2>

=PP3V3_ENET_MCP_RMGT

CRT_IG_B_COMP_PB

CRT_IG_G_Y_Y

CRT_IG_R_C_PR

CRT_IG_VSYNC

LVDS_IG_A_CLK_P LVDS_IG_A_CLK_N

DP_HOTPLUG_DET MCP_HDMI_HPD

=PP3V3R1V8_S0_MCP_IFP_VDD

=PP1V05_S0_MCP_HDMI_VDD

PP3V3_S0_MCP_VPLL

=MCP_HDMI_DDC_DATA

LVDS_IG_B_DATA_N<0>

LVDS_IG_DDC_DATA

=MCP_HDMI_DDC_CLK

LVDS_IG_DDC_CLK

LVDS_IG_B_DATA_N<3>

MCP_IFPAB_RSET

CRT_IG_HSYNC

LVDS_IG_A_DATA_P<1> LVDS_IG_A_DATA_N<1>

=PP3V3_S0_MCP_GPIO

LVDS_IG_A_DATA_N<3>

=PP3V3_ENET_MCP_RMGT

MCP_MII_VREF

ENET_RXD<0>

MCP_IFPAB_VPROBE

LVDS_IG_B_DATA_P<3>

LVDS_IG_B_DATA_N<2>

LVDS_IG_B_DATA_N<1> LVDS_IG_B_DATA_P<2>

LVDS_IG_B_DATA_P<0>

LVDS_IG_B_DATA_P<1>

LVDS_IG_B_CLK_N

LVDS_IG_B_CLK_P

LVDS_IG_A_DATA_N<2> LVDS_IG_A_DATA_P<3>

LVDS_IG_A_DATA_P<2>

LVDS_IG_A_DATA_N<0>

LVDS_IG_A_DATA_P<0>

MCP_HDMI_VPROBE

MCP_HDMI_RSET

MCP_HDMI_TXD_N<0>

LVDS_IG_BKL_PWM LVDS_IG_BKL_ON

=PP1V05_ENET_MCP_RMGT

PP1V05_ENET_MCP_PLL_MAC

MCP_TV_DAC_VREF

MCP_TV_DAC_RSET

TP_ENET_INTR_L

MCP_MII_COL

MCP_MII_RXER

ENET_RXD<2> ENET_RXD<3>

ENET_RX_CTRL

MCP_MII_CRS

TP_MCP_RGB_DAC_VREF

PP3V3_S0_MCP_DAC

ENET_RESET_L

MCP_CLK25M_BUF0_R

ENET_TX_CTRL

ENET_CLK125M_TXCLK

ENET_TXD<1>

TP_ENET_PWRDWN_L

ENET_MDIO

ENET_MDC

MCP_DDC_DATA0

MCP_DDC_CLK0

MCP_MII_COMP_GND

MCP_MII_COMP_VDD

NO_TEST=TRUE

NC_MCP_RGB_DAC_RSET

NC_MCP_RGB_GREEN

NO_TEST=TRUE

NC_MCP_RGB_HSYNC

8

20

8

18 24

8

25

8

25

8

19 21

8

18 24

8

24

25

73

OUT

BI BI BI BI

LPC PCIGND

PCI_INTW# PCI_INTX# PCI_INTY# PCI_INTZ#

GND65

LPC_DRQ1#/GPIO_19

LPC_PWRDWN#/GPIO_54/EXT_NMI#

PCI_TRDY#

LPC_DRQ0# LPC_SERIRQ

PCI_AD4

PCI_AD0

PCI_AD3

PCI_AD2

PCI_AD1

PCI_AD5 PCI_AD6

PCI_AD9

PCI_AD8

PCI_AD7

PCI_AD10 PCI_AD11

PCI_AD14

PCI_AD13

PCI_AD12

PCI_AD15 PCI_AD16 PCI_AD17

PCI_AD20

PCI_AD19

PCI_AD18

PCI_AD21 PCI_AD22

PCI_AD25

PCI_AD23

PCI_AD26

PCI_AD29

PCI_AD31

GND66 GND67

GND69

GND68

GND70 GND71 GND72

GND74

GND73

GND75 GND76 GND77

GND79

GND78

GND80 GND81

GND84

GND83

GND82

GND85 GND86 GND87

GND89

GND88

GND90 GND91 GND92

GND94

GND93

GND95 GND96 GND97

PCI_GNT0#

PCI_CBE2#

PCI_CBE0#

PCI_CBE3#

PCI_IRDY#

PCI_FRAME#

PCI_DEVSEL#

PCI_PAR

PCI_SERR# PCI_STOP#

PCI_RESET0# PCI_RESET1#

PCI_CLK2

PCI_CLK1

PCI_CLK0

PCI_CLKIN

LPC_FRAME#

LPC_AD1

LPC_AD0

LPC_RESET0#

LPC_CLK0

LPC_AD3

LPC_AD2

GND99

GND98

GND100

GND102

GND101

GND104

GND103

GND105 GND106 GND107

GND109

GND108

GND110 GND111 GND112

GND115

GND114

GND113

GND116 GND117

GND120

GND119

GND118

GND121 GND122 GND123

GND125

GND124

GND126 GND127 GND128

GND130

GND129

PCI_AD30

PCI_AD27

PCI_AD24

PCI_CLKRUN#/GPIO_42

PCI_AD28

PCI_GNT2#/GPIO_41/RS232_DTR# PCI_GNT3#/GPIO_39/RS232_RTS#

PCI_GNT4#/GPIO_53/RS232_SOUT#

PCI_GNT1#/FANCTL2

PCI_CBE1#

PCI_PERR#/GPIO_43/RS232_DCD#

PCI_REQ3#/GPIO_38/RS232_CTS# PCI_REQ4#/GPIO_52/RS232_SIN#

PCI_PME#/GPIO_30

PCI_REQ2#/GPIO_40/RS232_DSR#

PCI_REQ0# PCI_REQ1#/FANRPM2

IN

BI

OUT

IN

OUT

BI BI BI BI BI BI BI BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Strap for Boot ROM Selection (See HDA_SDOUT)

Int PU Int PU

Int PU (S5)

Int PU

72 43 41

7

72 26

72 43 41

7

72 43 41

7

72 43 41

7

72 43 41

7

OMIT

MCP79-TOPO-B

BGA

(7 OF 11)

U1400

AB18 H34

AB20 AB21

AB23

AB24 AB25

AB26

AB27 AB28

AB34

AB37 AB4

AB40 AC22

AC36

AC40 AB33

AC5

AD16 AD17

AD18

AD19 AD20

AD24 AD25

AD26

AD27 AD28

AD33

AD34

U24

U26

U39

U4

U8 V16

V17

V18 V20

V22

V24 V26

V27

V28 V33

V37

V4

V40

V7 W20

W22

W24 W36

W40

W43 Y16

Y17 Y18

Y19

Y20 Y22

Y24

Y25

Y26

Y27

AD3 AD2

AD1 AD5

AE9

AE1

AE2

AD4 AE12

AE5

AE6

AC3

AE10

AC9

AC10 AC11

AA1

AA5

Y5

W3

W6

W4

W7

AC4

V3

W8

V2

W9

U3

W11

U2

U5

U1

U6

AE11

T5

U7

AB3

AC6

AB2 AC7

AC8 AA2

AA3 AA6

AA11

W10

R6 R7

R8

R9

AD11

AA9

Y4

R3

U10 R4

U11 P3

P2

N3

N2

N1

AA10

Y1 AB9

T1

T2

V9

T3

U9

T4

R10

R11

AA7

Y2

Y3

43 41

7

43 41

7

72 26

43 41

7

22

5% 1/16W

402

MF-LF

PLACEMENT_NOTE=Place close to pin R8

R1910

1

2

402

5%

MF-LF1/16W

8.2K

R1989

1 2

402

MF-LF1/16W

5%

8.2K

R1991

1 2

5%

1/16W MF-LF

402

8.2K

R1990

1 2

8.2K

5%

MF-LF

402

1/16W

R1994

1 2

402

MF-LF1/16W

5%

8.2K

R1992

1 2

19

9

402

MF-LF

1/16W

5%

10K

R1961

1

2

22

5%

402

MF-LF1/16W

R1960

1 2

0

5%

1/16W MF-LF

402

R1950

1 2

0

1/16W5%MF-LF

402

R1951

1 2

0

5%

1/16W MF-LF

402

R1952

1 2

0

402

MF-LF1/16W

5%

R1953

1 2

26

35

19

9

19

13

7

72 13

7

72 13

7

72 13

7

72 13

7

72 13

7

72 13

7

72 13

7

72 13

7

109

19

SYNC_DATE=08/17/2008SYNC_MASTER=K36B_MLB

02

MCP PCI & LPC

051-8089

LPC_PWRDWN_L

LPC_RESET_L

LPC_AD_R<0>

LPC_FRAME_R_L

LPC_CLK33M_SMC_R

LPC_AD<3>

LPC_AD<2>

LPC_AD<1>

LPC_AD<0>

GMUX_JTAG_TDI

TP_PCI_C_BE_L<2> TP_PCI_C_BE_L<3>

TP_PCI_FRAME_L TP_PCI_IRDY_L TP_PCI_PAR TP_PCI_PERR_L TP_PCI_SERR_L TP_PCI_STOP_L

TP_PCI_RESET1_L

FW_PME_L

TP_PCI_AD<16>

TP_PCI_AD<15>

TP_PCI_AD<13>

TP_PCI_AD<12>

TP_PCI_AD<10>

TP_PCI_DEVSEL_L

TP_PCI_CLK1

TP_PCI_CLK0

MEM_VTT_EN_R

PM_LATRIGGER_L

PCI_REQ0_L

TP_PCI_C_BE_L<1>

TP_PCI_AD<11>

TP_PCI_AD<19>

GMUX_JTAG_TMS

PCI_REQ0_L PCI_REQ1_L CRTMUX_SEL_TV_L

MCP_RS232_SIN_L

MCP_DEBUG<1>

MCP_DEBUG<4>

TP_PCI_INTW_L

TP_PCI_AD<17> TP_PCI_AD<18>

PCI_REQ1_L

MCP_RS232_SIN_L

MCP_RS232_SOUT_L

PCI_CLK33M_MCP

LPC_AD_R<1> LPC_AD_R<2> LPC_AD_R<3>

TP_PCI_AD<14>

TP_PCI_AD<22> TP_PCI_AD<23>

TP_PCI_AD<27>

TP_PCI_AD<29> TP_PCI_AD<30> TP_PCI_AD<31>

PCI_CLK33M_MCP_R

TP_PCI_AD<20> TP_PCI_AD<21>

TP_PCI_AD<28>

LPC_SERIRQ

TP_LPC_DRQ0_L

TP_PCI_TRDY_L

TP_PCI_INTZ_L

TP_PCI_INTX_L TP_PCI_INTY_L

PM_CLKRUN_L

TP_PCI_AD<26>

TP_PCI_AD<25>

TP_PCI_AD<24>

AUD_IPHS_SWITCH_EN

TP_PCI_C_BE_L<0>

MCP_RS232_SOUT_L

TP_PCI_GNT1_L

TP_PCI_GNT0_L

MCP_DEBUG<0>

MCP_DEBUG<3>

MCP_DEBUG<5> MCP_DEBUG<6> MCP_DEBUG<7> TP_PCI_AD<8> TP_PCI_AD<9>

MCP_DEBUG<2>

CRTMUX_SEL_TV_L

=PP3V3_S0_MCP_GPIO

LPC_FRAME_L

19 72

19

72

19

8

18 21

BI BI

IN IN IN IN

SATA_B0_RX_N

SATA_A0_RX_P

SATA_A1_TX_P

GND160

GND158 GND159

GND157

GND156

GND155

GND153 GND154

GND152

GND151

GND150

GND148 GND149

GND147

GND146

GND145

GND143 GND144

GND142

GND141

GND140

GND139

GND136

GND133 GND134

GND132

GND131

USB_RBIAS_GND

USB11_N

USB11_P

USB10_N

USB10_P

USB9_N

USB9_P

USB7_N

USB8_N

USB8_P

USB7_P

USB6_N

USB6_P

USB5_N

USB4_N

USB4_P

USB5_P

USB2_N

USB2_P

USB0_N

USB1_N

USB1_P

USB0_P

SATA_TERMP

SATA_LED#

SATA_C1_RX_N SATA_C1_RX_P

SATA_C0_TX_P

SATA_B1_RX_N SATA_B1_RX_P

SATA_B1_TX_N

SATA_B1_TX_P

SATA_B0_TX_N

SATA_B0_RX_P

SATA_B0_TX_P

SATA_A1_RX_N SATA_A1_RX_P

SATA_A1_TX_N

SATA_A0_TX_P

GND138

GND137

GND135

USB3_P USB3_N

USB_OC0#/GPIO_25

USB_OC1#/GPIO_26 USB_OC2#/GPIO_27/MGPIO USB_OC3#/GPIO_28/MGPIO

SATA_A0_RX_N

SATA_A0_TX_N

SATA_C1_TX_N

SATA_C1_TX_P

SATA_C0_RX_P

SATA_C0_RX_N

SATA_C0_TX_N

+V_PLL_USB

+V_PLL_SATA

+DVDD0_SATA1 +DVDD0_SATA2 +DVDD0_SATA3 +DVDD0_SATA4

+DVDD1_SATA2

+AVDD0_SATA1 +AVDD0_SATA2 +AVDD0_SATA3 +AVDD0_SATA4 +AVDD0_SATA5 +AVDD0_SATA6 +AVDD0_SATA7 +AVDD0_SATA8 +AVDD0_SATA9

+AVDD1_SATA1 +AVDD1_SATA2 +AVDD1_SATA3 +AVDD1_SATA4

+DVDD1_SATA1

SATA

USB

OUT OUT

IN

OUT OUT

IN IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

127 mA (A01)

External C

ExpressCard

Bluetooth

IR

Camera

External D

AirPort (PCIe Mini-Card)

External A

External B

19 mA (A01)

84 mA (A01)

43 mA (A01)

Geyser Trackpad/Keyboard

72 39

72

9

72

9

72

9

72

9

72 66

72 40

72

9

72

9

72

9

72

9

72 39

72

9

72

9

72

9

72

9

39

42

2.49K

MF-LF

1% 1/16W

402

R2010

1

2

1/16W

402

1%

MF-LF

806

R2060

1

2

8.2K

402

1/16W

5%

MF-LF

R2053

1

2

8.2K

5% 1/16W MF-LF

402

R2052

1

2

1/16W MF-LF

5%

8.2K

402

R2051

1

2

OMIT

(8 OF 11)

BGA

MCP79-TOPO-B

U1400

AD35

AD37 AD38

AE22

AE24 AE39

AE4

AD6 AF16

AF17 AF18

AF20

AF22 AF26

AF27

AF28 AF33

AF34

AF37 AF40

AG18 AG20

AG22

AG26 AG36

AG40

AH18 AH20

AH22

AH24

AJ12

AN11 AK12

AK13

AL12 AM11

AM12 AN12

AL13

AN14

AL14

AM13 AM14

AF19 AG16

AG17

AG19

AH17 AH19

AE16

L28

AJ5

AJ4

AJ6

AJ7

AJ9 AK9

AJ10

AJ11

AJ2 AJ1

AJ3

AK2

AL4 AK3

AL3

AM4

AM2 AM3

AM1

AN1

AN3

AN2

AP2

AP3

E12

AE3

D29

C29

G25

F25

L23

K23

D28

C28

B28

A28

G29

F29

L27

K27

J27

J26

G27

F27

E27

D27

L25

K25

J25

H25

L21

K21 J21

H21

A27

71 38

8.2K

1/16W MF-LF

402

5%

R2050

1

2

051-8089

MCP SATA & USB

SYNC_MASTER=K36B_MLB SYNC_DATE=08/17/2008

109

20

02

SATA_ODD_D2R_P

TP_SATA_F_R2D_CP TP_SATA_F_R2D_CN

TP_SATA_F_D2RN

TP_MCP_SATALED_L

TP_SATA_F_D2RP

USB_EXTC_OC_L

=PP1V05_S0_MCP_SATA_DVDD1

PP3V3_S0_MCP_PLL_USB

PP1V05_S0_MCP_PLL_SATA

=PP1V05_S0_MCP_SATA_DVDD0

SATA_ODD_D2R_N

USB_EXCARD_P

USB_TPAD_P

MCP_SATA_TERMP

MCP_USB_RBIAS_GND

USB_EXTD_P

USB_IR_P USB_IR_N

USB_EXTA_P USB_EXTA_N

SATA_ODD_R2D_C_P

SATA_HDD_D2R_P

SATA_HDD_D2R_N

SATA_ODD_R2D_C_N

USB_EXTD_N

SATA_HDD_R2D_C_P

USB_CAMERA_N

USB_CAMERA_P

USB_MINI_N

USB_MINI_P

TP_SATA_E_R2D_CP

SATA_HDD_R2D_C_N

TP_SATA_E_D2RN

TP_SATA_E_R2D_CN

TP_USB_11N

TP_SATA_D_D2RP

TP_SATA_D_D2RN

TP_SATA_D_R2D_CN

TP_SATA_D_R2D_CP

TP_SATA_C_D2RP

TP_SATA_C_D2RN

TP_SATA_C_R2D_CN

TP_SATA_C_R2D_CP

USB_TPAD_N

USB_EXCARD_N

USB_EXTB_P

USB_BT_P USB_BT_N

USB_EXTB_N

USB_EXTC_P

TP_USB_10N

TP_USB_10P

USB_EXTC_N

=PP1V05_S0_MCP_SATA_AVDD1

=PP1V05_S0_MCP_SATA_AVDD0

TP_SATA_E_D2RP

=PP3V3_S5_MCP_GPIO

TP_USB_11P

USB_EXTA_OC_L USB_EXTB_OC_L

EXCARD_OC_L

8

24

8

71

72

8

18

OUT

BI

OUT

OUT OUT

OUT

IN

OUT

IN

OUT

IN IN

OUT

IN

OUT

HDA_SDATA_IN2_GPIO_3/PS2_KB_DATA

SLP_S3*

HDA_DOCK_EN*_GPIO_4/PS2_MS_CLK

SLP_RMGT*

HDA_BITCLK

HDA_SDATA_OUT

THERM_DIODE_N

THERM_DIODE_P

HDA_RESET*

HDA_PULLDN_COMP

HDA_SDATA_IN1_GPIO_2/PS2_KB_CLK

MCP_VID2/GPIO_15

MCP_VID1/GPIO_14

MCP_VID0/GPIO_13

EXT_SMI/GPIO_32*

FANCTL1/GPIO_62

FANRPM1/GPIO_63

FANCTL0/GPIO_61

FANRPM0/GPIO_60

SIO_PME*

KBRDRSTIN*

PKG_TEST

TEST_MODE_EN

BUF_SIO_CLK

CPUVDD_EN

SMB_DATA0

SMB_CLK0

SPKR

HDA_SYNC

XTALIN_RTC

XTALOUT

XTALOUT_RTC

JTAG_TRST*

XTALIN

JTAG_TCK

JTAG_TMS

CPU_VLD

JTAG_TDI JTAG_TDO

RTC_RST*

PS_PWRGD

PWRGD_SB

INTRUDER*

LID* LLB*

PWRBTN* RSTBTN*

CPU_DPRSLPVR

SLP_S5*

HDA_SDATA_IN0

SMB_CLK1/MSMB_CLK

SMB_DATA1/MSMB_DATA

SMB_ALERT*/GPIO_64

SPI_CS0/GPIO_10 SPI_CLK/GPIO_11

SPI_DI/GPIO_8 SPI_DO/GPIO_9

SUS_CLK/GPIO_34

+V_DUAL_HDA1 +V_DUAL_HDA2

HDA_DOCK_RST*_GPIO_5/PS2_MS_DATA

GPIO_1/PWRDN_OK/SPI_CS1

A20GATE

GPIO_12_SUS_STAT_ACCLMTR_EXT_TRIG_L

+V_PLL_SP_SPREF

+V_PLL_NV_H

MISC

HDA

OUT

IN

OUT

IN

OUT

IN

IN IN

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Int PU (S5)

Int PU

37 mA (A01)

17 mA

PCI

not use LPC for BootROM override.

LPC_FRAME# high for SPI1 ROM override.

SPI0 = SPI_CS0_L, SPI1 = SPI_CS1_L

Int PU

25 MHz

42 MHz 0

SPI1 option.

NOTE: MCP79 rev A01 does not support

LPC ROMs. So Apple designs will

0

1

HDA_SYNC

24 MHz

0

1

0

SPI_CLKSPI_DO

0

1

14.31818 MHz

BUF_SIO_CLK Frequency

Frequency

31 MHz

NOTE: Straps not provided on this page.

1 MHz

SPI Frequency Select

Frequency

NOTE: MCP79 does not support FWH, only

LPC

SPI0

SPI1

BIOS Boot Select

R1961 and R2160 selects SPI0 ROM by default, LPC+ debug card pulls

1

0

1

0

1

Int PU

Int PD

20 mA

Int PU (S5)

Int PU

Int PU (S5)

7 mA (A01)

HDA Output Caps

For EMI Reduction on HDA interface

Int PU (S5)

Int PD

I/F

HDA_SDOUT

LPC_FRAME#

72 43

64 41 36 33

64 42 41

72 44 13

7

72 44

72 44 13

7

72 44

61 21

47

21

61 21

33 31 21

47

9

69 60

41

72 52

MF-LF

1/16W

402

49.9K

1%

R2121

1

2

402

MF-LF

49.9K

1%

1/16W

R2120

1

2

402

MF-LF

1/16W

1K

1%

R2190

1

2

72 26

41

22

5%

402

1/16W MF-LF

R2170

1 2

22

402

1/16W

5%

MF-LF

R2171

1 2

1/16W MF-LF

5%

402

22

R2173

1 2

1/16W

5%

402

10K

MF-LF

R2163

1

2

402

MF-LF

8.2K

1/16W

5%

R2160

1

2

5%

10K

MF-LF

BOOT_MODE_SAFE

402

1/16W

R2180

1

2

1/16W

BOOT_MODE_USER

MF-LF 402

10K

5%

R2181

1

2

MF-LF

1/16W

22

5%

402

R2172

1 2

43

402

1%

MF-LF

1/16W

49.9

R2110

1

2

MF-LF

402

5%

1/16W

10K

R2150

1

2

13

7 6

13

7 6

13

7 6

13

7 6

6

CERM 402

5% 50V

10PF

C2171

1

2

CERM 402

5%

10PF

50V

C2173

1

2

CERM

402

5%

10PF

50V

C2170

1

2

CERM

402

5%

10PF

50V

C2172

1

2

OMIT

MCP79-TOPO-B

(9 OF 11)

BGA

U1400

K13

AE7

M22

C17 D17

C18

A12

C12

B12

D12

L26

L24

E15

K17

L17

A15

K15

G15

J14

J15

F15

L15

B20

G19

E19 F19

J19

J18

L13

M25

M24

L20

M20

M21

J16

K16

AE18

AE17

L22

E20

C16

D20

D16

C20

C19

J17

G17

H17

M23

L19

G21

K19

F21

D13

C14

C15

B14

C13

B18

K22

C11

B11

A16

A19

B16

B19

38

21

26 26

42 41 36 33

41 29 28 21

100K

5%

MF-LF

1/16W

402

R2147

1

2

100K

MF-LF

1/16W

402

5%

R2146

1

2

MF-LF

1/16W

10K

5%

402

R2142

1

2

402

MF-LF

1/16W

5%

10K

R2141

1

2

10K

402

1/16W MF-LF

5%

R2140

1

2

MF-LF 402

1/16W

5%

22K

R2157

1

2

402

1/16W MF-LF

5%

22K

R2156

1

2

402

1/16W MF-LF

5%

22K

R2155

1

2

402

5%

MF-LF

1/16W

100K

R2122

1

2

5%

1/16W

10K

402

MF-LF

R2159

1

2

10K

402

1/16W MF-LF

5%

R2143

1

2

26

41

26

43

72 43

SYNC_DATE=08/17/2008SYNC_MASTER=K36B_MLB

21

109

02

MCP HDA & MISC

051-8089

HDA_SDOUT

HDA_SYNC_R

TP_MCP_BUF_SIO_CLK

AUD_I2C_INT_L

HDA_RST_R_L

SPI_CS0_R_L

ARB_DETECT

SMC_IG_THROTTLE_L

ODD_PWR_EN_L

MEM_EVENT_L

MCP_CPUVDD_EN

SMBUS_MCP_1_DATA

SPI_CLK_R

HDA_BIT_CLK_R

MCP_CLK25M_XTALIN

JTAG_MCP_TCK

SM_INTRUDER_L

PM_DPRSLPVR

SMC_ADAPTER_EN

TP_MCP_KBDRSTIN_L

TP_SB_A20GATE

SMC_WAKE_SCI_L

TP_MCP_LID_L PM_BATLOW_L

PM_PWRBTN_L

MCP_HDA_PULLDN_COMP

SMC_RUNTIME_SCI_L

PP1V05_S0_MCP_PLL_NV

=PP3V3_S0_MCP

HDA_SYNC

HDA_RST_L

HDA_BIT_CLK

PP3V3_G3_RTC

=PP3V3R1V5_S0_MCP_HDA

MCP_VID<2>

MCP_VID<1>

MCP_VID<0>

TP_MLB_RAM_SIZE

TP_MLB_RAM_VENDOR

PM_SYSRST_DEBOUNCE_L

HDA_SDIN0

HDA_SYNC_R

HDA_SDOUT_R

HDA_RST_R_L

PM_CLK32K_SUSCLK_R

SPI_MOSI_R

SPI_MISO

PM_SLP_S4_L

HDA_SDOUT_R

=PP3V3R1V5_S0_MCP_HDA

MCP_TEST_MODE_EN

MCP_CLK25M_XTALOUT

RTC_CLK32K_XTALIN

HDA_BIT_CLK_R

JTAG_MCP_TRST_L

=PP3V3_S3_FET

RTC_CLK32K_XTALOUT

PM_RSMRST_L

JTAG_MCP_TDI

JTAG_MCP_TMS

JTAG_MCP_TDO

MCP_CPU_VLD

MCP_PS_PWRGD

RTC_RST_L

AP_PWR_EN

MEM_EVENT_L

AP_PWR_EN

SMBUS_MCP_1_CLK

SMBUS_MCP_0_DATA

SMBUS_MCP_0_CLK

MCP_SPKR

MCP_VID<2>

MCP_VID<1>

MCP_VID<0>

MCP_THMDIODE_N

MCP_THMDIODE_P

PM_SLP_S3_L

MCP_GPIO_4 AUD_I2C_INT_L

SMC_IG_THROTTLE_L

ARB_DETECT

MCP_GPIO_4

=PP3V3_S0_MCP_GPIO

PM_SLP_RMGT_L

=SPI_CS1_R_L_USE_MLB

21 72

21

21 72

21

21 42

21 72

72

24

8

22 24

22 26

8

21 24

21 61

21 72

8

21 24

21 72

8

65

21 31 33

21 28 29 41

9

21 42

21

8

18 19

GND

GND161

GND165 GND166

GND164

GND163

GND162

GND167 GND168

GND171

GND170

GND169

GND172 GND173

GND176

GND175

GND174

GND177 GND178

GND181

GND180

GND179

GND182 GND183 GND184

GND187

GND186

GND185

GND188 GND189

GND192

GND191

GND190

GND193 GND194

GND197

GND196

GND195

GND198

GND202

GND201

GND200

GND199

GND203

GND206 GND207

GND205

GND204

GND208

GND212

GND211

GND210

GND209

GND213 GND214

GND217

GND216

GND215

GND218 GND219

GND222

GND221

GND220

GND223 GND224 GND225

GND228

GND227

GND226

GND229 GND230

GND233

GND232

GND231

GND234 GND235

GND238

GND237

GND236

GND239 GND240

GND243

GND242

GND241

GND244

GND248

GND247

GND246

GND245

GND249

GND252

GND251

GND250 GND342

GND341

GND343

GND340

GND339

GND338

GND337

GND336

GND335

GND334

GND333

GND331 GND332

GND330

GND329

GND328

GND326 GND327

GND325

GND324

GND323

GND321 GND322

GND320

GND319

GND318

GND316 GND317

GND315

GND314

GND313

GND311

GND310

GND312

GND309

GND308

GND305 GND306 GND307

GND304

GND303

GND301

GND300

GND302

GND299

GND298

GND296

GND295

GND297

GND294

GND293

GND292

GND291

GND290

GND289

GND288

GND287

GND285 GND286

GND284

GND283

GND282

GND280 GND281

GND279

GND278

GND277

GND275 GND276

GND274

GND273

GND272

GND270

GND269

GND271

GND268

GND267

GND264 GND265 GND266

GND263

GND262

GND259 GND260 GND261

GND258

GND257

GND255

GND254

GND256

GND253

+VTT_CPUCLK

+VDD_CORE42

+3.3V_DUAL_USB2

+VTT_CPU17

+VTT_CPU16

+VTT_CPU15

+VTT_CPU14

+VTT_CPU13

+VTT_CPU12

+VTT_CPU11

+VTT_CPU10

+VTT_CPU1

+VDD_CORE7

+VDD_CORE1 +VDD_CORE2 +VDD_CORE3 +VDD_CORE4 +VDD_CORE5 +VDD_CORE6

+VDD_CORE13 +VDD_CORE14 +VDD_CORE15 +VDD_CORE16 +VDD_CORE17 +VDD_CORE18 +VDD_CORE19

+VDD_CORE21 +VDD_CORE22 +VDD_CORE23 +VDD_CORE24 +VDD_CORE25 +VDD_CORE26 +VDD_CORE27 +VDD_CORE28 +VDD_CORE29 +VDD_CORE30

+VDD_CORE32 +VDD_CORE33 +VDD_CORE34 +VDD_CORE35 +VDD_CORE36 +VDD_CORE37

+VDD_CORE39 +VDD_CORE40 +VDD_CORE41

+VDD_CORE47 +VDD_CORE48 +VDD_CORE49 +VDD_CORE50 +VDD_CORE51 +VDD_CORE52 +VDD_CORE53 +VDD_CORE54

+VTT_CPU51

+VTT_CPU50

+VTT_CPU47

+VTT_CPU46

+VTT_CPU45

+VTT_CPU43

+VTT_CPU42

+VTT_CPU41

+VTT_CPU40

+VTT_CPU39

+VTT_CPU38

+VTT_CPU37

+VTT_CPU36

+VTT_CPU35

+VTT_CPU34

+VTT_CPU32

+VTT_CPU31

+VTT_CPU30

+VTT_CPU29

+VTT_CPU28

+VTT_CPU26

+VTT_CPU25

+VTT_CPU24

+VTT_CPU23

+VTT_CPU22

+VTT_CPU21

+VTT_CPU20

+VTT_CPU19

+VTT_CPU18

+VTT_CPU9

+VTT_CPU8

+VTT_CPU7

+VTT_CPU6

+VTT_CPU5

+VTT_CPU4

+VTT_CPU3

+VDD_CORE38

+VTT_CPU33

+VTT_CPU27

+VDD_CORE55 +VDD_CORE56 +VDD_CORE57 +VDD_CORE58 +VDD_CORE59 +VDD_CORE60 +VDD_CORE61 +VDD_CORE62 +VDD_CORE63 +VDD_CORE64 +VDD_CORE65 +VDD_CORE66 +VDD_CORE67 +VDD_CORE68 +VDD_CORE69 +VDD_CORE70 +VDD_CORE71 +VDD_CORE72 +VDD_CORE73 +VDD_CORE74 +VDD_CORE75 +VDD_CORE76 +VDD_CORE77 +VDD_CORE78 +VDD_CORE79 +VDD_CORE80 +VDD_CORE81

+VBAT

+3.3V_1

+3.3V_8

+3.3V_DUAL1 +3.3V_DUAL2 +3.3V_DUAL3 +3.3V_DUAL4

+3.3V_DUAL_USB1

+3.3V_DUAL_USB3 +3.3V_DUAL_USB4

+VDD_AUXC1

+VDD_AUXC3

+VDD_AUXC2

+VDD_CORE43

+VTT_CPU2

+VDD_CORE46

+VDD_CORE45

+VDD_CORE44

+VTT_CPU52

+VDD_CORE31

+VTT_CPU49

+VTT_CPU48

+VTT_CPU44

+3.3V_7

+3.3V_6

+3.3V_5

+3.3V_4

+3.3V_3

+3.3V_2

+VDD_CORE20

+VDD_CORE12

+VDD_CORE11

+VDD_CORE10

+VDD_CORE9

+VDD_CORE8

POWER

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

105 mA (A01)

43 mA

1139 mA

250 mA

16996 mA (A01, 1.0V)

23065 mA (A01, 1.2V)

80 uA (S0)

10 uA (G3)

16 mA

266 mA (A01)

450 mA (A01)

1182 mA (A01)

BGA

MCP79-TOPO-B

(11 OF 11)

OMIT

U1400

AH26 AH33

AH34 AH37

AH38

AJ39

AJ8

AK10

AK33 AK34

AK37

AK4 AK40

AL36 AL40

AL5

AM10 AM16

AM18

AM20 AM22

AM24

AM26 AM30

AM34 AM35

AM37

AM38

AM5

AM6

AM7

AM9

AP26

AN28 AN30

AN39

AN4

Y7

AP10 AU26

AP14

AU14 AP28

AP32

AP34 AP36

AP37

AP4

AP40

AP7 AW23

AR28

AR32 AR40

AT10

AR12 AT13

AT29 AT33

AT6

AT7

AT9

AY21

AY22

L12

AU12

AU28 AP33

AU32 AR30

AU36

AU38

AU4

G28

F20 AV28

AV32

AV36

AV4

AV7 AW11

G20

AR43 AW43

AY10

AV12 AY30

AY33

AY34 AY37

AY38 AY41

AV40 BA1

BA4 AW31

AY6

L35 BC33

BC37

BC41 AY14

BC5

C2 D10

D14 D15

D18

D19 D22

D23

D26 D30

D37

D6 E13

E17 E21

E25

E29 E33

F12

F16 F32

F8

G10 G12

G14 G16

BC12

G22 G24

AW20

G34 G4

G43

G6 G8

H11 H15

AW35

H23 AN8

G40

J12 J8

K10

K12 K18

K26 K37

K4

K40 K8

AU1

L40 L43

L5

M10 M34

M35 M37

Y28

Y33 Y34

Y35

Y37 Y38

AB17

AB16 AN26

AD7 M11

AA4

AB19 AY13

P11

Y6 T11

V11

Y11 AH16

T22

MCP79-TOPO-B

BGA

(10 OF 11)

OMIT

U1400

AD10

AE8 AB10

AD9

Y10 AB11

AA8

Y9

G18

H19

J20 K20

G26 H27

J28

K28

A20

T21

U21

V21

AA25

AA26

AA27

AA28 AC16

AC17 AC18

AC19

AC20 AC21

AA17

AC23

AC24 AC25

AC26

AC27 AC28

AD21 AD23

W27

V25

AA18

U25

AE19

AE21 AE23

AE25

AE26 AE27

AE28 AF10

AF11

AA19

AH12

AF2

AF21

AF23 AF25

AF3

AF4 AF7

AH23

AF9

AA20

AG10

AG11 AG12

AG21

AG23 AG25

AG3

AG4

AA21

AG6 AG7

AG5

AG8

AG9 AH1

AH10

AH11

W26

AH2

AA23

W28

AH25

Y21

AH21

AH3

AH4 AH5

AH6

AH7 AH9

AA24

W21 W23

Y23

W25

AF12

AA16

R32

P31

AF32

AE32 AH32

AJ32 AK31

AK32

AD32 AL31

AB32

AC32

B41 B42

C40

C41 C42

D39 D40

D41

E38 E39

E40

F37

F38 F39

G36

G37 G38

H35 H37

J34

J35

J36

K33

K34

K35 L32

L33

L34 M31

M32 M33

N31

N32

P32 Y32

AA32

T32 U32

V32

W32

AG32

051-8089

MCP Power & Ground

SYNC_MASTER=K36B_MLB SYNC_DATE=08/17/2008

109

02

22

=PP3V3_S5_MCP

=PP1V05_S5_MCP_VDD_AUXC

=PP3V3_S0_MCP

PP3V3_G3_RTC

=PP1V05_S0_MCP_FSB

=PPVCORE_S0_MCP

8

24

8

24

8

21 24

21 26

8

14 24

8

24 46 61

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

24

MCP79 A01 Silicon Support

SYNC_MASTER=K36B_MLB

051-8089

109

02

SYNC_DATE=08/17/2008

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

5 mA (A01)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) Apple: 1x 2.2uF 0402 (2.2 uF)

Apple: 1x 2.2uF 0402 (2.2 uF)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)

131 mA (A01)

23065 mA (A01, 1.2V) 16996 mA (A01, 1.0V)

MCP Core Power

(No IG vs. EG data)

MCP PCIE (DVDD) Power

4771 MA (A01, DDR2)

MCP 1.05V AUX Power

MCP Memory Power

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

19 mA (A01)

450 mA (A01)

57 mA (A01) 43 mA (A01)

127 mA (A01)

206 mA (A01)

37 mA (A01)

87 mA (A01)

84 mA (A01)

83 mA (A01)

105 mA (A01)

MCP 1.05V RMGT Power

270 mA (A01)

MCP 3.3V Ethernet Power

Apple: 1x 2.2uF 0402 (2.2 uF)

MCP 3.3V AUX/USB Power

266 mA (A01)

MCP 3.3V/1.5V HDA Power

Apple: 1x 2.2uF 0402 (2.2 uF)

Apple: 5x 2.2uF 0402 (11 uF)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

MCP FSB (VTT) Power

MCP 3.3V Power

333 mA (A01)

19 mA (A01)

7 mA (A01)

Apple: 4x 2.2uF 0402 (8.8 uF)

NV: 1x 4.7uF 0603, 4x 0.1uF 0402 (5.1 uF)

MCP SATA (DVDD) Power

5 mA (A01)

Apple: 7x 2.2uF 0402 (15.4 uF)

1182 mA (A01)

Apple: 4x 4.7uF 0402, 4x 1uF 0402, 6x 0.1uF 0402 (23.4 uF)

NV: 1x 10uF 0805, 2x 4.7uF 0402, 3x 1uF 0402, 9x 0.1uF 0402 (23.3 uF)

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 1uF 0402, 2x 0.1uF 0402 (16.9 uF)

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF) Apple: 2x 2.2uF 0402 (4.4 uF)

562 mA (A01)

MCP79 Ethernet VRef

402

X5R

20%

4.7UF

4V

C2582

1

2

X5R 402

4V

4.7UF

20%

C2588

1

2

402

X5R

4V

20%

4.7UF

C2584

1

2

20%

4.7UF

4V

402

X5R

C2586

1

2

6.3V

20%

402-LF

CERM

2.2UF

C2555

1

2

20% X5R

402

4V

4.7UF

C2502

1

2

402-1

X5R

10%

1UF

10V

C2507

1

2

402-1

X5R

10%

1UF

10V

C2506

1

2

402-1

X5R

10%

1UF

10V

C2505

1

2

402-1

X5R

10%

1UF

10V

C2504

1

2

20% CERM

10V

0.1UF

402

C2511

1

2

20% CERM

10V

0.1UF

402

C2510

1

2

0.1UF

20% 10V CERM 402

C2509

1

2

402

20% CERM

10V

0.1UF

C2508

1

2

20% CERM

10V

0.1UF

402

C2513

1

2

20% CERM

10V

0.1UF

402

C2512

1

2

CERM 402-LF

20%

2.2UF

6.3V

C2536

1

2

2.2UF

20%

6.3V

402-LF

CERM

C2535

1

2

20%

6.3V

2.2UF

CERM 402-LF

C2534

1

2

20%

2.2UF

6.3V CERM 402-LF

C2533

1

2

CERM

20%

2.2UF

6.3V

402-LF

C2532

1

2

CERM

6.3V

2.2UF

20%

402-LF

C2531

1

2

CERM

20%

2.2UF

6.3V

402-LF

C2530

1

2

402-1

10V

1UF

10% X5R

C2517

1

2

402-1

X5R

10%

1UF

10V

C2516

1

2

20%

4V

4.7UF

402

X5R

C2515

1

2

CERM 402-LF

20%

2.2UF

6.3V

C2572

1

2

CERM 402-LF

20%

2.2UF

6.3V

C2571

1

2

20%

4.7UF

4V

402

X5R

C2520

1

2

CERM 402-LF

20%

2.2UF

6.3V

C2570

1

2

CERM 402-LF

20%

2.2UF

6.3V

C2574

1

2

CERM 402-LF

20%

6.3V

2.2UF

C2573

1

2

6.3V

2.2UF

20%

402-LF

CERM

C2576

1

2

CERM 402-LF

20%

2.2UF

6.3V

C2575

1

2

CERM 402-LF

20%

6.3V

2.2UF

C2553

1

2

CERM 402-LF

20%

2.2UF

6.3V

C2552

1

2

402-LF

20%

6.3V

2.2UF

CERM

C2551

1

2

CERM 402-LF

20%

2.2UF

6.3V

C2550

1

2

10V

402

20%

0.1UF

CERM

C2549

1

2

CERM

20% 10V

0.1UF

402

C2548

1

2

CERM

20%

0.1UF

402

10V

C2547

1

2

CERM

20%

0.1UF

402

10V

C2546

1

2

20%

0.1UF

402

10V CERM

C2545

1

2

CERM

20%

0.1UF

10V

402

C2544

1

2

CERM

20%

0.1UF

402

10V

C2543

1

2

CERM

20%

402

0.1UF

10V

C2542

1

2

20%

0.1UF

402

10V CERM

C2541

1

2

402

X5R

4V

4.7UF

20%

C2540

1

2

CERM 402-LF

20%

2.2UF

6.3V

C2562

1

2

6.3V

2.2UF

20%

402-LF

CERM

C2564

1

2

402

4V

20% X5R

4.7UF

C2580

1

2

30-OHM-5A

0603

L2570

1 2

0603

30-OHM-5A

L2575

1 2

0402

30-OHM-1.7A

L2582

1 2

0402

30-OHM-1.7A

L2584

1 2

0402

30-OHM-1.7A

L2588

1 2

0402

30-OHM-1.7A

L2586

1 2

30-OHM-1.7A

0402

L2555

1 2

20% X5R

402

4V

4.7UF

C2500

1

2

20%

4V

4.7UF

X5R 402

C2501

1

2

0402

30-OHM-1.7A

L2580

1 2

20%

402

CERM

10V

0.1uF

C2526

1

2

0.1uF

20%

402

CERM

10V

C2525

1

2

CERM 402-LF

20%

2.2UF

6.3V

C2560

1

2

20% 10V

0.1UF

402

CERM

C2589

1

2

20%

402

CERM

10V

0.1UF

C2590

1

2

402

X5R

4V

4.7UF

20%

C2595

1

2

0402

30-OHM-1.7A

L2595

1 2

1/16W

402

MF-LF

1%

1.47K

R2590

1

2

10V

20%

402

CERM

0.1UF

C2591

1

2

1/16W

1.47K

1%

MF-LF

402

R2591

1

2

18

0.1uF

20%

402

CERM

10V

C2521

1

2

0.1uF

10V

402

20% CERM

C2518

1

2

10V CERM

0.1uF

402

20%

C2519

1

2

402

10V

0.1UF

CERM

20%

C2581

1

2

10V

20%

402

0.1UF

CERM

C2583

1

2

402

10V

0.1UF

CERM

20%

C2585

1

2

402

10V

0.1UF

CERM

20%

C2587

1

2

0.1UF

20% CERM

10V 402

C2596

1

2

20%

402

CERM

10V

0.1uF

C2529

1

2

X5R

4V

4.7uF

402

20%

C2528

1

2

4.7UF

X5R 402

20%

4V

C2503

1

2

25

051-8089

SYNC_MASTER=K36B_MLB

109

02

MCP Standard Decoupling

SYNC_DATE=08/17/2008

=PP1V05_S5_MCP_VDD_AUXC

=PPVCORE_S0_MCP

=PP3V3_S0_MCP

=PP1V8R1V5_S0_MCP_MEM

=PP1V05_S0_MCP_FSB

=PP1V05_ENET_MCP_RMGT

=PP1V05_S0_MCP_SATA_DVDD

=PP3V3_ENET_MCP_RMGT

=PP3V3_S0_MCP_PLL_UF

=PP1V05_S0_MCP_AVDD_UF

=PP3V3_S5_MCP

=PP3V3R1V5_S0_MCP_HDA

=PP1V05_ENET_MCP_PLL_MAC

=PP1V05_S0_MCP_PEX_DVDD

=PP1V05_S0_MCP_PLL_UF

=PP3V3_ENET_MCP_RMGT

MCP_MII_VREF

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

VOLTAGE=1.05V

PP1V05_S0_MCP_PLL_CORE

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

PP3V3_S0_MCP_PLL_USB

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP1V05_S0_MCP_PLL_PEX

PP1V05_S0_MCP_PLL_SATA

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP1V05_S0_MCP_PLL_FSB

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP1V05_S0_MCP_PLL_NV

PP1V05_ENET_MCP_PLL_MAC

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

VOLTAGE=1.05V

PP1V05_S0_MCP_PEX_AVDD

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP1V05_S0_MCP_SATA_AVDD

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

8

22

8

22 46 61

8

21 22

8

16

8

14 22

8

18

8

18 24

8

22

8

21

8

18 24

16

20

17

20

14

21

18

7 8

A2

A1

SCL

A0

VCC

SDA

WP

GND

IN

BI

SCL

SDA

WP

VCC

GND

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

206 mA (A01)

NV: 1x 4.7uF 0603, 2x 0.1uF 0402 (4.9 uF) Apple: 2x 2.2uF 0402 (4.4 uF)

206 mA (A01)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

190 mA (A01, 1.8V)

16 mA (A01)

Apple: ???

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

16 mA (A01)

WF: Open question on which packge option(s) nVidia can support.

95 mA (A01)

WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

Apple: 1x 2.2uF 0402 (2.2 uF)

HDCP ROM

SYNC FROM T18 REMOVE MCP 27MHZ CRYSTAL CRICUIT SINCE NOT SUPPORTING TV-OUT REMOVE DAC TERMINATIONS R2665,C2665 AND R2670 TO R2672

402-LF

CERM

20%

6.3V

2.2UF

C2651

1

2

6.3V CERM 402-LF

20%

2.2UF

C2650

1

2

30-OHM-1.7A

0402

L2650

1 2

10V

CERM

20%

0.1UF

402

NO STUFF

C2620

1

2

1K

NO STUFF

402

1% 1/16W MF-LF

R2630

1

2

402

NO STUFF

20%

CERM

10V

0.1UF

C2630

1

2

X5R 402

4V

4.7UF

20%

C2615

1

2

4.7UF

CERM

603

20%

6.3V

C2640

1

2

30-OHM-1.7A

0402

L2640

1 2

10V

0.1uF

CERM 402

20%

C2641

1

2

10V

0.1UF

402

20% CERM

C2616

1

2

NO STUFF

AT24C08

SOIC

U2695

1

2

3

4

6

5

8

7

0.1UF

CERM

20% 10V

402

C2690

1

2

402

1/16W

5%

MF-LF

10K

R2690

1

2

44

NO STUFF

SOT23

AT24C01B

U2690

2

1

3

4

5

MF-LF

1K

1% 1/16W

402

R2620

1

2

6.3V

2.2UF

20%

402-LF

CERM

C2610

1

2

26

051-8089

SYNC_DATE=08/17/2008SYNC_MASTER=K36B_MLB

MCP Graphics Support

02

109

HDCPROM_WP

=PP3V3R1V8_S0_MCP_IFP_VDD

MCP_IFPAB_VPROBE

MCP_IFPAB_RSET

=I2C_HDCPROM_SCL

=I2C_HDCPROM_SDA

=PP1V05_S0_MCP_HDMI_VDD

=PP3V3_S0_HDCPROM

HDCPROM_WP

MCP_HDMI_VPROBE

MCP_HDMI_RSET

=PP3V3_S0_MCP_DAC_UF

PP3V3_S0_MCP_DAC

MIN_LINE_WIDTH=0.4 MM

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 MM

=PP3V3_S0_MCP_VPLL_UF

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP3V3_S0_MCP_VPLL

VOLTAGE=3.3V

25

8

18

18 71

8

18

8

25

18 71

8

18

8

18

IN

OUT

IN

OUT

IN

OUT

IN

NC NC

OUT

IN

OUT

IN

OUT

IN

OUT

Y

B

A

OUT

VIN

GND

VOUTEN

NC

IN

OUT

NC

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

MCP 25MHz Crystal

RTC Crystal

10K pull-up to 3.3V S0 inside MCP

MCP S0 PWRGD

Reset Button

SYNC FROM T18

ALIAS MEM_VTT_EN TO =DDRVTT_EN CHANGE Y2810 AND U2850 TO SMALLER PARTS

REMOVE R2824 AND NET PCI_CLK33M_SLOT_A

REMOVE UNUSED PCIE RESET SIGNALS

LPC Reset (Unbuffered)

CHANGE RESET BUTTOM TO RESET PADS

CHANGE RTC POWER SOURCE FROM COIN CELL TO SUPER CAPS

Platform Reset Connections

PCIE Reset (Unbuffered)

NC

RTC Power Sources

MCP 27MHZ CRYSTAL

PLACE C2872 CLOSE MCP

CERM

402

50V

5%

12pF

C2810

1 2

402

5%

12pF

50V

CERM

C2811

1 2

0

5%

1/16W

402

MF-LF

R2810

1 2

1/16W MF-LF

402

5%

10M

R2811

1

2

72 19

1/16W

402

5%

MF-LF

33

PLACEMENT_NOTE=Place close to U1400

R2883

1 2

402

MF-LF

1/16W

5%

33

PLACEMENT_NOTE=Place close to U1400

R2881

1 2

0

MF-LF

5%

1/16W

402

R2891

1 2

43

7

41

31

21

17

0

402

5% 1/16W MF-LF

1 2

R2826

PLACEMENT_NOTE=Place close to U1400

21

R2825

5%

402

MF-LF

1/16W

PLACEMENT_NOTE=Place close to U1400

22

72 19

50V

5%

12pF

402

CERM

C2815

1 2

5%

50V

CERM

402

12pF

C2816

1 2

CRITICAL

SM-3.2X2.5MM

25.0000M

Y2815

2 4

1 3

402

0

5% 1/16W MF-LF

R2815

1 2

NO STUFF

402

10M

MF-LF

5%

1/16W

R2816

1

2

21

72 41

5%

PLACEMENT_NOTE=Place close to U1400

402

22

MF-LF

1/16W

R2829

1 2

72 21

66

MF-LF

5%

402

1/16W

0

R2892

1 2

65 59

33

402

1/16W MF-LF

5%

R2870

1 2

19

21

0

1/16W

402

MF-LF

PLACEMENT_NOTE=Place close to U1400

5%

R2853

1 2

21

10V

402

20% CERM

0.1UF

C2850

1

2

64 41

7

60

21

72 43

7

72 41

21

402

10V

1UF

10%

X5R

NO STUFF

C2899

1

2

5%

33

1/16W MF-LF

402

R2899

1 2

402

5% 1/16W MF-LF

0

SILK_PART=SYS RST

NO STUFF

R2890

1

2

1/16W

402

XDP

0

5%

MF-LF

R2898

1 2

41

13 10

7

SM

2%

0.08F

XHHG

3.3V

C2800

1

2

27

5%

0

1/16W MF-LF

402

R2871

1 2

CRITICAL

32.768K

7X1.5X1.4-SM

Y2810

1 4

TC7SZ08AFEAPE

SOT665

U2850

2

1

3

5

4

MF-LF

402

1/16W

5%

0

R2872

1 2

35

CERM 402

1UF

6.3V

10%

C2801

1

2

100

MF-LF

1%

402

1/16W

R2801

1

2

402

CERM

50V

5%

10PF

NO STUFF

C2826

1

2

10%

402-1

1UF

X5R

10V

C2870

1

2

MIC5232-2.8YD5

TSOT-23-5

U2870

3

2

4

1

5

10%

402

0.47UF

X5R

10V

C2871

1

2

18

50V

5%

402

CERM

12pF

C2820

1 2

MF-LF

1/16W

402

5%

0

R2820

1 2

SM-2

27MHZ

CRITICAL

Y2820

2 4

1 3

NO STUFF

1/16W

5%

MF-LF

10M

402

R2821

1

2

402

CERM

5%

50V

12pF

C2821

1 2

18

28

051-8089

SB Misc

02

109

SYNC_MASTER=K36B_MLB SYNC_DATE=08/17/2008

LPC_CLK33M_SMC_R

PM_CLK32K_SUSCLK

MEM_VTT_EN_R

MCP_CLK27M_XTALIN

MCP_CLK27M_XTALOUT

FW_RESET_L

MAKE_BASE=TRUE

MEM_VTT_EN

PP3V3_G3_RTC

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

VOLTAGE=3.3V

=PP3V42_G3H_RTC_D

RTC_CLK32K_XTALOUT

PCIE_RESET_L

MCP_CLK25M_XTALIN

PM_SYSRST_L

LPC_RESET_L

PM_CLK32K_SUSCLK_R

LPC_CLK33M_LPCPLUS

LPC_CLK33M_SMC

XDP_DBRESET_L

BKLT_PLT_RST_L

SMC_LRESET_L

DEBUG_RESET_L

MINI_RESET_L

PCA9557D_RESET_L

=DDRVTT_EN

MCP_CPUVDD_EN

MCP_CPU_VLD

ALL_SYS_PWRGD

VR_PWRGOOD_DELAY

PM_SYSRST_DEBOUNCE_L

MCP_PS_PWRGD

=PP3V3_S5_MCPPWRGD

RTC_CLK32K_XTALOUT_R

MCP_CLK25M_XTALOUT_R

MCP_CLK25M_XTALOUT

RTC_CLK32K_XTALIN

G3_RTC_L

MCP_CLK27M_XTALOUT_R

21 22

8

V-

V+

V-

V+

V-

V+

V-

V+

RESET*

A0 A1 A2

SCL SDA

P0 P1 P2

P5 P6 P7

P3 P4

THRM

VCC

GND

PAD

NC NC

NC

IN

IN BI

VDD

VOUTD

VOUTC

VOUTB

VOUTA

SCL

SDA

A0

A1

GND

IN

BI

NC

OUT

NC

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

Place close to U1000.AD26

Page Notes

Power aliases required by this page:

ADDR=0x30(WR)/0x31(RD)

- =I2C_PCA9557D_SDA

- =I2C_PCA9557D_SCL

VREFMRGN AND NO VERFMRGN

- =PP3V3_S5_VREFMRGN

Signal aliases required by this page:

- =I2C_VREFDACS_SCL

- =I2C_VREFDACS_SDA

- =PP3V3_S3_VREFMRGN

- =PPVTT_S3_DDR_BUF

BOM options provided by this page:

ADDR=0x98(WR)/0x99(RD)

Voltage divider resistor values at op-amp outputs not yet finalized.

Place close to J3100.1

BOM OPTION TO SELECT VREF SOURCE

10mA max load

Place close to J3200.1

MAX4253

UCSP

VREFMRGN

U2902

A3

A2

A1

A4

B1

B4

MAX4253

VREFMRGN

UCSP

U2902

C3

C2

C1

C4

B1

B4

MAX4253

UCSP

VREFMRGN

U2904

C3

C2

C1

C4

B1

B4

MAX4253

VREFMRGN

UCSP

U2904

A3

A2

A1

A4

B1

B4

VREFMRGN

20% 10V

402

0.1UF

CERM

C2902

1

2

100K

MF-LF

VREFMRGN

5%

402

1/16W

R2902

1 2

100K

VREFMRGN

402

MF-LF

1/16W

5%

R2901

1 2

1/16W

1%

VREFMRGN

100

402

MF-LF

R2904

1 2

NO_VREFMRGN

402

0

5% 1/16W MF-LF

R2903

1 2

NO_VREFMRGN

0

1/16W

402

MF-LF

5%

R2905

1 2

100

VREFMRGN

MF-LF

402

1% 1/16W

R2906

1 2

PCA9557

QFN

VREFMRGN

U2901

3 4 5

8

6 7 9 10 11 12 13 14

15

1 2

17

16

26

44

DAC5574

MSOP

VREFMRGN

U2900

9

10

3

6

7

8

1

2

4

5

44

0.1UF

VREFMRGN

402

20% 10V CERM

C2901

1

2

2.2UF

VREFMRGN

6.3V CERM

20%

402-LF

C2900

1

2

VREFMRGN

402

CERM

10V

20%

0.1UF

C2905

1

2

402

100

1%

VREFMRGN

1/16W MF-LF

R2914

1 2

MF-LF

402

5%

100K

1/16W

VREFMRGN

R2913

1 2

VREFMRGN

0.1UF

402

20% CERM

10V

C2903

1

2

69 10

29

051-8089

FSB/DDR2 VREF MARGINING

SYNC_MASTER=K36B_MLB

109

02

SYNC_DATE=08/17/2008

RES, MTL FILM, 200, 1%, 0402, SM, LF

114S0149

R2903

VREFMRGN

1

RES, MTL FILM, 200, 1%, 0402, SM, LF

R2905

1

VREFMRGN114S0149

MIN_NECK_WIDTH=0.25 mm

MEM_VREF_B

MIN_LINE_WIDTH=0.25 mm

VREFMRGN_DQ_SODIMMA_BUF

=PPVTT_S3_DDR_BUF

MIN_LINE_WIDTH=0.25 mm

MEM_VREF_A

MIN_NECK_WIDTH=0.25 mm

VREFMRGN_DQ_SODIMMA_EN

=PP3V3_S3_VREFMRGN

VREFMRGN_DQ_SODIMMB_BUF

=I2C_VREFDACS_SCL

=I2C_PCA9557D_SCL

PCA9557D_RESET_L

=I2C_PCA9557D_SDA

=I2C_VREFDACS_SDA

VREFMRGN_CPUFSB_EN

VREFMRGN_DQ_SODIMMA_EN

CPU_GTLREF

VREFMRGN_DQ_SODIMMB_EN

VREFMRGN_CPUFSB_EN

VREFMRGN_CPUFSB_BUF

VREFMRGN_DQ_SODIMM

VREFMRGN_DQ_SODIMMB_EN

VREFMRGN_CPUFSB

29

8

59

28

27

8

27

VSS10

VSS2

DQ5

SA1

SA0

VSS58

DQ63

DQ62

VSS56

DQS7

DQS7*

VSS54

DQ60

VSS52

DQ54

VSS50

VSS48

CK1*

CK1

VSS46

DQ53

DQ52

VSS44

VSS42

DQS5

DQS5*

VSS39

DQ45

DQ44

VSS37

DQ39

DQ38

VSS35

DM4

VSS34

DQ37

DQ36

VSS32

NC3

VDD11

NC/A13

ODT0

VDD9

S0*

RAS*

BA1

VDD7

A0

A2

A4

VDD5

A6

A7

A11

VDD3

NC/A14

NC/A15

VDD1

NC/CKE1

VSS30

DQ31

DQ30

VSS28

DQS3

DQS3*

VSS26

DQ29

DQ28

VSS24

DQ23

DQ22

VSS22

DM2

NC0

VSS19

DQ21

DQ20

VSS17

VSS15

DQ15

DQ14

VSS13

CK0*

CK0

VSS11

DQ13

VSS7

DQ7

VSS5

DM0

DQ4

VSS0

DM1

DQ12

DQ6

DQ47

DQ46

DQ61

DQ55

DM6

VDDSPD

SCL

SDA

VSS57

DQ59

DQ58

VSS55

DM7

VSS53

DQ56

VSS51

DQ50

VSS49

DQS6*

VSS47

NC_TEST

VSS45

DQ49

DQ48

VSS43

VSS41

DM5

VSS40

DQ41

VSS38

DQ35

VSS36

DQS4

DQS4*

VSS33

DQ33

DQ32

VSS31

NC/ODT1

VDD10

NC/S1*

CAS*

VDD8

WE*

BA0

A10/AP

VDD6

A1

A3

A5

VDD4

A8

A9

A12

VDD2

BA2

NC2

VDD0

CKE0

VSS29

DQ27

DQ26

VSS27

NC1

DM3

VSS25

DQ25

DQ24

VSS23

DQ19

DQ18

VSS21

DQS2

DQS2*

VSS18

DQ17

DQ16

VSS16

VSS14

DQ11

DQ10

VSS12

DQS1

DQS1*

DQ9

DQ8

VSS8

DQ3

DQ2

VSS6

DQS0

DQS0*

VSS4

VSS1

VREF

DQ0 DQ1

DQ34

DQ40

DQ42 DQ43

DQS6

DQ51

DQ57

KEY

VSS9

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Page Notes

DIP DIMM CONN

NC

516-0135

- =I2C_MEM_SDA

- =I2C_MEM_SCL

- =PPSPD_S0_MEM (2.5V - 3.3V)

Power aliases required by this page:

DDR2 Bypass Caps

(NONE)

(For return current)

BOM options provided by this page:

Signal aliases required by this page:

- =PP1V8_S3_MEM

ADDR=0xA0(WR)/0xA1(RD)

NC

NC NC

NC

The 4.7uF and 1.0uF caps can be changed to 5x 2.2uF caps, when they get cheaper.

DDR2-800

20%

6.3V

4.7uF

603

CERM

C3121

1

2

10V

0.1UF

CERM

20%

402

C3110

1

2

0.1UF

20% 10V

402

CERM

C3101

1

2

0.1UF

CERM

10V

20% 402

C3131

1

2

402

2.2UF

20% X5R

4V

C3100

1

2

4V 402

20%

2.2UF

X5R

C3130

1

2

2.2UF

20%

6.3V

CERM 402-LF

C3118

1

2

2.2UF

20% CERM

6.3V

402-LF

C3120

1

2

2.2UF

20% CERM

6.3V

402-LF

C3119

1

2

F-RT-TH4

CRITICAL

DDR2-SODIMM-STD

J3100

102101

105

9089

100

99

9897

94

92

93

91

107

106

85

113

30 32

164 166

79

10

26

52

67

130

147

170

185

5 7

35 37

20 22

36 38

43 45

55 57

17

44 46

56 58

61 63

73 75

62 64

19

74 76

123 125

135 137

124 126

134 136

4

141 143

151 153

140 142

152 154

157 159

6

173 175

158 160

174 176

179 181

189 191

14

180 182

192 194

16

23 25

13

11

31

29

51

49

70

68

131

129

148

146

169

167

188

186

201

202

116

86

84

80

119

115

50

69

83

120

163

114

108 110

198 200

197

195

81 82

117 118

87 88

95 96

103 104

111 112

199

1 2 3

27 28

33 34

39 40 41 42

47 48

8

53 54

59 60

65 66

71 72

77 78

121 122

127 128

132

133

138

139

144

9

145

149 150

155 156

161 162

165

168

171

12

172

177 178

183 184

187

190

193

196

15

18

21

24

109

0.1UF

402

20%

10V

CERM

C3111

1

2

0.1UF

10V

20%

402

CERM

C3112

1

2

402

20%

10V

CERM

0.1UF

C3113

1

2

0.1UF

CERM

10V

20%

402

C3114

1

2

20% CERM

402

10V

0.1UF

C3115

1

2

2.2UF

20%

6.3V

CERM 402-LF

C3116

1

2

2.2UF

20%

6.3V

CERM 402-LF

C3117

1

2

10K

5% 1/16W MF-LF

402

R3141

1 2

10K

1/16W

402

MF-LF

5%

R3140

1 2

31

051-8089

DDR2 SO-DIMM Connector A

SYNC_DATE=08/17/2008

109

SYNC_MASTER=K36B_MLB

02

=PP1V8_S3_MEM

MEM_A_DQ<12>

MEM_A_DQ<27>

MEM_A_DQ<10>

MEM_A_DQ<29> MEM_A_DQ<28>

MEM_EVENT_L

MEM_A_DQS_P<3>

MEM_A_DQ<30>

MEM_A_DQ<31>

MEM_A_DQ<13>

MEM_A_DM<0>

MEM_A_DQ<0>

MEM_A_DQ<26>

MEM_A_DQ<18> MEM_A_DQ<21>

MEM_A_DQS_N<2>

=PP1V8_S3_MEM

MEM_A_DQ<17>

MEM_A_ODT<0>

MEM_A_DQ<45>

MEM_A_BA<2>

MEM_A_A<12> MEM_A_A<9> MEM_A_A<8>

MEM_A_A<3> MEM_A_A<1>

MEM_A_WE_L

MEM_A_A<5>

MEM_A_DQ<33>

MEM_A_DQ<32>

MEM_A_A<7>

MEM_A_A<11>

MEM_A_DM<1>

MEM_A_DQ<2>

MEM_A_DQ<3>

MEM_A_DQS_N<0>

MEM_A_CKE<0>

MEM_A_DQ<22>

MEM_A_DQ<23>

MEM_A_DQ<14>

MEM_A_DQ<15>

MEM_A_DM<2>

MEM_A_DQS_P<0>

MEM_A_DQS_P<4>

MEM_A_DQS_P<6>

MEM_A_DQ<51>

MEM_A_DM<7>

MEM_A_DQ<48>

MEM_A_DQ<63>

MEM_A_DQ<59>

=I2C_SODIMMA_SDA

MEM_A_SA1

MEM_A_SA0

MEM_A_DQ<57>

MEM_A_DQ<46>

MEM_A_DQ<43>

MEM_A_DQS_P<5>

MEM_A_DQ<55>

MEM_A_DQ<50>

MEM_A_DQ<9>

=I2C_SODIMMA_SCL

=GND_CHASSIS_DIPDIMM_LEFT

MEM_A_DQS_N<4>

MEM_A_DQ<38>

MEM_A_DM<5>

MEM_A_DQ<42>

MEM_A_DM<4>

MEM_A_DQ<34>

MEM_A_DQ<44>

MEM_A_DQ<54>

MEM_A_DQ<36> MEM_A_DQ<37>

MEM_A_DQ<39>

MEM_A_DQ<40> MEM_A_DQ<41>

MEM_A_DQ<47>

MEM_A_DQ<56>

MEM_A_DQS_N<7> MEM_A_DQS_P<7>

MEM_A_DQ<53>

MEM_A_DM<6>

=PPSPD_S0_MEM

MEM_A_DQ<60>

MEM_A_DQS_N<6>

MEM_A_DQ<49>

MEM_A_SA0

MEM_A_SA1

MEM_A_DQ<1>

MEM_A_DQ<58>

MEM_A_DQ<52>

MEM_A_DQ<62>

MEM_A_DQ<61>

MEM_A_CLK_N<1>

MEM_A_CLK_P<1>

MEM_A_DQ<16> MEM_A_DQ<20>

MEM_A_A<6>

MEM_A_DQS_N<3>

MEM_A_DQ<19>

MEM_A_DQS_N<5>

MEM_A_DQ<35>

MEM_A_CS_L<0>

MEM_A_A<4> MEM_A_A<2> MEM_A_A<0>

MEM_A_BA<1> MEM_A_RAS_L

MEM_A_A<13>

MEM_A_ODT<1>

MEM_A_CS_L<1>

MEM_A_CAS_L

MEM_A_BA<0>

MEM_A_A<10>

MEM_A_DQ<4>

MEM_A_DQ<6>

=GND_CHASSIS_DIPDIMM_CENTER

MEM_A_DQ<5>

MEM_A_A<14>

MEM_A_CKE<1>

MEM_A_A<15>

MEM_A_DM<3>

MEM_A_DQ<7>

MEM_A_DQ<8>

MEM_A_DQS_N<1> MEM_A_DQS_P<1>

MEM_A_DQS_P<2>

MEM_A_DQ<25>

MEM_A_DQ<24>

MEM_A_CLK_P<0> MEM_A_CLK_N<0>

MEM_VREF_A

MEM_A_DQ<11>

=PP1V8_S3_MEM

8

28 29

15 70

21 29 41

15 70

8

28 29

15 70

15 30 70

15 70

15 30 70

15 70

15 30 70

15 70

15 30 70

15 70

44

28

15 70

44

15 70

8

29

15 70

28

15 70

15 30 70

15 70

15 30 70

15 70

9 29

15 70

15 30 70

9

15 70

27

15 70

8

28 29

VSS10

VSS2

DQ5

SA1

SA0

VSS58

DQ63

DQ62

VSS56

DQS7

DQS7*

VSS54

DQ60

VSS52

DQ54

VSS50

VSS48

CK1*

CK1

VSS46

DQ53

DQ52

VSS44

VSS42

DQS5

DQS5*

VSS39

DQ45

DQ44

VSS37

DQ39

DQ38

VSS35

DM4

VSS34

DQ37

DQ36

VSS32

NC3

VDD11

NC/A13

ODT0

VDD9

S0*

RAS*

BA1

VDD7

A0

A2

A4

VDD5

A6

A7

A11

VDD3

NC/A14

NC/A15

VDD1

NC/CKE1

VSS30

DQ31

DQ30

VSS28

DQS3

DQS3*

VSS26

DQ29

DQ28

VSS24

DQ23

DQ22

VSS22

DM2

NC0

VSS19

DQ21

DQ20

VSS17

VSS15

DQ15

DQ14

VSS13

CK0*

CK0

VSS11

DQ13

VSS7

DQ7

VSS5

DM0

DQ4

VSS0

DM1

DQ12

DQ6

DQ47

DQ46

DQ61

DQ55

DM6

VDDSPD

SCL

SDA

VSS57

DQ59

DQ58

VSS55

DM7

VSS53

DQ56

VSS51

DQ50

VSS49

DQS6*

VSS47

NC_TEST

VSS45

DQ49

DQ48

VSS43

VSS41

DM5

VSS40

DQ41

VSS38

DQ35

VSS36

DQS4

DQS4*

VSS33

DQ33

DQ32

VSS31

NC/ODT1

VDD10

NC/S1*

CAS*

VDD8

WE*

BA0

A10/AP

VDD6

A1

A3

A5

VDD4

A8

A9

A12

VDD2

BA2

NC2

VDD0

CKE0

VSS29

DQ27

DQ26

VSS27

NC1

DM3

VSS25

DQ25

DQ24

VSS23

DQ19

DQ18

VSS21

DQS2

DQS2*

VSS18

DQ17

DQ16

VSS16

VSS14

DQ11

DQ10

VSS12

DQS1

DQS1*

DQ9

DQ8

VSS8

DQ3

DQ2

VSS6

DQS0

DQS0*

VSS4

VSS1

VREF

DQ0 DQ1

DQ34

DQ40

DQ42 DQ43

DQS6

DQ51

DQ57

KEY

VSS9

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

NC

DDR2-800

The 4.7uF and 1.0uF caps can be changed to 5x 2.2uF caps,

when they get cheaper.

NC

(NONE)

516-0135

NC

by another page.

The reference voltage must be provided

NOTE: This page does not supply VREF.

BOM options provided by this page:

- =I2C_MEM_SDA

- =I2C_MEM_SCL

Signal aliases required by this page:

- =PPSPD_S0_MEM (2.5V - 3.3V)

- =PP1V8_S3_MEM

Power aliases required by this page:

Page Notes

NC

Resistor prevents pwr-gnd short

ADDR=0XA2(WR)/0XA3(RD)

DIP DIMM CONN

DDR2 Bypass Caps

(For return current)

4.7uF

6.3V

20% CERM

603

C3221

1

2

0.1UF

10V CERM

20% 402

C3201

1

2

402

20%

10V

CERM

0.1UF

C3210

1

2

4V X5R 402

20%

2.2UF

C3200

1

2

402-LF

CERM

2.2UF

20%

6.3V

C3219

1

2

CERM

6.3V

20%

2.2UF

402-LF

C3218

1

2

402-LF

6.3V

CERM

2.2UF

20%

C3220

1

2

402

CERM

10V

0.1UF

20%

C3231

1

2

X5R 402

2.2UF

20% 4V

C3230

1

2

5% 1/16W MF-LF 402

10K

R3240

1

2

DDR2-SODIMM-STD

CRITICAL

F-RT-TH4

J3200

102101

105

9089

100

99

9897

94

92

93

91

107

106

85

113

30 32

164 166

79

10

26

52

67

130

147

170

185

5 7

35 37

20 22

36 38

43 45

55 57

17

44 46

56 58

61 63

73 75

62 64

19

74 76

123 125

135 137

124 126

134 136

4

141 143

151 153

140 142

152 154

157 159

6

173 175

158 160

174 176

179 181

189 191

14

180 182

192 194

16

23 25

13

11

31

29

51

49

70

68

131

129

148

146

169

167

188

186

201

202

116

86

84

80

119

115

50

69

83

120

163

114

108 110

198 200

197

195

81 82

117 118

87 88

95 96

103 104

111 112

199

1 2 3

27 28

33 34

39 40 41 42

47 48

8

53 54

59 60

65 66

71 72

77 78

121 122

127 128

132

133

138

139

144

9

145

149 150

155 156

161 162

165

168

171

12

172

177 178

183 184

187

190

193

196

15

18

21

24

109

0.1UF

CERM

20%

402

10V

C3211

1

2

10V

20%

402

CERM

0.1UF

C3212

1

2

0.1UF

CERM

10V

20%

402

C3213

1

2

0.1UF

20% CERM

10V

402

C3214

1

2

0.1UF

20% CERM

10V

402

C3215

1

2

CERM

6.3V

2.2UF

20%

402-LF

C3216

1

2

20%

6.3V

CERM

2.2UF

402-LF

C3217

1

2

1/16W 402

MF-LF

5%

10K

R3241

1

2

SYNC_DATE=08/17/2008SYNC_MASTER=K36B_MLB

02

109

DDR2 SO-DIMM Connector B

051-8089

32

MEM_B_DQS_N<0>

MEM_B_DQ<21> MEM_B_DQ<17>

MEM_EVENT_L

=PP1V8_S3_MEM

MEM_VREF_B

MEM_B_DQ<5>

MEM_B_DQ<6>

MEM_B_DQ<14>

MEM_B_DQ<12>

MEM_B_DQ<2>

MEM_B_DQ<8>

MEM_B_DM<2>

MEM_B_BA<2>

MEM_B_DM<6>

MEM_B_DQ<63> MEM_B_DQ<59>

MEM_B_SA0 J3201_SA1

MEM_B_DQS_P<7>

MEM_B_DQS_N<7>

MEM_B_DQ<51>

MEM_B_CLK_N<1>

=PPSPD_S0_MEM

MEM_B_SA0

J3201_SA1

MEM_B_DQ<38>

MEM_B_DQ<23>

MEM_B_DQ<19>

MEM_B_DQ<22>

MEM_B_A<8>

MEM_B_DQS_N<1> MEM_B_DQS_P<1>

MEM_B_DQ<9>

MEM_B_DQ<7>

MEM_B_DQS_P<0>

MEM_B_A<6>

MEM_B_A<13>

MEM_B_CS_L<1>

MEM_B_ODT<1>

MEM_B_WE_L

MEM_B_BA<0>

MEM_B_A<10>

MEM_B_A<3>

MEM_B_A<5>

MEM_B_RAS_L

MEM_B_DQ<35>

MEM_B_DQ<24>

MEM_B_DQS_P<2>

=GND_CHASSIS_DIPDIMM_CENTER

=GND_CHASSIS_DIPDIMM_RIGHT

MEM_B_DQ<61>

MEM_B_DQ<50>

MEM_B_DQS_P<6>

MEM_B_DQ<42>

MEM_B_DQ<45>

MEM_B_DQ<37>

MEM_B_DQ<1>

MEM_B_DQ<11>

MEM_B_DQS_N<2>

MEM_B_DQ<28>

MEM_B_DM<3>

MEM_B_DQ<29> MEM_B_DQ<25>

MEM_B_DQ<39> MEM_B_DQ<34>

MEM_B_DQS_N<4> MEM_B_DQS_P<4>

MEM_B_DQ<32>

MEM_B_DQ<44>

MEM_B_DM<5>

MEM_B_DQ<49> MEM_B_DQ<53>

MEM_B_DQS_N<6>

MEM_B_DQ<55>

MEM_B_DQ<60>

MEM_B_DM<7>

MEM_B_DQ<57> MEM_B_DQ<56>

=I2C_SODIMMB_SDA =I2C_SODIMMB_SCL

=PPSPD_S0_MEM

MEM_B_DQ<43>

MEM_B_DM<1>

MEM_B_DQ<3>

MEM_B_DQ<0> MEM_B_DQ<4>

MEM_B_DM<0>

MEM_B_DQ<13>

MEM_B_CLK_N<0>

MEM_B_DQ<10> MEM_B_DQ<15>

MEM_B_DQ<16> MEM_B_DQ<20>

MEM_B_DQ<30> MEM_B_DQ<26>

MEM_B_DQS_P<3>

MEM_B_DQ<27>

MEM_B_DQ<47>

MEM_B_DQ<46>

MEM_B_DQ<40> MEM_B_DQ<41>

MEM_B_DQS_N<5> MEM_B_DQS_P<5>

MEM_B_DQ<48>

MEM_B_CLK_P<1>

MEM_B_DQ<54>

MEM_B_DQ<58> MEM_B_DQ<62>

MEM_B_DQ<52>

MEM_B_CLK_P<0>

MEM_B_DQ<18>

MEM_B_CKE<1>

MEM_B_A<15> MEM_B_A<14>

MEM_B_A<11> MEM_B_A<7>

MEM_B_CKE<0>

MEM_B_A<12>

MEM_B_A<1>

MEM_B_A<9>

MEM_B_CAS_L

MEM_B_DQ<33>

MEM_B_BA<1>

MEM_B_DM<4>

MEM_B_DQ<36>

MEM_B_ODT<0>

=PP1V8_S3_MEM

MEM_B_DQ<31>

MEM_B_DQS_N<3>

MEM_B_CS_L<0>

MEM_B_A<0>

MEM_B_A<2>

MEM_B_A<4>

=PP1V8_S3_MEM

15 70

21 28 41

8

28 29

27

15 70

15 30 70

15 70

29

15 70

8

28 29

29

15 70

15 30 70

15 70

15 30 70

15 30 70 15 30 70

15 30 70

15 70

9 28

9

15 70

44

8

28 29

15 70

15 30 70

9

15 30 70

15 70

15 30 70

15 70

15 30 70

8

28 29

15 70

15 30 70

8

28 29

IN

IN IN IN IN IN IN IN IN IN IN IN IN IN IN

IN IN

IN

IN IN IN

IN

IN IN IN

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TO PP0V9_S0_MEM_TERM

LAYOUT NOTE:PLACE ONE CAP CLOSE TO EVERY TWO PULLUP RESISTORS TERMINATED

One cap for each side of every RPAK, one cap for every two discrete resistors BOMOPTION shown at the top of each group applies to every part below it

47

5%

MF-LF1/16W

402

R3301

1 2

47

402

MF-LF1/16W

5%

R3309

1 2

47

1/16WMF-LF

402

5%

R3311

1 2

47

MF-LF

402

1/16W

5%

R3325

1 2

5%

47

402

1/16WMF-LF

R3335

1 2

0

2

1

70 29 15

SM-LF

47

5%

1/16W

RP3300

3 6

47

1/16W

5%

SM-LF

RP3300

4 5

47

SM-LF

1/16W

5%

RP3300

1 8

47

1/16W

5%

SM-LF

RP3300

2 7

47

SM-LF

1/16W

5%

RP3301

2 7

47

1/16W

SM-LF

5%

RP3301

1 8

47

1/16W

5%

SM-LF

RP3301

4 5

47

1/16W

SM-LF

5%

RP3301

3 6

1/16W

5%

SM-LF

47

RP3302

4 5

47

1/16W

SM-LF

5%

RP3302

1 8

47

5%

SM-LF

1/16W

RP3302

3 6

47

1/16W

SM-LF

5%

RP3302

2 7

SM-LF

5%471/16W

RP3303

1 8

47

1/16W

5%

SM-LF

RP3303

2 7

47

SM-LF

1/16W

5%

RP3303

3 6

47

SM-LF

5%

1/16W

RP3303

4 5

47

SM-LF

1/16W

5%

RP3304

1 8

47

SM-LF

1/16W

5%

RP3304

3 6

47

5%

SM-LF

1/16W

RP3304

4 5

1/16W

SM-LF

5%

47

RP3305

1 8

47

5%

SM-LF

1/16W

RP3305

2 7

47

1/16W

5%

SM-LF

RP3305

3 6

47

SM-LF

1/16W

5%

RP3305

4 5

47

1/16W

5%

SM-LF

RP3306

2 7

47

SM-LF

1/16W

5%

RP3306

3 6

47

SM-LF

5%

1/16W

RP3307

4 5

47

SM-LF

5%

1/16W

RP3307

3 6

47

SM-LF

1/16W

5%

RP3307

2 7

47

1/16W

SM-LF

5%

RP3307

1 8

47

1/16W

5%

SM-LF

RP3308

4 5

47

SM-LF

5%

1/16W

RP3308

3 6

47

SM-LF

5%

1/16W

RP3308

2 7

47

SM-LF

1/16W

5%

RP3308

1 8

47

SM-LF

1/16W

5%

RP3309

1 8

47

SM-LF

1/16W

5%

RP3309

2 7

47

SM-LF

1/16W

5%

RP3309

3 6

47

SM-LF

1/16W

5%

RP3309

4 5

47

SM-LF

1/16W

5%

RP3310

3 6

47

SM-LF

1/16W

5%

RP3310

2 7

47

SM-LF

1/16W

5%

RP3310

1 8

47

5%

SM-LF

1/16W

RP3310

4 5

47

SM-LF

1/16W

5%

RP3311

1 8

47

SM-LF

1/16W

5%

RP3311

2 7

47

1/16W

5%

SM-LF

RP3311

4 5

47

SM-LF

1/16W

5%

RP3306

4 5

47

1/16W

5%

SM-LF

RP3311

3 6

70 29 15

402

CERM

10V

20%

0.1UF

C3300

1

2

0.1UF

20%

402

10V CERM

C3301

1

2

0.1UF

CERM

10V

20%

402

C3302

1

2

402

10V CERM

20%

0.1UF

C3303

1

2

0.1UF

CERM

10V

20%

402

C3304

1

2

0.1UF

402

20% 10V CERM

C3305

1

2

0.1UF

CERM

10V

20%

402

C3306

1

2

20% 10V CERM

0.1UF

402

C3307

1

2

402

20%

0.1UF

CERM

10V

C3308

1

2

402

20% 10V CERM

0.1UF

C3309

1

2

0.1UF

20% CERM

10V 402

C3310

1

2

20%

402

10V CERM

0.1UF

C3311

1

2

20%

402

CERM

10V

0.1UF

C3312

1

2

CERM

0.1UF

402

20% 10V

C3313

1

2

10V CERM

20%

402

0.1UF

C3314

1

2

402

20% 10V CERM

0.1UF

C3315

1

2

0.1UF

402

CERM

10V

20%

C3316

1

2

CERM

0.1UF

10V 402

20%

C3317

1

2

0.1UF

CERM

10V

20%

402

C3318

1

2

402

20% 10V CERM

0.1UF

C3319

1

2

0.1UF

CERM

10V

20%

402

C3320

1

2

402

20% 10V CERM

0.1UF

C3321

1

2

0.1UF

CERM

10V

20%

402

C3322

1

2

402

20% 10V CERM

0.1UF

C3323

1

2

0.1UF

CERM

10V

20%

402

C3324

1

2

0.1UF

CERM

10V

20%

402

C3325

1

2

70 28 15

70 29 15

14

70 29 15

47

SM-LF

1/16W

5%

RP3304

2 7

SM-LF

5%

1/16W

47

RP3306

1 8

1/16W

402

5%

MF-LF

47

R3327

1 2

70 28 15

70 29 15

70 28 15

70 29 15

1

0

2

0

1

2

3

4

5

6

7

10

11

9

8

13

12

70 28 15

109

02

Memory Active Termination

051-8089

33

MEM_A_BA<2..0>

MEM_A_A<14..0>

MEM_B_BA<2..0>

MEM_A_WE_L

MEM_A_CAS_L

MEM_A_RAS_L

MEM_B_CS_L<1>

=PP0V9_S3M_MEM_TERM

MEM_B_CKE<1>

MEM_B_A<14>

MEM_A_ODT<0> MEM_A_ODT<1>

MEM_B_A<0> MEM_B_A<3> MEM_B_A<2>

MEM_B_A<6>

MEM_B_WE_L

MEM_B_A<12>

MEM_B_A<11>

MEM_B_A<9> MEM_B_A<1>

MEM_B_ODT<0>

MEM_B_RAS_L MEM_B_CAS_L

MEM_B_ODT<1>

MEM_B_A<13>

MEM_B_A<7>

MEM_B_A<5>

MEM_B_A<8>

MEM_B_A<4>

MEM_B_A<10>

MEM_B_CS_L<0>

MEM_A_CS_L<1>

MEM_A_CS_L<0>

MEM_A_CKE<0>

MEM_B_CKE<0>

MEM_A_CKE<1>

8

Y

B

A

IN

NC

KEY

IN

OUT OUT

IN

OUT

IN

OUT

IN

S

G

D

BI

IN

D

SG

D

SG

SYM_VER-1

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

CONNECT TO M35 MODULE

OLD:516S0406 (FOXCONN ONLY) NEW:516S0635 (FOXCONN & ACON)

750 mA nominal max

PLACE C3422 NEAR J3400

AIRPORT

1000 mA peak

275 mA peak

206 mA nominal max

IT IS CO-LAY FUNCTION

PLACE C3420 AND C3421 NEAR Q3450

0402-LF

FERR-120-OHM-1.5A

L3405

12

CERM

402

10V

20%

0.1uF

C3452

1

2

TC7SZ08AFEAPE

SOT665

U3401

2

1

3

5

4

26

SOT-553

74LVC1G17DRL

U3402

2

3 1

5

4

MF-LF

5% 1/16W

33K

402

R3453

1

2

1/16W

5%

MF-LF 402

62K

R3454

1

2

402

1UF

10%

6.3V CERM

C3453

1

2

F-ST-SM

CRITICAL

ASOB226-S45B-7F

J3400

53

54

1

10 11 12 13 14

15

16 17 18 19

2

20 21 22 23 24 25 26 27 28 29

3

30 31 32 33 34 35 36 37 38 39

4

40 41 42 43 44 45 46 47 48 49

5

50 51 52

6 7 8 9

16V X5R 40210%

0.1uF

PLACEMENT_NOTE=PLACE CLOSE TO J3400.

C3430

1 2

71 17

7

71 17

7

71 17

7

31

71 17

7

0402-LF

FERR-120-OHM-1.5A

L3404

12

17

7

20%

CERM

10V

402

0.1uF

C3422

1

2

20%

0.1uF

402

CERM

10V

C3421

1

2

603

X5R

6.3V

20%

10uF

C3420

1

2

10%

X5R

0.1UF

402

16V

C3450

1 2

402

100K

1/16W

5%

MF-LF

R3450

1 2

0.033UF

10% 16V X5R 402

C3451

1

2

10K

5% 1/16W

402

MF-LF

R3451

1

2

33

FDC606P_G

SOT-6

Q3450

1 2 5 6

3

4

10%

0.1uF

X5R16V 402

PLACEMENT_NOTE=PLACE CLOSE TO J3400.

C3431

1 2

9

44

7

44

7

CERM

20% 10V

402

0.1UF

C3404

1

2

CERM

10V 402

20%

0.1UF

C3405

1

2

10V

20%

0.1UF

402

CERM

C3406

1

2

SSM6N15FEAPE

SOT563

Q3401

6

2

1

SOT563

SSM6N15FEAPE

Q3401

3

5

4

90-OHM DLP0NS

CRITICAL

L3402

1 2

34

051-8089

Right Clutch Connector

SYNC_MASTER=K36B_MLB SYNC_DATE=08/17/2008

02

109

PCIE_CLK100M_MINI_N

PCIE_CLK100M_MINI_P

MINI_RESET

PP3V3_S3_AIRPORT_CONN

I2C_MINI_PCIE_SCL

PCIE_MINI_R2D_P

PP3V3_WLAN

VOLTAGE=3.3 V

MIN_LINE_WIDTH=1 MM

MIN_NECK_WIDTH=0.5 MM

PCIE_MINI_D2R_P

PCIE_MINI_D2R_N

=PP1V5_S0_AIRPORT

PCIE_MINI_PRSNT_L

PP3V3_WLAN_F

MIN_LINK_WIDTH=1 MM

VOLTAGE=3.3 V MIN_NECK_WIDTH=0.5 MM

=USB_MINI_N

=USB_MINI_P

MINI_CLKREQ_CONN_L

MINI_CLKREQ_L

=PP3V3_S3_AIRPORT_AUX

=PP3V3_S3_WLAN

PP3V3_WLAN_BUF

MINI_RESET_L

P3V3WLAN_S5

PCIE_MINI_R2D_C_N PCIE_MINI_R2D_C_P

PP3V3_WLAN_RC

AP_PWR_EN

PM_WLAN_EN_L

=PP3V3_S3_AIRPORT_AUX

USB2_AIRPORT_P

PP3V3_WLAN_F

PCIE_WAKE_L

I2C_MINI_PCIE_SDA

USB2_AIRPORT_N

PCIE_MINI_R2D_N

7

71

7

8

17

31

7 17

8

31

8

21 33

8

31

7

72

31

7

71

TXD[2]

TXCTL

AVDD33

FB12

DVDD12

AVDD12

RXC

MDIO

GND

TXD[3]

RXD[0]

MDI+[0]

CKXTAL1 CKXTAL2

CLK125

RSET

PHYRSTB*

MDC

RXCTL

MDI-[2]

MDI+[2]

MDI+[3]

MDI+[1] MDI-[1]

ENSWREG

TXD[1]

TXD[0]

RXD[3]/AN1

RXD[1]/TXDLY

TXC

MDI-[3]

LED1/PHYAD1

LED2/RXDLY

LED0/PHYAD0

RXD[2]/AN0

MDI-[0]

REGOUT

VDDREG

DVDD33

REFERENCE

RGMII/MII

MEDIA DEPENDENT

MANAGEMENT

CLOCK

RESET

LED

IN IN IN IN

IN

IN BI

IN

BI

BI BI

OUT

OUT OUT OUT OUT

OUT

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

PHYAD = 01 (PHY Address 00001)

Configuration Settings:

AN[1:0] = 11 (Full auto-negotiation) RXDLY = 0 (RXCLK transitions with data) TXDLY = 0 (No TXCLK Delay)

PLACE R3796 CLOSE TO U1400, PIN D24

WF: Marvell numbers, update for Realtek

(19mA typ - Energy Detect)

(43mA typ - 1000base-T)

Alias to GND for external 1.05V supply.

NOTE: VDDREG rise time must be >1ms to avoid damage to switcher.

If internal switcher is used, must place inductor within 5mm

If internal switcher is not used, VDDREG and REGOUT can float.

1x 0.1uF caps within 5mm of U3700 pins 44 & 45.

If internal switcher is used, must place 1x 22uF &

WF: Marvell numbers, update for Realtek

(221mA typ - 1000base-T)

of U3700, and 1x 22uF & 1x 0.1uF caps within 5mm of inductor.

Reserved for EMI per RealTek request.

PHY_AD0/LED0

RXDLY/LED2

If false, ENET_RESET_L should be removed.

WF: Verify that ENET_RESET_L does not assert when WOL is active. If true, RC and 0-ohm resistor should be removed.

Alias to =PP3V3_ENET_PHY for internal switcher.

( 7mA typ - Energy Detect)

NO STUFF

10V CERM 402

20%

0.1UF

C3727

1

2

1/16W MF-LF

402

1%

2.49K

R3730

1

2

5%

402

1/16W

4.7K

MF-LF

NO STUFF

R3799

1

2

5% 1/16W MF-LF

10K

402

R3720

1

2

0402-LF

CRITICAL

FERR-120-OHM-1.5A

L3705

1

2

10%

402

X5R

16V

0.1UF

C3705

1

2

CRITICAL

RTL8211CLGR

TQFP

OMIT

U3700

10

40

6

41

42

43

32

28

36

152137

39

3

7

203347

34 35

38

30

2

1

5

4

9

8

12

11

31

29

48

46

19

13

14

16 17

18

22

27

23

24 25

26

44

45

10% X5R

16V

0.1UF

402

C3706

1

2

10%

402

0.1UF

X5R

16V

C3700

1

2

0.1UF

10%

402

X5R

16V

C3701

1

2

0.1UF

10% X5R

16V 402

C3702

1

2

73 18

33

73 34

402

22

1/16W5%MF-LF

R3790

1 2

22

5%

1/16W MF-LF

402

R3791

1 2

22

5%

1/16W MF-LF

402

R3792

1 2

5%

1/16W MF-LF

402

22

R3793

1 2

5%

1/16W MF-LF22402

R3794

1 2

5%

22

402

MF-LF1/16W

R3795

1 2

73 18

18

73 18

1/16W

5%

MF-LF

4.7K

402

R3755

1

2

1/16W

5%

MF-LF

4.7K

402

R3756

1

2

9

1/16W

4.7K

5%

MF-LF

402

R3752

1

2

1/16W

5%

MF-LF

4.7K

402

R3757

1

2

402

MF-LF

1/16W

4.7K

5%

R3750

1

2

402

1/16W

5% MF-LF

4.7K

R3751

1

2

10%

402

X5R

16V

0.1UF

C3715

1

2

10%

402

X5R

0.1UF

16V

C3716

1

2

CRITICAL

0402-LF

FERR-120-OHM-1.5A

L3715

1

2

402

10% X5R

16V

0.1UF

C3711

1

2

10%

402

X5R

16V

0.1UF

C3710

1

2

16V

0.1UF

X5R

10%

402

C3714

1

2

NO STUFF

10PF

50V

CERM

5%

402

C3790

1

2

5% 1/16W

MF-LF

0

402

R3796

1 2

73 18

5% 1/16W

402

MF-LF

0

R3700

1 2

22

5% 1/16W MF-LF 402

R3731

1

2

37

051-8089

Ethernet PHY (RTL8211CL)

02

SYNC_DATE=03/20/2008

SYNC_MASTER=SUMA

109

RTL8211_RSET

RTL8211_CLK125

RTL8211_CLK25M_CKXTAL1 TP_RTL8211_CKXTAL2

RTL8211_PHYRST_L

MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

MIN_LINE_WIDTH=0.6 MM

PP3V3_ENET_PHYAVDD

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PP1V05_ENET_PHYAVDD

VOLTAGE=1.05V

ENET_CLK125M_TXCLK

ENET_RXD_R<3>

ENET_RXD_R<2>

ENET_RESET_L

ENET_MDIO

ENET_TX_CTRL

ENET_MDC

RTL8211_PHYAD1

ENET_CLK125M_RXCLK

ENET_RXD<0> ENET_RXD<1> ENET_RXD<2> ENET_RXD<3>

ENET_MDI_N<0>

ENET_RX_CTRL

ENET_MDI_P<2>

RTL8211_RXDLY

ENET_RXD_R<1>

RTL8211_PHYAD0

=PP1V05_ENET_PHY

ENET_TXD<3>

ENET_TXD<2>

ENET_TXD<1>

=RTL8211_ENSWREG

ENET_TXD<0>

=PP3V3_ENET_PHY_VDDREG

=PP3V3_ENET_PHY

=RTL8211_REGOUT

ENET_RXD_R<0>

ENET_RXCTL_R

ENET_MDI_P<0>

ENET_MDI_P<1> ENET_MDI_N<1>

ENET_CLK125M_RXCLK_R

ENET_MDI_N<2>

ENET_MDI_P<3> ENET_MDI_N<3>

ENET_CLK125M_TXCLK_R

8

9

8

9

73 73

G

DS

IN

OUT

D

SG

IN

D

S G

IN

D

SG

D

SG

D

S

G

D

SG

IN

D

SG

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

1.05V ENET FET

NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.

Pull-up is with power FET.

"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))

WLAN Enable Generation

I(max) = 1.7A (85C)

Rds(on) = 90mOhm max

@ 2.5V Vgs:

3.3V ENET FET

MOBILE:

RTL8211 25MHz Clock

1.8V Vgs

=P1V05ENET_EN. Nets separated on

Recommend aliasing PM_SLP_RMGT_L and

ARB for alternate power options.

Non-ARB:

=P3V3ENET_EN. Nets separated on ARB for alternate power options.

Recommend aliasing PM_SLP_RMGT_L and

Designs must ensure PHY is powered whenever RMGT rails are, or use separate crystal.

NOTE: MCP79 can provide 25MHz clock, but clock runs whenever RMGT rails are powered.

SOT-23-HF

NTR4101P

CRITICAL

Q3810

3

1

2

10%

402

0.01UF

16V

CERM

C3810

12

0.033UF

10%

402

X5R

16V

C3811

1

2

MF-LF

402

100K

5%

1/16W

R3810

1 2

73 18

402

22

MF-LF

5%

1/16W

PLACEMENT_NOTE=Place close to U1400

R3895

1 2

32

1/16W

20.0K

1%

MF-LF

402

R3840

1 2

10%

402

CERM

0.01UF

16V

C3841

1

2

0.1UF

20%

CERM

10V

402

C3840

1

2

31

SSM6N15FEAPE

SOT563

Q3805

3

5

4

42 41 36 21

SSM6N15FEAPE

SOT563

Q3801

6

2

1

31 21

64 41 36 21

SSM6N15FEAPE

SOT563

Q3805

6

2

1

SOT563

SSM6N15FEAPE

Q3841

6

2

1

69.8K

1/16W

1%

402

MF-LF

R3842

1

2

SI2312BDS

SOT23

CRITICAL

Q3840

3

1

2

10K

5%

402

MF-LF

1/16W

R3800

1

2

SOT563

SSM6N15FEAPE

Q3801

3

5

4

9

SSM6N15FEAPE

SOT563

Q3841

3

5

4

9

10K

402

1/16W

1%

MF-LF

R3841

1 2

38

051-8089

Ethernet & AirPort Support

02

SYNC_MASTER=SUMA

SYNC_DATE=04/04/2008

109

=P3V3ENET_EN

AP_PWR_EN

SMC_ADAPTER_EN

AC_OR_S0_L

=P1V05ENET_EN

P3V3ENET_EN_L

MCP_CLK25M_BUF0_R

RTL8211_CLK25M_CKXTAL1

PM_SLP_S3_L

P1V05ENET_EN_L

PM_WLAN_EN_L

=PP3V3_ENET_FET

=PP3V3_S5_P3V3ENETFET

P3V3ENET_SS

P1V05ENET_SS

=PP1V05_ENET_P1V05ENETFET

P1V05ENET_EN_L_RC

=PP1V05_ENET_FET

=PP3V3_S5_P1V05ENETFET

8 8

8

BI

ENET_MDI_TRAN_N_3

ENET_MDI_TRAN_P_3

ENET_MDI_TRAN_N_2

ENET_MDI_TRAN_P_2

ENET_MDI_TRAN_N_1

ENET_MDI_TRAN_P_1

ENET_MDI_TRAN_N_0

ENET_MDI_TRAN_P_0

SYM_VER-1

RX

TX

RX

TX

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

ETHERNET CONNECTOR

514-0523

PLACE ONE CAP EACH NEAR PINS 3 AND 4 OF T3901 AND T3902

- COPY THIS PAGE FROM K36 CSA.39

73 32

F-RT-TH

RJ45-MG3-K36

CRITICAL

OMIT

J3900

2

4

6

8

1

3

5

7

10

9

X5R

16V

10%

0.1UF

402

C3902

1

2

0.1UF

16V 402

10% X5R

C3900

1

2

10% 16V

402

0.1UF

X5R

C3901

1

2

10% X5R

16V 402

0.1UF

C3903

1

2

75

MF-LF1/16W

1%

402

R3900

1 2

1/16W MF-LF1%402

75

R3901

1 2

1/16W

402

MF-LF

75

1%

R3902

1 2

402

1/16W1%MF-LF

75

R3903

1 2

CERM 1206

CRITICAL

10%

1000PF

2KV

C3910

1

2

SM

CRITICAL

TLA-6T213HF

T3902

1

10

11

12

2

3

4

5

6 7

8

9

CRITICAL

SM

TLA-6T213HF

T3901

1

10

11

12

2

3

4

5

6 7

8

9

02

SYNC_MASTER=SUMA

SYNC_DATE=04/04/2008

109

ETHERNET CONNECTOR

051-8089

39

ENET_CENTER_TAP<1>

ENET_MDI_P<3>

ENET_CENTER_TAP<0>

ENET_MDI_N<3>

ENET_MDI_P<1>

ENET_MDI_P<0>

ENET_CENTER_TAP<2>

ENET_MDI_N<1>

MIN_LINE_WIDTH=0.6MM

ENET_BOB_SMITH_CAP

MIN_NECK_WIDTH=0.25MM

ENET_CONN_CTAP

ENET_CENTER_TAP<3>

ENET_MDI_P<2>

ENET_MDI_N<2>

ENET_MDI_TRAN_N<3>

ENET_MDI_TRAN_P<1>

ENET_MDI_TRAN_P<0>

=GND_CHASSIS_RJ45

ENET_MDI_N<0>

ENET_MDI_TRAN_P<3>

ENET_MDI_TRAN_N<0>

ENET_MDI_TRAN_N<1>

ENET_MDI_TRAN_N<2>

ENET_MDI_TRAN_P<2>

9

DS2

ATBUSH ATBUSN

VP25

OCR_CTL_V10

VAUX_DETECT

TMS

TCK

REFCLKN

PCIE_TXD0P

TRST*

ATBUSB

TDI

DS1

TPA0N TPA0P

AVREG

CE

CLKREQN

FW_RESET*

FW620* JASI_EN

MODE_A

NAND_TREE

OCR_CTL_V12

PCIE_RXD0N PCIE_RXD0P PCIE_TXD0N

PERST*

R0

REFCLKP

REGCLT

REXT

SCIFCLK SCIFDAIN SCIFDOUT

SCIFMC

SCL SDA

SE SM

TDO

TPA1N

TPA2N TPA2P TPB0N TPB0P TPB1N TPB1P TPB2N TPB2P

TPBIAS0 TPBIAS1 TPBIAS2

TPCPS

VAUX_DISABLE

VBUF

VDDH

VP

VREG_PWR

WAKE*

XI

XO

DS0

TPA1P

VDD33

VDD10

VREG_VSS

VSS

SERIAL EEPROM

MISCELLANEOUS

CONTROLLER

POWER MANAGEMENT

TEST CONTROLLER

PCI EXPRESS PHY

CHIP RESET

SCIF

1394 PHY

NC NC NC

NC

IN IN

IN

OUT

IN IN IN

BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI

IN

NC NC

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

NT-4 (IPU) NT-3 (IPU)

FIXME!!! - TYPO IN SYMBOL REGCTL

NT-10 (IPD)

NT-12 (IPD)

(IPD) NT-21

(IPD) NT-20

(IPD) NT-19

110 mA Digital Core

114 mA FireWire PHY

NT-15 (IPD)

NT-17

NT-14 (IPD)

NT-16 (IPD)

NT-13

NT-1 (IPU)

25 mA PCIe SerDes

NT-2 (IPU)

(IPU)

NT-7

138 mA

7 mA I/O

17 mA PCIe SerDes

(IPD) NT-11

(IPU) NT-8

(IPD)

0 mA VReg PWR

(OD)

NT-5

NT-OUT

(Reserved)

NT-9 (IPD)

(IPU)

(IPD)

(IPD) NT-18

NAND tree order.

NOTE: NT-xx notes show

135 mA

NT-6

1%

402

MF-LF

191

1/16W

R4170

1

2

CERM-X5R 402

6.3V

0.33UF

10%

C4162

1

2

402

MF-LF

1/16W

5%

470K

R4162

1

2

CRITICAL

OMIT

BGA

FW643E

U4100

B13 A13 A11

A10

L13

L2

F12 E12 E13

D12

K13

D1

J2

K1

J12 J13

N8 N7 N5 N6

N4

B11

N9 N10

D13

L8

G2 G1 H1 F2

N12 M11

M13 N13

M4 N2 M1 M3

B8 A8 B5 A5 B3 A3 B9 A9 B6 A6 B4 A4

B7 C3 A2

B10

N1

E1 D2

H13

A1

B1

M12N3N11

B12

C13E2E10H2H12K2L1

C1

C12F1G12J1L3

L11M2A12D5D6D8L5

L10L6L9

K12

L12

B2

D4

F7

F8

F10

G4G6G7

G8

G10

H4

H6D7H7

H8

H10

J4J5J9

J10

K4K5K7D9K8K9L7

K6

K10

D10

E4E5E9F4F6

C2

G13

F13

CERM

22PF

5%

402

50V

C4151

1 2

22PF

50V

5%

CERM

402

C4150

1 2

390K

5%

1/16W

402

MF-LF

R4160

1

2

390

5%

402

1/16W MF-LF

R4150

1 2

10K

MF-LF

5% 1/16W

402

R4163

1

2

10K

MF-LF

5% 1/16W

402

R4164

1

2

FW643_LDO

5%

1/16W

402

MF-LF

10K

R4165

1

2

PLACEMENT_NOTE=PLACE C4176 CLOSE TO U4100

16V

0.1UF

X5R

10%

402

C4176

1 2

10% 16V

PLACEMENT_NOTE=PLACE C4175 CLOSE TO U4100

0.1UF

402X5R

C4175

1 2

10K

MF-LF

5% 1/16W

402

R4166

1

2

X5R

PLACEMENT_NOTE=Place C4171 close to U1400

0.1UF

10%

402

16V

C4171

1 2

0.1UF

PLACEMENT_NOTE=Place C4170 close to U1400

402X5R

10% 16V

C4170

1 2

402

1UF

CERM

6.3V

10%

C4130

1

2

402

6.3V

1UF

10%

CERM

C4131

1

2

1UF

10% CERM

402

6.3V

C4100

1

2

1UF

10% CERM

402

6.3V

C4101

1

2

CERM

402

6.3V

1UF

10%

C4132

1

2

CERM

10% 402

6.3V

1UF

C4102

1

2

10%

6.3V CERM 402

1UF

C4103

1

2

1UF

10%

CERM

402

6.3V

C4135

1

2

10%

1UF

CERM

402

6.3V

C4136

1

2

10%

6.3V

1UF

CERM 402

C4104

1

2

1UF

10%

6.3V CERM 402

C4110

1

2

402

CERM

6.3V

10%

1UF

C4105

1

2

10%

1UF

CERM 402

6.3V

C4106

1

2

CERM

1UF

10%

402

6.3V

C4120

1

2

1UF

10%

CERM

402

6.3V

C4121

1

2

1UF

10%

CERM

402

6.3V

C4122

1

2

1UF

10%

CERM

402

6.3V

C4123

1

2

10%

1UF

CERM

402

6.3V

C4124

1

2

0.1UF

10V

20%

CERM

402

C4141

1

2

6.3V

10%

1UF

402

CERM

C4111

1

2

10%

1UF

402

CERM

6.3V

C4140

1

2

71 17

19

17

1%

402

MF-LF

2.94K

1/16W

R4161

1

2

37

74 37

37

74 37

37

120-OHM-0.3A-EMI

0402-LF

L4130

1 2

0402-LF

120-OHM-0.3A-EMI

L4135

1 2

26

120-OHM-0.3A-EMI

0402-LF

L4110

1 2

24.576MHZ

SM-3.2X2.5MM

CRITICAL

Y4150

2 4

1 3

FireWire LLC/PHY(FW643E)

SYNC_DATE=08/17/2008SYNC_MASTER=K36B_MLB

02

109

051-8089

41

PP3V3_FW_FWPHY_VP25

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3VVOLTAGE=1.0V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP1V0_FW_FWPHY_AVDD

FW_CLK24P576M_XO

=PPVP_FW_PHY_CPS

PCIE_FW_R2D_N PCIE_FW_R2D_P

PCIE_FW_R2D_C_N

PCIE_FW_D2R_C_N PCIE_FW_D2R_C_P

PCIE_FW_D2R_P

=PP3V3_FW_FWPHY

FW_P0_TPA_N

=FW_PHY_DS1

FW643_VAUX_DETECT

TP_FW643_SCIFDAIN

PCIE_CLK100M_FW_P

TP_FW643_SCIFCLK

TP_FW643_SCIFDOUT TP_FW643_SCIFMC

TP_FW643_SDA

=FW_PHY_DS2

PCIE_CLK100M_FW_N

PCIE_FW_D2R_N

=FW_PHY_DS0

FW_P0_TPA_P

FW_P1_TPA_P

PCIE_FW_R2D_C_P

TP_FW643_OCR10_CTL

FW_RESET_L

FW_P0_TPB_N

FW_P1_TPB_N

FW_P2_TPA_N

FW_P0_TPB_P

FW_P1_TPB_P

TP_FW643_VBUF FW643_PU_RST_L

TP_FW643_SM

TP_FW643_AVREG

TP_FW643_JASI_EN

TP_FW643_CE

TP_FW643_SE

TP_FW643_FW620_L

FW643_SCL

FW_P2_TPA_P

FW_P1_TPA_N

TP_FW643_TDO

TP_FW643_TDI

TP_FW643_TCK

FW_P2_TPB_N FW_P2_TPB_P

FW_P1_TPBIAS

FW643_R0 FW643_TPCPS

TP_FW643_NAND_TREE FW643_REXT FW_CLK24P576M_XO_R FW_CLK24P576M_XI

FW_P2_TPBIAS

FW_P0_TPBIAS

TP_FW643_MODE_A

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

PP3V3_FW_FWPHY_VDDA

=PP3V3_FW_FWPHY

=PP1V0_FW_FWPHY

FW_CLKREQ_L

TP_FW643_VAUX_ENABLE

FW643_REGCTL

FW_PME_L

FW643_TRST_L

TP_FW643_TMS

37

71

8

35 37

8

35 37

8

V-

V+

D

SG

IN

D

SG

D

G S

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

- =PP3V3_FW_LATEVG_ACTIVE

FWLATEVG_3V_REF Hysteresis:

BOM options provided by this page:

(NONE)

- FW_PORT_FAULT_PU

2.81V on late Vg event and port power is off

2.95V when port power is on

is running or on AC.

Enables port power when machine

Page Notes

Power aliases required by this page:

- =PPBUS_S5_FWPWRSW (system supply for bus power)

Signal aliases required by this page:

- =PPVP_FW_SUMNODE (power passthru summation node)

Late-VG Event Detection

FireWire Port Power Switch

2.0M

1/16W

5%

402

MF-LF

R4219

1

2

10V

10%

603

CERM-X5R

0.33UF

C4219

1

2

0.1UF

20% 10V CERM 402

C4210

1

2

200K

1%

MF-LF

402

1/16W

R4210

1 2

SM-HF

LMC7211

U4210

4

3

1

5

2

402

MF-LF

1/16W

5%

10K

R4211

1

2

402

CERM

5%

50V

100pF

C4211

1

2

10K

MF-LF

1/16W

1%

402

R4212

1

2

80.6K

MF-LF 402

1% 1/16W

R4213

1

2

MBR0540XXH

SOD-123

D4219

12

SOI-HF

NDS9407

CRITICAL

Q4260

5

6

7

8

4

1

2

3

20%

CERM

16V 402

0.01uF

C4260

1

2

5%

402

MF-LF

1/16W

470K

R4260

1

2

SSM6N15FEAPE

SOT563

Q4261

3

5

4

402

1/16W MF-LF

5%

330K

R4261

1

2

42 41 33 21

64 41 33 21

CRITICAL

1.5A-24V

1812L15024HF

F4260

1 2

PWRDI5

PDS540XF

CRITICAL

D4260

1

2

3

SOT563

SSM6N15FEAPE

Q4261

6

2

1

SSM3K15FV

SOD-VESM-HF

Q4262

3

1

2

109

02

SYNC_MASTER=K36B_MLB SYNC_DATE=08/17/2008

FireWire Port Power

051-8089

42

PPBUS_FW_FWPWRSW_F

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm VOLTAGE=12.6V VOLTAGE=12.6V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

PPBUS_FW_FWPWRSW_D

FWPWR_EN_L

PM_SLP_S3_L

FW_PORTPWR_EN_FET

FW_PORTPWR_EN

=PP3V3_FW_LATEVG PP2V4_FW_LATEVG

=PPBUS_S5_FWPWRSW

FWPWR_EN_L_DIV

FW_PORTPWR_EN

SMC_ADAPTER_EN

FWLATEGV_3V_REF

LATEVG_EVENT_L

P2V4_FWLATEVG_RC

=PPBUS_S5_FW_FET

36

8

37

8

36

8

TPA+

TPA-

TPB-

TPB+

GROUND

POWER

OUT

G

S

(SYM-VER1)

D

SGD

(SYM-VER2)

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Configures PHY for:

Termination

Place close to FireWire PHY

(Common to all ports)

for snap-back diodes

ESD and late-VG rail

Late-VG Protection Power

to at least 2.1V for FW signal integrity and should be biased to 2.4V for margin R4390 should be 390 Ohms max for a 3.3V rail

NOTE: FireWire TPA/TPB pairs are NOT

FireWire TPA/TPB pairs to their

(NONE)

PP2V4_FWLATEVG needs to be biased

(NONE)

BOM options provided by this page:

NOTE: This page is expected to contain the necessary aliases to map the

appropriate connectors and/or to properly terminate unused signals.

constrained on this page. It is assumed that FireWire PHY page will provide the appropriate constraints to apply to entire TPA/TPB XNets.

1394b implementation based on Apple FireWire Design Guide (FWDG 0.6, 5/14/03)

Cable Power

Page Notes

Power aliases required by this page:

- =PPVP_FW_PORT1

- =PP3V3_FW_LATEVG

- =GND_CHASSIS_FW_PORT1

- =GND_CHASSIS_FW_EMI_R Signal aliases required by this page:

"Snapback" & "Late VG" Protection

NOTE: TRACE PPVP_FW_PORT1 MUST HANDLE UP TO 1A

PORT 1

FireWire PHY Config Straps

- 1-port Portable Power Class (0)

1/16W

1%

402

MF-LF

56.2

R4363

1

2

4.99K

1%

1/16W

402

MF-LF

R4364

1

2

56.2

1% 1/16W

402

MF-LF

R4362

1

2

25V

5%

402

CERM

220pF

C4364

1

2

402

1%

56.2

1/16W MF-LF

R4361

1

2

CERM-X5R 402

10%

6.3V

0.33UF

C4360

1

2

56.2

1% 1/16W

402

MF-LF

R4360

1

2

X7R

50V

10%

0.01UF

402

C4314

1

2

CRITICAL

SM

FERR-250-OHM

L4310

1 2

X7R

0.01uF

10% 50V

402

C4310

1

2

BAV99DW-X-G

SOT-363

DP4310

1

2

6

10% 50V

402

X7R

0.01uF

C4311

1

2

SOT-363

BAV99DW-X-G

DP4310

4

5

3

BAV99DW-X-G

SOT-363

DP4311

1

2

6

BAV99DW-X-G

SOT-363

DP4311

4

5

3

50V

10%

402

X7R

0.01uF

C4313

1

2

0.01uF

50V

10%

402

X7R

C4312

1

2

1/16W

1%

402

MF-LF

332

R4390

1 2

SOT23

CRITICAL

MMBZ5227BLT1H

D4390

1

3

MF-LF

402

1/16W

10K

1%

R4381

1

2

MF-LF

402

10K

1%

1/16W

R4382

1

2

10K

1/16W

1%

402

MF-LF

R4380

1

2

CRITICAL

1394A-MG3-K36

F-RT-TH

J4300

2

7 8

1

5

6

3

4

SM

TCM2010-100-4P

CRITICAL

FL4320

1

2

3

4

5

6

7

8

50V X7R 402

0.01uF

10%

C4316

1

2

BSS8402DW

SOT-363

Q4300

6

2

1

SOT-363

BSS8402DW

Q4300

3

5

4

5%

MF-LF

1/16W

402

330K

R4312

1

2

402

1/16W MF-LF

470K

5%

R4311

1

2

43

051-8089

FireWire Ports

SYNC_MASTER=K36B_MLB

SYNC_DATE=(MASTER)

109

02

MAKE_BASE=TRUE

NC_FW2_TPBP

MAKE_BASE=TRUE

NC_FW2_TPBN

MAKE_BASE=TRUE

NC_FW0_TPBP

MAKE_BASE=TRUE

NC_FW0_TPBN

MAKE_BASE=TRUE

NC_FW2_TPAP

MAKE_BASE=TRUE

NC_FW2_TPAN

MAKE_BASE=TRUE

NC_FW0_TPAP

MAKE_BASE=TRUE

NC_FW0_TPAN

MAKE_BASE=TRUE

NC_FW2_TPBIAS

MAKE_BASE=TRUE

NC_FW0_TPBIAS

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

PPVP_FW_PORT1_F

VOLTAGE=33V

MAKE_BASE=TRUE

FWPHY_DS1

MAKE_BASE=TRUE

FW_PORT1_TPA_N

MAKE_BASE=TRUE

FW_PORT1_TPA_P

MAKE_BASE=TRUE

FW_PORT1_TPB_P

MAKE_BASE=TRUE

FW_PORT1_TPB_N

PP2V4_FW_LATEVG

VOLTAGE=2.4V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

MAKE_BASE=TRUE

FWPHY_DS2

FWPHY_DS0

MAKE_BASE=TRUE

PPVP_FW_CPS

=PP3V3_FW_PHY

=GND_CHASSIS_FW_UPPER

FW_PORT_A_P

FW_PORT_B_N

FW_PORT1_TPA_P FW_PORT1_TPA_N

PP2V4_FW_LATEVG

FW_PORT1_TPB_N

FW_PORT1_TPB_P

FW_P0_TPBIAS FW_P2_TPBIAS

FW_P0_TPA_P

=PPVP_FW_PHY_CPS_FET

FW_P2_TPB_P

FW_P0_TPB_P

=FW_PHY_DS0

=FW_PHY_DS1

FW_PORT1_TPB_C

FW_P1_TPB_N

FW_P2_TPB_N

FW_P1_TPB_P

=FW_PHY_DS2

=PP3V3_FW_LATEVG

FW_P1_TPA_P FW_P1_TPA_N

CPS_EN_L

FW_P0_TPB_N

=PP3V3_FW_FWPHY

FW_P1_TPBIAS

FW_P2_TPA_P

FW_P2_TPA_N

FW_P0_TPA_N

CPS_EN_L_DIV

=PPVP_FW_PHY_CPS

=PPVP_FW_PORT1

=GND_CHASSIS_FW_DOWN

FW_PORT_B_P

FW_PORT_A_N

37

36 37

8

9

74

37

36 37

37

35

35 74

35

35 74

35

35 74

35

35 74

35

8

36

35 74

8

35

35 74

35

8

9

74

OUT

IN

D

SG

D

SG

SGD

SYM_VER-1

OUT

IN

SYM_VER-1

OUT

SYM_VER-1

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

518S0390

SATA ODD Port

ODD Power Control

SATA CONNECTOR

NC

SYSTEM (SLEEP) LED FILTER

PLACE R4550 AND C4550 NEAR J4501

(TO IR RECEIVER)

NC

PLACE R4522 AND C4522 NEAR J4501

NC

ensure the drive is unpowered in S3/S5.

NOTE: 3.3V must be S0 if 5V is S3 or S5 to

VALUE=3900PF IN REFERENCE SCHEM

516S0719

Indicates disc presence

PLACE L4501 NEAR J4501

FROM SB WITHIN EACH PAIR

CAPS TO BE SAME DISTANCE

41

7

33K

5% 1/16W MF-LF

402

R4590

1

2

21

SOT563

SSM6N15FEAPE

Q4596

3

5

4

MF-LF

402

5%

10K

1/16W

R4597

1

2

402

10K

5% 1/16W MF-LF

R4596

1

2

5%

1/16W

402

MF-LF

100K

R4595

1 2

10%

402

CERM

0.068UF

10V

C4595

1

2

16V

10%

CERM

402

0.01UF

C4596

1 2

SOT563

SSM6N15FEAPE

Q4596

6

2

1

SOT-6

FDC606P_G

CRITICAL

Q4590

1 2 5 6

3

4

20247-019E

F-ST-SM

CRITICAL

J4501

20

21

1

10 11 12 13 14 15 16 17 18 19

2 3 4 5 6 7 8 9

4.7UF

6.3V 603

CERM

20%

C4550

1

2

5%

1/16W

402

MF-LF

100

R4550

1 2

CERM 402

16V

10%

0.01UF

C4522

1

2

NO STUFF

0.1UF

16V

10% X5R

402

C4590

1

2

20% 603

X5R

10UF

6.3V

NO STUFF

C4591

1

2

10

1/16W MF-LF

5%

402

R4522

1 2

CRITICAL

90-OHM-100MA

DLP11S

L4501

1 2

34

402

0.01UF

C4500

1

2

0.01UF

402

C4502

1

2

0.01UF 402

C4503

1

2

0.01UF 402

C4501

1

2

40

7

71 20

40210%

0.01UF

16V

CERM

PLACEMENT_NOTE=Place C4526 close to J4500

C4526

1 2

0.01UF

CERM

10% 40216V

PLACEMENT_NOTE=Place C4525 next to C4526

C4525

1 2

CRITICAL

90-OHM-100MA

DLP11S

PLACEMENT_NOTE=PLACE FL4525 CLOSE TO J4500

FL4525

1 2

34

71 20

CRITICAL

PLACEMENT_NOTE=Place FL4520 close to J4500

90-OHM-100MA

DLP11S

FL4520

12

3 4

71 20

16V10%

0.01UF

402

PLACEMENT_NOTE=Place C4520 close to MCP79

CERM

C4520

1 2

0.01UF

10% 16V

CERM

PLACEMENT_NOTE=Place C4521 next to C4520

402

C4521

1 2

71 20

0603

FERR-70-OHM-4A

L4590

1 2

M-ST-SM

2-1775184-0

CRITICAL

J4500

109

02

SYNC_DATE=08/17/2008SYNC_MASTER=K36B_MLB

SATA Connectors

051-8089

45

SATA_ODD_R2D_C_P

SATA_ODD_R2D_C_N

SATA_ODD_R2D_UF_N

SATA_ODD_R2D_UF_P

PP5V_SW_ODD

MIN_LINE_WIDTH=0.6mm VOLTAGE=5V

MIN_NECK_WIDTH=0.4mm

SATA_ODD_D2R_UF_P

SATA_ODD_D2R_UF_N

SATA_ODD_D2R_N

SATA_ODD_D2R_P

SATA_ODD_D2R_C_P

SATA_ODD_R2D_P

SATA_ODD_R2D_N

SATA_ODD_D2R_C_N

SATA_HDD_R2D_C_P

SATA_HDD_R2D_UF_P

SATA_HDD_D2R_N

SATA_HDD_D2R_C_N SATA_HDD_D2R_C_P

SMC_ODD_DETECT

SATA_HDD_R2D_N

SATA_HDD_R2D_UF_N

SATA_HDD_R2D_P

SATA_HDD_D2R_P

SATA_HDD_R2D_C_N

ODD_PWR_EN_L

PP5V_S0_HDD_FLT

=PP5V_S0_HDD

SYS_LED_ANODE_L

=PP5V_S0_ODD

ODD_PWR_EN

=PP3V3_S0_ODD

SYS_LED_ANODE

=PP5V_S3_IR

PP5V_S3_IR_CONN

IR_RX_OUT

ODD_PWR_SS

ODD_PWR_EN_LS5V_L

=PP3V3_S0_ODD

71

7

71

7

71

7

71

7

71

7

71

7

8

7

8

38

42

8

40

7

8

38

OUT

BI

IN OUT

IN

OUT2

TPAD

GND

OUT1

OC1*

EN2

EN1 OC2*

IN

BI

OUT

IOIONC

GND

VBUS

NC

IOIONC

GND

VBUS

NC

VCC

GND

SELOE*

D+ D-

Y+ Y-

M+ M-

GND

D+

D-

VBUS

GND

D+

D-

VBUS

IN

SYM_VER-1

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

514-0527

SEL=0 Choose SMC SEL=1 Choose USB

Place L4600 and L4605 at connector pin

Port Power Switch

Left USB Port B

Left USB Port A

USB/SMC Debug Mux

514-0527

We can add protection to 5V if we want, but leaving NC for now

CRITICAL

PLACEMENT_NOTE=NEAR J4600

0603

FERR-220-OHM-2.5A

L4605

1 2

CASE-B2-SM

POLY-TANT

20%

6.3V

100UF

CRITICAL

C4696

1

2

6.3V

20%

10UF

X5R 603

C4695

1

2

CERM 402

10V

20%

0.1UF

C4691

1

2

20

72 20

10V

CERM

SMC_DEBUG_YES

0.1UF

20%

402

C4650

1

2

SMC_DEBUG_YES

1/16W

5%

402

MF-LF

10K

R4650

1

2

43 42 41

7

43 42 41

7

41

402

5%

0

MF-LF

1/16W

SMC_DEBUG_NO

R4651

1 2

MF-LF

1/16W

402

0

SMC_DEBUG_NO

5%

R4652

1 2

CERM

16V

20%

0.01uF

402

C4605

1

2

MSOP

TPS2064DGN

CRITICAL

U4690

3

4

1

2

8

5

7

6

9

0.01uF

20% 16V CERM 402

C4615

1

2

CRITICAL

0603

FERR-220-OHM-2.5A

PLACEMENT_NOTE=NEAR J4601

L4615

1 2

X5R 603

6.3V

10UF

20%

C4617

1

2

POLY-TANT

20%

100UF

6.3V CASE-B2-SM

CRITICAL

C4616

1

2

72 20

20

RCLAMP0502N

CRITICAL

SLP1210N6

D4600

1

5 42 3

6

SLP1210N6

CRITICAL

RCLAMP0502N

D4610

1

5 42 3

6

10UF

603

X5R

6.3V

20%

C4690

1

2

TQFN

CRITICAL

PI3USB102ZLE

SMC_DEBUG_YES

U4650

6

7

3

4

5

8

10

9

2

1

USB-K36-MG3

CRITICAL

F-RT-TH

OMIT

J4600

5

6

1 2 3 4

USB-K36-MG3

CRITICAL

F-RT-TH

OMIT

J4601

5

6

1 2 3 4

=USB_PWR_EN

64

DLP0NS

90-OHM

CRITICAL

L4610

1 2

34

CRITICAL

90-OHM DLP0NS

L4600

1 2

34

109

02

SYNC_DATE=08/17/2008SYNC_MASTER=K36B_MLB

External USB Connectors

051-8089

46

USB_EXTB_P

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.5 mm VOLTAGE=5V

PP5V_S3_RTUSB_B_F

USB2_EXTB_F_P

USB2_EXTB_F_N

USB_EXTB_N

USB2_EXTA_F_P

USB2_EXTA_F_N

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=5V

PP5V_S3_RTUSB_A_ILIM

MIN_NECK_WIDTH=0.5 mm

=PP3V42_G3H_SMCUSBMUX

=PP5V_S3_EXTUSB

SMC_RX_L SMC_TX_L

USB_EXTA_N

USB_EXTA_P

USB_DEBUGPRT_EN_L

USB_EXTB_OC_L

USB_EXTA_OC_L

USB2_EXTA_MUXED_P

VOLTAGE=5V

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.5 mm

PP5V_S3_RTUSB_B_ILIM

USB2_EXTA_MUXED_N

PP5V_S3_RTUSB_A_F

VOLTAGE=5V

MIN_NECK_WIDTH=0.5 mm

MIN_LINE_WIDTH=0.5 mm

72

8

72

BI BI

IN

SYM_VER-1

P0_3/INT1 P0_4/INT2 P0_5/TIO0 P0_6/TIO1

P0_7

P0_2/INT0

P0_1

THRM_PAD

NC

P1_7

P1_6/MISO

P1_5/SMOSI

P1_4/SCLK

P3_1

P3_0

P1_3/SSEL

P1_2/VREG

VDD

P1_1/D-

P1_0/D+

VSS

NC

P2_1

P2_0

P0_0

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

IR CTRL

PLACE L4800 NEAR J4810

PLACE L4811 NEAR J4810

518S0521

PLACE L4810 NEAR J4800

BLUETOOTH

PLACE C4810 C4811 NEAR L4810

TO M13D SLOT

SB HAS INTERNAL 15K PULL-DOWNS

X7R-CERM 402

0.1UF

16V

10%

C4801

1

2

CERM

0.001UF

50V

402

10%

C4804

1

2

MF-LF

5%

100

1/16W

402

R4800

1 2

72 20

38

7

603

10UF

6.3V

20% X5R

C4810

1

2

0.1UF

CERM

10V

20%

402

C4811

1

2

78171-0004

M-RT-SM

CRITICAL

J4810

5

6

1 2 3 4

120-OHM-0.3A-EMI

0402-LF

L4811

1 2

120-OHM-0.3A-EMI

0402-LF

L4810

1 2

90-OHM DLP0NS

CRITICAL

L4812

1 2

34

X5R

10V

10%

1UF

402-1

C4803

1

2

OMIT

CY7C63833

QFN

CRITICAL

U4800

10

11 12

17

19

27

28 29

30

31

7

6

5 4

3

2 1

32

14

15

18 20

23

24 25

26

9

8

21

22

331613

48

051-8089

Front Flex Support

SYNC_MASTER=K36B_MLB SYNC_DATE=07/17/2008

02

109

USB_IR_N DIFFERENTIAL_PAIR=USB2_IR NET_PHYSICAL_TYPE=USB_90D NET_SPACING_TYPE=USB

IR_VREF_FILTER

NET_PHYSICAL_TYPE=USB_90D

DIFFERENTIAL_PAIR=USB2_IR

NET_SPACING_TYPE=USB

USB_IR_P

USB2_BT_F_P_CONN

=USB2_BT_P

USB2_BT_F_N_CONN

=USB2_BT_N

GND_BT_F_CONN

IR_RX_OUT

IR_RX_OUT_RC

=PP5V_S3_IR

=PP3V3_S3_BT

PP3V3_S3_BT_F_CONN

CYPRESS ’ENCORE II’ USB CONTROLLER

P/N 338S0375

7

72

9

7

72

9

7

8

38

8

7

IN

OUT

IN

OUT

IN IN IN IN IN IN IN IN

IN

OUT

IN

OUT

BI

IN

OUT

BI OUT

OUT

IN

OUT

IN

OUT OUT OUT OUT

IN

IN IN

IN

IN IN

IN

OUT

IN

BI BI BI BI BI BI

OUT OUT

OUT

IN

OUT

IN

BI

OUT

IN

OUT

P13 P14 P15 P16 P66

P10 P11 P12

P17

P20 P21 P22 P23 P24 P25 P26 P27

P30 P31 P32 P33 P34

P36 P37

P40 P41 P42 P43 P44 P45 P46 P47

P50 P51 P52

P60 P61 P62 P63 P64 P65

P67

P70 P71 P72 P73 P74 P75 P76 P77

P80 P81

P84 P85 P86

P90 P91 P92 P93 P94 P95 P96 P97

P35

P83

P82

(1 OF 3)

PA5

PA4

PA0 PA1 PA2 PA3

PA6 PA7

PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7

PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7

PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7

PE0 PE1 PE2 PE3 PE4 PF0

PF1 PF2 PF3 PF4 PF5 PF6 PF7

PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7

PH0 PH1 PH2 PH3 PH4 PH5

(2 OF 3)

RES*

NMI

VSS

VCLVCC

NC

MD2

MD1

ETRST

AVSS

AVREF

AVCC

EXTAL

XTAL

(3 OF 3)

NC

OUT

NC

NC NC NC

NC

NC NC

NC NC NC

NC

NC NC

NC

NC NC

IN

OUT

BI BI BI BI

IN IN IN

OUT

BI

IN IN IN IN

BI

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

(OC) (OC)

(OC) (OC) (OC) (OC) (OC) (OC)

NOTE: Unused pins have "SMC_Pxx" names. Unused

(OC)

(DEBUG_SW_2)

(DEBUG_SW_1)

(OC)

those designated as inputs require pull-ups.

(OC)

If SMS interrupt is not used, pull up to SMC rail.

NOTE: SMS Interrupt can be active high or low, rename net accordingly.

NOTE: P94 and P95 are shorted, P95 could be spare.

(OC)

pins designed as outputs can be left floating,

6.3V CERM

22UF

20%

805

C4902

1

2

43 19

7

43 42

7

49 42

6.3V

402

10%

PLACEMENT_NOTE=Place C4907 close to U4900 pin F1

CERM-X5R

0.47UF

C4907

1

2

20%

402

CERM

10V

0.1UF

C4903

1

2

402

20%

PLACEMENT_NOTE=PLACE C4920 CLOSE TO U4900 PINS M12

10V

0.1UF

CERM

C4920

1

2

4.7

402

1/16W

5%

MF-LF

PLACEMENT_NOTE=PLACE R4999 CLOSE TO U4900 PINS M12

R4999

1 2

20%

402

CERM

10V

0.1UF

C4904

1

2

SM

XW4900

12

21

60

20% CERM

0.1UF

10V 402

C4905

1

2

21

64

64 26

7

42

20%

0.1UF

10V 402

CERM

C4906

1

2

46

45

42

46

45

46

42

56 42

57 56 42

43 42 41 39

7

43 42 41 39

7

64

44

10K

5%

402

MF-LF

1/16W

R4909

1

2

43

7

43

7

402

MF-LF

10K

5% 1/16W

R4901

1

2

1/16W

5%

MF-LF 402

10K

R4902

1

2

1/16W

5%

MF-LF

0

402

NO STUFF

R4903

1

2

10K

MF-LF

5% 1/16W

402

R4998

1

2

39

56 42

21

42

38

7

42

21

42

48

42

48

50

46

50

42

46

43 42

7

42

43 42

7

43 42

7

43 42

7

56 49 42

44

42

43 42 41 39

7

43 42 41 39

7

42

43 19

7

29 28 21

26

43

7

21

43 19

7

LGA-HF

OMIT

H8S2117

U4900

OMIT

LGA-HF

H8S2117

U4900

H8S2117

OMIT

LGA-HF

U4900

42

50

42 36 33 21

42

9

72 43 19

7

72 43 19

7

72 43 19

7

72 43 19

7

72 43 19

7

26

72 26

42

44

64 36 33 21

64 42 21

42

72 26

44

42

49

051-8089

SMC

109

SYNC_DATE=08/17/2008

02

SYNC_MASTER=K36B_MLB

ESTARLDO_EN

LPC_AD<0> LPC_AD<1>

LPC_AD<3> LPC_FRAME_L

LPC_CLK33M_SMC

PM_CLKRUN_L LPC_PWRDWN_L

SMC_LRESET_L

PM_CLK32K_SUSCLK

PM_SLP_S5_L

PM_SLP_S4_L

PM_SLP_S3_L

SMC_BS_ALRT_L

SMC_BC_ACOK

SMC_ONOFF_L

SMB_MGMT_CLK

SMC_RX_L

SMC_TX_L

SMC_WAKE_SCI_L

SMC_NB_MISC_ISENSE

SMC_BATT_ISENSE

SMC_PBUS_VSENSE

SMC_DCIN_ISENSE

SMC_GPU_VSENSE

SMC_CPU_VSENSE

SMC_CPU_ISENSE

SMC_BIL_BUTTON_L

SMC_ADAPTER_EN

SMB_0_S0_CLK

SMC_RX_L

SMC_TX_L

SMC_SYS_KBDLED

SMC_GFX_THROTTLE_L

SMS_ONOFF_L

SMB_MGMT_DATA

SMC_P41

LPC_SERIRQ

LPC_AD<2>

SMC_P26

SMC_P24

PM_PWRBTN_L

ALL_SYS_PWRGD

SMC_RSTGATE_L

SMC_EXCARD_PWR_EN

SMC_PROCHOT_3_3_L

IMVP_VR_ON

PM_RSMRST_L

RSMRST_PWRGD

SMB_0_S0_DATA

SMC_CASE_OPEN SMC_TCK SMC_TDI SMC_TDO SMC_TMS

SMC_MCP_SAFE_MODE

SMB_BSA_CLK SMB_A_S3_DATA SMB_A_S3_CLK SMB_B_S0_DATA SMB_B_S0_CLK

SMC_FWE ALS_GAIN

SMC_THRMTRIP

SMC_PROCHOT

SMB_BSA_DATA

=SMC_SMS_INT

SMC_LID

SMC_SYS_LED

ALS_RIGHT

ALS_LEFT

SMC_MCP_DDR_ISENSE

SMC_MCP_CORE_ISENSE

SMC_ANALOG_ID

SMS_Z_AXIS

SMS_Y_AXIS

SMS_X_AXIS

SMC_FAN_3_TACH

SMC_FAN_2_TACH

SMC_FAN_1_TACH

SMC_FAN_0_TACH

SMC_FAN_3_CTL

SMC_FAN_2_CTL

SMC_FAN_1_CTL

SMC_FAN_0_CTL

SMC_GFX_OVERTEMP_L

SMC_EXCARD_OC_L

SMC_EXCARD_CP

SMC_PB3

SMC_ODD_DETECT

SMC_RUNTIME_SCI_L

PM_BATLOW_L

SYS_ONEWIRE

USB_DEBUGPRT_EN_L

PM_SYSRST_L

SMC_PA1

SMC_PA0

MEM_EVENT_L

SMC_PA5

SMC_XTAL SMC_EXTAL

VOLTAGE=3.3V

PP3V3_S5_SMC_AVCC

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.25 MM

SMC_TRST_L

SMC_MD1

SMC_KBC_MDE

SMC_VCL

SMC_NMI

SMC_RESET_L

SMC_GPU_ISENSE

SMC_PM_G2_EN

GND_SMC_AVSS

=PP3V3_S5_SMC

PP3V3_S5_AVREF_SMC

42

42 45 46

8

42 50

42

D

S G

OUT

IN

OUT

BI

OUT

IN

D

S G

GND

OUT

IN

OUT

IN

D

G S

OUT

CD

GND

NC

OUT

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

PLACE R5016,R5002 ON TOP SIDE

SMC Reset "Button" / Brownout Detect

NC

PLACE R5016,R5002 ON TOP SIDE

PLACE R5015,R5001 ON BOTTOM SIDE

SMC Crystal Circuit

NEED TO TUNE VALUE FOR POWER SAVING

TO CPU

TO SMC

SMC FSB to 3.3V Level Shifting

ADD NC ALIASES FOR FAN1 SIGNALS

Debug Power "Button"

SMC AVREF Supply

System (Sleep) LED Circuit

0.1uF

20% 10V

CERM

402

C5000

1

2

SSM6N15FEAPE

SOT563

Q5059

3

5

4

6.3V

10%

402

0.47UF

CERM-X5R

C5020

1

2

16V

0.01UF

10%

402

CERM

C5026

1

2

603

X5R

20%

6.3V

10uF

C5025

1

2

5%

MF-LF

1/16W

0

402

R5095

1 2

402

MF-LF

5%

1/16W

10K

R5070

1 2

402

1/16W5%MF-LF

100K

R5071

1 2

402

1/16W MF-LF

5%

10K

R5072

1 2

MF-LF

5%

1/16W

402

10K

R5073

1 2

5%

MF-LF1/16W

402

100K

R5074

1 2

2.0K

MF-LF

5%

1/16W

402

ONEWIRE_PU

R5075

1 2

MF-LF

5%

1/16W

100K

402

R5076

1 2

MF-LF

5%

1/16W

10K

402

R5077

1 2

10K

1/16W5%MF-LF

402

R5078

1 2

MF-LF

10K

5%

1/16W

402

R5079

1 2

1/16W

10K

5%

402

MF-LF

R5080

1 2

5%

10K

402

MF-LF1/16W

R5085

1 2

10K

5%

402

MF-LF1/16W

R5086

1 2

10K

1/16W

5%

402

MF-LF

R5088

1 2

5%

1/16W

22K

MF-LF

402

R5090

1 2

43 41

7

41

69 14 10

0

SILK_PART=SMC_RST

NO STUFF

603

MF-LF

1/10W

5%

R5001

1

2

SILK_PART=PWR_BTN

603

0

MF-LF

5% 1/10W

NO STUFF

R5015

1

2

SOT563-HF

BC847BV-X-F

Q5060

2

6

1

MF-LF

1/16W

5%

402

3.3K

R5061

1

2

1/16W

402

3.3K

5%

MF-LF

R5062

1 2

470

402

MF-LF

1/16W

5%

R5060

1

2

69 60 14 10

41

SSM6N15FEAPE

SOT563

Q5059

6

2

1

402

100K

1/16W5%MF-LF

R5091

1 2

100K

MF-LF

5%

1/16W

402

R5092

1 2

CRITICAL

REF3333

SOT23-3

VR5020

3

1 2

41 20

402

1/16W

5%

1K

MF-LF

R5000

1

2

10K

402

1/16W MF-LF

5%

R5089

1 2

41

SOD-VESM-HF

SSM3K15FV

Q5032

3

1

2

9.09K

1%

1/16W

402

MF-LF

R5032

1

2

402

5% MF-LF

100

1/16W

R5030

1

2

1%

402

MF-LF

1/16W

2.37K

R5031

1

2

SOD

2SA2154MFV-YAE

Q5030

1

3

2

38

10K

1/16W MF-LF

402

5%

R5081

1 2

MF-LF

603

5%

1/10W

0

R5010

1 2

20.00MHZ

5X3.2-SM

CRITICAL

Y5010

1

2

402

50V

15pF

5%

CERM

C5011

1 2

402

15pF

5%

CERM

50V

C5010

1 2

SOT563-HF

BC847BV-X-F

Q5060

5

3

4

5%

1/16W

402

MF-LF

470K

R5087

1 2

603

MF-LF

0

1/10W

5%

SILK_PART=PWR_BTN

NO STUFF

R5016

1

2

MF-LF 603

1/10W

5%

0

SILK_PART=SMC_RST

NO STUFF

R5002

1

2

10K

402

5%

MF-LF

1/16W

R5054

1 2

402

5%

MF-LF

1/16W

10K

R5055

1 2

SOT23-5-HF

NCP303LSN

CRITICAL

U5000

5

3

2

4

1

49 42 41

10% 16V

CERM

0.01UF

402

C5001

1

2

SYNC_MASTER=K36B_MLB

02

SYNC_DATE=08/17/2008

109

SMC Support

051-8089

50

=PPVIN_S5_SMCVREF

SMS_INT_L

MAKE_BASE=TRUE

=SMC_SMS_INT

SMC_PB3

SMC_P24

SMC_P26

SMC_P41

SMC_RSTGATE_L

SMC_EXCARD_PWR_EN

ALS_RIGHT

ESTARLDO_EN

SMC_ANALOG_ID

SMC_SYS_KBDLED

NC_ALS_RIGHT

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SMC_SYS_KBDLED

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SMC_FAN_3_CTL

TP_SMC_EXCARD_PWR_EN

MAKE_BASE=TRUE

TP_SMC_RSTGATE_L

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SMC_FAN_1_TACH

NC_ESTARLDO_EN

NO_TEST=TRUE

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

PP3V3_S5_AVREF_SMC

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 mm

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

GND_SMC_AVSS

VOLTAGE=0V

NC_SMC_ANALOG_ID

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_SMC_P41

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SMC_FAN_2_TACH

NC_SMC_FAN_2_CTL

MAKE_BASE=TRUE

NO_TEST=TRUE

TP_SMC_P24

MAKE_BASE=TRUE

NC_SMC_PB3

MAKE_BASE=TRUE

NC_SMC_FAN_3_TACH

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_SMC_GFX_OVERTEMP_L

MAKE_BASE=TRUE

SMC_IG_THROTTLE_L

MAKE_BASE=TRUE

NC_ALS_GAIN

SMC_BC_ACOK

MAKE_BASE=TRUE

SMC_BMON_MUX_SEL

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SMC_FAN_1_CTL

SMC_FAN_3_CTL

SMC_FAN_3_TACH

SMC_GFX_OVERTEMP_L

=PP3V3_S5_SMC

SMC_RESET_L

SMC_MANUAL_RST_L

SMC_ONOFF_L

SMC_XTAL_R

SMC_XTAL

SMC_CPU_FSB_ISENSE

ALS_LEFT

SMC_MCP_VSENSE

SMC_GPU_VSENSE

=CHGR_ACOK

SMC_FAN_1_TACH

SMC_FAN_1_CTL

SMC_FAN_2_CTL

SMC_FAN_2_TACH

SMC_PA5

CPU_PROCHOT_L

SYS_LED_ANODE

SYS_LED_L_VDIV

SYS_LED_ILIM

SMC_FWE

CPU_PROCHOT_BUF

SMC_PROCHOT_3_3_L

CPU_PROCHOT_L_R

SMC_THRMTRIP

PM_THRMTRIP_L

SMC_RX_L

SMC_TX_L

SMC_SYS_LED

SYS_LED_L

SMC_BS_ALRT_L

=PP5V_S3_SYSLED

PM_SLP_S4_L

=PP3V3_S0_SMC

=PP1V05_S0_SMC_LS

SMC_PA1

SMC_EXTAL

SMC_PROCHOT

SMC_LID

SMC_TMS SMC_TDO

SMC_BC_ACOK

PM_SLP_S5_L

SMC_TCK

=PP3V3_S0_SMC

SMC_EXCARD_CP

SMC_CASE_OPEN

SMC_ADAPTER_EN

SMC_GPU_ISENSE

SMC_NB_MISC_ISENSE

SMC_BIL_BUTTON_L

SMC_TDI

=PP3V3_S5_SMC

SMC_EXCARD_OC_L

EXCARD_OC_L

SYS_ONEWIRE

SMC_ONOFF_L

SMC_PA0

ALS_GAIN

SMC_GFX_THROTTLE_L

8

50 41

41

41 45 46

21

41 42 56 57

46

41

8

41 42 50

41

46 41

45 41

41

7

39 41 43

7

39 41 43

41 56

8

21 41 64

8

42

8

41

41 49 56

7

41 43

7

41 43

41 42 56 57

41

7

41 43

8

42

41

21 33 36 41

41

7

41 43

8

41 42 50

41 56

41 42 49

41

BI

IN

OUT

OUT IN

IN

OUT

OUT IN

BI

IN

BI

OUT

IN

BI

IN

OUT

BI

IN

VCC

GND

SEL OE*

D+ D-

Y+ Y-

M+ M-

VCC

GND

SEL OE*

D+ D-

Y+ Y-

M+ M-

IN

OUT

IN

OUT

OUT OUT

OUT

IN

OUT

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

SPI Bus Series Resistance Option

LPC+SPI Connector

516S0573

Alternate SPI ROM Support

10V

0.1UF

20%

402

CERM

C5144

1

2

21

42 41 39

7

41

7

42 41

7

41

7

26

7

42 41

7

41 19

7

43

7

72 41 19

7

72 41 19

7

72 41 19

7

CRITICAL

55909-0374

LPCPLUS

M-ST-SM

J5100

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

30

31

32

33

34

4

5

6

7

8

9

18

7

42 41 39

7

41

7

42 41

7

42 41

7

42 41

7

41 19

7

41 19

7

43

7

43

7

43

7

72 41 19

7

72 41 19

7

72 26

7

LPCPLUS

TQFN

PI3USB102ZLE

U5110

6

7

3

4

5

8

10

9

2

1

LPCPLUS

TQFN

PI3USB102ZLE

U5120

6

7

3

4

5

8

10

9

2

1

0.1UF

20% 10V CERM 402

C5145

1

2

1/16W MF-LF

402

5%

10K

R5164

1

2

MF-LF

5%

1/16W

402

0

LPCPLUS

R5165

1 2

72 51 43

1/16W

402

5%

MF-LF

0

LPCPLUS_NO

R5160

1 2

72 43 21

43

7

43

7

51

20K

MF-LF

1/16W

402

5%

R5161

1

2

72 51 43

43

7

43

7

43 21

72 43 21

72 21

72 51 43

21

R5158

LPCPLUS_NO

MF-LF

5%

1/16W

402

0

LPCPLUS_NO

1/16W MF-LF

402

5%

R5157

1 2

33

LPCPLUS_NO

402

1/16W

5%

MF-LF

33

R5156

1 2

43 21

72 43 21

402

100K

MF-LF

5%

1/16W

R5140

1

2

5%

1/16W

402

10K

R5144

1

2

MF-LF

402

5%

1/16W

0

LPCPLUS

R5166

1 2

SYNC_MASTER=K36B_MLB SYNC_DATE=08/17/2008

02

109

LPC+SPI Debug Connector

051-8089

51

SPI_CLK_R

SPI_MOSI_R

=PP3V3_S5_ROM

=PP5V_S0_LPCPLUS

SPI_ALT_MOSI

=PP3V3_S5_LPCPLUS

SMC_MD1

SMC_TDO

SPIROM_USE_MLB

SPI_ALT_MISO

SPI_ALT_CS_L_MUX

SPI_MISO_MUX

SPI_MLB_CS_L_MUX

=PP3V3_S5_LPCPLUS

LPC_AD<1>

SMC_RESET_L

=PP3V3_S5_LPCPLUS

SMC_TMS

LPC_AD<2> LPC_AD<3>

SPI_ALT_CLK

SMC_TDI

LPC_PWRDWN_L

LPC_CLK33M_LPCPLUS

SMC_TX_L

SPI_ALT_CS_L

PM_CLKRUN_L

SMC_TRST_L

SPI_ALT_MISO

LPC_AD<0>

LPC_SERIRQ

SPI_ALT_CLK

SPI_CLK_MUX

SPI_MISO

SPI_MOSI_MUX

=PP3V3_S5_ROM

SPI_CS0_R_L

SPI_CLK_R

SPI_MOSI_R

SPI_MISO

LPC_FRAME_L

DEBUG_RESET_L

LPCPLUS_GPIO

SMC_RX_L

SMC_NMI

SMC_TCK

SPI_ALT_CS_L

=SPI_CS1_R_L_USE_MLB

SPIROM_USE_MLB

MAKE_BASE=TRUE

SPIROM_USE_MLB

=PP3V3_S5_LPCPLUS

SPI_MLB_CS_L

SPI_MOSI_MUX

SPI_CLK_MUX

SPI_ALT_MOSI

SPI_MISO_MUX

8

43 51

8

43

8

43

8

43

8

43 51

7

43

7

43

8

43

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

(Write: 0x98 Read: 0x99)

EMC1403-5: U5515

CPU Temp

C5270,C5271 close to destination end

C5280,C5281 close to destination end

(Write: 0xA0 Read: 0xA1)

SMC "0" SMBus Connections

SMC "Management" SMBus Connections

The bus formerly known as "Battery B"

Battery

Battery Charger

Battery Temp - (Write: 0x90 Read: 0x91)

Battery Manager - (Write: 0x16 Read: 0x17)

SMC

(MASTER)

U4900

(MASTER)

U4900

(Write: 0x98 Read: 0x99)

EMC1403-5: U5535

J3400

(Write: 0x52 Read: 0x53)

MINI-PCIE

(MASTER)

U4900

SMC

(All 8 addresses used)

MCP79

(Write: 0xA0-0xAE,

U2690 OR U2695

MCP79

(MASTER?)

(MASTER)

Read: 0xA1-0xAF)

U1400

J3100U1400

J3200

U4900

SMC

(MASTER)

Margin Control

(Write: 0x30 Read: 0x31)

(Write: 0x98 Read: 0x99)

(Write: 0x70 Read: 0x71)

U2900

SMS

U5930

U2901

HDCP ROM

(Write: 0xA2 Read: 0xA3)

MCP79 SMBUS "1" CONNECTIONS

Vref DACs

MCP Temp

U4900

J6950

(See Table)

Battery

SMC

SO-DIMM "A"

MCP79 SMBUS "0" CONNECTIONS

(MASTER)

SMC "A" SMBus Connections

NOTE: SMC RMT bus remains powered and may be active in S3 state

C5260,C5261 close to destination end

SMC "B" SMBus Connections

SMC

ISL6258A - U7000

(Write: 0x12 Read: 0x13)

C5250,C5251 close to Destination end

SMC "Battery A" SMBus Connections

SO-DIMM "B"

1/16W

4.7K

402

5%

MF-LF

R5200

1

2

4.7K

402

1/16W

5%

MF-LF

R5201

1

2

5%

1K

402

1/16W MF-LF

R5280

1

2

MF-LF 402

5% 1/16W

1K

R5281

1

2

5%

402

MF-LF

1/16W

4.7K

R5261

1

2

4.7K

1/16W

5%

402

MF-LF

R5260

1

2

MF-LF 402

1K

5% 1/16W

R5271

1

2

1K

5%

402

MF-LF

1/16W

R5270

1

2

1/16W MF-LF 402

5%

4.7K

R5251

1

2

402

4.7K

1/16W MF-LF

5%

R5250

1

2

10K

402

1/16W

5%

MF-LF

R5231

1

2

10K

5% 1/16W MF-LF

402

R5230

1

2

MF-LF

5%

402

4.7K

1/16W

R5290

1

2

4.7K

5% 1/16W

402

MF-LF

R5291

1

2

402

CERM

50V

5%

22PF

C5250

1

2

22PF

CERM 402

50V

5%

C5251

1

2

402

CERM

5%

22PF

50V

C5271

1

2

402

CERM

50V

5%

22PF

C5270

1

2

22PF

402

50V

5% CERM

C5261

1

2

22PF

5%

402

50V CERM

C5260

1

2

402

CERM

22PF

5% 50V

C5281

1

2

402

5% 50V CERM

22PF

C5280

1

2

52

051-8089

SMBUS CONNECTIONS

SYNC_MASTER=K36B_MLB SYNC_DATE=08/17/2008

02

109

=PP3V3_S0_SMBUS_SMC_0_S0

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_0_S0_SDA

MAKE_BASE=TRUE

SMBUS_SMC_BSA_SCL

MAKE_BASE=TRUE

SMBUS_SMC_A_S3_SDA

MAKE_BASE=TRUE

SMBUS_SMC_A_S3_SCL

SMBUS_SMC_BSA_SDA

MAKE_BASE=TRUE MAKE_BASE=TRUE

SMBUS_SMC_B_S0_SDA

MAKE_BASE=TRUE

SMBUS_SMC_B_S0_SCL =I2C_CPUTHMSNS_SCL

=PP3V3_S0_SMBUS_SMC_B_S0

SMB_B_S0_DATA

SMB_B_S0_CLK

=PP3V3_S3_SMBUS_SMC_A_S3

SMB_0_S0_CLK

MAKE_BASE=TRUE

SMBUS_MCP_1_CLK

MAKE_BASE=TRUE

SMBUS_MCP_1_DATA

SMBUS_MCP_0_DATA

MAKE_BASE=TRUE

SMBUS_SMC_MGMT_SDA

MAKE_BASE=TRUE

SMBUS_MCP_0_CLK

SMBUS_SMC_MGMT_SCL

MAKE_BASE=TRUE

SMB_A_S3_CLK

SMB_A_S3_DATA

=I2C_MCPTHMSNS_SCL

=PP3V3_S0_SMBUS_MCP_0

=I2C_SMS_SDA

=I2C_SMS_SCL

=I2C_PCA9557D_SCL

=I2C_PCA9557D_SDA

=I2C_VREFDACS_SDA

=I2C_VREFDACS_SCL

SMB_MGMT_CLK

SMB_MGMT_DATA

=PP3V3_S3_SMBUS_SMC_MGMT

=I2C_SODIMMA_SDA

=I2C_HDCPROM_SCL

=I2C_SODIMMB_SDA

=I2C_SODIMMA_SCL

=PP3V3_S0_SMBUS_MCP_0

=I2C_HDCPROM_SDA

=I2C_SODIMMB_SCL

SMB_0_S0_DATA

=I2C_MCPTHMSNS_SDA

I2C_MINI_PCIE_SCL

I2C_MINI_PCIE_SDA

=I2C_CPUTHMSNS_SDA

=SMBUS_BATT_SCL

=SMBUS_BATT_SDA

=SMBUS_CHGR_SDA

=SMBUS_CHGR_SCL

SMB_BSA_CLK

SMB_BSA_DATA

=PP3V42_G3H_SMBUS_SMC_BSA

8

75

75 75

75

47

8

41

8

41

21 72

7

13 21 72

75

7

13 21 72

75

41

47

8

44

27

27 41

41

8

28

25

29

28

8

44

25

29

41

47

7

31

7

31

47

56

57

41

8

OUT

D

N-CHANNEL

P-CHANNEL

G

S

D

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

CPU Voltage Sense / Filter

Place RC close to SMC

RTHEVENIN = 4573 OHMS

Place RC close to SMC

divider when high.

Enables PBUS VSense

PBUS VOLTAGE SENSE ENABLE & FILTER

Place RC close to SMC

MCP Voltage Sense / Filter

42

6.3V

0.22UF

X5R 402

20%

C5359

1

2

4.53K

1% 1/16W MF-LF

402

R5359

1 2

NTUD3127CXXG

SOT-963

Q5315

6

3

2

5

1

4

64

1%

1/16W

402

100K

MF-LF

R5316

1

2

MF-LF

1/16W

100K

402

1%

R5315

1

2

41

402

6.3V

20%

X5R

0.22UF

C5385

1

2

1%

402

MF-LF

1/16W

27.4K

R5385

1

2

1% 1/16W MF-LF

402

5.49K

R5386

1

2

SM

PLACEMENT_NOTE=Place near U1400 center

XW5359

1 2

41

1/16W

1%

402

MF-LF

4.53K

R5309

1 2

402

0.22UF

20%

X5R

6.3V

C5309

1

2

SM

PLACEMENT_NOTE=Place near U1000 center

XW5309

1 2

109

02

SYNC_DATE=08/17/2008SYNC_MASTER=K36B_MLB

VOLTAGE SENSING

051-8089

53

=PPVCORE_S0_CPU_VSENSE

CPUVSENSE_IN

SMC_MCP_VSENSE

=PPBUS_G3HRS5

PBUSVSENS_EN_L_DIV

=PBUSVSENS_EN

PBUSVSENS_EN_L

GND_SMC_AVSS

SMC_PBUS_VSENSE

GND_SMC_AVSS

MCPVSENSE_IN

SMC_CPU_VSENSE

GND_SMC_AVSS

=PPVCORE_S0_MCP_VSENSE

VOLTAGE=18.5V

PPBUS_G3HRS5_VSENSE

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.20 mm

8

41 42 45 46

8

V+

REFIN+

IN-

OUT

GND

OUT

IN

OUT

V+

REFIN+

IN-

OUT

GND

IN

OUT

V+

REFIN+

IN-

OUT

GND

OUT

IN

OUT

V+

REFIN+

IN-

OUT

GND

IN

OUT

IN

OUT

VER 1

VCC

A

1

0

B1

GND

B0

SEL

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

DC-IN (AMON) CURRENT SENSE

CHARGER BMON CURRENT SENSE

MCP VCore Current Sense

MCP VCore Current Sense Filter

REGULATOR SIDE

MCP MEM VDD Current Sense

Place RC close to SMC

LOAD SIDE

CPU 1.05V CURRENT SENSE

CPU VCORE LOAD SIDE CURRENT SENSOR / FILTER

STUFF EITHER R5431 OR U5413 DEPENDING ON BMON CURRENT SENSING METHOD

Place RC close to SMC

MCP MEM VDD Current Sense Filter

SC70

INA213

U5400

2

5

4

6

1

3

402

CERM

10V

20%

0.1uF

C5415

1

2

1/16W

1%

402

MF-LF

4.53K

R5416

12

41

0.22UF

X5R

20%

6.3V

402

C5472

1

2

1%

MF

0.001

1W

1206

R5490

1 2 3 4

61 24 22

8 8

MF-LF

402

1/16W

1%

4.53K

R5417

12

10V

20% CERM

0.1uF

402

C5416

1

2

8

SC70

INA210

U5401

2

5

4

6

1

3

0.002

1%

1/4W

MF

1206

R5491

1 2 3 4

8

41

402

0.22UF

20%

X5R

6.3V

C5435

1

2

4.53K

402

MF-LF

1/16W

1%

R5418

12

CERM

10V

20%

402

0.1uF

C5417

1

2

SC70

INA213

U5402

2

5

4

6

1

3

8

MF

1W

0.5%

0.01

0612

R5492

12 34

8

42

20%

X5R

6.3V

0.22UF

402

C5436

1

2

41

ENG_BMON

402

0.22UF

X5R

20%

6.3V

C5490

1

2

ENG_BMON

402

10V

0.1uF

20% CERM

C5418

1

2

SC70

INA213

ENG_BMON

U5403

2

5

4

6

1

3

57

402

ENG_BMON

5% MF-LF

1/16W

100K

R5423

1

2

57

PROD_BMON

402

MF-LF

0

5%

1/16W

R5431

1 2

57

MF-LF

402

1/16W

1%

6.19K

R5471

1 2

20%

0.22UF

402

X5R

6.3V

C5470

1

2

1%

MF-LF

17.4K

402

1/16W

R5480

1

2

60 41

4.53K

402

MF-LF

1/16W

1%

R5481

1 2

20%

402

X5R

6.3V

0.22UF

C5487

1

2

57 41

ENG_BMON

SC70

NC7SB3157P6XG

U5413

43

1

2

6

5

42

4.53K

1/16W

1%

402

MF-LF

R5401

1 2

ENG_BMON

0.1UF

20% 10V CERM 402

C5459

1

2

SYNC_MASTER=K36B_MLB SYNC_DATE=08/17/2008

109

02

Current Sensing

051-8089

54

=PP3V42_G3H_BMON_ISNS

BMON_AMUX_OUT

SMC_BMON_MUX_SEL

MAKE_BASE=TRUE

SMC_MCP_DDR_ISENSE

ISNS_PVCORES0MCP_P

CHGR_CSO_R_P

GND_SMC_AVSS

SMC_BATT_ISENSE

CHGR_BMON

IMVP6_IMON

SMC_DCIN_ISENSE

GND_SMC_AVSS GND_SMC_AVSS

MCPDDR_IOUT

GND_SMC_AVSS

CPUVTT_IOUT

=PP5VR3V3_S0_MCPCOREISNS

MCPCORE_IOUT

SMC_CPU_FSB_ISENSE

GND_SMC_AVSS

CHGR_AMON

CHGR_CSO_R_N

BMON_INAOUT

=PP3V3_S0_CPUVTTISNS

=PP3V3_S0_MCPDDRISNS

=PP1V8_S0_FET_R

=PP1V8_S0

ISNS_P1V5S0MCP_N

ISNS_P1V5S0MCP_P

GND_SMC_AVSS

ISNS_PVCORES0MCP_N

=PPVCORE_S0_MCP_REG_R

=PPVCORE_S0_MCP

SMC_CPU_ISENSE

ISNS_CPUVTT_N

ISNS_CPUVTT_P

=PPBUS_G3H_CPU_ISNS_R

=PPBUS_G3H_CPU_ISNS

SMC_MCP_CORE_ISENSE

MAKE_BASE=TRUE

8

41 42 45 46

41 42 45 46 41 42 45 46

41 42 45 46

8

41 42 45 46

8

41 42 45 46

61

DN2/DP3

DP1

DN1

DP2/DN3

SMCLK

GND

THERM*

SMDATA

VDD

ALERT*

BI

DN2/DP3

DP1

DN1

DP2/DN3

SMCLK

GND

THERM*

SMDATA

VDD

ALERT*

NC

BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

518S0521

CPU T-Diode Thermal Sensor

INTERNAL DIODE IN U5515 DETECTS CPU PROXIMITY TEMPERATURE

PLACEMENT NOTE: PLACE U5535 NEAR MCP

PLACEMENT NOTE: PLACE U5515 NEAR CPU

DETECT MCP DIE TEMPERATURE

DETECT CPU DIE TEMPERATURE

DETECT FIN-STACK TEMPERATURE

DETECT HEAT-PIPE TEMPERATURE

INTERNAL DIODE IN U5535 DETECTS MCP PROXIMITY TEMPERATURE

MCP T-Diode Thermal Sensor

CERM

402

SIGNAL_MODOL=EMPTY

0.0022uF

10% 50V

C5540

1

2

EMC1403-1-AIZL

TSSOP

CRITICAL

U5515

8

3

5

2

4

6

10

9

7

1

44

1/16W

5% MF-LF

10K

402

R5517

1

2

10K

MF-LF

5%

1/16W

402

R5516

1

2

402

1/16W

5% MF-LF

10K

R5537

1

2

402

10K

MF-LF

5%

1/16W

R5536

1

2

44

20%

402

CERM

0.1uF

10V

C5535

1

2

TSSOP

EMC1403-1-AIZL

CRITICAL

U5535

8

3

5

2

4

6

10

9

7

1

M-RT-SM

78171-0004

J5520

5

6

1 2 3 4

0.0022uF

50V

10%

SIGNAL_MODOL=EMPTY

CERM

402

C5521

1

2

SIGNAL_MODOL=EMPTY

402

CERM

0.0022uF

10% 50V

C5522

1

2

10

21

0.1uF

10V CERM 402

20%

C5515

1

2

47

1/16W

5%

MF-LF

402

R5515

1 2

402

50V

CERM

0.0022uF

10%

SIGNAL_MODOL=EMPTY

C5520

1

2

47

1/16W

402

MF-LF

5%

R5535

1 2

55

051-8089

Thermal Sensors

SYNC_MASTER=K36B_MLB SYNC_DATE=08/17/2008

109

02

CPUTHMSNS_D2_P

PP3V3_S0_CPUTHMSNS_R

MIN_LINE_WIDTH=0.25 mm VOLTAGE=3.3V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

PP3V3_S0_MCPTHMSNS_R

MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V

=PP3V3_S0_CPUTHMSNS

=I2C_MCPTHMSNS_SDA

MCPTHMSNS_D2_P

MCP_THMDIODE_N

MCP_THMDIODE_P

CPU_THERMD_N

CPU_THERMD_P

=I2C_CPUTHMSNS_SDA

=PP3V3_S0_MCPTHMSNS

=I2C_MCPTHMSNS_SCL

=I2C_CPUTHMSNS_SCL

MCPTHMSNS_THERM_L

MCPTHMSNS_ALERT_L

CPUTHMSNS_THERM_L

CPUTHMSNS_ALERT_L

MCPTHMSNS_D2_N

CPUTHMSNS_D2_N

7

8

7

8

7

D

GS

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

NC

518S0521

GND

MOTOR CONTROL

TACH

5V DC

402

MF-LF

1/16W

5%

47K

R5665

1 2

402

MF-LF

5%

1/16W

47K

R5660

1

2

100K

5%

1/16W

MF-LF

402

R5661

1

2

SSM3K15FV

SOD-VESM-HF

Q5660

3

1

2

M-RT-SM

78171-0004

CRITICAL

J5601

5

6

1 2 3 4

56

051-8089

Fan

109

SYNC_MASTER=K36B_MLB SYNC_DATE=08/17/2008

02

FAN_RT_TACH

FAN_RT_PWM

SMC_FAN_0_TACH

SMC_FAN_0_CTL

=PP3V3_S0_FAN_RT

=PP5V_S0_FAN_RT

7

41

8

OUT

BI

IN

IOIONC

GND

VBUS

NC

SYM_VER-2

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

516S0727

NC

(CONN_TPAD_USB_N)

PLACEMENT NOTE

PLACE L5800,L5801,L5803 NEAR J5800

- SYNC WITH T18

PLACE C5800,C5810,C5803 NEAR J5800 PLACE D5800 NEAR J5800

- COPY THIS PAGE FROM T18 CSA.58

GEYSER

PLACE D5800 CLOSE J5800

(CONN_TPAD_USB_P)

402

1/16W MF-LF

5%

1K

R5810

1 2

0.1UF

20%

402

10V CERM

PLACEMENT_NOTE=NEAR J5800

C5810

1

2

41 42

600-OHM-300MA

PLACEMENT_NOTE=NEAR J5800

0402

L5803

1 2

PLACEMENT_NOTE=NEAR J5800

402

10% 16V CERM

0.01uF

C5803

1

2

9 9

41 42 56

8

F-ST-SM

53307-8610

CRITICAL

J5800

1

10

2

3

4

5

6

7

8

9

402

0.1UF

10V

20% CERM

C5860

1

2

SLP1210N6

RCLAMP0502N

CRITICAL

D5800

1

5 42 3

6

0402

PLACEMENT_NOTE=NEAR J5800

600-OHM-300MA

L5804

1 2

0402

600-OHM-300MA

PLACEMENT_NOTE=NEAR J5800

L5802

1 2

DLP0NS 90-OHM

CRITICAL

L5801

1 2

3

4

SYNC_MASTER=K36B_MLB SYNC_DATE=08/17/2008

109

02

GEYSER

051-8089

58

=USB2_TPAD_P

=USB2_TPAD_N

SMC_ONOFF_L

SMC_LID

=PP5V_S3_TPAD

CONN_TPAD_USB_N

MIN_NECK_WIDTH=0.3MM

MIN_LINE_WIDTH=0.6MM

VOLTAGE=5V

PP5V_S3_TPAD_F

SMC_LID_LC

CONN_TPAD_USB_P

CONN_TPAD_ONOFF_FLTR_L

MIN_LINE_WIDTH=0.6MM

TPAD_GND_F

MIN_NECK_WIDTH=0.3MM

VOLTAGE=0V

72

7

72

7

OUT

NC NC

NC

FS PD ST

RES RES

GND

NC

NC NC

NC

NC NC

VOUTX

VOUTY

VOUTZ

VDD

NC

OUT

IN

OUT

NC

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

SMSINT_L SHOULD BE PULL UP IF NOT USED.

ANALOG SMS

1

+Z (up)

+Y

Desired orientation when placed on board top-side:

Package Top

+X

Front of system

Top-through View

+X

placed on board bottom-side:

Desired orientation when

+Y

1

+Z (down)

41

AP344ALH

LGA

CRITICAL

U5920

1

7

3 6 9

11 13 16

5

15

4

2

14

12

10

8

1/16W

5%

402

10K

MF-LF

R5920

1

2

1/16W

5%

10K

402

MF-LF

R5921

1

2

41

20% X5R

603

10UF

6.3V

C5926

1

2

5%

10K

402

MF-LF

1/16W

R5932

1

2

0.1uF

20% 10V CERM 402

C5920

1

2

402

16V

0.01UF

CERM

20%

C5906

1

2

402

16V

20%

0.01UF

CERM

C5905

1

2

0.01UF

20% 16V CERM 402

C5904

1

2

59

051-8089

SYNC_MASTER=K36B_MLB

109

02

SMS

SYNC_DATE=08/17/2008

SMS_Y_AXIS

SMS_Z_AXIS

SMS_SELFTEST

SMS_ONOFF_L

SMS_PWRDN

MAKE_BASE=TRUE

SMS_X_AXIS

=PP3V3_S3_SMS

SMS_INT_L

=PP3V3_S5_SMC

8

42

8

41 42

OUT

IN

GND

VCC

WP*/ACC

CE*

SI/SIO0

HOLD*

SCLK

SO/SIO1

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

25MHZ IS SECLECTED WITH R5164 AND R5144 ANY FO THE 4 FREQUENCIES CAN BE SELECTED WITH R6190, R6191, R5164 AND R5144

MCP79 SPI Frequency Select

1

SPI_MOSI

1 MHz

Frequency

31 MHz

42 MHz

25 MHz

0

1

0

1

SPI_CLK

CERM

402

10V

20%

0.1UF

C6100

1

2

72 43

1/16W MF-LF

5%

402

0

PLACEMENT_NOTE=PLACE CLOSE TO U6100

R6150

12

2 1

R6105

402

5%

MF-LF

1/16W

PLACEMENT_NOTE=PLACE CLOSE TO U6100

33

PLACEMENT_NOTE=PLACE CLOSE TO U6100

1/16W MF-LF

5%

402

0

R6152

12

3.3K

5% 1/16W MF-LF 402

R6101

1

2

402

MF-LF

1/16W

5%

3.3K

R6100

1

2

43

72 43

402

MF-LF

5%

1/16W

10K

NO STUFF

R6190

1

2

CRITICAL

32MBIT

MX25L3205DM2I-12G

OMIT

SOP

U6100

1

4

7

6

5

2

8

3

1/16W

402

5%

10K

MF-LF

R6191

1

2

NO STUFF

61

051-8089

SPI ROM

109

02

SYNC_DATE=081/17/2008

SYNC_MASTER=K36B_MLB

=PP3V3_S5_ROM

SPI_MOSI

SPI_MISO_R

SPI_MOSI_MUX

SPI_MISO_MUX

SPI_CLK_MUX

SPI_HOLD_L

SPI_CLK

SPI_MLB_CS_L

SPI_WP_L

8

43

72

IN IN IN

IN

OUT

THRM_PAD

NC

IN1

EN

IN2

OUT1 OUT2

NR/FB

GND

PORT-B-VREFO2

PORT-A-VREFO/DCVOL

PORT-E-L

THRM_PAD

AVSS1

SYNC

CD-R

PORT-F-VREFO

PORT-E-VREFO PORT-B-VREFO

PORT-C-VREFO

PORT-B-R

PORT-B-L

PORT-E-R

PORT-H-R

PORT-H-L

PORT-G-R

PORT-G-L

JDREF

VREF

PORT-D-R

PORT-D-L

PORT-C-R

PORT-C-L

SPDIFO

PORT-F-R

PORT-F-L

DVSS

CD-GND

BEEP

AVSS2

AVDD2

AVDD1

SDATA_IN

CD-L

SENSE_A SENSE_B

GPIO1/DMIC-L

BCLK

DVDD

NC

SPDIFI/EAPD/MIDI-I/DMIC-R

PORT-A-L PORT-A-R

RESET*

GPIO0/DMIC-CLK

SDATA_OUT

DVDD_IO

REV B3

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

AUDIO CODEC

APPLE P/N 353S1538

VOUT=1.2246V*[1+(R6210/R6211)]=4.58V

PLACE R6210, R6211, AND C6224 CLOSE TO U6201

APPLE P/N 353S1576

AUDIO 4.5V REGULATOR

0.1UF

CRITICAL

X5R 402

16V

10%

C6208

1

2

72 21

5%

MF-LF

39

402

1/16W

R6204

1 2

10% 50V CERM 402

0.001UF

C6212

1

2

402

CERM

50V

10%

0.001UF

C6206

1

2

10% 50V

0.001UF

CERM 402

C6203

1

2

CERM

20% 50V

402

0.001UF

C6207

1

2

0402

FERR-220-OHM

L6201

1 2

20.0K

1% 1/16W

402

MF-LF

R6205

1

2

CERM

6.3V

CRITICAL

10% 402

1UF

C6200

1

2

6.3V

20%

150UF

POLY-TANT

CASE-B2-SM

CRITICAL

C6205

1

2

20%

6.3V

POLY-TANT

CASE-B2-SM

CRITICAL

150UF

C6204

1

2

0402

FERR-220-OHM

L6200

1 2

10UF

20%

603

CRITICAL

X5R

6.3V

C6221

1

2

402

1K

1/16W

5%

MF-LF

R6202

1 2

402

0.1UF

10% X5R

16V

C6220

1

2

5%

402

MF-LF

1/16W

0

NO STUFF

R6200

1 2

CERM

50V

10%

0.001UF

402

C6223

1

2

0402

FERR-220-OHM

L6202

1 2

402

1/16W

29.4K

MF-LF

1%

R6211

1

2

1/16W

1% MF-LF

80.6K

402

R6210

1

2

402

MF-LF

39

1/16W

5%

R6206

1 2

402

5%

100K

MF-LF

1/16W

R6209

1

2

LREG_TPS79501DRB

SON

U6201

8

6

1 2

7

5

3 4

9

CRITICAL

QFN

ALC885Q-VB3-GR

U6200

25

38

26

42

6

12

19

18

20

1

9

4

7

2 3

40 37

39 41

33

21 22

28

32

23 24

29

35 36 14

15 31

16 17 30

43 44

45 46

11

8

5

13 34

47

48

10

49

27

MF-LF

10K

402

1/16W

5%

R6271

1

2

100K

402

MF-LF

1/16W

5%

NO STUFF

R6270

1

2

50V

15PF

5%

402

CERM

C6224

1

2

3.3UF

10%

CRITICAL

TANT

16V SMA-HF1

C6210

1

2

0.001UF

10% 50V CERM 402

C6201

1

2

100K

1/16W MF-LF 402

5%

R6203

1

2

1/16W MF-LF 402

NO STUFF

5%

0

R6201

1

2

62

02

109

051-8089

SYNC_MASTER=K36A_MLB

AUDIO: CODEC

AUD_GPIO_1

HDA_SDIN0

=GND_AUDIO_CODEC

AUD_SPDIF_I

AUD_SPDIF_O

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.30MM

=PP3V3_S0_AUDIO

AUD_SENSE_A AUD_SENSE_B

AUD_VREF_PORT_A

AUD_BI_PORT_A_L

AUD_4V5_REG_IN

4V5_REG_FB

NO_TEST

NC_AUD_BI_PORT_E_R

NO_TEST

NC_AUD_BI_PORT_E_L

NO_TEST

NC_AUD_BI_PORT_F_R

NO_TEST

NC_AUD_VREF_PORT_F

MIN_LINE_WIDTH=0.30 MM

VOLTAGE=5V

MIN_NECK_WIDTH=0.20 MM

=PP5V_S0_AUDIO

NO_TEST

NC_BAL_IN_COM

NO_TEST

NC_BAL_IN_R

NO_TEST

NC_BAL_IN_L

NO_TEST

NC_VRP

HDA_SYNC

BEEP

AUD_BI_PORT_C_L

AUD_SPDIF_OUT

CODEC_DVDD

CODEC_SDATA_IN

AUD_BI_PORT_D_R

AUD_REG_SHDN_L

HDA_BIT_CLK

HDA_SDOUT

=PP3V3_S0_AUDIO

=GND_AUDIO_CODEC

PP4V5_AUDIO_ANALOG

MIN_NECK_WIDTH=0.20MM

AVDD_ADC_DAC

MIN_NECK_WIDTH=0.20MM

VOLTAGE=3.3V

CODEC_DVDD

HDA_RST_L

NO_TEST

NC_AUD_BI_PORT_F_L

AUD_BI_PORT_A_R

VOLTAGE=4.5V

MIN_LINE_WIDTH=0.40MM MIN_NECK_WIDTH=0.20MM

PP4V5_AUDIO_ANALOG

AUD_BI_PORT_D_L

AUD_BI_PORT_C_R

AUD_GPIO_0

NC_AUD_VREF_PORT_E

NO_TEST

AUD_VREF_PORT_B AUD_BI_PORT_B_L AUD_BI_PORT_B_R

NO_TEST

NC_AUD_VREF_PORT_C

NO_TEST

NC_AUD_BI_PORT_H_R

AUD_CODEC_JDREF

=GND_AUDIO_CODEC

MIN_NECK_WIDTH=0.20 MM VOLTAGE=0V

MIN_LINE_WIDTH=0.30 MM

NC_AUD_BI_PORT_H_L

NO_TEST

AUD_BI_PORT_G_R

AUD_CODEC_VREF

NO_TEST

NC_AUD_BI_PORT_G_L

NO_TEST

NC_AUD_VREF_PORT_D

9

52 53 54 55

54

8

52 54 55

55

8

55

54

52

53

8

52 54 55

9

52 53 54 55

52

55

52

53

55

53

55

9

52 53 54 55

53

IN

OUT

IN

GND

PGND

VDD

PVDD

IN-

IN+

SYNC

OUT-

OUT+

SHDN*

THRML

PAD

GND

PGND

VDD

PVDD

IN-

IN+

SYNC

OUT-

OUT+

SHDN*

THRML

PAD

GND

PGND

VDD

PVDD

IN-

IN+

SYNC

OUT-

OUT+

SHDN*

THRML

PAD

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

APN:353S1595

GAIN

RIGHT SATELLITE

LEFT SATELLITE

SUB

12DB

80 HZ < FC < 132 HZ

SATELLITE & SUB TWEETER AMPLIFIER

169 HZ < FC < 282 HZ

SATELLITE

SUB-TWEETER

5%

402

10K

1/16W MF-LF

R6610

1

2

0.047UF

10% X7R

402

16V

CRITICAL

C6610

1 2

402

CRITICAL

0.047UF

X7R

16V

10%

C6620

1 2

0.1UF

X5R

CRITICAL

10%

402

16V

C6631

1

2

0402

FERR-1000-OHM

L6611

1 2

52

6.3V

10%

402

CERM

1uF

C6607

1

2

1/16W MF-LF

402

5%

0

R6600

1 2

FERR-1000-OHM

0402

L6620

1 2

0402

FERR-1000-OHM

L6610

1 2

54

7

54

7

54

7

54

7

1UF

10%

CERM

402

6.3V

C6606

1

2

54

7

54

7

0.1UF

X5R 402

16V

CRITICAL

10%

C6630

1 2

0402

FERR-1000-OHM

L6630

1 2

52

0.047UF

10%

CRITICAL

402

16V

X7R

C6621

1

2

CERM

10%

6.3V

1uF

402

C6609

1

2

POLY-TANT CASE-B2-SM

120UF

CRITICAL

6.3V

20%

C6605

1

2

MAX9705

TDFN1

CRITICAL

U6630

4

3

2

9

8

7

10

5

6

11

1

TDFN1

MAX9705

CRITICAL

U6610

4

3

2

9

8

7

10

5

6

11

1

CRITICAL

TDFN1

MAX9705

U6620

4

3

2

9

8

7

10

5

6

11

1

0.047UF

402

CRITICAL

16V

10% X7R

C6611

1

2

402

6.3V

CERM

10%

1uF

C6608

1

2

402

CERM

10%

1UF

6.3V

C6602

1

2

20% CASE-B3-SM1

CRITICAL

POLY

47UF

6.3V

C6601

1

2

47UF

20%

CASE-B3-SM1

POLY

CRITICAL

6.3V

C6603

1

2

6.3V

CERM

402

10%

1UF

C6604

1

2

1/16W MF-LF

5%

402

0

R6660

12

1/16W

0

402

5%

MF-LF

R6661

12

1/16W MF-LF

5%

402

0

R6670

12

1/16W

0

402

5%

MF-LF

R6671

12

1/16W MF-LF

5%

0

402

R6680

12

0

402

5%

MF-LF

1/16W

R6681

12

SM

XW6600

1 2

051-8089

SYNC_MASTER=K36A_MLB

AUDI0: SPEAKER AMP

SYNC_DATE=08/29/2008

109

66

02

SPKRAMP_THERMPLANE

=PP5V_S0_AUDIO_AMP

SPKRAMP_L_P_OUT

=PP5V_S0_AUDIO_AMP

=GND_AUDIO_AMP

VOLTAGE=5V MIN_LINE_WIDTH=0.60 MM MIN_NECK_WIDTH=0.20 MM =PP5V_S0_AUDIO_AMP

SPKRAMP_R_P_OUT SPKRAMP_R_N_OUT

=GND_AUDIO_AMP

SPKRAMP_L_N_OUT

=GND_AUDIO_AMP

SPKRAMP_SUB_N_OUT

VOLTAGE=5V MIN_LINE_WIDTH=0.30 MM MIN_NECK_WIDTH=0.20 MM

PP5V_S0_AUDIO_F

MAX9705_R_N

SPKRAMP_THERMPLANE

MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM SPKRCONN_L_N_OUT

PP5V_S0_AUDIO_F

SPKRAMP_SUB_P_OUT

AUD_SPKRAMP_INL

MAX9705_L_N

AUD_SPKRAMP_SHUTDOWN_L

PP5V_S0_AUDIO_F

SPKRAMP_THERMPLANE

=GND_AUDIO_CODEC

AUD_SPKRAMP_SHUTDOWN_L

MAX9705_SUB_N

=GND_AUDIO_CODEC

AUD_SPKRAMP_SHUTDOWN_L

SPKRAMP_R_N_OUT

MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM

SPKRAMP_SUB_N_OUT

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.30 mm

SPKRAMP_L_N_OUT

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.30 mm

MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM SPKRCONN_SUB_N_OUT

MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM SPKRCONN_R_N_OUT

MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM SPKRCONN_SUB_P_OUT

SPKRAMP_SUB_P_OUT

MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM SPKRCONN_L_P_OUT

MIN_LINE_WIDTH=0.30 mm

SPKRAMP_R_P_OUT

MIN_NECK_WIDTH=0.20 MM MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.30 mm

SPKRCONN_R_P_OUT

SPKRAMP_L_P_OUT

MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM

=GND_AUDIO_AMP

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.60 MM

AUD_SPKRAMP_INR

AUD_SPKRAMP_INL_L

AUD_SPKRAMP_INR_L

AUD_BI_PORT_G_R

AUD_GPIO_0

AUD_BI_PORT_D_L

SPKRAMP_THERMPLANE

AUD_SPKRAMP_INSUB

AUD_SPKRAMP_INSUB_L

AUD_BI_PORT_D_R

53

8

53

8

53

9

53

8

53

9

53

9

53

9

52 53 54 55

53

9

52 53 54 55

9

52 53 54 55

53

9

53 53

IN IN IN IN

IN

VCC GND

VOUT SHLD_PIN SHLD_PIN

GROUND

RIGHT

SWITCH

LEFT

DETECT FOR PLUG TYPE

GROUND

LEFT

RIGHT

SWITCH

DETECT FOR PLUG TYPE

VCC

VIN

GND

SHLD_PIN SHLD_PIN

OUT

BI

OUT

IN

BI

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

SPEAKER CONNECTOR

APN:518S0519

APN:514-0604

HF APN:514-0521

MIC EMI FILTER

APN:518S0521

AUDIO JACK 2: LINE IN CONNECTOR, SPDIF RX

AUDIO JACK 1: LO/HP CONNECTOR, SPDIF TX

HF APN:514-0519

APN:514-0603

APN:518S0392

MIC CONNECTOR

0402-LF

FERR-120-OHM-1.5A

L6700

1 2

0402

FERR-1000-OHM

L6702

1 2

0402

FERR-1000-OHM

L6703

1 2

0402

FERR-1000-OHM

L6705

1 2

0402

FERR-1000-OHM

L6707

1 2

10%

1UF

6.3V

CERM 402

C6700

1

2

7

53

7

53

7

53

7

53

SM

XW6700

1 2

SM

XW6701

1 2

10

402

5% 1/16W MF-LF

R6749

1 2

603

20%

6.3V

X5R

10uF

C6751

1

2

0402

FERR-220-OHM

L6790

1 2

7

53

7

53

MF-LF

5%

0

402

1/16W

R6791

1 2

OMIT

CRITICAL

AUDIO-IN-MG3-K36

F-RT-TH-HF

J6750

2

7

1

10

9

4

5

3

8

6

SM

XW6705

1 2

M-RT-SM

48227-0303

CRITICAL

J6701

4

5

1 2 3

OMIT

AUDIO-OUT-K36-MG3

CRITICAL

F-RT-TH-HF

J6700

2

6

1

10

9

4

5

3

7

8

CRITICAL

78171-0004

M-RT-SM

J6703

5

6

1 2 3 4

M-RT-SM

CRITICAL

78171-0002

J6702

3

4

1 2

55

0402-LF

FERR-120-OHM-1.5A

L6750

1 2

0402-LF

FERR-120-OHM-1.5A

L6751

1 2

0

5%

402

1/16W MF-LF

R6740

1

2

0402

FERR-1000-OHM

L6770

1 2

0402

FERR-1000-OHM

L6772

1 2

402

6.8V-100PF

CRITICAL

DZ6770

1

2

402

6.8V-100PF

CRITICAL

DZ6771

1

2

6.8V-100PF

CRITICAL

402

DZ6702

1

2

402

CRITICAL

6.8V-100PF

DZ6704

1

2

6.8V-100PF

402

CRITICAL

DZ6705

1

2

CRITICAL

402

6.8V-100PF

DZ6703

1

2

CRITICAL

6.8V-100PF

402

DZ6753

1

2

CRITICAL

402

6.8V-100PF

DZ6752

1

2

0402

FERR-1000-OHM

L6754

1 2

6.8V-100PF

CRITICAL

402

DZ6754

1

2

6.8V-100PF

402

CRITICAL

DZ6755

1

2

5.6V-15A

NO STUFF

0405

DZ6700

1 3

2 4

NO STUFF

5.6V-15A

0405

DZ6701

1 3

2 4

0405

5.6V-15A

NO STUFF

DZ6750

1 3

2 4

0405

5.6V-15A

NO STUFF

DZ6751

1 3

2 4

0402

FERR-1000-OHM

L6756

1 2

1/16W

5%

10K

402

MF-LF

R6750

1 2

1/16W

5%

402

4.7

MF-LF

R6751

1 2

CERM 402

50V

5%

100PF

C6756

1

2

0402

FERR-1000-OHM

L6755

1 2

FERR-1000-OHM

0402

L6753

1 2

0402

FERR-1000-OHM

L6752

1 2

0402

FERR-1000-OHM

L6757

1 2

CERM

6.3V

402

10%

1UF

C6750

1

2

52

55

52

55

0402-LF

FERR-120-OHM-1.5A

L6701

1 2

0402

FERR-1000-OHM

L6704

1 2

FERR-1000-OHM

0402

L6706

1 2

55

1/16W MF-LF

402

10K

5%

R6700

1 2

4.7

402

MF-LF

5%

1/16W

R6701

1 2

100PF

50V

CERM 402

5%

C6705

1

2

SYNC_MASTER=K36A_MLB SYNC_DATE=08/29/2008

109

02

67

051-8089

AUDIO: JACK

MIC_HI_CONN

AUD_CONNJ1_SLEEVEDET

PP3V3_S0_AUDIO_SPDIF

=PP3V3_S0_AUDIO

AUD_CONNJ1_TIPDET_F

AUD_CONNJ2_SLEEVE_F

AUD_CONNJ2_TIPDET_F

AUD_J1_TIPDET_R

CHASSIS_AUDIO_JACK_ISOL

AUD_J2_TIPDET_R

AUD_CONNJ2_SLEEVEDET_F

AUD_CONNJ2_TIP_F

AUD_CONNJ1_SLEEVEDET_F

AUD_PORTC_R

MIC_SHLD_CONN

CHASSIS_AUDIO_JACK_ISOL

AUD_CONNJ1_SLEEVE_F

SPKRCONN_SUB_P_OUT

AUD_PORTA_L

AUD_J1_SLEEVEDET_R

SPKRCONN_R_N_OUT

SPKRCONN_SUB_N_OUT SPKRCONN_R_P_OUT

MIC_SHLD_CONN

MIC_LO_CONN

AUD_CONNJ2_RING_F

=GND_CHASSIS_AUDIO_JACK

AUD_PORTC_L

=GND_AUDIO_CODEC

AUD_SPDIF_I

AUD_J2_COM

MIC_HI_CONN

MIC_LO_CONN

MIC_LO

MIC_HI

CHASSIS_AUDIO_JACK_ISOL

GND_AUDIO_SPDIF_DGND

AUD_CONNJ2_SLEEVEDET

AUD_CONNJ2_SLEEVE

AUD_CONNJ2_RING

AUD_CONNJ2_TIPDET

AUD_CONNJ2_TIP

AUD_J2_OPT_OUT

CHASSIS_AUDIO_JACK_ISOL

AUD_SPDIF_OUT

GND_AUDIO_SPDIF_DGND

AUD_CONNJ1_RING

AUD_CONNJ1_TIP

AUD_CONNJ1_TIPDET

AUD_CONNJ1_SLEEVE

PP3V3_S0_AUDIO_SPDIF

SPKRCONN_L_N_OUT

SPKRCONN_L_P_OUT

AUD_CONNJ1_TIP_F

AUD_CONNJ1_RING_F

AUD_J1_COM

AUD_PORTA_R

54

7

54

55 52

8

54

55 54

7

54

55 54

7

54

7

9

55 53 52

9

54

7

54

7

54

IN

OUT

IN

OUT

IN

OUT

IN

D

G S

D

SG

D

SG

D

SG

D

SG

OUTL

INR INL

OUTR

SHDN*

CEXT

VCC

GND PAD

THM

IN

OUT

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

PORT C LI

PLACE C6852 NEAR U6200

PORT E DETECT(SPDIF DELEGATE)

N/A

MIXER

VREF_B (80%)

HP/LO DE-POP SWITCH

CODEC OUTPUT SIGNAL PATHS

0X0F (15)

MIC IN

VOLUME

PIN COMPLEX

CONVERTER

FUNCTION

PORT A DETECT

N/A

PORT A HP/LO

LINE IN SPDIF IN

NC

SPDIF OUT

FUNCTION SAT SPKR

0X0E (14)

0X05 (5) 0X25 (37)

0X15 (21,PORTA) 0X16 (22,PORTG)

0X14 (20,PORTD) 0X1E (30,SPDIF OUT)

DET ASSIGNMENT N/A

N/A

GPIO 0 N/A

MUTE CONTROL

GPIO 0

VREF_A(100%)

0X26 (38)

0X1B (27,PORTE)

N/A

CODEC INPUT SIGNAL PATHS

0X23 (35) 0X24 (36)

MUTE CONTROL 0X08 (8)

VOLUME

N/A

PIN COMPLEX

CONVERTER 0X08 (8) 0X07 (7) 0X0A (10)

0X1A (26,PORTC) 0X18 (24,PORTB) 0X1F (31,SPDIF IN)

DET ASSIGNMENT N/A

N/A

VREF

0X15 (21,PORTA)

0X04 (4) 0X06 (6)

HP OUT

Line-in (PORT C) DETECT

SUB SPKR

0X08 (8) 0X07 (7)

N/A

0X07 (7)

0X1A (26,PORTC)

MIC INPUT CIRCUITRY

PLACE L6800/C6800 CLOSE TO Q6800

APN:353S1459

16V

X5R 402

10%

0.1UF

C6801

1

2

47K

1/16W MF-LF

402

5%

R6802

1 2

CASE-B2-SM

20%

6.3V

POLY-TANT

CRITICAL

100UF

C6830

1 2

6.3V

POLY-TANT

CASE-B2-SM

CRITICAL

100UF

20%

C6831

1 2

52

54

52 55 52

54

0.1uF

16V

402

10% X5R

CRITICAL

C6850

1 2

NO STUFF

MF-LF

5%

402

0

1/16W

R6853

1 2

SM

XW6800

1 2

1/16W

0

NO STUFF

5%

402

MF-LF

R6854

1 2

MF-LF

2.2K

1/16W

5%

402

R6855

1 2

5%

402

100K

MF-LF

1/16W

R6852

1

2

CRITICAL

402

CERM

50V

10%

680PF

C6851

1

2

54

7

0.1UF

10%

402

X5R

16V

C6800

1

2

FERR-1000-OHM

0402

L6800

1 2

39.2K

MF-LF

1/16W

402

1%

R6806

1

2

1/16W MF-LF

402

5%

100K

R6803

1 2

1/16W

5% MF-LF

402

270K

R6861

1

2

0.01UF

402

16V

10% CERM

C6802

1

2

52

55 54

402

5% 1/16W MF-LF

10K

R6813

1

2

10%

16V

X5R 402

0.1UF

C6811

1

2

1/16W

47K

MF-LF

5%

402

R6812

1 2

54

16V

0.1UF

402

X5R

10%

C6835

1

2

402

CRITICAL

CERM

50V

NO STUFF

100PF

5%

C6852

1

2

1/16W MF-LF

6.81K

402

1%

R6850

1 2

10% CERM

402

1UF

6.3V

C6836

1

2

402

X5R-CERM

20%

4.7UF

CRITICAL

6.3V

C6853

1

2

SSM3K15FV

SOD-VESM-HF

Q6802

3

1

2

SOT563

SSM6N15FEAPE

Q6800

6

2

1

SOT563

SSM6N15FEAPE

Q6800

3

5

4

SOT563

SSM6N15FEAPE

Q6801

6

2

1

SSM6N15FEAPE

SOT563

Q6801

3

5

4

TANT

16V

CRITICAL

SMA-HF1

10%

3.3UF

C6832

12

CRITICAL

3.3UF

10% 16V TANT

SMA-HF1

C6833

12

39.2K

1/16W

402

1% MF-LF

R6805

1

2

CRITICAL

MAX9890BETA+

TDFN

U6801

8

5

3

7 4

6

2

9

1

MF-LF

402

10K

1/16W

5%

R6839

1

2

52

270K

402

MF-LF

5% 1/16W

R6801

1

2

MF-LF

270K

402

5% 1/16W

R6811

1

2

52 54

1/16W

27.4K

402

MF-LF

1%

R6836

1

2

54

402

27.4K

1% 1/16W MF-LF

R6837

1

2

52

27.4K

1% 1/16W MF-LF

402

R6835

1

2

1/16W MF-LF

402

27.4K

1%

R6834

1

2

NO STUFF

MF-LF

0

402

1/16W

5%

R6856

1 2

SYNC_MASTER=K36A_MLB

AUDIO: JACK TRANSLATORS

051-8089

109

68

02

SYNC_DATE=08/29/2008

MAX9890_OUTL

AUD_PORTA_R

=PP5V_S0_AUDIO

=GND_AUDIO_CODEC

AUD_VREF_PORT_B

=PP3V3_S0_AUDIO

MIC_HI

=GND_AUDIO_CODEC

AUD_J1_TIPDET_R

AUD_J1_SLEEVEDET_INV

AUD_J2_DET_RC

=GND_AUDIO_CODEC

AUD_BI_PORT_B_L MAKE_BASE=TRUE

AUD_BI_PORT_B_R

PP3V3_S0_AUDIO_F

AUD_J1_SLEEVEDET_R

AUD_OUTJACK_INSERT_L

AUD_PORTC_R

AUD_PORTA_DET_L

AUD_INJACK_INSERT_L

MAX9890_CEXT

PP3V3_S0_AUDIO_F

AUD_J2_TIPDET_R

PP3V3_S0_AUDIO_F

AUD_PORTA_L

MAX9890_OUTR

AUD_BI_PORT_A_R

AUD_VREF_PORT_A

AUD_BI_PORT_A_L

AUD_PORTE_DET_L

AUD_SENSE_B

PP3V3_S0_AUDIO_F

AUD_SENSE_A

MIC_SHLD_CONN

=GND_CHASSIS_AUDIO_MIC

AUD_J1_DET_RC

AUD_SENSE_A

AUD_J1_SLEEVEDET_R

=GND_AUDIO_CODEC

MIC_LO

=GND_AUDIO_CODEC

VREF_PORT_B_R

=GND_AUDIO_CODEC

AUD_BI_PORT_C_L

AUD_BI_PORT_C_R

AUD_PORTC_L

8

52

9

52 53 54 55

52

8

52 54

9

52 53 54 55

9

52 53 54 55

52

55

54 55

55

9

52 55

9

52 53 54 55

9

52 53 54 55

9

52 53 54 55

9

52 53 54 55

9

52 53 54 55

V-

V+

BI

D

S G

D

S G

G

D

S

N-CHN

G

P-CHN

S

D

IN

NC

FB

BIAS

SW

SHDN*

NC

VIN

BOOST

GND

NC

D

G S

VOID

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

BATTERY/LID CONNECTOR

LID HALL EFFECT SENSOR

APN:516S0620

HFAPN:516S0735

If ADAPTER_SENSE > Vth then turn off FET

Supply needs to guarantee 3.31V delivered to SMC VRef generator

MLB TOP VIEW

Vout = 1.25V * (1 + Ra / Rb)

PIN 1

<Vth>

Vth = Vdcin * (Rb / (Ra + Rb)) Vth = Vdcin / 2

Q6920 used as bilateral switch to ensure

VOLTAGE DIVIDER FROM DCIN ENSURES Q6910 Vgs is met when SYS_ONEWIRE is high or low.

<Ra>

<Rb>

Q6910 restricts system load to 10K-70K window until adapter detects system and enables 16.5V output.

Vgs = 7.30V @ 20V DCIN Vgs = 4.74V @ 13V DCIN

<Ra>

<Rb>

3.425V "G3Hot" Supply

Vgs(max) = 8V

SYS_ONEWIRE doesn’t drive unpowered U6990

Vout = 3.425V

200mA max output

(Switcher limit)

1-Wire OverVoltage Protection

MagSafe DC Power Jack

- COPY THIS PAGE FROM T18 CSA.69

- DO WE NEED TO CHANGE BATTERY CONNECTOR?

518S0656

NCNC

180K

402

1/16W

5%

MF-LF

R6911

1

2

0.001UF

10% 50V

CERM

402

C6910

1

2

MF-LF

5%

1/16W

270K

402

R6917

1

2

402

270K

MF-LF

5%

1/16W

R6915

1

2

0.1UF

X5R

10% 25V

402

C6915

1

2

402

MF-LF

5%

100K

1/16W

R6913

1

2

CRITICAL

6AMP-24V

1206

F6905

1 2

1/16W

5%

MF-LF

470K

402

R6912

1

2

1/16W

5%

MF-LF

270K

402

R6918

1

2

0.001UF

402

50V

10% CERM

C6917

1

2

SOT23-5-HF

CRITICAL

LM397

U6915

2

4

1

3

5

402

24.3K

MF-LF

1% 1/16W

R6920

1

2

603

20% CERM

50V

0.01UF

C6905

1

2

402

MF-LF

100K

1/16W

5%

R6914

1

2

42 41

CRITICAL

SSM6N15FEAPE

SOT563

Q6920

3

5

4

SSM6N15FEAPE

SOT563

CRITICAL

Q6920

6

2

1

NTUD3127CXXG

SOT-963

CRITICAL

Q6910

6

2

1

SOT-963

NTUD3127CXXG

CRITICAL

Q6910

3

5

4

1/16W

5%

MF-LF

1K

402

R6910

1 2

57 42 41

MF-LF

1/16W

5%

402

270K

R6916

1

2

6.3V

20% CERM

805

22UF

C6999

1

2

CDPH4D19FHF-SM

33UH

CRITICAL

L6995

1 2

0.22uF

20% X5R

402

6.3V

C6994

1

2

MF-LF

402

348K

1%

1/16W

R6995

1

2

22pF

5% CERM

402

50V

C6995

1

2

200K

MF-LF

1%

1/16W

402

R6996

1

2

1206-1

X5R

25V

10%

10uF

C6990

1

2

CRITICAL

LT3470ETS8

TSOT23-8

U6990

7

6

8

4

2

1

5

3

47

1/8W

5%

MF-LF

805

R6905

1 2

78048-0573

M-RT-SM

CRITICAL

J6900

1 2 3 4 5

SOT665

HN2D01JEAPE

D6905

1

3

5

4

2

SOD-VESM-HF

SSM3K15FV

CRITICAL

Q6915

3

1

2

120-OHM-0.3A-EMI

0402-LF

L6904

1 2

0.001UF

50V CERM

10%

402

C6942

1

2

0.01uF

16V CERM

10%

402

C6921

1

2

CRITICAL

F-ST-SM

8199-3520-M281

J6950

1

10

1112 1314 1516 1718 19

2

20

34 56 78 9

600-OHM-300MA

0402

L6908

1 2

600-OHM-300MA

0402

L6907

1 2

0402

600-OHM-300MA

L6909

1 2

0.01uF

CERM

16V

10%

402

C6920

1

2

0.001UF

10% 50V CERM 402

C6943

1

2

47pF

50V CERM 402

5%

C6944

1

2

47pF

50V 402

CERM

5%

C6945

1

2

120-OHM-0.3A-EMI

0402-LF

L6903

1 2

0402-LF

120-OHM-0.3A-EMI

L6902

1 2

FERR-50-OHM

SM-LF

L6901

1 2

5%

MF-LF

402

0

1/16W

R6928

1 2

RCLAMP2402B

CRITICAL

SC-75

D6950

3

1

2

69

051-8089

DC-In & Battery Connectors

02

SYNC_MASTER=RAYMOND

109

SYNC_DATE=08/17/2008

PP3V42_G3H_LIDSWITCH_F

GND_SMC_LID_F

VOLTAGE=12.6V

MIN_NECK_WIDTH=0.3 mm

MIN_LINE_WIDTH=0.6 MM

BATT_POS_F

VOLTAGE=18.5V

MIN_NECK_WIDTH=0.20mm

MIN_LINE_WIDTH=0.25mm

PP18V5_DCIN_ONEWIRE

ADAPTER_SENSE_R

=PP18V5_DCIN_CONN

=PP3V42_G3H_REG

P3V42G3H_BOOST

=SMBUS_BATT_SDA

BATT_POS_F

ONEWIRE_DCIN_DIV

ONEWIRE_ESD

SMC_BC_ACOK_RC

SYS_ONEWIRE

SMC_BC_ACOK

SMC_BS_ALRT_L

=SMBUS_BATT_SCL

=PP3V42_G3H_LIDSWITCH

ONEWIRE_EN

SYS_ONEWIRE_BILAT

SMC_LID

P3V42G3H_FB

ONEWIRE_PWR_EN_L

ONEWIRE_PWR_EN_L_DIV

ADAPTER_SENSE

=GND_BATT_CHGND

ONEWIRE_OVERVOLT

P3V42G3H_SW

MIN_NECK_WIDTH=0.25 mm SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.5 mm

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.3 mm VOLTAGE=18.5V

PPDCIN_S5_P3V42G3H

VOLTAGE=18.5V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

PPVIN_G3H_P3V42G3H

MIN_LINE_WIDTH=1mm

VOLTAGE=18.5V

MIN_NECK_WIDTH=0.20mm

PP18V5_DCIN_FUSE

=PP18V5_DCIN_CONN

SMBUS_BATT_SDA_F

SMC_LID_F

SMC_BS_ALRT_L_F

PPVBAT_G3H_CONN_F

SMBUS_BATT_SCL_F

7

56 57

8

56

8

44

56 57

41 42

44

8

41 42 49

7

9

56

9

56

7

8

56

7

GND

VCC

D

SG

D

SG

CSON

CSOP

VNEG

VCOMP

ICOMP

VREF ACIN

SDA

VHST SCL

VDDP

BGATE

VDD

ACOK

THRM_PAD

AGATE

AGND

AMON BMON

BOOT

CSIN

CSIP

DCIN

LGATE

PGND

PHASE

UGATE

TRKL*

D

G

S

D

G

S

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

(CHGR_CSON)

(CHGR_CSO_R_N)

AMON PULLDOWN LOGIC

ACOK pullup/down on SMC page

TO SYSTEM

TO BATTERY

PWM FREQ. = 400KHZ MAX CURRENT = 7 A (??? LIMITED)

NC

(CHGR_CSOP)

(CHGR_ACIN)

BATTERY CHARGING

EMI request

MAX CURRENT = 7A PWM FREQ. = 400 KHZ

PBUS SUPPLY / BATTERY CHARGER

1W MF

0.5%

CRITICAL

0612

0.02

R7020

1

2

1/16W

5%

4.7

MF-LF

402

R7040

1 2

0.1UF

25V X5R 402

10%

C7025

1

2

402-1

X5R

10V

10%

1UF

C7041

1 2

603-1

1UF

25V

10% X5R

C7023

1

2

1UF

25V X5R

10% 603-1

C7022

1

2

CRITICAL

22UF

20% POLY-TANT

25V CASE-D2-SM

C7020

1

2

CRITICAL 22UF

POLY-TANT

20%

CASE-D2-SM

25V

C7021

1

2

402-1

X5R

10%

1UF

10V

C7040

1

2

1UF

402-1

10V

10% X5R

C7047

1

2

10%

0.1UF

402

X5R

25V

C7010

1

2

16V CERM 402

10%

0.01UF

C7044

1

2

1%

1/16W

402

MF-LF

56.2K

R7045

1

2

50V

CERM

10%

402

0.001UF

C7045

1

2

MF-LF

402

1%

1/16W

3.01K

R7046

1

2

10% 402

50V

470PF

CERM

C7046

1

2

SM

XW7000

1 2

0.001UF

50V X7R

10% 402

C7026

1

2

25V

10% X5R

402

0.1UF

C7063

1

2

57.6K

1% 1/16W MF-LF

402

R7060

1

2

1/16W

5%

100K

402

MF-LF

R7099

1 2

100K

5%

1/16W

402

MF-LF

R7098

1

2

SOT23-5

CRITICAL

TL331

U7060

1

3

4

5

2

0.1UF

10% 402

X5R

25V

C7060

1

2

SSM6N15FEAPE

SOT563

Q7070

6

2

1

SSM6N15FEAPE

SOT563

Q7070

3

5

4

SM

XW7021

1 2

SM

XW7020

1 2

402

CERM

10V

10%

0.047UF

C7024

1

2

10

1/16W MF-LF

402

5%

R7021

1 2

MF-LF

5%

10

402

1/16W

R7023

1 2

402

0.1UF

10% 25V X5R

C7061

1

2

402

0.1UF

10% 25V X5R

C7062

1

2

1/16W

402

62K

5%

MF-LF

R7062

1

2

MF-LF

5%

1/16W

402

62K

R7001

1 2

X5R

16V

0.1UF

402

10%

C7043

1 2

MF-LF

1/16W

30.1K

402

1%

R7010

1

2

1% 1/16W MF-LF

402

9.31K

R7011

1

2

5%

1/16W

MF-LF

402

1K

R7073

1

2

MF-LF

402

1/16W

1M

5%

R7074

1

2

NO STUFF

1/16W

402

1M

5%

MF-LF

R7075

1

2

1/16W

MF-LF

402

1.82K

1%

R7061

1

2

RJK0305DPB

CRITICAL

LFPAK-HF

Q7020

5

4

1 2 3

RJK0305DPB

LFPAK-HF

CRITICAL

Q7021

5

4

1 2 3

CRITICAL

1206

7AMP

F7000

1 2

10%

1UF

X5R

25V 603-1

C7011

1

2

16V POLY-TANT CASED2E-SM

CRITICAL

33UF

20%

C7008

1

2

5%

402

10

1/16W MF-LF

R7031

12

1/16W

10

MF-LF

5%

402

R7047

12

QFN

ISL6258A

CRITICAL

U7000

3

14

1

6

26

9

16

15

25

27

28

17

18

2

5

21

22

23

11 10

29

13

24

7

19

20

12

8

4

10% 16V X5R 402

0.033UF

C7042

1

2

CRITICAL

4.7UH-9.5A

IHLP4040DZ-SM

L7000

1 2

LFPAK-SM

HAT1127H

CRITICAL

Q7000

5

4

1 2 3

CRITICAL

LFPAK-SM

HAT1127H

Q7001

5

4

1 2 3

CRITICAL

FDS6681Z

SO-8

Q7050

5 6 7 8

4

1 2

3

50V 402

CERM

20%

0.001UF

C7028

1

2

0.001UF

CERM

402

20% 50V

C7027

1

2

402

0.1UF

16V X5R

10%

C7052

1

2

CRITICAL

FDS6681Z

SO-8

Q7052

5 6 7 8

4

1 2

3

330K

1/16W

402

5%

MF-LF

R7053

1 2

1M

1/16W

402

5%

MF-LF

R7052

1 2

SOD-723-HF

1SS418

D7010

1

2

0.01

0.5%

0612

MF

1W

R7008

1 2 3 4

NO STUFF

CERM

50V

5%

402

100PF

C7090

1

2

402

2.2

5% MF-LF

NO STUFF

1/16W

R7090

1

2

16V 402

10%

0.01uF

CERM

C7050

1

2

0.1UF

402

10% 16V X5R

C7051

1

2

70

051-8089

PBUS Supply/Battery Charger

SYNC_MASTER=K36B_MLB SYNC_DATE=08/17/2008

109

02

GND_CHGR_SGND

=PP3V42_G3H_CHGR

CHGR_VDDP

CHGR_SGATE

CHGR_CSIN CHGR_BGATE

CHGR_CSIP

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM

CHGR_AGATE

CHGR_CSIN_XW7021

CHGR_ACIN

CHGR_PHASE_SNUBBER

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

CHGR_LGATE

CHGR_PHASE

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

GND_CHGR_SGND

CHGR_BOOT

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

CHGR_UGATE

PPVBAT_G3H_CHGR_OUT

=PPBUS_G3H

PP18V5_S5_CHGR_SW_R

CHGR_CSIP_XW7020

GND_CHGR_SGND

CHGR_CSON

CHGR_CSO_R_N

CHGR_CSOP

SMC_BC_ACOK

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM

PPVBAT_G3H_CHGR_REG

CHGR_AMON

PPVBAT_G3H_CHGR_OUT

CHGR_DCIN

CHGR_LOWCURRENT_GATE_MOS

BATT_POS_F

=PP3V42_G3H_CHGR

CHGR_ACOK

CHGR_VDD_L

=SMBUS_CHGR_SDA

CHGR_VNEG_R

CHGR_VDD_R

CHGR_SDA

CHGR_SCL

CHGR_VDD

=SMBUS_CHGR_SCL

BATT_POS_INRUSH

CHGR_BGATE

CHGR_AMON

=PP3V42_G3H_CHGR

CHGR_BMON CHGR_ACOK

CHGR_ICOMP

CHGR_VCOMP_R

CHGR_AMON

=PP18V5_G3H_CHGR

CHGR_DCIN

BATT_POS_GATE

CHGR_LOWCURRENT_GATE

CHGR_LOWCURRENT_REF

PPVDCIN_G3H_PRE2

CHGR_SCL CHGR_SDA

CHGR_VNEG

CHGR_VCOMP

CHGR_VDD

CHGR_CSO_R_P

PPVDCIN_G3H_PRE

57

8

57

8

57

46

42 56 41

46 57

57

56

8

57

44

57

44

57

46 57

8

57

46

57

46 57

8

57

46

Q1

Q2

SW

IN

D

SG

D

SG

S

D

G

S

D

G

DRVH1

SKIPSEL

VBST1

GND

THRM_PAD

ENTRIP1

VFB1

VO1

DRVL1

LL1

EN0

VCLK

ENTRIP2

PGOOD

VO2

VFB2

DRVL2

LL2

DRVH2

VBST2

VREG5

VREG3

VREF

VIN

TONSEL

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

5V_RT/3.3V POWER SUPPLY

Place XW7204 by Pin 2 of L7220.

EMI request

Place XW7205 by C7252.

PWM FREQ. = 375 KHZ

EMI request

ROUTING NOTE:

MAX CURRENT = 4A

ROUTING NOTE:

VOUT = (2 * RC / RD) + 2

NC

SEPERATED MASTER PGOOD FOR BOTH 5V AND 3V3.

Place XW7201 between Pin 15 and Pin 25 of U7200.

NC

ROUTING NOTE:

Place XW7203 by Pin1 OF L7260.

VOUT = (2 * RA / RB) + 2

EMI request

- COPY THIS PAGE FROM K36 CSA.76

EMI request

PWM FREQ. = 300 KHZ

Place XW7202 by C7292.

ROUTING NOTE:

MAX CURRENT = 4A

EMI request

6.3V X5R 603

20%

10UF

C7273

1

2

SM

XW7201

1 2

CRITICAL

MLP

FDMS9600S

Q7220

2349

1

8

56

7

10

64

SOT563

SSM6N15FEAPE

Q7221

6

2

1

SSM6N15FEAPE

SOT563

Q7221

3

5

4

SM

XW7202

12

SM

XW7203

12

SM

XW7205

12

SM

XW7204

12

50V

0.001UF

20% CERM

402

C7230

1

2

0.1UF

10% X5R

402

16V

C7220

12

50V

20% CERM

0.001UF

402

C7231

1

2

50V 402

CERM

20%

0.001UF

C7232

1

2

20% 50V CERM 402

0.001UF

C7233

1

2

100PF

NO STUFF

402

5% 50V

CERM

C7295

1

2

NO STUFF

2.2

1/16W MF-LF 402

5%

R7295

1

2

402

CERM

50V

5%

100PF

NO STUFF

C7294

1

2

402

1/16W

5%

MF-LF

NO STUFF

2.2

R7294

1

2

CRITICAL

CASE-B2-SM

POLY-TANT

6.3V

20%

150UF

C7251

1

2

603

10UF

X5R

6.3V

20%

C7250

1

2

33UF

16V POLY-TANT CASED2E-SM

CRITICAL

20%

C7240

1

2

IHLP

3.3UH

CRITICAL

L7260

1 2

402

MF-LF

1%

6.49K

1/16W

R7270

1 2

1/16W

1% 402

MF-LF

10K

R7269

1 2

603-1

10% 25V

1UF

X5R

C7241

1

2

CASE-B2-SM

POLY-TANT

6.3V

20%

150UF

CRITICAL

C7252

1

2

402

X5R

16V

0.1UF

10%

C7260

12

MF-LF

1% 402

1/16W

15.0K

R7267

1 2

1/16W 402

10K

1% MF-LF

R7268

1 2

603-1

X5R

25V

10%

1UF

C7281

1

2

CRITICAL 33UF

20% POLY-TANT

16V CASED2E-SM

C7280

1

2

CASE-B2-SM

POLY-TANT

6.3V

20%

150UF

CRITICAL

C7292

1

2

20%

6.3V POLY-TANT CASE-B2-SM

CRITICAL 150UF

C7291

1

2

10UF

603

X5R

6.3V

20%

C7290

1

2

PWRPK-1212-8-HF

SI7110DN

CRITICAL

Q7260

5

4

123

4.7UH-5.5A

CRITICAL

IHLP2525CZ

L7220

1 2

CRITICAL

SI7110DN

PWRPK-1212-8-HF

Q7261

5

4

123

QFN

CRITICAL

5V3V3S5_REG5

TPS51125

U7200

21 10

19 12

13

1 6

15

20 11

23

14

25

4

22 9

18

2 5

16

24 7

3

8

17

402

MF-LF

1/16W

75K

1%

R7271

1

2

75K

MF-LF

402

1%

1/16W

R7272

1

2

10%

1UF

X5R

25V 603-1

C7272

1

2

20%

6.3V X5R 603

10UF

C7270

1

2

402

CERM

10V

0.22UF

10%

C7271

1

2

02

109

SYNC_DATE=08/17/2008SYNC_MASTER=K36B_MLB

5V/3.3V SUPPLY

051-8089

72

5VRT_S0_LL_SNUBBER

5VRT_S0_LL

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

VOLTAGE=5V

MIN_LINE_WIDTH=0.30 MM MIN_NECK_WIDTH=0.20 MM

=PP5VRT_S0_REG

5VRT_S0_DRVH

MIN_LINE_WIDTH=0.6 MM

MIN_NECK_WIDTH=0.2 MM

=PPVIN_S0_5VRTS0

5VRT_S0_DRVL

5VRT_S0_VO1

5VRT_S0_ENTRIP

5VRT_S0_VFB

5VRT_S0_VFB_XW7203

5VRTS3_3V3S5_VREF

=P5VRTS0_EN_L

=P3V3S5_EN_L

GND_5VRT3V3S5_SGND

3V3S5_VFB_R7270

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

5VRT_S0_VBST

=PPVIN_S0_5VRTS0

P5V3V3_PGOOD

GND_5VRT3V3S5_SGND

3V3S5_VFB

VOLTAGE=3.3V MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=1.5 mm

=PP3V3_S5_REG

3V3S5_LL_SNUBBER

=PPVIN_S5_3V3S5

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

3V3S5_LL

3V3S5_ENTRIP

5VRT_S0_VO2

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

3V3S5_DRVH

3V3S5_VBST

5V3V3S5_REG3

3V3S5DRVL

8

58

8

58

64

58

8

VDDQSET

S3

COMP

VTT

THRM_PAD

DRVH

LL

PGND

CS_GND

CS

PGOOD

NC1

S5

NC0

GND

VTTGND

MODE

DRVL

VTTREF VLDOIN

VBST V5IN

VDDQSNS

VTTSNSV5FILT

SYM (1 OF 2)

S

D

G

S

D

G

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

EMI request

1.8V/0.9V(DDR2) POWER SUPPLY

VOUT = 0.75V * (1 + RA / RB)

<RA>

<RB>

PWM FREQ. = 400 KHZ

MAX CURRENT = 12A

ROUTING NOTE:

PUT 6 VIAS UNDER THE THERMAL PAD

USING KEVIN CONNECTION.

ROUTING NOTE:

Place XW7303 by C7308.

Pin 3 and Pin 25

ROUTING NOTE:

CONNECT CS_GND TO Q7321 PIN1,2.3

STATE

S0

S5/G3HOT 0.0V

0.0VLOW

LOW

S3

of U7300.

Place XW7300 between

NC

ROUTING NOTE: ROUTING NOTE:

LOW

NC

PM_SLP_S4_L

HIGH HIGH

0.0V

HIGH

1.8V

0.9V

PP0V9_S0PP1V8_S3PM_SLP_S3_L

1.8V

ROUTING NOTE:

Place XW7301 by L7320.

PUT ONE BULK CAP NEXT TO THE LOAD

Place XW7302 by Q7321.

- COPY THIS PAGE FROM K36 CSA.75

TPS51116

QFN

CRITICAL

U7300

6

16

17

21

19

3

20

4 7

12

18

1310

11

25

141522

9

8

23

24

1

5

2

SM-IHLP-1

1.0UH-13A-5.6M-OHM

CRITICAL

L7320

1 2

0

5% 1/16W

402

MF-LF

R7300

1 2

402

X5R

16V

0.1uF

10%

C7309

1

2

20% CASED2E-SM

16V

CRITICAL

33UF

POLY-TANT

C7330

1

2

2.5V

20% POLY-TANT

CASE-D2E-SM

330UF

CRITICAL

C7342

1

2

10UF

X5R 603

20%

6.3V

C7341

1

2

10UF

6.3V

20% 603

X5R

C7302

1

2

1/16W 402

10.7K

1% MF-LF

R7310

1

2

1/16W MF-LF

4.7

5% 402

R7307

1 2

SM

XW7300

1 2

402

1/16W

1%

28K

MF-LF

R7321

1 2

402

MF

1/16W

0.1%

20K

R7322

1 2

NO STUFF

402

5%

100PF

50V CERM

C7303

1 2

10UF

X5R 603

20%

6.3V

C7301

1

2

402

0.033UF

10% 16V X5R

C7340

1 2

X5R-CERM

20%

22UF

6.3V 603

C7307

1

2

20%

6.3V 603

X5R-CERM

22UF

C7308

1

2

402-1

10V X5R

1UF

10%

C7300

1 2

330UF

20%

2.5V

CRITICAL

CASE-C2-SM1

POLY-TANT

C7343

1

2

SI7110DN

CRITICAL

PWRPK-1212-8-HF

Q7320

5

4

1 2 3

CRITICAL

PWRPK-1212-8-HF

SI7108DN

Q7321

5

4

1 2 3

1/16W

402

MF-LF

5%

100K

R7399

1 2

20% 16V POLY-TANT CASED2E-SM

33UF

CRITICAL

C7331

1

2

X5R 603-1

25V

10%

1UF

C7332

1

2

402

0.001UF

20% CERM

50V

C7333

1

2

402

CERM

0.001UF

20% 50V

C7344

1

2

SM

XW7301

1 2

SM

XW7302

1 2

SM

XW7303

1 2

402

50V

CERM

5%

100PF

NO STUFF

C7390

1

2

402

NO STUFF

MF-LF

2.2

1/16W

5%

R7390

1

2

SYNC_DATE=08/17/2008SYNC_MASTER=K36B_MLB

02

109

1.8V/0.9V DDR2 SUPPLY

051-8089

73

=PP0V9_S0_REG

GND_1V8S3_CSGND

=PP3V3_S3_PDCISENS

1V8S3_VBST_RC

=DDRVTT_EN

=DDRREG_EN

=PP5V_S3_1V8S3_0V9S0

1V8S3_VBST

1V8S3_CS

GND_1V8S3_SGND

1V8S3_V5FILT

=PPVTT_S3_DDR_BUF

=PPVIN_S5_1V8S3_0V9S0

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=1 mm

1V8S3_DRVL

1V8S3_VDDQSET

1V5S3_VTTSNS

MIN_LINE_WIDTH=1.5 mm

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.25 mm

=PP1V8_S3_REG

1V8S3_VDDQSNS

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=1 mm

1V8S3_DRVH

MIN_LINE_WIDTH=1 mm

1V8S3_LL

MIN_NECK_WIDTH=0.25 mm

DDRREG_PGOOD

1V8S3_LL_SNUBBER

8

26 65

64

8

27

8

IN

OUT

IN

VID0

DPRSTP*

NC

VW

COMP

FB

FB2

RBIAS

VR_TT* NTC

VR_ON PGOOD

PSI*

RTN

VSEN

DFB

DROOP

VO

OCSET

VSUM

ISEN2

VID1

VID3 VID2

VID4

VID5

VID6

PGND2

VIN VDD

PVCC

LGATE2

PHASE2

UGATE2

ISEN1

PGND1

LGATE1

UGATE1

PHASE1

BOOT1 BOOT2

3V3

VDIFF

SOFT

DPRSLPVR

TPAD

GND

CLK_EN*

IMON

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

OPERATION MODE

- COPY THIS PAGE FROM K36 CSA.71

(NC)

FROM SMC

(IMVP6_VSUM)

ERT-J1VR103J

(IMVP6_VW)

(IMVP6_VO)

PWM FREQ. = 300 KHZ

MAX CURRENT = 44A

LOAD LINE SLOPE = -2.1 MV/A

ERT-J0EV474J

DPRSLPVR

DCR=0.8MOHM

MIN_NECK_WIDTH

(IMVP6_COMP)

(IMVP6_ISEN2)

2-PHASE CCM

DCR=0.8MOHM

MPC1055LR36

0

1

PSI*

0

1

0 1

DPRSTP*

0

0 0

1

MPC1055LR36

MIN_NECK_WIDTHMIN_LINE_WIDTH

(GND)

1-PHASE DCM

1-PHASE CCM

(IMVP6_FB)

(IMVP6_VO)

R1100/R1101 **ON THE CPU PAGE** PROTECT THE IMVP6 IF THE CPU IS NOT INSTALLED

EMI request

(IMVP6_PHASE1)

(IMVP6_ISEN1)

(IMVP6_PHASE2)

LATEST ISSUE: 2007/01/23

MIN_LINE_WIDTH

1

IMVP6 CPU VCORE REGULATOR

NOTE 1: C7432,C7433 = 27.4 OHM FOR VALIDATING CPU ONLY.

(GND)

EMI request

0.0022UF

NO STUFF

CERM

10% 50V

402

C7400

1

2

OMIT

SM

XW7400

1

2

402

MF-LF

1% 1/16W

10K

R7400

1 2

3.65K

1/16W MF-LF 402

1%

R7401

1

2

0.1UF

X5R

16V 402

10%

C7415

1

2

402

1/16W MF-LF

1%

13.7K

R7416

1

2

69 14 10

10

41

26

402

MF-LF

1/16W

11K

1%

R7415

1

2

MF-LF

1%

10K

1/16W 402

R7405

1 2

402

6.3V CERM-X5R

10%

0.22uF

C7404

1 2

1/16W 402

3.65K

1% MF-LF

R7443

1

2

MPC1055-SM

CRITICAL

0.36UH-30A-0.80MOHM

L7401

1 2

CRITICAL

MPC1055-SM

0.36UH-30A-0.80MOHM

L7400

1 2

402

CERM

50V

10%

NO STUFF

0.0022UF

C7402

1

2

X5R

16V

10%

402

0.1UF

C7427

1

2

1/16W

5% MF-LF

402

10

R7420

1 2

402

MF-LF

5% 1/16W

10

R7412

1 2

402

10%

1UF

CERM

6.3V

C7426

1

2

402

CERM

10% 16V

0.01UF

C7496

1

2

5% 1/16W MF-LF

10

402

R7421

1 2

X5R

16V

10%

402

0.1uF

C7430

1

2

1/16W

NO STUFF

402

1K

MF-LF

1%

R7413

1 2

1K

MF-LF

1/16W

1%

402

R7409

1

2

1/16W

255

MF-LF

1%

402

R7411

1

2

CERM

50V

470PF

402

10%

C7414

1

2

97.6K

MF-LF

1/16W

1%

402

R7414

1

2

25V

220PF

5%

402

CERM

C7413

1

2

0.001UF

10% CERM

50V 402

C7407

1

2

6.81K

1% 1/16W MF-LF 402

R7410

1

2

1%

402

MF-LF

1/16W

4.42K

R7417

1 2

402

1% MF-LF

1/16W

1K

R7418

1

2

50V

180pF

CERM 402

5%

C7429

1

2

CERM-X5R

0.22UF

10%

6.3V 402

C7428

1

2

402

CERM

10V

10%

0.068UF

C7431

1 2

NO STUFF

402

CERM

16V

10%

0.01UF

C7432

1 2

X7R 402

10% 16V

0.018UF

C7433

1 2

5%

0

1/16W MF-LF 402

R7422

1

2

0

5% 1/16W

402

MF-LF

R7423

1

2

0.12UF

CERM-X5R

10.0V 402

10%

C7434

1

2

6.3V X5R

20%

603

10UF

C7435

1

2

NO STUFF

MF-LF

1%

402

4.02K

1/16W

R7427

1 2

NO STUFF

10%

402

16V CERM

0.01uF

C7410

1 2

0.015uF

16V

10%

402

X7R

C7405

1 2

147K

1% 1/16W MF-LF 402

R7408

1 2

0.001UF

50V CERM 402

10%

C7406

1

2

CERM 402

10% 50V

0.001UF

NO STUFF

C7416

1

2

3.92K

1/16W MF-LF

1%

402

R7430

1

2

CERM-X5R

10%

6.3V 402

0.22uF

C7421

1 2

0.22uF

6.3V 402

CERM-X5R

10%

C7403

1 2

1

5%

402

MF-LF

1/16W

R7404

1 2

402

MF-LF

1/16W

1

5%

R7407

1 2

10KOHM-5%

0603-LF

CRITICAL

R7431

1

2

69 21

MF-LF 402

1/16W

1%

499

R7445

1

2

NO STUFF

CRITICAL

402

470K

R7426

1 2

402

0

5% 1/16W MF-LF

R7425

1 2

402

MF-LF

1/16W

5%

0

R7424

1 2

0

5%

402

MF-LF

1/16W

NO STUFF

R7406

1 2

POLY-TANT CASED2E-SM

20%

CRITICAL

16V

33UF

C7409

1

2

CRITICAL

POLY-TANT CASED2E-SM

33UF

16V

20%

C7417

1

2

16V POLY-TANT

20%

33UF

CRITICAL

CASED2E-SM

C7401

1

2

CRITICAL

CASED2E-SM

POLY-TANT

16V

20%

33UF

C7408

1

2

603-1

X5R

1UF

25V

10%

C7418

1

2

X5R

10% 25V

1UF

603-1

C7411

1

2

CRITICAL

RJK0305DPB

LFPAK-HF

Q7400

5

4

1 2 3

LFPAK-HF

RJK0328DPB

CRITICAL

Q7401

5

4

1 2 3

LFPAK-HF

CRITICAL

RJK0305DPB

Q7402

5

4

1 2 3

CRITICAL

LFPAK-HF

RJK0328DPB

Q7403

5

4

1 2 3

QFN

ISL9504BCRZ

CRITICAL

U7400

48

36 26

47

10

17

45

46

16

11

12

21

3

24

23

32

30

25

6

8

33

29

1

34

28

2

31

4

15

7

49

35

27

22

13

37

38

39

40

41

42

43

20

18

44

5

14

19

9

46

10K

1%

1/16W

MF-LF

402

NO STUFF

R7452

1 2

MF-LF

1%

10K

402

1/16W

NO STUFF

R7451

1 2

402

5%

MF-LF

1/16W

2.0K

R7447

1

2

50V

0.001UF

20% 402

CERM

C7420

1

2

CERM

402

20%

0.001UF

50V

C7419

1

2

CERM

20%

0.001UF

50V 402

C7422

1

2

50V

0.001UF

20%

CERM

402

C7423

1

2

100PF

402

5% 50V

CERM

NO STUFF

C7491

1

2

402

1/16W

NO STUFF

MF-LF

5%

2.2

R7491

1

2

100PF

402

5% 50V

CERM

NO STUFF

C7490

1

2

2.2

5%

MF-LF

1/16W 402

NO STUFF

R7490

1

2

IMVP6 CPU VCore Regulator

SYNC_DATE=08/17/2008

109

02

SYNC_MASTER=K36B_MLB

051-8089

74

IMVP6_PHASE2_SNUBBER

IMVP6_ISEN1

IMVP6_SOFT

IMVP6_COMP

CPU_VCCSENSE_P CPU_VCCSENSE_N

1.5 MM

0.25 MM

IMVP6_PHASE1 IMVP6_BOOT1

0.25 MM 0.25 MM

1.5 MM

0.25 MM

IMVP6_LGATE1

=PP5V_S0_CPU_IMVP

IMVP6_LGATE1

=PPVIN_S5_CPU_IMVP

IMVP6_PHASE1

IMVP6_PHASE1_SNUBBER

=PPVCORE_S0_CPU_REG

IMVP6_VDIFF

CPU_VCCSENSE_P

0.20 MM0.25 MM

IMVP6_FB

0.20 MM0.25 MM

IMVP6_COMP

0.25 MM0.25 MM

IMVP6_VW

0.20 MM

IMVP6_OCSET

0.25 MM

0.50 MM 0.20 MM

GND_IMVP6_SGND

0.25 MM 0.20 MM

IMVP6_VO

0.20 MM0.25 MM

IMVP6_DROOP

0.20 MM0.25 MM

IMVP6_DFB

IMVP6_VSUM

0.20 MM0.25 MM

IMVP6_VDIFF

0.20 MM0.25 MM

IMVP6_RBIAS

0.20 MM0.25 MM

IMVP6_SOFT

0.25 MM 0.25 MM

IMVP6_PHASE2

0.25 MM0.25 MM

IMVP6_ISEN1

0.25 MM

1.5 MM

IMVP6_UGATE1

0.20 MM

IMVP6_FB2

0.25 MM

IMVP6_BOOT2

0.25 MM0.25 MM

IMVP6_LGATE2

0.25 MM 0.25 MM

IMVP6_UGATE2

0.25 MM0.25 MM

IMVP6_RTN

0.25 MM0.25 MM

0.25 MM

IMVP6_VSEN

0.25 MM

IMVP6_ISEN2

0.25 MM0.25 MM

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM

PP3V3_S0_IMVP6_3V3

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM

PPVIN_S5_IMVP6_VIN

MIN_LINE_WIDTH=0.25 MM VOLTAGE=5V

PP5V_S0_IMVP6_VDD

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=0 V

GND_IMVP6_SGND

CPU_VID<6>

IMVP6_NTC

IMVP6_VSEN

IMVP6_RTN

IMVP6_VW

IMVP6_FB

IMVP6_RBIAS

IMVP6_VO_R

IMVP6_BOOT1 IMVP6_BOOT2

PM_DPRSLPVR

IMVP6_VR_TT

IMVP_DPRSLPVR

IMVP6_IMON

VR_PWRGOOD_DELAY

IMVP6_NTC_R

=PPVIN_S5_CPU_IMVP

CPU_VID<5>

IMVP6_BOOT1_RC

IMVP6_COMP_RC

CPU_PROCHOT_L

IMVP_VR_ON

IMVP6_VDIFF_RC

IMVP6_BOOT2_RC

CPU_VID<4> CPU_VID<3>

CPU_VID<0>

CPU_DPRSTP_L

CPU_PSI_L

CPU_VID<1>

CPU_VID<2>

IMVP6_FB2

=PP3V3_S0_IMVP

=PPVIN_S5_CPU_IMVP

CPU_VCCSENSE_N

GND_IMVP6_SGND

IMVP6_UGATE1

IMVP6_UGATE2 IMVP6_PHASE2 IMVP6_LGATE2

IMVP6_ISEN2

IMVP6_VO

IMVP6_OCSET

IMVP6_VSUM

IMVP6_DFB

IMVP6_DROOP

60

11 60 69

60

8

60

8

60

8

60

11 60 69

60

11 69

60 60

60

69

8

60

11 69

10 14 42 69

11 69

60

8

60

11 60 69

60

D

SG

D

SG

LDOREFIN

LDO

PGND

GND

TONSEL

EN_LDO V5DRV1

VBST1

DRVL1

VSW

EN1

LL1

DRVH1

VOUT1

TRIP1 SKIPSEL

VBST2 DRVH2

LL2 DRVL2 VOUT2

EN2

THRM_PAD

VIN

VFB1

TRIP2

REFIN2

PGOOD2

PGOOD1

VREF2

V5DRV

VREF3

V5FILT

IN OUT OUT IN

IN IN IN

S

D

G

S

D

G

D

G S

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Vout = See below MAX CURRENT : 11A

(MCPCORES0_LGATE)

<Re>

EMI request

<Rd>

<Ra>

L7560 changed from T18 MLB inductor to 152S0782.

Changed R7514 to 280K, R7564 to 180K.

MCP VCORE/5V_S3 LEFT REGULATOR

FREQ = 300 KHZ

(MCPCORES0_UGATE)

from PVCC to VCC)

REGULATE TO AFTER SENSE RES

<Rb>

(Internal 10-ohm path

(SGND)

Max load 100mA

Max load 50uA

C7568 NEEDS TO BE PLACE CLOSE TO LOAD SIDE

Vout = 2.0V * Req / (Ra + Req) Req = Rb || Rc || Rd || Re

M97 DIFFERENCES FROM LAST SYNC ON 12/05/07 TO T18 MLB:

Tied TON to REF.

Changed Q7565 to 376S0637.

Added C7568 bulk cap on output.

Changed Q7510 to 376S0674. C7500 changed to 138S0638.

VID<2:0> Voltage Voltage MCP Target

Rev A01 Production

000 +1.224V +1.060V +1.05V 001 +1.159V +0.994V +1.00V

010 +1.101V +0.937V +0.95V 011 +1.049V +0.885V +0.90V

111 +0.876V +0.719V +0.70V

100 +0.995V +0.830V +0.85V 101 +0.952V +0.789V +0.80V 110 +0.913V +0.752V +0.75V

PLACE C7565 AND C7568 ONE CLOSE TO U7500 AND ANOTHER CLOSE TO MCP.

- SYNC WITH T18

Vout = 0.7V * (1 + Ra / Rb)

<Ra>

CONNECTING IT TO AFTER SENSE RESISTOR INSTEAD OF BEFORE

(MCPCORES0_PHASE)

- COPY THIS PAGE FROM T18 CSA.75

(P5VLTS3_UGATE)

EMI request

(P5VLTS3_PHASE)

(P5VLTS3_BOOT)

(P5VLTS3_LGATE)

(=PP5VLT_S3_REG)

(=P5VLTS3_EN)

FREQ = 400 KHZ

VOUT = 5V

7A MAX OUTPUT

(Q7510 LIMIT)

TDP: 5.2A

50V CERM

10%

0.0027UF

402

C7569

1

2

25V

10%

1UF

603-1

X5R

C7561

1

2

20% 16V

33UF

CRITICAL

CASED2E-SM

POLY-TANT

C7560

1

2

CRITICAL

LFPAK-HF

RJK0305DPB

Q7560

5

4

1 2 3

402

CERM

6.3V

1UF

10%

C7501

1

2

10UF

603

4V

20% X5R

C7566

1

2

330UF

2.5V CASE-C2-SM

POLY-TANT

20%

CRITICAL

C7565

1

2

10UF

20%

603

X5R

4V

C7567

1

2

CRITICAL

LFPAK-HF

RJK0328DPB

Q7565

5

4

1 2 3

110K

0.1%

MF 402

1/16W

R7582

1

2

SSM6N15FEAPE

SOT563

Q7580

6

2

1

10V 603

0.22UF

5%

CERM-X7R

C7564

1

2

237K

0.1%

MF 402

1/16W

R7581

1

2

SOT563

SSM6N15FEAPE

Q7580

3

5

4

475K

0.1%

MF 402

1/16W

R7580

1

2

10V

0.1UF

20%

402

CERM

C7592

1

2

402

10V

0.1UF

20%

CERM

C7591

1

2

10V

0.1UF

20%

402

CERM

C7590

1

2

402

6.3V

4.7UF

20% X5R-CERM

C7502

1

2

CERM

10%

6.3V

402

1UF

C7503

1

2

0.1%

MF

402

1/16W

48.7K

R7570

1

2

0.1%

MF

1/16W

54.9K

402

R7571

1

2

180K

5%

MF-LF

1/16W

402

R7530

1

2

CRITICAL

QFN

SN0802043

U7500

15

26

18

23

14

27

4

21

7 8

16

25

22

13 28

32

29

33

2

12

31

19203

17

24

11

6

10

30

1

5

9

0.1UF

CERM 402

20% 10V

C7530

1

2

SM

XW7500

1 2

402

5%

MF-LF

1/16W

7.5K

R7591

1 2

MF-LF

5%

1/16W

402

7.5K

R7590

1 2

MF-LF

5%

402

1/16W

7.5K

R7592

1 2

X5R

25V

805

10UF

10%

C7500

1

2

1UF

25V

603-1

10% X5R

C7511

1

2

POLY-TANT

CRITICAL

16V

33UF

20%

CASED2E-SM

C7510

1

2

X7R 603-1

50V

10%

0.1UF

C7514

1

2

PLACEMENT_NOTE=Place next to C7516

SM

XW7501

1

2

50V

5%

100PF

CERM

402

NO STUFF

C7520

1

2

MF-LF

NO STUFF

402

1% 1/16W

61.9K

R7521

1

2

MF-LF

1/16W

5%

0

402

R7522

1

2

64

21

10UF

X5R

20%

805

10V

C7516

1

2

CRITICAL

SI7110DN

PWRPK-1212-8-HF

Q7510

5

4

123

POLY-TANT

6.3V

20%

150UF

CRITICAL

CASE-B2-SM

C7517

1

2

CRITICAL

150UF

POLY-TANT

6.3V

20%

CASE-B2-SM

C7515

1

2

1/16W

402

MF-LF

5%

180K

R7520

1

2

3.3UH

IHLP

CRITICAL

L7520

1 2

CRITICAL

SI7110DN

PWRPK-1212-8-HF

Q7511

5

4

123

SSM3K15FV

SOD-VESM-HF

Q7582

3

1

2

0.001UF

20%

CERM

50V

402

C7518

1

2

CERM

402

0.001UF

50V

20%

C7512

1

2

0.001UF

20% 402

CERM

50V

C7562

1

2

0.001UF

20% 50V CERM 402

C7570

1

2

330UF

20% POLY-TANT

2.5V CASE-C2-SM

CRITICAL

C7568

1

2

402

6.3V

10%

1UF

CERM

C7504

1

2

1.0UH-13A-5.6M-OHM

SM-IHLP-1

CRITICAL

L7500

1 2

5%

NO STUFF

CERM

100PF

50V 402

C7596

1

2

2.2

402

1/16W

NO STUFF

MF-LF

5%

R7596

1

2

NO STUFF

CERM

50V

5%

402

100PF

C7595

1

2

1/16W

402

NO STUFF

MF-LF

5%

2.2

R7595

1

2

75

051-8089

MCP VCORE REGULATOR

109

02

SYNC_DATE=08/17/2008SYNC_MASTER=K36B_MLB

GATE_NODE=TRUE

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

P5VLTS3_UGATE

P5VLTS3_LGATE

MIN_NECK_WIDTH=0.2MM GATE_NODE=TRUE

MIN_LINE_WIDTH=0.6MM

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

P5VLTS3_BOOT

=PP5VLT_S3_REG

P5VLTS3_PHASE_SNUBBER

SWITCH_NODE=TRUE MIN_LINE_WIDTH=0.6MM

MIN_NECK_WIDTH=0.2MM

P5VLTS3_PHASE

P5VLTS3_VSNS

P5VLTS3_FB

=P5VLTS3_EN

=PPVIN_S0_MCPCORES0

PP5V_S3_MCPREG_LDO

P5VLTS3_ILIM

=PPVIN_S0_MCPREG_VIN

MCP_VID2_RC

PP5V_S0_MCPREG_VCC

MCPREG_VREF3

=PPVCORE_S0_MCP

MCP_VID1_RC

MCP_VID0_L

P5V_LT_S3_PGOOD

MCPCORES0_ILIM

MCP_VID0_RC

MCP_VID<1>

VOLTAGE=5V

PP5V_S3_MCPREG_LDO

VOLTAGE=5V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

PP5V_S0_MCPREG_VCC

MCP_VID<2>

MCP_VID<0>

=MCPCORES0_EN

MCPCORES0_PGOOD

MIN_NECK_WIDTH=0.25MM

=PPVIN_S3_5VLTS3

MIN_LINE_WIDTH=0.5MM

VOLTAGE=12.6V

MCP_VID2_L

MCPCORES0_PHASE_SNUBBER

MIN_NECK_WIDTH=0.2 MM SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.5 MM

MCPCORES0_PHASE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM GATE_NODE=TRUE

MCPCORES0_UGATE

=PPMCPCORE_S0_REG

MCPCORES0_BOOT

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM GATE_NODE=TRUE

MCPCORES0_LGATE

VOLTAGE=2V

PP2V_S0_MCPREG_REF

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0V

GND_MCPREG_SGND

ISNS_PVCORES0MCP_N

MCP_VID1_L

MCPCORES0_REFIN

8

61

8

61

8

22 24 46

61

8

46

S

D

G

S

D

G

THRM_PAD

VFB

TRIP

VOUT

EN_PSV

GND

PGND

V5DRV

V5FILT

DRVL

DRVH

LL

TON

VBST

PGOOD

SYM (2 OF 2)

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

8A max output F = 400 KHZ

EMI request

CPUVTT POWER SUPPLY

EMI request

<Rb>

<Ra>

Vout = 0.75V * (1 + Ra / Rb)

Place XW7601 by C7660.

ROUTING NOTE:

Vout = 1.052V

(=PPCPUVTT_S0_REG)

ROUTING NOTE:

(CPUVTTS0_VFB)

(GND)

(=PPCPUVTT_S0_REG)

Place XW7600 between Pin 7 and Pin 15 of U7600.

SI7110DN

PWRPK-1212-8-HF

CRITICAL

Q7620

5

4

1 2 3

PWRPK-1212-8-HF

SI7108DN

CRITICAL

Q7621

5

4

1 2 3

CRITICAL

2.5V

CASE-C2-SM

330UF

POLY-TANT

20%

C7660

1

2

603

10UF

6.3V

20% X5R

C7665

1

2

PLACEMENT_NOTE=Place XW7665 next to L7620

SM

XW7665

1

2

NO STUFF

CERM

402

50V

5%

100PF

C7670

1

2

1/16W MF-LF

8.45K

402

1%

R7670

1

2

20.0K

MF-LF

1% 1/16W

402

R7671

1

2

187K

1/16W

1%

MF-LF

402

R7603

1

2

X5R

25V

10%

603-1

1UF

C7695

1

2

POLY-TANT

CASED2E-SM

16V

20%

CRITICAL

33UF

C7630

1

2

603-1

0.1UF

10%

X7R

50V

C7603

1

2

603

X5R-CERM

6.3V

4.7UF

10%

C7604

1

2

TPS51117RGY_QFN14

QFN

CRITICAL

U7600

13

9

1

7

12

8

6

15

2

11

10

4

14

5

3

SM

XW7600

1 2

402-1

10V

1UF

X5R

10%

C7601

1

2

64

6.65K

1/16W

1%

MF-LF 402

R7604

1

2

301

1%

MF-LF

402

1/16W

R7601

1 2

20% 402

CERM

0.001UF

50V

C7696

1

2

402

CERM

20%

0.001UF

50V

C7661

1

2

CRITICAL

SM-IHLP-1

1.0UH-13A-5.6M-OHM

L7620

1 2

SM

XW7601

1

2

NO STUFF

CERM

402

100PF

50V

5%

C7690

1

2

2.2

5%

MF-LF

NO STUFF

1/16W 402

R7690

1

2

SYNC_DATE=08/17/2008

109

02

SYNC_MASTER=K36B_MLB

CPU VTT(1.05V) SUPPLY

051-8089

76

MIN_NECK_WIDTH=0.2 mm

PP5V_S0_CPUVTTS0_V5FILT

VOLTAGE=5V

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

CPUVTTS0_VBST

=CPUVTTS0_EN

CPUVTTS0_PGOOD

CPUVTTS0_TRIP

CPUVTTS0_TON

VOLTAGE=0V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

GND_CPUVTTS0_SGND

CPUVTT_VOUT

CPUVTTS0_VSNS

CPUVTTS0_VFB

CPUVTTS0_LL_SNUBBER

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

CPUVTTS0_LL

=PPVIN_S0_CPUVTTS0

=PP5V_S0_CPUVTTS0

=PPCPUVTT_S0_REG

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

GATE_NODE=TRUE

CPUVTTS0_DRVL

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

CPUVTTS0_DRVH

8

65

THRM_PAD

PVINAVIN

PG

MODE

OVT FB

AGND PGND

SWEN

SW

RUN VFB

GND

VIN

THRM_PAD

PVINAVIN

PG

MODE

OVT FB

AGND PGND

SWEN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

<Rb>

<Ra>

<Rb>

VOUT = 0.6V * (1 + Ra / Rb)

FireWire 1.0V (Core) Supply

1.5V S0 SWITCH

FREQ = 1MHZ

<Ra>

f = 2.25 MHz

MAX Current = 1.5A

VOUT = 1.5V MAX CURRENT = 1.5A

<Ra>

Vout = 1.05V

VOUT = 0.6V * (1 + Ra / Rb)

300mA max output (Switcher limit)

Vout = 0.8V * (1 + Ra / Rb)

<Rb>

Vout = 1.001V

FREQ = 1MHZ

MCP 1.05V_S5 AUXC SUPPLY

BQA

TPS62510

CRITICAL

U7750

3

9

6

4

7

5

8

2

10

1

11

0.1UF

16V 402

X5R

10%

C7781

1

2

1

5% 1/16W MF-LF 402

R7722

1

2

CRITICAL

CERM

6.3V

20%

22UF

805

C7720

1

2

402

CERM

50V

5%

22PF

C7782

1

2

2.2UH-3.25A

CRITICAL

1V05S5_SW

IHLP1616BZ-SM

L7720

1 2

392K

1/16W

MF-LF

1%

402

R7781

1

2

SM

XW7700

1 2

402

MF-LF

1/16W

1%

301K

R7780

1

2

22UF

20%

6.3V CERM 805

CRITICAL

C7783

1

2

6.3V

20%

4.7UF

402

X5R-CERM

C7710

1

2

CRITICAL

PCAA031B-SM

4.7UH-0.8A

L7710

1 2

200K

1/16W MF-LF

1%

402

R7713

1

2

CRITICAL

LTC3410ESC6

SC70

U7780

25

1

3

6

4

50V

22pF

5%

CERM

402

C7712

1

2

402

MF-LF

1% 1/16W

52.3K

R7712

1

2

6.3V X5R-CERM

4.7UF

20%

402

C7715

1

2

1% MF-LF

402

1/16W

301K

R7740

1

2

20% CERM

22UF

805

6.3V

C7743

1

2

200K

1% 1/16W MF-LF 402

R7741

1

2

BQA

CRITICAL

TPS62510

U7740

3

9

6

4

7

5

8

2

10

1

11

X5R

16V

10%

0.1UF

402

C7741

1

2

MF-LF

1/16W

5%

1

402

R7742

1

2

CERM

50V 402

5%

22PF

C7742

1

2

SM

XW7740

1 2

20%

22UF

805

CERM

6.3V

C7740

1

2

64

CRITICAL

IHLP1616BZ-SM

2.2UH-3.25A

L7740

1 2

77

051-8089

MISC POWER SUPPLIES

109

02

SYNC_MASTER=K36B_MLB SYNC_DATE=08/17/2008

1V5S0_AVIN

P1V5_S0_PGOOD

MODE_GND

P1V0FW_SW

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm SWITCH_NODE=TRUE

=PP3V3_FW_P1V0FW

=PP1V0_FW_REG

P1V0FW_VFB

1V5S0_SW

=P1V05_S5_EN

1V5S0_FB

=PP3V3_S5_P1V05S5

1V05S5_AVIN

=PP3V3_S0_FET

1V05S5_SGND

P1V05_S5_PGOOD

1V05S5_FB

=PP1V05_S5_REG

=PP1V5_S0_FET

=P1V5S0_EN

8

64

8

65

8

64

OUT

D

G S

D

G S

OUT

Y

B

A

OUT

IN

OUT

SENSE

CT

VDD

GND

RESET*

MR*

IN

ADJ1

SEL

ADJ2

REF

VCC

TMR

GND

THRM_PAD

RST*

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Unused PGOOD signal

Power Control Signals

(PM_SLP_S3_L_BUF)

(PM_SLP_S3_L)

LTC2901 THRESHOLD IS 95% (4.75V, 3.136V)

TIE TMR TO GND

S3 ENABLE

TRST = 200MS

NC

1.5V 1.05V COMPARED TO 0.5V

LAYOUT_NOTE: ADD XW IF NEEDS TO SAVE SPACE FOR PIN2,10,1,9

5.0V (RIGHT AND LEFT), 3.3V AND 1.5V S0 RAILS MONITOR CIRCUIT

NEED TO CHANGE SIMBOL

(PM_SLP_S3_L)

(PM_S4_STATE_L)

TPS3808 MR* HAS INTERNAL PULLUP

5VLT_S0, 3.3V_S0, 1.8V_S0 ENABLE

MCPDDR, CPUVTT,MCPCORES0 ENABLE

1.5V S0 AND 1.05V S0 ENABLE

(S0PGOOD_PWROK)

OTHER S0 RAILS PGOOD

3.3V 1.05V S5 ENABLE

58

402

CERM

20%

0.1UF

NO STUFF

10V

C7858

12

SSM3K15FV

SOD-VESM-HF

Q7813

3

1

2

SOD-VESM-HF

SSM3K15FV

Q7800

3

1

2

100K

5%

MF-LF

402

1/16W

R7802

12

41 26

7

1/16W

5%

MF-LF

402

68K

R7813

12

NO STUFF

0.068UF

10% 10V CERM 402

C7813

1

2

NO STUFF

TC7SZ08AFEAPE

SOT665

U7859

2

1

3

5

4

402

CERM

10V

10%

0.068UF

NO STUFF

C7802

1

2

5%

1/16W

402

5.1K

MF-LF

R7801

12

63

61

0

1/16W

5%

MF-LF 402

R7812

1 2

0.47UF

NO STUFF

CERM-X5R

6.3V

402

10%

C7812

1 2

61

402

MF-LF

5%

100K

1/16W

R7840

1

2

TPS3808G33DBVRG4

SOT23-6

U7840

4

2

3

15

6

402

10V

CERM

20%

0.1uF

C7840

1

2

20%

402

50V

CERM

0.001UF

C7841

1

2

CERM-X5R 402

6.3V

10%

0.47UF

C7801

1

2

58

LTC2909

DFN

U7870

8 7

5

6

4

1

9

2

3

10V

CERM

402

20%

0.1uF

C7870

1

2

1/16W MF-LF

402

5%

100

R7859

12

58

39

63

65

5% 1/16W MF-LF

100K

402

R7800

1

2

41

42 41 21

5%

402

1/16W

5.1K

MF-LF

R7811

1 2

0.47UF

6.3V

402

10%

CERM-X5R

C7810

1 2

59

45

1/16W

100K

5%

402

MF-LF

R7810

1

2

63

402

5.1K

5% 1/16W MF-LF

R7883

1

2

402

0

MF-LF

1/16W

5%

R7882

1

2

33K

5% 1/16W MF-LF

402

R7881

1

2

1/16W

5%

402

MF-LF

22K

R7880

1

2

0.47UF

CERM-X5R

6.3V

402

10%

C7883

1

2

0.47UF

10%

6.3V CERM-X5R 402

NO STUFF

C7882

1

2

10%

6.3V

402

CERM-X5R

0.47UF

C7881

1

2

0.47UF

CERM-X5R 402

6.3V

10%

C7880

1

2

62

41 36 33 21

100K

1/16W

5%

MF-LF

402

R7879

1

2

61

MF-LF

10K

402

1/16W

5%

R7820

1

2

61

62

65

109

02

SYNC_DATE=08/17/2008SYNC_MASTER=K36B_MLB

POWER SEQUENCING

051-8089

78

CPUVTTS0_PGOOD

P5V_LT_S3_PGOOD

MCPCORES0_PGOOD

P5V3V3_PGOOD

P1V5_S0_PGOOD

S0PGOOD_PWROK

=PP3V3_S0_PWRCTL

PM_SLP_S3_L

=P5VRTS0_EN_L

=PP3V42_G3H_PWRCTL

SMC_PM_G2_EN

=PBUSVSENS_EN

=P3V3S0_EN

=PP3V3_S5_PWRCTL

=PP3V42_G3H_PWRCTL

=P5VLTS3_EN

=MCPCORES0_EN

=USB_PWR_EN

=DDRREG_EN

ENETLV_PGOOD

=P3V3S5_EN_L

=CPUVTTS0_EN

=PP1V8_S0_VMON

=PP3V42_G3H_PWRCTL

=PP1V05_S0_VMON

=P1V05_S5_EN

=MCPDDR_EN

=P1V5S0_EN

=PP3V3_S0_VMON

P1V05_S5_PGOOD

RSMRST_PWRGD

CT

=PP3V3_S5_PWRCTL

=P3V3S3_EN

MAKE_BASE=TRUE

ALL_SYS_PWRGD

MAKE_BASE=TRUE

PM_G2_P3V3S5_EN_L

MAKE_BASE=TRUE

PM_SLP_S4_L

MAKE_BASE=TRUE

TP_ENETLV_PGOOD

MAKE_BASE=TRUE

PM_G2_P1V05S5_EN

P5VLTS3_EN

MAKE_BASE=TRUE

DDRREG_EN

MAKE_BASE=TRUE

PM_SLP_S3_L_INVERT

MAKE_BASE=TRUE

MCPCORES0_EN

MAKE_BASE=TRUE

P1V8S0_EN

MAKE_BASE=TRUE

CPUVTTS0_EN

MAKE_BASE=TRUE

MCPDDR_EN

PM_SLP_S3_L_BUF

MAKE_BASE=TRUE

8

64

8

64

8

64

8

64

8

63

41

8

64

IN

D

S

G

D

SG

D

SG

IN

D

SG

D

SG

IN

D

G S

D

G S

SGD

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

3.3V S3 FET

ON VTT RAIL, WHICH PULLS ALL CKE SIGNALS LOW THROUGH VTT TERMINATION RESISTORS.

1.8V S0 FET

(1.8V S0 FET FOR DDR2 MEM)

LOADING

RDS(ON)

N-TYPE

1.8V S0 FET

CKT FROM T18

MEM_VTT_EN OUTPUT FROM MCP79 USED TO ENABLE CLAMP

90mA max load @ 0.9V

81mW max power

MCP79 DDR PAD LEAKAGE IS HIGH ENOUGH THAT

5A (EDP)

15 MOHM @4.5V VGS

FDM6296G

CHANNEL

MOSFET

.

1.431 A (EDP)

26 MOHM @4.5V

FDC606P

P-TYPE

3.3V S0 FET

CHANNEL

MOSFET

RDS(ON)

LOADING

0.182 A (EDP)

P-TYPE

FDC638P

3.3V S3 FET

RDS(ON)

MOSFET

LOADING

CKT FROM T18

UNTIL AFTER RAIL TURNS BACK ON OR DIMMS WILL EXIT SELF-REFRESH PREMATURELY.

NVIDIA RECOMMENDS UNPOWERING DURING SLEEP. IN ORDER TO SUPPORT UNPOWERING RAIL, HARDWARE MUST GUARANTEE MEM_CKE SIGNALS ARE LOW BEFORE RAIL IS TURNED OFF, AND REMAINS LOW

MCP79 DDRVTT FET

48 mOhm @4.5V

CHANNEL

3.3V S0 FET

16V X5R 402

0.033UF

10%

C7911

1

2

47K

MF-LF

5%

1/16W

402

R7910

1 2

5%

MF-LF

1/16W

402

10K

R7912

1

2

10% 16V

0.01UF

402

CERM

C7930

1 2

402

X5R

16V

0.033UF

10%

C7931

1

2

1/16W MF-LF

5%

47K

402

R7930

1 2

1/16W

100K

5%

MF-LF

402

R7932

1

2

64

402

CERM

10V

10%

0.068UF

C7903

1

2

CRITICAL

MICROFET3X3

FDM6296G

Q7901

5

4

1 2 3

CERM

10V

0.1UF

20%

402

C7902

1

2

SOT563

SSM6N15FEAPE

Q7971

6

2

1

5% 1/16W MF-LF

402

47K

R7971

1 2

1%

10K

1/16W MF-LF

402

R7901

1 2

100K

5%

MF-LF

1/16W

402

R7903

1

2

SOT563

SSM6N15FEAPE

Q7971

3

5

4

64

SSM6N15FEAPE

SOT563

Q7975

6

2

1

NO STUFF

0.001UF

402

20% 50V

CERM

C7976

1

2

603

MF-LF

1/10W

5%

10

R7975

12

5%

1/16W

402

MF-LF

100K

R7976

1

2

SOT563

SSM6N15FEAPE

Q7975

3

5

4

59 26

SSM3K15FV

SOD-VESM-HF

Q7903

3

1

2

SSM3K15FV

SOD-VESM-HF

Q7905

3

1

2

CRITICAL

SOT-6

FDC606P_G

Q7930

1 2 5 6

3

4

402

16V

CERM

0.01UF

10%

C7910

1 2

805

5%

0

1/8W

MF-LF

R7955

1

2

FDC638P_G

CRITICAL

SM

Q7910

1

2

5

6

3

4

SYNC_MASTER=K36B_MLB

02

109

SYNC_DATE=08/17/2008

POWER FETS

051-8089

79

P3V3S3_SS

P3V3S3_EN_L

=PP3V3_S5_P3V3S3FET

=PP3V3_S3_FET

=PP1V8_S3_P1V8S0FET

MCPDDR_SS

=PP5V_S3_MCPDDRFET

MCPDDR_EN_L_RC

MCPDDR_EN_L

=PP3V3_S0_FET

=PP3V3_S5_P3V3S0FET

=P3V3S0_EN

P3V3S0_EN_L

P3V3S0_SS

=MCPDDR_EN

=PPVTT_S0_VTTCLAMP

VTTCLAMP_L

=PP5V_S3_VTTCLAMP

=DDRVTT_EN

=P3V3S3_EN

=PP1V8_S0_FET

VTTCLAMP_EN

=PP1V05_S0_FET

=PPCPUVTT_S0_REG

8

21

8

63

8

62

IN

D

G S

D

G S

Y

B

A

G

S

D

SGD

SYM_VER-1

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

LVDS: Power +VDD_IFPx at 1.8V Dual-channel TMDS: Power +VDD_IFPx at 3.3V

LCD + CAMERA CONNECTOR

THIS GND CONECTS TO CHASSIS GND

NC

(LVDS DDC POWER)

Plexi: 516S0212

CAMERA I/F

518S0521

INVERTER CONNECTOR

*Enclosure: 518S0364

IT IS CO-LAY FUNCTION

LCD I/F

0.0022UF

10% 50V

CERM

402

C9014

1 2

100K

402

1/16W MF-LF

1%

R9000

1

2

66 18

MF-LF

1/16W

2.7K

402

5%

R9016

1

2

1/16W MF-LF

2.7K

402

5%

R9015

1

2

20%

10UF

603

6.3V X5R

C9012

1

2

402

10% X5R

16V

0.1UF

C9011

1

2

0402-LF

FERR-120-OHM-1.5A

L9005

1 2

CERM 402

10% 50V

0.001UF

C9016

1

2

1/16W

5% MF-LF

402

100K

R9002

1

2

66 18

0402-LF

120-OHM-0.3A-EMI

L9008

1 2

402

1/16W MF-LF

5%

10K

R9023

1 2

S-050162B

F-RT-SM

CRITICAL

J9001

1

10 11 12 13 14 15 16 17 18 19

2

20 21 22

23

24

25

26

3 4 5 6 7 8 9

0

402

5%

MF-LF

1/16W

L9002

1 2

FERR-120-OHM-1.5A

0402-LF

L9003

1 2

100K

1% 1/16W MF-LF

402

R9001

1 2

SSM3K15FV

SOD-VESM-HF

Q9006

3

1

2

SOD-VESM-HF

SSM3K15FV

Q9004

3

1

2

SOT665

CRITICAL

TC7SZ08AFEAPE

U9053

2

1

3

5

4

X5R

0.1UF

10%

16V 402

C9059

1

2

NTK3142PXXH

SOT723-3-HF

Q9005

3

1

2

5%

100PF

50V CERM

402

C9002

1

2

0

5% 1/16W MF-LF 402

C9003

1

2

5%

402

CERM

50V

100PF

C9000

1

2

0.001UF

402

CERM

10% 50V

C9015

1

2

0.001UF

10% 50V CERM 402

C9010

1

2

M-RT-SM

78171-0004

CRITICAL

J9000

5

6

1 2 3 4

FDC606P_G

CRITICAL

SOT-6

Q9003

1

2

5

6

3

4

CRITICAL

90-OHM-200MA

AMC2012-SM

L9007

1

2 3

4

CRITICAL

90-OHM-200MA

AMC2012-SM

L9006

1

2 3

4

1/16W

1K

MF-LF

5%

402

R9019

1

2

MF-LF

1K

5%

1/16W

402

R9018

1

2

MF-LF

1/16W

402

1K

5%

R9012

1

2

402

CERM

50V

5%

100PF

C9001

1

2

120-OHM-0.3A-EMI

0402-LF

L9000

1 2

0402-LF

120-OHM-0.3A-EMI

L9001

1 2

FERR-120-OHM-1.5A

0402-LF

L9004

1 2

50V

10%

0.0033UF

402

CERM

C9013

1 2

INVERTER,LVDS

109

02

SYNC_MASTER=K36B_MLBSYNC_DATE=08/17/2008

051-8089

90

MIN_NECK_WIDTH=0.20 MM

PP5V_INV_F

VOLTAGE=5V

MIN_LINE_WIDTH=0.30 MM

INVT_CHGND

INV_BKLIGHT_PWM_L

INV_GND

VOLTAGE=5V

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.30 MM

PP5V_INV

=PPBUS_S5_INV

MIN_LINE_WIDTH=0.30 MM

MIN_NECK_WIDTH=0.20 MM

PPBUS_ALL_INV_CONN

VOLTAGE=12.6V

PP3V3_S0_LCD_F

MIN_LINE_WIDTH=0.25 MM

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.20 MM

LVDS_IG_DDC_DATA

LVDS_IG_A_DATA_N<0> LVDS_IG_A_DATA_P<0>

PP5V_S3_CAMERA_F

VOLTAGE=5V

MIN_LINE_WIDTH=0.30 MM

MIN_NECK_WIDTH=0.20 MM

VOLTAGE=3.3V

PP3V3_LCDVDD_SW_F

MIN_LINE_WIDTH=0.30 MM

MIN_NECK_WIDTH=0.20 MM

LVDS_IG_DDC_CLK

LVDS_IG_A_DATA_P<1> LVDS_IG_A_DATA_N<2> LVDS_IG_A_DATA_P<2> LVDS_IG_A_CLK_F_N LVDS_IG_A_CLK_F_P

USB2_CAMERA_CONN_P USB2_CAMERA_CONN_N

LVDS_IG_A_CLK_N

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.30 MM

VOLTAGE=3.3V

PP3V3_LCDVDD_SW

=PP3V3_S5_LCD

=GND_CHASSIS_LVDS

=PP5V_S0_LCD

LVDS_IG_BKL_ON

LVDS_IG_PANEL_PWR

INV_PWREN_L

INV_PWREN_F_L

USB_CAMERA_P

=PP5V_S3_CAMERA

=PP3V3_S0_LCD

LCDVDD_PWREN_L

LCDVDD_PWREN_L_R

LVDS_IG_DDC_DATA

LVDS_IG_DDC_CLK

BKLIGHT_CTL

LVDS_IG_BKL_PWM LVDS_IG_BKL_ON LVDS_IG_PANEL_PWR

=PP3V3_S0_LCD

BKLT_PLT_RST_L

USB_CAMERA_N

LVDS_IG_BKL_PWM

=PP3V3_S0_LCD

LVDS_IG_A_CLK_P

LVDS_IG_A_DATA_N<1>

7

9

7

8

7

18 66

7

18 71

7

18 71

7

18 66

7

18 71

7

18 71

7

18 71

7

72

7

72

18 71

8

9

66

9

66

8

20 72

8

66

7

18 66

7

18 66

8

66

26

20 72

18 66

8

66

18 71

7

18 71

IO NC NC

IO

GND

IO NC NC

IO

GND

IO NC NC

IO

GND

IO NC NC

IO

GND

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

D9301, D9302, D9303, D9304 PLACE CLOSE TO J9401

R9322, C9320 PLEASE PLACE CLOSE TO MCP79

R9321, L9320, C9321 PLEASE PLACE CLOSE TO J9401

Interface Mode Setting

1%

1/16W

402

MF-LF

499

R9301

1 2

0.1UF

20%10V 402

CERM

C9308

1

2

CERM

0.1UF

10V

402

20%

C9307

1

2

0.1UF

10V CERM

402

20%

C9303

1

2

0.1UF

402

CERM

10V 20%

C9301

1

2

20%10V

CERM

402

0.1UF

C9304

1

2

10V

0.1UF

402

20%

CERM

C9305

1

2

0.1UF

20%10V 402

CERM

C9306

1

2

CERM

10V 20%

402

0.1UF

C9302

1

2

180PF

5% 50V CERM 402

C9321

1

2

100PF

CERM

5% 50V

402

C9320

1

2

0402

600-OHM-300MA

L9320

1 2

1.00K

1/16W

0.1% MF

402

R9321

1 2

402

MF-LF

1/16W

100K

1%

R9322

1 2

SLP2510P8

RCLAMP0524P

CRITICAL

D9301

3

5 4 6 7

402

1% 1/16W MF-LF

499

R9308

1 2

SLP2510P8

RCLAMP0524P

CRITICAL

D9303

3

5 4 6 7

SLP2510P8

CRITICAL

RCLAMP0524P

D9301

3

2 1 9

10

RCLAMP0524P

SLP2510P8

CRITICAL

D9303

3

2 1 9

10

402

MF-LF

1/16W

1M

5%

R9370

1

2

499

1%

1/16W

402

MF-LF

R9306

1 2

402

MF-LF

1/16W

499

1%

R9307

1 2

MF-LF

402

1/16W

1%

499

R9304

1 2

MF-LF

499

1% 1/16W

402

R9305

1 2

499

1/16W MF-LF

402

1%

R9303

1 2

499

1/16W

402

MF-LF

1%

R9302

1 2

02

SYNC_DATE=08/17/2008

109

SYNC_MASTER=K36B_MLB

TMDS ALIASES

051-8089

93

MAKE_BASE=TRUE

DP_IG_DDC_DATA

TMDS_TX_CLK_N

DP_IG_CA_DET

TMDS_TX_P<0>

TMDS_TX_N<0>

MCP_HDMI_TXD_N<2>

MCP_HDMI_TXD_N<0>

TMDS_TX_P<2>

TMDS_TX_N<2>

=MCP_HDMI_DDC_DATA

MCP_HDMI_TXC_P

MCP_HDMI_TXC_N

TMDS_TX_CLK_P

MCP_HDMI_HPD

HDMI_HPD_R

MCP_HDMI_TXD_P<2>

MCP_HDMI_TXD_P<0>

TMDS_TX_P<1>

TMDS_TX_N<1>

TMDS_HTPLG

=MCP_HDMI_DDC_CLK

MCP_HDMI_TXD_N<1>

MCP_HDMI_TXD_P<1>

MAKE_BASE=TRUE

DP_IG_DDC_CLK

68

18

68

18

68

18

68

18

68

18

68

VCC

125

GND

A

Y

VCC

125

GND

A

Y

SYM_VER-1

D

S G

D

S G

BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

for VG signal trace, we need follow NV’s recommendation. So we need change the segment impedance base on NV design guide.

for B segment: 50 ohm B/W 2 150 PF res. inner layer width is 0.09 mm top/bottom layer width is 0.115 mm

R9493, R9494, R9495 PLACE CLOSE TO U1400

C9409 PLACE CLOSE TO Z0912

PLACE THE RESISTOR CLOSE TO MCP79 AND THE CAP NEAR THE CONNECTOR

for A segment: 37.5 ohm from MCP to 150 ohm PD res: Top/bottom layer width is 0.18 mm

NEED CHANGE SYMBOL

for C segment: 75 ohm from FL to connector, top/bottom layer width is 0.076 mm.

R9490, R9491, R9492 PLACE CLOSE TO FL9400

PLACE THE RESISTOR CLOSE TO MCP79 AND THE CAP NEAR J9401

NC

EXTERNAL VIDEO (VGA) INTERFACE

NOTE: CRT_DDC_* ARE NOT 5V COMPLIANT

NC

DVI power DIODE on page 95 (D9500)

C9408 PLACE CLOSE TO F9404

Video Connectors

Isolation required for DVI power switch

TMDS(MINI DVI) INTERFACE

SM-HF

0.5AMP-13.2V

CRITICAL

F9404

1 2

10% CERM

50V 402

0.001UF

C9410

1

2

402

CERM

10V

20%

0.1UF

C9460

1

2

2.7K

5% 1/16W MF-LF

402

R9462

1

2

MF-LF 402

5%

2.7K

1/16W

R9463

1

2

402

CERM

50V

5%

47PF

NO STUFF

C9442

1

2

CERM 402

5% 25V

220PF

C9411

1

2

402

50V CERM

5%

47PF

NO STUFF

C9443

1

2

US

SN74LVC2G125DCU

CRITICAL

U9404

5

4

7

8

3

CRITICAL

SN74LVC2G125DCU

US

U9404

2

4

1

8

6

90-OHM-100MA

1210-4SM1

CRITICAL

L9405

1

2 3

4

1210-4SM1

90-OHM-100MA

CRITICAL

L9406

1

2 3

4

1210-4SM

CRITICAL

300-OHM-100MA

L9404

1

2 3

4

1210-4SM1

90-OHM-100MA

CRITICAL

L9407

1

2 3

4

SSM6N15FEAPE

SOT563

Q9401

3

5

4

SOT563

SSM6N15FEAPE

Q9401

6

2

1

402

MF-LF

5%

1/16W

2.7K

R9422

1

2

1/16W MF-LF

0

5%

402

R9461

1 2

1/16W MF-LF

5%

39

402

R9470

1 2

402

39

5%

MF-LF

1/16W

R9471

1 2

CERM

5% 402

25V

220PF

C9412

1

2

MEA2010P-SM

210MHZ

CRITICAL

FL9400

2 7

3 6

4 5

1 8

CRITICAL

MINI-DVI-M42-MG3

F-RT-TH-HF

OMIT

J9401

17

20

8

7

6

5

4

3

2

1

26 18

25

9

10

28

30

32

11

12

13

14

15

16

22

29

24

333435

36

19

27

31

CRITICAL

SC70-6-1

RCLAMP0504F

D9400

1

3

4

6

2 5

16V X7R

10%

0.047UF

402

C9409

1

2

0.047UF

16V X7R

10% 402

C9408

1

2

SOD-723-HF

1SS418

D9401

12

1/16W

150

1% MF-LF

402

R9491

1 2

1/16W

150

1%

402

MF-LF

R9490

1 2

MF-LF

402

150

1% 1/16W

R9492

1 2

1%

402

MF-LF

150

1/16W

R9495

1 2

150

402

MF-LF

1% 1/16W

R9494

1 2

1/16W

150

1%

402

MF-LF

R9493

1 2

10V

0.1UF

402

20% CERM

C9404

1

2

0402

600-OHM-300MA

L9444

1 2

1/16W

5%

402

0

MF-LF

R9460

1 2

5%

2.7K

1/16W MF-LF

402

R9421

1

2

67

94

051-8089

SYNC_MASTER=K36B_MLBSYNC_DATE=08/17/2008

02

MINI-DVI CONNECTOR

109

TMDS_TX_P<0>

TMDS_TX_N<0>

VGA_B

=GND_CHASSIS_TMDS_UPPER

TMDS_TX_CONN_N<2>

MIN_NECK_WIDTH=0.20 MM

VOLTAGE=5V

MIN_LINE_WIDTH=0.30 MM

=PP5V_S0_TMDS

VGA_HSYNC

CRT_IG_VSYNC

=PP3V3_S0_TMDS

CRT_HSYNC_LS

VGA_VSYNC

TMDS_TX_P<2>

TMDS_TX_N<2>

VGA_VSYNC

CRT_HSYNC_LS_R

TMDS_TX_P<1>

VGA_HSYNC

TMDS_TX_N<1>

TMDS_TX_CLK_P

CRT_IG_HSYNC

DP_IG_DDC_CLK

VOLTAGE=5V

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.25 MM

PP5V_S0_DVIPORT

=GND_CHASSIS_TMDS_DOWN

CRT_IG_R_C_PR

=GND_CHASSIS_TMDS_UPPER

DP_IG_DDC_DATA

PP5V_S0_TMDS_FUSE

MIN_LINE_WIDTH=0.5 MM

VOLTAGE=5V

MIN_NECK_WIDTH=0.25 MM

PP5V_S0_DVIPORT

PP5V_S0_DVIPORT_D

TMDS_TX_CONN_P<2>

CRT_VSYNC_LS_R

GPU_CRT_DDC_DATA

TMDS_HTPLG

GPU_CRT_DDC_CLK

=PP3V3_S0_TMDS

CRT_VSYNC_LS

TMDS_TX_CLK_N

TMDS_TX_CONN_P<1>

TMDS_TX_CONN_CLK_N

CRT_IG_B_COMP_PB

CRT_IG_G_Y_Y

VGA_G

VGA_R

TMDS_TX_CONN_CLK_P

TMDS_TX_CONN_N<1>

TMDS_TX_CONN_P<0>

TMDS_TX_CONN_N<0>

67

9

68

8

68

18 71

8

68

67

68

67

68

67

18 71

68

9

18 71

9

68

67

8

68

67

18 71

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

FSB (Front-Side Bus) Constraints

FSB 4X signals / groups shown in signal table on right.

NOTE: Intel Design Guide allows closer spacing if signal lengths can be shortened.

FSB 1X signals shown in signal table on right.

Spacing is 1x dielectric between ADDR#, REQ# signals, with 2x dielectric spacing to ADSTB#.

FSB 2X signals / groups shown in signal table on right.

Signals within each 4x group should be matched within 5 ps of strobe.

DSTB# complementary pairs are spaced normally and are NOT routed as differential pairs.

DSTB# complementary pairs should be matched within 1 ps of each other, all DSTB#s matched to +/- 300 ps.

CPU / FSB Net Properties

(CPU_VCCSENSE) (CPU_VCCSENSE)

(FSB_CPURST_L)

Signals

NET_TYPE

SPACING

FSB 1X Signals

ELECTRICAL_CONSTRAINT_SET

FSB 4X Signal Groups

FSB 2X

PHYSICAL

Spacing is 2x dielectric between DATA#, DINV# signals, with 3x dielectric spacing to the DSTB#s.

Signals within each 2x group should be matched within 20 ps. ADTSB#s should be matched +/- 300 ps.

All 4x/2x/1x FSB signals with impedance requirements are 50-ohm single-ended.

NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.

SR DG recommends at least 25 mils, >50 mils preferred

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2

Most CPU signals with impedance requirements are 55-ohm single-ended.

FSB Clock Constraints

Some signals require 27.4-ohm single-ended impedance.

MCP FSB COMP Signal Constraints

SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4

Design Guide recommends each strobe/signal group is routed on the same layer. Intel Design Guide recommends FSB signals be routed only on internal layers.

SOURCE: Santa Rosa Platform DG, Rev 1.5 (#22294), Sections 4.2 & 4.3

CPU Signal Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.4

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.5

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2

Signals within each 1x group should be matched to CPU clock, +0/-1000 mils.

(See above)

* ?

FSB_1X =STANDARD

* ?

FSB_ADSTB

=2x_DIELECTRIC

*

=1:1_DIFFPAIR =1:1_DIFFPAIR

FSB_DSTB_50S

=50_OHM_SE

=50_OHM_SE =50_OHM_SE =50_OHM_SE

=2x_DIELECTRIC

?*

FSB_DATA

=3x_DIELECTRIC

?

TOP,BOTTOM

FSB_1X

=3x_DIELECTRIC

?

TOP,BOTTOM

FSB_ADDR

=5x_DIELECTRIC

?

FSB_DSTB

TOP,BOTTOM

=4x_DIELECTRIC

FSB_DATA

?

TOP,BOTTOM

?

FSB_ADDR

*

=STANDARD

=2x_DIELECTRIC

TOP,BOTTOM

?

CPU_AGTL

TOP,BOTTOM

?

CLK_FSB =4x_DIELECTRIC

=50_OHM_SE=50_OHM_SE =50_OHM_SE=50_OHM_SE

CPU_50S

=STANDARD=STANDARD

*

=STANDARD

* ?

CPU_AGTL

* ?

CPU_8MIL

8 MIL

25 MIL

*

CPU_COMP

?

=2:1_SPACING

?*

CPU_ITP

?*

CPU_GTLREF

25 MIL

?

CPU_VCCSENSE

*

=STANDARD=STANDARD

*

=50_OHM_SE =50_OHM_SE=50_OHM_SE

MCP_50S

=50_OHM_SE

MCP_FSB_COMP

?*

8 MIL

CLK_FSB_100D

*

=100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF

*

CLK_FSB

?

=3x_DIELECTRIC

CPU_27P4S

7 MIL 7 MIL

=27P4_OHM_SE=27P4_OHM_SE

*

=27P4_OHM_SE

=3x_DIELECTRIC

*

FSB_DSTB

?

=50_OHM_SE

=STANDARD

=50_OHM_SE=50_OHM_SE

FSB_50S

=STANDARD

*

=50_OHM_SE

02

SYNC_DATE=08/17/2008SYNC_MASTER=K36B_MLB

109

CPU/FSB Constraints

051-8089

100

=4x_DIELECTRIC

?

FSB_ADSTB

TOP,BOTTOM

FSB_CLK_CPU

FSB_CLK_CPU_P

CLK_FSB_100D

CLK_FSB

CLK_FSB_100D

CLK_FSB

FSB_CLK_ITP_N

FSB_CLK_ITP

CPU_50S

IMVP_DPRSLPVR

CPU_AGTL

FSB_DATA_GROUP0

FSB_50S

FSB_DINV_L<0>

FSB_DATA

FSB_50S

FSB_1X FSB_1X

FSB_LOCK_L

CPU_50S

CPU_ASYNC

CPU_A20M_L

CPU_AGTL

FSB_50S

FSB_DATA

FSB_DATA_GROUP2

FSB_D_L<47..32>

FSB_DSTB_L_N<1>

FSB_DSTB_50S

FSB_DSTB

FSB_DSTB1

FSB_ADSTB

FSB_50S

FSB_ADSTB_L<0>

FSB_ADSTB0

CPU_VID<6..0>

CPU_50S

CPU_8MIL

CPU_50S

IMVP6_VID<6..0>

CPU_8MIL

CPU_27P4S

CPU_VCCSENSE

IMVP6_VSEN_P

CPU_VCCSENSE

IMVP6_VSEN_N

CPU_27P4S

CPU_VCCSENSE

CPU_27P4S

CPU_VCCSENSE

CPU_VCCSENSE_N

CPU_VCCSENSE

CPU_27P4S

CPU_VCCSENSE

CPU_VCCSENSE_P

XDP_CPURST_L

CPU_ITPCPU_50S

XDP_BPM_L5

CPU_50S CPU_ITP

XDP_BPM_L<5>

XDP_BPM_L

CPU_50S

XDP_BPM_L<4..0>

CPU_ITP

XDP_TRST_L

CPU_50S CPU_ITP

XDP_TRST_L

XDP_TCK CPU_50S CPU_ITP

XDP_TCK

XDP_TMS CPU_50S

XDP_TMS

CPU_ITP

MCP_FSB_COMPMCP_CPU_COMP

MCP_50S

MCP_BCLK_VML_COMP_VDD

CPU_50S

CPU_ASYNC

FSB_DPWR_L

CPU_AGTL

CPU_50S

FSB_CPUSLP_L

CPU_AGTL

FSB_CPUSLP_L

CPU_PWRGD

CPU_AGTL

CPU_50S

CPU_ASYNC_R

CPU_NMI

CPU_AGTL

CPU_50S

CPU_ASYNC_R

CPU_INTR

CPU_AGTL

CPU_50S

CPU_ASYNC

CPU_IGNNE_L

CPU_AGTL

CPU_50S

CPU_FERR_L

CPU_8MIL

FSB_1X

FSB_TRDY_L

FSB_1X

FSB_50S

FSB_1X

FSB_RS_L<2..0>

FSB_1X

FSB_50S

FSB_CPURST_L

FSB_1X

FSB_50S

FSB_1X FSB_1X

FSB_HITM_L

FSB_50S

FSB_1X

FSB_HIT_L

FSB_1X

FSB_50S

FSB_1X

FSB_DEFER_L

FSB_1X

FSB_50S

FSB_1X

FSB_DBSY_L

FSB_1X

FSB_50S

FSB_1X FSB_1X

FSB_BPRI_L

FSB_50S

FSB_1X

FSB_BNR_L

FSB_1X

FSB_50S

FSB_BREQ1_L

FSB_1X

FSB_50S

FSB_BREQ0_L

FSB_1X

FSB_50S

FSB_1X FSB_1X

FSB_ADS_L

FSB_ADSTB_L<1>

FSB_ADSTB1

FSB_ADSTB

FSB_50S

FSB_ADDR_GROUP1

FSB_ADDR

FSB_A_L<35..17>

FSB_ADDR_GROUP0

FSB_REQ_L<4..0>

FSB_ADDR

FSB_50S

FSB_ADDR

FSB_ADDR_GROUP0

FSB_A_L<16..3>

FSB_50S

FSB_DSTB_50S

FSB_DSTB

FSB_DSTB3

FSB_DSTB_L_N<3>

FSB_DSTB_50S

FSB_DSTB_L_P<3>

FSB_DSTB

FSB_DSTB3

FSB_50S

FSB_DATA_GROUP3

FSB_DINV_L<3>

FSB_DATA

FSB_50S

FSB_D_L<63..48>

FSB_DATA_GROUP3

FSB_DATA

FSB_DSTB_50S

FSB_DSTB

FSB_DSTB2

FSB_DSTB_L_N<2>

FSB_DSTB_50S

FSB_DSTB_L_P<2>

FSB_DSTB

FSB_DSTB2

FSB_50S

FSB_DATA_GROUP2

FSB_DINV_L<2>

FSB_DATA

FSB_DSTB_50S

FSB_DSTB1

FSB_DSTB

FSB_DSTB_L_P<1>

FSB_50S

FSB_DATA_GROUP1

FSB_DINV_L<1>

FSB_DATA

FSB_50S

FSB_DATA_GROUP1

FSB_D_L<31..16>

FSB_DATA

FSB_DSTB_50S

FSB_DSTB0

FSB_DSTB

FSB_DSTB_L_N<0>

FSB_DSTB_50S

FSB_DSTB

FSB_DSTB0

FSB_DSTB_L_P<0>

FSB_DATA_GROUP0

FSB_50S

FSB_D_L<15..0>

FSB_DATA

CPU_50S

CPU_ASYNC

CPU_SMI_L

CPU_AGTL

CPU_50S

CPU_ASYNC

CPU_AGTL

CPU_STPCLK_L

CPU_50S

PM_THRMTRIP_L

CPU_8MIL

CPU_50S

CPU_FROM_SB

CPU_DPSLP_L

CPU_AGTL

MCP_FSB_COMPMCP_CPU_COMP

MCP_CPU_COMP_GND

MCP_50S

MCP_CPU_COMP

MCP_CPU_COMP_VCC

MCP_50S

MCP_FSB_COMP

MCP_CPU_COMP

MCP_BCLK_VML_COMP_GND

MCP_50S

MCP_FSB_COMP

CPU_50S

CPU_DPRSTP_L

CPU_AGTL

CPU_PROCHOT_L

CPU_AGTL

CPU_50S

CPU_INIT_L

CPU_AGTL

CPU_50S

CPU_BSEL

CPU_BSEL<2..0>

CPU_AGTL

FSB_50S

FSB_1X

FSB_DRDY_L

FSB_1X

XDP_TDI CPU_ITP

XDP_TDI

CPU_50S

CPU_COMP

CPU_27P4S

CPU_COMP<0>

CPU_COMP

CPU_50S

CPU_COMP

CPU_COMP<1>

CPU_COMP

CPU_27P4S

CPU_COMP<2>

CPU_COMP

CPU_COMP<3>

CPU_50S

CPU_COMP

CPU_50S

CPU_GTLREF

CPU_GTLREFCPU_GTLREF

CPU_50S

CPU_AGTL

PM_DPRSLPVR

CPU_50S

CPU_IERR_L

CLK_FSB

CLK_FSB_100D

FSB_CLK_MCP_N

FSB_CLK_MCP

CLK_FSB

CLK_FSB_100D

FSB_CLK_MCP_P

FSB_CLK_MCP

CLK_FSB

CLK_FSB_100D

FSB_CLK_ITP_P

FSB_CLK_ITP

FSB_CLK_CPU

CLK_FSB

CLK_FSB_100D

FSB_CLK_CPU_N

XDP_TDO

CPU_ITPCPU_50S

XDP_TDO1

10

9

10

10 14

7

13 14

60

10 14

11 60

7

13

7

10 13

7

10 13

6 7

10 13

6 7

10 13

6 7

10 13

14

10 14

13 14

14

13 14

10 14

14

10 14

14

10 14

14

10 14

14

10 14

14

10 14

14

10 14

14

10 14

14

10 14

14

10 14

14

10 14

14 42

14

14 60

14 42 60

14

10

14

6 7

10 13

10

10 27

21 60

10

14

7

13 14

10 14

6

10

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TABLE_SPACING_ASSIGNMENT_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

Memory Net Properties

DQ signals should be matched within 5 ps of associated DQS pair. DQS intra-pair matching should be within 1 ps, inter-pair matching shoulw be within 180 ps No DQS to clock matching requirement.

A/BA/cmd signals should be matched within 5 ps of CLK pairs. All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate). DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric.

DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric.

Need to support MEM_*-style wildcards!

Memory Bus Constraints

Memory Bus Spacing Group Assignments

DQ signals should be matched within 20 ps of associated DQS pair. DQS intra-pair matching should be within 1 ps, no inter-pair matching requirement. All DQS pairs should be matched within 100 ps of clocks. CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 140 ps. A/BA/cmd signals should be matched within 75 ps, no CLK matching requirement.

NET_TYPE

SPACING

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate).

CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 2 ps.

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3.4

MCP MEM COMP Signal Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3 SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2

DDR3:

DDR2:

MEM_DATA

*

MEM_CMD

MEM_CMD2MEM

=2:1_SPACING

MEM_CTRL2CTRL

* ?

?

=3:1_SPACING

MEM_DQS2MEM

*

MEM_DATA

*

MEM_DATA2MEM

MEM_CTRL

MCP_MEM_COMP

8 MIL

* ?

=STANDARD

7 MIL7 MIL

Y

MCP_MEM_COMP

*

=STANDARD =STANDARD

MEM_DQSMEM_DQS

MEM_DQS2MEM

*

MEM_DATA

*

MEM_DQS2MEM

MEM_DQS

MEM_CMD

*

MEM_CTRL2MEM

MEM_CTRL

MEM_DQS

MEM_CTRL

*

MEM_CTRL2MEM

MEM_DATA

MEM_CTRL2MEM

*

MEM_CTRL

MEM_CTRL2CTRL

MEM_CTRL

*

MEM_CTRL

MEM_CTRL2MEM

MEM_CLK

*

MEM_DQS

MEM_CLK2MEM

MEM_CLK

*

MEM_DATA

*

MEM_CLK

MEM_CLK2MEM

MEM_CMD

MEM_CLK2MEM

MEM_CLK

*

MEM_CLK

MEM_CTRL

MEM_CLK2MEM

*

MEM_CLK MEM_CLK

MEM_CLK2MEM

*

MEM_2OTHER

MEM_DQS

**

MEM_DQS

MEM_DATA2MEM

MEM_DATA

*

MEM_CMD2MEM

MEM_CMD

*

MEM_DQS

*

MEM_CMD MEM_CMD

MEM_CMD2CMD

MEM_CTRL

*

MEM_CMD

MEM_CMD2MEM

25 MIL

MEM_2OTHER

* ?

MEM_DATA2MEM =3:1_SPACING

* ?

MEM_40S

=STANDARD

*

=STANDARD

=40_OHM_SE =40_OHM_SE =40_OHM_SE=40_OHM_SE

MEM_CMDMEM_DQS

MEM_DQS2MEM

*

MEM_CTRL

*

MEM_DQS2MEM

MEM_DQS

MEM_CLK

*

MEM_DQS2MEM

MEM_DQS

=1.5:1_SPACING

MEM_CMD2CMD

* ?

MEM_CMD

*

MEM_CMD2MEM

MEM_CLK

=1.5:1_SPACING

MEM_DATA2DATA

* ?

MEM_CMD2MEM

* ?

=3:1_SPACING

MEM_CTRL2MEM

* ?

=2.5:1_SPACING

=4:1_SPACING

MEM_CLK2MEM

* ?

=70_OHM_DIFF

=70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF

*

=70_OHM_DIFF =70_OHM_DIFF

MEM_70D

MEM_40S_VDD

=40_OHM_SE=40_OHM_SE=40_OHM_SE

=STANDARD

*

=STANDARD

=40_OHM_SE

=70_OHM_DIFF

=70_OHM_DIFF=70_OHM_DIFF

*

=70_OHM_DIFF=70_OHM_DIFF=70_OHM_DIFF

MEM_70D_VDD

*

MEM_DATA2MEM

MEM_DATA

MEM_CLK

MEM_DATA2MEM

MEM_DATA

*

MEM_CMD

MEM_DATA

MEM_DATA2DATA

MEM_DATA

*

MEM_2OTHER

MEM_CLK

**

MEM_2OTHER

MEM_CTRL

* *

MEM_2OTHER

MEM_CMD

**

MEM_2OTHER

MEM_DATA

* *

SYNC_DATE=08/17/2008

Memory Constraints

02

109

SYNC_MASTER=K36B_MLB

051-8089

101

MEM_DATA

MEM_40S

MEM_B_DQ<31..24>

MEM_B_DQ_BYTE3

MEM_DATA

MEM_B_DQ<39..32>

MEM_40SMEM_B_DQ_BYTE4

MEM_DATA

MEM_40S

MEM_B_DQ<47..40>

MEM_B_DQ_BYTE5

MEM_DATA

MEM_40S

MEM_B_DQ<55..48>

MEM_B_DQ_BYTE6

MEM_DATA

MEM_40S

MEM_B_DQ<63..56>

MEM_B_DQ_BYTE7

MEM_DATA

MEM_40S

MEM_B_DM<1>

MEM_B_DQ_BYTE1

MEM_DATA

MEM_40S

MEM_B_DM<2>

MEM_B_DQ_BYTE2

MEM_DATA

MEM_40S

MEM_B_DM<5>

MEM_B_DQ_BYTE5

MEM_DATA

MEM_40SMEM_B_DQ_BYTE6

MEM_B_DM<6>

MEM_DQSMEM_70D

MEM_B_DQS_N<0>

MEM_B_DQS0

MEM_DQSMEM_70D

MEM_B_DQS_P<2>

MEM_B_DQS2

MEM_DQSMEM_70D

MEM_B_DQS_N<3>

MEM_B_DQS3

MEM_DQSMEM_70D

MEM_B_DQS7

MEM_B_DQS_P<7>

MEM_DQSMEM_70D

MEM_B_DQS_N<5>

MEM_B_DQS5

MEM_B_CLK

MEM_CLK

MEM_B_CLK_P<5..0>

MEM_70D_VDD

MEM_DQS

MEM_A_DQS_N<6>

MEM_A_DQS6

MEM_70D

MEM_DQS

MEM_A_DQS_P<6>

MEM_A_DQS6

MEM_70D

MEM_70D MEM_DQS

MEM_A_DQS_N<5>

MEM_A_DQS5

MEM_70D MEM_DQS

MEM_A_DQS_P<5>

MEM_A_DQS5

MEM_DQS

MEM_A_DQS_N<4>

MEM_A_DQS4

MEM_70D

MEM_70D MEM_DQS

MEM_A_DQS_P<4>

MEM_A_DQS4

MEM_70D MEM_DQS

MEM_A_DQS_N<3>

MEM_A_DQS3

MEM_70D MEM_DQS

MEM_A_DQS_P<3>

MEM_A_DQS3

MEM_DQS

MEM_A_DQS_N<2>

MEM_A_DQS2

MEM_70D

MEM_70D MEM_DQS

MEM_A_DQS_P<2>

MEM_A_DQS2

MEM_70D MEM_DQS

MEM_A_DQS_N<1>

MEM_A_DQS1

MEM_DQS

MEM_A_DQS1

MEM_A_DQS_P<1>

MEM_70D

MEM_70D MEM_DQS

MEM_A_DQS_N<0>

MEM_A_DQS0

MEM_40S

MEM_A_DM<7>

MEM_DATA

MEM_A_DQ_BYTE7

MEM_A_DQS_P<0>

MEM_70D MEM_DQS

MEM_A_DQS0

MEM_40S

MEM_A_DM<6>

MEM_DATA

MEM_A_DQ_BYTE6

MEM_40S

MEM_DATA

MEM_A_DM<5>

MEM_A_DQ_BYTE5

MEM_DATA

MEM_A_DM<4>

MEM_40SMEM_A_DQ_BYTE4

MEM_40SMEM_A_DQ_BYTE3

MEM_A_DM<3>

MEM_DATA

MEM_40SMEM_A_DQ_BYTE2

MEM_DATA

MEM_A_DM<2>

MEM_DATA

MEM_A_DQ<63..56>

MEM_A_DQ_BYTE7 MEM_40S

MEM_A_DQ<55..48>

MEM_A_DQ_BYTE6

MEM_DATA

MEM_40S

MEM_DATA

MEM_A_DQ<23..16>

MEM_A_DQ_BYTE2

MEM_A_WE_L

MEM_A_CMD

MEM_CMD

MEM_40S_VDD

MEM_CMD

MEM_A_CMD

MEM_A_BA<2..0>

MEM_40S_VDD

MEM_A_CNTL

MEM_A_ODT<3..0>

MEM_CTRL

MEM_40S_VDD

MEM_A_CNTL

MEM_A_CS_L<3..0>

MEM_CTRL

MEM_40S_VDD

MEM_A_CNTL

MEM_CTRL

MEM_A_CKE<3..0>

MEM_40S_VDD

MEM_CLK

MEM_A_CLK

MEM_A_CLK_N<5..0>

MEM_70D_VDD

MEM_A_A<14..0>

MEM_CMD

MEM_A_CMD

MEM_40S_VDD

MEM_CMD

MEM_A_RAS_L

MEM_A_CMD

MEM_40S_VDD

MEM_CLK

MEM_A_CLK

MEM_A_CLK_P<5..0>

MEM_70D_VDD

MEM_DATA

MEM_40S

MEM_B_DM<4>

MEM_B_DQ_BYTE4

MEM_DATA

MEM_40S

MEM_B_DM<7>

MEM_B_DQ_BYTE7

MEM_DQSMEM_70D

MEM_B_DQS_P<0>

MEM_B_DQS0

MEM_DQSMEM_70D

MEM_B_DQS_P<1>

MEM_B_DQS1

MEM_40S_VDD

MEM_CTRL

MEM_B_CNTL

MEM_B_CKE<3..0>

MEM_40SMEM_A_DQ_BYTE1

MEM_A_DM<1>

MEM_DATA

MEM_DQS

MEM_A_DQS_N<7>

MEM_A_DQS7

MEM_70D

MEM_40SMEM_A_DQ_BYTE0

MEM_A_DM<0>

MEM_DATA

MEM_A_DQ<7..0>

MEM_A_DQ_BYTE0

MEM_DATA

MEM_40S

MEM_A_CMD

MEM_CMD

MEM_A_CAS_L

MEM_40S_VDD

MEM_40SMEM_A_DQ_BYTE3

MEM_A_DQ<31..24>

MEM_DATA

MEM_40S

MEM_A_DQ<15..8>

MEM_A_DQ_BYTE1

MEM_DATA

MEM_A_DQ_BYTE4

MEM_DATA

MEM_A_DQ<39..32>

MEM_40S

MEM_A_DQ_BYTE5

MEM_DATA

MEM_A_DQ<47..40>

MEM_40S

MEM_DATA

MEM_40S

MEM_B_DQ<15..8>

MEM_B_DQ_BYTE1

MEM_DATA

MEM_40S

MEM_B_DQ<23..16>

MEM_B_DQ_BYTE2

MEM_40S_VDD

MEM_CMD

MEM_B_WE_L

MEM_B_CMD

MEM_DATA

MEM_40S

MEM_B_DQ<7..0>

MEM_B_DQ_BYTE0

MEM_DATA

MEM_40S

MEM_B_DM<0>

MEM_B_DQ_BYTE0

MEM_40S_VDD

MEM_CMD

MEM_B_BA<2..0>

MEM_B_CMD

MEM_DQSMEM_70D

MEM_B_DQS6

MEM_B_DQS_N<6>

MEM_DQSMEM_70D

MEM_B_DQS6

MEM_B_DQS_P<6>

MEM_DQSMEM_70D

MEM_B_DQS5

MEM_B_DQS_P<5>

MEM_DQS

MEM_B_DQS_N<4>

MEM_70D

MEM_B_DQS4

MEM_DQSMEM_70D

MEM_B_DQS_P<4>

MEM_B_DQS4

MEM_DQSMEM_70D

MEM_B_DQS_N<2>

MEM_B_DQS2

MEM_DQSMEM_70D

MEM_B_DQS_N<1>

MEM_B_DQS1

MEM_DQSMEM_70D

MEM_B_DQS_P<3>

MEM_B_DQS3

MEM_DATA

MEM_40S

MEM_B_DM<3>

MEM_B_DQ_BYTE3

MEM_DQSMEM_70D

MEM_B_DQS_N<7>

MEM_B_DQS7

MEM_40S_VDD

MEM_CTRL

MEM_B_CNTL

MEM_B_ODT<3..0>

MEM_40S_VDD

MEM_CTRL

MEM_B_CS_L<3..0>

MEM_B_CNTL

MEM_B_CLK

MEM_B_CLK_N<5..0>

MEM_CLK

MEM_70D_VDD

MCP_MEM_COMP_VDD

MCP_MEM_COMPMCP_MEM_COMPMCP_MEM_COMP

MCP_MEM_COMP_GND

MCP_MEM_COMPMCP_MEM_COMPMCP_MEM_COMP

MEM_70D MEM_DQS

MEM_A_DQS_P<7>

MEM_A_DQS7

MEM_40S_VDD

MEM_CMD

MEM_B_CAS_L

MEM_B_CMD

MEM_40S_VDD

MEM_CMD

MEM_B_RAS_L

MEM_B_CMD

MEM_40S_VDD

MEM_B_A<14..0>

MEM_CMD

MEM_B_CMD

15

15 29

29

15 29

29

15 29

15 28

28

15 28

28

15 28

15 28 30

28 30

15 28 30

28

15 28 30

15 28

15 29

15 29 30

28

15 28

15 28 30

28

15 28

15 29

15 29 30

15 29

15 29 30

29

15 29

29 30

15 29 30

29

16

15 28

15 29 30

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

SPACING

PCI-Express

PHYSICAL

NET_TYPE

ELECTRICAL_CONSTRAINT_SET

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.4

Analog Video Signal Constraints

- 37.5-ohm from MCP to first termination resistor.

- 50-ohm from first to second termination resistor.

- 75-ohm from output of three-pole filter to connector (if possible). R/G/B signals should be matched as close as possible and < 10 inches. SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.1 & 2.5.2.

Digital Video Signal Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4.

SATA Interface Constraints

Max length of LVDS/DisplayPort/TMDS traces: 12 inches.

DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals.

DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps.

LVDS intra-pair matching should be 5 mils. Pairs should be within 100 mils of clock length.

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.7.1.

CRT signal single-ended impedence varies by location:

MCP_DV_COMP

*

Y 20 MIL 20 MIL =STANDARD

=STANDARD =STANDARD

=3x_DIELECTRIC

TOP,BOTTOM

?

SATA

SATA_100D_HDD

*

=100_OHM_DIFF_HDD

=100_OHM_DIFF_HDD =100_OHM_DIFF_HDD =100_OHM_DIFF_HDD

=100_OHM_DIFF_HDD =100_OHM_DIFF_HDD

LVDS

*

=3x_DIELECTRIC

?

*

CRT_SYNC

16 MIL

?

CRT_2SWITCHER

*

250 MIL

?

CRT_2CLK

*

50 MIL

?

CRT CRT

*

CRT_2CRT

*

=STANDARD

?

CRT_50S

*

=50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE

=STANDARD =STANDARD

CLK_PCIE_100D

*

=100_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFF

DISPLAYPORT

TOP,BOTTOM

=4x_DIELECTRIC

?

PCIE

*

=3X_DIELECTRIC

?

MCP_PEX_COMP

*

8 MIL

?

CLK_PCIE

*

20 MIL

?

PCIE

TOP,BOTTOM

=4X_DIELECTRIC

?

PCIE_90D

*

=90_OHM_DIFF

=90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF

=90_OHM_DIFF =90_OHM_DIFF

CRT

*

=4:1_SPACING

?

MCP_DAC_COMP

*

=2:1_SPACING

?

DP_100D

*

=100_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFF

LVDS

TOP,BOTTOM

=4x_DIELECTRIC

?

=4x_DIELECTRIC

SATA

* ?

SATA_100D

*

=100_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFF

DISPLAYPORT

*

=3x_DIELECTRIC

?

102

051-8089

MCP Constraints 1

SYNC_MASTER=K36B_MLB

109

02

SYNC_DATE=08/17/2008

LVDS_100D

*

=100_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFF

SATA_TERMP

*

8 MIL

?

SATA_100D

SATA

SATA_ODD_R2D_C_P

SATA_ODD_R2D

SATA_100D

SATA

SATA_ODD_R2D_C_N

SATA_100D

SATA

SATA_ODD_R2D_P SATA_ODD_R2D_N

SATA_100D

SATA

SATA_ODD_R2D_UF_P

SATA_100D

SATA

SATA_HDD_D2R_C_N

SATA_100D_HDD

SATA

SATA_HDD_R2D_N

SATA_100D_HDD

SATA_HDD_R2D_UF_P

SATA_100D_HDD

SATA

SATA_HDD_R2D_UF_N

SATA_100D_HDD

SATA

SATA_HDD_D2R_P

SATA_HDD_D2R

SATA_100D_HDD

SATA

SATA_HDD_D2R_C_P

SATA_100D_HDD

SATA

SATA_HDD_D2R_N

SATA_100D_HDD

SATA

SATA_ODD_D2R_UF_P

SATA

SATA_100D

SATA_ODD_D2R_C_N

SATA_100D

SATA

SATA_ODD_D2R_C_P

SATA

SATA_100D

SATA_ODD_D2R_P

SATA

SATA_100D

SATA_ODD_D2R

SATA_ODD_R2D_UF_N

SATA_100D

SATA

SATA_HDD_R2D_P

SATA_100D_HDD

SATA

SATA_HDD_R2D_C_N

SATA_100D_HDD

MCP_IFPAB_VPROBE

MCP_IFPAB_RSET

MCP_DV_COMP

MCP_IFPAB_RSET

LVDS_IG_B_DATA3

LVDS_100D

LVDS

LVDS_IG_B_DATA_N<3>

LVDS_IG_B_DATA3

LVDS

LVDS_IG_B_DATA_P<3>

LVDS_100D

LVDS_IG_B_DATA

LVDS

LVDS_100D

LVDS_IG_B_DATA_N<2..0>

LVDS_IG_B_CLK

LVDS

LVDS_100D

LVDS_IG_B_CLK_N

LVDS_IG_A_DATA3

LVDS_100D

LVDS

LVDS_IG_A_DATA_P<3>

LVDS_IG_A_DATA

LVDS_100D

LVDS

LVDS_IG_A_DATA_P<2..0>

LVDS_IG_A_CLK

LVDS_100D

LVDS

LVDS_IG_A_CLK_N

LVDS_IG_A_CLK

LVDS_100D

LVDS

LVDS_IG_A_CLK_P

MCP_HDMI_VPROBE

MCP_DV_COMP

MCP_HDMI_RSET

MCP_DV_COMP

MCP_HDMI_RSET

DP_AUX_CH

DP_100D

DISPLAYPORT

TP_DP_IG_AUX_CH_N

TP_DP_IG_AUX_CH_P

DP_AUX_CH

DP_100D

DISPLAYPORT

TMDS_IG_TXD DISPLAYPORT

TMDS_IG_TXD_P<2..0>

DP_100D

TMDS_IG_TXC DISPLAYPORT

TMDS_IG_TXC_N

DP_100D

MCP_DAC_VREF MCP_DAC_COMP

MCP_TV_DAC_VREF

MCP_DAC_RSET MCP_DAC_COMP

MCP_TV_DAC_RSET

CRT_SYNCCRT_SYNC

CRT_50S

CRT_IG_VSYNC

PCIE_90D

PCIE

PEG_R2D_N<15..0>

PEG_D2R_P<15..0>

PEG_D2R

PCIE_90D

PCIE

PCIE_90D

PEG_D2R_C_N<15..0>

PCIE

PCIE_90D

PCIE

PCIE_MINI_R2D_N

PCIE_EXCARD_R2D

PCIE_90D

PCIE

PCIE_EXCARD_R2D_C_P

PCIE_EXCARD_D2R

PCIE_90D

PCIE

PCIE_EXCARD_D2R_P

PCIE

PCIE_EXCARD_D2R_N

PCIE_90D

MCP_PE0_REFCLK

CLK_PCIE_100D

CLK_PCIE

PEG_CLK100M_P

CRT

CRT_MCP_P

CRT_IG_B_COMP_PB

CRT_BLUE

CRT

CRT_MCP_PCRT_GREEN

CRT_IG_G_Y_Y

CRT

CRT_MCP_P

CRT_RED

CRT_IG_R_C_PR

MCP_PE1_REFCLK

CLK_PCIE_100D

CLK_PCIE

PCIE_CLK100M_MINI_P

CLK_PCIE_100D

CLK_PCIE

PCIE_CLK100M_EXCARD_N

CLK_PCIE_100D

CLK_PCIE

PCIE_CLK100M_FW_N

MCP_PEX_CLK_COMP

MCP_PEX_COMP

MCP_PEX_CLK_COMP

CRT_SYNC

CRT_50S

CRT_IG_HSYNC

CRT_SYNC

MCP_PE3_REFCLK

CLK_PCIE_100D

CLK_PCIE

PCIE_CLK100M_EXCARD_P

DP_IG_ML_P<3..0>

DP_ML

DISPLAYPORT

DP_100D

DP_IG_ML_N<3..0>

DP_ML

DISPLAYPORT

DP_100D

SATA_ODD_D2R_N

SATA

SATA_100D

TMDS_IG_TXD DISPLAYPORT

TMDS_IG_TXD_N<2..0>

DP_100D

SATA_HDD_R2D

SATA

SATA_HDD_R2D_C_P

SATA_100D_HDD

MCP_SATA_TERMP

SATA_TERMP

MCP_SATA_TERMP

LVDS_IG_A_DATA3

LVDS

LVDS_100D

LVDS_IG_A_DATA_N<3>

LVDS_IG_B_CLK

LVDS

LVDS_100D

LVDS_IG_B_CLK_P

LVDS_IG_B_DATA

LVDS

LVDS_100D

LVDS_IG_B_DATA_P<2..0>

PCIE

PCIE_FW_R2D_N

PCIE_90D

PCIE

PCIE_EXCARD_R2D_C_N

PCIE_90D

PCIE

PCIE_FW_R2D_C_N

PCIE_FW_D2R_N

PCIE_90D

PCIE

PCIE_90D

PCIE

PCIE_EXCARD_R2D_N

LVDS_IG_A_DATA

LVDS

LVDS_100D

LVDS_IG_A_DATA_N<2..0>

TMDS_IG_TXC DISPLAYPORT

TMDS_IG_TXC_P

DP_100D

PCIE_FW_D2R

PCIE_90D

PCIE

PCIE_FW_D2R_P

PCIE_FW_R2D

PCIE_90D

PCIE

PCIE_FW_R2D_C_P

PCIE_90D

PCIE

PCIE_FW_R2D_P

PCIE_90D

PCIE

PCIE_FW_D2R_C_P

PCIE_90D

PCIE_EXCARD_R2D_P

PCIE

CLK_PCIE_100D

CLK_PCIE

PEG_CLK100M_N

MCP_PE2_REFCLK

CLK_PCIE_100D

CLK_PCIE

PCIE_CLK100M_FW_P

CLK_PCIE

PCIE_CLK100M_MINI_N

CLK_PCIE_100D

PCIE_90D

PCIE

PCIE_FW_D2R_C_N

SATA_ODD_D2R_UF_N

SATA_100D

SATA

PEG_R2D_P<15..0>

PCIE_90D

PCIE

PEG_R2D

PCIE_90D

PEG_R2D_C_P<15..0>

PCIE

PEG_D2R_N<15..0>

PCIE_90D PCIE_90D

PCIE

PEG_D2R_C_P<15..0>

PCIE

PCIE_90D

PCIE_MINI_R2D_P

PCIE_MINI_R2D

PCIE_MINI_R2D_C_P

PCIE_90D

PCIE

PCIE_90D

PCIE

PCIE_MINI_D2R_N

PCIE_MINI_D2R

PCIE_MINI_D2R_P

PCIE

PCIE_90D

PEG_R2D

PEG_R2D_C_N<15..0>

PCIE_90D

PCIE

PCIE_MINI_R2D_C_N

PCIE

PCIE_90D

18

7

17

20 38

38

7

38

7

38

7

38

20 38

7

38

20 38

38

7

38

7

38

20 38

7

38

7

38

20 38

25

18 25

9

18

9

18

9

18

9

18

9

18

7

18 66

25

18 25

9

18

9

18

18 68

7

31

9

17

9

17

9

17

9

17

18 68

68

18 68

7

17 31

9

17

17 35

17

18 68

9

17

20 38

20

9

18

9

18

9

18

35

9

17

17 35

7

18 66

17 35

35

9

17

17 35

7

17 31

35

38

7

31

7

17 31

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

SMBus Interface Constraints

PCI Bus Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.11.1.

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.14.

SPACING

NET_TYPE

PHYSICAL

ELECTRICAL_CONSTRAINT_SET

SPI Interface Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.13.

SIO Signal Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.12.1.

HD Audio Interface Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.10.1.

USB 2.0 Interface Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.9.1.

LPC Bus Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.8.

I183

I184

I185

I186

I187

I188

I189

I190

I191

I192

I193

I194

*

=STANDARD=STANDARD

HDA_55S

=55_OHM_SE =55_OHM_SE =55_OHM_SE=55_OHM_SE

USB_90D

=90_OHM_DIFF =90_OHM_DIFF

*

=90_OHM_DIFF

=STANDARD =STANDARD

=55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE

CLK_LPC_55S

*

103

051-8089

MCP Constraints 2

109

02

SYNC_DATE=08/17/2008SYNC_MASTER=K36B_MLB

USB

?

TOP,BOTTOM

=4x_DIELECTRIC

PCI

* ?

=STANDARD

=55_OHM_SE=55_OHM_SE=55_OHM_SE

=STANDARD

CLK_PCI_55S

*

=55_OHM_SE

=STANDARD

CLK_PCI

* ?

8 MIL

=2x_DIELECTRIC

?*

SMB

?*

8 MIL

MCP_HDA_COMP

=2x_DIELECTRIC

HDA

* ?

=STANDARD

*

=STANDARD

=55_OHM_SE =55_OHM_SE

PCI_55S

=55_OHM_SE =55_OHM_SE

*

CLK_SLOW

?

8 MIL

* ?

USB

=2x_DIELECTRIC

=55_OHM_SE

*

=STANDARD =STANDARD

SMB_55S

=55_OHM_SE =55_OHM_SE =55_OHM_SE

?*

8 MIL

CLK_LPC

=STANDARD =STANDARD

CLK_SLOW_55S

=55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE

*

SPI

?

8 MIL

=STANDARD=STANDARD

*

=55_OHM_SE =55_OHM_SE =55_OHM_SE

SPI_55S

=55_OHM_SE

*

=55_OHM_SE =55_OHM_SE =55_OHM_SE

LPC_55S

=STANDARD

=55_OHM_SE

=STANDARD

MCP_USB_RBIAS

8 MIL 8 MIL

=STANDARD=STANDARD

=STANDARD

*

=STANDARD

*

LPC

6 MIL

?

USB2_BT_F_N_CONN

USB_BT

USB_90D

USB

USB_EXTB

USB_90D

USB_EXTB_P

USB

USB_EXTC_P

USB

USB_90D

USB_EXTC

MCP_USB_RBIAS MCP_USB_RBIAS

MCP_USB_RBIAS_GND

SMBUS_MCP_0_CLK

SMB

SMB_55S

USB_90D

USB

USB_EXTC_N

SMBUS_MCP_0_DATA

SMB

SMBUS_MCP_0_DATA

SMB_55S

USB_MINI_P

USB

USB_90D

USB_MINI

USB2_EXTA_F_N

USB_90D

USB_EXTA

USB

USB_EXTD_N

USB

USB_90D

USB_CAMERA_N

USB_CAMERA

USB

USB_90D

USB2_EXTA_MUXED_P

USB_90D

USB_EXTA

USB

USB2_EXTA_MUXED_N

USB

USB_90D

USB_EXTA

USB_EXTA_P

USB

USB_90D

USB_EXTA

MCP_PCI_CLK2

CLK_PCI_55S

CLK_PCI

PCI_CLK33M_MCP_R

PCI

PCI_FRAME_L

PCI_55S

PCI_CNTL

PCI

PCI_STOP_L

PCI_CNTL

PCI_55S

PCI_CNTL

PCI

PCI_55S

PCI_DEVSEL_L

PCI_AD<23..8>

PCI_AD

PCI

PCI_55S

MCP_DEBUG<7..0>

MCP_DEBUG

PCI

PCI_55S

PCI

PCI_REQ0_L

PCI_55S

PCI_REQ0_L

PCI

PCI_55S

PCI_TRDY_L

PCI_CNTL

PCI_AD24

PCI

PCI_AD<24>

PCI_55S

PCI

PCI_C_BE_L<3..0>

PCI_55S

PCI_C_BE_L

PCI

PCI_AD

PCI_PAR

PCI_55S

PCI

PCI_IRDY_L

PCI_55S

PCI_CNTL

PCI

PCI_PERR_L

PCI_55S

PCI_CNTL PCI_CNTL

PCI

PCI_SERR_L

PCI_55S

PCI_AD

PCI_AD<31..25>

PCI

PCI_55S

PCI

PCI_GNT1_L

PCI_55S

PCI_GNT1_L

PCI

PCI_REQ1_L

PCI_55S

PCI

PCI_GNT0_L

PCI_55S

PCI_GNT0_L

PM_CLK32K_SUSCLK_R

CLK_SLOW

CLK_SLOW_55S

MCP_SUS_CLK

PM_CLK32K_SUSCLK

CLK_SLOW_55S

CLK_SLOW

SPI_CLK_R

SPI_55SSPI_CLK

SPI

SPI_CLK_MUX

SPI_55S

SPI

SPI_55S

SPI

SPI_MOSI

SPI_MOSI_R SPI_MOSI_MUX

SPI_55S

SPI

SPI_MISO_MUX

SPI_55S

SPI_MISO

SPI

SPI_MISO_R

SPI_55S

SPI

SPI_CS0_R_L

SPI_CS0 SPI_55S

SPI

SPI_CS0_L

SPI_55S

SPI

HDA_BIT_CLK

HDA

HDA_55S

HDA_BIT_CLK_R

HDA

HDA_55S

HDA_SYNC_R

HDA

HDA_55S

HDA_SDIN_CODEC

HDA

HDA_55S

MCP_HDA_PULLDN_COMP

MCP_HDA_COMP

HDA_SDOUT_R

HDA

HDA_55S

HDA_SDOUT

HDA

HDA_SDOUT

HDA_SDIN0

HDA_55S

HDA

HDA_RST_L

HDA_55S

HDA

HDA_RST_R_L

HDA

HDA_55S

HDA_RST_L

SMBUS_MCP_1_DATA

SMB

SMB_55S

SMB

SMBUS_MCP_1_CLK

LPC_55S

LPC_AD

LPC

LPC_AD<3..0>

PCI_55S

PCI_INTX_L

PCI

PCI_INTX_L

PCI_CLK33M_MCP

CLK_PCI_55S

CLK_PCI

PCI_INTW_L

PCI

PCI_INTW_L

PCI_55S

LPC_FRAME_L

LPC_55S

LPC

LPC_FRAME_L0

PCI_INTZ_L

PCI_55S

PCI

PCI_INTZ_L

PCI_INTY_L

PCI

PCI_55S

HDA

HDA_SYNC

HDA_55S

HDA_SYNC

USB

USB_90D

USB_EXTA

USB_EXTA_N

USB2_EXTA_F_P

USB_90D

USB_EXTA

USB

USB_EXTD_P

USB

USB_EXTD

USB_90D

LPC_CLK33M_LPCPLUS

MCP_LPC_CLK

CLK_LPC_55S

CLK_LPC

LPC_CLK33M_SMC

MCP_LPC_CLK

CLK_LPC_55S

CLK_LPC

CLK_LPC_55SMCP_LPC_CLK

LPC_CLK33M_SMC_R

LPC_55S

LPC_RESET_L

LPC

LPC_RESET_L

USB_MINI_N

USB

USB_90D

USB_MINI

USB_90D

USB

USB_MINI

USB2_AIRPORT_P USB2_AIRPORT_N

USB

USB_MINI

USB_90D

USB_CAMERA

USB

USB_CAMERA_P

USB_90D

USB_IR

USB_90D

USB_IR_P

USB

USB2_CAMERA_CONN_N

USB_90D

USB

USB_CAMERA

USB2_CAMERA_CONN_P

USB_90D

USB_CAMERA

USB

USB_IR_N

USB_IR

USB

USB_90D

USB_TPAD_N

USB_TPAD

USB_90D

USB

USB_TPAD_P

USB_TPAD

USB_90D

USB

USB_EXTB

USB

USB_90D

USB2_EXTB_F_P

USB_90D

USB

USB_EXTB

USB2_EXTB_F_N

USB_90D

USB

USB_EXCARD_N

USB_90D

USB

USB_EXCARD_P

USB_EXCARD

USB_BT

USB2_BT_F_P_CONN

USB_90D

USB

USB_BT

USB_BT_N

USB

USB_90D

USB_BT

USB

USB_90D

USB_BT_P

CONN_TPAD_USB_N

USB_TPAD

USB

USB_90D

CONN_TPAD_USB_P

USB_TPAD

USB_90D

USB

USB_EXTB

USB_EXTB_N

USB_90D

USB

21

7

40

20 39

9

20

7

13 21 44

9

20

7

13 21 44

9

20

39

9

20

20 66

39

20 39

19

7

13 19

19

21 26

26 41

21 43

43 51

43

43 51

51

21 43

21 52

21

21 52

21

44

21 44

7

19 41 43

19

7

19 41 43

21 52

20 39

39

9

20

7

26 43

26 41

19 26

9

20

7

31

7

31

20 66

20 40

7

66

7

66

20 40

9

20

9

20

39

9

20

9

20

7

40

9

20

9

20

7

49

7

49

20 39

TABLE_PHYSICAL_RULE_ITEM

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MCP RGMII (Ethernet) Constraints

ELECTRICAL_CONSTRAINT_SET

SPACING

NET_TYPE

88E1116R (Ethernet PHY) Constraints

SOURCE: MCP73 Interface DG (DG-02974-001_v01), Sections 2.7.2 & 2.7.4

SOURCE: MCP73 Interface DG (DG-02974-001_v01), Section 2.7.4

PHYSICAL

12 MIL

ENET_MII

* ?

ENET_MDI

* ?

25 MIL

=55_OHM_SE

*

=STANDARD=STANDARD

ENET_MII_55S

=55_OHM_SE =55_OHM_SE =55_OHM_SE

=3:1_SPACING

?

MCP_BUF0_CLK

*

=STANDARD

MCP_MII_COMP

*

7.5 MIL

=STANDARD=STANDARD

=STANDARD

7.5 MIL

SYNC_MASTER=K36B_MLB SYNC_DATE=08/17/2008

02

109

Ethernet Constraints

051-8089

104

ENET_MDI_100D

=100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF

*

=100_OHM_DIFF

ENET_RXD<3..1>

ENET_MII

ENET_MII_55S

ENET_RXD_STRAP

ENET_MII

ENET_MII_55S

ENET_CLK125M_TXCLK_R

ENET_CLK125M_TXCLK

ENET_TXCLK

ENET_MII

ENET_MII_55S

ENET_MDI

ENET_MDI_N<3..0>

ENET_MDI_100D

ENET_MDIENET_MDI

ENET_MDI_P<3..0>

ENET_MDI_100D

ENET_MII

ENET_MII_55S

ENET_RESET_L

ENET_TXD<3..1>

ENET_TXD ENET_MII

ENET_MII_55S

ENET_MII

ENET_TX_CTRL

ENET_TXD

ENET_TXD<0>

ENET_TXD0

ENET_MII_55S

ENET_MII

ENET_MIIENET_RXD

ENET_MII_55S

ENET_RX_CTRL

MCP_MII_COMPMCP_MII_COMP

MCP_MII_COMP_VDD

ENET_MII_55S

ENET_INTR_L

ENET_MII

ENET_INTR_L

ENET_MII_55S

MCP_CLK25M_BUF0_R

MCP_CLK25M_BUF0

MCP_BUF0_CLK

MCP_MII_COMPMCP_MII_COMP

MCP_MII_COMP_GND

ENET_MII_55S MCP_BUF0_CLK

MCP_CLK25M_BUF0

ENET_MDIO

ENET_MII_55S

ENET_MII

ENET_MDIO

ENET_MII

ENET_MDC

ENET_MII_55S

ENET_MDC

ENET_MII

ENET_MII_55S

ENET_CLK125M_RXCLK

ENET_RXCLK

ENET_MII_55S

ENET_MII

ENET_CLK125M_RXCLK_R

ENET_PWRDWN_L

ENET_MII_55S

ENET_MII

18

18 32

32

18 32

32 34

18 32

18

18 33

18 32

32

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

FireWire Net Properties

ELECTRICAL_CONSTRAINT_SET

Port 2 Not Used

SPACING

NET_TYPE

PHYSICAL

FireWire Interface Constraints

*

=3:1_SPACING

?

FW_TP

=110_OHM_DIFF

FW_110D

=110_OHM_DIFF=110_OHM_DIFF

=110_OHM_DIFF

*

=110_OHM_DIFF

SYNC_MASTER=K36B_MLB SYNC_DATE=08/17/2008

02

109

FireWire Constraints

051-8089

105

FW_P1_TPB

FW_110D

FW_P1_TPB_P

FW_TP

FW_110D

FW_TP

FW_P1_TPB

FW_P1_TPB_N

FW_P1_TPA

FW_110D

FW_TP

FW_P1_TPA_N

FW_PORT_A_P

FW_P1_TPA

FW_110D

FW_TP

FW_P1_TPA

FW_110D

FW_TP

FW_PORT_A_N

FW_P1_TPB

FW_110D

FW_TP

FW_PORT_B_P

FW_110D

FW_TP

FW_P1_TPB

FW_PORT_B_N

FW_P1_TPA

FW_TP

FW_110D

FW_P1_TPA_P

FW_P0_TPB

FW_TP

FW_110D

FW_P0_TPB_N

FW_TP

FW_110D

FW_P0_TPB_P

FW_P0_TPB

FW_110D

FW_P0_TPA_N

FW_TP

FW_P0_TPA

FW_P0_TPA_P

FW_110D

FW_TP

FW_P0_TPA

35

37

35 37

37

35 37

37

35 37

TABLE_PHYSICAL_RULE_ITEM

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

PHYSICAL

SPACING

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

SPACING

SMC SMBus Net Properties

NET_TYPE

SMBus Charger Net Properties

=STANDARD =STANDARD =STANDARD

0.1 MM 0.1 MM

*

=STANDARD

1TO1_DIFFPAIR

106

051-8089

SMC Constraints

109

02

SYNC_DATE=08/17/2008SYNC_MASTER=K36B_MLB

SMB_55S

SMBUS_SMC_MGMT_SDA

SMB

SMBUS_SMC_MGMT_SDA

SMB_55S

SMBUS_SMC_MGMT_SCL

SMB

SMBUS_SMC_MGMT_SCL

SMBUS_SMC_A_S3_SDA

SMB_55S

SMB

SMBUS_SMC_A_S3_SDA

SMBUS_SMC_B_S0_SCL

SMB

SMB_55S

SMBUS_SMC_B_S0_SCL

SMB

SMBUS_SMC_A_S3_SCL

SMB_55S

SMBUS_SMC_A_S3_SCL

SMBUS_SMC_B_S0_SDA

SMB

SMB_55S

SMBUS_SMC_B_S0_SDA

SMB

SMB_55S

SMBUS_SMC_0_S0_SCL

CHGR_CSI_P

1TO1_DIFFPAIR

CHGR_CSI

CHGR_CSI_N

1TO1_DIFFPAIR

CHGR_CSO_N

1TO1_DIFFPAIR

CHGR_CSO_P

1TO1_DIFFPAIR

CHGR_CSO

SMB

SMB_55S

SMBUS_SMC_0_S0_SDA

SMB

SMBUS_SMC_BSA_SCL

SMB_55S

SMBUS_SMC_BSA_SCL

SMBUS_SMC_BSA_SDA

SMB

SMB_55S

SMBUS_SMC_BSA_SDA

44

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_BOARD_INFO

VERSION

ALLEGRO

(MIL or MM)

BOARD UNITS

BOARD LAYERS

BOARD AREAS

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

K36B BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS

0.165 MM

TOP,BOTTOM

0.165 MM

40_OHM_SE

Y

ISL3,ISL4,ISL9,ISL10

70_OHM_DIFF

Y

0.200 MM0.200 MM

0.175 MM0.175 MM

TOP,BOTTOM

27P4_OHM_SE

Y

0.310 MM0.310 MM

0.400 MM0.400 MM

0.095 MM0.095 MM

ISL3,ISL4,ISL9,ISL10

100_OHM_DIFF_HDD

Y

0.400 MM0.400 MM

0.095 MM0.095 MM

TOP,BOTTOM

100_OHM_DIFF_HDD

Y

=STANDARD

N*

100_OHM_DIFF_HDD

=STANDARD

=STANDARD =STANDARD

=STANDARD

110_OHM_DIFF

=STANDARD

*

=STANDARD=STANDARD

N

=STANDARD

110_OHM_DIFF

Y

ISL3,ISL4,ISL9,ISL10

0.330 MM 0.330 MM

0.075 MM0.075 MM

=STANDARD

1:1_DIFFPAIR

*

0.1 MM0.1 MM

=STANDARD=STANDARD

Y

110_OHM_DIFF

TOP,BOTTOM

Y

0.330 MM 0.330 MM

0.077 MM0.077 MM

TOP,BOTTOM

0.185 MM

70_OHM_DIFF

Y

0.185 MM

0.200 MM0.200 MM

100_OHM_DIFF

=STANDARD

*

=STANDARD

=STANDARD=STANDARD

N

=STANDARD

0.230 MM

100_OHM_DIFF

TOP,BOTTOM

0.091 MM

0.230 MM

0.091 MM

Y

100_OHM_DIFF

ISL3,ISL4,ISL9,ISL10

0.089 MM

0.230 MM 0.230 MM

0.089 MM

Y

*

=STANDARD=STANDARD

90_OHM_DIFF

=STANDARD

N

=STANDARD

TOP,BOTTOM

Y

90_OHM_DIFF

0.220 MM 0.220 MM

0.112 MM0.112 MM

=STANDARD

27P4_OHM_SE

* Y

=STANDARD =STANDARD

0.275 MM0.275 MM

0.380 MM

5X_DIELECTRIC

?

*

4X_DIELECTRIC

0.304 MM

?

*

0.228 MM

3X_DIELECTRIC

?

*

0.152 MM

2X_DIELECTRIC

?

*

0.350 MM

TOP,BOTTOM

?

5X_DIELECTRIC

0.210 MM

?

3X_DIELECTRIC

TOP,BOTTOM

0.140 MM

TOP,BOTTOM

?

2X_DIELECTRIC

?*

0.4 MM

4:1_SPACING

*

0.3 MM

?

3:1_SPACING

1.5:1_SPACING

*

0.15 MM

?

2:1_SPACING

0.2 MM

* ?

0.25 MM

?

2.5:1_SPACING

*

=DEFAULT

?

BGA_P3MM

=DEFAULTBGA_P2MM

* ?

*

0.1 MM

?

DEFAULT

STANDARD

* ?

=DEFAULT

BGA_P1MM

?*

=DEFAULT

BGA_P2MMBGA_P1MM

*

CLK_PCIE

BGA_P1MMCLK_SLOW

*

BGA_P2MM

BGA_P1MMFSB_DSTB BGA_P3MMFSB_DSTB

BGA_P1MM BGA_P2MM

*

CLK_PCI

CLK_LPC

BGA_P2MM

*

BGA_P1MM

BGA_P2MM

*

CLK_FSB

BGA_P1MM

* *

BGA_P1MM BGA_P1MM

*

BGA_P2MMBGA_P1MM

MEM_CLK

BGA_P1MM STANDARD

MEM_40S

STANDARDBGA_P1MM

MEM_40S_VDD

0.280 MM

TOP,BOTTOM

?

4X_DIELECTRIC

0.109 MM

ISL3,ISL4,ISL9,ISL10

90_OHM_DIFF

Y

0.220 MM 0.220 MM

0.109 MM

=STANDARD

70_OHM_DIFF

=STANDARD

* N

=STANDARD

TOP,BOTTOM

50_OHM_SE

Y

0.115 MM 0.115 MM

0.076 MM

*

0.076 MM

55_OHM_SE =STANDARD

=STANDARD

Y

=STANDARD

*

40_OHM_SE

Y

=STANDARD

0.145 MM0.145 MM

0.090 MM

50_OHM_SE

* Y

=STANDARD =STANDARD

=STANDARD

0.090 MM

TOP,BOTTOM

55_OHM_SE

Y

0.090 MM 0.090 MM

STANDARD =DEFAULT

=DEFAULT

*

=DEFAULT

12.7 MM

Y

=DEFAULT

*

DEFAULT

=50_OHM_SE=50_OHM_SE

30 MM

Y

0 MM 0 MM

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM

MM

15.5.1

NO_TYPE,BGA_P1MM

SYNC_DATE=08/17/2008SYNC_MASTER=K36B_MLB

02

109

K36B RULE DEFINITIONS

051-8089

109

Apple A1181, K36C Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual