Apple iMAC G5 iSight FINO M33 MLB 051-6863 Rev07 Schematic
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
78
6
5
4
3
ECN
ZONE
REV
DESCRIPTION OF CHANGE
FINO M33
07
ENGINEERING RELEASED
381758
12
CK
APPD
DATE
05/19/05
ENG
APPD
?
DATE
5/19/05
D
2
2
4
3
TABLE_TABLEOFCONTENTS_ITEM
5
4
TABLE_TABLEOFCONTENTS_ITEM
6
5
TABLE_TABLEOFCONTENTS_ITEM
7
6
TABLE_TABLEOFCONTENTS_ITEM
8
7
TABLE_TABLEOFCONTENTS_ITEM
9
8
TABLE_TABLEOFCONTENTS_ITEM
11
9
TABLE_TABLEOFCONTENTS_ITEM
12
10
TABLE_TABLEOFCONTENTS_ITEM
13
11
C
B
A
TABLE_TABLEOFCONTENTS_ITEM
12
TABLE_TABLEOFCONTENTS_ITEM
13
TABLE_TABLEOFCONTENTS_ITEM
14
TABLE_TABLEOFCONTENTS_ITEM
15
TABLE_TABLEOFCONTENTS_ITEM
16
TABLE_TABLEOFCONTENTS_ITEM
17
TABLE_TABLEOFCONTENTS_ITEM
18
TABLE_TABLEOFCONTENTS_ITEM
19
TABLE_TABLEOFCONTENTS_ITEM
20
TABLE_TABLEOFCONTENTS_ITEM
21
TABLE_TABLEOFCONTENTS_ITEM
22
TABLE_TABLEOFCONTENTS_ITEM
23
TABLE_TABLEOFCONTENTS_ITEM
24
TABLE_TABLEOFCONTENTS_ITEM
25
TABLE_TABLEOFCONTENTS_ITEM
26
TABLE_TABLEOFCONTENTS_ITEM
27
TABLE_TABLEOFCONTENTS_ITEM
28
TABLE_TABLEOFCONTENTS_ITEM
29
TABLE_TABLEOFCONTENTS_ITEM
30
TABLE_TABLEOFCONTENTS_ITEM
31
TABLE_TABLEOFCONTENTS_ITEM
32
TABLE_TABLEOFCONTENTS_ITEM
33
TABLE_TABLEOFCONTENTS_ITEM
34
TABLE_TABLEOFCONTENTS_ITEM
35
TABLE_TABLEOFCONTENTS_ITEM
36
TABLE_TABLEOFCONTENTS_ITEM
37
TABLE_TABLEOFCONTENTS_ITEM
15
16
17
19
20
23
24
25
26
27
28
29
30
31
32
33
39
41
42
43
44
47
48
49
50
52
CONTENTS
System Block Diagram
Power Block Diagram
Table Items
FUNC TEST 1 OF 2
POWER CONN / ALIAS
Signal Alias
FUNC TEST 2 OF 2
1.8V VREG
1.5V Vreg
1.2V Vreg
2.5V Vreg
5V & 3.3V Fets
Vesta Core / Misc
KODIAK CORE & BYPASS
KODIAK & SHASTA MISC
Shasta Core Power
Shasta Serial / Misc
PULSAR2 POWER
PULSAR2 CLOCKS
Pulsar Aliases
System Management Unit
SMU SUPPLEMENTAL (2)
SMU SUPPLEMENTAL (3)
SMU SUPPLEMENTAL (4)
Fan 0, 1 & System Temp
Fan 2 & HD Temp
I2C Connections
KODIAK EI PWR & CAPS
KODIAK EI A
CPU EI AND IO
KODIAK EI B
CPU STRAPS
CPU POWER AND BYPASS
PROC DECOUPLING
CPU VCORE VREG
CPU VCORE MORE BYPASS
8
SYNC MASTER SYNC MASTER
54
FINO-DD
FINO-PC
FINO-DD
FINO-ME
M33-PC
FINO-DD
FINO-ME
M33-PC
FINO-PC
FINO-PC
FINO-PC
FINO-PC
FINO-HC
Q63
FINO-ME
Q63
FINO-ME
Q63
FINO-ME
FINO-ME
Q63
FINO-MS
FINO-MS
FINO-MS
FINO-PC
FINO-PC
FINO-ME
Q63
Q63
FINO-MS
Q63
FINO-MS
FINO-MS
FINO-MS
M33-MS
FINO-MS
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
38
TABLE_TABLEOFCONTENTS_ITEMTABLE_TABLEOFCONTENTS_ITEM
39
TABLE_TABLEOFCONTENTS_ITEM
40
TABLE_TABLEOFCONTENTS_ITEM
41
TABLE_TABLEOFCONTENTS_ITEM
42
TABLE_TABLEOFCONTENTS_ITEM
43
TABLE_TABLEOFCONTENTS_ITEM
44
TABLE_TABLEOFCONTENTS_ITEM
45
TABLE_TABLEOFCONTENTS_ITEM
46
TABLE_TABLEOFCONTENTS_ITEM
47
TABLE_TABLEOFCONTENTS_ITEM
48
TABLE_TABLEOFCONTENTS_ITEM
49
TABLE_TABLEOFCONTENTS_ITEM
50
TABLE_TABLEOFCONTENTS_ITEM
51
TABLE_TABLEOFCONTENTS_ITEM
52
TABLE_TABLEOFCONTENTS_ITEM
53
TABLE_TABLEOFCONTENTS_ITEM
54
TABLE_TABLEOFCONTENTS_ITEM
55
TABLE_TABLEOFCONTENTS_ITEM
56
TABLE_TABLEOFCONTENTS_ITEM
57
TABLE_TABLEOFCONTENTS_ITEM
58
TABLE_TABLEOFCONTENTS_ITEM
59
TABLE_TABLEOFCONTENTS_ITEM
60
TABLE_TABLEOFCONTENTS_ITEM
61
TABLE_TABLEOFCONTENTS_ITEM
62
TABLE_TABLEOFCONTENTS_ITEM
63
TABLE_TABLEOFCONTENTS_ITEM
64
TABLE_TABLEOFCONTENTS_ITEM
65
TABLE_TABLEOFCONTENTS_ITEM
66
TABLE_TABLEOFCONTENTS_ITEM
67
TABLE_TABLEOFCONTENTS_ITEM
68
TABLE_TABLEOFCONTENTS_ITEM
69
TABLE_TABLEOFCONTENTS_ITEM
70
TABLE_TABLEOFCONTENTS_ITEM
71
TABLE_TABLEOFCONTENTS_ITEM
72
TABLE_TABLEOFCONTENTS_ITEM
73
TABLE_TABLEOFCONTENTS_ITEM
55
56
58
59
61
62
63
67
68
69
70
82
84
85
86
87
88
89
90
91
92
93
96
97
98
101
103
119
120
121
122
125
127
129
130
67
CONTENTS
CPU AVDD VREG
T,V,I SENSORS
CPU ALIASES & MISC
KODIAC NBMEM PWR & CAPS
Kodiak Memory Dq/Ctl
Parallel Term
Main Memory Clock Buffer
MEMORY ADDR BRANCHING
Memory Dimm A
MLB Mem Series Term
On-Board DDR SDRAM
On-Board DDR SDRAM
KODIAK PCI-E X16
GPU PCIe
Graphics Vregs
GPU Core Power
GPU Frame Buffer
FB Series Termination
GPU GDDR SDRAM A
GPU GDDR SDRAM B
FB Parallel Termination
GPU Straps
GPU DVI & DACs
TMDS / ExtVGA
KODIAK PCI-E CONST
KODIAK HT16
HT ALIASES
Shasta HyperTransport
Shasta PCI Interface
PCI SERIES TERMINATION
AIRPORT & BLUETOOTH
USB 2.0 PCI Interface
BootROM
Shasta Disk
Disk Connectors
ENET SERIES TERM
5
FINO-MS
FINO-MS
FINO-MS
Q63
FINO-RT
FINO-RT
FINO-RT
FINO-EG
FINO-RT
FINO-RT
FINO-RT
FINO-RT
Q63
FINO-DD
FINO-DD
FINO-DD
FINO-DD
FINO-DD
FINO-DD
FINO-DD
FINO-DD
FINO-DD
Q63
FINO-EG
Q63
Q63
FINO-EG
FINO-EG
Q63
Q63
M33-MB
M33-MB
FINO-HC
4
DATEPDF CSA
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
MASTERM33-DD
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
MASTERM33-DD
05/19/2005
05/19/2005
MASTERM33-DD
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
PDF CSACSAPDF DATE
TABLE_TABLEOFCONTENTS_HEADTABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_HEAD
74
131
TABLE_TABLEOFCONTENTS_ITEM
75
132
TABLE_TABLEOFCONTENTS_ITEM
76
136
TABLE_TABLEOFCONTENTS_ITEM
77
138
TABLE_TABLEOFCONTENTS_ITEM
78
139
TABLE_TABLEOFCONTENTS_ITEM
79
140
TABLE_TABLEOFCONTENTS_ITEM
80
142
TABLE_TABLEOFCONTENTS_ITEM
81
143
TABLE_TABLEOFCONTENTS_ITEM
82
144
TABLE_TABLEOFCONTENTS_ITEM
83
145
TABLE_TABLEOFCONTENTS_ITEM
84
147
TABLE_TABLEOFCONTENTS_ITEM
85
148
TABLE_TABLEOFCONTENTS_ITEM
86
150
TABLE_TABLEOFCONTENTS_ITEM
87
152
TABLE_TABLEOFCONTENTS_ITEM
88
153
TABLE_TABLEOFCONTENTS_ITEM
89
154
TABLE_TABLEOFCONTENTS_ITEM
DIMENSIONS ARE IN MILLIMETERS
XX
X.XX
X.XXX
ANGLES
DO NOT SCALE DRAWING
THIRD ANGLE PROJECTION
3
CONTENTS
Shasta Ethernet
Vesta Ethernet PHY
ETHERNET CONNECTOR
Shasta FireWire
Vesta FireWire PHY
FIREWIRE CONNECTORS
USB Host Interfaces
USB Device Interfaces
Flash Media Ctrl
Flash Connector
AUDIO: CODEC
AUDIO: LINE INPUT AMP
AUDIO: LINE OUT AMP
AUDIO: SPEAKER AMP
AUDIO: CONNECTORS
AUDIO: POWER SUPPLIES
METRIC
NOTED AS
DESIGN CK
MFG APPD
DESIGNER
SCALE
NONE
DRAFTER
ENG APPD
QA APPD
RELEASE
MATERIAL/FINISH
APPLICABLE
SYNC MASTER
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
TITLE
SIZE
DRAWING NUMBER
D
2
Q63
Q63
FINO-HC
Q63
Q63
FINO-HC
Q63
FINO-MB
FINO-PC
FINO-PC
FINO-SO
FINO-SO
FINO-SO
FINO-SO
FINO-SO
FINO-SO
Apple Computer Inc.
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
SCH,MLB,FINO,M33
051-6863
DATE
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
05/19/2005
SHT
1
REV.
1
07
OF
D
C
B
A
154
78
6
U4300
5
4
CPU
NEO 10S
PCIE
PAGE
82
MISC
SATA
PAGE 43,48
APPLE PI
PAGE 42
U1900
KODIAK
CORE
PAGE 19
HYPERTRANSPORT
HYPERTRANSPORT
PAGE 103
U2300
32-BIT
APPLE PI
ELASTIC INTERFACE
667MHZ OR 733MHZ
PAGE 98PAGE 20
64-BIT
MAIN MEMORY
1.8V/533MHZ
PAGE 59
MAIN MEMORY
8-BIT
HYPERTRANSPORT
1.2V/800MHZ
CONTROL = 2.5V
PCI
U6200
CLOCK
BUFFER
PAGE 62
PARALLEL
TERM
PAGE 61
UC500
BOOTROM
PAGE 125 PAGE 122 PAGE 121
PAGE 119
32-bit PCI (5V-3.3V/33MHz)
J6700
DIMM
PAGE 67
JE310/JE320/JE330
USB
CONNECTORS
PAGE 143 PAGE 143
5
321
4
USB
PAGE 142
UC200
USB 2.0
uPD720101
PCI
SERIES
TERM
PAGES 68
JE350
BNDI
INTERFACE
JC150
WIRELESS
CONNECTOR
J9602, J9603
TMDS
EXT VGA
D
U8900, U8901
FRAME
BUFFER A
PAGE 89
U2500
PULSAR2
POWER
C
CLOCKS
PAGE 26PAGE 25
HARD DRIVE
64-BIT
FRAME BUFFER
M23:1.8V/600MHZ
M33:1.8V/700MHZ
JC900
SATA
CONNECTOR
PAGE 129
PAGE 96
U8400
GPU
M23:RV370 XT
M33:RV380 XT
PAGES 84,86,87,93
64-BIT
FRAME BUFFER
M23:1.8V/600MHZ
M33:1.8V/700MHZ
U9000, U9001
FRAME
BUFFER B
PAGE 90
SATA/150
1.2V/1.5GHZ
PCIE X16
2.5GHZ
I2C
PAGE 39
SATA1 SATA2
PAGE 127
3
ONBOARD MEMORY
PAGES 67,70
UE401
PAGE 144
64MX8
MEMORY
USB
HUB
UE400
FLASH
CTLR
PAGE 144
JE500
MEDIA CARD CONNECTOR
CF
PAGE 145
SD
FANS
TEMP SENSORS
PAGES 32,33
U2800
SMU
PAGE 28
SMU SUPPLEMENTAL
BUTTONS
ALS
SYSTEM LED
BATTERY
PAGES 29,30
12
U2801
RTC
PAGE 28
D
C
SHASTA
PAGE 127
JC901
B
OPTICAL
UATA
CONNECTOR
PAGE 129
UATA/133
3.3V/133MHZ
U1701
UATA
CORE
PAGE 23
ETHERNET FIREWIRE
PAGE 131 PAGE 138
8-bit TX & 8-bit RX
GMII (3.3V/125MHz)
NCs
PAGE 142
I2S
PAGE 24
SCCA SCCB
1394 OHCI (3.3V/98MHz)
8-bit TX/RX
I2S1
VESTA
GIG ETHERNET
A
4 Diff pairs
JD600
ETHERNET
CONNECTOR
PAGE 136 PAGE 140
FIREWIRE A
PAGE 139PAGE 132
1
0
2 Diff pairs
JEC00, JEC01
FIREWIRE A
CONNECTORS
PAGE 24
GPIO/PCI64
I2S2I2S0
UE700
AUDIO CODEC
PCM3052A
LINE IN
AMP
PAGE 148
JF300
LINE IN
CONNECTOR
PAGE 153
PAGE 147
BNDI
INTERFACE
S/PDIF
LINE OUT
AMP
PAGE 150
SPEAKER
AMP
PAGE 152
OPTICAL OUT
JF303
COMBO OUT
CONNECTOR
PAGE 153
LINE OUT
JF301
SPEAKER
CONNECTOR
PAGE 153
System Block Diagram
SYNC_MASTER=FINO-DD
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
APPLE COMPUTER INC.
SYNC_DATE=05/19/2005
NOTICE OF PROPRIETARY PROPERTY
SIZE
DRAWING NUMBER
051-6863
D
NONE
SHT
2
SCALE
B
A
REV.
07
OF
154
8
67
5
4
3
2
1
78
6
5
4
3
12
D
C
B
J700
PAGE 7
PP12V_ALL
FW CONN
PP1V5_PWRON
SWITCHER
PAGE 12
PULSAR
KODIAK CORE
PP1V5_RUN
FET SWITCH
PAGE 12
EI
GPU CORE
SWITCHER
PAGE 85 PAGE 11
PP12V_RUN
20" PANEL POWER
17" LCD INVERTER
CPU CORE
SWITCHER
PAGE 50
PP1V8_PWRON
SWITCHER
MAIN MEMORY
PP1V8_RUN
POWER SW
PAGE 11
GPU MEMORY
PP0V9_GPU_VTT
LINEAR
PAGE 91
PP1V8_RUN
IN
POWER CONNECTOR
PP5V_RUN
OPTICAL
PP4V5_RUN_AUDIO
LINEAR
PAGE 154
AUDIO CODEC
PP5V_PWRON
FET SWITCH
PAGE 16
PP2V5_PWRON
PAGE 15
PP5V_ALL
USB CONN
FET SWITCH
PP2V5_ALL
LINEAR
PAGE 15
PP2V5_RUN
FET SWITCH
PAGE 15
VESTA
PP3V3_PWRON
PAGE 16
FET SWITCH
MODEM & BT
USB2 HOST
PP1V8_TPVDD
LINEAR
PAGE 85
PP3V3_RUNPP3V3_ALL
PP2V5_RUN_CPU_AVDD
LINEAR
PAGE 54
PP1V8_GPU
LINEAR
PAGE 85
SYS_POWERUP_L
PCI BUS
AUDIO CODEC
PP1V5_VDDC_CT
LINEAR
PAGE 85
PP1V2_PWRON
PAGE 13
SHASTA CORE
PAGE 13
PP2V5_GPU_A2VDD
LINEAR
PAGE 85
PP1V2_TPVDD
PAGE 85
FET SWITCH
R440
100K
5%
1/16W
MF-LF
402
PP1V2_ALL
SWITCHER
VESTA CORE
LINEAR
IN
IN
PP1V2_PWRON
21
1
C440
0.01UF
20%
16V
2
CERM
402
COMPARE_PP1V8
NC_SMU_PWRSEQ_P1_0
6
NC_SMU_PWRSEQ_P1_4
6
13 12 13 12
PP3V3_PWRON
TURN_ON_PP3V3_PWRON_L
15
16
PP1V2_RUN
FET SWITCH
PAGE 13
PP2V5_ALL
TURN_ON_PP1V2_L
PWR_GOOD_PP1V2
PWR_GOOD_PP1V8
IN
HT BUS
1
R442
150K
5%
1/16W
MF-LF
402
2
PS_1V_REF
4
1
R443
100K
1%
1/16W
MF-LF
402
2
SYS_POWERUP_L
POWER SEQUENCE PIN
SMU_PWRSEQ_P1_0
SMU_PWRSEQ_P1_4
SMU_PWRSEQ_P1_1
SMU_PWRSEQ_P9_5
SMU_PWRSEQ_P9_6
SMU_PWRSEQ_P1_2
SMU_PWRSEQ_P1_3
R430
100K
5%
1/16W
MF-LF
402
PP5V_ALL
3
V+
U400
GND
12
LM339A
SOI-LF
6
7
PS_1V_REF
4
21
COMPARE_PP1V2
1
C430
0.01UF
20%
16V
2
CERM
402
1
1
2
28
28
28
28
28
28
28
PP2V5_ALL
C441
0.1UF
20%
10V
CERM
402
SMU
1
R441
10K
5%
1/16W
MF-LF
402
2
PP2V5_ALL
1
2
8
9
R431
10K
5%
1/16W
MF-LF
402
V+
U400
GND
12
3
LM339A
SOI-LF
14
D
C
B
PP2V5_ALL
A
8
67
5
4
U400P2
3
V+
U400
GND
LM339A
SOI-LF
2
12
APPLE COMPUTER INC.
3
2
4
5
Power Block Diagram
SYNC_MASTER=FINO-PC
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
NONE
SHT
SCALE
SYNC_DATE=05/19/2005
051-6863
OF
4
1
A
REV.
07
154
78
6
5
4
3
12
PROCESSORS
QTY
D
337S3158
1
1
PART NUMBER
337S3165 337S3158
337S3164 337S3157 CPU_2_2GHZ
ALTERNATE FOR
PART NUMBER
DEVICE
PROCESSOR
PROCESSOR
PACKAGE
CBGA-576-1MM
CBGA-576-1MM
DESCRIPTION
IC,GPUL,DD3.1,2.0G,85C,CQA
IC,GPUL,DD3.1,2.2G,85C,FQA
BOM OPTION
CPU_2_0GHZ
REF DES
U4300
U4300
COMMENTS:
IC,DD3.1,2.0G,CJA
IC,DD3.1,2.0G,FJA
VALUE VOLT. WATT.
1.15V
2.2GHZ337S3157
1.15V
TABLE_ALT_HEAD
VOLTAGE
TABLE_ALT_ITEM
1.20V
TABLE_ALT_ITEM
1.20V
46W
51W
REFERENCE DESIGNATOR(S)
TOL.PART #
50MV
50MV
U4300
U4300
BOM OPTION
CPU_2_0GHZ2.0GHZ
CPU_2_2GHZ
TABLE_11_HEAD
TABLE_11_HEAD
TABLE_11_HEAD
C
PART#
343S0371
343S0283
343S0324
343S0319
PART#
051-6790
051-6863
820-1783
820-1766
825-6447
341T1751
341T1752
603-7318
603-7321
603-7322
875-1614
QTY
DESCRIPTION
1
IC,KODIAK,V1.1,PBGA,200MM
1
IC,ASIC,SHASTA,V1.1,PBGA
IC,ASIC,VESTA,V1.3
1
1
IC,PULSAR2,100P,P8MM,BGA
QTY
DESCRIPTION
PCB,SCHEM,MLB,M23
1
PCB,SCHEM,MLB,M33
1
1
PCB,FAB,MLB,M23
1
PCB,FAB,MLB,M33
1
SPEC,VENDOR PACKAGING PROCEDURE
1
BARCODE LABEL, MLB
1
IC,FLASH,1MX8,3.3V,90NS
1
PURCH ASSY, SMU BIG
1
M23 CPU HEATSINK
1
M33 CPU HEATSINK
M33 GPU HEATSINK
1
1
CPU GAP FILLER
ASICS
REFERENCE DESIGNATOR(S)
U1900
U2300
U1701
U2500
MISC PARTS
REFERENCE DESIGNATOR(S)
UC500
U2800
MECH1
MECH1
MECH2
SCH1
SCH1
MLB1
MLB1
VPP1062-2082
LBL1
GAP1
BOM OPTION
BOM OPTION
17_INCH_LCD
20_INCH_LCD
17_INCH_LCD
20_INCH_LCD
17_INCH_LCD
20_INCH_LCD
20_INCH_LCD
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
D
C
ALTERNATES
PART NUMBER
378S0119
376S0204 376S0130
B
376S0207 376S0146
ALTERNATE FOR
PART NUMBER
378S0114
BOM OPTION
REF DES
LED700,LED702
Q5010,Q5020
Q5011,Q5021
COMMENTS:
KINGBRIGHT LED
MOSFET,N-CH,VISHAY
MOSFET,N-CH,VISHAY
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
B
Table Items
A
APPLE COMPUTER INC.
SYNC_MASTER=FINO-DD
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
051-6863
D
SCALE
NONE
SYNC_DATE=05/19/2005
SHT
5
A
REV.
07
OF
154
8
67
5
4
3
2
1
78
6
5
4
3
12
NO TEST XW NETS
NO_TEST=YES
I947
NO_TEST=YES
I948
NO_TEST=YES
I949
NO_TEST=YES
I950
NO_TEST=YES
I951
NO_TEST=YES
I952
NO_TEST=YES
I953
NO_TEST=YES
I954
NO_TEST=YES
I984
D
I985
I986
I987
I988
I989
I990
I991
I992
I993
I994
I995
I996
I997
I1042
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
GND_U1100
GND_U1200
GND_U1300
PP_2V5PWRONNBMISC
PP_1V2PWRONSBVCORE
PP_3V3PWRONSBPCI64
PP_2V5PWRONSB
PP_1V2PWRONSBPLL45VDD
PP_OVDD_PULSAR1
PP_1V2PWRONPULSAR1
PP_1V5PULSAR2
PP_1V5PWRONPULSAR2
GND_SMU_AVSS
PP_3V3ALLSMUAVCC
PP_3V3ALLSMU
PP_VEINB
GND_CPU_AVDD
VC_AGND
VC_OUTSEN_R
KPVDD2_FMAX
GND_GPU_PVSS
GND_GPU_MPVSS
GND_AUDIO_MIC
EE IDENTIFIED NO TEST NETS
NO_TEST=YES
I955
NO_TEST=YES
I957
NO_TEST=YES
I958
NO_TEST=YES
I959
NO_TEST=YES
I960
NO_TEST=YES
I961
C
B
A
I962
I963
I964
I965
I969
I971
I972
I973
I975
I974
I976
I978
I977
I982
I1045
I1046
I1047
I1048
I1049
I1050
I1051
I1052
I1054
I1053
I1055
I1057
I1056
I1060
I1058
I1059
I1062
I1061
I1063
I1065
I1064
I1068
I1066
I1067
I1069
I1070
I1071
I1072
I1160
I1161
I1162
I1164
I1165
I1166
I1167
I1168
I1170
I1171
I1172
I1173
I1175
I1176
I1177
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NC_EI_NB_TO_CPU_B_CLK_P
NC_EI_NB_TO_CPU_B_CLK_N
NC_EI_NB_TO_CPU_B_AD<0..43>
NC_EI_NB_TO_CPU_B_SR_P<0..1>
NC_EI_NB_TO_CPU_B_SR_N<0..1>
NC_EI_CPU_B_TO_NB_CLK_P
NC_EI_CPU_B_TO_NB_CLK_N
NC_EI_CPU_B_TO_NB_AD<0..43>
NC_EI_CPU_B_TO_NB_SR_P<0..1>
NC_EI_CPU_B_TO_NB_SR_N<0..1>
NC_NB_CPU_A1_INT_L
NC_NB_CPU_B0_INT_L
NC_NB_CPU_B1_INT_L
NC_CPU_A1_QACK_L
NC_CPU_B0_QACK_L
NC_CPU_B1_QACK_L
NC_HT_MB_TO_NB_CAD_P<8..15>
NC_HT_MB_TO_NB_CAD_N<8..15>
NC_HT_NB_TO_MB_CAD_P<8..15>
NC_HT_NB_TO_MB_CAD_N<8..15>
NC_CLK_RAI_200M_N<0>
NC_CLK_RAI_200M_P<0>
NC_CLK_RAI_PCIEA_N<0>
NC_CLK_RAI_PCIEA_P<0>
NC_CLK_RAI_PCIEB_N<0>
NC_CLK_RAI_PCIEB_P<0>
NC_CLK_RAI_PCIEC_N<0>
NC_CLK_RAI_PCIEC_P<0>
NC_A_AVREG_0
NC_A_AVREG_1
NC_A_AVREG_2
NC_CPU_B_APSYNC
NC_EI_CPU_B_SYSCLK_N
NC_EI_CPU_B_SYSCLK_P
NC_HT_NB_TO_MB_CLK_N<1>
NC_HT_NB_TO_MB_CLK_P<1>
NC_J2904_11
NC_J2904_12
NC_NCV1009_1
NC_NCV1009_2
NC_NCV1009_3
NC_NCV1009_4
NC_NCV1009_5
NC_NCV1009_ADJ
NC_RAM_ARB0_REF25MHZ
NC_RAM_ARB1_REF25MHZ
NC_SMU_PWRSEQ_P1_0
NC_SMU_PWRSEQ_P1_4
RFBD<38>
RFBD<37>
RFBD<36>
RFBD<34>
RFBD<33>
RFBD<32>
RFBD<31>
RFBD<30>
RFBD<28>
RFBD<27>
RFBD<26>
RFBD<25>
RFBD<23>
RFBD<22>
RFBD<21>
NO_TEST=YES
I307
NO_TEST=YES
NO_TEST=YES
I998
12
13
20
23
23
23
24
25
25
25
25
55
28
28
28
41
48
50
50
55
86
87
154
153
NO_TEST=YES
I1000
NO_TEST=YES
I999
NO_TEST=YES
I1002
NO_TEST=YES
I1001
NO_TEST=YES
I1003
NO_TEST=YES
I1004
NO_TEST=YES
I1005
NO_TEST=YES
I1007
NO_TEST=YES
I1006
NO_TEST=YES
I1008
NO_TEST=YES
I1010
NO_TEST=YES
I1009
NO_TEST=YES
I1011
NO_TEST=YES
I1027
NO_TEST=YES
I1026
NO_TEST=YES
I1029
NO_TEST=YES
I1028
NO_TEST=YES
I1031
NO_TEST=YES
I1030
NO_TEST=YES
I1033
NO_TEST=YES
I1032
NO_TEST=YES
I1043 I1044
I1096
I1097
I1098
I1099
I1100
I1101
I1102
I1103
I1104
I1105
I1106
I1107
I1108
I1109
I1110
I1111
I1112
I1113
I1114
I1115
I1116
I1117
I1118
I1120
I1121
I1122
I1123
I1124
I1125
I1126
I1127
I1128
I1129
I1130
I1131
I1132
I1133
I1134
I1135
I1136
I1137
I1138
I1139
I1140
I1141
I1142
I1143
I1155
I1156
I1157
I1158
I1179
I1181
I1183
I1182
I1184
I1185
I1188
I1187
I1189
I1190
I1192
I1193
I1196
I1195
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
56
56
56
56
56
56
56
56
56
56
56
56
56
56
56
56
101
101
101
101
27
27
27
27
27
27
27
27
82
82
82
27
27
27
101
101
29
29
55
55
55
55
55
55
27
27
4
4
89
88
89
88
89
88
89
88
89
88
89
88
89
88
89
88
89
88
88
89
88
89
88
89
88
89
88
89
88
89
GND_GPU_TPVSS
GND_GPU_TXVSSR
GND_GPU_VSSDI
GND_GPU_AVSSN
GND_GPU_AVSSQ
GND_GPU_A2VSSN
GND_GPU_A2VSSQ
KOD_L15_GND
PP_3V3SBPCI_B9
PP_2V5PWRONSB_B9
PP_VIOPCIUSB2_C2
PP_1V2PWRONDISKSB_CC
PP2V5_VESTA_BIASVDD1
PP2V5_VESTA_XTALVDD1
PP1V2_VESTA_PLLVDD1
PP1V2_VESTA_PLLVDD2
PP2V5_VESTA_BIASVDD2
PP2V5_VESTA_XTALVDD2
PP1V2_VESTA_FAVDDL
PP2V5_VESTA_FAVDDM
PP3V3_VESTA_FAVDDH
PP3V3_PWRON_NEC_AVDD
GND_AUD_LOAMP
KPVDD2
KPGND2
CPU_DIODE_POS
CPU_DIODE_NEG
FMAXT_P
FMAXT_M
CORE_ISNS_P
CORE_ISNS_M
PPV_RUN_CPU_AVDD_R_L
NC_CLK_RAI_GIGE_25MHZ
NC_CLK_RAI_REFCLK_66M
NC_CPU_B_TBEN_CLK_US
NC_PMR_CLK_DIS_L
NC_I2S2_MCLK
NC_SATA_RXD_N2_C
NC_SATA_RXD_P2_C
NC_SATA_TXD_N2
NC_SATA_TXD_P2
TP_SB<29>
TP_SB<28>
TP_SB<27>
TP_SB<26>
TP_SB<25>
TP_SB<24>
TP_SB<23>
TP_SB<22>
TP_SB<21>
TP_SB<20>
TP_SB<19>
TP_SB<18>
TP_SB<17>
TP_SB<16>
TP_SB<15>
TP_SB<14>
TP_SB<13>
TP_SB<12>
TP_SB<11>
TP_SB<10>
TP_SB<9>
TP_SB<8>
TP_SB<7>
TP_SB<6>
TP_SB<5>
TP_SB<4>
TP_SB<3>
TP_SB<2>
TP_SB<1>
TP_SB<0>
RFBD<61>
RFBD<60>
RFBD<59>
RFBD<57>
RFBD<56>
P
RFBD<54>
RFBD<53>
RFBD<52>
RFBD<50>
RFBD<49>
RFBD<48>
RFBD<47>
RFBD<45>
RFBD<44>
RFBD<42>
RFBD<41>
RFBD<40>
re
93 11
93
93
93
93
93
93
98
101
119
119
122
127
132
132
132
139
139
139
139
139
139
142
154
150
I1012
I1014
I1013
I1016
I1015
I1017
I1018
I1019
I1020
I1022
I1024
I1023
I1035
I1034
I1037
I1036
I1039
I1038
I1041
I1040
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
55
50
48
55
50
48
55
48
48
55
55
55
55
55
48
27
27
26
20
154
129
129
129
129
142
142
142
142
142
142
142
142
142
142
142
142
142
142
142
142
142
142
142
142
142
142
142
142
142
142
142
142
142
142
89
88
88
89
88
89
89
88
88
89
88
89
89
88
88
89
89
88
89
88
89
88
89
88
88
89
88
89
88
89
88
89
89
88
I1197
I1200
I1199
I1202
I1203
I1204
I1206
I1207
I1208
I1210
I1211
I1212
I1214
I1215
I1216
I1218
I1220
I1219
I1221
I1223
I1224
I1226
I1227
I1228
I1229
I1230
I1232
I1233
I1234
I1236
I1237
I1238
I1239
I1242
I1241
I1244
I1245
I1246
I1248
I1249
I1250
I1252
I1253
I1254
I1255
I1257
I1258
I1259
I1262
GND_NEC_AVSS_R
GND_AUDIO_SPKRAMP_PLANE
GND_AUDIO_CODEC
KPGND2_FMAX
TDIODE_POS_FMAX
TDIODE_NEG_FMAX
DAGND
INA138_OUT
RAMCLK_AVSS
PP12V_AUDIO_SPKRAMP
GND_AUDIO
GND_AUDIO_SPKRAMP
KOD_H05_GND
KOD_K07_GND
KOD_G10_GND
KOD_J13_GND
KOD_L13_GND
KOD_H08_GND
PCIE_SLOTA_PRSNT_L
U8500_GND
GND_AUD_LOAMP_CHGPMP
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
l
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
RFBD<126>
RFBD<125>
RFBD<124>
RFBD<122>
RFBD<121>
RFBD<120>
RFBD<118>
RFBD<117>
RFBD<116>
RFBD<114>
RFBD<113>
RFBD<112>
RFBD<110>
RFBD<109>
RFBD<108>
RFBD<106>
RFBD<105>
RFBD<104>
RFBD<102>
RFBD<101>
RFBD<100>
RFBD<98>
RFBD<97>
RFBD<96>
RFBD<95>
i
RFBD<94>
RFBD<92>
RFBD<91>
RFBD<90>
RFBD<88>
RFBD<87>
RFBD<86>
RFBD<85>
RFBD<83>
RFBD<82>
RFBD<81>
RFBD<79>
RFBD<78>
RFBD<76>
RFBD<75>
RFBD<74>
RFBD<72>
RFBD<71>
RFBD<70>
RFBD<69>
RFBD<67>
RFBD<66>
RFBD<65>
RFBD<62>
142
154
152
154
150
148
147
55
55
55
55
55
62
152
7
154
7
154
152
7
97
82
97
82
97
82
97
82
97
82
97
82
84
82
85
154
150
90
88
90
88
90
88
90
88
90
88
90
88
90
88
90
88
90
88
90
88
90
88
90
88
90
88
90
88
90
88
90
88
90
88
90
88
90
88
90
88
90
88
m
90
88
90
88
90
88
90
88
90
88
90
88
90
88
90
88
90
88
90
88
90
88
90
88
90
88
90
88
90
88
90
88
90
88
90
88
90
88
90
88
90
88
90
88
90
88
90
88
90
88
90
88
90
88
89
88
I826
NO_TEST=YES
I837
NO_TEST=YES
I836
NO_TEST=YES
I839
NO_TEST=YES
I841
NO_TEST=YES
I846
NO_TEST=YES
I847
NO_TEST=YES
I848
NO_TEST=YES
I849
NO_TEST=YES
I850
NO_TEST=YES
I851
NO_TEST=YES
I429
NO_TEST=YES
I428
NO_TEST=YES
I375
NO_TEST=YES
I376
NO_TEST=YES
I348
NO_TEST=YES
I350
NO_TEST=YES
I349
NO_TEST=YES
I356
NO_TEST=YES
I357
NO_TEST=YES
I358
NO_TEST=YES
I360
NO_TEST=YES
I362
NO_TEST=YES
I361
NO_TEST=YES
I883
NO_TEST=YES
I1263
NO_TEST=YES
I1264
NO_TEST=YES
I1266
NO_TEST=YES
I1267
NO_TEST=YES
I1268
NO_TEST=YES
I1269
NO_TEST=YES
I1271
NO_TEST=YES
I1272
NO_TEST=YES
I1273
NO_TEST=YES
I1275
NO_TEST=YES
I1277
NO_TEST=YES
I1276
NO_TEST=YES
I1278
NO_TEST=YES
I1280
NO_TEST=YES
I1281
NO_TEST=YES
I1283
NO_TEST=YES
I1286
i
NO_TEST=YES
I1285
NO_TEST=YES
I1288
NO_TEST=YES
I1287
NO_TEST=YES
I1289
NO_TEST=YES
I1292
NO_TEST=YES
I1291
NO_TEST=YES
I1293
NO_TEST=YES
I1294
NO_TEST=YES
I1297
NO_TEST=YES
I1296
NO_TEST=YES
I1299
NO_TEST=YES
I1301
NO_TEST=YES
I1300
NO_TEST=YES
I1302
NO_TEST=YES
I1303
NO_TEST=YES
I1306
NO_TEST=YES
I1305
NO_TEST=YES
I1307
NO_TEST=YES
I1310
NO_TEST=YES
I1311
NO_TEST=YES
I1313
NO_TEST=YES
I1312
NO_TEST=YES
I1314
NO_TEST=YES
I1316
NO_TEST=YES
I1317
NO_TEST=YES
I1318
NO_TEST=YES
I1320
NO_TEST=YES
I1322
NO_TEST=YES
I1324
NO_TEST=YES
I1323
NO_TEST=YES
I1325
NO_TEST=YES
I1326
NO_TEST=YES
I1327
NO_TEST=YES
I1329
NO_TEST=YES
I1330
NO_TEST=YES
I1333
NO_TEST=YES
I1332
NO_TEST=YES
I1334
n
TP_FBBCS1_L
AUD_4V5_FB
ITS_RUNNING
LED801_1
LED802_1
PCI_CLK66M_SB_INT_R
Q800_D
Q800_G
Q801_B
Q802_B
Q802_E
Q803_B
TP_USB2_PWREN<0>
TP_USB2_PWREN<1>
TP_SB_FSTEST
TP_SB_PLLTEST
TP_USB2_PWREN<2>
TP_USB2_PWREN<3>
TP_USB2_PWREN<4>
TP_NEC_NTEST1
TP_NEC_SMC
TP_NEC_SMI_L
TP_NEC_SRCLK
TP_NEC_SRMOD
TP_NEC_TEST
UATA_DASP_L_DS
RFBD<19>
RFBD<18>
RFBD<16>
RFBD<15>
RFBD<14>
RFBD<13>
RFBD<11>
RFBD<10>
RFBD<8>
RFBD<7>
RFBD<6>
RFBD<5>
RFBD<3>
RFBD<2>
RFBD<1>
RAM_DQ_R<63>
RAM_DQ_R<60>
RAM_DQ_R<59>
RAM_DQ_R<58>
RAM_DQ_R<57>
RAM_DQ_R<56>
RAM_DQ_R<54>
RAM_DQ_R<53>
RAM_DQ_R<52>
RAM_DQ_R<50>
RAM_DQ_R<49>
RAM_DQ_R<48>
RAM_DQ_R<46>
RAM_DQ_R<45>
RAM_DQ_R<44>
RAM_DQ_R<43>
RAM_DQ_R<41>
RAM_DQ_R<40>
RAM_DQ_R<39>
RAM_DQ_R<38>
RAM_DQ_R<36>
RAM_DQ_R<34>
RAM_DQ_R<33>
RAM_DQ_R<32>
RAM_DQ_R<30>
RAM_DQ_R<29>
RAM_DQ_R<28>
RAM_DQ_R<26>
RAM_DQ_R<25>
RAM_DQ_R<24>
RAM_DQ_R<22>
RAM_DQ_R<21>
RAM_DQ_R<20>
RAM_DQ_R<19>
RAM_DQ_R<17>
RAM_DQ_R<16>
RAM_DQ_R<14>
RAM_DQ_R<13>
RAM_DQ_R<12>
RAM_DQ_R<11>
a
87
154
7
8
8
26
8
8
8
8
8
8
143
143
24
24
143
143
143
122
122
122
122
122
122
129
89
88
89
88
89
88
89
88
89
88
ry
89
88
89
88
89
88
89
88
89
88
89
88
89
88
89
88
89
88
89
88
68
70
61
68
70
61
68
70
61
70
68
61
70
68
61
70
68
61
70
68
61
70
68
61
70
68
61
70
68
61
70
68
61
70
68
61
70
68
61
70
68
61
70
68
61
70
68
61
70
68
61
70
68
61
70
68
61
70
68
61
70
68
61
70
68
61
68
61
70
70
68
61
69
68
61
69
68
61
69
68
61
69
68
61
69
68
61
69
68
61
69
68
61
69
68
61
69
68
61
68
61
69
69
68
61
68
61
69
69
68
61
69
68
61
69
68
61
69
68
61
I1080
I1088
I1089
I1091
I1092
I1093
I1094
I1095
I1335
I1336
I1337
I1338
I1339
I1340
I1090
7
7
7
PP1V8_RUN
7
PP2V5_RUN
7
PP3V3_RUN
7
PP12V_RUN
7
NO_TEST=YES
I1341
NO_TEST=YES
I1343
NO_TEST=YES
I1344
NO_TEST=YES
I1345
NO_TEST=YES
I1346
NO_TEST=YES
I1348
NO_TEST=YES
I1349
NO_TEST=YES
I1350
APPLE COMPUTER INC.
PP1V2_ALL
PP3V3_ALL
PP5V_ALL
FUNC TEST NETS
NOTES FROM TOM FUSSELMAN
PLACE TWO TEST POINTS ON TOP SIDE
FOR PP3V3_ALL AND GND
PLACE WITHIN 1 INCH OF EACH OTHER
USE FAT TRACES
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
SYNC_MASTER=FINO-ME
PPVCORE_CPU
=PP3V3_ALL_SMU
=PP5V_RUN_CPU
SYS_POWER_BUTTON_L
POWER_BUTTON_L
RESET_BUTTON_L
SMU_RESET_L
SYS_POWERUP_L
TOP SIDE ONLY
SMU_BOOT_SCLK
SMU_BOOT_RXD
SMU_BOOT_CE
SMU_BOOT_CNVSS
SMU_BOOT_TXD
SMU_BOOT_BUSY
SMU_MANUAL_RESET_L
PP1V2_ALL
PP1V8_RUN PP3V3_RUN
PP1V5_PWRON
7
GND
RAM_DQ_R<10>
RAM_DQ_R<8>
RAM_DQ_R<7>
RAM_DQ_R<6>
RAM_DQ_R<5>
RAM_DQ_R<3>
RAM_DQ_R<2>
RAM_DQ_R<1>
PP2V5_RUN
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC TEST 1 OF 2
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
051-6863
D
NONE
SHT
SCALE
50
29
28
7
8
7
29
28
29
29
29
28
12
28
85 50
7
29
28
29
28
29
28
29
28
29
28
29
28
29
PP3V3_ALL
68
69
61
68
69
61
68
69
61
69
68
61
69
68
61
69
68
61
69
68
61
69
68
61
SYNC_DATE=05/19/2005
OF
6
D
C
PP5V_ALL
PP12V_RUN
PP1V5_PWRON
B
A
REV.
07
154
8
67
5
4
3
2
1
125
OUT
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
P/N 518-0188
ON IN RUN AND SLEEP
PWRON RAILS
CHASSIS MOUNTING
GPU MOUNTING
ALL RAILS
RUN RAILS
SILKSCREEN:1 SILKSCREEN:2
SILKSCREEN:RUN
GND RAILS
ONLY ON IN RUN
ALWAYS ON WHEN UNIT HAS AC POWER (TRICKLE)
CHASSIS GND
PP5V_RUN
PP3V3_PWRON
PP1V5_PWRON
PP2V5_PWRON
PP1V2_PWRON
PP5V_ALL
PP5V_ALL
PP3V3_RUN
PP2V5_RUN
PP5V_PWRON
PP1V5_RUN
PP3V3_RUN
PP5V_RUN
SM
21
XW701
SM
21
XW702
SM
21
XW703
PP12V_RUN
PP1V2_RUN
CRITICAL
74LCX125
TSSOP
3
14
17
2
U700
CERM
0.1UF
10V
20%
402
2
1
C700
GREEN
2.0X1.25A
DEVELOPMENT
2
1
LED701
GREEN
2.0X1.25A
2
1
LED702
PP3V3_PWRON
330
1/10W
603
MF-LF
5%
21
R700
2.0X1.25A
GREEN
2
1
LED700
SM
21
XW705
SM
21
XW706
SM
21
XW707
PP12V_RUN
PP3V3_RUN
M-RT-TH
HM9607E-P2
9
87
65
43
2
1413
1211
10
1
J700
PP3V3_ALL PP12V_ALL
PP1V8_PWRON
OMIT
4P75R4
1
ZH700
OMIT
4P75R4
1
ZH701
OMIT
4P75R4
1
ZH702
OMIT
4P75R4
1
ZH703
0.01UF
20%
CERM
402
NOSTUFF
16V
2
1
C704
0.01UF
NOSTUFF
20%
16V
CERM
402
2
1
C702
NOSTUFF
16V
20%
CERM
402
0.01UF
2
1
C703
PP1V8_RUN
OMIT
4P25R3P5
ZH704
OMIT
4P25R3P5
ZH705
16V
NOSTUFF
0.01UF
20%
CERM
402
2
1
C707
0.01UF
20%
16V
CERM
402
NOSTUFF
2
1
C706
0.01UF
CERM
NOSTUFF
20%
16V
402
2
1
C705
MF-LF
402
1/16W
5%
10K
2
1
R702
PP3V3_ALL
PP3V3_ALL
PP1V2_ALL
PP2V5_ALL
PP12V_ALL
PP3V3_ALL
330
1/10W
5%
MF-LF
603
21
R710
MF-LF
NOSTUFF
0
5%
1/16W
402
21
R721
MF-LF
1/16W
5%
0
402
NOSTUFF
21
R711
SM
21
XW700
4P25R3P5
OMIT
1
ZH706
SM
21
XW708
SM-1
ELEC
6.3V
20%
330UF
2
1
C722
603
MF-LF
5%
330
1/10W
DEVELOPMENT
21
R701
PP5V_ALL
SYNC_MASTER=M33-PC
07
7
154
051-6863
POWER CONN / ALIAS
SYNC_DATE=05/19/2005
=PP5V_PWRON_BNDI
=PP5V_PWRON_USB
=PP3V3_ENET
=PP3V3_PWRON_BNDI
=PP3V3_PWRON_BT
=PP3V3_PWRON_CPU
=PP3V3_PWRON_PULSAR
=PP3V3_PWRON_SB
=PP3V3_PWRON_SB_PCI32
=PP3V3_PWRON_SB_PCI64
=PP3V3_PWRON_SMU
=PP3V3_PWRON_USB
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.60MM
VOLTAGE=0V
GND_CHASSIS_TMDS
=PP2V5_PWRON_NB_MISC
=PP2V5_PWRON_HT
=PP2V5_PWRON_NB_PCIE
=PP1V8_RUN_RAM
PP12V_AUDIO_SPKRAMP
=PP5V_RUN_CPU
ZH706P1
=PP5V_PATA
=PP3V3_AUDIO
=PP3V3_RUN_I2C
=PP3V3_RUN_PULSAR
=PP3V3_RUN_SMU
=PP3V3_SB_PCI
=PPVIO_PCI_USB2
=PP1V2_PWRON_HT_NBTX
=PP1V2_PWRON_PULSAR
=PP1V2_PWRON_SB_HT
=PP1V2_PWRON_SB_VCORE
INV_CUR_HI
GND_CHASSIS_FIREWIRE
GND_CHASSIS_RJ45
GND_CHASSIS_VGA
ZH700P1
GND_CHASSIS_USB
=PPOVDD_PULSAR
GND_CHASSIS_AUDIO_EXTERNAL
GND_AUDIO_SPKRAMP
=PPV_EI_CPU
=PPV_EI_NB
=PP1V5_PWRON_PULSAR
=PP1V8_PWRON_DIMM
=PP12V_GPU
=PP1V8_PWRON_NBMEM
=PP1V8_PWRON_RAM
=PPVCORE_PWRON_NB_HT
=PPVCORE_PWRON_NB
=PPVCORE_PWRON_NB_PCIE
=PP3V3_ALL_GPU
=PP2V5_ENETFW
=PP3V3_ENETFW
=PP2V5_RUN_I2C
=PPV_GPU_MEM
ZH703P1
=PP2V5_ENET
SYS_POWERUP_L
ITS_PLUGGED_IN
ITS_RUNNING
=PP2V5_PWRON_SB
GND_AUDIO
LCD_PWM
=PP1V2_GPU_PCIE
SYS_POWERFAIL_L
=PP2V5_PWRON_PULSAR
=PP1V2_ENETFW
=PP3V3_ALL_SMU
=PP3V3_FW
=PP12V_ALL_GPU
=PP5V_ALL_GPU
=PP3V3_ALL_CPU
ZH702P1
=PP12V_ALL_FW
=PP12V_CPU
HS_SDF801
ZH704P1
ZH705P1
=PP3V3_RUN_SB_PCI
=PP2V5_PWRON_NB_HT
PP5V_AUDIO_ANALOG
=PP3V3_RUN_CPU
=PP3V3_GPU
=PP3V3_PCI
=PP3V3_PATA
=PP1V8_PWRON_RAM_I2C_VDD
=PP5V_AUDIO
=PP5V_GPU
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
MAKE_BASE=TRUE
VOLTAGE=0
GND_CHASSIS_LEFT
NET_SPACING_TYPE=POWER
MIN_NECK_WIDTH=0.2MM
GND_CHASSIS_BNDI
MIN_LINE_WIDTH=0.6MM
VOLTAGE=0
MAKE_BASE=TRUE
NET_SPACING_TYPE=POWER
=PP1V2_PWRON_SB
=PP1V2_PWRON_DISK_SB
VOLTAGE=0
MIN_LINE_WIDTH=0.6MM
MAKE_BASE=TRUE
GND_CHASSIS_RIGHT
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=POWER
ITS_ALIVE
SYS_POWERUP_L_BUF
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
VOLTAGE=5V
NET_SPACING_TYPE=POWER
NET_SPACING_TYPE=POWER
VOLTAGE=3.3V
NET_SPACING_TYPE=POWER
VOLTAGE=12V
NET_SPACING_TYPE=POWER
MAKE_BASE=TRUE
VOLTAGE=1.2V
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
NET_SPACING_TYPE=POWER
NET_SPACING_TYPE=POWER
NET_SPACING_TYPE=POWER
VOLTAGE=3.3V
NET_SPACING_TYPE=POWER
MIN_LINE_WIDTH=0.6MM
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=POWER
MAKE_BASE=TRUE
PP5V_ALL
MAKE_BASE=TRUE
VOLTAGE=12V
PP12V_ALL
MIN_LINE_WIDTH=0.6MM
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=POWER
VOLTAGE=2.5V
PP2V5_ALL
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=POWER
NET_SPACING_TYPE=POWER
MIN_NECK_WIDTH=0.2MM
PP1V2_ALL
VOLTAGE=1.2V
MIN_LINE_WIDTH=0.6MM
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2MM
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.6MM
MAKE_BASE=TRUE
PP3V3_ALL
PP1V8_RUN
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.8V
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6MM
NET_SPACING_TYPE=POWER
MIN_NECK_WIDTH=0.2MM
VOLTAGE=2.5V
MIN_LINE_WIDTH=0.6MM
MAKE_BASE=TRUE
PP1V8_PWRON
NET_SPACING_TYPE=POWER
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
PP3V3_RUN
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
MAKE_BASE=TRUE
PP12V_RUN
PP1V2_RUN
PP1V5_RUN
MIN_NECK_WIDTH=0.2MM
MAKE_BASE=TRUE
VOLTAGE=1.5V
MIN_LINE_WIDTH=0.6MM
NET_SPACING_TYPE=POWER
VOLTAGE=5V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.25MM
MAKE_BASE=TRUE
PP5V_PWRON
VOLTAGE=2.5V
PP2V5_RUN
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
MAKE_BASE=TRUE
NET_SPACING_TYPE=POWER
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.2V
PP1V2_PWRON
VOLTAGE=2.5V
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
PP2V5_PWRON
NET_SPACING_TYPE=POWER
PP1V5_PWRON
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.5V
MAKE_BASE=TRUE
NET_SPACING_TYPE=POWER
MIN_LINE_WIDTH=0.6MM
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.25MM
PP3V3_PWRON
VOLTAGE=5V
PP5V_RUN
NET_SPACING_TYPE=POWER
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.60MM
VOLTAGE=0V
119
56
85
96
56
39
154
48
59
91
50
138
93
24
43
145
30
153
28
154
47
56
70
58
59
139
139
90
28
119
139
29
154
92
136
23
30
144
28
103
152
8
152
20
154
152
30
42
25
69
39
42
132
132
89
12
24
154
132
28
55
153
55
91
125
92
16
143
143
132
121
55
25
20
23
23
28
142
96
20
98
82
61
6
6
129
147
39
25
30
119
122
98
25
103
23
92
140
136
96
143
25
153
6
29
41
12
67
96
20
62
98
19
82
85
17
17
39
87
136
6
6
23
6
92
84
28
25
17
6
140
85
85
55
140
50
8
24
98
150
54
85
121
129
67
91
143
24
127
16
6
6
6
6
6
6
6
6
Preliminary
G
D
S
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
CPU HEATSINK MOUNTING HOLES
DIAG LED
(OVERTEMP LED)
SCC_GPIO_L
SCC_TRXC
SCC_TXD_L
SCC_RTS_L
SCC_DTR_L
SCC_RXD
SERIAL DEBUG
CHKSTOP LED
PLL LOCK LED
OMIT
4P75R4
1
ZH800
OMIT
4P75R4
1
ZH801
OMIT
4P75R4
1
ZH803
OMIT
4P75R4
1
ZH802
402
0.01UF
20%
16V
CERM
2
1
C880
402
0.01UF
20%
16V
CERM
2
1
C881
402
0.01UF
20%
CERM
16V
2
1
C882
402
0.01UF
20%
16V
CERM
2
1
C883
RED
SM
DEVELOPMENT
2
1
LED801
2N7002
SOT23-LF
DEVELOPMENT
Q800_D
2
1
3
Q800
2N3904LF
SOT23
DEVELOPMENT
Q801_B
2
3
1
Q801
SM
DEVELOPMENT
2N3906
2
3
1
Q802
1K
MF-LF
1/16W
DEVELOPMENT
402
5%
2
1
R835
GREEN
2.0X1.25A
DEVELOPMENT
2
1
LED802
180
MF-LF
402
5%
DEVELOPMENT
1/16W
2
1
R837
1/16W
MF-LF
DEVELOPMENT
1K
402
5%
2
1
R838
2N3904LF
SOT23
DEVELOPMENT
2
3
1
Q803
180
1/16W
MF-LF
402
5%
DEVELOPMENT
21
R839
SM
RED
2
1
LED850
SOT23
2N3904LF
2
3
1
Q850
5%
402
1/16W
1K
MF-LF
21
R851
PP5V_ALL
402
5%
1/16W
MF-LF
1K
2
1
R850
M-ST-5087
SM
DEVELOPMENT
9
8
7
65
4
3
2
10
1
J800
PP5V_PWRON
MF-LF
1/16W
5%
180
DEVELOPMENT
402
2
1
R833
5%
1/16W
MF-LF
DEVELOPMENT
1K
402
2
1
R834
402
MF-LF
5%
30K
1/16W
21
R836
SYNC_DATE=05/19/2005
SYNC_MASTER=FINO-DD
Signal Alias
07
8
154
051-6863
=PP5V_RUN_CPU
=PP5V_RUN_CPU
CPU_CHKSTOP_L
Q800_G
Q802_B
LED801_1
LED802_1
Q803_C
I2S1_RESET_L
I2S1_MCLK
I2S1_DEV_TO_SB_DTI
I2S1_SYNC
I2S1_BITCLK
I2S1_SB_TO_DEV_DTO
HS_SDF800
DIAG_LED
MAKE_BASE=TRUE
DIAG_LED_R
Q803_B
PLLLOCK
Q802_E
LED850P2
HS_SDF801 HS_SDF802 HS_SDF803
LED850P1
8 8 7
7
56
43
6
6
6
6
43
6
6
6
6
9
24
24
24 24
24
24
28
6
9
6
Preliminary
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
ADDING FUNC_TEST=TRUE TO THESE NETS
OF THE BOARD
LAYOUT HAVING DIFFICULTY PLACING TEST POINTS ON THESE NETS
PCB LAYOUT ADDS TEST POINTS. THIS LIST IS A RESULT OF PCB
NOTE FOR SHARING: DO NOT INCLUDE THIS LIST UNTIL
WHEN THE DEVELOPMENT BOM OPTION IS ENABLED
THE FOLLOWING NETS DO NOT HAVE
AND SIGNAL INTEGRITY.
TEST COVERAGE WILL BE BY FCT
TEST POINT BECAUSE OF ROUTING DENSITY
THE FOLLOWING NETS ARE USED ONLY
TESTED VIA TEST JET
THE FOLLOWING PULSAR NETS WILL BE
JTAG TEST POINTS NEED TO BE ON THE BOTTOM
I1
I10
I100
I101
I102
I103
I106
I109
I11
I114
I115
I116
I117
I118
I119
I12
I120
I121
I122
I123
I124
I125
I126
I127
I128
I129
I13
I130
I131
I132
I133
I134
I135
I136
I137
I138
I139
I14
I140
I141
I142
I143
I144
I145
I146
I147
I148
I149
I15
I150
I151
I152
I153
I154
I155
I156
I157
I158
I159
I16
I160
I161
I162
I163
I164
I165
I166
I167
I168
I169
I17
I170
I171
I172
I173
I174
I175
I176
I177
I178
I179
I18
I180
I181
I182
I183
I184
I185
I186
I187
I188
I189
I19
I191
I192
I193
I194
I195
I196
I197
I198
I199
I2
I20
I200
I201
I202
I203
I204
I205
I206
I207
I208
I209
I21
I210
I211
I212
I213
I214
I215
I216
I217
I218
I219
I22
I220
I221
I222
I223
I224
I225
I226
I227
I228
I229
I23
I230
I232
I233
I234
I235
I236
I238
I239
I24
I240
I241
I242
I244
I245
I246
I247
I248
I25
I26
I27
I28
I29
I3
I30
I31
I32
I33
I34
I35
I36
I37
I38
I39
I4
I40
I41
I42
I43
I44
I45
I46
I47
I48
I49
I5
I50
I51
I52
I53
I54
I55
I56
I57
I58
I59
I6
I60
I61
I62
I63
I64
I65
I66
I67
I68
I69
I7
I70
I71
I72
I73
I74
I75
I76
I77
I78
I79
I8
I80
I81
I82
I83
I84
I85
I86
I87
I88
I89
I9
I90
I91
I92
I93
I94
I95
I96
I97
I98
I99
154
9
051-6863
SYNC_DATE=05/19/2005
SYNC_MASTER=FINO-ME
07
FUNC TEST 2 OF 2
FUNC_TEST=TRUE
TP_JTAG_VESTA_TDO
FUNC_TEST=TRUE
TP_JTAG_VESTA_TDI
FUNC_TEST=TRUE
TP_JTAG_VESTA_TCK
FUNC_TEST=TRUE
JTAG_NB_TMS
FUNC_TEST=TRUE
JTAG_NB_TCK
FUNC_TEST=TRUE
TP_JTAG_SB_TCK
FUNC_TEST=TRUE
JTAG_SB_TRST_L
NO_TEST=YES
PCIE_SLOTA_TO_NB_P<0..15>
NO_TEST=YES
NB_PLL_OUT_TRG_R
NO_TEST=YES
PP5V_T555
NO_TEST=YES
ENET_TX_EN
ENET_RXD<0>
NO_TEST=YES
ENET_RXD<2>
NO_TEST=YES
ENET_RXD_R<4>
NO_TEST=YES
100M_P<0>
NO_TEST=YES
NO_TEST=YES
CLK_RAIREF_200M_P_R
NO_TEST=YES
PP1V5_RUN_FOR_LED
NO_TEST=YES
LED_PP1V5_RUN_N
ENET_RXD_R<3>
NO_TEST=YES
NO_TEST=YES
ENET_RXD_R<2>
TP_VESTA_TXC_RXC_DELAY
NO_TEST=YES
NO_TEST=YES
PULSAR_1V5_RUN_SWITCH
TP_VESTA_TVCO_24
NO_TEST=YES
NO_TEST=YES
SB_AIRPRT_CLK_33MHZ_R
SB_CLK25M_SATA_R
NO_TEST=YES
NO_TEST=YES
QUA0_REF_25MHZ_R
NO_TEST=YES
LED_PP1V2_RUN_N
ENET_RXD<3>
NO_TEST=YES
ENET_RXD<4>
NO_TEST=YES
NO_TEST=YES
TSENSE_GPU_ADD0
NO_TEST=YES
ENET_TXD<6>
NO_TEST=YES
LED8700_P
NO_TEST=YES
TP_VESTA_LINK2_L
ENET_TXD<4>
NO_TEST=YES
NO_TEST=YES
LED_PP1V5_RUN_P
NO_TEST=YES
LED_PP1V8_RUN_N
NO_TEST=YES
NC_J3108_11
NO_TEST=YES
NC_J3108_10
ENET_TXD_R<4>
NO_TEST=YES
ENET_TXD_R<7>
NO_TEST=YES
ENET_TXD_R<6>
NO_TEST=YES
ENET_TXD_R<3>
NO_TEST=YES
ENET_TXD_R<2>
NO_TEST=YES
ENET_RXD_R<5>
NO_TEST=YES
ENET_TXD<3>
NO_TEST=YES
NO_TEST=YES
NC_SMU_FAN_TACH3
NC_SMU_FAN_TACH7
NO_TEST=YES
NC_SMU_SER_SEL
NO_TEST=YES
NO_TEST=YES
NC_SYS_DOOR_AJAR_L
NO_TEST=YES
NC_SMU_CPU_VID_LE1
NO_TEST=YES
NC_SMU_FAN_RPM3
NO_TEST=YES
NC_SMU_FAN_RPM4
NO_TEST=YES
TP_HT_MB_TO_NB_CLK_P<1>
NC_I2C_SMU_CPU_SCL_IN
NO_TEST=YES
NC_PSRO
NO_TEST=YES
ENET_RXD<1>
NO_TEST=YES
NO_TEST=YES
ENET_TX_ER_R
ENET_RXD<7>
NO_TEST=YES
ENET_RXD<6>
NO_TEST=YES
ENET_RXD<5>
NO_TEST=YES
ENET_RXD_R<0>
NO_TEST=YES
ENET_TXD<2>
NO_TEST=YES
ENET_TXD_R<1>
NO_TEST=YES
ENET_TXD_R<0>
NO_TEST=YES
ENET_TXD<7>
NO_TEST=YES
NO_TEST=YES
ENET_TXD<5>
ENET_TXD_R<5>
NO_TEST=YES
NO_TEST=YES
NC_SLOT_TOTAL_PWR
NO_TEST=YES
NC_CPU_AFN
NO_TEST=YES
TP_HT_MB_TO_NB_CLK_N<1>
NO_TEST=YES
NC_SMU_FAN_RPM5
NO_TEST=YES
NC_SMU_FAN_TACH4
ENET_TX_EN_R
NO_TEST=YES
NO_TEST=YES
ENET_TX_ER
TP_VESTA_PHYA<4>
NO_TEST=YES
NO_TEST=YES
TP_VESTA_SPD0
NO_TEST=YES
TP_VESTA_REGSUP2
NO_TEST=YES
TP_VESTA_RGMIIEN
NO_TEST=YES
TP_VESTA_REGCTL1
TP_VESTA_REGSEN2
NO_TEST=YES
NO_TEST=YES
TP_VESTA_MANMS
NO_TEST=YES
TP_VESTA_FDXLED_L
NO_TEST=YES
TP_VESTA_HUB
NO_TEST=YES
TP_VESTA_LINK1_L
NO_TEST=YES
TP_VESTA_2_5V_EN
NO_TEST=YES
TP_VESTA_DNC_C9
NO_TEST=YES
TP_VESTA_DNC_E9
NO_TEST=YES
TP_VESTA_EN_10B
NO_TEST=YES
TP_VESTA_FDX
NO_TEST=YES
TP_VESTA_AN_EN
NO_TEST=YES
NC_SMU_FAN_TACH5
NO_TEST=YES
TP_VESTA_ER
ENET_TXD<1>
NO_TEST=YES
ENET_RXD_R<6>
NO_TEST=YES
NO_TEST=YES
NC_SMU_CPU_VID_LE0
NC_PSRO_ENABLE
NO_TEST=YES
TP_VESTA_PHYA<0>
NO_TEST=YES
NO_TEST=YES
TP_VESTA_REGSEN1
TP_VESTA_PHYA<1>
NO_TEST=YES
NO_TEST=YES
TP_VESTA_RBC0
NO_TEST=YES
TP_VESTA_RBC1
TP_VESTA_REGCTL2
NO_TEST=YES
TP_VESTA_PHYA<3>
NO_TEST=YES
NO_TEST=YES
TP_VESTA_F1000
TP_VESTA_PHYA<2>
NO_TEST=YES
NO_TEST=YES
TP_VESTA_REGSUP1
TP_VESTA_TDBL<0>
NO_TEST=YES
ENET_RXD_R<1>
NO_TEST=YES
NO_TEST=YES
LED_PP1V8_RUN_P
NC_J3108_9
NO_TEST=YES
ENET_RXD_R<7>
NO_TEST=YES
NO_TEST=YES
TSENSE_GPU_ADD1
NO_TEST=YES
GPU_DIODE_PLUS
NO_TEST=YES
CPU_A_TBEN_CLK_R
NO_TEST=YES
CPU_B_TBEN_CLK_R
NO_TEST=YES
CPU_B_APSYNC_R
NO_TEST=YES
HT_SB_REFCLK_R
NO_TEST=YES
HT_NB_REFCLK_H0_R
NO_TEST=YES
CLK_RAIREF_200M_N_R
NO_TEST=YES
NB_PMR_CLK_P_R
NO_TEST=YES
NB_PMR_CLK_N_R
NO_TEST=YES
NB_PCIE_REFCLK_P_C
NO_TEST=YES
NB_PCIE_REFCLK_N_C
NO_TEST=YES
QUA1_REF_25MHZ_R
NO_TEST=YES
NB_DDR_REFCLK_N_R
NO_TEST=YES
NB_DDR_REFCLK_P_R
NO_TEST=YES
PCIE_C_REFCLKIN_N_C
NO_TEST=YES
PCIE_C_REFCLKIN_P_C
NO_TEST=YES
PCIE_B_REFCLKIN_N_C
NO_TEST=YES
PCIE_B_REFCLKIN_P_C
NO_TEST=YES
PCIE_A_REFCLKIN_N_C
NO_TEST=YES
PCIE_A_REFCLKIN_P_C
NO_TEST=YES
GFX_SLOT_PCIE_REFCLK_N_C
NO_TEST=YES
GFX_SLOT_PCIE_REFCLK_P_C
NO_TEST=YES
SB_USB2_CLK_33MHZ_R
NO_TEST=YES
CLK_RAI_REFCLK_66M_R
NO_TEST=YES
PCI_CLK33M_SB_EXT_R
NO_TEST=YES
NB_APSYNC_R
NO_TEST=YES
CLK_RAI_GIGE_25MHZ_R
NO_TEST=YES
ENET_TXD<0>
NO_TEST=YES
NC_PP1V5_PULSAR
NC_JTAGMUX_3
NO_TEST=YES
NC_J3108_8
NO_TEST=YES
NC_J3108_12
NO_TEST=YES
NO_TEST=YES
NC_CPU_TBEN_CLK
NO_TEST=YES
TP_SB_WATCHDOG
NO_TEST=YES
TP_NB_APSYNC
NO_TEST=YES
TP_I2S2_SB_TO_DEV_DTO
Q803_C
NO_TEST=YES
100M_N<0>
NO_TEST=YES
CKA_P<0>
NO_TEST=YES
HT_NB_P<0>
NO_TEST=YES
HT_NB_REFCLK_NF<0>
NO_TEST=YES
HT_NB_REFCLK_PF<0>
NO_TEST=YES
HT_NB_TO_SB_CAD_P<0..7>
NO_TEST=YES
HT_NB_TO_SB_CLK_P<0>
NO_TEST=YES
HT_NB_TO_SB_CLK_N<0>
NO_TEST=YES
NO_TEST=YES
HT_SB_TO_NB_CAD_N<0..7>
NO_TEST=YES
HT_SB_TO_NB_CAD_P<0..7>
NO_TEST=YES
EI_NB_TO_CPU_SR_N<0>
NO_TEST=YES
EI_NB_TO_CPU_CLK_P
NO_TEST=YES
EI_NB_TO_CPU_CLK_N
NO_TEST=YES
EI_CPU_TO_NB_SR_P<1>
NO_TEST=YES
EI_CPU_TO_NB_SR_N<1>
NO_TEST=YES
EI_CPU_TO_NB_CLK_P
NO_TEST=YES
EI_CPU_TO_NB_CLK_N
NO_TEST=YES
CLK_KOD_100M_PF<0>
NO_TEST=YES
CLK_KOD_100M_NF<0>
NO_TEST=YES
HT_SB_TO_NB_CTL_P<0>
NO_TEST=YES
HT_NB_TO_SB_CTL_N<0>
NO_TEST=YES
HT_NB_TO_MB_CTL_P<1>
NO_TEST=YES
HT_NB_TO_MB_CTL_N<1>
NO_TEST=YES
PCIE_NB_TO_SLOTA_PF<4>
NO_TEST=YES
PCIE_NB_TO_SLOTA_NF<12>
HT_SB_TO_NB_CLK_P<0>
NO_TEST=YES
NO_TEST=YES
HT_MB_TO_NB_CTL_N<1>
NO_TEST=YES
PCIE_NB_TO_SLOTA_PF<10>
NO_TEST=YES
PCIE_NB_TO_SLOTA_PF<14>
LED_PP1V2_RUN_P
NO_TEST=YES
NO_TEST=YES
KP_V<1>
NO_TEST=YES
KP_V<2>
NO_TEST=YES
PP1V2_RUN_FOR_LED
NO_TEST=YES
PCIE_NB_TO_SLOTA_PF<13>
NO_TEST=YES
PCIE_NB_TO_SLOTA_P<10>
PCIE_NB_TO_SLOTA_P<1>
NO_TEST=YES
PCIE_NB_TO_SLOTA_N<3>
NO_TEST=YES
NO_TEST=YES
UATA_DD<14>
PCIE_NB_TO_SLOTA_N<0>
NO_TEST=YES
CPU_SENSE_KP_V
NO_TEST=YES
NO_TEST=YES
NB_PLL_OUT_TRG
NO_TEST=YES
GPU_DIODE_MINUS
NO_TEST=YES
CPU_A_APSYNC_R
NO_TEST=YES
HT_NB_REFCLK_L0_R
LED8701_P
NO_TEST=YES
NO_TEST=YES
TSENSE_GPU_OVERTEMP_L
NO_TEST=YES
PP3V3_GPU_TSENSE
NO_TEST=YES
T555_PWM
NO_TEST=YES
T555_OUT
NO_TEST=YES
T555_THRES
NO_TEST=YES
T555_DISC
HT_SB_TO_NB_CLK_N<0>
NO_TEST=YES
CKA_N<0>
NO_TEST=YES
HT_NB_N<0>
NO_TEST=YES
PCIE_SLOTA_TO_NB_N<0..15>
NO_TEST=YES
NO_TEST=YES
UATA_DD<1>
NO_TEST=YES
PCIE_NB_TO_SLOTA_NF<7>
PCIE_NB_TO_SLOTA_NF<13>
NO_TEST=YES
NO_TEST=YES
UATA_DA<0>
HT_NB_TO_SB_CAD_N<0..7>
NO_TEST=YES
NO_TEST=YES
PLLLOCK
TP_VESTA_TEST_1394<1>
NO_TEST=YES
TP_VESTA_TEST_1394<0>
NO_TEST=YES
NO_TEST=YES
TP_NB_B_TRIGGER_OUT
NO_TEST=YES
TP_NB_A_TRIGGER_OUT
NO_TEST=YES
CARD_READER_ACTIVITY_R
TP_VESTA_TVCO
NO_TEST=YES
TP_VESTA_TEST<0>
NO_TEST=YES
TP_VESTA_TDBL<1>
NO_TEST=YES
TP_VESTA_TDBL<2>
NO_TEST=YES
TP_VESTA_TEST<1>
NO_TEST=YES
NO_TEST=YES
TP_VESTA_FAVDDL
NO_TEST=YES
EI_NB_TO_CPU_SR_P<0>
FUNC_TEST=TRUE
JTAG_NB_TRST_L
FUNC_TEST=TRUE
JTAG_NB_TDI
FUNC_TEST=TRUE
TP_JTAG_VESTA_TRST_L
FUNC_TEST=TRUE
TP_JTAG_VESTA_TMS
FUNC_TEST=TRUE
JTAG_NB_TDO
FUNC_TEST=TRUE
TP_JTAG_SB_TMS
FUNC_TEST=TRUE
TP_JTAG_SB_TDO
FUNC_TEST=TRUE
TP_JTAG_SB_TDI
JTAG_CPU_TCK
FUNC_TEST=TRUE
JTAG_CPU_TDI
FUNC_TEST=TRUE
JTAG_CPU_TDO
FUNC_TEST=TRUE
JTAG_CPU_TRST_L
FUNC_TEST=TRUE
JTAG_CPU_TMS
FUNC_TEST=TRUE
NO_TEST=YES
HT_MB_TO_NB_CTL_P<1>
97
132
132
132
132
132
132
132
132
132
132
132
132
132
132
132
132
132
132
97
97
97
97
97
47
30
30
24
84
131
131
131
131
97
131
131
131
131
131
131
131
131
131
131
131
131
131
131
131
131
131
131
131
131
131
131
131
131
131
131
131
131
131
131
131
131
97
97
101
101
101
56
56
56
56
56
56
56
97
97
97
97
97
97
97
84
84
84
129
84
97
101
84
129
97
97
129
43
56
30
30
43
43
43
47
43
20
20
20
20
82
92
130
130
130
130
82
26
12
12
130
130
132
12
139
26
26
26
13
130
130
93
130
136
132
130
12
11
31
31
130
130
130
130
130
130
130
31
31
31
31
31
31
31
101
31
56
130
130
130
130
130
130
130
130
130
130
130
130
31
56
101
31
31
130
130
132
132
17
132
17
17
132
132
132
132
17
17
17
132
132
132
31
132
130
130
31
56
132
17
132
132
132
17
132
132
132
17
139
130
11 31
130
93
93
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
130
12
30
31
31
27
24
44
154
8
82
84
98
98
98
101
101
101
101
101
43
43
43
43
43
43
43
82
82
101
101
98
98
82
82
101
98
82
82
13
55
55
13
82
82
82
82
127
82
55
59
93
26
26
136
93
92
92
92
92
101
84
98
82
127
82
82
127
101
8
139
139
56
56
144
132
132
139
139
132
139
43
20
20
20
20
20
30
30
30
43
30
98
Preliminary
FB
LD
HD
GND
COMP
SS
VCC
VC
G
D
S
G
D
S
G
D
S
LM339A
V+
GND
G
D
S
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
U1100_FEEDBACK
1.8V VOLTAGE REGULATOR
PLACE LED NEAR VREG
POWER BUDGET CURRENT OF TOTAL RAILS
NOTE:
10.9A PEAK
7.2A CONTINUOUS
SET OUTPUT=1.85V FOR FRAMEBUFFER.
VOUT=VREF*(R903+R905)/R905=1.85VDC
IRU3037ACS VREF=0.8VDC
HIGH TO ENABLE
POWER BUDGET CURRENT OF FET
2.7A PEAK
2.3A CONTINUOUS
0
805
1/8W
5%
MF-LF
21
R1102
402
1%
1/16W
MF-LF
3.32K
2
1
R1105
1.1K
NOSTUFF
805
MF-LF
5%
1/8W
2
1
R1104
PP5V_ALL
1UF
CERM
10%
6.3V
402
2
1
C1104
PP12V_ALL
MBR0520LXXG
SOD-123
2 1
D1100
SOD-123
MBR0520LXXG
2 1
D1101
SOD-123
MBR0520LXXG
2
1
D1102
CERM
1UF
20%
25V
805
2
1
C1117
2200PF
603
5%
50V
CERM
2
1
C1105
805
CERM
25V
20%
1UF
2
1
C1116
PP1V8_PWRON
PP1V8_RUN
220PF
25V
5%
CERM
402
2
1
C1106
IHLP
1.5UH
CRITICAL
21
L1101
SOI
IRU3037ACS
2 6
8
3
5
4
1
7
U1100
1%
1/16W
MF-LF
402
4.42K
2
1
R1103
0.1UF
25V
603
CERM
20%
2
1
C1115
402
1%
1/16W
MF-LF
4.99K
2
1
R1101
5%
CERM
50V
330PF
805
2
1
C1113
NOSTUFF
603
3300PF
10%
CERM
50V
2
1
C1107
50V
CERM
603
0.0180UF
10%
2
1
C1114
4.7
805
1/8W
MF-LF
5%
2
1
R1100
SO-8
IRF7413
321
4
8765
Q1103
PP12V_RUN
2N7002
SOT23-LF
2
1
3
Q1140
470K
402
5%
1/16W
MF-LF
2
1
R1140
1UF
25V
20%
NOSTUFF
CERM
805
2
1
C1112
NTD60N02R
CASE369
3
1
4
Q1101
NTD60N02R
CASE369
3
1
4
Q1102
20%
ELEC
TH-MCZ
16V
680UF
2
1
C1102
20%
ELEC
TH-MCZ
16V
680UF
2
1
C1103
CERM
10UF
10%
16V
1210
2
1
C1111
CERM
0.001UF
20%
50V
402
NOSTUFF
2
1
C1140
8X11.5-TH
390UF
20%
ELEC
6.3V
2
1
C1109
330
MF-LF
DEVELOPMENT
402
1/16W
5%
2
1
R1160
DEVELOPMENT
2.0X1.25A
GREEN
2
1
LED1100
10UF
20%
6.3V
CERM
1206
C1110
PP1V8_RUN
SOI-LF
DEVELOPMENT
3
14
9
8
12
U1201
PP3V3_RUN
SOT23-LF
2N7002
2
1
3
Q1100
SM
21
XW1100
SYNC_DATE=05/19/2005
SYNC_MASTER=M33-PC
1.8V VREG
051-6863
07
11
154
MIN_LINE_WIDTH=0.45MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=0 V
GND_U1100
Q903_GATE
U1100_SS
MIN_LINE_WIDTH=0.45MM
MIN_NECK_WIDTH=0.25MM
U1100_GATE_H
GND_U1100
U1100_VC_R
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.45MM
1V1_REF
LED_PP1V8_RUN_N
LED_PP1V8_RUN_P
Q1101_GATE
MIN_LINE_WIDTH=0.45MM
MIN_NECK_WIDTH=0.25MM
Q1102_DRAIN
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.45MM
U1100_GATE_L
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.45MM
U1100_VC_D
U1100_COMP
MIN_LINE_WIDTH=0.45MM
MIN_NECK_WIDTH=0.25MM
R904_P2
R1101_P2
SYS_SLEEP
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.45MM
U1100_VC
PWRON_L
U1100_FEEDBACK
GND_U1100
54 30 26 16
16
85
15
15
11
11
13
13
13
11
6
6
12
9
9
12
12
6
Preliminary
G
D
S
G
D
S
FB
LD
HD
GND
COMP
SS
VCC
VC
G
D
S
LM339A
V+
GND
G
D
S
GND
VOUT
VIN
NOISE
CONT
S
G
D
G
D
S
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
TABLE_5_ITEM
KODIAK CORE VOLTAGE REGULATOR
NOTE:
U1200_FEEDBACK
TURNING ON PP2V5_PWRON WITH 1V2_PWRON
SO THAT 1.5V IS THE FIRST RAIL UP ON KODIAK
PLACE LED NEAR VREG
LOAD FROM POWER BUDGET
@ VGS=3.5 V
RDSON=0.012 OHM
1.3A PEAK CURRENT DRAW
1.0A CONTINUOUS CURRENT DRAW
PP1V5_PWRON_PULSAR
LOAD FROM POWER BUDGET
IRU3037ACS VREF=0.8VDC
7.2A CONTINUOUS CURRENT DRAW
8.5A PEAK CURRENT DRAW
1.25V R1205=4.02K
1.30V R1205=3.24K
1.35V R1205=2.87K
VOUT=VREF*(R1203+R1205)/R1205=1.30VDC
CERM
16V
10%
10UF
1210
2
1
C1201
ELEC
1500UF
20%
6.3V
TH-MCZ
2
1
C1209
ELEC
1500UF
6.3V
20%
TH-MCZ
2
1
C1208
3.24K
MF-LF
1%
402
1/16W
2
1
R1205
603
CERM
20%
10V
1UF
NOSTUFF
2
1
C1207
NOSTUFF
CERM
1UF
20%
25V
1206
2
1
C1212
PP5V_ALL
NTD60N02R
CASE369
3
1
4
Q1201
50V
CERM
20%
1800PF
805
2
1
C1205
0
805
1/8W
MF-LF
5%
21
R1202
1UF
CERM
402
6.3V
10%
2
1
C1204
220PF
5%
25V
CERM
402
2
1
C1206
PP12V_ALL
0.1UF
CERM
16V
20%
603
2
1
C1214
603
10V
1UF
CERM
20%
2
1
C1216
CERM
1UF
25V
805
20%
2
1
C1217
MBR0520LXXG
SOD-123
2 1
D1200
MBR0520LXXG
SOD-123
2 1
D1201
SOD-123
MBR0520LXXG
2
1
D1202
NTD60N02R
CASE369
3
1
4
Q1202
SM
1.53UH
3
2
1
L1201
NOSTUFF
MF-LF
1.1K
5%
1/4W
1206
2
1
R1204
IRU3037ACS
SOI
2 6
8
3
5
4
1
7
U1200
MF-LF
402
1%
1/16W
2.05K
2
1
R1203
8.45K
MF-LF
1%
402
1/16W
2
1
R1201
CERM
50V
0.012UF
805
10%
2
1
C1215
5%
50V
CERM
150PF
402
2
1
C1213
805
MF-LF
1/8W
5%
10
2
1
R1200
PP1V5_RUN
402
CERM
10V
20%
0.1UF
2
1
C1250
SOT23-LF
2N7002
2
1
3
Q1251
PP5V_PWRON
5%
MF-LF
402
100K
1/16W
2 1
R1250
20%
ELEC
680UF
16V
TH-MCZ
2
1
C1202
10UF
1210
16V
10%
CERM
2
1
C1210
DEVELOPMENT
402
330
MF-LF
1/16W
5%
2
1
R1260
2.0X1.25A
DEVELOPMENT
GREEN
2
1
LED1200
DEVELOPMENT
SOI-LF
3
1
7
6
12
U1201
MF-LF
1/16W
5%
0
402
DEVELOPMENT
21
R1261
6.3V
10UF
805-1
20%
CERM
2
1
C1218
PP1V5_PWRON
PP1V5_PWRON
PP3V3_RUN
SOT23-LF
2N7002
2
1
3
Q1200
NOSTUFF
0
5%
1/16W
MF-LF
402
21
R1206
0
5%
402
1/16W
MF-LF
21
R1207
10%
X5R
10UF
805
6.3V
2
1
C1272
0.01UF
16V
CERM
20%
402
2
1
C1271
OMIT
MM1572FN
SOT-25A
5
1
4
2
3
U1270
10K
402
MF-LF
1/16W
5%
2
1
R1270
805
CERM
20%
1UF
10V
2
1
C1270
PP3V3_PWRON
SM
21
XW1200
IRLML2402
SOT23
DEVELOPMENT
2
1
3
Q1271
SOT23-LF
2N7002
DEVELOPMENT
2
1
3
Q1270
DEVELOPMENT
5%
10K
1/16W
MF-LF
402
2
1
R1273
5%
10K
1/16W
MF-LF
402
DEVELOPMENT
2
1
R1274
PP12V_RUN
SI3446DVLF
TSOP
4
36
5
2
1
Q1250
20%
16V
CERM
402
0.01UF
2 1
C1275
051-6863
07
12
154
SYNC_MASTER=FINO-PC
SYNC_DATE=05/19/2005
1.5V Vreg
353S1145 MM1571FN
1
CRITICAL
U1270
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.45MM
U1200_GATE_L
PULSAR_1V5_RUN_SWITCH
VOLTAGE=1.5V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
PP1V5_RUN_PULSAR
PP1V5_PWRON_PULSAR
VOLTAGE=1.5V
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM
MAKE_BASE=TRUE
U1270_CONT
MAKE_BASE=TRUE
NC_PP1V5_PULSAR
U1270_NOISE
=PP1V5_PWRON_PULSAR
SYS_POWERUP_L
SYS_SLEEP
PP1V5_RUN_FOR_LED
1V1_REF
LED_PP1V5_RUN_N
LED_PP1V5_RUN_P
U1200_SS
PWRON_L
TURN_ON_PP1V5_L
TURN_ON_PP1V2_L
R1201_P2
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.45MM
U1200_VC
MIN_LINE_WIDTH=0.45MM
MIN_NECK_WIDTH=0.25MM
R2204_P2
U1200_COMP
GND_U1200
=PP1V5_PULSAR
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.45MM
VOLTAGE=0 V
GND_U1200
Q1202_DRAIN
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
GND_U1200
Q1250G
MIN_LINE_WIDTH=0.45MM
MIN_NECK_WIDTH=0.25MM
U1200_GATE_H
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.45MM
U1200_VC_D
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.45MM
U1200_VC_R
U1200_FEEDBACK
Q1201_GATE
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.45MM
54 30
85
26
50
16
16
28
15
85
15
25
7
13
13
13
13
12
12
12
9
9
7
6
11
9
11
9
9
11
4
6
25
6
6
Preliminary
G
D
S
G
D
S
FB
LD
HD
GND
COMP
SS
VCC
VC
G
D
S
LM339A
V+
GND
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
2.6A CONTINUOUS
PEAK CURRENT 1.3A IF KODIAK 1.2V CAN BE TURNED OFF IN SLEEP. 0.6A/M33 0.0A/M23 IF NOT
1.0A CONTINUOUS
@ VGS=2.5 V
PP1V2_PWRON FET SWITCH
RDSON=0.04 OHM
SET OUTPUT=1.22-1.23V
U1300_FEEDBACK
VOUT=VREF*(R1003+R1005)/R1005=1.22-1.23VDC
IRU3037ACS VREF=0.8VDC
@ VGS=2.5 V
NOTE:
PLACE LED NEAR VREG
POWER BUDGET CURRENT OF TOTAL RAILS
3.2A PEAK
PP1V2_PWRON COMES UP BEFORE GPU_POWERUP_L SO THAT SHASTA CORE GETS POWER BEFORE ANYTHING ELSE
PEAK CURRENT 1.3A
RDSON=0.04 OHM
PP1V2_RUN FET SWITCH
PP1V2_ALL VOLTAGE REGULATOR
NOSTUFF
5%
MF-LF
0
402
1/16W
21
R1314
47K
5%
1/16W
MF-LF
402
20_INCH_LCD&DEVELOPMENT
21
R1315
PP1V2_ALL
PP1V2_ALL
PP1V2_ALL
PP3V3_RUN
PP5V_RUN
PP3V3_RUN
CERM
20%
402
16V
0.01UF
20_INCH_LCD&DEVELOPMENT
2
1
C1320
CDRH104R-SM
3.8UH
21
L1301
2N7002
SOT23-LF
20_INCH_LCD&DEVELOPMENT
2
1
3
Q1304
NOSTUFF
SOT23-LF
2N7002
2
1
3
Q1307
NOSTUFF
1%
MF-LF
402
10K
1/16W
2
1
R1306
SM
21
XW1300
0.01UF
402
20%
CERM
16V
2
1
C1321
20_INCH_LCD&DEVELOPMENT
20%
16V
CERM
402
0.01UF
21
C1322
NOSTUFF
3300PF
10%
CERM
603
50V
2
1
C1307
1/16W
1%
MF-LF
402
10K
2
1
R1305
NOSTUFF
1.1K
5%
MF-LF
1/4W
1206
2
1
R1304
NOSTUFF
25V
CERM
20%
1UF
1206
2
1
C1312
SOD-123
MBR0520LXXG
2
1
D1302
PP12V_ALL
25V
805
1UF
20%
CERM
2
1
C1317
50V
CERM
20%
1800PF
805
2
1
C1305
MBR0520LXXG
SOD-123
2 1
D1300
SOD-123
MBR0520LXXG
2 1
D1301
805
MF-LF
1/8W
5%
0
21
R1300
805
25V
1UF
20%
CERM
2
1
C1300
220PF
CERM
5%
25V
402
2
1
C1306
1UF
10%
6.3V
402
CERM
2
1
C1304
IRU3037ACS
SOI
2 6
8
3
5
4
1
7
U1300
1800UF
20%
ELEC
6.3V
TH-KZJ-LF
2
1
C1309
5.36K
402
MF-LF
1/16W
1%
2
1
R1303
PP1V2_RUN
PP5V_ALL
1/16W
100K
MF-LF
5%
402
20_INCH_LCD&DEVELOPMENT
2 1
R1308
PP5V_ALL
SI3446DV
TSOP
4
3 6
521
Q1306
PP1V2_PWRON
2N7002
SOT23-LF
2
1
3
Q1305
1/16W
5%
MF-LF
402
100K
2 1
R1309
PP5V_ALL
402
25V
10%
0.0068UF
CERM
2
1
C1314
402
56PF
5%
50V
CERM
2
1
C1313
603
16V
CERM
20%
0.1UF
2
1
C1315
5%
18K
1/16W
MF-LF
402
2
1
R1301
5%
MF-LF
1/16W
0
402
21
R1312
402
MF-LF
NOSTUFF
1/16W
5%
0
21
R1313
805
4.7
5%
1/8W
MF-LF
2
1
R1302
IRF7807ZPBF
SO-8
321
4
8765
Q1301
IRF7807ZPBF
SO-8
321
4
8765
Q1302
1210
10UF
CERM
16V
10%
2
1
C1302
1210
10UF
CERM
16V
10%
2
1
C1303
TSOP
SI3446DV
20_INCH_LCD&DEVELOPMENT
4
3 6
5
2
1
Q1303
10UF
16V
10%
CERM
1210
2
1
C1301
DEVELOPMENT
SOI-LF
3
2
5
4
12
U1201
402
330
DEVELOPMENT
MF-LF
1/16W
5%
2
1
R1350
2.0X1.25A
GREEN
DEVELOPMENT
2
1
LED1300
MF-LF
1/16W
5%
100K
402
DEVELOPMENT
2
1
R1351
1/16W
5%
47K
402
DEVELOPMENT
MF-LF
2
1
R1352
5%
DEVELOPMENT
402
1/16W
MF-LF
0
21
R1353
CERM
10V
20%
402
DEVELOPMENT
0.1UF
2
1
C1350
1.2V Vreg
SYNC_DATE=05/19/2005
SYNC_MASTER=FINO-PC
154
13
07
051-6863
Q1006_G
Q1003_G
Q1305_G
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
Q1302_DRAIN
PWRON_L
U1300_SS
SYS_SLEEP
GPU_POWERUP_L
Q1301_GATE
MIN_LINE_WIDTH=0.45MM
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.45MM
MIN_NECK_WIDTH=0.25MM
U1300_GATE_H
U1300_VC_R
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.45MM
MIN_NECK_WIDTH=0.25MM
R1304_P2
MIN_LINE_WIDTH=0.45MM
MIN_LINE_WIDTH=0.45MM
MIN_NECK_WIDTH=0.25MM
U1300_VC
R1301_P2
PP1V2_RUN_FOR_LED
LED_PP1V2_RUN_N
LED_PP1V2_RUN_P
TURN_ON_PP1V2_L
MIN_LINE_WIDTH=0.45MM
MIN_NECK_WIDTH=0.25MM
U1300_VC_D
U1300_COMP
MIN_LINE_WIDTH=0.45MM
MIN_NECK_WIDTH=0.25MM
U1300_GATE_L
GND_U1300
MIN_LINE_WIDTH=0.45MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=0 V
TURN_ON_PP1V2_L
Q1304_G
GND_U1300
1V1_REF
GND_U1300
U1300_FEEDBACK
54 30 26
16
16
15
15
13
13
85
12
12
12
13
12
13
12
13
11
11
85
9
9
9
4
6
4
6
11
6
Preliminary
G
D
S
G
D
S
G
D
S
EN
GND
IN
OUT
ADJ
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
PP2V5_PWRON FET SWITCH
PEAK CURRENT 0.1A
@ VGS=2.5 V
RDSON=0.04 OHM
PP2V5_ALL VOLTAGE REGULATOR
RDSON=0.04 OHM
0.1A CONTINUOUS
NOSTUFF OPTION TO DELAY 2.5V PWRON TO COME UP WITH 3.3V PWRON
VOUT=VREF*(R1581+R1582)+1=5.505VDC
IRU3037CS VREF=1.24VDC
SET OUTPUT=2.5V
PP2V5_RUN FET SWITCH
@ VGS=2.5 V
POWER BUDGET CURRENT OF TOTAL RAILS
NOTE:
0.2A PEAK
PEAK CURRENT 0.1A
6.3V
CERM
1206
10UF
20%
2
1
C1580
PP2V5_ALL
PP3V3_ALL
PP2V5_ALL
PP2V5_ALL
0.01UF
20%
402
CERM
16V
2
1
C1581
20%
16V
CERM
402
0.01UF
21
C1582
PP2V5_RUN
SOT-363
2N7002DW-X-F
4
5
3
Q1504
2N7002DW-X-F
SOT-363
1
2
6
Q1504
PP5V_ALL
5%
100K
402
1/16W
MF-LF
2 1
R1508
SI3446DV
TSOP
4
3 6
521
Q1506
PP2V5_PWRON
2N7002
SOT23-LF
2
1
3
Q1505
5%
MF-LF
1/16W
402
100K
2 1
R1509
PP5V_ALL
NOSTUFF
402
0
1/16W
MF-LF
5%
21
R1512
0
5%
1/16W
MF-LF
402
21
R1513
TSOP
SI3446DV
4
3 6
5
2
1
Q1503
CASE-C1
ELEC
6.3V
20%
330UF
2
1
C1583
1%
1/16W
MF-LF
402
1.02K
2
1
R1581
1/16W
1%
402
1K
MF-LF
2
1
R1582
CRITICAL
SOP-8
MIC39102
3
2
8765
1
4
U1580
402
5%
3.3K
1/16W
MF-LF
2
1
R1580
SYNC_DATE=05/19/2005
SYNC_MASTER=FINO-PC
154
15
07
051-6863
2.5V Vreg
TURN_ON_PP3V3_PWRON_L
SYS_SLEEP
U1580_ADJ
U1580_EN
PWRON_L
Q1505_G
Q1503_G
Q1506_G
54 30 26 16
16
13
13
16
12
12
4
11
11
Preliminary
G
D
S
G
D
S
02
G
D
S
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
POWER SEQUENCING PIN TO DELAY TO BRING UP 3.3V LAST FOR SHASTA
IRF7413
SO-8
CRITICAL
321
4
8765
Q1600
5%
1/16W
MF-LF
402
47K
2
1
R1600
1/16W
402
3.6K
5%
MF-LF
2
1
R1602
SO-8
IRF7413
321
4
8765
Q1602
402
1/16W
MF-LF
5%
3.6K
2
1
R1607
1/16W
402
MF-LF
5%
47K
2
1
R1601
SOT-363
2N7002DW-X-F
4
5
3
Q1601
2N7002DW-X-F
SOT-363
1
2
6
Q1601
CERM
402
0.01UF
20%
16V
2
1
C1600
0.01UF
20%
16V
CERM
402
2
1
C1601
SN74LVC1G02
SOT23-5
4
5
3
2
1
U1601
PP12V_ALL
PP5V_ALL
PP3V3_ALL
PP12V_ALL
PP5V_PWRON
PP3V3_ALL
PP3V3_PWRON
402
5%
MF-LF
0
1/16W
2
1
R1604
NOSTUFF
402
0
1/16W
5%
MF-LF
21
R1603
20%
CERM
402
0.1UF
10V
2
1
C1603
SOT23-LF
2N7002
2
1
3
Q1603
10K
1/16W
402
5%
MF-LF
2
1
R1605
NOSTUFF
402
5%
MF-LF
1/16W
10K
2
1
R1608
NOSTUFF
1/16W
MF-LF
5%
402
3.3K
2
1
R1609
SYNC_DATE=05/19/2005
SYNC_MASTER=FINO-PC
051-6863
07
16
154
5V & 3.3V Fets
Q1601G
SYS_SLEEP
TURN_ON_PP3V3_PWRON_L
GATE_5V_PWRON
SYS_POWERUP_L_BUF
PP3V3_RUN
SYS_POWERUP
PWRON_L
GATE_3V3_PWRON
54 30 26 15
13
13
12
12
15
7
11
11
4
7
6
15
Preliminary
RESET*
TDI
DVDD
VESTA MISC
1 OF 3
PVDD
AVDDL
AVDD
GND
AGND
OVDD
REGSUP1
REGSEN1
REGCTL1
REGSUP2
REGSEN2
REGCTL2
2.5V_EN
DNC
DNC
TDO
TCK
TMS
TRST*
NC
NC
G
D
S
G
D
S
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
Page Notes
IPU
IPU
VESTA HAS INTERNAL PULLUPS. MLB
PULLUPS MAY BE NOSTUFFED IN EVT.
RESET ASSERT REQUIREMENT IS 20MS TO 100MS
To keep Vesta from being held
IPU
IPU
IPU
0 - OVDD=3.3V
1 - OVDD=2.5V
2.5V_EN
WHEN OVDD=2.5V GMII PINS ARE NOT 3.3V TOLERANT
IPD
SCHMITT TRIGGER W/ INTERNAL PULLUP
M23: PP3V3_ENETFW IS AN ALL RAIL
M23: PP3V3_ENETFW IS AN ALL RAIL
VESTA JTAG
(NONE)
regulator will be in continuous mode.
Signal aliases required by this page:
Controls operating mode of Vesta 1.2V
Power aliases required by this page:
regulator. If both options are off the
NC
NC
L9/M9 N5/N6
N9/N10
M23: ADDED C1726 AND C1744 PER BROADCOM RECOMMENDATIONS
in reset when system is off
NOTE: Reset GPIO is active HIGH
L6/M6
BOM options provided by this page:
- VESTA1V2_BURST / VESTA1V2_PULSE
10V
402
CERM
0.1uF
20%
2
1
C1710
402
CERM
10V
20%
0.1uF
2
1
C1711
402
10V
20%
CERM
0.1uF
2
1
C1712
20%
10V
CERM
402
0.1uF
2
1
C1713
CERM
0.1uF
20%
10V
402
2
1
C1703
10V
CERM
402
20%
0.1uF
2
1
C1702
402
10V
20%
CERM
0.1uF
2
1
C1701
20%
10V
0.1uF
402
CERM
2
1
C1700
402
CERM
10V
20%
0.1uF
2
1
C1722
10V
CERM
402
20%
0.1uF
2
1
C1725
CERM
10V
402
20%
0.1uF
2
1
C1721
402
CERM
10V
20%
0.1uF
2
1
C1724
0.1uF
402
CERM
10V
20%
2
1
C1731
0.1uF
20%
10V
CERM
402
2
1
C1730
10V
CERM
402
20%
0.1uF
2
1
C1720
10V
CERM
402
20%
0.1uF
2
1
C1723
0.1uF
402
CERM
10V
20%
2
1
C1743
0.1uF
402
20%
10V
CERM
2
1
C1742
0.1uF
402
20%
CERM
10V
2
1
C1741
0.1uF
402
CERM
10V
20%
2
1
C1740
805
6.3V
X5R
10%
10UF
2
1
C1708
FERR-EMI-600-OHM
SM
21
L1700
VESTA-V1.3
FBGA-200-LF
OMIT
D8
E8
E10
D7
E7
H4
E2
E1
F2
F1
G4
G5
N4
A15
K1
F15
A7
A1
M13
C3
K2
J2
F14
C14
B7B2A2
J1
C15
B15
B1
E9
C9
N10
N9N6N5M9M6L9L6
R12
R3
P11
P10
P5
P4
N8N7M8
M7L8L7
J12
J11
P9P8P7
P6
H12
H11
M3
U1701
5%
1/16W
MF-LF
402
1K
2
1
R1740
402
MF-LF
1/16W
5%
1K
2
1
R1743
402
MF-LF
1/16W
5%
1K
2
1
R1742
402
MF-LF
1/16W
5%
1K
2
1
R1741
10UF
10%
X5R
6.3V
805
2
1
C1726
805
X5R
10%
10UF
6.3V
2
1
C1744
0
5%
1/16W
402
MF-LF
NOSTUFF
21
R1720
402
CERM
10%
1UF
6.3V
2
1
C1750
47K
MF-LF
402
5%
1/16W
2
1
R1751
SOT-363
2N7002DW-X-F
1
2
6
Q1750
10K
5%
MF-LF
402
1/16W
2
1
R1750
SOT-363
2N7002DW-X-F
4
5
3
Q1750
10UF
805
6.3V
X5R
10%
2
1
C1714
10K
1/16W
402
MF-LF
5%
2
1
R1752
Vesta Core / Misc
051-6863
07
SYNC_MASTER=FINO-HC
SYNC_DATE=05/19/2005
17
154
VESTA_RESET_RC
=PP3V3_ENETFW
=PP2V5_ENETFW
VESTA_RESET_H
ENETFW_RESET
=PP3V3_ENETFW
MAKE_BASE=TRUE
TP_JTAG_VESTA_TMS
MAKE_BASE=TRUE
TP_JTAG_VESTA_TDO
=JTAG_VESTA_TRST_L
=JTAG_VESTA_TCK
=JTAG_VESTA_TDO
=JTAG_VESTA_TMS
TP_VESTA_2_5V_EN
TP_VESTA_REGCTL1
TP_VESTA_REGSUP1
TP_VESTA_REGSEN1
TP_VESTA_REGCTL2
TP_VESTA_REGSUP2
TP_VESTA_REGSEN2
TP_VESTA_DNC_C9
TP_VESTA_DNC_E9
=JTAG_VESTA_TCK
=JTAG_VESTA_TDI
=JTAG_VESTA_TDO
MAKE_BASE=TRUE
TP_JTAG_VESTA_TCK
=PP3V3_ENETFW
=JTAG_VESTA_TDI
VOLTAGE=1.2V
PP1V2_VESTA_AVDDL
MIN_NECK_WIDTH=0.25 MM
MIN_LINE_WIDTH=0.50 MM
=PP3V3_ENETFW
=PP3V3_ENETFW
VESTA_RESET_L
=JTAG_VESTA_TRST_L
MAKE_BASE=TRUE
TP_JTAG_VESTA_TDI
MAKE_BASE=TRUE
TP_JTAG_VESTA_TRST_L
=JTAG_VESTA_TMS
=PP1V2_ENETFW
139
139
139
139
139
132
139
132
132
132
132
139
17
132
17
17
17
17
132
7
7
132
24
7
17
17
17
17
9
9
9
9
9
9
9
9
9
17
17
17
7
17
7
7
17
17
7
Preliminary
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
VDD_CORE
CORE & PCI-E POWER
(9 OF 10)
(1.6V-1.2V)
PP
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
DRAWING
Q63 = PP1V6
1.6V
2
PAGE 19
KODIAK CORE
KODIAK-ASIC-040812
BGA
SEE_TABLE
U15
T20
T16
R22
R18
R14
P21
AC22
AC18
AC14
AB21
AB17
AA23
P17
AA19
AA15
Y20
Y16
W22
W18
W14
V21
V17
U19
N15
U14
T21
T17
R23
R19
R15
P20
AC23
AC19
AC15
AB20
AB16
AA22
P16
AA18
AA14
Y21
Y17
W23
W19
W15
V20
V16
U18
N14
U1900
6.3V
1UF
CERM
402
10%
2
1
C1906
6.3V
1UF
CERM
402
10%
2
1
C1900
6.3V
1UF
CERM
402
10%
2
1
C1905
6.3V
1UF
CERM
402
10%
2
1
C1914
6.3V
1UF
CERM
402
10%
2
1
C1913
6.3V
1UF
CERM
402
10%
2
1
C1919
6.3V
1UF
CERM
402
10%
2
1
C1924
6.3V
1UF
CERM
402
10%
2
1
C1918
6.3V
1UF
CERM
402
10%
2
1
C1923
6.3V
1UF
CERM
402
10%
2
1
C1912
6.3V
1UF
CERM
402
10%
2
1
C1911
6.3V
1UF
CERM
402
10%
2
1
C1917
6.3V
1UF
CERM
402
10%
2
1
C1922
6.3V
1UF
CERM
402
10%
2
1
C1916
6.3V
1UF
CERM
402
10%
2
1
C1921
6.3V
1UF
CERM
402
10%
2
1
C1910
6.3V
1UF
CERM
402
10%
2
1
C1915
6.3V
1UF
CERM
402
10%
2
1
C1920
6.3V
1UF
CERM
402
10%
2
1
C1904
P4MM
SM
1
PP1900
6.3V
1UF
CERM
402
10%
2
1
C1909
6.3V
1UF
CERM
402
10%
2
1
C1903
6.3V
1UF
CERM
402
10%
2
1
C1908
6.3V
1UF
CERM
402
10%
2
1
C1902
6.3V
1UF
CERM
402
10%
2
1
C1907
6.3V
1UF
CERM
402
10%
2
1
C1901
07
051-6863
19 154
SYNC_DATE=05/19/2005
SYNC_MASTER=Q63
KODIAK CORE & BYPASS
=PPVCORE_PWRON_NB
<XR_PAGE_TITLE>
LAST_MODIFIED=Thu May 19 14:26:38 2005
59A6 42A4 20A8
3A4
Preliminary
PP
PP
ADD1
ADD0
ALERT
SMBDATA
SMBCLK
VCC
NC_5
NC_1
STBY
DXP
NC_16
GND
NC_9
NC_13
DXN
(SYM_VER2)
PMR_CLK_STOP_L
CE1_LT_TCK
CE1_B_TDO
CE1_DI1_TMS
CE1_MC_TDI
CE1_DI2_TRST
CE0_TEST
SYS_THDIO_D
SYS_THDIO_G
VD5_0
VD5_1
VD5_2
NORTH_BRIDGE_RESET_L
HRESET_L
SUSPENDACK_L
SUSPENDREQ_L
SYS_ISCL0
SYS_ISCA0
SYS_ISCA1
SYS_ISCL1
API_ISCA
API_ISCL
PMR_CLK_P
PMR_CLK_N
(10 OF 10)
POWER/TEST/MISC
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
ON PAGE 24 )
SHASTA GPIO TERMINATIONS
NOTE:
PLACE TERM R/C CLOSE TO KODIAK
NOTE: LOW = DISABLE PMR_CLK
PMR_CLK_STOP CAN BE USED TO STOP ALL CLOCKS IN KODIAK
KODIAK JTAG_TRST PULLED HIGH
AND SYS_IO_RESET_L (SMU)
PCI_RESET_L IS AN ’AND’ OF SB_PCI_RESET_L (SB)
THESE PINS HAVE INTERNAL PULLUPS OR PULLDOWNS
PLACE R2012 IN AN ACCESSIBLE LOCATION
USED FOR DEBUG
C2055 ADDED FOR KODIAK RAM DECOUPLING
PAGE 58 IS SHORT ONE CAP
KODIAK ALIASES
1 | 0 | 98/99
hiZ | 1 | 56/57
1 | hiZ| 9A/9B
A0 | A1 | ADDR
----+----+----- 0 | 0 | 30/31
0 | hiZ| 32/33
0 | 1 | 34/35
hiZ | 0 | 52/53
1 | 1 | 9C/9D
hiZ | hiZ| 54/55
NEED TO CHECK ALL I2C ADDRESSES
TO ALLOW SMU DEBUG ACCESS
(SOME OF THESE ARE NOSTUFF
SHASTA ALIASES
SHASTA JTAG
NB_OVERTEMP
PLACE BY IC
1UF
402
CERM
6.3V
10%
2
1
C2052
402
CERM
6.3V
10%
1UF
2
1
C2051
CERM
402
1UF
10%
6.3V
2
1
C2050
1.5PF
402
CERM
NOSTUFF
50V
+/-0.25PF
2
1
C2053
402
5%
MF-LF
0
1/16W
2
1
R2000
402
1/16W
1%
MF-LF
60.4
NOSTUFF
2
1
R2001
402
1/16W
1%
MF-LF
60.4
NOSTUFF
2
1
R2002
402
1/16W
1%
MF-LF
1K
2
1
R2003
NOSTUFF
0
5%
1/16W
402
MF-LF
21
R2012
10K
MF-LF
5%
1/16W
402
2
1
R2013
SM
2
1
XW2000
SM
P4MM
1
TP2000
SM
P4MM
1
TP2002
402
MF-LF
4.7K
5%
1/16W
2
1
R2053
1/16W
MF-LF
402
5%
4.7K
NOSTUFF
2
1
R2054
10K
5%
1/16W
MF-LF
402
21
R2061
10K
5%
1/16W
MF-LF
402
21
R2062
402
MF-LF
1/16W
5%
10K
21
R2063
402
MF-LF
1/16W
5%
10K
21
R2064
0
NOSTUFF
5%
1/16W
MF-LF
402
21
R2074
1/16W
MF-LF
5%
4.7K
402
2
1
R2073
1UF
10%
6.3V
CERM
402
2
1
C2055
1/16W
5%
MF-LF
0
402
NOSTUFF
21
R2087
5%
1/16W
MF-LF
1K
NOSTUFF
402
2
1
R2084
402
5%
1/16W
MF-LF
1K
2
1
R2085
5%
1/16W
MF-LF
1K
402
2
1
R2083
5%
1/16W
MF-LF
1K
NOSTUFF
402
2
1
R2086
CERM
10V
20%
0.1UF
402
2
1
C2080
10%
0.0022UF
50V
CERM
402
21
C2081
MAX6690MEE
QSOP
2
15
12
14
9
5
16
13
1
87
3
4
11
6
10
U2080
1/16W
5%
MF-LF
402
200
21
R2082
BGA
KODIAK-ASIC-040812
AH01
AF05
AF02
G15
F15
AJ05
AK03
AH06
AG04
AJ01
AJ03
AG02
AE09
AE10
AL01
AG01
AG07
AJ04
AK06
AL02
AG05
AG08
AH03
AG03
U1900
KODIAK & SHASTA MISC
051-6863
07
20
154
SYNC_MASTER=FINO-ME
SYNC_DATE=05/19/2005
=PP3V3_RUN_SMU
MIN_NECK_WIDTH=0.38MM
MIN_LINE_WIDTH=0.38mm
TSENSE_NB_VCC
NB_THERM_K
MIN_LINE_WIDTH=0.25mm
MIN_NECK_WIDTH=0.25MM
DIFFERENTIAL_PAIR=TSENSE_NB
NET_SPACING_TYPE=TSENSE_DIFPAIR
NET_PHYSICAL_TYPE=10MIL_WIDTH
I2C_NB_TEMP_SCL
I2C_NB_TEMP_SDA
TSENSE_NB_ADD0
TSENSE_NB_OVERTEMP_L
TSENSE_NB_ADD1
SYS_OVERTEMP_L
=PP1V8_PWRON_NBMEM
RAI_EXP_INTR_L<2>
JTAG_SB_TRST_L
JTAG_NB_TCK
NB_PU_RST_L
=PP2V5_PWRON_NB_MISC
JTAG_NB_TRST_L
MAKE_BASE=TRUE
TP_JTAG_SB_TMS
MAKE_BASE=TRUE
NB_SLOT_RESET_L
JTAG_SB_TDI
JTAG_SB_TCK
MAKE_BASE=TRUE
TP_JTAG_SB_TCK
MAKE_BASE=TRUE
TP_JTAG_SB_TDO
RAI_EXP_INTR_L<1>
RAI_EXP_INTR_L<0>
MAKE_BASE=TRUE
TP_JTAG_SB_TDI
NB_PU_RST_L
NB_THERM_A
CE0TEST
JTAG_NB_TRST_L
JTAG_NB_TDO
NB_PMR_CLK_P
NB_HRST_L
I2C_NB_A_SCL
NB_PMR_CLK_N
I2C_NB_C_SCL
I2C_NB_B_SDA
JTAG_NB_TDI
JTAG_NB_TMS
I2C_NB_B_SCL
I2C_NB_A_SDA
I2C_NB_C_SDA
NB_SUSPEND_REQ_L
NB_SUSPEND_ACK_L
TERM_RC
=PP2V5_PWRON_NB_MISC
PMR_CLK_DIS_L
PP_2V5PWRONNBMISC
PCI_RESET_L
MAKE_BASE=TRUE
=PCI_ROM_RESET_L
=PCI_USB2_RESET_L
=PCI_AIRPORT_RESET_L
=GPU_RESET_L
JTAG_SB_TDO
JTAG_SB_TMS
RAI_EXP_INTR_L<3>
MAKE_BASE=TRUE
NC_PMR_CLK_DIS_L
PMR_CLK_DIS_L
NB_THERM_K
NB_PMR_CLK_STOP_L
=PP2V5_PWRON_NB_MISC
=PP3V3_PWRON_SB
MIN_LINE_WIDTH=0.25mm
MIN_NECK_WIDTH=0.25MM
DIFFERENTIAL_PAIR=TSENSE_NB
NET_PHYSICAL_TYPE=10MIL_WIDTH
NET_SPACING_TYPE=TSENSE_DIFPAIR
NB_THERM_A
39
39
39
119
59
30
30
30
56
30
93
58
28
28
28
24
28
28
39
24
30
30
20
20
30
20
30
27
27
30
30
62
20
119
20
23
7
20
39
39
24
7
24
9
9
20
7
9
9
24
24
24
9
9
24
24
9
20
20
9
9
26
39
26
39
39
9
9
39
39
39
30
30
7
20
6
92
125
122
121
84
24
24
24
6
20
20
7
7
20
Preliminary
VIO1
POWER
VDDO33
VDDO25
VIO2
VDDP_KL
VDDC
GND
GND
GND
(1 OF 8)
PP
PP
PP
DRAWING
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
Shasta max (est 06/30/03) current:
DIGITAL - 1.2V - 950 mA (1175 mW)
VDDPs - 2.5V - 100 mA ( 250 mW)
I/O 3.3 - 3.3V - 220 mA ( 770 mW)
Page Notes
Power aliases required by this page:
- =PP3V3_PWRON_SB_PCI64 (VIO1) (TO 5V OR 3.3V)
- =PP3V3_PWRON_SB
- =PP2V5_PWRON_SB
- =PP1V2_PWRON_SB_VCORE
characteristics required by the PCI
appropriate PCI bus voltage and
other Shasta supplies.
Signal aliases required by this page:
For PCI_AD<63..32>
ANALOG12 - 1.2V - 600 mA ( 760 mW)
I/O 2.5 - 2.5V - 20 mA ( 60 mW)
For PCI_AD<31..0>
PCI, otherwise 3.3V.
(NONE)
(NONE)
Power Sequencing:
Total: 3015 mW
Must power Shasta VCore rail before any
BOM options provided by this page:
spec for 5V vs. 3.3V operation.
different drive timing
NOTE: PCI pads use the VIO supply to meet
CONNECT VIO2 TO
VIO1 TO SAME IF 64-BIT
- =PP3V3_PWRON_SB_PCI32 (VIO2) (TO 5V OR 3.3V)
10V
0.1uF
CERM
402
20%
2
1
C2304
10V
0.1uF
CERM
402
20%
2
1
C2305
10V
0.1uF
CERM
402
20%
2
1
C2306
10V
0.1uF
CERM
402
20%
2
1
C2307
10V
0.1uF
CERM
402
20%
2
1
C2308
10V
0.1uF
CERM
402
20%
2
1
C2309
10V
0.1uF
CERM
402
20%
2
1
C2302
10V
0.1uF
CERM
402
20%
2
1
C2301
10V
0.1uF
CERM
402
20%
2
1
C2300
10V
0.1uF
CERM
402
20%
2
1
C2314
10V
0.1uF
CERM
402
20%
2
1
C2313
10V
0.1uF
CERM
402
20%
2
1
C2312
10V
0.1uF
CERM
402
20%
2
1
C2311
10V
0.1uF
CERM
402
20%
2
1
C2310
0.1uF
10V
CERM
402
20%
2
1
C2334
0.1uF
10V
CERM
402
20%
2
1
C2333
10V
0.1uF
CERM
402
20%
2
1
C2339
10V
0.1uF
CERM
402
20%
2
1
C2338
10V
0.1uF
CERM
402
20%
2
1
C2332
10V
0.1uF
CERM
402
20%
2
1
C2331
10V
0.1uF
CERM
402
20%
2
1
C2337
10V
0.1uF
CERM
402
20%
2
1
C2336
10V
0.1uF
CERM
402
20%
2
1
C2330
10V
0.1uF
CERM
402
20%
2
1
C2335
10V
0.1uF
CERM
402
20%
2
1
C2324
402
10V
0.1uF
CERM
20%
2
1
C2323
10V
0.1uF
CERM
402
20%
2
1
C2329
402
10V
0.1uF
CERM
20%
2
1
C2328
0.1uF
10V
CERM
402
20%
2
1
C2322
10V
0.1uF
CERM
402
20%
2
1
C2321
10V
0.1uF
CERM
402
20%
2
1
C2327
0.1uF
10V
CERM
402
20%
2
1
C2326
10V
0.1uF
CERM
402
20%
2
1
C2320
10V
0.1uF
CERM
402
20%
2
1
C2325
10V
0.1uF
CERM
402
20%
2
1
C2351
10V
0.1uF
CERM
402
20%
2
1
C2350
10V
0.1uF
CERM
402
20%
2
1
C2357
10V
0.1uF
CERM
402
20%
2
1
C2356
10V
0.1uF
CERM
402
20%
2
1
C2355
10V
0.1uF
CERM
402
20%
2
1
C2362
10V
0.1uF
CERM
402
20%
2
1
C2361
10V
0.1uF
CERM
402
20%
2
1
C2360
10V
0.1uF
CERM
402
20%
2
1
C2365
V1.1
SEE_TABLE
SHASTA
BGA-LF
Y19
W22
L21
K21
H17
H18
V8
D1
B5
B2
B1
AB6
AB2
AB10
AA3
W4
V7
U9
U12
R2
M1
L7
H1
F8
F4
AA2
AA1
G15
D19
P15N8M15L8L15K8J15
J12
T15
T10R9R12
R10
H8
H15
D2
C19
AB22
AB1
W5
W19
U22
U13
U10
T12
R19
P9
P4
AA6
P14
P13
P12
P10
N9
N22
N13
N12
N11
N10
AA10
M2
M14
M13
M12
M11
M10
L9
L16
L14
L13A5L12
L11
L10
K9
K7
K13
K12
K11
K10
J22
A22
J16
J14
J13
J11
J10
H9
H2
F7
F3
E22
A2
A1
U2300
SM
2
1
XW2304
SM
2
1
XW2303
SM
2
1
XW2300
SM
P4MM
1
PP2300
P4MM
SM
1
PP2303
SM
P4MM
1
PP2304
10V
0.1uF
CERM
402
20%
2
1
C2303
ABBREV=DRAWING
TITLE=KILOHANA
23 154
051-6863
07
SYNC_MASTER=Q63
SYNC_DATE=05/19/2005
Shasta Core Power
NO_TEST=YES
PP_2V5PWRONSB
=PP3V3_PWRON_SB
PP_3V3PWRONSBPCI64
=PP3V3_PWRON_SB_PCI64
=PP1V2_PWRON_SB_VCORE
=PP2V5_PWRON_SB
=PP3V3_PWRON_SB_PCI32
PP_1V2PWRONSBVCORE
=PP2V5_PWRON_SB
<XR_PAGE_TITLE>
LAST_MODIFIED=Thu May 19 14:26:40 2005
154D2
149A3 120C4 119A3
29C7 29B4 24D2 24C3
138C6
138C6
24B7
119C3
119C3
24A6
24D5
24D5
20D2
23B2
23C2
3A3
3A2
3B2
3C1
3A2
3C1
Preliminary
GND
PLL_49
GND
XTAL_18 PLL_45
GND
VIO
PME
PLL_49
VDD
PLL_45
VDD
XGI
XTALS
TEST
PWR_MGT
PCI
GPIO
I2C
I2S2 I2S1 I2S0
(2 OF 8)
PCI1C_BE_4_L
PCI1C_BE_5_L
PCI1C_BE_6_L
PCI1C_BE_7_L
PCI1PAR64_H
XGI_DTI_H
XGI_DTO1_H
XGI_CLK_H
XGI_DTO0_H
PCI1ACK64_L
PCI1REQ64_L
PCI1AD_60_H
PCI1AD_63_H
PCI1AD_62_H
PCI1AD_61_H
PCI1AD_50_H
PCI1AD_52_H
PCI1AD_53_H
PCI1AD_51_H
PCI1AD_59_H
PCI1AD_58_H
PCI1AD_57_H
PCI1AD_56_H
PCI1AD_55_H
PCI1AD_54_H
PCI1AD_40_H
PCI1AD_41_H
PCI1AD_42_H
PCI1AD_43_H
PCI1AD_44_H
PCI1AD_49_H
PCI1AD_48_H
PCI1AD_47_H
PCI1AD_46_H
PCI1AD_45_H
PCI1AD_39_H
PCI1REQ_5_L
PCI1AD_32_H
PCI1AD_34_H
PCI1AD_38_H
PCI1AD_37_H
PCI1AD_36_H
PCI1AD_33_H
PCI1AD_35_H
PCI1GNT_5_L
PCI1GNT_4_L
PCI1REQ_4_L
PCI1GNT_3_L
PCI1REQ_3_L
XTAL_18XTAL
VDD VDD
FSTEST
XTAL_18_I
XTAL_18_O
XTALI
XTALO
PLLTEST
TEST_MODE_H
TDI
TCK
TMS
TDO
INTRWD_H
I2CDATA_H
I2CCLK_H
PCI_SEL32BIT_H
GPIO_H_3
GPIO_H_2
GPIO_H_1
I2S2SYNC_H
I2S2BITCLK_H
I2S2MCLK_H
I2S2DTO_H
I2S2DTI_H
GPIO_H_0
I2S1DTO_H
I2S1MCLK_H
I2S1BITCLK_H
I2S1SYNC_H
I2S1DTI_H
I2S0BITCLK_H
I2S0SYNC_H
I2S0DTI_H
I2S0DTO_H
I2S0MCLK_H
RESET_L
STOPXTALS_L
SUSPENDREQ_L
SUSPENDACK_L
PCI1PME_L
TRST_L
PP
PP
PP
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
DRAWING
PLACE R2402 CLOSE TO SHASTA
AUDIO GPIO - see note on right
NorthBridge / SouthBridge MPIC Routing
DIFFERENTIAL_PAIR
DO NOT swap between RPAKs
ELECTRICAL_CONSTRAINT_SET
- _PP2V5_PWRON_SB
- _PP3V3_PCI
Power aliases required by this page:
Signal aliases required by this page:
BOM options provided by this page:
- PCI_64BIT:
- MPIC_NB/MPIC_SB:
Page Notes
- _PP3V3_PWRON_SB
- _PP1V2_PWRON_SB
(NONE)
NOTE: XGC required for Shasta GPIOs
the audio circuit to provide the
NOTE: It is the responsibility of
36
8
14
GPIO
16
24
13
(SCCB)
20
19
21
9
22
15
12
45
26
35
(I2S1_RESET_L)
I2S2: S/P-DIF
NC
46
53
54
52
48
27
34
33
32
30
49
7
(SCCA)
51
(I2S0_DEV_TO_SB_DTI)
6
50
47
31
29
I2S0: Audio DAC
(I2S2_DEV_TO_SB_DTI)
25
28
10
11
17
37
38
39
40
41
42
43
44
AUDIO GPIOS
SPEC SHOWS LOAD CAPACITANCE OF 16PF FOR 197S0004
necessary pull-ups & pull-downs.
FROM SOUTHBRIDGE
FROM NORTHBRIDGE
TO CPU
Configures Shasta for 64-bit PCI
To SouthBridge ->
NET_SPACING_TYPE
AUDIO PAGES IS RESPONSIBLE FOR TERMINATION OF I2S0 AND I2S2
DO NOT ADD PULLUP/DOWN FOR I2S0 AND IS=2S2 IN THIS PAGE
(I2S1_DEV_TO_SB_DTI)
Re-pin within each RPAK as necessary
interrupt controller.
Selects whether NorthBridge or
SouthBridge MPIC will be used for
I2S1: Soft Modem
23
18
(I2S2_RESET_L)
PLACE R2432 CLOSE TO SHASTA
805
X5R
6.3V
10%
10UF
2
1
C2400
10%
6.3V
1uF
CERM
402
2
1
C2401
10%
6.3V
1uF
CERM
402
2
1
C2411
805
X5R
6.3V
10%
10UF
2
1
C2410
805
X5R
6.3V
10%
10UF
2
1
C2420
10%
6.3V
1uF
CERM
402
2
1
C2421
805
X5R
6.3V
10%
10UF
2
1
C2430
10%
6.3V
1uF
CERM
402
2
1
C2431
1/16W
5%
402
10K
MF-LF
2
1
R2400
CRITICAL
18.432M
SM
21
Y2490
200
MF-LF
402
1%
1/16W
2
1
R2490
50V
22pF
CERM
402
5%
2
1
C2491
50V
22pF
CERM
402
5%
2
1
C2490
4.7K
MF-LF
402
1%
1/16W
2
1
R2480
SHASTA
V1.1
BGA-LF
Y13
V13
W13
AB12
W14
V15
U15
T9
U7
W2
Y4
W17
W12
Y11
A3
W11
AA11
AB11
U11
V11
W10
E9
Y12
AA12
AA13AB13
U14
W6
U16
AB21
U17
K17
W18
E18
Y20
AA20
AA19
K20
K22
H22
J20
H21
G22
F22
J19
H20
G21
F21
J17
H19
K18
D22
G20
D21
C22
G19
F20
C21
E20
D20
F19
E19
G18
G17
C20
B21
A21
F16
G16
F17
F18
A20
D18
L17
V12
W9
Y7
Y8
AA5
AB4
AA7
V9
AB5
V10
AA8
Y6
U8
Y5
W7
AA4
AB7
Y9
W8
AB3
Y2
V5
V14
U2300
10V
0.1uF
CERM
402
20%
2
1
C2440
10K
MF-LF
402
5%
1/16W
1 2
R2450
10K
MF-LF
402
5%
1/16W
1 2
R2451
10K
MF-LF
402
5%
1/16W
1 2
R2452
10K
MF-LF
402
5%
1/16W
1 2
R2453
10K
MF-LF
402
5%
1/16W
21
R2456
10K
MF-LF
402
5%
1/16W
1 2
R2457
10K
MF-LF
402
5%
1/16W
21
R2459
1/16W
5%
402
10K
MF-LF
21
R2463
SAT_PWRON
1K
MF-LF
402
1%
1/16W
21
R2460
MF-LF
402
5%
1/16W
4.7K
21
R2461
10K
MF-LF
402
5%
1/16W
21
R2466
10K
MF-LF
402
5%
1/16W
21
R2465
10K
MF-LF
402
5%
1/16W
21
R2467
10K
MF-LF
402
5%
1/16W
21
R2468
1K
MF-LF
402
1%
1/16W
NOSTUFF
21
R2462
10K
MF-LF
402
5%
1/16W
21
R2455
10K
MF-LF
402
5%
1/16W
21
R2454
3.3
MF-LF
805
5%
1/8W
21
R2405
MF-LF
3.3
805
5%
1/8W
21
R2410
3.3
MF-LF
805
5%
1/8W
21
R2420
3.3
MF-LF
805
5%
1/8W
21
R2430
10K
MF-LF
402
5%
1/16W
21
R2464
10K
MF-LF
402
5%
1/16W
21
R2422
MF-LF
402
5%
1/16W
4.7K
NOSTUFF
21
R2406
10K
MF-LF
402
5%
1/16W
21
R2404
10K
MF-LF
402
5%
1/16W
21
R2421
SAT_RUN
1K
MF-LF
402
1%
1/16W
21
R2416
NOSTUFF
10K
MF-LF
402
5%
1/16W
21
R2417
10K
MF-LF
402
5%
1/16W
2 1
R2413
10K
MF-LF
402
5%
1/16W
2 1
R2414
10K
MF-LF
402
5%
1/16W
2 1
R2415
1/16W
5%
MF-LF
10K
402
2
1
R2476
MPIC_SB
2N3904LF
SOT23
2
3
1
Q2476
MPIC_SB
10K
MF-LF
402
5%
1/16W
21
R2475
1/16W
5%
402
MF-LF
0
MPIC_SB
21
R2478
MPIC_NB
0
MF-LF
402
5%
1/16W
2
1
R2479
NO STUFF
0
MF-LF
402
5%
1/16W
21
R2407
MPIC_NB
10K
21
R2408
MPIC_NB
21
R2409
MPIC_NB
21
R2412
MPIC_NB
MF-LF
402
5%
1/16W
21
R2418
10K
MF-LF
402
5%
1/16W
21
R2419
SM
2
1
XW2400
P4MM
SM
1
PP2400
P4MM
SM
1
PP2405
P4MM
SM
1
PP2406
I586
I587
I588
I589
I590
I591
I592
I593
I594
I595
I596
I597
I598
I599
I600
I601
33
63
RP2410
33
54
RP2410
33
81
RP2420
33
72
RP2410
33
63
RP2420
33
81
RP2410
33
63
RP2430
33
72
RP2430
33
54
RP2430
33
81
RP2430
33
72
RP2420
33
54
RP2420
0
MF-LF
402
5%
1/16W
21
R2402
0
MF-LF
402
5%
1/16W
21
R2432
Shasta Serial / Misc
SYNC_DATE=05/19/2005
SYNC_MASTER=FINO-ME
154
051-6863
07
24
TITLE=KILOHANA
ABBREV=DRAWING
SB_CPU_VDNAP2
NB_SLOT_RESET_L
PCI_AIRPORT_INT_L
NB_SLOT_RESET_L_R
SB_PCI_SEL32BIT
RAI_EXP_INTR_L<3>
RAI_EXP_INTR_L<0>
=PP3V3_PWRON_SB
VOLTAGE=1.2V
PP1V2_PWRON_SB_PLL45VDD
MIN_NECK_WIDTH=0.38mm
MIN_LINE_WIDTH=0.50mm
P3MM SPACING
PCI_AIRPORT_INT_L
I2S1_DEV_TO_SB_DTI
I2S1_RESET_L
CPU_A0_INT_R_L
NB_CPU_A0_INT_L
I2S0_MCLK
I2S0_TO_DEV
AUDIO
I2S0_MCLK
I2S0_BITCLK
I2S0_MCLK_R
I2S2_SB_TO_DEV_DTO_R
I2S2_MCLK_R
I2S2_BITCLK_R
I2S2_SYNC_R
I2S2_SB_TO_DEV_DTO
I2S1_SYNC_R
I2S1_BITCLK_R
I2S1_MCLK_R
I2S1_SB_TO_DEV_DTO_R
I2S1_SYNC
I2S1_BITCLK
I2S1_MCLK
I2S1_SB_TO_DEV_DTO
I2S0_SYNC_R
I2S0_BITCLK_R
I2S0_SB_TO_DEV_DTO_R
I2S0_SYNC
I2S0_SB_TO_DEV_DTO
P3MM SPACING
PCI_USB2_INT_L
P3MM SPACING
SB_CPU_A1_SRESET_L
SB_CPU_B0_SRESET_L
P3MM SPACING
SB_CPU_B1_SRESET_L
P3MM SPACING
=PP2V5_PWRON_SB
I2S0_DEV_TO_SB_DTI
P3MM SPACING
I2S1_RESET_L
SB_GPIO_H_3
=PP3V3_RUN_SB_PCI
NB_TO_SB_INT
SB_CPU_A0_INT_L
NB_INT_L_R
=PP3V3_RUN_SB_PCI
MAKE_TBEN_SYNC_L
SYS_OVERTEMP_L
PCI_USB2_INT_L
PCI_AIRPORT_INT_L
I2S1_RESET_L
SB_CPU_A0_INT_L
SB_CPU_A1_INT_L
SB_CPU_B0_INT_L
SB_CPU_B1_INT_L
RAI_ALERT_L
SB_CLK18M_XTALO
PP_1V2PWRONSBPLL45VDD
ENET_ENERGYDET
FW_LOWPWR
ENETFW_RESET
MAKE_TBEN_SYNC_L
SMU_TO_SB_INT_L
SYS_SLEWING_L
RAI_FATAL_L
GIGE_P2_INTB_L
GIGE_P1_INTA_L
FW_LOWPWR_R
=PP3V3_PWRON_SB
NB_CHP_FLT_N_B
SB_CPU_VDNAP1
SB_TO_SMU_INT_L
SB_VDNAP0
SB_GPIO14
SB_CPU_VDNAP2
LOGIC_BRD_GOOD
SYS_OVERTEMP_L
MB_SLOT_RESET_L
NB_SLOT_RESET_L
PCIX_INT_L
=PP1V2_PWRON_SB
SB_SFC_RESET_L
I2S2_DEV_TO_SB_DTI
I2S2_TO_SB
SB_CLK18M_XTALO
0.38mm SPACING
I2S2_BIDIR
I2S2_SYNC
I2S1_SYNC
I2S1_BIDIR
I2S1_BITCLK
I2S1_BIDIR
I2S1_MCLK
I2S1_TO_DEV
0.25mm SPACING
I2S0_BITCLK
I2S0_BIDIR
I2S0_DEV_TO_SB_DTI
I2S0_TO_SB
SB_CLK25M_SATA
SB_CLK25M_ATA
0.38mm SPACING
SB_CLK18M_XTALO_R
0.38mm SPACING
I2S2_MCLK
I2S2_TO_DEV
0.25mm SPACING
I2S0_SB_TO_DEV_DTO
I2S0_TO_DEV
I2S1_SB_TO_DEV_DTO
I2S1_TO_DEV
SB_CLK18M_XTAL 0.38mm SPACING
SB_CLK18M_XTALI
I2S0_SYNC
I2S0_BIDIR
I2S1_DEV_TO_SB_DTI
I2S1_TO_SB
I2S2_SB_TO_DEV_DTO
I2S2_TO_DEV
TP_SB_FSTEST
=PP3V3_PWRON_SB
VOLTAGE=1.2V
PP1V2_PWRON_SB_PLL49VDD
MIN_LINE_WIDTH=0.50mm
MIN_NECK_WIDTH=0.38mm
SB_CPU_B0_SRESET_L
SB_CPU_B1_SRESET_L
SB_CPU_A1_SRESET_L
SB_CPU_A0_SRESET_L
SB_CPU_B1_INT_L
SB_CPU_B0_INT_L
SB_CPU_A1_INT_L
SB_CPU_A0_INT_L
AUDIO_MIC_ID
AUDIO_HP_DET_L
AUDIO_LI_OPTICAL_PLUG_L
AUDIO_LO_DET_L
AUDIO_LO_OPTICAL_PLUG_L
ENET_ENERGYDET
MAKE_TBEN_SYNC_L
PCI_USB2_INT_L
ENETFW_RESET
FW_LOWPWR_R
RAI_FATAL_L
RAI_ALERT_L
GIGE_P2_INTB_L
GIGE_P1_INTA_L
RAI_EXP_INTR_L<1>
RAI_EXP_INTR_L<2>
PCIX_INT_L
SB_GPIO14
MB_SLOT_RESET_L
SYS_OVERTEMP_L
SB_VDNAP0
LOGIC_BRD_GOOD
SB_TO_SMU_INT_L
SB_CPU_VDNAP1
NB_CHP_FLT_N_B
SB_CLK25M_SATA
SB_CLK18M_XTALO_R
SB_CLK18M_XTALI
SB_TEST_MODE_PD
TP_SB_PLLTEST
JTAG_SB_TMS
JTAG_SB_TDI
JTAG_SB_TDO
JTAG_SB_TCK
TP_SB_WATCHDOG
I2C_SB_SDA
I2C_SB_SCL
SB_GPIO_H_3
I2S0_RESET_L
VOLTAGE=2.5V
PP2V5_PWRON_SB_XTALVDD
MIN_LINE_WIDTH=0.50mm
MIN_NECK_WIDTH=0.38mm
VOLTAGE=2.5V
PP2V5_PWRON_SB_XTAL18VDD
MIN_LINE_WIDTH=0.50mm
MIN_NECK_WIDTH=0.38mm
SB_STOPXTALS_L
SMU_SUSPENDREQ_L
SB_SUSPENDACK_L
SYS_PME_L
JTAG_SB_TRST_L
SYS_SLEWING_L
NB_TO_SB_INT
SMU_TO_SB_INT_L
NET_SPACING_TYPE=P3MM SPACING
SB_SFC_RESET_L
I2S0_RESET_L
P3MM SPACING
P3MM SPACING
SB_CPU_B0_INT_L
P3MM SPACING
SB_CPU_B1_INT_L
MB_SLOT_RESET_L
P3MM SPACING
SB_CPU_A0_SRESET_L
P3MM SPACING
P3MM SPACING
SB_CPU_A0_INT_L
P3MM SPACING
NB_TO_SB_INT
P3MM SPACING
NB_SLOT_RESET_L
P3MM SPACING
I2S2_RESET_L
I2S2_SYNC
I2S2_RESET_L
I2S2_BITCLK
=PP3V3_PWRON_SB
SHASTA_SYS_IO_RESET_L
SYS_IO_RESET_L
I2S2_DEV_TO_SB_DTI
I2S2_MCLK
P3MM SPACING
SB_CPU_A1_INT_L
I2S2_BITCLK
I2S2_BIDIR
AUDIO_LI_DET_L
AUDIO_SPKR_ID
AUDIO_SPDIFIN_INT_L
AUDIO_HP_MUTE_L
AUDIO_LO_MUTE_L
AUDIO_SPKR_MUTE_L
AUDIO_EXT_MCLK_SEL
LAST_MODIFIED=Thu May 19 14:26:41 2005
119
119
119
119
56
56
56
56
24
138
93
50
24
93
24
93
50
24
122
23
119
28
28
23
28
23
28
43
28
23
119
28
24
121
20
121
24
24
154
154
147
154
24
24
24
24
147
147
122
56
56
56
23
147
24
24
24
24
122
121
24
132
24
26
20
28
28
31
143
28
24
24
154
154
24
24
24
147
147
26
154
147
24
147
24
154
20
56
56
56
56
132
122
24
143
24
31
28
28
26
147
30
122
20
26
147
56
24
154
154
154
154
20
30
154
154
154
24
20
24
20
20
7
24
8
8
56
42
24
24
24
24
8
8
8
8
24
24
24
24
24
24
7
24
8
24
7
24
24
7
24
20
24
24
8
24
24
24
24
24
24
6
24
139
17
24
24
24
24
24
24
24
7
24
24
24
24
24
24
24
20
24
20
24
7
24
24
24
24
8
8
8
24
24
24
24
24
24
8
24
24
8
24
6
7
24
24
24
24
24
24
24
24
154
154
154
153
153
24
24
24
17
24
24
24
24
24
20
20
24
24
24
20
24
24
24
24
24
24
24
24
6
20
20
20
20
9
39
39
24
24
28
28
28
28
9
24
24
24
24
24
24
24
24
24
24
24
20
24
24
24
24
7
28
24
24
24
24
153
153
154
154
150
152
154
Preliminary
VDD_OVDD_2
VDD_OVDD_3
VDD_OVDD_5 VSS_OVDD_5
VSS_OVDD_3
VSS_OVDD_1VDD_OVDD_1
VDD_33_XTAL
VDD_OVDD_4 VSS_OVDD_4
VSS_15_C4
VSS_OVDD_2
VSS_15_PLL2VDD_15_PLL2
VDD_15_12_4
VDD_15_C4
VDD_15_PLL1
VSS_33_XTAL
VSS_15_PLL1
VDD_33_I VSS_33_I
VSS_12_6
VDD_15_C1
VDD_12_5
VSS_25
VSS_15_C3VDD_15_C3
VDD_25
VSS_12_5
VSS_33_BC
VSS_12_4VDD_12_4
VSS_15_PLL4
VSS_12_1
VSS_12_2
VDD_33_BC
VDD_12_1
VSS_15_C2
VDD_12_2
VDD_12_3 VSS_12_3
VDD_15_PLL4
VDD_15_C2
VDD_15_PLL3 VSS_15_PLL3
VDD_15_12_1
VDD_15_12_2
VDD_15_12_3
SHARED PIN
SYM 2 OF 2
VSS_15_C1
PP
PP
PP
PP
PP
PP
PP
PP
PP
DRAWING
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
Q63 APPLICATION IS PWRON
PLL_VDD ON IN SLEEP
ON IN SLEEP
ON IN SLEEP
PLACE NEAR PULSAR2
PLACE NEAR PULSAR2
PLACE NEAR PULSAR2
PLACE NEAR PULSAR2
PLACE NEAR PULSAR2
Q63 APPLICATION IS RUN
Q63 APPLICATION IS POWER ON
Q63 APPLICATION IS RUN
1/16W
5%
402
MF-LF
4.7
21
R2501
BGA
PULSAR2
SEE_TABLE
A3
B5
A7
B7
B10
D11
E1
K2
G1
L8
M4
D1
D12
C8
G11
M6
E12
J10
K11
M12
K8
K4
A1
B4
A5
C9
B11
B12
C2
L2
G2
K9
L4
D2
D10
B8
F11
L6
F2
C5
A9
J11
K5
H11
K12
M10
M7
M3
U2500
1/16W
5%
402
MF-LF
0
21
R2510
1/16W
5%
402
MF-LF
0
NOSTUFF
21
R2511
20%
402
CERM
0.1UF
10V
2
1
C2572
20%
402
CERM
0.1UF
10V
2
1
C2573
1/16W
5%
402
MF-LF
0
21
R2512
1/16W
5%
402
MF-LF
0
21
R2513
1/16W
5%
402
MF-LF
0
21
R2514
1/16W
5%
402
MF-LF
0
21
R2515
1/16W
5%
402
MF-LF
0
21
R2516
20%
402
CERM
0.1UF
10V
2
1
C2501
20%
402
CERM
0.1UF
10V
2
1
C2575
SM
2
1
XW2500
SM
P4MM
1
PP2500
SM
2
1
XW2501
SM
2
1
XW2502
SM
2
1
XW2503
SM
P4MM
1
PP2501
SM
P4MM
1
PP2502
P4MM
SM
1
PP2503
SM
P4MM
1
PP2506
SM
P4MM
1
PP2505
P4MM
SM
1
PP2507
SM
P4MM
1
PP2504
P4MM
SM
1
PP2508
1/16W
5%
402
MF-LF
4.7
21
R2503
1/16W
5%
402
MF-LF
4.7
21
R2505
20%
402
CERM
0.1UF
10V
2
1
C2505
0603
180-OHM-1.5A
21
L2501
20%
402
CERM
0.1UF
10V
2
1
C2509
20%
402
CERM
0.1UF
10V
2
1
C2511
0603
180-OHM-1.5A
21
L2503
20%
402
CERM
0.1UF
10V
2
1
C2513
0603
180-OHM-1.5A
21
L2505
20%
402
CERM
0.1UF
10V
2
1
C2515
0603
180-OHM-1.5A
21
L2507
20%
402
CERM
0.1UF
10V
2
1
C2517
20%
402
CERM
0.1UF
10V
2
1
C2519
20%
402
CERM
0.1UF
10V
2
1
C2522
1/16W
5%
402
MF-LF
4.7
21
R2507
0603
180-OHM-1.5A
21
L2509
20%
402
CERM
0.1UF
10V
2
1
C2520
20%
402
CERM
0.1UF
10V
2
1
C2527
20%
402
CERM
0.1UF
10V
2
1
C2528
20%
402
CERM
0.1UF
10V
2
1
C2529
20%
402
CERM
0.1UF
10V
2
1
C2530
20%
402
CERM
0.1UF
10V
2
1
C2551
20%
402
CERM
0.1UF
10V
2
1
C2523
20%
402
CERM
0.1UF
10V
2
1
C2524
20%
402
CERM
0.1UF
10V
2
1
C2525
20%
402
CERM
0.1UF
10V
2
1
C2526
20%
402
CERM
0.1UF
10V
2
1
C2531
20%
402
CERM
0.1UF
10V
2
1
C2532
20%
402
CERM
0.1UF
10V
2
1
C2533
20%
402
CERM
0.1UF
10V
2
1
C2534
10V
0.1UF
CERM
402
20%
2
1
C2535
10V
0.1UF
CERM
402
20%
2
1
C2536
10V
0.1UF
CERM
402
20%
2
1
C2537
10V
0.1UF
CERM
402
20%
2
1
C2538
10V
0.1UF
CERM
402
20%
2
1
C2574
1/16W
5%
402
MF-LF
4.7
21
R2509
20%
603
CERM1
2.2UF
6.3V
2
1
C2545
20%
603
CERM1
2.2UF
6.3V
2
1
C2569
20%
603
CERM1
2.2UF
6.3V
2
1
C2503
20%
603
CERM1
2.2UF
6.3V
2
1
C2507
20%
603
CERM1
2.2UF
6.3V
2
1
C2521
ABBREV=DRAWING
TITLE=KILOHANA
PULSAR2 POWER
SYNC_DATE=05/19/2005
SYNC_MASTER=Q63
051-6863
07
15425
C2545_1
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.5MM
=PP3V3_PWRON_PULSAR
=PP3V3_PWRON_PULSAR
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.64mm
MIN_NECK_WIDTH=0.2MM
PP3V3_PSL_XTAL
PP1V5_PSL_PLL2
VOLTAGE=1.5V
MIN_LINE_WIDTH=0.64mm
MIN_NECK_WIDTH=0.2MM
PP_1V5PULSAR2
PP_1V2PWRONPULSAR1
=PP1V5_PWRON_PULSAR
=PP1V5_PULSAR
=PP1V2_PWRON_PULSAR
=PP1V5_PULSAR
=PP1V5_PWRON_PULSAR
=PP3V3_PWRON_PULSAR
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.5MM
C2521_1
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.5MM
C2507_1
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.5MM
C2503_1
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.5MM
C2569_1
=PP3V3_RUN_PULSAR
=PP1V2_PWRON_PULSAR
=PP2V5_PWRON_PULSAR
PP3V3_PLSR_I
PP_OVDD_PULSAR1
PP_1V5PWRONPULSAR2
NO_TEST=YES
MIN_NECK_WIDTH=0.22MM
MIN_LINE_WIDTH=0.64MM
VOLTAGE=3.3V
PP3V3_PLSR_I
VOLTAGE=1.5V
MIN_LINE_WIDTH=0.64mm
MIN_NECK_WIDTH=0.2MM
PP1V5_PSL_PLL1
VOLTAGE=1.5V
MIN_LINE_WIDTH=0.64mm
MIN_NECK_WIDTH=0.2MM
PP1V5_PSL_PLL4
VOLTAGE=1.5V
MIN_LINE_WIDTH=0.64mm
MIN_NECK_WIDTH=0.2MM
PP1V5_PSL_PLL3
=PP1V5_PWRON_PULSAR
=PPOVDD_PULSAR
=PP2V5_PWRON_PULSAR
=PPOVDD_PULSAR
<XR_PAGE_TITLE>
LAST_MODIFIED=Thu May 19 14:26:42 2005
25C4
25B8
25D8
25C3
25C4
25D8
25B8
25B2
25A5
25B5
25A5
25D3
25A5
25B2
25D3
25B4
26D8
26D8
25C3
25B3
25C3
25D3
3B4
3B4
3A4
3A4
3B2
3A4
3A4
3B4
3A7
3B2
3C1
25C4
25B2
3A4
3A3
3C1
3A3
Preliminary
XIN
GPCLK33_F1
GPCLK33_F2
GPCLK33_F0
GPCLK33_E1
GPCLK33_E0
GPCLK25_F0
GPCLK25_F1
GPCLK25_E0
GPCLK25_E1
HTBEN_1
HTBEN_0
SLEWING*
HCLKN_2
HCLKN_1
HCLKP_0
HSYNC_2
SCLK
SDATA
HCLKP_2
HCLKN_0
HSYNC_1
PD
HSYNC_0
XOUT
HCLKP_1
RESET*
OEMODE
TEST_MODE
GPCLK12_C0
REF_25
REF_15
REF_33
GPCLK12P_A1
GPCLK12P_B0
GPCLK12N_A0
GPCLK12N_A1
GPCLK12N_B0
GPCLK12P_A0
ASEL_INT*
GPCLK12P_C0
GPCLK12N_C0
GPCLK12P_C1
GPCLK12N_C1
GPCLK12P_C2
GPCLK12N_C2
GPCLK12P_C3
GPCLK12N_C3
GPCLK12P_C4
GPCLK12N_C4
GPCLK12P_D0
GPCLK12N_D0
SYM 1 OF 2
PP
PP
PP
DRAWING
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
MB_PCIX_REFCLK
66MHZ, 1.5VOVDD
33MHZ, 3.3V
33MHZ, 3.3V
PLACE ALL 0-OHM SERIES RESISTORSRES
ON THIS PAGE NEAR PULSAR
PULLED UP TO PP3V3_RUN ON P.28
1.5VOVDD
1.5VOVDD
1.5VOVDD
33MHZ, 3.3V
66MHZ, 3.3V
66MHZ, 3.3V
25MHZ, 2.5V
25MHZ, 2.5V
25MHZ, 2.5V
25MHZ, 2.5V
66MHZ, 1.2V
66MHZ, 1.2V
66MHZ, 1.2V
100MHZ, 1.2V
100MHZ, 1.2V
100MHZ, 1.2V
100MHZ, 1.2V
100MHZ, 1.2V
100MHZ, 1.2V
100MHZ, 1.2V
100MHZ, 1.2V
100MHZ, 1.2V
300MHZ, 1.2V
300MHZ, 1.2V
200MHZ, 1.2V
200MHZ, 1.2V
200MHZ, 1.2V
200MHZ, 1.2V
(100MHZ FOR ASPEN)
66MHZ, 1.5VOVDD
200MHZ, 1.5VOVDD
200MHZ, 1.5VOVDD
200MHZ, 1.5VOVDD
200MHZ, 1.5VOVDD
TO 1.8V ON QUASAR PAGES
QUASAR CLOCKS ARE RESISTOR DIVIDED DOWN
LAST MODIFIED: APR 26, 04
200MHZ, 1.5VOVDD
200MHZ, 1.5VOVDD
PLACE R2602 BESIDE R2659
BGA
PULSAR2
C11
C12
E3
A12
B2
B1
C3
L1
F1
H10
C1
E2
A10
A11
C10
B9
A8
B3
C4
A6
A2
A4
B6
M2
M1
K1
J2
J1
J3
H2
H3
H1
E10
G12
K10
L11
L10
M9
L7
M5
K3
E11
F12
J12
L12
M11
L9
M8
L5
L3
H12
D3
U2500
1/16W
5%
402
MF-LF
0
21
R2654
1/16W
5%
402
MF-LF
0
21
R2656
5%
1/16W
402
MF-LF
0
NO STUFF
21
R2652
1/16W
5%
402
MF-LF
330K
NO STUFF
21
R2658
SM-2
CRITICAL
25.0000M
21
Y2601
CERM
402
5%
33PF
50V
2
1
C2605
5%
402
CERM
33PF
50V
2
1
C2607
1/16W
5%
402
MF-LF
24
NOSTUFF
2
1
R2662
F-ST-SM
U.FL-R_SMT
NOSTUFF
1
2
3
J2600
1/16W
5%
402
MF-LF
24
NOSTUFF
2
1
R2664
1/16W
1%
402
MF-LF
1K
2
1
R2625
MF-LF
402
1/16W
1%
1K
2
1
R2626
1/16W
1%
402
MF-LF
1K
2
1
R2627
5%
402
0
21
R2612
1/16W
5%
402
MF-LF
10K
2
1
R2613
1/16W
1%
402
MF-LF
1K
NOSTUFF
2
1
R2618
NOSTUFF
1/16W
1%
402
MF-LF
1K
2
1
R2621
1/16W
5%
402
MF-LF
10K
NOSTUFF
2
1
R2614
1/16W
5%
402
MF-LF
0
2
1
R2623
1/16W
5%
402
MF-LF
10K
2
1
R2616
1/16W
5%
402
MF-LF
0
21
R2628
1/16W
5%
402
MF-LF
0
21
R2631
1/16W
5%
402
MF-LF
0
21
R2632
1/16W
5%
402
MF-LF
0
21
R2635
1/16W
5%
402
MF-LF
0
21
R2636
1/16W
5%
402
0
MF-LF
21
R2641
1/16W
5%
402
MF-LF
0
21
R2643
1/16W
5%
402
MF-LF
0
21
R2645
1/16W
5%
402
MF-LF
0
21
R2647
1/16W
5%
402
MF-LF
0
21
R2649
1/16W
5%
402
MF-LF
0
21
R2651
1/16W
5%
402
MF-LF
0
21
R2653
0
402
MF-LF
1/16W
5%
21
R2655
0
MF-LF
402
5%
1/16W
21
R2657
0
5%
402
MF-LF
1/16W
21
R2659
1/16W
5%
402
MF-LF
0
21
R2660
1/16W
5%
402
MF-LF
0
21
R2663
1/16W
5%
402
MF-LF
0
21
R2665
1/16W
5%
402
MF-LF
0
21
R2637
1/16W
5%
402
MF-LF
0
21
R2639
1/16W
5%
402
MF-LF
0
21
R2634
5%
402
MF-LF
0
1/16W
21
R2633
1/16W
5%
402
MF-LF
0
21
R2629
1/16W
5%
402
MF-LF
0
NOSTUFF
21
R2630
1/16W
5%
402
MF-LF
0
21
R2668
1/16W
5%
402
MF-LF
0
21
R2669
1/16W
5%
402
MF-LF
0
21
R2670
5%
402
MF-LF
0
1/16W
21
R2671
1/16W
5%
402
MF-LF
0
21
R2672
1/16W
5%
402
MF-LF
0
21
R2673
1/16W
5%
402
MF-LF
0
21
R2666
1/16W
5%
402
MF-LF
0
21
R2667
402
0
MF-LF
1/16W
5%
21
R2675
1/16W
5%
402
MF-LF
0
21
R2674
5%
402
0
21
R2600
SM
P4MM
1
PP2602
P4MM
SM
1
PP2600
P4MM
SM
1
PP2601
1/16W
402
MF-LF
1%
49.9
NOSTUFF
21
R2601
ABBREV=DRAWING
TITLE=KILOHANA
PULSAR2 CLOCKS
SYNC_DATE=05/19/2005
SYNC_MASTER=FINO-ME
26
051-6863
07
154
EI_NB_SYSCLK_N
EI_CPU_B_SYSCLK_P
EI_CPU_B_SYSCLK_N
HT_CLK66M_SB
CPU_A_APSYNC_R
CPU_B_TBEN_CLK_R
CLK_RAI_PCIEB_N<0>
HT_NB_REFCLK_N<0>
HT_NB_REFCLK_P<0>
CLK_KOD_100M_P<0>
PCIE_C_REFCLKIN_N_C
PCIE_B_REFCLKIN_N_C
PCIE_B_REFCLKIN_P_C
PCIE_A_REFCLKIN_N_C
GFX_SLOT_PCIE_REFCLK_N_C
CLK_RAI_PCIEA_P<0>
CLK_RAI_PCIEC_N<0>
CLK_RAI_PCIEC_P<0>
CLK_RAI_PCIEB_P<0>
CLK_RAI_PCIEA_N<0>
PCIE_A_REFCLKIN_P_C
NB_PMR_CLK_N
NB_PMR_CLK_P_R
NB_PCIE_REFCLK_P_C
NB_PCIE_REFCLK_N_C
GFX_SLOT_PCIE_REFCLK_P_C
CLK_RAIREF_200M_P_R
NB_APSYNC_R
CPU_B_APSYNC_R
HT_SB_REFCLK_R
HT_NB_REFCLK_L0_R
SB_USB2_CLK_33MHZ_R
NB_DDR_REFCLK_P
PLS2_X_OUT_B
PLS2_INTERM
PCI_CLK33M_USB2
CLOCK_RESET_L
NB_PMR_CLK_P
NB_PMR_CLK_N_R
PLS2_REF33
PLS2_REF25
SYS_SLEWING_L_R
SB_CLK25M_SATA_R
EI_CPU_A_SYSCLK_P
EI_CPU_A_SYSCLK_N
SYS_SLEWING_L
CPU_A_TBEN_CLK_US
NC_CPU_B_TBEN_CLK_US
CPU_A_APSYNC
CPU_B_APSYNC
CLK_RAI_200M_N<0>
NB_APSYNC
EI_NB_SYSCLK_P
CLK_RAI_200M_P<0>
CLK_KOD_100M_N<0>
CLK_PCIE_SLOTA_P<0>
CLK_PCIE_SLOTA_N<0>
NB_DDR_REFCLK_N
CLK_RAI_GIGE_25MHZ
CPU_A_TBEN_CLK_R
CLK_RAIREF_200M_N_R
QUA0_REF_25MHZ_R
QUA1_REF_25MHZ_R
RAM_ARB1_REF25MHZ
PLS2_X_IN_B
PLS2_EXTCLK
I2C_CLOCK_B_SDA
PLSR2_OEMODE
SYS_SLEEP
PLS2_REF15
PLSR2_PD
PP3V3_PLSR_I
PCIE_C_REFCLKIN_P_C
HT_NB_REFCLK_H0_R
PLSR2_TM
I2C_CLOCK_B_SCL
PLSR2_ASEL_INT_L
PLS2_RESET_L
PLS2_X_IN
RAM_ARB0_REF25MHZ
PCI_CLK66M_SB_INT_R
PCI_CLK66M_SB_INT
CLK_RAI_REFCLK_66M_R
PCI_CLK33M_AIRPORT
PCI_CLK33M_SB_EXT_RR
PLS2_X_OUT
SB_AIRPRT_CLK_33MHZ_R
CLK_RAI_GIGE_25MHZ_R
NB_DDR_REFCLK_P_R
NB_DDR_REFCLK_N_R
SB_CLK25M_SATA
CLK_RAI_REFCLK_66M
CPU_TBEN_CLK
PCI_CLK33M_SB_EXT_R
LAST_MODIFIED=Thu May 19 14:26:43 2005
54 30 16 15
50
13
56
101
101
97
27
27
28
56
56
97
97
97
12
119
119
42
27
27
103
9
9
27
98
98
82
9
9
9
9
9
27
27
27
27
27
9
20
9
9
9
9
9
9
9
9
9
9
59
27
28
20
9
9
56
56
24
56
6
56
27
27
42
42
27
82
84
84
59
27
9
9
9
9
27
39
11
25
9
9
39
27
6
27
9
121
27
9
9
9
9
24
27
27
9
Preliminary
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
N/C CPUB CLOCKS
GENERATES CPUA AND CPUB TBEN_CLK
IT IS THE INPUT TO THE AND GATE WHICH
CPU_TBEN_CLK IS FOR Q63 ONLY
N/C QUASAR CLOCKS
N/C RAINIER CLOCKS
CLOCK CONSTRAINTS
RESPECTIVE BUS PAGES
NOTE:
NET_SPACING_TYPE
N/C ALIASES
ELECTRICAL_CONSTAINT_SET
ALL OTHER CLOCK CONTRAINTS ON THEIR
NET_PHYSICAL_TYPEDIFFERENTIAL_PAIR
I67
I68
I69
I70
SYNC_MASTER=FINO-ME
Pulsar Aliases
154
27
07
051-6863
SYNC_DATE=05/19/2005
P3MM SPACING
PCI_CLK_SB
PCI_CLK_SB
PCI_CLK66M_SB_INT
NB_PMR_CLK
NB_PMR_CLK
NB_PMR_CLK_SP
NB_PMR_CLK
NB_PMR_CLK_P
MAKE_BASE=TRUE
NC_CLK_RAI_REFCLK_66M
NB_PMR_CLK_N
NB_PMR_CLK
NB_PMR_CLK
NB_PMR_CLK_SP
NB_PMR_CLK
MAKE_BASE=TRUE
PCI_CLK33M_USB2
=PCI_CLK33M_USB2
CLK_RAI_200M_N<0>
MAKE_BASE=TRUE
NC_CLK_RAI_200M_N<0>
CLK_RAI_GIGE_25MHZ
MAKE_BASE=TRUE
NC_CLK_RAI_200M_P<0>
MAKE_BASE=TRUE
NC_CLK_RAI_PCIEA_N<0>
CLK_RAI_PCIEA_N<0>
MAKE_BASE=TRUE
NC_CLK_RAI_PCIEA_P<0>
CLK_RAI_PCIEA_P<0>
MAKE_BASE=TRUE
NC_CLK_RAI_PCIEB_N<0>
CLK_RAI_PCIEB_N<0>
MAKE_BASE=TRUE
NC_CLK_RAI_PCIEB_P<0>
CLK_RAI_PCIEB_P<0>
CLK_RAI_REFCLK_66M
CLK_RAI_200M_P<0>
CLK_RAI_PCIEC_P<0>
MAKE_BASE=TRUE
NC_CLK_RAI_PCIEC_P<0>
CLK_RAI_PCIEC_N<0>
MAKE_BASE=TRUE
NC_CLK_RAI_PCIEC_N<0>
CPU_TBEN_CLK
EI_CPU_B_SYSCLK_P
EI_CPU_B_SYSCLK_N
CPU_B_APSYNC
RAM_ARB0_REF25MHZ
MAKE_BASE=TRUE
NC_RAM_ARB0_REF25MHZ
RAM_ARB1_REF25MHZ
MAKE_BASE=TRUE
NC_RAM_ARB1_REF25MHZ
MAKE_BASE=TRUE
NC_CLK_RAI_GIGE_25MHZ
PCI_CLK_SB
PCI_CLK_SB PCI_CLK_SBPCI_CLK33M_SB_EXT_RR
MAKE_BASE=TRUE
NC_CPU_TBEN_CLK
MAKE_BASE=TRUE
NC_CPU_B_APSYNC
MAKE_BASE=TRUE
NC_EI_CPU_B_SYSCLK_N
MAKE_BASE=TRUE
NC_EI_CPU_B_SYSCLK_P
26
26
26
119
20
6
20
26
122
26
6
26
6
6
26
6
26
6
26
6
26
26
26
26
6
26
6
26
26
26
26
26
6
26
6
6
26
9
6
6
6
Preliminary
P9[7]
P9[6]
P9[5]
P8[7]
P8[6]
P8[5]
P3[7]
P3[6]
P3[5]
P3[4]
P2[6]
P2[7]
P2[4]
P2[5]
P1[4]
P1[3]
P1[2]
P1[1]
P1[0]
P0[4]
P0[0]
P0[2]
P0[3]
P0[1]
P0[7]
P0[6]
P0[5]
P3[3]
P3[2]
P3[1]
P3[0]
P2[3]
P2[2]
P2[1]
P2[0]
P1[5]
P1[6]
P1[7]
PCNVSS
RESET*
XOUT
VREF
XIN
P7[7]
P7[6]
P7[5]
P7[4]
P7[3]
P7[2]
P7[1]
P7[0]
P6[7]
P6[6]
P6[5]
P6[4]
P6[3]
P6[2]
P6[1]
P6[0]
P10[0]
P10[1]
P9[3]
P9[2]
P9[1]
P9[0]
P8[4]
P8[3]
P8[2]
P8[1]
P8[0]
P10[6]
P10[7]
P10[2]
P10[3]
P10[4]
P10[5]
VCC
AVSS
VSS
AVCC
SQW/
OUT
VBAT
SDA
SCL
X1
X2
GND
VCC
PP
PP
PP
PP
PP
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
DRAWING
P1[0] NOT USED --->
System Management Unit
DRIVEN PUSH/PULL
PULLUP AT LEVEL SHIFTER P.30
CLK1
Y
Portable
RXD0
S
AN02
RTS0*/
Desktop
S
CTS0*
RXD1
Y = Primary function
(see aliases below)
S = Spare
AN06
AN07
AN21
INT4*
AN2
Y
Y
Y
Y
Y
S
Y Y
TA2in
INT5*
Y
Y
AC adapter ID.
affect other analog inputs such as
this page.
NOTE: Some primary and alternate functions
NOTE: All analog inputs to SMU should have
a 100pF capacitor to the SMU AVSS
signal (GND_SMU_AVSS). None of
provided on another page.
provided on this page. Please.
reuire pull-ups that are not.
to ensure missing pull-ups are
review the latest SMU specification
those capacitors are provided on
NOTE: Pinout matches SMU pinout v1.51.
Caps should connect to GND_SMU_AVSS.
(NONE)
(NONE)
NOTE: CPU current/voltage monitoring
BOM options provided by this page:
YYS
S
Y Y
SS
SS
Y Y
Y
Y
Y
Y Y
Y
Y
Y
Y
Y
Y Y
Y
Y
YY
Y
Y
S N YY
NS
S
Y Y Y Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
S
S
IOC3
CLK3
IOC7
Sin3
IOC6
IOC5
Sout3
YY YYY
YYYY
Y YYY
YY
Y
Y
N S YY
Y
SYYN
N
Y
YY
S
Y
Y
YY
S
Y Y
SN Y Y
Y Y Y Y
YYY Y
Y Y
YY
Y Y
NNS
SYYY
Y
Y S
Y S
S
Y Y
S
S
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
AN22
IOC2
AN05
AN04
AN20
AN03
KI3*
Y
Y SYY
YYYSY
AN27
AN26
KI1*
AN0
AN1
AN3
KI0*
Y
Y
Y
Y
Y
Y
S
S
AN25
INT2*
CE*
AN24
TB2in
NMI*
Y
Y
Y
Y
Y
Y
Y
Y
Y
YYY
YYY
Y
YY Y
YY Y
YYY
Y
Y
Y
Y
Y YYY
SS
SYYS
SS
Y Y
Y
Y
YSY
Y
Y
Y Y Y
Y
Y
Y
Y
S
Y
Y
Y
Y
Y Y S S
YYY Y
Y
Y Y YY
Y
Y
SS SS
TA3in
TA3out
TA2out
Y
Y
Y
Y
N
Y
Y
Y
SDA
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
YY
Y
Y
Y
Y N
YSY
NYYY
N
Y
N
Y
Y
YYYYYY
YYY
Y Y Y
Y
Y
Y
Y
Y
NYY
Y Y
YYY
Y S
S
N
N
S
S
S
N = Alternate function
Y Y
Server
Portable
ConsumerYEntry Desktop
S
Consumer
Desktop
Server
Entry Desktop
N NY Y
Tower & Server
Real Time Clock
NC
Alternate Functions
Port
6.4
6.3
Port
6.1
6.2
6.0
7.2
Y
Y
S
Y
TA1out
SCL
TXD1
(BUSY)
RTS1*
TXD0
CLK0
TA4out
TA4in
INT0*
INT1*
Page Notes
Power aliases required by this page:
Signal aliases required by this page:
(CPU_SENSE_I/CPU_SENSE_V) requires
100K/10uF RC filter at SMU pins.
SMU_VREF should be same signal or
reference used by monitoring
circuit, but be aware that this will
N
Y
Y
Y
SCLmm
TB1in
TB0in
INT3*
Keep crystal subcircuit close to SMU.
IOC4
SDAmm
KI2*
N
SY
Y
AN00
AN01
YY
YYYY
Y
3.0
3.1
3.2
3.3
10.7
8.5
YY
TA1in
AN23
YY
DIFFERENTIAL_PAIR
ELECTRICAL_CONSTRAINT_SET
NET_SPACING_TYPE
Y2800’S LOAD CAPACITANCE IS 12PF
7.4
SMU Pull-ups / pull-down
NET_SPACING_TYPE
DIFFERENTIAL_PAIR
- =PPVREF_SMU (SMU AVCC OR 2.5V REFERENCE)
- =PP3V3_PWRON_SMU
- =PP3V3_ALL_RTC
- =PP3V3_ALL_SMU
ELECTRICAL_CONSTRAINT_SET
CRITICAL
10.0000M
8X4.5MM-SM
21
Y2800
SEE_TABLE
M30280F8-LF
QFP-80
10
12
11
77
13
9
79
80
1
2
3
4
5
7
8
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
40
41
42
43
32
33
34
35
36
37
38
39
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
68
69
70
71
72
73
74
76
59
60
61
62
63
64
65
66
67
6
75
78
U2800
DS1338U-33
MSOP
2
1
8
3
7
5
6
4
U2801
6.3V
1uF
CERM
402
10%
2
1
C2825
10K
MF-LF
402
5%
1/16W
2
1
R2825
50V
18PF
CERM
402
5%
2
1
C2804
50V
18PF
CERM
402
5%
2
1
C2805
0
MF-LF
402
5%
1/16W
2
1
R2817
NO STUFF
10M
MF-LF
402
5%
1/16W
21
R2816
10K
MF-LF
402
5%
1/16W
2
1
R2827
1/16W
1%
402
MF-LF
2.0K
21
R2812
1/16W
1%
402
MF-LF
2.0K
NOSTUFF
21
R2811
1/16W
5%
402
MF-LF
10K
NOSTUFF
21
R2813
1/16W
1%
402
MF-LF
100K
21
R2810
10K
1/16W
5%
402
MF-LF
21
R2802
10K
MF-LF
402
5%
1/16W
21
R2800
1/16W
5%
402
MF-LF
10K
12
R2804
10V
0.1uF
CERM
402
20%
2
1
C2809
10V
0.1uF
CERM
402
20%
2
1
C2808
0.1uF
10V
CERM
402
20%
2
1
C2802
0.1uF
20%
10V
CERM
402
2
1
C2801
805
10UF
6.3V
X5R
10%
2
1
C2800
6.3V
1uF
CERM
402
10%
2
1
C2803
4.7
MF-LF
402
5%
1/16W
21
R2815
SM
21
XW2800
CRITICAL
32.768K
SM-LF
4
1
Y2801
I456
I457
10K
1/16W
5%
402
MF-LF
21
R2801
P4MM
SM
1
PP2800
SM
2
1
XW2802
P4MM
SM
1
PP2801
SM
2
1
XW2801
SM
P4MM
1
PP2806
SM
P4MM
1
PP2805
P4MM
SM
1
PP2804
I472
I473
I474
I475
051-6863
07
28 154
SYNC_MASTER=Q63
SYNC_DATE=05/19/2005
System Management Unit
ABBREV=DRAWING
TITLE=KILOHANA
P3MM SPACING
SYS_RESET_BUTTON_L
P3MM SPACING
CLOCK_RESET_L
P3MM SPACING
SMU_IO_RESET_L
SMU_RESET_L
SMU_IO_RESET_L
SYS_POWER_BUTTON_L
SMU_CLK10M_XOUT_R
SMU_CLK10M_XIN
PP_3V3ALLSMUAVCC
=PP3V3_ALL_SMU
PP_3V3ALLSMU
SMU_CLK10M_XIN
SMU_CLK10M_XTAL
0.38MM SPACING
SMU_BOOT_CE
=PP3V3_ALL_SMU
SMU_RESET
SYS_IO_RESET_L
0.25MM SPACING
SYS_POWERUP_L
SMU_SLEEP
SMU_SUSPENDREQ_L
SYS_SLEWING_L
SYS_PME_L
=PP2V5_PWRON_NB_MISC
=PP3V3_RUN_SMU
=PP3V3_PWRON_SMU
CPU_VID<2>
I2C_SMU_CPU_SDA_IN
I2C_SMU_A_SDA_IN
I2C_SMU_A_SDA
I2C_SMU_A_SCL
RTC_CLK32K_X1
RTC_CLK32K_XTAL
0.38MM SPACING
SMU_SER_SEL
SMU_FAN_RPM3
SMU_PWRSEQ_P1_4
SMU_FAN_RPM6
SMU_FAN_RPM7
SAT_MRESET_L
CPU_A_INSERTED_L
SMU_FAN_PWM8
CPU_B_INSERTED_L
SMU_FAN_PWM9
SMU_CLK10M_XOUT
0.38MM SPACING
RTC_CLK32K_X2
0.38MM SPACING
NB_TDI
NB_TCK
NB_TMS
NB_TDO_SMU
SMU_BOOT_BUSY
MAKE_BASE=TRUE
CPU_VID<5>
SMU_BOOT_SCLK
I2C_SMU_CPU_SCL_OUT_L
I2C_SMU_CPU_SDA_OUT_L
I2C_SMU_A_SCL_OUT_L
I2C_SMU_A_SCL_IN
I2C_SMU_E_SDA
I2C_SMU_A_SCL_OUT_L
I2C_SMU_A_SDA_OUT_L
SMU_FAN_TACH1
SMU_FAN_TACH2
SMU_FAN_TACH4
SMU_FAN_TACH5
I2C_SMU_A_SDA_IN
I2C_SMU_A_SCL_IN
SMU_FAN_TACH6
SMU_FAN_TACH7
SMU_FAN_TACH3
I2C_SMU_E_SCL
SYS_OVERTEMP_L
SMU_CLK10M_XOUT
SMU_FAN_RPM4
CPU_VID<2>
CPU_VID<1>
I2C_SMU_B_SDA
I2C_SMU_B_SCL
SMU_SLEEP
SMU_FAN_TACH8
SB_TO_SMU_INT_L
SB_STOPXTALS_L
SMU_PWRSEQ_P9_5
I2C_SMU_CPU_SCL_OUT_L
SMU_PWRSEQ_P1_1
SMU_PWRSEQ_P1_0
SMU_FAN_TACH9
SYS_DOOR_AJAR_L
SMU_FAN_TACH0
I2C_SMU_A_SDA_OUT_L
DIAG_LED
SMU_SUSPENDREQ_L
SYS_POWERFAIL_L
I2C_SMU_CPU_SCL_IN
CPU_VID<1>
CPU_VID<0>
CPU_VID<4>
CPU_VID<3>
I2C_RTC_SDA
=PP3V3_ALL_SMU
=PP3V3_ALL_RTC
RTC_CLK32K_X1
RTC_CLK32K_X2
I2C_RTC_SCL
GND_SMU_AVSS
SMU_FAN_RPM5
CPU_BYPASS
CPU_SENSE_V
SMU_PWRSEQ_P1_3
SMU_PWRSEQ_P1_2
SMU_BOOT_TXD
SMU_BOOT_CNVSS
SMU_FAN_RPM1
SMU_FAN_RPM2
SMU_BOOT_RXD
SYS_POWERUP_L
MAKE_BASE=TRUE
I2C_SMU_CPU_SDA_OUT_L
SYS_SLEWING_L
SYS_PME_L
SYS_LED
SB_SUSPENDACK_L
NB_SUSPENDACK_L
SYS_POWER_BUTTON_L
=PPVREF_SMU
0.38MM SPACING
SMU_CLK10M_XOUT_R
VOLTAGE=0V
GND_SMU_AVSS
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.38mm
CPU_TEMP
CPU_SENSE_I
CPU_VID<4>
CPU_VID<3>
PP3V3_ALL_SMU_AVCC
MIN_LINE_WIDTH=0.38mm
MIN_NECK_WIDTH=0.2MM
VOLTAGE=3.3V
CPU_VID<0>
I2C_SMU_CPU_SDA_IN
I2C_SMU_CPU_SCL_IN
SB_CPU_VDNAP2
SMU_FAN_RPM0
SMU_PWRSEQ_P9_6
SYS_SLOT_PWR
SB_CPU_VDNAP1
SB_CPU_VDNAP0_OR_QREQ_OR_SPDIF
CLOCK_RESET_L
SYS_RESET_BUTTON_L
SYS_RESET_BUTTON_L
SYS_NORTH_RESET_L
0.25MM SPACING
SMU_RESET
SYS_NORTH_RESET_L
SYS_NORTH_RESET_L
0.25MM SPACING
SYS_NORTH_RESET_L
<XR_PAGE_TITLE>
LAST_MODIFIED=Thu May 19 14:26:45 2005
157D3
157D3
157D3
157A6
157A6
157A6
38B3
38B3
157D6
38B3
30B6
30B6
157D5
30B6
30A6
30A6
157C2
30A6
29D7
29D7
38D7
29D7
29D3
29D3
38D2
29D3
29C7
29C7
39D4
38C7
38B3
45A4
29C7
29B7
29B7
45A6
30D6
38B8
30D8
43A4
29B7
45A6
30D8
30D8
30D8
30D8
29A6
29A6
122A7
30C8
43A6
122A7
30C6
38B1
30C8
38C3
30C8
29A6
43A6
122A7
28D6
28D6
28D6
28D3
28C1
157C6
28D2
28D6
119A4
30C8
30A7
28C3
113A6
29C3
29D5
30C5
24C2
30C8
30A7
45A8
28D6
31A4
28B1
113A6
157C6
31A4
45B1
45B1
28D3
28D3
28D3
28C3
28D3
28C3
28B3
30B8
30B8
28C1
28C2
28D2
29D6
28B3
29D8
30A5
26D4
28C3
20C1
29A4
30B7
29C3
24B3
39A7
39A7
29D8
30A5
43A8
28C2
29A1
157C8
28C1
26D4
28B1
28B3
29A1
43B1
43B1
28B3
28C1
28C3
28B1
28B1
28B1
8D6
28B3
29D8
29A4
29D8
8D6
8A5
8A5
24B7
16C8
28B3
28B3
24B2
24B5
20B3
8D8
29D7
157C6
32D8
32C8
32D8
32C8
20B3
32D8
32C8
24A7
29C6
29C6
28B1
32D8
24C3
32C8
38B3
8B6
28B1
8A3
8A5
28A4
121B1
121B1
16C8
24B2
24B5
8D6
28D4
24D2
24D2
28D4
8D6
8D6
20C3
20C3
20C3
20C3
6C7
26D7
28B3
6C7
28D6
6C7
28D6
28D6
3B6
28B6
29D3
3B6
21C5
8A6
6C7
24B5
24A3
21C1
3C1
3A7
3B4
28C3
28C3
28B6 39D8
39D8
28D1
157A8
32B8
4D1
32B5
32A5
29A5
30D4
32B5
30C3
32A5
28A7
28D1
29C3
29C3
6C7
29D7
29D1
29D3
28B3
28B3
28B6
28B6
39B8
28A4
28B6
32C5
32B8
32A8
32D5
28A5
28A4
32B5
32A5
32A8
39B8
8B5
28D6
32A8
28A5
28A5
6D7
6D7
6C7
32B5
24C2
24B5
4D1
28A4
4D1
4D1
32A5
8B8
32C5
28A5
8A7
24B5
7A4
28C3
28C3
28C3
28C3
28C3
39B5
3B6
3C4
28D6
28D6
39B5
6A5
32D5
30A7
30A7
4D1
4D1
29D1
29D3
32C5
32B8
157D1
8A6
28A4
24A3
21C1
8C7
24B5
30B3
6C7
29B1
28B6
6A5
30A7
30A7
28A4
28A4
29B3
28A5
28A5
28A5
24C3
32C5
4D1
31A4
24C3
157C6
26D7
6C7
6C7
6B7
6B7
6B7
6B7
Preliminary
G
D
S
G
D
S
REFERENCE DESIGNATOR(S)
BOM OPTION
TABLE_5_HEAD
QTY
DESCRIPTION
PART#
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
TABLE_5_ITEM
518S0171
I2C ADDR:72(1001000)
DIGITAL GND THROUGHOUT
SYS LED’S
SAME CONNECTOR AS Q63 CPU CARD FOR SAT
POWERRESET
SYS POWER AND RESET BUTTON
SMU RESET BUTTON
SMU DEBUG/DOWNLOAD CONNECTOR
FROM SMU
DRIVE STRONG HRESET AND BYPASS TO CPU
PCB: PLACE Q2984 NEAR CPU
ALWAYS ON (TRICKLE)
RTC BATTERY
AMBIENT LIGHT SENSOR CONNECTOR
518S0170
POWER BUTTON HEADER
TH
BB10209-A5
CRITICAL
1 2
J2902
SPST
SM
43
21
SW2902
SPST
SM
DEVELOPMENT
43
21
SW2900
5%
1K
402
MF-LF
1/16W
21
R2913
SPST
SM
DEVELOPMENT
43
21
SW2901
DEVELOPMENT
5%
402
1K
1/16W
MF-LF
21
R2912
5%
1/16W
MF-LF
402
1K
21
R2902
PP5V_PWRON
SM6
WHITE
2
1
LED2901
NOSTUFF
402
MF-LF
1/16W
5%
0
21
R2900
17_INCH_LCD
56.2
1%
MF-LF
1/16W
402
2
1
R2903
FDV301N
SM
2
1
3
Q2901
4.7K
5%
1/16W
MF-LF
402
NOSTUFF
2
1
R2908
SOT23
MMBD914XXG
3
1
D2900
SOD-123
B0530WXF
2 1
DS2900
MF-LF
402
1/16W
5%
30K
2
1
R2929
6.3V
CERM
402
1UF
10%
2
1
C2900
DEVELOPMENT
5%
402
1/16W
MF-LF
0
21
R2931
DEVELOPMENT
F-RT-SM
SM12B-SRSS-TB-LF
9
8
7
6
5
4
3
2
12
11
10
1
13
14
J2904
I6
1/16W
402
MF-LF
5%
0
NOSTUFF
2
1
R2925
1%
100
DEVELOPMENT
402
1/16W
MF-LF
21
R2930
402
MF-LF
1/16W
5%
1K
21
R2983
402
MF-LF
1/16W
5%
1K
21
R2984
2N7002DW-X-F
SOT-363
1
2
6
Q2984
SOT-363
2N7002DW-X-F
4
5
3
Q2984
SM
53398-0471
4
3
2
1
6
5
J2901
PP3V3_PWRON
53398-0271
SM
2
1
4
3
J2903
10K
5%
MF-LF
402
1/16W
2
1
R2924
10K
5%
MF-LF
402
1/16W
NOSTUFF
2
1
R2923
CERM
402
10V
20%
0.1UF
2
1
C2904
10V
402
0.1UF
20%
CERM
2
1
C2905
R2903
114S3921
20_INCH_LCD
1
RES, 39.2 OHM, 1%, 402
SMU SUPPLEMENTAL (2)
07
051-6863
29
154
SYNC_MASTER=FINO-MS
SYNC_DATE=05/19/2005
NC_J2904_6
SMU_BOOT_SCLK
SMU_BOOT_CNVSS
POWER_BUTTON_L
CPU_HRESET_L
CPU_BYPASS_L
CPU_BYPASS
CPU_HRESET
SYS_RESET_BUTTON_L
SYS_POWER_BUTTON_L
=PP3V3_ALL_RTC
MIN_NECK_WIDTH=0.2MM
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.6MM
PP3V3_ALL_BATT_SAFETY
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
MAKE_BASE=TRUE
PP3V3_ALL_RTC
PP3V3_ALL_BATT
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=3.3V
=PPV_EI_CPU
=PP3V3_ALL_SMU
SMU_BOOT_CE
SMU_MANUAL_RESET_L
SMU_BOOT_TXD
NC_J2904_11
NC_J2904_12
SMU_BOOT_BUSY
SMU_MANUAL_RESET_L
=PP3V3_ALL_SMU
RESET_BUTTON_L
POWER_BUTTON_L
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
SYS_LED_DRV_K
SYS_LED_DRV_C
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.25MM
SYS_LED
SMU_RESET_L
SMU_BOOT_RXD
I2C_ALS_SCL
I2C_ALS_SDA
SMU_BOOT_BUSY_R
56 48
29
29
47
28
28
28
28
29
28
30
7
28
29
28
28
29
7
29
28
28
6
6
6
43
43
28
31
28
6
28
7
6
6
6
6
6
6
6
6
6
6
6
28
6
6
39
39
Preliminary
G
D
S
G
D
S
125
125
G
D
S
G
D
S
G
D
S
EN*
GND
B
A
A*/B
Y*
Y
VCC
G
D
S
G
D
S
Y0
Y1
GND
E*
A
VCC
G
D
S
Y
A
GND
VCC
125
Y
GND
VCC
A
34
Y
GND
VCC
A
34
Y
GND
VCC
A
34
Y
GND
VCC
A
34
G
D
S
G
D
S
G
D
S
G
D
S
G
D
S
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
PCB; PLACE U5640 AND R3039 NEAR CPU
LEVEL SHIFT TDO FROM CPU TO MUX
CONSIDER COMBINING Q3040 AND Q3006 TO A DUAL PART
TO LEVEL SHIFTER
PULLDOWNS TO BUFFERS/LOGIC GATES
SHARE CPU AND NB JTAG TDO WITH SMU
VIH=2V
SYS_NORTH_RESET FROM SMU TO NB_PU_RST
SAME AS Q63
SAME AS Q63
SMU TO NB SUSPEND_REQ
MISC. SMU BUFFERS
SAME AS (Q63).
U700 IS POWERED BY PP3V3_ALL
NB SUSPEND_ACK_L LEVEL 2.5V TO 3.3V LEVEL SHIFTER
VCC RANGE 0.8V - 2.7V
VIH = 1.0V, 3.3V TOLERANT
VCC RANGE 0.8V - 2.7V
VCC RANGE 0.8V - 2.7V
VIH = 1.0V, 3.3V TOLERANT
VIH = 2.0V, 3.3V TOLERANT
VIH = 2.0V, 3.3V TOLERANT
NB JTAG IS A DEVELOPMENT ONLY FEATURE
SHARE CPU AND NB JTAG TMS WITH SMU
ALL JTAG-RELATED PINS
SMU DRIVES 3.3V PUSH-PULL ON
STRAIGHT TO NB
PULLUP IF
KODIAK JTAG IS NOSTUFFED
PCB: PLACE U3030 AND U3031 NEAR CPU AND KODIAK.
PCB: PLACE 33 OHM RES NEAR U3030/31 PART.
PCB: PLACE R3050, Q3050, R3051 NEAR CPU. PLACE Q3021, R3052 NEAR SMU.
PCB: PLACE U3070 NEAR SMU
PCB: PLACE U3071 NEAR SMU OR NEAR KODIAK.
VCC RANGE 0.8V - 2.7V
3.3V TOLERANT
SHARE SMU JTAG TCK WITH CPU AND NB (PRIMARY PLAN)
LEVEL SHIFT SMU TMS TO CPU (PRIMARY PLAN)
U5640 IS POWERED BY PPV_EI_CPU
VIH = 1.0V
DEMUX DRIVES PUSH-PULL 2.5V
LEVEL SHIFT SMU TMS TO CPU (BACKUP PLAN)
STUFF IF USING REGISTERED DIMM
SHARE SMU JTAG TDI WITH CPU AND NB (PRIMARY PLAN)
SMU JTAG TDI TO CPU (BACKUP PLAN)
SMU JTAG TCK TO CPU (BACKUP PLAN)
SOT-363
2N7002DW-X-F
1
2
6
Q3005
2N7002DW-X-F
SOT-363
4
5
3
Q3000
402
MF-LF
1/16W
0
NOSTUFF
5%
21
R3008
5%
100
402
MF-LF
1/16W
2 1
R3022
5%
100
MF-LF
402
1/16W
2 1
R3023
TSSOP
74LCX125
8
14
107
9
U700
5%
1/16W
4.7K
402
MF-LF
2
1
R3021
74LCX125
TSSOP
6
14
47
5
U700
2N7002
SOT23-LF
NOSTUFF
2
1
3
Q3040
1K
1/16W
MF-LF
402
NOSTUFF
5%
2
1
R3040
2N7002DW-X-F
SOT-363
4
5
3
Q3005
5%
4.7K
402
MF-LF
1/16W
2
1
R3003
5%
1/16W
MF-LF
402
4.7K
2
1
R3010
2N7002
SOT23-LF
NOSTUFF
2
1
3
Q3006
CRITICAL
TSSOP
SN74LVC2G157
3
5
8
4
7
2
6
1
U3070
0.1UF
CERM
10V
20%
402
2
1
C3070
NOSTUFF
0
1/16W
MF-LF
402
5%
21
R3009
5%
MF-LF
402
1/16W
10K
2 1
R3050
5%
402
MF-LF
1/16W
1K
2
1
R3051
100
MF-LF
402
1/16W
5%
2
1
R3052
SOT23
2N3904LF
2
3
1
Q3050
0.1UF
CERM
10V
20%
402
2
1
C3071
5%
1K
1/16W
402
MF-LF
2
1
R3093
5%
402
MF-LF
1/16W
1K
2
1
R3091
SOT23
2N3904LF
NB_SUSPEND_ACK_L_R
2
3
1
Q3090
MF-LF
402
1/16W
10K
5%
2 1
R3090
5%
MF-LF
1/16W
0
NOSTUFF
402
2 1
R3092
2N7002DW-X-F
SOT-363
1
2
6
Q3000
2N7002DW-X-F
SOT-363
4
5
3
Q3021
CRITICAL
74LVC1G
SC70-6
4
6
5
2
3
1
U3071
0.1UF
CERM
10V
20%
402
2
1
C3030
5%
MF-LF
402
1/16W
33
2 1
R3030
33
1/16W
402
MF-LF
5%
2 1
R3031
33
DEVELOPMENT
5%
MF-LF
402
1/16W
2 1
R3033
33
5%
MF-LF
402
1/16W
DEVELOPMENT
2 1
R3032
DEVELOPMENT
0.1UF
CERM
10V
20%
402
2
1
C3031
MF-LF
402
1/16W
5%
10K
2
1
R3034
MF-LF
402
1/16W
5%
10K
2
1
R3035
33
1/16W
402
MF-LF
5%
2 1
R3039
SOT-363
2N7002DW-X-F
1
2
6
Q3021
MF-LF
402
1/16W
10K
5%
2 1
R3038
100K
5%
402
MF-LF
1/16W
21
R3036
1/16W
MF-LF
402
5%
100K
21
R3071
100K
5%
402
MF-LF
1/16W
21
R3037
100K
5%
402
MF-LF
1/16W
21
R3070
CRITICAL
VSSOP
SN74AUC2G125
6
8
1
4
2
U5640
CRITICAL
SOT23-6
SN74AUC2G34
6
5
2
1
U3030
SOT23-6
SN74AUC2G34
4
5
2
3
U3030
DEVELOPMENT
SOT23-6
SN74AUC2G34
6
5
2
1
U3031
DEVELOPMENT
SOT23-6
SN74AUC2G34
4
5
2
3
U3031
SOT-363
2N7002DW-X-F
1
2
6
Q3080
1/16W
MF-LF
4.7K
402
5%
2
1
R3083
SOT-363
2N7002DW-X-F
1
2
6
Q3081
1/16W
MF-LF
402
5%
1K
2
1
R3084
NOSTUFF
33
1/16W
402
MF-LF
5%
2 1
R3085
5%
MF-LF
402
1/16W
33
NOSTUFF
2 1
R3082
1K
5%
402
MF-LF
1/16W
2
1
R3081
2N7002DW-X-F
SOT-363
4
5
3
Q3081
5%
402
4.7K
MF-LF
1/16W
2
1
R3080
2N7002DW-X-F
SOT-363
4
5
3
Q3080
NOSTUFF
0
1/16W
402
MF-LF
5%
21
R3099
NOSTUFF
0
1/16W
402
MF-LF
5%
21
R3098
1K
MF-LF
402
1/16W
5%
2
1
R3027
SOT-363
2N7002DW-X-F
4
5
3
Q3031
1K
1/16W
MF-LF
402
5%
2
1
R3026
SOT23
2N3904LF
2
3
1
Q3030
5%
MF-LF
402
1/16W
10K
2 1
R3020
NOSTUFF
5%
MF-LF
402
1/16W
33
2 1
R3028
5%
402
MF-LF
1/16W
1K
2
1
R3000
5%
1/16W
MF-LF
402
100
2
1
R3001
5%
MF-LF
402
1/16W
0
NOSTUFF
21
R3002
5%
402
4.7K
MF-LF
1/16W
2
1
R3007
5%
10K
1/16W
MF-LF
402
2
1
R3006
SYNC_MASTER=FINO-MS
SYNC_DATE=05/19/2005
SMU SUPPLEMENTAL (3)
051-6863
07
30
154
JTAG_CPU_TCK
SMU_JTAG_TDI
SMU_JTAG_TDI_L
JTAG_CPU_TDI
JTAG_CPU_TDI_2_R
=PP3V3_RUN_SMU
=PPV_EI_CPU
JTAG_CPU_TMS
JTAG_CPU_TMS_R
SMU_CPU_TMS
=PP3V3_PWRON_SMU
JTAG_CPU_TMS_2_L
SMU_CPU_TMS
JTAG_SMU_TMS_2_R
SMU_JTAG_TCK
SMU_JTAG_TCK_L
JTAG_CPU_TCK_2_R
=PP3V3_RUN_SMU
=PPV_EI_CPU
SYS_IO_RST_L_R
SMU_IO_RESET
=PP3V3_PWRON_SMU
JTAG_CPU_TMS_2_R
JTAG_CPU_TMS
=PPV_EI_CPU
SMU_JTAG_TCK
JTAG_NB_TCK_R
=PP2V5_PWRON_NB_MISC
SMU_JTAG_TDI
JTAG_NB_TDI_R
JTAG_CPU_TCK_RJTAG_CPU_TDI_R
SMU_CPU_NB_SEL
=PP3V3_PWRON_SMU
JTAG_NB_TDO
NB_SUSPENDACK_L
NB_SUSPENDACK
JTAG_NB_TMS
SMU_CPU_TMS
=PP2V5_PWRON_NB_MISC
=PP2V5_PWRON_NB_MISC
JTAG_CPU_TDI JTAG_CPU_TCK
JTAG_NB_TDI JTAG_NB_TCK
=PP3V3_PWRON_SMU
SYS_IO_RESET_L
=PP3V3_PWRON_SMU
SMU_SLEEP
SMU_IO_RESET_L
SYS_SLEEP_R
SYS_SLEEP
NB_PU_RESET
=PP2V5_PWRON_NB_MISC
PMU_SUSPEND_REQ
SYS_SLEEP
SYS_2SLEEP_R
=PP2V5_PWRON_NB_MISC
SYS_IO_RST_L_R
=PP3V3_PWRON_SMU
=PP3V3_PWRON_SMU
NC_JTAGMUX_3
SMU_JTAG_TDO
JTAG_CPU_TDO_3V3
SMU_JTAG_TMS
NB_SUSPEND_ACK_L
SMU_JTAG_TDI
SMU_JTAG_TCK
SMU_JTAG_TMS
SMU_CPU_NB_SEL
SMU_SUSPENDREQ_L
NB_SUSPEND_REQ_L
SYS_NORTH_RESET_L
NB_PU_RST_L
SYS_NORTH_RESET_L_R
JTAG_CPU_TDO
JTAG_CPU_TDO_R
JTAG_CPU_TDO_L
=PP3V3_PWRON_SMU
JTAG_CPU_TDO_3V3
=PP2V5_PWRON_NB_MISC
JTAG_NB_TDO
=PPV_EI_CPU
SMU_SUSPENDREQ_L_R
54
54
30
30
56
56
56
26
26
56
48
48
48
39
39
39
16
39
16
39
39
48
30
47
43
30
47
43
47
30
43
30
30
43
122
43
15
30
15
30
43
43
43
30
47
28
30
30
28
30
30
30
28
30
28
28
30
119
30
13
28
13
28
30
30
43
30
28
30
43
31
43
20
29
43
28
31
20
29
28
43
29
31
20
31
31
28
30
20
20
43 43
28
28
28
12
20
12
20
28
28
31
31
31
31
31
28
47
28
20
30
29
30
30
30
7
7
30 30
7
30
30
7
7
30
67
7
30
7
30
7
30
30
7
20
28
20
30
7
7
30 30
20 20
7
24
7
28
28
11
7
11
7
30
7
7
9
31
30
30
20
30
30
30
30
24
20
28
20
43
7
30
7
20
7
Preliminary
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
SELECT BETWEEN CPU OR NB TMS AND TDO FROM/TO SMU
M23/M33 ONLY CONNECTS I2C TO KODIAK NOW; CPU HAS PULLUPS ON ITS PG.
CPU VID<0:5>
VID CONTROLLED BY SMU
2.2V FOR CPU VRM10.
NOTE:PULL UP CPU_VID<5>TO
Q63 NET NAME (SHARED PAGE)
P0.5
P0.6
P0.4
P0.3
P0.2
P0.1
P0.0
P0.7
P1.6
P1.7
P2.0
P1.5
P2.1
P1.4
P1.0
P1.1
P1.2
P1.3
M23 SMU ALLOCATION
CPU_VID_LE0
CPU_VID_LE1
CPU_SENSE_I1
CPU_SENSE_V1
CPU_TEMP1
POWERFAIL*
FAN_TACH2_1
DOOR_AJAR*
SMU_SCCL_SEL
FAN_CNTL0_6
FAN_CNTL0_5
FAN_CNTL0_4
CPU_SENSE_I0
CPU_SENSE_V0
CPU_TEMP0
CPU_BYPASS
PS1_3
PS1_4
P2.7
P3.0
P3.1
P3.2
P3.3
P2.6
P2.5
P2.2
P2.3
P2.4
P3.4
P3.5
P3.6
P3.7
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
CPU_VID[2]
CPU_VID[1]
CPU_VID[0]
OVERTEMP*
IIC_E_CLK
IIC_E_DAT
CPU_VID[3]
CPU_VID[4]
CPU_VID[5]
IIC_A_CLK
IIC_A_DAT
FAN_TACH2_7
FAN_TACH2_6
FAN_TACH2_5
FAN_TACH2_4
FAN_TACH2_3
FAN_TACH2_2
DIAG_LED
TCK
TDI
P7.2
P7.7
P7.6
P7.5
P7.4
P7.3
P7.0
P7.1
P6.6
P6.7
P8.0
P9.2
P9.1
P9.0
P8.1
P8.2
P8.3
P8.4
P8.5
P8.6
P8.7
SMU_DOORBELL*
CPU_HRESET
CLK_RESET*
NB_RESET*
SYSTEM_LED
FAN_CNTL7_7
FAN_CNTL7_5
FAN_CNTL7_4
FAN_CNTL7_3
DEBUG_RXD
DEBUG_TXD
IIC_B_DAT
IIC_B_CLK
SLEEP
POWERUP*
NB_TMS
SLEWING*
VDNAP0
PME*
VDNAP2
CPU_TMS
P10.1
P10.4
P10.3
P10.2
P10.0
P9.3
P9.5
P9.6
P9.7
P10.5
P10.6
P10.7
RST_BUTTON*
PWR_BUTTON*
SUSPEND_REQ*
SUSPEND_IO_ACK*
SUSPEND_ACK*
IO_RESET*
STOP_XTAL*
SLOT_TOTAL_PWR
TDO
VDNAP1
PS9_5
PS9_6
M23 NET NAME
M23/M33 DOESN’T USE. P1.0 NC ON PG 7.
M23/M33 DOESN’T USE P1.4. NC ON PG 7.
COMMENT (ONLY IF USE DIFFERS FROM Q63)
M23/M33 DOESN’T HAVE THOSE FANS.
Q63 USES SMU_SER_SEL FOR SPDIF-SMU-DEBUG. NOT M23/M33 FEATURE.
M23/M33 DOESN’T NEED TO MAKE VDNAP0 DO TRIPLE-DUTY.
M23/M33 USES TACH0 (P2.2), TACH1 (P2.3), TACH2 (P2.4) ONLY.
M23/M33 DOESN’T HAVE THIS FAN (P7.4)
M23/M33 USES FAN_RPM0 (P7.3), FAN_RPM1 (P7.5), FAN_RPM2 (P7.7) ONLY.
Q63 USE OF P7.2 IS PWM FAN
SMU USES P1.1, P1.2, P1.3, P9.5, P9.6 FOR PWRSEQ ON PG 7.
SMU USES P1.1, P1.2, P1.3, P9.5, P9.6 FOR PWRSEQ ON PG 7.
Q63 USE OF P9.1 IS TACH 8.
M23/M33 HAS NO SLOTS.
M23/M33 DOESN’T HAVE FAN TACHS P2.5, P2.6, P2.7.
CPU_VID_LE0 FOR Q82. NOT M23/M33 FEATURE.
CPU_VID_LE1 FOR Q82. NOT M23/M33 FEATURE.
M23/M33 DOESN’T HAVE THIS FAN.
CONSIDER DOOR_AJAR FOR M23/M33 DIMM ACCESS DOOR?
SMU ALIASES
ALIASES ARE ONLY NECESSARY WHERE USE DIFFERS FROM Q63.
Q63 NC’S THESE AS IT USES A SAT.
PP3V3_RUN
MF-LF
402
10K
5%
1/16W
2
1
R3104
10K
1/16W
MF-LF
402
5%
2
1
R3109
10K
402
MF-LF
1/16W
5%
2
1
R3108
MF-LF
1/16W
5%
20K
402
2
1
R3111
NOSTUFF
5%
1/16W
MF-LF
1K
402
2
1
R3127
1/16W
NOSTUFF
1K
5%
MF-LF
402
2
1
R3129
NOSTUFF
1/16W
1K
5%
MF-LF
402
2
1
R3130
10K
5%
1/16W
MF-LF
402
2
1
R3117
1/16W
10K
5%
MF-LF
402
2
1
R3116
402
MF-LF
1/16W
5%
10K
2
1
R3114
NOSTUFF
1K
5%
1/16W
MF-LF
402
2
1
R3131
1K
NOSTUFF
5%
1/16W
MF-LF
402
2
1
R3132
NOSTUFF
F-ST-SM
BM12B-SRSS-TB
9876543
2
121110
11314
J3108
1/16W
5%
0
402
MF-LF
21
R3120
0
5%
1/16W
MF-LF
402
21
R3122
402
MF-LF
0
5%
1/16W
21
R3119
402
5%
MF-LF
0
1/16W
21
R3121
402
5%
MF-LF
1/16W
0
21
R3124
402
5%
MF-LF
1/16W
0
21
R3123
31
154
07
051-6863
SYNC_DATE=05/19/2005
SYNC_MASTER=FINO-MS
SMU SUPPLEMENTAL (4)
MAKE_BASE=TRUE
SMU_JTAG_TDO
I2C_SMU_CPU_SCL_OUT_L
MAKE_BASE=TRUE
NC_SLOT_TOTAL_PWR
SYS_SLOT_PWR
I2C_SMU_CPU_SDA_OUT_L
MAKE_BASE=TRUE
CPU_HRESET
SMU_FAN_TACH8
MAKE_BASE=TRUE
SB_VDNAP0
SB_CPU_VDNAP0_OR_QREQ_OR_SPDIF
MAKE_BASE=TRUE
NC_I2C_SMU_CPU_SCL_IN
I2C_SMU_CPU_SCL_IN
I2C_SMU_CPU_SDA_IN
MAKE_BASE=TRUE
SMU_JTAG_TCK
I2C_SMU_A_SCL_OUT_L
MAKE_BASE=TRUE
SMU_JTAG_TDI
I2C_SMU_A_SCL_IN
MAKE_BASE=TRUE
NC_SMU_FAN_TACH5
SMU_FAN_TACH5
MAKE_BASE=TRUE
NC_SMU_FAN_TACH7
SMU_FAN_TACH7
MAKE_BASE=TRUE
NC_SMU_CPU_VID_LE1
SMU_FAN_TACH6
MAKE_BASE=TRUE
NC_SYS_DOOR_AJAR_L
SYS_DOOR_AJAR_L
MAKE_BASE=TRUE
NC_SMU_CPU_VID_LE0
SMU_FAN_TACH9
MAKE_BASE=TRUE
NC_SMU_SER_SEL
SMU_SER_SEL
MAKE_BASE=TRUE
NC_SMU_FAN_RPM5
SMU_FAN_RPM5
MAKE_BASE=TRUE
NC_SMU_FAN_RPM3
SMU_FAN_RPM3
MAKE_BASE=TRUE
NC_SMU_FAN_RPM4
SMU_FAN_RPM4
CPU_VID_R<2>
CPU_VID_R<3>
CPU_VID_R<0>
CPU_VID_R<1>
CPU_VID_R<5>
CPU_VID_R<4>
MAKE_BASE=TRUE
NC_SMU_FAN_TACH3
SMU_FAN_TACH4
SMU_FAN_TACH3
MAKE_BASE=TRUE
NC_SMU_FAN_TACH4
MAKE_BASE=TRUE
I2C_SMU_A_SCL
I2C_SMU_A_SDA_IN
I2C_SMU_A_SDA_OUT_L
MAKE_BASE=TRUE
I2C_SMU_A_SDA
MAKE_BASE=TRUE
SMU_JTAG_TMS
MAKE_BASE=TRUE
SMU_CPU_NB_SEL
NC_J3108_8
NC_J3108_9
NC_J3108_10
NC_J3108_11
NC_J3108_12
CPU_VID<1>
MAKE_BASE=TRUE
CPU_VID<2>
MAKE_BASE=TRUE
CPU_VID<3>
MAKE_BASE=TRUE
CPU_VID<4>
MAKE_BASE=TRUE
CPU_VID<5>
MAKE_BASE=TRUE
CPU_VID<0>
MAKE_BASE=TRUE
39
39
30 28
9
28
28
29 28
24 28
9
28
28
30 28
30 28
9
28
9
28
9
28
9
28
9
28
9
28
9
28
9
28
9
28
50
50
50
50
50
50
9
28
28
9
28
28
28
28
30
30
9
9
9 9 9
28
28
28
28
28
28
Preliminary
G
D
S
G
D
S
G
D
S
G
D
S
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
12V DC
GND
TACH
GND
FAN 0
FAN 1
12V DC
TACH
MOTOR CONTROL
518S0083
MOTOR CONTROL
518S0193
M23: ODD FAN
M33: ODD FAN
M23: HD FAN
M33: CPU FAN
PP3V3_RUN
10K
402
1/16W
MF-LF
5%
2
1
R3210
PP3V3_RUN
5%
402
MF-LF
1/16W
10K
2
1
R3259
NOSTUFF
603
0.1UF
20%
25V
CERM
2
1
C3202
1206
MF-LF
1/4W
5%
1.5K
2
1
R3205
1206A-03
NTHS5443T1
5
4
87632
1
Q3203
805
MF-LF
5%
1.5K
1/8W
2
1
R3207
MMBD914XXG
SOT23
3
1
D3202
805
0
5%
1/8W
MF-LF
21
R3208
16V
X7R
805
0.47UF
10%
2
1
C3204
805
MF-LF
1/8W
5%
3.9K
R3206
PP12V_RUN
SOT-363
2N7002DW-X-F
4
5
3
Q3201
MF-LF
1/8W
5%
1.0K
805
2
1
R3202
SOT-363
2N7002DW-X-F
1
2
6
Q3201
NTHS5443T1
1206A-03
5
4
87632
1
Q3253
CERM
20%
0.1UF
603
NOSTUFF
25V
2
1
C3252
805
MF-LF
5%
1.5K
1/8W
2
1
R3257
805
5%
0
1/8W
MF-LF
21
R3258
16V
X7R
0.47UF
805
10%
2
1
C3254
MF-LF
805
1/8W
5%
3.9K
R3256
MMBD914XXG
SOT23
3
1
D3252
1206
1.5K
5%
1/4W
MF-LF
2
1
R3255
SOT-363
2N7002DW-X-F
4
5
3
Q3251
PP12V_RUN
1.0K
MF-LF
1/8W
5%
805
2
1
R3252
SOT-363
2N7002DW-X-F
1
2
6
Q3251
ELEC
16V
20%
6.3X11-TH-LF
120UF
2
1
C3203
120UF
6.3X11-TH-LF
ELEC
20%
16V
2
1
C3253
805
1.0K
5%
1/8W
MF-LF
NOSTUFF
2
1
R3215
805
MF-LF
1/8W
5%
1.0K
NOSTUFF
2
1
R3265
805
0
5%
1/8W
MF-LF
21
R3266
1/8W
MF-LF
5%
0
805
21
R3216
B130LBT01XF
NOSTUFF
SMB
21
D3203
NOSTUFF
B130LBT01XF
SMB
21
D3253
CRITICAL
M-RT-SM
53261-0498
4
3
2
1
6
5
J3200
53261-0571
M-RT-SM
CRITICAL
5
4
3
2
1
7
6
J3201
SYNC_DATE=05/19/2005
SYNC_MASTER=FINO-PC
Fan 0, 1 & System Temp
07
051-6863
154
32
F1_DRV
SMU_FAN_RPM1
F0_VOLTAGE8R5
F0_DRV
SMU_FAN_RPM0
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM
FAN_1_OUT
F1_GATESLOWDN
F0_RCFEEDBK
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
FAN_0_PWR
MIN_LINE_WIDTH=0.5MM
SMU_FAN_TACH0
SMU_FAN_TACH1
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM
FAN_1_PWR
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
FAN_0_OUT
F0_GATESLOWDN
F1_RCFEEDBK
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
F1_VOLTAGE8R5
28
28
28
28
Preliminary
G
D
S
G
D
S
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
518S0193
ODD TEMP SENSOR
518S0193
12V DC
TACH
GND
FAN 2
I2C ADDR:0X92(1001001)
I2C ADDR:0X90(1001000)
M33: HD FAN
HD TEMP SENSOR
MOTOR CONTROL
M23: CPU FAN
518S0193
PP3V3_RUN
5%
402
MF-LF
1/16W
10K
2
1
R3309
PP3V3_RUN
CRITICAL
53261-0498
M-RT-SM
4
3
2
1
6
5
J3301
1206A-03
NTHS5443T1
5
4
87632
1
Q3303
SOT23
MMBD914XXG
3
1
D3302
25V
603
0.1UF
20%
CERM
NOSTUFF
2
1
C3302
805
MF-LF
1.5K
1/8W
5%
2
1
R3307
5%
MF-LF
805
1/8W
0
21
R3308
16V
X7R
805
10%
0.47UF
2
1
C3304
805
MF-LF
1/8W
5%
3.9K
R3306
MF-LF
1/4W
5%
1.5K
1206
2
1
R3305
SOT-363
2N7002DW-X-F
4
5
3
Q3301
PP12V_RUN
805
1.0K
5%
1/8W
MF-LF
2
1
R3302
SOT-363
2N7002DW-X-F
1
2
6
Q3301
6.3X11-TH-LF
ELEC
16V
20%
120UF
2
1
C3303
MF-LF
5%
1.0K
805
NOSTUFF
1/8W
2
1
R3315
MF-LF
1/8W
5%
0
805
21
R3316
B130LBT01XF
SMB
NOSTUFF
21
D3303
CRITICAL
53261-0498
M-RT-SM
4
3
2
1
6
5
J3302
PP3V3_RUN
CRITICAL
SM
53398-0471
4
3
2
1
6
5
J3300
SYNC_DATE=05/19/2005
SYNC_MASTER=FINO-PC
Fan 2 & HD Temp
154
33
07
051-6863
I2C_ODD_TEMP_SDA
SMU_FAN_TACH2
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
FAN_2_PWR
I2C_HD_TEMP_SDA
I2C_HD_TEMP_SCL
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM
FAN_2_OUT
F2_GATESLOWDN
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
F2_RCFEEDBK
I2C_ODD_TEMP_SCL
SMU_FAN_RPM2
F2_DRV
F2_VOLTAGE8R5
39
28
39
39
39
28
Preliminary
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