Apple iMAC G5 iSight FINO M23 DVT2 MLB 051-6790 Rev19 Schematic
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
78
6
5
4
3
ECN
ZONE
REV
DESCRIPTION OF CHANGE
FINO M23
397409
19
ENGINEERING RELEASED
12
CK
APPD
DATE
08/30/05
ENG
APPD
?
DATE
DVT2 - 8/30/05
PDF CSA
D
TABLE_TABLEOFCONTENTS_HEAD
2 2
TABLE_TABLEOFCONTENTS_ITEM
3 4
TABLE_TABLEOFCONTENTS_ITEM
4 5
5 6
TABLE_TABLEOFCONTENTS_ITEM
6 7
TABLE_TABLEOFCONTENTS_ITEM
7 8
TABLE_TABLEOFCONTENTS_ITEM
8 9
TABLE_TABLEOFCONTENTS_ITEM
9
11
TABLE_TABLEOFCONTENTS_ITEM
10 12
TABLE_TABLEOFCONTENTS_ITEM
11 13
C
B
A
TABLE_TABLEOFCONTENTS_ITEM
12 15
TABLE_TABLEOFCONTENTS_ITEM
13 16
TABLE_TABLEOFCONTENTS_ITEM
14 17
TABLE_TABLEOFCONTENTS_ITEM
15 19
TABLE_TABLEOFCONTENTS_ITEM
16 20
TABLE_TABLEOFCONTENTS_ITEM
17 23
TABLE_TABLEOFCONTENTS_ITEM
18 24
TABLE_TABLEOFCONTENTS_ITEM
19 25
TABLE_TABLEOFCONTENTS_ITEM
20 26
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
2721
TABLE_TABLEOFCONTENTS_ITEM
22 28
TABLE_TABLEOFCONTENTS_ITEM
23 29
TABLE_TABLEOFCONTENTS_ITEM
24 30
TABLE_TABLEOFCONTENTS_ITEM
25 31
TABLE_TABLEOFCONTENTS_ITEM
26 32
TABLE_TABLEOFCONTENTS_ITEM
27 33
TABLE_TABLEOFCONTENTS_ITEM
28 39
TABLE_TABLEOFCONTENTS_ITEM
29 41
TABLE_TABLEOFCONTENTS_ITEM
30 42
TABLE_TABLEOFCONTENTS_ITEM
31 43
TABLE_TABLEOFCONTENTS_ITEM
32 44
TABLE_TABLEOFCONTENTS_ITEM
33 47
TABLE_TABLEOFCONTENTS_ITEM
34 48
TABLE_TABLEOFCONTENTS_ITEM
35 49
TABLE_TABLEOFCONTENTS_ITEM
36 50
TABLE_TABLEOFCONTENTS_ITEM
37 52
TABLE_TABLEOFCONTENTS_ITEM
CONTENTS
System Block Diagram
Power Block Diagram
Table Items
FUNC TEST 1 OF 2
Power Conn / Alias
Signal Alias
FUNC TEST 2 OF 2
1.8V Vreg
1.5V Vreg
1.2V Vreg
2.5V Vreg
5V & 3.3V Fets
Vesta Core / Misc
KODIAK CORE & BYPASS
KODIAK & SHASTA MISC
Shasta Core Power
Shasta Serial / Misc
PULSAR2 POWER
PULSAR2 CLOCKS
Pulsar Aliases
System Management Unit
SMU SUPPLEMENTAL (2)
SMU SUPPLEMENTAL (3)
SMU SUPPLEMENTAL (4)
Fan 0, 1 & System Temp
Fan 2 & HD Temp
I2C Connections
KODIAK EI PWR & CAPS
KODIAK EI A
CPU EI AND IO
KODIAK EI B
CPU STRAPS
CPU POWER AND BYPASS
PROC DECOUPLING
CPU VCORE VREG
CPU VCORE MORE BYPASS
8
SYNC MASTER
FINO-DD
FINO-PC
FINO-DD
FINO-ME
M23-PC
FINO-DD
FINO-ME
M23-PC
FINO-PC
FINO-PC
FINO-PC
FINO-PC
FINO-DC
Q63
FINO-ME
Q63
FINO-ME
Q63
FINO-ME
FINO-ME
Q63
FINO-HS
FINO-HS
FINO-HS
FINO-HS
FINO-HS
FINO-ME
Q63
Q63
FINO-HS
Q63
FINO-HS
FINO-HS
FINO-HS
M23-HS
FINO-HS
DATE
06/20/2005
06/20/2005
06/20/2005
06/20/2005
06/20/2005
06/20/2005
06/20/2005
06/20/2005
06/20/2005
06/20/2005
06/20/2005
06/20/2005
06/20/2005
08/01/2005
06/20/2005
08/01/2005
06/20/2005
08/01/2005
06/20/2005
06/20/2005
08/01/2005
06/20/2005
06/20/2005
06/20/2005
06/20/2005
06/20/2005
06/20/2005
08/01/2005
08/01/2005
06/20/2005
08/01/2005
06/20/2005
06/20/2005
06/20/2005
06/20/2005
06/20/2005
PDF CSA
TABLE_TABLEOFCONTENTS_HEAD
38 54
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
39 55
TABLE_TABLEOFCONTENTS_ITEM
40 56
TABLE_TABLEOFCONTENTS_ITEMTABLE_TABLEOFCONTENTS_ITEM
58
41
TABLE_TABLEOFCONTENTS_ITEM
42
59
TABLE_TABLEOFCONTENTS_ITEM
43
61
TABLE_TABLEOFCONTENTS_ITEM
44 62
TABLE_TABLEOFCONTENTS_ITEM
45 63
TABLE_TABLEOFCONTENTS_ITEM
46 67
TABLE_TABLEOFCONTENTS_ITEM
47 68
TABLE_TABLEOFCONTENTS_ITEM
48 69
TABLE_TABLEOFCONTENTS_ITEM
49 70
TABLE_TABLEOFCONTENTS_ITEM
50 82
TABLE_TABLEOFCONTENTS_ITEM
51 84
52 85
TABLE_TABLEOFCONTENTS_ITEM
53 86
TABLE_TABLEOFCONTENTS_ITEM
54 87
TABLE_TABLEOFCONTENTS_ITEM
55 88
TABLE_TABLEOFCONTENTS_ITEM
56 89
57 90
TABLE_TABLEOFCONTENTS_ITEM
58 92
TABLE_TABLEOFCONTENTS_ITEM
59 93
TABLE_TABLEOFCONTENTS_ITEM
60 96
TABLE_TABLEOFCONTENTS_ITEM
61 97
TABLE_TABLEOFCONTENTS_ITEM
62 98
TABLE_TABLEOFCONTENTS_ITEM
63 101
TABLE_TABLEOFCONTENTS_ITEM
64 103
TABLE_TABLEOFCONTENTS_ITEM
65 119
TABLE_TABLEOFCONTENTS_ITEM
66 120
TABLE_TABLEOFCONTENTS_ITEM
67 121
TABLE_TABLEOFCONTENTS_ITEM
68 122
TABLE_TABLEOFCONTENTS_ITEM
69 125
TABLE_TABLEOFCONTENTS_ITEM
70 127
TABLE_TABLEOFCONTENTS_ITEM
71 129
TABLE_TABLEOFCONTENTS_ITEM
72 130
TABLE_TABLEOFCONTENTS_ITEM
73 131
TABLE_TABLEOFCONTENTS_ITEM
67
CONTENTS
CPU AVDD VREG
T,V,I SENSORS
CPU ALIASES & MISC
KODIAC NBMEM PWR & CAPS
Kodiak Memory Dq/Ctl
Parallel Term
Main Memory Clock Buffer
MEMORY ADDR BRANCHING
Memory Dimm A
MLB Mem Series Term
On-Board DDR SDRAM
On-Board DDR SDRAM
KODIAK PCI-E X16
GPU PCIe
Graphics Vregs
GPU Core Power
GPU Frame Buffer
FB Series Termination
GPU GDDR SDRAM A
GPU GDDR SDRAM B
GPU Straps
GPU DVI & DACs
TMDS/Inverter/ExtVGA
KODIAK PCI-E CONST
KODIAK HT16
HT ALIASES
Shasta HyperTransport
Shasta PCI Interface
PCI SERIES TERMINATION
AIRPORT & BLUETOOTH
USB 2.0 PCI Interface
BootROM
Shasta Disk
Disk Connectors
ENET SERIES TERM
Shasta Ethernet
5
SYNC MASTER
FINO-HS
FINO-HS
FINO-HS
Q63
FINO-DS
FINO-DS
FINO-DS
FINO-DS
FINO-DS
FINO-DS
FINO-DS
FINO-DS
Q63
FINO-DD
M23-DD
FINO-DD
FINO-DD
FINO-DD
FINO-DD
FINO-DD
FINO-DD
FINO-DD
M23-DD
FINO-DD
Q63
FINO-ME
Q63
Q63
FINO-MW
FINO-MW
Q63
Q63
M23-DC
M23-DC
FINO-DC
Q63
4
DATE
06/20/2005
06/20/2005
06/20/2005
08/01/2005
06/20/2005
06/20/2005
06/20/2005
06/20/2005
06/20/2005
06/20/2005
06/20/2005
06/20/2005
08/01/2005
06/20/2005
06/20/2005
06/20/2005
06/20/2005
06/20/2005
06/20/2005
06/20/2005
06/20/2005
06/20/2005
06/20/2005
06/20/2005
08/01/2005
06/20/2005
08/01/2005
08/01/2005
06/20/2005
06/20/2005
08/01/2005
08/01/2005
06/20/2005
06/20/2005
06/20/2005
08/01/2005
PDF CSA
TABLE_TABLEOFCONTENTS_HEAD
74
132
136
75
TABLE_TABLEOFCONTENTS_ITEM
138
76
TABLE_TABLEOFCONTENTS_ITEM
139
77
TABLE_TABLEOFCONTENTS_ITEM
140
78
TABLE_TABLEOFCONTENTS_ITEM
142
79
TABLE_TABLEOFCONTENTS_ITEM
143
80
TABLE_TABLEOFCONTENTS_ITEM
144
81
TABLE_TABLEOFCONTENTS_ITEM
145
82
TABLE_TABLEOFCONTENTS_ITEM
147
83
TABLE_TABLEOFCONTENTS_ITEM
148
84
TABLE_TABLEOFCONTENTS_ITEM
85
150
TABLE_TABLEOFCONTENTS_ITEM
152
86
TABLE_TABLEOFCONTENTS_ITEM
153
87
TABLE_TABLEOFCONTENTS_ITEMTABLE_TABLEOFCONTENTS_ITEM
154
88
TABLE_TABLEOFCONTENTS_ITEM
DIMENSIONS ARE IN MILLIMETERS
XX
X.XX
X.XXX
ANGLES
DO NOT SCALE DRAWING
THIRD ANGLE PROJECTION
3
CONTENTS
Vesta Ethernet PHY
ETHERNET CONNECTOR
Shasta FireWire
Vesta FireWire PHY
FIREWIRE CONNECTORS
USB Host Interfaces
USB Device Interfaces
Flash Media Ctrl
Flash Connector
AUDIO: CODEC
AUDIO: LINE INPUT AMP
AUDIO: LINE OUT AMP
AUDIO: SPEAKER AMP
AUDIO: CONNECTORS
AUDIO: POWER SUPPLIES
METRIC
NOTED AS
DESIGN CK
MFG APPD
DESIGNER
SCALE
NONE
SIZE
D
DRAFTER
ENG APPD
QA APPD
RELEASE
MATERIAL/FINISH
APPLICABLE
2
SYNC MASTER
Q63
FINO-DC
Q63
Q63
FINO-DC
Q63
FINO-PC
FINO-PC
FINO-PC
FINO-SO
FINO-SO
FINO-SO
FINO-SO
FINO-SO
FINO-SO
DATE
08/01/2005
06/20/2005
08/01/2005
08/01/2005
06/20/2005
07/05/2005
06/20/2005
06/20/2005
06/20/2005
08/01/2005
08/01/2005
08/01/2005
08/01/2005
08/01/2005
08/01/2005
Apple Computer Inc.
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
TITLE
SCH,MLB,FINO,M23
DRAWING NUMBER
051-6790
REV.
19
SHT
OF
1
1
D
C
B
A
154
78
6
U4300
5
4
CPU
NEO 10S
PCIE
PAGE
82
MISC
SATA
PAGE 43,48
APPLE PI
PAGE 42
U1900
KODIAK
CORE
PAGE 19
HYPERTRANSPORT
HYPERTRANSPORT
PAGE 103
U2300
32-BIT
APPLE PI
ELASTIC INTERFACE
667MHZ OR 733MHZ
PAGE 98PAGE 20
64-BIT
MAIN MEMORY
1.8V/533MHZ
PAGE 59
MAIN MEMORY
8-BIT
HYPERTRANSPORT
1.2V/800MHZ
CONTROL = 2.5V
PCI
U6200
CLOCK
BUFFER
PAGE 62
PARALLEL
TERM
PAGE 61
UC500
BOOTROM
PAGE 125 PAGE 122 PAGE 121
PAGE 119
32-bit PCI (5V-3.3V/33MHz)
J6700
DIMM
PAGE 67
JE310/JE320/JE330
USB
CONNECTORS
PAGE 143 PAGE 143
5
321
4
USB
PAGE 142
UC200
USB 2.0
uPD720101
PCI
SERIES
TERM
PAGES 68
JE350
BNDI
INTERFACE
JC150
WIRELESS
CONNECTOR
J9602, J9603
TMDS
EXT VGA
D
U8900, U8901
FRAME
BUFFER A
PAGE 89
U2500
PULSAR2
POWER
C
CLOCKS
PAGE 26PAGE 25
HARD DRIVE
64-BIT
FRAME BUFFER
M23:1.8V/600MHZ
M33:1.8V/700MHZ
JC900
SATA
CONNECTOR
PAGE 129
PAGE 96
U8400
GPU
M23:RV370 XT
M33:RV380 XT
PAGES 84,86,87,93
64-BIT
FRAME BUFFER
M23:1.8V/600MHZ
M33:1.8V/700MHZ
U9000, U9001
FRAME
BUFFER B
PAGE 90
SATA/150
1.2V/1.5GHZ
PCIE X16
2.5GHZ
I2C
PAGE 39
SATA1 SATA2
PAGE 127
3
ONBOARD MEMORY
PAGES 67,70
UE401
PAGE 144
64MX8
MEMORY
USB
HUB
UE400
FLASH
CTLR
PAGE 144
JE500
MEDIA CARD CONNECTOR
CF
PAGE 145
SD
FANS
TEMP SENSORS
PAGES 32,33
U2800
SMU
PAGE 28
SMU SUPPLEMENTAL
BUTTONS
ALS
SYSTEM LED
BATTERY
PAGES 29,30
12
U2801
RTC
PAGE 28
D
C
SHASTA
PAGE 127
JC901
B
OPTICAL
UATA
CONNECTOR
PAGE 129
UATA/133
3.3V/133MHZ
U1701
UATA
CORE
PAGE 23
ETHERNET FIREWIRE
PAGE 131 PAGE 138
8-bit TX & 8-bit RX
GMII (3.3V/125MHz)
NCs
PAGE 142
I2S
PAGE 24
SCCA SCCB
1394 OHCI (3.3V/98MHz)
8-bit TX/RX
I2S1
VESTA
GIG ETHERNET
A
4 Diff pairs
JD600
ETHERNET
CONNECTOR
PAGE 136 PAGE 140
FIREWIRE A
PAGE 139PAGE 132
1
0
2 Diff pairs
JEC00, JEC01
FIREWIRE A
CONNECTORS
PAGE 24
GPIO/PCI64
I2S2I2S0
UE700
AUDIO CODEC
PCM3052A
LINE IN
AMP
PAGE 148
JF300
LINE IN
CONNECTOR
PAGE 153
PAGE 147
BNDI
INTERFACE
S/PDIF
LINE OUT
AMP
PAGE 150
SPEAKER
AMP
PAGE 152
OPTICAL OUT
JF303
COMBO OUT
CONNECTOR
PAGE 153
LINE OUT
JF301
SPEAKER
CONNECTOR
PAGE 153
System Block Diagram
SYNC_MASTER=FINO-DD
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
APPLE COMPUTER INC.
SYNC_DATE=06/20/2005
NOTICE OF PROPRIETARY PROPERTY
SIZE
DRAWING NUMBER
051-6790
D
NONE
SHT
2
SCALE
B
A
REV.
19
OF
154
8
67
5
4
3
2
1
78
6
5
4
3
12
D
C
B
J700
PAGE 7
PP12V_ALL
FW CONN
PP1V5_PWRON
SWITCHER
PAGE 12
PULSAR
KODIAK CORE
PP1V5_RUN
FET SWITCH
PAGE 12
EI
GPU CORE
SWITCHER
PAGE 85 PAGE 11
PP12V_RUN
20" PANEL POWER
17" LCD INVERTER
CPU CORE
SWITCHER
PAGE 50
PP1V8_PWRON
SWITCHER
MAIN MEMORY
PP1V8_RUN
POWER SW
PAGE 11
GPU MEMORY
PP0V9_GPU_VTT
LINEAR
PAGE 91
PP1V8_RUN
IN
POWER CONNECTOR
PP5V_RUN
OPTICAL
PP4V5_RUN_AUDIO
LINEAR
PAGE 154
AUDIO CODEC
PP5V_PWRON
FET SWITCH
PAGE 16
PP2V5_PWRON
PAGE 15
PP5V_ALL
USB CONN
FET SWITCH
PP2V5_ALL
LINEAR
PAGE 15
PP2V5_RUN
FET SWITCH
PAGE 15
VESTA
PP3V3_PWRON
PAGE 16
FET SWITCH
MODEM & BT
USB2 HOST
PP1V8_TPVDD
LINEAR
PAGE 85
PP3V3_RUNPP3V3_ALL
PP2V5_RUN_CPU_AVDD
LINEAR
PAGE 54
PP1V8_GPU
LINEAR
PAGE 85
SYS_POWERUP_L
PCI BUS
AUDIO CODEC
PP1V5_VDDC_CT
LINEAR
PAGE 85
PP1V2_PWRON
PAGE 13
SHASTA CORE
PAGE 13
PP2V5_GPU_A2VDD
LINEAR
PAGE 85
PP1V2_TPVDD
PAGE 85
FET SWITCH
R440
100K
5%
1/16W
MF-LF
402
PP1V2_ALL
SWITCHER
VESTA CORE
LINEAR
IN
21
1
C440
0.01UF
20%
16V
2
CERM
402
COMPARE_PP1V8
NC_SMU_PWRSEQ_P1_0
6
NC_SMU_PWRSEQ_P1_4
6
12 13 12 13
PP3V3_PWRON
TURN_ON_PP3V3_PWRON_L
15
16
PP1V2_RUN
FET SWITCH
PAGE 13
PP2V5_ALL
TURN_ON_PP1V2_L
PWR_GOOD_PP1V5
PWR_GOOD_PP1V8
IN
HT BUS
1
R442
150K
5%
1/16W
MF-LF
402
2
PS_1V_REF
4
1
R443
100K
1%
1/16W
MF-LF
402
2
SYS_POWERUP_L
POWER SEQUENCE PIN
SMU_PWRSEQ_P1_0
SMU_PWRSEQ_P1_4
SMU_PWRSEQ_P1_1
SMU_PWRSEQ_P9_5
SMU_PWRSEQ_P9_6
SMU_PWRSEQ_P1_2
SMU_PWRSEQ_P1_3
PP1V5_PWRON
R430
100K
1/16W
MF-LF
402
PP5V_ALL
3
V+
U400
GND
12
LM339A
SOI-LF
6
7
5%
1
PS_1V_REF
4
21
COMPARE_PP1V5
PP2V5_ALL
1
C441
0.1UF
20%
10V
2
CERM
402
28
28
28
28
28
28
28
1
C430
0.01UF
20%
16V
2
CERM
402
SMU
1
R441
10K
5%
1/16W
MF-LF
402
2
PP2V5_ALL
1
2
8
9
R431
10K
5%
1/16W
MF-LF
402
V+
U400
GND
12
3
LM339A
SOI-LF
14
D
C
B
PP2V5_ALL
A
8
67
5
4
U400P2
3
V+
U400
GND
LM339A
SOI-LF
2
12
APPLE COMPUTER INC.
3
2
4
5
Power Block Diagram
SYNC_MASTER=FINO-PC
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
NONE
SHT
SCALE
SYNC_DATE=06/20/2005
051-6790
OF
4
1
A
REV.
19
154
TABLE_5_ITEM
TABLE_11_HEAD
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
TABLE_5_ITEM
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
REFERENCE DESIGNATOR(S)
BOM OPTION
TABLE_5_HEAD
QTY
DESCRIPTION
PART#
TABLE_ALT_ITEM
TABLE_11_HEAD
TABLE_11_HEAD
REFERENCE DESIGNATOR(S)
BOM OPTION
QTY
DESCRIPTION
VALUE VOLT. WATT.
TOL.PART #
PACKAGE
DEVICE
TABLE_ALT_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
REFERENCE DESIGNATOR(S)
BOM OPTION
TABLE_5_HEAD
QTY
DESCRIPTION
PART#
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
NEED TO UPDATED BIN CODES AS NOTES
PROCESSORS ASICS
MISC PARTS
ALTERNATES
PCB,SCHEM,MLB,M33
051-6863
1
20_INCH_LCD
SCH1
337S3226
17_INCH_LCD
U4300
337S3224
IC,DD3.1,1.9G,1.20V
2.1GHZ
45W
PROCESSOR
1
U4300
50MV
20_INCH_LCD
CRITICAL
CBGA-576-1MM
337S3220
1.10V
IC,GPUL,DD3.1,2.1G,85C
U4300
337S3221 337S3220
20_INCH_LCD
IC,DD3.1,2.1G,1.15V
343S0379
IC,KODIAK,V1.2,PBGA,200MM
CRITICAL
1
U1900
1
343S0377
CRITICAL
IC,ASIC,SHASTA,V1.1,PBGA,LF
U2300
IC,ASIC,VESTA,V1.3,LF
CRITICAL
343S0356
U1701
1
IC,PULSAR2,100P,P8MM,BGA
U2500
343S0319
1
CRITICAL
IC,DD3.0X,1.9G,1.20V
337S3229
17_INCH_LCD
337S3224
U4300
IC,DD3.0X,1.9G,1.30V
337S3231
17_INCH_LCD
U4300
337S3224
20_INCH_LCD
337S3220
U4300
337S3223
IC,DD3.1,2.1G,1.25V
337S3220
20_INCH_LCD
U4300
337S3222
IC,DD3.1,2.1G,1.20V
IC,DD3.0X,1.9G,1.25V
337S3230
17_INCH_LCD
U4300
337S3224
SPEC,VENDOR PACKAGING PROCEDURE
062-2082
1
VPP1
SYNC_MASTER=FINO-DD
SYNC_DATE=06/20/2005
19
5
154
Table Items
051-6790
1.10V
PROCESSOR
1.9GHZ
CBGA-576-1MM
45W
1
U4300
50MV
17_INCH_LCD
CRITICAL
337S3224
IC,GPUL,DD3.1,1.9G,85C
PCB,SCHEM,MLB,M23
1
051-6790 SCH1
17_INCH_LCD
17_INCH_LCD
CRITICAL
MECH3
M23 NB HEATSINK
603-7320
1
860-0708
SDFC900,SDFC901
M33 ODD NUTS
20_INCH_LCD
CRITICAL
2
875-1905
1
GAP1
CPU GAP FILLER
CRITICAL603-7322
1
MECH2
M33 GPU HEATSINK
20_INCH_LCD
1
603-7323
MECH3
20_INCH_LCD
M33 NB HEATSINK
CRITICAL
343S0356 VESTA A4
U1701
343S0388
126S0088126S0068
EL CAP
CF000
CRITICAL
U2800
341T1752
1
PURCH ASSY, SMU BIG
17_INCH_LCD
CRITICAL
MECH1
603-7318
1
M23 CPU HEATSINK
CRITICAL
20_INCH_LCD
MECH1
M33 CPU HEATSINK
1
603-7321
CRITICAL
17_INCH_LCD
MECH2
1
M23 GPU HEATSINK
603-7319
KINGBRIGHT LED
378S0141
LED700,LED702
378S0140
126S0078
EL CAP
126S0086 C722
337S3224
17_INCH_LCD
337S3225
IC,DD3.1,1.9G,1.15V
U4300
IC,DD3.1,1.9G,1.25V
337S3227 337S3224
17_INCH_LCD
U4300
337S3228
IC,DD3.0X,1.9G,1.15V
337S3224
17_INCH_LCD
U4300
CRITICAL341T1751
UC500
1
IC,FLASH,1MX8,3.3V,90NS
825-6447
1
LBL1
BARCODE LABEL, MLB
820-1766
1
MLB1
20_INCH_LCD
CRITICAL
PCB,FAB,MLB,M33
PCB,FAB,MLB,M23
820-1783
1
MLB1
17_INCH_LCD
CRITICAL
Preliminary
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
TOP SIDE ONLY
USE FAT TRACES
PLACE WITHIN 1 INCH OF EACH OTHER
FOR PP3V3_ALL AND GND
PLACE TWO TEST POINTS ON TOP SIDE
NOTES FROM TOM FUSSELMAN
FUNC TEST NETS
EE IDENTIFIED NO TEST NETS
NO TEST XW NETS
I1000
I1001
I1002
I1003
I1004
I1005
I1006
I1007
I1008
I1009
I1010
I1011
I1012
I1013
I1014
I1015
I1016
I1017
I1018
I1019
I1020
I1022
I1023
I1024
I1026
I1027
I1028
I1029
I1030
I1031
I1032
I1033
I1034
I1035
I1036
I1037
I1038
I1039
I1040
I1041
I1042
I1043 I1044
I1045
I1046
I1047
I1048
I1049
I1050
I1051
I1052
I1053
I1054
I1055
I1056
I1057
I1058
I1059
I1060
I1061
I1062
I1063
I1064
I1065
I1066
I1067
I1068
I1069
I1070
I1071
I1072
I1080
I1088
I1089
I1090
I1091
I1092
I1093
I1094
I1095
I1096
I1097
I1098
I1099
I1100
I1101
I1102
I1103
I1104
I1105
I1106
I1107
I1108
I1109
I1110
I1111
I1112
I1113
I1114
I1115
I1116
I1117
I1118
I1120
I1121
I1122
I1123
I1124
I1125
I1126
I1127
I1128
I1129
I1130
I1131
I1132
I1133
I1134
I1135
I1136
I1137
I1138
I1139
I1140
I1141
I1142
I1143
PP1V8_RUN PP3V3_RUN
PP1V5_PWRON
PP1V2_ALL
PP2V5_RUN
PP5V_ALL
PP3V3_ALL
PP12V_RUN
I1155
I1156
I1157
I1158
I1160
I1161
I1162
I1164
I1165
I1166
I1167
I1168
I1170
I1171
I1172
I1173
I1175
I1176
I1177
I1179
I1181
I1182
I1183
I1184
I1185
I1187
I1188
I1189
I1190
I1192
I1193
I1195
I1196
I1197
I1199
I1200
I1202
I1203
I1204
I1206
I1207
I1208
I1210
I1211
I1212
I1214
I1215
I1216
I1218
I1219
I1220
I1221
I1223
I1224
I1226
I1227
I1228
I1229
I1230
I1232
I1233
I1234
I1236
I1237
I1238
I1239
I1241
I1242
I1244
I1245
I1246
I1248
I1249
I1250
I1252
I1253
I1254
I1255
I1257
I1258
I1259
I1262
I1263
I1264
I1266
I1267
I1268
I1269
I1271
I1272
I1273
I1275
I1276
I1277
I1278
I1280
I1281
I1283
I1285
I1286
I1287
I1288
I1289
I1291
I1292
I1293
I1294
I1296
I1297
I1299
I1300
I1301
I1302
I1303
I1305
I1306
I1307
I1310
I1311
I1312
I1313
I1314
I1316
I1317
I1318
I1320
I1322
I1323
I1324
I1325
I1326
I1327
I1329
I1330
I1332
I1333
I1334
I1335
I1336
I1337
I1338
I1339
I1340
I1341
I1343
I1344
I1345
I1346
I1348
I1349
I1350
I307
I348
I349
I350
I356
I357
I358
I360
I361
I362
I375
I376
I428
I429
I826
I836
I837
I839
I841
I846
I847
I848
I849
I850
I851
I883
I947
I948
I949
I950
I951
I952
I953
I954
I955
I957
I958
I959
I960
I961
I962
I963
I964
I965
I969
I971
I972
I973
I974
I975
I976
I977
I978
I982
I984
I985
I986
I987
I988
I989
I990
I991
I992
I993
I994
I995
I996
I997
I998
I999
FUNC TEST 1 OF 2
051-6790
154
6
19
SYNC_MASTER=FINO-ME
SYNC_DATE=06/20/2005
FUNC_TEST=TRUE
PP1V8_RUN
PP3V3_RUN
FUNC_TEST=TRUE
PP1V5_PWRON
FUNC_TEST=TRUE
PP1V2_ALL
FUNC_TEST=TRUE
PP2V5_RUN
FUNC_TEST=TRUE
PP5V_ALL
FUNC_TEST=TRUE
PP3V3_ALL
FUNC_TEST=TRUE
FUNC_TEST=TRUE
PP12V_RUN
GND
FUNC_TEST=TRUE
NO_TEST=YES
GND_AUDIO_CODEC
RFBD<94>
NO_TEST=YES
RFBD<92>
NO_TEST=YES
RFBD<91>
NO_TEST=YES
RFBD<90>
NO_TEST=YES
NO_TEST=YES
RAM_DQ_R<30>
NO_TEST=YES
RAM_DQ_R<29>
NO_TEST=YES
RAM_DQ_R<31>
NO_TEST=YES
RAM_DQ_R<22>
NO_TEST=YES
RAM_DQ_R<21>
NO_TEST=YES
RAM_DQ_R<20>
NO_TEST=YES
RAM_DQ_R<19>
RAM_DQ_R<24>
NO_TEST=YES
NO_TEST=YES
RAM_DQ_R<32>
NO_TEST=YES
RAM_DQ_R<33>
NO_TEST=YES
RAM_DQ_R<34>
NO_TEST=YES
RAM_DQ_R<50>
RAM_DQ_R<52>
NO_TEST=YES
RAM_DQ_R<53>
NO_TEST=YES
NO_TEST=YES
RAM_DQ_R<54>
NO_TEST=YES
RAM_DQ_R<5>
RAM_DQ_R<7>
NO_TEST=YES
RAM_DQ_R<2>
NO_TEST=YES
NO_TEST=YES
RAM_DQ_R<44>
RFBD<85>
NO_TEST=YES
RFBD<106>
NO_TEST=YES
RFBD<112>
NO_TEST=YES
RFBD<109>
NO_TEST=YES
RFBD<105>
NO_TEST=YES
RFBD<104>
NO_TEST=YES
RFBD<102>
NO_TEST=YES
RFBD<101>
NO_TEST=YES
RFBD<108>
NO_TEST=YES
RFBD<126>
NO_TEST=YES
NO_TEST=YES
Q803_B
NO_TEST=YES
Q802_E
NO_TEST=YES
Q801_B
NO_TEST=YES
Q800_D
NO_TEST=YES
PCI_CLK66M_SB_INT_R
NO_TEST=YES
LED801_1
NO_TEST=YES
Q800_G
NO_TEST=YES
Q802_B
NO_TEST=YES
TP_USB2_PWREN<1>
NO_TEST=YES
TP_SB_FSTEST
NO_TEST=YES
TP_NEC_SMC
NO_TEST=YES
TP_NEC_TEST
NO_TEST=YES
UATA_DASP_L_DS
NO_TEST=YES
RFBD<16>
NO_TEST=YES
RFBD<15>
RFBD<11>
NO_TEST=YES
NO_TEST=YES
RFBD<6>
RFBD<2>
NO_TEST=YES
NO_TEST=YES
RAM_DQ_R<60>
NO_TEST=YES
RAM_DQ_R<59>
NO_TEST=YES
RAM_DQ_R<57>
NO_TEST=YES
RAM_DQ_R<56>
NO_TEST=YES
RAM_DQ_R<38>
NO_TEST=YES
RAM_DQ_R<25>
NO_TEST=YES
RAM_DQ_R<6>
NO_TEST=YES
RAM_DQ_R<9>
RAM_DQ_R<8>
NO_TEST=YES
RAM_DQ_R<1>
NO_TEST=YES
NO_TEST=YES
RAM_DQ_R<12>
NO_TEST=YES
RAM_DQ_R<11>
NO_TEST=YES
RAM_DQ_R<13>
NO_TEST=YES
RAM_DQ_R<14>
NO_TEST=YES
RAM_DQ_R<16>
NO_TEST=YES
RAM_DQ_R<17>
RAM_DQ_R<3>
NO_TEST=YES
RAM_DQ_R<43>
NO_TEST=YES
NO_TEST=YES
RFBD<3>
RFBD<1>
NO_TEST=YES
NO_TEST=YES
RAM_DQ_R<63>
NO_TEST=YES
RAM_DQ_R<58>
NO_TEST=YES
RAM_DQ_R<46>
NO_TEST=YES
RAM_DQ_R<36>
NO_TEST=YES
RFBD<8>
NO_TEST=YES
NC_CLK_RAI_REFCLK_66M
NO_TEST=YES
NC_CPU_B_TBEN_CLK_US
NO_TEST=YES
NC_CLK_RAI_PCIEA_P<0>
NO_TEST=YES
NC_CLK_RAI_PCIEB_P<0>
NC_CLK_RAI_200M_N<0>
NO_TEST=YES
NO_TEST=YES
NC_HT_MB_TO_NB_CAD_N<8..15>
NC_CPU_B0_QACK_L
NO_TEST=YES
NO_TEST=YES
RAM_DQ_R<40>
NO_TEST=YES
RAM_DQ_R<41>
NO_TEST=YES
RAM_DQ_R<28>
NO_TEST=YES
RAM_DQ_R<37>
NC_SATA_TXD_N2
NO_TEST=YES
NO_TEST=YES
NC_PMR_CLK_DIS_L
NO_TEST=YES
KOD_H05_GND
NO_TEST=YES
DAGND
NO_TEST=YES
TDIODE_NEG_FMAX
PP12V_AUDIO_SPKRAMP
NO_TEST=YES
PP_2V5PWRONSB_B9
NO_TEST=YES
PP_1V2PWRONSBPLL45VDD
NO_TEST=YES
PP_1V2PWRONSBVCORE
NO_TEST=YES
NO_TEST=YES
GND_U1300
NO_TEST=YES
PP_3V3PWRONSBPCI64
NC_NB_CPU_B1_INT_L
NO_TEST=YES
NC_CPU_A1_QACK_L
NO_TEST=YES
NO_TEST=YES
NC_EI_CPU_B_TO_NB_SR_N<0..1>
NO_TEST=YES
NC_NB_CPU_A1_INT_L
RFBD<124>
NO_TEST=YES
NO_TEST=YES
GND_AUD_LOAMP_CHGPMP
GND_AUD_LOAMP
NO_TEST=YES
PP_2V5PWRONSB
NO_TEST=YES
PP_OVDD_PULSAR1
NO_TEST=YES
NO_TEST=YES
RFBD<13>
NO_TEST=YES
LED802_1
NO_TEST=YES
RFBD<7>
NO_TEST=YES
NC_I2S2_MCLK
NO_TEST=YES
TP_SB<11>
RFBD<49>
NO_TEST=YES
RFBD<31>
NO_TEST=YES
NO_TEST=YES
NC_NCV1009_2
NO_TEST=YES
NC_SATA_RXD_P2_C
NO_TEST=YES
TP_SB<17>
NO_TEST=YES
TP_SB<20>
NO_TEST=YES
TP_SB<23>
NO_TEST=YES
TP_SB<22>
NO_TEST=YES
TP_SB<16>
RFBD<30>
NO_TEST=YES
NO_TEST=YES
TP_NEC_SMI_L
NO_TEST=YES
TP_USB2_PWREN<4>
NO_TEST=YES
TP_NEC_NTEST1
NO_TEST=YES
TP_USB2_PWREN<3>
NO_TEST=YES
TP_USB2_PWREN<2>
TP_SB_PLLTEST
NO_TEST=YES
NO_TEST=YES
TP_USB2_PWREN<0>
ITS_RUNNING
NO_TEST=YES
NO_TEST=YES
TP_FBBCS1_L
NO_TEST=YES
AUD_4V5_FB
RFBD<41>
NO_TEST=YES
RFBD<42>
NO_TEST=YES
RFBD<44>
NO_TEST=YES
RFBD<45>
NO_TEST=YES
RFBD<52>
NO_TEST=YES
RFBD<54>
NO_TEST=YES
RFBD<56>
NO_TEST=YES
RFBD<59>
NO_TEST=YES
RFBD<60>
NO_TEST=YES
RFBD<23>
NO_TEST=YES
RFBD<22>
NO_TEST=YES
RFBD<21>
NO_TEST=YES
RFBD<25>
NO_TEST=YES
RFBD<26>
NO_TEST=YES
RFBD<27>
NO_TEST=YES
RFBD<28>
NO_TEST=YES
NO_TEST=YES
TP_SB<0>
NO_TEST=YES
TP_SB<1>
NO_TEST=YES
TP_SB<3>
NO_TEST=YES
TP_SB<2>
NO_TEST=YES
TP_SB<5>
NO_TEST=YES
TP_SB<4>
NO_TEST=YES
TP_SB<6>
NO_TEST=YES
TP_SB<8>
NO_TEST=YES
TP_SB<7>
NO_TEST=YES
TP_SB<9>
NO_TEST=YES
TP_SB<10>
NO_TEST=YES
TP_SB<13>
NO_TEST=YES
TP_SB<12>
NO_TEST=YES
TP_SB<14>
NO_TEST=YES
TP_SB<15>
NO_TEST=YES
TP_SB<18>
NO_TEST=YES
TP_SB<19>
NO_TEST=YES
TP_SB<21>
NO_TEST=YES
NC_SMU_PWRSEQ_P1_4
NO_TEST=YES
NC_SMU_PWRSEQ_P1_0
NO_TEST=YES
NC_RAM_ARB1_REF25MHZ
NO_TEST=YES
NC_RAM_ARB0_REF25MHZ
NO_TEST=YES
NC_NCV1009_4
NO_TEST=YES
NC_NCV1009_ADJ
NO_TEST=YES
NC_NCV1009_5
NO_TEST=YES
NC_NCV1009_3
NO_TEST=YES
NC_NCV1009_1
NO_TEST=YES
NC_J2904_12
NO_TEST=YES
NC_J2904_11
NC_HT_NB_TO_MB_CLK_P<1>
NO_TEST=YES
NO_TEST=YES
NC_EI_CPU_B_SYSCLK_P
NC_HT_NB_TO_MB_CLK_N<1>
NO_TEST=YES
NO_TEST=YES
NC_EI_CPU_B_SYSCLK_N
NO_TEST=YES
NC_CPU_B_APSYNC
NO_TEST=YES
NC_A_AVREG_2
NO_TEST=YES
NC_A_AVREG_0
NO_TEST=YES
NC_A_AVREG_1
NC_CLK_RAI_PCIEC_P<0>
NO_TEST=YES
NC_CLK_RAI_PCIEC_N<0>
NO_TEST=YES
NO_TEST=YES
NC_CLK_RAI_PCIEB_N<0>
NO_TEST=YES
NC_CLK_RAI_PCIEA_N<0>
NC_CLK_RAI_200M_P<0>
NO_TEST=YES
NO_TEST=YES
NC_HT_NB_TO_MB_CAD_N<8..15>
NC_HT_NB_TO_MB_CAD_P<8..15>
NO_TEST=YES
NC_HT_MB_TO_NB_CAD_P<8..15>
NO_TEST=YES
NC_CPU_B1_QACK_L
NO_TEST=YES
NC_NB_CPU_B0_INT_L
NO_TEST=YES
NO_TEST=YES
NC_EI_CPU_B_TO_NB_SR_P<0..1>
NO_TEST=YES
NC_EI_CPU_B_TO_NB_AD<0..43>
NO_TEST=YES
NC_EI_CPU_B_TO_NB_CLK_N
NO_TEST=YES
NC_EI_CPU_B_TO_NB_CLK_P
NO_TEST=YES
NC_EI_NB_TO_CPU_B_SR_N<0..1>
NO_TEST=YES
NC_EI_NB_TO_CPU_B_SR_P<0..1>
NC_EI_NB_TO_CPU_B_AD<0..43>
NO_TEST=YES
NO_TEST=YES
NC_EI_NB_TO_CPU_B_CLK_N
NO_TEST=YES
NC_EI_NB_TO_CPU_B_CLK_P
NO_TEST=YES
GND_AUDIO_MIC
GND_GPU_MPVSS
NO_TEST=YES
VC_OUTSEN_R
NO_TEST=YES
KPVDD2_FMAX
NO_TEST=YES
GND_GPU_PVSS
NO_TEST=YES
VC_AGND
NO_TEST=YES
NO_TEST=YES
GND_CPU_AVDD
GND_SMU_AVSS
NO_TEST=YES
PP_3V3ALLSMUAVCC
NO_TEST=YES
PP_3V3ALLSMU
NO_TEST=YES
NO_TEST=YES
PP_VEINB
PP_1V5PWRONPULSAR2
NO_TEST=YES
PP_1V5PULSAR2
NO_TEST=YES
PP_1V2PWRONPULSAR1
NO_TEST=YES
PP_2V5PWRONNBMISC
NO_TEST=YES
GND_U1200
NO_TEST=YES
NO_TEST=YES
TP_SB<27>
NO_TEST=YES
TP_SB<29>
NO_TEST=YES
TP_SB<28>
NC_SATA_RXD_N2_C
NO_TEST=YES
NO_TEST=YES
PPV_RUN_CPU_AVDD_R_L
CORE_ISNS_M
NO_TEST=YES
CORE_ISNS_P
NO_TEST=YES
NO_TEST=YES
FMAXT_M
CPU_DIODE_NEG
NO_TEST=YES
FMAXT_P
NO_TEST=YES
NO_TEST=YES
CPU_DIODE_POS
NO_TEST=YES
KPGND2
NO_TEST=YES
KPVDD2
NO_TEST=YES
PP3V3_PWRON_NEC_AVDD
NO_TEST=YES
PP3V3_VESTA_FAVDDH
NO_TEST=YES
PP2V5_VESTA_FAVDDM
NO_TEST=YES
PP1V2_VESTA_FAVDDL
NO_TEST=YES
PP2V5_VESTA_XTALVDD2
NO_TEST=YES
PP2V5_VESTA_BIASVDD2
NO_TEST=YES
PP1V2_VESTA_PLLVDD1
NO_TEST=YES
PP1V2_VESTA_PLLVDD2
NO_TEST=YES
PP2V5_VESTA_XTALVDD1
NO_TEST=YES
PP2V5_VESTA_BIASVDD1
PP_1V2PWRONDISKSB_CC
NO_TEST=YES
PP_VIOPCIUSB2_C2
NO_TEST=YES
NO_TEST=YES
PP_3V3SBPCI_B9
KOD_L15_GND
NO_TEST=YES
GND_GPU_A2VSSQ
NO_TEST=YES
GND_GPU_A2VSSN
NO_TEST=YES
GND_GPU_AVSSQ
NO_TEST=YES
NO_TEST=YES
GND_GPU_AVSSN
NO_TEST=YES
GND_GPU_VSSDI
GND_GPU_TXVSSR
NO_TEST=YES
NO_TEST=YES
U8500_GND
NO_TEST=YES
PCIE_SLOTA_PRSNT_L
NO_TEST=YES
KOD_H08_GND
NO_TEST=YES
KOD_L13_GND
NO_TEST=YES
KOD_J13_GND
NO_TEST=YES
KOD_G10_GND
NO_TEST=YES
KOD_K07_GND
NO_TEST=YES
GND_AUDIO_SPKRAMP
NO_TEST=YES
GND_AUDIO
NO_TEST=YES
RAMCLK_AVSS
NO_TEST=YES
INA138_OUT
NO_TEST=YES
TDIODE_POS_FMAX
KPGND2_FMAX
NO_TEST=YES
GND_AUDIO_SPKRAMP_PLANE
NO_TEST=YES
GND_U1100
NO_TEST=YES
GND_GPU_TPVSS
NO_TEST=YES
GND_NEC_AVSS_R
NO_TEST=YES
RFBD<53>
NO_TEST=YES
RFBD<57>
NO_TEST=YES
RFBD<61>
NO_TEST=YES
RFBD<47>
NO_TEST=YES
RFBD<48>
NO_TEST=YES
RFBD<50>
NO_TEST=YES
RFBD<38>
NO_TEST=YES
RFBD<37>
NO_TEST=YES
RFBD<40>
NO_TEST=YES
RFBD<36>
NO_TEST=YES
RFBD<34>
NO_TEST=YES
RFBD<33>
NO_TEST=YES
RFBD<32>
NO_TEST=YES
NO_TEST=YES
RFBD<19>
NO_TEST=YES
RFBD<18>
RFBD<14>
NO_TEST=YES
RFBD<10>
NO_TEST=YES
NO_TEST=YES
RAM_DQ_R<45>
NO_TEST=YES
RFBD<5>
NO_TEST=YES
NC_CLK_RAI_GIGE_25MHZ
NO_TEST=YES
TP_SB<24>
NO_TEST=YES
RAM_DQ_R<49>
NO_TEST=YES
TP_NEC_SRMOD
NO_TEST=YES
TP_NEC_SRCLK
FUNC_TEST=TRUE
PPVCORE_CPU
=PP3V3_ALL_SMU
FUNC_TEST=TRUE
=PP5V_RUN_CPU
FUNC_TEST=TRUE
SYS_POWER_BUTTON_L
FUNC_TEST=TRUE
SMU_RESET_L
FUNC_TEST=TRUE
RESET_BUTTON_L
FUNC_TEST=TRUE
SYS_POWERUP_L
FUNC_TEST=TRUE
POWER_BUTTON_L
FUNC_TEST=TRUE
SMU_BOOT_SCLK
FUNC_TEST=TRUE
SMU_BOOT_RXD
FUNC_TEST=TRUE
FUNC_TEST=TRUE
SMU_BOOT_CNVSS
FUNC_TEST=TRUE
SMU_BOOT_CE
FUNC_TEST=TRUE
SMU_BOOT_BUSY
FUNC_TEST=TRUE
SMU_BOOT_TXD
FUNC_TEST=TRUE
SMU_MANUAL_RESET_L
RFBD<65>
NO_TEST=YES
RFBD<78>
NO_TEST=YES
RFBD<81>
NO_TEST=YES
RFBD<69>
NO_TEST=YES
RFBD<70>
NO_TEST=YES
RFBD<72>
NO_TEST=YES
RFBD<71>
NO_TEST=YES
RFBD<82>
NO_TEST=YES
RFBD<83>
NO_TEST=YES
RFBD<79>
NO_TEST=YES
RFBD<76>
NO_TEST=YES
RFBD<75>
NO_TEST=YES
RFBD<74>
NO_TEST=YES
RFBD<67>
NO_TEST=YES
RFBD<95>
NO_TEST=YES
RFBD<88>
NO_TEST=YES
RFBD<87>
NO_TEST=YES
RFBD<86>
NO_TEST=YES
RFBD<114>
NO_TEST=YES
RFBD<120>
NO_TEST=YES
NO_TEST=YES
RFBD<117>
RFBD<118>
NO_TEST=YES
RFBD<122>
NO_TEST=YES
NO_TEST=YES
RFBD<98>
RFBD<100>
NO_TEST=YES
RFBD<97>
NO_TEST=YES
RFBD<125>
NO_TEST=YES
RFBD<121>
NO_TEST=YES
RFBD<116>
NO_TEST=YES
RFBD<110>
NO_TEST=YES
RFBD<96>
NO_TEST=YES
RFBD<66>
NO_TEST=YES
RFBD<62>
NO_TEST=YES
NO_TEST=YES
TP_SB<26>
RFBD<113>
NO_TEST=YES
NO_TEST=YES
RAM_DQ_R<48>
NO_TEST=YES
NC_SATA_TXD_P2
NO_TEST=YES
TP_SB<25>
85
154
50
150
69
69
69
69
69
69
69
69
70
70
70
70
70
70
70
69
69
69
70
70
70
70
70
70
69
69
69
69
69
69
69
69
69
69
69
69
70
70
70
70
70
70
70
69
70
55
55
154
70
70
29
28
70
16
148
90
90
90
90
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
90
90
90
90
90
90
90
90
90
90
89
89
89
89
89
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
89
89
68
68
68
68
89
68
68
68
68
97
152
90
154 154
89
89
89
89
89
89
89
89
89
89
89
89
89
89
89
89
89
89
89
89
89
154
55
55
55
50
50
101
84
97
97
97
97
97
152
154
154
89
89
89
89
89
89
89
89
89
89
89
89
89
89
89
89
89
68
89
68
28
8
29
29
12
29
29
29
29
29
29
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
89
90
68
7
7
7
7
7
7
7
7
147
88
88
88
88
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
88
88
88
88
88
88
88
88
88
88
8
8
8
8
26
8
8
8
143
24
122
122
129
88
88
88
88
88
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
88
88
61
61
61
61
88
27
26
27
27
27
101
56
61
61
61
61
129
20
82
55
55
7
119
24
23
13
23
56
56
56
56
88
150 150
23
25
88
8
88
154
142
88
88
55
129
142
142
142
142
142
88
122
143
122
143
143
24
143
7
87
154
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
142
142
142
142
142
142
142
142
142
142
142
142
142
142
142
142
142
142
4
4
27
27
55
55
55
55
55
29
29
101
27
101
27
27
82
82
82
27
27
27
27
27
101
101
101
56
56
56
56
56
56
56
56
56
56
56
153
87
50
55
86
50
48
28
28
28
41
25
25
25
20
12
142
142
142
129
48
55
55
55
48
55
48
48
48
142
139
139
139
139
139
132
139
132
132
127
122
98
93
93
93
93
93
93
85
82
82
82
82
82
82
7
7
62
55
55
55
152
11 93
142
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
61
88
27
142
61
122
122
50
7
7
28
28
29
7
29
28
28
28
28
28
28
29
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
142
88
61
129
142
Preliminary
125
NBC
G
D
S
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
SILKSCREEN:1
CHASSIS GND
GND RAILS
TO MATCH Q63
SILKSCREEN:RUN
ALL RAILS
ON IN RUN AND SLEEP
ALWAYS ON WHEN UNIT HAS AC POWER (TRICKLE)
ONLY ON IN RUN
SILKSCREEN:2
PWRON RAILS
PLANE STICHING CAPS
RUN RAILS
P/N 518-0189
3V3_RUN LEAKAGE FIX
PP5V_RUN
PP3V3_PWRON
PP1V5_PWRON
PP2V5_PWRON
PP1V2_PWRON
PP5V_ALL
PP5V_ALL
PP3V3_RUN
PP2V5_RUN
PP5V_PWRON
PP1V5_RUN
PP3V3_RUN
PP5V_RUN
SM
21
XW701
SM
21
XW702
SM
21
XW703
PP12V_RUN
PP1V2_RUN
74LC125
TSSOP
CRITICAL
3
14
17
2
U700
20%
402
10V
CERM
0.1UF
2
1
C700
DEVELOPMENT
GREEN-3.6MCD
2.0X1.25MM-SM
2
1
LED701
2.0X1.25MM-SM
GREEN-3.6MCD
2
1
LED702
PP3V3_PWRON
820
603
MF-LF
5%
1/10W
21
R700
2.0X1.25MM-SM
GREEN-3.6MCD
2
1
LED700
SM
21
XW705
SM
21
XW706
SM
21
XW707
PP12V_RUN
PP3V3_RUN
HM9606E-P2
M-RT-TH
CRITICAL
9
87
65
43
2
1211
10
1
J700
PP3V3_ALL PP12V_ALL
PP1V8_PWRON
4P25R3P5
OMIT
1
ZH701
4P25R3P5
OMIT
1
ZH702
4P25R3P5
OMIT
1
ZH703
NOSTUFF
20%
0.01UF
CERM
16V
402
2
1
C701
NOSTUFF
0.01UF
20%
16V
CERM
402
2
1
C702
16V
NOSTUFF
0.01UF
20%
CERM
402
2
1
C703
PP1V8_RUN
PP3V3_ALL
PP1V2_ALL
PP2V5_ALL
PP12V_ALL
402
MF-LF
1/16W
5%
10K
2
1
R702
PP3V3_ALL
1.5K
1/10W
MF-LF
603
5%
21
R710
PP3V3_ALL
NOSTUFF
0
5%
1/16W
402
MF-LF
21
R721
4P25R3P5
OMIT
1
ZH704
NOSTUFF
0.01UF
20%
16V
CERM
402
2
1
C704
NOSTUFF
5%
MF-LF
402
1/16W
0
21
R711
160R138
OMIT
1
ZH706
SM
21
XW700
0.01UF
20%
402
CERM
16V
2
1
C750
PP1V8_RUN PP3V3_RUN
CERM
16V
20%
0.01UF
402
2
1
C751
PP1V2_PWRON
PP1V8_RUN
CERM
16V
20%
0.01UF
402
2
1
C752
0.01UF
20%
16V
CERM
402
2
1
C755
0.01UF
20%
16V
CERM
402
2
1
C756
20%
16V
CERM
402
0.01UF
2
1
C753
0.01UF
20%
16V
CERM
402
2
1
C759
PP12V_ALL
402
CERM
16V
20%
0.01UF
2
1
C764
PP3V3_RUN
PP12V_ALL
402
CERM
20%
0.01UF
16V
2
1
C767
PP1V8_RUN
SM
21
XW708
ELEC
20%
330UF
6.3V
6.3X8-SM
2
1
C722
SOT23-LF
2N7002
2
1
3
Q790
805
1/8W
MF-LF
5%
33
2
1
R790
PP3V3_RUN
DEVELOPMENT
1/10W
330
5%
MF-LF
603
21
R701
PP5V_ALL
Power Conn / Alias
051-6790
154
7
19
SYNC_DATE=06/20/2005
SYNC_MASTER=M23-PC
NET_SPACING_TYPE=POWER
MIN_LINE_WIDTH=0.6MM
MAKE_BASE=TRUE
VOLTAGE=2.5V
MIN_NECK_WIDTH=0.2MM
PP2V5_ALL
SYS_POWERUP_L_BUF
=PP1V8_RUN_RAM
=PPV_GPU_MEM
=PPVIO_PCI_USB2
=PP5V_RUN_CPU
Q790D
=PPV_PWRON_NB_REFCLK
SYS_POWERUP_L_BUF
SYS_POWERFAIL_L
PP5V_AUDIO_ANALOG
PP12V_AUDIO_SPKRAMP
=PP1V5_PULSAR
MIN_LINE_WIDTH=0.5MM
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.25MM
VOLTAGE=1.5V
PP1V5_PWRON_PULSAR
=PP1V2_PWRON_PULSAR
=PP1V5_PWRON_PULSAR
GND_CHASSIS_RJ45
GND_CHASSIS_USB
SYS_POWERUP_L
ITS_RUNNING
=PP12V_GPU
=PP1V2_PWRON_DISK_SB
=PP1V2_PWRON_HT_NBTX
=PP1V2_PWRON_SB
=PP1V2_PWRON_SB_HT
=PP1V2_PWRON_SB_VCORE
GND_CHASSIS_AUDIO_INTERNAL
=PP12V_ALL_FW
=PP1V5_PWRON_PULSAR
=PP3V3_PWRON_BT
=PP3V3_PWRON_CPU
=PP3V3_PWRON_PULSAR
=PP3V3_PWRON_SB
=PP3V3_PWRON_SB_PCI32
=PP3V3_PWRON_SB_PCI64
=PP3V3_PWRON_SMU
=PP12V_CPU
ZH701P1
ZH703P1
ZH702P1
=PP1V2_VESTA
=PP12V_ALL_GPU
=PP1V2_ENETFW
=PP5V_ALL_GPU
=PP3V3_ALL_CPU
=PP3V3_ALL_SMU
=PP2V5_ENETFW
ITS_PLUGGED_IN
=PP2V5_PWRON_PULSAR
=PP2V5_PWRON_SB
=PPV_EI_CPU
=PP3V3_ENETFW
=PP2V5_PWRON_NB_PCIE
=PP2V5_PWRON_HT
GND_AUDIO_SPKRAMP
=PP2V5_PWRON_NB_MISC
=PPVCORE_PWRON_NB_HT
=PPV_EI_NB
=PP3V3_PWRON_USB
=PPVCORE_PWRON_NB_PCIE
=PPVCORE_PWRON_NB
NET_SPACING_TYPE=POWER
GND_CHASSIS_IO_LEFT
MIN_NECK_WIDTH=0.2MM
MAKE_BASE=TRUE
VOLTAGE=0
MIN_LINE_WIDTH=0.6MM
PPVCORE_GPU
NET_SPACING_TYPE=POWER
MIN_NECK_WIDTH=0.25MM
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6MM
=PP1V2_GPU_PCIE
=PP3V3_RUN_SB_PCI
=PP3V3_RUN_PULSAR
=PP5V_PWRON_USB
=PP5V_PWRON_BNDI
PPVCORE_GPU
=PP3V3_PWRON_BNDI
=PP3V3_ENET
=PP1V8_PWRON_NBMEM
=PP1V8_PWRON_RAM
=PP1V8_PWRON_DIMM
=PP3V3_RUN_I2C
PP3V3_RUN_SB
=PP3V3_RUN_SMU
=PP2V5_RUN_I2C
=PP3V3_SB_PCI
=PP3V3_PCI
=PP3V3_PATA
=PP3V3_RUN_CPU
=PP3V3_AUDIO
=PP3V3_GPU
=PP5V_PATA
PPVCORE_GPU
ITS_ALIVE
=PP3V3_FW
=PP3V3_ALL_GPU
GND_AUDIO
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=POWER
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6MM
VOLTAGE=0
GND_CHASSIS_IO_RIGHT
GND_CHASSIS_VGA
GND_CHASSIS_FIREWIRE
ZH704P1
=PP1V8_PWRON_RAM_I2C_VDD
=PPOVDD_PULSAR
=PP2V5_ENET
=PP2V5_PWRON_NB_HT
GND_CHASSIS_AUDIO_EXTERNAL
GND_CHASSIS_BNDI
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
NET_SPACING_TYPE=POWER
MAKE_BASE=TRUE
VOLTAGE=0
NET_SPACING_TYPE=POWER
NET_SPACING_TYPE=POWER
NET_SPACING_TYPE=POWER
VOLTAGE=3.3V
NET_SPACING_TYPE=POWER
NET_SPACING_TYPE=POWER
NET_SPACING_TYPE=POWER
VOLTAGE=3.3V
NET_SPACING_TYPE=POWER
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=POWER
MIN_NECK_WIDTH=0.2MM
VOLTAGE=5V
MIN_LINE_WIDTH=0.6MM
PP5V_ALL
MAKE_BASE=TRUE
PP12V_ALL
MAKE_BASE=TRUE
VOLTAGE=12V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=POWER
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
VOLTAGE=1.2V
MAKE_BASE=TRUE
PP1V2_ALL
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
MAKE_BASE=TRUE
PP3V3_ALL
VOLTAGE=3.3V
PP1V8_RUN
MAKE_BASE=TRUE
NET_SPACING_TYPE=POWER
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
VOLTAGE=1.8V
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=2.5V
PP1V8_PWRON
NET_SPACING_TYPE=POWER
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM
PP3V3_RUN
VOLTAGE=12V
PP12V_RUN
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=POWER
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6MM
PP1V2_RUN
NET_SPACING_TYPE=POWER
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6MM
VOLTAGE=1.2V
MIN_NECK_WIDTH=0.2MM
PP1V5_RUN
NET_SPACING_TYPE=POWER
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
MAKE_BASE=TRUE
VOLTAGE=1.5V
MIN_NECK_WIDTH=0.25MM
VOLTAGE=5V
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6MM
PP5V_PWRON
VOLTAGE=2.5V
PP2V5_RUN
MIN_LINE_WIDTH=0.6MM
MAKE_BASE=TRUE
NET_SPACING_TYPE=POWER
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
MAKE_BASE=TRUE
VOLTAGE=1.2V
PP1V2_PWRON
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6MM
VOLTAGE=2.5V
MIN_NECK_WIDTH=0.2MM
PP2V5_PWRON
NET_SPACING_TYPE=POWER
PP1V5_PWRON
NET_SPACING_TYPE=POWER
MIN_NECK_WIDTH=0.2MM
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6MM
VOLTAGE=1.5V
MIN_NECK_WIDTH=0.2MM
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6MM
PP3V3_PWRON
VOLTAGE=5V
PP5V_RUN
NET_SPACING_TYPE=POWER
VOLTAGE=0V
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
85
119
56
50
56
138
48
39
59
154
96
90
154
28
24
43
139
29
139
119
47
139
154
30
56
145
86
86
58
70
30
153
93
86
16
62
89
8
59
16
153
152
25
12
25
23
30
55
132
28
132
24
30
132
103
152
28
42
144
85
85
136
39
69
28
125
55
152
92
85
154
154
16
7
61
87
122
6
42
7
28
150
6
25
12
25
7
136
143
6
6
96
127
98
24
103
23
153
140
7
121
55
25
20
23
23
28
50
85
17
85
55
6
17
25
23
29
17
82
98
6
20
98
41
142
82
19
7
84
24
25
143
143
7
132
20
62
67
39
119
20
39
121
129
54
147
85
129
7
140
85
6
96
140
67
25
136
98
153
143
6
6
6
6
6
6
62
6
6
Preliminary
G
D
S
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
CPU HEATSINK MOUNTING HOLES
SCC_GPIO_L
SCC_TRXC
SCC_TXD_L
SCC_RTS_L
SCC_DTR_L
CHKSTOP LED
PLL LOCK LED
DIAG LED
(OVERTEMP LED)
SCC_RXD
SERIAL DEBUG
OMIT
4P75R4
1
ZH800
OMIT
4P75R4
1
ZH801
OMIT
4P75R4
1
ZH803
OMIT
4P75R4
1
ZH802
402
0.01UF
20%
16V
CERM
2
1
C880
402
0.01UF
20%
16V
CERM
2
1
C881
402
0.01UF
20%
CERM
16V
2
1
C882
402
0.01UF
20%
16V
CERM
2
1
C883
DEVELOPMENT
2N7002
SOT23-LF
Q800_D
2
1
3
Q800
2N3904LF
SOT23
DEVELOPMENT
Q801_B
2
3
1
Q801
SOT23-LF
DEVELOPMENT
2N3906
2
3
1
Q802
1K
MF-LF
1/16W
DEVELOPMENT
402
5%
2
1
R835
GREEN-3.6MCD
2.0X1.25MM-SM
DEVELOPMENT
2
1
LED802
180
MF-LF
402
5%
DEVELOPMENT
1/16W
2
1
R837
1/16W
MF-LF
DEVELOPMENT
1K
402
5%
2
1
R838
2N3904LF
SOT23
DEVELOPMENT
2
3
1
Q803
180
1/16W
MF-LF
402
5%
DEVELOPMENT
21
R839
SOT23
2N3904LF
2
3
1
Q850
5%
402
1/16W
1K
MF-LF
21
R851
PP5V_ALL
402
2.0K
MF-LF
1/16W
5%
2
1
R850
DEVELOPMENT
M-ST-5087
SM-LF
9
8
7
65
4
3
2
10
1
J800
PP5V_PWRON
MF-LF
1/16W
5%
180
DEVELOPMENT
402
2
1
R833
402
4.7K
5%
1/16W
MF-LF
DEVELOPMENT
2
1
R834
1/16W
5%
MF-LF
10K
402
DEVELOPMENT
21
R836
RED-4.0MCD
2X1.25MM-SM
2
1
LED850
RED-4.0MCD
DEVELOPMENT
2X1.25MM-SM
2
1
LED801
SYNC_DATE=06/20/2005
SYNC_MASTER=FINO-DD
Signal Alias
19
8
154
051-6790
I2S1_DEV_TO_SB_DTI
I2S1_SYNC
CPU_CHKSTOP_L
Q803_B
LED801_1
=PP5V_RUN_CPU
Q802_B
=PP5V_RUN_CPU
Q800_G
LED802_1
Q803_C
I2S1_RESET_L
I2S1_MCLK
I2S1_BITCLK
I2S1_SB_TO_DEV_DTO
HS_SDF800
DIAG_LED
MAKE_BASE=TRUE
DIAG_LED_R
PLLLOCK
Q802_E
HS_SDF801 HS_SDF802 HS_SDF803
LED850P2
LED850P1
8
8
56
7
7
43
6
6
24 24
43
6
6
6
6
6
6
6
9
24
24 24
24
28
9
6
33
Preliminary
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
JTAG TEST POINTS NEED TO BE ON THE BOTTOM
THE FOLLOWING NETS ARE USED ONLY
TEST POINT BECAUSE OF ROUTING DENSITY
TEST COVERAGE WILL BE BY FCT
AND SIGNAL INTEGRITY.
THE FOLLOWING NETS DO NOT HAVE
WHEN THE DEVELOPMENT BOM OPTION IS ENABLED
NOTE FOR SHARING: DO NOT INCLUDE THIS LIST UNTIL
LAYOUT HAVING DIFFICULTY PLACING TEST POINTS ON THESE NETS
OF THE BOARD
ADDING FUNC_TEST=TRUE TO THESE NETS
PCB LAYOUT ADDS TEST POINTS. THIS LIST IS A RESULT OF PCB
ADDING NO_TEST TO ALL PCIE NETS
TO AVOID STUBS
WILL GET COVERAGE IN FCT WITH A DIAG
THAT CHECKS THAT THE BUS IS 16 LANES WIDE
THE FOLLOWING PULSAR NETS WILL BE
TESTED VIA TEST JET
I1
I10
I100
I101
I102
I103
I106
I109
I11
I114
I115
I116
I117
I118
I119
I12
I120
I121
I122
I123
I124
I125
I126
I127
I128
I129
I13
I130
I131
I132
I133
I134
I135
I136
I137
I138
I139
I14
I140
I141
I142
I143
I144
I145
I146
I147
I148
I149
I15
I150
I151
I152
I153
I154
I155
I156
I157
I158
I159
I16
I160
I161
I162
I163
I164
I165
I166
I167
I168
I169
I17
I170
I171
I172
I173
I174
I175
I176
I177
I178
I179
I18
I180
I181
I182
I183
I184
I185
I186
I187
I188
I189
I19
I191
I192
I193
I194
I195
I196
I197
I198
I199
I2
I20
I200
I201
I202
I203
I204
I205
I206
I207
I208
I209
I21
I210
I211
I212
I213
I214
I215
I216
I217
I218
I219
I22
I220
I221
I222
I223
I224
I225
I226
I227
I228
I229
I23
I230
I232
I233
I234
I235
I236
I238
I239
I24
I240
I241
I242
I244
I245
I246
I247
I248
I249
I25
I250
I251
I252
I253
I254
I255
I256
I257
I258
I259
I26
I260
I261
I262
I263
I264
I265
I266
I267
I27
I28
I29
I3
I30
I31
I32
I33
I34
I35
I36
I37
I38
I39
I4
I40
I41
I42
I43
I44
I45
I46
I47
I48
I49
I5
I50
I51
I52
I53
I54
I55
I56
I57
I58
I59
I6
I60
I61
I62
I63
I64
I65
I66
I67
I68
I69
I7
I70
I71
I72
I73
I74
I75
I76
I77
I78
I79
I8
I80
I81
I82
I83
I84
I85
I86
I87
I88
I89
I9
I90
I91
I92
I93
I94
I95
I96
I97
I98
I99
FUNC TEST 2 OF 2
19
SYNC_MASTER=FINO-ME
SYNC_DATE=06/20/2005
051-6790
9
154
NO_TEST=YES
NB_PMR_CLK_N_R
NO_TEST=YES
NB_PCIE_REFCLK_P_C
NO_TEST=YES
EI_NB_TO_CPU_SR_P<0>
NO_TEST=YES
EI_NB_TO_CPU_SR_N<0>
NO_TEST=YES
PCIE_B_REFCLKIN_P_C
NO_TEST=YES
PCIE_B_REFCLKIN_N_C
GFX_SLOT_PCIE_REFCLK_N_C
NO_TEST=YES
NO_TEST=YES
GFX_SLOT_PCIE_REFCLK_P_C
PLLTESTOUT
NO_TEST=YES
RFBD<51>
NO_TEST=YES
SB_AIRPRT_CLK_33MHZ_R
NO_TEST=YES
CLK_RAI_REFCLK_66M_R
NO_TEST=YES
NO_TEST=YES
PCIE_C_REFCLKIN_P_C
CLK_RAIREF_200M_N_R
NO_TEST=YES
NB_PMR_CLK_P_R
NO_TEST=YES
CPU_A_TBEN_CLK_R
NO_TEST=YES
CPU_A_APSYNC_R
NO_TEST=YES
EI_CPU_TO_NB_SR_P<1>
NO_TEST=YES
EI_NB_TO_CPU_SR_N<0>
NO_TEST=YES
CPU_B_TBEN_CLK_R
NO_TEST=YES
CPU_B_APSYNC_R
NO_TEST=YES
EI_CPU_TO_NB_SR_N<1>
NO_TEST=YES
EI_NB_TO_CPU_CLK_P
NO_TEST=YES
NO_TEST=YES
PCI_CLK33M_SB_EXT_R
NO_TEST=YES
SB_CLK25M_SATA_R
PCIE_SLOTA_TO_NB_P<0..15>
NO_TEST=YES
PCIE_SLOTA_TO_NB_N<0..15>
NO_TEST=YES
PCIE_SLOTA_TO_NB_PF<0..15>
NO_TEST=YES
PCIE_SLOTA_TO_NB_NF<0..15>
NO_TEST=YES
PCIE_NB_TO_SLOTA_P<0..15>
NO_TEST=YES
PCIE_NB_TO_SLOTA_N<0..15>
NO_TEST=YES
NO_TEST=YES
PCIE_NB_TO_SLOTA_PF<0..15>
NO_TEST=YES
PCIE_NB_TO_SLOTA_NF<0..15>
CLK_KOD_100M_PF<0>
NO_TEST=YES
HT_NB_TO_SB_CTL_N<0>
NO_TEST=YES
HT_NB_TO_MB_CTL_P<1>
NO_TEST=YES
HT_NB_TO_MB_CTL_N<1>
NO_TEST=YES
HT_MB_TO_NB_CTL_N<1>
NO_TEST=YES
UATA_DD<1>
NO_TEST=YES
UATA_DA<0>
NO_TEST=YES
UATA_DD<14>
NO_TEST=YES
NO_TEST=YES
CPU_SENSE_KP_V
LED_PP1V5_RUN_N
NO_TEST=YES
LED_PP1V5_RUN_P
NO_TEST=YES
PULSAR_1V5_RUN_SWITCH
NO_TEST=YES
PP1V2_RUN_FOR_LED
NO_TEST=YES
LED_PP1V2_RUN_N
NO_TEST=YES
T555_DISC
NO_TEST=YES
NO_TEST=YES
TSENSE_GPU_OVERTEMP_L
NB_APSYNC_R
NO_TEST=YES
CLK_RAIREF_200M_P_R
NO_TEST=YES
NB_PCIE_REFCLK_N_C
NO_TEST=YES
NO_TEST=YES
NC_PSRO_ENABLE
NC_CPU_AFN
NO_TEST=YES
NO_TEST=YES
PCIE_A_REFCLKIN_N_C
CLK_RAI_GIGE_25MHZ_R
NO_TEST=YES
PCIE_NB_TO_SLOTA_PF<10>
NO_TEST=YES
NO_TEST=YES
HT_NB_REFCLK_PF<0>
PLLLOCK
NO_TEST=YES
PP5V_T555
NO_TEST=YES
T555_THRES
NO_TEST=YES
ENET_TXD<5>
NO_TEST=YES
NO_TEST=YES
ENET_TXD_R<4>
HT_MB_TO_NB_CTL_P<1>
NO_TEST=YES
FUNC_TEST=TRUE
JTAG_CPU_TMS
FUNC_TEST=TRUE
JTAG_CPU_TRST_L
FUNC_TEST=TRUE
JTAG_CPU_TDO
FUNC_TEST=TRUE
JTAG_CPU_TDI
FUNC_TEST=TRUE
JTAG_CPU_TCK
FUNC_TEST=TRUE
TP_JTAG_SB_TDI
TP_JTAG_SB_TDO
FUNC_TEST=TRUE
TP_JTAG_SB_TMS
FUNC_TEST=TRUE
JTAG_NB_TDO
FUNC_TEST=TRUE
TP_JTAG_VESTA_TMS
FUNC_TEST=TRUE
TP_JTAG_VESTA_TRST_L
FUNC_TEST=TRUE
JTAG_NB_TDI
FUNC_TEST=TRUE
JTAG_NB_TRST_L
FUNC_TEST=TRUE
TP_VESTA_FAVDDL
NO_TEST=YES
NO_TEST=YES
TP_VESTA_TEST<1>
NO_TEST=YES
TP_VESTA_TDBL<2>
NO_TEST=YES
TP_VESTA_TDBL<1>
NO_TEST=YES
TP_VESTA_TEST<0>
NO_TEST=YES
TP_VESTA_TVCO
CARD_READER_ACTIVITY_R
NO_TEST=YES
TP_NB_A_TRIGGER_OUT
NO_TEST=YES
TP_NB_B_TRIGGER_OUT
NO_TEST=YES
NO_TEST=YES
TP_VESTA_TEST_1394<0>
NO_TEST=YES
TP_VESTA_TEST_1394<1>
NO_TEST=YES
HT_NB_TO_SB_CAD_N<0..7>
NO_TEST=YES
PCIE_NB_TO_SLOTA_NF<13>
PCIE_NB_TO_SLOTA_NF<7>
NO_TEST=YES
NO_TEST=YES
PCIE_SLOTA_TO_NB_N<0..15>
NO_TEST=YES
HT_NB_N<0>
NO_TEST=YES
CKA_N<0>
NO_TEST=YES
HT_SB_TO_NB_CLK_N<0>
T555_OUT
NO_TEST=YES
T555_PWM
NO_TEST=YES
PP3V3_GPU_TSENSE
NO_TEST=YES
NO_TEST=YES
LED8701_P
GPU_DIODE_MINUS
NO_TEST=YES
NB_PLL_OUT_TRG
NO_TEST=YES NO_TEST=YES
PCIE_NB_TO_SLOTA_N<0>
NO_TEST=YES
PCIE_NB_TO_SLOTA_N<3>
NO_TEST=YES
PCIE_NB_TO_SLOTA_P<1>
PCIE_NB_TO_SLOTA_P<10>
NO_TEST=YES
PCIE_NB_TO_SLOTA_PF<13>
NO_TEST=YES
KP_V<2>
NO_TEST=YES
KP_V<1>
NO_TEST=YES
NO_TEST=YES
LED_PP1V2_RUN_P
PCIE_NB_TO_SLOTA_PF<14>
NO_TEST=YES
NO_TEST=YES
HT_SB_TO_NB_CLK_P<0>
PCIE_NB_TO_SLOTA_NF<12>
NO_TEST=YES
PCIE_NB_TO_SLOTA_PF<4>
NO_TEST=YES
HT_SB_TO_NB_CTL_P<0>
NO_TEST=YES
CLK_KOD_100M_NF<0>
NO_TEST=YES
EI_CPU_TO_NB_CLK_N
NO_TEST=YES
EI_CPU_TO_NB_CLK_P
NO_TEST=YES
EI_NB_TO_CPU_CLK_N
NO_TEST=YES
HT_SB_TO_NB_CAD_P<0..7>
NO_TEST=YES
HT_SB_TO_NB_CAD_N<0..7>
NO_TEST=YES
NO_TEST=YES
HT_NB_TO_SB_CLK_N<0>
NO_TEST=YES
HT_NB_TO_SB_CLK_P<0>
NO_TEST=YES
HT_NB_TO_SB_CAD_P<0..7>
NO_TEST=YES
HT_NB_REFCLK_NF<0>
NO_TEST=YES
HT_NB_P<0>
NO_TEST=YES
CKA_P<0>
NO_TEST=YES
100M_N<0>
NO_TEST=YES
Q803_C
TP_I2S2_SB_TO_DEV_DTO
NO_TEST=YES
TP_NB_APSYNC
NO_TEST=YES
TP_SB_WATCHDOG
NO_TEST=YES
NC_CPU_TBEN_CLK
NO_TEST=YES
NO_TEST=YES
NC_J3108_12
NO_TEST=YES
NC_J3108_8
NO_TEST=YES
NC_JTAGMUX_3
NC_PP1V5_PULSAR
NO_TEST=YES
ENET_TXD<0>
NO_TEST=YES
SB_USB2_CLK_33MHZ_R
NO_TEST=YES
NO_TEST=YES
PCIE_A_REFCLKIN_P_C
NO_TEST=YES
PCIE_C_REFCLKIN_N_C
NO_TEST=YES
NB_DDR_REFCLK_P_R
NO_TEST=YES
NB_DDR_REFCLK_N_R
QUA1_REF_25MHZ_R
NO_TEST=YES
GPU_DIODE_PLUS
NO_TEST=YES
TSENSE_GPU_ADD1
NO_TEST=YES
NO_TEST=YES
ENET_RXD_R<7>
NO_TEST=YES
NC_J3108_9
LED_PP1V8_RUN_P
NO_TEST=YES
NO_TEST=YES
ENET_RXD_R<1>
NO_TEST=YES
TP_VESTA_TDBL<0>
TP_VESTA_REGSUP1
NO_TEST=YES
NO_TEST=YES
TP_VESTA_PHYA<2>
TP_VESTA_F1000
NO_TEST=YES
NO_TEST=YES
TP_VESTA_PHYA<3>
NO_TEST=YES
TP_VESTA_REGCTL2
TP_VESTA_RBC1
NO_TEST=YES
TP_VESTA_RBC0
NO_TEST=YES
NO_TEST=YES
TP_VESTA_PHYA<1>
TP_VESTA_REGSEN1
NO_TEST=YES
NO_TEST=YES
TP_VESTA_PHYA<0>
NC_SMU_CPU_VID_LE0
NO_TEST=YES
NO_TEST=YES
ENET_RXD_R<6>
NO_TEST=YES
ENET_TXD<1>
TP_VESTA_ER
NO_TEST=YES
NC_SMU_FAN_TACH5
NO_TEST=YES
TP_VESTA_AN_EN
NO_TEST=YES
TP_VESTA_FDX
NO_TEST=YES
TP_VESTA_EN_10B
NO_TEST=YES
TP_VESTA_DNC_E9
NO_TEST=YES
TP_VESTA_DNC_C9
NO_TEST=YES
TP_VESTA_2_5V_EN
NO_TEST=YES
TP_VESTA_LINK1_L
NO_TEST=YES
TP_VESTA_HUB
NO_TEST=YES
TP_VESTA_FDXLED_L
NO_TEST=YES
TP_VESTA_MANMS
NO_TEST=YES
NO_TEST=YES
TP_VESTA_REGSEN2
TP_VESTA_REGCTL1
NO_TEST=YES
TP_VESTA_RGMIIEN
NO_TEST=YES
TP_VESTA_REGSUP2
NO_TEST=YES
TP_VESTA_SPD0
NO_TEST=YES
NO_TEST=YES
TP_VESTA_PHYA<4>
ENET_TX_ER
NO_TEST=YES
NO_TEST=YES
ENET_TX_EN_R
NC_SMU_FAN_TACH4
NO_TEST=YES
NC_SMU_FAN_RPM5
NO_TEST=YES
TP_HT_MB_TO_NB_CLK_N<1>
NO_TEST=YES
NC_SLOT_TOTAL_PWR
NO_TEST=YES
NO_TEST=YES
ENET_TXD_R<5>
NO_TEST=YES
ENET_TXD<7>
NO_TEST=YES
ENET_TXD_R<0>
NO_TEST=YES
ENET_TXD_R<1>
NO_TEST=YES
ENET_TXD<2>
NO_TEST=YES
ENET_RXD_R<0>
NO_TEST=YES
ENET_RXD<6>
NO_TEST=YES
ENET_RXD<7>
ENET_TX_ER_R
NO_TEST=YES
NO_TEST=YES
ENET_RXD<1>
NO_TEST=YES
NC_PSRO
NO_TEST=YES
NC_I2C_SMU_CPU_SCL_IN
TP_HT_MB_TO_NB_CLK_P<1>
NO_TEST=YES
NC_SMU_FAN_RPM4
NO_TEST=YES
NC_SMU_FAN_RPM3
NO_TEST=YES
NC_SMU_CPU_VID_LE1
NO_TEST=YES
NC_SYS_DOOR_AJAR_L
NO_TEST=YES
NO_TEST=YES
NC_SMU_SER_SEL
NO_TEST=YES
NC_SMU_FAN_TACH7
NC_SMU_FAN_TACH3
NO_TEST=YES
NO_TEST=YES
ENET_TXD<3>
NO_TEST=YES
ENET_RXD_R<5>
NO_TEST=YES
ENET_TXD_R<2>
NO_TEST=YES
ENET_TXD_R<3>
NO_TEST=YES
ENET_TXD_R<6>
NO_TEST=YES
ENET_TXD_R<7>
NC_J3108_10
NO_TEST=YES
NC_J3108_11
NO_TEST=YES
LED_PP1V8_RUN_N
NO_TEST=YESNO_TEST=YES
ENET_TXD<4>
TP_VESTA_LINK2_L
NO_TEST=YES
LED8700_P
NO_TEST=YES
ENET_TXD<6>
NO_TEST=YES
TSENSE_GPU_ADD0
NO_TEST=YES
NO_TEST=YES
ENET_RXD<3>
QUA0_REF_25MHZ_R
NO_TEST=YES
NO_TEST=YES
TP_VESTA_TVCO_24
NO_TEST=YES
TP_VESTA_TXC_RXC_DELAY
ENET_RXD_R<2>
NO_TEST=YES
NO_TEST=YES
ENET_RXD_R<3>
PP1V5_RUN_FOR_LED
NO_TEST=YES
NO_TEST=YES
100M_P<0>
NO_TEST=YES
ENET_RXD_R<4>
NO_TEST=YES
ENET_RXD<2>
NO_TEST=YES
ENET_RXD<0>
ENET_TX_EN
NO_TEST=YES
NB_PLL_OUT_TRG_R
NO_TEST=YES
PCIE_SLOTA_TO_NB_P<0..15>
NO_TEST=YES
FUNC_TEST=TRUE
JTAG_SB_TRST_L
FUNC_TEST=TRUE
TP_JTAG_SB_TCK
FUNC_TEST=TRUE
JTAG_NB_TCK
JTAG_NB_TMS
FUNC_TEST=TRUE
TP_JTAG_VESTA_TCK
FUNC_TEST=TRUE
TP_JTAG_VESTA_TDI
FUNC_TEST=TRUE
TP_JTAG_VESTA_TDO
FUNC_TEST=TRUE
NO_TEST=YES
ENET_RXD<4>
NO_TEST=YES
ENET_RXD<5>
HT_NB_REFCLK_H0_R
NO_TEST=YES
HT_SB_REFCLK_R
NO_TEST=YES
HT_NB_REFCLK_L0_R
NO_TEST=YES
NO_TEST=YES
EI_CPU_TO_NB_SR_P<1>
NO_TEST=YES
EI_CPU_TO_NB_SR_N<1>
NO_TEST=YES
EI_CPU_SYSCLK_P
UATA_DD<12>
NO_TEST=YES
TP_CPU_TRIGGER_OUT
NO_TEST=YES
CPU_SPARE2
NO_TEST=YES
NO_TEST=YES
UATA_DD<13>
EI_NB_TO_CPU_SR_P<0>
NO_TEST=YES
97
97
97
97
97
97
97
97
97
97
56
56
56
56
56
84
84
84
84
97
97
97
132
47
97
97
84
84
84
84
84
97
97
97
97
132
132
132
132
132
132
132
132
132
132
132
132
132
132
132
132
132
84
56
56
56
43
43
47
89
43
43
43
56
82
82
97
97
82
82
82
82
97
129
129
129
82
101
43
131
131
43
47
43
43
43
30
30
82
82
82
101
97
82
82
82
82
82
82
82
82
97
56
56
56
101
101
97
97
131
131
131
131
131
131
131
131
131
131
131
131
131
131
131
131
131
131
131
131
131
131
131
131
131
131
131
131
97
131
131
131
131
82
24
30
30
131
131
43
43
56
129
47
129
43
26
26
9
9
26
26
26
26
43
88
26
26
26
26
26
26
26
9
9
26
26
9
43
26
26
9
9
84
84
9
9
9
9
82
101
98
98
98
127
127
127
55
12
12
12
13
13
93
26
26
26
56
56
26
26
9
98
8
130
130
98
30
43
30
30
30
20
20
20
20
17
17
20
20
139
132
139
139
132
132
144
56
56
139
139
101
9
9
9
98
84
101
93
136
93
59
9
9
9
9
9
55
55
13
9
101
9
9
101
82
43
43
43
101
101
101
101
101
98
98
84
82
8
154
44
24
31
31
30
12
130
26
26
26
26
26
26
93
93
130
31 11
130
139
17
132
132
132
17
132
132
132
17
132
31
130
130
132
31
132
132
132
17
17
17
132
132
132
132
17
17
132
17
132
132
130
130
31
31
101
31
130
130
130
130
130
130
130
130
130
130
56
31
101
31
31
31
31
31
31
31
130
130
130
130
130
130
31
31
11
130
132
136
130
93
130
26
139
132
130
130
12
82
130
130
130
130
9
20
20
20
20
17
17
17
130
130
26
26
26
9
9
43
127
56
43
127
9
Preliminary
FB
LD
HD
GND
COMP
SS
VCC
VC
G
D
S
G
D
S
G
D
S
LM339A
V+
GND
G
D
S
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
4.5A CONTINUOUS
IRU3037ACS VREF=0.8VDC
SET OUTPUT=1.85V FOR FRAMEBUFFER.
VOUT=VREF*(R903+R905)/R905=1.85VDC
POWER BUDGET CURRENT OF TOTAL RAILS
PLACE LED NEAR VREG
9.8A PEAK
POWER BUDGET CURRENT OF FET
7.4A PEAK
NOTE:
6.7A CONTINUOUS
U900_FEEDBACK
HIGH TO ENABLE
1.8V VOLTAGE REGULATOR
MF-LF
805
1/8W
5%
0
21
R1102
MF-LF
1/16W
1%
402
9.31K
2
1
R1105
1206
1/4W
MF-LF
1%
5.11
2
1
R1104
PP5V_ALL
1UF
CERM
402
6.3V
10%
2
1
C1104
PP12V_ALL
SOD-123
MBR0520LXXG
2 1
D1100
MBR0520LXXG
SOD-123
2 1
D1101
SOD-123
MBR0520LXXG
2
1
D1102
25V
805
1UF
20%
CERM
2
1
C1117
0.0018UF
10%
402
CERM
50V
2
1
C1105
CERM
805
25V
20%
1UF
2
1
C1116
PP1V8_PWRON
PP1V8_RUN
25V
402
5%
CERM
220PF
2
1
C1106
CRITICAL
1.53UH
TH-LF
21
L1101
IRU3037ACS
CRITICAL
SOI-LF
2 6
8
3
5
4
1
7
U1100
MF-LF
12.4K
402
1%
1/16W
2
1
R1103
25V
0.1UF
20%
CERM
603
2
1
C1115
1/16W
402
1%
MF-LF
9.31K
2
1
R1101
50V
5%
CERM
805
100PF
2
1
C1113
CERM
NOSTUFF
603
3300PF
10%
50V
2
1
C1107
6800PF
CERM
603
50V
10%
2
1
C1114
4.7
805
1/8W
MF-LF
5%
2
1
R1100
SO-8
IRF7413PBF
321
4
8765
Q1103
PP12V_RUN
2N7002
SOT23-LF
2
1
3
Q1140
470K
MF-LF
1/16W
402
5%
2
1
R1140
1000PF
1206
CERM
50V
5%
2
1
C1112
NTD60N02R
CASE369-LF
CRITICAL
3
1
4
Q1101
NTD60N02R
CASE369-LF
CRITICAL
3
1
4
Q1102
680UF
TH-MCZ
ELEC
16V
20%
2
1
C1102
ELEC
16V
20%
680UF
TH-MCZ
2
1
C1103
1210
CERM
10UF
10%
16V
2
1
C1111
20%
CERM
402
50V
0.001UF
2
1
C1140
CRITICAL
TH-MCZ
20%
ELEC
6.3V
1500UF
2
1
C1109
1/16W
DEVELOPMENT
MF-LF
330
402
5%
2
1
R1160
DEVELOPMENT
2.0X1.25MM-SM
GREEN-3.6MCD
2
1
LED1100
DEVELOPMENT
SOI-LF
3
14
9
8
12
U1201
1206
10UF
20%
CERM
6.3V
C1110
PP1V8_RUN
PP3V3_RUN
SOT23-LF
2N7002
2
1
3
Q1100
SM
21
XW1100
2.5V-ESR9V
POLY
CASE-D2E-LF
NOSTUFF
20%
330UF
2
1
C1119
1.8V Vreg
SYNC_MASTER=M23-PC
051-6790
19
11
154
SYNC_DATE=06/20/2005
Q1101,Q1102
376S0340 376S0388
Q903_GATE
VOLTAGE=0 V
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.45MM
GND_U1100
U1100_FEEDBACK
SYS_SLEEP
MIN_NECK_WIDTH=0.25MM
U1100_VC_D
MIN_LINE_WIDTH=0.45MM
MIN_LINE_WIDTH=0.45MM
U1100_GATE_H
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.45MM
U1100_GATE_L
MIN_NECK_WIDTH=0.25MM
U1100_COMP
GND_U1100
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.45MM
R1104_P2
GND_U1100
Q1101_GATE
MIN_LINE_WIDTH=0.45MM
MIN_NECK_WIDTH=0.25MM
U1100_SS
1V1_REF
LED_PP1V8_RUN_N
R1101_P2
LED_PP1V8_RUN_P
PWRON_L
U1100_VC_R
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.45MM
U1100_VC
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.45MM
Q1102_DRAIN
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.25MM
54 30 26 16
16
15
85
15
11
13
11
11
13
13
6
12
6
6
12
9
9
12
Preliminary
G
D
S
G
D
S
FB
LD
HD
GND
COMP
SS
VCC
VC
G
D
S
LM339A
V+
GND
G
D
S
CONT
NOISE
VIN
VOUT
GND
S
G
D
G
D
S
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
TABLE_ALT_ITEM
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_HEAD
1.0A CONTINUOUS CURRENT DRAW
7.2A CONTINUOUS CURRENT DRAW
1.30V R1205=3.24K
LOAD FROM POWER BUDGET
@ VGS=3.5 V
LOAD FROM POWER BUDGET
SO THAT 1.5V IS THE FIRST RAIL UP ON KODIAK
TURNING ON PP2V5_PWRON WITH 1V2_PWRON
U1200_FEEDBACK
1.3A PEAK CURRENT DRAW
NOTE:
8.5A PEAK CURRENT DRAW
PLACE LED NEAR VREG
1.35V R1205=2.87K
IRU3037ACS VREF=0.8VDC
VOUT=VREF*(R1203+R1205)/R1205=1.25VDC
1.25V R1205=3.65K
KODIAK CORE VOLTAGE REGULATOR
RDSON=0.012 OHM
PP1V5_PWRON_PULSAR
1210
CERM
16V
10%
10UF
2
1
C1201
CRITICAL
ELEC
1500UF
20%
6.3V
TH-MCZ
2
1
C1209
CRITICAL
ELEC
1500UF
6.3V
20%
TH-MCZ
2
1
C1208
MF-LF
1/16W
402
2.87K
1%
2
1
R1205
603
CERM
20%
10V
1UF
NOSTUFF
2
1
C1207
1000PF
50V
1206
CERM
5%
2
1
C1212
PP5V_ALL
CASE369-LF
NTD60N02R
CRITICAL
3
1
4
Q1201
0.0018UF
10%
CERM
50V
402
2
1
C1205
0
805
1/8W
MF-LF
5%
21
R1202
CERM
1UF
402
6.3V
10%
2
1
C1204
25V
220PF
CERM
402
5%
2
1
C1206
PP12V_ALL
0.1UF
603
20%
16V
CERM
2
1
C1214
CERM
10V
20%
1UF
603
2
1
C1216
CERM
25V
1UF
805
20%
2
1
C1217
MBR0520LXXG
SOD-123
2 1
D1200
MBR0520LXXG
SOD-123
2 1
D1201
MBR0520LXXG
SOD-123
2
1
D1202
CRITICAL
NTD60N02R
CASE369-LF
3
1
4
Q1202
SM
1.53UH
CRITICAL
3
2
1
L1201
5.11
MF-LF
1/4W
1%
1206
2
1
R1204
IRU3037ACS
CRITICAL
SOI-LF
2 6
8
3
5
4
1
7
U1200
MF-LF
402
1%
1/16W
2.05K
2
1
R1203
15.8K
402
1/16W
1%
MF-LF
2
1
R1201
603
6800PF
CERM
50V
10%
2
1
C1215
402
CERM
50V
5%
56PF
2
1
C1213
805
MF-LF
1/8W
5%
10
2
1
R1200
PP1V5_RUN
402
CERM
10V
20%
0.1UF
2
1
C1250
2N7002
SOT23-LF
2
1
3
Q1251
PP5V_PWRON
5%
MF-LF
402
100K
1/16W
2 1
R1250
20%
ELEC
680UF
16V
TH-MCZ
2
1
C1202
10UF
1210
16V
10%
CERM
2
1
C1210
DEVELOPMENT
402
330
MF-LF
1/16W
5%
2
1
R1260
2.0X1.25MM-SM
DEVELOPMENT
GREEN-3.6MCD
2
1
LED1200
DEVELOPMENT
SOI-LF
3
1
7
6
12
U1201
1/16W
MF-LF
5%
0
402
DEVELOPMENT
21
R1261
6.3V
10UF
805-1
20%
CERM
2
1
C1218
PP1V5_PWRON
PP1V5_PWRON
PP3V3_RUN
2N7002
SOT23-LF
2
1
3
Q1200
NOSTUFF
MF-LF
1/16W
0
5%
402
21
R1206
0
5%
402
1/16W
MF-LF
21
R1207
10%
X5R
10UF
805
6.3V
2
1
C1272
0.01UF
16V
CERM
20%
402
2
1
C1271
CRITICAL
SOT-25A
MM1571FN
U1270
MF-LF
402
10K
1/16W
5%
2
1
R1270
805
CERM
20%
1UF
10V
2
1
C1270
PP3V3_PWRON
SM
21
XW1200
DEVELOPMENT
IRLM2402PBF
SOT23
2
1
3
Q1271
SOT23-LF
2N7002
DEVELOPMENT
2
1
3
Q1270
5%
DEVELOPMENT
10K
1/16W
MF-LF
402
2
1
R1273
5%
10K
1/16W
MF-LF
402
DEVELOPMENT
2
1
R1274
PP12V_RUN
CRITICAL
TSOP-LF
SI3446DV
4
36
5
2
1
Q1250
DEVELOPMENT
20%
16V
CERM
402
0.01UF
2 1
C1275
1.5V Vreg
051-6790
19
12
154
SYNC_MASTER=FINO-PC
SYNC_DATE=06/20/2005
Q1201,Q1202
376S0340 376S0388
MIN_NECK_WIDTH=0.25MM
U1200_VC_R
MIN_LINE_WIDTH=0.45MM
U1200_GATE_L
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.45MM
U1200_COMP
U1200_SS
MIN_NECK_WIDTH=0.2MM
Q1202_DRAIN
MIN_LINE_WIDTH=0.6MM
Q1250G
1V1_REF
U1270_NOISE
U1200_FEEDBACK
MIN_LINE_WIDTH=0.45MM
MIN_NECK_WIDTH=0.25MM
U1200_GATE_H
GND_U1200
VOLTAGE=0 V
MIN_LINE_WIDTH=0.45MM
MIN_NECK_WIDTH=0.25MM
PP1V5_RUN_FOR_LED
PP1V5_PWRON_PULSAR
U1270_CONT
Q1201_GATE
MIN_LINE_WIDTH=0.45MM
MIN_NECK_WIDTH=0.25MM
U1200_VC_D
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.45MM
GND_U1200
GND_U1200
U1200_VC
MIN_LINE_WIDTH=0.45MM
MIN_NECK_WIDTH=0.25MM
R1201_P2
TURN_ON_PP1V2_L
TURN_ON_PP1V5_L
PWRON_L
LED_PP1V5_RUN_P
SYS_SLEEP
SYS_POWERUP_L
MAKE_BASE=TRUE
NC_PP1V5_PULSAR
PP1V5_RUN_PULSAR
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=1.5V
PULSAR_1V5_RUN_SWITCH
LED_PP1V5_RUN_N
MIN_LINE_WIDTH=0.45MM
MIN_NECK_WIDTH=0.25MM
R2204_P2
54 30 26
85
16
16
50
85
15
15
28
13
12
12
12
13
13
13
7
11
6
9
7
6
6
4
11
9
11
6
9
9
9
Preliminary
G
D
S
G
D
S
FB
LD
HD
GND
COMP
SS
VCC
VC
G
D
S
LM339A
V+
GND
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
1.0A CONTINUOUS
@ VGS=2.5 V
RDSON=0.04 OHM
2.6A CONTINUOUS
@ VGS=2.5 V
PP1V2_PWRON FET SWITCH
RDSON=0.04 OHM
SET OUTPUT=1.22-1.23V
U1300_FEEDBACK
VOUT=VREF*(R1003+R1005)/R1005=1.22-1.23VDC
IRU3037ACS VREF=0.8VDC
NOTE:
PLACE LED NEAR VREG
POWER BUDGET CURRENT OF TOTAL RAILS
3.2A PEAK
PP1V2_PWRON COMES UP BEFORE GPU_POWERUP_L SO THAT SHASTA CORE GETS POWER BEFORE ANYTHING ELSE
PEAK CURRENT 1.3A
PP1V2_ALL VOLTAGE REGULATOR
PEAK CURRENT 1.3A IF KODIAK 1.2V CAN BE TURNED OFF IN SLEEP. 0.6A/M33 0.0A/M23 IF NOT
PP1V2_RUN FET SWITCH
402
MF-LF
1/16W
0
5%
NOSTUFF
21
R1314
DEVELOPMENT
402
MF-LF
1/16W
5%
47K
21
R1315
PP1V2_ALL
PP1V2_ALL
PP1V2_ALL
PP3V3_RUN
PP5V_RUN
PP3V3_RUN
DEVELOPMENT
0.01UF
16V
402
20%
CERM
2
1
C1320
3.8UH
SM2
21
L1301
DEVELOPMENT
2N7002
SOT23-LF
2
1
3
Q1304
SOT23-LF
NOSTUFF
2N7002
2
1
3
Q1307
1/16W
10K
402
MF-LF
1%
NOSTUFF
2
1
R1306
SM
21
XW1300
16V
CERM
20%
402
0.01UF
2
1
C1321
DEVELOPMENT
0.01UF
402
CERM
16V
20%
21
C1322
NOSTUFF
50V
603
CERM
10%
3300PF
2
1
C1307
10K
402
MF-LF
1%
1/16W
2
1
R1305
1206
5.11
1%
1/4W
MF-LF
2
1
R1304
1206
1000PF
5%
50V
CERM
2
1
C1312
MBR0520LXXG
SOD-123
2
1
D1302
PP12V_ALL
1UF
CERM
20%
805
25V
2
1
C1317
50V
CERM
0.0018UF
10%
402
2
1
C1305
SOD-123
MBR0520LXXG
2 1
D1300
MBR0520LXXG
SOD-123
2 1
D1301
0
5%
1/8W
MF-LF
805
21
R1300
CERM
20%
1UF
25V
805
2
1
C1300
402
25V
5%
CERM
220PF
2
1
C1306
CERM
402
6.3V
10%
1UF
2
1
C1304
CRITICAL
SOI-LF
IRU3037ACS
2 6
8
3
5
4
1
7
U1300
CRITICAL
TH-KZJ-LF
6.3V
ELEC
20%
1800UF
2
1
C1309
1%
1/16W
MF-LF
402
5.36K
2
1
R1303
PP1V2_RUN
PP5V_ALL
DEVELOPMENT
100K
402
5%
MF-LF
1/16W
2 1
R1308
PP5V_ALL
CRITICAL
TSOP-LF
SI3446DV
4
3 6
521
Q1306
PP1V2_PWRON
SOT23-LF
2N7002
2
1
3
Q1305
100K
402
MF-LF
5%
1/16W
2 1
R1309
PP5V_ALL
CERM
0.0068UF
10%
25V
402
2
1
C1314
CERM
50V
5%
56PF
402
2
1
C1313
0.1UF
20%
CERM
16V
603
2
1
C1315
402
MF-LF
1/16W
18K
5%
2
1
R1301
402
0
1/16W
MF-LF
5%
21
R1312
0
5%
1/16W
NOSTUFF
MF-LF
402
21
R1313
MF-LF
1/8W
5%
4.7
805
2
1
R1302
CRITICAL
IRF7807ZPBF
SO-8
321
4
8765
Q1301
CRITICAL
SO-8
IRF7807ZPBF
321
4
8765
Q1302
10%
16V
CERM
10UF
1210
2
1
C1302
10%
16V
CERM
10UF
1210
2
1
C1303
CRITICAL
DEVELOPMENT
SI3446DV
TSOP-LF
4
3 6
5
2
1
Q1303
1210
CERM
10%
16V
10UF
2
1
C1301
SOI-LF
DEVELOPMENT
3
2
5
4
12
U1201
5%
1/16W
MF-LF
DEVELOPMENT
330
402
2
1
R1350
DEVELOPMENT
GREEN-3.6MCD
2.0X1.25MM-SM
2
1
LED1300
DEVELOPMENT
402
100K
5%
1/16W
MF-LF
2
1
R1351
MF-LF
DEVELOPMENT
402
47K
5%
1/16W
2
1
R1352
0
MF-LF
1/16W
402
DEVELOPMENT
5%
21
R1353
0.1UF
DEVELOPMENT
402
20%
10V
CERM
2
1
C1350
051-6790
19
13
154
SYNC_MASTER=FINO-PC
SYNC_DATE=06/20/2005
1.2V Vreg
U1300_FEEDBACK
PP1V2_RUN_FOR_LED
U1300_GATE_L
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.45MM
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
Q1302_DRAIN
Q1305_G
Q1006_G
PWRON_L
U1300_SS
GPU_POWERUP_L
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.45MM
Q1301_GATE
U1300_GATE_H
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.45MM
MIN_LINE_WIDTH=0.45MM
MIN_NECK_WIDTH=0.25MM
U1300_VC_R
MIN_LINE_WIDTH=0.45MM
R1304_P2
MIN_NECK_WIDTH=0.25MM
MIN_NECK_WIDTH=0.25MM
U1300_VC
MIN_LINE_WIDTH=0.45MM
R1301_P2
LED_PP1V2_RUN_N
LED_PP1V2_RUN_P
TURN_ON_PP1V2_L
U1300_COMP
VOLTAGE=0 V
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.45MM
GND_U1300
TURN_ON_PP1V2_L
Q1304_G
GND_U1300
1V1_REF
GND_U1300
U1300_VC_D
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.45MM
Q1003_G
SYS_SLEEP
54 30 26
16
16
15
13
13
85
15
12
12
13
12
13
12
13
12
9
11
85
9
9
4
6
4
6
11
6
11
Preliminary
G
D
S
G
D
S
G
D
S
EN
GND
IN
OUT
ADJ
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
NOTE:
PEAK CURRENT 0.1A
0.2A PEAK
POWER BUDGET CURRENT OF TOTAL RAILS
@ VGS=2.5 V
PP2V5_RUN FET SWITCH
SET OUTPUT=2.5V
IRU3037CS VREF=1.24VDC
VOUT=VREF*(R1581+R1582)+1=5.505VDC
NOSTUFF OPTION TO DELAY 2.5V PWRON TO COME UP WITH 3.3V PWRON
0.1A CONTINUOUS
RDSON=0.04 OHM
PP2V5_ALL VOLTAGE REGULATOR
RDSON=0.04 OHM
@ VGS=2.5 V
PEAK CURRENT 0.1A
PP2V5_PWRON FET SWITCH
10UF
20%
1206
CERM
6.3V
2
1
C1580
PP2V5_ALL
PP3V3_ALL
PP2V5_ALL
PP2V5_ALL
16V
CERM
402
20%
0.01UF
2
1
C1581
0.01UF
402
CERM
16V
20%
21
C1582
PP2V5_RUN
2N7002DW-X-F
SOT-363
4
5
3
Q1504
SOT-363
2N7002DW-X-F
1
2
6
Q1504
PP5V_ALL
MF-LF
1/16W
402
100K
5%
2 1
R1508
CRITICAL
TSOP-LF
SI3446DV
4
3 6
521
Q1506
PP2V5_PWRON
SOT23-LF
2N7002
2
1
3
Q1505
100K
402
1/16W
MF-LF
5%
2 1
R1509
PP5V_ALL
5%
MF-LF
1/16W
0
402
NOSTUFF
21
R1512
402
MF-LF
1/16W
5%
0
21
R1513
CRITICAL
TSOP-LF
SI3446DV
4
3 6
5
2
1
Q1503
6.3X8-SM
CRITICAL
20%
ELEC
6.3V
330UF
2
1
C1583
1.02K
402
MF-LF
1/16W
1%
2
1
R1581
MF-LF
1K
402
1%
1/16W
2
1
R1582
CRITICAL
MIC39102
SOP-8-LF
3
2
8765
1
4
U1580
MF-LF
1/16W
3.3K
5%
402
2
1
R1580
2.5V Vreg
051-6790
19
15
154
SYNC_MASTER=FINO-PC
SYNC_DATE=06/20/2005
U1580_ADJ
Q1506_G
Q1505_G
PWRON_L
SYS_SLEEP
TURN_ON_PP3V3_PWRON_L
Q1503_G
U1580_EN
54 30 26
16
16
13
13
12
12
16
11
11
4
Preliminary
G
D
S
G
D
S
02
G
D
S
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
POWER SEQUENCING PIN TO DELAY TO BRING UP 3.3V LAST FOR SHASTA
CRITICAL
SO-8
IRF7413PBF
321
4
8765
Q1600
5%
47K
402
MF-LF
1/16W
2
1
R1600
MF-LF
5%
3.6K
402
1/16W
2
1
R1602
IRF7413PBF
CRITICAL
SO-8
321
4
8765
Q1602
3.6K
1/16W
MF-LF
5%
402
2
1
R1607
MF-LF
47K
5%
402
1/16W
2
1
R1601
2N7002DW-X-F
SOT-363
4
5
3
Q1601
SOT-363
2N7002DW-X-F
1
2
6
Q1601
16V
20%
0.01UF
402
CERM
2
1
C1600
402
10V
0.1UF
20%
CERM
2
1
C1601
SN74LVC1G02
SOT23-5-LF
4
5
3
2
1
U1601
PP12V_ALL
PP5V_ALL
PP3V3_ALL
PP12V_ALL
PP5V_PWRON
PP3V3_ALL
PP3V3_PWRON
402
1/16W
0
MF-LF
5%
2
1
R1604
MF-LF
5%
1/16W
0
402
NOSTUFF
21
R1603
10V
CERM
402
0.1UF
20%
2
1
C1603
2N7002
SOT23-LF
2
1
3
Q1603
MF-LF
5%
402
1/16W
10K
2
1
R1605
10K
1/16W
MF-LF
5%
402
NOSTUFF
2
1
R1608
3.3K
402
5%
MF-LF
1/16W
NOSTUFF
2
1
R1609
5V & 3.3V Fets
SYNC_DATE=06/20/2005
154
16
19
051-6790
SYNC_MASTER=FINO-PC
Q1601G
TURN_ON_PP3V3_PWRON_L
GATE_5V_PWRON
SYS_POWERUP_L_BUF
PP3V3_RUN
SYS_SLEEP
PWRON_L
SYS_POWERUP
GATE_3V3_PWRON
54 30 26 15
15
13
13
15
7
12
12
4
7
6
11
11
Preliminary
RESET*
TDI
DVDD
VESTA MISC
1 OF 3
PVDD
AVDDL
AVDD
GND
AGND
OVDD
REGSUP1
REGSEN1
REGCTL1
REGSUP2
REGSEN2
REGCTL2
2.5V_EN
DNC
DNC
TDO
TCK
TMS
TRST*
NC
NC
G
D
S
G
D
S
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
Page Notes
IPU
IPU
VESTA HAS INTERNAL PULLUPS. MLB
PULLUPS MAY BE NOSTUFFED IN EVT.
To keep Vesta from being held
IPU
IPU
IPU
0 - OVDD=3.3V
1 - OVDD=2.5V
2.5V_EN
WHEN OVDD=2.5V GMII PINS ARE NOT 3.3V TOLERANT
IPD
SCHMITT TRIGGER W/ INTERNAL PULLUP
M23: PP3V3_ENETFW IS AN ALL RAIL
M23: PP3V3_ENETFW IS AN ALL RAIL
VESTA JTAG
(NONE)
regulator will be in continuous mode.
Signal aliases required by this page:
Controls operating mode of Vesta 1.2V
Power aliases required by this page:
regulator. If both options are off the
NC
NC
L9/M9 N5/N6
N9/N10
M23: ADDED C1726 AND C1744 PER BROADCOM RECOMMENDATIONS
in reset when system is off
NOTE: Reset GPIO is active HIGH
L6/M6
BOM options provided by this page:
- VESTA1V2_BURST / VESTA1V2_PULSE
RESET ASSERT REQUIREMENT IS 20MS TO 100MS
20%
0.1uF
CERM
402
10V
2
1
C1710
0.1uF
20%
10V
CERM
402
2
1
C1711
0.1uF
CERM
20%
10V
402
2
1
C1712
0.1uF
402
CERM
10V
20%
2
1
C1713
0.1uF
402
10V
20%
CERM
2
1
C1703
0.1uF
20%
402
CERM
10V
2
1
C1702
0.1uF
CERM
20%
10V
402
2
1
C1701
CERM
402
0.1uF
10V
20%
2
1
C1700
0.1uF
20%
10V
CERM
402
2
1
C1722
0.1uF
20%
402
CERM
10V
2
1
C1725
0.1uF
20%
402
10V
CERM
2
1
C1721
0.1uF
20%
10V
CERM
402
2
1
C1724
20%
10V
CERM
402
0.1uF
2
1
C1731
402
CERM
10V
20%
0.1uF
2
1
C1730
0.1uF
20%
402
CERM
10V
2
1
C1720
0.1uF
20%
402
CERM
10V
2
1
C1723
20%
10V
CERM
402
0.1uF
2
1
C1743
0.1uF
CERM
10V
20%
402
2
1
C1742
20%
0.1uF
10V
CERM
402
2
1
C1741
20%
10V
CERM
402
0.1uF
2
1
C1740
6.3V
X5R
10UF
10%
805
2
1
C1708
SM
FERR-EMI-600-OHM
21
L1700
SEE_TABLE
FBGA-200-LF
VESTA-V1.3
D8
E8
E10
D7
E7
H4
E2
E1
F2
F1
G4
G5
N4
A15
K1
F15
A7
A1
M13
C3
K2
J2
F14
C14
B7B2A2
J1
C15
B15
B1
E9
C9
N10
N9N6N5M9M6L9L6
R12
R3
P11
P10
P5
P4
N8N7M8M7L8
L7
J12
J11
P9P8P7
P6
H12
H11
M3
U1701
1K
402
MF-LF
1/16W
5%
2
1
R1740
1K
5%
1/16W
MF-LF
402
2
1
R1743
1K
5%
1/16W
MF-LF
402
2
1
R1742
1K
5%
1/16W
MF-LF
402
2
1
R1741
805
6.3V
X5R
10%
10UF
2
1
C1726
6.3V
10UF
10%
X5R
805
2
1
C1744
NOSTUFF
MF-LF
402
1/16W
5%
0
21
R1720
6.3V
1UF
10%
CERM
402
2
1
C1750
1/16W
5%
402
MF-LF
47K
2
1
R1751
2N7002DW-X-F
SOT-363
1
2
6
Q1750
1/16W
402
MF-LF
5%
10K
2
1
R1750
2N7002DW-X-F
SOT-363
4
5
3
Q1750
10%
X5R
6.3V
805
10UF
2
1
C1714
5%
MF-LF
402
1/16W
10K
2
1
R1752
154
17
SYNC_DATE=06/20/2005
SYNC_MASTER=FINO-DC
19
051-6790
Vesta Core / Misc
=PP1V2_ENETFW
VESTA_RESET_L
=PP2V5_ENETFW
MIN_NECK_WIDTH=0.25 MM
PP1V2_VESTA_AVDDL
MIN_LINE_WIDTH=0.50 MM
VOLTAGE=1.2V
MAKE_BASE=TRUE
TP_JTAG_VESTA_TDO
=JTAG_VESTA_TMS
=JTAG_VESTA_TRST_L
VESTA_RESET_RC
=PP3V3_ENETFW
VESTA_RESET_H
ENETFW_RESET
=PP3V3_ENETFW
MAKE_BASE=TRUE
TP_JTAG_VESTA_TMS
=JTAG_VESTA_TRST_L
=JTAG_VESTA_TCK
=JTAG_VESTA_TDO
TP_VESTA_2_5V_EN
TP_VESTA_REGCTL1
TP_VESTA_REGSUP1
TP_VESTA_REGSEN1
TP_VESTA_REGCTL2
TP_VESTA_REGSUP2
TP_VESTA_REGSEN2
TP_VESTA_DNC_C9
TP_VESTA_DNC_E9
=JTAG_VESTA_TCK
=JTAG_VESTA_TDI
=JTAG_VESTA_TDO
MAKE_BASE=TRUE
TP_JTAG_VESTA_TCK
=PP3V3_ENETFW
=JTAG_VESTA_TDI
=PP3V3_ENETFW
=PP3V3_ENETFW
MAKE_BASE=TRUE
TP_JTAG_VESTA_TDI
MAKE_BASE=TRUE
TP_JTAG_VESTA_TRST_L
=JTAG_VESTA_TMS
139
139
139
139
139
139
139
132
132
132
132
132
132
132
17
17
17
17
17
7
7
9
17
17
7
132
24
7
9
17
17
17
9
9
9
9
9
9
9
9
9
17
17
17
9
7
17
7
7
9
9
17
Preliminary
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
VDD_CORE
CORE & PCI-E POWER
(9 OF 10)
(1.6V-1.2V)
PP
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
DRAWING
KODIAK CORE
PAGE 19
2
1.6V
Q63 = PP1V6
SEE_TABLE
BGA
KODIAK-ASIC-040812
U15
T20
T16
R22
R18
R14
P21
AC22
AC18
AC14
AB21
AB17
AA23
P17
AA19
AA15
Y20
Y16
W22
W18
W14
V21
V17
U19
N15
U14
T21
T17
R23
R19
R15
P20
AC23
AC19
AC15
AB20
AB16
AA22
P16
AA18
AA14
Y21
Y17
W23
W19
W15
V20
V16
U18
N14
U1900
10%
402
CERM
1UF
6.3V
2
1
C1906
10%
402
CERM
1UF
6.3V
2
1
C1900
10%
402
CERM
1UF
6.3V
2
1
C1905
10%
402
CERM
1UF
6.3V
2
1
C1914
10%
402
CERM
1UF
6.3V
2
1
C1913
10%
402
CERM
1UF
6.3V
2
1
C1919
10%
402
CERM
1UF
6.3V
2
1
C1924
10%
402
CERM
1UF
6.3V
2
1
C1918
10%
402
CERM
1UF
6.3V
2
1
C1923
10%
402
CERM
1UF
6.3V
2
1
C1912
10%
402
CERM
1UF
6.3V
2
1
C1911
10%
402
CERM
1UF
6.3V
2
1
C1917
10%
402
CERM
1UF
6.3V
2
1
C1922
10%
402
CERM
1UF
6.3V
2
1
C1916
10%
402
CERM
1UF
6.3V
2
1
C1921
10%
402
CERM
1UF
6.3V
2
1
C1910
10%
402
CERM
1UF
6.3V
2
1
C1915
10%
402
CERM
1UF
6.3V
2
1
C1920
10%
402
CERM
1UF
6.3V
2
1
C1904
SM
P4MM
1
PP1900
10%
402
CERM
1UF
6.3V
2
1
C1909
10%
402
CERM
1UF
6.3V
2
1
C1903
10%
402
CERM
1UF
6.3V
2
1
C1908
10%
402
CERM
1UF
6.3V
2
1
C1902
10%
402
CERM
1UF
6.3V
2
1
C1907
10%
402
CERM
1UF
6.3V
2
1
C1901
KODIAK CORE & BYPASS
SYNC_MASTER=Q63
SYNC_DATE=08/01/2005
154
19
051-6790
19
=PPVCORE_PWRON_NB
LAST_MODIFIED=Tue Aug 30 17:23:19 2005
7
Preliminary
PP
PP
ADD1
ADD0
ALERT
SMBDATA
SMBCLK
VCC
NC_5
NC_1
STBY
DXP
NC_16
GND
NC_9
NC_13
DXN
(SYM_VER2)
PMR_CLK_STOP_L
CE1_LT_TCK
CE1_B_TDO
CE1_DI1_TMS
CE1_MC_TDI
CE1_DI2_TRST
CE0_TEST
SYS_THDIO_D
SYS_THDIO_G
VD5_0
VD5_1
VD5_2
NORTH_BRIDGE_RESET_L
HRESET_L
SUSPENDACK_L
SUSPENDREQ_L
SYS_ISCL0
SYS_ISCA0
SYS_ISCA1
SYS_ISCL1
API_ISCA
API_ISCL
PMR_CLK_P
PMR_CLK_N
(10 OF 10)
POWER/TEST/MISC
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
NEED TO CHECK ALL I2C ADDRESSES
PMR_CLK_STOP CAN BE USED TO STOP ALL CLOCKS IN KODIAK
NOTE:
ON PAGE 24 )
SHASTA GPIO TERMINATIONS
PLACE TERM R/C CLOSE TO KODIAK
NOTE: LOW = DISABLE PMR_CLK
KODIAK JTAG_TRST PULLED HIGH
AND SYS_IO_RESET_L (SMU)
PCI_RESET_L IS AN ’AND’ OF SB_PCI_RESET_L (SB)
THESE PINS HAVE INTERNAL PULLUPS OR PULLDOWNS
PLACE R2012 IN AN ACCESSIBLE LOCATION
C2055 ADDED FOR KODIAK RAM DECOUPLING
PAGE 58 IS SHORT ONE CAP
KODIAK ALIASES
1 | 0 | 98/99
hiZ | 1 | 56/57
1 | hiZ| 9A/9B
A0 | A1 | ADDR
----+----+----- 0 | 0 | 30/31
0 | hiZ| 32/33
0 | 1 | 34/35
hiZ | 0 | 52/53
1 | 1 | 9C/9D
hiZ | hiZ| 54/55
TO ALLOW SMU DEBUG ACCESS
(SOME OF THESE ARE NOSTUFF
SHASTA ALIASES
SHASTA JTAG
NB_OVERTEMP
PLACE BY IC
USED FOR DEBUG
10%
6.3V
CERM
402
1UF
2
1
C2052
1UF
10%
6.3V
CERM
402
2
1
C2051
6.3V
10%
1UF
402
CERM
2
1
C2050
+/-0.25PF
50V
NOSTUFF
CERM
402
1.5PF
2
1
C2053
1/16W
0
MF-LF
5%
402
2
1
R2000
NOSTUFF
60.4
MF-LF
1%
1/16W
402
2
1
R2001
NOSTUFF
60.4
MF-LF
1%
1/16W
402
2
1
R2002
1K
MF-LF
1%
1/16W
402
2
1
R2003
MF-LF
402
1/16W
5%
0
NOSTUFF
21
R2012
402
1/16W
5%
MF-LF
10K
2
1
R2013
SM
2
1
XW2000
P4MM
SM
1
TP2000
P4MM
SM
1
TP2002
1/16W
5%
4.7K
MF-LF
402
2
1
R2053
NOSTUFF
4.7K
5%
402
MF-LF
1/16W
2
1
R2054
402
MF-LF
1/16W
5%
10K
21
R2061
402
MF-LF
1/16W
5%
10K
21
R2062
10K
5%
1/16W
MF-LF
402
21
R2063
10K
5%
1/16W
MF-LF
402
21
R2064
402
MF-LF
1/16W
5%
NOSTUFF
0
21
R2074
402
4.7K
5%
MF-LF
1/16W
2
1
R2073
402
CERM
6.3V
10%
1UF
2
1
C2055
NOSTUFF
402
0
MF-LF
5%
1/16W
21
R2087
NOSTUFF
402
1K
MF-LF
1/16W
5%
2
1
R2084
1K
MF-LF
1/16W
5%
402
2
1
R2085
402
1K
MF-LF
1/16W
5%
2
1
R2083
402
NOSTUFF
1K
MF-LF
1/16W
5%
2
1
R2086
402
6.3V
10%
1UF
CERM
2
1
C2080
0.0022UF
CERM
402
50V
10%
21
C2081
QSOP
MAX6690MEE
CRITICAL
2
15
12
14
9
5
16
13
1
87
3
4
11
6
10
U2080
402
5%
1/16W
2.2
MF-LF
21
R2082
KODIAK-ASIC-040812
BGA
AH01
AF05
AF02
G15
F15
AJ05
AK03
AH06
AG04
AJ01
AJ03
AG02
AE09
AE10
AL01
AG01
AG07
AJ04
AK06
AL02
AG05
AG08
AH03
AG03
U1900
SYNC_DATE=06/20/2005
SYNC_MASTER=FINO-ME
154
20
19
051-6790
KODIAK & SHASTA MISC
=PCI_ROM_RESET_L
I2C_NB_TEMP_SCL
I2C_NB_TEMP_SDA
TSENSE_NB_ADD0
TSENSE_NB_OVERTEMP_L
TSENSE_NB_ADD1
SYS_OVERTEMP_L
=PP1V8_PWRON_NBMEM
JTAG_SB_TRST_L
JTAG_NB_TCK
NB_PU_RST_L
=PP2V5_PWRON_NB_MISC
JTAG_NB_TRST_L
MAKE_BASE=TRUE
TP_JTAG_SB_TMS
MAKE_BASE=TRUE
NB_SLOT_RESET_L
JTAG_SB_TDI
JTAG_SB_TCK
MAKE_BASE=TRUE
TP_JTAG_SB_TCK
MAKE_BASE=TRUE
TP_JTAG_SB_TDO
RAI_EXP_INTR_L<1>
MAKE_BASE=TRUE
TP_JTAG_SB_TDI
NB_PU_RST_L
NB_THERM_A
CE0TEST
JTAG_NB_TRST_L
JTAG_NB_TDO
NB_PMR_CLK_P
NB_HRST_L
I2C_NB_A_SCL
NB_PMR_CLK_N
I2C_NB_C_SCL
I2C_NB_B_SDA
JTAG_NB_TDI
JTAG_NB_TMS
I2C_NB_B_SCL
I2C_NB_A_SDA
I2C_NB_C_SDA
NB_SUSPEND_REQ_L
NB_SUSPEND_ACK_L
TERM_RC
=PP2V5_PWRON_NB_MISC
MAKE_BASE=TRUE
PCI_RESET_L
=PCI_USB2_RESET_L
=PCI_AIRPORT_RESET_L
=GPU_RESET_L
JTAG_SB_TDO
JTAG_SB_TMS
RAI_EXP_INTR_L<3>
MAKE_BASE=TRUE
NC_PMR_CLK_DIS_L
PMR_CLK_DIS_L
NB_THERM_K
NB_PMR_CLK_STOP_L
=PP2V5_PWRON_NB_MISC
=PP3V3_PWRON_SB
PMR_CLK_DIS_L
PP_2V5PWRONNBMISC
RAI_EXP_INTR_L<2>
RAI_EXP_INTR_L<0>
NET_PHYSICAL_TYPE=10MIL_WIDTH
NET_SPACING_TYPE=TSENSE_DIFPAIR
DIFFERENTIAL_PAIR=TSENSE_NB
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.25mm
NB_THERM_K
NET_SPACING_TYPE=TSENSE_DIFPAIR
NET_PHYSICAL_TYPE=10MIL_WIDTH
DIFFERENTIAL_PAIR=TSENSE_NB
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.25mm
NB_THERM_A
MIN_LINE_WIDTH=0.38mm
MIN_NECK_WIDTH=0.38MM
TSENSE_NB_VCC
=PP3V3_RUN_SMU
39
39
39
119
59
30
30
30
56
93
58
28
28
28
24
30
28
39
24
30
30
20
20
30
20
30
27
27
30
30
62
20
119
20
23
28
125
39
39
24
7
9
9
20
7
9
9
24
24
24
9
9
24
9
20
20
9
9
26
39
26
39
39
9
9
39
39
39
30
30
7
92
122
121
84
24
24
24
6
20
20
7
7
20
6
24
24
20
20
7
Preliminary
VIO1
POWER
VDDO33
VDDO25
VIO2
VDDP_KL
VDDC
GND
GND
GND
(1 OF 8)
PP
PP
PP
DRAWING
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
- =PP3V3_PWRON_SB_PCI32 (VIO2) (TO 5V OR 3.3V)
VIO1 TO SAME IF 64-BIT
CONNECT VIO2 TO
NOTE: PCI pads use the VIO supply to meet
different drive timing
spec for 5V vs. 3.3V operation.
BOM options provided by this page:
Must power Shasta VCore rail before any
Total: 3015 mW
Power Sequencing:
(NONE)
(NONE)
PCI, otherwise 3.3V.
For PCI_AD<31..0>
I/O 2.5 - 2.5V - 20 mA ( 60 mW)
ANALOG12 - 1.2V - 600 mA ( 760 mW)
For PCI_AD<63..32>
Signal aliases required by this page:
other Shasta supplies.
appropriate PCI bus voltage and
characteristics required by the PCI
- =PP1V2_PWRON_SB_VCORE
- =PP2V5_PWRON_SB
- =PP3V3_PWRON_SB
- =PP3V3_PWRON_SB_PCI64 (VIO1) (TO 5V OR 3.3V)
Power aliases required by this page:
Page Notes
I/O 3.3 - 3.3V - 220 mA ( 770 mW)
VDDPs - 2.5V - 100 mA ( 250 mW)
DIGITAL - 1.2V - 950 mA (1175 mW)
Shasta max (est 06/30/03) current:
10V
0.1uF
CERM
402
20%
2
1
C2304
10V
0.1uF
CERM
402
20%
2
1
C2305
10V
0.1uF
CERM
402
20%
2
1
C2306
10V
0.1uF
CERM
402
20%
2
1
C2307
10V
0.1uF
CERM
402
20%
2
1
C2308
10V
0.1uF
CERM
402
20%
2
1
C2309
10V
0.1uF
CERM
402
20%
2
1
C2302
10V
0.1uF
CERM
402
20%
2
1
C2301
10V
0.1uF
CERM
402
20%
2
1
C2300
10V
0.1uF
CERM
402
20%
2
1
C2314
10V
0.1uF
CERM
402
20%
2
1
C2313
10V
0.1uF
CERM
402
20%
2
1
C2312
10V
0.1uF
CERM
402
20%
2
1
C2311
10V
0.1uF
CERM
402
20%
2
1
C2310
0.1uF
10V
CERM
402
20%
2
1
C2334
0.1uF
10V
CERM
402
20%
2
1
C2333
10V
0.1uF
CERM
402
20%
2
1
C2339
10V
0.1uF
CERM
402
20%
2
1
C2338
10V
0.1uF
CERM
402
20%
2
1
C2332
10V
0.1uF
CERM
402
20%
2
1
C2331
10V
0.1uF
CERM
402
20%
2
1
C2337
10V
0.1uF
CERM
402
20%
2
1
C2336
10V
0.1uF
CERM
402
20%
2
1
C2330
10V
0.1uF
CERM
402
20%
2
1
C2335
10V
0.1uF
CERM
402
20%
2
1
C2324
402
10V
0.1uF
CERM
20%
2
1
C2323
10V
0.1uF
CERM
402
20%
2
1
C2329
402
10V
0.1uF
CERM
20%
2
1
C2328
0.1uF
10V
CERM
402
20%
2
1
C2322
10V
0.1uF
CERM
402
20%
2
1
C2321
10V
0.1uF
CERM
402
20%
2
1
C2327
0.1uF
10V
CERM
402
20%
2
1
C2326
10V
0.1uF
CERM
402
20%
2
1
C2320
10V
0.1uF
CERM
402
20%
2
1
C2325
10V
0.1uF
CERM
402
20%
2
1
C2351
10V
0.1uF
CERM
402
20%
2
1
C2350
10V
0.1uF
CERM
402
20%
2
1
C2357
10V
0.1uF
CERM
402
20%
2
1
C2356
10V
0.1uF
CERM
402
20%
2
1
C2355
10V
0.1uF
CERM
402
20%
2
1
C2362
10V
0.1uF
CERM
402
20%
2
1
C2361
10V
0.1uF
CERM
402
20%
2
1
C2360
10V
0.1uF
CERM
402
20%
2
1
C2365
V1.1
SEE_TABLE
SHASTA
BGA-LF
Y19
W22
L21
K21
H17
H18
V8
D1
B5
B2
B1
AB6
AB2
AB10
AA3
W4
V7
U9
U12
R2
M1
L7
H1
F8
F4
AA2
AA1
G15
D19
P15N8M15L8L15K8J15
J12
T15
T10
R9
R12
R10
H8
H15
D2
C19
AB22
AB1
W5
W19
U22
U13
U10
T12
R19
P9
P4
AA6
P14
P13
P12
P10
N9
N22
N13
N12
N11
N10
AA10
M2
M14
M13
M12
M11
M10L9L16
L14
L13A5L12
L11
L10
K9
K7
K13
K12
K11
K10
J22
A22
J16
J14
J13
J11
J10
H9
H2
F7
F3
E22
A2
A1
U2300
SM
2
1
XW2304
SM
2
1
XW2303
SM
2
1
XW2300
SM
P4MM
1
PP2300
P4MM
SM
1
PP2303
SM
P4MM
1
PP2304
10V
0.1uF
CERM
402
20%
2
1
C2303
ABBREV=DRAWING
TITLE=KILOHANA
23
154
051-6790
19
SYNC_MASTER=Q63
SYNC_DATE=08/01/2005
Shasta Core Power
=PP2V5_PWRON_SB
PP_1V2PWRONSBVCORE
=PP3V3_PWRON_SB_PCI32
=PP2V5_PWRON_SB
=PP1V2_PWRON_SB_VCORE
=PP3V3_PWRON_SB_PCI64
PP_3V3PWRONSBPCI64
=PP3V3_PWRON_SB
NO_TEST=YES
PP_2V5PWRONSB
LAST_MODIFIED=Tue Aug 30 17:23:22 2005
138
138
119
119
119
56
24
24
24
23
23
20
7
6
7
7
7
7
6
7
6
Preliminary
GND
PLL_49
GND
XTAL_18 PLL_45
GND
VIO
PME
PLL_49
VDD
PLL_45
VDD
XGI
XTALS
TEST
PWR_MGT
PCI
GPIO
I2C
I2S2 I2S1 I2S0
(2 OF 8)
PCI1C_BE_4_L
PCI1C_BE_5_L
PCI1C_BE_6_L
PCI1C_BE_7_L
PCI1PAR64_H
XGI_DTI_H
XGI_DTO1_H
XGI_CLK_H
XGI_DTO0_H
PCI1ACK64_L
PCI1REQ64_L
PCI1AD_60_H
PCI1AD_63_H
PCI1AD_62_H
PCI1AD_61_H
PCI1AD_50_H
PCI1AD_52_H
PCI1AD_53_H
PCI1AD_51_H
PCI1AD_59_H
PCI1AD_58_H
PCI1AD_57_H
PCI1AD_56_H
PCI1AD_55_H
PCI1AD_54_H
PCI1AD_40_H
PCI1AD_41_H
PCI1AD_42_H
PCI1AD_43_H
PCI1AD_44_H
PCI1AD_49_H
PCI1AD_48_H
PCI1AD_47_H
PCI1AD_46_H
PCI1AD_45_H
PCI1AD_39_H
PCI1REQ_5_L
PCI1AD_32_H
PCI1AD_34_H
PCI1AD_38_H
PCI1AD_37_H
PCI1AD_36_H
PCI1AD_33_H
PCI1AD_35_H
PCI1GNT_5_L
PCI1GNT_4_L
PCI1REQ_4_L
PCI1GNT_3_L
PCI1REQ_3_L
XTAL_18XTAL
VDD VDD
FSTEST
XTAL_18_I
XTAL_18_O
XTALI
XTALO
PLLTEST
TEST_MODE_H
TDI
TCK
TMS
TDO
INTRWD_H
I2CDATA_H
I2CCLK_H
PCI_SEL32BIT_H
GPIO_H_3
GPIO_H_2
GPIO_H_1
I2S2SYNC_H
I2S2BITCLK_H
I2S2MCLK_H
I2S2DTO_H
I2S2DTI_H
GPIO_H_0
I2S1DTO_H
I2S1MCLK_H
I2S1BITCLK_H
I2S1SYNC_H
I2S1DTI_H
I2S0BITCLK_H
I2S0SYNC_H
I2S0DTI_H
I2S0DTO_H
I2S0MCLK_H
RESET_L
STOPXTALS_L
SUSPENDREQ_L
SUSPENDACK_L
PCI1PME_L
TRST_L
PP
PP
PP
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
DRAWING
PLACE R2402 CLOSE TO SHASTA
AUDIO GPIO - see note on right
NorthBridge / SouthBridge MPIC Routing
DIFFERENTIAL_PAIR
DO NOT swap between RPAKs
ELECTRICAL_CONSTRAINT_SET
- _PP2V5_PWRON_SB
- _PP3V3_PCI
Power aliases required by this page:
Signal aliases required by this page:
BOM options provided by this page:
- PCI_64BIT:
- MPIC_NB/MPIC_SB:
Page Notes
- _PP3V3_PWRON_SB
- _PP1V2_PWRON_SB
(NONE)
NOTE: XGC required for Shasta GPIOs
the audio circuit to provide the
NOTE: It is the responsibility of
36
8
14
GPIO
16
24
13
(SCCB)
20
19
21
9
22
15
12
45
26
35
(I2S1_RESET_L)
I2S2: S/P-DIF
NC
46
53
54
52
48
27
34
33
32
30
49
7
(SCCA)
51
(I2S0_DEV_TO_SB_DTI)
6
50
47
31
29
I2S0: Audio DAC
(I2S2_DEV_TO_SB_DTI)
25
28
10
11
17
37
38
39
40
41
42
43
44
AUDIO GPIOS
SPEC SHOWS LOAD CAPACITANCE OF 16PF FOR 197S0004
necessary pull-ups & pull-downs.
FROM SOUTHBRIDGE
FROM NORTHBRIDGE
TO CPU
Configures Shasta for 64-bit PCI
To SouthBridge ->
NET_SPACING_TYPE
AUDIO PAGES IS RESPONSIBLE FOR TERMINATION OF I2S0 AND I2S2
DO NOT ADD PULLUP/DOWN FOR I2S0 AND IS=2S2 IN THIS PAGE
(I2S1_DEV_TO_SB_DTI)
Re-pin within each RPAK as necessary
interrupt controller.
Selects whether NorthBridge or
SouthBridge MPIC will be used for
I2S1: Soft Modem
23
18
(I2S2_RESET_L)
PLACE R2432 CLOSE TO SHASTA
10UF
10%
6.3V
X5R
805
2
1
C2400
402
CERM
1uF
6.3V
10%
2
1
C2401
402
CERM
1uF
6.3V
10%
2
1
C2411
10UF
10%
6.3V
X5R
805
2
1
C2410
10UF
10%
6.3V
X5R
805
2
1
C2420
402
CERM
1uF
6.3V
10%
2
1
C2421
10UF
10%
6.3V
X5R
805
2
1
C2430
402
CERM
1uF
6.3V
10%
2
1
C2431
MF-LF
10K
402
5%
1/16W
2
1
R2400
SM
18.432M
CRITICAL
21
Y2490
1/16W
1%
402
MF-LF
200
2
1
R2490
5%
402
CERM
22pF
50V
2
1
C2491
5%
402
CERM
22pF
50V
2
1
C2490
1/16W
1%
402
MF-LF
4.7K
2
1
R2480
BGA-LF
V1.1
SHASTA
Y13
V13
W13
AB12
W14
V15
U15
T9
U7
W2
Y4
W17
W12
Y11
A3
W11
AA11
AB11
U11
V11
W10
E9
Y12
AA12
AA13AB13
U14
W6
U16
AB21
U17
K17
W18
E18
Y20
AA20
AA19
K20
K22
H22
J20
H21
G22
F22
J19
H20
G21
F21
J17
H19
K18
D22
G20
D21
C22
G19
F20
C21
E20
D20
F19
E19
G18
G17
C20
B21
A21
F16
G16
F17
F18
A20
D18
L17
V12
W9
Y7
Y8
AA5
AB4
AA7
V9
AB5
V10
AA8
Y6
U8
Y5
W7
AA4
AB7
Y9
W8
AB3
Y2
V5
V14
U2300
20%
402
CERM
0.1uF
10V
2
1
C2440
1/16W
5%
402
MF-LF
10K
1 2
R2450
1/16W
5%
402
MF-LF
10K
1 2
R2451
1/16W
5%
402
MF-LF
10K
1 2
R2452
1/16W
5%
402
MF-LF
10K
1 2
R2453
1/16W
5%
402
MF-LF
10K
21
R2456
1/16W
5%
402
MF-LF
10K
1 2
R2457
1/16W
5%
402
MF-LF
10K
21
R2459
MF-LF
10K
402
5%
1/16W
21
R2463
1/16W
1%
402
MF-LF
1K
SAT_PWRON
21
R2460
4.7K
1/16W
5%
402
MF-LF
21
R2461
1/16W
5%
402
MF-LF
10K
21
R2466
1/16W
5%
402
MF-LF
10K
21
R2465
1/16W
5%
402
MF-LF
10K
21
R2467
1/16W
5%
402
MF-LF
10K
21
R2468
NOSTUFF
1/16W
1%
402
MF-LF
1K
21
R2462
1/16W
5%
402
MF-LF
10K
21
R2455
1/16W
5%
402
MF-LF
10K
21
R2454
1/8W
5%
805
MF-LF
3.3
21
R2405
1/8W
5%
805
3.3
MF-LF
21
R2410
1/8W
5%
805
MF-LF
3.3
21
R2420
1/8W
5%
805
MF-LF
3.3
21
R2430
1/16W
5%
402
MF-LF
10K
21
R2464
1/16W
5%
402
MF-LF
10K
21
R2422
NOSTUFF
4.7K
1/16W
5%
402
MF-LF
21
R2406
1/16W
5%
402
MF-LF
10K
21
R2404
1/16W
5%
402
MF-LF
10K
21
R2421
1/16W
1%
402
MF-LF
1K
SAT_RUN
21
R2416
1/16W
5%
402
MF-LF
10K
NOSTUFF
21
R2417
1/16W
5%
402
MF-LF
10K
2 1
R2413
1/16W
5%
402
MF-LF
10K
2 1
R2414
1/16W
5%
402
MF-LF
10K
2 1
R2415
402
10K
MF-LF
5%
1/16W
2
1
R2476
SOT23
2N3904LF
MPIC_SB
2
3
1
Q2476
1/16W
5%
402
MF-LF
10K
MPIC_SB
21
R2475
MPIC_SB
0
MF-LF
402
5%
1/16W
21
R2478
1/16W
5%
402
MF-LF
0
MPIC_NB
2
1
R2479
1/16W
5%
402
MF-LF
0
NO STUFF
21
R2407
10K
MPIC_NB
21
R2408
MPIC_NB
21
R2409
MPIC_NB
21
R2412
1/16W
5%
402
MF-LF
MPIC_NB
21
R2418
1/16W
5%
402
MF-LF
10K
21
R2419
SM
2
1
XW2400
SM
P4MM
1
PP2400
SM
P4MM
1
PP2405
SM
P4MM
1
PP2406
I586
I587
I588
I589
I590
I591
I592
I593
I594
I595
I596
I597
I598
I599
I600
I601
33
63
RP2410
33
54
RP2410
33
81
RP2420
33
72
RP2410
33
63
RP2420
33
81
RP2410
33
63
RP2430
33
72
RP2430
33
54
RP2430
33
81
RP2430
33
72
RP2420
33
54
RP2420
1/16W
5%
402
MF-LF
0
21
R2402
1/16W
5%
402
MF-LF
0
21
R2432
24
19
051-6790
154
SYNC_MASTER=FINO-ME
SYNC_DATE=06/20/2005
Shasta Serial / Misc
ABBREV=DRAWING
TITLE=KILOHANA
SB_CPU_VDNAP2
NB_SLOT_RESET_L
PCI_AIRPORT_INT_L
NB_SLOT_RESET_L_R
SB_PCI_SEL32BIT
RAI_EXP_INTR_L<3>
RAI_EXP_INTR_L<0>
=PP3V3_PWRON_SB
MIN_LINE_WIDTH=0.50mm
MIN_NECK_WIDTH=0.38mm
PP1V2_PWRON_SB_PLL45VDD
VOLTAGE=1.2V
PCI_AIRPORT_INT_L
P3MM SPACING
I2S1_DEV_TO_SB_DTI
I2S1_RESET_L
CPU_A0_INT_R_L
NB_CPU_A0_INT_L
AUDIO
I2S0_TO_DEV
I2S0_MCLK
I2S0_MCLK
I2S0_BITCLK
I2S0_MCLK_R
I2S2_SB_TO_DEV_DTO_R
I2S2_MCLK_R
I2S2_BITCLK_R
I2S2_SYNC_R
I2S2_SB_TO_DEV_DTO
I2S1_SYNC_R
I2S1_BITCLK_R
I2S1_MCLK_R
I2S1_SB_TO_DEV_DTO_R
I2S1_SYNC
I2S1_BITCLK
I2S1_MCLK
I2S1_SB_TO_DEV_DTO
I2S0_SYNC_R
I2S0_BITCLK_R
I2S0_SB_TO_DEV_DTO_R
I2S0_SYNC
I2S0_SB_TO_DEV_DTO
PCI_USB2_INT_L
P3MM SPACING
SB_CPU_A1_SRESET_L
P3MM SPACING
P3MM SPACING
SB_CPU_B0_SRESET_L
P3MM SPACING
SB_CPU_B1_SRESET_L
=PP2V5_PWRON_SB
I2S0_DEV_TO_SB_DTI
I2S1_RESET_L
P3MM SPACING
SB_GPIO_H_3
=PP3V3_RUN_SB_PCI
NB_TO_SB_INT
SB_CPU_A0_INT_L
NB_INT_L_R
=PP3V3_RUN_SB_PCI
MAKE_TBEN_SYNC_L
SYS_OVERTEMP_L
PCI_USB2_INT_L
PCI_AIRPORT_INT_L
I2S1_RESET_L
SB_CPU_A0_INT_L
SB_CPU_A1_INT_L
SB_CPU_B0_INT_L
SB_CPU_B1_INT_L
RAI_ALERT_L
SB_CLK18M_XTALO
PP_1V2PWRONSBPLL45VDD
ENET_ENERGYDET
FW_LOWPWR
ENETFW_RESET
MAKE_TBEN_SYNC_L
SMU_TO_SB_INT_L
SYS_SLEWING_L
RAI_FATAL_L
GIGE_P2_INTB_L
GIGE_P1_INTA_L
FW_LOWPWR_R
=PP3V3_PWRON_SB
NB_CHP_FLT_N_B
SB_CPU_VDNAP1
SB_TO_SMU_INT_L
SB_VDNAP0
SB_GPIO14
SB_CPU_VDNAP2
LOGIC_BRD_GOOD
SYS_OVERTEMP_L
MB_SLOT_RESET_L
NB_SLOT_RESET_L
PCIX_INT_L
=PP1V2_PWRON_SB
SB_SFC_RESET_L
I2S2_TO_SB
I2S2_DEV_TO_SB_DTI
0.38mm SPACING
SB_CLK18M_XTALO
I2S2_SYNC
I2S2_BIDIR
I2S1_BIDIR
I2S1_SYNC
I2S1_BIDIR
I2S1_BITCLK
0.25mm SPACING
I2S1_TO_DEV
I2S1_MCLK
I2S0_BIDIR
I2S0_BITCLK
I2S0_TO_SB
I2S0_DEV_TO_SB_DTI
0.38mm SPACING
SB_CLK25M_ATA
SB_CLK25M_SATA
0.38mm SPACING
SB_CLK18M_XTALO_R
0.25mm SPACING
I2S2_TO_DEV
I2S2_MCLK
I2S0_TO_DEV
I2S0_SB_TO_DEV_DTO
I2S1_TO_DEV
I2S1_SB_TO_DEV_DTO
SB_CLK18M_XTALI
0.38mm SPACINGSB_CLK18M_XTAL
I2S0_BIDIR
I2S0_SYNC
I2S1_TO_SB
I2S1_DEV_TO_SB_DTI
I2S2_TO_DEV
I2S2_SB_TO_DEV_DTO
TP_SB_FSTEST
=PP3V3_PWRON_SB
MIN_NECK_WIDTH=0.38mm
MIN_LINE_WIDTH=0.50mm
PP1V2_PWRON_SB_PLL49VDD
VOLTAGE=1.2V
SB_CPU_B0_SRESET_L
SB_CPU_B1_SRESET_L
SB_CPU_A1_SRESET_L
SB_CPU_A0_SRESET_L
SB_CPU_B1_INT_L
SB_CPU_B0_INT_L
SB_CPU_A1_INT_L
SB_CPU_A0_INT_L
AUDIO_MIC_ID
AUDIO_HP_DET_L
AUDIO_LI_OPTICAL_PLUG_L
AUDIO_LO_DET_L
AUDIO_LO_OPTICAL_PLUG_L
ENET_ENERGYDET
MAKE_TBEN_SYNC_L
PCI_USB2_INT_L
ENETFW_RESET
FW_LOWPWR_R
RAI_FATAL_L
RAI_ALERT_L
GIGE_P2_INTB_L
GIGE_P1_INTA_L
RAI_EXP_INTR_L<1>
RAI_EXP_INTR_L<2>
PCIX_INT_L
SB_GPIO14
MB_SLOT_RESET_L
SYS_OVERTEMP_L
SB_VDNAP0
LOGIC_BRD_GOOD
SB_TO_SMU_INT_L
SB_CPU_VDNAP1
NB_CHP_FLT_N_B
SB_CLK25M_SATA
SB_CLK18M_XTALO_R
SB_CLK18M_XTALI
SB_TEST_MODE_PD
TP_SB_PLLTEST
JTAG_SB_TMS
JTAG_SB_TDI
JTAG_SB_TDO
JTAG_SB_TCK
TP_SB_WATCHDOG
I2C_SB_SDA
I2C_SB_SCL
SB_GPIO_H_3
I2S0_RESET_L
MIN_NECK_WIDTH=0.38mm
MIN_LINE_WIDTH=0.50mm
PP2V5_PWRON_SB_XTALVDD
VOLTAGE=2.5V
MIN_NECK_WIDTH=0.38mm
MIN_LINE_WIDTH=0.50mm
PP2V5_PWRON_SB_XTAL18VDD
VOLTAGE=2.5V
SB_STOPXTALS_L
SMU_SUSPENDREQ_L
SB_SUSPENDACK_L
SYS_PME_L
JTAG_SB_TRST_L
SYS_SLEWING_L
NB_TO_SB_INT
SMU_TO_SB_INT_L
SB_SFC_RESET_L
NET_SPACING_TYPE=P3MM SPACING
P3MM SPACING
I2S0_RESET_L
SB_CPU_B0_INT_L
P3MM SPACING
SB_CPU_B1_INT_L
P3MM SPACING
P3MM SPACING
MB_SLOT_RESET_L
P3MM SPACING
SB_CPU_A0_SRESET_L
SB_CPU_A0_INT_L
P3MM SPACING
NB_TO_SB_INT
P3MM SPACING
NB_SLOT_RESET_L
P3MM SPACING
I2S2_RESET_L
P3MM SPACING
I2S2_SYNC
I2S2_RESET_L
I2S2_BITCLK
=PP3V3_PWRON_SB
SHASTA_SYS_IO_RESET_L
SYS_IO_RESET_L
I2S2_DEV_TO_SB_DTI
I2S2_MCLK
SB_CPU_A1_INT_L
P3MM SPACING
I2S2_BIDIR
I2S2_BITCLK
AUDIO_LI_DET_L
AUDIO_SPKR_ID
AUDIO_SPDIFIN_INT_L
AUDIO_HP_MUTE_L
AUDIO_LO_MUTE_L
AUDIO_SPKR_MUTE_L
AUDIO_EXT_MCLK_SEL
LAST_MODIFIED=Tue Aug 30 17:23:23 2005
119
119
119
119
56
56
56
56
24
138
93
50
24
93
24
93
50
24
122
23
119
28
28
23
28
23
28
43
28
23
119
28
24
121
20
121
24
24
154
154
147
154
24
24
24
24
147
147
122
56
56
56
23
147
24
24
24
24
122
121
24
132
24
26
20
28
28
31
143
28
24
24
154
154
24
24
24
147
147
26
154
147
24
147
24
154
20
56
56
56
56
132
122
24
143
24
31
28
28
26
147
30
122
20
26
147
56
24
154
154
154
154
20
30
154
154
154
24
20
24
20
20
7
24
8
8
56
42
24
24
24
24
8
8
8
8
24
24
24
24
24
24
7
24
8
24
7
24
24
7
24
20
24
24
8
24
24
24
24
24
24
6
24
139
17
24
24
24
24
24
24
24
7
24
24
24
24
24
24
24
20
24
20
24
7
24
24
24
24
8
8
8
24
24
24
24
24
24
8
24
24
8
24
6
7
24
24
24
24
24
24
24
24
154
154
154
153
153
24
24
24
17
24
24
24
24
24
20
20
24
24
24
20
24
24
24
24
24
24
24
24
6
20
20
20
20
9
39
39
24
24
28
28
28
28
9
24
24
24
24
24
24
24
24
24
24
24
20
24
24
24
24
7
28
24
24
24
24
153
153
154
154
150
152
154
Preliminary
VDD_OVDD_2
VDD_OVDD_3
VDD_OVDD_5 VSS_OVDD_5
VSS_OVDD_3
VSS_OVDD_1VDD_OVDD_1
VDD_33_XTAL
VDD_OVDD_4 VSS_OVDD_4
VSS_15_C4
VSS_OVDD_2
VSS_15_PLL2VDD_15_PLL2
VDD_15_12_4
VDD_15_C4
VDD_15_PLL1
VSS_33_XTAL
VSS_15_PLL1
VDD_33_I VSS_33_I
VSS_12_6
VDD_15_C1
VDD_12_5
VSS_25
VSS_15_C3VDD_15_C3
VDD_25
VSS_12_5
VSS_33_BC
VSS_12_4VDD_12_4
VSS_15_PLL4
VSS_12_1
VSS_12_2
VDD_33_BC
VDD_12_1
VSS_15_C2
VDD_12_2
VDD_12_3 VSS_12_3
VDD_15_PLL4
VDD_15_C2
VDD_15_PLL3 VSS_15_PLL3
VDD_15_12_1
VDD_15_12_2
VDD_15_12_3
SHARED PIN
SYM 2 OF 2
VSS_15_C1
PP
PP
PP
PP
PP
PP
PP
PP
PP
DRAWING
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
Q63 APPLICATION IS RUN
Q63 APPLICATION IS POWER ON
Q63 APPLICATION IS RUN
PLACE NEAR PULSAR2
PLACE NEAR PULSAR2
PLACE NEAR PULSAR2
PLACE NEAR PULSAR2
PLACE NEAR PULSAR2
ON IN SLEEP
ON IN SLEEP
PLL_VDD ON IN SLEEP
Q63 APPLICATION IS PWRON
1/16W
5%
402
MF-LF
4.7
21
R2501
BGA
PULSAR2
SEE_TABLE
A3
B5
A7
B7
B10
D11
E1
K2
G1
L8
M4
D1
D12
C8
G11
M6
E12
J10
K11
M12
K8
K4
A1
B4
A5
C9
B11
B12
C2
L2
G2
K9
L4
D2
D10
B8
F11
L6
F2
C5
A9
J11
K5
H11
K12
M10
M7
M3
U2500
1/16W
5%
402
MF-LF
0
21
R2510
1/16W
5%
402
MF-LF
0
NOSTUFF
21
R2511
20%
402
CERM
0.1UF
10V
2
1
C2572
20%
402
CERM
0.1UF
10V
2
1
C2573
1/16W
5%
402
MF-LF
0
21
R2512
1/16W
5%
402
MF-LF
0
21
R2513
1/16W
5%
402
MF-LF
0
21
R2514
1/16W
5%
402
MF-LF
0
21
R2515
1/16W
5%
402
MF-LF
0
21
R2516
20%
402
CERM
0.1UF
10V
2
1
C2501
20%
402
CERM
0.1UF
10V
2
1
C2575
SM
2
1
XW2500
SM
P4MM
1
PP2500
SM
2
1
XW2501
SM
2
1
XW2502
SM
2
1
XW2503
SM
P4MM
1
PP2501
SM
P4MM
1
PP2502
P4MM
SM
1
PP2503
SM
P4MM
1
PP2506
SM
P4MM
1
PP2505
P4MM
SM
1
PP2507
SM
P4MM
1
PP2504
P4MM
SM
1
PP2508
1/16W
5%
402
MF-LF
4.7
21
R2503
1/16W
5%
402
MF-LF
4.7
21
R2505
20%
402
CERM
0.1UF
10V
2
1
C2505
0603
180-OHM-1.5A
21
L2501
20%
402
CERM
0.1UF
10V
2
1
C2509
20%
402
CERM
0.1UF
10V
2
1
C2511
0603
180-OHM-1.5A
21
L2503
20%
402
CERM
0.1UF
10V
2
1
C2513
0603
180-OHM-1.5A
21
L2505
20%
402
CERM
0.1UF
10V
2
1
C2515
0603
180-OHM-1.5A
21
L2507
20%
402
CERM
0.1UF
10V
2
1
C2517
20%
402
CERM
0.1UF
10V
2
1
C2519
20%
402
CERM
0.1UF
10V
2
1
C2522
1/16W
5%
402
MF-LF
4.7
21
R2507
0603
180-OHM-1.5A
21
L2509
20%
402
CERM
0.1UF
10V
2
1
C2520
20%
402
CERM
0.1UF
10V
2
1
C2527
20%
402
CERM
0.1UF
10V
2
1
C2528
20%
402
CERM
0.1UF
10V
2
1
C2529
10V
0.1UF
CERM
402
20%
2
1
C2530
20%
402
CERM
0.1UF
10V
2
1
C2551
20%
402
CERM
0.1UF
10V
2
1
C2523
20%
402
CERM
0.1UF
10V
2
1
C2524
20%
402
CERM
0.1UF
10V
2
1
C2525
20%
402
CERM
0.1UF
10V
2
1
C2526
20%
402
CERM
0.1UF
10V
2
1
C2531
20%
402
CERM
0.1UF
10V
2
1
C2532
20%
402
CERM
0.1UF
10V
2
1
C2533
20%
402
CERM
0.1UF
10V
2
1
C2534
10V
0.1UF
CERM
402
20%
2
1
C2535
10V
0.1UF
CERM
402
20%
2
1
C2536
10V
0.1UF
CERM
402
20%
2
1
C2537
10V
0.1UF
CERM
402
20%
2
1
C2538
10V
0.1UF
CERM
402
20%
2
1
C2574
1/16W
5%
402
MF-LF
4.7
21
R2509
20%
603
CERM1
2.2UF
6.3V
2
1
C2545
20%
603
CERM1
2.2UF
6.3V
2
1
C2569
20%
603
CERM1
2.2UF
6.3V
2
1
C2503
20%
603
CERM1
2.2UF
6.3V
2
1
C2507
20%
603
CERM1
2.2UF
6.3V
2
1
C2521
ABBREV=DRAWING
TITLE=KILOHANA
PULSAR2 POWER
SYNC_DATE=08/01/2005
SYNC_MASTER=Q63
051-6790
19
154
25
=PPOVDD_PULSAR
=PP1V5_PWRON_PULSAR
=PP2V5_PWRON_PULSAR
=PPOVDD_PULSAR
PP1V5_PSL_PLL3
VOLTAGE=1.5V
MIN_LINE_WIDTH=0.64mm
MIN_NECK_WIDTH=0.2MM
PP1V5_PSL_PLL4
VOLTAGE=1.5V
MIN_LINE_WIDTH=0.64mm
MIN_NECK_WIDTH=0.2MM
PP1V5_PSL_PLL1
VOLTAGE=1.5V
MIN_LINE_WIDTH=0.64mm
MIN_NECK_WIDTH=0.2MM
MIN_NECK_WIDTH=0.22MM
MIN_LINE_WIDTH=0.64MM
VOLTAGE=3.3V
PP3V3_PLSR_I
PP_1V5PWRONPULSAR2
NO_TEST=YES
PP_OVDD_PULSAR1
PP3V3_PLSR_I
=PP2V5_PWRON_PULSAR
=PP1V2_PWRON_PULSAR
=PP3V3_RUN_PULSAR
C2569_1
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.5MM
C2503_1
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.5MM
C2507_1
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.5MM
C2521_1
=PP3V3_PWRON_PULSAR
=PP1V5_PWRON_PULSAR
=PP1V5_PULSAR
=PP1V2_PWRON_PULSAR
=PP1V5_PULSAR
=PP1V5_PWRON_PULSAR
PP_1V2PWRONPULSAR1
PP_1V5PULSAR2
VOLTAGE=1.5V
MIN_LINE_WIDTH=0.64mm
MIN_NECK_WIDTH=0.2MM
PP1V5_PSL_PLL2
PP3V3_PSL_XTAL
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.64mm
MIN_NECK_WIDTH=0.2MM
=PP3V3_PWRON_PULSAR
=PP3V3_PWRON_PULSAR
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.5MM
C2545_1
LAST_MODIFIED=Tue Aug 30 17:23:24 2005
25
25
25
25
26
26
25
25
25
25
25
25
25
25
25
25
7
7
7
7
25
6
6
25
7
7
7
7
7
7
7
7
7
6
6
7
7
Preliminary
XIN
GPCLK33_F1
GPCLK33_F2
GPCLK33_F0
GPCLK33_E1
GPCLK33_E0
GPCLK25_F0
GPCLK25_F1
GPCLK25_E0
GPCLK25_E1
HTBEN_1
HTBEN_0
SLEWING*
HCLKN_2
HCLKN_1
HCLKP_0
HSYNC_2
SCLK
SDATA
HCLKP_2
HCLKN_0
HSYNC_1
PD
HSYNC_0
XOUT
HCLKP_1
RESET*
OEMODE
TEST_MODE
GPCLK12_C0
REF_25
REF_15
REF_33
GPCLK12P_A1
GPCLK12P_B0
GPCLK12N_A0
GPCLK12N_A1
GPCLK12N_B0
GPCLK12P_A0
ASEL_INT*
GPCLK12P_C0
GPCLK12N_C0
GPCLK12P_C1
GPCLK12N_C1
GPCLK12P_C2
GPCLK12N_C2
GPCLK12P_C3
GPCLK12N_C3
GPCLK12P_C4
GPCLK12N_C4
GPCLK12P_D0
GPCLK12N_D0
SYM 1 OF 2
PP
PP
PP
DRAWING
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
33MHZ, 3.3V
33MHZ, 3.3V
PLACE ALL 0-OHM SERIES RESISTORSRES
ON THIS PAGE NEAR PULSAR
PULLED UP TO PP3V3_RUN ON P.28
1.5VOVDD
1.5VOVDD
33MHZ, 3.3V
66MHZ, 3.3V
66MHZ, 3.3V
25MHZ, 2.5V
25MHZ, 2.5V
25MHZ, 2.5V
25MHZ, 2.5V
66MHZ, 1.2V
66MHZ, 1.2V
66MHZ, 1.2V
100MHZ, 1.2V
100MHZ, 1.2V
100MHZ, 1.2V
100MHZ, 1.2V
100MHZ, 1.2V
100MHZ, 1.2V
100MHZ, 1.2V
100MHZ, 1.2V
100MHZ, 1.2V
300MHZ, 1.2V
300MHZ, 1.2V
200MHZ, 1.2V
200MHZ, 1.2V
200MHZ, 1.2V
200MHZ, 1.2V
(100MHZ FOR ASPEN)
66MHZ, 1.5VOVDD
200MHZ, 1.5VOVDD
200MHZ, 1.5VOVDD
200MHZ, 1.5VOVDD
LAST MODIFIED: APR 26, 04
200MHZ, 1.5VOVDD
200MHZ, 1.5VOVDD
MB_PCIX_REFCLK
QUASAR CLOCKS ARE RESISTOR DIVIDED DOWN
REMOVED R2632 AND R2630
FROM UNUSED CLOCKS FOR EMC
1.5VOVDD
66MHZ, 1.5VOVDD
TO 1.8V ON QUASAR PAGES
200MHZ, 1.5VOVDD
BGA
PULSAR2
C11
C12
E3
A12
B2
B1
C3
L1
F1
H10
C1
E2
A10
A11
C10
B9
A8
B3
C4
A6
A2
A4
B6
M2
M1
K1
J2
J1
J3
H2
H3
H1
E10
G12
K10
L11
L10
M9
L7
M5
K3
E11
F12
J12
L12
M11
L9
M8
L5
L3
H12
D3
U2500
1/16W
5%
402
MF-LF
0
21
R2654
5%
402
MF-LF
0
1/16W
21
R2656
5%
1/16W
402
MF-LF
0
NO STUFF
21
R2652
1/16W
402
330K
NO STUFF
5%
MF-LF
21
R2658
CRITICAL
25.0000M
8X4.5MM-SM2
21
Y2601
402
5%
50V
33PF
CERM
2
1
C2605
5%
402
CERM
50V
33PF
2
1
C2607
1/16W
402
MF-LF
24
NOSTUFF
5%
2
1
R2662
F-ST-SM
U.FL-R_SMT
NOSTUFF
1
2
3
J2600
1/16W
5%
402
MF-LF
24
NOSTUFF
2
1
R2664
1/16W
1%
402
MF-LF
1K
2
1
R2625
MF-LF
402
1/16W
1%
1K
2
1
R2626
1/16W
1%
402
MF-LF
1K
2
1
R2627
5%
402
0
21
R2612
1/16W
5%
402
MF-LF
10K
2
1
R2613
1/16W
1%
402
MF-LF
1K
NOSTUFF
2
1
R2618
NOSTUFF
1/16W
1%
402
MF-LF
1K
2
1
R2621
1/16W
5%
402
MF-LF
NOSTUFF
10K
2
1
R2614
1/16W
5%
402
MF-LF
0
2
1
R2623
1/16W
5%
402
MF-LF
10K
2
1
R2616
1/16W
5%
402
MF-LF
0
21
R2628
0
402
5%
1/16W
MF-LF
21
R2631
1/16W
5%
402
MF-LF
0
21
R2635
1/16W
5%
402
MF-LF
0
21
R2636
1/16W
5%
402
0
MF-LF
21
R2641
1/16W
5%
402
MF-LF
0
21
R2643
1/16W
5%
402
MF-LF
0
21
R2645
1/16W
5%
402
MF-LF
0
21
R2647
1/16W
5%
402
MF-LF
0
21
R2649
1/16W
5%
402
MF-LF
0
21
R2651
1/16W
5%
402
0
MF-LF
21
R2653
0
402
MF-LF
1/16W
5%
21
R2655
0
MF-LF
402
5%
1/16W
21
R2657
0
5%
402
MF-LF
1/16W
21
R2659
1/16W
5%
402
MF-LF
0
21
R2660
1/16W
402
MF-LF
0
5%
21
R2663
1/16W
5%
402
MF-LF
0
21
R2665
1/16W
5%
402
MF-LF
0
21
R2637
1/16W
5%
402
MF-LF
0
21
R2639
1/16W
402
MF-LF
0
5%
21
R2634
402
5%
1/16W
0
MF-LF
21
R2633
1/16W
5%
402
0
MF-LF
21
R2629
1/16W
5%
402
MF-LF
0
21
R2668
1/16W
5%
402
MF-LF
0
21
R2669
1/16W
5%
402
MF-LF
0
21
R2670
5%
402
MF-LF
0
1/16W
21
R2671
1/16W
5%
402
MF-LF
0
21
R2672
1/16W
5%
402
MF-LF
0
21
R2673
1/16W
5%
402
MF-LF
0
21
R2666
5%
1/16W
402
MF-LF
0
21
R2667
402
0
MF-LF
1/16W
5%
21
R2675
1/16W
5%
402
MF-LF
0
21
R2674
5%
402
0
21
R2600
SM
P4MM
1
PP2602
P4MM
SM
1
PP2600
P4MM
SM
1
PP2601
ABBREV=DRAWING
TITLE=KILOHANA
SYNC_DATE=06/20/2005
SYNC_MASTER=FINO-ME
26
051-6790
19
154
PULSAR2 CLOCKS
EI_NB_SYSCLK_P
SYS_SLEWING_L_R
CPU_A_APSYNC_R
GFX_SLOT_PCIE_REFCLK_N_C
CLK_RAIREF_200M_N_R
NB_PMR_CLK_N
CLK_RAI_200M_P<0>
NB_DDR_REFCLK_N
PCIE_C_REFCLKIN_P_C
PCIE_C_REFCLKIN_N_C
PCIE_A_REFCLKIN_N_C
NB_PMR_CLK_P_R
CPU_A_TBEN_CLK_R
CPU_B_TBEN_CLK_R
CPU_B_APSYNC_R
CPU_A_APSYNC
MAKE_BASE=TRUE
NC_CPU_B_TBEN_CLK_US
EI_NB_SYSCLK_N
NB_PCIE_REFCLK_P_C
EI_CPU_B_SYSCLK_N
NB_APSYNC_R
HT_SB_REFCLK_R
HT_NB_REFCLK_L0_R
CPU_B_APSYNC
NB_APSYNC
QUA0_REF_25MHZ_R
QUA1_REF_25MHZ_R
PCI_CLK66M_SB_INT_R
PLSR2_OEMODE
EI_CPU_A_SYSCLK_P
EI_CPU_A_SYSCLK_N
EI_CPU_B_SYSCLK_P
HT_CLK66M_SB
HT_NB_REFCLK_H0_R
CLK_RAIREF_200M_P_R
HT_NB_REFCLK_P<0>
PLSR2_PD
PLS2_X_IN_B
PLS2_X_OUT_B
NB_DDR_REFCLK_P_R
PCIE_B_REFCLKIN_N_C
PCIE_A_REFCLKIN_P_C
NB_PMR_CLK_N_R
SB_CLK25M_SATA
PCI_CLK33M_SB_EXT_R
CLK_RAI_REFCLK_66M_R
SB_AIRPRT_CLK_33MHZ_R
NB_DDR_REFCLK_N_R
CLK_RAI_GIGE_25MHZ
PCI_CLK33M_SB_EXT_RR
RAM_ARB0_REF25MHZ
PCI_CLK66M_SB_INT
CLK_RAI_GIGE_25MHZ_R
CLK_RAI_PCIEB_N<0>
HT_NB_REFCLK_N<0>
CLK_KOD_100M_P<0>
PCIE_B_REFCLKIN_P_C
CLK_RAI_PCIEA_P<0>
CLK_RAI_PCIEC_N<0>
CLK_RAI_PCIEC_P<0>
CLK_RAI_PCIEB_P<0>
CLK_RAI_PCIEA_N<0>
NB_PCIE_REFCLK_N_C
GFX_SLOT_PCIE_REFCLK_P_C
SB_USB2_CLK_33MHZ_R
NB_DDR_REFCLK_P
PLS2_INTERM
PCI_CLK33M_USB2
CLOCK_RESET_L
NB_PMR_CLK_P
PLS2_REF33
PLS2_REF25
SB_CLK25M_SATA_R
SYS_SLEWING_L
CPU_A_TBEN_CLK_US
CLK_RAI_200M_N<0>
CLK_KOD_100M_N<0>
CLK_PCIE_SLOTA_P<0>
CLK_PCIE_SLOTA_N<0>
RAM_ARB1_REF25MHZ
PLS2_EXTCLK
I2C_CLOCK_B_SDA
SYS_SLEEP
PLS2_REF15
PP3V3_PLSR_I
PLSR2_TM
I2C_CLOCK_B_SCL
PLSR2_ASEL_INT_L
PLS2_RESET_L
PLS2_X_IN
PCI_CLK33M_AIRPORT
PLS2_X_OUT
CLK_RAI_REFCLK_66M
LAST_MODIFIED=Tue Aug 30 17:23:25 2005
54 30 16 15
50
13
56
27
56
56
101
119
119
101
97
27
28
97
97
97
12
42
9
9
9
20
27
59
9
9
9
9
9
9
9
56
6
42
9
27
9
9
9
27
42
9
9
6
56
56
27
103
9
9
98
9
9
9
9
24
9
9
9
9
27
27
27
27
9
27
98
82
9
27
27
27
27
27
9
9
9
59
27
28
20
9
24
56
27
82
84
84
27
39
11
25 39
121
27
Preliminary
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
ELECTRICAL_CONSTAINT_SET
NET_SPACING_TYPE
NOTE:
CLOCK CONSTRAINTS
N/C QUASAR CLOCKS
N/C ALIASES
N/C CPUB CLOCKS
N/C RAINIER CLOCKS
DIFFERENTIAL_PAIR NET_PHYSICAL_TYPE
RESPECTIVE BUS PAGES
ALL OTHER CLOCK CONTRAINTS ON THEIR
I67
I68
I69
I70
SYNC_DATE=06/20/2005
051-6790
19
27
154
Pulsar Aliases
SYNC_MASTER=FINO-ME
PCI_CLK_SBPCI_CLK_SB
PCI_CLK_SB_CAP
PCI_CLK33M_SB_EXT_RR
PCI_CLK_SB
PCI_CLK_SB
P3MM SPACING
PCI_CLK66M_SB_INT
NB_PMR_CLK
NB_PMR_CLK_SP
NB_PMR_CLK
NB_PMR_CLK
NB_PMR_CLK_N
NB_PMR_CLK
NB_PMR_CLK_SP
NB_PMR_CLK
NB_PMR_CLK
NB_PMR_CLK_P
MAKE_BASE=TRUE
NC_CPU_B_APSYNC
MAKE_BASE=TRUE
NC_EI_CPU_B_SYSCLK_P
MAKE_BASE=TRUE
NC_EI_CPU_B_SYSCLK_N
MAKE_BASE=TRUE
NC_CLK_RAI_GIGE_25MHZ
MAKE_BASE=TRUE
NC_RAM_ARB1_REF25MHZ
RAM_ARB1_REF25MHZ
MAKE_BASE=TRUE
NC_RAM_ARB0_REF25MHZ
RAM_ARB0_REF25MHZ
CPU_B_APSYNC
EI_CPU_B_SYSCLK_N
EI_CPU_B_SYSCLK_P
MAKE_BASE=TRUE
NC_CLK_RAI_PCIEC_N<0>
CLK_RAI_PCIEC_N<0>
MAKE_BASE=TRUE
NC_CLK_RAI_PCIEC_P<0>
CLK_RAI_PCIEC_P<0>
CLK_RAI_200M_P<0>
CLK_RAI_REFCLK_66M
CLK_RAI_PCIEB_P<0>
MAKE_BASE=TRUE
NC_CLK_RAI_PCIEB_P<0>
CLK_RAI_PCIEB_N<0>
MAKE_BASE=TRUE
NC_CLK_RAI_PCIEB_N<0>
CLK_RAI_PCIEA_P<0>
MAKE_BASE=TRUE
NC_CLK_RAI_PCIEA_P<0>
CLK_RAI_PCIEA_N<0>
MAKE_BASE=TRUE
NC_CLK_RAI_PCIEA_N<0>
MAKE_BASE=TRUE
NC_CLK_RAI_200M_P<0>
CLK_RAI_GIGE_25MHZ
MAKE_BASE=TRUE
NC_CLK_RAI_200M_N<0>
CLK_RAI_200M_N<0>
=PCI_CLK33M_USB2
MAKE_BASE=TRUE
PCI_CLK33M_USB2
MAKE_BASE=TRUE
NC_CLK_RAI_REFCLK_66M
119
119
26
26
26
26
20
20
6
6
6
6
6
26
6
26
26
26
26
6
26
6
26
26
26
26
6
26
6
26
6
26
6
6
26
6
26
122
26
6
Preliminary
P9[7]
P9[6]
P9[5]
P8[7]
P8[6]
P8[5]
P3[7]
P3[6]
P3[5]
P3[4]
P2[6]
P2[7]
P2[4]
P2[5]
P1[4]
P1[3]
P1[2]
P1[1]
P1[0]
P0[4]
P0[0]
P0[2]
P0[3]
P0[1]
P0[7]
P0[6]
P0[5]
P3[3]
P3[2]
P3[1]
P3[0]
P2[3]
P2[2]
P2[1]
P2[0]
P1[5]
P1[6]
P1[7]
PCNVSS
RESET*
XOUT
VREF
XIN
P7[7]
P7[6]
P7[5]
P7[4]
P7[3]
P7[2]
P7[1]
P7[0]
P6[7]
P6[6]
P6[5]
P6[4]
P6[3]
P6[2]
P6[1]
P6[0]
P10[0]
P10[1]
P9[3]
P9[2]
P9[1]
P9[0]
P8[4]
P8[3]
P8[2]
P8[1]
P8[0]
P10[6]
P10[7]
P10[2]
P10[3]
P10[4]
P10[5]
VCC
AVSS
VSS
AVCC
SQW/
OUT
VBAT
SDA
SCL
X1
X2
GND
VCC
PP
PP
PP
PP
PP
DRAWING
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
ELECTRICAL_CONSTRAINT_SET
- =PP3V3_ALL_SMU
- =PP3V3_ALL_RTC
- =PP3V3_PWRON_SMU
- =PPVREF_SMU (SMU AVCC OR 2.5V REFERENCE)
DIFFERENTIAL_PAIR
NET_SPACING_TYPE
SMU Pull-ups / pull-down
7.4
Y2800’S LOAD CAPACITANCE IS 12PF
NET_SPACING_TYPE
ELECTRICAL_CONSTRAINT_SET
DIFFERENTIAL_PAIR
Y Y
AN23
TA1in
Y Y
8.5
10.7
3.3
3.2
3.1
3.0
Y
Y Y Y Y
Y Y
AN01
AN00
Y
Y S
N
KI2*
SDAmm
IOC4
Keep crystal subcircuit close to SMU.
INT3*
TB0in
TB1in
SCLmm
Y
Y
Y
N
circuit, but be aware that this will
reference used by monitoring
SMU_VREF should be same signal or
100K/10uF RC filter at SMU pins.
(CPU_SENSE_I/CPU_SENSE_V) requires
Signal aliases required by this page:
Power aliases required by this page:
Page Notes
INT1*
INT0*
TA4in
TA4out
CLK0
TXD0
RTS1*
(BUSY)
TXD1
SCL
TA1out
Y
S
Y
Y
7.2
6.0
6.2
6.1
Port
6.3
6.4
Port
Alternate Functions
NC
Real Time Clock
Tower & Server
YY NN
Entry Desktop
Server
Desktop
Consumer
S
Entry Desktop
Y
Consumer
Portable
Server
YY
N = Alternate function
S
S
S
N
N
SSYYYY
YY
Y Y N
Y
Y
Y
Y
Y
YYY
Y Y Y
YYY
Y Y
Y
Y
Y
N
Y
N
Y YYN
YSY
NY
Y
Y
Y
Y Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
SDA
Y
Y
Y
N
Y
Y
Y
Y
TA2out
TA3out
TA3in
S SS S
Y
Y
Y YYY
YYYY
Y
SSYY
Y
Y
Y
Y
S
Y
Y
Y
Y
YYY
Y
Y
YSY
Y
Y
YY
S S
S Y Y S
S S
Y Y YY
Y
Y
Y
Y
YYY
YY Y
YY Y
YYY
Y
Y Y Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
NMI*
TB2in
AN24
CE*
INT2*
AN25
S
S
Y
Y
Y
Y
Y
Y
KI0*
AN3
AN1
AN0
KI1*
AN26
AN27
Y
S
Y Y Y
Y Y SY
Y
KI3*
AN03
AN20
AN04
AN05
IOC2
AN22
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
S
S
YY
S
SY
SY
YYY Y
SSN
N
YY
Y Y
YY
YY
Y
Y
YYYY
YYN S
YY
S
Y Y
Y
Y
S
Y Y
Y
N
N
Y Y
S
Y
Y YSN
Y
Y
Y Y
YYYY
Y
Y Y
Y
Y Y YY Y
Sout3
IOC5
IOC6
Sin3
IOC7
CLK3
IOC3
S
S
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
YYYY
S
S N
Y YNS
Y
Y
Y Y
Y
YYYY
Y
Y
Y
Y
YY
Y
Y
Y
YY
S S
S S
YY
SSY
Y
BOM options provided by this page:
NOTE: CPU current/voltage monitoring
(NONE)
(NONE)
Caps should connect to GND_SMU_AVSS.
NOTE: Pinout matches SMU pinout v1.51.
those capacitors are provided on
review the latest SMU specification
to ensure missing pull-ups are
reuire pull-ups that are not.
provided on this page. Please.
provided on another page.
signal (GND_SMU_AVSS). None of
a 100pF capacitor to the SMU AVSS
NOTE: All analog inputs to SMU should have
NOTE: Some primary and alternate functions
this page.
affect other analog inputs such as
AC adapter ID.
Y
Y
INT5*
TA2in
YY
S
Y
Y
Y
Y
Y
AN2
INT4*
AN21
AN07
AN06
S = Spare
(see aliases below)
Y = Primary function
RXD1
CTS0*
S
Desktop
RTS0*/
AN02
S
RXD0
Portable
Y
CLK1
PULLUP AT LEVEL SHIFTER P.30
DRIVEN PUSH/PULL
System Management Unit
P1[0] NOT USED --->
CRITICAL
10.0000M
8X4.5MM-SM
21
Y2800
SEE_TABLE
M30280F8-LF
QFP-80
10
12
11
77
13
9
79
80
1
2
3
4
5
7
8
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
40
41
42
43
32
33
34
35
36
37
38
39
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
68
69
70
71
72
73
74
76
59
60
61
62
63
64
65
66
67
6
75
78
U2800
CRITICAL
DS1338U-33
MSOP
2
1
8
3
7
5
6
4
U2801
6.3V
1uF
CERM
402
10%
2
1
C2825
10K
MF-LF
402
5%
1/16W
2
1
R2825
50V
18PF
CERM
402
5%
2
1
C2804
50V
18PF
CERM
402
5%
2
1
C2805
470
1/16W
5%
402
MF-LF
2
1
R2817
10M
MF-LF
402
5%
1/16W
21
R2816
10K
MF-LF
402
5%
1/16W
2
1
R2827
1/16W
1%
402
MF-LF
2.0K
21
R2812
1/16W
1%
402
MF-LF
2.0K
NOSTUFF
21
R2811
1/16W
5%
402
MF-LF
10K
NOSTUFF
21
R2813
1/16W
1%
402
MF-LF
100K
21
R2810
10K
1/16W
5%
402
MF-LF
21
R2802
10K
MF-LF
402
5%
1/16W
21
R2800
1/16W
5%
402
MF-LF
10K
12
R2804
10V
0.1uF
CERM
402
20%
2
1
C2809
10V
0.1uF
CERM
402
20%
2
1
C2808
0.1uF
10V
CERM
402
20%
2
1
C2802
0.1uF
20%
10V
CERM
402
2
1
C2801
805
10UF
6.3V
X5R
10%
2
1
C2800
6.3V
1uF
CERM
402
10%
2
1
C2803
4.7
MF-LF
402
5%
1/16W
21
R2815
SM
21
XW2800
CRITICAL
32.768K
SM-LF
4
1
Y2801
I456
I457
10K
1/16W
5%
402
MF-LF
21
R2801
P4MM
SM
1
PP2800
SM
2
1
XW2802
P4MM
SM
1
PP2801
SM
2
1
XW2801
SM
P4MM
1
PP2806
SM
P4MM
1
PP2805
P4MM
SM
1
PP2804
I472
I473
I474
I475
ABBREV=DRAWING
TITLE=KILOHANA
051-6790
19
28
154
SYNC_MASTER=Q63
SYNC_DATE=08/01/2005
System Management Unit
0.25MM SPACING
SYS_NORTH_RESET_L
SYS_NORTH_RESET_L
0.25MM SPACING
SMU_RESET
SYS_NORTH_RESET_L
SYS_NORTH_RESET_L
SYS_RESET_BUTTON_L
SYS_RESET_BUTTON_L
CLOCK_RESET_L
SB_CPU_VDNAP0_OR_QREQ_OR_SPDIF
SB_CPU_VDNAP1
SYS_SLOT_PWR
SMU_PWRSEQ_P9_6
SMU_FAN_RPM0
SB_CPU_VDNAP2
I2C_SMU_CPU_SCL_IN
I2C_SMU_CPU_SDA_IN
CPU_VID<0>
PP3V3_ALL_SMU_AVCC
MIN_LINE_WIDTH=0.38mm
MIN_NECK_WIDTH=0.2MM
VOLTAGE=3.3V
CPU_VID<3>
CPU_VID<4>
CPU_SENSE_I
CPU_TEMP
VOLTAGE=0V
GND_SMU_AVSS
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.38mm
0.38MM SPACING
SMU_CLK10M_XOUT_R
=PPVREF_SMU
SYS_POWER_BUTTON_L
NB_SUSPENDACK_L
SB_SUSPENDACK_L
SYS_LED
SYS_PME_L
SYS_SLEWING_L
I2C_SMU_CPU_SDA_OUT_L
SYS_POWERUP_L
MAKE_BASE=TRUE
SMU_BOOT_RXD
SMU_FAN_RPM2
SMU_FAN_RPM1
SMU_BOOT_CNVSS
SMU_BOOT_TXD
SMU_PWRSEQ_P1_2
SMU_PWRSEQ_P1_3
CPU_SENSE_V
CPU_BYPASS
SMU_FAN_RPM5
GND_SMU_AVSS
I2C_RTC_SCL
RTC_CLK32K_X2
RTC_CLK32K_X1
=PP3V3_ALL_RTC
=PP3V3_ALL_SMU
I2C_RTC_SDA
CPU_VID<3>
CPU_VID<4>
CPU_VID<0>
CPU_VID<1>
I2C_SMU_CPU_SCL_IN
SYS_POWERFAIL_L
SMU_SUSPENDREQ_L
DIAG_LED
I2C_SMU_A_SDA_OUT_L
SMU_FAN_TACH0
SYS_DOOR_AJAR_L
SMU_FAN_TACH9
SMU_PWRSEQ_P1_0
SMU_PWRSEQ_P1_1
I2C_SMU_CPU_SCL_OUT_L
SMU_PWRSEQ_P9_5
SB_STOPXTALS_L
SB_TO_SMU_INT_L
SMU_FAN_TACH8
SMU_SLEEP
I2C_SMU_B_SCL
I2C_SMU_B_SDA
CPU_VID<1>
CPU_VID<2>
SMU_FAN_RPM4
SMU_CLK10M_XOUT
SYS_OVERTEMP_L
I2C_SMU_E_SCL
SMU_FAN_TACH3
SMU_FAN_TACH7
SMU_FAN_TACH6
I2C_SMU_A_SCL_IN
I2C_SMU_A_SDA_IN
SMU_FAN_TACH5
SMU_FAN_TACH4
SMU_FAN_TACH2
SMU_FAN_TACH1
I2C_SMU_A_SDA_OUT_L
I2C_SMU_A_SCL_OUT_L
I2C_SMU_E_SDA
I2C_SMU_A_SCL_IN
I2C_SMU_A_SCL_OUT_L
I2C_SMU_CPU_SDA_OUT_L
I2C_SMU_CPU_SCL_OUT_L
SMU_BOOT_SCLK
CPU_VID<5>
SMU_BOOT_BUSY
MAKE_BASE=TRUE
NB_TDO_SMU
NB_TMS
NB_TCK
NB_TDI
RTC_CLK32K_X2
0.38MM SPACING
SMU_CLK10M_XOUT
0.38MM SPACING
SMU_FAN_PWM9
CPU_B_INSERTED_L
SMU_FAN_PWM8
CPU_A_INSERTED_L
SAT_MRESET_L
SMU_FAN_RPM7
SMU_FAN_RPM6
SMU_PWRSEQ_P1_4
SMU_FAN_RPM3
SMU_SER_SEL
RTC_CLK32K_X1
RTC_CLK32K_XTAL
0.38MM SPACING
I2C_SMU_A_SCL
I2C_SMU_A_SDA
I2C_SMU_A_SDA_IN
I2C_SMU_CPU_SDA_IN
CPU_VID<2>
=PP3V3_PWRON_SMU
=PP3V3_RUN_SMU
=PP2V5_PWRON_NB_MISC
SYS_PME_L
SYS_SLEWING_L
SMU_SUSPENDREQ_L
SMU_SLEEP
SYS_POWERUP_L
SMU_RESET
SYS_IO_RESET_L
0.25MM SPACING
=PP3V3_ALL_SMU
SMU_BOOT_CE
SMU_CLK10M_XIN
SMU_CLK10M_XTAL
0.38MM SPACING
PP_3V3ALLSMU
=PP3V3_ALL_SMU
PP_3V3ALLSMUAVCC
SMU_CLK10M_XOUT_R
SYS_POWER_BUTTON_L
SMU_IO_RESET_L
SMU_RESET_L
P3MM SPACING
SMU_IO_RESET_L
P3MM SPACING
CLOCK_RESET_L
P3MM SPACING
SYS_RESET_BUTTON_L
SMU_CLK10M_XIN
LAST_MODIFIED=Tue Aug 30 17:23:28 2005
85
85
50
50
50
28
29
43
39
50
43
28
122
29
29
55
29
122
28
12
55
28
30
93
43
30
30
122
28
30
12
119
28
28
29
30
30
30
30
29
29
28
31
31
31
31
31
28
28
28
26
31
7
29
29
29
28
7
31
31
31
31
31
28
31
31
30
31
31
24
31
31
31
31
31
31
31
31
29
29
39
39 31
31
31
30
20
20
28
26
28
30
7
30
7
29
7
28
30
29
30
28
29
28
28
28
28
28
28
26
31
24
31
4
32
24
28
28
28
28
28
55
55
6
28
55
6
30
24
29
24
24
28
6
6
33
32
6
6
4
4
55
29
31
6
39
28
28
29
6
39
28
28
28
28
28
7
24
8
28
32
31
31
4
4
28
4
24
24
31
28
39
39
28
28
31
28
20
39
31
31
31
28
28
31
31
33
32
28
28
39
28
28
28
28
6
31
6
28
28
4
31
31
28
31
31 28
28
28
7
7
7
24
24
24
28
6
24
6
6
28
6
6
6
28
6
28
6
28
26
28
28
Preliminary
G
D
S
G
D
S
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
REFERENCE DESIGNATOR(S)
BOM OPTION
TABLE_5_HEAD
QTY
DESCRIPTION
PART#
TABLE_5_ITEM
SAME CONNECTOR AS Q63 CPU CARD FOR SAT
SMU DEBUG/DOWNLOAD CONNECTOR
SMU RESET BUTTON
518S0327
I2C ADDR:72(1001000)
RESET
AMBIENT LIGHT SENSOR CONNECTOR
ALWAYS ON (TRICKLE)
PCB: PLACE Q2984 NEAR CPU
DRIVE STRONG HRESET AND BYPASS TO CPU
FROM SMU
POWER
SYS LED’S
RTC BATTERY
DIGITAL GND THROUGHOUT
518S0328
POWER BUTTON HEADER
SYS POWER AND RESET BUTTON
CRITICAL
BB10209-A5
TH
1 2
J2902
SPST
SM-LF
43
21
SW2902
SPST
DEVELOPMENT
SM-LF
43
21
SW2900
1/16W
402
1K
5%
MF-LF
21
R2913
SPST
DEVELOPMENT
SM-LF
43
21
SW2901
DEVELOPMENT
1K
1/16W
5%
402
MF-LF
21
R2912
1K
402
MF-LF
1/16W
5%
21
R2902
PP5V_PWRON
WHITE-500MCD
CRITICAL
3X2MM-SM
2
1
LED2901
0
5%
1/16W
MF-LF
402
NOSTUFF
21
R2900
402
1/16W
MF-LF
1%
56.2
17_INCH_LCD
2
1
R2903
SOT23-LF
FDV301N
2
1
3
Q2901
NOSTUFF
1/16W
4.7K
402
MF-LF
5%
2
1
R2908
MMBD914XXG
SOT23
3
1
D2900
SOD-123
B0530WXF
2 1
DS2900
30K
5%
1/16W
402
MF-LF
2
1
R2929
10%
1UF
402
CERM
6.3V
2
1
C2900
DEVELOPMENT
402
0
5%
1/16W
MF-LF
21
R2931
DEVELOPMENT
F-RT-SM
SM12B-SRSS-TB-LF
9
8
7
6
5
4
3
2
12
11
10
1
13
14
J2904
I6
NOSTUFF
0
5%
MF-LF
402
1/16W
2
1
R2925
DEVELOPMENT
100
1%
402
1/16W
MF-LF
21
R2930
1K
5%
1/16W
MF-LF
402
21
R2983
1K
5%
1/16W
MF-LF
402
21
R2984
SOT-363
2N7002DW-X-F
1
2
6
Q2984
2N7002DW-X-F
SOT-363
4
5
3
Q2984
F-ST-SM
53398-0476
CRITICAL
4
3
2
1
6
5
J2901
PP3V3_PWRON
M-ST-SM
53398-0276
CRITICAL
2
1
4
3
J2903
1/16W
402
MF-LF
5%
10K
2
1
R2924
10K
NOSTUFF
1/16W
402
MF-LF
5%
2
1
R2923
0.1UF
20%
10V
402
CERM
2
1
C2904
CERM
20%
402
10V
0.1UF
2
1
C2905
114S0081
RES, 39.2 OHM, 1%, 402, LF
1
20_INCH_LCD
R2903
SYNC_DATE=06/20/2005
SYNC_MASTER=FINO-HS
154
29
051-6790
19
SMU SUPPLEMENTAL (2)
SMU_BOOT_BUSY
I2C_ALS_SCL
I2C_ALS_SDA
SYS_LED_DRV_K
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
SYS_LED
SYS_LED_DRV_C
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.6MM
=PP3V3_ALL_SMU
=PPV_EI_CPU
PP3V3_ALL_BATT
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.6MM
PP3V3_ALL_BATT_SAFETY
SYS_POWER_BUTTON_L
SYS_RESET_BUTTON_L
CPU_HRESET
CPU_BYPASS
CPU_BYPASS_L
CPU_HRESET_L
SMU_RESET_L
POWER_BUTTON_L
=PP3V3_ALL_SMU
SMU_BOOT_SCLK
PP3V3_ALL_RTC
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
MAKE_BASE=TRUE
VOLTAGE=3.3V
=PP3V3_ALL_RTC
POWER_BUTTON_L
RESET_BUTTON_L
SMU_BOOT_CNVSS
NC_J2904_12
NC_J2904_6
SMU_MANUAL_RESET_L
SMU_BOOT_RXD
SMU_BOOT_BUSY_R
NC_J2904_11
SMU_BOOT_TXD
SMU_MANUAL_RESET_L
SMU_BOOT_CE
56
29
48
29
28
47
28
28
7
30
28
28
29
7
28
29
28
29
28
28
29
28
6
39
39
28
6
7
6
28
31
28
43
43
6
6
6
6
28
6
6
6
6
6
6
6
6
6
6
Preliminary
G
D
S
G
D
S
125
125
G
D
S
G
D
S
G
D
S
EN*
GND
B
A
A*/B
Y*
Y
VCC
G
D
S
G
D
S
Y0
Y1
GND
E*
A
VCC
G
D
S
Y
A
GND
VCC
125
Y
GND
VCC
A
34
Y
GND
VCC
A
34
G
D
S
G
D
S
G
D
S
G
D
S
G
D
S
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
PULLDOWNS TO BUFFERS/LOGIC GATES
SHARE SMU JTAG TCK WITH CPU AND NB (PRIMARY PLAN)
TO AVOID STUBS
NOTE: WE WENT WITH BACKUP PLAN, PRIMARY REMOVED
PLACE O-OHM R3030 AND R3031 TO AVOID STUBS
CONSIDER COMBINING Q3040 AND Q3006 TO A DUAL PART
PULLUP IF
LEVEL SHIFT TDO FROM CPU TO MUX
LEVEL SHIFT SMU TMS TO CPU (BACKUP PLAN)
PCB: PLACE U3030 AND U3031 NEAR CPU AND KODIAK.
KODIAK JTAG IS NOSTUFFED
VIH = 2.0V, 3.3V TOLERANT
LEFTOVER FROM UNUSED PRIMARY PLAN - NOT STUFFED
SMU JTAG TCK TO CPU (BACKUP PLAN)
U700 IS POWERED BY PP3V3_ALL
TO LEVEL SHIFTER
SHARE CPU AND NB JTAG TDO WITH SMU
VIH=2V
SYS_NORTH_RESET FROM SMU TO NB_PU_RST
SAME AS Q63
SAME AS Q63
SMU TO NB SUSPEND_REQ
MISC. SMU BUFFERS
SAME AS (Q63).
NB SUSPEND_ACK_L LEVEL 2.5V TO 3.3V LEVEL SHIFTER
SHARE CPU AND NB JTAG TMS WITH SMU
ALL JTAG-RELATED PINS
STRAIGHT TO NB
PCB: PLACE R3050, Q3050, R3051 NEAR CPU. PLACE Q3021, R3052 NEAR SMU.
PCB: PLACE U3070 NEAR SMU
PCB: PLACE U3071 NEAR SMU OR NEAR KODIAK.
3.3V TOLERANT
SMU DRIVES 3.3V PUSH-PULL ON
SMU JTAG TDI TO CPU (BACKUP PLAN)
STUFF IF USING REGISTERED DIMM
SHARE SMU JTAG TDI WITH CPU AND NB (PRIMARY PLAN)
NB JTAG IS A DEVELOPMENT ONLY FEATURE
VIH = 2.0V, 3.3V TOLERANT
VCC RANGE 0.8V - 2.7V VCC RANGE 0.8V - 2.7V
PCB: PLACE 33 OHM RES NEAR U3030/31 PART.
SOT-363
2N7002DW-X-F
1
2
6
Q3005
2N7002DW-X-F
SOT-363
4
5
3
Q3000
402
1/16W
0
NOSTUFF
5%
MF-LF
21
R3008
5%
100
402
MF-LF
1/16W
2 1
R3022
5%
100
MF-LF
402
1/16W
2 1
R3023
TSSOP
74LC125
8
14
107
9
U700
MF-LF
402
5%
1/16W
4.7K
2
1
R3021
TSSOP
74LC125
6
14
47
5
U700
2N7002
NOSTUFF
SOT23-LF
2
1
3
Q3040
1K
1/16W
MF-LF
402
NOSTUFF
5%
2
1
R3040
2N7002DW-X-F
SOT-363
4
5
3
Q3005
5%
4.7K
402
MF-LF
1/16W
2
1
R3003
5%
1/16W
MF-LF
402
4.7K
2
1
R3010
SOT23-LF
2N7002
NOSTUFF
2
1
3
Q3006
CRITICAL
TSSOP
SN74LVC2G157
3
5
8
4
7
2
6
1
U3070
0.1UF
CERM
10V
20%
402
2
1
C3070
0
1/16W
MF-LF
402
5%
NOSTUFF
21
R3009
5%
MF-LF
1/16W
10K
402
2 1
R3050
5%
402
MF-LF
1/16W
1K
2
1
R3051
100
MF-LF
402
1/16W
5%
2
1
R3052
SOT23
2N3904LF
2
3
1
Q3050
0.1UF
CERM
10V
20%
402
2
1
C3071
5%
1K
1/16W
402
MF-LF
2
1
R3093
5%
402
MF-LF
1/16W
1K
2
1
R3091
SOT23
2N3904LF
NB_SUSPEND_ACK_L_R
2
3
1
Q3090
MF-LF
402
1/16W
10K
5%
2 1
R3090
5%
MF-LF
1/16W
0
NOSTUFF
402
2 1
R3092
2N7002DW-X-F
SOT-363
1
2
6
Q3000
2N7002DW-X-F
SOT-363
4
5
3
Q3021
CRITICAL
74LVC1G
SC70-6
4
6
5
2
3
1
U3071
DEVELOPMENT
33
5%
402
1/16W
MF-LF
2 1
R3033
DEVELOPMENT
33
MF-LF
402
1/16W
5%
2 1
R3032
DEVELOPMENT
CERM
10V
402
0.1UF
20%
2
1
C3031
1/16W
MF-LF
5%
10K
402
2
1
R3034
MF-LF
402
1/16W
10K
5%
2
1
R3035
SOT-363
2N7002DW-X-F
1
2
6
Q3021
MF-LF
402
1/16W
10K
5%
2 1
R3038
100K
5%
402
1/16W
MF-LF
21
R3036
1/16W
MF-LF
402
5%
100K
21
R3071
100K
5%
402
MF-LF
1/16W
21
R3037
5%
402
1/16W
100K
MF-LF
21
R3070
VSSOP
SN74AUC2G125
NOSTUFF
6
8
1
4
2
U5640
DEVELOPMENT
SN74AUC2G34
SOT23-6
6
5
2
1
U3031
SOT23-6
SN74AUC2G34
DEVELOPMENT
4
5
2
3
U3031
SOT-363
2N7002DW-X-F
1
2
6
Q3080
1/16W
MF-LF
4.7K
402
5%
2
1
R3083
SOT-363
2N7002DW-X-F
1
2
6
Q3081
MF-LF
402
5%
1K
1/16W
2
1
R3084
33
1/16W
402
MF-LF
5%
2 1
R3085
MF-LF
1/16W
402
5%
33
2 1
R3082
1K
5%
402
MF-LF
1/16W
2
1
R3081
SOT-363
2N7002DW-X-F
4
5
3
Q3081
MF-LF
1/16W
5%
402
4.7K
2
1
R3080
2N7002DW-X-F
SOT-363
4
5
3
Q3080
NOSTUFF
0
1/16W
402
MF-LF
5%
21
R3099
NOSTUFF
0
1/16W
402
MF-LF
5%
21
R3098
MF-LF
402
1/16W
5%
1K
2
1
R3027
SOT-363
2N7002DW-X-F
4
5
3
Q3031
1K
1/16W
5%
402
MF-LF
2
1
R3026
SOT23
2N3904LF
2
3
1
Q3030
5%
MF-LF
402
1/16W
10K
2 1
R3020
5%
MF-LF
402
1/16W
33
2 1
R3028
402
0
5%
1/16W
MF-LF
DEVELOPMENT
2
1
R3031
DEVELOPMENT
5%
0
402
1/16W
MF-LF
2
1
R3030
5%
402
MF-LF
1/16W
1K
2
1
R3000
5%
1/16W
MF-LF
402
100
2
1
R3001
5%
MF-LF
402
1/16W
0
NOSTUFF
21
R3002
5%
4.7K
1/16W
MF-LF
402
2
1
R3007
5%
10K
1/16W
402
MF-LF
2
1
R3006
SYNC_MASTER=FINO-HS
SYNC_DATE=06/20/2005
051-6790
19
30
154
SMU SUPPLEMENTAL (3)
SMU_JTAG_NB_TCK
=PP2V5_PWRON_NB_MISC
SMU_JTAG_NB_TDI
=PP2V5_PWRON_NB_MISC
SYS_NORTH_RESET_L
SMU_SUSPENDREQ_L
JTAG_NB_TDO
SMU_JTAG_TCK
SMU_JTAG_TCK
NB_PU_RST_L
SMU_JTAG_TDI
JTAG_CPU_TCK
SMU_JTAG_TDI
SMU_JTAG_TDI_L
JTAG_CPU_TDI
JTAG_CPU_TDI_2_R
=PP3V3_RUN_SMU
=PPV_EI_CPU
=PP3V3_PWRON_SMU
JTAG_CPU_TMS_2_L
SMU_CPU_TMS
JTAG_SMU_TMS_2_R
SMU_JTAG_TCK_L
=PP3V3_RUN_SMU
=PPV_EI_CPU
SYS_IO_RST_L_R
SMU_IO_RESET
=PP3V3_PWRON_SMU
JTAG_CPU_TMS_2_R
JTAG_CPU_TMS
=PPV_EI_CPU
JTAG_NB_TCK_RJTAG_NB_TDI_R
SMU_CPU_NB_SEL
=PP3V3_PWRON_SMU
JTAG_NB_TDO
NB_SUSPENDACK_L
JTAG_NB_TMS
SMU_CPU_TMS
=PP2V5_PWRON_NB_MISC
JTAG_NB_TCK
=PP3V3_PWRON_SMU
SYS_IO_RESET_L
=PP3V3_PWRON_SMU
SYS_SLEEP_R
SYS_SLEEP
NB_PU_RESET
=PP2V5_PWRON_NB_MISC
SYS_IO_RST_L_R
=PP3V3_PWRON_SMU
=PP3V3_PWRON_SMU
NC_JTAGMUX_3
SMU_JTAG_TDO
JTAG_CPU_TDO_3V3
SMU_JTAG_TMS
NB_SUSPEND_ACK_L
SMU_JTAG_TDI
SMU_JTAG_TCK
SMU_JTAG_TMS
SMU_CPU_NB_SEL
SYS_NORTH_RESET_L_R
JTAG_CPU_TDO
JTAG_CPU_TDO_R
JTAG_CPU_TDO_L
=PP3V3_PWRON_SMU
JTAG_CPU_TDO_3V3
=PP2V5_PWRON_NB_MISC
SMU_SUSPENDREQ_L_R
SYS_2SLEEP_R
JTAG_CPU_TCK_2_R
SMU_SLEEP
SMU_IO_RESET_L
NB_SUSPENDACK
NB_SUSPEND_REQ_L
PMU_SUSPEND_REQ
=PP2V5_PWRON_NB_MISC
SYS_SLEEP
JTAG_NB_TDI
54
54
30
30
56
56
56
26
26
39
39
48
48
48
39
16
39
39
39
16
30
30
30
47
43
30
47
43
47
43
30
43
122
43
15
30
43
43
43
30
30
15
28
28
43
30
28
30
30
28
30
30
30
30
30
28
30
119
30
13
28
30
30
47
30
28
28
13
20
20
28
20
31
31 31
43
31
43
20
29
28
20
29
28
43
29
31
28
20
20
20
20
28
28
28
12
20
28
28
31
62
31
31
31
31
43
28
20
20
12
20
7
7
28
24
9
30
30
20
30
9
30
9
7
7
7
30
7
7
30
67
7
9
7
30
7
9
28
9
30
7
9
7
24
7
11
7
30
7
7
9
31
30
30
20
30
30
30
30
9
7
30
7
28
28
20
7
11
9
Preliminary
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
SELECT BETWEEN CPU OR NB TMS AND TDO FROM/TO SMU
M23/M33 ONLY CONNECTS I2C TO KODIAK NOW; CPU HAS PULLUPS ON ITS PG.
Q63 NET NAME (SHARED PAGE)
P0.5
P0.6
P0.4
P0.3
P0.2
P0.1
P0.0
P0.7
P1.6
P1.7
P2.0
P1.5
P1.4
P1.0
P1.1
P1.2
P1.3
M23 SMU ALLOCATION
CPU_VID_LE0
CPU_VID_LE1
CPU_SENSE_I1
CPU_SENSE_V1
CPU_TEMP1
POWERFAIL*
FAN_TACH2_1
DOOR_AJAR*
SMU_SCCL_SEL
FAN_CNTL0_6
FAN_CNTL0_5
FAN_CNTL0_4
CPU_SENSE_I0
CPU_TEMP0
CPU_BYPASS
PS1_3
PS1_4
P2.7
P3.0
P3.1
P3.2
P3.3
P2.6
P2.5
P2.3
P2.4
P3.4
P3.5
P3.6
P3.7
P6.0
P6.1
P6.2
P6.3
CPU_VID[2]
CPU_VID[1]
CPU_VID[0]
OVERTEMP*
IIC_E_CLK
IIC_E_DAT
IIC_A_CLK
IIC_A_DAT
FAN_TACH2_7
FAN_TACH2_3
FAN_TACH2_2
DIAG_LED
TCK
TDI
P7.2
P7.7
P7.6
P7.5
P7.4
P7.3
P7.0
P7.1
P6.6
P6.7
P8.0
P9.2
P9.1
P9.0
P8.1
P8.2
P8.3
P8.6
P8.7
SMU_DOORBELL*
CPU_HRESET
CLK_RESET*
NB_RESET*
SYSTEM_LED
FAN_CNTL7_7
FAN_CNTL7_5
FAN_CNTL7_4
FAN_CNTL7_3
DEBUG_TXD
IIC_B_DAT
IIC_B_CLK
SLEEP
POWERUP*
NB_TMS
SLEWING*
VDNAP0
VDNAP2
CPU_TMS
P10.1
P10.4
P10.3
P10.2
P10.0
P9.3
P9.5
P9.6
P9.7
P10.5
P10.6
P10.7
RST_BUTTON*
PWR_BUTTON*
SUSPEND_REQ*
SUSPEND_IO_ACK*
SUSPEND_ACK*
IO_RESET*
STOP_XTAL*
SLOT_TOTAL_PWR
TDO
VDNAP1
PS9_5
PS9_6
M23 NET NAME
M23/M33 DOESN’T USE. P1.0 NC ON PG 7.
M23/M33 DOESN’T USE P1.4. NC ON PG 7.
M23/M33 DOESN’T NEED TO MAKE VDNAP0 DO TRIPLE-DUTY.
M23/M33 USES TACH0 (P2.2), TACH1 (P2.3), TACH2 (P2.4) ONLY.
M23/M33 DOESN’T HAVE THIS FAN (P7.4)
M23/M33 USES FAN_RPM0 (P7.3), FAN_RPM1 (P7.5), FAN_RPM2 (P7.7) ONLY.
Q63 USE OF P7.2 IS PWM FAN
SMU USES P1.1, P1.2, P1.3, P9.5, P9.6 FOR PWRSEQ ON PG 7.
Q63 USE OF P9.1 IS TACH 8.
M23/M33 HAS NO SLOTS.
M23/M33 DOESN’T HAVE FAN TACHS P2.5, P2.6, P2.7.
CPU_VID_LE0 FOR Q82. NOT M23/M33 FEATURE.
CPU_VID_LE1 FOR Q82. NOT M23/M33 FEATURE.
M23/M33 DOESN’T HAVE THIS FAN.
CONSIDER DOOR_AJAR FOR M23/M33 DIMM ACCESS DOOR?
Q63 NC’S THESE AS IT USES A SAT.
SMU USES P1.1, P1.2, P1.3, P9.5, P9.6 FOR PWRSEQ ON PG 7.
CPU_VID[3]
P6.4
P6.5
DEBUG_RXD
CPU_VID[5]
NOTE:PULL UP CPU_VID<5>TO
2.2V FOR CPU VRM10.
SO PULLUPS MUST BE 1K
CPU_VID[4]
NOTE: SC2642 VID PINS HAVE LEAKAGE TO GND.
CPU_SENSE_V0
COMMENT (ONLY IF USE DIFFERS FROM Q63)
ALIASES ARE ONLY NECESSARY WHERE USE DIFFERS FROM Q63.
SMU ALIASES
P2.1
P2.2
FAN_TACH2_4
FAN_TACH2_5
FAN_TACH2_6
PME*
P8.4
P8.5
Q63 USES SMU_SER_SEL FOR SPDIF-SMU-DEBUG. NOT M23/M33 FEATURE.
M23/M33 DOESN’T HAVE THOSE FANS.
CPU VID<0:5>
VID CONTROLLED BY SMU
PP3V3_RUN
1K
1/16W
MF-LF
5%
402
2
1
R3104
1K
1/16W
402
MF-LF
5%
2
1
R3109
1K
1/16W
402
MF-LF
5%
2
1
R3108
2.0K
MF-LF
1/16W
5%
402
2
1
R3111
402
1K
MF-LF
1/16W
5%
NOSTUFF
2
1
R3127
402
MF-LF
5%
1K
NOSTUFF
1/16W
2
1
R3129
402
MF-LF
5%
1K
1/16W
NOSTUFF
2
1
R3130
1/16W
5%
1K
MF-LF
402
2
1
R3117
1K
1/16W
5%
MF-LF
402
2
1
R3116
1K
5%
1/16W
MF-LF
402
2
1
R3114
402
MF-LF
1/16W
5%
1K
NOSTUFF
2
1
R3131
402
MF-LF
1/16W
5%
NOSTUFF
1K
2
1
R3132
BM12B-SRSS-TB
F-ST-SM
NOSTUFF
9876543
2
121110
11314
J3108
0
1/16W
MF-LF
402
5%
21
R3120
0
402
MF-LF
1/16W
5%
21
R3122
0
5%
1/16W
MF-LF
402
21
R3119
1/16W
0
MF-LF
5%
402
21
R3121
0
1/16W
MF-LF
5%
402
21
R3124
MF-LF
0
1/16W
5%
402
21
R3123
B0530WXF
SOD-123
2 1
DS3100
SMU SUPPLEMENTAL (4)
SYNC_MASTER=FINO-HS
SYNC_DATE=06/20/2005
051-6790
19
154
31
PP3V3_CPU_VID_D
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
MAKE_BASE=TRUE
CPU_VID<1>
CPU_VID_R<0>
CPU_VID<2>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
CPU_VID<3>
MAKE_BASE=TRUE
CPU_VID<4>
I2C_SMU_CPU_SDA_OUT_L
MAKE_BASE=TRUE
SMU_JTAG_TMS
MAKE_BASE=TRUE
SB_VDNAP0
MAKE_BASE=TRUE
NC_I2C_SMU_CPU_SCL_IN
MAKE_BASE=TRUE
SMU_CPU_NB_SEL
MAKE_BASE=TRUE
SMU_JTAG_TCK
MAKE_BASE=TRUE
SMU_JTAG_TDI
MAKE_BASE=TRUE
I2C_SMU_A_SDA
MAKE_BASE=TRUE
NC_SMU_FAN_TACH5
MAKE_BASE=TRUE
NC_SMU_CPU_VID_LE1
SYS_DOOR_AJAR_L
SMU_FAN_TACH9
CPU_VID_R<1>
CPU_VID_R<2>
CPU_VID_R<4>
CPU_VID_R<5>
CPU_VID_R<3>
MAKE_BASE=TRUE
CPU_VID<5>
CPU_VID<0>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SMU_JTAG_TDO
I2C_SMU_CPU_SCL_OUT_L
MAKE_BASE=TRUE
NC_SLOT_TOTAL_PWR
SYS_SLOT_PWR
MAKE_BASE=TRUE
CPU_HRESET
SMU_FAN_TACH8
SB_CPU_VDNAP0_OR_QREQ_OR_SPDIF
I2C_SMU_CPU_SCL_IN
I2C_SMU_CPU_SDA_IN
I2C_SMU_A_SCL_OUT_L
I2C_SMU_A_SCL_IN
SMU_FAN_TACH5
MAKE_BASE=TRUE
NC_SMU_FAN_TACH7
SMU_FAN_TACH7
SMU_FAN_TACH6
MAKE_BASE=TRUE
NC_SYS_DOOR_AJAR_L
MAKE_BASE=TRUE
NC_SMU_CPU_VID_LE0
MAKE_BASE=TRUE
NC_SMU_SER_SEL
SMU_SER_SEL
MAKE_BASE=TRUE
NC_SMU_FAN_RPM5
SMU_FAN_RPM5
MAKE_BASE=TRUE
NC_SMU_FAN_RPM3
SMU_FAN_RPM3
MAKE_BASE=TRUE
NC_SMU_FAN_RPM4
SMU_FAN_RPM4
MAKE_BASE=TRUE
NC_SMU_FAN_TACH3
SMU_FAN_TACH4
SMU_FAN_TACH3
MAKE_BASE=TRUE
NC_SMU_FAN_TACH4
MAKE_BASE=TRUE
I2C_SMU_A_SCL
I2C_SMU_A_SDA_IN
I2C_SMU_A_SDA_OUT_L
NC_J3108_8
NC_J3108_9
NC_J3108_10
NC_J3108_11
NC_J3108_12
39
39
28
50
28
28
28
28 30
24
9
30
30
30
28
9
9
28
28
50
50
50
50
50
28
28
30 28
9
28
29 28
28
28
28
28
28
28
9
28
28
9
9
9
28
9
28
9
28
9
28
9
28
28
9
28
28
28
9
9
9 9 9
Preliminary
G
D
S
G
D
S
G
D
S
G
D
S
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
M33: CPU FAN
M23: HD FAN
M33: ODD FAN
M23: ODD FAN
518S0193
MOTOR CONTROL
MOTOR CONTROL
TACH
FAN 1
FAN 0
GND
TACH
GND
12V DC
12V DC
518S0326
PP3V3_RUN
5%
MF-LF
1/16W
402
10K
2
1
R3210
PP3V3_RUN
10K
1/16W
MF-LF
402
5%
2
1
R3259
CERM
25V
20%
0.1UF
603
NOSTUFF
2
1
C3202
1.5K
5%
1/4W
MF-LF
1206
2
1
R3205
NTHS5443T1
1206A-03-LF
CRITICAL
5
4
87632
1
Q3203
1/8W
1.5K
5%
MF-LF
805
2
1
R3207
SOT23
MMBD914XXG
3
1
D3202
MF-LF
1/8W
5%
0
805
21
R3208
10%
0.47UF
805
X7R
16V
2
1
C3204
3.9K
5%
1/8W
MF-LF
805
R3206
PP12V_RUN
2N7002DW-X-F
SOT-363
4
5
3
Q3201
805
1.0K
5%
1/8W
MF-LF
2
1
R3202
2N7002DW-X-F
SOT-363
1
2
6
Q3201
CRITICAL
1206A-03-LF
NTHS5443T1
5
4
87632
1
Q3253
25V
NOSTUFF
603
0.1UF
20%
CERM
2
1
C3252
1/8W
1.5K
5%
MF-LF
805
2
1
R3257
MF-LF
1/8W
0
5%
805
21
R3258
10%
805
0.47UF
X7R
16V
2
1
C3254
3.9K
5%
1/8W
805
MF-LF
R3256
MMBD914XXG
SOT23
3
1
D3252
MF-LF
1/4W
5%
1.5K
1206
2
1
R3255
2N7002DW-X-F
SOT-363
4
5
3
Q3251
PP12V_RUN
805
5%
1/8W
MF-LF
1.0K
2
1
R3252
2N7002DW-X-F
SOT-363
1
2
6
Q3251
120UF
6.3X11-TH-LF
20%
16V
ELEC
2
1
C3203
16V
20%
ELEC
6.3X11-TH-LF
120UF
2
1
C3253
NOSTUFF
MF-LF
1/8W
5%
1.0K
805
2
1
R3215
NOSTUFF
1.0K
5%
1/8W
MF-LF
805
2
1
R3265
MF-LF
1/8W
5%
0
805
21
R3266
805
0
5%
MF-LF
1/8W
21
R3216
SMB
NOSTUFF
B130LBT01XF
21
D3203
SMB
B130LBT01XF
NOSTUFF
21
D3253
53261-0498
M-RT-SM
CRITICAL
4
3
2
1
6
5
J3200
53261-0598
M-RT-SM
CRITICAL
5
4
3
2
1
7
6
J3201
32
154
051-6790
19
Fan 0, 1 & System Temp
SYNC_MASTER=FINO-HS
SYNC_DATE=06/20/2005
SMU_FAN_TACH1
FAN_1_PWR
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
F1_VOLTAGE8R5
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM
F1_RCFEEDBK
F0_GATESLOWDN
FAN_0_OUT
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM
SMU_FAN_TACH0
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM
FAN_0_PWR
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
F0_RCFEEDBK
F1_GATESLOWDN
FAN_1_OUT
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
SMU_FAN_RPM0
F0_DRV
F0_VOLTAGE8R5
SMU_FAN_RPM1
F1_DRV
28
28
28
28
Preliminary
G
D
S
G
D
S
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
HD TEMP SENSOR
518S0193
CAPS ARE FOR EMC ON M23 ONLY
CAPS ARE FOR EMC ON M23 ONLY
I2C ADDR:0X90(1001000)
GND
TACH
FAN 2
M33: HD FAN
MOTOR CONTROL
M23: CPU FAN
518S0328
518S0193
12V DC
ODD TEMP SENSOR
I2C ADDR:0X92(1001001)
PP3V3_RUN
10K
1/16W
MF-LF
402
5%
2
1
R3309
PP3V3_RUN
CRITICAL
53261-0498
M-RT-SM
4
3
2
1
6
5
J3301
NTHS5443T1
1206A-03-LF
5
4
87632
1
Q3303
MMBD914XXG
SOT23
3
1
D3302
NOSTUFF
CERM
20%
0.1UF
603
25V
2
1
C3302
5%
1/8W
1.5K
MF-LF
805
2
1
R3307
5%
1/8W
0
805
MF-LF
21
R3308
805
16V
X7R
10%
0.47UF
2
1
C3304
3.9K
5%
1/8W
MF-LF
805
R3306
MF-LF
1206
1.5K
5%
1/4W
2
1
R3305
2N7002DW-X-F
SOT-363
4
5
3
Q3301
PP12V_RUN
MF-LF
1/8W
5%
1.0K
805
2
1
R3302
2N7002DW-X-F
SOT-363
1
2
6
Q3301
120UF
20%
16V
ELEC
6.3X11-TH-LF
2
1
C3303
NOSTUFF
1/8W
805
1.0K
5%
MF-LF
2
1
R3315
0
805
5%
1/8W
MF-LF
21
R3316
B130LBT01XF
NOSTUFF
SMB
21
D3303
CRITICAL
53261-0498
M-RT-SM
4
3
2
1
6
5
J3302
PP3V3_RUN
F-ST-SM
53398-0476
CRITICAL
4
3
2
1
6
5
J3300
17_INCH_LCD
16V
CERM
20%
0.01UF
402
2
1
C3393
NOSTUFF
0.01UF
CERM
20%
16V
402
2
1
C3392
NOSTUFF
CERM
20%
0.01UF
402
16V
2
1
C3390
17_INCH_LCD
0.01UF
20%
CERM
16V
402
2
1
C3391
17_INCH_LCD
0.01UF
20%
402
16V
CERM
2
1
C3395
NOSTUFF
402
0.01UF
CERM
16V
20%
2
1
C3394
17_INCH_LCD
CERM
0.01UF
402
16V
20%
2
1
C3397
NOSTUFF
0.01UF
20%
402
16V
CERM
2
1
C3396
051-6790
19
33
154
Fan 2 & HD Temp
SYNC_MASTER=FINO-HS
SYNC_DATE=06/20/2005
HS_SDF801
HS_SDF801
I2C_ODD_TEMP_SCL
FAN_2_OUT
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
SMU_FAN_RPM2
F2_DRV
F2_GATESLOWDN
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM
FAN_2_PWR
F2_VOLTAGE8R5
F2_RCFEEDBK
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
I2C_ODD_TEMP_SDA
SMU_FAN_TACH2
HS_SDF801
HS_SDF801
I2C_HD_TEMP_SCL
I2C_HD_TEMP_SDA
33
33
33
33
8
8
39
28
39
28
8
8
39
39
Preliminary
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