Apple A1138 Schematic

TABLE_TABLEOFCONTENTS_ITEM

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

ANGLES

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

DATE

APPD

ENG

DATE

APPD

CK

ECN

ZONE

REV

DO NOT SCALE DRAWING

X.XXX

X.XX

XX

DIMENSIONS ARE IN MILLIMETERS

THIRD ANGLE PROJECTION

D

SIZE

APPLICABLE

NOTED AS

MATERIAL/FINISH

NONE

SCALE

DESIGNER

MFG APPD

DESIGN CK

RELEASE

QA APPD

ENG APPD

DRAFTER

METRIC

OF

SHT

DRAWING NUMBER

TITLE

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

Apple Computer Inc.

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

DESCRIPTION OF CHANGE

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

PDF CSAPDF CSA

N/A

Revision History

N/A

5 5

N/A

Sudden Motion Sensor

N/A

29 32

N/A

ALS Support

N/A

28 31

N/A

Fan Controller

N/A

27 30

N/A

Power Sequencing

N/A

26 29

N/A

Power Management Unit (PMU05)

N/A

25 27

N/A

LEDs/Reset/Debug

N/A

24 26

N/A

PCI Clock Buffer

N/A

23 25

N/A

I2 Miscellaneous

N/A

22 24

N/A

I2 Supplemental

N/A

21 23

N/A

I2 Power Supplies

N/A

20 22

N/A

Spacing & Physical Constraints 2

N/A

76 111

N/A

Vesta Power & Misc

N/A

18 19

N/A

2.5V Supply

N/A

17 17

N/A

1.8V/1.5V Supplies

N/A

16 16

N/A

5V/3.3V Supplies

N/A

15 15

N/A

12.8V PBUS/PMU Supplies

N/A

14 14

N/A

Battery Charger

N/A

13 13

N/A

Power Inputs

N/A

12 12

N/A

Signal Synonyms

N/A

11 11

N/A

I2C Connections

N/A

8 8

N/A

Q16C Internal I/O II

N/A

31 34

N/A

Q16C Internal I/O I

N/A

30 33

Q16C_BST_VRAM_H

[EEE:TMK]

1

826-4393

LBL,P/N LABEL,PCB,28MM X 6MM

Q16C_BST_VRAM_S

[EEE:SYU]

LBL,P/N LABEL,PCB,28MM X 6MM

826-4393

1

820-1875

PCBF,MLB,Q16C

PCB1 CRITICAL

051-6929

1

SCHEM,MARIAS-STD,Q16C

SCH1

SCHEM,MARIAS-STD,Q16C

115

1

051-6929

C

?

09/09/05

399027

PRODUCTION RELEASED

C

N/A

Power Block Diagram

N/A

4 4

N/A

Q16C Pin Swaps

N/A

6 6

N/A

JTAG Connections

N/A

9 9

N/A

Power Synonyms

N/A

10 10

N/A

I2 Power

N/A

19 21

N/A

DDR2 SO-DIMM Slot A

N/A

40 50

N/A

Memory Series Termination

N/A

39 48

N/A

I2 Memory Interface

N/A

38 47

N/A

CPU AVDD Supply

N/A

37 46

N/A

CPU VCore Supply

N/A

36 39

MULLET

A8 Power (CPU0)

08/02/2005

35 38

MULLET

A8 Configuration Straps

08/02/2005

34 37

MULLET

A8 MaxBus (CPU0)

08/02/2005

33 36

N/A

I2 Processor Interface

N/A

32 35

N/A

Functional Test Points

N/A

7 7

N/A

BootROM

N/A

58 71

N/A

External Display Conns

N/A

57 70

N/A

Internal Display Conns

N/A

56 69

N/A

Upper TMDS Transmitter

N/A

55 68

N/A

Lower TMDS Transmitter

N/A

54 67

N/A

GPU (M11) DVI/DAC Outputs

N/A

53 66

N/A

GPU (M11) Clocks/Misc

N/A

52 65

N/A

GPU (M11) GPIOs/Straps

N/A

51 64

N/A

GPU Frame Buffer B

N/A

50 63

N/A

GPU Frame Buffer A

N/A

49 62

N/A

GPU (M11) Frame Buffer I/F

N/A

48 61

N/A

GPU (M11) I/O Power

N/A

47 60

N/A

GPU (M11) Core Power

N/A

46 59

N/A

GPU VCore Supply

N/A

45 58

N/A

GPU (M11) AGP Interface

N/A

44 57

N/A

I2 AGP Interface

N/A

43 56

N/A

M11 Frame Buffer Constraints

N/A

42 55

CONTENTS

DATE

SYNC MASTER

N/A

Table Of Contents

N/A

1 1

CONTENTS

DATE

SYNC MASTER

N/A

DDR2 SO-DIMM Slot B

N/A

41 52

N/A

I2 PCI Interface

N/A

59 72

N/A

System Block Diagram

N/A

3 3

N/A

Board Information

N/A

2 2

Cross Reference Page

80 115

Cross Reference Page

79 114

Cross Reference Page

78 113

Cross Reference Page

77 112

N/A

Spacing & Physical Constraints

N/A

75 110

N/A

Audio Board Connector

N/A

74 100

N/A

NEC USB2 Interface

N/A

73 93

N/A

I2 USB Interface

N/A

72 92

N/A

FireWire Series Term

N/A

71 91

N/A

FireWire Ports

N/A

70 90

N/A

Vesta FireWire PHY

N/A

69 89

N/A

I2 FireWire Interface

N/A

68 88

N/A

Ethernet Connector

N/A

67 86

N/A

Vesta Ethernet PHY

N/A

66 85

N/A

I2 Ethernet Interface

N/A

65 84

N/A

HDD/ODD Connectors

N/A

64 82

N/A

I2 UATA Interface

N/A

63 81

N/A

NEC USB2

N/A

62 75

N/A

Cardbus

N/A

61 74

N/A

Q85 Airport/BT Connector

N/A

60 73

TABLE_SPACING_RULE

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

TABLE_BOARD_INFO

TABLE_SPACING_RULE

TABLE_PHYSICAL_RULE

TABLE_SPACING_ASSIGNMENT

TABLE_SPACING_RULE

TABLE_PHYSICAL_RULE

TABLE_SPACING_ASSIGNMENT

TABLE_PHYSICAL_RULE

TABLE_SPACING_RULE

TABLE_PHYSICAL_RULE

TABLE_SPACING_RULE

TABLE_PHYSICAL_RULE

TABLE_SPACING_RULE

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_SPACING_RULE

TABLE_BOMGROUP_ITEM

TABLE_PHYSICAL_RULE

TABLE_SPACING_RULE

TABLE_PHYSICAL_RULE

TABLE_SPACING_RULE

TABLE_PHYSICAL_RULE

TABLE_SPACING_RULE

TABLE_PHYSICAL_RULE

TABLE_SPACING_RULE

TABLE_PHYSICAL_RULE

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

TABLE_PHYSICAL_RULE

TABLE_SPACING_RULE

TABLE_PHYSICAL_RULE

TABLE_SPACING_ASSIGNMENT

TABLE_SPACING_RULE

TABLE_SPACING_ASSIGNMENT

TABLE_SPACING_RULE

TABLE_PHYSICAL_RULE

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_PHYSICAL_RULE

TABLE_SPACING_ASSIGNMENT

TABLE_PHYSICAL_RULE

Design-Specific Rules

reduce DRCs caused by fan-out.

"BGA_P2MM" rule ensures these critical

Portable-specific Override Rules

"1MM" area defined around BGAs to

NO_TEST Properties

12

11

10

9

8

7

6

5

PREPREG

CORE

PREPREG

CORE

PREPREG

2

1

3

PREPREG

CORE

CONVENTIONAL CONSTRUCTION WITH Pxx TH VIA

SEE BOARD FILE FOR DETAILED INFORMATION

GROUND (1/2 OZ)

SIGNAL (1/2 OZ)

GROUND (1/2 OZ)

SIGNAL (1/2 OZ)

SIGNAL (1/2 OZ + COPPER PLATING)

CUT POWER PLANE (1 OZ)

SIGNAL (1/2 OZ + COPPER PLATING)

BOARD STACK-UP AND CONSTRUCTION

Layer-specific rules for 100-ohm differential impedance

Layer-specific rules for 110-ohm differential impedance

Layer-specific rules for 60-ohm single-ended impedance

Layer-specific rules for 50-ohm single-ended impedance

to any other signals.

LWR RT GPU

LWR CPU

LEFT CPU

UPPER RT GPU

DVI

1394

CHASSIS MOUNTS

BATT. CHGR

BOARD HOLES

CHASSIS GND CONNECTIONS

MECH. HOLES

HEATSINK MOUNTS

signals do not fan-out routed next

4

PREPREG

Layer-specific rules for 90-ohm differential impedance

INVERTER

BOM OPTIONS

Module Components

IS

OG-503040

SHLD-SM-LF

3

2

1

SH0200

HOLE-VIA-P5RP25

1

ZT0200

HOLE-VIA-P5RP25

1

ZT0201

HOLE-VIA-P5RP25

1

ZT0203

HOLE-VIA-P5RP25

1

ZT0202

HOLE-VIA-P5RP25

1

ZT0210

HOLE-VIA-P5RP25

1

ZT0211

HOLE-VIA-P5RP25

1

ZT0212

HOLE-VIA-P5RP25

1

ZT0221

HOLE-VIA-P5RP25

1

ZT0222

HOLE-VIA-P5RP25

1

ZT0223

GND_CHASSIS_UPPER_DVI

GND_CHASSIS_FW_LOWER_DVI

GND_CHASSIS_LCD

GND_CHASSIS_BATT_CHGR

GND_CHASSIS_INVERTER

I244

I245 I246

I247 I248

I249

I250

I251 I252

I253 I254

I255

I256

I257 I258

I259 I260

I261

I262

I263

I264 I265

I266

I267 I268

I269 I270

I271

I272 I273

I274

I275 I276

I277

110_OHM_DIFF

2.5 MM 1.0 MM

TOP,BOTTOM

2.5 MM

0.330 MM

337S3077

CPU_A8

1

CRITICAL

U3600

IC,A8,xxxGHZ

A7PM_1P5_LGA

IC,A7PM,R1.5,1.5GHZ,LGA,1.28V,23W,85C

CRITICAL

1

U3600

337S3163

U2100

IC,ASIC,I2,REV1.2,NB/SB,974 BGA

343S0383 CRITICAL

1

U2700

PMU_PROG

CRITICAL

1

341S1772

IC,PMU05,V1,QFP

2.5 MM 1.0 MM

90_OHM_DIFF

TOP,BOTTOM

2.5 MM

0.200 MM

Y

5 MM

0.1 MM

90_OHM_DIFF

*

0.125 MM

2.5 MM 1.0 MM2.5 MM

100_OHM_DIFF

*

0.200 MM

50_OHM_SE

1.25 MM

0.100 MM0.100 MM

* Y

USB2_NEC,USB1P1_NEC,TPAD_SEQ_PMU

gUSB

0.1 MM

*

DEFAULT

2.5 MM

10.0 MM 15.0 MM0.15 MM

U8500

343S0356343S0388

v1.4 is alt to v1.3

100_OHM_DIFF

Y

5 MM

0.1 MM

TOP,BOTTOM

0.092 MM

0.100 MM 0.100 mm

1.25 MM

Y

DEFAULT

*

1MM

*

AGP_STB

BGA_P2MM

Y

5 MM

0.1 MM

TOP,BOTTOM

0.118 MM

90_OHM_DIFF

=60_OHM_SE

VGA

=60_OHM_SE =60_OHM_SE =60_OHM_SE

*

50_OHM_SE

*

1.0 MM2.5 MM

0.125 MM

2.5 MM

=DEFAULT

TV

=DEFAULT =DEFAULT=DEFAULT

*

0.15 MM

151

BGA_P1MM

1MM

* *

2.5 MM 1.0 MM2.5 MM

110_OHM_DIFF

*

0.300 MM

201 0.2 MMAGP

*

=60_OHM_SE =60_OHM_SE

TV

=60_OHM_SE =60_OHM_SE

*

PCBA,MLB,BESTMHZ,MARIAS,VRAM_S,Q16C

630-7016

COMMON,ALTERNATE,gQ16C,gQ16C_BST,Q16C_BST_VRAM_S,VRAM_SAMSUNG,gCommon

U2700

1

337S3135

PMU_BLANK

CRITICAL

IC,PMU05,BLANK,QFP

0.200 MM

100_OHM_DIFF

2.5 MM 1.0 MM

TOP,BOTTOM

2.5 MM

TOP,BOTTOM

0.1 MM

5 MM

Y

110_OHM_DIFF

0.080 MM

*

STANDARD =DEFAULT =DEFAULT =DEFAULT=DEFAULT

*

=DEFAULT=DEFAULT =DEFAULT=DEFAULT

VGA

0.15 MM

151

=50_OHM_SE

Y

60_OHM_SE

*

0.076 MM

=50_OHM_SE

RAM_DIFF

*

BGA_P2MM

1MM

2.5 MM 1.0 MM2.5 MM

*

0.200 MM

90_OHM_DIFF

337S3162

IC,A7PM,R1.5,1.67GHZ,LGA,1.28V,23W,85C

A7PM_1P67_LGA

CRITICAL

1

U3600

CRITICAL

4

IC,GDDR SDRAM,2MX32X4,300MHZ, LF FBGA144

333S0314

VRAM_HYNIX

U6200,U6250,U6300,U6350

CRITICAL

IC,GDDR SDRAM,2MX32X4,300MHZ, LF FBGA144

4

333S0317

VRAM_SAMSUNG

U6200,U6250,U6300,U6350

1

U8500

CRITICAL343S0356

IC,ASIC,VESTA,V1.3,LF

*

BGA_P2MM

1MM

CLOCK

0.085 MM

0.1 MM

5 MM

Y

110_OHM_DIFF

*

0.25 MM

251

AGP_STB

*

NO_TYPE,1MM

MM

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM

*

100_OHM_DIFF

0.1 MM

5 MM

Y

0.100 MM

U7100

341S1736

BOOTROM_PROG

CRITICAL

1

IC,BOOTROM,B,Q16C

BOOTROM_BLANK

335S0088

U7100

CRITICAL

BOOTROM,BLANK

1

U5700

1

CRITICAL

IC,GPU,M11P

338S0252

BGA_P2MM

0.20 MM

*20

1.25 MM

0.1 MM

12.5 MM 15.0 MM

0.10 MM 1.25 MM

0.1 MM

12.5 MM

BGA_P1MM

*10

15.0 MM

=DEFAULTSTANDARD =DEFAULT =DEFAULT=DEFAULT

*

=DEFAULT=DEFAULT

A7PM_1P67_LGA,CPU0_BUSRATIO_10.0X,CPU0_VCORE_1V28,CPU0_AVDD_1V28,Q16BST

gQ16C_BST

Q16C_PARTS,BOOTROM_PROG,PMU_PROG,MAXBUS_TBEN_SYNC

gQ16C

VESTA_PORT2_DISABLE,DVO_1V8,TMDS_DUAL,VCORE_OFFSET,VCORE_OFFSET_SW,gUSB

gCommon4

CPU_VCORE_2STATES,I2_MAXBUS_166MHZ,I2VCORE_1V5,I2VCORE_BURST,gCommon4

gCommon3

I2_REV1_NOT,I2_MAXBUS_FBCLK_MATCHED,I2_AGP_FBCLK_MATCHED,I2_PCI_FBCLK_MATCHED,gCommon3

gCommon2

MMM_ACCEL_KIONIX,GPU_PWRPLAY,GPU_SS,GPU_LVDDR_2V8,GPU_MEMIO_1V8,gCommon2

gCommon1

5V_HD_LOGIC,BACKUP_BATT,CPU_A7PM,I2_FW_BETA,I2_MAXBUS_50OHM,MAXBUS_1V8,gCommon1

gCommon

PCBA,MLB,BESTMHZ,MARIAS,VRAM_H,Q16C

630-7185

COMMON,ALTERNATE,gQ16C,gQ16C_BST,Q16C_BST_VRAM_H,VRAM_HYNIX,gCommon

Board Information

SYNC_DATE=N/A

SYNC_MASTER=N/A

051-6929

C

115

2

=GND_CHASSIS_BATTCHGR_HOLE

=GND_CHASSIS_INV_GND_CLIP

NO_TEST=TRUE

UATA_DA_R<1>

NO_TEST=TRUE

UATA_DA_R<0>

TP_NEC_SRCLK

NO_TEST=TRUE

TP_USB2_PWREN<3>

NO_TEST=TRUE

TP_USB2_PWREN<2>

NO_TEST=TRUE

TP_USB2_PWREN<0>

NO_TEST=TRUE

=GND_CHASSIS_SLEEP_LED

=GND_CHASSIS_BATTCHGR_HOLE

=GND_CHASSIS_INVERTER1 =GND_CHASSIS_INVERTER2

=GND_CHASSIS_DVI_HOLE =GND_CHASSIS_DVI2 =GND_CHASSIS_DVI4

=GND_CHASSIS_FW_HOLE =GND_CHASSIS_DVI1 =GND_CHASSIS_DVI3 =GND_CHASSIS_TV =GND_CHASSIS_ENET =GND_CHASSIS_FW_PORT1 =GND_CHASSIS_FW_PORT2 =GND_CHASSIS_FW_EMI

=GND_CHASSIS_LCD1 =GND_CHASSIS_LCD2 =GND_CHASSIS_LCD3 =GND_CHASSIS_LCD4

TP_OPTICAL_DRIVE_SCREW

TP_RT_KYBRD_SCREW

TP_LEFT_KYBRD_SCREW

=GND_CHASSIS_FW_HOLE

=GND_CHASSIS_DVI_HOLE

NO_TEST=TRUE

TMDS_CONN_CLKP

NO_TEST=TRUE

1778_ITH_RC

UATA_DD_R<0>

NO_TEST=TRUE

TP_VESTA_DNC_E9

NO_TEST=TRUE

TP_VESTA_F1000

NO_TEST=TRUE

TP_VESTA_PHYA<0> TP_VESTA_REGSEN2

NO_TEST=TRUE NO_TEST=TRUE

TP_VESTA_SPD0 USB_NEC_BT_N

NO_TEST=TRUE NO_TEST=TRUE

USB_NEC_N<1>

USB_NEC_P<1>

NO_TEST=TRUE

SI_TMDS_DP<3>

NO_TEST=TRUE

SI_TMDS_DN<2>

NO_TEST=TRUE

SI_TMDS_DN<1>

NO_TEST=TRUE

SI_TMDS_DN<4>

NO_TEST=TRUE

SI_TMDS_DN<5>

USB_NEC_N<2>

NO_TEST=TRUE NO_TEST=TRUE

USB_NEC_N<3>

SI_TMDS_CLKP

NO_TEST=TRUE

SI_TMDS_DN<0>

NO_TEST=TRUE

USB_NEC_P<0>

NO_TEST=TRUE

1778_VRNG

NO_TEST=TRUE

GPU_DVOD_R<18>

NO_TEST=TRUE

LTC3412_RUNSS

NO_TEST=TRUE

UATA_DD_R<8>

NO_TEST=TRUE

UATA_DD_R<10>

TP_NEC_SMC

NO_TEST=TRUE

TP_NEC_SMI_L

NO_TEST=TRUE

MIN_NECK_WIDTH=0.25 mm

VOLTAGE=0V

MAKE_BASE=TRUE MIN_LINE_WIDTH=0.5 mm

MAKE_BASE=TRUE VOLTAGE=0V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=0V

MAKE_BASE=TRUE

MAKE_BASE=TRUE VOLTAGE=0V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=0V

MAKE_BASE=TRUE

63

11

53

63

2

6

62

73

30

2

56

2

57

2

57

67

70

56

2

57

45

6

18

66

18

66

6

73

55

54

55

73

54

73

45

6

17

6

62

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

U2100

(x2 Channels)

64BITS

240MHZ

ATI

MEMORY CH A U6200/U6250

Connector

P.70

2 DATA PAIRS @ 400MHZ

P.58

MEMORY BUS

1.8V

64BITS

167MHZ

1.8V

MEMORY BUS

1.5V/3.3V 32BITS

M11P

P.44-53

P.49

MEMORY CH B

4 DATA PAIRS

U8500

Vesta Combo

Ethernet

FW - A

J9020

P.30

BOOT ROM

Connector

128MB

U6300/U6350

LEFT USB2

P.50

P.60

P.30

P.74

JA000J3320

10/100/1000

3.3V

P.67

Ethernet

J8600

Audio

U5700

8BIT TX 8BIT RX

P.69

FireWire

EDID (I2C)

COMPOSITE

ALS Sensors

Connector

10/100/1000

800 Mb/S

FIREWIRE

P.63

P.21

x2

P.27

U2700

P.57

125MHZ

100MHZ

UATA

P.24

CARDBUS

J7400

SMS Sensor

P.29

U3220

Connector

S-Video

(VIA SIL1178)

Connector

LCD Panel

P.43

4X AGP

P.59

32BITS

PCI

P.21

BOOTROM

1M X 8

J7300

AIRPORT

Connector

P.57

RGB

P.60

NEC USB2.0

P.62

66MHZ

AGP BUS

RIGHT USB2

Trackpad (1.1)

BlueTooth (1.1)

P.56

J6900

DDR2 MEMORY

G/MII

UNUSABLE

Connector

P.66

P.7

CPU PLL

Config

P.33-35

(MPC7448)

U3600

167MHZ

1.8V

MAXBUS

A7PM

CPU

64BIT DATA

32BIT ADDR

J5000/J5200

P.40/41

P.47

MAXBUS

P.32

ETHERNET

PORTS A-F

USB2.0

P.73

P.65

3.3V

8BIT TX/RX

P.68

I2

UATA 100

P.64

DDR2 SDRAM DIMM 1

DDR2 SDRAM DIMM 0

SO-DIMM Connector

Connector

Inverter

J6950

P.56

LVDS

J7060 J7000

TMDS

S-VIDEO

33MHZ

P.21

SCCA

VIA/PMU

P.21

x2

I2S

I2C

P.21

U7100

I2C

Circuit

Fan

Serial Debug

Connector

J2690

P.24

U3000

PHY

1394 OHCI

P.70

@ 200MHz

2 DATA PAIRS

J8200/J8250

HDD/ODD

Connectors

FW - B

J9010

Connector

SW MODEM

Connector

SLEEP

LED

DVI-I

U1250

DDC

CONN

P.25

SMBUS

3.3V

PMU

U7500

U7400

Connector

TI PCI1510

CardBus

Controller

EHCI HC

P.61

PCI BUS

33MHZ

32BITS

3.3V

33MHZ 16/32 BITS

3.3V/5V

SENSOR

P.12

Battery

Connector

BATTERY

CURRENT

J1250

& Charger

Power Supply

P.13-17

Connector

J3400

P.31

DC-In

SYNC_DATE=N/A

051-6929

C

115

3

SYNC_MASTER=N/A

System Block Diagram

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

VRAM I/O

VRAM CORE

PMU

GPU_VCORE

CPU_VCORE

INCORRECT

3S 2P 18650 CELLS

SLEEP: STOPPED

SLEEP

5V_RUN

5V_PWRON

3V3_PWRON 3V3_RUN

3V_5V_OK 2V5_PWRON

1V8_PWRON 1V8_RUN

1V5_PWRON

GPU_VCORE

CPU_VCORE

1V5_RUN

2V5_RUN

(CONTROLLED BY PMU)

14V_PBUS

POWER SEQUENCE

NO INRUSH PROTECTION

5V_PWRON

3V3_ALL

4V6_ALL

3V3_ALL

I2 CORE

+1.5V

SLEEP: RUNNING

RUN: RUNNING

SHUTDOWN: STOPPED

(LTC3412)

DC/DC

(LTC3412)

SHUTDOWN: STOPPED

RUN: RUNNING

SLEEP: RUNNING

2V5_PWRON

SHUTDOWN: STOPPED

+24V_PBUS

VCC

RC AT 1M*0.1UF @ 24V

+24V_PBUS

& BOOST OUTPUT

MAXBUS

5V_PWRON

3V3_PWRON

5V_PWRON

(+1.3V)

(LTC3707)

SHUTDOWN: STOPPED

RUN: RUNNING

+1.3V

AGP I/O

DDR2 POWER

1V8_1V5_OK

1V5_PWRON

1V8_PWRON

5V_PWRON

MAIN 3V/5V

INTERNAL ZENER CLAMP TO 6V

PGOOD

RUN/SS - 5V

RC AT 1M*0.047UF @ 24V

RUN: RUNNING

SLEEP: RUNNING

SHUTDOWN: RUNNING

AC: 12.8V

<~13.44V SHUTS-OFF

>~13.44V TURNS-ON

POWER SYSTEM ARCHITECTURE

MAIN 1.8V/1.5V

1625 NOT RUNNING

INVERTER

<100UA ALLOWED

DC/DC

STBYMD

SLEEP: RUNNING

RUN: RUNNING

INTERNAL ZENER CLAMP TO 6V

<100UA ALLOWED

TURNS ON AT >1V

RUN/SS - 3V

WHEN ONLY BATTERY IS CONNECTED

BATTERY VOLTAGE

FEED-IN PATH

BACKUP BATTERY

24V IS OUTPUT ONLY FROM

BACKUP

+BATT

AC

+PBUS

14V CHARGES BACKUP BATTERY

+PBUS

14V_PBUS

1V20_REF

TURNS ON AT >1V

LDO

BACKUP BATTERY CIRCUIT CHARGES OFF +PBUS

+PBUS

(UNTIL DRAINED)

-

+

INTERNAL 1.2UA CURRENT SOURCE

AND PREVENTS +PBUS AND +24V_PBUS FROM DROPPING BELOW 6V

IN

INRUSH

LIMITER

RUN/SS

BUCK

REGULATOR

VCC

NO AC: BATTERY VOLTAGE

(LTC1625)

(MAX1772)

CHARGER

BATTERY

+BATT

CHARGER INPUT

BATTERY

NO INRUSH PROTECTION

3V_5V_OK

BACKLIGHT

VCC

DC/DC

(MAX1715)

PGOOD

SHUTDOWN: STOPPED

SLEEP: RUNNING

RUN: RUNNING

TURNS ON OUTPUT @ 2.4V

ON1/ON2

VCC

DC/DC

(MAX1717)

SHUTDOWN: STOPPED

SLEEP: STOPPED

RUN: RUNNING

VCC

EXT_VCC

DC/DC

(LTC1778)

TURNS ON AS LOW AS 0.8V/TYP 1.5V

RUN/SS

HOLDS BOTH RUN/SS AT GND WHEN IT’S CONNECTED TO GND

TURNS CONTROL TO RUN/SS WHEN IT’S OPEN

SHUT-DOWN

RUN

SLEEP

RUN

SHUT-DOWN

~8.2MS

??? MS

2.4V - ??? MS

~7.36MS

~2.23MS

ADAPTER

SYNC_DATE=N/A

SYNC_MASTER=N/A

Power Block Diagram

4

115

C

051-6929

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

- Added R0985 10K pull down on JTAG_CPU0_TCK

- Added R3772 10K pull down on CPU0_EXT_QUAL on Mullet and sync’d

- Changed R2949 to NO STUFF for BOM.

- Changed C1721 and C2205 to 2200pF

- Changed C1730 to 5.6pF

- Changed C1700 and C1701 and C2215 andC2216 to 47uF

- Changed R1720 and R2205 to 7.5K

- Changed D1460,D1461 to 60V schottky to reduce reverse leakage

- Changed R2958 to 10K for improved power sequencing timing

REVISION HISTORY

- Beginning revision history

- Modem connector moved to non-shared page

- Chassis grounds partitioned as in previous products

- Made additional FB pin swaps

- Changed DDR2 CS/CKE RPAKs to RPAK2P (added RP4871, RP4876)

04/11/2005

08/02/2005 08/03/2005

08/16/2005 08/17/2005

- Various Pb-free replacements

- Changed TMDS drive strength resistors to 301 ohm, which was built at EVT

- Changed CPU Vcore to 2-states only (no MUX)

- Removed 1.5GHz config

- Added external 1K pullups in parallel with all I2 internal pullups

- Changed TMDS transmitter ferrites to part with higher current rating (1.5A)

- Released as REV 06 for DVT

- Replaced 371S0299 with 371S0300

- Changed PCI ZDB output series term to 22 ohms

- Changed power supply jumpers to shorts

- Added remaining spacing and physical rule tables

04/12/2005

04/06/2005

- Changed Q2941 to level shift/pass FET to correct GPU VCore and CPU Vcore power sequencing

- Moved R2943 to SYS_PWRSEQ_1_L to correct trackpad power state in sleep

- Moved =PP3V3_I2C_SB to RUN rail to correct pumpup problem in sleep

- Added FET to allow PMU control of trackpad power sequencing

- Removed I2’s connection to TBEN (leakage path)

- Changed NEC USB2 series R value to 39.2 ohm

- Added BOMOPTIONs for and stuffed CPU Vcore at 1.28V and 1.30V

- Added resistor mux for I2’s MAXBUS I/O rail (PWRON vs RUN)

- Moved UATA_DSTROBE cap to other side of series resistor

- Changed PCI clock series Rs to 0 ohms

- Changed CPU clock series Rs to 10 ohms

07/18/2005

07/06/2005

07/08/2005 07/09/2005

- Removed series R isolating VG from digital ground on FW ports (per design guide)

- Corrected synonym problems on PMU port usage

- Moved FB series R to page 61

- Made DDR2 and FB pin swaps as requested by CM

- CPU0 Vcore A/B select line hooked to I2 GPIO1

- Stuffed R2903 to disable FW port power when off on AC

- Corrected MIN_LINE_WIDTH properties on PP3V3_PWRON

- Corrected line and neck width properties

07/14/2005

- Implemented FireWire pin swaps

- Added 1.5V DVO option to GPU

- Added NO_TEST properties to buses between JTAG enabled devices

- Added external pullups to replace missing internal I2 pullups

- Corrected load capacitance for Vesta FireWire crystal (to 18pF)

- Various Pb-free component replacements

EVT

04/04/2005

04/18/2005

- Corrected ENET power rail to PWRON from RUN (for Wake-on-LAN)

- Fixed ENET_LOWPWR and VESTA_RESET circuits per Vesta design guide

- Corrected STOP_AGP_L net name (hooked to I2 now) and removed redundant pullup

- Pinswapped UATA I/F, DVO I/F, USB pulldowns

- Corrected USB2 diff pair and spacing/physical rules on port connections

- Released as REV 02 for EVT

06/02/2005

- Corrected FireWire VP caps to 50V

- Removed SMS PIC microcontroller

- Added NEC USB2 controller

- Added ZDB clock buffer for PCI clocks

04/14/2005 - Changed GPU to M11

05/20/2005 05/21/2005

- Corrected AGP_INT_L connection between I2 and GPU

- Added DASP signal between HDD and ODD connectors

05/23/2005

- Release as REV 01 for Pre-EVT/EVT

- Corrected VGA sync connections at GPU

05/25/2005

05/24/2005

- Added PDIAG signal between HDD and ODD connectors

05/19/2005 - Various Pb-free component replacements

- Added TBEN sync circuit

- Various Pb-free component replacements

- Pinswaps for I2 RPAKs to match up with Q41C style layout

05/13/2005

- Added pulldown to Vesta LPWR_1394

05/10/2005

05/05/2005

- Added pulldowns to unused serial debug signals (DTR/RTS)

05/04/2005

- Added extra cap at input to I2 USBAVDD

05/03/2005

- Changed 220uF CPU VCore caps to 330 uF LF caps

04/22/2005

- Disconnected FW_POWERDOWN from Vesta LPWR_1394 pin

04/21/2005

04/20/2005

04/15/2005

04/13/2005

- Changed audio caps to X5R (CA033, CA050, CA051)

04/06/2005

- Added RAM_DQS_N pulldowns

04/19/2005

05/16/2005

- Added Hynix VRAM option and PCBAs

05/31/2005

05/26/2005

06/01/2005

06/03/2005

06/07/2005

- Added ADC caps at PMU

- Added CPU0 VCore VID mux

06/28/2005

- Implemented more DDR2 pin swaps

- Added upper LVDS channel to functional test page

- Released as REV 04 for EVT

- Added audio mute sequencing FETs

- Added line width constraints to LTC1625 and CPU Vcore gate nodes

- Added 150 ohm pulldowns to FW_CTL lines at Vesta

07/19/2005

07/22/2005 07/25/2005

- Changed 32.768kHz crystal to new APN specifing 1uW drive parts

- Changed to USB1P1_NEC BOMOPTION

- Corrected alternate errors and a leaded table item

- Released as REV 03 for EVT

- Corrected pulldown resistor value for 0.006 ohm battery current sense

- Added page 6 and modified pages 11,35,81 for design specific pin swaps

- Changed all external I2 GPIO pullups to 10K

- Stuffed R2452, R2462, R2463 to correct I2 2.5V pullup problem

- Swapped I2_MAXBUS_33OHM and I2_MAXBUS_50OHM BOMOPTIONs

- Changed to Vesta v1.4 as primary U8500, Vesta v1.3 as alternate

07/26/2005

- Swapped locations (i.e values) of C2500 and C2501

07/29/2005

DVT

- Changed battery sense resistor to 0.006 ohm (R1250)

- Added 10K pullup to VIA_REQ_L

- Added 2 0.1uF caps to GPU Vcore regulator output

- Various Pb-free component replacements

- Changed GPU FB MVREFs into separate dividers

- Changed R5880 to 6.34K to take GPU Vcore to 1.3V/1.05V

- Updated straps, VREF inputs and decoupling on GPU

- Added high/low swing BOMOPTIONs for DVO on SI TMDS parts

- Reduced MIN_NECK_WIDTH property on GND to 0.2 mm for TMDS parts

- Corrected TMDS DIFFERENTIAL_PAIR properties at DVI connector

- Updated BOM options on CPU Vcore and AVDD for 1.22,1.30, and 1.33V

08/22/2005

08/18/2005

- Added five ceramic caps to Vcore supply

- Changed C3940-C3947 to 1206 ceramic caps

08/05/2005

- Released as REV 07 for DVT

- Added FETs to prevent leakage onto Vesta rails

- Changed C8600-C8603 to 1uF due to insertion of FET

- Changed R5822 to 100K for power sequence improvement

- NO STUFFed R2969 for power sequence improvement

Pre-PVT

PVT

08/24/2005

- Released as REV 08 for Pre-PVT

- Released as REV A for PVT

08/29/2005

- Stuffed R8420 with 10K, 5% to ensure MDIO logic levels

08/31/2005 09/02/2005

- Stuffed R2464 to correct unused GPIO logic level

- Changed MLB to 820-1940, which corrects tolerance on DIMM conn holes

C

5

115

C

051-6929

SYNC_MASTER=N/A

SYNC_DATE=N/A

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(IDE_CS1FX_L)

UATA Series Rs

Upper DVO Series Rs

AGP Pullups

PCI Pullups

Lower DVO Series Rs

I2S Series Rs

MAXBUS Pullups

USB Pulldowns

FW Series Rs

Q16C Pin Swaps

SYNC_DATE=N/A

SYNC_MASTER=N/A

6

115

C

051-6929

NO_TEST=YES

MAKE_BASE=TRUE

NC_MAXBUS_I2_TBEN

MAXBUS_CPU1_INT_L

MAKE_BASE=TRUE

MAXBUS_CPU0_DRDY_L

=RP3513P3 =RP3513P4

FW_D_R<7>

MAKE_BASE=TRUE

MAXBUS_TEA_L

MAKE_BASE=TRUE

FW_D<5>

MAKE_BASE=TRUE

FW_D<1>

MAKE_BASE=TRUE

FW_D<0>

MAKE_BASE=TRUE

FW_D<6>

MAKE_BASE=TRUE

FW_D<4>

MAKE_BASE=TRUE

FW_D<2>

MAKE_BASE=TRUE

FW_D<3>

MAKE_BASE=TRUE

FW_D<7>

=RP9100P7

=RP9100P8

=RP9100P2

=RP9100P1

=RP9101P8

=RP9100P6 =RP9100P5

=RP9101P5

=RP9101P6

=RP9101P7

=RP9101P1

=RP9100P4

=RP9100P3

=RP9101P4

=RP9101P3

=RP9101P2

FW_D_R<5>

MAKE_BASE=TRUE

FW_D_R<1>

MAKE_BASE=TRUE

FW_D_R<6>

MAKE_BASE=TRUE

FW_D_R<0>

MAKE_BASE=TRUE

FW_D_R<3>

MAKE_BASE=TRUE

FW_D_R<2>

MAKE_BASE=TRUE

FW_D_R<4>

MAKE_BASE=TRUE

=RP9301P5

=RP9301P6

=RP9301P7

=RP9301P8

=RP9300P5

=RP9300P6

=RP9300P7

=RP9300P8

USB_NEC_BT_P

MAKE_BASE=TRUE

USB_NEC_BT_N

MAKE_BASE=TRUE

USB_NEC_TPAD_N

MAKE_BASE=TRUE

USB_NEC_TPAD_P

MAKE_BASE=TRUE

USB2_NEC_RIGHT_PORT_P

MAKE_BASE=TRUE

USB2_NEC_RIGHT_PORT_N

MAKE_BASE=TRUE

USB2_NEC_LEFT_PORT_N

MAKE_BASE=TRUE

USB2_NEC_LEFT_PORT_P

MAKE_BASE=TRUE

USB_I2_BT_P

MAKE_BASE=TRUE

USB_I2_BT_N

MAKE_BASE=TRUE

USB2_I2_RIGHT_PORT_N

MAKE_BASE=TRUE

USB2_I2_RIGHT_PORT_P

MAKE_BASE=TRUE

USB2_I2_P<3>

MAKE_BASE=TRUE

USB2_I2_N<3>

MAKE_BASE=TRUE

USB2_I2_N<1>

MAKE_BASE=TRUE

USB2_I2_P<1>

=RP9210P8 =RP9210P7 =RP9210P6 =RP9210P5

=RP9211P8 =RP9211P7 =RP9211P6 =RP9211P5

MAKE_BASE=TRUE

PCI_FRAME_L

=RP7251P4

MAKE_BASE=TRUE

PCI_CBUS_GNT_L

=RP7251P3

MAKE_BASE=TRUE

PCI_CBUS_REQ_L

=RP7251P1

MAKE_BASE=TRUE

PCI_AIRPORT_REQ_L

=RP7251P2

=RP3511P2 =RP3511P3 =RP3511P4

=RP3510P1 =RP3510P2

=RP3511P1

MAKE_BASE=TRUE

MAXBUS_TS_L MAXBUS_CPU1_BG_L

MAKE_BASE=TRUE

MAXBUS_CPU0_BG_L

MAKE_BASE=TRUE MAKE_BASE=TRUE

MAXBUS_CPU1_HIT_L

MAKE_BASE=TRUE

MAXBUS_CPU0_HIT_L MAXBUS_CPU0_BR_L

MAKE_BASE=TRUE

I2S0_SB_TO_DEV_DTO_R I2S0_BITCLK_R

MAKE_BASE=TRUE

I2S0_MCLK_R

MAKE_BASE=TRUE

I2S0_SYNC_R

MAKE_BASE=TRUE

I2S1_SYNC_R

MAKE_BASE=TRUE

I2S1_SB_TO_DEV_DTO_R

I2S1_MCLK_R

MAKE_BASE=TRUE

I2S1_BITCLK_R

MAKE_BASE=TRUE

=RP1150P1 =RP1150P2 =RP1150P3 =RP1150P4

=RP1151P1 =RP1151P2 =RP1151P3 =RP1151P4

=RP1150P7

=RP1150P8

=RP1150P6 =RP1150P5

=RP1151P7

=RP1151P8

=RP1151P6 =RP1151P5

MAKE_BASE=TRUE

I2S0_SB_TO_DEV_DTO I2S0_BITCLK

MAKE_BASE=TRUE

I2S0_MCLK

MAKE_BASE=TRUE

I2S0_SYNC

MAKE_BASE=TRUE

I2S1_BITCLK

MAKE_BASE=TRUE

I2S1_SYNC

MAKE_BASE=TRUE

I2S1_SB_TO_DEV_DTO

I2S1_MCLK

MAKE_BASE=TRUE

MAXBUS_TA_L

MAKE_BASE=TRUE

MAXBUS_CPU1_BR_L

MAKE_BASE=TRUE

MAXBUS_CPU0_INT_L

MAKE_BASE=TRUE

MAXBUS_AACK_L

MAKE_BASE=TRUE

MAXBUS_ARTRY_L

MAKE_BASE=TRUE

MAXBUS_CPU1_DBG_L

=RP3514P3

=RP3514P2

=RP3512P2

=RP3512P1

=RP3512P4

=RP3512P3

=RP3513P2

MAKE_BASE=TRUE

UATA_DD_R<4>

MAKE_BASE=TRUE

UATA_DD_R<9>

MAKE_BASE=TRUE

UATA_DD_R<5>

MAKE_BASE=TRUE

UATA_DD_R<6>

MAKE_BASE=TRUE

UATA_DA_R<2>

MAKE_BASE=TRUE

UATA_DD_R<10>

MAKE_BASE=TRUE

UATA_DD_R<8>

MAKE_BASE=TRUE

UATA_DA_R<0>

MAKE_BASE=TRUE

UATA_DD_R<13>

MAKE_BASE=TRUE

UATA_DD_R<1>

MAKE_BASE=TRUE

UATA_DD_R<0>

MAKE_BASE=TRUE

UATA_DA_R<1>

=RP8153P4

=RP8154P1

=RP8154P3

=RP8154P2

=RP8154P4

=RP8153P5

=RP8154P8 =RP8154P7 =RP8154P6 =RP8154P5

=RP8152P2

=RP8152P1

=RP8152P4

=RP8152P3

=RP8153P1

=RP8153P3

=RP8153P2

=RP8152P8 =RP8152P7 =RP8152P6 =RP8152P5

=RP8153P7

=RP8153P8

=RP8153P6

MAKE_BASE=TRUE

UATA_DD<9>

MAKE_BASE=TRUE

UATA_DD<4>

MAKE_BASE=TRUE

UATA_DD<6>

MAKE_BASE=TRUE

UATA_DD<5>

MAKE_BASE=TRUE

UATA_DD<8>

MAKE_BASE=TRUE

UATA_DA<2>

MAKE_BASE=TRUE

UATA_DD<10>

MAKE_BASE=TRUE

UATA_DA<0>

MAKE_BASE=TRUE

UATA_DD<13>

MAKE_BASE=TRUE

UATA_DD<0>

MAKE_BASE=TRUE

UATA_DD<1>

MAKE_BASE=TRUE

UATA_DA<1>

GPU_DVOD_R<20>

MAKE_BASE=TRUE

GPU_DVOD_R<22>

MAKE_BASE=TRUE

GPU_DVOD_R<23>

MAKE_BASE=TRUE

GPU_DVOD_R<18>

MAKE_BASE=TRUE

=RP6823P1

=RP6823P3

=RP6823P2

=RP6823P4

GPU_DVOD<16>

MAKE_BASE=TRUE

=RP6720P8

GPU_DVOD<7>

MAKE_BASE=TRUE

=RP6720P6

GPU_DVOD<4>

MAKE_BASE=TRUE

=RP6720P7

GPU_DVOD<11>

MAKE_BASE=TRUE

=RP6721P8

GPU_DVOD<6>

MAKE_BASE=TRUE

=RP6720P5

=RP6720P1

GPU_DVOD_R<16>

MAKE_BASE=TRUE

=RP6720P3

GPU_DVOD_R<7>

MAKE_BASE=TRUE

=RP6720P2

GPU_DVOD_R<4>

MAKE_BASE=TRUE

=RP6720P4

GPU_DVOD_R<6>

MAKE_BASE=TRUE

=RP6721P1

GPU_DVOD_R<11>

MAKE_BASE=TRUE

GPU_DVOD<9>

MAKE_BASE=TRUE

=RP6721P7

GPU_DVOD<10>

MAKE_BASE=TRUE

=RP6721P6

GPU_DVO_HSYNC

MAKE_BASE=TRUE

=RP6721P5

GPU_DVOD<3>

MAKE_BASE=TRUE

=RP6722P8

GPU_DVOD<5>

MAKE_BASE=TRUE

=RP6722P7

GPU_DVOD<13>

MAKE_BASE=TRUE

=RP6722P6

GPU_DVOD<12>

MAKE_BASE=TRUE

=RP6722P5

GPU_DVOD<2>

MAKE_BASE=TRUE

=RP6723P8

GPU_DVOD<1>

MAKE_BASE=TRUE

=RP6723P7

GPU_DVOD<0>

MAKE_BASE=TRUE

=RP6723P6

GPU_DVOD<14>

MAKE_BASE=TRUE

=RP6723P5

=RP6721P2

GPU_DVOD_R<9>

MAKE_BASE=TRUE

=RP6721P3

GPU_DVOD_R<10>

MAKE_BASE=TRUE

=RP6721P4

GPU_DVO_HSYNC_R

MAKE_BASE=TRUE

=RP6722P1

GPU_DVOD_R<3>

MAKE_BASE=TRUE

=RP6722P2

GPU_DVOD_R<5>

MAKE_BASE=TRUE

=RP6722P3

GPU_DVOD_R<13>

MAKE_BASE=TRUE

=RP6722P4

GPU_DVOD_R<12>

MAKE_BASE=TRUE

=RP6723P1

GPU_DVOD_R<2>

MAKE_BASE=TRUE

=RP6723P2

GPU_DVOD_R<1>

MAKE_BASE=TRUE

=RP6723P3

GPU_DVOD_R<0>

MAKE_BASE=TRUE

=RP6723P4

GPU_DVOD_R<14>

MAKE_BASE=TRUE

PCI_STOP_L

MAKE_BASE=TRUE

PCI_TRDY_L

MAKE_BASE=TRUE

PCI_IRDY_L

MAKE_BASE=TRUE

PCI_AIRPORT_GNT_L

=RP7250P4

=RP7250P2 =RP7250P3

=RP7250P1

MAKE_BASE=TRUE

AGP_TRDY_L

MAKE_BASE=TRUE

AGP_REQ_L

MAKE_BASE=TRUE

AGP_RBF_L

MAKE_BASE=TRUE

AGP_IRDY_L

MAKE_BASE=TRUE

AGP_FRAME_L

MAKE_BASE=TRUE

AGP_DEVSEL_L

MAKE_BASE=TRUE

AGP_STOP_L

MAKE_BASE=TRUE

AGP_GNT_L

=RP5611P2 =RP5611P3 =RP5611P4

=RP5610P1

=RP5610P3 =RP5610P4

=RP5610P2

=RP5611P1

=RP6823P8 =RP6823P7 =RP6823P6 =RP6823P5

GPU_DVOD<20>

MAKE_BASE=TRUE

GPU_DVOD<22>

MAKE_BASE=TRUE

GPU_DVOD<23>

MAKE_BASE=TRUE

GPU_DVOD<18>

MAKE_BASE=TRUE

=RP9212P8 =RP9212P7 =RP9212P6 =RP9212P5

MAKE_BASE=TRUE

USB2_I2_LEFT_PORT_N

MAKE_BASE=TRUE

USB2_I2_LEFT_PORT_P

MAKE_BASE=TRUE

USB_I2_TPAD_P

MAKE_BASE=TRUE

USB_I2_TPAD_N

MAKE_BASE=TRUE

GPU_DVO_DE_R

MAKE_BASE=TRUE

GPU_DVO_VSYNC_R

MAKE_BASE=TRUE

GPU_DVO_CLKP_R

MAKE_BASE=TRUE

GPU_DVOD_R<8>

MAKE_BASE=TRUE

GPU_DVOD_R<21>

MAKE_BASE=TRUE

GPU_DVOD_R<19>

MAKE_BASE=TRUE

GPU_DVOD_R<17>

MAKE_BASE=TRUE

GPU_DVOD_R<15>

=RP6822P4

=RP6821P2

=RP6821P1

=RP6821P4

=RP6821P3

=RP6822P1

=RP6822P3

=RP6822P2

=RP6822P5

=RP6821P8 =RP6821P7 =RP6821P6 =RP6821P5

=RP6822P7

=RP6822P8

=RP6822P6

MAKE_BASE=TRUE

GPU_DVOD<15>

MAKE_BASE=TRUE

GPU_DVO_DE

MAKE_BASE=TRUE

GPU_DVO_VSYNC

MAKE_BASE=TRUE

GPU_DVO_CLKP

MAKE_BASE=TRUE

GPU_DVOD<8>

MAKE_BASE=TRUE

GPU_DVOD<21>

MAKE_BASE=TRUE

GPU_DVOD<19>

MAKE_BASE=TRUE

GPU_DVOD<17>

UATA_DD_R<12>

MAKE_BASE=TRUE

UATA_DD_R<14>

MAKE_BASE=TRUE

UATA_DD_R<11>

MAKE_BASE=TRUE

UATA_CS0_L_R

MAKE_BASE=TRUE

UATA_DD_R<7>

MAKE_BASE=TRUE

UATA_DD_R<2>

MAKE_BASE=TRUE

UATA_DD_R<3>

MAKE_BASE=TRUE

UATA_DD_R<15>

MAKE_BASE=TRUE

=RP8151P2 =RP8151P3 =RP8151P4

=RP8150P1

=RP8150P3 =RP8150P4

=RP8150P2

=RP8151P1

=RP8151P7 =RP8151P6 =RP8151P5

=RP8150P8 =RP8150P7

=RP8150P5

=RP8150P6

=RP8151P8

UATA_DD<12>

MAKE_BASE=TRUE

UATA_CS0_L

MAKE_BASE=TRUE

UATA_DD<11>

MAKE_BASE=TRUE

UATA_DD<14>

MAKE_BASE=TRUE

UATA_DD<2>

MAKE_BASE=TRUE

UATA_DD<7>

MAKE_BASE=TRUE

UATA_DD<3>

MAKE_BASE=TRUE

UATA_DD<15>

MAKE_BASE=TRUE

=RP3514P1

MAKE_BASE=TRUE

MAXBUS_CPU1_DRDY_L

=RP3510P3 =RP3510P4

MAXBUS_CPU0_DBG_L

MAKE_BASE=TRUE

62

61

64

61

64

33

68

33

69

68

11

60

33

74

33

34

33

63

63 53

55

60

44

55

63

33

32

9

32

9

71

9

73

11

2

11

72

59 59

11 59

32

22

11

7

30

32

63

2

63

2

63

7

53

2

55

55 54

54 54

54 53

54 54

55 54

54 54

55 54

54 53

59

11

59

43

55

72

72 11

11

53

53 55

55

54

55

63

7

32

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

of ODD/HDD connector.

AUDIO

INVERTER

UATA LVDS

POWER

Place within 25 mm of LVDS connector.

Place within 25 mm of inverter connector.

Place within 25 mm of audio connector.

Place within 50 mm

Functional test points use a P6 pad placed on bottom side.

Enhanced MAC-1 Test Coverage

Place 5-10 GND TPs.

Place 2 TPs @ connector

Place within 50 mm of power supply.

of TPAD connector.

Place within 25 mm

Place within 25 mm of fan connector.

of fan connector.

Place within 25 mm

of battery connector.

Place within 25 mm

of debug connector.

Place within 25 mm

of ALS connector.

of right USB connector.

of left USB connector.

SYSTEM

GPU FAN CPU FAN

ALS

SCCA

BACKUP

BATT

RT USBLT USB

I1

I10

I100

I101

I102

I104

I105 I106

I107 I108

I109

I11

I110 I111

I112

I113

I114

I115

I116

I117 I118

I119

I12

I120

I121

I13 I14

I15

I16

I17

I18

I19

I2

I20

I21

I22

I23

I24

I25

I29

I3

I30

I31

I32

I33

I34

I35

I36

I37

I38

I39

I4

I40

I41 I42

I43

I44

I45

I46

I47

I48

I49

I5

I50

I51

I52

I53

I55

I56

I57 I58

I59

I6

I60

I61

I62

I63

I64 I65

I66

I68

I69

I7

I70

I71

I72

I73

I74

I75

I76

I77

I78

I79

I8

I80

I81 I82

I83

I84 I85

I86

I87

I88

I89

I9

I90

I91

I96

I97

I98

SYNC_DATE=N/A

SYNC_MASTER=N/A

7

051-6929

C

115

Functional Test Points

USB2_LEFT_PORT_P

FUNC_TEST=YES

USB2_LEFT_PORT_N

FUNC_TEST=YES

=PP5V_PWRON_LEFT_USB

FUNC_TEST=YES

USB2_RIGHT_PORT_N

FUNC_TEST=YES

USB2_RIGHT_PORT_P

FUNC_TEST=YES

=PP5V_PWRON_RIGHT_USB

=PPVOUT_BU_BATT

FUNC_TEST=YES

=PPVIO_BU_BATT

FUNC_TEST=YES

SCCA_TXD_L

FUNC_TEST=YES

SCCA_RXD

FUNC_TEST=YES

ALS_GAIN_BOOST

FUNC_TEST=YES

ALS_0_OUT

FUNC_TEST=YES

=PP3V3_PWRON_LEFT_ALS

FUNC_TEST=YES

=FTP_GND

FUNC_TEST=YES

FAN2_PWM

FUNC_TEST=YES

FAN2_TACH

FUNC_TEST=YES

=PP5V_FAN2_PWR

FUNC_TEST=YES

=FTP_GND

FUNC_TEST=YES

FAN1_TACH

FUNC_TEST=YES FUNC_TEST=YES

FAN1_PWM

=PP5V_FAN1_PWR

FUNC_TEST=YES

=I2C_DS1775_SCL

FUNC_TEST=YES

=I2C_DS1775_SDA

FUNC_TEST=YES

KBDLED_RETURN

FUNC_TEST=YES

KBDLED_ANODE

FUNC_TEST=YES

SYS_ADAPTER_ANALOG_AC_DET

FUNC_TEST=YES

SYS_CHARGE_LED_L

FUNC_TEST=YES

=FTP_SLEEP_LED

SYS_POWER_BUTTON_L_F

FUNC_TEST=YES

SYS_LID_OPEN_F

FUNC_TEST=YES

PP3V3_ALL_HALL_EFFECT_R

FUNC_TEST=YES

SYS_OVERTEMP_L

FUNC_TEST=YES

PP3V3_PWRON_DS1775_R

FUNC_TEST=YES

USB_TPAD_N

FUNC_TEST=YES

USB_TPAD_P

FUNC_TEST=YES

PP5V_TPAD_F

FUNC_TEST=YES

PP24V_ADAPTER

FUNC_TEST=YES

PP24V_ALL_PBUSA

FUNC_TEST=YES FUNC_TEST=YES

PP12V8_ALL_PBUSB

FUNC_TEST=YES

PPVCORE_RUN_CPU

FUNC_TEST=YES

PPVCORE_RUN_GPU

FUNC_TEST=YES

PP1V8_PWRON

FUNC_TEST=YES

PP2V5_PWRON

FUNC_TEST=YES

PP5V_PWRON

FUNC_TEST=YES

PP3V3_PWRON

FUNC_TEST=YES

PP5V_RUN

FUNC_TEST=YES

PP3V3_ALL

FUNC_TEST=YES

=FTP_GND

LVDS_U0_P

FUNC_TEST=YES

LVDS_U0_N

FUNC_TEST=YES

LVDS_U1_P

FUNC_TEST=YES

LVDS_U1_N

FUNC_TEST=YES

LVDS_U2_P

FUNC_TEST=YES

LVDS_U2_N

FUNC_TEST=YES

CLKLVDS_U_P

FUNC_TEST=YES

LVDS_L0_P

FUNC_TEST=YES

CLKLVDS_U_N

FUNC_TEST=YES

LVDS_L0_N

FUNC_TEST=YES

LVDS_L1_P

FUNC_TEST=YES

LVDS_L1_N

FUNC_TEST=YES

LVDS_L2_N

FUNC_TEST=YES

LVDS_L2_P

FUNC_TEST=YES

CLKLVDS_L_P

FUNC_TEST=YES

CLKLVDS_L_N LVDS_DDC_CLK

FUNC_TEST=YES

LVDS_DDC_DATA

FUNC_TEST=YES

=PP3V3_DDC_LCD

FUNC_TEST=YES

PP3V3_LCD_CONN

FUNC_TEST=YES

PPBUS_INVERTER

FUNC_TEST=YES

PP5V_INV_SW

FUNC_TEST=YES

BRIGHT_PWM

FUNC_TEST=YES

GND_INVERTER

FUNC_TEST=YES

=PP5V_RUN_HDD

FUNC_TEST=YES

=PP5V_RUN_ODD

FUNC_TEST=YES

PP3V3R5V_RUN_HDD_LOGIC

FUNC_TEST=YES FUNC_TEST=YES

UATA_DD<15..0>

FUNC_TEST=YES

UATA_DMARQ

FUNC_TEST=YES

UATA_DMACK_L

FUNC_TEST=YES

UATA_DSTROBE

FUNC_TEST=YES

UATA_DA<2..0>

FUNC_TEST=YES

UATA_CS0_L

FUNC_TEST=YES

UATA_CS1_L

FUNC_TEST=YES

UATA_HSTROBE

FUNC_TEST=YES

UATA_RESET_L

FUNC_TEST=YES

UATA_STOP

FUNC_TEST=YES

UATA_INTRQ

FUNC_TEST=YES

PP5V_PWRON_AUDIO_PVDD

FUNC_TEST=YES

PP5V_PWRON_AUDIO_AVDD

FUNC_TEST=YES

PP3V3_PWRON_AUDIO_AVDD =PP3V3_RUN_AUDIO

FUNC_TEST=YES

=I2C_AUDIO_SCL

FUNC_TEST=YES

=I2C_AUDIO_SDA

FUNC_TEST=YES

I2S0_MCLK

FUNC_TEST=YES

I2S0_BITCLK

FUNC_TEST=YES

I2S0_SYNC

FUNC_TEST=YES

I2S0_SB_TO_DEV_DTO

FUNC_TEST=YES

I2S0_DEV_TO_SB_DTI

FUNC_TEST=YES

AUDIO_LO_MUTE_L

FUNC_TEST=YES

AUDIO_SPKR_MUTE_L

FUNC_TEST=YES

AUDIO_CODEC_RESET_L

FUNC_TEST=YES

AUDIO_SPDIFRX_RESET_L

FUNC_TEST=YES

AUDIO_LO_DET_L

FUNC_TEST=YES

AUDIO_LI_DET_L

FUNC_TEST=YES FUNC_TEST=YES

AUDIO_LO_OPTICAL_PLUG_L

FUNC_TEST=YES

AUDIO_LI_OPTICAL_PLUG_L

FUNC_TEST=YES

AUDIO_I2S_DTIB_SEL

FUNC_TEST=YES

AUDIO_EXT_MCLK_SEL

FUNC_TEST=YES

AUDIO_GPIO_11

FUNC_TEST=YES

GND_AUDIO_AGND GND_AUDIO_PGND

FUNC_TEST=YES

31

30

64

74

31

24

28

31

10

31

10

31

30

74

25

30

10

56

64

63

64

63

64

74

11

10

11

10

22

25

10

7

27

10

7

27

10

8

28

12

24

30

11

30

11

30 10

10

7

53

51

10

56

10

64

6

63

6

63

74

10

8

6

22

74

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

U2100

JA000U2100

SPDIF

Codec

Audio Board

(Write: 0x8C Read: 0x8D) (Write: 0x22 Read: 0x23)

(MASTER)

U5700

GPU I2C Bus

EXT TMDS/S

EXT TMDS/M

U6700

U6800

(Write: 0x70 Read: 0x71)

(Write: 0x72 Read: 0x73)

PMU SMBus

PMU unstead. One ADT7467 connects to NB

NOTE: Neither option is necessary when

PMU

Signal aliases required by this page:

- GOV_I2C / GOV_I2C_BYPASS

I2C bus 1 to resolve address conflict.

Selects whether MMM MCU is powered all

BOM options provided by this page:

Power aliases required by this page:

MMM_MCU_PMU BOM option is selected.

(NONE)

it can be monitored by in shutdown.

ALL moves the MCU to the PMU I2C bus so

the time or only when the system is on.

Most devices are connected directly to

Allows bypassing Governator I2C bus.

- MMM_PWR_ALL / MMM_PWR_PWRON

J790

Battery Conn

(Write: 0x16 Read: 0x17)

(MASTER)

PMU

U1300

(NONE)

PMU I2C Bus

U1300

(MASTER)

SouthBridge I2C Bus

J5000A / J5000B

DIMMs

(Write: 0xA0 / 0xA2, Read: 0xA1 / 0xA3)

(MASTER)

I2

NorthBridge I2C Bus

I2

GPU

Page Notes

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

SPACING

NET_TYPE

DIFFERENTIAL_PAIR

U3000

ADT7467

(Write: 0x5C Read: 0x5D)

DS1775

On Trackpad Flex

(Write: 0x92 Read: 0x93)

1/16W MF-LF 402

1%

7.15K

2

1

R0851

7.15K

1% 1/16W MF-LF

402

2

1

R0850

1K

5% 1/16W MF-LF 402

2

1

R0821

402

5%

1K

MF-LF

1/16W

2

1

R0820

5% 1/16W MF-LF

1K

402

2

1

R0843

1K

5% 1/16W MF-LF

402

2

1

R0842

402

1K

MF-LF

1/16W

5%

2

1

R0841

402

MF-LF

1/16W

5%

1K

2

1

R0840

1/16W

402

MF-LF

5%

2.0K

2

1

R0830

1/16W MF-LF 402

2.0K

5%

2

1

R0831

SYNC_DATE=N/A

SYNC_MASTER=N/A

I2C Connections

C

8

115

051-6929

=I2C_DS1775_SDA

=I2C_DS1775_SCL

=I2C_ADT7467_SDA

=I2C_ADT7467_SCL

I2C_I2_NB_SCL

MAKE_BASE=TRUE

I2C_I2_NB_SDA

MAKE_BASE=TRUE

I2C_I2_SB_SCL

I2CI2C

I2C_I2_SB_SDA

I2CI2C

I2C_GPU_TMDS_SDA

I2CI2C

I2C_GPU_TMDS_SCL

I2C I2C

I2C_NB

I2C_I2_NB_SCL

I2CI2C

I2C_PMU_SMB_SDA

I2CI2C

I2C_PMU_SDA

I2CI2C

I2C_PMU_SCL

I2C_PMU_SMB_SCL

I2C I2C

I2C_NB

I2C_I2_NB_SDA

I2CI2C

=I2C_I2_NB_SDA

=I2C_SODIMM_SDA

=I2C_I2_NB_SCL

=I2C_SODIMM_SCL

=PPI2C_I2_NB

=PPI2C_I2_SB

=I2C_I2_SB_SDA

=I2C_I2_SB_SCL

=I2C_PMU_SMB_SDA

=I2C_BATT_SDA

=I2C_PMU_SDA

=I2C_PMU_SCL

=I2C_PMU_SMB_SCL

=PPI2C_SYS1

=I2C_BATT_SCL

=PPI2C_SYS0

I2C_PMU_SCL

MAKE_BASE=TRUE

I2C_PMU_SDA

MAKE_BASE=TRUE

I2C_PMU_SMB_SCL

MAKE_BASE=TRUE

I2C_PMU_SMB_SDA

=PPI2C_GPU

MAKE_BASE=TRUE

I2C_GPU_TMDS_SCL

MAKE_BASE=TRUE

I2C_GPU_TMDS_SDA

=I2C_SI_M_SCL

=I2C_SI_M_SDA

=I2C_SI_S_SCL

=I2C_SI_S_SDA

=I2C_GPU_TMDS_SCL

=I2C_GPU_TMDS_SDA

MAKE_BASE=TRUE

I2C_I2_SB_SCL

MAKE_BASE=TRUE

I2C_I2_SB_SDA

=I2C_AUDIO_SCL

=I2C_AUDIO_SDA

30

41

74

7

27

8

22 40

10

22

25 12

25

10

12

10

8

10

8

54

55

51

8

7

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

I2

CPU0

VESTA

FIREWIRE

ENET

Nets not requiring TPs due to JTAG

MAXBUS

PMU (BOOTBANGER)

I100 I101

I102

I103

MF-LF 402

1/16W

5%

10K

NO STUFF

2

1

R0985

5%

10K

1/16W SM-LF

8

1

RP0990

5% 1/16W

10K

SM-LF

6

3

RP0990

402

MF-LF

1/16W

5%

1K

2

1

R0990

5% 1/16W

10K

SM-LF

2

7

RP0990

10K

5%

MF-LF

402

1/16W

2

1

R0950

10K

402

5%

MF-LF

1/16W

2

1

R0981

MF-LF 402

10K

5% 1/16W

2

1

R0982

402

1/16W

5%

10K

MF-LF

2

1

R0983

402

MF-LF

1/16W

5%

200

2

1

R0984

5% 1/16W MF-LF

402

10K

NO STUFF

2

1

R0980

I76 I77

I78 I79

I80

I81 I82

I83

I85

I86 I87

I88 I89

I90

I91

I92

I93

I94 I95

I96

I97 I98

I99

SYNC_MASTER=N/A

SYNC_DATE=N/A

JTAG Connections

115

9

051-6929

C

JTAG_CPU_TMS

MAKE_BASE=TRUE

JTAG_CPU_TCK

MAKE_BASE=TRUE

NO_TEST=YES

FW_CTL<1..0>

NO_TEST=YES

FW_CTL_R<1..0>

NO_TEST=YES

ENET_TXD<7..0>

NO_TEST=YES

FW_LREQ_R

NO_TEST=YES

FW_LPS

NO_TEST=YES

ENET_COL

NO_TEST=YES

ENET_RX_DV

NO_TEST=YES

ENET_MDC

NO_TEST=YES

ENET_MDIO

FW_LREQ

NO_TEST=YES

FW_LPS_R

NO_TEST=YES

FW_D_R<7..0>

NO_TEST=YES

FW_D<7..0>

NO_TEST=YES

ENET_RXD<7..0>

NO_TEST=YES

ENET_TX_ER

NO_TEST=YES

ENET_TX_EN

NO_TEST=YES

ENET_RX_ER

NO_TEST=YES

ENET_CRS

NO_TEST=YES

MAXBUS_DTI<2..0>

NO_TEST=YES

MAXBUS_TT<4..0>

NO_TEST=YES

MAXBUS_TSIZ<2..0>

NO_TEST=YES

MAXBUS_ADDR<31..0>

NO_TEST=YES

MAXBUS_DATA<63..0>

NO_TEST=YES

MAXBUS_CI_L

NO_TEST=YES

MAXBUS_TBST_L

NO_TEST=YES

MAXBUS_GBL_L

NO_TEST=YES

MAXBUS_WT_L

MAKE_BASE=TRUE

TP_JTAG_VESTA_TMS

MAKE_BASE=TRUE

JTAG_VESTA_TRST_L

MAKE_BASE=TRUE

TP_JTAG_VESTA_TCK

=JTAG_VESTA_TMS

=JTAG_VESTA_TDO

MAKE_BASE=TRUE

TP_JTAG_VESTA_TDOTP_JTAG_VESTA_TDI

MAKE_BASE=TRUE

=JTAG_VESTA_TCK

=JTAG_VESTA_TRST_L

=JTAG_VESTA_TDI

=PPJTAG_CPU

MAKE_BASE=TRUE

TP_JTAG_CPU_TDO

=JTAG_CPU0_TDO

=JTAG_CPU0_TMS =JTAG_CPU0_TRST_L =JTAG_CPU0_TCK

=JTAG_CPU0_TDI

=JTAG_BBANGER_TDI

=JTAG_BBANGER_TMS

=JTAG_BBANGER_TRST_L

=JTAG_BBANGER_TCK

=PP3V3_PWRON_JTAG_ASIC

MAKE_BASE=TRUE

JTAG_ASIC_TCK

MAKE_BASE=TRUE

JTAG_ASIC_TMS

MAKE_BASE=TRUE

JTAG_ASIC_TRST_L

MAKE_BASE=TRUE

TP_JTAG_I2_TDO

=JTAG_I2_TDO

=JTAG_I2_TMS =JTAG_I2_TRST_L =JTAG_I2_TCK

=JTAG_I2_TDI

MAKE_BASE=TRUE

JTAG_I2_TDI

MAKE_BASE=TRUE

JTAG_CPU_TDI

MAKE_BASE=TRUE

JTAG_CPU_TRST_L

33

71

65

71

68

69

65

33

32

33

69

68

11

68

69

11

69

68

6

11

32

21

32

18

10

34

25

10

22

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

0

5%

1/8W

MF-LF

805

21

R1018

805

MF-LF

1/8W

5%

0

21

R1015

0

5%

1/8W

MF-LF

805

21

R1025

805

MF-LF

1/8W

5%

0

21

R1033

SM

21

XW1013

SM

21

XW1019

SM

21

XW1050

SM

21

XW1033

SM

21

XW1025

SM

21

XW1018

SM

21

XW1015

SM

21

XW1012

SM

21

XW1017

Power Synonyms

10

115

C

051-6929

SYNC_DATE=N/A

SYNC_MASTER=N/A

=PPVCORE_PWRON_I2_REG

VOLTAGE=1.5V MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

MAKE_BASE=TRUE

PPVCORE_PWRON_I2

=PPVCORE_GPU_REG

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=1.3V

MAKE_BASE=TRUE

PPVCORE_RUN_GPU

PP1V5_PWRON_REG

MAKE_BASE=TRUE VOLTAGE=1.5V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

PP1V8_PWRON_REG

MAKE_BASE=TRUE VOLTAGE=1.8V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

PP2V5_PWRON_REG

MAKE_BASE=TRUE VOLTAGE=2.5V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

=PP1V5_PWRON_RUNFET =PP1V5_I2_AGP

=PP1V5R1V8_PWRON_I2_MAXBUS

=PP1V8_PWRON_I2_RAM

=PP1V8_PWRON_DDR2

=PP1V8_PWRON_RUNFET

=PPVIN_PWRON_I2PLLVDD

=PP2V5_ENET

=PP2V5_PWRON_RUNFET

=PP1V5_PWRON_REG

PP1V5_PWRON

MAKE_BASE=TRUE VOLTAGE=1.5V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

=PP1V8_PWRON_REG

=PP2V5_PWRON_REG

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=1.8V

MAKE_BASE=TRUE

PP1V8_PWRON

PP2V5_PWRON

MAKE_BASE=TRUE VOLTAGE=2.5V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

=PP3V3_PWRON_REG

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=3.3V

MAKE_BASE=TRUE

PP3V3_PWRON

=PP5V_PWRON_REG

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=5V

MAKE_BASE=TRUE

PP5V_PWRON

MAKE_BASE=TRUE

PP3V3_VESTA

MIN_NECK_WIDTH=0.25 mm

VOLTAGE=3.3V MIN_LINE_WIDTH=0.5 mm

=PP3V3_ALL_BATT_CHGR

=PP3V3_ALL_BATT0_DET

=PP1V8_GPU_PWRSEQ

=PP24V_PBUSA_HOLDUP_CAPS

=PPBUS_FWPWRSW

=PPI2C_SYS0

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=3.3V

PP3V3_ALL

MAKE_BASE=TRUE

=PP3V3_ALL_DEBUG

=PP2V5R3V3_PWRON_I2_ENET

=PP3V3_PWRON_RT_ALS

=PP3V3_PWRON_I2_MISC

=PP3V3_PWRON_JTAG_ASIC

=PP5V_PWRON_LEFT_USB

PP3V3_RUN

MAKE_BASE=TRUE VOLTAGE=3.3V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

=PPVIN_CPU0_AVDD

=TPS2211_SHDN_L =PP3V3_RUN_AUDIO =PPVIO_PCI_USB2 =PP3V3_PCI_USB2 =PP3V3_PCI_ZDB =PPI2C_I2_SB

=PP1V5_RUN_RUNFET

=PP2V5_RUN_RUNFET

=PP1V8_GPU

=PP3V3_ENETFW

MIN_LINE_WIDTH=0.25 mm

VOLTAGE=5V

PP5V_TPAD

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.15 mm

=FTP_GND

PP5V_RUN

MAKE_BASE=TRUE VOLTAGE=5V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

=PPVCORE_CPU_ADT7467

PPVCORE_CPU_ADT7467

MAKE_BASE=TRUE MIN_LINE_WIDTH=0.25 mm

VOLTAGE=1.3V MIN_NECK_WIDTH=0.15 mm

=PPFW_P3V3VESTA

PPFW_CABLE_POWER

MAKE_BASE=TRUE VOLTAGE=33V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

MAKE_BASE=TRUE VOLTAGE=24V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

PP24V_ALL_PBUSA

=PPBUS_DVI_PWRSW

MAKE_BASE=TRUE MIN_LINE_WIDTH=0.25 mm

MIN_NECK_WIDTH=0.15 mm

VOLTAGE=12.8V

PPBUS_DVI_PWRSW

=PP5V_PWRON_PWRSEQ

=PP1V5R1V8_RUN_I2_MAXBUS

=PP1V5R1V8_MAXBUS

=PP1V5_GPU

=PPVBATT_BATT_VSNS

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

VOLTAGE=12.8V

MAKE_BASE=TRUE

PPVBATT_BATT_CHRG_VSNS

=PPVIN_BATT_CHRG_VSNS

=PP24V_ADAPTER_CONN

=PPVBATT_ISNS_N

=PP24V_ADAPTER_PMU_SUPPLY

=PP24V_ADAPTER_RAW

=PPVBATT_BATTERY_PMU_SUPPLY

=PPVBATT_BATT

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=12.8V

MAKE_BASE=TRUE

PPVBATT_BATT

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=24V

MAKE_BASE=TRUE

PP24V_ADAPTER

=PPI2C_GPU

=PP3V3_GPU

=PP3V3_PCI

=PP3V3_DDC_LCD

=PP3V3_DDC_DVI

=PP3V3_ALL_PWRSEQ

=PPVCORE_PWRON_I2

=PP1V05R1V3_GPU_VCORE

=PPFW_PORT2

=PPVCORE_CPU_REG

=PPVCORE_CPU0

=PP3V3_PWRON_CPUVCORE_OFFSET

=PP3V3_PWRON_CPUVCORE_VID

=PP3V3_PWRON_MODEM

=PP3V3_ALL_PMU

=PP5V_RUN_HDDFET

PP5V_RUN_HDD

MAKE_BASE=TRUE VOLTAGE=5V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

=PP5V_RUN_HDD

=PP5V_FAN1_PWR

=PPVIN_GPU_LVDDR_LDO

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=3.3V

MAKE_BASE=TRUE

PP3V3_GPU

=PP3V3_GPU_PWRSEQ

=PP2V5_GPU

=PP2V5_GPU_PVDD

=PP2V5_GPU_A2VDD

=PP2V5_GPU_PWRSEQ

=PP2V5_GPU_LVDS_IO

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=2.5V

MAKE_BASE=TRUE

PP2V5_GPU

=PP3V3_RUN_SI

=PP3V3_GPU =PP3V3_AGP

=PP3V3_GPU_VDDR3

=PP1V5_GPU_VDD15

=PP1V5_AGP=PP1V5_GPU

=PP4V85_ALL_VREG

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

VOLTAGE=4.85V

MAKE_BASE=TRUE

PP4V85_ALL

=PP4V85_ALL_A29_DET

=PPVIN_ALL_LTC1625

=PPVIN_ALL_LTC3707

=PPVIN_ALL_MAX1715

=PP12V8_PBUSB_HOLDUP_CAPS

=PPVIN_LTC1778_GPU

=PPVIN_CPUVCORE_MAX1717 =PPBUS_INVERTER

=PPVBATT_BATT_PBUSA

=PP14VR24V_ALL_PBUS_A

=PPVOUT_BU_BATT

=PPVBATT_BATT_PBUSB

=PP12V8_LTC1625_VREG

=PPVIO_BU_BATT

=PP3V3_VESTA

=PP3V3_VESTA_2V5REG

=PP3V3_VESTA_REG

PP2V5_VESTA

MAKE_BASE=TRUE MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.25 mm

VOLTAGE=2.5V

MAKE_BASE=TRUE

PP1V2_VESTA

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

VOLTAGE=1.2V

=PP2V5_VESTA =PP2V5_ENETFW

=PP1V2_VESTA

=PPFW_PHY_CPS =PPFW_PORT1

=PP2V5_VESTA_LDO

=PP1V2_VESTA_REG

=PPBUS_FW_FET

=PP3V3_ALL_VREG

=PP3V3_ALL_PBUS_ILIM

=PP3V3_ALL_LTC1625_SW

=PP3V3_ALL_A29_DET

=PP3V3_ALL_AC_DETECT

=PP5V_PWRON_PMU_SUPPLY

=PP5V_PWRON_LTC1625_EXTVCC

=PP5V_PWRON_RUNFET

=PP5V_PWRON_LTC3707_EXTVCC

=PP5V_RUN_ODD

=PP5V_RUN_FANPWM

=PPBU_RUN_FW

=PP5V_RUN_KEYBRD_LED =PP5V_RUN_DVI_DDC

=PP5V_RUN_RUNFET

=PP3V3_RUN_RUNFET

=PP2V5_RUN_PCI1510 =PP2V5_GPU

=PP3V3_BATT_IMON

PP3V3_ALL_PMU_AVCC

MAKE_BASE=TRUE

=PP3V3_RUN_KEYBRD_LED

=PP3V3_GPU_GPIOS

=PP5V_TPAD

=PP5V_TPAD_FET

MIN_LINE_WIDTH=0.5 mm

MAKE_BASE=TRUE

PP2V5_RUN

MIN_NECK_WIDTH=0.25 mm

VOLTAGE=2.5V

=PP1V8_RUN_RUNFET

=PP1V8_GPU_PANEL_IO

=PP1V8_GPU

=PP2V8_GPU_LVDS_IO

MAKE_BASE=TRUE

PP2V8_GPU_LVDDR

MIN_NECK_WIDTH=0.25 mm

VOLTAGE=2.8V MIN_LINE_WIDTH=0.38 mm

=PP2V8_GPU_LVDDR_LDO

=PP5V_FAN2_PWR

=PP1V8_GPU_DVO

=PP3V3_PCI_AIRPORT =PP3V3_RUN_PCI1510_R =PP3V3_RUN_HDD =PP3V3_GPU_CLOCKS =PP3V3_RUN_FWPORTPWRSW =PP3V3_RUN_FANTACH

=PPVOUT_CPU0_AVDD

PPAVDD_CPU0

MAKE_BASE=TRUE VOLTAGE=1.22V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

=PPAVDD_CPU0

=PP1V5_PWRON_I2PLL_LDO

=PP5V_RUN_PWRSEQ

=PP1V5_PWRON_I2_USBPLL

PP1V5_PWRON_I2PLL

VOLTAGE=1.5V MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

MAKE_BASE=TRUE

=PP1V5_PWRON_I2_PLL

=PP3V3_RUN_PWRSEQ

=PPJTAG_CPU

=PP5V_PWRON_AUDIO_AVDD =PP5V_PWRON_AUDIO_PVDD =PP5V_PWRON_RIGHT_USB =PP5V_PWRON_SLEEPLED =PP5V_PWRON_TRACKPAD =PP5V_PWRON_INVERTER

=PP1V5_GPU_PWRSEQ

MIN_LINE_WIDTH=0.38 mm

VOLTAGE=1.5V

PP1V5_GPU

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 mm

=PP1V5_GPU_DVO

=PP1V8R2V5_GPU_FB_VIO =PP1V8_FB_VDD =PP1V8_FB_VDDQ

=PP1V8_GPU_TPVDD

=PP1V8_GPU_AVDD

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

VOLTAGE=1.3V

MAKE_BASE=TRUE

PPVCORE_RUN_CPU

=PP1V8_GPU_MEMVMODE

PP1V8_GPU

MAKE_BASE=TRUE VOLTAGE=1.8V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

=PP1V8_RAM_I2_VREF =PP1V8_RUN_TBEN_SYNC

PP1V8_RUN

MAKE_BASE=TRUE MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.25 mm

VOLTAGE=1.8V

PP12V8_ALL_PBUSB

MAKE_BASE=TRUE MIN_LINE_WIDTH=0.5 mm

VOLTAGE=12.8V MIN_NECK_WIDTH=0.25 mm

=PP3V3_PWRON_VGASYNC

=PP3V3_PWRON_DS1775

=PP3V3_PWRON_AUDIO_AVDD

=PP3V3_PWRON_BT

=PP3V3_PCI_ROM

=PP3V3_PWRON_VDDSPD

=PP3V3_I2_PCISLOTEGPIOS =PP3V3_PWRON_I2_AGPPCI

=PPVIN_ALL_BATT_CHGR

=PP5V_PWRON_CPUVCORE_VDD

=PP5V_PWRON_CPUVCORE_PWRSEQ

=PP5V_PWRON_GPUVCORE_PWRPLAY

=PP5V_PWRON_LTC1778_GPU_EXTVCC

=PP5V_PWRON_TPS2211

=PP5V_PWRON_MAX1715_VDD

=PP1V2_ENETFW

=PP3V3_FW

=PP3V3_VESTA_1V2REG

PP1V5_RUN

MAKE_BASE=TRUE MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.25 mm

VOLTAGE=1.5V

=PP3V3_PWRON_LEFT_ALS

=PP3V3_PWRON_PMU

=PP3V3_ADT7467

=PP3V3_PWRON_TPS2211

=PP3V3_PWRON_LTC3412

=PP3V3_PWRON_RUNFET

=PP3V3_PWRON_MMM

=PP12V8_PBUS_PMU_SUPPLY

=PP3V3_PWRON_USB2

=PP3V3_PWRON_I2_MAXBUS

=PP2V7R5V5_PWRON_I2VCORE

=PP3V3_PWRON_LCD =PP3V3_PWRON_INVERTER

=PP3V3_PWRON_I2_IO1 =PP3V3_PWRON_I2_IO2 =PP3V3_PWRON_PWRSEQ =PP3V3_ENET

=PPI2C_SYS1

=PP3V3_AUDIO_MUTESEQ

=PP3V3_ALL_HALL_EFFECT

=PPI2C_I2_NB

=PPVREF_PMU

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

MAKE_BASE=TRUE VOLTAGE=5V

PP5V_PWRON_REG

PP3V3_PWRON_REG

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=3.3V

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=1.3V

MAKE_BASE=TRUE

PPVCORE_GPU_REG

VOLTAGE=1.5V

MAKE_BASE=TRUE

PPVCORE_PWRON_I2_REG

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

GND

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=0V

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

34

67

33

47

66

41

7

74

7

32

7

56

25

64

31

55

44

31

65

69

64

53

31

48

50

41

69

70

31

20

45

7

16

43

32

38

40

16

20

67

17

16

17

7

15

7

15

7

13

12

52

31

18

8

24

65

28

22

9

7

37

61

7

62

23

8

16

17

10

69

7

27

18

57

26

32

21

10

12 13

31

12

14

12

14

13

8

10

59

7

57

26

19

46

70

36 35

36

30

24

15

7

52

10

51

53

52

47

54

10 43

47

46

43 10

14 12

14

15

16

31

45

36

56

13

7

13

14

7

18

66

18

69

70

18

14

13

14

12

14

15

7

27

18

28

57

15

61

10

12

25

28

51

30 15

16

47 10

47 52

7

47

60

61

64

52

18

27

37 35

20

26

72

19

26

9

74

7

24

15

56

52

47

49

53

48

38

21

7

57

30

74

60

58

40

22

19

13

36

45

61

16

66

69

18

7

25

27

61

17

15

29

14

73

19

20

56

19

26

66

8

22

30

8

25

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

USB Controller Mux

USB Port Assignments

CPU Clocks

PCI

- I2S0_SYNC(_R)

- I2S0_BITCLK(_R)

I2S0 Series Rs

- I2S0_SB_TO_DEV_DTO(_R)

GPU

- I2S1_MCLK(_R)

- I2S1_BITCLK(_R)

- I2S1_SYNC(_R)

One resistor for each of:

- I2S1_SB_TO_DEV_DTO(_R)

I2S1 Series Rs

MISC

PMU Connections

Vesta Ethernet

- I2S0_MCLK(_R)

One resistor for each of:

I105

I106

I107

I108

MAXBUS_TBEN_SYNC

1/16W

5%

22

MF-LF

402

21

R1130

MAXBUS_TBEN_SYNC

5%

402

MF-LF

1/16W

10

21

R1111

402

MF-LF

1/16W

5%

22

21

R1120

22

1/16W

5%

MF-LF

402

21

R1137

402

USB2_I2

MF-LF

1/16W

5%

0

21

R1165

402

MF-LF

1/16W

5%

0

USB2_NEC

21

R1164

402

USB2_NEC

0

5% 1/16W MF-LF

21

R1166

402

0

5% 1/16W MF-LF

USB2_I2

21

R1167

402

USB1P1_NEC

0

5% 1/16W MF-LF

21

R1174

402

USB2_I2

0

5% 1/16W MF-LF

21

R1161

402

USB2_NEC

0

5% 1/16W MF-LF

21

R1160

402

MF-LF

1/16W

5%

0

USB2_NEC

21

R1162

402

USB2_I2

MF-LF

1/16W

5%

0

21

R1163

402

USB1P1_NEC

0

5% 1/16W MF-LF

21

R1170

402

0

5% 1/16W MF-LF

USB1P1_I2

21

R1175

402

MF-LF

1/16W

5%

0

USB1P1_NEC

21

R1176

402

USB1P1_I2

MF-LF

1/16W

5%

0

21

R1177

402

0

5% 1/16W MF-LF

USB1P1_I2

21

R1171

402

MF-LF

1/16W

5%

0

USB1P1_NEC

21

R1172

USB1P1_I2

402

MF-LF

1/16W

5%

0

21

R1173

22

MF-LF

1/16W

5%

402

21

R1135

22

5% 1/16W MF-LF

402

21

R1136

1/16W

5%

402

MF-LF

10

21

R1110

22

402

5% 1/16W MF-LF

21

R1140

100K

5% 1/16W MF-LF

402

2

1

R1185

SM-LF

1/16W

5%

33

5

6

7

8

4

3

2

1

RP1150

33

5%

1/16W SM-LF

5

6

7

8

4

3

2

1

RP1151

11

115

C

051-6929

SYNC_MASTER=N/A

SYNC_DATE=N/A

Signal Synonyms

USB_NEC_TPAD_P

MAXBUS_CLK_CPU0_R

=RP1150P5

=RP1150P6

=RP1150P7

TP_MAXBUS_CPU1_QACK_L

=ROM_PWD_L

=CPU0_VID_AB_SEL

MAKE_BASE=TRUE

PMU_CPU_CLK_EN

=I2_STOPCPU_L

=I2_STOPXTAL_L

MAKE_BASE=TRUE

SYS_PWRSEQ_FINAL

USB_I2_BT_N

PCI_SLOTD_GNT_L

PCI_SLOTD_INT_L

=ENET_TX_EN

=ENET_TX_ER

=ENET_TXD<7..0>

=ENET_RXD_R<7..0>

ENET_RXD<7..0>

MAKE_BASE=TRUE

=ENET_RX_DV_R

ENET_RX_DV

MAKE_BASE=TRUE

=ENET_RX_ER_R

MAKE_BASE=TRUE

ENET_RX_ER

=ENET_COL_R

MAKE_BASE=TRUE

ENET_COL

=ENET_CRS_R

MAKE_BASE=TRUE

ENET_CRS

=VESTA_CLK125M_GBE_REF

MAKE_BASE=TRUE

ENET_CLK125M_GBE_REF

=VESTA_CLK125M_RX

ENET_CLK125M_RX

MAKE_BASE=TRUE

=VESTA_CLK25M_TX

ENET_CLK25M_TX

MAKE_BASE=TRUE

=VESTA_MDC

MAKE_BASE=TRUE

ENET_MDC

=VESTA_MDIO

ENET_MDIO

MAKE_BASE=TRUE

ENET_TX_EN

ENET_TX_EN_R

MAKE_BASE=TRUE

ENET_TX_ER

ENET_TX_ER_R

MAKE_BASE=TRUE

ENET_TXD<7..0>

ENET_TXD_R<7..0>

=VESTA_ENERGYDET

MAKE_BASE=TRUE

TP_ENET_ENERGYDET

USB2_NEC_P<0>

MAKE_BASE=TRUE

USB2_NEC_LEFT_PORT_P

USB2_NEC_N<0>

MAKE_BASE=TRUE

USB2_NEC_LEFT_PORT_N

USB2_NEC_N<1>

MAKE_BASE=TRUE

USB2_NEC_RIGHT_PORT_N

USB2_NEC_P<1>

MAKE_BASE=TRUE

USB2_NEC_RIGHT_PORT_P

USB2_NEC_P<2>

MAKE_BASE=TRUE

USB_NEC_BT_P

USB2_NEC_N<2>

MAKE_BASE=TRUE

USB_NEC_BT_N

USB2_NEC_P<3>

MAKE_BASE=TRUE

USB_NEC_TPAD_P

USB2_NEC_N<3>

MAKE_BASE=TRUE

USB_NEC_TPAD_N

USB2_I2_P<0>

MAKE_BASE=TRUE

USB2_I2_LEFT_PORT_P

USB2_I2_N<0>

MAKE_BASE=TRUE

USB2_I2_LEFT_PORT_N

USB2_I2_N<2>

MAKE_BASE=TRUE

USB2_I2_RIGHT_PORT_N

USB2_I2_P<2>

MAKE_BASE=TRUE

USB2_I2_RIGHT_PORT_P

USB2_I2_P<4>

MAKE_BASE=TRUE

USB_I2_BT_P

USB2_I2_N<5>

MAKE_BASE=TRUE

USB_I2_TPAD_N

USB2_I2_N<4>

MAKE_BASE=TRUE

USB_I2_BT_N

USB2_I2_P<5>

MAKE_BASE=TRUE

USB_I2_TPAD_P

TP_PMU_P7_5

MAKE_BASE=TRUE

PMU_CHARGE_V

=ADT7467_THERM_L

MAKE_BASE=TRUE

SYS_OVERTEMP_L

=CPU_HRESET_L

MAKE_BASE=TRUE

PMU_CPU_HRESET_L

TP_GOV_RESET_L

MAKE_BASE=TRUE

GOV_RESET_L

TP_PMU_AN_P10_6

MAKE_BASE=TRUE

SYS_PMU_ANALOG_AC_DET

MAKE_BASE=TRUE

PMU_SYS_CLK_EN

=CPU0_MAX1717_AB_SEL

=SLEEP_LED_CONN

NC_MAXBUS_CPU1_QACK_L

MAKE_BASE=TRUE NO_TEST=YES

MAKE_BASE=TRUE

PCI_RESET_L

CPU0_VID_AB_SEL

MAKE_BASE=TRUE

I2_GPIO_EXT_02

SLEEP_LED_IOUT

MAKE_BASE=TRUE MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm

=SLEEP_LED_IOUT

CPU0_MAX1717_AB_SEL

MAKE_BASE=TRUE

=SPI_I2_REQ

ENET_RESET_L

=RP1151P1 =RP1151P2 =RP1151P3 =RP1151P4

=RP1151P8 =RP1151P7 =RP1151P6 =RP1151P5

MIN_NECK_WIDTH=0.15 mm

MIN_LINE_WIDTH=0.25 mm

VOLTAGE=0.75V

MAKE_BASE=TRUE

AGP_VREF

AGP_CLK66M_GPU

AGP_CLK66M_GPU_R

=AGP_GPU_RESET_L

MAKE_BASE=TRUE

PCI_RESET_L

=SI_TMDS_RESET_L

=GPU_AGP_VREF

=AGP_VREF

=I2_AGP_VREF

SI_TMDS_RESET_L

MAKE_BASE=TRUE

TP_EXTTMDS_RESET_L

=RP1150P1 =RP1150P2 =RP1150P3 =RP1150P4

=RP1150P8

=PCI_CLK33M_ZDB_IN

=CLK33M_TBEN_SYNC

=PCI_CLK33M_AIRPORT

=PCI_AIRPORT_REQ_L

=PCI_AIRPORT_GNT_L

=PCI_AIRPORT_INT_L

PCI_CLK33M_ZDB

MAKE_BASE=TRUE

PCI_CLK33M_TBEN_SYNC

MAKE_BASE=TRUE

PCI_CLK33M_AIRPORT

MAKE_BASE=TRUE

PCI_AIRPORT_INT_L

MAKE_BASE=TRUE

PCI_AIRPORT_GNT_L

MAKE_BASE=TRUE

PCI_SLOTA_GNT_L

MAKE_BASE=TRUE

PCI_AIRPORT_REQ_L

PCI_SLOTA_REQ_L

PCI_CLK33M_ZDB_R

MAKE_BASE=TRUE

TP_PCI_CLK33M_SLOTA_R

PCI_CLK33M_TBEN_SYNC_R

MAKE_BASE=TRUE

TP_PCI_CLK33M_SLOTD_R

PCI_CLK33M_AIRPORT_R

MAKE_BASE=TRUE

=PCI_CLK33M_ZDBOUT_R<0>

=PCI_AIRPORT_IDSEL

MAKE_BASE=TRUE

PCI_AD<17>

=PCI_AIRPORT_RESET_L

MAKE_BASE=TRUE

PCI_RESET_L

=PCI_CLK33M_CBUS

=PCI_CBUS_REQ_L

=PCI_CBUS_GNT_L

=PCI_CBUS_INT_L

=PCI_CBUS_IDSEL

MAKE_BASE=TRUE

PCI_AD<20>

=PCI_CBUS_RESET_L

MAKE_BASE=TRUE

PCI_RESET_L

=PCI_CLK33M_USB2

MAKE_BASE=TRUE

PCI_CBUS_REQ_L

PCI_SLOTD_REQ_L

PCI_CLK33M_CBUS

MAKE_BASE=TRUE

PCI_CBUS_GNT_L

MAKE_BASE=TRUE

PCI_CBUS_INT_L

MAKE_BASE=TRUE

PCI_CLK33M_USB2

=PCI_USB2_REQ_L

=PCI_USB2_GNT_L

=PCI_USB2_INT_L

=PCI_USB2_IDSEL

MAKE_BASE=TRUE

PCI_AD<21>

=PCI_USB2_RESET_L

MAKE_BASE=TRUE

PCI_RESET_L

PCI_USB2_GNT_L

MAKE_BASE=TRUE

PCI_SLOTE_GNT_L

PCI_USB2_REQ_L

MAKE_BASE=TRUE

PCI_SLOTE_REQ_L

PCI_USB2_INT_L

MAKE_BASE=TRUE

PCI_SLOTE_INT_L

MAKE_BASE=TRUE

PCI_CLK33M_CBUS_R

=PCI_CLK33M_ZDBOUT_R<1>

PCI_CLK33M_USB2_R

MAKE_BASE=TRUE

=PCI_CLK33M_ZDBOUT_R<2>

MAKE_BASE=TRUE

TP_PCI_CLK33M_ZDBOUT3

=PCI_CLK33M_ZDBOUT_R<3>

=MAXBUS_CPU0_CLK

=SYSCLK_TBEN_SYNC

MAXBUS_CLK_CPU0

MAKE_BASE=TRUE

MAXBUS_CLK_TBEN_SYNC

MAKE_BASE=TRUE

MAXBUS_CLK_CPU1_R

TP_MAXBUS_CLK_CPU1_R

DIFFERENTIAL_PAIR=USB_BT

NET_PHYSICAL_TYPE=USB2

NET_SPACING_TYPE=USB2

USB_BT_P

DIFFERENTIAL_PAIR=USB_BT

NET_PHYSICAL_TYPE=USB2

NET_SPACING_TYPE=USB2

USB_BT_N

DIFFERENTIAL_PAIR=USB_TPAD

NET_PHYSICAL_TYPE=USB2

NET_SPACING_TYPE=USB2

USB_TPAD_P

DIFFERENTIAL_PAIR=USB_TPAD

NET_PHYSICAL_TYPE=USB2

NET_SPACING_TYPE=USB2

USB_TPAD_N

NET_SPACING_TYPE=USB2 NET_PHYSICAL_TYPE=USB2 DIFFERENTIAL_PAIR=USB2_LT_PORT

USB2_LEFT_PORT_N

NET_SPACING_TYPE=USB2 NET_PHYSICAL_TYPE=USB2 DIFFERENTIAL_PAIR=USB2_RT_PORT

USB2_RIGHT_PORT_P

NET_SPACING_TYPE=USB2 NET_PHYSICAL_TYPE=USB2 DIFFERENTIAL_PAIR=USB2_RT_PORT

USB2_RIGHT_PORT_N

USB_NEC_BT_P

USB_I2_BT_P

USB_NEC_BT_N

USB_I2_TPAD_P

USB_I2_TPAD_N

USB_NEC_TPAD_N

USB2_NEC_LEFT_PORT_P

USB2_I2_LEFT_PORT_P

USB2_I2_LEFT_PORT_N

USB2_NEC_LEFT_PORT_N

USB2_I2_RIGHT_PORT_P

USB2_NEC_RIGHT_PORT_P

USB2_I2_RIGHT_PORT_N

USB2_NEC_RIGHT_PORT_N

PCI_SLOTA_INT_L

NET_SPACING_TYPE=USB2 NET_PHYSICAL_TYPE=USB2 DIFFERENTIAL_PAIR=USB2_LT_PORT

USB2_LEFT_PORT_P

TP_PMU_AN_P0_2

TP_PMU_AN_P0_3

MAKE_BASE=TRUE

SYS_PWRSEQ_3_L

TP_PMU_AN_P0_4

TP_PMU_AN_P0_5

TP_PMU_P7_4

MAKE_BASE=TRUE

SYS_PWRSEQ_6_L

TP_PMU_AN_P10_5

TP_PMU_AN_P0_1

TP_PMU_AN_P0_0

MAKE_BASE=TRUE

SYS_PWRSEQ_5

MAKE_BASE=TRUE

SYS_PWRSEQ_TPAD_L

MAKE_BASE=TRUE

SYS_PWRSEQ_1

MAKE_BASE=TRUE

SYS_PWRSEQ_2

MAKE_BASE=TRUE

SYS_PWRSEQ_4

TP_PMU_P3_3

MAKE_BASE=TRUE

TP_PMU_P3_2

MAKE_BASE=TRUE

TP_PMU_P3_1

MAKE_BASE=TRUE

TP_PMU_P3_0

MAKE_BASE=TRUE

62

61

62

11

30

60

61

11

59

65

9

11

6

11

25

55

6

59

25

59

25

6

60

25

30

74

31

11

6

11

59

74

6

32

6

32

58

36

25 22

22

26

6

59

22

66

9

66

9

66

9

66

9

66

9

66

65

66 65

66

9

66

9

65

66

73

6

73

6

73

6

73

6

73

6

73

2

73

6

73

6

72

6

72

6

72

6

72

6

72

6

72

6

72

6

72

6

25 13

27

7

34 25

25

25 12

25

36

30

11

22

24

22

65

6

44 43

44 11

54

44

43

51

6

23

21

60

59

23

60 58

60 11

61

61 58

61 11

62

59

62

62 59

62 11

22

23

33

21 32

60

7

6

2

6

22

7

25

25 26

25

25 26

25

26

25

G

D

S

G

D

S

V-

V+

GND

OUT

VIN+ VIN-

V+

G

D

S

V-

V+

G

D

S

G

D

S

GATE

D4 D3

D2

D1

S2

S3

S1

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

SPACING

PHYSICAL

DIFFERENTIAL_PAIR

to facilitate design reuse)

(Connector is on separate page

Adapter Connector Side

ADAPTER INPUT/INRUSH LIMITER

GREATER THAN 13.1V DETECT

signal to enable use of AC in system. Q1208 ensures SYS_ACIN goes low as soon as SYS_AC_DET goes low. Therefore, hardware immediately disables the AC upon removal but only software can enable AC after detection by the PMU.

System Side

AIRLINE

Q11 (65W) A29 (45W)

ADAPTER

ADAPTER IDs ID RANGE

0.33-0.99V

2.31-2.97V

1.65-2.31V

A29 ADAPTER DETECTION

0.589-0.663V

PIN VOLTAGE

2.007-2.066V

2.558-2.661V

BATTERY INPUT/CURRENT SENSE

(BATT_IN_PD)

SYS_AC_DET indicates adapter presence. SYS_ACIN is code-controlled

402

MF-LF

1/16W

5%

470K

1

2

R1209

805

CERM

50V

20%

0.1uF

1

2

C1210

330K

5% 1/16W MF-LF

402

1

2

R1210

402

CERM

16V

20%

0.01uF

2

1

C1200

1M

402

MF-LF

1/16W

5%

21

R1206

1% 1/16W

402

20.0K

MF-LF

1

2

R1201

100K

1% 1/16W MF-LF

402

2

1

R1204

97.6K

1% 1/16W MF-LF

402

1

2

R1202

57.6K

1% 1/16W MF-LF

402

1

2

R1205

402

MF-LF

1/16W

1%

10K

1

2

R1203

10K

5% 1/16W MF-LF 402

2

1

R1208

470K

5% 1/16W MF-LF

402

1

2

R1207

SOT-363

2N7002DW-X-F

4

5

3

Q1215

SOT-363

2N7002DW-X-F

1

2

6

Q1208

LMC7211

SM-LF

2

5

1

3

4

U1200

10UF

20% 4V X5R 603

2

1

C1252

1% 1/16W MF-LF

402

49.9K

21

R1252

SM

21

XW1252

1% 1W

MF-LF

2512

0.006

21

R1250

SM

21

XW1251

402

MF-LF

1/16W

1%

249K

2

1

R1251

INA138

CRITICAL

SOT23-5-LF

43

5 1

2

U1250

CERM

10V

20%

0.1UF

402

2

1

C1250

402

MF-LF

1/16W

5%

100K

2

1

R1228

0.1uF

20% 10V CERM 402

2

1

C1220

SOT23-LF

2N7002

2

1

3

Q1220

MF-LF

402

1/16W

5%

4.7M

21

R1227

LMC7211

SM-LF

2

5

1

3

4

U1220

52.3K

1% 1/16W MF-LF 402

2

1

R1225

100K

1% 1/16W MF-LF 402

1

2

R1221

402

MF-LF

1/16W

1%

127K

2

1

R1226

402

MF-LF

1/16W

1%

100K

2

1

R1222

1%

402K

402

MF-LF

1/16W

2

1

R1223

402

MF-LF

1/16W

5%

10K

21

R1224

FERR-50-OHM

SM-LF

21

L1250

FERR-EMI-100-OHM

SM

21

L1253

FERR-EMI-100-OHM

SM

21

L1254

SM

FERR-EMI-100-OHM

1

2

L1252

SM-LF

FERR-50-OHM

21

L1251

M-RT-SM

87438-0832

CRITICAL

8

7

6

5

4

3

2

1

J1250

SOT-363

2N7002DW-X-F

4

5

3

Q1208

10K

5% 1/16W MF-LF 402

2

1

R1215

SOT-363

2N7002DW-X-F

1

2

6

Q1215

402

MF-LF

1/16W

5%

10K

2

1

R1216

I317

I318

1K

5% 1/16W MF-LF

402

21

R1255

402

MF-LF

1/16W

5%

470K

2

1

R1256

SOI

IRF7416BF

3 2 1

4

8 7 6 5

Q1210

Power Inputs

C

051-6929

115

12

SYNC_MASTER=N/A

SYNC_DATE=N/A

=I2C_BATT_SDA

=I2C_BATT_SCL

MAKE_BASE=TRUE

BATT_ISNS

VOLTAGE=12.8V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

PPVBATT_BATT_RAW

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

VOLTAGE=12.8V

PPVBATT_ISNS_VINP

VOLTAGE=12.8V

PPVBATT_ISNS_VINN

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm

=PPVBATT_ISNS_N

=PP4V85_ALL_A29_DET

A29_DETECT

=PP3V3_ALL_A29_DET

A29_DET_L

A29_DET_REF

SYS_ADAPTER_ANALOG_AC_DET

ANALOG_AC_DET

SYS_PMU_ANALOG_AC_DET

BATT_ISNS_R

AC_ENABLE_L

SYS_ACIN_L

SYS_ACIN

SYS_AC_DET_L

=PP3V3_ALL_AC_DETECT

SYS_AC_DET

1V20_REF

AC_DET_DIV

BATTERY_ISNS

PPVBATT_ISNS_VINN

THERMTHERM

BATTERY_ISNS

PPVBATT_ISNS_VINP

THERMTHERM

SYS_BATT0_DET_L

=PPVBATT_BATT_VSNS

=PP3V3_BATT_IMON

PPVBATT_BATTPOS_CONN

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

VOLTAGE=10.8V

VOLTAGE=0V

GND_BATT_CONN

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

BATT_DATA

BATT_CLK

BATT0_DET_L

=PP3V3_ALL_BATT0_DET

PP24V_ADAPTER_SW

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=24V

AC_ENABLE_GATE

=PP24V_ADAPTER_RAW

25

74

18

25

8

25

12 12

10

13

10

7

11

13

24

10

25

14

12

24

10

13

10

CSIP CSIN

BATT

PGND

DLO

LX

DHI

BST

DLOV

LDO

CELLS

GND

CSSNCSSP

REF

CCS

CCI

CCV

IINP

ICHG

ICTL

VCTL

RFIN

ACOK

ACIN

DCIN

CLS

G

D

S

G

D

S

G

D

S

G

D

S

G

D

S

G

D

S

G

D

S

G

D

S

G

D

S

G

D

S

G

D

S

D

G

D

S

GND

OUT

PG

RS-

V+

RS+

NC2

NC1

GATE

D4 D3

D2

D1

S2

S3

S1

GATE

D4 D3

D2

D1

S2

S3

S1

V-

V+

TABLE_5_ITEM

REFERENCE DESIGNATOR(S)

BOM OPTION

TABLE_5_HEAD

QTY

DESCRIPTION

PART#

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

BATTERY SWITCH-OVER CIRCUIT

+PBUS CURRENT LIMIT

VCTL

REFIN

ICTL

_62

OD OUTPUT LOW - WHEN AC GREATER THAN 18V

(+3V_PMU)

PLACE U1370 NEXT TO R1300

PROTECTION

ROUTE LTC1625_ITH CAREFULLY

PLACE R383 CLOSE TO LTC1625

V = CELLS X (4.096 + (0.4096 * V / V ))

BATT For 4.15V cells, VCTL = 0.123 REFIN For 4.20V cells, VCTL = 0.245 REFIN

CHG

I = (0.2048/R ) * (V / V )

CHARGE THROTTLED BY LOW BATTERY VOLTAGE

PMU SELECTS BETWEEN TWO VOLTAGES

RC TIME IS 480K*10UF @ +3V_PMU

WHEN AC IS NOT PLUGGED, P-CHANNEL FETS ARE ON

WHEN AC IS IN, P-CHANNEL FETS ARE QUICKLY (DIODE) TURNED OFF

(GND)

NC

SWITCHER VOLTAGE CONTROL

CHARGE DISABLED BY PMU OR INPUT VOLTAGE <18V

SWITCHER CURRENT CONTROL

Place close to RS-

BACKFEED

IS

QSOP-LF

CRITICAL

MAX1772

15

13

4

20

23

2

28

14 10

98

22

21

24

1

27 26

19 18

3

16

7

5

6

25

17

12

11

U1300

1uF

20% 10V CERM 603

2

1

C1317

402

5%

47K

1/16W MF-LF

2

1

R1390

402

MF-LF

1/16W

5%

10K

2

1

R1391

SM-LF

5AMP-125V

2

1

F1390

SM-LF

5AMP-125V

2

1

F1395

1% 1/16W

1K

MF-LF 402

2

1

R1324

1% 1/16W MF-LF

402

1K

2

1

R1323

MF-LF

1206

1/4W

5%

33

21

R1319

MF-LF

1/16W

100K

402

5%

2

1

R1317

SOT-363

2N7002DW-X-F

4

5

3

Q1392

1/16W

158K

1% MF-LF

402

2

1

R1392

MMBD914XXG

SOT23

31

D1319

47K

5% 1/16W MF-LF

402

2

1

R1395

10K

5% 1/16W MF-LF

402

2

1

R1396

1

603

MF-LF

5%

1/10W

2

1

R1304

SOT-363

2N7002DW-X-F

1

2

6

Q1340

SOT-363

2N7002DW-X-F

4

5

3

Q1340

603

CERM

25V

20%

0.1uF

2

1

C1319

5% 1/16W MF-LF

402

100K

2

1

R1340

603

X5R

20%

6.3V

10uF

2

1

C1392

2N7002DW-X-F

SOT-363

1

2

6

Q1348

402

MF-LF

1/16W

1%

10K

2

1

R1346

2N7002DW-X-F

SOT-363

4

5

3

Q1348

2N7002DW-X-F

SOT-363

1

2

6

Q1347

402

5% 1/16W MF-LF

100K

2

1

R1347

SOT-363

2N7002DW-X-F

4

5

3

Q1347

20% 50V

CERM

805

0.1uF

2

1

C1320

SOT-363

BAS16TW-X-F

5 2

DP1390

SOT-363

BAS16TW-X-F

43

DP1390

4.7uF

20% 25V CERM 1206

2

1

C1305

100K

1/16W

5%

402

MF-LF

2

1

R1318

4.7uF

20%

25V CERM 1206

2

1

C1306

4.7uF

20%

25V CERM 1206

2

1

C1308

4.7uF

20% 25V CERM 1206

2

1

C1307

402

MF-LF

1/16W

1%

4.12K

2

1

R1329

MF-LF

10K

402

1/16W

1%

2

1

R1328

SO-8-LF

CRITICAL

IRF7811W

321

4

8765

Q1301

1/16W

402

MF-LF

5%

4.7

2

1

R1301

SOT23-5-LF

LMC7111

2

5

1

3

4

U1380

SOT-363

2N7002DW-X-F

1

2

6

Q1384

SOT-363

2N7002DW-X-F

4

5

3

Q1384

1/16W

5% MF-LF

402

4.7

2

1

R1302

SOT-363

BAS16TW-X-F

6 1

DP1390

1uF

20%

CERM

603

10V

2

1

C1384

CERM

50V

0.47UF

10%

1206

2

1

C1301

6.34K

1/16W

402

1%

MF-LF

2

1

R1330

MBRS140XXG

SMB

2

1

D1300

50V CERM 1206

0.47UF

10%

2

1

C1302

SOT-363

2N7002DW-X-F

1

2

6

Q1330

SOT-363

2N7002DW-X-F

4

5

3

Q1330

SUD45P03

CRITICAL

TO-252-LF

3

1

4

Q1395

0.0022UF

50V CERM 402

10%

NO STUFF

2

1

C1321

10%

2.2UF

50V X7R 1206

2

1

C1312

X7R 1206

10%

2.2UF

50V

2

1

C1313

X7R

1206

10%

50V

2.2UF

2

1

C1316

1206

2.2UF

10% 50V X7R

2

1

C1314

50V

10%

2.2UF

X7R 1206

2

1

C1315

1/16W MF-LF

47K

402

5%

2

1

R1360

68K

5%

402

MF-LF

1/16W

2

1

R1361

CERM

0.01UF

20% 50V

603

2

1

C1361

SOT-363

2N7002DW-X-F

1

2

6

Q1392

0.1UF

603-1

X7R

50V

10%

2

1

C1371

603

0.01uF

CERM

20% 50V

2

1

C1370

MF-LF

2.21k

0.1%

1/16W

603

CRITICAL

2

1

R1370

TSSOP-LF

MAX4172

CRITICAL

8

21

7

64

3

5

U1370

MF-LF

1/16W

0.1%

42.2K

CRITICAL

603

2

1

R1380

CERM

10V

20%

0.1uF

402

2

1

C1380

CRITICAL

51.1K

0.1% 1/16W MF-LF 603

2

1

R1383

MF-LF

1/16W

0.1%

42.2K

603

CRITICAL

2

1

R1381

MF-LF

CRITICAL

1/16W

0.1%

82.5K

603

2

1

R1382

1K

1% 1/16W MF-LF

402

2 1

R1386

150

1% 1/16W MF-LF

402

2 1

R1387

10K

1% 1/16W MF-LF

402

2 1

R1385

MF-LF

1/16W

5%

100K

402

2

1

R1384

1uF

20% 10V

603

CERM

2

1

C1327

402

MF-LF

1/16W

1%

100K

2

1

R1321

20% 10V

CERM

0.1uF

402

21

C1386

0.025

1% 1W MF

CRITICAL

2512-1

21

R1300

CRITICAL

33uF

20% 25V ELEC SM1-LF

2

1

C1311

SOI

IRF7416BF

3 2 1

4

8 7 6 5

Q1360

IRF7416BF

SOI

CRITICAL

3 2 1

4

8 7 6 5

Q1390

402

MF-LF

1%

1/16W

12.7K

2

1

R1322

1uF

20% CERM

1210

50V

2

1

C1303

CRITICAL

10uH

SM1-LF

21

L1300

0.05

1W

1%

MF-LF

2512

21

R1303

1

603

MF-LF

1/10W

5%

2

1

R1305

0.01uF

CERM

16V

20%

402

2

1

C1326

603

CERM

0.1uF

25V

20%

2

1

C1322

603

CERM

25V

20%

0.1uF

2

1

C1323

1% 1/16W MF-LF

402

27.4K

2

1

R1341

MF-LF

402

1/16W

1%

4.12K

2

1

R1342

10K

1% 1/16W MF-LF

402

2

1

R1344

402

MF-LF

1/16W

1%

OMIT

20.0K

2

1

R1345

1% 1/16W MF-LF 402

5.23K

2

1

R1343

402

0.01uF

CERM

16V

20%

2

1

C1325

402

1%

MF-LF

1/16W

1K

2

1

R1348

CRITICAL

RLA130N03

SO8

321

4

8765

Q1300

LMC7211

SM-LF

2

5

1

3

4

U1350

1/16W

1%

MF-LF

1K

402

2

1

R1325

100K

402

MF-LF

1/16W

1%

2

1

R1353

100K

402

MF-LF

1/16W

1%

2

1

R1354

1/16W MF-LF 402

1%

499K

2

1

R1351

402

MF-LF

1/16W

1%

100K

2

1

R1352

402

CERM

16V

10%

0.047uF

2

1

C1352

402

CERM

10V

20%

0.1uF

2

1

C1350

MMBD914XXG

SOT23

3

1

D1303

CERM 402

0.1uF

10V

20%

2

1

C1324

20% 25V CERM

4.7uF

1206

2

1

C1309

25V

CERM

20%

1206

4.7uF

2

1

C1310

SM

21

XW1300

5% 1/10W MF-LF 603

4.7

2

1

R1320

Primary is 260C/Alt is 250C part

126S0079126S0084

C1311

Battery Charger

13

115

051-6929

C

SYNC_MASTER=N/A

SYNC_DATE=N/A

RES,20K,1%,1/16W,MF-LF,402

114S0343

1

Q16C_PARTS

R1345

RES,48.7K,1%,1/16W,MF-LF,402

114S0382

1

Q41C_PARTS

R1345

1772_CSIN

1772_CSIP

PPVBATT_BATT_PBUSA_FUSE

MAKE_BASE=TRUE

PP24V_ADAPTER_SW

BKFD_PROT_GATE

=PP14VR24V_ALL_PBUS_A

=PPVBATT_BATT_PBUSA

BATT_24V_GATE

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=14V

PPVBATT_BATT_PBUSA_FUSE

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=24V

PP24V_ADAPTER_ILIM_P

IAC_RC_COMP

ADAPTER_I_REG

=PP3V3_ALL_PBUS_ILIM

AC_GTR_18V

LTC1625_ITH

1625_COMP

IAC_FB

MAX4172_OUT

CURRENT_THRESHOLD

A29_CURRENT_ADJ

OVER_18V_ADJ

=PP3V3_ALL_PBUS_ILIM

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

PPVOUT_BATT_CHRG_R

VOLTAGE=14V

1772_ICTL

1772_ACOK_L

1772_CSSP

1772_ICHG 1772_IINP

1772_VCTL

1772_BST_ESR

1772_BST

1772_DLOV

1772_CSSN

1772_CELLS

1772_CCV_RC

1772_CCV

BATT_LOW_L

CHARGE_DISABLE

BATTV_LOW

1772_CCS

1772_LDO

=PP3V3_ALL_BATT_CHGR

BATTV_HIGH

=PP3V3_ALL_BATT_CHGR

1V65_REF

A29_DETECT

A29_CLS_ADJ

1772_CCI

A29_DETECT

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

VOLTAGE=14V

PPVBATT_BATT_PBUSB_FUSE

=PPVBATT_BATT_PBUSB

BATT_14V_GATE

BATT_14PBUS_ENBATT_24PBUS_EN

SYS_ACIN

BKFD_PROT_EN_L

1772_ACIN

1772_ACOK_L

1772_DLO

1772_REF

=PPVIN_BATT_CHRG_VSNS

BATT_DIV

PP24V_ADAPTER_SW

1772_DCIN

=PPVBATT_BATT

BATT_LOW

1772_CLS

=PPVOUT_BATT_CHRG

PMU_CHARGE_V

SYS_ACIN_L

SYS_ACIN_L_RC

PMU_BATT0_CHARGE

1772_LX

=PPVIN_ALL_BATT_CHGR

1772_DHI

1772_GND

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=0V

25

13

18

13

12

10

13

10

14

10

13

10

12

10

12

13

10

12

10

11

12

25

10

V-

V+

G1

S1

D1

G2

D2

S2

SHUT

PLUS5VTAP

LP2951

ERR

FDBK

GND

SENSE

OUTIN

VTAP

IN OUT

SENSE

GND

FDBK

ERR

LP2951

SHUT

BOOST

SW

SGND PGND

TK

VIN

SYNC RUN/SS

VPROG

ITH FCB

INTVCC

TG

VOSENSE

BG

LTC1625

EXTVCC

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

PMU SUPPLY

NC

SUPERCAP HOOKS IN HERE

IF SUPERCAP BOM OPTION IS CHOSEN: OUTPUT AT U22.8 IS 5.4V

OUTPUT AT U23.1 IS 5.65V

NC

CONNECT LTC1625 TK PIN AT TOP-SIDE FET

12.8V PBUS SUPPLY

NC

KEEP VIN/TK LOOP SHORT

1625 IS SHUT-OFF

WHEN +24V_PBUS IS BELOW ~13.1V,

BOOTSTRAP SYSTEM FROM ADAPTER, MAIN BATTERY OR BACKUP BATTERY

NC

603

MF-LF

1/10W

5%

1

2

R1427

402

MF-LF

1/16W

1%

4.99K

1

2

R1425

SO8

RLA130N03

CRITICAL

321

4

8765

Q1400

MMBD914XXG

SOT23

3 1

D1420

10V 402

CERM

20%

0.1uF

2

1

C1400

402

158K

1% 1/16W MF-LF

2

1

R1401

16.2K

402

MF-LF

1/16W

1%

2

1

R1402

LMC7211

SM-LF

2

5

1

3

4

U1420

402

CERM

10V

20%

0.1uF

2

1

C1420

1%

1/16W

402

MF-LF

97.6K

2

1

R1420

10K

1/16W MF-LF

402

1%

2

1

R1421

1M

402

MF-LF

1/16W

1%

21

R1422

CRITICAL

FDG6324L

SC70-6-LF

1

5

6

Q1430

SC70-6-LF

FDG6324L

CRITICAL

4

3 2

6

Q1430

402

MF-LF

1/16W

5%

470K

2

1

R1430

603

MF-LF

5%

2.2

1/10W

2

1

R1410

4.7uF

1206

CERM

10V

20%

2

1

C1411

0

1/16W MF-LF 402

5%

NO STUFF

2

1

R1415

402

MF-LF

1/16W

5%

0

2

1

R1416

SM

21

XW1400

MBR0540XXG

SOD-123

21

D1450

390

5%

1/4W

MF-LF

1206

21

R1450

MBR0540XXG

SOD-123

21

D1452

1/10W MF-LF 603

5%

1

2

1

R1461

20%

603

X5R

6.3V

10UF

2

1

C1461

BACKUP_BATT

RB160M-60

SOD-123

21

D1460

RB160M-60

SOD-123

21

D1461

20% 10V CERM 402

0.1uF

2

1

C1460

BACKUP_BATT

603

1/10W MF-LF

5%

1

2

1

R1453

805

20% CERM

10V

2.2uF

BACKUP_BATT

2

1

C1453

470pF

10% 50V CERM 603

2

1

C1452

BACKUP_BATT

294K

1% 1/16W MF-LF

402

2

1

R1451

100K

1/16W

MF-LF

1%

402

2

1

R1452

402

0.1uF

20% 10V

CERM

2

1

C1451

SOI-LF

3

2

6

18

4

7

5

U1450

0.1uF

20%

805

CERM

50V

2

1

C1450

0.0047uF

25V CERM 402

10%

NO STUFF

2

1

C1412

SO-8-LF

CRITICAL

IRF7811W

321

4

8765

Q1401

MBRS140XXG

SMB

2

1

D1400

MMBD914XXG

SOT23

31

D1451

SM1

CRITICAL

8.0uH-6.8A

3

1

2

L1400

10%

1206

X7R

50V

2.2UF

2

1

C1403

2.2UF

10%

1206

X7R

50V

2

1

C1405

1206

X7R

50V

10%

2.2UF

2

1

C1407

2.2UF

10% 50V X7R 1206

2

1

C1404

2.2UF

10% 50V X7R 1206

2

1

C1406

2.2UF

10% 50V X7R 1206

2

1

C1408

SOI-3.3V-LF1

6

3

2

18

4

7

5

U1460

805

25V

20% CERM

0.22uF

2

1

C1410

4.7uF

20%

25V CERM 1206

2

1

C1402

25V 1206

CERM

20%

4.7uF

2

1

C1401

MBR0540XXG

SOD-123

21

D1410

CRITICAL

SSOP-LF

8

7

16 15 13

2

14

639

5

11

4

1

12

10

U1400

603

CERM

25V

5%

4700pF

2

1

C1421

603

CERM

50V

10%

470pF

2

1

C1425

805

CERM

50V

20%

0.1uF

2

1

C1427

603

CERM

25V

5%

4700pF

2

1

C1426

R1451

RES,MF-LF,1/16W,357K OHM,1%,0402,SMD

114S0465

?

SUPERCAP

1

12.8V PBUS/PMU Supplies

SYNC_DATE=N/A

C

051-6929

14

115

SYNC_MASTER=N/A

1625_FCB

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=5V

1625_INTVCC

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

1625_TG

PPVIN_ALL_ADAPT_OR_BATT

VOLTAGE=18V MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

FB_4_85V_BU

=PP4V85_ALL_VREG

=PP3V3_ALL_VREG

3V_PMU_VTAP

1625_VSW

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

VOLTAGE=4.6V

PP4V85_ALL_ESR

=PP24V_ADAPTER_PMU_SUPPLY

PP24V_ADAPT_PMU_ILIM

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

VOLTAGE=24V

=PP12V8_PBUS_PMU_SUPPLY

=PPVBATT_BATTERY_PMU_SUPPLY

1625_BST_ESR

COMP_RC

1625_COMP

=PP12V8_LTC1625_VREG

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

1625_BG

VOLTAGE=0V MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

1625_SGND

1625_RUNSS

1625_VIN

=PP3V3_ALL_LTC1625_SW

1625_DIV

1V20_REF

1625_VFB

1625_BST

=PP5V_SUPERCAP

PP3V3_ALL_ESR

MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm

VOLTAGE=3.3V

=PP5V_PWRON_LTC1625_EXTVCC

1625_ENABLE_L

1625_ENABLE

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

VOLTAGE=5V

PP5V_LTC1625_EXTVCC_SW

=PPVIN_ALL_LTC1625

PP4V6_ALL_RAW

MAKE_BASE=TRUE VOLTAGE=4.6V MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm

=PP5V_PWRON_PMU_SUPPLY

10

10 10

10

13

10

12

10

SGND PGND

STBYMD

FCB FREQSET

SNS1-

PGOOD

VOSNS2

VOUT

3.3

VCCVCC

EXT INT VIN

TG2

SW2

SNS2-

BG2

SNS2+

BOOST2

ITH2 RUN/

SS2SS1

SNS1+

BG1

SW1

BOOST1

TG1

VOSNS1 ITH1 RUN/

G

D

S

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

3V START TO TURN ON ~25MS AFTER =5V3V3PWRON_EN_L goes low

5V START TO TURN ON ~12.5MS =5V3V3PWRON_EN_L goes low

POWERDOWN DELAY IS AROUND 4MS-15.6MS, VIA RC NETWORK

DIODE WILL ENSURE REGULATOR TURNS ON QUICKLY

NC

3.3V/5V SWITCHER

SSOP-LF

LTC3707

CRITICAL

12

4

24

1627

1726

6

9

13

14

3

2

15

1

28

20

11

8

21

5

7

22

1825

1923

10

U1500

402

10

5% 1/16W MF-LF

2

1

R1502

MF-LF

CRITICAL

1/4W

1%

0.005

1206

21

R1551

805

CERM

25V

20%

0.22uF

2

1

C1511

0.01uF

402

CERM

16V

20%

21

C1585

SI3443DV

TSOP-LF

4

3 6

5 2 1

Q1585

SI3443DV

TSOP-LF

4

3 6

5 2 1

Q1580

20% 10V

CERM

402

0.1uF

21

C1580

10UF

20%

6.3V X5R 603

2

1

C1581

2.2

5% 1/10W MF-LF 603

2

1

R1511

20% 50V

CERM

402

0.001uF

21

C1514

SI3443DV

TSOP-LF

4

3 6

5 2 1

Q1590

402

10%

0.0022uF

CERM

50V

12

C1590

402

MF-LF

1/16W

1%

113K

2

1

R1504

MBR0540XXG

SOD-123

2

1

D1511

SOD-123

MBR0540XXG

2

1

D1561

2.2

5% 1/10W MF-LF

603

2

1

R1561

SOT23

MMBD914XXG

3 1

D1533

402

MF-LF

1/16W

5%

1M

21

R1533

402

0.01uF

20% 16V CERM

2

1

C1533

603

X5R

6.3V

20%

10UF

2

1

C1586

402

MF-LF

1/16W

1%

21.5K

2

1

R1505

402

CERM

25V

5%

220pF

2

1

C1532

2N7002

SOT23-LF

2

1

3

Q1533

402

CERM

50V

5%

180pF

NO STUFF

2

1

C1504

1206

CERM

10V

20%

4.7uF

2

1

C1530

402

0.1uF

20% 10V CERM

2

1

C1560

MBRS140XXG

SMB

2

1

D1551

SMB

MBRS140XXG

2

1

D1501

402

CERM

16V

10%

0.047uF

2

1

C1510

IHLP-5050

CRITICAL

4.7uH

2 1

L1501

IHLP-5050

CRITICAL

4.7uH

21

L1551

402

CERM

50V

10%

0.0022UF

NO STUFF

2

1

C1565

402

CERM

50V

10%

0.0022UF

NO STUFF

2

1

C1515

TANT

6.3V

20%

330uF

CRITICAL

CASE-D4-LF

2

1

C1553

CRITICAL

TANT

330uF

20%

6.3V

CASE-D4-LF

2

1

C1503

SO8

RLA130N03

CRITICAL

3 2 1

4

8 7 6 5

Q1501

CRITICAL

RLA130N03

SO8

321

4

8765

Q1551

SO-8-LF

IRF7811W

CRITICAL

3 2 1

4

8 7 6 5

Q1502

SO-8-LF

IRF7811W

CRITICAL

321

4

8765

Q1552

1206

2.2UF

10% 50V X7R

2

1

C1570

1206

2.2UF

10% 50V X7R

2

1

C1571

1206

2.2UF

10% 50V X7R

2

1

C1572

1206

X7R

50V

10%

2.2UF

2

1

C1573

1206

X7R

50V

10%

2.2UF

2

1

C1522

1206

X7R

50V

10%

2.2UF

2

1

C1523

1206

2.2UF

10% 50V X7R

2

1

C1521

1206

X7R

50V

10%

2.2UF

2

1

C1520

805

0.22uF

20% 25V CERM

2

1

C1561

100UF

20%

6.3V POLY B2

C1587

100UF

20%

6.3V POLY B2

2

1

C1582

B2

POLY

6.3V

20%

100UF

2

1

C1591

SI3443DV

TSOP-LF

4

3 6

5 2 1

Q1535

10UF

20%

6.3V X5R 603

2

1

C1592

603

X5R

6.3V

20%

10UF

2

1

C1536

402

MF-LF

1/16W

5%

100K

TPAD_SEQ_PMU

2

1

R1535

402

CERM

50V

5%

180pF

NO STUFF

2

1

C1554

402

MF-LF

1/16W

1%

63.4K

2

1

R1554

402

MF-LF

1/16W

1%

20.0K

2

1

R1555

CERM

16V

20%

0.01uF

402

2

1

C1531

402

MF-LF

1/16W

5%

0

2

1

R1532

402

MF-LF

1/16W

1%

100K

2

1

R1530

402

MF-LF

1/16W

1%

100K

2

1

R1531

402

0.0022uF

10% 50V CERM

2

1

C1562

402

100pF

5%

50V

CERM

2

1

C1563

12.7K

1% 1/16W MF-LF 402

2

1

R1562

402

CERM

50V

10%

0.0022uF

2

1

C1512

CERM

50V

5%

100pF

402

2

1

C1513

402

MF-LF

1/16W

1%

15.0K

2

1

R1512

1210

CERM

10V

20%

22uF

2

1

C1552

1210

CERM

10V

20%

22uF

2

1

C1551

1210

CERM

10V

20%

22uF

2

1

C1502

1210

CERM

10V

20%

22uF

2

1

C1501

SM

2

1

XW1500

10

5% 1/16W MF-LF 402

2

1

R1503

402

MF-LF

1/16W

5%

10

2

1

R1552

402

MF-LF

1/16W

5%

10

2

1

R1553

MF-LF

0.005

1%

1/4W

CRITICAL

1206

21

R1501

20% 50V

CERM

402

0.001uF

21

C1564

1M

5% 1/16W MF-LF

402

2

1

R1510

1M

5% 1/16W MF-LF 402

2

1

R1560

15

115

C

051-6929

SYNC_MASTER=N/A

SYNC_DATE=N/A

5V/3.3V Supplies

=PP5V_PWRON_REG

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=5V

3707_INTVCC

3707_SGND

VOLTAGE=0V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

=PP5V_TPAD_FET

=5VPWRONTPAD_EN_L

=PP5V_PWRON_TRACKPAD

=PP5V_PWRON_RUNFET

5VRUN_EN_L

=PP5V_RUN_RUNFET

5VRUNHD_EN_L

=PP5V_RUN_HDDFET

5V3VPWRON_EN_L_RC

=5V3V3PWRON_EN_L

3707_STBYMD

5V_RUNSS

5V_ITH

5V_VOSNS

5V_SNSP

5V_BG

5V_BOOST

3V_RUNSS

3V_ITH

3V_SNSM

3V_SNSP

3V_BG

3V_BOOST

=PP5V_PWRON_LTC3707_EXTVCC

3V_VOSNS

=5V3VPWRON_PGOOD

5V_SNSM

3707_FSET

3707_FCB

=PP3V3_PWRON_REG

3V_RSNS

3V_ITH_RC

3V_BOOST_ESR

5V_BOOST_ESR

5V_ITH_RC

5V_RSNS

=PP3V3_RUN_RUNFET

3V3RUN_EN_L

=PP3V3_PWRON_RUNFET

5V_SW

5V_TG

3V_SW

=PPVIN_ALL_LTC3707

3V_TG

10

26

10

26

10

26

10

26

10

26

10

26

10

AGND

THRML

NC_28

NC_23

NC_15

BST2

OUT1

TON

PGOOD REF

DL1

LX1

DH1

VCC

BST1

ON2

ON1

ILIM2

ILIM1

OUT2

SKIP

DL2

LX2

PGND

DH2

VDD

V+

FB1

FB2

G

D

S

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Rb

Ra

Vout = 1.0V * (1 + Ra/Rb)

Ra

Rb

MAX1715_GND

1.5V/1.8V SWITCHER

NC

DIODE PROVIDE PROVIDE QUICK TURN-ON POWER DOWN DELAY 1.5MS TO 3.5MS

1uF

20% 10V CERM 603

2

1

C1632

20

5% 1/16W MF-LF

402

2 1

R1630

QSOP-LF

CRITICAL

MAX1715

2021

4

5

29

69

7

22

14

1

11

10

28

23

15

1627

12

3

13

2

1924

1726

1825

8

U1600

CRITICAL

4.7uH

SM4-LF

21

L1651

SO8

CRITICAL

RLA130N03

3 2 1

4

8 7 6 5

Q1651

CRITICAL

RLA130N03

SO8

321

4

8765

Q1601

158K

1% 1/16W MF-LF 402

2

1

R1671

158K

1% 1/16W MF-LF

402

2

1

R1621

SOT-363

BAS16TW-X-F

5 2

DP1620

603

MF-LF

1/10W

5%

4.7

21

R1670

603

MF-LF

1/10W

5%

4.7

21

R1620

603

0.1uF

20% 25V CERM

2

1

C1670

B130LBT01XF

SMB

2

1

D1651

5.11K

1% 1/16W MF-LF 402

2

1

R1651

10K

1/16W MF-LF 402

1%

2

1

R1652

603

0.1uF

20% 25V CERM

2

1

C1620

CRITICAL

4.7uH

SM4-LF

21

L1601

0

5% 1/16W MF-LF 402

2

1

R1634

402

1/16W MF-LF

5%

0

NO STUFF

2

1

R1633

330UF

20%

2.5V-ESR9V POLY

CASE-D2E-LF

2

1

C1653

150uF

20%

6.3V POLY CASE-D2-LF

2

1

C1604

1206

CERM

25V

20%

4.7uF

CRITICAL

2

1

C1601

1206

CERM

25V

20%

4.7uF

CRITICAL

2

1

C1602

1206

CERM

25V

20%

4.7uF

CRITICAL

2

1

C1652

4.7uF

1206

CERM

25V

20%

CRITICAL

2

1

C1651

NO STUFF

0

5% 1/16W MF-LF 402

2

1

R1631

NO STUFF

0

5% 1/16W MF-LF 402

2

1

R1632

B130LBT01XF

SMB

2

1

D1601

SM

21

XW1600

10UF

20%

6.3V X5R 603

2

1

C1686

603

X5R

6.3V

20%

10UF

2

1

C1603

603

X5R

6.3V

20%

10UF

2

1

C1655

805

CERM

10V

20%

2.2uF

2

1

C1631

CERM

10V

20%

2.2uF

805

2

1

C1630

SOT-363

BAS16TW-X-F

6 1

DP1620

402

MF-LF

1/16W

5%

330K

21

R1640

CERM

16V

20%

0.01uF

402

2

1

C1640

TSOP-LF

SI3446DV

4

36

5

2

1

Q1685

2N7002

SOT23-LF

2

1

3

Q1640

100K

5% 1/16W MF-LF

402

2

1

R1641

402

X7R

25V

10%

1000pF

2

1

C1685

10%

0.0022UF

CERM 402

50V

NO STUFF

2

1

C1621

0.0022UF

50V 402

CERM

10%

NO STUFF

2

1

C1671

1% 1/16W MF-LF

402

8.06K

2

1

R1601

10K

1% 1/16W MF-LF

402

2

1

R1602

IRF7805ZPBF

SO-8

CRITICAL

3 2 1

4

8 7 6 5

Q1652

SO-8

IRF7805ZPBF

CRITICAL

321

4

8765

Q1602

SOT-363

BAS16TW-X-F

4 3

DP1620

330UF

20%

2.5V-ESR9V CASE-D2E-LF

POLY

2

1

C1605

CRITICAL

TSSOP

SI6467BDQ-E3

7632

4

851

Q1680

603

10UF

20%

6.3V X5R

2

1

C1680

402

MF-LF

1/16W

5%

100K

2

1

R1680

5%

50V

CERM

2200pF

603

21

C1681

X7R

25V

10%

1000PF

NO STUFF

402

2

1

C1682

115

16

051-6929

C

SYNC_MASTER=N/A

SYNC_DATE=N/A

1.8V/1.5V Supplies

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=0V

MAX1715_GND

=PPVIN_ALL_MAX1715

1_8V_LX

1_5V_DH

=PPVIN_ALL_MAX1715

1_8V_DL

=1V8_1V5PWRON_EN_L

MAX1715_EN_L_RC

MAX1715_ON

=PPVIN_ALL_MAX1715

=PP5V_PWRON_MAX1715_VDD

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

VOLTAGE=5V

PP5V_MAX1715_VCC

1V5RUN_EN

=1V8_1V5PWRON_PGOOD

=PP1V5_PWRON_RUNFET

=PP1V5_RUN_RUNFET

1_5V_DL

1_5V_BST

MAX1715_REF

1_8V_FB

MAX1715_SKIP

1_8V_ILIM

MAX1715_GND

1_5V_ILIM

1_8V_BST

MAX1715_TON

1_5V_BOOST 1_8V_BOOST

=PP1V8_RUN_RUNFET

=PP1V8_PWRON_RUNFET

1V8RUN_EN_L

=PP1V8_PWRON_REG

1_8V_DH

1_5V_FB

1_5V_LX

=PP1V5_PWRON_REG

16

10

26

10 10

26

10 10

16

10

26

10

SW

SGND PGND

PAD

THERM

SVIN PVIN

PGOOD

VFB

ITH SYNC/MODE

RUN/SS

RT

G

D

S

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

2.5V SWITCHER

CONTINUOUS MODE

BURST MODE

1206-1

6.3V

20%

47uF

X5R

2

1

C1700

7.5K

1/16W MF-LF

1%

402

2

1

R1720

5%

CERM

603

2200pF

50V

2

1

C1721

SM

21

XW1700

TSSOP-LF

LTC3412

CRITICAL

4

17

6

15

14

11

10

1

8

7

5

16

9

2

13

12

3

U1700

402

100PF

5%

50V

CERM

2

1

C1720

110K

1% 1/16W MF-LF 402

2

1

R1731

402

75K

1% 1/16W MF-LF

2

1

R1732

CERM

50V

5.6pF

402

+/-0.25pF

2

1

C1730

402

1% 1/16W MF-LF

402K

2

1

R1730

402

10% 50V

CERM

470PF

2

1

C1722

402

MF-LF

1/16W

5%

4.7M

2

1

R1722

402

NO STUFF

0

5% 1/16W MF-LF

2

1

R1724

402

MF-LF

1/16W

5%

0

2

1

R1723

402

309K

1% 1/16W MF-LF

2

1

R1733

1.0uH-3.48A

SM-LF

CRITICAL

21

L1700

1206-1

20%

6.3V

47uF

X5R

2

1

C1701

CERM

6.3V

20%

22UF

1206

2

1

C1710

SOT-363

2N7002DW-X-F

4

5

3

Q1740

1000pF

402

X7R

25V

10%

21

C1780

SI6467BDQ-E3

TSSOP

7632

4

851

Q1780

603

10UF

20%

6.3V X5R

2

1

C1781

1206

CERM

6.3V

20%

22UF

2

1

C1711

2.5V Supply

SYNC_MASTER=N/A

SYNC_DATE=N/A

115

C

17

051-6929

=2V5PWRON_PGOOD

LTC3412_RUNSS

LTC3412_RT

=2V5PWRON_EN_L

=PP2V5_RUN_RUNFET

2V5RUN_EN_L

=PP2V5_PWRON_RUNFET

LTC3412_SW

LTC3412_VFB_DIV

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=0V

LTC3412_GND

LTC3412_VFB

=PP3V3_PWRON_LTC3412

LTC3412_SYNC

LTC3412_ITH_RC

LTC3412_ITH

=PP2V5_PWRON_REG

26

2

26

10

26

10

VESTA MISC

1 OF 3

PVDDDVDD

AVDDL

AVDD

GND

AGND

OVDD

REGSUP1 REGSEN1 REGCTL1

REGSUP2 REGSEN2 REGCTL2

2.5V_EN

NC

DNC

NC

TDO TCK TMS TRST*

TDI

RESET*

PVINSVIN

SHDN/RT SYNC/MODE

SW VFB ITH

PGOOD

PGND SGND

GND

VOUT

VIN

NOISE

CONT

G

D

S

G

D

S

G

D

S

ON/OFF

GND

VOUT

FB

VIN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

R1952 to enable wirespeed feature

Burst Mode

Mode

Continuous

Port Power Switch

1.2V Regulator

Page Notes

- =PPBUS_FW (system supply for bus power)

Signal aliases required by this page:

- =PP3V3_RUN_FWPORTPWRSW

- =PPBU_RUN_FW (backup PHY power)

regulator will be in continuous mode.

regulator. If both options are off the

Power aliases required by this page:

Controls operating mode of Vesta 1.2V

BOM options provided by this page:

Vout = 2.5V @ 150 mA

<R1>

2.5V LDO

<R2>

- VESTA1V2_BURST / VESTA1V2_PULSE

(NONE)

Vout = 1.199V @ 1.2 A

Vout = 0.8V * (1 + (R2 / R1))

3.3V Regulator

If =FWPWR_PWRON is NC:

Enables port power when machine is

If =FWPWR_PWRON is low when off:

running or on AC.

Pulse Mode

Vout = 3.3V @ 500mA

L6/M6 L9/M9

NC

N5/N6

N9/N10

NC?

running or on AC and not shut down.

NC

(Int PU)

Schmitt trigger

Reset circuit per Vesta design guide

10V

20%

402

CERM

0.1uF

2

1

C1910

10V

20%

402

CERM

0.1uF

2

1

C1911

10V

20%

402

CERM

0.1uF

2

1

C1912

10V

20%

402

CERM

0.1uF

2

1

C1913

0.1uF

CERM

402

20% 10V

2

1

C1903

10V

20%

402

CERM

0.1uF

2

1

C1902

CERM

10V

20%

402

0.1uF

2

1

C1901

0.1uF

20% 10V

402

CERM

2

1

C1900

0.1uF

CERM

402

20% 10V

2

1

C1922

0.1uF

CERM

402

20% 10V

2

1

C1925

0.1uF

CERM

402

20% 10V

2

1

C1921

0.1uF

CERM

402

20% 10V

2

1

C1924

0.1uF

402

20%

CERM

10V

2

1

C1931

0.1uF

CERM

402

20% 10V

2

1

C1930

0.1uF

CERM

402

20% 10V

2

1

C1920

0.1uF

CERM

402

20% 10V

2

1

C1923

0.1uF

20%

402

CERM

10V

2

1

C1943

0.1uF

CERM

402

20% 10V

2

1

C1942

0.1uF

CERM

402

20% 10V

2

1

C1941

0.1uF

CERM

402

20% 10V

2

1

C1940

10%

6.3V 402

CERM

1uF

2

1

C1950

BCM5462

FBGA-200

OMIT

D8

E8

E10

D7

E7

H4

E2

E1

F2

F1

G4

G5

N4

A15

K1

F15

A7

A1

M13

C3

K2

J2

F14

C14

B7B2A2

J1

C15

B15

B1

E9

C9

B9

N10

N9N6N5M9M6L9L6

R12R3P11

P10P5P4

N8N7M8M7L8

L7

J12

J11

P9P8P7

P6

H12

H11

M3

U8500

MF-LF

5%

402

1/16W

20K

2

1

R1950

10UF

X5R 603

20%

6.3V

2

1

C1908

SM

FERR-EMI-600-OHM

21

L1900

MSOP-LF

LTC3411

CRITICAL

9

2

4

7

1

3

6

8

5

10

U1990

50V

5%

402

CERM

100pF

2

1

C1993

1%

402

MF-LF

4.99K

1/16W

2

1

R1996

50V

402

CERM

0.0033uF

10%

2

1

C1994

CRITICAL

2.2uH

SM1-LF

21

L1990

50V

5%

402

CERM

22pF

2

1

C1992

1/16W

1%

402

MF-LF

4.99K

2

1

R1997

10K

1/16W

1%

402

MF-LF

2

1

R1998

20%

22uF

X5R 805

6.3V

2

1

C1995

402

CERM

1uF

10%

6.3V 2

1

C1991

10

MF-LF

402

5%

1/16W

21

R1990

10UF

X5R 603

20%

6.3V

2

1

C1990

1/16W

1%

402

MF-LF

324K

2

1

R1995

1M

MF-LF

402

5%

1/16W

2

1

R1994

402

1/16W

5%

MF-LF

1M

2

1

R1991

VESTA1V2_PULSE

1/16W

5%

402

MF-LF

10K

2

1

R1993

VESTA1V2_BURST

1/16W

5%

402

MF-LF

10K

2

1

R1992

SM

21

XW1990

0.01uF

CERM

402

20% 16V

2

1

C1981

402

CERM

1uF

10%

6.3V 2

1

C1980

10UF

X5R 603

20%

6.3V

2

1

C1982

330K

MF-LF 402

5% 1/16W

2

1

R1966

0.01uF

CERM

20% 16V

402

2

1

C1965

470K

MF-LF 402

5% 1/16W

2

1

R1965

SOT-363

BAS16TW-X-F

43

DP1960

SOT-363

BAS16TW-X-F

5 2

DP1960

BAS16TW-X-F

SOT-363

61

DP1960

1/16W

5%

402

MF-LF

10K

21

R1961

MF-LF

1/16W

5%

402

100K

2

1

R1960

1/16W

5%

402

MF-LF

470K

2

1

R1963

SOT-25A-LF

CRITICAL

MM1572FN

51

4

2

3

U1980

SMB

B340XF

CRITICAL

21

D1965

SOI-LF

CRITICAL

NDS9407

3 2

1

4

8

7

6 5

Q1965

MINISMDC

1.5A-24V

21

F1965

10K

MF-LF

402

5%

1/16W

2

1

R1952

SMD

MMBRM140XXG

2

1

D1970

SOT23-LF

2N7002

2

1

3

Q1960

MF-LF

5%

402

1/16W

10K

2

1

R1951

2N7002DW-X-F

SOT-363

1

2

6

Q1950

SOT-363

2N7002DW-X-F

4

5

3

Q1950

SC-59

SMD20E40C-X-F

3

2

1

D1975

CRITICAL

LM2594

SM-LF

8

7

56

4

U1970

50V

N20P20%

2320

CERM

10uF

2

1

C1970

100UF

B2

20%

6.3V POLY

CRITICAL

2

1

C1971

PLC

100uH-0.8A

CRITICAL

21

L1970

C

051-6929

19

115

Vesta Power & Misc

SYNC_MASTER=N/A

SYNC_DATE=N/A

=PP3V3_VESTA

VESTA_RESET_L_RC

VESTA_RESET

VESTA_RESET_L

VOLTAGE=25V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

PPBUS_FWPWRSW_F

=PPBUS_FWPWRSW

=PP2V5_VESTA

=PP3V3_VESTA

=PP1V2_VESTA

=PP3V3_VESTA

PP1V2_VESTA_AVDDL

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=1.2V

=JTAG_VESTA_TRST_L

=JTAG_VESTA_TMS

=JTAG_VESTA_TCK

=JTAG_VESTA_TDI =JTAG_VESTA_TDO

TP_VESTA_2_5V_EN

TP_VESTA_REGSUP1 TP_VESTA_REGSEN1

TP_VESTA_REGSUP2 TP_VESTA_REGSEN2

VESTA1V2_MODE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

FWPWR_EN_L

FWPWR_EN

=FWPWR_PWRON

=PP2V5_VESTA_LDO

=PP1V2_VESTA_REG

=PP3V3_VESTA_2V5REG

VESTA1V2_ITH

VESTA2V5_NOISE

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

=PPBUS_FW_FET

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=25V

PPBUS_FW_FET_D

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

FWPWR_EN_L_DIV

=PPBU_RUN_FW

=PPFW_P3V3VESTA

=PP3V3_VESTA_REG

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

VOLTAGE=33V

PPVIN_VESTA3V3

FWPWR_RUN

FWPWR_ACIN

SYS_ACIN

=PP3V3_RUN_FWPORTPWRSW

VESTA1V2_ITH_RC

VESTA1V2_VFB

VESTA1V2_SW

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

VESTA3V3_SW

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

VOLTAGE=0V

VESTA1V2_SGND

MIN_NECK_WIDTH=0.25 mm

VOLTAGE=3.3V MIN_LINE_WIDTH=0.5 mm

PPVOUT_VESTA1V2

=PP3V3_VESTA_1V2REG

VESTA1V2_RT

TP_VESTA_DNC_E9

TP_VESTA_DNC_C9

TP_VESTA_DNC_B9

TP_VESTA_REGCTL1

TP_VESTA_REGCTL2

67

66

65

25

18

13

10

66

10

9

2

26

10

12

10

2

VDD15_0

VDD15_1

VDD15_2

VDD15_3

VDD15_4

VDD15_5

VDD15_6

VDD15_7

VDD15_8

VDD15_9

VDD15_10

VDD15_11

VDD15_12

VDD15_13

VDD15_15

VDD15_14

VDD15_16

VDD15_17

VDD15_18

VDD15_19

VDD15_20

VDD15_21

VDD15_22

VDD15_23

VDD15_24

VSS_49

VSS_48

VSS_46 VSS_47

VSS_45

VSS_44

VSS_43

VSS_41 VSS_42

VSS_40

VSS_39

VSS_38

VSS_35 VSS_36 VSS_37

VSS_33 VSS_34

VSS_32

VSS_30 VSS_31

VSS_28 VSS_29

VSS_27

VSS_25 VSS_26

VSS_23 VSS_24

VSS_21

VSS_20

VSS_19

VSS_17 VSS_18

VSS_15

VSS_13

VSS_12

VSS_10 VSS_11

VSS_5

VSS_2 VSS_3 VSS_4

VSS_1

VSS_0

VSS_98 VSS_99

VSS_149

VSS_148

VSS_96 VSS_97

VSS_95

VSS_93 VSS_94

VSS_91 VSS_92

VSS_90

VSS_88 VSS_89

VSS_86

VSS_85

VSS_87

VSS_83 VSS_84

VSS_82

VSS_81

VSS_80

VSS_79

VSS_78

VSS_147

VSS_146

VSS_145

VSS_143 VSS_144

VSS_142

VSS_141

VSS_140

VSS_138 VSS_139

VSS_137

VSS_136

VSS_135

VSS_133 VSS_134

VSS_131 VSS_132

VSS_130

VSS_128 VSS_129

VSS_198 VSS_199

VSS_197

VSS_196

VSS_195

VSS_193 VSS_194

VSS_192

VSS_191

VSS_190

VSS_188 VSS_189

VSS_186 VSS_187

VSS_185

VSS_183 VSS_184

VSS_182

VSS_181

VSS_180

VSS_179

VSS_178

VSS_77

VSS_76

VSS_75

VSS_74

VSS_73

VSS_72

VSS_70 VSS_71

VSS_69

VSS_67 VSS_68

VSS_65 VSS_66

VSS_64

VSS_62 VSS_63

VSS_60 VSS_61

VSS_58

VSS_57

VSS_59

VSS_126 VSS_127

VSS_125

VSS_123 VSS_124

VSS_122

VSS_121

VSS_120

VSS_117 VSS_118 VSS_119

VSS_116

VSS_115

VSS_112

VSS_114

VSS_113

VSS_111

VSS_110

VSS_107

VSS_109

VSS_108

VSS_55 VSS_56

VSS_53

VSS_52

VSS_54

VSS_50 VSS_51

VSS_106

VSS_105

VSS_102 VSS_103 VSS_104

VSS_100 VSS_101

VSS_176 VSS_177

VSS_175

VSS_174

VSS_173

VSS_172

VSS_171

VSS_170

VSS_169

VSS_167 VSS_168

VSS_166

VSS_165

VSS_164

VSS_163

VSS_162

VSS_161

VSS_160

VSS_159

VSS_158

VSS_157

VSS_156

VSS_155

VSS_153 VSS_154

VSS_152

VSS_150 VSS_151

VSS_22

VSS_16

VSS_14

VSS_9

VSS_8

VSS_7

VSS_6

CORE POWER & GND

(1 of 14)

VDD33_47

VDD33_46

VDD33_45

VDD33_44

VDD33_41 VDD33_42 VDD33_43

VDD33_39 VDD33_40

VDD33_38

VDD33_37

VDD33_36

VDD33_34 VDD33_35

VDD33_33

VDD33_32

VDD33_31

VDD33_30

VDD33_29

VDD33_28

VDD33_27

VDD33_26

VDD33_24 VDD33_25

VDD33_23

VDD33_21 VDD33_22

VDD33_19 VDD33_20

VDD33_18

VDD33_16 VDD33_17

VDD33_15

VDD33_14

VDD33_13

VDD33_12

VDD33_11

VDD33_8

VDD33_5 VDD33_6 VDD33_7

VDD33_3 VDD33_4

VDD33_0

VDD33_2

VDD33_1

VDD33_9

VDD33_10

(2 of 14)

3.3V I/O POWER

PLL1_AVDD

PLL2_AVDD

PLL1_VSSA

PLL3_AVDD

PLL2_VSSA

PLL4_AVDD

PLL3_VSSA

PLL4_VSSA

PLL5_AVDD

PLL5_VSSA

PLL6_AVDD

PLL6_VSSA

PLL7_AVDD

PLL7_VSSA

PLL9_AVDD

PLL9_VSSA

AGP TRACK

PLL9

PCI TRACK

PLL7

PLL6

SYS TRACK

ATA

PCI AGP

INT REF

PLL5

SYSCLK

PLL4

AGP(SS)

PCI(SS)

49.15 MHZ

PLL3

45.16 MHZ

PLL2

32/48 MHZ

PLL1

(3 of 14)

PLL POWER

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

4 X 10uF (0603) 25 X 1uF (0402)

48 X 1uF (0402)

1 X 10uF (0603)

VCore Bypassing

(25 Balls on I2)

VDD33_IO_1 (14)

For USB, FireWire,

For GPIOs, Pwr Mgt

VDD33_IO_2 (12)

VDD33_PCI (18)

VDD33_

MAXBUS

- =PP1V5_PWRON_I2_PLL

Page Notes

I2S and some GPIOs

VDD33_AGP

(48 Balls on I2)

out separately for test purposes. NOTE: When these four rails are not aliased together, make sure there is at least one 10uF cap per rail.

(NONE)

BOM options provided by this page:

Signal aliases required by this page:

aliased together. They are called

NOTE: The four 3.3V rails are meant to be

- =PP3V3_PWRON_I2_MAXBUS

- =PP3V3_PWRON_I2_AGPPCI

- =PP3V3_PWRON_I2_IO2

- =PP3V3_PWRON_I2_IO1

- =PPVCORE_PWRON_I2

Power aliases required by this page:

3.3V I/O DECOUPLING

6.3V

10%

402

CERM

1uF

2

1

C2158

1uF

CERM 402

10%

6.3V

2

1

C2126

1uF

CERM 402

10%

6.3V

2

1

C2133

6.3V

20%

603

X5R

10UF

2

1

C2147

1uF

402

CERM

10%

6.3V

2

1

C2144

6.3V

10%

402

CERM

1uF

2

1

C2163

BGA

I2

OMIT

E29

E26

E23

E20

E2

E17

E14

E11

B8

B5

AB22

B35

B32

B29

B26

B23

B20

B2

B17

B14

B11

AB16

AR8

AR5

AR35

AR32

AR29

AR26

AR23

AR20

AR2

AR17

AB15

AR14

AR11

AM8

AM7

AM5

AM35

AM32

AM29

AM26

AM23

AB12

AM20

AM2

AM17

AM14

AM11

AJ8

AJ5

AJ35

AJ32

AJ29

AA29

AJ27

AJ26

AJ24

AJ23

AJ20

AJ2

AJ17

AJ14

AJ11

AH14

AA25

AG29

AG14

AG11

AF8

AF5

AF35

AF32

AF29

AF27

AF2

AA21

AF18

AF10

AE25

AE20

AE19

AE17

AE15

AE14

AD29

AD21

AA17

Y8

Y5

Y35

Y32

Y29

Y22

Y2

Y18

Y16

Y11

AD16

W26

W25

W21

W19

W15

V28

V20

V16

V12

U8

AC5

U5

U35

U32

U28

U25

U21

U2

U16

U13

T20

AC35

T18

T16

R29

R25

R22

R20

R19

R17

R15

R13

AC32

P8

P5

P35

P32

P29

P27

P24

P21

P2

P17

AC29

N25

N23

N18

N16

N14

M26

M23

M21

M19

M17

AC26

M15

M13

L8

L5

L35

L32

L29

L27

L20

L2

AC25

K29

K26

K25

K23

K20

K17

K14

K11

K10

H8

AC20

H5

H35

H32

H29

H27

H26

H24

H23

H20

H2

AC2

H18

H17

H15

H14

H12

H11

E8

E5

E35

E32

AB24

AA15

AA13

R21

R18

R16

P20

P16

N17

AC19

Y17

Y15

W22

W20

W18

AC16

V22

V19

V17

U22

U20

U18

U15

T22

T19

T15

AB21

AA22

U2100

1uF

CERM 402

10%

6.3V

2

1

C2139

1uF

CERM 402

10%

6.3V

2

1

C2138

BGA

I2

OMIT

N13

L6

L3

L10

J8

AP32

AP29

AP26

AP23

AL30

AL29

AL27

AL26

H6

AL24

AL23

AH27

AH26

AH24

AH23

AH20

AD22

AD20

AC21

H3

M22

M18

M16

Y13

AM3

AJ6

AJ3

AF9

AF6

AF3

F5

AF11

AC6

AC3

AC15

AB13

T13

R14

P6

P3

P12

E3

AH17

U2100

6.3V

10%

402

CERM

1uF

2

1

C2169

6.3V

10%

402

CERM

1uF

2

1

C2168

6.3V

10%

402

CERM

1uF

2

1

C2152

6.3V

10%

402

CERM

1uF

2

1

C2151

1uF

CERM 402

10%

6.3V

2

1

C2132

1uF

CERM 402

10%

6.3V

2

1

C2131

1uF

CERM 402

10%

6.3V

2

1

C2130

1uF

6.3V

10%

402

CERM

2

1

C2101

1uF

6.3V

10%

402

CERM

2

1

C2102

1uF

6.3V

10%

CERM 402

2

1

C2103

1uF

6.3V

10%

402

CERM

2

1

C2104

1uF

402

CERM

10%

6.3V

2

1

C2105

1uF

6.3V

10%

CERM 402

2

1

C2106

1uF

6.3V

10%

402

CERM

2

1

C2107

6.3V

10%

402

CERM

1uF

2

1

C2150

1uF

6.3V

10%

402

CERM

2

1

C2109

4.7

5%

MF-LF

402

1/16W

21

R2101

4.7

5%

MF-LF

402

1/16W

21

R2102

4.7

5%

MF-LF

402

1/16W

21

R2103

4.7

MF-LF

5%

402

1/16W

21

R2104

4.7

1/16W

402

MF-LF

5%

21

R2105

4.7

MF-LF

5%

402

1/16W

21

R2106

4.7

MF-LF

5%

402

1/16W

21

R2107

4.7

5%

402

1/16W MF-LF

21

R2109

OMIT

BGA

I2

AL10

AK10

AH21

AH22

N24

M24

AE9

AD9

H10

H9

AJ19

AK19

Y19

AA19

Y20

AA20

U2100

6.3V

10%

402

CERM

1uF

2

1

C2162

10UF

X5R 603

20%

6.3V 2

1

C2146

10UF

X5R 603

20%

6.3V 2

1

C2149

10UF

X5R 603

20%

6.3V 2

1

C2148

6.3V

10UF

X5R 603

20%

2

1

C2199

6.3V

10%

402

CERM

1uF

2

1

C2157

6.3V

10%

402

CERM

1uF

2

1

C2156

402

CERM

6.3V

10%

1uF

2

1

C2174

6.3V

10%

402

CERM

1uF

2

1

C2155

6.3V

10%

402

CERM

1uF

2

1

C2161

6.3V

10%

402

CERM

1uF

2

1

C2160

6.3V

10%

402

CERM

1uF

2

1

C2167

6.3V

10%

402

CERM

1uF

2

1

C2166

6.3V

10%

402

CERM

1uF

2

1

C2165

6.3V

10%

402

CERM

1uF

2

1

C2173

6.3V

10%

402

CERM

1uF

2

1

C2172

6.3V

10%

1uF

402

CERM

2

1

C2171

6.3V

10%

402

CERM

1uF

2

1

C2170

1uF

CERM

402

10%

6.3V 2

1

C2179

1uF

CERM

402

10%

6.3V 2

1

C2178

1uF

CERM

402

10%

6.3V 2

1

C2177

1uF

CERM

402

10%

6.3V 2

1

C2176

CERM

402

6.3V

10%

1uF

2

1

C2175

1uF

CERM

402

10%

6.3V 2

1

C2185

1uF

CERM

402

10%

6.3V 2

1

C2191

1uF

CERM

402

10%

6.3V 2

1

C2184

CERM

402

1uF

10%

6.3V 2

1

C2183

1uF

CERM

402

10%

6.3V 2

1

C2182

1uF

CERM

402

10%

6.3V 2

1

C2181

6.3V

10%

402

CERM

1uF

2

1

C2154

1uF

CERM

402

10%

6.3V 2

1

C2180

1uF

CERM

402

10%

6.3V 2

1

C2190

1uF

CERM

402

10%

6.3V 2

1

C2189

1uF

CERM

402

10%

6.3V 2

1

C2188

1uF

CERM

402

10%

6.3V 2

1

C2187

1uF

CERM

402

10%

6.3V 2

1

C2186

1uF

CERM

402

10%

6.3V 2

1

C2197

1uF

CERM

402

10%

6.3V 2

1

C2196

6.3V

10%

402

CERM

1uF

2

1

C2153

1uF

CERM

402

10%

6.3V 2

1

C2195

1uF

CERM

402

10%

6.3V 2

1

C2194

1uF

CERM

402

10%

6.3V 2

1

C2193

1uF

CERM

402

10%

6.3V 2

1

C2192

1uF

CERM 402

10%

6.3V

2

1

C2125

1uF

CERM 402

10%

6.3V

2

1

C2137

6.3V

10%

402

CERM

1uF

2

1

C2159

1uF

CERM 402

10%

6.3V

2

1

C2124

1uF

CERM 402

10%

6.3V

2

1

C2136

1uF

CERM 402

10%

6.3V

2

1

C2135

1uF

CERM 402

10%

6.3V

2

1

C2129

1uF

CERM 402

10%

6.3V

2

1

C2123

1uF

CERM 402

10%

6.3V

2

1

C2122

1uF

CERM 402

10%

6.3V

2

1

C2128

1uF

CERM 402

10%

6.3V

2

1

C2134

402

CERM

1uF

10%

6.3V

2

1

C2143

6.3V

10%

402

CERM

1uF

2

1

C2164

402

CERM

1uF

10%

6.3V

2

1

C2142

402

CERM

1uF

10%

6.3V

2

1

C2141

402

CERM

1uF

10%

6.3V

2

1

C2140

1uF

CERM 402

10%

6.3V

2

1

C2121

1uF

CERM 402

10%

6.3V

2

1

C2127

1uF

CERM 402

10%

6.3V

2

1

C2120

SYNC_DATE=N/A

SYNC_MASTER=N/A

I2 Power

051-6929

C

115

21

=PP3V3_PWRON_I2_MAXBUS =PP3V3_PWRON_I2_AGPPCI

=PP3V3_PWRON_I2_IO1

=PP3V3_PWRON_I2_IO2

=PPVCORE_PWRON_I2

PP1V5_PWRON_I2_PLL1AVDD

VOLTAGE=1.5V MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm

VOLTAGE=1.5V

PP1V5_PWRON_I2_PLL2AVDD

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm

VOLTAGE=1.5V

PP1V5_PWRON_I2_PLL3AVDD

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.25 mm

VOLTAGE=1.5V

PP1V5_PWRON_I2_PLL4AVDD

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm

VOLTAGE=1.5V

PP1V5_PWRON_I2_PLL5AVDD

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.25 mm

VOLTAGE=1.5V

PP1V5_PWRON_I2_PLL6AVDD

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.25 mm

VOLTAGE=1.5V

PP1V5_PWRON_I2_PLL7AVDD

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm

VOLTAGE=1.5V

PP1V5_PWRON_I2_PLL9AVDD

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.25 mm

=PP1V5_PWRON_I2_PLL

10

SW

SGND PGND

PAD

THERM

SVIN PVIN

PGOOD

VFB

ITH SYNC/MODE

RUN/SS

RT

ADJ

BYP GND

OUT

NC

SHDN

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

One for each PVIN pin

I2 VCore Regulator

Open-Collector

Page Notes

<Rb>

<Ra>

<Rb1>

<Rb2>

Vburst = 0.8V * (Rb2 / (Rb1 + Rb2))

If I2VCORE_BURST is selected: Iburst = (Vburst - 0.2V) * (3.75A / 0.8V)

Iadj = 30nA at 25 C

I2 PLL LDO

- =PP1V5_PWRON_I2PLLVDD_LDO

- =PPVIN_PWRON_I2PLLVDD

indicated LTC3412 output voltage.

- I2VCORE_xVx

- I2VCORE_CONT / I2VCORE_BURST

burst mode for LTC3412 regulator.

- =I2VCORE_PGOOD

BOM options provided by this page:

Selects appropriate resistor for the

Selects between forced continuous and

Signal aliases required by this page:

- =PPVCORE_PWRON_I2_REG

Power aliases required by this page:

NC

- =PP2V7R5V5_PWRON_I2VCORE

Vout = 1.22V * (1 + Ra/Rb) + (Iadj * Ra)

Vout = 0.8V * (1 + (Ra / (Rb1 + Rb2)))

LTC3412

CRITICAL

TSSOP-LF

4

17

6

15

14

11

10

1

8

7

5

16

9

2

13

12

3

U2200

402

309K

MF-LF

1/16W

1%

2

1

R2204

SM-LF

1.0uH-3.48A

CRITICAL

21

L2200

SM

21

XW2200

I2VCORE_1V5

162K

1%

1/16W

402

MF-LF

2

1

R2210

1%

MF-LF

110K

402

1/16W

2

1

R2211

22pF

402

5% 50V CERM

2

1

C2210

1/16W

1%

75K

402

MF-LF

2

1

R2212

5%

1/16W

402

0

MF-LF

I2VCORE_BURST

2

1

R2209

1/16W

5%

I2VCORE_CONT

MF-LF

402

0

2

1

R2208

CERM

50V

5%

100pF

402

2

1

C2206

6.3V

20%

22uF

CERM 1206

2

1

C2201

CERM

22uF

1206

20%

6.3V

2

1

C2200

X5R

47uF

20%

6.3V

1206-1

2

1

C2216

47uF

6.3V

20%

X5R 1206-1

2

1

C2215

402

1% 1/16W MF-LF

7.5K

2

1

R2205

50V

2200pF

603

CERM

5%

2

1

C2205

CERM

50V

10%

470pF

402

2

1

C2207

1/16W MF-LF

402

4.7M

5%

2

1

R2207

CRITICAL

LT1962-ADJ

MSOP-LF

5

1

7

6

8

4

3

2

U2250

20% 10V

1uF

CERM

603

2

1

C2250

10%

0.01uF

16V

CERM

402

2

1

C2254

1% 1/16W MF-LF 402

15.8K

2

1

R2255

1% 1/16W MF-LF 402

68.1K

2

1

R2256

10uF

X5R

6.3V

20%

603

2

1

C2259

22

115

C

051-6929

I2 Power Supplies

SYNC_MASTER=N/A

SYNC_DATE=N/A

R2210

114S0446

1

I2VCORE_1V8

RES,232K,1%,MF-LF,0402

114S0442

R2210

1

I2VCORE_1V7

RES,210K,1%,MF-LF,0402

RES,185K,1%,MF-LF,0402

114S0437

1

R2210

I2VCORE_1V6

=PPVCORE_PWRON_I2_REG

VOLTAGE=0V MIN_LINE_WIDTH=0.75 mm MIN_NECK_WIDTH=0.25 mm

GND_I2VCORE

MIN_LINE_WIDTH=0.20 mm MIN_NECK_WIDTH=0.15 mm

I2VCORE_ITH_RC

I2VCORE_VFB

MIN_LINE_WIDTH=0.20 mm MIN_NECK_WIDTH=0.15 mm

=PPVIN_PWRON_I2PLLVDD

=PP1V5_PWRON_I2PLL_LDO

MIN_NECK_WIDTH=0.15 mm

MIN_LINE_WIDTH=0.20 mm

I2VCORE_RUNSS

MIN_NECK_WIDTH=0.15 mm

I2VCORE_ITH

MIN_LINE_WIDTH=0.20 mm

I2VCORE_RT

MIN_NECK_WIDTH=0.15 mm

MIN_LINE_WIDTH=0.20 mm

=I2VCORE_PGOOD

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.75 mm

I2VCORE_SW

I2PLLVDD_BYP

I2PLLVDD_ADJ

I2VCORE_MODE

MIN_NECK_WIDTH=0.15 mm

MIN_LINE_WIDTH=0.20 mm

I2VCORE_MODE_VDIV

=PP2V7R5V5_PWRON_I2VCORE

10

26

10

GND

VCC

PRE

Q

CLK

D CLR

Q*

GND

VCC

PRE

Q

CLK

D CLR

Q*

GND

VCC

PRE

Q

CLK

D CLR

Q*

IN

OUT

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

0001

1110

1010

0010

1100

0100

1000

MaxBus Feedback Clock Network

NET_TYPE

PHYSICAL

ELECTRICAL_CONSTRAINT_SET

SPACING

DIFFERENTIAL_PAIR

I2 Configuration Straps

199.68MHz CPU / 399.36MHz DDR

194.13MHz CPU / 388.26MHz DDR

188.59MHz CPU / 377.18MHz DDR

183.04MHz CPU / 366.08MHz DDR

177.49MHz CPU / 354.98MHz DDR

171.95MHz CPU / 342.90MHz DDR

166.40MHz CPU / 332.80MHz DDR

149.76MHz CPU / 299.52MHz DDR

133.12MHz CPU / 266.24MHz DDR

Description

0110

0000

Tied

See Table Below

Description

1394b Support (Beta Mode)

1394a Support (Legacy Mode)

50-Ohm MaxBus Drivers

33-Ohm MaxBus Drivers

Tied

HIGH

LOW

HIGH

MAXBUS_DATA<44:41>

MAXBUS_DATA<54>

MAXBUS_DATA<62>

Signal

Keep shortKeep short

AGP Feedback Clock Ladder

PCI Feedback Clock Ladder

NC NC

MAXBUS_D41_PU

402

10K

MF-LF

5% 1/16W

2

1

R2310

I2_MAXBUS_50OHM

MF-LF

10K

402

5% 1/16W

2

1

R2303

I104

I105

MAXBUS_TBEN_SYNC

BGA-YZP

74AUC1G74

CRITICAL

A2

C1

D2

B2

D1

B1

C2

A1

U2390

MAXBUS_TBEN_SYNC CRITICAL

74AUC1G74

BGA-YZP

A2

C1

D2

B2

D1

B1

C2

A1

U2391

MAXBUS_TBEN_SYNC

74AUC1G74

BGA-YZP

CRITICAL

A2

C1

D2

B2

D1

B1

C2

A1

U2392

MAXBUS_D44_PD

5%

402

10K

1/16W MF-LF

2

1

R2305

MAXBUS_TBEN_SYNC

402

CERM

10V

20%

0.1uF

2

1

C2390

MAXBUS_TBEN_SYNC

0.1uF

20% 10V CERM 402

2

1

C2391

MAXBUS_TBEN_SYNC

402

CERM

10V

20%

0.1uF

2

1

C2392

MAXBUS_TBEN_SYNC

402

MF-LF

1/16W

5%

0

21

R2392

I119

I2_FW_BETA

402

10K

MF-LF

5%

1/16W

2

1

R2300

I120

I2_FW_LEGACY

1/16W

5%

MF-LF

10K

402

2

1

R2301

MAXBUS_D42_PU

402

1/16W

5%

MF-LF

10K

2

1

R2308

MAXBUS_D41_PD

1/16W

5%

402

MF-LF

10K

2

1

R2311

0

5%

MF-LF

402

1/16W

I2_AGP_FBCLK_MATCHED

21

R2365

1/16W

0

5%

402

MF-LF

I2_AGP_FBCLK_MATCHED

21

R2367

5% 1/16W MF-LF

0

402

I2_AGP_FBCLK_SHORTEST

2

1

R2360

MAXBUS_D42_PD

1/16W

5%

402

MF-LF

10K

2

1

R2309

0

5% 1/16W MF-LF

402

I2_PCI_FBCLK_MATCHED

21

R2385

0

1/16W

5%

402

MF-LF

I2_PCI_FBCLK_MATCHED

21

R2387

I2_PCI_FBCLK_SHORTEST

402

0

MF-LF

1/16W

5%

2

1

R2380

MAXBUS_D43_PU

402

1/16W

5%

MF-LF

10K

2

1

R2306

I2_MAXBUS_FBCLK_SHORTEST

5% 1/16W MF-LF

402

0

21

R2340

MAXBUS_D44_PU

1/16W

402

10K

MF-LF

5%

2

1

R2304

0

402

MF-LF

1/16W

5%

I2_MAXBUS_FBCLK_MATCHED

2

1

R2350

5% 1/16W MF-LF 402

0

I2_MAXBUS_FBCLK_MATCHED

2

1

R2352

32

43

59

MAXBUS_D43_PD

10K

MF-LF 402

5% 1/16W

2

1

R2307

43

59

32

I2_MAXBUS_33OHM

10K

MF-LF 402

5% 1/16W

2

1

R2302

051-6929

C

115

23

I2 Supplemental

SYNC_MASTER=N/A

SYNC_DATE=N/A

MAXBUS_D44_PD,MAXBUS_D43_PU,MAXBUS_D42_PU,MAXBUS_D41_PD

I2_MAXBUS_189MHZ

I2_MAXBUS_200MHZ

MAXBUS_D44_PD,MAXBUS_D43_PD,MAXBUS_D42_PD,MAXBUS_D41_PU

MAXBUS_D44_PD,MAXBUS_D43_PD,MAXBUS_D42_PD,MAXBUS_D41_PD

I2_MAXBUS_133MHZ

I2_MAXBUS_150MHZ

MAXBUS_D44_PU,MAXBUS_D43_PD,MAXBUS_D42_PD,MAXBUS_D41_PD

I2_MAXBUS_177MHZ

MAXBUS_D44_PD,MAXBUS_D43_PD,MAXBUS_D42_PU,MAXBUS_D41_PD

I2_MAXBUS_194MHZ

MAXBUS_D44_PU,MAXBUS_D43_PU,MAXBUS_D42_PU,MAXBUS_D41_PD

I2_MAXBUS_172MHZ

MAXBUS_D44_PU,MAXBUS_D43_PU,MAXBUS_D42_PD,MAXBUS_D41_PD

I2_MAXBUS_166MHZ

MAXBUS_D44_PD,MAXBUS_D43_PU,MAXBUS_D42_PD,MAXBUS_D41_PD

I2_MAXBUS_183MHZ

MAXBUS_D44_PU,MAXBUS_D43_PD,MAXBUS_D42_PU,MAXBUS_D41_PD

MAXBUS_DATA<62>

MAXBUS_DATA<44>

=SYSCLK_TBEN_SYNC

=CLK33M_TBEN_SYNC

CLOCKCLOCK CLOCKCLOCK

=SYSCLK_TBEN_SYNC

I2_PCI_FBCLK_MATCHED

I2_FBCLKI2_FBCLK

I2_PCI_FBCLK_IN

I2_FBCLKI2_FBCLK

MAXBUS_TBEN

MAXBUS_TBEN_SYNC

=PP1V8_RUN_TBEN_SYNC

TBEN_SYNC_CLR_L

TBEN_SYNC_F1 TBEN_SYNC_F2

=I2_PCI_FBCLK_IN

MAKE_BASE=TRUE

I2_PCI_FBCLK_IN

I2_PCI_FBCLK_OUT

I2_PCI_FBCLK_MATCHED

=I2_AGP_FBCLK_IN

MAKE_BASE=TRUE

I2_AGP_FBCLK_IN

I2_AGP_FBCLK_OUT

I2_AGP_FBCLK_MATCHED

I2_AGP_FBCLK_IN

I2_FBCLK I2_FBCLK I2_FBCLK I2_FBCLK

I2_AGP_FBCLK_MATCHED

I2_FBCLKI2_FBCLK

I2_MAXBUS_FBCLK_IN

I2_FBCLKI2_FBCLK

I2_MAXBUS_FBCLK_MATCHED

=I2_MAXBUS_FBCLK_IN

I2_MAXBUS_FBCLK_IN

MAKE_BASE=TRUE

I2_MAXBUS_FBCLK_OUT

MAXBUS_DATA<54>

MAXBUS_DATA<43>

MAXBUS_DATA<41>

MAXBUS_DATA<42>

=PP1V5R1V8_MAXBUS

I2_MAXBUS_FBCLK_MATCHED

34

33

32

21

32

9

11

21

33

10

21

9

10

21

G

D

S

G

D

S

G

D

S

G

D

S

GPIO_16_H - See Ethernet Sym

EXT_05_H - See Ethernet Sym

GPIO INTERFACE

TEST/JTAG

(4 OF 14)

MISCELLANEOUS

I2S 0

I2S 1

I2C

POWER MGMT/CLOCK

SCCB/VIA

SCCA

REF_CLK_IN

REF_CLK_OUT

PWR_SPDREQ_L

PWR_STPXTL_L

REF_PURESET_L

PWR_STPCPU_L

JTG_TRSTN_L

JTG_TMS_H JTG_TCK_H

JTG_TDI_H

TST_PLLEN_H

TST_TEI_H

SCC_TRXCB_H

SCC_GPIOB_L

SCC_RXDB_H

SCC_RXDA_H

PWR_SPDACK_L

PWR_INTRWD_H

PWR_PCI_PME_L

JTG_TDO_H

SCC_RTSB_L

SCC_TXDB_L

SCC_TXDA_L

EXT_00_H EXT_01_H EXT_02_H

EXT_08_H EXT_09_H

EXT_11_H

EXT_15_H

EXT_14_H

GPIO_EXT_01_H

GPIO_EXT_03_H

GPIO_EXT_02_H

GPIO_05_H

GPIO_04_H

GPIO_06_H

GPIO_11_H

GPIO_09_H

IIC_CLK_0_H

IIC_D_0_H

IIC_CLK_2_H

IIC_D_2_H

AUD_DTO_A_H AUD_CLKOUT_A_H AUD_BITCLK_A_H

AUD_SYNC_A_H

MOD_DTO_B_H MOD_CLKOUT_B_H MOD_BITCLK_B_H

MOD_SYNC_B_H

AUD_DTI_A_H

MOD_DTI_B_H

GPIO_15_H

GPIO_12_H

EXT_12_H

PWR_PENDINT_H

GPIO_EXT_00_H

EXT_16_H

EXT_13_H

EXT_10_H

EXT_03_H EXT_04_H

EXT_07_H

EXT_06_H

G

D

S

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

GPIO_15

GPIO_12

Pull-up/down to be provided by audio page. (*) - See above

Internal pull-up to 3.3V PWRON

Pull-up/down to be provided by audio page.

GPIO_16 0x0_007A N/A No

Pull-up/down to be provided by audio page.

GPIO Pull-ups / Pull-downs

Pull-up/down to be provided by audio page. (*) - See above

Pull-up/down to be provided by audio page.

Internal pull-up to 3.3V PWRON

EXT_12

Internal pull-up to 3.3V PWRON

EXT_09

EXT_00 EXT_01

EXT_05 0x0_005D 51 (0x33) No EXT_06 0x0_005E 52 (0x34) No EXT_07 0x0_005F 53 (0x35) No EXT_08 0x0_0060 54 (0x36) Yes EXT_09 0x0_0061 55 (0x37) Yes

(Int PU)

(Int PU - rev 1)

(Int PU)

(NONE)

Use for I2 revisions > 1.0

(Slave)

(Master)

Signal Direction

Pin Direction

Crystal load capacitance is 16pF

Put crystal circuit close to I2

GPIO_04 0x0_006E N/A No

GPIO_15 0x0_0079 N/A No

EXT_02 0x0_005A 48 (0x30) No

EXT_10 0x0_0062 56 (0x38) No

EXT_04 0x0_005C 50 (0x32) No

EXT_03 0x0_005B 49 (0x31) No

EXT_01 0x0_0059 47 (0x2F) Yes

Pin Address MPIC Int Int PU? Alt Func

EXT_05

EXT_04

EXT_03

EXT_02

EXT_06 EXT_07

EXT_08

EXT_10 EXT_11

EXT_13

GPIO_EXT_01

Internal pull-up to 3.3V PWRON

(I2_EXT_13)

10K Pull-up to Enet OVdd on I2 Enet page. 10K Pull-up to 3.3V on I2 PCI page.

EXT_16 0x0_0068 62 (0x3F) Yes

EXT_00 0x0_0058 46 (0x2E) Yes PCI_REQ_2_L (When PCI1_Slot2En = 10)

EXT_13 0x0_0065 59 (0x3B) No PCI_GNT_2_L (When PCI1_Slot2En = 11)

GPIO_01 0x0_006B 15 (0x0F) No SPIREQ (When SPISReqEn = 1)

10K Pull-up to 3.3V on I2 PCI page.

Pull-up/down to be provided by audio page.

EXT_14

EXT_15 EXT_16

GPIO_EXT_00

GPIO_06

GPIO_05

GPIO_09

GPIO_16

(Int PU - rev 1)

ELECTRICAL_CONSTRAINT_SET

(I2_XTAL)

NET_TYPE

SPACING

DIFFERENTIAL_PAIR

Page Notes

(I2_XTAL)

PHYSICAL

Pull-up/down to be provided by design.

GPIO_04

GPIO_EXT_03

GPIO_EXT_02

GPIO_11

(Int PU)

Power aliases required by this page:

- =PP3V3_PWRON_I2_GPIO

Internal pull-up to 3.3V PWRON 10K Pull-up to 3.3V on I2 AGP page.

Internal pull-up to 3.3V PWRON

BOM options provided by this page:

Signal aliases required by this page:

- =PP3V3_I2_PCISLOTEGPIOS (PWRON or PCI) Should be same as =PP3V3_PCI if slot E

EXT_12 0x0_0064 58 (0x3A) Yes

EXT_15 0x0_0067 61 (0x3D) No

GPIO_00 0x0_006A 14 (0x0E) No

GPIO_03 0x0_006D 17 (0x11) Yes

Use MAKE_BASE to force net name

Alternate GPIO Functions

(*) - Rev 1.0: Missing internal pull-up to 3.3V PWRON

Pull-up/down to be provided by audio page.

(I2_EXT_14)

(*) - Rev 1.0: Missing internal pull-up to 3.3V PWRON

(*) - Rev 1.0: Internal pull-up to 3.3V PWRON

(I2_EXT_08)

- I2_REV1_NOT

is used, or else =PP3V3_PWRON_I2_GPIO.

GPIO_06 0x0_0070 N/A No GPIO_09 0x0_0073 N/A No GPIO_11 0x0_0075 N/A Yes GPIO_12 0x0_0076 N/A Yes

GPIO_05 0x0_006F N/A No

GPIO_02 0x0_006C 16 (0x10) Yes PCI_GNT_2_L (When PCI1_Slot2En = 10)

EXT_14 0x0_0066 60 (0x3C) No PCI_REQ_2_L (When PCI1_Slot2En = 11)

EXT_11 0x0_0063 57 (0x39) Yes

(Int PU - rev 1)

(Master)

Audio Mute Sequencing

Prevents mute glitch from reaching audio circuit

402

100K

5% 1/16W MF-LF

2

1

R2470

SOT-363

2N7002DW-X-F

1

2

6

Q2470

402

5% 1/16W MF-LF

100K

2

1

R2472

402

MF-LF

1/16W

5%

10K

2

1

R2481

SOT-363

2N7002DW-X-F

4

5

3

Q2480

402

100K

5% 1/16W MF-LF

2

1

R2480

SOT-363

2N7002DW-X-F

1

2

6

Q2480

100K

402

5% 1/16W MF-LF

2

1

R2482

2N7002DW-X-F

SOT-363

1

2

6

Q2481

BGA

I2

OMIT

AL6 AL5

AL2

AE5

AL1

AL3

AG5

AL4AM1

AK3

AC12

AC13

AH7 AH6

AH5 AK5

AK6

AK7

AL7

G6

G5J5 J6

J7

AP1

AN2

AN4AN6

AN3

F1

J3

F4

J1

AH3

AH4

AJ1

AK2

AG6

AG7

G2

AG8

G1

G3

M1

G4

H1

AE4

AF1

AG2

AG3

AG1

AK1

AG4

AN33

AR33

J2

AH2

AT19

AK4

AH1

D2

C1E1

F2

F3

U2100

5%

402

CERM

22pF

50V

2

1

C2410

0

MF-LF

1/16W

5%

402

2

1

R2411

8X4.5MM-SM1

CRITICAL

18.432M

21

Y2410

50V

22pF

CERM

402

5%

2

1

C2411

NO STUFF

10M

402

MF-LF

1/16W

5%

21

R2410

10K

402

MF-LF

1/16W

5%

2

1

R2400

10K

402

MF-LF

1/16W

5%

2

1

R2401

5%

1/16W

10K

SM-LF

72

RP2450

5%

1/16W

10K

SM-LF

81

RP2450

5% 1/16W MF-LF

402

10K

2

1

R2490

10K

1/16W

5%

SM-LF

63

RP2450

5% 1/16W MF-LF

10K

402

I2_REV1_NOT

21

R2455

10K

1/16W

5%

SM-LF

54

RP2450

10K

NO STUFF

402

MF-LF

1/16W

5%

21

R2451

10K

5% 1/16W MF-LF

402

21

R2452

10K

402

MF-LF

NO STUFF

5%

1/16W

21

R2460

10K

NO STUFF

402

5% 1/16W MF-LF

21

R2461

10K

402

MF-LF

1/16W

5%

21

R2462

10K

5% 1/16W MF-LF

402

21

R2463

10K

1/16W

402

MF-LF

5%

21

R2464

402

MF-LF

1/16W

5%

10K

2

1

R2471

SOT-363

2N7002DW-X-F

4

5

3

Q2470

SYNC_MASTER=N/A

24

115

C

051-6929

I2 Miscellaneous

SYNC_DATE=N/A

MUTE_CONTROL

SYS_WARM_RESET_L

I2_AUDIO_SPKR_MUTE_L

SYS_WARM_RESET_L

AUDIO_SPKR_MUTE_L

AUDIO_SPKR_MUTE

I2S1_SYNC_R

SCCA_TXD_L

AGP_INT_L

I2S0_SYNC_R

VIA_REQ_L

AUDIO_LI_DET_L

=PP3V3_AUDIO_MUTESEQ

AUDIO_LO_MUTE_L

MUTE_CONTROL

I2_AUDIO_LO_MUTE_L

I2S0_SB_TO_DEV_DTO_R

I2SI2S

I2S0_DTO

I2S0_MCLK_R

I2SI2S

I2S0_MCLK

I2S

I2S0_BITCLK_R

I2S

I2S0_BITCLK

XTAL XTAL

I2_CLK18M_XOUT

I2_GPIO_11

I2S1_MCLK_R

PMU_INT_L

PMU_SB_NMI_L

PCI_SLOTE_GNT_L

PCI_SLOTE_REQ_L

FW_POWERDOWN

I2_EXT_13 I2_EXT_14 AUDIO_LO_DET_L AUDIO_GPIO_11

I2_GPIO_EXT_02 MODEM_RESET_L

I2_AUDIO_LO_MUTE_L I2_AUDIO_SPKR_MUTE_L

FW_POWERDOWN

MMM_SIRQ_L

AUDIO_EXT_MCLK_SEL

PCI_SLOTE_GNT_L

I2S0_DEV_TO_SB_DTI

PCI_SLOTE_REQ_L

PCI_SLOTE_INT_L

I2S0_MCLK_R

I2S0_SB_TO_DEV_DTO_R

=I2C_I2_SB_SDA

=I2C_I2_NB_SDA

=I2C_I2_NB_SCL

=I2C_I2_SB_SCL

AUDIO_I2S_DTIB_SEL

=SPI_I2_REQ

AUDIO_CODEC_RESET_L

=SPI_I2_MOSI

I2S1_BITCLK_R

I2S1_SB_TO_DEV_DTO_R

PCI_SLOTD_INT_L

MODEM_RING2SYS_L

I2S1_DEV_TO_SB_DTI

I2SI2S

I2S1_DTI

I2S1_SB_TO_DEV_DTO_R

I2S I2S

I2S1_DTO

I2S1_MCLK_R

I2S I2S

I2S1_MCLK

I2S1_BITCLK_R

I2S I2S

I2S1_BITCLK

I2S0_SYNC_R

I2SI2S

I2S0_SYNC

I2S0_DEV_TO_SB_DTI

I2S I2S

I2S0_DTI

I2_GPIO_11

AUDIO_SPDIFRX_RESET_L

I2_EXT_08

I2S I2S

I2S1_SYNC_R

I2S1_SYNC

I2_CLK18M_XOUT_R

XTALXTAL

I2_XTAL

XTAL XTAL

I2_CLK18M_XIN

=PP3V3_I2_PCISLOTEGPIOS

=SPI_I2_REQ

=SPI_I2_MISO

=PP3V3_PWRON_I2_MISC

=SPI_I2_CLK

I2_CLK18M_XOUT

I2_GPIO_EXT_02

PCI_SLOTA_INT_L

AUDIO_LI_OPTICAL_PLUG_L

AUDIO_LO_OPTICAL_PLUG_L

TP_I2_PENDINT

I2S1_DEV_TO_SB_DTI

I2S0_BITCLK_R

MMM_FFIRQ_L

PMU_SB_NMI_L

PMU_INT_L

VIA_SB_TO_PMU

SYS_WATCHDOG

NB_SUSPENDACK_L

SCCA_RXD

VIA_PMU_TO_SB VIA_ACK_L VIA_CLK

I2_TST_PLLEN

=JTAG_I2_TDI

=JTAG_I2_TCK

=JTAG_I2_TMS

=JTAG_I2_TRST_L

=I2_STOPCPU_L

=I2_STOPXTAL_L

NB_SUSPENDREQ_L

I2_CLK18M_XOUT_R I2_CLK18M_XIN

I2_TST_TEI

MMM_SIRQ_L

PCI_SLOTE_INT_L

MODEM_RING2SYS_L

MMM_FFIRQ_L

SYS_PME_L

=JTAG_I2_TDO

AUDIO_LO_MUTE

=PP3V3_PWRON_I2_MISC

62

74

30

74

30

25

74

22

24

44

22

74

22

74

22

25

22

74

22

25

74

22

74

22

74

22

59

25

30

22

74

22

59

74

30

22

25

24

25

22

25

62

22

7

6

7

43

6

25

7

10

7

22

6

22

6

22

11

22

7

11

30

22

7

11

7

11

6

8

7

11

7

6

11

22

6

7

22

7

6

22

10

11

10

22

11

7

22

6

22

25

7

25

9

11

25

22

11

22

25

9

10

CLKIN

CLKOUT

1Y3

GND

1Y2

1Y1

1Y0

VDD

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(NONE)

BOM options provided by this page:

- I2_REV1_NOT

is used, or else =PP3V3_PWRON_I2_GPIO.

Signal aliases required by this page:

Use for I2 revisions > 1.0

- =PP3V3_I2_PCISLOTEGPIOS (PWRON or PCI) Should be same as =PP3V3_PCI if slot E

Power aliases required by this page:

- =PP3V3_PWRON_I2_GPIO

Page Notes

DIFFERENTIAL_PAIR

PHYSICAL

NET_TYPE

SPACING

ELECTRICAL_CONSTRAINT_SET

CRITICAL

CDCVF2505

SOIC

6

4

8

1

7

5

2

3

U2500

6.3V

10%

1uF

402

CERM

2

1

C2501

0.001uF

50V

20%

CERM

402

NO STUFF

2

1

C2502

10V

20%

0.1uF

CERM

402

2

1

C2500

I72

I73 I74

I75 I76

PCI Clock Buffer

25

115

C

051-6929

SYNC_MASTER=N/A

SYNC_DATE=N/A

=PP3V3_PCI_ZDB

=PCI_CLK33M_ZDB_IN

PCI_ZDBOUT3

=PCI_CLK33M_ZDBOUT_R<3>

CLOCK CLOCK

PCI_ZDBOUT2

=PCI_CLK33M_ZDBOUT_R<2>

CLOCKCLOCK

PCI_ZDBOUT1

=PCI_CLK33M_ZDBOUT_R<1>

CLOCKCLOCK

=PCI_CLK33M_ZDB_IN

CLOCK CLOCK

PCI_ZDBOUT0

=PCI_CLK33M_ZDBOUT_R<0>

CLOCKCLOCK

PCI_CLK_DELAY_ADJ

=PCI_CLK33M_ZDBOUT_R<0> =PCI_CLK33M_ZDBOUT_R<1> =PCI_CLK33M_ZDBOUT_R<2> =PCI_CLK33M_ZDBOUT_R<3>

23

10

11

G

D

S

G

D

S

G

D

S

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(WAS COMM_TRXC)

(WAS COMM_GPIO_L)

(WAS PMU_BOOT_CE)

NC

SERIAL DEBUG INTERFACE

PMU RESET CIRCUIT

PLACE "SYS RESET" IN SILK NEAR RESISTOR

PLACE "PMU RESET" IN SILK NEAR RESISTOR

DEBUGGING AIDS

PLACE ON TOP SIDE NEAR FRONT EDGE OF BOARD

PLACE "POWER BTN" IN SILK NEAR RESISTOR

CHARGE LED

SLEEP LED

402

MF-LF

1/16W

5%

100

2

1

R2600

OMIT

603

MF-LF

1/10W

5%

470K

21

R2691

OMIT

470K

5% 1/10W MF-LF

603

21

R2692

SOT-363

2N7002DW-X-F

1

2

6

Q2680

402

MF-LF

1/16W

5%

100K

2

1

R2680

SOT-363

BAS16TW-X-F

6 1

DP2680

SOT23-LF

2N3906

2

3

1

Q2600

BAS16TW-X-F

SOT-363

5 2

DP2680

2N7002DW-X-F

SOT-363

4

5

3

Q2680

2.2K

5% 1/16W MF-LF

402

2

1

R2601

402

MF-LF

1/16W

5%

470K

2

1

R2610

402

MF-LF

1/16W

5%

4.7K

R2602

SOT23-LF

2N7002

2

1

3

Q2601

M-ST-SM

QT500166-L020

DEVELOPMENT

CRITICAL

9

87

65

43

2

1615

1413

1211

10

1

J2690

402

MF-LF

1/16W

5%

10K

DEVELOPMENT

2

1

R2696

402

MF-LF

1/16W

5%

10K

DEVELOPMENT

2

1

R2695

OMIT

470K

5% 1/10W MF-LF

603

21

R2690

SYNC_DATE=N/A

SYNC_MASTER=N/A

26

115

C

051-6929

LEDs/Reset/Debug

PMU_RESET_L

PMU_CUSTOMER_RESET

SLEEP_LED_SW_L

SYS_LED

=SLEEP_LED_IOUT

=PP5V_PWRON_SLEEPLED

SLEEP_LED_L

SYS_ONEWIRE

SYS_CHARGE_LED_L

=PP3V3_ALL_PMU

SYS_AC_DET_L

PMU_RESET_L

SYS_POWER_BUTTON_L

SYS_RESET_BUTTON_L

SYS_POWER_BUTTON_L

SYS_BATT0_DET_L

SLEEP_LED_I

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm

=PP3V3_ALL_DEBUG

SCCA_TXD_L

PMU_BOOT_SCLK PMU_BOOT_CNVSS

PMU_RESET_L

PMU_BOOT_BUSY

PMU_BOOT_RXD

PMU_BOOT_TXD

PMU_BOOT_RP_L

SCCA_RXD

COMM_DTR_L

NO_TEST=TRUE

COMM_RTS_L

NO_TEST=TRUE

57

36

25

30

25

74

24

25

36

25

22

25

22

24

25

11

10

25

7

10

12

24

25

24

12

10

7

25

24

25

7

Apple A1138 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual