Apple A1138 Schematic

TABLE_TABLEOFCONTENTS_ITEM

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

ANGLES

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

DATE

APPD

ENG

DATE

APPD

CK

ECN

ZONE

REV

DO NOT SCALE DRAWING

X.XXX

X.XX

XX

DIMENSIONS ARE IN MILLIMETERS

THIRD ANGLE PROJECTION

D

SIZE

APPLICABLE

NOTED AS

MATERIAL/FINISH

NONE

SCALE

DESIGNER

MFG APPD

DESIGN CK

RELEASE

QA APPD

ENG APPD

DRAFTER

METRIC

OF

SHT

DRAWING NUMBER

TITLE

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

Apple Computer Inc.

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

DESCRIPTION OF CHANGE

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

PDF CSAPDF CSA

N/A

Revision History

N/A

5 5

N/A

Sudden Motion Sensor

N/A

29 32

N/A

ALS Support

N/A

28 31

N/A

Fan Controller

N/A

27 30

N/A

Power Sequencing

N/A

26 29

N/A

Power Management Unit (PMU05)

N/A

25 27

N/A

LEDs/Reset/Debug

N/A

24 26

N/A

PCI Clock Buffer

N/A

23 25

N/A

I2 Miscellaneous

N/A

22 24

N/A

I2 Supplemental

N/A

21 23

N/A

I2 Power Supplies

N/A

20 22

N/A

Spacing & Physical Constraints 2

N/A

76 111

N/A

Vesta Power & Misc

N/A

18 19

N/A

2.5V Supply

N/A

17 17

N/A

1.8V/1.5V Supplies

N/A

16 16

N/A

5V/3.3V Supplies

N/A

15 15

N/A

12.8V PBUS/PMU Supplies

N/A

14 14

N/A

Battery Charger

N/A

13 13

N/A

Power Inputs

N/A

12 12

N/A

Signal Synonyms

N/A

11 11

N/A

I2C Connections

N/A

8 8

N/A

Q16C Internal I/O II

N/A

31 34

N/A

Q16C Internal I/O I

N/A

30 33

Q16C_BST_VRAM_H

[EEE:TMK]

1

826-4393

LBL,P/N LABEL,PCB,28MM X 6MM

Q16C_BST_VRAM_S

[EEE:SYU]

LBL,P/N LABEL,PCB,28MM X 6MM

826-4393

1

820-1875

PCBF,MLB,Q16C

PCB1 CRITICAL

051-6929

1

SCHEM,MARIAS-STD,Q16C

SCH1

SCHEM,MARIAS-STD,Q16C

115

1

051-6929

C

?

09/09/05

399027

PRODUCTION RELEASED

C

N/A

Power Block Diagram

N/A

4 4

N/A

Q16C Pin Swaps

N/A

6 6

N/A

JTAG Connections

N/A

9 9

N/A

Power Synonyms

N/A

10 10

N/A

I2 Power

N/A

19 21

N/A

DDR2 SO-DIMM Slot A

N/A

40 50

N/A

Memory Series Termination

N/A

39 48

N/A

I2 Memory Interface

N/A

38 47

N/A

CPU AVDD Supply

N/A

37 46

N/A

CPU VCore Supply

N/A

36 39

MULLET

A8 Power (CPU0)

08/02/2005

35 38

MULLET

A8 Configuration Straps

08/02/2005

34 37

MULLET

A8 MaxBus (CPU0)

08/02/2005

33 36

N/A

I2 Processor Interface

N/A

32 35

N/A

Functional Test Points

N/A

7 7

N/A

BootROM

N/A

58 71

N/A

External Display Conns

N/A

57 70

N/A

Internal Display Conns

N/A

56 69

N/A

Upper TMDS Transmitter

N/A

55 68

N/A

Lower TMDS Transmitter

N/A

54 67

N/A

GPU (M11) DVI/DAC Outputs

N/A

53 66

N/A

GPU (M11) Clocks/Misc

N/A

52 65

N/A

GPU (M11) GPIOs/Straps

N/A

51 64

N/A

GPU Frame Buffer B

N/A

50 63

N/A

GPU Frame Buffer A

N/A

49 62

N/A

GPU (M11) Frame Buffer I/F

N/A

48 61

N/A

GPU (M11) I/O Power

N/A

47 60

N/A

GPU (M11) Core Power

N/A

46 59

N/A

GPU VCore Supply

N/A

45 58

N/A

GPU (M11) AGP Interface

N/A

44 57

N/A

I2 AGP Interface

N/A

43 56

N/A

M11 Frame Buffer Constraints

N/A

42 55

CONTENTS

DATE

SYNC MASTER

N/A

Table Of Contents

N/A

1 1

CONTENTS

DATE

SYNC MASTER

N/A

DDR2 SO-DIMM Slot B

N/A

41 52

N/A

I2 PCI Interface

N/A

59 72

N/A

System Block Diagram

N/A

3 3

N/A

Board Information

N/A

2 2

Cross Reference Page

80 115

Cross Reference Page

79 114

Cross Reference Page

78 113

Cross Reference Page

77 112

N/A

Spacing & Physical Constraints

N/A

75 110

N/A

Audio Board Connector

N/A

74 100

N/A

NEC USB2 Interface

N/A

73 93

N/A

I2 USB Interface

N/A

72 92

N/A

FireWire Series Term

N/A

71 91

N/A

FireWire Ports

N/A

70 90

N/A

Vesta FireWire PHY

N/A

69 89

N/A

I2 FireWire Interface

N/A

68 88

N/A

Ethernet Connector

N/A

67 86

N/A

Vesta Ethernet PHY

N/A

66 85

N/A

I2 Ethernet Interface

N/A

65 84

N/A

HDD/ODD Connectors

N/A

64 82

N/A

I2 UATA Interface

N/A

63 81

N/A

NEC USB2

N/A

62 75

N/A

Cardbus

N/A

61 74

N/A

Q85 Airport/BT Connector

N/A

60 73

TABLE_SPACING_RULE

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

TABLE_BOARD_INFO

TABLE_SPACING_RULE

TABLE_PHYSICAL_RULE

TABLE_SPACING_ASSIGNMENT

TABLE_SPACING_RULE

TABLE_PHYSICAL_RULE

TABLE_SPACING_ASSIGNMENT

TABLE_PHYSICAL_RULE

TABLE_SPACING_RULE

TABLE_PHYSICAL_RULE

TABLE_SPACING_RULE

TABLE_PHYSICAL_RULE

TABLE_SPACING_RULE

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_SPACING_RULE

TABLE_BOMGROUP_ITEM

TABLE_PHYSICAL_RULE

TABLE_SPACING_RULE

TABLE_PHYSICAL_RULE

TABLE_SPACING_RULE

TABLE_PHYSICAL_RULE

TABLE_SPACING_RULE

TABLE_PHYSICAL_RULE

TABLE_SPACING_RULE

TABLE_PHYSICAL_RULE

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

TABLE_PHYSICAL_RULE

TABLE_SPACING_RULE

TABLE_PHYSICAL_RULE

TABLE_SPACING_ASSIGNMENT

TABLE_SPACING_RULE

TABLE_SPACING_ASSIGNMENT

TABLE_SPACING_RULE

TABLE_PHYSICAL_RULE

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_PHYSICAL_RULE

TABLE_SPACING_ASSIGNMENT

TABLE_PHYSICAL_RULE

Design-Specific Rules

reduce DRCs caused by fan-out.

"BGA_P2MM" rule ensures these critical

Portable-specific Override Rules

"1MM" area defined around BGAs to

NO_TEST Properties

12

11

10

9

8

7

6

5

PREPREG

CORE

PREPREG

CORE

PREPREG

2

1

3

PREPREG

CORE

CONVENTIONAL CONSTRUCTION WITH Pxx TH VIA

SEE BOARD FILE FOR DETAILED INFORMATION

GROUND (1/2 OZ)

SIGNAL (1/2 OZ)

GROUND (1/2 OZ)

SIGNAL (1/2 OZ)

SIGNAL (1/2 OZ + COPPER PLATING)

CUT POWER PLANE (1 OZ)

SIGNAL (1/2 OZ + COPPER PLATING)

BOARD STACK-UP AND CONSTRUCTION

Layer-specific rules for 100-ohm differential impedance

Layer-specific rules for 110-ohm differential impedance

Layer-specific rules for 60-ohm single-ended impedance

Layer-specific rules for 50-ohm single-ended impedance

to any other signals.

LWR RT GPU

LWR CPU

LEFT CPU

UPPER RT GPU

DVI

1394

CHASSIS MOUNTS

BATT. CHGR

BOARD HOLES

CHASSIS GND CONNECTIONS

MECH. HOLES

HEATSINK MOUNTS

signals do not fan-out routed next

4

PREPREG

Layer-specific rules for 90-ohm differential impedance

INVERTER

BOM OPTIONS

Module Components

IS

OG-503040

SHLD-SM-LF

3

2

1

SH0200

HOLE-VIA-P5RP25

1

ZT0200

HOLE-VIA-P5RP25

1

ZT0201

HOLE-VIA-P5RP25

1

ZT0203

HOLE-VIA-P5RP25

1

ZT0202

HOLE-VIA-P5RP25

1

ZT0210

HOLE-VIA-P5RP25

1

ZT0211

HOLE-VIA-P5RP25

1

ZT0212

HOLE-VIA-P5RP25

1

ZT0221

HOLE-VIA-P5RP25

1

ZT0222

HOLE-VIA-P5RP25

1

ZT0223

GND_CHASSIS_UPPER_DVI

GND_CHASSIS_FW_LOWER_DVI

GND_CHASSIS_LCD

GND_CHASSIS_BATT_CHGR

GND_CHASSIS_INVERTER

I244

I245 I246

I247 I248

I249

I250

I251 I252

I253 I254

I255

I256

I257 I258

I259 I260

I261

I262

I263

I264 I265

I266

I267 I268

I269 I270

I271

I272 I273

I274

I275 I276

I277

110_OHM_DIFF

2.5 MM 1.0 MM

TOP,BOTTOM

2.5 MM

0.330 MM

337S3077

CPU_A8

1

CRITICAL

U3600

IC,A8,xxxGHZ

A7PM_1P5_LGA

IC,A7PM,R1.5,1.5GHZ,LGA,1.28V,23W,85C

CRITICAL

1

U3600

337S3163

U2100

IC,ASIC,I2,REV1.2,NB/SB,974 BGA

343S0383 CRITICAL

1

U2700

PMU_PROG

CRITICAL

1

341S1772

IC,PMU05,V1,QFP

2.5 MM 1.0 MM

90_OHM_DIFF

TOP,BOTTOM

2.5 MM

0.200 MM

Y

5 MM

0.1 MM

90_OHM_DIFF

*

0.125 MM

2.5 MM 1.0 MM2.5 MM

100_OHM_DIFF

*

0.200 MM

50_OHM_SE

1.25 MM

0.100 MM0.100 MM

* Y

USB2_NEC,USB1P1_NEC,TPAD_SEQ_PMU

gUSB

0.1 MM

*

DEFAULT

2.5 MM

10.0 MM 15.0 MM0.15 MM

U8500

343S0356343S0388

v1.4 is alt to v1.3

100_OHM_DIFF

Y

5 MM

0.1 MM

TOP,BOTTOM

0.092 MM

0.100 MM 0.100 mm

1.25 MM

Y

DEFAULT

*

1MM

*

AGP_STB

BGA_P2MM

Y

5 MM

0.1 MM

TOP,BOTTOM

0.118 MM

90_OHM_DIFF

=60_OHM_SE

VGA

=60_OHM_SE =60_OHM_SE =60_OHM_SE

*

50_OHM_SE

*

1.0 MM2.5 MM

0.125 MM

2.5 MM

=DEFAULT

TV

=DEFAULT =DEFAULT=DEFAULT

*

0.15 MM

151

BGA_P1MM

1MM

* *

2.5 MM 1.0 MM2.5 MM

110_OHM_DIFF

*

0.300 MM

201 0.2 MMAGP

*

=60_OHM_SE =60_OHM_SE

TV

=60_OHM_SE =60_OHM_SE

*

PCBA,MLB,BESTMHZ,MARIAS,VRAM_S,Q16C

630-7016

COMMON,ALTERNATE,gQ16C,gQ16C_BST,Q16C_BST_VRAM_S,VRAM_SAMSUNG,gCommon

U2700

1

337S3135

PMU_BLANK

CRITICAL

IC,PMU05,BLANK,QFP

0.200 MM

100_OHM_DIFF

2.5 MM 1.0 MM

TOP,BOTTOM

2.5 MM

TOP,BOTTOM

0.1 MM

5 MM

Y

110_OHM_DIFF

0.080 MM

*

STANDARD =DEFAULT =DEFAULT =DEFAULT=DEFAULT

*

=DEFAULT=DEFAULT =DEFAULT=DEFAULT

VGA

0.15 MM

151

=50_OHM_SE

Y

60_OHM_SE

*

0.076 MM

=50_OHM_SE

RAM_DIFF

*

BGA_P2MM

1MM

2.5 MM 1.0 MM2.5 MM

*

0.200 MM

90_OHM_DIFF

337S3162

IC,A7PM,R1.5,1.67GHZ,LGA,1.28V,23W,85C

A7PM_1P67_LGA

CRITICAL

1

U3600

CRITICAL

4

IC,GDDR SDRAM,2MX32X4,300MHZ, LF FBGA144

333S0314

VRAM_HYNIX

U6200,U6250,U6300,U6350

CRITICAL

IC,GDDR SDRAM,2MX32X4,300MHZ, LF FBGA144

4

333S0317

VRAM_SAMSUNG

U6200,U6250,U6300,U6350

1

U8500

CRITICAL343S0356

IC,ASIC,VESTA,V1.3,LF

*

BGA_P2MM

1MM

CLOCK

0.085 MM

0.1 MM

5 MM

Y

110_OHM_DIFF

*

0.25 MM

251

AGP_STB

*

NO_TYPE,1MM

MM

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM

*

100_OHM_DIFF

0.1 MM

5 MM

Y

0.100 MM

U7100

341S1736

BOOTROM_PROG

CRITICAL

1

IC,BOOTROM,B,Q16C

BOOTROM_BLANK

335S0088

U7100

CRITICAL

BOOTROM,BLANK

1

U5700

1

CRITICAL

IC,GPU,M11P

338S0252

BGA_P2MM

0.20 MM

*20

1.25 MM

0.1 MM

12.5 MM 15.0 MM

0.10 MM 1.25 MM

0.1 MM

12.5 MM

BGA_P1MM

*10

15.0 MM

=DEFAULTSTANDARD =DEFAULT =DEFAULT=DEFAULT

*

=DEFAULT=DEFAULT

A7PM_1P67_LGA,CPU0_BUSRATIO_10.0X,CPU0_VCORE_1V28,CPU0_AVDD_1V28,Q16BST

gQ16C_BST

Q16C_PARTS,BOOTROM_PROG,PMU_PROG,MAXBUS_TBEN_SYNC

gQ16C

VESTA_PORT2_DISABLE,DVO_1V8,TMDS_DUAL,VCORE_OFFSET,VCORE_OFFSET_SW,gUSB

gCommon4

CPU_VCORE_2STATES,I2_MAXBUS_166MHZ,I2VCORE_1V5,I2VCORE_BURST,gCommon4

gCommon3

I2_REV1_NOT,I2_MAXBUS_FBCLK_MATCHED,I2_AGP_FBCLK_MATCHED,I2_PCI_FBCLK_MATCHED,gCommon3

gCommon2

MMM_ACCEL_KIONIX,GPU_PWRPLAY,GPU_SS,GPU_LVDDR_2V8,GPU_MEMIO_1V8,gCommon2

gCommon1

5V_HD_LOGIC,BACKUP_BATT,CPU_A7PM,I2_FW_BETA,I2_MAXBUS_50OHM,MAXBUS_1V8,gCommon1

gCommon

PCBA,MLB,BESTMHZ,MARIAS,VRAM_H,Q16C

630-7185

COMMON,ALTERNATE,gQ16C,gQ16C_BST,Q16C_BST_VRAM_H,VRAM_HYNIX,gCommon

Board Information

SYNC_DATE=N/A

SYNC_MASTER=N/A

051-6929

C

115

2

=GND_CHASSIS_BATTCHGR_HOLE

=GND_CHASSIS_INV_GND_CLIP

NO_TEST=TRUE

UATA_DA_R<1>

NO_TEST=TRUE

UATA_DA_R<0>

TP_NEC_SRCLK

NO_TEST=TRUE

TP_USB2_PWREN<3>

NO_TEST=TRUE

TP_USB2_PWREN<2>

NO_TEST=TRUE

TP_USB2_PWREN<0>

NO_TEST=TRUE

=GND_CHASSIS_SLEEP_LED

=GND_CHASSIS_BATTCHGR_HOLE

=GND_CHASSIS_INVERTER1 =GND_CHASSIS_INVERTER2

=GND_CHASSIS_DVI_HOLE =GND_CHASSIS_DVI2 =GND_CHASSIS_DVI4

=GND_CHASSIS_FW_HOLE =GND_CHASSIS_DVI1 =GND_CHASSIS_DVI3 =GND_CHASSIS_TV =GND_CHASSIS_ENET =GND_CHASSIS_FW_PORT1 =GND_CHASSIS_FW_PORT2 =GND_CHASSIS_FW_EMI

=GND_CHASSIS_LCD1 =GND_CHASSIS_LCD2 =GND_CHASSIS_LCD3 =GND_CHASSIS_LCD4

TP_OPTICAL_DRIVE_SCREW

TP_RT_KYBRD_SCREW

TP_LEFT_KYBRD_SCREW

=GND_CHASSIS_FW_HOLE

=GND_CHASSIS_DVI_HOLE

NO_TEST=TRUE

TMDS_CONN_CLKP

NO_TEST=TRUE

1778_ITH_RC

UATA_DD_R<0>

NO_TEST=TRUE

TP_VESTA_DNC_E9

NO_TEST=TRUE

TP_VESTA_F1000

NO_TEST=TRUE

TP_VESTA_PHYA<0> TP_VESTA_REGSEN2

NO_TEST=TRUE NO_TEST=TRUE

TP_VESTA_SPD0 USB_NEC_BT_N

NO_TEST=TRUE NO_TEST=TRUE

USB_NEC_N<1>

USB_NEC_P<1>

NO_TEST=TRUE

SI_TMDS_DP<3>

NO_TEST=TRUE

SI_TMDS_DN<2>

NO_TEST=TRUE

SI_TMDS_DN<1>

NO_TEST=TRUE

SI_TMDS_DN<4>

NO_TEST=TRUE

SI_TMDS_DN<5>

USB_NEC_N<2>

NO_TEST=TRUE NO_TEST=TRUE

USB_NEC_N<3>

SI_TMDS_CLKP

NO_TEST=TRUE

SI_TMDS_DN<0>

NO_TEST=TRUE

USB_NEC_P<0>

NO_TEST=TRUE

1778_VRNG

NO_TEST=TRUE

GPU_DVOD_R<18>

NO_TEST=TRUE

LTC3412_RUNSS

NO_TEST=TRUE

UATA_DD_R<8>

NO_TEST=TRUE

UATA_DD_R<10>

TP_NEC_SMC

NO_TEST=TRUE

TP_NEC_SMI_L

NO_TEST=TRUE

MIN_NECK_WIDTH=0.25 mm

VOLTAGE=0V

MAKE_BASE=TRUE MIN_LINE_WIDTH=0.5 mm

MAKE_BASE=TRUE VOLTAGE=0V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=0V

MAKE_BASE=TRUE

MAKE_BASE=TRUE VOLTAGE=0V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=0V

MAKE_BASE=TRUE

63

11

53

63

2

6

62

73

30

2

56

2

57

2

57

67

70

56

2

57

45

6

18

66

18

66

6

73

55

54

55

73

54

73

45

6

17

6

62

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

U2100

(x2 Channels)

64BITS

240MHZ

ATI

MEMORY CH A U6200/U6250

Connector

P.70

2 DATA PAIRS @ 400MHZ

P.58

MEMORY BUS

1.8V

64BITS

167MHZ

1.8V

MEMORY BUS

1.5V/3.3V 32BITS

M11P

P.44-53

P.49

MEMORY CH B

4 DATA PAIRS

U8500

Vesta Combo

Ethernet

FW - A

J9020

P.30

BOOT ROM

Connector

128MB

U6300/U6350

LEFT USB2

P.50

P.60

P.30

P.74

JA000J3320

10/100/1000

3.3V

P.67

Ethernet

J8600

Audio

U5700

8BIT TX 8BIT RX

P.69

FireWire

EDID (I2C)

COMPOSITE

ALS Sensors

Connector

10/100/1000

800 Mb/S

FIREWIRE

P.63

P.21

x2

P.27

U2700

P.57

125MHZ

100MHZ

UATA

P.24

CARDBUS

J7400

SMS Sensor

P.29

U3220

Connector

S-Video

(VIA SIL1178)

Connector

LCD Panel

P.43

4X AGP

P.59

32BITS

PCI

P.21

BOOTROM

1M X 8

J7300

AIRPORT

Connector

P.57

RGB

P.60

NEC USB2.0

P.62

66MHZ

AGP BUS

RIGHT USB2

Trackpad (1.1)

BlueTooth (1.1)

P.56

J6900

DDR2 MEMORY

G/MII

UNUSABLE

Connector

P.66

P.7

CPU PLL

Config

P.33-35

(MPC7448)

U3600

167MHZ

1.8V

MAXBUS

A7PM

CPU

64BIT DATA

32BIT ADDR

J5000/J5200

P.40/41

P.47

MAXBUS

P.32

ETHERNET

PORTS A-F

USB2.0

P.73

P.65

3.3V

8BIT TX/RX

P.68

I2

UATA 100

P.64

DDR2 SDRAM DIMM 1

DDR2 SDRAM DIMM 0

SO-DIMM Connector

Connector

Inverter

J6950

P.56

LVDS

J7060 J7000

TMDS

S-VIDEO

33MHZ

P.21

SCCA

VIA/PMU

P.21

x2

I2S

I2C

P.21

U7100

I2C

Circuit

Fan

Serial Debug

Connector

J2690

P.24

U3000

PHY

1394 OHCI

P.70

@ 200MHz

2 DATA PAIRS

J8200/J8250

HDD/ODD

Connectors

FW - B

J9010

Connector

SW MODEM

Connector

SLEEP

LED

DVI-I

U1250

DDC

CONN

P.25

SMBUS

3.3V

PMU

U7500

U7400

Connector

TI PCI1510

CardBus

Controller

EHCI HC

P.61

PCI BUS

33MHZ

32BITS

3.3V

33MHZ 16/32 BITS

3.3V/5V

SENSOR

P.12

Battery

Connector

BATTERY

CURRENT

J1250

& Charger

Power Supply

P.13-17

Connector

J3400

P.31

DC-In

SYNC_DATE=N/A

051-6929

C

115

3

SYNC_MASTER=N/A

System Block Diagram

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

VRAM I/O

VRAM CORE

PMU

GPU_VCORE

CPU_VCORE

INCORRECT

3S 2P 18650 CELLS

SLEEP: STOPPED

SLEEP

5V_RUN

5V_PWRON

3V3_PWRON 3V3_RUN

3V_5V_OK 2V5_PWRON

1V8_PWRON 1V8_RUN

1V5_PWRON

GPU_VCORE

CPU_VCORE

1V5_RUN

2V5_RUN

(CONTROLLED BY PMU)

14V_PBUS

POWER SEQUENCE

NO INRUSH PROTECTION

5V_PWRON

3V3_ALL

4V6_ALL

3V3_ALL

I2 CORE

+1.5V

SLEEP: RUNNING

RUN: RUNNING

SHUTDOWN: STOPPED

(LTC3412)

DC/DC

(LTC3412)

SHUTDOWN: STOPPED

RUN: RUNNING

SLEEP: RUNNING

2V5_PWRON

SHUTDOWN: STOPPED

+24V_PBUS

VCC

RC AT 1M*0.1UF @ 24V

+24V_PBUS

& BOOST OUTPUT

MAXBUS

5V_PWRON

3V3_PWRON

5V_PWRON

(+1.3V)

(LTC3707)

SHUTDOWN: STOPPED

RUN: RUNNING

+1.3V

AGP I/O

DDR2 POWER

1V8_1V5_OK

1V5_PWRON

1V8_PWRON

5V_PWRON

MAIN 3V/5V

INTERNAL ZENER CLAMP TO 6V

PGOOD

RUN/SS - 5V

RC AT 1M*0.047UF @ 24V

RUN: RUNNING

SLEEP: RUNNING

SHUTDOWN: RUNNING

AC: 12.8V

<~13.44V SHUTS-OFF

>~13.44V TURNS-ON

POWER SYSTEM ARCHITECTURE

MAIN 1.8V/1.5V

1625 NOT RUNNING

INVERTER

<100UA ALLOWED

DC/DC

STBYMD

SLEEP: RUNNING

RUN: RUNNING

INTERNAL ZENER CLAMP TO 6V

<100UA ALLOWED

TURNS ON AT >1V

RUN/SS - 3V

WHEN ONLY BATTERY IS CONNECTED

BATTERY VOLTAGE

FEED-IN PATH

BACKUP BATTERY

24V IS OUTPUT ONLY FROM

BACKUP

+BATT

AC

+PBUS

14V CHARGES BACKUP BATTERY

+PBUS

14V_PBUS

1V20_REF

TURNS ON AT >1V

LDO

BACKUP BATTERY CIRCUIT CHARGES OFF +PBUS

+PBUS

(UNTIL DRAINED)

-

+

INTERNAL 1.2UA CURRENT SOURCE

AND PREVENTS +PBUS AND +24V_PBUS FROM DROPPING BELOW 6V

IN

INRUSH

LIMITER

RUN/SS

BUCK

REGULATOR

VCC

NO AC: BATTERY VOLTAGE

(LTC1625)

(MAX1772)

CHARGER

BATTERY

+BATT

CHARGER INPUT

BATTERY

NO INRUSH PROTECTION

3V_5V_OK

BACKLIGHT

VCC

DC/DC

(MAX1715)

PGOOD

SHUTDOWN: STOPPED

SLEEP: RUNNING

RUN: RUNNING

TURNS ON OUTPUT @ 2.4V

ON1/ON2

VCC

DC/DC

(MAX1717)

SHUTDOWN: STOPPED

SLEEP: STOPPED

RUN: RUNNING

VCC

EXT_VCC

DC/DC

(LTC1778)

TURNS ON AS LOW AS 0.8V/TYP 1.5V

RUN/SS

HOLDS BOTH RUN/SS AT GND WHEN IT’S CONNECTED TO GND

TURNS CONTROL TO RUN/SS WHEN IT’S OPEN

SHUT-DOWN

RUN

SLEEP

RUN

SHUT-DOWN

~8.2MS

??? MS

2.4V - ??? MS

~7.36MS

~2.23MS

ADAPTER

SYNC_DATE=N/A

SYNC_MASTER=N/A

Power Block Diagram

4

115

C

051-6929

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

- Added R0985 10K pull down on JTAG_CPU0_TCK

- Added R3772 10K pull down on CPU0_EXT_QUAL on Mullet and sync’d

- Changed R2949 to NO STUFF for BOM.

- Changed C1721 and C2205 to 2200pF

- Changed C1730 to 5.6pF

- Changed C1700 and C1701 and C2215 andC2216 to 47uF

- Changed R1720 and R2205 to 7.5K

- Changed D1460,D1461 to 60V schottky to reduce reverse leakage

- Changed R2958 to 10K for improved power sequencing timing

REVISION HISTORY

- Beginning revision history

- Modem connector moved to non-shared page

- Chassis grounds partitioned as in previous products

- Made additional FB pin swaps

- Changed DDR2 CS/CKE RPAKs to RPAK2P (added RP4871, RP4876)

04/11/2005

08/02/2005 08/03/2005

08/16/2005 08/17/2005

- Various Pb-free replacements

- Changed TMDS drive strength resistors to 301 ohm, which was built at EVT

- Changed CPU Vcore to 2-states only (no MUX)

- Removed 1.5GHz config

- Added external 1K pullups in parallel with all I2 internal pullups

- Changed TMDS transmitter ferrites to part with higher current rating (1.5A)

- Released as REV 06 for DVT

- Replaced 371S0299 with 371S0300

- Changed PCI ZDB output series term to 22 ohms

- Changed power supply jumpers to shorts

- Added remaining spacing and physical rule tables

04/12/2005

04/06/2005

- Changed Q2941 to level shift/pass FET to correct GPU VCore and CPU Vcore power sequencing

- Moved R2943 to SYS_PWRSEQ_1_L to correct trackpad power state in sleep

- Moved =PP3V3_I2C_SB to RUN rail to correct pumpup problem in sleep

- Added FET to allow PMU control of trackpad power sequencing

- Removed I2’s connection to TBEN (leakage path)

- Changed NEC USB2 series R value to 39.2 ohm

- Added BOMOPTIONs for and stuffed CPU Vcore at 1.28V and 1.30V

- Added resistor mux for I2’s MAXBUS I/O rail (PWRON vs RUN)

- Moved UATA_DSTROBE cap to other side of series resistor

- Changed PCI clock series Rs to 0 ohms

- Changed CPU clock series Rs to 10 ohms

07/18/2005

07/06/2005

07/08/2005 07/09/2005

- Removed series R isolating VG from digital ground on FW ports (per design guide)

- Corrected synonym problems on PMU port usage

- Moved FB series R to page 61

- Made DDR2 and FB pin swaps as requested by CM

- CPU0 Vcore A/B select line hooked to I2 GPIO1

- Stuffed R2903 to disable FW port power when off on AC

- Corrected MIN_LINE_WIDTH properties on PP3V3_PWRON

- Corrected line and neck width properties

07/14/2005

- Implemented FireWire pin swaps

- Added 1.5V DVO option to GPU

- Added NO_TEST properties to buses between JTAG enabled devices

- Added external pullups to replace missing internal I2 pullups

- Corrected load capacitance for Vesta FireWire crystal (to 18pF)

- Various Pb-free component replacements

EVT

04/04/2005

04/18/2005

- Corrected ENET power rail to PWRON from RUN (for Wake-on-LAN)

- Fixed ENET_LOWPWR and VESTA_RESET circuits per Vesta design guide

- Corrected STOP_AGP_L net name (hooked to I2 now) and removed redundant pullup

- Pinswapped UATA I/F, DVO I/F, USB pulldowns

- Corrected USB2 diff pair and spacing/physical rules on port connections

- Released as REV 02 for EVT

06/02/2005

- Corrected FireWire VP caps to 50V

- Removed SMS PIC microcontroller

- Added NEC USB2 controller

- Added ZDB clock buffer for PCI clocks

04/14/2005 - Changed GPU to M11

05/20/2005 05/21/2005

- Corrected AGP_INT_L connection between I2 and GPU

- Added DASP signal between HDD and ODD connectors

05/23/2005

- Release as REV 01 for Pre-EVT/EVT

- Corrected VGA sync connections at GPU

05/25/2005

05/24/2005

- Added PDIAG signal between HDD and ODD connectors

05/19/2005 - Various Pb-free component replacements

- Added TBEN sync circuit

- Various Pb-free component replacements

- Pinswaps for I2 RPAKs to match up with Q41C style layout

05/13/2005

- Added pulldown to Vesta LPWR_1394

05/10/2005

05/05/2005

- Added pulldowns to unused serial debug signals (DTR/RTS)

05/04/2005

- Added extra cap at input to I2 USBAVDD

05/03/2005

- Changed 220uF CPU VCore caps to 330 uF LF caps

04/22/2005

- Disconnected FW_POWERDOWN from Vesta LPWR_1394 pin

04/21/2005

04/20/2005

04/15/2005

04/13/2005

- Changed audio caps to X5R (CA033, CA050, CA051)

04/06/2005

- Added RAM_DQS_N pulldowns

04/19/2005

05/16/2005

- Added Hynix VRAM option and PCBAs

05/31/2005

05/26/2005

06/01/2005

06/03/2005

06/07/2005

- Added ADC caps at PMU

- Added CPU0 VCore VID mux

06/28/2005

- Implemented more DDR2 pin swaps

- Added upper LVDS channel to functional test page

- Released as REV 04 for EVT

- Added audio mute sequencing FETs

- Added line width constraints to LTC1625 and CPU Vcore gate nodes

- Added 150 ohm pulldowns to FW_CTL lines at Vesta

07/19/2005

07/22/2005 07/25/2005

- Changed 32.768kHz crystal to new APN specifing 1uW drive parts

- Changed to USB1P1_NEC BOMOPTION

- Corrected alternate errors and a leaded table item

- Released as REV 03 for EVT

- Corrected pulldown resistor value for 0.006 ohm battery current sense

- Added page 6 and modified pages 11,35,81 for design specific pin swaps

- Changed all external I2 GPIO pullups to 10K

- Stuffed R2452, R2462, R2463 to correct I2 2.5V pullup problem

- Swapped I2_MAXBUS_33OHM and I2_MAXBUS_50OHM BOMOPTIONs

- Changed to Vesta v1.4 as primary U8500, Vesta v1.3 as alternate

07/26/2005

- Swapped locations (i.e values) of C2500 and C2501

07/29/2005

DVT

- Changed battery sense resistor to 0.006 ohm (R1250)

- Added 10K pullup to VIA_REQ_L

- Added 2 0.1uF caps to GPU Vcore regulator output

- Various Pb-free component replacements

- Changed GPU FB MVREFs into separate dividers

- Changed R5880 to 6.34K to take GPU Vcore to 1.3V/1.05V

- Updated straps, VREF inputs and decoupling on GPU

- Added high/low swing BOMOPTIONs for DVO on SI TMDS parts

- Reduced MIN_NECK_WIDTH property on GND to 0.2 mm for TMDS parts

- Corrected TMDS DIFFERENTIAL_PAIR properties at DVI connector

- Updated BOM options on CPU Vcore and AVDD for 1.22,1.30, and 1.33V

08/22/2005

08/18/2005

- Added five ceramic caps to Vcore supply

- Changed C3940-C3947 to 1206 ceramic caps

08/05/2005

- Released as REV 07 for DVT

- Added FETs to prevent leakage onto Vesta rails

- Changed C8600-C8603 to 1uF due to insertion of FET

- Changed R5822 to 100K for power sequence improvement

- NO STUFFed R2969 for power sequence improvement

Pre-PVT

PVT

08/24/2005

- Released as REV 08 for Pre-PVT

- Released as REV A for PVT

08/29/2005

- Stuffed R8420 with 10K, 5% to ensure MDIO logic levels

08/31/2005 09/02/2005

- Stuffed R2464 to correct unused GPIO logic level

- Changed MLB to 820-1940, which corrects tolerance on DIMM conn holes

C

5

115

C

051-6929

SYNC_MASTER=N/A

SYNC_DATE=N/A

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(IDE_CS1FX_L)

UATA Series Rs

Upper DVO Series Rs

AGP Pullups

PCI Pullups

Lower DVO Series Rs

I2S Series Rs

MAXBUS Pullups

USB Pulldowns

FW Series Rs

Q16C Pin Swaps

SYNC_DATE=N/A

SYNC_MASTER=N/A

6

115

C

051-6929

NO_TEST=YES

MAKE_BASE=TRUE

NC_MAXBUS_I2_TBEN

MAXBUS_CPU1_INT_L

MAKE_BASE=TRUE

MAXBUS_CPU0_DRDY_L

=RP3513P3 =RP3513P4

FW_D_R<7>

MAKE_BASE=TRUE

MAXBUS_TEA_L

MAKE_BASE=TRUE

FW_D<5>

MAKE_BASE=TRUE

FW_D<1>

MAKE_BASE=TRUE

FW_D<0>

MAKE_BASE=TRUE

FW_D<6>

MAKE_BASE=TRUE

FW_D<4>

MAKE_BASE=TRUE

FW_D<2>

MAKE_BASE=TRUE

FW_D<3>

MAKE_BASE=TRUE

FW_D<7>

=RP9100P7

=RP9100P8

=RP9100P2

=RP9100P1

=RP9101P8

=RP9100P6 =RP9100P5

=RP9101P5

=RP9101P6

=RP9101P7

=RP9101P1

=RP9100P4

=RP9100P3

=RP9101P4

=RP9101P3

=RP9101P2

FW_D_R<5>

MAKE_BASE=TRUE

FW_D_R<1>

MAKE_BASE=TRUE

FW_D_R<6>

MAKE_BASE=TRUE

FW_D_R<0>

MAKE_BASE=TRUE

FW_D_R<3>

MAKE_BASE=TRUE

FW_D_R<2>

MAKE_BASE=TRUE

FW_D_R<4>

MAKE_BASE=TRUE

=RP9301P5

=RP9301P6

=RP9301P7

=RP9301P8

=RP9300P5

=RP9300P6

=RP9300P7

=RP9300P8

USB_NEC_BT_P

MAKE_BASE=TRUE

USB_NEC_BT_N

MAKE_BASE=TRUE

USB_NEC_TPAD_N

MAKE_BASE=TRUE

USB_NEC_TPAD_P

MAKE_BASE=TRUE

USB2_NEC_RIGHT_PORT_P

MAKE_BASE=TRUE

USB2_NEC_RIGHT_PORT_N

MAKE_BASE=TRUE

USB2_NEC_LEFT_PORT_N

MAKE_BASE=TRUE

USB2_NEC_LEFT_PORT_P

MAKE_BASE=TRUE

USB_I2_BT_P

MAKE_BASE=TRUE

USB_I2_BT_N

MAKE_BASE=TRUE

USB2_I2_RIGHT_PORT_N

MAKE_BASE=TRUE

USB2_I2_RIGHT_PORT_P

MAKE_BASE=TRUE

USB2_I2_P<3>

MAKE_BASE=TRUE

USB2_I2_N<3>

MAKE_BASE=TRUE

USB2_I2_N<1>

MAKE_BASE=TRUE

USB2_I2_P<1>

=RP9210P8 =RP9210P7 =RP9210P6 =RP9210P5

=RP9211P8 =RP9211P7 =RP9211P6 =RP9211P5

MAKE_BASE=TRUE

PCI_FRAME_L

=RP7251P4

MAKE_BASE=TRUE

PCI_CBUS_GNT_L

=RP7251P3

MAKE_BASE=TRUE

PCI_CBUS_REQ_L

=RP7251P1

MAKE_BASE=TRUE

PCI_AIRPORT_REQ_L

=RP7251P2

=RP3511P2 =RP3511P3 =RP3511P4

=RP3510P1 =RP3510P2

=RP3511P1

MAKE_BASE=TRUE

MAXBUS_TS_L MAXBUS_CPU1_BG_L

MAKE_BASE=TRUE

MAXBUS_CPU0_BG_L

MAKE_BASE=TRUE MAKE_BASE=TRUE

MAXBUS_CPU1_HIT_L

MAKE_BASE=TRUE

MAXBUS_CPU0_HIT_L MAXBUS_CPU0_BR_L

MAKE_BASE=TRUE

I2S0_SB_TO_DEV_DTO_R I2S0_BITCLK_R

MAKE_BASE=TRUE

I2S0_MCLK_R

MAKE_BASE=TRUE

I2S0_SYNC_R

MAKE_BASE=TRUE

I2S1_SYNC_R

MAKE_BASE=TRUE

I2S1_SB_TO_DEV_DTO_R

I2S1_MCLK_R

MAKE_BASE=TRUE

I2S1_BITCLK_R

MAKE_BASE=TRUE

=RP1150P1 =RP1150P2 =RP1150P3 =RP1150P4

=RP1151P1 =RP1151P2 =RP1151P3 =RP1151P4

=RP1150P7

=RP1150P8

=RP1150P6 =RP1150P5

=RP1151P7

=RP1151P8

=RP1151P6 =RP1151P5

MAKE_BASE=TRUE

I2S0_SB_TO_DEV_DTO I2S0_BITCLK

MAKE_BASE=TRUE

I2S0_MCLK

MAKE_BASE=TRUE

I2S0_SYNC

MAKE_BASE=TRUE

I2S1_BITCLK

MAKE_BASE=TRUE

I2S1_SYNC

MAKE_BASE=TRUE

I2S1_SB_TO_DEV_DTO

I2S1_MCLK

MAKE_BASE=TRUE

MAXBUS_TA_L

MAKE_BASE=TRUE

MAXBUS_CPU1_BR_L

MAKE_BASE=TRUE

MAXBUS_CPU0_INT_L

MAKE_BASE=TRUE

MAXBUS_AACK_L

MAKE_BASE=TRUE

MAXBUS_ARTRY_L

MAKE_BASE=TRUE

MAXBUS_CPU1_DBG_L

=RP3514P3

=RP3514P2

=RP3512P2

=RP3512P1

=RP3512P4

=RP3512P3

=RP3513P2

MAKE_BASE=TRUE

UATA_DD_R<4>

MAKE_BASE=TRUE

UATA_DD_R<9>

MAKE_BASE=TRUE

UATA_DD_R<5>

MAKE_BASE=TRUE

UATA_DD_R<6>

MAKE_BASE=TRUE

UATA_DA_R<2>

MAKE_BASE=TRUE

UATA_DD_R<10>

MAKE_BASE=TRUE

UATA_DD_R<8>

MAKE_BASE=TRUE

UATA_DA_R<0>

MAKE_BASE=TRUE

UATA_DD_R<13>

MAKE_BASE=TRUE

UATA_DD_R<1>

MAKE_BASE=TRUE

UATA_DD_R<0>

MAKE_BASE=TRUE

UATA_DA_R<1>

=RP8153P4

=RP8154P1

=RP8154P3

=RP8154P2

=RP8154P4

=RP8153P5

=RP8154P8 =RP8154P7 =RP8154P6 =RP8154P5

=RP8152P2

=RP8152P1

=RP8152P4

=RP8152P3

=RP8153P1

=RP8153P3

=RP8153P2

=RP8152P8 =RP8152P7 =RP8152P6 =RP8152P5

=RP8153P7

=RP8153P8

=RP8153P6

MAKE_BASE=TRUE

UATA_DD<9>

MAKE_BASE=TRUE

UATA_DD<4>

MAKE_BASE=TRUE

UATA_DD<6>

MAKE_BASE=TRUE

UATA_DD<5>

MAKE_BASE=TRUE

UATA_DD<8>

MAKE_BASE=TRUE

UATA_DA<2>

MAKE_BASE=TRUE

UATA_DD<10>

MAKE_BASE=TRUE

UATA_DA<0>

MAKE_BASE=TRUE

UATA_DD<13>

MAKE_BASE=TRUE

UATA_DD<0>

MAKE_BASE=TRUE

UATA_DD<1>

MAKE_BASE=TRUE

UATA_DA<1>

GPU_DVOD_R<20>

MAKE_BASE=TRUE

GPU_DVOD_R<22>

MAKE_BASE=TRUE

GPU_DVOD_R<23>

MAKE_BASE=TRUE

GPU_DVOD_R<18>

MAKE_BASE=TRUE

=RP6823P1

=RP6823P3

=RP6823P2

=RP6823P4

GPU_DVOD<16>

MAKE_BASE=TRUE

=RP6720P8

GPU_DVOD<7>

MAKE_BASE=TRUE

=RP6720P6

GPU_DVOD<4>

MAKE_BASE=TRUE

=RP6720P7

GPU_DVOD<11>

MAKE_BASE=TRUE

=RP6721P8

GPU_DVOD<6>

MAKE_BASE=TRUE

=RP6720P5

=RP6720P1

GPU_DVOD_R<16>

MAKE_BASE=TRUE

=RP6720P3

GPU_DVOD_R<7>

MAKE_BASE=TRUE

=RP6720P2

GPU_DVOD_R<4>

MAKE_BASE=TRUE

=RP6720P4

GPU_DVOD_R<6>

MAKE_BASE=TRUE

=RP6721P1

GPU_DVOD_R<11>

MAKE_BASE=TRUE

GPU_DVOD<9>

MAKE_BASE=TRUE

=RP6721P7

GPU_DVOD<10>

MAKE_BASE=TRUE

=RP6721P6

GPU_DVO_HSYNC

MAKE_BASE=TRUE

=RP6721P5

GPU_DVOD<3>

MAKE_BASE=TRUE

=RP6722P8

GPU_DVOD<5>

MAKE_BASE=TRUE

=RP6722P7

GPU_DVOD<13>

MAKE_BASE=TRUE

=RP6722P6

GPU_DVOD<12>

MAKE_BASE=TRUE

=RP6722P5

GPU_DVOD<2>

MAKE_BASE=TRUE

=RP6723P8

GPU_DVOD<1>

MAKE_BASE=TRUE

=RP6723P7

GPU_DVOD<0>

MAKE_BASE=TRUE

=RP6723P6

GPU_DVOD<14>

MAKE_BASE=TRUE

=RP6723P5

=RP6721P2

GPU_DVOD_R<9>

MAKE_BASE=TRUE

=RP6721P3

GPU_DVOD_R<10>

MAKE_BASE=TRUE

=RP6721P4

GPU_DVO_HSYNC_R

MAKE_BASE=TRUE

=RP6722P1

GPU_DVOD_R<3>

MAKE_BASE=TRUE

=RP6722P2

GPU_DVOD_R<5>

MAKE_BASE=TRUE

=RP6722P3

GPU_DVOD_R<13>

MAKE_BASE=TRUE

=RP6722P4

GPU_DVOD_R<12>

MAKE_BASE=TRUE

=RP6723P1

GPU_DVOD_R<2>

MAKE_BASE=TRUE

=RP6723P2

GPU_DVOD_R<1>

MAKE_BASE=TRUE

=RP6723P3

GPU_DVOD_R<0>

MAKE_BASE=TRUE

=RP6723P4

GPU_DVOD_R<14>

MAKE_BASE=TRUE

PCI_STOP_L

MAKE_BASE=TRUE

PCI_TRDY_L

MAKE_BASE=TRUE

PCI_IRDY_L

MAKE_BASE=TRUE

PCI_AIRPORT_GNT_L

=RP7250P4

=RP7250P2 =RP7250P3

=RP7250P1

MAKE_BASE=TRUE

AGP_TRDY_L

MAKE_BASE=TRUE

AGP_REQ_L

MAKE_BASE=TRUE

AGP_RBF_L

MAKE_BASE=TRUE

AGP_IRDY_L

MAKE_BASE=TRUE

AGP_FRAME_L

MAKE_BASE=TRUE

AGP_DEVSEL_L

MAKE_BASE=TRUE

AGP_STOP_L

MAKE_BASE=TRUE

AGP_GNT_L

=RP5611P2 =RP5611P3 =RP5611P4

=RP5610P1

=RP5610P3 =RP5610P4

=RP5610P2

=RP5611P1

=RP6823P8 =RP6823P7 =RP6823P6 =RP6823P5

GPU_DVOD<20>

MAKE_BASE=TRUE

GPU_DVOD<22>

MAKE_BASE=TRUE

GPU_DVOD<23>

MAKE_BASE=TRUE

GPU_DVOD<18>

MAKE_BASE=TRUE

=RP9212P8 =RP9212P7 =RP9212P6 =RP9212P5

MAKE_BASE=TRUE

USB2_I2_LEFT_PORT_N

MAKE_BASE=TRUE

USB2_I2_LEFT_PORT_P

MAKE_BASE=TRUE

USB_I2_TPAD_P

MAKE_BASE=TRUE

USB_I2_TPAD_N

MAKE_BASE=TRUE

GPU_DVO_DE_R

MAKE_BASE=TRUE

GPU_DVO_VSYNC_R

MAKE_BASE=TRUE

GPU_DVO_CLKP_R

MAKE_BASE=TRUE

GPU_DVOD_R<8>

MAKE_BASE=TRUE

GPU_DVOD_R<21>

MAKE_BASE=TRUE

GPU_DVOD_R<19>

MAKE_BASE=TRUE

GPU_DVOD_R<17>

MAKE_BASE=TRUE

GPU_DVOD_R<15>

=RP6822P4

=RP6821P2

=RP6821P1

=RP6821P4

=RP6821P3

=RP6822P1

=RP6822P3

=RP6822P2

=RP6822P5

=RP6821P8 =RP6821P7 =RP6821P6 =RP6821P5

=RP6822P7

=RP6822P8

=RP6822P6

MAKE_BASE=TRUE

GPU_DVOD<15>

MAKE_BASE=TRUE

GPU_DVO_DE

MAKE_BASE=TRUE

GPU_DVO_VSYNC

MAKE_BASE=TRUE

GPU_DVO_CLKP

MAKE_BASE=TRUE

GPU_DVOD<8>

MAKE_BASE=TRUE

GPU_DVOD<21>

MAKE_BASE=TRUE

GPU_DVOD<19>

MAKE_BASE=TRUE

GPU_DVOD<17>

UATA_DD_R<12>

MAKE_BASE=TRUE

UATA_DD_R<14>

MAKE_BASE=TRUE

UATA_DD_R<11>

MAKE_BASE=TRUE

UATA_CS0_L_R

MAKE_BASE=TRUE

UATA_DD_R<7>

MAKE_BASE=TRUE

UATA_DD_R<2>

MAKE_BASE=TRUE

UATA_DD_R<3>

MAKE_BASE=TRUE

UATA_DD_R<15>

MAKE_BASE=TRUE

=RP8151P2 =RP8151P3 =RP8151P4

=RP8150P1

=RP8150P3 =RP8150P4

=RP8150P2

=RP8151P1

=RP8151P7 =RP8151P6 =RP8151P5

=RP8150P8 =RP8150P7

=RP8150P5

=RP8150P6

=RP8151P8

UATA_DD<12>

MAKE_BASE=TRUE

UATA_CS0_L

MAKE_BASE=TRUE

UATA_DD<11>

MAKE_BASE=TRUE

UATA_DD<14>

MAKE_BASE=TRUE

UATA_DD<2>

MAKE_BASE=TRUE

UATA_DD<7>

MAKE_BASE=TRUE

UATA_DD<3>

MAKE_BASE=TRUE

UATA_DD<15>

MAKE_BASE=TRUE

=RP3514P1

MAKE_BASE=TRUE

MAXBUS_CPU1_DRDY_L

=RP3510P3 =RP3510P4

MAXBUS_CPU0_DBG_L

MAKE_BASE=TRUE

62

61

64

61

64

33

68

33

69

68

11

60

33

74

33

34

33

63

63 53

55

60

44

55

63

33

32

9

32

9

71

9

73

11

2

11

72

59 59

11 59

32

22

11

7

30

32

63

2

63

2

63

7

53

2

55

55 54

54 54

54 53

54 54

55 54

54 54

55 54

54 53

59

11

59

43

55

72

72 11

11

53

53 55

55

54

55

63

7

32

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

of ODD/HDD connector.

AUDIO

INVERTER

UATA LVDS

POWER

Place within 25 mm of LVDS connector.

Place within 25 mm of inverter connector.

Place within 25 mm of audio connector.

Place within 50 mm

Functional test points use a P6 pad placed on bottom side.

Enhanced MAC-1 Test Coverage

Place 5-10 GND TPs.

Place 2 TPs @ connector

Place within 50 mm of power supply.

of TPAD connector.

Place within 25 mm

Place within 25 mm of fan connector.

of fan connector.

Place within 25 mm

of battery connector.

Place within 25 mm

of debug connector.

Place within 25 mm

of ALS connector.

of right USB connector.

of left USB connector.

SYSTEM

GPU FAN CPU FAN

ALS

SCCA

BACKUP

BATT

RT USBLT USB

I1

I10

I100

I101

I102

I104

I105 I106

I107 I108

I109

I11

I110 I111

I112

I113

I114

I115

I116

I117 I118

I119

I12

I120

I121

I13 I14

I15

I16

I17

I18

I19

I2

I20

I21

I22

I23

I24

I25

I29

I3

I30

I31

I32

I33

I34

I35

I36

I37

I38

I39

I4

I40

I41 I42

I43

I44

I45

I46

I47

I48

I49

I5

I50

I51

I52

I53

I55

I56

I57 I58

I59

I6

I60

I61

I62

I63

I64 I65

I66

I68

I69

I7

I70

I71

I72

I73

I74

I75

I76

I77

I78

I79

I8

I80

I81 I82

I83

I84 I85

I86

I87

I88

I89

I9

I90

I91

I96

I97

I98

SYNC_DATE=N/A

SYNC_MASTER=N/A

7

051-6929

C

115

Functional Test Points

USB2_LEFT_PORT_P

FUNC_TEST=YES

USB2_LEFT_PORT_N

FUNC_TEST=YES

=PP5V_PWRON_LEFT_USB

FUNC_TEST=YES

USB2_RIGHT_PORT_N

FUNC_TEST=YES

USB2_RIGHT_PORT_P

FUNC_TEST=YES

=PP5V_PWRON_RIGHT_USB

=PPVOUT_BU_BATT

FUNC_TEST=YES

=PPVIO_BU_BATT

FUNC_TEST=YES

SCCA_TXD_L

FUNC_TEST=YES

SCCA_RXD

FUNC_TEST=YES

ALS_GAIN_BOOST

FUNC_TEST=YES

ALS_0_OUT

FUNC_TEST=YES

=PP3V3_PWRON_LEFT_ALS

FUNC_TEST=YES

=FTP_GND

FUNC_TEST=YES

FAN2_PWM

FUNC_TEST=YES

FAN2_TACH

FUNC_TEST=YES

=PP5V_FAN2_PWR

FUNC_TEST=YES

=FTP_GND

FUNC_TEST=YES

FAN1_TACH

FUNC_TEST=YES FUNC_TEST=YES

FAN1_PWM

=PP5V_FAN1_PWR

FUNC_TEST=YES

=I2C_DS1775_SCL

FUNC_TEST=YES

=I2C_DS1775_SDA

FUNC_TEST=YES

KBDLED_RETURN

FUNC_TEST=YES

KBDLED_ANODE

FUNC_TEST=YES

SYS_ADAPTER_ANALOG_AC_DET

FUNC_TEST=YES

SYS_CHARGE_LED_L

FUNC_TEST=YES

=FTP_SLEEP_LED

SYS_POWER_BUTTON_L_F

FUNC_TEST=YES

SYS_LID_OPEN_F

FUNC_TEST=YES

PP3V3_ALL_HALL_EFFECT_R

FUNC_TEST=YES

SYS_OVERTEMP_L

FUNC_TEST=YES

PP3V3_PWRON_DS1775_R

FUNC_TEST=YES

USB_TPAD_N

FUNC_TEST=YES

USB_TPAD_P

FUNC_TEST=YES

PP5V_TPAD_F

FUNC_TEST=YES

PP24V_ADAPTER

FUNC_TEST=YES

PP24V_ALL_PBUSA

FUNC_TEST=YES FUNC_TEST=YES

PP12V8_ALL_PBUSB

FUNC_TEST=YES

PPVCORE_RUN_CPU

FUNC_TEST=YES

PPVCORE_RUN_GPU

FUNC_TEST=YES

PP1V8_PWRON

FUNC_TEST=YES

PP2V5_PWRON

FUNC_TEST=YES

PP5V_PWRON

FUNC_TEST=YES

PP3V3_PWRON

FUNC_TEST=YES

PP5V_RUN

FUNC_TEST=YES

PP3V3_ALL

FUNC_TEST=YES

=FTP_GND

LVDS_U0_P

FUNC_TEST=YES

LVDS_U0_N

FUNC_TEST=YES

LVDS_U1_P

FUNC_TEST=YES

LVDS_U1_N

FUNC_TEST=YES

LVDS_U2_P

FUNC_TEST=YES

LVDS_U2_N

FUNC_TEST=YES

CLKLVDS_U_P

FUNC_TEST=YES

LVDS_L0_P

FUNC_TEST=YES

CLKLVDS_U_N

FUNC_TEST=YES

LVDS_L0_N

FUNC_TEST=YES

LVDS_L1_P

FUNC_TEST=YES

LVDS_L1_N

FUNC_TEST=YES

LVDS_L2_N

FUNC_TEST=YES

LVDS_L2_P

FUNC_TEST=YES

CLKLVDS_L_P

FUNC_TEST=YES

CLKLVDS_L_N LVDS_DDC_CLK

FUNC_TEST=YES

LVDS_DDC_DATA

FUNC_TEST=YES

=PP3V3_DDC_LCD

FUNC_TEST=YES

PP3V3_LCD_CONN

FUNC_TEST=YES

PPBUS_INVERTER

FUNC_TEST=YES

PP5V_INV_SW

FUNC_TEST=YES

BRIGHT_PWM

FUNC_TEST=YES

GND_INVERTER

FUNC_TEST=YES

=PP5V_RUN_HDD

FUNC_TEST=YES

=PP5V_RUN_ODD

FUNC_TEST=YES

PP3V3R5V_RUN_HDD_LOGIC

FUNC_TEST=YES FUNC_TEST=YES

UATA_DD<15..0>

FUNC_TEST=YES

UATA_DMARQ

FUNC_TEST=YES

UATA_DMACK_L

FUNC_TEST=YES

UATA_DSTROBE

FUNC_TEST=YES

UATA_DA<2..0>

FUNC_TEST=YES

UATA_CS0_L

FUNC_TEST=YES

UATA_CS1_L

FUNC_TEST=YES

UATA_HSTROBE

FUNC_TEST=YES

UATA_RESET_L

FUNC_TEST=YES

UATA_STOP

FUNC_TEST=YES

UATA_INTRQ

FUNC_TEST=YES

PP5V_PWRON_AUDIO_PVDD

FUNC_TEST=YES

PP5V_PWRON_AUDIO_AVDD

FUNC_TEST=YES

PP3V3_PWRON_AUDIO_AVDD =PP3V3_RUN_AUDIO

FUNC_TEST=YES

=I2C_AUDIO_SCL

FUNC_TEST=YES

=I2C_AUDIO_SDA

FUNC_TEST=YES

I2S0_MCLK

FUNC_TEST=YES

I2S0_BITCLK

FUNC_TEST=YES

I2S0_SYNC

FUNC_TEST=YES

I2S0_SB_TO_DEV_DTO

FUNC_TEST=YES

I2S0_DEV_TO_SB_DTI

FUNC_TEST=YES

AUDIO_LO_MUTE_L

FUNC_TEST=YES

AUDIO_SPKR_MUTE_L

FUNC_TEST=YES

AUDIO_CODEC_RESET_L

FUNC_TEST=YES

AUDIO_SPDIFRX_RESET_L

FUNC_TEST=YES

AUDIO_LO_DET_L

FUNC_TEST=YES

AUDIO_LI_DET_L

FUNC_TEST=YES FUNC_TEST=YES

AUDIO_LO_OPTICAL_PLUG_L

FUNC_TEST=YES

AUDIO_LI_OPTICAL_PLUG_L

FUNC_TEST=YES

AUDIO_I2S_DTIB_SEL

FUNC_TEST=YES

AUDIO_EXT_MCLK_SEL

FUNC_TEST=YES

AUDIO_GPIO_11

FUNC_TEST=YES

GND_AUDIO_AGND GND_AUDIO_PGND

FUNC_TEST=YES

31

30

64

74

31

24

28

31

10

31

10

31

30

74

25

30

10

56

64

63

64

63

64

74

11

10

11

10

22

25

10

7

27

10

7

27

10

8

28

12

24

30

11

30

11

30 10

10

7

53

51

10

56

10

64

6

63

6

63

74

10

8

6

22

74

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

U2100

JA000U2100

SPDIF

Codec

Audio Board

(Write: 0x8C Read: 0x8D) (Write: 0x22 Read: 0x23)

(MASTER)

U5700

GPU I2C Bus

EXT TMDS/S

EXT TMDS/M

U6700

U6800

(Write: 0x70 Read: 0x71)

(Write: 0x72 Read: 0x73)

PMU SMBus

PMU unstead. One ADT7467 connects to NB

NOTE: Neither option is necessary when

PMU

Signal aliases required by this page:

- GOV_I2C / GOV_I2C_BYPASS

I2C bus 1 to resolve address conflict.

Selects whether MMM MCU is powered all

BOM options provided by this page:

Power aliases required by this page:

MMM_MCU_PMU BOM option is selected.

(NONE)

it can be monitored by in shutdown.

ALL moves the MCU to the PMU I2C bus so

the time or only when the system is on.

Most devices are connected directly to

Allows bypassing Governator I2C bus.

- MMM_PWR_ALL / MMM_PWR_PWRON

J790

Battery Conn

(Write: 0x16 Read: 0x17)

(MASTER)

PMU

U1300

(NONE)

PMU I2C Bus

U1300

(MASTER)

SouthBridge I2C Bus

J5000A / J5000B

DIMMs

(Write: 0xA0 / 0xA2, Read: 0xA1 / 0xA3)

(MASTER)

I2

NorthBridge I2C Bus

I2

GPU

Page Notes

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

SPACING

NET_TYPE

DIFFERENTIAL_PAIR

U3000

ADT7467

(Write: 0x5C Read: 0x5D)

DS1775

On Trackpad Flex

(Write: 0x92 Read: 0x93)

1/16W MF-LF 402

1%

7.15K

2

1

R0851

7.15K

1% 1/16W MF-LF

402

2

1

R0850

1K

5% 1/16W MF-LF 402

2

1

R0821

402

5%

1K

MF-LF

1/16W

2

1

R0820

5% 1/16W MF-LF

1K

402

2

1

R0843

1K

5% 1/16W MF-LF

402

2

1

R0842

402

1K

MF-LF

1/16W

5%

2

1

R0841

402

MF-LF

1/16W

5%

1K

2

1

R0840

1/16W

402

MF-LF

5%

2.0K

2

1

R0830

1/16W MF-LF 402

2.0K

5%

2

1

R0831

SYNC_DATE=N/A

SYNC_MASTER=N/A

I2C Connections

C

8

115

051-6929

=I2C_DS1775_SDA

=I2C_DS1775_SCL

=I2C_ADT7467_SDA

=I2C_ADT7467_SCL

I2C_I2_NB_SCL

MAKE_BASE=TRUE

I2C_I2_NB_SDA

MAKE_BASE=TRUE

I2C_I2_SB_SCL

I2CI2C

I2C_I2_SB_SDA

I2CI2C

I2C_GPU_TMDS_SDA

I2CI2C

I2C_GPU_TMDS_SCL

I2C I2C

I2C_NB

I2C_I2_NB_SCL

I2CI2C

I2C_PMU_SMB_SDA

I2CI2C

I2C_PMU_SDA

I2CI2C

I2C_PMU_SCL

I2C_PMU_SMB_SCL

I2C I2C

I2C_NB

I2C_I2_NB_SDA

I2CI2C

=I2C_I2_NB_SDA

=I2C_SODIMM_SDA

=I2C_I2_NB_SCL

=I2C_SODIMM_SCL

=PPI2C_I2_NB

=PPI2C_I2_SB

=I2C_I2_SB_SDA

=I2C_I2_SB_SCL

=I2C_PMU_SMB_SDA

=I2C_BATT_SDA

=I2C_PMU_SDA

=I2C_PMU_SCL

=I2C_PMU_SMB_SCL

=PPI2C_SYS1

=I2C_BATT_SCL

=PPI2C_SYS0

I2C_PMU_SCL

MAKE_BASE=TRUE

I2C_PMU_SDA

MAKE_BASE=TRUE

I2C_PMU_SMB_SCL

MAKE_BASE=TRUE

I2C_PMU_SMB_SDA

=PPI2C_GPU

MAKE_BASE=TRUE

I2C_GPU_TMDS_SCL

MAKE_BASE=TRUE

I2C_GPU_TMDS_SDA

=I2C_SI_M_SCL

=I2C_SI_M_SDA

=I2C_SI_S_SCL

=I2C_SI_S_SDA

=I2C_GPU_TMDS_SCL

=I2C_GPU_TMDS_SDA

MAKE_BASE=TRUE

I2C_I2_SB_SCL

MAKE_BASE=TRUE

I2C_I2_SB_SDA

=I2C_AUDIO_SCL

=I2C_AUDIO_SDA

30

41

74

7

27

8

22 40

10

22

25 12

25

10

12

10

8

10

8

54

55

51

8

7

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

I2

CPU0

VESTA

FIREWIRE

ENET

Nets not requiring TPs due to JTAG

MAXBUS

PMU (BOOTBANGER)

I100 I101

I102

I103

MF-LF 402

1/16W

5%

10K

NO STUFF

2

1

R0985

5%

10K

1/16W SM-LF

8

1

RP0990

5% 1/16W

10K

SM-LF

6

3

RP0990

402

MF-LF

1/16W

5%

1K

2

1

R0990

5% 1/16W

10K

SM-LF

2

7

RP0990

10K

5%

MF-LF

402

1/16W

2

1

R0950

10K

402

5%

MF-LF

1/16W

2

1

R0981

MF-LF 402

10K

5% 1/16W

2

1

R0982

402

1/16W

5%

10K

MF-LF

2

1

R0983

402

MF-LF

1/16W

5%

200

2

1

R0984

5% 1/16W MF-LF

402

10K

NO STUFF

2

1

R0980

I76 I77

I78 I79

I80

I81 I82

I83

I85

I86 I87

I88 I89

I90

I91

I92

I93

I94 I95

I96

I97 I98

I99

SYNC_MASTER=N/A

SYNC_DATE=N/A

JTAG Connections

115

9

051-6929

C

JTAG_CPU_TMS

MAKE_BASE=TRUE

JTAG_CPU_TCK

MAKE_BASE=TRUE

NO_TEST=YES

FW_CTL<1..0>

NO_TEST=YES

FW_CTL_R<1..0>

NO_TEST=YES

ENET_TXD<7..0>

NO_TEST=YES

FW_LREQ_R

NO_TEST=YES

FW_LPS

NO_TEST=YES

ENET_COL

NO_TEST=YES

ENET_RX_DV

NO_TEST=YES

ENET_MDC

NO_TEST=YES

ENET_MDIO

FW_LREQ

NO_TEST=YES

FW_LPS_R

NO_TEST=YES

FW_D_R<7..0>

NO_TEST=YES

FW_D<7..0>

NO_TEST=YES

ENET_RXD<7..0>

NO_TEST=YES

ENET_TX_ER

NO_TEST=YES

ENET_TX_EN

NO_TEST=YES

ENET_RX_ER

NO_TEST=YES

ENET_CRS

NO_TEST=YES

MAXBUS_DTI<2..0>

NO_TEST=YES

MAXBUS_TT<4..0>

NO_TEST=YES

MAXBUS_TSIZ<2..0>

NO_TEST=YES

MAXBUS_ADDR<31..0>

NO_TEST=YES

MAXBUS_DATA<63..0>

NO_TEST=YES

MAXBUS_CI_L

NO_TEST=YES

MAXBUS_TBST_L

NO_TEST=YES

MAXBUS_GBL_L

NO_TEST=YES

MAXBUS_WT_L

MAKE_BASE=TRUE

TP_JTAG_VESTA_TMS

MAKE_BASE=TRUE

JTAG_VESTA_TRST_L

MAKE_BASE=TRUE

TP_JTAG_VESTA_TCK

=JTAG_VESTA_TMS

=JTAG_VESTA_TDO

MAKE_BASE=TRUE

TP_JTAG_VESTA_TDOTP_JTAG_VESTA_TDI

MAKE_BASE=TRUE

=JTAG_VESTA_TCK

=JTAG_VESTA_TRST_L

=JTAG_VESTA_TDI

=PPJTAG_CPU

MAKE_BASE=TRUE

TP_JTAG_CPU_TDO

=JTAG_CPU0_TDO

=JTAG_CPU0_TMS =JTAG_CPU0_TRST_L =JTAG_CPU0_TCK

=JTAG_CPU0_TDI

=JTAG_BBANGER_TDI

=JTAG_BBANGER_TMS

=JTAG_BBANGER_TRST_L

=JTAG_BBANGER_TCK

=PP3V3_PWRON_JTAG_ASIC

MAKE_BASE=TRUE

JTAG_ASIC_TCK

MAKE_BASE=TRUE

JTAG_ASIC_TMS

MAKE_BASE=TRUE

JTAG_ASIC_TRST_L

MAKE_BASE=TRUE

TP_JTAG_I2_TDO

=JTAG_I2_TDO

=JTAG_I2_TMS =JTAG_I2_TRST_L =JTAG_I2_TCK

=JTAG_I2_TDI

MAKE_BASE=TRUE

JTAG_I2_TDI

MAKE_BASE=TRUE

JTAG_CPU_TDI

MAKE_BASE=TRUE

JTAG_CPU_TRST_L

33

71

65

71

68

69

65

33

32

33

69

68

11

68

69

11

69

68

6

11

32

21

32

18

10

34

25

10

22

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

0

5%

1/8W

MF-LF

805

21

R1018

805

MF-LF

1/8W

5%

0

21

R1015

0

5%

1/8W

MF-LF

805

21

R1025

805

MF-LF

1/8W

5%

0

21

R1033

SM

21

XW1013

SM

21

XW1019

SM

21

XW1050

SM

21

XW1033

SM

21

XW1025

SM

21

XW1018

SM

21

XW1015

SM

21

XW1012

SM

21

XW1017

Power Synonyms

10

115

C

051-6929

SYNC_DATE=N/A

SYNC_MASTER=N/A

=PPVCORE_PWRON_I2_REG

VOLTAGE=1.5V MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

MAKE_BASE=TRUE

PPVCORE_PWRON_I2

=PPVCORE_GPU_REG

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=1.3V

MAKE_BASE=TRUE

PPVCORE_RUN_GPU

PP1V5_PWRON_REG

MAKE_BASE=TRUE VOLTAGE=1.5V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

PP1V8_PWRON_REG

MAKE_BASE=TRUE VOLTAGE=1.8V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

PP2V5_PWRON_REG

MAKE_BASE=TRUE VOLTAGE=2.5V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

=PP1V5_PWRON_RUNFET =PP1V5_I2_AGP

=PP1V5R1V8_PWRON_I2_MAXBUS

=PP1V8_PWRON_I2_RAM

=PP1V8_PWRON_DDR2

=PP1V8_PWRON_RUNFET

=PPVIN_PWRON_I2PLLVDD

=PP2V5_ENET

=PP2V5_PWRON_RUNFET

=PP1V5_PWRON_REG

PP1V5_PWRON

MAKE_BASE=TRUE VOLTAGE=1.5V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

=PP1V8_PWRON_REG

=PP2V5_PWRON_REG

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=1.8V

MAKE_BASE=TRUE

PP1V8_PWRON

PP2V5_PWRON

MAKE_BASE=TRUE VOLTAGE=2.5V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

=PP3V3_PWRON_REG

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=3.3V

MAKE_BASE=TRUE

PP3V3_PWRON

=PP5V_PWRON_REG

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=5V

MAKE_BASE=TRUE

PP5V_PWRON

MAKE_BASE=TRUE

PP3V3_VESTA

MIN_NECK_WIDTH=0.25 mm

VOLTAGE=3.3V MIN_LINE_WIDTH=0.5 mm

=PP3V3_ALL_BATT_CHGR

=PP3V3_ALL_BATT0_DET

=PP1V8_GPU_PWRSEQ

=PP24V_PBUSA_HOLDUP_CAPS

=PPBUS_FWPWRSW

=PPI2C_SYS0

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=3.3V

PP3V3_ALL

MAKE_BASE=TRUE

=PP3V3_ALL_DEBUG

=PP2V5R3V3_PWRON_I2_ENET

=PP3V3_PWRON_RT_ALS

=PP3V3_PWRON_I2_MISC

=PP3V3_PWRON_JTAG_ASIC

=PP5V_PWRON_LEFT_USB

PP3V3_RUN

MAKE_BASE=TRUE VOLTAGE=3.3V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

=PPVIN_CPU0_AVDD

=TPS2211_SHDN_L =PP3V3_RUN_AUDIO =PPVIO_PCI_USB2 =PP3V3_PCI_USB2 =PP3V3_PCI_ZDB =PPI2C_I2_SB

=PP1V5_RUN_RUNFET

=PP2V5_RUN_RUNFET

=PP1V8_GPU

=PP3V3_ENETFW

MIN_LINE_WIDTH=0.25 mm

VOLTAGE=5V

PP5V_TPAD

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.15 mm

=FTP_GND

PP5V_RUN

MAKE_BASE=TRUE VOLTAGE=5V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

=PPVCORE_CPU_ADT7467

PPVCORE_CPU_ADT7467

MAKE_BASE=TRUE MIN_LINE_WIDTH=0.25 mm

VOLTAGE=1.3V MIN_NECK_WIDTH=0.15 mm

=PPFW_P3V3VESTA

PPFW_CABLE_POWER

MAKE_BASE=TRUE VOLTAGE=33V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

MAKE_BASE=TRUE VOLTAGE=24V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

PP24V_ALL_PBUSA

=PPBUS_DVI_PWRSW

MAKE_BASE=TRUE MIN_LINE_WIDTH=0.25 mm

MIN_NECK_WIDTH=0.15 mm

VOLTAGE=12.8V

PPBUS_DVI_PWRSW

=PP5V_PWRON_PWRSEQ

=PP1V5R1V8_RUN_I2_MAXBUS

=PP1V5R1V8_MAXBUS

=PP1V5_GPU

=PPVBATT_BATT_VSNS

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

VOLTAGE=12.8V

MAKE_BASE=TRUE

PPVBATT_BATT_CHRG_VSNS

=PPVIN_BATT_CHRG_VSNS

=PP24V_ADAPTER_CONN

=PPVBATT_ISNS_N

=PP24V_ADAPTER_PMU_SUPPLY

=PP24V_ADAPTER_RAW

=PPVBATT_BATTERY_PMU_SUPPLY

=PPVBATT_BATT

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=12.8V

MAKE_BASE=TRUE

PPVBATT_BATT

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=24V

MAKE_BASE=TRUE

PP24V_ADAPTER

=PPI2C_GPU

=PP3V3_GPU

=PP3V3_PCI

=PP3V3_DDC_LCD

=PP3V3_DDC_DVI

=PP3V3_ALL_PWRSEQ

=PPVCORE_PWRON_I2

=PP1V05R1V3_GPU_VCORE

=PPFW_PORT2

=PPVCORE_CPU_REG

=PPVCORE_CPU0

=PP3V3_PWRON_CPUVCORE_OFFSET

=PP3V3_PWRON_CPUVCORE_VID

=PP3V3_PWRON_MODEM

=PP3V3_ALL_PMU

=PP5V_RUN_HDDFET

PP5V_RUN_HDD

MAKE_BASE=TRUE VOLTAGE=5V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

=PP5V_RUN_HDD

=PP5V_FAN1_PWR

=PPVIN_GPU_LVDDR_LDO

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=3.3V

MAKE_BASE=TRUE

PP3V3_GPU

=PP3V3_GPU_PWRSEQ

=PP2V5_GPU

=PP2V5_GPU_PVDD

=PP2V5_GPU_A2VDD

=PP2V5_GPU_PWRSEQ

=PP2V5_GPU_LVDS_IO

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=2.5V

MAKE_BASE=TRUE

PP2V5_GPU

=PP3V3_RUN_SI

=PP3V3_GPU =PP3V3_AGP

=PP3V3_GPU_VDDR3

=PP1V5_GPU_VDD15

=PP1V5_AGP=PP1V5_GPU

=PP4V85_ALL_VREG

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

VOLTAGE=4.85V

MAKE_BASE=TRUE

PP4V85_ALL

=PP4V85_ALL_A29_DET

=PPVIN_ALL_LTC1625

=PPVIN_ALL_LTC3707

=PPVIN_ALL_MAX1715

=PP12V8_PBUSB_HOLDUP_CAPS

=PPVIN_LTC1778_GPU

=PPVIN_CPUVCORE_MAX1717 =PPBUS_INVERTER

=PPVBATT_BATT_PBUSA

=PP14VR24V_ALL_PBUS_A

=PPVOUT_BU_BATT

=PPVBATT_BATT_PBUSB

=PP12V8_LTC1625_VREG

=PPVIO_BU_BATT

=PP3V3_VESTA

=PP3V3_VESTA_2V5REG

=PP3V3_VESTA_REG

PP2V5_VESTA

MAKE_BASE=TRUE MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.25 mm

VOLTAGE=2.5V

MAKE_BASE=TRUE

PP1V2_VESTA

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

VOLTAGE=1.2V

=PP2V5_VESTA =PP2V5_ENETFW

=PP1V2_VESTA

=PPFW_PHY_CPS =PPFW_PORT1

=PP2V5_VESTA_LDO

=PP1V2_VESTA_REG

=PPBUS_FW_FET

=PP3V3_ALL_VREG

=PP3V3_ALL_PBUS_ILIM

=PP3V3_ALL_LTC1625_SW

=PP3V3_ALL_A29_DET

=PP3V3_ALL_AC_DETECT

=PP5V_PWRON_PMU_SUPPLY

=PP5V_PWRON_LTC1625_EXTVCC

=PP5V_PWRON_RUNFET

=PP5V_PWRON_LTC3707_EXTVCC

=PP5V_RUN_ODD

=PP5V_RUN_FANPWM

=PPBU_RUN_FW

=PP5V_RUN_KEYBRD_LED =PP5V_RUN_DVI_DDC

=PP5V_RUN_RUNFET

=PP3V3_RUN_RUNFET

=PP2V5_RUN_PCI1510 =PP2V5_GPU

=PP3V3_BATT_IMON

PP3V3_ALL_PMU_AVCC

MAKE_BASE=TRUE

=PP3V3_RUN_KEYBRD_LED

=PP3V3_GPU_GPIOS

=PP5V_TPAD

=PP5V_TPAD_FET

MIN_LINE_WIDTH=0.5 mm

MAKE_BASE=TRUE

PP2V5_RUN

MIN_NECK_WIDTH=0.25 mm

VOLTAGE=2.5V

=PP1V8_RUN_RUNFET

=PP1V8_GPU_PANEL_IO

=PP1V8_GPU

=PP2V8_GPU_LVDS_IO

MAKE_BASE=TRUE

PP2V8_GPU_LVDDR

MIN_NECK_WIDTH=0.25 mm

VOLTAGE=2.8V MIN_LINE_WIDTH=0.38 mm

=PP2V8_GPU_LVDDR_LDO

=PP5V_FAN2_PWR

=PP1V8_GPU_DVO

=PP3V3_PCI_AIRPORT =PP3V3_RUN_PCI1510_R =PP3V3_RUN_HDD =PP3V3_GPU_CLOCKS =PP3V3_RUN_FWPORTPWRSW =PP3V3_RUN_FANTACH

=PPVOUT_CPU0_AVDD

PPAVDD_CPU0

MAKE_BASE=TRUE VOLTAGE=1.22V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

=PPAVDD_CPU0

=PP1V5_PWRON_I2PLL_LDO

=PP5V_RUN_PWRSEQ

=PP1V5_PWRON_I2_USBPLL

PP1V5_PWRON_I2PLL

VOLTAGE=1.5V MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

MAKE_BASE=TRUE

=PP1V5_PWRON_I2_PLL

=PP3V3_RUN_PWRSEQ

=PPJTAG_CPU

=PP5V_PWRON_AUDIO_AVDD =PP5V_PWRON_AUDIO_PVDD =PP5V_PWRON_RIGHT_USB =PP5V_PWRON_SLEEPLED =PP5V_PWRON_TRACKPAD =PP5V_PWRON_INVERTER

=PP1V5_GPU_PWRSEQ

MIN_LINE_WIDTH=0.38 mm

VOLTAGE=1.5V

PP1V5_GPU

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 mm

=PP1V5_GPU_DVO

=PP1V8R2V5_GPU_FB_VIO =PP1V8_FB_VDD =PP1V8_FB_VDDQ

=PP1V8_GPU_TPVDD

=PP1V8_GPU_AVDD

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

VOLTAGE=1.3V

MAKE_BASE=TRUE

PPVCORE_RUN_CPU

=PP1V8_GPU_MEMVMODE

PP1V8_GPU

MAKE_BASE=TRUE VOLTAGE=1.8V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

=PP1V8_RAM_I2_VREF =PP1V8_RUN_TBEN_SYNC

PP1V8_RUN

MAKE_BASE=TRUE MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.25 mm

VOLTAGE=1.8V

PP12V8_ALL_PBUSB

MAKE_BASE=TRUE MIN_LINE_WIDTH=0.5 mm

VOLTAGE=12.8V MIN_NECK_WIDTH=0.25 mm

=PP3V3_PWRON_VGASYNC

=PP3V3_PWRON_DS1775

=PP3V3_PWRON_AUDIO_AVDD

=PP3V3_PWRON_BT

=PP3V3_PCI_ROM

=PP3V3_PWRON_VDDSPD

=PP3V3_I2_PCISLOTEGPIOS =PP3V3_PWRON_I2_AGPPCI

=PPVIN_ALL_BATT_CHGR

=PP5V_PWRON_CPUVCORE_VDD

=PP5V_PWRON_CPUVCORE_PWRSEQ

=PP5V_PWRON_GPUVCORE_PWRPLAY

=PP5V_PWRON_LTC1778_GPU_EXTVCC

=PP5V_PWRON_TPS2211

=PP5V_PWRON_MAX1715_VDD

=PP1V2_ENETFW

=PP3V3_FW

=PP3V3_VESTA_1V2REG

PP1V5_RUN

MAKE_BASE=TRUE MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.25 mm

VOLTAGE=1.5V

=PP3V3_PWRON_LEFT_ALS

=PP3V3_PWRON_PMU

=PP3V3_ADT7467

=PP3V3_PWRON_TPS2211

=PP3V3_PWRON_LTC3412

=PP3V3_PWRON_RUNFET

=PP3V3_PWRON_MMM

=PP12V8_PBUS_PMU_SUPPLY

=PP3V3_PWRON_USB2

=PP3V3_PWRON_I2_MAXBUS

=PP2V7R5V5_PWRON_I2VCORE

=PP3V3_PWRON_LCD =PP3V3_PWRON_INVERTER

=PP3V3_PWRON_I2_IO1 =PP3V3_PWRON_I2_IO2 =PP3V3_PWRON_PWRSEQ =PP3V3_ENET

=PPI2C_SYS1

=PP3V3_AUDIO_MUTESEQ

=PP3V3_ALL_HALL_EFFECT

=PPI2C_I2_NB

=PPVREF_PMU

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

MAKE_BASE=TRUE VOLTAGE=5V

PP5V_PWRON_REG

PP3V3_PWRON_REG

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=3.3V

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=1.3V

MAKE_BASE=TRUE

PPVCORE_GPU_REG

VOLTAGE=1.5V

MAKE_BASE=TRUE

PPVCORE_PWRON_I2_REG

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

GND

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=0V

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

34

67

33

47

66

41

7

74

7

32

7

56

25

64

31

55

44

31

65

69

64

53

31

48

50

41

69

70

31

20

45

7

16

43

32

38

40

16

20

67

17

16

17

7

15

7

15

7

13

12

52

31

18

8

24

65

28

22

9

7

37

61

7

62

23

8

16

17

10

69

7

27

18

57

26

32

21

10

12 13

31

12

14

12

14

13

8

10

59

7

57

26

19

46

70

36 35

36

30

24

15

7

52

10

51

53

52

47

54

10 43

47

46

43 10

14 12

14

15

16

31

45

36

56

13

7

13

14

7

18

66

18

69

70

18

14

13

14

12

14

15

7

27

18

28

57

15

61

10

12

25

28

51

30 15

16

47 10

47 52

7

47

60

61

64

52

18

27

37 35

20

26

72

19

26

9

74

7

24

15

56

52

47

49

53

48

38

21

7

57

30

74

60

58

40

22

19

13

36

45

61

16

66

69

18

7

25

27

61

17

15

29

14

73

19

20

56

19

26

66

8

22

30

8

25

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

USB Controller Mux

USB Port Assignments

CPU Clocks

PCI

- I2S0_SYNC(_R)

- I2S0_BITCLK(_R)

I2S0 Series Rs

- I2S0_SB_TO_DEV_DTO(_R)

GPU

- I2S1_MCLK(_R)

- I2S1_BITCLK(_R)

- I2S1_SYNC(_R)

One resistor for each of:

- I2S1_SB_TO_DEV_DTO(_R)

I2S1 Series Rs

MISC

PMU Connections

Vesta Ethernet

- I2S0_MCLK(_R)

One resistor for each of:

I105

I106

I107

I108

MAXBUS_TBEN_SYNC

1/16W

5%

22

MF-LF

402

21

R1130

MAXBUS_TBEN_SYNC

5%

402

MF-LF

1/16W

10

21

R1111

402

MF-LF

1/16W

5%

22

21

R1120

22

1/16W

5%

MF-LF

402

21

R1137

402

USB2_I2

MF-LF

1/16W

5%

0

21

R1165

402

MF-LF

1/16W

5%

0

USB2_NEC

21

R1164

402

USB2_NEC

0

5% 1/16W MF-LF

21

R1166

402

0

5% 1/16W MF-LF

USB2_I2

21

R1167

402

USB1P1_NEC

0

5% 1/16W MF-LF

21

R1174

402

USB2_I2

0

5% 1/16W MF-LF

21

R1161

402

USB2_NEC

0

5% 1/16W MF-LF

21

R1160

402

MF-LF

1/16W

5%

0

USB2_NEC

21

R1162

402

USB2_I2

MF-LF

1/16W

5%

0

21

R1163

402

USB1P1_NEC

0

5% 1/16W MF-LF

21

R1170

402

0

5% 1/16W MF-LF

USB1P1_I2

21

R1175

402

MF-LF

1/16W

5%

0

USB1P1_NEC

21

R1176

402

USB1P1_I2

MF-LF

1/16W

5%

0

21

R1177

402

0

5% 1/16W MF-LF

USB1P1_I2

21

R1171

402

MF-LF

1/16W

5%

0

USB1P1_NEC

21

R1172

USB1P1_I2

402

MF-LF

1/16W

5%

0

21

R1173

22

MF-LF

1/16W

5%

402

21

R1135

22

5% 1/16W MF-LF

402

21

R1136

1/16W

5%

402

MF-LF

10

21

R1110

22

402

5% 1/16W MF-LF

21

R1140

100K

5% 1/16W MF-LF

402

2

1

R1185

SM-LF

1/16W

5%

33

5

6

7

8

4

3

2

1

RP1150

33

5%

1/16W SM-LF

5

6

7

8

4

3

2

1

RP1151

11

115

C

051-6929

SYNC_MASTER=N/A

SYNC_DATE=N/A

Signal Synonyms

USB_NEC_TPAD_P

MAXBUS_CLK_CPU0_R

=RP1150P5

=RP1150P6

=RP1150P7

TP_MAXBUS_CPU1_QACK_L

=ROM_PWD_L

=CPU0_VID_AB_SEL

MAKE_BASE=TRUE

PMU_CPU_CLK_EN

=I2_STOPCPU_L

=I2_STOPXTAL_L

MAKE_BASE=TRUE

SYS_PWRSEQ_FINAL

USB_I2_BT_N

PCI_SLOTD_GNT_L

PCI_SLOTD_INT_L

=ENET_TX_EN

=ENET_TX_ER

=ENET_TXD<7..0>

=ENET_RXD_R<7..0>

ENET_RXD<7..0>

MAKE_BASE=TRUE

=ENET_RX_DV_R

ENET_RX_DV

MAKE_BASE=TRUE

=ENET_RX_ER_R

MAKE_BASE=TRUE

ENET_RX_ER

=ENET_COL_R

MAKE_BASE=TRUE

ENET_COL

=ENET_CRS_R

MAKE_BASE=TRUE

ENET_CRS

=VESTA_CLK125M_GBE_REF

MAKE_BASE=TRUE

ENET_CLK125M_GBE_REF

=VESTA_CLK125M_RX

ENET_CLK125M_RX

MAKE_BASE=TRUE

=VESTA_CLK25M_TX

ENET_CLK25M_TX

MAKE_BASE=TRUE

=VESTA_MDC

MAKE_BASE=TRUE

ENET_MDC

=VESTA_MDIO

ENET_MDIO

MAKE_BASE=TRUE

ENET_TX_EN

ENET_TX_EN_R

MAKE_BASE=TRUE

ENET_TX_ER

ENET_TX_ER_R

MAKE_BASE=TRUE

ENET_TXD<7..0>

ENET_TXD_R<7..0>

=VESTA_ENERGYDET

MAKE_BASE=TRUE

TP_ENET_ENERGYDET

USB2_NEC_P<0>

MAKE_BASE=TRUE

USB2_NEC_LEFT_PORT_P

USB2_NEC_N<0>

MAKE_BASE=TRUE

USB2_NEC_LEFT_PORT_N

USB2_NEC_N<1>

MAKE_BASE=TRUE

USB2_NEC_RIGHT_PORT_N

USB2_NEC_P<1>

MAKE_BASE=TRUE

USB2_NEC_RIGHT_PORT_P

USB2_NEC_P<2>

MAKE_BASE=TRUE

USB_NEC_BT_P

USB2_NEC_N<2>

MAKE_BASE=TRUE

USB_NEC_BT_N

USB2_NEC_P<3>

MAKE_BASE=TRUE

USB_NEC_TPAD_P

USB2_NEC_N<3>

MAKE_BASE=TRUE

USB_NEC_TPAD_N

USB2_I2_P<0>

MAKE_BASE=TRUE

USB2_I2_LEFT_PORT_P

USB2_I2_N<0>

MAKE_BASE=TRUE

USB2_I2_LEFT_PORT_N

USB2_I2_N<2>

MAKE_BASE=TRUE

USB2_I2_RIGHT_PORT_N

USB2_I2_P<2>

MAKE_BASE=TRUE

USB2_I2_RIGHT_PORT_P

USB2_I2_P<4>

MAKE_BASE=TRUE

USB_I2_BT_P

USB2_I2_N<5>

MAKE_BASE=TRUE

USB_I2_TPAD_N

USB2_I2_N<4>

MAKE_BASE=TRUE

USB_I2_BT_N

USB2_I2_P<5>

MAKE_BASE=TRUE

USB_I2_TPAD_P

TP_PMU_P7_5

MAKE_BASE=TRUE

PMU_CHARGE_V

=ADT7467_THERM_L

MAKE_BASE=TRUE

SYS_OVERTEMP_L

=CPU_HRESET_L

MAKE_BASE=TRUE

PMU_CPU_HRESET_L

TP_GOV_RESET_L

MAKE_BASE=TRUE

GOV_RESET_L

TP_PMU_AN_P10_6

MAKE_BASE=TRUE

SYS_PMU_ANALOG_AC_DET

MAKE_BASE=TRUE

PMU_SYS_CLK_EN

=CPU0_MAX1717_AB_SEL

=SLEEP_LED_CONN

NC_MAXBUS_CPU1_QACK_L

MAKE_BASE=TRUE NO_TEST=YES

MAKE_BASE=TRUE

PCI_RESET_L

CPU0_VID_AB_SEL

MAKE_BASE=TRUE

I2_GPIO_EXT_02

SLEEP_LED_IOUT

MAKE_BASE=TRUE MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm

=SLEEP_LED_IOUT

CPU0_MAX1717_AB_SEL

MAKE_BASE=TRUE

=SPI_I2_REQ

ENET_RESET_L

=RP1151P1 =RP1151P2 =RP1151P3 =RP1151P4

=RP1151P8 =RP1151P7 =RP1151P6 =RP1151P5

MIN_NECK_WIDTH=0.15 mm

MIN_LINE_WIDTH=0.25 mm

VOLTAGE=0.75V

MAKE_BASE=TRUE

AGP_VREF

AGP_CLK66M_GPU

AGP_CLK66M_GPU_R

=AGP_GPU_RESET_L

MAKE_BASE=TRUE

PCI_RESET_L

=SI_TMDS_RESET_L

=GPU_AGP_VREF

=AGP_VREF

=I2_AGP_VREF

SI_TMDS_RESET_L

MAKE_BASE=TRUE

TP_EXTTMDS_RESET_L

=RP1150P1 =RP1150P2 =RP1150P3 =RP1150P4

=RP1150P8

=PCI_CLK33M_ZDB_IN

=CLK33M_TBEN_SYNC

=PCI_CLK33M_AIRPORT

=PCI_AIRPORT_REQ_L

=PCI_AIRPORT_GNT_L

=PCI_AIRPORT_INT_L

PCI_CLK33M_ZDB

MAKE_BASE=TRUE

PCI_CLK33M_TBEN_SYNC

MAKE_BASE=TRUE

PCI_CLK33M_AIRPORT

MAKE_BASE=TRUE

PCI_AIRPORT_INT_L

MAKE_BASE=TRUE

PCI_AIRPORT_GNT_L

MAKE_BASE=TRUE

PCI_SLOTA_GNT_L

MAKE_BASE=TRUE

PCI_AIRPORT_REQ_L

PCI_SLOTA_REQ_L

PCI_CLK33M_ZDB_R

MAKE_BASE=TRUE

TP_PCI_CLK33M_SLOTA_R

PCI_CLK33M_TBEN_SYNC_R

MAKE_BASE=TRUE

TP_PCI_CLK33M_SLOTD_R

PCI_CLK33M_AIRPORT_R

MAKE_BASE=TRUE

=PCI_CLK33M_ZDBOUT_R<0>

=PCI_AIRPORT_IDSEL

MAKE_BASE=TRUE

PCI_AD<17>

=PCI_AIRPORT_RESET_L

MAKE_BASE=TRUE

PCI_RESET_L

=PCI_CLK33M_CBUS

=PCI_CBUS_REQ_L

=PCI_CBUS_GNT_L

=PCI_CBUS_INT_L

=PCI_CBUS_IDSEL

MAKE_BASE=TRUE

PCI_AD<20>

=PCI_CBUS_RESET_L

MAKE_BASE=TRUE

PCI_RESET_L

=PCI_CLK33M_USB2

MAKE_BASE=TRUE

PCI_CBUS_REQ_L

PCI_SLOTD_REQ_L

PCI_CLK33M_CBUS

MAKE_BASE=TRUE

PCI_CBUS_GNT_L

MAKE_BASE=TRUE

PCI_CBUS_INT_L

MAKE_BASE=TRUE

PCI_CLK33M_USB2

=PCI_USB2_REQ_L

=PCI_USB2_GNT_L

=PCI_USB2_INT_L

=PCI_USB2_IDSEL

MAKE_BASE=TRUE

PCI_AD<21>

=PCI_USB2_RESET_L

MAKE_BASE=TRUE

PCI_RESET_L

PCI_USB2_GNT_L

MAKE_BASE=TRUE

PCI_SLOTE_GNT_L

PCI_USB2_REQ_L

MAKE_BASE=TRUE

PCI_SLOTE_REQ_L

PCI_USB2_INT_L

MAKE_BASE=TRUE

PCI_SLOTE_INT_L

MAKE_BASE=TRUE

PCI_CLK33M_CBUS_R

=PCI_CLK33M_ZDBOUT_R<1>

PCI_CLK33M_USB2_R

MAKE_BASE=TRUE

=PCI_CLK33M_ZDBOUT_R<2>

MAKE_BASE=TRUE

TP_PCI_CLK33M_ZDBOUT3

=PCI_CLK33M_ZDBOUT_R<3>

=MAXBUS_CPU0_CLK

=SYSCLK_TBEN_SYNC

MAXBUS_CLK_CPU0

MAKE_BASE=TRUE

MAXBUS_CLK_TBEN_SYNC

MAKE_BASE=TRUE

MAXBUS_CLK_CPU1_R

TP_MAXBUS_CLK_CPU1_R

DIFFERENTIAL_PAIR=USB_BT

NET_PHYSICAL_TYPE=USB2

NET_SPACING_TYPE=USB2

USB_BT_P

DIFFERENTIAL_PAIR=USB_BT

NET_PHYSICAL_TYPE=USB2

NET_SPACING_TYPE=USB2

USB_BT_N

DIFFERENTIAL_PAIR=USB_TPAD

NET_PHYSICAL_TYPE=USB2

NET_SPACING_TYPE=USB2

USB_TPAD_P

DIFFERENTIAL_PAIR=USB_TPAD

NET_PHYSICAL_TYPE=USB2

NET_SPACING_TYPE=USB2

USB_TPAD_N

NET_SPACING_TYPE=USB2 NET_PHYSICAL_TYPE=USB2 DIFFERENTIAL_PAIR=USB2_LT_PORT

USB2_LEFT_PORT_N

NET_SPACING_TYPE=USB2 NET_PHYSICAL_TYPE=USB2 DIFFERENTIAL_PAIR=USB2_RT_PORT

USB2_RIGHT_PORT_P

NET_SPACING_TYPE=USB2 NET_PHYSICAL_TYPE=USB2 DIFFERENTIAL_PAIR=USB2_RT_PORT

USB2_RIGHT_PORT_N

USB_NEC_BT_P

USB_I2_BT_P

USB_NEC_BT_N

USB_I2_TPAD_P

USB_I2_TPAD_N

USB_NEC_TPAD_N

USB2_NEC_LEFT_PORT_P

USB2_I2_LEFT_PORT_P

USB2_I2_LEFT_PORT_N

USB2_NEC_LEFT_PORT_N

USB2_I2_RIGHT_PORT_P

USB2_NEC_RIGHT_PORT_P

USB2_I2_RIGHT_PORT_N

USB2_NEC_RIGHT_PORT_N

PCI_SLOTA_INT_L

NET_SPACING_TYPE=USB2 NET_PHYSICAL_TYPE=USB2 DIFFERENTIAL_PAIR=USB2_LT_PORT

USB2_LEFT_PORT_P

TP_PMU_AN_P0_2

TP_PMU_AN_P0_3

MAKE_BASE=TRUE

SYS_PWRSEQ_3_L

TP_PMU_AN_P0_4

TP_PMU_AN_P0_5

TP_PMU_P7_4

MAKE_BASE=TRUE

SYS_PWRSEQ_6_L

TP_PMU_AN_P10_5

TP_PMU_AN_P0_1

TP_PMU_AN_P0_0

MAKE_BASE=TRUE

SYS_PWRSEQ_5

MAKE_BASE=TRUE

SYS_PWRSEQ_TPAD_L

MAKE_BASE=TRUE

SYS_PWRSEQ_1

MAKE_BASE=TRUE

SYS_PWRSEQ_2

MAKE_BASE=TRUE

SYS_PWRSEQ_4

TP_PMU_P3_3

MAKE_BASE=TRUE

TP_PMU_P3_2

MAKE_BASE=TRUE

TP_PMU_P3_1

MAKE_BASE=TRUE

TP_PMU_P3_0

MAKE_BASE=TRUE

62

61

62

11

30

60

61

11

59

65

9

11

6

11

25

55

6

59

25

59

25

6

60

25

30

74

31

11

6

11

59

74

6

32

6

32

58

36

25 22

22

26

6

59

22

66

9

66

9

66

9

66

9

66

9

66

65

66 65

66

9

66

9

65

66

73

6

73

6

73

6

73

6

73

6

73

2

73

6

73

6

72

6

72

6

72

6

72

6

72

6

72

6

72

6

72

6

25 13

27

7

34 25

25

25 12

25

36

30

11

22

24

22

65

6

44 43

44 11

54

44

43

51

6

23

21

60

59

23

60 58

60 11

61

61 58

61 11

62

59

62

62 59

62 11

22

23

33

21 32

60

7

6

2

6

22

7

25

25 26

25

25 26

25

26

25

G

D

S

G

D

S

V-

V+

GND

OUT

VIN+ VIN-

V+

G

D

S

V-

V+

G

D

S

G

D

S

GATE

D4 D3

D2

D1

S2

S3

S1

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

SPACING

PHYSICAL

DIFFERENTIAL_PAIR

to facilitate design reuse)

(Connector is on separate page

Adapter Connector Side

ADAPTER INPUT/INRUSH LIMITER

GREATER THAN 13.1V DETECT

signal to enable use of AC in system. Q1208 ensures SYS_ACIN goes low as soon as SYS_AC_DET goes low. Therefore, hardware immediately disables the AC upon removal but only software can enable AC after detection by the PMU.

System Side

AIRLINE

Q11 (65W) A29 (45W)

ADAPTER

ADAPTER IDs ID RANGE

0.33-0.99V

2.31-2.97V

1.65-2.31V

A29 ADAPTER DETECTION

0.589-0.663V

PIN VOLTAGE

2.007-2.066V

2.558-2.661V

BATTERY INPUT/CURRENT SENSE

(BATT_IN_PD)

SYS_AC_DET indicates adapter presence. SYS_ACIN is code-controlled

402

MF-LF

1/16W

5%

470K

1

2

R1209

805

CERM

50V

20%

0.1uF

1

2

C1210

330K

5% 1/16W MF-LF

402

1

2

R1210

402

CERM

16V

20%

0.01uF

2

1

C1200

1M

402

MF-LF

1/16W

5%

21

R1206

1% 1/16W

402

20.0K

MF-LF

1

2

R1201

100K

1% 1/16W MF-LF

402

2

1

R1204

97.6K

1% 1/16W MF-LF

402

1

2

R1202

57.6K

1% 1/16W MF-LF

402

1

2

R1205

402

MF-LF

1/16W

1%

10K

1

2

R1203

10K

5% 1/16W MF-LF 402

2

1

R1208

470K

5% 1/16W MF-LF

402

1

2

R1207

SOT-363

2N7002DW-X-F

4

5

3

Q1215

SOT-363

2N7002DW-X-F

1

2

6

Q1208

LMC7211

SM-LF

2

5

1

3

4

U1200

10UF

20% 4V X5R 603

2

1

C1252

1% 1/16W MF-LF

402

49.9K

21

R1252

SM

21

XW1252

1% 1W

MF-LF

2512

0.006

21

R1250

SM

21

XW1251

402

MF-LF

1/16W

1%

249K

2

1

R1251

INA138

CRITICAL

SOT23-5-LF

43

5 1

2

U1250

CERM

10V

20%

0.1UF

402

2

1

C1250

402

MF-LF

1/16W

5%

100K

2

1

R1228

0.1uF

20% 10V CERM 402

2

1

C1220

SOT23-LF

2N7002

2

1

3

Q1220

MF-LF

402

1/16W

5%

4.7M

21

R1227

LMC7211

SM-LF

2

5

1

3

4

U1220

52.3K

1% 1/16W MF-LF 402

2

1

R1225

100K

1% 1/16W MF-LF 402

1

2

R1221

402

MF-LF

1/16W

1%

127K

2

1

R1226

402

MF-LF

1/16W

1%

100K

2

1

R1222

1%

402K

402

MF-LF

1/16W

2

1

R1223

402

MF-LF

1/16W

5%

10K

21

R1224

FERR-50-OHM

SM-LF

21

L1250

FERR-EMI-100-OHM

SM

21

L1253

FERR-EMI-100-OHM

SM

21

L1254

SM

FERR-EMI-100-OHM

1

2

L1252

SM-LF

FERR-50-OHM

21

L1251

M-RT-SM

87438-0832

CRITICAL

8

7

6

5

4

3

2

1

J1250

SOT-363

2N7002DW-X-F

4

5

3

Q1208

10K

5% 1/16W MF-LF 402

2

1

R1215

SOT-363

2N7002DW-X-F

1

2

6

Q1215

402

MF-LF

1/16W

5%

10K

2

1

R1216

I317

I318

1K

5% 1/16W MF-LF

402

21

R1255

402

MF-LF

1/16W

5%

470K

2

1

R1256

SOI

IRF7416BF

3 2 1

4

8 7 6 5

Q1210

Power Inputs

C

051-6929

115

12

SYNC_MASTER=N/A

SYNC_DATE=N/A

=I2C_BATT_SDA

=I2C_BATT_SCL

MAKE_BASE=TRUE

BATT_ISNS

VOLTAGE=12.8V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

PPVBATT_BATT_RAW

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

VOLTAGE=12.8V

PPVBATT_ISNS_VINP

VOLTAGE=12.8V

PPVBATT_ISNS_VINN

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm

=PPVBATT_ISNS_N

=PP4V85_ALL_A29_DET

A29_DETECT

=PP3V3_ALL_A29_DET

A29_DET_L

A29_DET_REF

SYS_ADAPTER_ANALOG_AC_DET

ANALOG_AC_DET

SYS_PMU_ANALOG_AC_DET

BATT_ISNS_R

AC_ENABLE_L

SYS_ACIN_L

SYS_ACIN

SYS_AC_DET_L

=PP3V3_ALL_AC_DETECT

SYS_AC_DET

1V20_REF

AC_DET_DIV

BATTERY_ISNS

PPVBATT_ISNS_VINN

THERMTHERM

BATTERY_ISNS

PPVBATT_ISNS_VINP

THERMTHERM

SYS_BATT0_DET_L

=PPVBATT_BATT_VSNS

=PP3V3_BATT_IMON

PPVBATT_BATTPOS_CONN

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

VOLTAGE=10.8V

VOLTAGE=0V

GND_BATT_CONN

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

BATT_DATA

BATT_CLK

BATT0_DET_L

=PP3V3_ALL_BATT0_DET

PP24V_ADAPTER_SW

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=24V

AC_ENABLE_GATE

=PP24V_ADAPTER_RAW

25

74

18

25

8

25

12 12

10

13

10

7

11

13

24

10

25

14

12

24

10

13

10

CSIP CSIN

BATT

PGND

DLO

LX

DHI

BST

DLOV

LDO

CELLS

GND

CSSNCSSP

REF

CCS

CCI

CCV

IINP

ICHG

ICTL

VCTL

RFIN

ACOK

ACIN

DCIN

CLS

G

D

S

G

D

S

G

D

S

G

D

S

G

D

S

G

D

S

G

D

S

G

D

S

G

D

S

G

D

S

G

D

S

D

G

D

S

GND

OUT

PG

RS-

V+

RS+

NC2

NC1

GATE

D4 D3

D2

D1

S2

S3

S1

GATE

D4 D3

D2

D1

S2

S3

S1

V-

V+

TABLE_5_ITEM

REFERENCE DESIGNATOR(S)

BOM OPTION

TABLE_5_HEAD

QTY

DESCRIPTION

PART#

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

BATTERY SWITCH-OVER CIRCUIT

+PBUS CURRENT LIMIT

VCTL

REFIN

ICTL

_62

OD OUTPUT LOW - WHEN AC GREATER THAN 18V

(+3V_PMU)

PLACE U1370 NEXT TO R1300

PROTECTION

ROUTE LTC1625_ITH CAREFULLY

PLACE R383 CLOSE TO LTC1625

V = CELLS X (4.096 + (0.4096 * V / V ))

BATT For 4.15V cells, VCTL = 0.123 REFIN For 4.20V cells, VCTL = 0.245 REFIN

CHG

I = (0.2048/R ) * (V / V )

CHARGE THROTTLED BY LOW BATTERY VOLTAGE

PMU SELECTS BETWEEN TWO VOLTAGES

RC TIME IS 480K*10UF @ +3V_PMU

WHEN AC IS NOT PLUGGED, P-CHANNEL FETS ARE ON

WHEN AC IS IN, P-CHANNEL FETS ARE QUICKLY (DIODE) TURNED OFF

(GND)

NC

SWITCHER VOLTAGE CONTROL

CHARGE DISABLED BY PMU OR INPUT VOLTAGE <18V

SWITCHER CURRENT CONTROL

Place close to RS-

BACKFEED

IS

QSOP-LF

CRITICAL

MAX1772

15

13

4

20

23

2

28

14 10

98

22

21

24

1

27 26

19 18

3

16

7

5

6

25

17

12

11

U1300

1uF

20% 10V CERM 603

2

1

C1317

402

5%

47K

1/16W MF-LF

2

1

R1390

402

MF-LF

1/16W

5%

10K

2

1

R1391

SM-LF

5AMP-125V

2

1

F1390

SM-LF

5AMP-125V

2

1

F1395

1% 1/16W

1K

MF-LF 402

2

1

R1324

1% 1/16W MF-LF

402

1K

2

1

R1323

MF-LF

1206

1/4W

5%

33

21

R1319

MF-LF

1/16W

100K

402

5%

2

1

R1317

SOT-363

2N7002DW-X-F

4

5

3

Q1392

1/16W

158K

1% MF-LF

402

2

1

R1392

MMBD914XXG

SOT23

31

D1319

47K

5% 1/16W MF-LF

402

2

1

R1395

10K

5% 1/16W MF-LF

402

2

1

R1396

1

603

MF-LF

5%

1/10W

2

1

R1304

SOT-363

2N7002DW-X-F

1

2

6

Q1340

SOT-363

2N7002DW-X-F

4

5

3

Q1340

603

CERM

25V

20%

0.1uF

2

1

C1319

5% 1/16W MF-LF

402

100K

2

1

R1340

603

X5R

20%

6.3V

10uF

2

1

C1392

2N7002DW-X-F

SOT-363

1

2

6

Q1348

402

MF-LF

1/16W

1%

10K

2

1

R1346

2N7002DW-X-F

SOT-363

4

5

3

Q1348

2N7002DW-X-F

SOT-363

1

2

6

Q1347

402

5% 1/16W MF-LF

100K

2

1

R1347

SOT-363

2N7002DW-X-F

4

5

3

Q1347

20% 50V

CERM

805

0.1uF

2

1

C1320

SOT-363

BAS16TW-X-F

5 2

DP1390

SOT-363

BAS16TW-X-F

43

DP1390

4.7uF

20% 25V CERM 1206

2

1

C1305

100K

1/16W

5%

402

MF-LF

2

1

R1318

4.7uF

20%

25V CERM 1206

2

1

C1306

4.7uF

20%

25V CERM 1206

2

1

C1308

4.7uF

20% 25V CERM 1206

2

1

C1307

402

MF-LF

1/16W

1%

4.12K

2

1

R1329

MF-LF

10K

402

1/16W

1%

2

1

R1328

SO-8-LF

CRITICAL

IRF7811W

321

4

8765

Q1301

1/16W

402

MF-LF

5%

4.7

2

1

R1301

SOT23-5-LF

LMC7111

2

5

1

3

4

U1380

SOT-363

2N7002DW-X-F

1

2

6

Q1384

SOT-363

2N7002DW-X-F

4

5

3

Q1384

1/16W

5% MF-LF

402

4.7

2

1

R1302

SOT-363

BAS16TW-X-F

6 1

DP1390

1uF

20%

CERM

603

10V

2

1

C1384

CERM

50V

0.47UF

10%

1206

2

1

C1301

6.34K

1/16W

402

1%

MF-LF

2

1

R1330

MBRS140XXG

SMB

2

1

D1300

50V CERM 1206

0.47UF

10%

2

1

C1302

SOT-363

2N7002DW-X-F

1

2

6

Q1330

SOT-363

2N7002DW-X-F

4

5

3

Q1330

SUD45P03

CRITICAL

TO-252-LF

3

1

4

Q1395

0.0022UF

50V CERM 402

10%

NO STUFF

2

1

C1321

10%

2.2UF

50V X7R 1206

2

1

C1312

X7R 1206

10%

2.2UF

50V

2

1

C1313

X7R

1206

10%

50V

2.2UF

2

1

C1316

1206

2.2UF

10% 50V X7R

2

1

C1314

50V

10%

2.2UF

X7R 1206

2

1

C1315

1/16W MF-LF

47K

402

5%

2

1

R1360

68K

5%

402

MF-LF

1/16W

2

1

R1361

CERM

0.01UF

20% 50V

603

2

1

C1361

SOT-363

2N7002DW-X-F

1

2

6

Q1392

0.1UF

603-1

X7R

50V

10%

2

1

C1371

603

0.01uF

CERM

20% 50V

2

1

C1370

MF-LF

2.21k

0.1%

1/16W

603

CRITICAL

2

1

R1370

TSSOP-LF

MAX4172

CRITICAL

8

21

7

64

3

5

U1370

MF-LF

1/16W

0.1%

42.2K

CRITICAL

603

2

1

R1380

CERM

10V

20%

0.1uF

402

2

1

C1380

CRITICAL

51.1K

0.1% 1/16W MF-LF 603

2

1

R1383

MF-LF

1/16W

0.1%

42.2K

603

CRITICAL

2

1

R1381

MF-LF

CRITICAL

1/16W

0.1%

82.5K

603

2

1

R1382

1K

1% 1/16W MF-LF

402

2 1

R1386

150

1% 1/16W MF-LF

402

2 1

R1387

10K

1% 1/16W MF-LF

402

2 1

R1385

MF-LF

1/16W

5%

100K

402

2

1

R1384

1uF

20% 10V

603

CERM

2

1

C1327

402

MF-LF

1/16W

1%

100K

2

1

R1321

20% 10V

CERM

0.1uF

402

21

C1386

0.025

1% 1W MF

CRITICAL

2512-1

21

R1300

CRITICAL

33uF

20% 25V ELEC SM1-LF

2

1

C1311

SOI

IRF7416BF

3 2 1

4

8 7 6 5

Q1360

IRF7416BF

SOI

CRITICAL

3 2 1

4

8 7 6 5

Q1390

402

MF-LF

1%

1/16W

12.7K

2

1

R1322

1uF

20% CERM

1210

50V

2

1

C1303

CRITICAL

10uH

SM1-LF

21

L1300

0.05

1W

1%

MF-LF

2512

21

R1303

1

603

MF-LF

1/10W

5%

2

1

R1305

0.01uF

CERM

16V

20%

402

2

1

C1326

603

CERM

0.1uF

25V

20%

2

1

C1322

603

CERM

25V

20%

0.1uF

2

1

C1323

1% 1/16W MF-LF

402

27.4K

2

1

R1341

MF-LF

402

1/16W

1%

4.12K

2

1

R1342

10K

1% 1/16W MF-LF

402

2

1

R1344

402

MF-LF

1/16W

1%

OMIT

20.0K

2

1

R1345

1% 1/16W MF-LF 402

5.23K

2

1

R1343

402

0.01uF

CERM

16V

20%

2

1

C1325

402

1%

MF-LF

1/16W

1K

2

1

R1348

CRITICAL

RLA130N03

SO8

321

4

8765

Q1300

LMC7211

SM-LF

2

5

1

3

4

U1350

1/16W

1%

MF-LF

1K

402

2

1

R1325

100K

402

MF-LF

1/16W

1%

2

1

R1353

100K

402

MF-LF

1/16W

1%

2

1

R1354

1/16W MF-LF 402

1%

499K

2

1

R1351

402

MF-LF

1/16W

1%

100K

2

1

R1352

402

CERM

16V

10%

0.047uF

2

1

C1352

402

CERM

10V

20%

0.1uF

2

1

C1350

MMBD914XXG

SOT23

3

1

D1303

CERM 402

0.1uF

10V

20%

2

1

C1324

20% 25V CERM

4.7uF

1206

2

1

C1309

25V

CERM

20%

1206

4.7uF

2

1

C1310

SM

21

XW1300

5% 1/10W MF-LF 603

4.7

2

1

R1320

Primary is 260C/Alt is 250C part

126S0079126S0084

C1311

Battery Charger

13

115

051-6929

C

SYNC_MASTER=N/A

SYNC_DATE=N/A

RES,20K,1%,1/16W,MF-LF,402

114S0343

1

Q16C_PARTS

R1345

RES,48.7K,1%,1/16W,MF-LF,402

114S0382

1

Q41C_PARTS

R1345

1772_CSIN

1772_CSIP

PPVBATT_BATT_PBUSA_FUSE

MAKE_BASE=TRUE

PP24V_ADAPTER_SW

BKFD_PROT_GATE

=PP14VR24V_ALL_PBUS_A

=PPVBATT_BATT_PBUSA

BATT_24V_GATE

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=14V

PPVBATT_BATT_PBUSA_FUSE

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=24V

PP24V_ADAPTER_ILIM_P

IAC_RC_COMP

ADAPTER_I_REG

=PP3V3_ALL_PBUS_ILIM

AC_GTR_18V

LTC1625_ITH

1625_COMP

IAC_FB

MAX4172_OUT

CURRENT_THRESHOLD

A29_CURRENT_ADJ

OVER_18V_ADJ

=PP3V3_ALL_PBUS_ILIM

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

PPVOUT_BATT_CHRG_R

VOLTAGE=14V

1772_ICTL

1772_ACOK_L

1772_CSSP

1772_ICHG 1772_IINP

1772_VCTL

1772_BST_ESR

1772_BST

1772_DLOV

1772_CSSN

1772_CELLS

1772_CCV_RC

1772_CCV

BATT_LOW_L

CHARGE_DISABLE

BATTV_LOW

1772_CCS

1772_LDO

=PP3V3_ALL_BATT_CHGR

BATTV_HIGH

=PP3V3_ALL_BATT_CHGR

1V65_REF

A29_DETECT

A29_CLS_ADJ

1772_CCI

A29_DETECT

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

VOLTAGE=14V

PPVBATT_BATT_PBUSB_FUSE

=PPVBATT_BATT_PBUSB

BATT_14V_GATE

BATT_14PBUS_ENBATT_24PBUS_EN

SYS_ACIN

BKFD_PROT_EN_L

1772_ACIN

1772_ACOK_L

1772_DLO

1772_REF

=PPVIN_BATT_CHRG_VSNS

BATT_DIV

PP24V_ADAPTER_SW

1772_DCIN

=PPVBATT_BATT

BATT_LOW

1772_CLS

=PPVOUT_BATT_CHRG

PMU_CHARGE_V

SYS_ACIN_L

SYS_ACIN_L_RC

PMU_BATT0_CHARGE

1772_LX

=PPVIN_ALL_BATT_CHGR

1772_DHI

1772_GND

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=0V

25

13

18

13

12

10

13

10

14

10

13

10

12

10

12

13

10

12

10

11

12

25

10

V-

V+

G1

S1

D1

G2

D2

S2

SHUT

PLUS5VTAP

LP2951

ERR

FDBK

GND

SENSE

OUTIN

VTAP

IN OUT

SENSE

GND

FDBK

ERR

LP2951

SHUT

BOOST

SW

SGND PGND

TK

VIN

SYNC RUN/SS

VPROG

ITH FCB

INTVCC

TG

VOSENSE

BG

LTC1625

EXTVCC

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

PMU SUPPLY

NC

SUPERCAP HOOKS IN HERE

IF SUPERCAP BOM OPTION IS CHOSEN: OUTPUT AT U22.8 IS 5.4V

OUTPUT AT U23.1 IS 5.65V

NC

CONNECT LTC1625 TK PIN AT TOP-SIDE FET

12.8V PBUS SUPPLY

NC

KEEP VIN/TK LOOP SHORT

1625 IS SHUT-OFF

WHEN +24V_PBUS IS BELOW ~13.1V,

BOOTSTRAP SYSTEM FROM ADAPTER, MAIN BATTERY OR BACKUP BATTERY

NC

603

MF-LF

1/10W

5%

1

2

R1427

402

MF-LF

1/16W

1%

4.99K

1

2

R1425

SO8

RLA130N03

CRITICAL

321

4

8765

Q1400

MMBD914XXG

SOT23

3 1

D1420

10V 402

CERM

20%

0.1uF

2

1

C1400

402

158K

1% 1/16W MF-LF

2

1

R1401

16.2K

402

MF-LF

1/16W

1%

2

1

R1402

LMC7211

SM-LF

2

5

1

3

4

U1420

402

CERM

10V

20%

0.1uF

2

1

C1420

1%

1/16W

402

MF-LF

97.6K

2

1

R1420

10K

1/16W MF-LF

402

1%

2

1

R1421

1M

402

MF-LF

1/16W

1%

21

R1422

CRITICAL

FDG6324L

SC70-6-LF

1

5

6

Q1430

SC70-6-LF

FDG6324L

CRITICAL

4

3 2

6

Q1430

402

MF-LF

1/16W

5%

470K

2

1

R1430

603

MF-LF

5%

2.2

1/10W

2

1

R1410

4.7uF

1206

CERM

10V

20%

2

1

C1411

0

1/16W MF-LF 402

5%

NO STUFF

2

1

R1415

402

MF-LF

1/16W

5%

0

2

1

R1416

SM

21

XW1400

MBR0540XXG

SOD-123

21

D1450

390

5%

1/4W

MF-LF

1206

21

R1450

MBR0540XXG

SOD-123

21

D1452

1/10W MF-LF 603

5%

1

2

1

R1461

20%

603

X5R

6.3V

10UF

2

1

C1461

BACKUP_BATT

RB160M-60

SOD-123

21

D1460

RB160M-60

SOD-123

21

D1461

20% 10V CERM 402

0.1uF

2

1

C1460

BACKUP_BATT

603

1/10W MF-LF

5%

1

2

1

R1453

805

20% CERM

10V

2.2uF

BACKUP_BATT

2

1

C1453

470pF

10% 50V CERM 603

2

1

C1452

BACKUP_BATT

294K

1% 1/16W MF-LF

402

2

1

R1451

100K

1/16W

MF-LF

1%

402

2

1

R1452

402

0.1uF

20% 10V

CERM

2

1

C1451

SOI-LF

3

2

6

18

4

7

5

U1450

0.1uF

20%

805

CERM

50V

2

1

C1450

0.0047uF

25V CERM 402

10%

NO STUFF

2

1

C1412

SO-8-LF

CRITICAL

IRF7811W

321

4

8765

Q1401

MBRS140XXG

SMB

2

1

D1400

MMBD914XXG

SOT23

31

D1451

SM1

CRITICAL

8.0uH-6.8A

3

1

2

L1400

10%

1206

X7R

50V

2.2UF

2

1

C1403

2.2UF

10%

1206

X7R

50V

2

1

C1405

1206

X7R

50V

10%

2.2UF

2

1

C1407

2.2UF

10% 50V X7R 1206

2

1

C1404

2.2UF

10% 50V X7R 1206

2

1

C1406

2.2UF

10% 50V X7R 1206

2

1

C1408

SOI-3.3V-LF1

6

3

2

18

4

7

5

U1460

805

25V

20% CERM

0.22uF

2

1

C1410

4.7uF

20%

25V CERM 1206

2

1

C1402

25V 1206

CERM

20%

4.7uF

2

1

C1401

MBR0540XXG

SOD-123

21

D1410

CRITICAL

SSOP-LF

8

7

16 15 13

2

14

639

5

11

4

1

12

10

U1400

603

CERM

25V

5%

4700pF

2

1

C1421

603

CERM

50V

10%

470pF

2

1

C1425

805

CERM

50V

20%

0.1uF

2

1

C1427

603

CERM

25V

5%

4700pF

2

1

C1426

R1451

RES,MF-LF,1/16W,357K OHM,1%,0402,SMD

114S0465

?

SUPERCAP

1

12.8V PBUS/PMU Supplies

SYNC_DATE=N/A

C

051-6929

14

115

SYNC_MASTER=N/A

1625_FCB

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=5V

1625_INTVCC

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

1625_TG

PPVIN_ALL_ADAPT_OR_BATT

VOLTAGE=18V MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

FB_4_85V_BU

=PP4V85_ALL_VREG

=PP3V3_ALL_VREG

3V_PMU_VTAP

1625_VSW

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

VOLTAGE=4.6V

PP4V85_ALL_ESR

=PP24V_ADAPTER_PMU_SUPPLY

PP24V_ADAPT_PMU_ILIM

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

VOLTAGE=24V

=PP12V8_PBUS_PMU_SUPPLY

=PPVBATT_BATTERY_PMU_SUPPLY

1625_BST_ESR

COMP_RC

1625_COMP

=PP12V8_LTC1625_VREG

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

1625_BG

VOLTAGE=0V MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

1625_SGND

1625_RUNSS

1625_VIN

=PP3V3_ALL_LTC1625_SW

1625_DIV

1V20_REF

1625_VFB

1625_BST

=PP5V_SUPERCAP

PP3V3_ALL_ESR

MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm

VOLTAGE=3.3V

=PP5V_PWRON_LTC1625_EXTVCC

1625_ENABLE_L

1625_ENABLE

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

VOLTAGE=5V

PP5V_LTC1625_EXTVCC_SW

=PPVIN_ALL_LTC1625

PP4V6_ALL_RAW

MAKE_BASE=TRUE VOLTAGE=4.6V MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm

=PP5V_PWRON_PMU_SUPPLY

10

10 10

10

13

10

12

10

SGND PGND

STBYMD

FCB FREQSET

SNS1-

PGOOD

VOSNS2

VOUT

3.3

VCCVCC

EXT INT VIN

TG2

SW2

SNS2-

BG2

SNS2+

BOOST2

ITH2 RUN/

SS2SS1

SNS1+

BG1

SW1

BOOST1

TG1

VOSNS1 ITH1 RUN/

G

D

S

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

3V START TO TURN ON ~25MS AFTER =5V3V3PWRON_EN_L goes low

5V START TO TURN ON ~12.5MS =5V3V3PWRON_EN_L goes low

POWERDOWN DELAY IS AROUND 4MS-15.6MS, VIA RC NETWORK

DIODE WILL ENSURE REGULATOR TURNS ON QUICKLY

NC

3.3V/5V SWITCHER

SSOP-LF

LTC3707

CRITICAL

12

4

24

1627

1726

6

9

13

14

3

2

15

1

28

20

11

8

21

5

7

22

1825

1923

10

U1500

402

10

5% 1/16W MF-LF

2

1

R1502

MF-LF

CRITICAL

1/4W

1%

0.005

1206

21

R1551

805

CERM

25V

20%

0.22uF

2

1

C1511

0.01uF

402

CERM

16V

20%

21

C1585

SI3443DV

TSOP-LF

4

3 6

5 2 1

Q1585

SI3443DV

TSOP-LF

4

3 6

5 2 1

Q1580

20% 10V

CERM

402

0.1uF

21

C1580

10UF

20%

6.3V X5R 603

2

1

C1581

2.2

5% 1/10W MF-LF 603

2

1

R1511

20% 50V

CERM

402

0.001uF

21

C1514

SI3443DV

TSOP-LF

4

3 6

5 2 1

Q1590

402

10%

0.0022uF

CERM

50V

12

C1590

402

MF-LF

1/16W

1%

113K

2

1

R1504

MBR0540XXG

SOD-123

2

1

D1511

SOD-123

MBR0540XXG

2

1

D1561

2.2

5% 1/10W MF-LF

603

2

1

R1561

SOT23

MMBD914XXG

3 1

D1533

402

MF-LF

1/16W

5%

1M

21

R1533

402

0.01uF

20% 16V CERM

2

1

C1533

603

X5R

6.3V

20%

10UF

2

1

C1586

402

MF-LF

1/16W

1%

21.5K

2

1

R1505

402

CERM

25V

5%

220pF

2

1

C1532

2N7002

SOT23-LF

2

1

3

Q1533

402

CERM

50V

5%

180pF

NO STUFF

2

1

C1504

1206

CERM

10V

20%

4.7uF

2

1

C1530

402

0.1uF

20% 10V CERM

2

1

C1560

MBRS140XXG

SMB

2

1

D1551

SMB

MBRS140XXG

2

1

D1501

402

CERM

16V

10%

0.047uF

2

1

C1510

IHLP-5050

CRITICAL

4.7uH

2 1

L1501

IHLP-5050

CRITICAL

4.7uH

21

L1551

402

CERM

50V

10%

0.0022UF

NO STUFF

2

1

C1565

402

CERM

50V

10%

0.0022UF

NO STUFF

2

1

C1515

TANT

6.3V

20%

330uF

CRITICAL

CASE-D4-LF

2

1

C1553

CRITICAL

TANT

330uF

20%

6.3V

CASE-D4-LF

2

1

C1503

SO8

RLA130N03

CRITICAL

3 2 1

4

8 7 6 5

Q1501

CRITICAL

RLA130N03

SO8

321

4

8765

Q1551

SO-8-LF

IRF7811W

CRITICAL

3 2 1

4

8 7 6 5

Q1502

SO-8-LF

IRF7811W

CRITICAL

321

4

8765

Q1552

1206

2.2UF

10% 50V X7R

2

1

C1570

1206

2.2UF

10% 50V X7R

2

1

C1571

1206

2.2UF

10% 50V X7R

2

1

C1572

1206

X7R

50V

10%

2.2UF

2

1

C1573

1206

X7R

50V

10%

2.2UF

2

1

C1522

1206

X7R

50V

10%

2.2UF

2

1

C1523

1206

2.2UF

10% 50V X7R

2

1

C1521

1206

X7R

50V

10%

2.2UF

2

1

C1520

805

0.22uF

20% 25V CERM

2

1

C1561

100UF

20%

6.3V POLY B2

C1587

100UF

20%

6.3V POLY B2

2

1

C1582

B2

POLY

6.3V

20%

100UF

2

1

C1591

SI3443DV

TSOP-LF

4

3 6

5 2 1

Q1535

10UF

20%

6.3V X5R 603

2

1

C1592

603

X5R

6.3V

20%

10UF

2

1

C1536

402

MF-LF

1/16W

5%

100K

TPAD_SEQ_PMU

2

1

R1535

402

CERM

50V

5%

180pF

NO STUFF

2

1

C1554

402

MF-LF

1/16W

1%

63.4K

2

1

R1554

402

MF-LF

1/16W

1%

20.0K

2

1

R1555

CERM

16V

20%

0.01uF

402

2

1

C1531

402

MF-LF

1/16W

5%

0

2

1

R1532

402

MF-LF

1/16W

1%

100K

2

1

R1530

402

MF-LF

1/16W

1%

100K

2

1

R1531

402

0.0022uF

10% 50V CERM

2

1

C1562

402

100pF

5%

50V

CERM

2

1

C1563

12.7K

1% 1/16W MF-LF 402

2

1

R1562

402

CERM

50V

10%

0.0022uF

2

1

C1512

CERM

50V

5%

100pF

402

2

1

C1513

402

MF-LF

1/16W

1%

15.0K

2

1

R1512

1210

CERM

10V

20%

22uF

2

1

C1552

1210

CERM

10V

20%

22uF

2

1

C1551

1210

CERM

10V

20%

22uF

2

1

C1502

1210

CERM

10V

20%

22uF

2

1

C1501

SM

2

1

XW1500

10

5% 1/16W MF-LF 402

2

1

R1503

402

MF-LF

1/16W

5%

10

2

1

R1552

402

MF-LF

1/16W

5%

10

2

1

R1553

MF-LF

0.005

1%

1/4W

CRITICAL

1206

21

R1501

20% 50V

CERM

402

0.001uF

21

C1564

1M

5% 1/16W MF-LF

402

2

1

R1510

1M

5% 1/16W MF-LF 402

2

1

R1560

15

115

C

051-6929

SYNC_MASTER=N/A

SYNC_DATE=N/A

5V/3.3V Supplies

=PP5V_PWRON_REG

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=5V

3707_INTVCC

3707_SGND

VOLTAGE=0V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

=PP5V_TPAD_FET

=5VPWRONTPAD_EN_L

=PP5V_PWRON_TRACKPAD

=PP5V_PWRON_RUNFET

5VRUN_EN_L

=PP5V_RUN_RUNFET

5VRUNHD_EN_L

=PP5V_RUN_HDDFET

5V3VPWRON_EN_L_RC

=5V3V3PWRON_EN_L

3707_STBYMD

5V_RUNSS

5V_ITH

5V_VOSNS

5V_SNSP

5V_BG

5V_BOOST

3V_RUNSS

3V_ITH

3V_SNSM

3V_SNSP

3V_BG

3V_BOOST

=PP5V_PWRON_LTC3707_EXTVCC

3V_VOSNS

=5V3VPWRON_PGOOD

5V_SNSM

3707_FSET

3707_FCB

=PP3V3_PWRON_REG

3V_RSNS

3V_ITH_RC

3V_BOOST_ESR

5V_BOOST_ESR

5V_ITH_RC

5V_RSNS

=PP3V3_RUN_RUNFET

3V3RUN_EN_L

=PP3V3_PWRON_RUNFET

5V_SW

5V_TG

3V_SW

=PPVIN_ALL_LTC3707

3V_TG

10

26

10

26

10

26

10

26

10

26

10

26

10

AGND

THRML

NC_28

NC_23

NC_15

BST2

OUT1

TON

PGOOD REF

DL1

LX1

DH1

VCC

BST1

ON2

ON1

ILIM2

ILIM1

OUT2

SKIP

DL2

LX2

PGND

DH2

VDD

V+

FB1

FB2

G

D

S

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Rb

Ra

Vout = 1.0V * (1 + Ra/Rb)

Ra

Rb

MAX1715_GND

1.5V/1.8V SWITCHER

NC

DIODE PROVIDE PROVIDE QUICK TURN-ON POWER DOWN DELAY 1.5MS TO 3.5MS

1uF

20% 10V CERM 603

2

1

C1632

20

5% 1/16W MF-LF

402

2 1

R1630

QSOP-LF

CRITICAL

MAX1715

2021

4

5

29

69

7

22

14

1

11

10

28

23

15

1627

12

3

13

2

1924

1726

1825

8

U1600

CRITICAL

4.7uH

SM4-LF

21

L1651

SO8

CRITICAL

RLA130N03

3 2 1

4

8 7 6 5

Q1651

CRITICAL

RLA130N03

SO8

321

4

8765

Q1601

158K

1% 1/16W MF-LF 402

2

1

R1671

158K

1% 1/16W MF-LF

402

2

1

R1621

SOT-363

BAS16TW-X-F

5 2

DP1620

603

MF-LF

1/10W

5%

4.7

21

R1670

603

MF-LF

1/10W

5%

4.7

21

R1620

603

0.1uF

20% 25V CERM

2

1

C1670

B130LBT01XF

SMB

2

1

D1651

5.11K

1% 1/16W MF-LF 402

2

1

R1651

10K

1/16W MF-LF 402

1%

2

1

R1652

603

0.1uF

20% 25V CERM

2

1

C1620

CRITICAL

4.7uH

SM4-LF

21

L1601

0

5% 1/16W MF-LF 402

2

1

R1634

402

1/16W MF-LF

5%

0

NO STUFF

2

1

R1633

330UF

20%

2.5V-ESR9V POLY

CASE-D2E-LF

2

1

C1653

150uF

20%

6.3V POLY CASE-D2-LF

2

1

C1604

1206

CERM

25V

20%

4.7uF

CRITICAL

2

1

C1601

1206

CERM

25V

20%

4.7uF

CRITICAL

2

1

C1602

1206

CERM

25V

20%

4.7uF

CRITICAL

2

1

C1652

4.7uF

1206

CERM

25V

20%

CRITICAL

2

1

C1651

NO STUFF

0

5% 1/16W MF-LF 402

2

1

R1631

NO STUFF

0

5% 1/16W MF-LF 402

2

1

R1632

B130LBT01XF

SMB

2

1

D1601

SM

21

XW1600

10UF

20%

6.3V X5R 603

2

1

C1686

603

X5R

6.3V

20%

10UF

2

1

C1603

603

X5R

6.3V

20%

10UF

2

1

C1655

805

CERM

10V

20%

2.2uF

2

1

C1631

CERM

10V

20%

2.2uF

805

2

1

C1630

SOT-363

BAS16TW-X-F

6 1

DP1620

402

MF-LF

1/16W

5%

330K

21

R1640

CERM

16V

20%

0.01uF

402

2

1

C1640

TSOP-LF

SI3446DV

4

36

5

2

1

Q1685

2N7002

SOT23-LF

2

1

3

Q1640

100K

5% 1/16W MF-LF

402

2

1

R1641

402

X7R

25V

10%

1000pF

2

1

C1685

10%

0.0022UF

CERM 402

50V

NO STUFF

2

1

C1621

0.0022UF

50V 402

CERM

10%

NO STUFF

2

1

C1671

1% 1/16W MF-LF

402

8.06K

2

1

R1601

10K

1% 1/16W MF-LF

402

2

1

R1602

IRF7805ZPBF

SO-8

CRITICAL

3 2 1

4

8 7 6 5

Q1652

SO-8

IRF7805ZPBF

CRITICAL

321

4

8765

Q1602

SOT-363

BAS16TW-X-F

4 3

DP1620

330UF

20%

2.5V-ESR9V CASE-D2E-LF

POLY

2

1

C1605

CRITICAL

TSSOP

SI6467BDQ-E3

7632

4

851

Q1680

603

10UF

20%

6.3V X5R

2

1

C1680

402

MF-LF

1/16W

5%

100K

2

1

R1680

5%

50V

CERM

2200pF

603

21

C1681

X7R

25V

10%

1000PF

NO STUFF

402

2

1

C1682

115

16

051-6929

C

SYNC_MASTER=N/A

SYNC_DATE=N/A

1.8V/1.5V Supplies

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=0V

MAX1715_GND

=PPVIN_ALL_MAX1715

1_8V_LX

1_5V_DH

=PPVIN_ALL_MAX1715

1_8V_DL

=1V8_1V5PWRON_EN_L

MAX1715_EN_L_RC

MAX1715_ON

=PPVIN_ALL_MAX1715

=PP5V_PWRON_MAX1715_VDD

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

VOLTAGE=5V

PP5V_MAX1715_VCC

1V5RUN_EN

=1V8_1V5PWRON_PGOOD

=PP1V5_PWRON_RUNFET

=PP1V5_RUN_RUNFET

1_5V_DL

1_5V_BST

MAX1715_REF

1_8V_FB

MAX1715_SKIP

1_8V_ILIM

MAX1715_GND

1_5V_ILIM

1_8V_BST

MAX1715_TON

1_5V_BOOST 1_8V_BOOST

=PP1V8_RUN_RUNFET

=PP1V8_PWRON_RUNFET

1V8RUN_EN_L

=PP1V8_PWRON_REG

1_8V_DH

1_5V_FB

1_5V_LX

=PP1V5_PWRON_REG

16

10

26

10 10

26

10 10

16

10

26

10

SW

SGND PGND

PAD

THERM

SVIN PVIN

PGOOD

VFB

ITH SYNC/MODE

RUN/SS

RT

G

D

S

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

2.5V SWITCHER

CONTINUOUS MODE

BURST MODE

1206-1

6.3V

20%

47uF

X5R

2

1

C1700

7.5K

1/16W MF-LF

1%

402

2

1

R1720

5%

CERM

603

2200pF

50V

2

1

C1721

SM

21

XW1700

TSSOP-LF

LTC3412

CRITICAL

4

17

6

15

14

11

10

1

8

7

5

16

9

2

13

12

3

U1700

402

100PF

5%

50V

CERM

2

1

C1720

110K

1% 1/16W MF-LF 402

2

1

R1731

402

75K

1% 1/16W MF-LF

2

1

R1732

CERM

50V

5.6pF

402

+/-0.25pF

2

1

C1730

402

1% 1/16W MF-LF

402K

2

1

R1730

402

10% 50V

CERM

470PF

2

1

C1722

402

MF-LF

1/16W

5%

4.7M

2

1

R1722

402

NO STUFF

0

5% 1/16W MF-LF

2

1

R1724

402

MF-LF

1/16W

5%

0

2

1

R1723

402

309K

1% 1/16W MF-LF

2

1

R1733

1.0uH-3.48A

SM-LF

CRITICAL

21

L1700

1206-1

20%

6.3V

47uF

X5R

2

1

C1701

CERM

6.3V

20%

22UF

1206

2

1

C1710

SOT-363

2N7002DW-X-F

4

5

3

Q1740

1000pF

402

X7R

25V

10%

21

C1780

SI6467BDQ-E3

TSSOP

7632

4

851

Q1780

603

10UF

20%

6.3V X5R

2

1

C1781

1206

CERM

6.3V

20%

22UF

2

1

C1711

2.5V Supply

SYNC_MASTER=N/A

SYNC_DATE=N/A

115

C

17

051-6929

=2V5PWRON_PGOOD

LTC3412_RUNSS

LTC3412_RT

=2V5PWRON_EN_L

=PP2V5_RUN_RUNFET

2V5RUN_EN_L

=PP2V5_PWRON_RUNFET

LTC3412_SW

LTC3412_VFB_DIV

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=0V

LTC3412_GND

LTC3412_VFB

=PP3V3_PWRON_LTC3412

LTC3412_SYNC

LTC3412_ITH_RC

LTC3412_ITH

=PP2V5_PWRON_REG

26

2

26

10

26

10

VESTA MISC

1 OF 3

PVDDDVDD

AVDDL

AVDD

GND

AGND

OVDD

REGSUP1 REGSEN1 REGCTL1

REGSUP2 REGSEN2 REGCTL2

2.5V_EN

NC

DNC

NC

TDO TCK TMS TRST*

TDI

RESET*

PVINSVIN

SHDN/RT SYNC/MODE

SW VFB ITH

PGOOD

PGND SGND

GND

VOUT

VIN

NOISE

CONT

G

D

S

G

D

S

G

D

S

ON/OFF

GND

VOUT

FB

VIN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

R1952 to enable wirespeed feature

Burst Mode

Mode

Continuous

Port Power Switch

1.2V Regulator

Page Notes

- =PPBUS_FW (system supply for bus power)

Signal aliases required by this page:

- =PP3V3_RUN_FWPORTPWRSW

- =PPBU_RUN_FW (backup PHY power)

regulator will be in continuous mode.

regulator. If both options are off the

Power aliases required by this page:

Controls operating mode of Vesta 1.2V

BOM options provided by this page:

Vout = 2.5V @ 150 mA

<R1>

2.5V LDO

<R2>

- VESTA1V2_BURST / VESTA1V2_PULSE

(NONE)

Vout = 1.199V @ 1.2 A

Vout = 0.8V * (1 + (R2 / R1))

3.3V Regulator

If =FWPWR_PWRON is NC:

Enables port power when machine is

If =FWPWR_PWRON is low when off:

running or on AC.

Pulse Mode

Vout = 3.3V @ 500mA

L6/M6 L9/M9

NC

N5/N6

N9/N10

NC?

running or on AC and not shut down.

NC

(Int PU)

Schmitt trigger

Reset circuit per Vesta design guide

10V

20%

402

CERM

0.1uF

2

1

C1910

10V

20%

402

CERM

0.1uF

2

1

C1911

10V

20%

402

CERM

0.1uF

2

1

C1912

10V

20%

402

CERM

0.1uF

2

1

C1913

0.1uF

CERM

402

20% 10V

2

1

C1903

10V

20%

402

CERM

0.1uF

2

1

C1902

CERM

10V

20%

402

0.1uF

2

1

C1901

0.1uF

20% 10V

402

CERM

2

1

C1900

0.1uF

CERM

402

20% 10V

2

1

C1922

0.1uF

CERM

402

20% 10V

2

1

C1925

0.1uF

CERM

402

20% 10V

2

1

C1921

0.1uF

CERM

402

20% 10V

2

1

C1924

0.1uF

402

20%

CERM

10V

2

1

C1931

0.1uF

CERM

402

20% 10V

2

1

C1930

0.1uF

CERM

402

20% 10V

2

1

C1920

0.1uF

CERM

402

20% 10V

2

1

C1923

0.1uF

20%

402

CERM

10V

2

1

C1943

0.1uF

CERM

402

20% 10V

2

1

C1942

0.1uF

CERM

402

20% 10V

2

1

C1941

0.1uF

CERM

402

20% 10V

2

1

C1940

10%

6.3V 402

CERM

1uF

2

1

C1950

BCM5462

FBGA-200

OMIT

D8

E8

E10

D7

E7

H4

E2

E1

F2

F1

G4

G5

N4

A15

K1

F15

A7

A1

M13

C3

K2

J2

F14

C14

B7B2A2

J1

C15

B15

B1

E9

C9

B9

N10

N9N6N5M9M6L9L6

R12R3P11

P10P5P4

N8N7M8M7L8

L7

J12

J11

P9P8P7

P6

H12

H11

M3

U8500

MF-LF

5%

402

1/16W

20K

2

1

R1950

10UF

X5R 603

20%

6.3V

2

1

C1908

SM

FERR-EMI-600-OHM

21

L1900

MSOP-LF

LTC3411

CRITICAL

9

2

4

7

1

3

6

8

5

10

U1990

50V

5%

402

CERM

100pF

2

1

C1993

1%

402

MF-LF

4.99K

1/16W

2

1

R1996

50V

402

CERM

0.0033uF

10%

2

1

C1994

CRITICAL

2.2uH

SM1-LF

21

L1990

50V

5%

402

CERM

22pF

2

1

C1992

1/16W

1%

402

MF-LF

4.99K

2

1

R1997

10K

1/16W

1%

402

MF-LF

2

1

R1998

20%

22uF

X5R 805

6.3V

2

1

C1995

402

CERM

1uF

10%

6.3V 2

1

C1991

10

MF-LF

402

5%

1/16W

21

R1990

10UF

X5R 603

20%

6.3V

2

1

C1990

1/16W

1%

402

MF-LF

324K

2

1

R1995

1M

MF-LF

402

5%

1/16W

2

1

R1994

402

1/16W

5%

MF-LF

1M

2

1

R1991

VESTA1V2_PULSE

1/16W

5%

402

MF-LF

10K

2

1

R1993

VESTA1V2_BURST

1/16W

5%

402

MF-LF

10K

2

1

R1992

SM

21

XW1990

0.01uF

CERM

402

20% 16V

2

1

C1981

402

CERM

1uF

10%

6.3V 2

1

C1980

10UF

X5R 603

20%

6.3V

2

1

C1982

330K

MF-LF 402

5% 1/16W

2

1

R1966

0.01uF

CERM

20% 16V

402

2

1

C1965

470K

MF-LF 402

5% 1/16W

2

1

R1965

SOT-363

BAS16TW-X-F

43

DP1960

SOT-363

BAS16TW-X-F

5 2

DP1960

BAS16TW-X-F

SOT-363

61

DP1960

1/16W

5%

402

MF-LF

10K

21

R1961

MF-LF

1/16W

5%

402

100K

2

1

R1960

1/16W

5%

402

MF-LF

470K

2

1

R1963

SOT-25A-LF

CRITICAL

MM1572FN

51

4

2

3

U1980

SMB

B340XF

CRITICAL

21

D1965

SOI-LF

CRITICAL

NDS9407

3 2

1

4

8

7

6 5

Q1965

MINISMDC

1.5A-24V

21

F1965

10K

MF-LF

402

5%

1/16W

2

1

R1952

SMD

MMBRM140XXG

2

1

D1970

SOT23-LF

2N7002

2

1

3

Q1960

MF-LF

5%

402

1/16W

10K

2

1

R1951

2N7002DW-X-F

SOT-363

1

2

6

Q1950

SOT-363

2N7002DW-X-F

4

5

3

Q1950

SC-59

SMD20E40C-X-F

3

2

1

D1975

CRITICAL

LM2594

SM-LF

8

7

56

4

U1970

50V

N20P20%

2320

CERM

10uF

2

1

C1970

100UF

B2

20%

6.3V POLY

CRITICAL

2

1

C1971

PLC

100uH-0.8A

CRITICAL

21

L1970

C

051-6929

19

115

Vesta Power & Misc

SYNC_MASTER=N/A

SYNC_DATE=N/A

=PP3V3_VESTA

VESTA_RESET_L_RC

VESTA_RESET

VESTA_RESET_L

VOLTAGE=25V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

PPBUS_FWPWRSW_F

=PPBUS_FWPWRSW

=PP2V5_VESTA

=PP3V3_VESTA

=PP1V2_VESTA

=PP3V3_VESTA

PP1V2_VESTA_AVDDL

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=1.2V

=JTAG_VESTA_TRST_L

=JTAG_VESTA_TMS

=JTAG_VESTA_TCK

=JTAG_VESTA_TDI =JTAG_VESTA_TDO

TP_VESTA_2_5V_EN

TP_VESTA_REGSUP1 TP_VESTA_REGSEN1

TP_VESTA_REGSUP2 TP_VESTA_REGSEN2

VESTA1V2_MODE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

FWPWR_EN_L

FWPWR_EN

=FWPWR_PWRON

=PP2V5_VESTA_LDO

=PP1V2_VESTA_REG

=PP3V3_VESTA_2V5REG

VESTA1V2_ITH

VESTA2V5_NOISE

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

=PPBUS_FW_FET

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=25V

PPBUS_FW_FET_D

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

FWPWR_EN_L_DIV

=PPBU_RUN_FW

=PPFW_P3V3VESTA

=PP3V3_VESTA_REG

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

VOLTAGE=33V

PPVIN_VESTA3V3

FWPWR_RUN

FWPWR_ACIN

SYS_ACIN

=PP3V3_RUN_FWPORTPWRSW

VESTA1V2_ITH_RC

VESTA1V2_VFB

VESTA1V2_SW

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

VESTA3V3_SW

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

VOLTAGE=0V

VESTA1V2_SGND

MIN_NECK_WIDTH=0.25 mm

VOLTAGE=3.3V MIN_LINE_WIDTH=0.5 mm

PPVOUT_VESTA1V2

=PP3V3_VESTA_1V2REG

VESTA1V2_RT

TP_VESTA_DNC_E9

TP_VESTA_DNC_C9

TP_VESTA_DNC_B9

TP_VESTA_REGCTL1

TP_VESTA_REGCTL2

67

66

65

25

18

13

10

66

10

9

2

26

10

12

10

2

VDD15_0

VDD15_1

VDD15_2

VDD15_3

VDD15_4

VDD15_5

VDD15_6

VDD15_7

VDD15_8

VDD15_9

VDD15_10

VDD15_11

VDD15_12

VDD15_13

VDD15_15

VDD15_14

VDD15_16

VDD15_17

VDD15_18

VDD15_19

VDD15_20

VDD15_21

VDD15_22

VDD15_23

VDD15_24

VSS_49

VSS_48

VSS_46 VSS_47

VSS_45

VSS_44

VSS_43

VSS_41 VSS_42

VSS_40

VSS_39

VSS_38

VSS_35 VSS_36 VSS_37

VSS_33 VSS_34

VSS_32

VSS_30 VSS_31

VSS_28 VSS_29

VSS_27

VSS_25 VSS_26

VSS_23 VSS_24

VSS_21

VSS_20

VSS_19

VSS_17 VSS_18

VSS_15

VSS_13

VSS_12

VSS_10 VSS_11

VSS_5

VSS_2 VSS_3 VSS_4

VSS_1

VSS_0

VSS_98 VSS_99

VSS_149

VSS_148

VSS_96 VSS_97

VSS_95

VSS_93 VSS_94

VSS_91 VSS_92

VSS_90

VSS_88 VSS_89

VSS_86

VSS_85

VSS_87

VSS_83 VSS_84

VSS_82

VSS_81

VSS_80

VSS_79

VSS_78

VSS_147

VSS_146

VSS_145

VSS_143 VSS_144

VSS_142

VSS_141

VSS_140

VSS_138 VSS_139

VSS_137

VSS_136

VSS_135

VSS_133 VSS_134

VSS_131 VSS_132

VSS_130

VSS_128 VSS_129

VSS_198 VSS_199

VSS_197

VSS_196

VSS_195

VSS_193 VSS_194

VSS_192

VSS_191

VSS_190

VSS_188 VSS_189

VSS_186 VSS_187

VSS_185

VSS_183 VSS_184

VSS_182

VSS_181

VSS_180

VSS_179

VSS_178

VSS_77

VSS_76

VSS_75

VSS_74

VSS_73

VSS_72

VSS_70 VSS_71

VSS_69

VSS_67 VSS_68

VSS_65 VSS_66

VSS_64

VSS_62 VSS_63

VSS_60 VSS_61

VSS_58

VSS_57

VSS_59

VSS_126 VSS_127

VSS_125

VSS_123 VSS_124

VSS_122

VSS_121

VSS_120

VSS_117 VSS_118 VSS_119

VSS_116

VSS_115

VSS_112

VSS_114

VSS_113

VSS_111

VSS_110

VSS_107

VSS_109

VSS_108

VSS_55 VSS_56

VSS_53

VSS_52

VSS_54

VSS_50 VSS_51

VSS_106

VSS_105

VSS_102 VSS_103 VSS_104

VSS_100 VSS_101

VSS_176 VSS_177

VSS_175

VSS_174

VSS_173

VSS_172

VSS_171

VSS_170

VSS_169

VSS_167 VSS_168

VSS_166

VSS_165

VSS_164

VSS_163

VSS_162

VSS_161

VSS_160

VSS_159

VSS_158

VSS_157

VSS_156

VSS_155

VSS_153 VSS_154

VSS_152

VSS_150 VSS_151

VSS_22

VSS_16

VSS_14

VSS_9

VSS_8

VSS_7

VSS_6

CORE POWER & GND

(1 of 14)

VDD33_47

VDD33_46

VDD33_45

VDD33_44

VDD33_41 VDD33_42 VDD33_43

VDD33_39 VDD33_40

VDD33_38

VDD33_37

VDD33_36

VDD33_34 VDD33_35

VDD33_33

VDD33_32

VDD33_31

VDD33_30

VDD33_29

VDD33_28

VDD33_27

VDD33_26

VDD33_24 VDD33_25

VDD33_23

VDD33_21 VDD33_22

VDD33_19 VDD33_20

VDD33_18

VDD33_16 VDD33_17

VDD33_15

VDD33_14

VDD33_13

VDD33_12

VDD33_11

VDD33_8

VDD33_5 VDD33_6 VDD33_7

VDD33_3 VDD33_4

VDD33_0

VDD33_2

VDD33_1

VDD33_9

VDD33_10

(2 of 14)

3.3V I/O POWER

PLL1_AVDD

PLL2_AVDD

PLL1_VSSA

PLL3_AVDD

PLL2_VSSA

PLL4_AVDD

PLL3_VSSA

PLL4_VSSA

PLL5_AVDD

PLL5_VSSA

PLL6_AVDD

PLL6_VSSA

PLL7_AVDD

PLL7_VSSA

PLL9_AVDD

PLL9_VSSA

AGP TRACK

PLL9

PCI TRACK

PLL7

PLL6

SYS TRACK

ATA

PCI AGP

INT REF

PLL5

SYSCLK

PLL4

AGP(SS)

PCI(SS)

49.15 MHZ

PLL3

45.16 MHZ

PLL2

32/48 MHZ

PLL1

(3 of 14)

PLL POWER

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

4 X 10uF (0603) 25 X 1uF (0402)

48 X 1uF (0402)

1 X 10uF (0603)

VCore Bypassing

(25 Balls on I2)

VDD33_IO_1 (14)

For USB, FireWire,

For GPIOs, Pwr Mgt

VDD33_IO_2 (12)

VDD33_PCI (18)

VDD33_

MAXBUS

- =PP1V5_PWRON_I2_PLL

Page Notes

I2S and some GPIOs

VDD33_AGP

(48 Balls on I2)

out separately for test purposes. NOTE: When these four rails are not aliased together, make sure there is at least one 10uF cap per rail.

(NONE)

BOM options provided by this page:

Signal aliases required by this page:

aliased together. They are called

NOTE: The four 3.3V rails are meant to be

- =PP3V3_PWRON_I2_MAXBUS

- =PP3V3_PWRON_I2_AGPPCI

- =PP3V3_PWRON_I2_IO2

- =PP3V3_PWRON_I2_IO1

- =PPVCORE_PWRON_I2

Power aliases required by this page:

3.3V I/O DECOUPLING

6.3V

10%

402

CERM

1uF

2

1

C2158

1uF

CERM 402

10%

6.3V

2

1

C2126

1uF

CERM 402

10%

6.3V

2

1

C2133

6.3V

20%

603

X5R

10UF

2

1

C2147

1uF

402

CERM

10%

6.3V

2

1

C2144

6.3V

10%

402

CERM

1uF

2

1

C2163

BGA

I2

OMIT

E29

E26

E23

E20

E2

E17

E14

E11

B8

B5

AB22

B35

B32

B29

B26

B23

B20

B2

B17

B14

B11

AB16

AR8

AR5

AR35

AR32

AR29

AR26

AR23

AR20

AR2

AR17

AB15

AR14

AR11

AM8

AM7

AM5

AM35

AM32

AM29

AM26

AM23

AB12

AM20

AM2

AM17

AM14

AM11

AJ8

AJ5

AJ35

AJ32

AJ29

AA29

AJ27

AJ26

AJ24

AJ23

AJ20

AJ2

AJ17

AJ14

AJ11

AH14

AA25

AG29

AG14

AG11

AF8

AF5

AF35

AF32

AF29

AF27

AF2

AA21

AF18

AF10

AE25

AE20

AE19

AE17

AE15

AE14

AD29

AD21

AA17

Y8

Y5

Y35

Y32

Y29

Y22

Y2

Y18

Y16

Y11

AD16

W26

W25

W21

W19

W15

V28

V20

V16

V12

U8

AC5

U5

U35

U32

U28

U25

U21

U2

U16

U13

T20

AC35

T18

T16

R29

R25

R22

R20

R19

R17

R15

R13

AC32

P8

P5

P35

P32

P29

P27

P24

P21

P2

P17

AC29

N25

N23

N18

N16

N14

M26

M23

M21

M19

M17

AC26

M15

M13

L8

L5

L35

L32

L29

L27

L20

L2

AC25

K29

K26

K25

K23

K20

K17

K14

K11

K10

H8

AC20

H5

H35

H32

H29

H27

H26

H24

H23

H20

H2

AC2

H18

H17

H15

H14

H12

H11

E8

E5

E35

E32

AB24

AA15

AA13

R21

R18

R16

P20

P16

N17

AC19

Y17

Y15

W22

W20

W18

AC16

V22

V19

V17

U22

U20

U18

U15

T22

T19

T15

AB21

AA22

U2100

1uF

CERM 402

10%

6.3V

2

1

C2139

1uF

CERM 402

10%

6.3V

2

1

C2138

BGA

I2

OMIT

N13

L6

L3

L10

J8

AP32

AP29

AP26

AP23

AL30

AL29

AL27

AL26

H6

AL24

AL23

AH27

AH26

AH24

AH23

AH20

AD22

AD20

AC21

H3

M22

M18

M16

Y13

AM3

AJ6

AJ3

AF9

AF6

AF3

F5

AF11

AC6

AC3

AC15

AB13

T13

R14

P6

P3

P12

E3

AH17

U2100

6.3V

10%

402

CERM

1uF

2

1

C2169

6.3V

10%

402

CERM

1uF

2

1

C2168

6.3V

10%

402

CERM

1uF

2

1

C2152

6.3V

10%

402

CERM

1uF

2

1

C2151

1uF

CERM 402

10%

6.3V

2

1

C2132

1uF

CERM 402

10%

6.3V

2

1

C2131

1uF

CERM 402

10%

6.3V

2

1

C2130

1uF

6.3V

10%

402

CERM

2

1

C2101

1uF

6.3V

10%

402

CERM

2

1

C2102

1uF

6.3V

10%

CERM 402

2

1

C2103

1uF

6.3V

10%

402

CERM

2

1

C2104

1uF

402

CERM

10%

6.3V

2

1

C2105

1uF

6.3V

10%

CERM 402

2

1

C2106

1uF

6.3V

10%

402

CERM

2

1

C2107

6.3V

10%

402

CERM

1uF

2

1

C2150

1uF

6.3V

10%

402

CERM

2

1

C2109

4.7

5%

MF-LF

402

1/16W

21

R2101

4.7

5%

MF-LF

402

1/16W

21

R2102

4.7

5%

MF-LF

402

1/16W

21

R2103

4.7

MF-LF

5%

402

1/16W

21

R2104

4.7

1/16W

402

MF-LF

5%

21

R2105

4.7

MF-LF

5%

402

1/16W

21

R2106

4.7

MF-LF

5%

402

1/16W

21

R2107

4.7

5%

402

1/16W MF-LF

21

R2109

OMIT

BGA

I2

AL10

AK10

AH21

AH22

N24

M24

AE9

AD9

H10

H9

AJ19

AK19

Y19

AA19

Y20

AA20

U2100

6.3V

10%

402

CERM

1uF

2

1

C2162

10UF

X5R 603

20%

6.3V 2

1

C2146

10UF

X5R 603

20%

6.3V 2

1

C2149

10UF

X5R 603

20%

6.3V 2

1

C2148

6.3V

10UF

X5R 603

20%

2

1

C2199

6.3V

10%

402

CERM

1uF

2

1

C2157

6.3V

10%

402

CERM

1uF

2

1

C2156

402

CERM

6.3V

10%

1uF

2

1

C2174

6.3V

10%

402

CERM

1uF

2

1

C2155

6.3V

10%

402

CERM

1uF

2

1

C2161

6.3V

10%

402

CERM

1uF

2

1

C2160

6.3V

10%

402

CERM

1uF

2

1

C2167

6.3V

10%

402

CERM

1uF

2

1

C2166

6.3V

10%

402

CERM

1uF

2

1

C2165

6.3V

10%

402

CERM

1uF

2

1

C2173

6.3V

10%

402

CERM

1uF

2

1

C2172

6.3V

10%

1uF

402

CERM

2

1

C2171

6.3V

10%

402

CERM

1uF

2

1

C2170

1uF

CERM

402

10%

6.3V 2

1

C2179

1uF

CERM

402

10%

6.3V 2

1

C2178

1uF

CERM

402

10%

6.3V 2

1

C2177

1uF

CERM

402

10%

6.3V 2

1

C2176

CERM

402

6.3V

10%

1uF

2

1

C2175

1uF

CERM

402

10%

6.3V 2

1

C2185

1uF

CERM

402

10%

6.3V 2

1

C2191

1uF

CERM

402

10%

6.3V 2

1

C2184

CERM

402

1uF

10%

6.3V 2

1

C2183

1uF

CERM

402

10%

6.3V 2

1

C2182

1uF

CERM

402

10%

6.3V 2

1

C2181

6.3V

10%

402

CERM

1uF

2

1

C2154

1uF

CERM

402

10%

6.3V 2

1

C2180

1uF

CERM

402

10%

6.3V 2

1

C2190

1uF

CERM

402

10%

6.3V 2

1

C2189

1uF

CERM

402

10%

6.3V 2

1

C2188

1uF

CERM

402

10%

6.3V 2

1

C2187

1uF

CERM

402

10%

6.3V 2

1

C2186

1uF

CERM

402

10%

6.3V 2

1

C2197

1uF

CERM

402

10%

6.3V 2

1

C2196

6.3V

10%

402

CERM

1uF

2

1

C2153

1uF

CERM

402

10%

6.3V 2

1

C2195

1uF

CERM

402

10%

6.3V 2

1

C2194

1uF

CERM

402

10%

6.3V 2

1

C2193

1uF

CERM

402

10%

6.3V 2

1

C2192

1uF

CERM 402

10%

6.3V

2

1

C2125

1uF

CERM 402

10%

6.3V

2

1

C2137

6.3V

10%

402

CERM

1uF

2

1

C2159

1uF

CERM 402

10%

6.3V

2

1

C2124

1uF

CERM 402

10%

6.3V

2

1

C2136

1uF

CERM 402

10%

6.3V

2

1

C2135

1uF

CERM 402

10%

6.3V

2

1

C2129

1uF

CERM 402

10%

6.3V

2

1

C2123

1uF

CERM 402

10%

6.3V

2

1

C2122

1uF

CERM 402

10%

6.3V

2

1

C2128

1uF

CERM 402

10%

6.3V

2

1

C2134

402

CERM

1uF

10%

6.3V

2

1

C2143

6.3V

10%

402

CERM

1uF

2

1

C2164

402

CERM

1uF

10%

6.3V

2

1

C2142

402

CERM

1uF

10%

6.3V

2

1

C2141

402

CERM

1uF

10%

6.3V

2

1

C2140

1uF

CERM 402

10%

6.3V

2

1

C2121

1uF

CERM 402

10%

6.3V

2

1

C2127

1uF

CERM 402

10%

6.3V

2

1

C2120

SYNC_DATE=N/A

SYNC_MASTER=N/A

I2 Power

051-6929

C

115

21

=PP3V3_PWRON_I2_MAXBUS =PP3V3_PWRON_I2_AGPPCI

=PP3V3_PWRON_I2_IO1

=PP3V3_PWRON_I2_IO2

=PPVCORE_PWRON_I2

PP1V5_PWRON_I2_PLL1AVDD

VOLTAGE=1.5V MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm

VOLTAGE=1.5V

PP1V5_PWRON_I2_PLL2AVDD

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm

VOLTAGE=1.5V

PP1V5_PWRON_I2_PLL3AVDD

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.25 mm

VOLTAGE=1.5V

PP1V5_PWRON_I2_PLL4AVDD

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm

VOLTAGE=1.5V

PP1V5_PWRON_I2_PLL5AVDD

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.25 mm

VOLTAGE=1.5V

PP1V5_PWRON_I2_PLL6AVDD

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.25 mm

VOLTAGE=1.5V

PP1V5_PWRON_I2_PLL7AVDD

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm

VOLTAGE=1.5V

PP1V5_PWRON_I2_PLL9AVDD

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.25 mm

=PP1V5_PWRON_I2_PLL

10

SW

SGND PGND

PAD

THERM

SVIN PVIN

PGOOD

VFB

ITH SYNC/MODE

RUN/SS

RT

ADJ

BYP GND

OUT

NC

SHDN

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

One for each PVIN pin

I2 VCore Regulator

Open-Collector

Page Notes

<Rb>

<Ra>

<Rb1>

<Rb2>

Vburst = 0.8V * (Rb2 / (Rb1 + Rb2))

If I2VCORE_BURST is selected: Iburst = (Vburst - 0.2V) * (3.75A / 0.8V)

Iadj = 30nA at 25 C

I2 PLL LDO

- =PP1V5_PWRON_I2PLLVDD_LDO

- =PPVIN_PWRON_I2PLLVDD

indicated LTC3412 output voltage.

- I2VCORE_xVx

- I2VCORE_CONT / I2VCORE_BURST

burst mode for LTC3412 regulator.

- =I2VCORE_PGOOD

BOM options provided by this page:

Selects appropriate resistor for the

Selects between forced continuous and

Signal aliases required by this page:

- =PPVCORE_PWRON_I2_REG

Power aliases required by this page:

NC

- =PP2V7R5V5_PWRON_I2VCORE

Vout = 1.22V * (1 + Ra/Rb) + (Iadj * Ra)

Vout = 0.8V * (1 + (Ra / (Rb1 + Rb2)))

LTC3412

CRITICAL

TSSOP-LF

4

17

6

15

14

11

10

1

8

7

5

16

9

2

13

12

3

U2200

402

309K

MF-LF

1/16W

1%

2

1

R2204

SM-LF

1.0uH-3.48A

CRITICAL

21

L2200

SM

21

XW2200

I2VCORE_1V5

162K

1%

1/16W

402

MF-LF

2

1

R2210

1%

MF-LF

110K

402

1/16W

2

1

R2211

22pF

402

5% 50V CERM

2

1

C2210

1/16W

1%

75K

402

MF-LF

2

1

R2212

5%

1/16W

402

0

MF-LF

I2VCORE_BURST

2

1

R2209

1/16W

5%

I2VCORE_CONT

MF-LF

402

0

2

1

R2208

CERM

50V

5%

100pF

402

2

1

C2206

6.3V

20%

22uF

CERM 1206

2

1

C2201

CERM

22uF

1206

20%

6.3V

2

1

C2200

X5R

47uF

20%

6.3V

1206-1

2

1

C2216

47uF

6.3V

20%

X5R 1206-1

2

1

C2215

402

1% 1/16W MF-LF

7.5K

2

1

R2205

50V

2200pF

603

CERM

5%

2

1

C2205

CERM

50V

10%

470pF

402

2

1

C2207

1/16W MF-LF

402

4.7M

5%

2

1

R2207

CRITICAL

LT1962-ADJ

MSOP-LF

5

1

7

6

8

4

3

2

U2250

20% 10V

1uF

CERM

603

2

1

C2250

10%

0.01uF

16V

CERM

402

2

1

C2254

1% 1/16W MF-LF 402

15.8K

2

1

R2255

1% 1/16W MF-LF 402

68.1K

2

1

R2256

10uF

X5R

6.3V

20%

603

2

1

C2259

22

115

C

051-6929

I2 Power Supplies

SYNC_MASTER=N/A

SYNC_DATE=N/A

R2210

114S0446

1

I2VCORE_1V8

RES,232K,1%,MF-LF,0402

114S0442

R2210

1

I2VCORE_1V7

RES,210K,1%,MF-LF,0402

RES,185K,1%,MF-LF,0402

114S0437

1

R2210

I2VCORE_1V6

=PPVCORE_PWRON_I2_REG

VOLTAGE=0V MIN_LINE_WIDTH=0.75 mm MIN_NECK_WIDTH=0.25 mm

GND_I2VCORE

MIN_LINE_WIDTH=0.20 mm MIN_NECK_WIDTH=0.15 mm

I2VCORE_ITH_RC

I2VCORE_VFB

MIN_LINE_WIDTH=0.20 mm MIN_NECK_WIDTH=0.15 mm

=PPVIN_PWRON_I2PLLVDD

=PP1V5_PWRON_I2PLL_LDO

MIN_NECK_WIDTH=0.15 mm

MIN_LINE_WIDTH=0.20 mm

I2VCORE_RUNSS

MIN_NECK_WIDTH=0.15 mm

I2VCORE_ITH

MIN_LINE_WIDTH=0.20 mm

I2VCORE_RT

MIN_NECK_WIDTH=0.15 mm

MIN_LINE_WIDTH=0.20 mm

=I2VCORE_PGOOD

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.75 mm

I2VCORE_SW

I2PLLVDD_BYP

I2PLLVDD_ADJ

I2VCORE_MODE

MIN_NECK_WIDTH=0.15 mm

MIN_LINE_WIDTH=0.20 mm

I2VCORE_MODE_VDIV

=PP2V7R5V5_PWRON_I2VCORE

10

26

10

GND

VCC

PRE

Q

CLK

D CLR

Q*

GND

VCC

PRE

Q

CLK

D CLR

Q*

GND

VCC

PRE

Q

CLK

D CLR

Q*

IN

OUT

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

0001

1110

1010

0010

1100

0100

1000

MaxBus Feedback Clock Network

NET_TYPE

PHYSICAL

ELECTRICAL_CONSTRAINT_SET

SPACING

DIFFERENTIAL_PAIR

I2 Configuration Straps

199.68MHz CPU / 399.36MHz DDR

194.13MHz CPU / 388.26MHz DDR

188.59MHz CPU / 377.18MHz DDR

183.04MHz CPU / 366.08MHz DDR

177.49MHz CPU / 354.98MHz DDR

171.95MHz CPU / 342.90MHz DDR

166.40MHz CPU / 332.80MHz DDR

149.76MHz CPU / 299.52MHz DDR

133.12MHz CPU / 266.24MHz DDR

Description

0110

0000

Tied

See Table Below

Description

1394b Support (Beta Mode)

1394a Support (Legacy Mode)

50-Ohm MaxBus Drivers

33-Ohm MaxBus Drivers

Tied

HIGH

LOW

HIGH

MAXBUS_DATA<44:41>

MAXBUS_DATA<54>

MAXBUS_DATA<62>

Signal

Keep shortKeep short

AGP Feedback Clock Ladder

PCI Feedback Clock Ladder

NC NC

MAXBUS_D41_PU

402

10K

MF-LF

5% 1/16W

2

1

R2310

I2_MAXBUS_50OHM

MF-LF

10K

402

5% 1/16W

2

1

R2303

I104

I105

MAXBUS_TBEN_SYNC

BGA-YZP

74AUC1G74

CRITICAL

A2

C1

D2

B2

D1

B1

C2

A1

U2390

MAXBUS_TBEN_SYNC CRITICAL

74AUC1G74

BGA-YZP

A2

C1

D2

B2

D1

B1

C2

A1

U2391

MAXBUS_TBEN_SYNC

74AUC1G74

BGA-YZP

CRITICAL

A2

C1

D2

B2

D1

B1

C2

A1

U2392

MAXBUS_D44_PD

5%

402

10K

1/16W MF-LF

2

1

R2305

MAXBUS_TBEN_SYNC

402

CERM

10V

20%

0.1uF

2

1

C2390

MAXBUS_TBEN_SYNC

0.1uF

20% 10V CERM 402

2

1

C2391

MAXBUS_TBEN_SYNC

402

CERM

10V

20%

0.1uF

2

1

C2392

MAXBUS_TBEN_SYNC

402

MF-LF

1/16W

5%

0

21

R2392

I119

I2_FW_BETA

402

10K

MF-LF

5%

1/16W

2

1

R2300

I120

I2_FW_LEGACY

1/16W

5%

MF-LF

10K

402

2

1

R2301

MAXBUS_D42_PU

402

1/16W

5%

MF-LF

10K

2

1

R2308

MAXBUS_D41_PD

1/16W

5%

402

MF-LF

10K

2

1

R2311

0

5%

MF-LF

402

1/16W

I2_AGP_FBCLK_MATCHED

21

R2365

1/16W

0

5%

402

MF-LF

I2_AGP_FBCLK_MATCHED

21

R2367

5% 1/16W MF-LF

0

402

I2_AGP_FBCLK_SHORTEST

2

1

R2360

MAXBUS_D42_PD

1/16W

5%

402

MF-LF

10K

2

1

R2309

0

5% 1/16W MF-LF

402

I2_PCI_FBCLK_MATCHED

21

R2385

0

1/16W

5%

402

MF-LF

I2_PCI_FBCLK_MATCHED

21

R2387

I2_PCI_FBCLK_SHORTEST

402

0

MF-LF

1/16W

5%

2

1

R2380

MAXBUS_D43_PU

402

1/16W

5%

MF-LF

10K

2

1

R2306

I2_MAXBUS_FBCLK_SHORTEST

5% 1/16W MF-LF

402

0

21

R2340

MAXBUS_D44_PU

1/16W

402

10K

MF-LF

5%

2

1

R2304

0

402

MF-LF

1/16W

5%

I2_MAXBUS_FBCLK_MATCHED

2

1

R2350

5% 1/16W MF-LF 402

0

I2_MAXBUS_FBCLK_MATCHED

2

1

R2352

32

43

59

MAXBUS_D43_PD

10K

MF-LF 402

5% 1/16W

2

1

R2307

43

59

32

I2_MAXBUS_33OHM

10K

MF-LF 402

5% 1/16W

2

1

R2302

051-6929

C

115

23

I2 Supplemental

SYNC_MASTER=N/A

SYNC_DATE=N/A

MAXBUS_D44_PD,MAXBUS_D43_PU,MAXBUS_D42_PU,MAXBUS_D41_PD

I2_MAXBUS_189MHZ

I2_MAXBUS_200MHZ

MAXBUS_D44_PD,MAXBUS_D43_PD,MAXBUS_D42_PD,MAXBUS_D41_PU

MAXBUS_D44_PD,MAXBUS_D43_PD,MAXBUS_D42_PD,MAXBUS_D41_PD

I2_MAXBUS_133MHZ

I2_MAXBUS_150MHZ

MAXBUS_D44_PU,MAXBUS_D43_PD,MAXBUS_D42_PD,MAXBUS_D41_PD

I2_MAXBUS_177MHZ

MAXBUS_D44_PD,MAXBUS_D43_PD,MAXBUS_D42_PU,MAXBUS_D41_PD

I2_MAXBUS_194MHZ

MAXBUS_D44_PU,MAXBUS_D43_PU,MAXBUS_D42_PU,MAXBUS_D41_PD

I2_MAXBUS_172MHZ

MAXBUS_D44_PU,MAXBUS_D43_PU,MAXBUS_D42_PD,MAXBUS_D41_PD

I2_MAXBUS_166MHZ

MAXBUS_D44_PD,MAXBUS_D43_PU,MAXBUS_D42_PD,MAXBUS_D41_PD

I2_MAXBUS_183MHZ

MAXBUS_D44_PU,MAXBUS_D43_PD,MAXBUS_D42_PU,MAXBUS_D41_PD

MAXBUS_DATA<62>

MAXBUS_DATA<44>

=SYSCLK_TBEN_SYNC

=CLK33M_TBEN_SYNC

CLOCKCLOCK CLOCKCLOCK

=SYSCLK_TBEN_SYNC

I2_PCI_FBCLK_MATCHED

I2_FBCLKI2_FBCLK

I2_PCI_FBCLK_IN

I2_FBCLKI2_FBCLK

MAXBUS_TBEN

MAXBUS_TBEN_SYNC

=PP1V8_RUN_TBEN_SYNC

TBEN_SYNC_CLR_L

TBEN_SYNC_F1 TBEN_SYNC_F2

=I2_PCI_FBCLK_IN

MAKE_BASE=TRUE

I2_PCI_FBCLK_IN

I2_PCI_FBCLK_OUT

I2_PCI_FBCLK_MATCHED

=I2_AGP_FBCLK_IN

MAKE_BASE=TRUE

I2_AGP_FBCLK_IN

I2_AGP_FBCLK_OUT

I2_AGP_FBCLK_MATCHED

I2_AGP_FBCLK_IN

I2_FBCLK I2_FBCLK I2_FBCLK I2_FBCLK

I2_AGP_FBCLK_MATCHED

I2_FBCLKI2_FBCLK

I2_MAXBUS_FBCLK_IN

I2_FBCLKI2_FBCLK

I2_MAXBUS_FBCLK_MATCHED

=I2_MAXBUS_FBCLK_IN

I2_MAXBUS_FBCLK_IN

MAKE_BASE=TRUE

I2_MAXBUS_FBCLK_OUT

MAXBUS_DATA<54>

MAXBUS_DATA<43>

MAXBUS_DATA<41>

MAXBUS_DATA<42>

=PP1V5R1V8_MAXBUS

I2_MAXBUS_FBCLK_MATCHED

34

33

32

21

32

9

11

21

33

10

21

9

10

21

G

D

S

G

D

S

G

D

S

G

D

S

GPIO_16_H - See Ethernet Sym

EXT_05_H - See Ethernet Sym

GPIO INTERFACE

TEST/JTAG

(4 OF 14)

MISCELLANEOUS

I2S 0

I2S 1

I2C

POWER MGMT/CLOCK

SCCB/VIA

SCCA

REF_CLK_IN

REF_CLK_OUT

PWR_SPDREQ_L

PWR_STPXTL_L

REF_PURESET_L

PWR_STPCPU_L

JTG_TRSTN_L

JTG_TMS_H JTG_TCK_H

JTG_TDI_H

TST_PLLEN_H

TST_TEI_H

SCC_TRXCB_H

SCC_GPIOB_L

SCC_RXDB_H

SCC_RXDA_H

PWR_SPDACK_L

PWR_INTRWD_H

PWR_PCI_PME_L

JTG_TDO_H

SCC_RTSB_L

SCC_TXDB_L

SCC_TXDA_L

EXT_00_H EXT_01_H EXT_02_H

EXT_08_H EXT_09_H

EXT_11_H

EXT_15_H

EXT_14_H

GPIO_EXT_01_H

GPIO_EXT_03_H

GPIO_EXT_02_H

GPIO_05_H

GPIO_04_H

GPIO_06_H

GPIO_11_H

GPIO_09_H

IIC_CLK_0_H

IIC_D_0_H

IIC_CLK_2_H

IIC_D_2_H

AUD_DTO_A_H AUD_CLKOUT_A_H AUD_BITCLK_A_H

AUD_SYNC_A_H

MOD_DTO_B_H MOD_CLKOUT_B_H MOD_BITCLK_B_H

MOD_SYNC_B_H

AUD_DTI_A_H

MOD_DTI_B_H

GPIO_15_H

GPIO_12_H

EXT_12_H

PWR_PENDINT_H

GPIO_EXT_00_H

EXT_16_H

EXT_13_H

EXT_10_H

EXT_03_H EXT_04_H

EXT_07_H

EXT_06_H

G

D

S

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

GPIO_15

GPIO_12

Pull-up/down to be provided by audio page. (*) - See above

Internal pull-up to 3.3V PWRON

Pull-up/down to be provided by audio page.

GPIO_16 0x0_007A N/A No

Pull-up/down to be provided by audio page.

GPIO Pull-ups / Pull-downs

Pull-up/down to be provided by audio page. (*) - See above

Pull-up/down to be provided by audio page.

Internal pull-up to 3.3V PWRON

EXT_12

Internal pull-up to 3.3V PWRON

EXT_09

EXT_00 EXT_01

EXT_05 0x0_005D 51 (0x33) No EXT_06 0x0_005E 52 (0x34) No EXT_07 0x0_005F 53 (0x35) No EXT_08 0x0_0060 54 (0x36) Yes EXT_09 0x0_0061 55 (0x37) Yes

(Int PU)

(Int PU - rev 1)

(Int PU)

(NONE)

Use for I2 revisions > 1.0

(Slave)

(Master)

Signal Direction

Pin Direction

Crystal load capacitance is 16pF

Put crystal circuit close to I2

GPIO_04 0x0_006E N/A No

GPIO_15 0x0_0079 N/A No

EXT_02 0x0_005A 48 (0x30) No

EXT_10 0x0_0062 56 (0x38) No

EXT_04 0x0_005C 50 (0x32) No

EXT_03 0x0_005B 49 (0x31) No

EXT_01 0x0_0059 47 (0x2F) Yes

Pin Address MPIC Int Int PU? Alt Func

EXT_05

EXT_04

EXT_03

EXT_02

EXT_06 EXT_07

EXT_08

EXT_10 EXT_11

EXT_13

GPIO_EXT_01

Internal pull-up to 3.3V PWRON

(I2_EXT_13)

10K Pull-up to Enet OVdd on I2 Enet page. 10K Pull-up to 3.3V on I2 PCI page.

EXT_16 0x0_0068 62 (0x3F) Yes

EXT_00 0x0_0058 46 (0x2E) Yes PCI_REQ_2_L (When PCI1_Slot2En = 10)

EXT_13 0x0_0065 59 (0x3B) No PCI_GNT_2_L (When PCI1_Slot2En = 11)

GPIO_01 0x0_006B 15 (0x0F) No SPIREQ (When SPISReqEn = 1)

10K Pull-up to 3.3V on I2 PCI page.

Pull-up/down to be provided by audio page.

EXT_14

EXT_15 EXT_16

GPIO_EXT_00

GPIO_06

GPIO_05

GPIO_09

GPIO_16

(Int PU - rev 1)

ELECTRICAL_CONSTRAINT_SET

(I2_XTAL)

NET_TYPE

SPACING

DIFFERENTIAL_PAIR

Page Notes

(I2_XTAL)

PHYSICAL

Pull-up/down to be provided by design.

GPIO_04

GPIO_EXT_03

GPIO_EXT_02

GPIO_11

(Int PU)

Power aliases required by this page:

- =PP3V3_PWRON_I2_GPIO

Internal pull-up to 3.3V PWRON 10K Pull-up to 3.3V on I2 AGP page.

Internal pull-up to 3.3V PWRON

BOM options provided by this page:

Signal aliases required by this page:

- =PP3V3_I2_PCISLOTEGPIOS (PWRON or PCI) Should be same as =PP3V3_PCI if slot E

EXT_12 0x0_0064 58 (0x3A) Yes

EXT_15 0x0_0067 61 (0x3D) No

GPIO_00 0x0_006A 14 (0x0E) No

GPIO_03 0x0_006D 17 (0x11) Yes

Use MAKE_BASE to force net name

Alternate GPIO Functions

(*) - Rev 1.0: Missing internal pull-up to 3.3V PWRON

Pull-up/down to be provided by audio page.

(I2_EXT_14)

(*) - Rev 1.0: Missing internal pull-up to 3.3V PWRON

(*) - Rev 1.0: Internal pull-up to 3.3V PWRON

(I2_EXT_08)

- I2_REV1_NOT

is used, or else =PP3V3_PWRON_I2_GPIO.

GPIO_06 0x0_0070 N/A No GPIO_09 0x0_0073 N/A No GPIO_11 0x0_0075 N/A Yes GPIO_12 0x0_0076 N/A Yes

GPIO_05 0x0_006F N/A No

GPIO_02 0x0_006C 16 (0x10) Yes PCI_GNT_2_L (When PCI1_Slot2En = 10)

EXT_14 0x0_0066 60 (0x3C) No PCI_REQ_2_L (When PCI1_Slot2En = 11)

EXT_11 0x0_0063 57 (0x39) Yes

(Int PU - rev 1)

(Master)

Audio Mute Sequencing

Prevents mute glitch from reaching audio circuit

402

100K

5% 1/16W MF-LF

2

1

R2470

SOT-363

2N7002DW-X-F

1

2

6

Q2470

402

5% 1/16W MF-LF

100K

2

1

R2472

402

MF-LF

1/16W

5%

10K

2

1

R2481

SOT-363

2N7002DW-X-F

4

5

3

Q2480

402

100K

5% 1/16W MF-LF

2

1

R2480

SOT-363

2N7002DW-X-F

1

2

6

Q2480

100K

402

5% 1/16W MF-LF

2

1

R2482

2N7002DW-X-F

SOT-363

1

2

6

Q2481

BGA

I2

OMIT

AL6 AL5

AL2

AE5

AL1

AL3

AG5

AL4AM1

AK3

AC12

AC13

AH7 AH6

AH5 AK5

AK6

AK7

AL7

G6

G5J5 J6

J7

AP1

AN2

AN4AN6

AN3

F1

J3

F4

J1

AH3

AH4

AJ1

AK2

AG6

AG7

G2

AG8

G1

G3

M1

G4

H1

AE4

AF1

AG2

AG3

AG1

AK1

AG4

AN33

AR33

J2

AH2

AT19

AK4

AH1

D2

C1E1

F2

F3

U2100

5%

402

CERM

22pF

50V

2

1

C2410

0

MF-LF

1/16W

5%

402

2

1

R2411

8X4.5MM-SM1

CRITICAL

18.432M

21

Y2410

50V

22pF

CERM

402

5%

2

1

C2411

NO STUFF

10M

402

MF-LF

1/16W

5%

21

R2410

10K

402

MF-LF

1/16W

5%

2

1

R2400

10K

402

MF-LF

1/16W

5%

2

1

R2401

5%

1/16W

10K

SM-LF

72

RP2450

5%

1/16W

10K

SM-LF

81

RP2450

5% 1/16W MF-LF

402

10K

2

1

R2490

10K

1/16W

5%

SM-LF

63

RP2450

5% 1/16W MF-LF

10K

402

I2_REV1_NOT

21

R2455

10K

1/16W

5%

SM-LF

54

RP2450

10K

NO STUFF

402

MF-LF

1/16W

5%

21

R2451

10K

5% 1/16W MF-LF

402

21

R2452

10K

402

MF-LF

NO STUFF

5%

1/16W

21

R2460

10K

NO STUFF

402

5% 1/16W MF-LF

21

R2461

10K

402

MF-LF

1/16W

5%

21

R2462

10K

5% 1/16W MF-LF

402

21

R2463

10K

1/16W

402

MF-LF

5%

21

R2464

402

MF-LF

1/16W

5%

10K

2

1

R2471

SOT-363

2N7002DW-X-F

4

5

3

Q2470

SYNC_MASTER=N/A

24

115

C

051-6929

I2 Miscellaneous

SYNC_DATE=N/A

MUTE_CONTROL

SYS_WARM_RESET_L

I2_AUDIO_SPKR_MUTE_L

SYS_WARM_RESET_L

AUDIO_SPKR_MUTE_L

AUDIO_SPKR_MUTE

I2S1_SYNC_R

SCCA_TXD_L

AGP_INT_L

I2S0_SYNC_R

VIA_REQ_L

AUDIO_LI_DET_L

=PP3V3_AUDIO_MUTESEQ

AUDIO_LO_MUTE_L

MUTE_CONTROL

I2_AUDIO_LO_MUTE_L

I2S0_SB_TO_DEV_DTO_R

I2SI2S

I2S0_DTO

I2S0_MCLK_R

I2SI2S

I2S0_MCLK

I2S

I2S0_BITCLK_R

I2S

I2S0_BITCLK

XTAL XTAL

I2_CLK18M_XOUT

I2_GPIO_11

I2S1_MCLK_R

PMU_INT_L

PMU_SB_NMI_L

PCI_SLOTE_GNT_L

PCI_SLOTE_REQ_L

FW_POWERDOWN

I2_EXT_13 I2_EXT_14 AUDIO_LO_DET_L AUDIO_GPIO_11

I2_GPIO_EXT_02 MODEM_RESET_L

I2_AUDIO_LO_MUTE_L I2_AUDIO_SPKR_MUTE_L

FW_POWERDOWN

MMM_SIRQ_L

AUDIO_EXT_MCLK_SEL

PCI_SLOTE_GNT_L

I2S0_DEV_TO_SB_DTI

PCI_SLOTE_REQ_L

PCI_SLOTE_INT_L

I2S0_MCLK_R

I2S0_SB_TO_DEV_DTO_R

=I2C_I2_SB_SDA

=I2C_I2_NB_SDA

=I2C_I2_NB_SCL

=I2C_I2_SB_SCL

AUDIO_I2S_DTIB_SEL

=SPI_I2_REQ

AUDIO_CODEC_RESET_L

=SPI_I2_MOSI

I2S1_BITCLK_R

I2S1_SB_TO_DEV_DTO_R

PCI_SLOTD_INT_L

MODEM_RING2SYS_L

I2S1_DEV_TO_SB_DTI

I2SI2S

I2S1_DTI

I2S1_SB_TO_DEV_DTO_R

I2S I2S

I2S1_DTO

I2S1_MCLK_R

I2S I2S

I2S1_MCLK

I2S1_BITCLK_R

I2S I2S

I2S1_BITCLK

I2S0_SYNC_R

I2SI2S

I2S0_SYNC

I2S0_DEV_TO_SB_DTI

I2S I2S

I2S0_DTI

I2_GPIO_11

AUDIO_SPDIFRX_RESET_L

I2_EXT_08

I2S I2S

I2S1_SYNC_R

I2S1_SYNC

I2_CLK18M_XOUT_R

XTALXTAL

I2_XTAL

XTAL XTAL

I2_CLK18M_XIN

=PP3V3_I2_PCISLOTEGPIOS

=SPI_I2_REQ

=SPI_I2_MISO

=PP3V3_PWRON_I2_MISC

=SPI_I2_CLK

I2_CLK18M_XOUT

I2_GPIO_EXT_02

PCI_SLOTA_INT_L

AUDIO_LI_OPTICAL_PLUG_L

AUDIO_LO_OPTICAL_PLUG_L

TP_I2_PENDINT

I2S1_DEV_TO_SB_DTI

I2S0_BITCLK_R

MMM_FFIRQ_L

PMU_SB_NMI_L

PMU_INT_L

VIA_SB_TO_PMU

SYS_WATCHDOG

NB_SUSPENDACK_L

SCCA_RXD

VIA_PMU_TO_SB VIA_ACK_L VIA_CLK

I2_TST_PLLEN

=JTAG_I2_TDI

=JTAG_I2_TCK

=JTAG_I2_TMS

=JTAG_I2_TRST_L

=I2_STOPCPU_L

=I2_STOPXTAL_L

NB_SUSPENDREQ_L

I2_CLK18M_XOUT_R I2_CLK18M_XIN

I2_TST_TEI

MMM_SIRQ_L

PCI_SLOTE_INT_L

MODEM_RING2SYS_L

MMM_FFIRQ_L

SYS_PME_L

=JTAG_I2_TDO

AUDIO_LO_MUTE

=PP3V3_PWRON_I2_MISC

62

74

30

74

30

25

74

22

24

44

22

74

22

74

22

25

22

74

22

25

74

22

74

22

74

22

59

25

30

22

74

22

59

74

30

22

25

24

25

22

25

62

22

7

6

7

43

6

25

7

10

7

22

6

22

6

22

11

22

7

11

30

22

7

11

7

11

6

8

7

11

7

6

11

22

6

7

22

7

6

22

10

11

10

22

11

7

22

6

22

25

7

25

9

11

25

22

11

22

25

9

10

CLKIN

CLKOUT

1Y3

GND

1Y2

1Y1

1Y0

VDD

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(NONE)

BOM options provided by this page:

- I2_REV1_NOT

is used, or else =PP3V3_PWRON_I2_GPIO.

Signal aliases required by this page:

Use for I2 revisions > 1.0

- =PP3V3_I2_PCISLOTEGPIOS (PWRON or PCI) Should be same as =PP3V3_PCI if slot E

Power aliases required by this page:

- =PP3V3_PWRON_I2_GPIO

Page Notes

DIFFERENTIAL_PAIR

PHYSICAL

NET_TYPE

SPACING

ELECTRICAL_CONSTRAINT_SET

CRITICAL

CDCVF2505

SOIC

6

4

8

1

7

5

2

3

U2500

6.3V

10%

1uF

402

CERM

2

1

C2501

0.001uF

50V

20%

CERM

402

NO STUFF

2

1

C2502

10V

20%

0.1uF

CERM

402

2

1

C2500

I72

I73 I74

I75 I76

PCI Clock Buffer

25

115

C

051-6929

SYNC_MASTER=N/A

SYNC_DATE=N/A

=PP3V3_PCI_ZDB

=PCI_CLK33M_ZDB_IN

PCI_ZDBOUT3

=PCI_CLK33M_ZDBOUT_R<3>

CLOCK CLOCK

PCI_ZDBOUT2

=PCI_CLK33M_ZDBOUT_R<2>

CLOCKCLOCK

PCI_ZDBOUT1

=PCI_CLK33M_ZDBOUT_R<1>

CLOCKCLOCK

=PCI_CLK33M_ZDB_IN

CLOCK CLOCK

PCI_ZDBOUT0

=PCI_CLK33M_ZDBOUT_R<0>

CLOCKCLOCK

PCI_CLK_DELAY_ADJ

=PCI_CLK33M_ZDBOUT_R<0> =PCI_CLK33M_ZDBOUT_R<1> =PCI_CLK33M_ZDBOUT_R<2> =PCI_CLK33M_ZDBOUT_R<3>

23

10

11

G

D

S

G

D

S

G

D

S

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(WAS COMM_TRXC)

(WAS COMM_GPIO_L)

(WAS PMU_BOOT_CE)

NC

SERIAL DEBUG INTERFACE

PMU RESET CIRCUIT

PLACE "SYS RESET" IN SILK NEAR RESISTOR

PLACE "PMU RESET" IN SILK NEAR RESISTOR

DEBUGGING AIDS

PLACE ON TOP SIDE NEAR FRONT EDGE OF BOARD

PLACE "POWER BTN" IN SILK NEAR RESISTOR

CHARGE LED

SLEEP LED

402

MF-LF

1/16W

5%

100

2

1

R2600

OMIT

603

MF-LF

1/10W

5%

470K

21

R2691

OMIT

470K

5% 1/10W MF-LF

603

21

R2692

SOT-363

2N7002DW-X-F

1

2

6

Q2680

402

MF-LF

1/16W

5%

100K

2

1

R2680

SOT-363

BAS16TW-X-F

6 1

DP2680

SOT23-LF

2N3906

2

3

1

Q2600

BAS16TW-X-F

SOT-363

5 2

DP2680

2N7002DW-X-F

SOT-363

4

5

3

Q2680

2.2K

5% 1/16W MF-LF

402

2

1

R2601

402

MF-LF

1/16W

5%

470K

2

1

R2610

402

MF-LF

1/16W

5%

4.7K

R2602

SOT23-LF

2N7002

2

1

3

Q2601

M-ST-SM

QT500166-L020

DEVELOPMENT

CRITICAL

9

87

65

43

2

1615

1413

1211

10

1

J2690

402

MF-LF

1/16W

5%

10K

DEVELOPMENT

2

1

R2696

402

MF-LF

1/16W

5%

10K

DEVELOPMENT

2

1

R2695

OMIT

470K

5% 1/10W MF-LF

603

21

R2690

SYNC_DATE=N/A

SYNC_MASTER=N/A

26

115

C

051-6929

LEDs/Reset/Debug

PMU_RESET_L

PMU_CUSTOMER_RESET

SLEEP_LED_SW_L

SYS_LED

=SLEEP_LED_IOUT

=PP5V_PWRON_SLEEPLED

SLEEP_LED_L

SYS_ONEWIRE

SYS_CHARGE_LED_L

=PP3V3_ALL_PMU

SYS_AC_DET_L

PMU_RESET_L

SYS_POWER_BUTTON_L

SYS_RESET_BUTTON_L

SYS_POWER_BUTTON_L

SYS_BATT0_DET_L

SLEEP_LED_I

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm

=PP3V3_ALL_DEBUG

SCCA_TXD_L

PMU_BOOT_SCLK PMU_BOOT_CNVSS

PMU_RESET_L

PMU_BOOT_BUSY

PMU_BOOT_RXD

PMU_BOOT_TXD

PMU_BOOT_RP_L

SCCA_RXD

COMM_DTR_L

NO_TEST=TRUE

COMM_RTS_L

NO_TEST=TRUE

57

36

25

30

25

74

24

25

36

25

22

25

22

24

25

11

10

25

7

10

12

24

25

24

12

10

7

25

24

25

7

P9[7]

P9[6]

P9[5]

P8[7]

P8[6]

P8[5]

P3[7]

P3[6]

P3[5]

P3[4]

P2[6] P2[7]

P2[4] P2[5]

P1[4]

P1[3]

P1[2]

P1[1]

P1[0]

P0[4]

P0[0]

P0[2] P0[3]

P0[1]

P0[7]

P0[6]

P0[5]

P3[3]

P3[2]

P3[1]

P3[0]

P2[3]

P2[2]

P2[1]

P2[0]

P1[5] P1[6] P1[7]

PCNVSS RESET* XOUT

VREF

XIN

P7[7]

P7[6]

P7[5]

P7[4]

P7[3]

P7[2]

P7[1]

P7[0]

P6[7]

P6[6]

P6[5]

P6[4]

P6[3]

P6[2]

P6[1]

P6[0]

P10[0] P10[1]

P9[3]

P9[2]

P9[1]

P9[0]

P8[4]

P8[3]

P8[2]

P8[1]

P8[0]

P10[6] P10[7]

P10[2] P10[3] P10[4] P10[5]

VCC

AVSS

VSS

AVCC

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

SPACING

Signal aliases required by this page:

- =PPVREF_PMU (PMU AVCC or 2.5V reference)

Page Notes

ELECTRICAL_CONSTRAINT_SET

PMU Pull-ups / pull-downs

as analog inputs.

NOTE: All analog inputs to PMU should have

reserved for alternate functions.

- =JTAG_BBANGER_TCK

MMM

CPU T-Diodes

ALS

SPI Dual Battery Charger

Battery Current Mon

those capacitors are provided on

AN06

Power Management Unit

AN21

DIFFERENTIAL_PAIR

AN01

AN04

AN00

AN05

AN22

- =PP3V3_ALL_PMU

Sout3

PHYSICAL

NET_TYPE

AN20

AN0

AN3

KI0*/AN4

KI1*/AN5 KI2*/AN6

KI3*/AN7

Sout4/AN26

CLK4/AN25

AN24

TB2in

TB0in

TA4in INT0*

INT2*

CE*/Xcout

Xcin

RP/NMI*

TA4out

INT1*

TA3in

TA2out

CLK1

CLK0

CTS0*

AN2

TxD1

TxD0

RxD0

RTS1*/BUSY

TA1in

RTS0*/

INT5*

INT4*

INT3*/ADtrig

ICOC2

ICOC3

ICOC4 ICOC5

ICOC6

ICOC7

CLK2/TA1out

SCL/RxD2/TA0in

SDA/TxD2/

TA0out

AN03

AN02

RxD1

- =I2C_PMU_SCL

- =I2C_PMU_SDA

- =I2C_PMU_SMB_SCL

- =I2C_PMU_SMB_SDA

- =JTAG_BBANGER_TMS

- =JTAG_BBANGER_TRST_L NOTE: Boot-banger pins can be aliased to TP_ or NC_ if not implemented.

BOM options provided by this page: (NONE)

NOTE: TP_PMU_Px_x signals are general-

TP_PMU_AN_Px_x signals are general-

purpose spares. Some pins are

purpose spares that can also be used

a 100pF capacitor to the PMU AVSS

this page.

Keep crystal subcircuit close to PMU.

Y2740’s load capacitance is 12pF

- =JTAG_BBANGER_TDI

signal (GND_PMU_AVSS). None of

Spares (Analog capable)

AN23

AN07

ICOC1/SCLmm

TA2in

TA3out

ICOC0/SDAmm

Spares (Analog capable)

TB1in

- =PP3V3_PWRON_PMU

Power aliases required by this page:

AN1

Sin4//AN27

CLK3 Sin3

Additional PMU05 "Modules"

CRITICAL

8X4.5MM-SM1

10.0000M

21

Y2740

MMBD914XXG

SOT23

3

1

D2710

6.3V

10%

402

CERM

1uF

2

1

C2720

1/16W

5%

402

MF-LF

4.7K

2

1

R2715

1/16W

5%

402

MF-LF

150K

2

1

R2710

0.22uF

CERM-X5R

402

10%

6.3V 2

1

C2710

402

50V

18pF

5%

CERM

2

1

C2741

402

5%

18pF

50V

CERM

2

1

C2740

0

1/16W

5%

402

MF-LF

2

1

R2741

MF-LF

1/16W

5%

402

10M

NO STUFF

21

R2740

100K

MF-LF

402

5%

1/16W

21

R2774

10K

MF-LF

402

5%

1/16W

21

R2761

10K

MF-LF

402

5%

1/16W

21

R2760

10K

402

5% 1/16W MF-LF

12

R2765

10V

0.1uF

402

20%

CERM

2

1

C2700

10V

0.1uF

CERM

402

20%

2

1

C2701

10UF

X5R

20%

6.3V

603

2

1

C2702

6.3V

1uF

CERM 402

10%

2

1

C2705

402

MF-LF

4.7

1/16W

5%

21

R2705

SM

21

XW2700

1/16W

5%

402

MF-LF

100K

21

R2772

402

MF-LF

1/16W

5%

100K

21

R2771

MF-LF

100K

402

5% 1/16W

21

R2773

402

NO STUFF

1/16W

5%

MF-LF

10M

21

R2750

1/16W MF-LF 402

5%

0

2

1

R2751

12pF

50V CERM 402

5%

2

1

C2751

12pF

402

50V CERM

5%

2

1

C2750

1/16W

5%

402

100K

MF-LF

21

R2770

4.7K

1/16W

5%

402

MF-LF

2

1

R2730

1/16W

5%

402

MF-LF

100K

21

R2766

10K

MF-LF

402

5% 1/16W

21

R2767

CRITICAL

OMIT

SM1

32.768K

21

Y2750

M30280F8-LF

QFP-80

OMIT

10

12

11

77

13

9

79

80

1

2

3

4

5

7

8

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

40

41

42

43

32

33

34

35

36

37

38

39

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

68

69

70

71

72

73

74

76

59

60

61

62

63

64

65

66

67

6

75

78

U2700

1/16W

5%

402

MF-LF

10K

21

R2768

051-6929

115

27

C

Power Management Unit (PMU05)

SYNC_MASTER=N/A

SYNC_DATE=N/A

CRITICAL

Y2750

XTAL,32.768KHZ,4.1X1.5X0.9MM,SMD

1

197S0163

?

TP_PMU_P7_2

TP_PMU_P3_2

PMU_CLK10M_XOUT_R

MODEM_RING2SYS_L

SYS_POWER_BUTTON_L

SYS_RESET_BUTTON_L

SYS_OVERTEMP_L

SYS_ONEWIRE PMU_CLK32K_XOUT_R

PMU_BOOT_RXD PMU_BOOT_TXD PMU_BOOT_RP_L

SYS_COLD_RESET_L

TP_PMU_AN_P0_0

TP_PMU_AN_P0_2

TP_PMU_P3_3

VIA_ACK_L VIA_REQ_L PMU_INT_L PMU_SB_NMI_L VIA_CLK

TP_PMU_AN_P10_7

TP_PMU_AN_P10_5 TP_PMU_AN_P10_6

TP_PMU_AN_P10_4

TP_PMU_AN_P10_2 TP_PMU_AN_P10_3

TP_PMU_AN_P10_0 TP_PMU_AN_P10_1

SYS_AC_DET

VIA_PMU_TO_SB VIA_SB_TO_PMU

=I2C_PMU_SMB_SDA =I2C_PMU_SMB_SCL

SYS_KBDLED

TP_PMU_P7_4

SYS_ACIN

TP_PMU_P7_5

TP_PMU_P7_1

TP_PMU_P7_0

PMU_BOOT_SCLK

SYS_WARM_RESET_L

PMU_BOOT_BUSY

PCI_RESET_L

GOV_RESET_L

PMU_SYS_CLK_EN

PMU_CPU_CLK_EN

NB_SUSPENDACK_L

NB_SUSPENDREQ_L

TP_PMU_AN_P0_1

TP_PMU_AN_P0_4

TP_PMU_AN_P0_3

TP_PMU_AN_P0_7

TP_PMU_AN_P0_6

TP_PMU_AN_P0_5

SYS_LID_OPEN

SYS_SLEEP

PMU_POWER_UP_L

PMU_CPU_HRESET_L

SYS_WATCHDOG

=JTAG_BBANGER_TCK

=JTAG_BBANGER_TDI

=JTAG_BBANGER_TRST_L =JTAG_BBANGER_TMS

TP_PMU_P3_0 TP_PMU_P3_1

=I2C_PMU_SDA =I2C_PMU_SCL

PMU_CLK10M_XOUT

SYS_SLEEP

SYS_WARM_RESET_L

GND_PMU_AVSS

VOLTAGE=0V MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm

VOLTAGE=3.3V

PP3V3_ALL_PMU_AVCC

=PP3V3_ALL_PMU

PMU_CLK10M_XIN

=PPVREF_PMU

PMU_BOOT_CNVSS PMU_RESET_L

=PP3V3_ALL_PMU

GND_PMU_AVSS

TP_PMU_AN_P10_7

BATT_ISNS

SPI_PMU_CHGR_CLK

TP_PMU_P3_0

SPI_PMU_TO_CHGR_MOSI

TP_PMU_P3_2

SPI_CHGR_TO_PMU_MISO

TP_PMU_P3_1

SPI_PMU_CHGR_CS

TP_PMU_P3_3

ALS_1_OUT ALS_GAIN_BOOST

ALS_0_OUT

CPU1_TEMP

CPU0_TEMP

TP_PMU_AN_P10_5 TP_PMU_AN_P10_6

TP_PMU_AN_P10_4 TP_PMU_P7_2

TP_PMU_AN_P10_3

MMM_Z_AXIS

TP_PMU_AN_P10_2

MMM_Y_AXIS

TP_PMU_AN_P10_1

MMM_X_AXIS

TP_PMU_AN_P10_0

MMM_SIRQ_L

TP_PMU_P7_1

MMM_FFIRQ_LTP_PMU_P7_0

MMM_ACC_PWRDOWN

TP_PMU_AN_P0_6

MMM_ACC_SELFTEST

TP_PMU_AN_P0_7

PMU_BATT1_DET_L

TP_PMU_P7_4

PMU_BATT1_CHARGE

TP_PMU_P7_5

SYS_COLD_RESET_L

PCI_RESET_L

NB_SUSPENDREQ_L

=PP3V3_ALL_PMU

PMU_POWER_UP_L

SYS_POWER_BUTTON_L

SYS_PME_L

VIA_REQ_L

SYS_OVERTEMP_L

SYS_RESET_BUTTON_L

=PP3V3_PWRON_PMU

XTAL

PMU_CLK32K_XOUT_R

XTAL

PMU_CLK10M_XOUT_R

XTAL XTAL

PMU_CLK10M_XOUT

XTALXTAL

PMU_CLK32K_XOUT

PMU_CLK32K_XIN

SYS_PME_L

SYS_BATT0_DET_L

PMU_BATT0_CHARGE

SYS_LED

PMU_CLK10M_XIN

PMU_CLK10M_XTAL

XTAL XTAL

PMU_CLK32K_XTAL

PMU_CLK32K_XIN

XTAL XTAL

PMU_CLK32K_XOUT

XTAL XTAL

57

36

30

31

36

30

36

25

18

62

29

25

29

31

25

30

62

25

36

62

25

30

25

11

25

13

25

26

25

28

24

28

25

28

31

25

24

26

25

11

25

24

25

11

25

22

24

7

24

25

24

25

11

22

25

11

25

12

22

8

28

11

12

11

25

24

22

24

11

22

11

25

11

30

25

11

22

9

11

8

25

22

25

10 10

25

10

24

10

25

25 12 11

11

28

7

11

25

29 25

22 25

29 25

11

25

11

22

10

25

24

22

7

24

10

25

22

12

13

24

25

G

D

S

G

D

S

G

S D

G

S D

G

S D

G

D

S

G

D

S

G

D

S

G

D

S

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

WAKE

ACTIVE-HIGH, OUTPUT/INPUT, OPEN-COLLECTOR

ACTIVE-HIGH, OUTPUT, PUSH-PULL

SHUT-DOWN

POWER-UP

SLEEP

ACTIVE-LOW, OUTPUT, PUSH-PULL

Used to see if last rail is up

ACTIVE-LOW, OUTPUT, PUSH-PULL

ANALOG INPUT, SENSE > 1.7V

ACTIVE-HIGH, OUTPUT/INPUT, OPEN-COLLECTOR

ACTIVE-HIGH, OUTPUT, PUSH-PULL

100K pull-up to 3.3V_ALL on pg 13

ACTIVE-LOW, OUTPUT, OPEN-COLLECTOR

100K

5%

MF-LF

1/16W

402

21

R2920

402

MF-LF

1/16W

0

5%

21

R2902

2N7002DW-X-F

SOT-363

4

5

3

Q2900

5%

402

100K

1/16W MF-LF

2

1

R2910

MF-LF

0

1/16W

5%

402

21

R2912

MF-LF

0

1/16W

402

5%

21

R2911

2N7002DW-X-F

SOT-363

1

2

6

Q2940

5%

1/16W

100K

402

MF-LF

21

R2921

MF-LF

1/16W

100K

402

5%

2

1

R2941

2N7002DW-X-F

SOT-363

1

2

6

Q2941

1/16W MF-LF

402

5%

100K

21

R2922

402

MF-LF

0

5%

1/16W

TPAD_SEQ_HW

21

R2943

2N7002DW-X-F

SOT-363

4

5

3

Q2941

2N7002

SOT23-LF

TPAD_SEQ_PMU

2

1

3

Q2948

TPAD_SEQ_PMU

100K

402

MF-LF

1/16W

5%

2

1

R2948

1/16W

5%

MF-LF

402

0

21

R2930

402

100K

MF-LF

5%

1/16W

2

1

R2935

SOT-363

2N7002DW-X-F

4

5

3

Q2910

100K

MF-LF

5%

1/16W

402

21

R2936

5%

MF-LF

1/16W

402

0

NO STUFF

21

R2940

1/16W

402

MF-LF

5%

0

21

R2951

402

MF-LF

1/16W

5%

100K

2

1

R2965

2N7002DW-X-F

SOT-363

4

5

3

Q2940

100K

5%

MF-LF

402

1/16W

21

R2966

0

402

MF-LF

1/16W

5%

21

R2967

NO STUFF

402

MF-LF

5%

0

1/16W

2

1

R2949

SM

21

XW2970

NO STUFF

0

5% 1/16W MF-LF

402

21

R2969

5% 1/16W MF-LF 402

10K

2

1

R2958

100K

1/16W

402

5%

MF-LF

1

2

R2913

100K

1/16W 402

MF-LF

5%

2

1

R2901

SOT-363

2N7002DW-X-F

1

2

6

Q2900

SOT-363

2N7002DW-X-F

1

2

6

Q2910

5%

100K

1/16W

402

MF-LF

2

1

R2929

0

5%

MF-LF

402

1/16W

21

R2903

402

MF-LF

1/16W

5%

0

21

R2900

Power Sequencing

SYNC_DATE=N/A

SYNC_MASTER=N/A

051-6929

C

115

29

=1V8_1V5PWRON_PGOOD =2V5PWRON_PGOOD =I2VCORE_PGOOD

=PP3V3_RUN_PWRSEQ

PWRON_REGS_PGOOD

MAKE_BASE=TRUE

SYS_PWRSEQ_5

SYS_PWRSEQ_1

SYS_PWRSEQ_2_L

=PP3V3_PWRON_PWRSEQ

SYS_PWRSEQ_4

SYS_PWRSEQ_6_L

VCORE_CPU0_SHDN_L

1V8RUN_EN_L

FWPWR_PWRON

MAKE_BASE=TRUE

1V8_1V5PWRON_EN_L

SYS_POWERUP

5VRUN_EN_L

=FWPWR_PWRON

MAKE_BASE=TRUE

5VTPAD_EN_L

=PP3V3_PWRON_PWRSEQ

SYS_PWRSEQ_TPAD_L

3V3RUN_EN_L

5VRUNHD_EN_L

SYS_PWRSEQ_1_L

GPUPVDD_EN

GPUVDD15_EN

SYS_PWRSEQ_6_LS5

MAKE_BASE=TRUE

=PP5V_RUN_PWRSEQ

2V5RUN_EN_L

SYS_POWER_UP_L

=PP3V3_ALL_PWRSEQ

2V5PWRON_EN_L

MAKE_BASE=TRUE

=2V5PWRON_EN_L

=1V8_1V5PWRON_EN_L

SYS_PWRSEQ_3_LS5

PP1V8_GPU_PVDD

1V5RUN_EN

=PP5V_RUN_PWRSEQ

=5V3VPWRON_PGOOD

5V3V3PWRON_EN_L

MAKE_BASE=TRUE

=5V3V3PWRON_EN_L

=GPUVCORE_PGOOD

GPUVCORE_PGOOD

MAKE_BASE=TRUE

TP_VCORE_PGOOD

MAKE_BASE=TRUE

=VCORE_PGOOD

=5VPWRONTPAD_EN_L

GPUVCORE_SHDN_L

=PP3V3_ALL_PWRSEQ

CPU_AVDD_EN

SYS_PWRSEQ_FINAL

SYS_PWRSEQ_3_L

SYS_PWRSEQ_2

PMU_POWER_UP_L

=PP5V_PWRON_PWRSEQ

26

16

17

20

10

11

10

11

36

16

15

18

10

11

15

51

46

10

17

10

17

16

51

16

10

15

45

36

15

45

10

37

11

25

10

VCCP

TACH3

THERM#/

SMBALERT#/GPIO

D1-

D1+

D2-

D2+

SCL

VCC

XTO

TACH1

SMBALERT#

TACH2

TACH4/

PWM2/

PWM1/

GND

SDA

PWM3

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(Device is connected so as to be backward compatible with the ADT7460.)

I2C READ ADDR = 0x5C, WRITE ADDR = 0x5D

NC

KEEP STUFFING RESISTORS CLOSE TO ADT7467 CONTROLLER

PLACE CLOSE TO CPU

PLACE CLOSE TO BATTERY CHARGER/VCORE

PLACE UNDERNEATH UPPER RAM

PLACE IN BETWEEN 3/5/1.5/2.5V PWR SUPPLY

MAIN1

MAIN2

ALTERNATE1

ALTERNATE2

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

SPACING

PHYSICAL

DIFFERENTIAL_PAIR

FAN CONTROLLER

0.1uF

20% 10V CERM 402

C3001

402

MF-LF

1/16W

5%

10K

2

1

R3004

SOT23

2N3904LF

2

3

1

Q3001

SOT23

2N3904LF

2

3

1

Q3002

402

MF-LF

1/16W

5%

10K

2

1

R3005

SOT23

2N3904LF

2

3

1

Q3004

SOT23

2N3904LF

2

3

1

Q3003

0

402

MF-LF

1/16W

5%

21

R3012

0

5% 1/16W MF-LF

402

21

R3013

402

MF-LF

1/16W

5%

0

21

R3010

402

MF-LF

1/16W

5%

0

21

R3011

NO STUFF

0

5% 1/16W MF-LF

402

21

R3020

NO STUFF

402

MF-LF

1/16W

5%

0

21

R3021

NO STUFF

0

5% 1/16W

402

MF-LF

21

R3022

402

MF-LF

1/16W

5%

0

NO STUFF

21

R3023

402

MF-LF

1/16W

5%

10K

2

1

R3001

1uF

10%

6.3V CERM

603

C3000

402

MF-LF

1/16W

5%

10

R3000

1000pF

10% 25V X7R 402

C3002

1000pF

10% 25V X7R 402

C3003

QSOP-LF CRITICAL

ADT7467

14

3

9

4

7

6

16

1

8

5

15

2

10

11

12

13

U3000

402

MF-LF

1/16W

5%

10K

2

1

R3003

402

MF-LF

1/16W

5%

10K

2

1

R3002

I528

I529

I530 I531

I532

I533

I534 I535

I536

I537

I538

I539

Fan Controller

C

051-6929

115

30

SYNC_DATE=N/A

SYNC_MASTER=N/A

THERM_D1_PTHERM1_M_P

THERM_D2_PTHERM2_M_P

THERM_D1_NTHERM1_M_N

THERM_D2_NTHERM2_M_N

THERM_D1_PTHERM1_A_P

THERM_D2_PTHERM2_A_P

THERM_D1_NTHERM1_A_N

THERM_D2_NTHERM2_A_N

=PP3V3_RUN_FANTACH

=PP5V_RUN_FANPWM

FAN1_TACH

FAN2_TACH

FAN2_PWM

FAN1_PWM

VOLTAGE=3.3V MIN_LINE_WiDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm

PP3V3_ADT7467

ADT7467_ADR_ENABLE_L

=PP3V3_ADT7467

=PPVCORE_CPU_ADT7467

=I2C_ADT7467_SDA =I2C_ADT7467_SCL

=ADT7467_THERM_L

THERM2_M

THERM2_M_P

THERMTHERM

THERM1_M

THERM1_M_N

THERMTHERM

THERM1_A

THERM1_A_P

THERMTHERM

THERM2_M

THERM2_M_N

THERMTHERM

THERM

THERM2_A

THERM2_A_P

THERM

THERM1_A

THERM1_A_N

THERMTHERM

THERM2_A

THERM

THERM2_A_N

THERM

THERM2_A_N

THERM2_A_P

THERM1_A_N

THERM1_A_P

THERM2_M_N

THERM2_M_P

THERM1_M_N

THERM1_M_P

THERM1_M

THERM1_M_P

THERMTHERM

THERM_D2_N

THERM_D2_P

THERM_D1_N

THERM_D1_P

THERM_D1

THERMTHERM

THERM_D1_N

THERM_D1

THERMTHERM

THERM_D1_P

THERM_D2

THERMTHERM

THERM_D2_N

THERM_D2

THERMTHERM

THERM_D2_P

31

27 27

10 10

7

10

8

11

27

V+

V-

G

D

S

NC

CNTRL

THRML_PAD

VDD

SW

AGNDPGND

FB

VOUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

RT ALS SENSOR

IS

Place cap at PMU!

SHDN_L

Keyboard LED Driver

NC

MAX4236EUTT

CRITICAL

SOT23-6-LF

2

6

5

1

4

3

U3100

402

1K

1% 1/16W MF-LF

21

R3105

402

120K

5% 1/16W MF-LF

21

R3104

0.22uF

10%

CERM-X5R

6.3V 402

21

C3104

15.0K

1% 1/16W MF-LF

402

2

1

R3102

402

MF-LF

1/16W

1%

1K

2

1

R3103

402

0.1UF

20% 10V CERM

2

1

C3100

402

1K

1% 1/16W MF-LF

21

R3101

402

MF-LF

1/16W

5%

5.1M

2

1

R3100

402

CERM

16V

20%

0.01UF

2

1

C3101

CRITICAL

BS520EOF

TH

2 1

PD3100

SOT-363

2N7002DW-X-F

1

2

6

Q3103

805

MF-LF

1/8W

1%

25.5

2

1

R3131

1210

0.22uF

10% 50V CERM

2

1

C3131

10K

5% 1/16W MF-LF

402

NO STUFF

2

1

R3132

402

MF-LF

1/16W

5%

10K

2

1

R3130

LLP

MM3120

8

197

5

6 4

3

2

U3130

603

1UF

10%

6.3V CERM

2

1

C3130

3.8X3.8X1.5MM

22UH

21

L3130

0.001uF

10% 50V CERM 402

2

1

C3105

SYNC_MASTER=N/A

SYNC_DATE=N/A

115

31

051-6929

C

ALS Support

Primary is unity gain stable/Alt is stable at G=5

353S1191 353S1186

U3100

=PP3V3_PWRON_RT_ALS

GAIN_SETTING2

RT_ALS_OP_COMP

ALS_GAIN_BOOST

MAKE_BASE=TRUE

RT_ALS_OUT_FB

RT_ALS_PHOTODIODE

=PP5V_RUN_KEYBRD_LED

KBDLED_ANODE

KBDLED_RETURN

=PP3V3_RUN_KEYBRD_LED

MM3120_SW

SYS_KBDLED

GND_PMU_AVSS

MAKE_BASE=TRUE

ALS_1_OUT

RT_ALS_OP_IN

31

25

30

29

10

7

10

7

10

25

OUTPUTY

OUTPUTZ

DNC

RSVD

TEST

SELF

PS

PARITY

RSVD

GND PAD

THRML

OUTPUTX

VDD

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

TABLE_5_ITEM

REFERENCE DESIGNATOR(S)

BOM OPTION

TABLE_5_HEAD

QTY

DESCRIPTION

PART#

1

+Y

+Z (up)

Package Top

+X

NC

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

SPACING

PHYSICAL

DIFFERENTIAL_PAIR

OMIT

KXM52

QFN

8

15

10

11

7

6

4

9

5

14

13

2

12

3

1

U3220

402

MF-LF

1/16W

5%

10K

MMM_ACCEL_KIONIX

2

1

R3220

MMM_ACCEL_KIONIX

0.1uF

20% 10V

402

CERM

2

1

C3220

I57

I58 I59

402

CERM

10V

20%

0.1uF

OMIT

2

1

C3204

0.1uF

20% 10V CERM 402

OMIT

2

1

C3205

402

CERM

10V

20%

0.1uF

OMIT

2

1

C3206

1

CRITICAL

MMM_ACCEL_KIONIX

338S0222

IC,KIONIX,KXM52-2050,3AXIS ACCELEROMETER,SMD

U3220

32

C

115

051-6929

SYNC_MASTER=N/A

SYNC_DATE=N/A

Sudden Motion Sensor

CAP,CER,0.033UF,10%,16V,X5R/X7R,0402,SMD

132S0131

MMM_ACCEL_KIONIX

C3204,C3205,C3206

3

=PP3V3_PWRON_MMM

MAKE_BASE=TRUE

MMM_ACC_SELFTEST

THERMTHERM

MMM_X_AXIS

THERMTHERM

MMM_Y_AXIS

THERMTHERM

MMM_Z_AXIS

MAKE_BASE=TRUE

MMM_Y_AXIS

MMM_X_AXIS

MAKE_BASE=TRUE

GND_PMU_AVSS

MAKE_BASE=TRUE

MMM_ACC_PWRDOWN

31

29

28

10

25

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

SLEEP LED CONNECTOR

NOTE: KEEP FERRITE CLOSE TO CAP

PLACE NEAR CONNECTOR PINS

SOFT MODEM CONN

NC

USB Trackpad Connector

402

MF-LF

1/16W

5%

22

2 1

R3353

402

CERM

50V

20%

0.001uF

2

1

C3353

SM-1

400-OHM-EMI

21

L3354

SM-1

400-OHM-EMI

21

L3355

402

0.001uF

20% 50V

CERM

2

1

C3354

402

0.001uF

20% 50V

CERM

2

1

C3355

0

5% 1/16W MF-LF

402

2 1

R3352

CRITICAL

QT500166-L020

M-ST-SM

9

87

65

43

2

1615

1413

1211

10

1

J3350

402

CERM

50V

20%

0.001uF

2

1

C3352

402

CERM

50V

20%

0.001uF

2

1

C3350

400-OHM-EMI

SM-1

21

L3350

NO STUFF

15V

SOT23LF

3

2

1

D3354

CRITICAL

SM-2MT-LF

2

1

4

3

J3300

SM

400-OHM-EMI

2

1

L3300

603

CERM

50V

10%

470pF

C3300

0

5% 1/16W MF-LF 402

2

1

R3300

0

5% 1/16W MF-LF 402

2

1

R3301

402

MF-LF

1/16W

5%

100K

2

1

R3355

NO STUFF

10K

5% 1/16W MF-LF 402

2

1

R3320

CERM

6.3V

20%

4.7uF

603

C3320

10K

5% 1/16W MF-LF

402

2

1

R3321

CRITICAL

QT500166-L020

M-ST-SM

9

87

65

43

2

1615

1413

1211

10

1

J3320

SYNC_DATE=N/A

SYNC_MASTER=N/A

C

051-6929

115

33

Q16C Internal I/O I

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

SLEEP_LED_CONN

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm

VOLTAGE=0V

SLEEP_LED_DGND

=FTP_SLEEP_LED

=SLEEP_LED_CONN

=PP5V_TPAD

=PP3V3_PWRON_DS1775

KBDLED_RETURN

SYS_POWER_BUTTON_L_F

=I2C_DS1775_SCL

=I2C_DS1775_SDA

USB_TPAD_P USB_TPAD_N

SYS_OVERTEMP_L

KBDLED_ANODE

SYS_LID_OPEN_F

SYS_POWER_BUTTON_L

=PP3V3_ALL_HALL_EFFECT

SYS_LID_OPEN

MODEM_RESET_L I2S1_SYNC

I2S1_DEV_TO_SB_DTI

I2S1_SB_TO_DEV_DTO

=GND_CHASSIS_SLEEP_LED

=PP3V3_PWRON_MODEM

SOFTMODEM_FC_RGDT

I2S1_MCLK

I2S1_BITCLK

MODEM_RING2SYS_L

PP5V_TPAD_F

VOLTAGE=5V MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.15 mm

PP3V3_PWRON_DS1775_R

MIN_NECK_WIDTH=0.10 mm

VOLTAGE=3.3V MIN_LINE_WIDTH=0.15 mm

PP3V3_ALL_HALL_EFFECT_R

VOLTAGE=3.3V MIN_LINE_WIDTH=0.15 mm MIN_NECK_WIDTH=0.10 mm

57

25

36

28

8

11

28

25

11

10

7

24

10

25

22

6

22

6

2

10

6

22

7

7 7

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Place cap at PMU!

NC

FROM BATTERY

ADAPTER CONNECTOR

INPUT TO AND OUTPUT

OUTPUT FROM BATTERY

BACKUP BATTERY CONNECTOR

GPU FANCPU FAN

LEFT ALS CONNECTOR

RIGHT USB BOARD

PBUS HOLD-UP CAPS

CRITICAL

87438-0443

M-RT-SM-LF

4

3

2

1

J3400

603-1

X7R

50V

10%

0.1uF

2

1

C3400

CRITICAL

SM1-LF

ELEC

35V

20%

100uF

2

1

C3450

CRITICAL

220uF

SM-LF

ELEC

25V

20%

2

1

C3460

M-ST-SM

QT500166-L020

CRITICAL

9

8 7

6 5

4 3

2

16 15

14 13

12 11

10

1

J3410

SM04B-SSR

CRITICAL

M-RT-SM-LF

4

3

2

1

6

5

J3460

CRITICAL

SM04B-SSR

M-RT-SM-LF

4

3

2

1

6

5

J3450

402

CERM

50V

10%

0.001uF

2

1

C3430

BACKUP_BATT

CRITICAL

M-RT-SM

53780-0370

3

2

1

5

4

J3420

SM-2MT-LF

CRITICAL

4

3

2

1

6

5

J3430

SYNC_DATE=N/A

SYNC_MASTER=N/A

34

115

051-6929

C

Q16C Internal I/O II

=PP12V8_PBUSB_HOLDUP_CAPS

=PP5V_PWRON_RIGHT_USB

ALS_0_OUT

MAKE_BASE=TRUE

ALS_GAIN_BOOST

MAKE_BASE=TRUE

=PP3V3_PWRON_LEFT_ALS

=PPVOUT_BU_BATT

=PPVIO_BU_BATT

=PP5V_FAN1_PWR FAN1_TACH FAN1_PWM

=PP5V_FAN2_PWR FAN2_TACH FAN2_PWM

=PP24V_PBUSA_HOLDUP_CAPS

=PP24V_ADAPTER_CONN

USB2_RIGHT_PORT_N USB2_RIGHT_PORT_P

GND_PMU_AVSS

28

29

10

25

10

27

10

27

11

28

10

7

10

7

25

(5 of 14)

PROCESSOR INTERFACE

MAXBUS INTERFACE

PROCESSOR 1

PROCESSOR 0

MAX_FBCLK_OUT_H

MAX_TBEN_H

MAX_TA_L

MAX_TEA_L

MAX_DTI_1_H MAX_DTI_2_H

MAX_DTI_0_H

MAX_D_63_H

MAX_D_60_H MAX_D_61_H MAX_D_62_H

MAX_D_59_H

MAX_D_58_H

MAX_D_55_H

MAX_D_57_H

MAX_D_56_H

MAX_D_53_H MAX_D_54_H

MAX_D_52_H

MAX_D_51_H

MAX_D_50_H

MAX_D_49_H

MAX_D_48_H

MAX_D_47_H

MAX_D_46_H

MAX_D_45_H

MAX_D_44_H

MAX_D_43_H

MAX_D_42_H

MAX_D_41_H

MAX_D_40_H

MAX_D_37_H

MAX_D_39_H

MAX_D_38_H

MAX_D_35_H MAX_D_36_H

MAX_D_34_H

MAX_D_33_H

MAX_D_32_H

MAX_D_30_H MAX_D_31_H

MAX_D_29_H

MAX_D_28_H

MAX_D_27_H

MAX_D_26_H

MAX_D_25_H

MAX_D_24_H

MAX_D_23_H

MAX_D_22_H

MAX_D_21_H

MAX_D_20_H

MAX_D_19_H

MAX_D_17_H MAX_D_18_H

MAX_D_15_H

MAX_D_14_H

MAX_D_16_H

MAX_D_12_H MAX_D_13_H

MAX_D_11_H

MAX_D_10_H

MAX_D_09_H

MAX_D_08_H

MAX_D_07_H

MAX_D_05_H MAX_D_06_H

MAX_D_04_H

MAX_D_03_H

MAX_D_02_H

MAX_D_01_H

MAX_D_00_H

MAX_AACK_L

MAX_CLK_1_H

MAX_DBG_1_L CPU_INT_1_L

MAX_BG_1_L

MAX_QACK_1_L

MAX_CLK_0_H

CPU_INT_0_L

MAX_DBG_0_L

MAX_BG_0_L

MAX_QACK_0_L

MAX_TT_1_H MAX_TT_2_H

MAX_TT_0_H

MAX_TT_3_H MAX_TT_4_H MAX_WT_L

ACS_REF_H

MAX_CLK_FB_IN_H

MAX_A_03_H

MAX_A_02_H

MAX_A_05_H

MAX_A_04_H

MAX_A_06_H

MAX_A_08_H

MAX_A_07_H

MAX_A_10_H

MAX_A_09_H

MAX_A_11_H

MAX_A_13_H

MAX_A_12_H

MAX_A_14_H MAX_A_15_H MAX_A_16_H

MAX_A_18_H

MAX_A_17_H

MAX_A_20_H

MAX_A_19_H

MAX_A_21_H

MAX_A_23_H

MAX_A_22_H

MAX_A_24_H

MAX_A_26_H

MAX_A_25_H

MAX_A_28_H

MAX_A_27_H

MAX_A_29_H

MAX_A_31_H

MAX_A_30_H

MAX_CI_L MAX_GBL_L MAX_TBST_L MAX_TSIZ_0_H

MAX_TSIZ_2_H

MAX_TSIZ_1_H

MAX_BR_0_L MAX_DRDY_0_L MAX_HIT_0_L

MAX_QREQ_1_L MAX_BR_1_L MAX_DRDY_1_L MAX_HIT_1_L

MAX_TS_L MAX_ARTRY_L

MAX_A_00_H MAX_A_01_H

MAX_QREQ_0_L

VDD18_40

VDD18_39

VDD18_38

VDD18_37

VDD18_36

VDD18_30 VDD18_31 VDD18_32 VDD18_33 VDD18_34 VDD18_35

VDD18_27 VDD18_28 VDD18_29

VDD18_26

VDD18_25

VDD18_24

VDD18_23

VDD18_22

VDD18_21

VDD18_20

VDD18_19

VDD18_17 VDD18_18

VDD18_16

VDD18_15

VDD18_14

VDD18_12 VDD18_13

VDD18_9

VDD18_11

VDD18_10

VDD18_7 VDD18_8

VDD18_4

VDD18_6

VDD18_5

VDD18_3

VDD18_2

VDD18_1

VDD18_0

MAXBUS POWER

(6 of 14)

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

I2 CPU1 Support

I2 CPU0 Support

MaxBus Pull-ups / Pull-downs

(41 Balls on I2)

MaxBus I/O DECOUPLING

ELECTRICAL_CONSTRAINT_SET

1.5V IN

DIFFERENTIAL_PAIR

PHYSICAL

NET_TYPE

SPACING

Signal aliases required by this page:

- =I2_MAXBUS_FBCLK_IN - MaxBus feedback clock input. Length should match that of clock(s) from I2 to CPU(s).

Power aliases required by this page:

Output impedance is 50 Ohms

1.5V-1.8V OUT (Matches MaxBus OVdd)

One resistor for each of:

- MAXBUS_TEA_L

- MAXBUS_TA_L

- MAXBUS_TS_L

- MAXBUS_AACK_L

- MAXBUS_CPU1_INT_L

- MAXBUS_CPU1_HIT_L

- MAXBUS_CPU1_DRDY_L

- MAXBUS_CPU1_DBG_L

- MAXBUS_CPU1_BG_L

- MAXBUS_CPU1_BR_L

One resistor for each of:

- MAXBUS_CPU0_BR_L

- MAXBUS_CPU0_BG_L

- MAXBUS_CPU0_DBG_L

- MAXBUS_CPU0_DRDY_L

- MAXBUS_CPU0_HIT_L

- MAXBUS_CPU0_INT_L

1 X 10uF (0603) 41 X 1uF (0402)

BOM options provided by this page:

- MAXBUS_1V8 - Provides required voltage divider for FBCLK if MaxBus OVdd=1.8V.

- =PP1V5R1V8_RUN_I2_MAXBUS

- =PP1V5R1V8_PWRON_I2_MAXBUS

- MAXBUS_ARTRY_L

- (Spare)

10K

1/16W

5%

SM-LF

72

RP3510

5% 1/16W SM-LF

10K

81

RP3510

10K

SM-LF

5%

1/16W

54

RP3510

1/16W

5%

SM-LF

10K

63

RP3511

1/16W

5%

SM-LF

10K

72

RP3512

1/16W

5%

SM-LF

10K

63

RP3512

10K

SM-LF

5% 1/16W

81

RP3511

10K

SM-LF

5% 1/16W

63

RP3510

1/16W

5%

SM-LF

10K

54

RP3511

1/16W

5%

SM-LF

10K

81

RP3512

1/16W 402

MF-LF

1K

1%

2

1

R3500

1/16W

5%

SM-LF

10K

63

RP3513

1/16W

5%

SM-LF

10K

72

RP3513

1/16W

5%

SM-LF

10K

81

RP3514

1/16W

5%

SM-LF

10K

54

RP3513

1/16W

5%

SM-LF

10K

72

RP3514

10K

SM-LF

5%

1/16W

72

RP3511

1uF

CERM

402

10%

6.3V 2

1

C3554

1uF

CERM

402

10%

6.3V 2

1

C3553

1uF

CERM

402

10%

6.3V 2

1

C3559

1uF

CERM

402

10%

6.3V 2

1

C3564

1uF

CERM

402

10%

6.3V 2

1

C3558

1uF

CERM

402

10%

6.3V 2

1

C3563

1uF

CERM

402

10%

6.3V 2

1

C3569

1uF

CERM

402

10%

6.3V 2

1

C3568

1uF

CERM

402

10%

6.3V 2

1

C3552

1uF

CERM

402

10%

6.3V 2

1

C3551

1uF

CERM

402

10%

6.3V 2

1

C3550

20%

603

10uF

X5R

6.3V

2

1

C3599

1uF

CERM

402

10%

6.3V 2

1

C3562

1uF

10%

CERM

402

6.3V 2

1

C3557

1uF

CERM

402

10%

6.3V 2

1

C3567

1uF

CERM

402

10%

6.3V 2

1

C3556

1uF

CERM

402

10%

6.3V 2

1

C3561

1uF

CERM

402

10%

6.3V 2

1

C3555

1uF

CERM

402

10%

6.3V 2

1

C3560

1uF

CERM

402

10%

6.3V 2

1

C3566

1uF

CERM

402

10%

6.3V 2

1

C3565

1uF

CERM

402

10%

6.3V 2

1

C3574

1uF

CERM

402

10%

6.3V 2

1

C3573

1uF

CERM

402

10%

6.3V 2

1

C3572

1uF

CERM

402

10%

6.3V 2

1

C3571

1uF

CERM

402

10%

6.3V 2

1

C3570

1uF

CERM

402

10%

6.3V 2

1

C3575

1uF

CERM

402

10%

6.3V 2

1

C3579

1uF

CERM

402

10%

6.3V 2

1

C3578

1uF

CERM

402

10%

6.3V 2

1

C3577

1uF

CERM

402

10%

6.3V 2

1

C3576

1uF

CERM

402

10%

6.3V 2

1

C3585

1uF

CERM

402

10%

6.3V 2

1

C3584

1uF

CERM

402

10%

6.3V 2

1

C3583

1uF

CERM

402

10%

6.3V 2

1

C3582

1uF

CERM

402

10%

6.3V 2

1

C3581

1uF

CERM

402

10%

6.3V 2

1

C3580

OMIT

I2

BGA

D24

A22

A21

E18

D22

B22

B21

C18

D19

B27

D28

E16

C24

G19

E27

E25

G18

F18

C21

E21

A24

J22

A29

A30

C27

F25

G25

G24

F24

F10

B4

G10

E7

E9

F9

A5

F6

C12

C5

C15

A15

B13

D13

A12

A14

B12

D15

B15

C13

A16

A13

C16

B16

D4

G9

D3

C4

F7

E6

A3

G7

D6

C6

B6

E10

A6

F13

F12

G12

A7

D7

E12

E13

G13

F16

A8

B7

C7

E15

D10

B9

G15

F15

C9

D9

G16

C10

B10

A11

D12

A9

A10

D16

H22

J21

H21

A26

G21

F21

E24

E22

C30

A31

B19

A17

C22

B18

E28

B30

F27

F28

C31

D30

G27

E19

B25

B28

A27

D27

E30

F19

D31

C25

G28

B24

B31

D25

C28

A18

A25

D21

A23

A19

A28

D18

H19

J19

K9

U2100

1uF

CERM

402

10%

6.3V 2

1

C3590

1uF

CERM

402

10%

6.3V 2

1

C3589

1uF

CERM

402

10%

6.3V 2

1

C3588

1uF

CERM

402

10%

6.3V 2

1

C3587

1uF

CERM

402

10%

6.3V 2

1

C3586

OMIT

I2

BGA

C8

C32

C3

C29

C26

P22

C23

P18

P15

P14

N22

N21

N19

N15

M20

L23

L17

C20

L14

J27

J26

J24

J23

J20

J18

J17

J15

J14

C17

J12

J11

F8

F29

F26

F23

F20

F17

F14

F11

C14

C11

U2100

1/16W

5%

SM-LF

10K

63

RP3514

1/16W

5%

SM-LF

10K

54

RP3512

10

1/16W

5%

402

MF-LF

21

R3505

MAXBUS_1V8

360

MF-LF

402

5%

1/16W

2

1

R3506

402

10K

5% 1/16W MF-LF

21

R3514

MF-LF

1/16W

5%

10K

402

21

R3513

603

MF-LF

1/10W

5%

0

21

R3550

NO STUFF

0

5% 1/10W MF-LF

603

21

R3551

I2 Processor Interface

C

051-6929

115

35

SYNC_MASTER=N/A

SYNC_DATE=N/A

TP_MAXBUS_TBEN_I2

MAXBUS_TEA_L

I2_MAXBUS_FBCLK_OUT

I2_MAXBUS_FBCLK

I2_FBCLKI2_FBCLK

I2_MAXBUS_FBCLK_OUT_R

I2_FBCLKI2_FBCLK

I2_MAXBUS_FBCLK_OUT

MAXBUSMAXBUS

MAXBUS_CPUS_BIDIR

MAXBUS_DATA<55..61>

MAXBUS MAXBUS

MAXBUS_DATA62

MAXBUS_DATA<62>

MAXBUS

MAXBUS_CPUS_BIDIR_R

MAXBUS_TS_L

MAXBUS

MAXBUS_NB_TO_CPUS_R

MAXBUS_AACK_L

MAXBUS

MAXBUS_NB_TO_CPU0_R

MAXBUS

MAXBUS_CPU0_BG_L

MAXBUS_WT_L

MAXBUS

MAXBUS_WT_L

MAXBUS

MAXBUS_CPU1_TO_NB_R

MAXBUS

MAXBUS_CPU1_BR_L

MAXBUSMAXBUS

MAXBUS_NB_TO_CPU1_R

MAXBUS_CPU1_BG_L

MAXBUSMAXBUS

MAXBUS_CPU0_TO_NB_R

MAXBUS_CPU0_HIT_L

MAXBUS_NB_TO_CPU0_R

MAXBUSMAXBUS

MAXBUS_CPU0_DBG_L

MAXBUS

MAXBUS_CPU0_TO_NB_R

MAXBUS

MAXBUS_CPU0_BR_L

MAXBUSMAXBUS

MAXBUS_CPU1_TO_NB_R

MAXBUS_CPU1_HIT_L

=RP3510P2

Page Notes

MAXBUS

MAXBUS_CPU1_DRDY_L

MAXBUS

MAXBUS_CPU1_DRDY_L

MAXBUS

MAXBUS_NB_TO_CPU1_R

MAXBUS

MAXBUS_CPU1_DBG_L

MAXBUS_GBL_L

MAXBUSMAXBUS

MAXBUS_NB_TO_CPUS_R

MAXBUS_TA_L

MAXBUSMAXBUS

MAXBUS_CPUS_BIDIR

MAXBUS_DATA<63>

CLOCKCLOCK

MAXBUS_CLK_CPU0_R

MAXBUS_CLK_CPU0 MAXBUS_CLK_CPU1

CLOCK CLOCK

TP_MAXBUS_CLK_CPU1_R

MAXBUS_DATA54

MAXBUS

MAXBUS_DATA<54>

MAXBUS

MAXBUS_CPUS_TO_NBIO

MAXBUS_CI_L

MAXBUSMAXBUS

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=1.5V

PP1V5R1V8_I2_MAXBUS

=PP1V5R1V8_PWRON_I2_MAXBUS

=PP1V5R1V8_RUN_I2_MAXBUS

MAXBUS_CPU0_QREQ_L

MAXBUS_CPU1_QREQ_L

MAXBUS MAXBUS

MAXBUS_DATA43

MAXBUS_DATA<43>

MAXBUS MAXBUS

MAXBUS_DATA42

MAXBUS_DATA<42>

MAXBUS

MAXBUS_DATA<41>

MAXBUS_DATA41

MAXBUS

MAXBUS_CPUS_BIDIR

MAXBUS_DATA<45..53>

MAXBUS

MAXBUS_NB_TO_CPUS_R

MAXBUS_TEA_L

MAXBUS

MAXBUS_CPUS_BIDIR_R

MAXBUS_ARTRY_L

MAXBUSMAXBUS

MAXBUS_DTI

MAXBUS_DTI<0..2>

MAXBUSMAXBUS

MAXBUS_CPUS_BIDIR

MAXBUS_TT<0..4>

MAXBUSMAXBUS

MAXBUS_CPUS_TO_NBIO

MAXBUS_TBST_L

MAXBUSMAXBUS

MAXBUS_CPUS_TO_NBIO

MAXBUS_TSIZ<0..2>

MAXBUSMAXBUS

MAXBUS_CPU0_DRDY_L

MAXBUS_CPUS_BIDIR

MAXBUS_ADDR<0..31>

MAXBUSMAXBUS

MAXBUS

MAXBUS_CPUS_BIDIR

MAXBUS_DATA<0..40>

MAXBUS

=PP1V5R1V8_MAXBUS

=RP3510P1

TP_MAXBUS_CLK_CPU1_R

MAXBUS_CPU1_DBG_L MAXBUS_CPU1_INT_L

MAXBUS_CPU1_BG_L

TP_MAXBUS_CPU1_QACK_L

MAXBUS_CLK_CPU0_R

MAXBUS_CPU0_INT_L

MAXBUS_CPU0_DBG_L

MAXBUS_CPU0_BG_L

MAXBUS_CPU0_QACK_L

I2_MAXBUS_FBCLK_OUT_R

MAXBUS_DTI<0> MAXBUS_DTI<1>

MAXBUS_DATA<60>

MAXBUS_CPU1_QREQ_L MAXBUS_CPU1_BR_L

MAXBUS_ADDR<17>

MAXBUS_DTI<2>

MAXBUS_TA_L

MAXBUS_DATA<25> MAXBUS_DATA<26> MAXBUS_DATA<27> MAXBUS_DATA<28> MAXBUS_DATA<29>

MAXBUS_DATA<31>

MAXBUS_DATA<30>

MAXBUS_DATA<32> MAXBUS_DATA<33> MAXBUS_DATA<34>

MAXBUS_DATA<36>

MAXBUS_DATA<35>

MAXBUS_DATA<38> MAXBUS_DATA<39>

MAXBUS_DATA<37>

MAXBUS_DATA<40> MAXBUS_DATA<41> MAXBUS_DATA<42> MAXBUS_DATA<43> MAXBUS_DATA<44> MAXBUS_DATA<45> MAXBUS_DATA<46> MAXBUS_DATA<47> MAXBUS_DATA<48> MAXBUS_DATA<49> MAXBUS_DATA<50> MAXBUS_DATA<51> MAXBUS_DATA<52>

MAXBUS_DATA<54>

MAXBUS_DATA<53>

MAXBUS_DATA<56> MAXBUS_DATA<57>

MAXBUS_DATA<55>

MAXBUS_DATA<59>

MAXBUS_DATA<62>

MAXBUS_DATA<61>

MAXBUS_DATA<63>

MAXBUS_AACK_L

MAXBUS_DATA<0> MAXBUS_DATA<1> MAXBUS_DATA<2> MAXBUS_DATA<3> MAXBUS_DATA<4>

MAXBUS_DATA<6>

MAXBUS_DATA<5>

MAXBUS_DATA<7> MAXBUS_DATA<8> MAXBUS_DATA<9> MAXBUS_DATA<10> MAXBUS_DATA<11>

MAXBUS_DATA<13>

MAXBUS_DATA<12>

MAXBUS_DATA<16>

MAXBUS_DATA<14> MAXBUS_DATA<15>

MAXBUS_DATA<18>

MAXBUS_DATA<17>

MAXBUS_DATA<19> MAXBUS_DATA<20> MAXBUS_DATA<21> MAXBUS_DATA<22> MAXBUS_DATA<23> MAXBUS_DATA<24>

=I2_MAXBUS_FBCLK_IN

MAXBUS_CPU0_QREQ_L

MAXBUS_ADDR<1>

MAXBUS_ADDR<0>

MAXBUS_ARTRY_L

MAXBUS_CPU1_DRDY_L

MAXBUS_CPU0_HIT_L

MAXBUS_CPU0_DRDY_L

MAXBUS_CPU0_BR_L

MAXBUS_TSIZ<1> MAXBUS_TSIZ<2>

MAXBUS_GBL_L

MAXBUS_ADDR<30>

MAXBUS_ADDR<28>

MAXBUS_ADDR<25>

MAXBUS_ADDR<24>

MAXBUS_ADDR<22>

MAXBUS_ADDR<21>

MAXBUS_ADDR<19> MAXBUS_ADDR<20>

MAXBUS_ADDR<18>

MAXBUS_ADDR<16>

MAXBUS_ADDR<15>

MAXBUS_ADDR<14>

MAXBUS_ADDR<12>

MAXBUS_ADDR<9> MAXBUS_ADDR<10>

MAXBUS_ADDR<7> MAXBUS_ADDR<8>

MAXBUS_ADDR<6>

MAXBUS_ADDR<4> MAXBUS_ADDR<5>

MAXBUS_ADDR<3>

MAXBUS_WT_L

MAXBUS_TT<4>

MAXBUS_TT<3>

MAXBUS_TT<0>

MAXBUS_TT<2>

MAXBUS_TT<1>

=RP3510P3

=RP3511P1

=RP3510P4

=RP3511P2

MAXBUS_ADDR<13>

MAXBUS_ADDR<2>

MAXBUS_CPU1_HIT_L

MAXBUS_ADDR<11>

MAXBUS_ADDR<23>

MAXBUS_TS_L

=RP3511P4

=RP3511P3

=RP3512P1

=RP3512P2

=RP3512P4

=RP3512P3

=RP3513P2

=RP3513P3

=RP3514P1

=RP3513P4

=RP3514P3

=RP3514P2

MAXBUS_ADDR<31>

MAXBUS_CI_L

MAXBUS_TBST_L MAXBUS_TSIZ<0>

MAXBUS_ADDR<29>

MAXBUS_ADDR<27>

MAXBUS_ADDR<26>

MAXBUS

MAXBUS_DATA44

MAXBUS_DATA<44>

MAXBUS

MAXBUS_DATA<58>

I2_ACS_REF

33

34

33

32

33

32

33

32

33

32

33

32

33

32

33

32

33

32

21

32

21

32

33

21

32

21

32

34

32

21

32

21

32

21

32

33

32

21

32

6

21

32

21

9

6

9

6

9

6

9

11

9

10

32

9

6

9

6

9

10

6

11

6

11

6

33

32

9

32

6

9

6

9

6

9

21

32

9

6

9

6

9

6

9

6

9

CKSTP_OUT*

CKSTP_IN*

QACK*

QREQ*

CLK_OUT

TBEN

SHD0*

SYSCLK

SHD1*

AACK*

ARTRY*

CI*

GBL*

WT*

TSIZ2

TSIZ0

TBST*

TT4

TT1

TT3

TT2

TT0

AP2 AP3 AP4

AP0 AP1

A2

A11

A34 A35

A33

A32

A31

A30

A29

A27 A28

A26

A24

A23

A21

A19

A17 A18

A16

A14 A15

A12 A13

A9 A10

A8

A7

A3

A1

TS*

A0

BG*

BR*

A25

A20

A4

A6

A22

A5

TSIZ1

(1 OF 6)

D3

DP6

DP5

DP4

DP3

DP2

DP1

DP0

D63

D62

D61

D60

D59

D58

D57

D56

D55

D53 D54

D52

D51

D50

D49

D48

D46 D47

D45

D44

D43

D41 D42

D40

D38 D39

D36 D37

D35

D33 D34

D32

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

D9

D8

D5 D6

D4

D1

D0

D7

D2

DP7

DTI0 DTI1 DTI2 DTI3

DRDY*

DBG*

HIT*

TEA*

TA*

(2 OF 6)

OVDDSENSE2

OVDDSENSE1

OVDD

(5 OF 6)

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(Kelvin sense points)

ADD GND TP NEAR CLKOUT TP

MAXBUS Straps

NC

PLACE RC GLITCH FILTER

CLOSE TO CPU PIN

26 X 1UF (0402) 2 X 10UF (0603)

VIO DECOUPLING (28 PINS)

(NONE)

- =PP1V5R1V8_MAXBUS

- =MAXBUS_CPU0_CLK

Power aliases required by this page:

Page Notes

BOM options provided by this page:

Signal aliases required by this page:

DIFFERENTIAL_PAIR

SPACING

NET_TYPE

PHYSICAL

ELECTRICAL_CONSTRAINT_SET

10%

402

CERM

1uF

6.3V

2

1

C3695

10%

402

CERM

1uF

6.3V

2

1

C3694

10%

402

CERM

1uF

6.3V

2

1

C3693

10%

402

CERM

1uF

6.3V

2

1

C3692

10%

402

CERM

1uF

6.3V

2

1

C3691

10%

402

CERM

1uF

6.3V

2

1

C3690

BGA

A8-X.X

XXGHZ-XXV

OMIT

CRITICAL

D3

C5

E9

F6

E6

E5

E7

F7

G6

L4

F11

E1

A10

H5

E4

P4 G5

E2

H2

B1

A3

J1

D2 M1

N2

G7

F5

H6

E3

C1

R1

G2

C10

D1

D11

L2

F10

B11

G10

C4

B12

W1

N5

G3

U1

V2

T1

N3

P5

M5

J3

N4

K4

J2

C11

W2

K5

R2

J4

V1

F4

T2

G4

L3

D12

H1

E11

U3600

CRITICAL

OMIT

XXGHZ-XXV

A8-X.X

BGA

L1

K6

B2

N1

P1

K1

G1

R3

W6

N8

V3

M6

W9

T4

W4

T3

M2

W13

V13

P14

T8

W8

R8

P6

U15

R7

U7

U8

U4

V17

W3

T17

T18

T16

W18

T15

W17

U18

W19

U19

T19

V19

R18

V18

R19

P17

W16

V6

P7

R6

W7

U5

T5

U6

W5

V9

U9

V16

W10

R9

U10

P10

N9

R10

T11

W11

U11

R11

T14

N10

N11

V12

W12

T12

R12

W14

U14

P13

T13

W15

R15

U3600

CRITICAL

OMIT

XXGHZ-XXV

A8-X.X

BGA

G18

E18

L5

K2

J5

H3

F2

D5

C12

V14

V10

V7

V4

U16

U12

U2

C2

T9

T6

R16

R13

R4

P11

P8

P2

N6

M3

B4

U3600

1K

1% 1/16W MF-LF

402

21

R3620

402

MF-LF

1/16W

1%

10K

21

R3611

402

MF-LF

1/16W

5%

10K

21

R3610

I1020

4V

603

20%

10uF

X5R

2

1

C3699

20%

10uF

X5R

4V

603

2

1

C3698

1/16W

5%

402

MF-LF

470

21

R3601

0

MF-LF

402

5%

1/16W

21

R3600

50V

10PF

CERM 402

5%

2

1

C3600

10%

402

CERM

1uF

6.3V

2

1

C3670

10%

402

CERM

1uF

6.3V

2

1

C3671

10%

402

CERM

1uF

6.3V

2

1

C3672

10%

402

CERM

1uF

6.3V

2

1

C3673

10%

402

CERM

1uF

6.3V

2

1

C3674

10%

402

CERM

1uF

6.3V

2

1

C3675

10%

402

CERM

1uF

6.3V

2

1

C3676

10%

402

CERM

1uF

6.3V

2

1

C3677

10%

402

CERM

1uF

6.3V

2

1

C3678

10%

402

CERM

1uF

6.3V

2

1

C3679

10%

402

CERM

1uF

6.3V

2

1

C3689

10%

402

CERM

1uF

6.3V

2

1

C3688

10%

402

CERM

1uF

6.3V

2

1

C3687

10%

402

CERM

1uF

6.3V

2

1

C3686

10%

402

CERM

1uF

6.3V

2

1

C3685

10%

402

CERM

1uF

6.3V

2

1

C3684

10%

402

CERM

1uF

6.3V

2

1

C3683

10%

402

CERM

1uF

6.3V

2

1

C3682

10%

402

CERM

1uF

6.3V

2

1

C3681

10%

402

CERM

1uF

6.3V

2

1

C3680

A8 MaxBus (CPU0)

115

051-6929

C

36

SYNC_MASTER=MULLET

SYNC_DATE=08/02/2005

=MAXBUS_CPU0_CLK

CLOCKCLOCK

MAXBUS_DATA<3>

MAXBUS_DATA<16>

MAXBUS_DATA<15>

MAXBUS_DATA<14>

MAXBUS_DATA<13>

MAXBUS_DATA<12>

MAXBUS_DATA<11>

MAXBUS_DATA<10>

MAXBUS_DATA<9>

MAXBUS_DATA<8>

MAXBUS_DATA<5> MAXBUS_DATA<6>

MAXBUS_DATA<4>

MAXBUS_DATA<1>

MAXBUS_DATA<0>

MAXBUS_DATA<7>

MAXBUS_DATA<2>

TP_CPU0_OVDDSENSE2

TP_CPU0_OVDDSENSE1

=PP1V5R1V8_MAXBUS

MAXBUS_TT<0>

MAXBUS_TT<2> MAXBUS_TT<3>

MAXBUS_TT<1>

MAXBUS_TSIZ<1>

MAXBUS_TT<4> MAXBUS_TBST_L MAXBUS_TSIZ<0>

MAXBUS_TSIZ<2>

MAXBUS_WT_L

MAXBUS_GBL_L

MAXBUS_CI_L

MAXBUS_ARTRY_L

MAXBUS_AACK_L

MAXBUS_SHD1_L =MAXBUS_CPU0_CLK

MAXBUS_SHD0_L

MAXBUS_TBEN

TP_CPU0_CLKOUT

MAXBUS_CPU0_QREQ_L MAXBUS_CPU0_QACK_L

CPU_CHKSTP_OUT_L

MAXBUS_DATA<63>

MAXBUS_DATA<62>

MAXBUS_DATA<61>

MAXBUS_DATA<60>

MAXBUS_DATA<59>

MAXBUS_DATA<58>

MAXBUS_DATA<57>

MAXBUS_DATA<56>

MAXBUS_DATA<55>

MAXBUS_DATA<53> MAXBUS_DATA<54>

MAXBUS_DATA<52>

MAXBUS_DATA<51>

MAXBUS_DATA<50>

MAXBUS_DATA<49>

MAXBUS_DATA<48>

MAXBUS_DATA<46> MAXBUS_DATA<47>

MAXBUS_DATA<45>

MAXBUS_DATA<44>

MAXBUS_DATA<43>

MAXBUS_DATA<41> MAXBUS_DATA<42>

MAXBUS_DATA<40>

MAXBUS_DATA<38> MAXBUS_DATA<39>

MAXBUS_DATA<36> MAXBUS_DATA<37>

MAXBUS_DATA<35>

MAXBUS_DATA<33> MAXBUS_DATA<34>

MAXBUS_DATA<32>

MAXBUS_DATA<31>

MAXBUS_DATA<30>

MAXBUS_DATA<29>

MAXBUS_DATA<28>

MAXBUS_DATA<27>

MAXBUS_DATA<26>

MAXBUS_DATA<25>

MAXBUS_DATA<24>

MAXBUS_DATA<23>

MAXBUS_DATA<22>

MAXBUS_DATA<21>

MAXBUS_DATA<20>

MAXBUS_DATA<19>

MAXBUS_DATA<18>

MAXBUS_DATA<17>

MAXBUS_EDTI

MAXBUS_DTI<1> MAXBUS_DTI<2>

MAXBUS_CPU0_DRDY_L_R

MAXBUS_CPU0_DBG_L

MAXBUS_CPU0_HIT_L

MAXBUS_TEA_L

MAXBUS_TA_L

MAXBUS_DTI<0>

MAXBUS_CPU0_DRDY_L

MAXBUS_ADDR<1>

MAXBUS_ADDR<18>

MAXBUS_ADDR<2>

MAXBUS_ADDR<0>

MAXBUS_ADDR<16>

MAXBUS_ADDR<21>

MAXBUS_CPU0_BR_L MAXBUS_CPU0_BG_L

MAXBUS_TS_L

MAXBUS_ADDR<3> MAXBUS_ADDR<4>

MAXBUS_ADDR<6>

MAXBUS_ADDR<5>

MAXBUS_ADDR<9>

MAXBUS_ADDR<8>

MAXBUS_ADDR<11>

MAXBUS_ADDR<10>

MAXBUS_ADDR<12>

MAXBUS_ADDR<14>

MAXBUS_ADDR<13>

MAXBUS_ADDR<15>

MAXBUS_ADDR<17>

MAXBUS_ADDR<19> MAXBUS_ADDR<20>

MAXBUS_ADDR<22>

MAXBUS_ADDR<24>

MAXBUS_ADDR<23>

MAXBUS_ADDR<25> MAXBUS_ADDR<26> MAXBUS_ADDR<27> MAXBUS_ADDR<28> MAXBUS_ADDR<29>

MAXBUS_ADDR<31>

MAXBUS_ADDR<30>

MAXBUS_ADDR<7>

CPU0_PULLDOWN

=PP1V5R1V8_MAXBUS

MAXBUS_EDTI

=PP1V5R1V8_MAXBUS

MAXBUS_SHD0_L

MAXBUS_SHD1_L

34

33

32

33

32

21

32

33

32

21

32

21

32

21

32

21

11

9

10

9

6

33

11

33

21

32

34

9

33

9

6

9

6

9

6

9

10

33

10

33

HPR_N

TEMP_CATHODE

TEMP_ANODE

EXT_QUAL

BMODE0* BMODE1*

PMON_IN*

PMON_OUT*

SRESET* HRESET*

MCP*

SMI*

INT*

PLL_CFG1

L2_TSTCLK

L1_TSTCLK

LSSD_MODE*

TRST*

TCK

TMS

TDO

TDI

PLL_CFG3 PLL_CFG4

PLL_CFG2

PLL_CFG0

BVSEL1

PLL_CFG5

LVRAM*

DFS4*

DFS2*

BVSEL0

(3 OF 6)

TABLE_BOMGROUP_ITEM

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TEST2

One of these must be selected to set the Maxbus voltage

- =CPU_HRESET_L (Reset given to all processors)

- =PP1V5R1V8_MAXBUS

Power aliases required by this page:

- CPU0_PLL0_0/1

- CPU0_PLL1_0/1

frequency ratio to attain the desired spec

- CPU_A8

INTERRUPT PULL-UPS

A7PM

1.8V INTERFACE

() Indicates DFS setting supported by A8 only

CPU0 FREQUENCY CONFIGURATION

A7PM BVSEL

A7PM

CFGEXT

A7PM

TEST0

TEST4

TEST3 TEST1

60X BUS MODE

MAX BUS MODE

MODETIED

CPU_HRESET_L

HIGH

CPU0_BMODE0_L

(PROCESSOR)

SIGNAL

- =CPU0_JTAG_TCK

- =CPU0_JTAG_TMS

- =CPU0_JTAG_TDO

- =CPU0_JTAG_TDI

Signal aliases required by this page:

Page Notes

(SPEC request this pull down resistor should less than 250 ohm)

MAXBUS VSEL

- =PP3V3_PWRON_PLLSEL

BOM options provided by this page:

- =CPU0_JTAG_TRST_L

CPU0 PLL CONFIG CIRCUITRY

- MAXBUS_1V8

strap is interpreted correctly

- CPU_A7PM

- CPU0_PLL2_0/1

CPU PULLDOWNS

CPU PULLUPS

PID<0> SELECT

OVDD

BVSEL1

CPU_HRESET_INV

BVSEL0

GND

OVDD

CPU_HRESET_L

BVSEL1

OVDD

GND

OVDD

CPU_HRESET_INV

CPU_HRESET_L

GND

OVDD

GND

OVDD

BVSEL0

RESERVED(1.5V)

2.5V INTERFACE

1.5V INTERFACE

2.5V INTERFACE

OVDD

A8

OVDD

RESERVED

- CPU0_PLL3_0/1

- CPU0_PLL4_0/1

- CPU0_PLL5_0/1 These must be selected to set the CPU core to Maxbus

- MAXBUS_1V5

* the MAXBUS_1V5 option does not exist for A7PM

One of these must be selected to ensure the the above

2.5V INTERFACE

1.8V INTERFACE

2.5V INTERFACE

BUS TYPE SELECT

1/16W

5%

402

MF-LF

10K

21

R3756

1/16W

5%

402

MF-LF

1K

2 1

R3761

10K

MF-LF

402

5%

1/16W

21

R3759

10K

MF-LF

402

5%

1/16W

21

R3758

1/16W

5%

402

MF-LF

10K

21

R3753

1/16W

5%

402

MF-LF

10K

21

R3752

10K

MF-LF

402

5%

1/16W

21

R3769

10K

MF-LF

402

5%

1/16W

21

R3771

CPU_PMON_IN_L

CRITICAL

BGA

XXGHZ-XXV

A8-X.X

OMIT

A5

F1

N19

N18

A4

B9

C6

A2

F9

A9

D9

D10

A7

D7

C7

C8

B8

C9

B10

E8

B3

G8

D4

D8

A6

A11

B6

A12

E10

B7

F8

G9

U3600

10K

MF-LF

402

5%

1/16W

21

R3765

10K

MF-LF

402

5%

1/16W

21

R3766

10K

MF-LF

402

5%

1/16W

21

R3767

MAXBUS_1V5

1/16W

5%

402

MF-LF

10

2 1

R3703

1K

5% 1/16W MF-LF

402

CPU_A8

2

1

R3706

10K

5% 1/16W MF-LF

402

CPU_A7PM

21

R3705

CPU0_PLL5_1

MF-LF

5% 1/16W

402

10K

2

1

R3730

CPU0_PLL5_0

402

MF-LF

5% 1/16W

10K

2

1

R3731

1/16W

5%

402

MF-LF

10K

21

R3757

1/16W

5%

402

MF-LF

1K

2 1

R3772

1/16W

5%

402

MF-LF

22

2 1

R3704

MAXBUS_1V8

1/16W

402

MF-LF

10

5%

2

1

R3702

1/16W

5%

402

MF-LF

CPU0_PLL3_0

10K

2

1

R3727

1/16W

5%

402

MF-LF

10K

CPU0_PLL3_1

2

1

R3726

1/16W

5%

402

MF-LF

10K

CPU0_PLL2_1

2

1

R3724

CPU0_PLL2_0

MF-LF 402

5% 1/16W

10K

2

1

R3725

10K

MF-LF 402

5% 1/16W

CPU0_PLL1_1

2

1

R3722

1/16W

5%

402

MF-LF

CPU0_PLL1_0

10K

2

1

R3723

1/16W

5%

402

MF-LF

10K

CPU0_PLL0_1

2

1

R3720

1/16W

5%

402

MF-LF

CPU0_PLL0_0

10K

2

1

R3721

10K

MF-LF 402

5% 1/16W

CPU0_PLL4_0

2

1

R3729

1/16W

5%

402

MF-LF

10K

CPU0_PLL4_1

2

1

R3728

1K

MF-LF

402

5%

1/16W

2 1

R3707

CPU0_BUSRATIO_28.0X

14.0X

7.0X

111010

CPU0_PLL0_1,CPU0_PLL1_1,CPU0_PLL2_1,CPU0_PLL3_0,CPU0_PLL4_1,CPU0_PLL5_0

CPU0_PLL0_0,CPU0_PLL1_0,CPU0_PLL2_0,CPU0_PLL3_0,CPU0_PLL4_0,CPU0_PLL5_0

CPU0_BUSRATIO_11.5X

(5.75X)

-

000000

CPU0_BUSRATIO_12.5X

(6.25X)

-

111110

CPU0_PLL0_1,CPU0_PLL1_1,CPU0_PLL2_1,CPU0_PLL3_1,CPU0_PLL4_1,CPU0_PLL5_0

CPU0_BUSRATIO_10.5X

(5.25X)

-

100010

CPU0_PLL0_1,CPU0_PLL1_0,CPU0_PLL2_0,CPU0_PLL3_0,CPU0_PLL4_1,CPU0_PLL5_0

CPU0_PLL0_1,CPU0_PLL1_1,CPU0_PLL2_1,CPU0_PLL3_0,CPU0_PLL4_0,CPU0_PLL5_0

CPU0_BUSRATIO_13.5X

(6.75X)

-

111000

CPU0_BUSRATIO_16.0X

8.0X 4.0X

110110

CPU0_PLL0_1,CPU0_PLL1_1,CPU0_PLL2_0,CPU0_PLL3_1,CPU0_PLL4_1,CPU0_PLL5_0

CPU0_BUSRATIO_18.0X

9.0X 4.5X

001010

CPU0_PLL0_0,CPU0_PLL1_0,CPU0_PLL2_1,CPU0_PLL3_0,CPU0_PLL4_1,CPU0_PLL5_0

CPU0_BUSRATIO_20.0X

10.0X

5.0X

001110

CPU0_PLL0_0,CPU0_PLL1_0,CPU0_PLL2_1,CPU0_PLL3_1,CPU0_PLL4_1,CPU0_PLL5_0

CPU0_BUSRATIO_13.0X

6.5X

(3.25X)

010110

CPU0_PLL0_0,CPU0_PLL1_1,CPU0_PLL2_0,CPU0_PLL3_1,CPU0_PLL4_1,CPU0_PLL5_0

CPU0_PLL0_1,CPU0_PLL1_0,CPU0_PLL2_0,CPU0_PLL3_1,CPU0_PLL4_0,CPU0_PLL5_0

CPU0_BUSRATIO_5.5X

(2.75X)

-

100100

CPU0_PLL0_1,CPU0_PLL1_1,CPU0_PLL2_0,CPU0_PLL3_1,CPU0_PLL4_0,CPU0_PLL5_0

CPU0_BUSRATIO_6.0X

3.0X

-

110100

CPU0_PLL0_0,CPU0_PLL1_1,CPU0_PLL2_0,CPU0_PLL3_1,CPU0_PLL4_0,CPU0_PLL5_0

CPU0_BUSRATIO_6.5X

(3.25X)

-

010100

CPU0_PLL0_0,CPU0_PLL1_0,CPU0_PLL2_1,CPU0_PLL3_0,CPU0_PLL4_0,CPU0_PLL5_0

CPU0_BUSRATIO_7.0X

3.5X

-

001000

CPU0_BUSRATIO_15.0X

7.5X

(3.75X)

000110

CPU0_PLL0_0,CPU0_PLL1_0,CPU0_PLL2_0,CPU0_PLL3_1,CPU0_PLL4_1,CPU0_PLL5_0

CPU0_BUSRATIO_11.0X

5.5X

(2.75X)

100110

CPU0_PLL0_1,CPU0_PLL1_0,CPU0_PLL2_0,CPU0_PLL3_1,CPU0_PLL4_1,CPU0_PLL5_0

CPU0_BUSRATIO_10.0X

5.0X 2.5X

101010

CPU0_PLL0_1,CPU0_PLL1_0,CPU0_PLL2_1,CPU0_PLL3_0,CPU0_PLL4_1,CPU0_PLL5_0

F/4

PLL BITS

DFS SUPPORT

F/2 012345

CPU0_PLL0_0,CPU0_PLL1_1,CPU0_PLL2_1,CPU0_PLL3_0,CPU0_PLL4_0,CPU0_PLL5_0

CPU0_BUSRATIO_8.5X

(4.25X)

-

011000

CPU0_BUSRATIO_9.0X

4.5X

(2.25X)

011110

CPU0_PLL0_0,CPU0_PLL1_1,CPU0_PLL2_1,CPU0_PLL3_1,CPU0_PLL4_1,CPU0_PLL5_0

CPU0_BUSRATIO_12.0X

6.0X 3.0X

101110

CPU0_PLL0_1,CPU0_PLL1_0,CPU0_PLL2_1,CPU0_PLL3_1,CPU0_PLL4_1,CPU0_PLL5_0

A8 Configuration Straps

37

115

C

051-6929

SYNC_MASTER=MULLET

SYNC_DATE=08/02/2005

CPU0_PLL0_1,CPU0_PLL1_0,CPU0_PLL2_1,CPU0_PLL3_1,CPU0_PLL4_0,CPU0_PLL5_0

CPU0_BUSRATIO_5.0X

2.5X

-

101100

CPU0_PLL0_0,CPU0_PLL1_1,CPU0_PLL2_1,CPU0_PLL3_1,CPU0_PLL4_0,CPU0_PLL5_0

CPU0_BUSRATIO_9.5X

(4.75X)

-

011100

--

CPU0_BUSRATIO_1.0X

CPU0_PLL0_0,CPU0_PLL1_0,CPU0_PLL2_1,CPU0_PLL3_1,CPU0_PLL4_0,CPU0_PLL5_0

001100

--

CPU0_BUSRATIO_2.0X

010000

CPU0_PLL0_0,CPU0_PLL1_1,CPU0_PLL2_0,CPU0_PLL3_0,CPU0_PLL4_0,CPU0_PLL5_0

100000

--

CPU0_BUSRATIO_3.0X

CPU0_PLL0_1,CPU0_PLL1_0,CPU0_PLL2_0,CPU0_PLL3_0,CPU0_PLL4_0,CPU0_PLL5_0

101000

-

2.0X

CPU0_BUSRATIO_4.0X

CPU0_PLL0_1,CPU0_PLL1_0,CPU0_PLL2_1,CPU0_PLL3_0,CPU0_PLL4_0,CPU0_PLL5_0

CPU0_BUSRATIO_17.0X

8.5X

(4.25X)

000010

CPU0_PLL0_0,CPU0_PLL1_0,CPU0_PLL2_0,CPU0_PLL3_0,CPU0_PLL4_1,CPU0_PLL5_0

CPU0_BUSRATIO_14.0X

7.0X 3.5X

110010

CPU0_PLL0_1,CPU0_PLL1_1,CPU0_PLL2_0,CPU0_PLL3_0,CPU0_PLL4_1,CPU0_PLL5_0

CPU0_PLL0_1,CPU0_PLL1_1,CPU0_PLL2_0,CPU0_PLL3_0,CPU0_PLL4_0,CPU0_PLL5_0

CPU0_BUSRATIO_8.0X

4.0X 2.0X

110000

CPU0_BUSRATIO_21.0X

10.5X

(5.25X)

010010

CPU0_PLL0_0,CPU0_PLL1_1,CPU0_PLL2_0,CPU0_PLL3_0,CPU0_PLL4_1,CPU0_PLL5_0

CPU0_PLL0_0,CPU0_PLL1_0,CPU0_PLL2_0,CPU0_PLL3_1,CPU0_PLL4_0,CPU0_PLL5_0

CPU0_BUSRATIO_7.5X

(3.75X)

-

000100

CPU0_BUSRATIO_24.0X

12.0X

6.0X

011010

CPU0_PLL0_0,CPU0_PLL1_1,CPU0_PLL2_1,CPU0_PLL3_0,CPU0_PLL4_1,CPU0_PLL5_0

CPU0_SRESET_L

CPU_BVSEL<1>

CPU0_BMODE1_L

=CPU_HRESET_L

CPU0_L2TSTCLK

CPU_PMON_IN_L

CPU0_DFS4_L

CPU0_LVRAM_L

CPU_MCP_L

CPU0_DFS2_L

CPU_CHKSTP_OUT_L

CPU_LSSD_MODE_L

CPU0_L1TSTCLK

TP_CPU0_HPR_N

TP_CPU0_TEMP_CATHODE

TP_CPU0_TEMP_ANODE

CPU0_DFS4_L CPU0_PLL_CFG<5>

CPU0_DFS2_L

CPU_BVSEL<1>

CPU0_EXT_QUAL

CPU0_BMODE0_L CPU0_BMODE1_L

TP_CPU0_PMON_OUT_L

CPU0_SRESET_L =CPU_HRESET_L

CPU0_SMI_L

MAXBUS_CPU0_INT_L

CPU0_PLL_CFG<1>

CPU0_L2TSTCLK

CPU0_L1TSTCLK

CPU_LSSD_MODE_L

=JTAG_CPU0_TRST_L

=JTAG_CPU0_TCK

=JTAG_CPU0_TMS

=JTAG_CPU0_TDO

=JTAG_CPU0_TDI

CPU0_PLL_CFG<3>

CPU0_PLL_CFG<2>

CPU_BVSEL<0>

=PP1V5R1V8_MAXBUS

=CPU_HRESET_LCPU0_BMODE0_L

=PP1V5R1V8_MAXBUS

CPU0_PLL_CFG<5>

CPU0_PLL_CFG<4>

CPU0_PLL_CFG<3>

CPU0_PLL_CFG<2>

CPU0_PLL_CFG<1>

CPU0_PLL_CFG<0>

=PP1V5R1V8_MAXBUS

CPU0_PLL_CFG<0>

CPU0_PLL_CFG<4>

CPU_BVSEL<0>

=PP1V5R1V8_MAXBUS

CPU0_LVRAM_L

CPU_MCP_L

CPU0_SMI_L

CPU0_EXT_QUAL

34

33

32

34

32

21

34

21

34

11

34

33

34

11

34

6

34

9

34

10

11 34

10

34

10

34

10

34

SENSEVDD1 SENSEVDD2

AVDD

VDD

(4 OF 6)

VDD

N/C_36

N/C_38 N/C_39

N/C_37

N/C_35

N/C_34

N/C_33

N/C_32

N/C_31

N/C_30

N/C_29

N/C_28

N/C_27

N/C_26

N/C_25

N/C_24

N/C_23

N/C_22

N/C_21

N/C_20

N/C_19

N/C_18

N/C_17

N/C_15

N/C_14

N/C_13

N/C_12

N/C_11

N/C_10

N/C_16

N/C_9

N/C_8

N/C_7

N/C_6

N/C_5

N/C_4

N/C_3

N/C_2

N/C_1

SENSEGND1 SENSEGND2

GND GND

(6 OF 6)

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

24 X 10 UF (0603)

40 X 1 UF (0402)

VCORE BULK CAPS

Page Notes

Power aliases required by this page:

Signal aliases required by this page: (NONE)

BOM options provided by this page:

(NONE)

NC

NCNCNC

NC

NCNCNC

NC

NCNC

NC

NCNCNC

NC

NCNC

NC

NCNCNC

NC

NCNC

NC

NCNCNC

NC

NCNC

NC

NC NC

NCNCNC NC

NCNC

NCNCNC NC

- =PPVCORE_CPU0

(Kelvin sense points)

4V

X5R 603

20%

10uF

2

1

C3802

4V

X5R 603

20%

10uF

2

1

C3801

X5R 603

20%

10uF

4V

2

1

C3800

4V

X5R 603

20%

10uF

2

1

C3803

4V

X5R 603

20%

10uF

2

1

C3804

4V

X5R 603

20%

10uF

2

1

C3805

4V

X5R 603

20%

10uF

2

1

C3806

4V

X5R 603

20%

10uF

2

1

C3807

4V

X5R 603

20%

10uF

2

1

C3808

4V

X5R 603

20%

10uF

2

1

C3809

4V

X5R 603

20%

10uF

2

1

C3819

4V

X5R 603

20%

10uF

2

1

C3818

4V

X5R 603

20%

10uF

2

1

C3817

4V

X5R 603

20%

10uF

2

1

C3816

4V

X5R 603

20%

10uF

2

1

C3815

4V

X5R 603

20%

10uF

2

1

C3814

4V

X5R 603

20%

10uF

2

1

C3813

4V

X5R 603

20%

10uF

2

1

C3812

4V

X5R 603

20%

10uF

2

1

C3811

4V

X5R 603

20%

10uF

2

1

C3810

4V

X5R 603

20%

10uF

2

1

C3823

4V

X5R 603

20%

10uF

2

1

C3821

4V

X5R 603

20%

10uF

2

1

C3822

4V

X5R 603

20%

10uF

2

1

C3820

BGA

A8-X.X

XXGHZ-XXV

OMIT

CRITICAL

K10

K8

J13

J11

J9

P18

P16

J7

N17

N15

M18

M16

M14

H19

H17

H14

G16

G11

H12

F19

F17

F12

E16

E13

C13

B19

B17

A18

A16

H10

A13

M12

M10

M8

L13

L11

L9

L7

K14

K12

H8

G13

N12

A8

U3600

10%

402

CERM

1UF

6.3V

2

1

C3830

10%

402

CERM

1UF

6.3V

2

1

C3831

10%

402

CERM

1UF

6.3V

2

1

C3832

10%

402

CERM

1UF

6.3V

2

1

C3833

10%

402

CERM

1UF

6.3V

2

1

C3834

10%

402

CERM

1UF

6.3V

2

1

C3835

10%

402

CERM

1UF

6.3V

2

1

C3836

10%

402

CERM

1UF

6.3V

2

1

C3837

10%

402

CERM

1UF

6.3V

2

1

C3845

10%

402

CERM

1UF

6.3V

2

1

C3844

10%

402

CERM

1UF

6.3V

2

1

C3843

10%

402

CERM

1UF

6.3V

2

1

C3842

10%

402

CERM

1UF

6.3V

2

1

C3841

10%

402

CERM

1UF

6.3V

2

1

C3840

10%

402

CERM

1UF

6.3V

2

1

C3839

10%

402

CERM

1UF

6.3V

2

1

C3838

10%

402

CERM

1UF

6.3V

2

1

C3853

10%

402

CERM

1UF

6.3V

2

1

C3852

10%

402

CERM

1UF

6.3V

2

1

C3851

10%

402

CERM

1UF

6.3V

2

1

C3850

10%

402

CERM

1UF

6.3V

2

1

C3849

10%

402

CERM

1UF

6.3V

2

1

C3848

10%

402

CERM

1UF

6.3V

2

1

C3847

10%

402

CERM

1UF

6.3V

2

1

C3846

10%

402

CERM

1UF

6.3V

2

1

C3861

10%

402

CERM

1UF

6.3V

2

1

C3860

10%

402

CERM

1UF

6.3V

2

1

C3859

10%

402

CERM

1UF

6.3V

2

1

C3858

10%

402

CERM

1UF

6.3V

2

1

C3857

10%

402

CERM

1UF

6.3V

2

1

C3856

10%

402

CERM

1UF

6.3V

2

1

C3855

10%

402

CERM

1UF

6.3V

2

1

C3854

CRITICAL

OMIT

XXGHZ-XXV

A8-X.X

BGA

G12

N13

B15

A15

G14

F14

E14

D14

L19

K19

J19

L18

K18

J18

L17

K17

J17

L16

C14

K16

J16

H16

D19

C19

D18

C18

D17

C17

D16

B14

C16

L15

K15

J15

H15

G15

F15

E15

D15

C15

A14

H7

H4

G17

P19

P15

N16

N14

M19

M17

M15

L14

F3

J14

H18

G19

F18

F16

F13

E19

E12

B18

B16

E17

B13

A19

A17

V15

V11

V8

V5

U17

U13

U3

D13

T10

T7

R17

R14

R5

P12

P9

P3

N7

M13

D6

M11

M9

M7

M4

L12

L10

L8

L6

K13

K11

C3

K9

K3

K7

J12

J10

J8

J6

H13

H11

H9

B5

U3600

A8 Power (CPU0)

051-6929

C

115

38

SYNC_MASTER=MULLET

SYNC_DATE=08/02/2005

TP_CPU0_SENSEGND2

TP_CPU0_SENSEGND1

TP_CPU0_SENSEVDD1 TP_CPU0_SENSEVDD2

=PPVCORE_CPU0

=PPAVDD_CPU0

35

10

D0 D1 D2 D3 D4

SKP/SDN

VCC VDD

V+

ILIM

FBS

GNDS

A/B

REF

TON CC

BST

DH

LX DL

GND

VGATE

FB

TIME

G

D

S

G

D

S

SYM_VER-2

GND

OE

SEL

B4

B3 A4

A3

A2 B2

Y3

Y4

A1 B1

VCC

Y2

Y1

TABLE_5_ITEM

REFERENCE DESIGNATOR(S)

BOM OPTION

TABLE_5_HEAD

QTY

DESCRIPTION

PART#

TABLE_5_ITEM

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

TABLE_5_ITEM

(CPU SPEC: 1.220V -> 0.930V)

1.320V -> 0.940V

(CPU SPEC: 1.280V -> 0.930V)

(CPU SPEC: 1.300V -> 0.930V)

1.370V -> 0.940V

Keep trace fat (1.00-2.54 mm) and short!!

to GND at bottom-side FET

Connect MAX1717 GND pin 13

PLACE CLOSE TO

<D3>

1.260V -> 0.940V

MAX1717 VID CAN TAKE 3.3V TO 5.5V INPUTS

(WITH VCORE OFFSET)

1.67GHZ

(CPU SPEC: 1.330V -> 0.930V)

1.340V -> 0.940V

DIFFERENTIAL_PAIR

<D0>

1.5GHZ

If all pull-ups are >=100K and all

"Low" and "Mid" States

<D1>

to VID_B.

NET_TYPE

PHYSICAL

ELECTRICAL_CONSTRAINT_SET

NOTE: R3945 (R2) NO STUFFED FOR NO OFFSET CASE

"High" State

A

B

(VCORE_VPLUS)

(VCORE_SNS)

(VCORE_GNDSNS)

NC (RFU)

1.275

0.925

0.950

0.975

1.000

1.025

1.050

1.075

1.100

1.125

1.150

1.175

1.200

1.225

1.250

1.40

1.45

1.50

1.55

1.60

1.65

1.70

1.75

1.80

1.85

1.90

1.95

2.00

1

1 1

1

1 1

1

0

0 0

0

D<4..0> <= 1K PU >= 100K PU

<= 1K PD

>= 100K PD

1 0 0

1

Hi/Fast

1 1 0

0

A/B_ =

GROUND SENSE VOLTAGE DIVIDER

ROUTE AS DIFFERENTIAL PAIR

NO CPU NO CPU

1.30

1.35

When A/B_ is high (fast): D4-D0 read as-is When A/B_ is low (slow): <=1K-ohm -> 0

pull-downs are <=1K, V = V .

TO PINS 15 & 13

R1

R2

>=100K-ohm -> 1

D4=0D4=1

D3 D2 D1 D0

DACV

SPACING

This allows for an offset to the ground sense to adjust the output voltage.

FMAX CONNECTOR

Keep trace fat and short!!

VREF = 2.0V WITH A 0.85 SCALE FACTOR, HENCE VOFFSET = 1.7V * (R1/(R1+R2)) AND VCORE = VDAC + VOFFSET.

CLOSEST TO CPU

PIN OF 1000uF CAP

PLACE THIS SHORT AT

0

FOR V-STEP:

Lo/Slow

1

0

OUTPUT VOLTAGE

Pullup on =CPU0_VID_AB_SEL will set default mux state

SM

XW3900

CASE-D2E-LF

POLY

2.5V-ESR9V

330uF

20%

CRITICAL

2

1

C3916

SM

2 1

XW3901

CASE-D2E-LF

POLY

2.5V-ESR9V

330uF

20%

CRITICAL

2

1

C3915

SOD-123

B0530WXF

2

1

D3901

603

1UF

20% 10V CERM

2

1

C3900

20

5% 1/16W MF-LF

402

2

1

R3960

CASE-D2E-LF

POLY

2.5V-ESR9V

330uF

20%

CRITICAL

2

1

C3914

POLY

2.5V-ESR9V

330uF

20%

CRITICAL

CASE-D2E-LF

2

1

C3912

CASE-D2E-LF

POLY

2.5V-ESR9V

330uF

20%

CRITICAL

2

1

C3913

603

CERM

25V

20%

0.1UF

2

1

C3951

CRITICAL

MAX1717

QSOP-LF

12

15

7

1

8

3

2

9

23

10 11

13

5

4

14

24

17

18

19

20

21

6

22

16

U3900

100

402

5% 1/16W MF-LF

21

R3910

SM

XW3911

CERM

50V

20%

0.001UF

402

2

1

C3950

390K

5% 1/16W MF-LF

402

2

1

R3950

603

CERM

10V

20%

1UF

2

1

C3960

MF-LF

402

1/16W

5%

0

2

1

R3961

402

CERM

25V

5%

220PF

2

1

C3963

27.4K

1% 1/16W MF-LF

402

2

1

R3962

CERM

10V

1UF

603

20%

2

1

C3962

402

MF-LF

1/16W

1%

12.7K

2

1

R3963

402

0.01UF

CERM

16V

20%

2

1

C3964

NO STUFF

0

5% 1/16W MF-LF 402

2

1

R3988

Q16BST&Q41

402

0

5% 1/16W MF-LF

2

1

R3989

SM

XW3910

1/16W MF-LF

2.0K

1%

402

OMIT

2

1

R3946

603

162K

1% 1/10W MF-LF

VCORE_OFFSET

2

1

R3945

66.5K

1% 1/16W MF-LF

402

2

1

R3964

0.0047uF

10% 25V CERM

NO STUFF

402

2

1

C3902

402

CERM

50V

10%

0.0022UF

2

1

C3903

2.2

1/4W

5%

MF-LF

1206

NO STUFF

2

1

R3901

603

2.2

5% 1/10W MF-LF

2 1

R3951

0.0022uF

10%

NO STUFF

603

CERM

50V

2

1

C3901

CASE-D2E-LF

POLY

2.5V-ESR9V

330uF

20%

CRITICAL

2

1

C3911

CASE-D2E-LF

POLY

2.5V-ESR9V

330uF

CRITICAL

20%

2

1

C3910

M-ST-SM-52465-1217

OMIT

CRITICAL

3

2

1

7

8

9

10

11

6

5

4

12

J3999

402

OMIT

2.05K

1% 1/16W MF-LF

21

R3998

402

OMIT

MF-LF

1/16W

1%

100

21

R3999

CASE-D2E-LF

POLY

2.5V-ESR9V

330uF

20%

CRITICAL

2

1

C3917

CASE-D2E-LF

330uF

20%

2.5V-ESR9V POLY

CRITICAL

2

1

C3918

VCORE_OFFSET_SW

2N7002DW-X-F

SOT-363

4

5

3

Q3940

NO STUFF

402

0

MF-LF

1/16W

5%

21

R3940

MF-LF

VCORE_OFFSET_SW

402

1/16W

5%

0

AB_SEL_LOW

21

R3941

100K

402

MF-LF

1/16W

5%

VCORE_OFFSET_SW

21

R3943

OMIT

6.04K

1% 1/16W MF-LF 402

2

1

R3944

402

MF-LF

1/16W

5%

100K

NO STUFF

2

1

R3942

SOT-363

2N7002DW-X-F

VCORE_OFFSET_SW

1

2

6

Q3940

CRITICAL

MF-LF

0.001

1% 1W

2512

21

R3900

NO STUFF

402

MF-LF

1/16W

5%

470K

2

1

R3980

Q16BST&Q41

470K

5% MF-LF

402

1/16W

2

1

R3981

MF-LF

1/16W

Q16BST&Q41

402

5%

470K

2

1

R3982

NO STUFF

470K

5% 1/16W MF-LF 402

2

1

R3983

5%

470K

Q16BST&Q41

402

MF-LF

1/16W

2

1

R3984

NO STUFF

402

MF-LF

1/16W

5%

470K

2

1

R3985

Q16BST&Q41

470K

5% 1/16W MF-LF 402

2

1

R3986

NO STUFF

470K

5% 1/16W MF-LF 402

2

1

R3987

HAT2168H

CRITICAL

LFPAK

321

4

5

Q3900

LFPAK

HAT2160H

CRITICAL

321

4

5

Q3902

CRITICAL

HAT2160H

LFPAK

321

4

5

Q3903

CRITICAL

1.0uH-20.5

SM1

3

2

1

L3900

CRITICAL

SNM540XF

PWRMITE

3

2

1

D3900

I400

I401

CRITICAL

CPU_VCORE_3STATES

74CBTLV3257

QSOP

12

9

7

4

16

1

13

14

10

11

6

5

3

2

8

15

U3990

470K

5% 1/16W MF-LF 402

NO STUFF

2

1

R3976

402

MF-LF

1/16W

5%

470K

NO STUFF

2

1

R3974

MF-LF 402

1/16W

5%

470K

NO STUFF

2

1

R3972

MF-LF 402

1/16W

5%

470K

NO STUFF

2

1

R3970

402

MF-LF

1/16W

5%

470K

NO STUFF

2

1

R3977

MF-LF

1/16W

5%

470K

NO STUFF

402

2

1

R3975

470K

5% 1/16W MF-LF 402

NO STUFF

2

1

R3973

470K

5% 1/16W MF-LF 402

NO STUFF

2

1

R3971

CERM 402

10V

20%

0.1uF

CPU_VCORE_3STATES

2

1

C3990

0

5% 1/16W SM-LF

CPU_VCORE_2STATES

5678

4321

RP3990

402

MF-LF

1/16W

5%

1K

CPU_VCORE_3STATES

2

1

R3990

X5R

10% 25V

1206

CRITICAL

10uF

2

1

C3937

10%

CRITICAL

10uF

1206

X5R

25V

2

1

C3938

1206

25V

10%

CRITICAL

X5R

10uF

2

1

C3939

CRITICAL

10%

10uF

25V X5R 1206

2

1

C3940

25V

10%

CRITICAL

X5R

10uF

1206

2

1

C3944

1206

10uF

10% 25V

CRITICAL

X5R

2

1

C3945

25V

10%

CRITICAL

10uF

1206

X5R

2

1

C3946

X5R

CRITICAL

10uF

1206

25V

10%

2

1

C3947

25V

10%

CRITICAL

X5R

10uF

1206

2

1

C3942

10uF

X5R

CRITICAL

10% 25V

1206

2

1

C3941

1206

10uF

X5R

CRITICAL

10% 25V

2

1

C3949

1206

10uF

CRITICAL

25V

10% X5R

2

1

C3948

X5R

10% 25V

1206

CRITICAL

10uF

2

1

C3943

1/16W

100K

1% MF-LF

402

2

1

R3965

114S0270

R3946

CPU0_VCORE_1V22

1

RES,3.48K,1%,1/16W,MF-LF,402,SMD

R3944

1

CPU0_VCORE_1V33

114S0294

RES,6.04K,1%,1/16W,MF-LF,402,SMD

RES,2.61K,1%,1/16W,MF-LF,402,SMD

114S0258

1

R3944

CPU0_VCORE_1V22

114S0246

1

CPU0_VCORE_1V28

R3946

RES,2.0K,1%,1/16W,MF-LF,402,SMD

115

051-6929

C

39

SYNC_MASTER=N/A

SYNC_DATE=N/A

CPU VCore Supply

R3946

1

CPU0_VCORE_1V30

RES,4.02K,1%,1/16W,MF-LF,402,SMD

114S0276

RES,2.0K,1%,1/16W,MF-LF,402,SMD

114S0246

R3946

1

CPU0_VCORE_1V33

114S0254

1

R3944

CPU0_VCORE_1V30

RES,2.43K,1%,1/16W,MF-LF,402,SMD

RES,6.04K,1%,1/16W,MF-LF,402,SMD

114S0294

CPU0_VCORE_1V28

R3944

1

VCORE_VID<2>

=PP5V_PWRON_CPUVCORE_PWRSEQ

=PP3V3_PWRON_CPUVCORE_VID

VOLTAGE=12.8V MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm

VCORE_VCC

CPU_VCORE_SNUB

VCORE_FB

MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm

VOLTAGE=0V

VCORE_GND

MIN_NECK_WIDTH=0.25 mm

VCORE_DL

MIN_LINE_WIDTH=0.5 mm

VCORE_BST

VCORE_DH

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VCORE_BOOST

VCORE_GNDDIV

VCORE_GNDDIV_TEST

=PP3V3_PWRON_CPUVCORE_OFFSET

VCORE_GNDSNS_TEST

VCORE_GNDSNS

SYS_POWER_BuTTON_L

SYS_RESET_BUTTON_L

VCORE_VID<3> VCORE_VID<4>

VCORE_VID<2>

VCORE_VID<1>

VCORE_VID<0>

VCORE_VID_A<2> VCORE_VID_A<3>

VCORE_VID_A<1>

VCORE_VID_A<4>

VCORE_VID_A<3>

VCORE_VID_A<2>

VCORE_VID_A<1>

VCORE_VID<3>

VCORE_VID<4>

VCORE_VID<1>

VCORE_VID_A<1>

VCORE_VID_A<2> VCORE_VID_B<2> VCORE_VID_A<3> VCORE_VID_B<3> VCORE_VID_A<4> VCORE_VID_B<4>

=CPU0_VID_AB_SEL

VCORE_VID_B<1>

VID_MUX_OE_L

=PPVCORE_CPU_REG

=CPU0_MAX1717_AB_SEL

VCORE_TIME

=VCORE_PGOOD

VCORE_TON

VCORE_VID_B<3>

VCORE_VID_B<2>

VCORE_VID_B<1>

VCORE_VID_B<4>

=CPU0_MAX1717_AB_SEL

VCORE_ILIM

THERM

VCORE_SNS

THERM

=PP3V3_PWRON_CPUVCORE_VID

VCORE_GNDSNS

VOLTAGE=0V

MIN_NECK_WIDTH=0.15 mm

MIN_LINE_WIDTH=0.25 mm

VCORE_SNS

VOLTAGE=1.3V

MIN_NECK_WIDTH=0.15 mm

MIN_LINE_WIDTH=0.25 mm

VCORE_GNDDIV

VCORE_GNDA

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

VOLTAGE=0V

MIN_NECK_WIDTH=0.15 mm

MIN_LINE_WIDTH=0.25 mm

VCORE_VID<4>

MIN_NECK_WIDTH=0.15 mm

VCORE_VID<3>

MIN_LINE_WIDTH=0.25 mm

VCORE_VID<2>

MIN_NECK_WIDTH=0.15 mm

MIN_LINE_WIDTH=0.25 mm

MIN_NECK_WIDTH=0.15 mm

MIN_LINE_WIDTH=0.25 mm

VCORE_VID<0> VCORE_VID<1>

MIN_NECK_WIDTH=0.15 mm

MIN_LINE_WIDTH=0.25 mm

VCORE_VID_A<4>

VCORE_GNDSNS

THERM THERM

VCORE_SEL_ON

VCORE_SEL_OFF_PU

VCORE_CC

VCORE_REF

=PP5V_PWRON_CPUVCORE_VDD

VCORE_LX

CPUVCORE_VSENSE_R

VCORE_CPU0_SHDN_L

=PPVIN_CPUVCORE_MAX1717

57 30

36

25

36

10

36

10

36

24

24 36

36

36 36

36

11

36

10

11

26

36

11

36

10

36

10

26

10

PG EN

VIN

ADJ

VOUT

GND

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

TABLE_5_ITEM

REFERENCE DESIGNATOR(S)

BOM OPTION

TABLE_5_HEAD

QTY

DESCRIPTION

PART#

AVDD=0.59*(1+R4620/R4621)

CPU PLL POWER SUPPLY

402

6.3V CERM

1UF

10%

2

1

C4625

24.9K

1/16W

1%

402

MF-LF

2

1

R4620

OMIT

1% MF-LF

402

1/16W

23.2K

2

1

R4621

2.2uF

10%

603-1

6.3V CERM1

2

1

C4600

10V 402

CERM

20%

0.1UF

2

1

C4610

FAN2558

CRITICAL

SOT23-6-LF

61

4

2

3 5

U4600

CERM 402

16V

0.01UF

10%

2

1

C4620

MF-LF

1% 1/16W

402

357K

NO STUFF

2

1

R4611

5%

0

402

MF-LF

1/16W

21

R4600

402

5%

MF-LF

10

1/16W

21

R4625

20% 10V

0.1UF

CERM 402

2

1

C4626

805

4.7UF

CERM

20%

6.3V

2

1

C4627

CRITICAL

SOT23

BAT54E3

3 1

D4610

402

100K

1% 1/16W MF-LF

21

R4610

115

051-6929

C

46

SYNC_MASTER=N/A

SYNC_DATE=N/A

CPU AVDD Supply

CPU0_AVDD_1V33

1

RES,19.6K,1%,1/16W,MF-LF,402,SMD

114S0342

R4621

1

RES,20.5K,1%,1/16W,MF-LF,402,SMD

114S0344

CPU0_AVDD_1V30

R4621

1

CPU0_AVDD_1V28

RES,21.5K,1%,1/16W,MF-LF,402,SMD

114S0346

1

114S0349

CPU0_AVDD_1V22

R4621

RES,23.2K,1%,1/16W,MF-LF,402,SMD

=PPVIN_CPU0_AVDD

FAN2558_ADJ_CPU0

VOLTAGE=1.22V MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm PPVOUT_CPU0_AVDD_R

=PPVOUT_CPU0_AVDD

FAN2558_EN_CPU0

VOLTAGE=3.3V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

PPVIN_CPU0_AVDD

CPU_AVDD_EN

10

26

DDR2 POWER

(8 of 14) VTT18_0 VTT18_1 VTT18_2 VTT18_3 VTT18_4

VTT18_6 VTT18_7 VTT18_8

VTT18_10 VTT18_11

VTT18_9

VTT18_13

VTT18_12

VTT18_16

VTT18_14 VTT18_15

VTT18_17 VTT18_18

VTT18_21

VTT18_19 VTT18_20

VTT18_22 VTT18_23 VTT18_24 VTT18_25 VTT18_26

VTT18_29

VTT18_28

VTT18_27

VTT18_30 VTT18_31

VTT18_38 VTT18_39

VTT18_37

VTT18_36

VTT18_35

VTT18_34

VTT18_33

VTT18_32

VTT18_40 VTT18_41 VTT18_42

VTT18_44 VTT18_45 VTT18_46 VTT18_47

VTT18_43

VTT18_5

(7 of 14)

MEMORY INTERFACE

DDR_D_02_H

SD_REF_H

DDR_D_62_H

DDR_D_60_H

DDR_D_59_H

DDR_D_04_H

DDR_D_03_H

DDR_D_05_H DDR_D_06_H DDR_D_07_H

DDR_D_09_H

DDR_D_08_H

DDR_D_11_H

DDR_D_10_H

DDR_D_12_H

DDR_D_14_H

DDR_D_13_H

DDR_D_15_H

DDR_D_17_H

DDR_D_16_H

DDR_D_18_H DDR_D_19_H DDR_D_20_H

DDR_D_22_H

DDR_D_21_H

DDR_D_23_H DDR_D_24_H DDR_D_25_H

DDR_D_27_H

DDR_D_26_H

DDR_D_30_H

DDR_D_29_H

DDR_D_28_H

DDR_D_31_H DDR_D_32_H DDR_D_33_H

DDR_D_35_H

DDR_D_34_H

DDR_D_36_H

DDR_D_38_H

DDR_D_37_H

DDR_D_40_H

DDR_D_39_H

DDR_D_41_H DDR_D_42_H DDR_D_43_H

DDR_D_45_H

DDR_D_44_H

DDR_D_46_H DDR_D_47_H DDR_D_48_H

DDR_D_50_H

DDR_D_49_H

DDR_D_51_H DDR_D_52_H DDR_D_53_H

DDR_D_55_H

DDR_D_54_H

DDR_D_56_H DDR_D_57_H DDR_D_58_H

DDR_D_61_H

DDR_D_63_H

DDR_VREF_1_H

DDR_VREF_0_H

DDR_VREF_3_H

DDR_VREF_2_H

DDR_D_00_H DDR_A_00_H

DDR_A_01_H DDR_A_02_H

DDR_A_04_H

DDR_A_03_H

DDR_A_05_H DDR_A_06_H DDR_A_07_H DDR_A_08_H DDR_A_09_H DDR_A_10_H

DDR_A_12_H

DDR_A_11_H

DDR_BA_0_H

DDR_A_13_H

DDR_BA_1_H DDR_BA_2_H

DDR_CS_0_L DDR_CS_1_L DDR_CS_2_L DDR_CS_3_L

DDR_DQS_0_L

DDR_DQS_2_L

DDR_DQS_1_L

DDR_DQS_3_L DDR_DQS_4_L DDR_DQS_5_L DDR_DQS_6_L DDR_DQS_7_L

DDR_DM_0_L

DDR_DM_2_L

DDR_DM_1_L

DDR_DM_3_L DDR_DM_4_L DDR_DM_5_L DDR_DM_6_L DDR_DM_7_L

DDR_RAS_L

DDR_WE_L

DDR_CAS_L

DDR_CKE_0_L DDR_CKE_1_L DDR_CKE_2_L DDR_CKE_3_L

ODT0

DDR_MCLK_0_P

ODT1

DDR_MCLK_0_N

DDR_MCLK_1_N

DDR_MCLK_1_P

DDR_MCLK_2_P DDR_MCLK_2_N

DDR_MCLK_3_P DDR_MCLK_3_N

DDR_D_01_H

OUT OUT

OUT

BI

OUT

BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

1 X 10uF (0603) 40 X 1uF (0402)

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

DIFFERENTIAL_PAIR

NET_TYPE

SPACING

(40 Balls on I2)

DDR2 I/O DECOUPLING

U2100.V21U2100.AG28

Power aliases required by this page:

- =PP1V8_PWRON_I2_RAM

- =PP1V8_RAM_I2_VREF

Signal aliases required by this page:

BOM options provided by this page:

(NONE)

6.3V

20%

603

X5R

10UF

2

1

C4749

6.3V

10%

402

CERM

1uF

2

1

C4751

6.3V

10%

402

CERM

1uF

2

1

C4752

6.3V

10%

402

CERM

1uF

2

1

C4753

6.3V 402

10% CERM

1uF

2

1

C4754

6.3V

10%

402

CERM

1uF

2

1

C4755

6.3V

10%

402

CERM

1uF

2

1

C4756

6.3V

10%

402

CERM

1uF

2

1

C4757

6.3V

10%

402

CERM

1uF

2

1

C4758

6.3V

10%

402

CERM

1uF

2

1

C4759

6.3V

10%

402

CERM

1uF

2

1

C4769

6.3V

10%

402

CERM

1uF

2

1

C4768

6.3V

10%

402

CERM

1uF

2

1

C4767

6.3V

10%

402

CERM

1uF

2

1

C4766

6.3V

10%

402

CERM

1uF

2

1

C4765

6.3V

10%

402

CERM

1uF

2

1

C4764

402

6.3V

10% CERM

1uF

2

1

C4763

6.3V

10%

402

CERM

1uF

2

1

C4762

6.3V

10%

402

CERM

1uF

2

1

C4761

6.3V

10%

402

CERM

1uF

2

1

C4760

6.3V

10%

402

CERM

1uF

2

1

C4779

6.3V

10%

402

CERM

1uF

2

1

C4778

6.3V

10%

402

CERM

1uF

2

1

C4777

6.3V

10%

402

CERM

1uF

2

1

C4776

6.3V

10%

402

CERM

1uF

2

1

C4775

6.3V

10%

402

CERM

1uF

2

1

C4774

6.3V

10%

402

CERM

1uF

2

1

C4773

6.3V

10%

402

CERM

1uF

2

1

C4772

6.3V

10%

402

CERM

1uF

2

1

C4771

6.3V

10%

402

CERM

1uF

2

1

C4770

MF-LF

1/16W

1%

402

1K

2

1

R4700

0.1UF

CERM 402

20% 10V

2

1

C4705

1K

1%

1/16W

402

MF-LF

2

1

R4701

0.1UF

CERM 402

20% 10V

2

1

C4706

6.3V

10%

402

CERM

1uF

2

1

C4784

6.3V

10%

402

CERM

1uF

2

1

C4789

6.3V

10%

402

CERM

1uF

2

1

C4788

6.3V

10%

402

CERM

1uF

2

1

C4783

6.3V

10%

402

CERM

1uF

2

1

C4782

6.3V

10%

402

CERM

1uF

2

1

C4787

6.3V

10%

402

CERM

1uF

2

1

C4781

6.3V

10%

402

CERM

1uF

2

1

C4780

6.3V

10%

402

CERM

1uF

2

1

C4786

6.3V

10%

402

CERM

1uF

2

1

C4785

BGA

I2

OMIT

AD24

AC34

AC31

AC28

AC27

Y34

Y31

Y28

Y25

W24

V29

V26

V25

AC24

U34

U31

U29

U27

U24

T25

R28

R26

R24

P34

AB26

P31

P28

N26

M25

L34

L31

L28

K28

H34

H31

AA28

E34

C34

AP34

AM34

AJ34

AJ31

AF34

AF31

AF28

AD28

AA26

AA24

U2100

6.3V

10%

402

CERM

1uF

2

1

C4794

6.3V

10%

402

CERM

1uF

2

1

C4797

6.3V

10%

402

CERM

1uF

2

1

C4793

6.3V

10%

402

CERM

1uF

2

1

C4796

6.3V

10%

402

CERM

1uF

2

1

C4792

6.3V

10%

402

CERM

1uF

2

1

C4795

6.3V

10%

402

CERM

1uF

2

1

C4791

6.3V

10%

402

CERM

1uF

2

1

C4790

BGA

I2

OMIT

AC22

AB30

J31

N34

T21

V21

Y21

AG28

N35

W35

W34

W29

W28

V36

V35

W31

W30

E31

G35

J32

M29

AB33

AD32

AG32

AH30

C36

F32

K35

N28

AB35

AE32

AH33

AJ36

D35

D34

D33

C33

B33

F30

A34

A32

F33

E36

G32

F34

G33

F35

F36

G34

K34

K33

J35

J34

J33

J36

H36

K32

M30

M31

L36

M32

M33

M34

M35

M36

AB34

AB36

AA32

AA33

AA34

AA35

AA36

Y36

AD36

AD35

AD34

AE36

AD33

AE35

AE34

AE33

AH34

AH35

AH36

AG33

AG34

AG35

AG36

AF36

AK36

AK35

AK33

AK34

AH31

AL33

AK32

AK31

AL32

AL35

AL31

AM36

AL34

AP36

AL36

AN35

N33

V34

R32

N36

N32

V33

V32

P36

U36

T35

T36

T34

T33

R36

T32

R35

R34

R33

U2100

0 0

1

2

3

4

5

7

6

1K

1% MF-LF

402

1/16W

2

1

R4710

8

9

11

10

12

13

0

1

2

0

2

1

3

0

2

1

3

0

2

1

3

4

6

5

7

0

1

2

3

4

5

6

7

39 38

39 38 39 38

1

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

6.3V

10%

402

CERM

1uF

2

1

C4750

SYNC_DATE=N/A

SYNC_MASTER=N/A

I2 Memory Interface

47

115

C

051-6929

RAM_DATA_R<63..0> RAM_ADDR_R<13..0>

RAM_BA_R<2..0>

RAM_CKE_R<3..0>

RAM_CS_L_R<3..0>

RAM_DQS_P_R<7..0>

RAM_DQM_R<7..0>

RAMRAM

RAM_ODT1

RAM_ODT_R<1>

RAM RAM

RAM_ODT0

RAM_ODT_R<0>

RAMRAM

RAM_DATA_7

RAM_DATA_R<63..56>

RAM_DATA_R<55..48>

RAMRAM

RAM_DATA_6

RAM_DATA_R<47..40>

RAMRAM

RAM_DATA_5

RAM_DATA_R<39..32>

RAMRAM

RAM_DATA_4

RAM_DATA_R<31..24>

RAMRAM

RAM_DATA_3

RAM_DATA_R<23..16>

RAM_DATA_2

RAMRAM

RAM_DATA_1

RAM_DATA_R<15..8>

RAM

RAM_DATA_R<7..0>

RAM_DATA_0

RAM

RAM_DQM_R<7>

RAMRAM

RAM_DQM7

RAMRAM

RAM_DQM6

RAM_DQM_R<6>

RAM_DQM_R<5>

RAM_DQM5

RAM RAM

RAM_DQM_R<4>

RAMRAM

RAM_DQM4

RAMRAM

RAM_DQM3

RAM_DQM_R<3>

RAMRAM

RAM_DQM2

RAM_DQM_R<2>

RAMRAM

RAM_DQM1

RAM_DQM_R<1>

RAMRAM

RAM_DQM0

RAM_DQM_R<0>

RAMRAM

RAM_DQS6

RAM_DQS_P_R<6>

RAM_DQS7

RAMRAM

RAM_DQS_P_R<7>

RAM_DQS_P_R<5>

RAMRAM

RAM_DQS5

RAMRAM

RAM_DQS4

RAM_DQS_P_R<4>

RAMRAM

RAM_DQS3

RAM_DQS_P_R<3>

RAMRAM

RAM_DQS2

RAM_DQS_P_R<2>

RAMRAM

RAM_DQS1

RAM_DQS_P_R<1>

RAMRAM

RAM_DQS0

RAM_DQS_P_R<0>

Page Notes

RAM_CAS_L_R

RAM_ADDR_CTL

RAM RAM

RAM_CKE_R<1..0>

RAM_CKE_0

RAM RAM

RAM

RAM_ADDR_CTL

RAM_WE_L_R

RAM

=PP1V8_RAM_I2_VREF

RAM RAM

RAM_BA_R<2..0>

RAM_ADDR_CTL

RAM_RAS_L_R

RAM_ADDR_CTL

RAMRAM

RAM_CS_L_R<1..0>

RAM_CS_0

RAM RAM

RAM_DIFFRAM_DIFF

RAM_CLK_0

RAM_CLK_0_R

RAM_CLKDDR_0_N_R

RAM_DIFFRAM_DIFF

RAM_CLKDDR_1_N_R

RAM_CLK_1

RAM_CLK_1_R

RAM_DIFFRAM_DIFF

RAM_CLKDDR_0_P_R

RAM_CLK_0

RAM_CLK_0_R

RAM_DIFFRAM_DIFF

RAM_CLKDDR_1_P_R

RAM_CLK_1

RAM_CLK_1_R

RAM_DIFFRAM_DIFF

RAM_CLKDDR_2_P_R

RAM_CLK_2

RAM_CLK_2_R

RAM_DIFFRAM_DIFF

RAM_CLK_2

RAM_CLKDDR_2_N_R

RAM_CLK_2_R

RAM_DIFFRAM_DIFF

RAM_CLK_3_R

RAM_CLKDDR_3_P_R

RAM_CLK_3

RAM_DIFFRAM_DIFF

RAM_CLK_3_R

RAM_CLK_3

RAM_CLKDDR_3_N_R

RAM_CKE_R<3..2>

RAM_CKE_1

RAM RAM

RAM_CS_1

RAM_CS_L_R<3..2>

RAM RAM

RAM_ADDR_CTL

RAM_ADDR_R<13..0>

RAM RAM

=PP1V8_PWRON_I2_RAM

RAM_ODT_R<1>

RAM_CLKDDR_0_P_R RAM_CLKDDR_0_N_R

RAM_CLKDDR_1_P_R RAM_CLKDDR_1_N_R

RAM_CLKDDR_2_P_R RAM_CLKDDR_2_N_R

RAM_CAS_L_R

RAM_RAS_L_R

RAM_ODT_R<0>

RAM_CLKDDR_3_N_R

RAM_CLKDDR_3_P_R

RAM_WE_L_R

I2_MEM_VREF

I2_SD_REF

39

38

10

38

10

OUT

IN

OUT OUT

IN IN

IN

IN IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

SERIES RESISTORS FOR CS / CKE

Do not swap with other RPAKs

PINS ARE SWAPPABLE FOR RPAKS RP4800-RP4804

SERIES RESISTORS FOR CONTROL SIGNALS

SERIES RESISTORS FOR CLOCKS

Main Memory Series Termination

DIFFERENTIAL_PAIR

PHYSICAL

NET_TYPE

SPACING

ECSETs provided by

memory controller.

ELECTRICAL_CONSTRAINT_SET

40 39

41 39

22

402

MF-LF

1/16W

5%

21

R4851

22

402

MF-LF

1/16W

5%

21

R4850

1/16W MF-LF

402

22

5%

21

R4855

5%

MF-LF

402

22

1/16W

21

R4856

22

1/16W

5%

402

MF-LF

21

R4861

22

402

MF-LF

1/16W

5%

21

R4860

38

5% 1/16W MF-LF

402

22

21

R4866

5% 1/16W MF-LF

402

22

21

R4865

38

I193

I194

I195

I196

I197

I198

I199

I200

I201

I202

I203

I204

I205

I206

I207

I208

I209

I210

0

5% 1/16W MF-LF

402

21

R4810

402

MF-LF

1/16W

5%

0

21

R4811

I259

40 39

41 39

40 39

41 39

40 39

41 39

40 39

41 39

SM-LF

5%

1/16W

22

3

4

2

1

RP4870

38

SM-LF

1/16W

5%

22

3

4

2

1

RP4871

SM-LF

22

5%

1/16W

3

4

2

1

RP4875

SM-LF

22

5%

1/16W

3

4

2

1

RP4876

38

SM-LF

1/16W

10K 5%

5

6

7

8

4

3

2

1

RP4872

SM-LF

1/16W

10K 5%

5

6

7

8

4

3

2

1

RP4873

SM-LF

10K 5% 1/16W

5

6

7

8

4

3

2

1

RP4877

5%

10K 1/16W

SM-LF

5

6

7

8

4

3

2

1

RP4878

SM-LF

1/16W

5%

22

72

RP4803

SM-LF

22

1/16W

5%

63

RP4800

SM-LF

22

5%

1/16W

81

RP4803

1/16W

5%

22

SM-LF

54

RP4801

SM-LF

22

5%

1/16W

63

RP4803

SM-LF

1/16W

5%

22

54

RP4803

SM-LF

1/16W

5%

22

54

RP4802

1/16W

5%

22

SM-LF

72

RP4802

SM-LF

22

5%

1/16W

63

RP4802

SM-LF

1/16W

22

5%

81

RP4802

SM-LF

1/16W

5%

22

63

RP4801

1/16W

5%

22

SM-LF

54

RP4804

SM-LF

1/16W

5%

22

72

RP4800

22

5%

1/16W SM-LF

72

RP4801

SM-LF

1/16W

5%

22

54

RP4800

1/16W

22

5%

SM-LF

81

RP4800

22

5%

1/16W SM-LF

81

RP4801

SM-LF

1/16W

5%

22

81

RP4804

SM-LF

22

5%

1/16W

72

RP4804

1/16W

5%

22

SM-LF

63

RP4804

Memory Series Termination

SYNC_DATE=N/A

SYNC_MASTER=N/A

051-6929

C

115

48

RAM_CAS_L

RAMRAM

RAM_WE_L

RAMRAM

RAM_ODT<1..0>

RAMRAM

RAM_RAS_L

RAMRAM

RAM_BA<2..0>

RAMRAM

RAM_ADDR<13..0>

RAM_CS_L<3..0>

RAM RAM

RAM_CKE<3..0>

RAMRAM

RAM_CLK_2

RAM_CLKDDR_2_P

RAM_DIFF RAM_DIFF

RAM_CLK_3

RAM_CLKDDR_3_P

RAM_DIFF RAM_DIFF

RAM_CLK_2

RAM_CLKDDR_2_N

RAM_DIFF RAM_DIFF

RAM_CLK_4

RAM_CLKDDR_3_N

RAM_DIFF RAM_DIFF

RAM_CLK_1

RAM_CLKDDR_1_P

RAM_DIFF RAM_DIFF

RAM_CLK_1

RAM_CLKDDR_1_N

RAM_DIFF RAM_DIFF

RAM_CLK_0

RAM_CLKDDR_0_N

RAM_DIFF RAM_DIFF

RAM_CLK_0

RAM_CLKDDR_0_P

RAM_DIFF RAM_DIFF

RAM RAM

RAM_DQS<7..0> RAM_DQM<7..0>

RAMRAM

RAM_DATA<63..0>

RAM RAM

RAM_CLKDDR_0_N

RAM_CLKDDR_1_N

RAM_CLKDDR_2_N

RAM_CLKDDR_3_N

RAM_CLKDDR_0_P

RAM_CLKDDR_1_P

RAM_CLKDDR_0_P_R

RAM_CLKDDR_0_N_R

RAM_CLKDDR_1_P_R

RAM_CLKDDR_1_N_R

RAM_CLKDDR_2_P

RAM_CLKDDR_3_P

RAM_CLKDDR_2_P_R

RAM_CLKDDR_2_N_R

RAM_CLKDDR_3_P_R

RAM_CLKDDR_3_N_R

RAM_ODT<0>

RAM_ODT_R<0>

RAM_ODT<1>

RAM_ODT_R<1>

RAM_CS_L<0> RAM_CS_L<2>

RAM_DATA_A<63..0>

RAM_CKE<1> RAM_CKE<3>

RAM_CKE<2>

RAM_CKE<0>

RAM_CS_L<3>

RAM_DATA<63..0>

MAKE_BASE=TRUE

RAM_DQS_B_P<7..0>

RAM_DQS_A_P<7..0>

RAM_DQM_B<7..0>

RAM_DQM_A<7..0>

RAM_DATA_B<63..0>

RAM_DQS<7..0>

MAKE_BASE=TRUE

RAM_DQM<7..0>

RAM_CS_L_R<0> RAM_CS_L_R<2>

RAM_DATA_R<63..0>

RAM_CKE_R<1> RAM_CKE_R<3>

RAM_CKE_R<2>

RAM_CKE_R<0>

RAM_CS_L_R<3>

RAM_CS_L_R<1>

RAM_DQS_P_R<7..0>

RAM_DQM_R<7..0>

RAM_CS_L<1>

RAM_DQS_B_N<1> RAM_DQS_A_N<1> RAM_DQS_A_N<0> RAM_DQS_B_N<0>

RAM_DQS_B_N<7> RAM_DQS_A_N<7> RAM_DQS_B_N<6> RAM_DQS_A_N<6>

RAM_DQS_A_N<3> RAM_DQS_B_N<3> RAM_DQS_A_N<2> RAM_DQS_B_N<2>

RAM_DQS_B_N<5> RAM_DQS_A_N<5> RAM_DQS_B_N<4> RAM_DQS_A_N<4>

RAM_ADDR<1>

RAM_ADDR_R<1>

RAM_ADDR<2>

RAM_ADDR_R<2>

RAM_ADDR<0>

RAM_ADDR_R<0>

RAM_ADDR<3>

RAM_ADDR_R<3>

RAM_ADDR<5>

RAM_ADDR_R<5>

RAM_ADDR<7>

RAM_ADDR_R<7>

RAM_ADDR<9>

RAM_ADDR_R<9>

RAM_ADDR<10>

RAM_ADDR_R<10>

RAM_ADDR<6>

RAM_ADDR_R<6>

RAM_ADDR<8>

RAM_ADDR_R<8>

RAM_ADDR<4>

RAM_ADDR_R<4>

RAM_ADDR<11>

RAM_ADDR_R<11>

RAM_ADDR<13>

RAM_ADDR_R<13>

RAM_BA<1>

RAM_BA_R<1>

RAM_BA<2>

RAM_BA_R<2>

RAM_BA<0>

RAM_BA_R<0>

RAM_ADDR<12>

RAM_ADDR_R<12>

RAM_RAS_L

RAM_RAS_L_R

RAM_WE_L

RAM_WE_L_R

RAM_CAS_L

RAM_CAS_L_R

41

40

41

40

41

39

40

39

39 38

40

41

40

41

40

41

38

41

40

41

40

41

40

41

40

41

40

41

40

39 38

VSS25

VSS28

VSS26 DQS3*

VSS0

(2 OF 2)

VSS1 DQ0

VSS4 DQS0*

DQ1

VSS9

KEY

DQ57

DQ51

DQS6

DQ43

DQ42

DQ40

DQ34

VREF

DQS0 VSS6 DQ2 DQ3 VSS8 DQ8 DQ9 VSS10 DQS1* DQS1 VSS12 DQ10 DQ11 VSS14

VSS16 DQ16 DQ17 VSS18 DQS2* DQS2 VSS21 DQ18 DQ19 VSS23 DQ24 DQ25

DM3 NC1 VSS27 DQ26 DQ27 VSS29 CKE0 VDD0 NC2 BA2 VDD2 A12 A9 A8 VDD4 A5 A3 A1 VDD6 A10/AP BA0 WE* VDD8 CAS* NC/S1* VDD10

VSS31 DQ32 DQ33 VSS33 DQS4* DQS4 VSS36

DQ35 VSS38

DQ41 VSS40 DM5 VSS41

VSS43 DQ48 DQ49 VSS45 NC_TEST VSS47 DQS6*

VSS49 DQ50

VSS51 DQ56

VSS53 DM7 VSS55 DQ58 DQ59 VSS57 SDA SCL VDDSPD

DM6

DQ55

DQ61

DQ46 DQ47

DQ6

DQ12

DM1

DM0

DQ7

DQ13

VSS11

CK0

CK0*

VSS13

DQ14 DQ15

VSS15

VSS17

DQ20 DQ21

VSS19

NC0 DM2

VSS22

DQ22 DQ23

VSS24

DQ28 DQ29

DQS3

DQ30 DQ31

VSS30

NC/CKE1

VDD1 NC/A15 NC/A14

VDD3

A11

A7 A6

VDD5

A4 A2 A0

VDD7

BA1

S0* VDD9 ODT0

NC/A13

VDD11

NC3

VSS32

DQ36 DQ37

VSS34

DM4

VSS35

DQ38 DQ39

VSS37

DQ44 DQ45

VSS39 DQS5*

DQS5

VSS42

VSS44

DQ52 DQ53

VSS46

CK1 CK1*

VSS48

VSS50

DQ54

VSS52

DQ60

VSS54 DQS7*

DQS7

VSS56

DQ62 DQ63

VSS58

SA0

SA1

DQ5 VSS2

DQ4

RAS*

NC/ODT1

VSS5

VSS7

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

FACTORY SLOT

LOWER SLOT

SLOT "A"

ADDR=0XA0(WR)/0XA1(RD)

NC

NC NC

NC

SLOT "A"

DDR2 BYPASS

ONE 0.1UF PER SLOT

DDR2 VREF

ADD ONE 0.1UF PER SLOT

NC

(ODT<1>)

NC

Distribute C502x caps along connector

F-RT-SM

DDR2-SODIMM-DUAL

CRITICAL

109A

24A

21A

18A

15A

12A

196A

193A

190A

187A

184A183A

178A177A

172A

9A

171A

168A

165A

162A161A

156A155A

150A149A

145A

144A

139A

138A

133A

132A

128A127A

122A121A

78A

8A

77A

72A71A

66A65A

60A59A

54A53A

3A

48A47A

42A41A

40A39A

34A33A

28A27A

2A1A

199A

112A111A

104A103A

96A95A

88A87A

82A

118A117A

81A

195A 197A

200A

198A

110A

108A

114A

163A

120A

83A

69A

50A

115A

119A

80A

84A 86A

116A

404

403

186A 188A

167A 169A

146A 148A

129A 131A

68A 70A

49A 51A

29A 31A

11A 13A

25A

23A

16A

14A

194A

192A

182A

180A

6A

191A

189A

181A

179A

176A

174A

160A

158A

175A

173A

4A

159A

157A

154A

152A

142A

140A

153A

151A

143A

141A

19A

136A

134A

126A

124A

137A

135A

125A

123A

76A

74A

17A

64A

62A

75A

73A

63A

61A

58A

56A

46A

44A

7A

57A

55A

45A

43A

38A

36A

22A

20A

37A

35A

5A

185A

170A

147A

130A

67A

52A

26A

10A

79A

166A

164A

32A

30A

113A

85A

106A

107A

91A 93A

92A 94A

97A 98A 99A

100A

101A

89A 90A

105A

102A

J5000

1K

1% 1/16W MF-LF 402

2

1

R5001

402

MF-LF

1/16W

1%

1K

2

1

R5002

0.1uF

20% 10V CERM 402

2

1

C5019

0.1uF

20% 10V CERM 402

2

1

C5018

0.1uF

20% 10V CERM 402

2

1

C5017

20%

0.1uF

10V 402

CERM

2

1

C5016

0.1uF

10V

20% CERM

402

2

1

C5015

402

CERM

10V

20%

0.1uF

2

1

C5023

402

CERM

10V

20%

0.1uF

2

1

C5022

CERM 402

10V

0.1uF

20%

2

1

C5021

402

CERM

20% 10V

0.1uF

2

1

C5020

10UF

20%

6.3V X5R 603

2

1

C5008

603

X5R

6.3V

20%

10UF

2

1

C5009

0.1uF

20% 10V CERM 402

2

1

C5001

402

CERM

20% 10V

0.1uF

2

1

C5010

CERM 402

10V

0.1uF

20%

2

1

C5011

402

CERM

10V

20%

0.1uF

2

1

C5013

402

CERM

10V

20%

0.1uF

2

1

C5012

0.1uF

20% 10V CERM 402

2

1

C5014

DDR2 SO-DIMM Slot A

50

115

C

051-6929

SYNC_MASTER=N/A

SYNC_DATE=N/A

=PP1V8_PWRON_DDR2

RAM_DATA_A<26>

RAM_DATA_A<24>

RAM_DQS_A_P<3>

RAM_DATA_A<54>

RAM_DATA_A<44>

RAM_DATA_A<60>

RAM_DATA_A<57>

RAM_DQS_A_P<7>

RAM_DQS_A_N<7>

RAM_DATA_A<62>

RAM_DATA_A<58>

RAM_DATA_A<50>

RAM_DQM_A<6>

RAM_CLKDDR_1_N

RAM_CLKDDR_1_P

RAM_DATA_A<48>

RAM_DATA_A<53>

RAM_DATA_A<45>

RAM_DQS_A_P<5>

RAM_DQS_A_N<5>

RAM_DATA_A<46>

RAM_DATA_A<40>

RAM_DATA_A<32>

RAM_DATA_A<33>

RAM_DQM_A<4>

RAM_DATA_A<38>

RAM_DATA_A<39>

RAM_ADDR<13>

=PP1V8_PWRON_DDR2

RAM_CS_L<0>

RAM_ADDR<2>

RAM_ADDR<4>

RAM_ADDR<6>

RAM_ADDR<7>

RAM_DATA_A<23>

RAM_DATA_A<11>

RAM_CLKDDR_0_N

RAM_CLKDDR_0_P

RAM_DQM_A<1>

RAM_DATA_A<12>

RAM_DATA_A<15>

RAM_DATA_A<4>

RAM_DATA_A<5>

RAM_DQM_A<0>

RAM_DATA_A<3>

RAM_DATA_A<0>

=PP3V3_PWRON_VDDSPD

=I2C_SODIMM_SCL

=I2C_SODIMM_SDA

RAM_DATA_A<56>

RAM_DATA_A<59>

RAM_DQM_A<7>

RAM_DATA_A<61>

RAM_DATA_A<63>

RAM_DATA_A<55>

RAM_DATA_A<52>

RAM_DQS_A_P<6>

RAM_DQS_A_N<6>

RAM_DATA_A<49>

RAM_DATA_A<51>

RAM_DATA_A<41>

RAM_DATA_A<42>

RAM_DQM_A<5>

RAM_DATA_A<43>

RAM_DATA_A<47>

RAM_DATA_A<37>

RAM_DATA_A<34>

RAM_DQS_A_P<4>

RAM_DQS_A_N<4>

RAM_DATA_A<35>

RAM_DATA_A<36>

RAM_DATA_A<8>

RAM_WE_L

RAM_BA<0>

RAM_ADDR<10>

=PP1V8_PWRON_DDR2

RAM_ADDR<1>

RAM_ADDR<3>

RAM_ADDR<5>

RAM_ADDR<8>

RAM_ADDR<9>

RAM_ADDR<12>

RAM_BA<2>

RAM_CKE<0>

RAM_DATA_A<29>

RAM_DATA_A<27>

RAM_DQM_A<3>

RAM_DATA_A<25>

RAM_DATA_A<19>

RAM_DATA_A<22>

RAM_DQS_A_P<2>

RAM_DQS_A_N<2>

RAM_DATA_A<16>

RAM_DATA_A<17>

RAM_DATA_A<10>

RAM_DQS_A_P<1>

RAM_DQS_A_N<1>

RAM_DATA_A<13>

RAM_DATA_A<14>

RAM_DATA_A<7>

RAM_DATA_A<6>

RAM_DQS_A_P<0>

RAM_DQS_A_N<0>

RAM_DATA_A<2>

RAM_DATA_A<1>

=RAM_VREF_A

RAM_CKE<1>

RAM_BA<1>

RAM_DATA_A<9>

RAM_DATA_A<20>

RAM_DQM_A<2>

RAM_DATA_A<21>

RAM_DATA_A<31> RAM_DATA_A<30>

RAM_DATA_A<28>

RAM_ADDR<11>

RAM_ADDR<0>

RAM_RAS_L

RAM_ODT<0>

RAM_CS_L<1>

RAM_CAS_L

RAM_DATA_A<18>

RAM_DQS_A_N<3>

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

MAKE_BASE=TRUE

RAM_VREF

=RAM_VREF_A

=PP1V8_PWRON_DDR2

=RAM_VREF_A

=RAM_VREF_B

41

41 41

41

40

41

40

41

40

41

40

10

39

10

39

10

8

39

10

39

40

39

40

10

40

41

DQ4

VSS2

DQ5

SA1

SA0

VSS58

DQ63

DQ62

VSS56

DQS7

DQS7*

VSS54

DQ60

VSS52

DQ54

VSS50

VSS48

CK1*

CK1

VSS46

DQ53

DQ52

VSS44

VSS42

DQS5

DQS5*

VSS39

DQ45

DQ44

VSS37

DQ39

DQ38

VSS35

DM4

VSS34

DQ37

DQ36

VSS32

NC3

VDD11

NC/A13

ODT0

VDD9

S0*

RAS*

BA1

VDD7

A0

A2

A4

VDD5

A6

A7

A11

VDD3

NC/A14

NC/A15

VDD1

NC/CKE1

VSS30

DQ31

DQ30

VSS28

DQS3

DQS3*

VSS26

DQ29

DQ28

VSS24

DQ23

DQ22

VSS22

DM2

NC0

VSS19

DQ21

DQ20

VSS17

VSS15

DQ15

DQ14

VSS13

CK0*

CK0

VSS11

DQ13

VSS7

DQ7

VSS5

DM0

VSS0

DM1

DQ12

DQ6

DQ47

DQ46

DQ61

DQ55

DM6

VDDSPD

SCL

SDA

VSS57

DQ59

DQ58

VSS55

DM7

VSS53

DQ56

VSS51

DQ50

VSS49

DQS6*

VSS47

NC_TEST

VSS45

DQ49

DQ48

VSS43

VSS41

DM5

VSS40

DQ41

VSS38

DQ35

VSS36

DQS4

DQS4*

VSS33

DQ33

DQ32

VSS31

NC/ODT1

VDD10

NC/S1*

CAS*

VDD8

WE*

BA0

A10/AP

VDD6

A1

A3

A5

VDD4

A8

A9

A12

VDD2

BA2

NC2

VDD0

CKE0

VSS29

DQ27

DQ26

VSS27

NC1

DM3

VSS25

DQ25

DQ24

VSS23

DQ19

DQ18

VSS21

DQS2

DQS2*

VSS18

DQ17

DQ16

VSS16

VSS14

DQ11

DQ10

DQS1

DQS1*

VSS10

DQ9

DQ8

VSS8

DQ3

DQ2

VSS6

DQS0

DQS0*

VSS4

VSS1

VREF

DQ0 DQ1

DQ34

DQ40

DQ42 DQ43

DQS6

DQ51

DQ57

KEY

VSS9

(1 OF 2)

VSS12

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NC

DDR2 VREF

ONE 0.1UF PER SLOT

DDR2 BYPASS

NC

SLOT "B" UPPER SLOT CUSTOMER SLOT

ADDR=0XA2(WR)/0XA3(RD)

SLOT "B"

NC

(ODT<1>)

Distribute C522x caps along connector

DDR2-SODIMM-DUAL

CRITICAL

F-RT-SM

109B

24B

21B

18B

15B

12B

196B

193B

190B

187B

184B183B

178B177B

172B

9B

171B

168B

165B

162B161B

156B155B

150B149B

145B

144B

139B

138B

133B

132B

128B127B

122B121B

78B

8B

77B

72B71B

66B65B

60B59B

54B53B

3B

48B47B

42B41B

40B39B

34B33B

28B27B

2B1B

199B

112B111B

104B103B

96B95B

88B87B

82B

118B117B

81B

195B 197B

200B

198B

110B

108B

114B

163B

120B

83B

69B

50B

115B

119B

80B

84B 86B

116B

402

401

186B 188B

167B 169B

146B 148B

129B 131B

68B 70B

49B 51B

29B 31B

11B 13B

25B

23B

16B

14B

194B

192B

182B

180B

6B

191B

189B

181B

179B

176B

174B

160B

158B

175B

173B

4B

159B

157B

154B

152B

142B

140B

153B

151B

143B

141B

19B

136B

134B

126B

124B

137B

135B

125B

123B

76B

74B

17B

64B

62B

75B

73B

63B

61B

58B

56B

46B

44B

7B

57B

55B

45B

43B

38B

36B

22B

20B

37B

35B

5B

185B

170B

147B

130B

67B

52B

26B

10B

79B

166B

164B

32B

30B

113B

85B

106B

107B

91B 93B

92B 94B

97B 98B 99B

100B

101B

89B 90B

105B

102B

J5000

402

CERM

10V

20%

0.1uF

2

1

C5219

0.1uF

20% 10V CERM 402

2

1

C5218

0.1uF

20% 10V CERM 402

2

1

C5217

20%

0.1uF

10V 402

CERM

2

1

C5216

0.1uF

10V

20% CERM

402

2

1

C5215

0.1uF

20% 10V CERM 402

2

1

C5223

0.1uF

20% 10V CERM 402

2

1

C5222

20%

0.1uF

10V 402

CERM

2

1

C5221

0.1uF

10V

20% CERM

402

2

1

C5220

603

X5R

6.3V

20%

10UF

2

1

C5208

10UF

20%

6.3V X5R 603

2

1

C5209

402

CERM

10V

20%

0.1uF

2

1

C5201

402

CERM

20% 10V

0.1uF

2

1

C5210

CERM 402

10V

0.1uF

20%

2

1

C5211

402

CERM

10V

20%

0.1uF

2

1

C5213

402

CERM

10V

20%

0.1uF

2

1

C5212

0.1uF

402

CERM

10V

20%

2

1

C5214

DDR2 SO-DIMM Slot B

SYNC_DATE=N/A

SYNC_MASTER=N/A

051-6929

C

115

52

=PP1V8_PWRON_DDR2

=RAM_VREF_B

RAM_DATA_B<1> RAM_DATA_B<2>

RAM_DQS_B_N<0> RAM_DQS_B_P<0>

RAM_DATA_B<6> RAM_DATA_B<7>

RAM_DATA_B<14> RAM_DATA_B<13>

RAM_DQS_B_N<1> RAM_DQS_B_P<1>

RAM_DATA_B<10> RAM_DATA_B<8>

RAM_DATA_B<17> RAM_DATA_B<16>

RAM_DQS_B_N<2> RAM_DQS_B_P<2>

RAM_DATA_B<22> RAM_DATA_B<19>

RAM_DATA_B<26> RAM_DATA_B<25>

RAM_DQM_B<3>

RAM_DATA_B<27> RAM_DATA_B<29>

RAM_CKE<2>

RAM_BA<2>

RAM_ADDR<12> RAM_ADDR<9> RAM_ADDR<8>

RAM_ADDR<5> RAM_ADDR<3> RAM_ADDR<1>

RAM_ADDR<10> RAM_BA<0> RAM_WE_L

RAM_CAS_L RAM_CS_L<3>

=PP1V8_PWRON_DDR2

RAM_DATA_B<36> RAM_DATA_B<35>

RAM_DQS_B_N<4> RAM_DQS_B_P<4>

RAM_DATA_B<34> RAM_DATA_B<37>

RAM_DATA_B<47> RAM_DATA_B<43>

RAM_DQM_B<5>

RAM_DATA_B<41>

RAM_DATA_B<51> RAM_DATA_B<49>

RAM_DQS_B_N<6> RAM_DQS_B_P<6>

RAM_DATA_B<52> RAM_DATA_B<55>

RAM_DATA_B<63> RAM_DATA_B<61>

RAM_DQM_B<7>

RAM_DATA_B<59> RAM_DATA_B<56>

=I2C_SODIMM_SDA =I2C_SODIMM_SCL =PP3V3_PWRON_VDDSPD

RAM_DATA_B<42>

RAM_RAS_L RAM_CS_L<2>

RAM_ODT<1> RAM_ADDR<13>

RAM_DATA_B<38>

RAM_DQM_B<4>

RAM_DATA_B<33> RAM_DATA_B<32>

RAM_DATA_B<40> RAM_DATA_B<46>

RAM_DQS_B_N<5> RAM_DQS_B_P<5>

RAM_DATA_B<45> RAM_DATA_B<44>

RAM_DATA_B<53> RAM_DATA_B<48>

RAM_CLKDDR_3_P RAM_CLKDDR_3_N

RAM_DQM_B<6>

RAM_DATA_B<50> RAM_DATA_B<54>

RAM_DATA_B<58> RAM_DATA_B<62>

RAM_DQS_B_N<7> RAM_DQS_B_P<7>

RAM_DATA_B<57> RAM_DATA_B<60>

=PP3V3_PWRON_VDDSPD

RAM_DATA_B<39>

RAM_DATA_B<0> RAM_DATA_B<3>

RAM_DQM_B<0>

RAM_DATA_B<5> RAM_DATA_B<4>

RAM_DATA_B<15> RAM_DATA_B<12>

RAM_DQM_B<1>

RAM_CLKDDR_2_P RAM_CLKDDR_2_N

RAM_DATA_B<9> RAM_DATA_B<11>

RAM_DATA_B<18> RAM_DATA_B<20>

RAM_DQM_B<2>

RAM_DATA_B<23> RAM_DATA_B<21>

RAM_DATA_B<31> RAM_DATA_B<30>

RAM_DQS_B_N<3> RAM_DQS_B_P<3>

RAM_DATA_B<24> RAM_DATA_B<28>

RAM_CKE<3>

RAM_ADDR<11> RAM_ADDR<7> RAM_ADDR<6>

RAM_ADDR<4> RAM_ADDR<2> RAM_ADDR<0>

=PP1V8_PWRON_DDR2

RAM_BA<1>

41

40

41

40

10

40

39

10

39

8

10

39

10

39

10

39

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(provided above)

ELECTRICAL_CONSTRAINT_SET

SPACING

PHYSICAL

DIFFERENTIAL_PAIR

NET_TYPE

DIFFERENTIAL_PAIR

PHYSICAL

SPACING

ELECTRICAL_CONSTRAINT_SET

I1059

I1060

I1061

I1062

I1068

I1069 I1071

I1072

I1073 I1074

I1075

I1076

I1078 I1079

I1080 I1081

I1082

I1083

I1084

I1085

I1086

I1087 I1088

I1089 I1090

I1091

I1092

I1093 I1094

I1095

I1096 I1097

I1098

I1099 I1100

I1101

I1102

I1103

I1104

I1105

I1106

I1107

I1108

I1109

I1110

I1111

I1112

I1113

I1114

I1115 I1116

I1117

I1118 I1119

I1120

I1121

I1122

I1123

I1124

I1125

I1126

I1127

I1128

I1129

I1130

I1131

I1132

I1133

I1134 I1135

M11 Frame Buffer Constraints

SYNC_DATE=N/A

SYNC_MASTER=N/A

C

051-6929

115

55

FB_B_DQ7

FB_B_DQ_R<63..56>

RAM RAM

FB_B_DQ6

FB_B_DQ_R<55..48>

RAM RAM

FB_B_DQ5

FB_B_DQ_R<47..40>

RAM RAM

FB_B_DQ4

FB_B_DQ_R<39..32>

RAM RAM

FB_B_DQ3

FB_B_DQ_R<31..24>

RAM RAM

FB_B_DQ2

FB_B_DQ_R<23..16>

RAM RAM

FB_B_DQ0

FB_B_DQ_R<7..0>

RAM RAM

FB_B_DQ1

FB_B_DQ_R<15..8>

RAM RAM

FB_B_DQM_R<7>

RAMRAM

FB_B_DQM7

FB_B_DQM_R<6>

RAMRAM

FB_B_DQM6

FB_B_DQM_R<5>

RAMRAM

FB_B_DQM5

FB_B_DQM_R<3>

RAM RAM

FB_B_DQM3

FB_B_DQM_R<4>

RAMRAM

FB_B_DQM4

FB_B_DQM_R<0>

RAM RAM

FB_B_DQM0

FB_B_DQM_R<1>

RAM RAM

FB_B_DQM1

FB_B_DQM_R<2>

RAM RAM

FB_B_DQM2

FB_B_DQS_R<7>

RAMRAM

FB_B_DQS7

FB_B_DQS_R<6>

RAMRAM

FB_B_DQS6

FB_B_DQS_R<5>

RAMRAM

FB_B_DQS5

FB_B_DQS_R<4>

RAMRAM

FB_B_DQS4

FB_B_DQS_R<3>

RAM RAM

FB_B_DQS3

FB_B_DQS_R<2>

RAM RAM

FB_B_DQS2

FB_B_DQS_R<1>

RAM RAM

FB_B_DQS1

FB_B_WE_L_R

RAMRAM

FB_B_ADDR_CTL

FB_B_DQS_R<0>

RAM RAM

FB_B_DQS0

FB_B_CAS_L_R

RAMRAM

FB_B_ADDR_CTL

FB_B_RAS_L_R

RAMRAM

FB_B_ADDR_CTL

FB_B_BA_R<2..0>

RAMRAM

FB_B_ADDR_CTL

FB_B_ADDR_R<12..0>

RAMRAM

FB_B_ADDR_CTL

FB_B_CS_L_R

RAM RAM

FB_B_ADDR_CTL

FB_B_CLKDDR_1_N_R

FB_B_CLK_1_R

RAM_DIFF RAM_DIFF

FB_B_CKE_R

RAM RAM

FB_B_ADDR_CTL

FB_B_CLKDDR_0_P_R

FB_B_CLK_0_R

FB_B_CLK_0

RAM_DIFF RAM_DIFF

FB_B_CLKDDR_0_N_R

FB_B_CLK_0_R

RAM_DIFF RAM_DIFF

FB_B_CLKDDR_1_P_R

FB_B_CLK_1_R

FB_B_CLK_1

RAM_DIFF RAM_DIFF

FB_A_DQ7

FB_A_DQ_R<63..56>

RAM RAM

FB_A_DQ6

FB_A_DQ_R<55..48>

RAM RAM

FB_A_DQ5

FB_A_DQ_R<47..40>

RAM RAM

FB_A_DQ4

FB_A_DQ_R<39..32>

RAM RAM

FB_A_DQ3

FB_A_DQ_R<31..24>

RAM RAM

FB_A_DQ2

FB_A_DQ_R<23..16>

RAM RAM

FB_A_DQ1

FB_A_DQ_R<15..8>

RAM RAM

FB_A_DQ0

FB_A_DQ_R<7..0>

RAM RAM

FB_A_DQM7

FB_A_DQM_R<7>

RAMRAM

FB_A_DQM6

FB_A_DQM_R<6>

RAMRAM

FB_A_DQM5

FB_A_DQM_R<5>

RAMRAM

FB_A_DQM4

FB_A_DQM_R<4>

RAMRAM

FB_A_DQM3

FB_A_DQM_R<3>

RAM RAM

FB_A_DQM2

FB_A_DQM_R<2>

RAM RAM

FB_A_DQM1

FB_A_DQM_R<1>

RAM RAM

FB_A_DQM0

FB_A_DQM_R<0>

RAM RAM

FB_A_DQS7

FB_A_DQS_R<7>

RAMRAM

FB_A_DQS6

FB_A_DQS_R<6>

RAMRAM

FB_A_DQS5

FB_A_DQS_R<5>

RAMRAM

FB_A_DQS3

FB_A_DQS_R<3>

RAM RAM

FB_A_DQS4

FB_A_DQS_R<4>

RAMRAM

FB_A_DQS2

FB_A_DQS_R<2>

RAM RAM

FB_A_DQS1

FB_A_DQS_R<1>

RAM RAM

FB_A_DQS0

FB_A_DQS_R<0>

RAM RAM

RAMRAM

FB_A_ADDR_CTL

FB_A_WE_L_R

RAMRAM

FB_A_ADDR_CTL

FB_A_CAS_L_R

RAMRAM

FB_A_ADDR_CTL

FB_A_RAS_L_R

RAMRAM

FB_A_BA_R<2..0>

FB_A_ADDR_CTL

RAMRAM

FB_A_ADDR_R<12..0>

FB_A_ADDR_CTL

FB_A_CS_L_R

RAM RAM

FB_A_ADDR_CTL

FB_A_CKE_R

RAM RAM

FB_A_ADDR_CTL

FB_A_CLK_1

FB_A_CLK_1_R

FB_A_CLKDDR_1_P_R

RAM_DIFF RAM_DIFF

FB_A_CLK_1_R

FB_A_CLKDDR_1_N_R

RAM_DIFF RAM_DIFF

FB_A_CLK_0_R

FB_A_CLKDDR_0_N_R

RAM_DIFF RAM_DIFF

FB_A_CLK_0

FB_A_CLK_0_R

FB_A_CLKDDR_0_P_R

RAM_DIFF RAM_DIFF

48

(9 of 14)

AGP INTERFACE

(3.3V SIGNALS)

(VDDAGP SIGNALS)

AGP_ST_2_H

AGP_ST_0_H AGP_ST_1_H

AGP_SB_STB_N

AGP_SB_STB_P

AGP_SBA_7_H

AGP_SBA_6_H

AGP_SBA_5_H

AGP_SBA_4_H

AGP_SBA_3_H

AGP_SBA_2_H

AGP_SBA_1_H

AGP_SBA_0_H

VDDAGP_24

VDDAGP_23

VDDAGP_22

VDDAGP_21

VDDAGP_20

VDDAGP_19

VDDAGP_18

VDDAGP_17

VDDAGP_16

VDDAGP_14 VDDAGP_15

VDDAGP_13

VDDAGP_12

VDDAGP_11

VDDAGP_10

VDDAGP_9

VDDAGP_8

VDDAGP_7

VDDAGP_6

VDDAGP_5

VDDAGP_4

VDDAGP_3

VDDAGP_2

VDDAGP_1

VDDAGP_0

AGP_FBCLK_OUT_H

AGP_PVTREF_H

AGP_FB_CLK_IN_H

AGP_VREF_0_H

AGP_AD_22_H

AGP_AD_20_H

AGP_AD_18_H

AGP_AD_07_H

AGP_AD_04_H

AGP_AD_STB1_P AGP_AD_STB1_N

AGP_AD_31_H AGP_CBE_3_L

AGP_AD_29_H AGP_AD_30_H

AGP_AD_28_H

AGP_AD_27_H

AGP_AD_26_H

AGP_AD_24_H AGP_AD_25_H

AGP_CBE_2_L

AGP_AD_23_H

AGP_AD_21_H

AGP_AD_19_H

AGP_AD_17_H

AGP_AD_16_H

AGP_AD_STB0_N

AGP_AD_STB0_P

AGP_AD_15_H AGP_CBE_1_L

AGP_AD_13_H AGP_AD_14_H

AGP_AD_12_H

AGP_AD_11_H

AGP_AD_10_H

AGP_AD_09_H

AGP_AD_08_H

AGP_PIPE_L AGP_WBF_L AGP_RBF_L

AGP_STOP_L AGP_DEVSEL_L

AGP_TRDY_L AGP_IRDY_L

AGP_FRAME_L

AGP_PAR_H

AGP_REQ_L

AGP_CBE_0_L

AGP_AD_06_H

AGP_AD_05_H

AGP_AD_03_H

AGP_AD_02_H

AGP_AD_01_H

AGP_AD_00_H

AGP_GNT_L

AGP_BUSY_L

AGP_CLK_H

AGP_STP_L

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

25 X 1uF (0402)

1 X 10uF (0603)

- AGP_TRDY_L

- AGP_DEVSEL_L

- AGP_RBF_L

- AGP_GNT_L

- AGP_FRAME_L

- AGP_REQ_L

- AGP_STOP_L

- AGP_IRDY_L

One resistor for each of:

AGP I/O DECOUPLING

ELECTRICAL_CONSTRAINT_SET

(NONE)

- =PP1V5_AGP

- =PP1V5_I2_AGP

- =PP3V3_AGP

NOTE: I2 implements an AGP 4x bridge.

BOM options provided by this page:

clock from I2 to AGP device.

- =I2_AGP_FBCLK_IN - AGP feedback clock

- =I2_AGP_VREF - VRef from graphics

AGP 8x signals are not provided by this page.

input. Length should match that of

card or on-board graphics controller

Signal aliases required by this page:

Power aliases required by this page:

Page Notes

AGP PULL-UPS/PULL DOWNS

DIFFERENTIAL_PAIR

PHYSICAL

NET_TYPE

SPACING

1.5V OUT

1.5V IN

(25 Balls on I2)

6.3V

10%

1uF

CERM 402

2

1

C5654

6.3V

10%

1uF

CERM 402

2

1

C5653

6.3V

10%

1uF

402

CERM

2

1

C5659

6.3V

10%

402

CERM

1uF

2

1

C5664

6.3V

10%

402

CERM

1uF

2

1

C5658

6.3V

10%

1uF

CERM 402

2

1

C5652

6.3V

10%

1uF

CERM 402

2

1

C5651

6.3V

10%

1uF

CERM 402

2

1

C5650

6.3V

20%

603

X5R

10UF

2

1

C5649

6.3V

10%

402

CERM

1uF

2

1

C5657

OMIT

BGA

I2

AH11

AG16

AG13

AF14

AE18

AE16

AE13

AP8

AP5

AP3

AP20

AP17

AD19

AP14

AP11

AL9

AL8

AL20

AL17

AL14

AL12

AL11

AH13

AD17

AD15

AT18

AD18

AM16

AT21

AT14

AP16

AN16

AR16

AT17

AT16

AK18

AM18

AN18

AP18

AR18

AL18

AH16

AJ16

AR19

AM19

AJ18

AN19

AT15

AR15

AL16

AK16

AM9

AM10

AP15

AH19

AP13

AR10

AP9

AT3

AP19

AK13

AJ13

AH9

AJ9

AN15

AM15

AT13

AR13

AT12

AR12

AN13

AL15

AT11

AP12

AM13

AK15

AT10

AN12

AP10

AM12

AT9

AT8

AR9

AN10

AT7

AR7

AP7

AN9

AT6

AR6

AL13

AN7

AT5

AR4

AP4

AP6

U2100

6.3V

10%

1uF

CERM 402

2

1

C5669

6.3V

10%

1uF

CERM 402

2

1

C5668

6.3V

10%

1uF

CERM 402

2

1

C5667

6.3V

10%

1uF

CERM 402

2

1

C5666

6.3V

10%

1uF

CERM 402

2

1

C5665

6.3V

10%

1uF

CERM 402

2

1

C5674

6.3V

10%

1uF

CERM 402

2

1

C5673

6.3V

10% CERM

402

1uF

2

1

C5672

6.3V

10% CERM

402

1uF

2

1

C5671

6.3V

10%

402

CERM

1uF

2

1

C5656

6.3V

10%

402

CERM

1uF

2

1

C5655

6.3V

10%

402

CERM

1uF

2

1

C5663

1%

60.4

1/16W MF-LF 402

2

1

R5600

6.3V

10%

402

CERM

1uF

2

1

C5662

6.3V

10%

402

CERM

1uF

2

1

C5661

6.3V

10%

402

CERM

1uF

2

1

C5660

6.3V

10%

1uF

CERM 402

2

1

C5670

22

402

5% 1/16W MF-LF

21

R5605

10K

5% 1/16W MF-LF

402

21

R5620

10K

MF-LF

402

5% 1/16W

21

R5613

10K

MF-LF

402

5%

1/16W

21

R5612

10K

MF-LF

402

5% 1/16W

21

R5615

MF-LF

402

10K

5%

1/16W

21

R5616

10K

MF-LF

402

5%

1/16W

21

R5614

10K

MF-LF

402

5%

1/16W

21

R5618

10K

MF-LF

402

5% 1/16W

21

R5617

10K

MF-LF

402

5% 1/16W

21

R5619

5% 1/16W

10K

402

MF-LF

21

R5610

10K

SM-LF

5%

1/16W

72

RP5610

10K

5% 1/16W SM-LF

63

RP5611

10K

SM-LF

5% 1/16W

81

RP5611

10K

SM-LF

5%

1/16W

81

RP5610

10K

SM-LF

5%

1/16W

72

RP5611

10K

SM-LF

5% 1/16W

63

RP5610

10K

SM-LF

5% 1/16W

54

RP5610

10K

SM-LF

5%

1/16W

54

RP5611

10K

5% 1/16W MF-LF

402

21

R5611

I2 AGP Interface

C

051-6929

56

115

SYNC_MASTER=N/A

SYNC_DATE=N/A

=PP1V5_AGP

=RP5610P2

=RP5611P2

=RP5611P4

=RP5610P1

AGP_PIPE_L

AGP_AD_STB1_P

=RP5610P4

=RP5610P3

=RP5611P3

=RP5611P1

AGP_WBF_L

AGP_SB_STB_P

AGP_AD_STB0_P

AGP_AD_STB_0

AGP_STB

AGP_AD_STB0

AGP_STB

AGP_AD_STB0_N

AGP_STOP_L

AGP AGP

AGP_CTL

AGP_AD<31..16>

AGPAGP

AGP_AD_1

AGP_AD_STB_1

AGP_AD_STB1

AGP_STB AGP_STB

AGP_AD_STB1_N

AGP AGP

AGP_PAR

AGP_SB_STB

AGP_STB

AGP_SB_STB

AGP_STB

AGP_SB_STB_N

AGP_SB_STB

AGP_STBAGP_STB

AGP_SB_STB_P

AGP_SB_STB

AGP_AD_STB_0

AGP_STB

AGP_AD_STB0

AGP_STB

AGP_AD_STB0_P

AGP_CBE_L<1..0>

AGP AGP

AGP_AD_0

I2_AGP_FBCLK_OUT_R

I2_AGP_FBCLK_OUT

STOP_AGP_L

AGP_CLK66M_GPU_R

AGP_BUSY_L

AGP_GNT_L

AGP_AD<0> AGP_AD<1> AGP_AD<2> AGP_AD<3>

AGP_AD<5> AGP_AD<6>

AGP_CBE_L<0>

AGP_REQ_L

AGP_PAR AGP_FRAME_L

AGP_IRDY_L

AGP_TRDY_L

AGP_DEVSEL_L

AGP_STOP_L

AGP_WBF_L

AGP_PIPE_L

AGP_AD<8> AGP_AD<9> AGP_AD<10> AGP_AD<11> AGP_AD<12>

AGP_AD<14>

AGP_AD<13>

AGP_CBE_L<1>

AGP_AD<15>

AGP_AD_STB0_P AGP_AD_STB0_N

AGP_AD<16> AGP_AD<17>

AGP_AD<19>

AGP_AD<21>

AGP_AD<23> AGP_CBE_L<2>

AGP_AD<25>

AGP_AD<24>

AGP_AD<26> AGP_AD<27> AGP_AD<28>

AGP_AD<30>

AGP_AD<29>

AGP_CBE_L<3>

AGP_AD<31>

AGP_AD_STB1_N

AGP_AD_STB1_P

AGP_AD<4>

AGP_AD<7>

AGP_AD<18>

AGP_AD<20>

AGP_AD<22>

=I2_AGP_VREF

=I2_AGP_FBCLK_IN

AGP_SBA<0> AGP_SBA<1>

AGP_SBA<3> AGP_SBA<4> AGP_SBA<5> AGP_SBA<6> AGP_SBA<7>

AGP_SB_STB_N

AGP_ST<1>

AGP_ST<0>

AGP_ST<2>

=PP1V5_I2_AGP

AGP_AD_STB_1

AGP_AD_STB1

AGP_STB AGP_STB

AGP_AD_STB1_P

AGP_AD_STB1_N

AGP_AD_STB0_N

AGP_SB_STB_N

AGP_BUSY_L

=PP3V3_AGP

AGP_INT_L

STOP_AGP_L

AGP AGP

AGP_AD_1

AGP_CBE_L<3..2>

AGP_CLK

CLOCKCLOCK

AGP_CLK66M_GPU_R

AGP_DEV_CTL

AGP_WBF_L

AGPAGP

AGP_DEV_CTL

AGP_PIPE_L

AGPAGP

AGP_REQ_L

AGPAGP

AGP_DEV_CTL

AGP_RBF_L

AGPAGP

AGP_IRDY_L

AGP AGP

AGP_CTL

AGP_DEVSEL_L

AGP AGP

AGP_CTL

AGP

AGP_ST<3..0>

AGP_ST

AGP

AGP_FRAME_L

AGP AGP

AGP_CTL

AGP_TRDY_L

AGP AGP

AGP_CTL

AGP_AD<15..0>

AGP_AD_0

AGPAGP

I2_FBCLKI2_FBCLK

I2_AGP_FBCLK_OUT

I2_FBCLKI2_FBCLK

I2_AGP_FBCLK

I2_AGP_FBCLK_OUT_R

AGP AGP

AGP_SBA<7..0>

AGP_SBA

AGP_RBF_L

AGP_SBA<2>

I2_AGP_PVTREF

=PP1V5_AGP

AGP_GNT_L

AGPAGP

AGP_SB_STB_P

47

44

44 44

44

43

44

43

44

43

44

43

44

43

44

43

44

43

44

43

44

43

44

43

44

43

44

43

44

43

44

10

6

43

6

43

6

43

21

43

11

43

6

43

6

43

6

43

11

21

43

10

43

10

22

43

11

43

6

43

6

43

21

43

6

43

10

6

43

AD_14

AD_2

DBI_LO

AD_21

AD_26

AD_24

AD_3 AD_4

AD_11

AD_0 AD_1

AD_10

AD_12 AD_13

AD_15 AD_16 AD_17 AD_18 AD_19 AD_20

AD_22 AD_23

AD_25

AD_27 AD_28 AD_29 AD_30

AD_5 AD_6 AD_7 AD_8 AD_9

AD_STBF_0

AD_STBF_1

AD_STBS_0

AD_STBS_1

AGP_BUSY*

AGP8X_DET*

AGPREF

AGPTEST

C_BE_0* C_BE_1* C_BE_2* C_BE_3*

DBI_HI

DEVSEL*

FRAME*

GNT*

INTA*

IRDY*

PAR

PCICLK

RBF*

REQ*

RST*

SB_STBF SB_STBS

SBA_0 SBA_1 SBA_2 SBA_3 SBA_4 SBA_5 SBA_6 SBA_7

ST_0 ST_1 ST_2

STOP*

STP_AGP*

SUS_STAT*

TRDY*

WBF*

AD_31

AGP 8X

AGP ONLY

AGP/PCI INTERFACE

(1 OF 8)

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

SPACING

PHYSICAL

DIFFERENTIAL_PAIR

(NONE)

by this page.

both GPU and NB

- =PP1V5_AGP

- =PP3V3_AGP

NOTE: AGP 8x signals are not provided

BOM options provided by this page:

- =AGP_GPU_RESET_L - Active low reset for GPU

- =AGP_VREF - VRef divider output for

Signal aliases required by this page:

Power aliases required by this page:

Page Notes

PLACE C5731 AT GPU PLACE C5732 AT NB PLACE RESISTORS MIDWAY BETWEEN

CONNECT TO GPU AGP REF CAN ALSO CONNECT TO NB

IF CHIPS ARE CO-LOCATED

10% 16V X5R

0.1uF

402

2

1

C5731

402

MF-LF

1/16W

5%

47K

2

1

R5725

47K

5% 1/16W MF-LF 402

2

1

R5726

402

MF-LF

1/16W

5%

10K

2

1

R5720

47

5% 1/16W MF-LF

402

21

R5700

47

1% 1/16W MF-LF

402

2

1

R5721

1%

1K

1/16W MF-LF 402

2

1

R5730

1%

1K

402

MF-LF

1/16W

2

1

R5731

20K

5% 1/16W MF-LF 402

2

1

R5722

402

0.1uF

X5R

16V

10%

2

1

C5732

BGA

M11P

OMIT

CRITICAL

AC26

V28

AG26

AH30

N26

AE28

AD27

AF29

Y29

Y28

AA29

AA28

AC29

AC28

AD29

AD28

AB28

AB29

AG28

AF28

AE29

AG30

M25

W29

AE26

AD26

W28

V29

AB26

AB25

U26

P26

U28

N29

M27 M26

AH29

AC25

V26

M29

V25

M28

P29

N28

L28

L29

K28

K29

AA27

AA25

J28

AA26

Y25

Y26

W25

W26

V27

U25

T26

T25

R25

J29

R27

P25

R26

N25

U29

T28

T29

R28

R29

P28

H28

H29

U5700

I798

GPU (M11) AGP Interface

SYNC_DATE=N/A

SYNC_MASTER=N/A

C

051-6929

115

57

AGP_INT_L

AGP_GNT_L

AGP_AD<14>

AGP_AD<2>

ATI_DBI_LO_PU

AGP_AD<21>

AGP_AD<26>

AGP_AD<24>

AGP_AD<3> AGP_AD<4>

AGP_AD<11>

AGP_AD<0> AGP_AD<1>

AGP_AD<10>

AGP_AD<12> AGP_AD<13>

AGP_AD<15> AGP_AD<16> AGP_AD<17> AGP_AD<18> AGP_AD<19> AGP_AD<20>

AGP_AD<22> AGP_AD<23>

AGP_AD<25>

AGP_AD<27> AGP_AD<28> AGP_AD<29> AGP_AD<30>

AGP_AD<5> AGP_AD<6> AGP_AD<7> AGP_AD<8> AGP_AD<9>

AGP_AD_STB0_P

AGP_AD_STB1_P

AGP_AD_STB0_N

AGP_AD_STB1_N

AGP_BUSY_L

AGP8X_DET_PU

=GPU_AGP_VREF

GPU_AGPTEST

AGP_CBE_L<0> AGP_CBE_L<1> AGP_CBE_L<2> AGP_CBE_L<3>

ATI_DBI_HI_PU

AGP_DEVSEL_L

AGP_FRAME_L

AGP_IRDY_L

AGP_PAR

AGP_CLK66M_GPU

AGP_RBF_L

AGP_REQ_L

AGP_ATI_RESET_L

AGP_SB_STB_P AGP_SB_STB_N

AGP_SBA<0> AGP_SBA<1> AGP_SBA<2> AGP_SBA<3> AGP_SBA<4> AGP_SBA<5> AGP_SBA<6> AGP_SBA<7>

AGP_ST<0> AGP_ST<1> AGP_ST<2>

AGP_STOP_L

AGP_SUS_STAT_L_PU

AGP_TRDY_L

AGP_WBF_L

AGP_AD<31>

=PP1V5_AGP

=PP3V3_AGP

=PP1V5_AGP

=AGP_GPU_RESET_L

=AGP_VREF

=PP3V3_AGP

STOP_AGP_L

AGP_CLK66M_GPU

CLOCKCLOCK

47

44

44 44

44

43

44

43

43 43

43

44

22

6

43

11

43

6

43

11

6

43

6

43

10

10 10

11

10

43

11

B00ST

SW

TG

EXT VCC VCC

INT

VIN

SGND PGND

RUN/SS

BG

VFB

ITH

ION

PGOOD

VRNG FCB

G

D

S

G

D

S

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

WHEN VCORE_CNTL LOW => 1.054V

NOTE: Implements "Power Miser" feature for ATI GPUs

BOM options provided by this page:

signal for power sequencing

- =GPUVCORE_PGOOD - Active high Power Good

- =PP5V_PWRON_LTC1778_GPU_EXTVCC

- =PPVIN_LTC1778_GPU

- =PPVCORE_GPU_REG

Signal aliases required by this page:

Power aliases required by this page:

Page Notes

GPU VCORE SUPPLY

Rc

- GPU_PWRPLAY

WHEN VCORE_CNTL HIGH => 1.307V

1.054V = 0.8V * (1 + Ra / Rb)

1.307V = 0.8V * (1 + Ra*(Rc+Rb) / (Rc*Rb))

Ra

Rb

CRITICAL

22uF

20%

10V CERM 1210

2

1

C5801

SMB

B340LBXF

2

1

D5800

603

CERM

25V

20%

0.1uF

2

1

C5823

2.2

5% 1/10W MF-LF

603

21

R5823

603

CERM

20%

0.1uF

25V

2

1

C5820

1/10W

5%

603

MF-LF

1

2

1

R5820

402

MF-LF

1/16W

1%

576K

2

1

R5821

402

0

5% 1/16W MF-LF

2

1

R5828

SM

21

XW5800

SSOP-LF

CRITICAL

LTC1778

3

10

8

15 14

6

1

2

13

5

7

1149

16

12

U5800

402

NO STUFF

0

5% 1/16W MF-LF

2

1

R5829

402

CERM

25V

5%

220pF

2

1

C5831

20%

1206

CERM

25V

4.7uF

2

1

C5811

100K

5% 1/16W MF-LF

402

2

1

R5822

0.1uF

20% 10V CERM 402

2

1

C5822

10% 50V

CERM

402

470pF

2

1

C5830

402

20.0K

1% 1/16W MF-LF

2

1

R5830

402

NO STUFF

63.4K

1% 1/16W MF-LF

2

1

R5826

402

0

5% 1/16W MF-LF

2

1

R5827

4.7uF

20%

25V CERM 1206

2

1

C5810

SO-8-PWRPK-LF

SI7860DP

CRITICAL

321

4

5

Q5800

NO STUFF

50V 402

CERM

0.0022UF

10%

2

1

C5824

470uF

2.5V TANT

7343-H2.9

CRITICAL

20%

2

1

C5803

20%

CRITICAL

7343-H2.9

TANT

2.5V

470uF

2

1

C5802

2.1uH-11A

SM

CRITICAL

3

1

2

L5800

4.7UF

20% 10V CERM 1206

2

1

C5825

MBR0540XXG

SOD-123

2

1

D5823

SO-8-PWRPK-LF

SI7892DP

CRITICAL

321

4

5

Q5801

GPU_PWRPLAY

402

MF-LF

1/16W

1%

18.2K

2

1

R5881

GPU_PWRPLAY

402

MF-LF

1/16W

1%

1.82K

2

1

R5882

GPU_PWRPLAY

0.1uF

20% 10V

CERM

402

2

1

C5882

GPU_PWRPLAY

SOT-363

2N7002DW-X-F

4

5

3

Q5884

GPU_PWRPLAY

100K

5% 1/16W MF-LF

402

2

1

R5884

GPU_PWRPLAY

2N7002DW-X-F

SOT-363

1

2

6

Q5884

0.1uF

20% 10V

CERM

402

NO STUFF

2

1

C5885

GPU_PWRPLAY

MF-LF

402

10K

5%

1/16W

21

R5885

6.34K

1% 1/16W MF-LF

402

2

1

R5880

20.0K

1% 1/16W MF-LF

402

2

1

R5883

CERM

10V

20%

0.1uF

402

2

1

C5804

CERM

10V

20%

0.1uF

402

2

1

C5805

C

051-6929

115

58

GPU VCore Supply

SYNC_MASTER=N/A

SYNC_DATE=N/A

=PP5V_PWRON_LTC1778_GPU_EXTVCC

=PPVCORE_GPU_REG

GPUVCORE_SHDN_L

GPU_VCORE_HI_L

GPU_VCORE_HI_L_RC

1778_VRNG 1778_FCB

1778_ION

1778_BG

1778_BST_RC

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=0V

1778_GND

1778_ITH_RC

1778_ITH

MIN_LINE_WIDTH=0.38 mm

VOLTAGE=5V MIN_NECK_WIDTH=0.25 mm

PPVOUT_1778_VCC

GPU_VCORE_HI

HIGH_GPU_VCORE_DIV

PPVIN_1778_VIN

MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm

VOLTAGE=12.8V

=PP5V_PWRON_GPUVCORE_PWRPLAY

HIGH_GPU_VCORE_L

1778_BST 1778_TG

=GPUVCORE_PGOOD

1778_VFB

GPU_VCORE_SW

=PPVIN_LTC1778_GPU

10

26

51

2

10

26

10

VSS

HOST GROUND

(6 OF 8)

CORE GND

I/O GROUND

VDD15

VDDCI

VDDC

(8 OF 8)

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

- =PP1VR1V3_GPU_VCORE

(NONE)

- =PP1V5_GPU_VDD15

Power aliases required by this page:

Signal aliases required by this page:

BOM options provided by this page:

Page Notes

Internal I/O - 1.5V

(500mA)

Internal I/O - 1.3V/1.05V

GPU VCORE - 1.3V/1.05V

402

0.22UF

10%

6.3V CERM-X5R

2

1

C5902

603

10UF

20%

6.3V X5R

2

1

C5900

603

10UF

20%

6.3V X5R

2

1

C5901

402

0.22UF

10%

6.3V CERM-X5R

2

1

C5903

402

CERM-X5R

6.3V

10%

0.22UF

2

1

C5904

603

X5R

6.3V

20%

10UF

2

1

C5955

0.01uF

20% 16V CERM 402

2

1

C5954

402

CERM

16V

20%

0.01uF

2

1

C5953

402

CERM

16V

20%

0.01uF

2

1

C5952

402

CERM

16V

20%

0.01uF

2

1

C5951

402

CERM

16V

20%

0.01uF

2

1

C5959

16V 402

CERM

20%

0.01uF

2

1

C5958

402

CERM

16V

20%

0.01uF

2

1

C5957

402

CERM

16V

20%

0.01uF

2

1

C5956

0805

FERR-220-OHM

21

L5950

SM

60-OHM-EMI

21

L5990

402

0.22UF

10%

6.3V CERM-X5R

2

1

C5907

402

CERM-X5R

6.3V

10%

0.22UF

2

1

C5906

402

CERM-X5R

6.3V

10%

0.22UF

2

1

C5905

402

CERM-X5R

6.3V

10%

0.22UF

2

1

C5908

402

CERM-X5R

6.3V

10%

0.22UF

2

1

C5909

0.22UF

10%

6.3V CERM-X5R 402

2

1

C5914

CERM-X5R

6.3V

10%

0.22UF

402

2

1

C5913

0.22UF

10%

6.3V CERM-X5R 402

2

1

C5919

0.22UF

10%

6.3V CERM-X5R 402

2

1

C5918

CERM-X5R

6.3V

10%

0.22UF

402

2

1

C5912

10%

6.3V CERM-X5R

0.22UF

402

2

1

C5911

10%

6.3V CERM-X5R

0.22UF

402

2

1

C5910

CERM-X5R

6.3V

10%

0.22UF

402

2

1

C5917

0.22UF

10%

6.3V CERM-X5R 402

2

1

C5916

0.22UF

10%

6.3V CERM-X5R 402

2

1

C5915

402

CERM-X5R

6.3V

10%

0.22UF

2

1

C5924

402

0.22UF

10%

6.3V CERM-X5R

2

1

C5923

402

0.22UF

10%

6.3V CERM-X5R

2

1

C5922

0.22UF

CERM-X5R

6.3V

10%

402

2

1

C5921

0.22UF

CERM-X5R

6.3V

10%

402

2

1

C5920

0.01uF

20% 16V CERM 402

2

1

C5994

402

CERM

16V

20%

0.01uF

2

1

C5993

10UF

20%

6.3V X5R 603

2

1

C5990

402

CERM

16V

20%

0.01uF

2

1

C5991

TSOP-LF

SI3446DV

CRITICAL

4

3 6

521

Q5950

10% 25V X7R 402

1000pF

2

1

C5950

BGA

M11P

OMIT

CRITICAL

R8

R7

R30

R24

R23

R18

R17

R16

R15

R14

AB27

R13

R12

P4

P16

P15

N27

N24

N23

N16

N15

AB24

M8

M7

M30

M16

L4

K8

K7

K30

K27

K24

AB23

K23

K1

H9

H8

H4

H27

H23

H21

H18

H16

AB1

H14

H12

G9

G24

G21

G18

G16

G12

F27

E4

AA30

D9D6D4

D27

D25

D24

D21

D18

D15

D12

A29

D10

C30

C3

C28

C1

AK29

AK2

AJ30

AJ1

AG9

A22

AG5

AG27

AG22

AG18

AG15

AG11

AE27

AD30

AD25

AD18

A2

AD16

AD12

AC4

AC18

AC16

AC14

AC12

Y4

W8

W7

W27

AB8

W24

W23

W15

V30

V16

V15

U8

U4

U23

U16

AB7

U15

T27

T19

T18

T17

T16

T15

T14

T13

T1

AB4

A16

A10

U5700

OMIT

CRITICAL

BGA

M11P

W16

T12

R19

M15

M18

M17

M14

M13

M12

W19

AD15

W18

W17

W14

W13

W12

V19

V18

V17

V14

V13

AD13

V12

U19

U18

U17

U14

U13

U12

P19

P18

P17

AC17

P14

P13

P12

N19

N18

N17

N14

N13

N12

M19

AC15

AC13

Y8

Y23

P8

L23

H20

H11

AC20

AC11

U5700

0.01uF

20% 16V CERM 402

2

1

C5992

C

051-6929

115

59

SYNC_DATE=N/A

SYNC_MASTER=N/A

GPU (M11) Core Power

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

VOLTAGE=1.3V

PP1VR1V3_GPU_VDDCI

PP1V5_GPU_VDD15_F

VOLTAGE=1.5V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

GPUVDD15_EN

PP1V5_GPU_VDD15

VOLTAGE=1.5V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

=PP1V5_GPU_VDD15

=PP1V05R1V3_GPU_VCORE

26

10

VDDR1

VDDR4

VDDR3

VDDP

LPVDD

LVDDR_18_0 LVDDR_18_1

LVDDR_25_0 LVDDR_25_1

VDDRH0

VDDRH1

VSSRH1

VSSRH0

(7 OF 8)

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

- GPU_LVDDR_2V8

- GPU_LVDDR_2V5

(20mA)

Power aliases required by this page:

- =PP3V3_GPU_VDDR3

- =PP1V8R2V5_GPU_FB_VIO

- =PP1V5_GPU_DVO

- =PP1V8_GPU_DVO

- =PP1V5R3V3_DVO_VREF

Signal aliases required by this page: (NONE)

BOM options provided by this page:

- DVO_1V5

- DVO_1V8

Page Notes

- =PP1V8_GPU_PANEL_IO

- =PP1V8_GPU_LVDS_PLL

- =PP2V5_GPU_LVDS_IO

- =PP1V5_AGP

NOTE: Implements a low-swing DVO bus only

MEMORY I/O - 1.8V/2.5V

ALSO TXVDDR

LVDS PLL - 1.8V

AGP 4X I/O - 1.5V

(Max Current varies, depends on usage)

(1200mA)

(350mA)

(40mA)

LVDS I/O - 1.8V

(180mA)

GPIO - 3.3V

DVO I/O (EXT.TMDS) - 1.5V/1.8V

LVDS I/O - 2.5V/2.8V

402

CERM

10V

20%

0.1uF

2

1

C6054

20%

10V CERM 402

0.1uF

2

1

C6059

0.01uF

20% 16V CERM 402

2

1

C6064

0.1uF

20% 10V CERM 402

2

1

C6053

0.1uF

20% 10V CERM 402

2

1

C6058

0.01uF

16V

20% CERM

402

2

1

C6063

0.1uF

20% 10V CERM 402

2

1

C6052

402

10V CERM

20%

0.1uF

2

1

C6057

16V

0.01uF

CERM

20%

402

2

1

C6062

6.3V 603

10UF

X5R

20%

2

1

C6051

10V

0.1uF

20% CERM

402

2

1

C6056

0.1uF

20% 10V CERM 402

2

1

C6061

X5R

10UF

20%

6.3V 603

2

1

C6050

0.1uF

20% 10V CERM 402

2

1

C6055

0.1uF

20% 10V

402

CERM

2

1

C6060

FERR-220-OHM

0805

21

L6050

603

X5R

6.3V

20%

10UF

2

1

C6024

0.1uF

20% 10V CERM 402

2

1

C6023

0.01uF

20% 16V CERM 402

2

1

C6028

402

CERM

10V

20%

0.1uF

2

1

C6022

0.01uF

20% 16V CERM 402

2

1

C6027

0.1uF

20% 10V CERM 402

2

1

C6021

0.01uF

20% 16V CERM 402

2

1

C6026

402

CERM

10V

20%

0.1uF

2

1

C6020

0.01uF

402

CERM

16V

20%

2

1

C6025

FERR-10-OHM-500MA

SM

21

L6020

402

CERM

16V

20%

0.01uF

2

1

C6049

603

X5R

6.3V

20%

10UF

2

1

C6048

0.01uF

20% 16V CERM 402

2

1

C6042

16V

0.01uF

20% CERM

402

2

1

C6041

10UF

6.3V X5R 603

20%

2

1

C6040

16V

0.01uF

20% CERM

402

2

1

C6046

402

CERM

10V

20%

0.1uF

2

1

C6045

402

CERM

10V

20%

0.1uF

2

1

C6044

603

X5R

6.3V

20%

10UF

2

1

C6043

FERR-220-OHM

0402

21

L6043

DVO_1V8

SM

FERR-10-OHM-500MA

21

L6010

SM

FERR-10-OHM-500MA

2 1

L6000

402

0.1uF

20% 10V CERM

2

1

C6003

20%

0.1uF

10V CERM 402

2

1

C6002

0.1uF

20% 10V CERM 402

2

1

C6001

10UF

20%

6.3V X5R 603

2

1

C6000

402

10V

20%

0.1uF

CERM

2

1

C6006

0.1uF

20% 10V CERM 402

2

1

C6005

402

0.1uF

20% 10V CERM

2

1

C6004

0.01uF

402

CERM

16V

20%

2

1

C6097

20% 16V CERM 402

0.01uF

2

1

C6096

10UF

20%

6.3V X5R 603

2

1

C6095

402

CERM

16V

20%

0.01uF

2

1

C6047

0402

FERR-220-OHM

21

L6048

GPU_LVDDR_2V5

FERR-10-OHM-500MA

SM

21

L6040

402

CERM

10V

20%

0.1uF

2

1

C6069

0.1uF

20% 10V CERM 402

2

1

C6068

20%

10V CERM 402

0.1uF

2

1

C6074

0.01uF

20% 16V CERM 402

2

1

C6079

0.1uF

20% 10V CERM 402

2

1

C6073

16V

0.01uF

20% CERM

402

2

1

C6078

0.1uF

20% 10V CERM 402

2

1

C6067

6.3V 603

10UF

X5R

20%

2

1

C6066

X5R

10UF

20%

6.3V 603

2

1

C6065

402

10V CERM

20%

0.1uF

2

1

C6072

16V

0.01uF

CERM

20%

402

2

1

C6077

10V

0.1uF

20% CERM

402

2

1

C6071

0.1uF

20% 10V CERM 402

2

1

C6076

0.1uF

20% 10V CERM 402

2

1

C6070

0.1uF

20% 10V

402

CERM

2

1

C6075

0402

FERR-220-OHM

21

L6095

0.1uF

20% 10V CERM 402

2

1

C6013

0.1uF

20% 10V CERM 402

2

1

C6012

402

CERM

10V

20%

0.1uF

2

1

C6011

10UF

20%

6.3V X5R 603

2

1

C6010

402

CERM

10V

20%

0.1uF

2

1

C6015

GPU_LVDDR_2V8

SM

FERR-10-OHM-500MA

21

L6041

DVO_1V5

SM

FERR-10-OHM-500MA

21

L6011

CRITICAL

OMIT

M11P

BGA

M6

F19

N6 F18

AG7

AD9

AD10

AC9

AC10

AD7

AD22

AD21

AD19

AC8

AC22

AC21

AC19

AD4

AA8

AA7

AA4

V8

V7

V4

T8

T7

T4

R4

AA1

R1

N8

N7

N4

M4

L8

L27

J8

J7

J4

A9

J24

J23

J1

H22

H19

H17

H15

H13

H10

G7

A3

G27

G22

G19

G15

G13

G10

F4

E27

D8

D5

A28

D26

D23

D20

D19

D17

D14

D13

D11

B30

B1

A21

A15

M24

M23

J30

AF27

AE30

AC27

AC23

Y27

AB30

W30

V24

V23

U27

T30

T24

T23

P27

P23

N30

AA24

AA23

AE20

AE17

AF21

AE15

AJ20

U5700

402

CERM

10V

20%

0.1uF

2

1

C6014

0.1uF

10V CERM 402

20%

2

1

C6030

0.1uF

20% 10V CERM 402

2

1

C6031

402

CERM

10V

20%

0.1uF

2

1

C6032

10V

0.1uF

402

CERM

20%

2

1

C6033

402

CERM

16V

20%

0.01uF

2

1

C6029

0.1uF

20% 10V CERM 402

2

1

C6084

0.1uF

402

CERM

10V

20%

2

1

C6089

402

CERM

16V

20%

0.01uF

2

1

C6094

402

CERM

10V

20%

0.1uF

2

1

C6083

402

CERM

10V

20%

0.1uF

2

1

C6082

20% X5R

10UF

603

6.3V

2

1

C6081

603

6.3V

20%

10UF

X5R

2

1

C6080

402

CERM

10V

20%

0.1uF

2

1

C6088

16V

0.01uF

402

CERM

20%

2

1

C6093

0.1uF

20% CERM

10V 402

2

1

C6087

16V

0.01uF

402

20% CERM

2

1

C6092

402

CERM

20%

0.1uF

10V

2

1

C6086

402

CERM

10V

20%

0.1uF

2

1

C6091

402

CERM

10V

20%

0.1uF

2

1

C6085

CERM 402

10V

20%

0.1uF

2

1

C6090

GPU (M11) I/O Power

SYNC_DATE=N/A

SYNC_MASTER=N/A

60

115

051-6929

C

MIN_LINE_WIDTH=0.38 mm

VOLTAGE=1.8V MIN_NECK_WIDTH=0.25 mm

PP1V8_GPU_VDD_MEM_CLK

PP3V3_GPU_VDDR3

VOLTAGE=3.3V MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

PP2V5R2V8_GPU_LVDS_IO

VOLTAGE=2.8V MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.25 mm

PP1V8_GPU_LVDS_PLL

VOLTAGE=1.8V MIN_LINE_WIDTH=0.38 mm

MIN_NECK_WIDTH=0.25 mm

=PP1V5_GPU_DVO

=PP1V5_AGP

=PP1V8R2V5_GPU_FB_VIO

=PP3V3_GPU_VDDR3

=PP1V8_GPU_DVO

=PP1V5R3V3_DVO_VREF

=PP1V8_GPU_PANEL_IO

PP1V8_GPU_PANEL_IO

VOLTAGE=1.8V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

=PP2V5_GPU_LVDS_IO

=PP2V8_GPU_LVDS_IO

PP1V5R3V3_GPU_VDDR4

MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm

VOLTAGE=1.8V

MAKE_BASE=TRUE

=PP1V8_GPU_LVDS_PLL

PP1V5_GPU_AGP

VOLTAGE=1.5V MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.25 mm

VOLTAGE=1.8V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

PP1V8R2V5_GPU_FB_VIO

44 43

48

51

10

54

10 53

10

53

51

DQA_0

DQA_6

DQA_5

DQA_21

WEA*

RASA*

QSA_7

QSA_6

QSA_5

QSA_4

QSA_3

QSA_2

QSA_1

QSA_0

MVREFS

MVREFD

MAA_14

MAA_13

MAA_12

MAA_11

MAA_10

MAA_9

MAA_8

MAA_7

MAA_6

MAA_5

MAA_4

MAA_3

MAA_2

MAA_1

MAA_0

DQMA_7*

DQMA_6*

DQMA_5*

DQMA_4*

DQMA_3*

DQMA_2*

DQMA_0*

DQA_59

DQA_58

DQA_57

DQA_56

DQA_55

DQA_54

DQA_53

DQA_52

DQA_51

DQA_50

DQA_49

DQA_48

DQA_47

DQA_46

DQA_45

DQA_44

DQA_43

DQA_42

DQA_41

DQA_40

DQA_39

DQA_38

DQA_37

DQA_36

DQA_35

DQA_34

DQA_33

DQA_32

DQA_31

DQA_30

DQA_29

DQA_28

DQA_26

DQA_25

DQA_24

DQA_23

DQA_22

DQA_15

DQA_14

DQA_12

DQA_11

DQA_10

DQA_9

DQA_8

DQA_7

DQA_4

DQA_2

DQA_1

CSA_1*

CSA_0*

CLKA1*

CLKA1

CLKA0*

CLKA0

CKEA

CASA*

DQA_3

DQA_13

DQMA_1*

DQA_27

DQA_20

DQA_19

DQA_18

DQA_17

DQA_63

DQA_62

DQA_61

DQA_60

DIMA_0 DIMA_1

DQA_16

(4 OF 8)

MEMORY INTERFACE A

DQB_1 DQB_2 DQB_3

MAB_11

QSB_1

MAB_14

CASB*

CKEB

CLKB0

CLKB0*

CLKB1

CLKB1*

DQB_0

DQB_4 DQB_5 DQB_6 DQB_7 DQB_8 DQB_9 DQB_10 DQB_11 DQB_12 DQB_13 DQB_14 DQB_15 DQB_16 DQB_17 DQB_18 DQB_19 DQB_20 DQB_21 DQB_22 DQB_23 DQB_24 DQB_25 DQB_26 DQB_27 DQB_28 DQB_29 DQB_30 DQB_31 DQB_32 DQB_33 DQB_34 DQB_35 DQB_36 DQB_37 DQB_38 DQB_39 DQB_40 DQB_41 DQB_42 DQB_43 DQB_44 DQB_45 DQB_46 DQB_47 DQB_48 DQB_49 DQB_50 DQB_51 DQB_52 DQB_53 DQB_54 DQB_55 DQB_56 DQB_57 DQB_58

DQMB_0* DQMB_1* DQMB_2* DQMB_3* DQMB_4* DQMB_5* DQMB_6* DQMB_7*

MAB_0 MAB_1 MAB_2 MAB_3 MAB_4 MAB_5 MAB_6 MAB_7 MAB_8 MAB_9

MAB_10

MAB_12 MAB_13

QSB_0

QSB_2 QSB_3 QSB_4 QSB_5

RASB*

WEB*

QSB_7

QSB_6

MEMVMODE_1

MEMVMODE_0

DQB_63

DQB_62

DQB_61

DQB_59 DQB_60

CSB_1*

CSB_0*

TEST_YCLK

TEST_MCLK

MEMTEST

DIMB_0 DIMB_1

(5 OF 8)

MEMORY INTERFACE B

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

GPU Frame Buffer Series Term

NC

Page Notes

- GPU_MEMIO_2V5

Power aliases required by this page:

- =PP1V8R2V5_GPU_FB_VIO

- =PP1V8_GPU_MEMVMODE

Signal aliases required by this page:

BOM options provided by this page:

- GPU_MEMIO_1V8

(NONE)

6

7

0

1

2

3

5

4

6

7

9

8

10

11

0

1

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

1%

1K

1/16W MF-LF 402

2

1

R6190

1%

1K

1/16W MF-LF 402

2

1

R6191

402

X5R

16V

10%

0.1uF

2

1

C6191

4.7K

1/16W MF-LF

402

5%

GPU_MEMIO_1V8

2

1

R6196

4.7K

5%

402

MF-LF

1/16W

GPU_MEMIO_2V5

2

1

R6197

45.3

1%

402

MF-LF

1/16W

2

1

R6194

BGA

M11P

CRITICAL

OMIT

E19

A19

F10

B11

B16

E16

B27

F24

F30

J27

B8

B7

A24

C21

F21

F22

C22

C23

B24

B23

C19

B20

E21

A25

C24

B22

E22

E11

C11

C15

F15

A27

E25

F29

J25

D29

G30

G26

F8

F9

E9

F11

H26

F12

E10

E12

E13

B10

B9

C9

C10

B12

C12

H25

A12

A13

C16

C14

B14

C13

B15

B17

B18

C17

J26

F13

E14

F14

E15

F16

D16

E17

F17

B26

C26

K26

B25

B28

C27

C25

C29

B29

D22

E23

F23

E24

K25

F25

E26

F26

G25

F28

G28

G29

E29

E28

D28

L26

L25

B13

D30

F20

E20

A18

C18

C20

B21

B19

E18

U5700

BGA

M11P

CRITICAL

OMIT

T6

E8

B6

R2

AD1

AC5

W1

V5

G1

K6

B3

F6

C7

C6

C8

K2

N3

P6

M5

M2

L2

L3

M3

P2

P3

P5

J2

K3

M1

N5

AD2

AC6

W2

W6

G3

J5

B2

E6

C5

B5

C4

AE3

AE2

AE1

AD3

E5

AC3

AC2

AB3

AB2

AE4

AE5

AD5

AD6

AB5

AB6

F5

AA5

AA6

AA2

Y3

Y2

W3

V3

V1

V2

U2

G5

Y5

Y6

W4

W5

V6

U3

U5

U6

H3

F1

G6

J3

F2

E2

H2

F3

G2

L5

L6

K4

K5

E7

J6

H5

H6

G4

D2

D1

D3

C2

B4

A4

F7

D7

AA3

E3

R6

R5

T3

T2

N2

N1

R3

T5

U5700

4.7K

5%

402

MF-LF

1/16W

GPU_MEMIO_2V5

2

1

R6198

4.7K

1/16W MF-LF 402

5%

GPU_MEMIO_1V8

2

1

R6199

0

1

2

3

4

5

6

7

8

9

10

11

0

1

SM-LF

1/16W

5%

0

54

RP6152

SM-LF

1/16W

5%

0

72

RP6151

0

1

2

SM-LF

0

5%

1/16W

81

RP6152

SM-LF

0

5%

1/16W

63

RP6150

SM-LF

0

5%

1/16W

72

RP6152

3

SM-LF

0

5%

1/16W

54

RP6150

4

5

0

1

2

3

4

5

SM-LF

0

5%

1/16W

72

RP6102

SM-LF

0

5%

1/16W

81

RP6101

0

1

2

1/16W

5%

0

SM-LF

63

RP6101

SM-LF

1/16W

5%

0

63

RP6100

SM-LF

1/16W

5%

0

81

RP6102

3

SM-LF

1/16W

5%

0

72

RP6101

4

5

SM-LF

1/16W

5%

0

81

RP6151

SM-LF

1/16W

5%

0

63

RP6151

6

7

SM-LF

0

5%

1/16W

63

RP6152

8

SM-LF

0

5%

1/16W

72

RP6150

SM-LF

1/16W

5%

0

81

RP6150

SM-LF

1/16W

5%

0

54

RP6151

9

10

402

MF-LF

1/16W

5%

0

21

R6153

11

0

5% 1/16W MF-LF

402

21

R6154

0

5% 1/16W MF-LF

402

21

R6156

1

0

5% 1/16W MF-LF

402

21

R6155

0

5% 1/16W MF-LF

402

21

R6158

0

5% 1/16W MF-LF

402

21

R6157

402

MF-LF

1/16W

5%

0

21

R6159

6

7

8

9

10

11

0

1

SM-LF

10

5%

1/16W

41

RP6158

SM-LF

1/16W

5%

10

32

RP6158

SM-LF

1/16W

5%

10

32

RP6159

SM-LF

10

5%

1/16W

41

RP6159

SM-LF

0

5%

1/16W

63

RP6102

SM-LF

0

5%

1/16W

54

RP6101

7

6

SM-LF

1/16W

5%

0

54

RP6102

8

SM-LF

1/16W

5%

0

54

RP6100

SM-LF

1/16W

5%

0

81

RP6100

9

SM-LF

0

5%

1/16W

72

RP6100

10

MF-LF

402

1/16W

5%

0

21

R6103

0

11

0

5% 1/16W MF-LF

402

21

R6104

402

MF-LF

1/16W

5%

0

21

R6106

402

MF-LF

1/16W

5%

0

21

R6105

1

402

MF-LF

1/16W

5%

0

21

R6108

402

MF-LF

1/16W

5%

0

21

R6107

0

5% 1/16W MF-LF

402

21

R6109

SM-LF

10

5%

1/16W

41

RP6108

SM-LF

1/16W

5%

10

32

RP6109

SM-LF

1/16W

5%

10

32

RP6108

SM-LF

10

5%

1/16W

41

RP6109

X5R

10uF

20%

6.3V 603

2

1

C6190

402

MF-LF

1/16W

1K

1%

2

1

R6192

402

MF-LF

1/16W

1K

1%

2

1

R6193

0.1uF

10% 16V X5R 402

2

1

C6193

603

6.3V

20%

10uF

X5R

2

1

C6192

1

0

3

2

4

6

5

8

9

7

10

11

14

12

13

16

15

18

19

17

20

21

22

24

23

26

25

27

28

29

32

30

31

34

33

36

37

35

38

39

40

42

41

44

43

45

46

47

50

48

49

52

51

54

55

53

56

57

60

58

59

62

61

63

1

0

3

2

4

6

5

8

9

7

10

11

14

12

13

16

15

18

19

17

20

21

22

24

23

26

25

27

28

29

32

30

31

34

33

36

37

35

38

39

40

42

41

44

43

45

46

47

50

48

49

52

51

54

55

53

56

57

60

58

59

62

61

63

0

1

2

3

5

4

6

7

9

8

10

11

0

1

0

1

2

3

4

5

6

7

0

1

2

3

4

5

SYNC_MASTER=N/A

SYNC_DATE=N/A

61

115

051-6929

C

GPU (M11) Frame Buffer I/F

NO_TEST=YES

FB_A_BA_R<1..0>

FB_A_BA<1..0>

NO_TEST=YES

FB_B_ADDR<11..0>

NO_TEST=YES

FB_B_BA<1..0>

NO_TEST=YES

FB_B_ADDR_R<11..0>

NO_TEST=YES

FB_A_ADDR<11..0>

NO_TEST=YES

FB_A_ADDR_R<11..0>

NO_TEST=YES

FB_B_BA_R<1..0>

FB_B_DQ_R<63..0>

FB_B_ADDR_R<11..0>

FB_B_DQS_R<7..0>

FB_B_DQM_R<7..0>

FB_B_BA_R<1..0>

FB_A_DQ_R<63..0>

FB_A_DQS_R<7..0>

FB_A_BA_R<1..0>

FB_A_ADDR_R<11..0>

FB_A_DQM_R<7..0>

VOLTAGE=0.9V MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.15 mm

GPU_MVREFS

FB_A_CAS_L_R

FB_A_CKE_R

FB_A_CLKDDR_0_P_R FB_A_CLKDDR_0_N_R

FB_A_CLKDDR_1_P_R FB_A_CLKDDR_1_N_R

FB_A_CS_L_R

FB_A_RAS_L_R

FB_A_WE_L_R

FB_B_CS_L_R

FB_B_WE_L_R

FB_B_RAS_L_R

FB_B_CLKDDR_1_N_R

FB_B_CLKDDR_1_P_R

FB_B_CLKDDR_0_N_R

FB_B_CLKDDR_0_P_R

FB_B_CKE_R

FB_B_CAS_L_R

GPU_MEMTEST

GPU_MEMVMODE1 GPU_MEMVMODE0

=PP1V8_GPU_MEMVMODE

NO_TEST=YES

FB_A_CLKDDR_0_P_R

NO_TEST=YES

FB_A_CLKDDR_0_N_R

NO_TEST=YES

FB_A_CLKDDR_1_P_R

NO_TEST=YES

FB_A_CLKDDR_1_N_R

FB_A_DQM_R<7..0>

FB_A_DQ_R<63..0>

FB_A_DQS_R<7..0>

NO_TEST=YES

FB_A_RAS_L_R

NO_TEST=YES

FB_A_WE_L_R

NO_TEST=YES

FB_A_CAS_L_R

NO_TEST=YES

FB_A_CKE_R

FB_A_CLKDDR_0_P

FB_A_CLKDDR_1_P

FB_A_CS_L

NO_TEST=YES

FB_A_CAS_L

FB_A_CKE

NO_TEST=YES

MAKE_BASE=TRUE

FB_A_DQM<7..0>

NO_TEST=YES

MAKE_BASE=TRUE

FB_A_DQ<63..0>

NO_TEST=YES

MAKE_BASE=TRUE

FB_A_DQS<7..0>

FB_A_CLKDDR_0_N

FB_A_CLKDDR_1_N

NO_TEST=YES

FB_B_CLKDDR_1_N_R

NO_TEST=YES

FB_B_CLKDDR_1_P_R

NO_TEST=YES

FB_B_CLKDDR_0_N_R

NO_TEST=YES

FB_B_CLKDDR_0_P_R

FB_B_DQM_R<7..0>

FB_B_DQS_R<7..0>

FB_B_DQ_R<63..0>

NO_TEST=YES

FB_A_RAS_L

NO_TEST=YES

FB_A_WE_L

NO_TEST=YES

FB_B_WE_L_R

NO_TEST=YES

FB_B_RAS_L_R

NO_TEST=YES

FB_B_CS_L_R

NO_TEST=YES

FB_B_CAS_L_R

NO_TEST=YES

FB_B_CKE_R

FB_B_CLKDDR_1_P

FB_B_CLKDDR_0_P

FB_B_CS_L

NO_TEST=YES

FB_B_CAS_L

FB_B_CKE

NO_TEST=YES

MAKE_BASE=TRUE

FB_B_DQM<7..0>

NO_TEST=YES

MAKE_BASE=TRUE

FB_B_DQS<7..0>

NO_TEST=YES

MAKE_BASE=TRUE

FB_B_DQ<63..0>

FB_B_CLKDDR_1_N

FB_B_CLKDDR_0_N

NO_TEST=YES

FB_B_WE_L

NO_TEST=YES

FB_B_RAS_L

=PP1V8R2V5_GPU_FB_VIO

VOLTAGE=0.9V MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.15 mm

GPU_MVREFD

FB_A_CS_L_R

NO_TEST=YES

48

48 48

48

47

48

42 49

50

42

49

42

10

42

49

49 42

42

49

49 42

42

50

10

42

NC

RFU2

RFU1

MCL

DQ4

DQ6

DQ5

DQ3

DQ2

DQ1

DQ0

DQ7 DQ8

DQ10 DQ11

DQ9

DQ12 DQ13

DQ15 DQ16

DQ14

DQ17

DQ21

DQ19 DQ20

DQ18

DQ22

DQ24

DQ23

DQ25 DQ26 DQ27

DQ30

DQ29

DQ28

DQ31

A7

A4 A5 A6

A3

A2

A1

A0

A8/AP

DQS0

DQS3

DQS1 DQS2

DM0

A9 A10 A11

DM1 DM2 DM3

BA0 BA1

CLK

CKE

CLK*

CS* RAS*

WE*

CAS*

(1 OF 2)

(2 OF 2)

VDD

VSS

VDDQ

VSS_THERM

VREF

VSSQ

(2 OF 2)

VDD

VSS

VDDQ

VSS_THERM

VREF

VSSQ

NC

RFU2

RFU1

MCL

DQ4

DQ6

DQ5

DQ3

DQ2

DQ1

DQ0

DQ7 DQ8

DQ10 DQ11

DQ9

DQ12 DQ13

DQ15 DQ16

DQ14

DQ17

DQ21

DQ19 DQ20

DQ18

DQ22

DQ24

DQ23

DQ25 DQ26 DQ27

DQ30

DQ29

DQ28

DQ31

A7

A4 A5 A6

A3

A2

A1

A0

A8/AP

DQS0

DQS3

DQS1 DQS2

DM0

A9 A10 A11

DM1 DM2 DM3

BA0 BA1

CLK

CKE

CLK*

CS* RAS*

WE*

CAS*

(1 OF 2)

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NC

NC NC NC

NC NC NC NC NC

NC

NCNC

NC

- =PP1V8_FB_VDD

- =PP1V8_FB_VDDQ

(NONE)

Power aliases required by this page:

Page Notes

Signal aliases required by this page:

BOM options provided by this page:

DIFFERENTIAL_PAIR

PHYSICAL

NET_TYPE

SPACING

ELECTRICAL_CONSTRAINT_SET

ECSETs provided by GPU

300MHZ-BGA-LF

SDRAM_GDDR-2MX32X4

K4D553235F

CRITICAL

OMIT

L3

M10

L9

M2

N3

M4

M3

L13

L12

H11

H4

C11

C4

M13

B13

H2

H13

B2

K12

K13

E2

D2

D3

C2

B8

C9

B5

B9

B10

C13

D12

D13

E13

K3

K2

J2

J3

B6

G2

G3

F2

F3

F12

F13

G12

G13

J12

J13

C6

B7

B12

H3

H12

B3

N2

M12

M11

N12

L2

M5

N4

M8

N11

N10

N9

M9

N8

N7

M6

M7

L6

N6

N5

U6200

402

MF-LF

1/16W

5%

1K

2

1

R6240

402

MF-LF

1/16W

5%

1K

2

1

R6241

10uF

20% 4V X5R 603

2

1

C6200

402

X5R

16V

10%

0.1uF

2

1

C6203

10uF

20% 4V X5R 603

2

1

C6210

10uF

20% 4V X5R 603

2

1

C6211

0.1uF

10% 16V X5R 402

2

1

C6202

402

X5R

16V

10%

0.1uF

2

1

C6204

0.1uF

10% 16V X5R 402

2

1

C6201

0.1uF

10% 16V X5R 402

2

1

C6212

402

X5R

16V

10%

0.1uF

2

1

C6213

0.1uF

10% 16V X5R 402

2

1

C6214

402

X5R

16V

10%

0.1uF

2

1

C6215

0.1uF

10% 16V X5R 402

2

1

C6216

402

X5R

16V

10%

0.1uF

2

1

C6217

0.1uF

10% 16V X5R 402

2

1

C6218

402

X5R

16V

10%

0.1uF

2

1

C6219

0.1uF

10% 16V X5R 402

2

1

C6220

402

X5R

16V

10%

0.1uF

2

1

C6221

0.1uF

10% 16V X5R 402

2

1

C6254

0.1uF

10% 16V X5R 402

2

1

C6253

0.1uF

10% 16V X5R 402

2

1

C6263

0.1uF

10% 16V X5R 402

2

1

C6267

402

X5R

16V

10%

0.1uF

2

1

C6252

402

X5R

16V

10%

0.1uF

2

1

C6251

402

X5R

16V

10%

0.1uF

2

1

C6262

402

X5R

16V

10%

0.1uF

2

1

C6266

603

X5R

4V

20%

10uF

2

1

C6261

0.1uF

10% 16V X5R 402

2

1

C6265

603

X5R

4V

20%

10uF

2

1

C6250

402

X5R

16V

10%

0.1uF

2

1

C6264

603

X5R

4V

20%

10uF

2

1

C6260

K4D553235F

300MHZ-BGA-LF

SDRAM_GDDR-2MX32X4

CRITICAL

OMIT

E9

E6

D11

D10

D9

D6

D5

D4

K10

K5

J10

J5

H10

H5

G10

G5

F10

F5

B11

B4

H7

H6

G9

G8

G7

G6

F9

F8

J9

J8

J7

J6

H9

H8

F7

F6

L10

L5

K9

K8

K7

K6

E10

E8

E7

E5

N13

F11

F4

E12

E3

C12

C10

C8

C7

K11

K4

J11

J4

G11

G4

C5

C3

L11

L8

L7

L4

E11

E4

D8

D7

U6250

0.1uF

10% 16V X5R 402

2

1

C6271

0.1uF

10% 16V X5R 402

2

1

C6291

1K

5% 1/16W MF-LF 402

2

1

R6290

1K

5% 1/16W MF-LF 402

2

1

R6291

402

X5R

16V

10%

0.1uF

2

1

C6270

0.1uF

10% 16V X5R 402

2

1

C6269

SDRAM_GDDR-2MX32X4

300MHZ-BGA-LF

K4D553235F

CRITICAL

OMIT

E9

E6

D11

D10

D9

D6

D5

D4

K10

K5

J10

J5

H10

H5

G10

G5

F10

F5

B11

B4

H7

H6

G9

G8

G7

G6

F9

F8

J9

J8

J7

J6

H9

H8

F7

F6

L10

L5

K9

K8

K7

K6

E10

E8

E7

E5

N13

F11

F4

E12

E3

C12

C10

C8

C7

K11

K4

J11

J4

G11

G4

C5

C3

L11

L8

L7

L4

E11

E4

D8

D7

U6200

K4D553235F

SDRAM_GDDR-2MX32X4

300MHZ-BGA-LF

CRITICAL

OMIT

L3

M10

L9

M2

N3

M4

M3

L13

L12

H11

H4

C11

C4

M13

B13

H2

H13

B2

K12

K13

E2

D2

D3

C2

B8

C9

B5

B9

B10

C13

D12

D13

E13

K3

K2

J2

J3

B6

G2

G3

F2

F3

F12

F13

G12

G13

J12

J13

C6

B7

B12

H3

H12

B3

N2

M12

M11

N12

L2

M5

N4

M8

N11

N10

N9

M9

N8

N7

M6

M7

L6

N6

N5

U6250

402

X5R

16V

10%

0.1uF

2

1

C6268

10% 50V

470pF

CERM 402

2

1

C6245

56

5% 1/16W MF-LF

402

2

1

R6245

402

MF-LF

1/16W

5%

56

2

1

R6246

56

5% 1/16W MF-LF

402

2

1

R6296

402

MF-LF

1/16W

5%

56

2

1

R6295

50V

10%

470pF

402

CERM

2

1

C6295

I244

I245

I246 I247

I248

I249 I250

I251

I252

I253

I254

I255

I256 I257

402

X5R

16V

10%

0.1uF

2

1

C6241

SYNC_MASTER=N/A

GPU Frame Buffer A

051-6929

C

115

62

SYNC_DATE=N/A

RAM RAM

FB_A_DQ<63..0>

FB_A_CAS_L

RAMRAM

FB_A_WE_L

RAMRAM

FB_A_DQS<7..0>

RAM RAM

FB_A_DQM<7..0>

RAMRAM

FB_A_CKE

RAMRAM

FB_A_CS_L

RAM RAM

FB_A_ADDR<11..0>

RAMRAM

FB_A_BA<1..0>

RAMRAM

FB_A_RAS_L

RAMRAM

RAM_DIFFRAM_DIFF

FB_A_CLKDDR_0_P

FB_A_CLK_0

RAM_DIFFRAM_DIFF

FB_A_CLKDDR_0_N

FB_A_CLK_0

RAM_DIFFRAM_DIFF

FB_A_CLKDDR_1_P

FB_A_CLK_1

RAM_DIFFRAM_DIFF

FB_A_CLKDDR_1_N

FB_A_CLK_1

=PP1V8_FB_VDDQ

=PP1V8_FB_VDD

FB_A_DDRCLK_1_RC

FB_A_WE_L

FB_A_RAS_L FB_A_CAS_L

FB_A_CS_L

FB_A_CKE

FB_A_CLKDDR_1_N

FB_A_CLKDDR_1_P

FB_C0_VREF

=PP1V8_FB_VDDQ

=PP1V8_FB_VDD

FB_C1_VREF

FB_A_DDRCLK_0_RC

FB_A_CLKDDR_0_P FB_A_CLKDDR_0_N FB_A_CKE FB_A_CS_L

FB_A_CAS_L

FB_A_RAS_L

FB_A_WE_L

FB_A_ADDR<0> FB_A_ADDR<1> FB_A_ADDR<2> FB_A_ADDR<3> FB_A_ADDR<4> FB_A_ADDR<5>

FB_A_BA<0> FB_A_BA<1>

FB_A_DQM<3>

FB_A_DQS<3>

FB_A_DQM<2> FB_A_DQM<1> FB_A_DQM<0>

FB_A_ADDR<6> FB_A_ADDR<7> FB_A_ADDR<8> FB_A_ADDR<9> FB_A_ADDR<10> FB_A_ADDR<11>

FB_A_DQS<2> FB_A_DQS<1> FB_A_DQS<0>

FB_A_DQ<26> FB_A_DQ<29> FB_A_DQ<30> FB_A_DQ<31> FB_A_DQ<24> FB_A_DQ<25> FB_A_DQ<28> FB_A_DQ<27> FB_A_DQ<16> FB_A_DQ<17> FB_A_DQ<21> FB_A_DQ<19> FB_A_DQ<23> FB_A_DQ<22> FB_A_DQ<18> FB_A_DQ<20> FB_A_DQ<8> FB_A_DQ<13> FB_A_DQ<12> FB_A_DQ<9> FB_A_DQ<15> FB_A_DQ<10> FB_A_DQ<11> FB_A_DQ<14> FB_A_DQ<0> FB_A_DQ<1> FB_A_DQ<2> FB_A_DQ<3> FB_A_DQ<5> FB_A_DQ<7> FB_A_DQ<4> FB_A_DQ<6>

FB_A_ADDR<5>

FB_A_ADDR<4>

FB_A_ADDR<3>

FB_A_ADDR<2>

FB_A_ADDR<1>

FB_A_ADDR<0>

FB_A_DQS<5>

FB_A_DQS<7>

FB_A_DQS<4>

FB_A_ADDR<11>

FB_A_ADDR<10>

FB_A_ADDR<9>

FB_A_ADDR<8>

FB_A_ADDR<7>

FB_A_ADDR<6>

FB_A_DQM<5>

FB_A_DQM<7>

FB_A_DQM<4>

FB_A_DQS<6>

FB_A_DQM<6>

FB_A_BA<1>

FB_A_BA<0>

FB_A_DQ<49>

FB_A_DQ<52>

FB_A_DQ<55>

FB_A_DQ<53>

FB_A_DQ<54>

FB_A_DQ<32>

FB_A_DQ<39>

FB_A_DQ<33>

FB_A_DQ<38>

FB_A_DQ<35>

FB_A_DQ<36>

FB_A_DQ<34>

FB_A_DQ<48>

FB_A_DQ<50>

FB_A_DQ<51>

FB_A_DQ<41>

FB_A_DQ<57>

FB_A_DQ<58>

FB_A_DQ<61>

FB_A_DQ<56>

FB_A_DQ<62>

FB_A_DQ<63>

FB_A_DQ<59>

FB_A_DQ<60>

FB_A_DQ<37>

FB_A_DQ<44>

FB_A_DQ<46>

FB_A_DQ<45>

FB_A_DQ<43>

FB_A_DQ<47>

FB_A_DQ<42>

FB_A_DQ<40>

50

49

48

10

48

10

48

NC

RFU2

RFU1

MCL

DQ4

DQ6

DQ5

DQ3

DQ2

DQ1

DQ0

DQ7 DQ8

DQ10 DQ11

DQ9

DQ12 DQ13

DQ15 DQ16

DQ14

DQ17

DQ21

DQ19 DQ20

DQ18

DQ22

DQ24

DQ23

DQ25 DQ26 DQ27

DQ30

DQ29

DQ28

DQ31

A7

A4 A5 A6

A3

A2

A1

A0

A8/AP

DQS0

DQS3

DQS1 DQS2

DM0

A9 A10 A11

DM1 DM2 DM3

BA0 BA1

CLK

CKE

CLK*

CS* RAS*

WE*

CAS*

(1 OF 2)

(2 OF 2)

VDD

VSS

VDDQ

VSS_THERM

VREF

VSSQ

(2 OF 2)

VDD

VSS

VDDQ

VSS_THERM

VREF

VSSQ

NC

RFU2

RFU1

MCL

DQ4

DQ6

DQ5

DQ3

DQ2

DQ1

DQ0

DQ7 DQ8

DQ10 DQ11

DQ9

DQ12 DQ13

DQ15 DQ16

DQ14

DQ17

DQ21

DQ19 DQ20

DQ18

DQ22

DQ24

DQ23

DQ25 DQ26 DQ27

DQ30

DQ29

DQ28

DQ31

A7

A4 A5 A6

A3

A2

A1

A0

A8/AP

DQS0

DQS3

DQS1 DQS2

DM0

A9 A10 A11

DM1 DM2 DM3

BA0 BA1

CLK

CKE

CLK*

CS* RAS*

WE*

CAS*

(1 OF 2)

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

violation

due to MCO

C6367 removed

NC

NC NC NC

NC NC NC NC NC

NC

NC NC

NC

BOM options provided by this page:

Signal aliases required by this page:

Page Notes

Power aliases required by this page:

(NONE)

- =PP1V8_FB_VDDQ

- =PP1V8_FB_VDD

DIFFERENTIAL_PAIR

PHYSICAL

NET_TYPE

SPACING

ELECTRICAL_CONSTRAINT_SET

ECSETs provided by GPU

300MHZ-BGA-LF

SDRAM_GDDR-2MX32X4

K4D553235F

CRITICAL

OMIT

L3

M10

L9

M2

N3

M4

M3

L13

L12

H11

H4

C11

C4

M13

B13

H2

H13

B2

K12

K13

E2

D2

D3

C2

B8

C9

B5

B9

B10

C13

D12

D13

E13

K3

K2

J2

J3

B6

G2

G3

F2

F3

F12

F13

G12

G13

J12

J13

C6

B7

B12

H3

H12

B3

N2

M12

M11

N12

L2

M5

N4

M8

N11

N10

N9

M9

N8

N7

M6

M7

L6

N6

N5

U6300

402

MF-LF

1/16W

5%

1K

2

1

R6340

402

MF-LF

1/16W

5%

1K

2

1

R6341

10uF

20% 4V X5R 603

2

1

C6300

402

X5R

16V

10%

0.1uF

2

1

C6303

10uF

20% 4V X5R 603

2

1

C6310

10uF

20% 4V X5R 603

2

1

C6311

0.1uF

10% 16V X5R 402

2

1

C6302

402

X5R

16V

10%

0.1uF

2

1

C6304

0.1uF

10% 16V X5R 402

2

1

C6301

0.1uF

10% 16V X5R 402

2

1

C6312

402

X5R

16V

10%

0.1uF

2

1

C6313

0.1uF

10% 16V X5R 402

2

1

C6314

402

X5R

16V

10%

0.1uF

2

1

C6315

0.1uF

10% 16V X5R 402

2

1

C6316

402

X5R

16V

10%

0.1uF

2

1

C6317

0.1uF

10% 16V X5R 402

2

1

C6318

402

X5R

16V

10%

0.1uF

2

1

C6319

0.1uF

10% 16V X5R 402

2

1

C6320

402

X5R

16V

10%

0.1uF

2

1

C6321

0.1uF

10% 16V X5R 402

2

1

C6354

0.1uF

10% 16V X5R 402

2

1

C6353

0.1uF

10% 16V X5R 402

2

1

C6363

402

X5R

16V

10%

0.1uF

2

1

C6352

402

X5R

16V

10%

0.1uF

2

1

C6351

402

X5R

16V

10%

0.1uF

2

1

C6362

402

X5R

16V

10%

0.1uF

2

1

C6366

603

X5R

4V

20%

10uF

2

1

C6361

0.1uF

10% 16V X5R 402

2

1

C6365

603

X5R

4V

20%

10uF

2

1

C6350

402

X5R

16V

10%

0.1uF

2

1

C6364

603

X5R

4V

20%

10uF

2

1

C6360

K4D553235F

300MHZ-BGA-LF

SDRAM_GDDR-2MX32X4

CRITICAL

OMIT

E9

E6

D11

D10

D9

D6

D5

D4

K10

K5

J10

J5

H10

H5

G10

G5

F10

F5

B11

B4

H7

H6

G9

G8

G7

G6

F9

F8

J9

J8

J7

J6

H9

H8

F7

F6

L10

L5

K9

K8

K7

K6

E10

E8

E7

E5

N13

F11

F4

E12

E3

C12

C10

C8

C7

K11

K4

J11

J4

G11

G4

C5

C3

L11

L8

L7

L4

E11

E4

D8

D7

U6350

0.1uF

10% 16V X5R 402

2

1

C6371

0.1uF

10% 16V X5R 402

2

1

C6391

1K

5% 1/16W MF-LF 402

2

1

R6390

1K

5% 1/16W MF-LF 402

2

1

R6391

402

X5R

16V

10%

0.1uF

2

1

C6370

0.1uF

10% 16V X5R 402

2

1

C6369

SDRAM_GDDR-2MX32X4

300MHZ-BGA-LF

K4D553235F

CRITICAL

OMIT

E9

E6

D11

D10

D9

D6

D5

D4

K10

K5

J10

J5

H10

H5

G10

G5

F10

F5

B11

B4

H7

H6

G9

G8

G7

G6

F9

F8

J9

J8

J7

J6

H9

H8

F7

F6

L10

L5

K9

K8

K7

K6

E10

E8

E7

E5

N13

F11

F4

E12

E3

C12

C10

C8

C7

K11

K4

J11

J4

G11

G4

C5

C3

L11

L8

L7

L4

E11

E4

D8

D7

U6300

K4D553235F

SDRAM_GDDR-2MX32X4

300MHZ-BGA-LF

CRITICAL

OMIT

L3

M10

L9

M2

N3

M4

M3

L13

L12

H11

H4

C11

C4

M13

B13

H2

H13

B2

K12

K13

E2

D2

D3

C2

B8

C9

B5

B9

B10

C13

D12

D13

E13

K3

K2

J2

J3

B6

G2

G3

F2

F3

F12

F13

G12

G13

J12

J13

C6

B7

B12

H3

H12

B3

N2

M12

M11

N12

L2

M5

N4

M8

N11

N10

N9

M9

N8

N7

M6

M7

L6

N6

N5

U6350

402

X5R

16V

10%

0.1uF

2

1

C6368

56

5% 1/16W MF-LF

402

2

1

R6396

402

MF-LF

1/16W

5%

56

2

1

R6395

402

CERM

470pF

10% 50V

2

1

C6395

56

5% 1/16W MF-LF

402

2

1

R6346

402

MF-LF

1/16W

5%

56

2

1

R6345

402

CERM

470pF

10% 50V

2

1

C6345

I243

I244

I245

I246

I247

I248

I249 I250

I251

I252

I253

I254

I255 I256

402

X5R

16V

10%

0.1uF

2

1

C6341

SYNC_MASTER=N/A

SYNC_DATE=N/A

051-6929

C

115

63

GPU Frame Buffer B

FB_B_WE_L

RAM RAM

FB_B_DQS<7..0>

RAMRAM

FB_B_DQM<7..0>

RAM RAM

FB_B_DQ<63..0>

RAMRAM

FB_B_CS_L

RAMRAM

FB_B_RAS_L

RAM RAM

FB_B_CAS_L

RAM RAM

FB_B_BA<1..0>

RAM RAM

FB_B_ADDR<11..0>

RAM RAM

FB_B_CLK_0

FB_B_CLKDDR_0_N

RAM_DIFF RAM_DIFF

FB_B_CLKDDR_1_P

FB_B_CLK_1

RAM_DIFF RAM_DIFF

FB_B_CKE

RAM RAM

FB_B_CLKDDR_1_N

FB_B_CLK_1

RAM_DIFF RAM_DIFF

FB_B_CLK_0

FB_B_CLKDDR_0_P

RAM_DIFF RAM_DIFF

FB_B_DQ<45> FB_B_DQ<44> FB_B_DQ<46>

FB_B_DQ<41> FB_B_DQ<42> FB_B_DQ<43> FB_B_DQ<47>

FB_B_DQ<39> FB_B_DQ<63> FB_B_DQ<60> FB_B_DQ<62> FB_B_DQ<61> FB_B_DQ<56> FB_B_DQ<58> FB_B_DQ<59> FB_B_DQ<57> FB_B_DQ<40>

FB_B_DQ<35> FB_B_DQ<33> FB_B_DQ<34> FB_B_DQ<36> FB_B_DQ<37> FB_B_DQ<38>

FB_B_DQ<52> FB_B_DQ<49> FB_B_DQ<50> FB_B_DQ<32>

FB_B_DQ<54> FB_B_DQ<48>

FB_B_DQ<51> FB_B_DQ<53> FB_B_DQ<55>

FB_B_DQS<5>

FB_B_DQS<7>

FB_B_DQS<4>

FB_B_ADDR<11>

FB_B_ADDR<10>

FB_B_ADDR<9>

FB_B_ADDR<8>

FB_B_DQM<5>

FB_B_DQM<7>

FB_B_DQM<4>

FB_B_DQS<6>

FB_B_DQM<6>

FB_B_BA<1>

FB_B_BA<0>

FB_B_ADDR<7>

FB_B_ADDR<6>

FB_B_ADDR<5>

FB_B_ADDR<4>

FB_B_ADDR<3>

FB_B_ADDR<2>

FB_B_ADDR<1>

FB_B_ADDR<0>

FB_B_DQ<16>

FB_B_DQ<18>

FB_B_DQ<17>

FB_B_DQ<19>

FB_B_DQ<22>

FB_B_DQ<21>

FB_B_DQ<20>

FB_B_DQ<23>

FB_B_DQ<15>

FB_B_DQ<14>

FB_B_DQ<9>

FB_B_DQ<13>

FB_B_DQ<8>

FB_B_DQ<11>

FB_B_DQ<10>

FB_B_DQ<12>

FB_B_DQ<6>

FB_B_DQ<7>

FB_B_DQ<0>

FB_B_DQ<5>

FB_B_DQ<4>

FB_B_DQ<3>

FB_B_DQ<2>

FB_B_DQ<1>

FB_B_DQ<27>

FB_B_DQ<28>

FB_B_DQ<25>

FB_B_DQ<30>

FB_B_DQ<26>

FB_B_DQ<24> FB_B_DQ<29>

FB_B_DQ<31>

FB_B_DQS<2>

FB_B_DQS<1>

FB_B_DQS<0>

FB_B_ADDR<11>

FB_B_ADDR<10>

FB_B_ADDR<9>

FB_B_ADDR<8>

FB_B_DQM<2>

FB_B_DQM<1>

FB_B_DQM<0>

FB_B_DQS<3>

FB_B_DQM<3>

FB_B_BA<1>

FB_B_BA<0>

FB_B_ADDR<7>

FB_B_ADDR<6>

FB_B_ADDR<5>

FB_B_ADDR<4>

FB_B_ADDR<3>

FB_B_ADDR<2>

FB_B_ADDR<1>

FB_B_ADDR<0>

=PP1V8_FB_VDDQ

FB_D1_VREF

=PP1V8_FB_VDD=PP1V8_FB_VDD

=PP1V8_FB_VDDQ

FB_D0_VREF

FB_B_WE_L

FB_B_RAS_L FB_B_CAS_L

FB_B_CS_L

FB_B_CKE

FB_B_CLKDDR_0_N

FB_B_CLKDDR_0_P

FB_B_DDRCLK_0_RC

FB_B_CKE FB_B_CS_L

FB_B_CAS_L

FB_B_RAS_L

FB_B_WE_L

FB_B_CLKDDR_1_N

FB_B_CLKDDR_1_P

FB_B_DDRCLK_1_RC

50

50 50

50

49

49 49

49

50

48

10

10 10

10

48

CONT

NOISE

VIN

VOUT

GND

GPIO_15

GPIO_14

GPIO_13

DMINUS

DDC1CLK

DDC1DATA

DDC2CLK

DDC3CLK

DDC3DATA

DPLUS

GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 GPIO_6 GPIO_7 GPIO_8 GPIO_9 GPIO_10 GPIO_11 GPIO_12

GPIO_16

HPD1

LPVSS

LVSSR_0 LVSSR_1 LVSSR_2 LVSSR_3

MPVSS

PLLTEST

RSTB_MSK

SSIN

VREFG

XTALIN

MPVDD

PVDD PVSS

XTALOUT

DDC2DATA

TESTEN

ROMCS*

(2 OF 8)

MULTI-FUNCTION GENERAL PURPOSE I/O

TEST

LVDS PLL

AND I/O

GND

BUS POWER MGMT

EXTERNAL SSC

ROM

MONITOR

INTERFACE

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

PAGE INDICATED BY CREF

PROPERTIES PROVIDED BY

NC

MEMORY PLL - 1.8V

(150mA MAX)

NC

(20mA)

(21mA)

GPU PLL - 1.8V

NC

- =I2C_GPU_TMDS_SDA - I2C data line for

Page Notes

Power aliases required by this page:

Signal aliases required by this page:

- =PP1V8_GPU_LVDS_PLL

- =PP2V5_PVDD

- =PP3V3_GPU_GPIOS

BOM options provided by this page:

- =I2C_GPU_TMDS_SCL - I2C clock line for external TMDS transmitters

external TMDS transmitters

(NONE)

402

MF-LF

1/16W

5%

1K

21

R6499

5% 1/16W MF-LF

402

10K

NO STUFF

2

1

R6470

0

5% MF-LF

402

1/16W

2

1

R6400

10UF

20% X5R

603

6.3V

2

1

C6402

5%

0

402

1/16W MF-LF

21

R6490

20%

0.01uF

402

CERM

16V

2

1

C6401

CRITICAL

SOT-25A-LF

MM1571J

51 4

2

3

U6400

603

CERM

10V

20%

1uF

2

1

C6400

1%

402

MF-LF

1/16W

1K

2

1

R6420

0.01uF

20% 16V CERM 402

2

1

C6411

0.1uF

10% 16V X5R 402

2

1

C6421

603

X5R

6.3V

20%

10UF

2

1

C6410

0402

FERR-220-OHM

21

L6410

402

CERM

16V

20%

0.01uF

2

1

C6405

0.1uF

20% 10V CERM 402

2

1

C6404

X5R

6.3V

20%

10UF

603

2

1

C6403

FERR-220-OHM

0402

21

L6403

1%

402

MF-LF

1/16W

1K

2

1

R6421

NO STUFF

402

MF-LF

1/16W

5%

10K

2

1

R6462

NO STUFF

10K

5% 1/16W MF-LF 402

2

1

R6460

NO STUFF

402

MF-LF

1/16W

5%

10K

2

1

R6458

1/16W

10K

5% MF-LF

402

NO STUFF

2

1

R6456

NO STUFF

402

MF-LF

1/16W

5%

10K

2

1

R6454

NO STUFF

5% 1/16W

10K

MF-LF 402

2

1

R6463

NO STUFF

5% 1/16W

402

MF-LF

10K

2

1

R6461

NO STUFF

1/16W MF-LF 402

5%

10K

2

1

R6459

5%

10K

1/16W MF-LF 402

NO STUFF

2

1

R6457

10K

5% 1/16W MF-LF 402

NO STUFF

2

1

R6455

402

MF-LF

1/16W

5%

10K

2

1

R6452

10K

5% 1/16W MF-LF 402

2

1

R6450

10K

5% 1/16W MF-LF 402

NO STUFF

2

1

R6453

402

MF-LF

5% 1/16W

10K

NO STUFF

2

1

R6451

OMIT

CRITICAL

M11P

BGA

AJ29

AH28

AG4

AH27

AK25

AG29

AF5

AJ28

AK28

AE25

A6

A7

AF20

AF15

AE19

AE16

AJ19

AF12

AJ2

AH3

AK3

AJ3

AF4

AH4

AK4

AJ4

AF2

AF3

AG2

AG1

AG3

AH1

AH2

AH5

AJ5

AF11 AE11

AG24 AG23

AE14 AE13

AF25 AF24

U5700

402

MF-LF

1/16W

5%

1K

21

R6498

VRAM_HYNIX

402

MF-LF

1/16W

5%

10K

2

1

R6422

VRAM_SAMSUNG

402

MF-LF

5% 1/16W

10K

2

1

R6423

GPU (M11) GPIOs/Straps

64

115

C

051-6929

SYNC_MASTER=N/A

SYNC_DATE=N/A

HPD_PWR_SNS_EN

ATI_MEMTYPE

TP_ATI_GPIO9 TP_ATI_GPIO10 TP_ATI_GPIO11 TP_ATI_GPIO12

ATI_CLK27M_SS

TP_EXTTMDS_RESET_L TP_ATI_GPIO8

=I2C_GPU_TMDS_SDA =I2C_GPU_TMDS_SCL

=PP1V8_GPU_LVDS_PLL

ATI_PVDD_BYP

1_8V_PVDD_STD

GPUPVDD_EN

ATI_CLK27M

GPU_DVI_DDC_DATA GPU_DVI_DDC_CLK

GPU_TESTEN

LVDS_DDC_DATA

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

VOLTAGE=1.8V

PP1V8_GPU_PLL

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

VOLTAGE=1.8V

PP1V8_GPU_MEMPLL

GPU_RSTB_MSK

GPU_DVI_HPD

ATI_BUS_CFG<2>

ATI_BUS_CFG<1>

ATI_BUS_CFG<0>

ATI_X1CLK_SKEW<1>

ATI_X1CLK_SKEW<0>

ATI_AGP_FBSKEW<1>

LVDS_DDC_CLK

GPU_SSIN_PD

PP3V3_GPU_VDDR3

GPU_VREFG

GPU_VCORE_HI_L

=PP3V3_GPU_GPIOS

ATI_AGP_FBSKEW<0>

=PP3V3_GPU_GPIOS

ATI_MEMTYPE

MAKE_BASE=TRUE

PP1V8_GPU_PVDD

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

VOLTAGE=1.8V

=PP2V5_GPU_PVDD

53

56

51

57

51

52

11

8

47

26

52

57

7

57

7

47

45

10

51

26

10

OE

GND

OUT

VCC

OSC

XIN/CLKIN

SSCLK

VSS

S0

S1

FRSEL

XOUT

VDD

SHDN* SET

IN

FAULT*

OUT2

OUT1

CC

GND

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

SPREAD SPECTRUM SUPPORT

Page Notes

- =PP3V3_GPU_PWRSEQ

DIFFERENTIAL_PAIR

(PLACE THE OSCILLATOR AND R6501/R6502

S0=1;S1=M => -1.5% DOWN-SPREAD

IS

LVDDR 2.8V LDO

27M OSC

- GPU_LVDDR_2V8

NC

CLOSE TO M18 IC)

(PLACE R6500 CLOSE TO OSC)

- =PP2V5_GPU_PWRSEQ

- =PP1V8_GPU_PWRSEQ

- =PP1V5_GPU_PWRSEQ

BOM options provided by this page:

Signal aliases required by this page:

Power aliases required by this page:

- GPU_SS

(NONE)

- =PPVIN_GPU_LVDDR_LDO

- =PP2V5_GPU_LVDDR_LDO

- =PP3V3_GPU_CLOCKS

PHYSICAL

NET_TYPE

SPACING

ELECTRICAL_CONSTRAINT_SET

M11 Power Shutdown Sequencing

402

MF-LF

1/16W

5%

100K

NO STUFF

2

1

R6503

27MHZ

SM

CRITICAL

14

81

7

G6500

GPU_SS

402

CERM

10V

20%

0.1uF

2

1

C6511

GPU_SS

10UF

20%

6.3V 603

X5R

2

1

C6510

CY25811

CRITICAL

GPU_SS

SOI-LF

8

1

2

7

5

3 4

6

U6510

0

5% 1/16W MF-LF 402

GPU_SS

2

1

R6513

0

5% 1/16W MF-LF 402

NO STUFF

2

1

R6514

402

1/16W

5%

0

NO STUFF

MF-LF

2

1

R6511

402

MF-LF

1/16W

5%

0

NO STUFF

2

1

R6512

FERR-EMI-100-OHM

SM

21

L6500

GPU_SS

FERR-EMI-100-OHM

SM

21

L6510

SM

21

XW6593

SOT-363

BAS16TW-X-F

61

DP6590

SOT-363

BAS16TW-X-F

52

DP6590

BAS16TW-X-F

SOT-363

43

DP6590

SM

21

XW6590

20%

805

CERM

6.3V

4.7uF

2

1

C6501

SM

21

XW6591

SM

21

XW6592

MAX8860EUA27+T

CRITICAL

GPU_LVDDR_2V8

UMAX1

7

5

4

1

2

3

8

6

U6530

GPU_LVDDR_2V8

2.2uF

20%

6.3V

CERM1

603

2

1

C6530

402

X7R

10V

20%

0.033uF

GPU_LVDDR_2V8

2

1

C6531

GPU_LVDDR_2V8

100K

5% 1/16W MF-LF 402

2

1

R6530

GPU_LVDDR_2V8

603

CERM1

6.3V

20%

2.2uF

2

1

C6532

402

GPU_SS

33

5% 1/16W MF-LF

21

R6510

0

5% 1/16W MF-LF

402

GPU_SS

21

R6500

I50

I51 I52

I54 I55

0.1uF

20% 10V

CERM

402

2

1

C6500

1/16W

402

MF-LF

1%

287

2

1

R6501

402

162

1% 1/16W MF-LF

2

1

R6502

Primary is 2.77V/Alt is 2.82V

GPU_LVDDR_2V8

U6530

353S1188 353S1140

GPU (M11) Clocks/Misc

051-6929

C

115

65

SYNC_MASTER=N/A

SYNC_DATE=N/A

ATI_CLK27M_SS_R

ATI_CLK27M_SS

CLOCK CLOCK

ATI_CLK27M_SSIN

=PPVIN_GPU_LVDDR_LDO

=PP3V3_GPU_CLOCKS

=PP3V3_GPU_PWRSEQ

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

VOLTAGE=3.3V

PP3V3_GPU_PSNECK

=PP1V8_GPU_PWRSEQ

=PP2V5_GPU_PWRSEQ

=PP1V5_GPU_PWRSEQ

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

VOLTAGE=2.5V

PP2V5_GPU_PSNECK

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

VOLTAGE=1.8V

PP1V8_GPU_PSNECK

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

VOLTAGE=1.5V

PP1V5_GPU_PSNECK

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

VOLTAGE=3.3V

PP3V3_GPU_OSC

ATI_CLK27M

ATI_OSC_OE

PP3V3_GPU_SS

VOLTAGE=3.3V MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

ATI_CLK27M_R

CY25811_S1 CY25811_S0

ATI_CLK27M_SSIN

ATI_CLK27M_SS

=PP2V8_GPU_LVDDR_LDO

ATI_CLK27M_SSIN

MAX8860_CC

MAX8860_FAULT_L

ATI_CLK27M_SS_R

ATI_CLK27M_SS

CLOCK CLOCK

ATI_CLK27M

CLOCKCLOCK

ATI_CLK27M_R

ATI_CLK27M

52

10

51

52

51

10

52

51

52

DVOVMODE

TXOUT_L0N

TXOUT_L2P

TXCLK_LP

TXVSSR2

TXVSSR1

TXVSSR0

ZV_LCDDATA_22

ZV_LCDDATA_21

ZV_LCDDATA_20

ZV_LCDDATA_19

ZV_LCDDATA_18

ZV_LCDDATA_17

ZV_LCDDATA_16

ZV_LCDDATA_15

ZV_LCDDATA_14

ZV_LCDDATA_13

ZV_LCDDATA_11

ZV_LCDDATA_10

ZV_LCDDATA_4

ZV_LCDDATA_3

ZV_LCDDATA_2

ZV_LCDDATA_1

ZV_LCDDATA_0

ZV_LCDCNTL_3

ZV_LCDCNTL_2

ZV_LCDCNTL_1

ZV_LCDCNTL_0

Y_G

VSYNC

VSS2DI

VSS1DI

VDD2DI

VDD1DI

V2SYNC

TXVDDR1 TXVDDR0

TXOUT_U3P TXOUT_U3N

TXOUT_U2P TXOUT_U2N

TXOUT_U1P TXOUT_U1N

TXOUT_U0P TXOUT_U0N

TXOUT_L3P TXOUT_L3N

TXOUT_L2N

TXOUT_L1P TXOUT_L1N

TXOUT_L0P

TXCP

TXCM

TXCLK_UP TXCLK_UN

TXCLK_LN

TX2P

TX2M

TX1P

TX1M

TX0P

TX0M

TPVSS

TPVDD

SSOUT

RSET

R

HSYNC

H2SYNC

G

DIGON

C_R

B

AVSSQ AVSSN

AVDD

AUXWIN

A2VSSQ

A2VSSN1

A2VSSN0

A2VDDQ

A2VDD1

ZV_LCDDATA_12

ZV_LCDDATA_9

ZV_LCDDATA_8

ZV_LCDDATA_7

ZV_LCDDATA_6

ZV_LCDDATA_5

A2VDD0

R2SET

ZV_LCDDATA_23

BLON

COMP_B

LVDS CHANNEL

CONTROL AND

EXTERNAL SSC

INTEGRATED TMDS

DAC2

DAC/CRT

(3 OF 8)

(TV/CRT2)

VIP HOST/ EXTERNAL TMDS

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

- DVO_1V8

- DVO_1V5

(NONE)

Signal aliases required by this page:

BOM options provided by this page:

- DVO_3V3

- GPU_VDDR4_3V3

- =PP3V3_GPU_GPIOS

- =PP1V8_GPU_AVDD

- =PP2V5_GPU_A2VDD

- =PP1V8_GPU_TPVDD

Power aliases required by this page:

Page Notes

ELECTRICAL_CONSTRAINT_SET

DIFFERENTIAL_PAIR

PHYSICAL

SPACING

NET_TYPE

(AVDD+VDDDI=75mA)

(140mA)

(2mA)

PROPERTIES PROVIDED BY PAGE INDICATED BY CREF

(PP1V8_GPU_AVDD)

(PP1V8_GPU_VDDDI)

(PP1V8_GPU_A2VDDQ)

(PP2V5_GPU_A2VDD)

NC

NC NC

NC

NC NC

NC

ECSETs provided by SI TMDS

0402

FERR-220-OHM

21

L6615

0402

FERR-220-OHM

21

L6625

0402

FERR-220-OHM

21

L6620

FERR-220-OHM

0402

21

L6600

402

CERM

20%

16V

0.01uF

2

1

C6601

CERM

6.3V

1uF

402

10%

2

1

C6600

I108

I109

I110

I111

I112

I113

I114 I115

I116

I117 I118

I119

I120

I121

I122

I123

I124

I125

I126

I127 I128

I129

I130

I131

I132

I133

I134

I135

I136

I137

I138 I139

I140

M11P

CRITICAL

OMIT

BGA

AJ9

AH9

AJ8

AH8

AJ7

AK7

AH7

AF10

AG10

AF9

AE9

AK6

AF8

AG8

AE8

AF7

AE7

AF6

AG6

AE6

AH10

AK9

AJ6

AH6

AH11

AJ11

AK10

AJ10

AJ22

AH25

AE21

AE23

AE22

AE24

AK24

AH12

AG14

AG13

AF14 AF13

AG20 AH20

AE18 AF18

AF17 AG17

AF16 AG16

AH19 AK19

AJ17 AH18

AJ16 AH17

AH16 AK16

AK13

AH13

AG19 AF19

AJ18 AK18

AK15

AJ15

AH15

AJ14

AH14

AJ13

AJ12

AK12

AJ25

AH26

AK21

AK27

AG25

AJ24

AJ27

AE10

AE12

AK22

AJ23

AG12

AJ26

AD24 AH23

AH24

AF26

AF23

AJ21

AH22

AF22

AH21

AG21

U5700

402

MF-LF

1/16W

5%

10K

DVO_3V3&GPU_VDDR4_3V3

2 1

R6641

10K

5%

1/16W

402

MF-LF

2

1

R6690

402

MF-LF

1/16W

5%

10K

2

1

R6642

10K

5% 1/16W MF-LF 402

DVO_1V5&DVO_1V8

2

1

R6640

402

MF-LF

1/16W

1%

75

2

1

R6672

75

MF-LF

402

1/16W

1%

2

1

R6671

75

1% 1/16W MF-LF 402

2

1

R6670

10K

5% 1/16W MF-LF

402

2

1

R6681

10K

5% 1/16W MF-LF

402

2

1

R6680

75

1% 1/16W MF-LF 402

2

1

R6662

1% 1/16W

402

MF-LF

75

2

1

R6661

75

1% 1/16W MF-LF 402

2

1

R6660

MF-LF 402

1/16W

1%

499

2

1

R6650

715

1% 1/16W MF-LF 402

2

1

R6651

0.01uF

402

CERM

20% 16V

2

1

C6622

402

CERM

16V

20%

0.01uF

2

1

C6621

10UF

603

X5R

20%

6.3V

2

1

C6620

0.01uF

20% 16V CERM 402

2

1

C6626

603

X5R

6.3V

20%

10UF

2

1

C6625

0.01uF

16V

20%

CERM 402

2

1

C6611

603

X5R

20%

10UF

6.3V

2

1

C6610

0.01uF

20% 16V CERM 402

2

1

C6607

20% CERM

402

0.1uF

10V

2

1

C6606

10V

20%

402

CERM

0.1uF

2

1

C6605

0402

FERR-220-OHM

21

L6610

402

CERM

16V

20%

0.01uF

2

1

C6617

402

CERM

16V

20%

0.01uF

2

1

C6616

603

6.3V X5R

20%

10UF

2

1

C6615

GPU (M11) DVI/DAC Outputs

051-6929

C

115

66

SYNC_MASTER=N/A

SYNC_DATE=N/A

LVDS_DATA

LVDS

LVDS_U0

LVDS

LVDS_U0_P

PP1V5R3V3_GPU_VDDR4

GPU_DVOD_R<20>

PP1V5R3V3_GPU_VDDR4

GPU_DVOD_R<23>

GPU_DVOD_R<5> GPU_DVOD_R<6> GPU_DVOD_R<7> GPU_DVOD_R<8> GPU_DVOD_R<9>

GPU_DVOD_R<12>

GPU_VGA_HSYNC

CLKLVDS_L_N

CLKLVDS_U_N

CLKLVDS_U_P

LVDS_L0_P

LVDS_L1_N

LVDS_L1_P

LVDS_L2_N

NO_TEST=YES

TP_LVDS_L3_N

NO_TEST=YES

TP_LVDS_L3_P

LVDS_U0_N

LVDS_U0_P

LVDS_U1_N

LVDS_U1_P

LVDS_U2_N

LVDS_U2_P

NO_TEST=YES

TP_LVDS_U3_N

NO_TEST=YES

TP_LVDS_U3_P

GPU_VGA_VSYNC

GPU_DVO_VSYNC_R GPU_DVO_HSYNC_R GPU_DVO_DE_R GPU_DVO_CLKP_R

GPU_DVOD_R<0> GPU_DVOD_R<1> GPU_DVOD_R<2> GPU_DVOD_R<3> GPU_DVOD_R<4>

GPU_DVOD_R<10> GPU_DVOD_R<11>

GPU_DVOD_R<13> GPU_DVOD_R<14> GPU_DVOD_R<15> GPU_DVOD_R<16> GPU_DVOD_R<17> GPU_DVOD_R<18> GPU_DVOD_R<19>

GPU_DVOD_R<21> GPU_DVOD_R<22>

CLKLVDS_L_P

LVDS_L2_P

LVDS_L0_N

ATI_R2SET

INV_ON_PWM PANEL_PWR_EN

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=2.5V

PP2V5_GPU_A2VDD

GPU_TV_COMP

GPU_TV_C

GPU_TV_Y

GPU_VGA_B

GPU_VGA_G

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

VOLTAGE=1.8V

PP1V8_GPU_VDDDI

GPU_VGA_R

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm

VOLTAGE=1.8V

PP1V8_GPU_A2VDDQ

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

VOLTAGE=1.8V

PP1V8_GPU_AVDD

VOLTAGE=1.8V

PP1V8_GPU_TPVDD

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

ATI_RSET

GPU_TV_C

TV TV

GPU_TV_Y

TV TV

GPU_TV_COMP

TV TV

TV_COMP

TV_CONN TV_CONN

TV_Y

TV_CONN TV_CONN

TV_C

TV_CONN TV_CONN

LVDS_CLK_LOWER

LVDS_LCLK

CLKLVDS_L_P

LVDS LVDS

LVDS_LCLK

CLKLVDS_L_N

LVDS LVDS

LVDS

LVDS_UCLK

LVDS

CLKLVDS_U_N

LVDS_CLK_UPPER

LVDS

LVDS_UCLK

LVDS

CLKLVDS_U_P

LVDS

LVDS_U2

LVDS

LVDS_U2_N

LVDS

LVDS_U0

LVDS

LVDS_U0_N

LVDS_DATA

LVDS

LVDS_U2

LVDS

LVDS_U2_P

LVDS

LVDS_U1

LVDS

LVDS_U1_N

LVDS_DATA

LVDS

LVDS_U1

LVDS

LVDS_U1_P

DVO DVO

GPU_DVOD_R<23..0>

DVO DVO

GPU_DVO_HSYNC_R

DVO DVO

GPU_DVO_CLKP_R

DVO DVO

GPU_DVO_DE_R

DVO DVO

GPU_DVO_VSYNC_R

LVDS_DATA

LVDSLVDS

LVDS_L1_P

LVDS_L1

LVDSLVDS

LVDS_L1_N

LVDS_L1

LVDS_DATA

LVDSLVDS

LVDS_L2_P

LVDS_L2

LVDSLVDS

LVDS_L0_N

LVDS_L0

LVDS_DATA

LVDSLVDS

LVDS_L0_P

LVDS_L0

LVDSLVDS

LVDS_L2_N

LVDS_L2

GPU_VGA_R

VGA VGA

GPU_VGA_G

VGA VGA

GPU_VGA_B

VGA VGA

VGA_B

VGA_CONN VGA_CONN

VGA_G

VGA_CONN VGA_CONN

VGA_R

VGA_CONN VGA_CONN

=PP1V8_GPU_AVDD

=PP1V8_GPU_TPVDD

=PP2V5_GPU_A2VDD

PP1V8_GPU_PANEL_IO

GPU_DVOVMODE

GPU_AUXWIN_PU

=PP3V3_GPU_GPIOS

GPU_AUXWIN_PU

56

53

56

53

56

53

6

53

57

53

6

53

57

51

7

47

6

47

6

57

7

57

6

2

6

7

56

53

57

7

2

6

7

53

57

10

47

53

10

53

EHTPLG D0

TXC+ TXC-

TX0+

D1

TX0-

EXT_SWING

TX2+

PGND

MSEN

TX1+ TX1-

TX2-

VREF

D2 D3

D5

D4

D7

D6

D8

D10

D9

DE

D11

HSYNC

IDCK+

VSYNC

IDCK-

AGND

GND

AGND

GND

PAD

VCC

AVCC

PVCC2

PVCC1

THRML

SCL

RST*

SDA CTL3/A1

SYNCO/SYNCI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

- =SI_TMDS_RESET_L

Lower DVO Termination

Place close to GPU

One each for: GPU_DVOD<0..11> GPU_DVO_HSYNC GPU_DVO_VSYNC GPU_DVO_DE GPU_DVO_CLKP

signaling. The power rail for the reference

The DVO bus can be run with 3.3V or 1.5V/1.8V

should be connected to the GPU DVO rail.

- TMDS_DUAL

- TMDS_EXT

- =SI_I2C_DATA

- =SI_I2C_CLK

- =PP3V3_RUN_SI

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

SPACING

PHYSICAL

DIFFERENTIAL_PAIR

NOTE: Target differential impedance for TMDS data pairs is 100 ohms.

Net Physical Type: TMDS

Net Spacing Type: TMDS

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

SPACING

PHYSICAL

DIFFERENTIAL_PAIR

Place C6726/C6727 at pin 28 Place C6728/C6729 at pin 46

TERMINATION NETWORK SHOULD BE CONNECTED AS SHOWN

EXTERNAL TMDS TERMINATION

Signal aliases required by this page:

Power aliases required by this page:

Page Notes

BOM options provided by this page:

SILICON IMAGE TMDS

- DVO_3V3

- =PP1V5R3V3_DVO_VREF

- =RP67xxPy (pinswappable series R)

- DVO_1V5

- DVO_1V8

TMDS_EXT&TMDS_DUAL

180-OHM-1.5A

0603

21

L6720

5%

402

CERM

50V

100pF

TMDS_EXT&TMDS_DUAL

2

1

C6722

50V

TMDS_EXT&TMDS_DUAL

100pF

CERM 402

5%

2

1

C6721

50V

TMDS_EXT&TMDS_DUAL

100pF

CERM 402

5%

2

1

C6729

50V

TMDS_EXT&TMDS_DUAL

100pF

CERM 402

5%

2

1

C6727

TMDS_EXT&TMDS_DUAL

5%

402

CERM

100pF

50V

2

1

C6725

TMDS_EXT&TMDS_DUAL

5%

402

CERM

100pF

50V

2

1

C6724

10%

805

10UF

TMDS_EXT&TMDS_DUAL

6.3V

X5R

2

1

C6723

6.3V

10UF

X5R 805

10%

TMDS_EXT&TMDS_DUAL

2

1

C6720

TMDS_EXT&TMDS_DUAL

180-OHM-1.5A

0603

21

L6723

TMDS_EXT&TMDS_DUAL

180-OHM-1.5A

0603

21

L6726

TMDS_EXT&TMDS_DUAL

10

SM-LF

5%

1/16W

41

RP6707

TMDS_EXT&TMDS_DUAL

10

SM-LF

5%

1/16W

32

RP6707

TMDS_EXT&TMDS_DUAL

10

SM-LF

5%

1/16W

41

RP6708

TMDS_EXT&TMDS_DUAL

10

SM-LF

5%

1/16W

32

RP6709

TMDS_EXT&TMDS_DUAL

10

SM-LF

5%

1/16W

32

RP6708

TMDS_EXT&TMDS_DUAL

1/16W

5%

SM-LF

10

32

RP6710

TMDS_EXT&TMDS_DUAL

10

SM-LF

5%

1/16W

41

RP6709

TMDS_EXT&TMDS_DUAL

10

SM-LF

5%

1/16W

41

RP6710

20%

402

CERM

0.1uF

10V

TMDS_EXT&TMDS_DUAL

2

1

C6740

1K

MF-LF 402

1% 1/16W

TMDS_EXT&TMDS_DUAL

2

1

R6740

1/16W

1%

402

MF-LF

1K

DVO_1V5&DVO_1V8

2

1

R6741

TMDS_EXT&TMDS_DUAL

1/16W

1%

402

MF-LF

49.9

21

R6761

TMDS_EXT&TMDS_DUAL

49.9

MF-LF

402

1%

1/16W

21

R6760

TMDS_EXT&TMDS_DUAL

10%

402

CERM

0.001uF

50V

2

1

C6760

TMDS_EXT&TMDS_DUAL

1/16W

1%

402

MF-LF

49.9

21

R6763

TMDS_EXT&TMDS_DUAL

50V

0.001uF

CERM

402

10%

2

1

C6762

TMDS_DN<1>

TMDS_EXT&TMDS_DUAL

49.9

MF-LF

402

1%

1/16W

21

R6765

TMDS_EXT&TMDS_DUAL

1/16W

1%

402

MF-LF

49.9

21

R6762

TMDS_EXT&TMDS_DUAL

49.9

MF-LF

402

1%

1/16W

21

R6764

TMDS_EXT&TMDS_DUAL

10%

402

CERM

0.001uF

50V

2

1

C6764

TMDS_EXT&TMDS_DUAL

1/16W

1%

402

MF-LF

49.9

21

R6767

TMDS_EXT&TMDS_DUAL

10%

402

CERM

0.001uF

50V

2

1

C6766

TMDS_EXT&TMDS_DUAL

49.9

MF-LF

402

1%

1/16W

21

R6766

6.3V

TMDS_EXT&TMDS_DUAL

10UF

X5R 805

10%

2

1

C6728

1/16W

402

MF-LF

TMDS_EXT&TMDS_DUAL

1%

301

2

1

R6752

1/16W

1%

402

MF-LF

4.99K

NO STUFF

2

1

R6754

10

SM-LF

5%

1/16W

TMDS_EXT&TMDS_DUAL

81

RP6720

10

SM-LF

5%

1/16W

TMDS_EXT&TMDS_DUAL

72

RP6720

10

SM-LF

5%

1/16W

TMDS_EXT&TMDS_DUAL

63

RP6720

1/16W

5%

SM-LF

10

TMDS_EXT&TMDS_DUAL

54

RP6720

10

5% 1/16W SM-LF

TMDS_EXT&TMDS_DUAL

81

RP6721

1/16W

5%

10

SM-LF

TMDS_EXT&TMDS_DUAL

72

RP6721

10

5% 1/16W SM-LF

TMDS_EXT&TMDS_DUAL

63

RP6721

1/16W

5%

10

SM-LF

TMDS_EXT&TMDS_DUAL

54

RP6721

10

5% 1/16W SM-LF

TMDS_EXT&TMDS_DUAL

81

RP6722

10

5% 1/16W SM-LF

TMDS_EXT&TMDS_DUAL

72

RP6722

10

5% 1/16W SM-LF

TMDS_EXT&TMDS_DUAL

63

RP6722

1/16W

5%

10

SM-LF

TMDS_EXT&TMDS_DUAL

54

RP6722

1/16W

5%

SM-LF

10

TMDS_EXT&TMDS_DUAL

81

RP6723

1/16W

5%

SM-LF

10

TMDS_EXT&TMDS_DUAL

72

RP6723

1/16W

5%

10

SM-LF

TMDS_EXT&TMDS_DUAL

63

RP6723

1/16W

5%

10

SM-LF

TMDS_EXT&TMDS_DUAL

54

RP6723

NO STUFF

100K

MF-LF

402

5%

1/16W

2

1

R6732

1/16W

5%

402

MF-LF

10K

TMDS_EXT&TMDS_DUAL

2

1

R6731

TMDS_EXT&TMDS_DUAL

1/16W

5%

402

MF-LF

10K

2

1

R6730

I306

I309

I310

I311

I312

TSSOP

CRITICAL

SIL1178CS48

TMDS_EXT&TMDS_DUAL

21

2

22

3

32

33

41

42

38

39

35

36

49

47

26

27

25

46

28

45

29

48

11

12

20

1234

30

44

19

7

8

9

10

13

14

15

16

5

6

17

18

24

40

34

314337

U6700

10% X5R

10UF

TMDS_EXT&TMDS_DUAL

6.3V

805

2

1

C6726

I316

I317

I318

I319

I320

I321

I322

I323

I329

I330

I331

I332

I333

I334

I335

I336

0

5% 1/16W MF-LF

402

DVO_1V5&DVO_1V8

2 1

R6742

DVO_3V3

1K

MF-LF

402

5%

1/16W

2

1

R6733

TMDS_EXT&TMDS_DUAL

10K

MF-LF

402

5%

1/16W

2

1

R6734

051-6929

115

67

C

SYNC_DATE=N/A

SYNC_MASTER=N/A

Lower TMDS Transmitter

SI_IDCK_N

EXT_TMDS_D1_CMF

TMDS_CLKN

TMDS_DN<2>

TMDS_DN<0>

TMDS_DP<2>

EXT_TMDS_D2_CMF

EXT_TMDS_D0_CMF

EXT_TMDS_CLK_CMF

SI_TMDS_DP<2>

TMDS_DP<2>

SI_HTPLG

SI_M_A1

SI_M_EXTSWING

SI_M_MSEN

=PP3V3_RUN_SI

SI_TMDS_DN<2>

TMDS_DN<2>

SI_TMDS_DP<1>

TMDS_DP<1>

SI_TMDS_DN<1>

TMDS_DN<1>

GPU_DVO_VSYNC GPU_DVO_CLKP

GPU_DVO_HSYNC

GPU_DVOD<11> GPU_DVO_DE

GPU_DVOD<9> GPU_DVOD<10>

GPU_DVOD<8>

GPU_DVOD<6> GPU_DVOD<7>

GPU_DVOD<4> GPU_DVOD<5>

GPU_DVOD<3>

GPU_DVOD<2>

GPU_DVOD<1>

GPU_DVOD<0>

SI_SYNC

=PP3V3_RUN_SI

SI_VREF

TMDS_DP<1>

TMDS_CLKP

TMDS_DP<0>

=RP6722P1

=RP6721P4

=RP6721P3

=RP6722P8

=RP6721P5

=RP6721P6

=I2C_SI_M_SDA

=I2C_SI_M_SCL

TMDS_CLKN

SI_TMDS_CLKN

TMDS_DN<0>

SI_TMDS_DN<0>

TMDS_CLKP

SI_TMDS_CLKP

TMDS_DP<0>

SI_TMDS_DP<0>

SI_TMDS_DN<2>

SI_TMDS_DN<1>

SI_TMDS_DP<1>

SI_TMDS_DP<2>

SI_TMDS_DN<0>

SI_TMDS_DP<0>

SI_TMDS_CLKN

SI_TMDS_CLKP

TMDSTMDS

TMDS_CLKP

TMDS_CLK

TMDSTMDS

TMDS_DP<0>

TMDS_D0

TMDSTMDS

TMDS_CLKN

TMDS_CLK

TMDS TMDS

TMDS_DP<1>

TMDS_D1

TMDSTMDS

TMDS_DN<0>

TMDS_D0

TMDS TMDS

TMDS_DN<1>

TMDS_D1

TMDS TMDS

TMDS_DP<2>

TMDS_D2

TMDS TMDS

TMDS_DN<2>

TMDS_D2

GPU_DVOD<0..11>

GPU_DVO_LOWER

DVODVO

GPU_DVO_HSYNC

DVODVO

GPU_DVO_BOTH

GPU_DVO_DE

GPU_DVO_BOTH

DVODVO

GPU_DVO_VSYNC

GPU_DVO_BOTH

DVODVO

GPU_DVO_CLKP

DVODVO

TMDS_CLK

SI_TMDS_CLK

TMDSTMDS

SI_TMDS_CLKP

SI_TMDS_CLK

TMDSTMDS

SI_TMDS_CLKN

TMDS_DATA

SI_TMDS_DP<0>

SI_TMDS_D0

TMDSTMDS

SI_TMDS_DN<0>

SI_TMDS_D0

TMDSTMDS

TMDS_DATA

SI_TMDS_DP<1>

SI_TMDS_D1

TMDS TMDS

SI_TMDS_DN<1>

SI_TMDS_D1

TMDS TMDS

TMDS_DATA

SI_TMDS_DP<2>

SI_TMDS_D2

TMDS TMDS

SI_TMDS_DN<2>

SI_TMDS_D2

TMDS TMDS

SI_IDCK_N

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

SI_VREF

=PP1V5R3V3_DVO_VREF

=RP6720P2

=RP6720P4

=RP6721P2

=RP6720P1

=RP6720P3

=RP6721P1

=RP6720P8

=RP6720P7

=RP6720P6

=RP6720P5

=RP6721P8

=RP6721P7

=RP6722P3 =RP6722P6

=RP6723P1 =RP6723P8

=RP6723P3 =RP6723P6

=RP6722P2 =RP6722P7

=RP6722P4 =RP6722P5

=RP6723P2 =RP6723P7

=RP6723P4 =RP6723P5

=SI_TMDS_RESET_L

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.38 mm

MIN_NECK_WIDTH=0.2 mm

PP3V3_SI_M_VCC

MIN_LINE_WIDTH=0.38 mm VOLTAGE=3.3V

PP3V3_SI_M_PVCC

MIN_NECK_WIDTH=0.2 mm

PP3V3_SI_M_AVCC

MIN_LINE_WIDTH=0.38 mm VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

=PP3V3_RUN_SI

55

57

55

57

54

54 57

57

54 57

54

55

57

57 54

57

54

54 57

57

54

55

54

54 54

55

10

2

54

54 54

2

54

6

55

10

54

6

8

54 54

54

2

54

2

54 54

2

54

2

54

2

54

6

2

54

2

54

2

54

2

54

47

6

6 6

11

10

EHTPLG D0

TXC+ TXC-

TX0+

D1

TX0-

EXT_SWING

TX2+

PGND

MSEN

TX1+ TX1-

TX2-

VREF

D2 D3

D5

D4

D7

D6

D8

D10

D9

DE

D11

HSYNC

IDCK+

VSYNC

IDCK-

AGND

GND

AGND

GND

PAD

VCC

AVCC

PVCC2

PVCC1

THRML

SCL

RST*

SDA CTL3/A1

SYNCO/SYNCI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NC

Signal aliases required by this page:

Power aliases required by this page:

Page Notes

Upper Channel Series Termination

Upper Channel Common-mode Termination

BOM options provided by this page:

Place C6836/C6837 at pin 28.

Place C6838/C6839 at pin 46.

Net Spacing Type: TMDS Net Physical Type: TMDS

NOTE: Target differential impedance for TMDS data pairs is 100 ohms.

DIFFERENTIAL_PAIR

PHYSICAL

NET_TYPE

SPACING

ELECTRICAL_CONSTRAINT_SET

PROVIDED BY LOWER TXMR

PROVIDED BY LOWER TXMR PROVIDED BY LOWER TXMR

- =PP3V3_RUN_SI

- TMDS_DUAL

- =SI_I2C_CLK

- =SI_I2C_DATA

- =RP68xxPy (pinswappable series R)

- =SI_TMDS_RESET_L

One for each of: GPU_DVOD<12..23>

Place close to GPU

Upper DVO series termination

5%

402

CERM

100pF

TMDS_DUAL

50V

2

1

C6839

50V

TMDS_DUAL

100pF

CERM 402

5%

2

1

C6837

1%

301

1/16W

402

MF-LF

TMDS_DUAL

2

1

R6881

6.3V

TMDS_DUAL

10UF

X5R 805

10%

2

1

C6836

TMDS_DUAL

180-OHM-1.5A

0603

21

L6830

10%

805

X5R

10UF

TMDS_DUAL

6.3V

2

1

C6833

10K

MF-LF

402

5%

1/16W

TMDS_DUAL

2

1

R6880

TMDS_DUAL

10

SM-LF

5%

1/16W

41

RP6811

1/16W

5%

SM-LF

10

TMDS_DUAL

32

RP6812

TMDS_DUAL

1/16W SM-LF

10

5%

32

RP6811

TMDS_DUAL

1/16W SM-LF

10

5%

32

RP6813

TMDS_DUAL

1/16W

5%

SM-LF

10

41

RP6812

TMDS_DUAL

10

SM-LF

5%

1/16W

41

RP6813

50V

TMDS_DUAL

100pF

CERM 402

5%

2

1

C6832

TMDS_DUAL

49.9

MF-LF

402

1%

1/16W

21

R6805

TMDS_DUAL

1/16W

1%

402

MF-LF

49.9

21

R6803

TMDS_DUAL

10%

402

CERM

0.001uF

50V

2

1

C6804

TMDS_DUAL

1/16W

1%

402

MF-LF

49.9

21

R6804

TMDS_DUAL

1/16W

1%

402

MF-LF

49.9

21

R6802

TMDS_DUAL

1/16W

1%

402

MF-LF

49.9

21

R6801

TMDS_DUAL

10%

402

CERM

0.001uF

50V

2

1

C6802

TMDS_DUAL

10%

402

CERM

0.001uF

50V

2

1

C6800

50V

TMDS_DUAL

100pF

CERM 402

5%

2

1

C6831

TMDS_DUAL

1/16W

1%

402

MF-LF

49.9

21

R6800

SM-LF

TMDS_DUAL

1/16W

5%

10

81

RP6821

SM-LF

TMDS_DUAL

1/16W

5%

10

72

RP6821

TMDS_DUAL

1/16W

5%

SM-LF

10

63

RP6821

TMDS_DUAL

1/16W

5%

SM-LF

10

54

RP6821

SM-LF

TMDS_DUAL

1/16W

5%

10

72

RP6822

SM-LF

TMDS_DUAL

1/16W

5%

10

81

RP6822

SM-LF

TMDS_DUAL

1/16W

5%

10

54

RP6822

SM-LF

TMDS_DUAL

1/16W

5%

10

63

RP6822

6.3V

TMDS_DUAL

10UF

X5R 805

10%

2

1

C6830

SM-LF

TMDS_DUAL

1/16W

5%

10

81

RP6823

SM-LF

TMDS_DUAL

1/16W

5%

10

72

RP6823

SM-LF

TMDS_DUAL

1/16W

5%

10

63

RP6823

SM-LF

1/16W

5%

10

TMDS_DUAL

54

RP6823

I54

I55

I56

I58

I59

TMDS_DUAL

180-OHM-1.5A

0603

21

L6833

I60

NO STUFF

4.99K

MF-LF 402

1% 1/16W

2

1

R6882

SIL1178CS48

TSSOP

TMDS_DUAL

CRITICAL

21

2

22

3

32

33

41

42

38

39

35

36

49

47

26

27

25

46

28

45

29

48

11

12

20

1234

30

44

19

7

8

9

10

13

14

15

16

5

6

17

18

24

40

34

314337

U6800

TMDS_DUAL

180-OHM-1.5A

0603

21

L6836

6.3V

TMDS_DUAL

10UF

X5R 805

10%

2

1

C6838

I74

I75

I76

I77

I78

I79

5%

402

CERM

100pF

TMDS_DUAL

50V

2

1

C6835

I80

I81

I82

I83

I84

I85

5%

402

CERM

100pF

TMDS_DUAL

50V

2

1

C6834

Upper TMDS Transmitter

C

051-6929

68

115

SYNC_MASTER=N/A

SYNC_DATE=N/A

=RP6823P6

=RP6823P5

=RP6823P8

=RP6823P7

=RP6822P6

=RP6822P5

=RP6822P8

=RP6822P7

=RP6821P6

=RP6821P5

=RP6821P7

=RP6821P8

=RP6823P3

=RP6823P4

=RP6823P1

=RP6823P2

=RP6822P3

=RP6822P4

=RP6822P1

=RP6822P2

=RP6821P3

=RP6821P4

=RP6821P2

=RP6821P1

TMDS TMDS

TMDS_D5

TMDS_DN<5>

TMDS TMDS

TMDS_D4

TMDS_DN<4>

TMDS TMDS

TMDS_D5

TMDS_DP<5>

TMDS TMDS

TMDS_D4

TMDS_DP<4>

TMDSTMDS

TMDS_D3

TMDS_DN<3>

TMDSTMDS

TMDS_D3

TMDS_DP<3>

TMDSTMDS

SI_TMDS_DN<5>

SI_TMDS_D5

TMDS_DATA

TMDSTMDS

SI_TMDS_DP<5>

SI_TMDS_D5

TMDSTMDS

SI_TMDS_DN<4>

SI_TMDS_D4

TMDS_DATA

TMDSTMDS

SI_TMDS_DP<4>

SI_TMDS_D4

TMDS TMDS

SI_TMDS_DN<3>

SI_TMDS_D3

TMDS_DATA

TMDS TMDS

SI_TMDS_DP<3>

SI_TMDS_D3

GPU_DVO_CLKP

GPU_DVO_DE

GPU_DVO_VSYNC

DVODVO

GPU_DVOD<21..23>

GPU_DVO_UPPER

GPU_DVOD20

GPU_DVOD<20>

DVO DVO

DVO

GPU_DVO_UPPER

GPU_DVOD<12..19>

DVO

SI_SYNC

MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

PP3V3_SI_S_AVCC MIN_LINE_WIDTH=0.38 mm

=SI_TMDS_RESET_L

TMDS_DP<5>

TMDS_DP<4>

TMDS_DP<3>

SI_TMDS_DP<5>

TMDS_DP<5>

=PP3V3_RUN_SI

SI_S_MSEN

SI_S_EXTSWING

TMDS_DN<5>

TMDS_DP<4>

TMDS_DN<4>

TMDS_DP<3>

TMDS_DN<3>

SI_TMDS_DN<5>

SI_TMDS_DN<4>

SI_TMDS_DN<3>

SI_TMDS_DP<3>

SI_TMDS_DP<4>

GPU_DVO_DE GPU_DVO_HSYNC

GPU_DVO_CLKP

GPU_DVO_VSYNC

SI_IDCK_N

=I2C_SI_S_SCL =I2C_SI_S_SDA

SI_HTPLG

GPU_DVOD<12> GPU_DVOD<13> GPU_DVOD<14> GPU_DVOD<15> GPU_DVOD<16>

SI_S_A1

GPU_DVOD<17>

GPU_DVOD<19>

GPU_DVOD<18>

GPU_DVOD<20>

GPU_DVOD<22>

GPU_DVOD<21>

GPU_DVOD<23>

SI_TMDS_DP<3> SI_TMDS_DN<3>

SI_TMDS_DP<4> SI_TMDS_DN<4>

SI_TMDS_DP<5> SI_TMDS_DN<5>

SI_VREF

TMDS_DN<3>

TMDS_D3_CMF

TMDS_DN<4>

TMDS_DN<5>

TMDS_D4_CMF

TMDS_D5_CMF

=PP3V3_RUN_SI

MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

MIN_LINE_WIDTH=0.38 mm

PP3V3_SI_S_VCC

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=3.3V

PP3V3_SI_S_PVCC

MIN_LINE_WIDTH=0.38 mm

55

57

55

54

55

54

57

54

57

55

54

55

57

54

6

55

2

55

2

55

2

6

54

11

55

55 55

10

55

2

55

2

55

6

54

8

54

6

2

55

2

55

2

54

55

10

G2

D2

S2

G1

S1

D1

A

B

Y

G

D

S

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

INVERTER EXPECTS ACTIVE HIGH SIGNAL

LCD (LVDS) INTERFACE

100K pull-ups are for no-panel case (development) Panel has 2K pull-ups

INVERTER INTERFACE

NC

402

MF-LF

1/16W

5%

100K

2

1

R6950

0.001uF

20% 50V

CERM

402

2

1

C6954

0.001uF

20% 50V CERM 402

2

1

C6951

0.001uF

20% 50V CERM 402

2

1

C6952

603

X5R

6.3V

20%

10UF

2

1

C6950

FERR-1K-OHM-EMI

SM

12

L6952

400-OHM-EMI

SM-1

21

L6953

0.1uF

20% 10V

CERM

402

2

1

C6953

SC70-6-LF

FDG6324L

4

3 2

6

Q6950

SC70-6-LF

FDG6324L

1

5

6

Q6950

SM-2MT-LF

CRITICAL

4

3

2

1

6

5

J6950

400-OHM-EMI

SM-1

21

L6950

402

CERM

50V

20%

0.001uF

2

1

C6920

100K

5% 1/16W MF-LF

402

2

1

R6910

402

CERM

50V

20%

0.001uF

2

1

C6910

100K

5% 1/16W MF-LF 402

2

1

R6911

20% 50V

CERM

402

0.001uF

2 1

C6921

0.01uF

CERM

50V

20%

603

21

C6999

MF-LF

1/16W

5%

0

402

21

R6999

MSC-RB30-5-FA

F-RT-SM

CRITICAL

9

8

7

6

5

4

30

3

29

28

27

26

25

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

34

33

J6900

SC70-LF

NC7S32

4

5

3

2

1

U6953

402

CERM

50V

20%

0.001uF

NO STUFF

2

1

C6911

SM

FERR-250-OHM

2

1

L6955

CERM

50V

20%

0.001uF

402

2

1

C6955

402

CERM

50V

20%

0.001uF

2

1

C6901

SM

FERR-250-OHM

21

L6900

5%

50V

CERM

603

2200pF

21

C6900

402

MF-LF

1/16W

5%

100K

21

R6901

100K

5% 1/16W MF-LF

402

2

1

R6900

TSOP-LF

SI3443DV

4

3 6

5 2 1

Q6900

SOT23-LF

2N7002

2

1

3

Q6901

Internal Display Conns

SYNC_DATE=N/A

051-6929

C

115

69

SYNC_MASTER=N/A

BRIGHT_PWM

VOLTAGE=5V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

PP5V_INV_SW

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=0V

GND_INVERTER

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=12.8V MIN_NECK_WIDTH=0.25 mm

PPBUS_INVERTER

=GND_CHASSIS_INVERTER2

=GND_CHASSIS_INVERTER1

PP5V_INV_SW_F

VOLTAGE=5V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

PANEL_PWR_EN

FP_PWR_EN_L

=PP5V_PWRON_INVERTER

PP3V3_LCD_SW

VOLTAGE=3.3V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

LVDS_DDC_CLK

=PP3V3_DDC_LCD

LCD_PWREN_L

=PP3V3_PWRON_LCD

PP3V3_LCD_CONN

VOLTAGE=3.3V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

LVDS_DDC_DATA

LCD_DIGON_L

PANEL_PWR_EN

LVDS_L0_P

LVDS_L0_N

LVDS_U0_N

CLKLVDS_L_N CLKLVDS_L_P

LVDS_L2_P

LVDS_L2_N

LVDS_L1_P

LVDS_L1_N

LVDS_U0_P

LVDS_U1_N LVDS_U1_P

LVDS_U2_N LVDS_U2_P

CLKLVDS_U_N CLKLVDS_U_P

INV_ON_PWM

=PP3V3_PWRON_INVERTER

=PPBUS_INVERTER

BRIGHT_PWM_F

=GND_CHASSIS_LCD4

=GND_CHASSIS_LCD3

=GND_CHASSIS_LCD2

=GND_CHASSIS_LCD1

56

51

10

51

56

53

7

2

53

10

7

10

7

53

7

53

10

2

G

SD

G

SD

G

SD

SYM_VER-1

LCFILTER

SYM_VER-1

D

S

G

DS

V-

V+

G

D

S

G S D

MINIDIN

SYM_VER-1

32

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Q41C/514-0256/MH11773-MR8N-7F

Q16C/514-0265/MH11773-MR8A-7F

ELECTRICAL_CONSTRAINT_SET

SPACING

PHYSICAL

NET_TYPE

DIFFERENTIAL_PAIR

(55mA requirement per DVI spec)

DVI DDC CURRENT LIMIT

Isolation required for DVI power switch

(PP5V_RUN_DDC)

on, driving SYS_POWER_BUTTON_L low.

DVI POWER SWITCH

SIGNAL IS TRISTATED INITIALLY

ANALOG FILTERING

PLACE NEAR 3, 11 & 19

PLACE CLOSE TO CONNECTOR

powered DDC clock

has active, self-

on when DVI monitor

3904 from turning

Pulldown prevents

pullup.

will be low, TP0610 will turn As host rails rise, TP0610

into DDC_CLK. Since host rails

Power key detect path when DDC_CLK is isolated from

GPU during shutdown. When power key on remote device is pressed, 5V will be driven

system is shutdown or asleep..

by GPU.

HPD will be driven to 5V.

on remote device pressed,

3.3V. When power key

HPD normally driven to

when system is running.

Power key detect path

Comparator output enabled

will turn off, as will remote device path into DDC_CLK. Isolation will be disabled as well.

NEED PULL-DOWN BECAUSE THIS

S-VIDEO/COMP OUT INTERFACE

Place GND shorts at graphics controller

NOTE: Pulldown for DVI_HPD provided by DVI power switch interface

DVI INTERFACE

PLACE NEAR C5A & C5B

3V LEVEL SHIFTERS

PLACE CLOSE TO CONNECTOR

TMDS FILTERING

VGA SYNC BUFFERS

PLACE R7050 & R7051 CLOSE TO DVI CONNECTOR

10K

5% 1/16W MF-LF 402

2

1

R7021

10K

5% 1/16W MF-LF 402

2

1

R7020

2N7002DW-X-F

SOT-363

1

2

6

Q7011

2N7002DW-X-F

SOT-363

4

5

3

Q7011

100K

5% 1/16W MF-LF 402

2

1

R7022

CERM

5%

100pF

50V 402

2

1

C7013

4.7K

5% 1/16W MF-LF 402

2

1

R7012

4.7K

5% 1/16W MF-LF

402

2

1

R7010

402

CERM

5%

100pF

50V

2

1

C7011

0.01uF

20% 50V

CERM

603

2

1

C7010

SM-1

400-OHM-EMI

21

L7010

2N7002DW-X-F

SOT-363

4

5

3

Q7014

CRITICAL

0.5AMP-13.2V

SM-LF

21

F7010

SOD-123

B0530WXF

21

D7010

402

CERM

5%

100pF

50V

2

1

C7014

603

CERM

50V

20%

0.01uF

C7060

402

CERM

50V

10%

560pF

C7063

FERR-10-OHM-500MA

SM

L7060

3.3uH

0603

L7062

3.3uH

0603

L7064

402

CERM

50V

10%

560pF

C7065

402

CERM

50V

10%

560pF

C7067

0.01uF

20% 50V

603

CERM

C7061

0603

3.3uH

L7066

SM

FERR-10-OHM-500MA

L7061

560pF

10% 50V

CERM

402

C7062

560pF

402

CERM

50V

10%

C7064

402

CERM

50V

10%

560pF

C7066

SM

XW7060

SM

XW7061

MF-LF

1/16W

5%

100

402

21

R7011

MF-LF

1/16W

5%

100

402

21

R7013

MF-LF

1/16W

5%

100

402

21

R7014

CRITICAL

QH81127-CK1

F-RT-TH-LF

9

8

7

6

5

4

3

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

36

35

34

33

32

31

C5B C5A

C4

C3

C2

C1

J7000

MF-LF

1/16W

5%

0

402

2 1

R7030

MF-LF

1/16W

5%

0

402

2 1

R7031

TMDS_EXT&TMDS_DUAL

370-OHM

CRITICAL

SM

4

32

1

L7006

3.3pF

0.25% 50V CERM 402

2

1

C7041

NO STUFF

MF-LF

1/16W

1%

75

402

2

1

R7042

NO STUFF

MF-LF

1/16W

1%

75

402

2

1

R7040

NO STUFF

MF-LF

1/16W

1%

75

402

2

1

R7041

3.3pF

0.25% 50V CERM 402

2

1

C7042

3.3pF

0.25% 50V CERM 402

2

1

C7040

SM-220MHZ-LF

CRITICAL

43

21

FL7040

SM-220MHZ-LF

CRITICAL

43

21

FL7041

SM-220MHZ-LF

CRITICAL

43

21

FL7042

TMDS_EXT&TMDS_DUAL

90-OHM-300mA

CRITICAL

2012H

4

32

1

L7002

TMDS_EXT&TMDS_DUAL

CRITICAL

90-OHM-300mA

2012H

4

32

1

L7001

33

5% 1/16W MF-LF

402

21

R7050

402

MF-LF

1/16W

5%

33

21

R7051

402

10K

5% 1/16W MF-LF

21

R7083

330

5% 1/16W MF-LF

402

2

1

R7082

402

MF-LF

5%

680

1/16W

2 1

R7081

402

MF-LF

1/16W

5%

20K

21

R7080

402

MF-LF

1/16W

5%

68K

2

1

R7079

1210

CERM

6.3V

20%

47UF

2

1

C7079

MF-LF

1/16W

5%

330

402

21

R7078

100K

5% 1/16W MF-LF

402

2

1

R7077

SOT-363

2N7002DW-X-F

4

5

3

Q7076

402

CERM

20%

0.1uF

10V

2

1

C7070

TP0610

S0T23-3

2 3

Q7075

402

MF-LF

1/16W

5%

100K

2

1

R7075

68.1K

1% 1/16W MF-LF

402

2

1

R7072

SM-LF

LMC7211

2

5

1

3

4

U7070

402

MF-LF

1/16W

1%

100K

2

1

R7073

SOT-363

2N7002DW-X-F

1

2

6

Q7076

402

MF-LF

1/16W

5%

100K

2

1

R7076

402

MF-LF

1/16W

1%

10K

21

R7070

10K

1% 1/16W MF-LF

402

2

1

R7071

TP0610

S0T23-3

2

1

3

Q7081

SOT-363-LF

MMDT3904XF

4

3

5

Q7080

SOT-363-LF

MMDT3904XF

1

6

2

Q7080

CRITICAL

MH11773-MR8A-7F

RT-TH-LF

5

4 3 2 1

1110

98

J7060

TMDS_DUAL

90-OHM-300mA

CRITICAL

2012H

4

32

1

L7003

TMDS_DUAL

CRITICAL

90-OHM-300mA

2012H

4

32

1

L7004

TMDS_DUAL

90-OHM-300mA

CRITICAL

2012H

4

32

1

L7005

TMDS_EXT&TMDS_DUAL

90-OHM-300mA

CRITICAL

2012H

4

32

1

L7000

I548

I549

I550 I551

I552 I553

I554

I555

I558

I559

I560

I561 I562

I563

0.1uF

402

CERM

10V

20%

21

C7051

20% 10V

CERM

402

0.1uF

21

C7050

74AHC1G32

SM-LF

5

4

2

1

3

U7051

74AHC1G32

SM-LF

5

4

2

1

3

U7050

SYNC_DATE=N/A

051-6929

C

115

70

SYNC_MASTER=N/A

External Display Conns

GPU_HSYNC_BUF

GPU_VGA_HSYNC

VGA_HSYNC

GPU_VSYNC_BUF

GPU_VGA_VSYNC

VGA_VSYNC

=PP3V3_PWRON_VGASYNC

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

VOLTAGE=5V

PP5V_RUN_DDC

TMDS_DN<5>

TMDS_DP<5>

TMDS_CONN_DP<5>

TMDS_CONN_DN<5>

TMDS_DN<4>

TMDS_DP<4>

TMDS_CONN_DP<4>

TMDS_CONN_DN<4>

TMDS_DN<3>

TMDS_DP<3>

TMDS_CONN_DP<3>

TMDS_CONN_DN<3>

TMDS_CLKP

TMDS_CLKN

TMDS_CONN_CLKN

TMDS_CONN_CLKP

TMDS_DN<2>

TMDS_DP<2>

TMDS_CONN_DP<2>

TMDS_CONN_DN<2>

TMDS_DN<1>

TMDS_DP<1>

TMDS_CONN_DP<1>

TMDS_CONN_DN<1>

TMDS_DN<0>

TMDS_DP<0>

TMDS_CONN_DP<0>

TMDS_CONN_DN<0>

TMDS_CONN_DP<0>

DVI_DDC_DATA_UF

=GND_CHASSIS_DVI3

=GND_CHASSIS_DVI2

=GND_CHASSIS_DVI1

=GND_CHASSIS_TV

TMDS_CONN_DP<3>

TMDS_CONN_DP<4>

TMDS_CONN_DN<3>

TMDS_CONN_DN<4>

TMDS_CONN_DN<2> TMDS_CONN_DN<1>

TMDS_CONN_DP<1>

TMDS_CONN_DP<2>

VGA_HSYNC

VGA_B

TMDS_CONN_CLKN

TMDS_CONN_CLKP

TMDS_CONN_DN<5>

TMDS_CONN_DP<5>

TV_COMP

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

VOLTAGE=0V

GND_TV1

TV_Y

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

VOLTAGE=0V

GND_TV2

TV_C

GPU_VGA_B

GPU_VGA_G

=PP3V3_DDC_DVI

HPD_PWR_SNS_EN

DVI_HPD_DIV

DVI_HPD_UF

HPD_PWR_SW

DVI_TURN_ON

DVI_DDC_CLK_UF

HPD_ON

DVI_TURN_ON_ILIM

DVI_TURN_ON_BASE

HPD_BASE

COMP_DISABLE

HPD_4V_REF

=PPBUS_DVI_PWRSW

HPD_ON_RC

PP5V_RUN_DDC

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

VOLTAGE=0V

GND_GPU_TV2

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

VOLTAGE=0V

GND_GPU_TV1

GPU_VGA_R

COMP_ENABLE

VGA_VSYNC

VGA_R

VGA_G

SYS_POWER_BUTTON_L

=PP5V_RUN_DVI_DDC

PP5V_RUN_DDC_FUSE

VOLTAGE=5V MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm

VGA_B

VGA_G

VGA_R

VOLTAGE=5V MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm

PP5V_RUN_DDC_PULLUPS

DVI_DDC_CLK_UF

DVI_HPD_UF

GPU_DVI_DDC_CLK

DVI_DDC_CLK

GPU_DVI_DDC_DATA

DVI_DDC_DATA

=PP3V3_DDC_DVI

GPU_DVI_HPD

DVI_HPD

=GND_CHASSIS_DVI4

GPU_TV_Y

GPU_TV_C

GPU_TV_COMP

TMDS_CONN_DN<2>

TMDS_CONNTMDS_CONN

TMDS_CONN_D2

TMDS_CONN_DP<2>

TMDS_CONNTMDS_CONN

TMDS_CONN_D2

TMDS_CONN_DP<1>

TMDS_CONNTMDS_CONN

TMDS_CONN_D1

TMDS_CONN_DN<1>

TMDS_CONNTMDS_CONN

TMDS_CONN_D1

TMDS_CONN_DN<0>

TMDS_CONNTMDS_CONN

TMDS_CONN_D0

TMDS_CONN_CLKN

TMDS_CONNTMDS_CONN

TMDS_CONN_CLK

TMDS_CONN_DP<0>

TMDS_CONNTMDS_CONN

TMDS_CONN_D0

TMDS_CONN_CLKP

TMDS_CONNTMDS_CONN

TMDS_CONN_CLK

TMDS_CONN_DP<3>

TMDS_CONNTMDS_CONN

TMDS_CONN_D3

TMDS_CONN_DN<3>

TMDS_CONNTMDS_CONN

TMDS_CONN_D3

TMDS_CONN_DN<4>

TMDS_CONNTMDS_CONN

TMDS_CONN_D4

TMDS_CONN_DP<4>

TMDS_CONNTMDS_CONN

TMDS_CONN_D4

TMDS_CONN_DN<5>

TMDS_CONNTMDS_CONN

TMDS_CONN_D5

TMDS_CONN_DP<5>

TMDS_CONNTMDS_CONN

TMDS_CONN_D5

36 30

57

25

57

53

57

53

57

10

57

55

55 57

57

55

55 57

57

55

55 57

57

54

54 57

2

54

54 57

57

54

54 57

57

54

54 57

57

2

57

53

57

2

57

53

10

51

57

10

57

53

57

53

24

10

53

57

51

10

51

2

53

57

2

57

DQ1

VCCVPP

DQ7

DQ4

DQ3

DQ2

DQ5 DQ6

DQ0

GND

PWD

WP

WE

OE

CE

A19

A18

A17

A20

A16

A15

A14

A13

A12

A11

A10

A7 A8 A9

A5

A4

A3

A2

A6

A1

A0

IN

BI BI

IN IN

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Page Notes

Power aliases required by this page:

- =PP3V3_PCI_ROM

Signal aliases required by this page:

BOM options provided by this page:

NOTE: This page does not specify a BootROM part number. Must use a

U7100 part number.

TABLE_x_ITEM symbol to declare

- =ROM_PWD_L

(NONE)

to intercept ROM chip select

Allows ROM override module

1MX8-3.3V-90.0NS

TSOP

OMIT

12

9

11 3130

10

24

3923

35

34

33

32

28

27

26

25

22

7

8

14

15

16

17

18

38

19

37

13

40

1

2

3

4

5

6

36

20

21

U7100

5%

MF-LF

402

1/16W

470

21

R7152

60 59

60

0

1

2

5

4

3

8

7

6

11

10

9

14

13

12

17

16

15

20

19

18

62 61 60 59 11 62 61 60 59

24

25

26

27

28

29

30

31

60 59

11

10K

MF-LF 402

5% 1/16W

2

1

R7151

10K

MF-LF

402

5%

1/16W

2

1

R7150

X5R

6.3V

10%

603

2.2uF

2

1

C7100

10V

0.1uF

402

20%

CERM

2

1

C7101

10V

CERM

402

20%

0.1uF

2

1

C7102

SYNC_DATE=N/A

SYNC_MASTER=N/A

BootROM

71

115

051-6929

C

PCI_AD<20:0>

PCI_AD<31:24>

=ROM_PWD_L

ROM_WE_L

ROM_OE_L

=PP3V3_PCI_ROM

ROM_WP_L

=PP3V3_PCI_ROM

ROM_ONBOARD_CS_L

ROM_CS_L

58

10

PCI/ROM INTERFACE

ROM INTERFACE

(10 of 14)

PCI DEVICE 0

PCI DEVICE 1

PCI INTERFACE

ROM_WE_L

ROM_CS_L ROM_OE_L

PCI_DEVSEL_L

PCI_STOP_L

PCI_TRDY_L PCI_IRDY_L

PCI_PAR_H PCI_FRAME_L

PCI_REQ_1_L

PCI_REQ_0_L

PCI_CBE_0_L

PCI_AD_07_H

PCI_AD_06_H

PCI_AD_05_H

PCI_AD_02_H PCI_AD_03_H PCI_AD_04_H

PCI_AD_01_H

PCI_AD_00_H

PCI_GNT_1_L

PCI_CLK_1_H

PCI_GNT_0_L

PCI_CLK_0_H

PCI_FB_CLK_IN_H

PCI_CBE_3_L

PCI_FBCLK_OUT_H

PCI_AD_30_H PCI_AD_31_H

PCI_AD_29_H

PCI_AD_28_H

PCI_AD_27_H

PCI_AD_25_H PCI_AD_26_H

PCI_CBE_2_L

PCI_AD_24_H

PCI_AD_22_H PCI_AD_23_H

PCI_AD_21_H

PCI_AD_20_H

PCI_AD_19_H

PCI_AD_16_H PCI_AD_17_H PCI_AD_18_H

PCI_CBE_1_L

PCI_AD_15_H

PCI_AD_14_H

PCI_AD_13_H

PCI_AD_12_H

PCI_AD_11_H

PCI_AD_09_H PCI_AD_10_H

PCI_AD_08_H

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Output Impedance is about 20 Ohms

PCI PULL-UPS

SLOT E REQ/GNT pull-ups not provided by this page.

"Slot D" - AD20

BOM options provided by this page: (NONE)

- =PP3V3_PCI

longest clock from I2 to PCI device.

input. Length should match that of

- =I2_PCI_FBCLK_IN - PCI feedback clock

Signal aliases required by this page:

Page Notes

NET_TYPE

SPACING

PHYSICAL

DIFFERENTIAL_PAIR

Power aliases required by this page:

(BOOTROM ADDR)

(SLOT E IDSEL)

ELECTRICAL_CONSTRAINT_SET

3.3V OUT

3.3V IN

(SLOT D IDSEL)

(BOOTROM ADDR/SLOT A IDSEL)

"Slot A" - AD17

(PCI ONLY) (BOOTROM DATA)

- PCI_SLOTD_REQ_L

- PCI_SLOTD_GNT_L

- PCI_SLOTA_REQ_L

- PCI_SLOTA_GNT_L

One resistor for each of:

- PCI_FRAME_L

- PCI_TRDY_L

- PCI_IRDY_L

- PCI_STOP_L

1/16W

5%

SM-LF

10K

72

RP7250

10K

SM-LF

5%

1/16W

81

RP7251

10K

SM-LF

5%

1/16W

72

RP7251

1/16W

5%

SM-LF

10K

54

RP7251

10K

SM-LF

5%

1/16W

63

RP7251

SM-LF

5%

1/16W

10K

81

RP7250

10K

SM-LF

5%

1/16W

63

RP7250

10K

SM-LF

5%

1/16W

54

RP7250

BGA

I2

OMIT

AN34

AM31

AP33

AN24

AP27

AT20

AR21

AP28

AR25

AN21

AL19

AT24

AE23AM28

AM25

AR27

AL25

AM22

AM24

AT29

AR30

AP21

AT22

AL21

AK21

AR22

AN22

AP22

AM21

AT23

AK22

AT25

AR24

AP24

AT26

AL22

AP25

AR28

AN25

AT27

AN27

AT30

AT28

AM30

AM27

AR31

AN30

AT34

AN28

AP30

AT31

AT32

AP31

U2100

10K

MF-LF

402

5%

1/16W

21

R7252

1/16W MF-LF

33

5%

402

21

R7205

1/16W

5%

402

MF-LF

10K

21

R7254

1/16W

5%

402

MF-LF

10K

21

R7253

72

115

C

051-6929

I2 PCI Interface

SYNC_MASTER=N/A

SYNC_DATE=N/A

PCI PCI

PCI_FRAME_L

PCI_CTL

PCI_DEVSEL_L

PCI PCI

PCI_IRDY_L

PCI_CTL

PCI PCI

PCI_CTL

PCI_TRDY_L

PCI PCI

PCI_CTL

PCI_STOP_L

PCI PCI

PCI

PCI_SLOTA_REQ_L

PCI

PCI PCI

PCI_SLOTD_REQ_L

PCI

PCI_SLOTA_GNT_L

PCI

PCI_SLOTD_GNT_L

PCI

PCI_CLK_SLOTA

CLOCK

TP_PCI_CLK33M_SLOTA_R

CLOCK

I2_PCI_FBCLK_OUT

I2_FBCLKI2_FBCLK

PCI_AD<16..0>

PCI

PCI_AD16_0

PCI

PCIPCI

PCI_AD<31..24>

PCI_AD31_24

PCI_AD<23..22>

PCI PCI

PCI_AD23_22

PCI

PCI_AD<21>

PCI

PCI_AD21

PCI_AD<20>

PCIPCI

PCI_AD20

PCI_AD<19..18>

PCI

PCI_AD19_18

PCI

PCI_AD<17>

PCIPCI

PCI_AD17

=I2_PCI_FBCLK_IN

PCI_CBE

PCI PCI

PCI_CBE_L<3..0>

I2_PCI_FBCLK_OUT_R

I2_PCI_FBCLK

I2_FBCLK I2_FBCLK

PCI_PAR

PCI PCI

TP_PCI_CLK33M_SLOTD_R

CLOCK CLOCK

PCI_CLK_SLOTD

I2_PCI_FBCLK_OUT_R

I2_PCI_FBCLK_OUT

ROM_WE_L

ROM_CS_L ROM_OE_L

PCI_CBE_L<0>

PCI_SLOTD_GNT_L

TP_PCI_CLK33M_SLOTD_R

PCI_SLOTA_GNT_L

PCI_CBE_L<3>

PCI_CBE_L<2>

PCI_AD<21>

PCI_CBE_L<1>

PCI_AD<17>

PCI_AD<20>

TP_PCI_CLK33M_SLOTA_R

PCI_DEVSEL_L

PCI_STOP_L

PCI_TRDY_L PCI_IRDY_L

PCI_PAR PCI_FRAME_L

PCI_SLOTD_REQ_L

PCI_SLOTA_REQ_L

PCI_AD<31>

PCI_AD<30>

PCI_AD<29>

PCI_AD<28>

PCI_AD<27>

PCI_AD<26>

PCI_AD<25>

PCI_AD<24>

PCI_AD<23>

PCI_AD<22>

PCI_AD<19>

PCI_AD<18>

PCI_AD<16>

PCI_AD<15>

PCI_AD<14>

PCI_AD<13>

PCI_AD<12>

PCI_AD<11>

PCI_AD<10>

PCI_AD<9>

PCI_AD<8>

PCI_AD<7>

PCI_AD<6>

PCI_AD<5>

PCI_AD<4>

PCI_AD<3>

PCI_AD<2>

PCI_AD<1>

PCI_AD<0>

=RP7250P3

=RP7250P2

=RP7250P1

=RP7251P2

=RP7251P3

=RP7251P1

=RP7251P4

=RP7250P4

PCI_DEVSEL_L

PCI_SLOTD_INT_L

PCI_SLOTA_INT_L

=PP3V3_PCI

62

61

62

61

62

61

62

61

62

61

62

61

60

61

60

62

61

62

60

62

61

62

61

62

61

62

60

61

60

61

60

59

60

59

61

60

61

59

61

60

61

60

61

60

61

59

60

59

60

59

58

59

58

60

59

60

59

60

59

60

58

59

60

59

60

59

60

59

60

22

6

59

6

11

21

58

59

11

58

11

21

59

11

59

21

58

59

11

59

11

59

11

59

6

59

6

11

58

59

58

6

59

11

10

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(NONE)

AD17 (Slot "A") - AirPort (0x????/0x????)

- =USB_BT_N (Bluetooth USB D-)

- =USB_BT_P (Bluetooth USB D+)

- =PP3V3_PCI (802.11g Power)

- =PP3V3_PWRON_BT (Bluetooth Power)

not support PME#.

BOM options provided by this page:

- =PCI_AIRPORT_RESET_L (PCI Reset)

Page Notes

Power aliases required by this page:

Signal aliases required by this page:

- =PCI_CLK33M_AIRPORT (33MHz PCI clock)

PCI Devices implemented on this page:

NOTE: This AirPort implementation does

ELECTRICAL_CONSTRAINT_SET

SPACING

NET_TYPE

PHYSICAL

DIFFERENTIAL_PAIR

Q16C/516S0361/F-ST-SM Q41C/516S0352/M-ST-SM-LF

Q85 Connector

NC

10K

MF-LF 402

5% 1/16W

2

1

R7305

1/16W

5%

402

MF-LF

22

21

R7300

CRITICAL

QT510806-L111-7F

F-ST-SM

9

84

83 82

81

80879

78 77

76 75

74 73

72 71

70769

68 67

66 65

64 63

62 61

60659

58 57

56 55

54 53

52 51

50549

48 47

46 45

44 43

42 41

40439

38 37

36 35

34 33

32 31

30329

28 27

26 25

24 23

22 21

20219

18 17

16 15

14 13

12 11

10

1

J7300

I315

SYNC_DATE=N/A

SYNC_MASTER=N/A

051-6929

C

115

73

Q85 Airport/BT Connector

PCI_AD<31> AIRPORT_CLKRUN_L_PD TP_AIRPORT_PME_L =PCI_AIRPORT_GNT_L

=PP3V3_PCI_AIRPORT

PCI_AD<24> =PCI_AIRPORT_RESET_L PCI_AD<28>

PCI_AD<23>

PCI_AD<20> PCI_FRAME_L PCI_AD<17>

PCI_TRDY_L

PCI_CBE_L<2> =PCI_CLK33M_AIRPORT

PCI_AD<14> PCI_AD<13>

PCI_AD<10> PCI_AD<15> TP_AIRPORT_ALT_ANTENNA PCI_CBE_L<1> PCI_AD<4>

PCI_AD<11> ROM_WE_L PCI_AD<2>

=PCI_AIRPORT_INT_L ROM_OE_L

USB_BT_N

PCI_CBE_L<0>

PCI_AD<30>

PCI_AD<27> =PCI_AIRPORT_REQ_L PCI_AD<25> PCI_AD<29>

PCI_CBE_L<3> PCI_AD<26> PCI_AD<22> PCI_AIRPORT_IDSEL

PCI_AD<19> PCI_AD<21> PCI_IRDY_L PCI_AD<18> PCI_DEVSEL_L

PCI_AD<16> PCI_STOP_L PCI_AD<12> PCI_PAR

PCI_AD<8> PCI_AD<9>

PCI_AD<7> PCI_AD<3> PCI_AD<6>

PCI_AD<1> PCI_AD<5> PCI_AD<0>

ROM_ONBOARD_CS_L ROM_CS_L

=PP3V3_PWRON_BT

USB_BT_P

=PCI_AIRPORT_IDSEL

=PCI_CLK33M_AIRPORT

CLOCK CLOCK

62

61

62

61

62

61

62

59

61

59

61

62

61

62

61

62

61

62

61

62

61

62

61

62

61

59

61

58

59

58

59

61

60

59

61

59

61

59

61

59

61

59

61

59

61

59

60

58

11

10

58

11

58

59

11

6

11

6

59

11

58

59

58

11

58

11

59

58

11

58

59

58

59

58

11

6

58

59

58

6

58

59

58

10

11

C/BE3*

C/BE2*

C/BE1*

C/BE0*

VR_EN* VR_PORT

VCCCB

VCCP

GND

VCC

GRST

MFUNC4 MFUNC5 MFUNC6

MFUNC3

MFUNC0

SUSPEND

MFUNC1 MFUNC2

PCLK

SPKROUT

GNT

TRDY

STOP

FRAME

PRST REQ

DEVSEL

PERR

IDSEL

SERR

IRDY

AD31

PAR

AD30

AD29

AD28

AD27

AD20 AD21

AD18 AD19

AD26

AD25

AD24

AD23

AD22

AD17

AD10 AD11

AD9

AD8

AD16

AD15

AD14

AD13

AD12

AD7

AD0

AD2 AD3 AD4 AD5 AD6

AD1

D14/RSVD

D13/CAD6

D12/CAD4

D11/CAD2

D10/CAD31

D15/CAD8

D9/CAD30

D8/CAD28

D7/CAD7

D6/CAD5

D5/CAD3

D4/CAD1

D3/CAD0

D2/RSVD

D1/CAD29

D0/CAD27

A22/CTRDY*

A20/CSTOP*

A23/CFRAME*

A21/CDEVSEL*

A19/CBLOCK*

A15/CIRDY*

A14/CPERR*

A12/CC/BE2*

A8/CC/BE1*

A25/CAD19

A24/CAD17

A18/RSVD

A17/CAD16

A16/CCLK

A13/CPAR

A11/CAD12

A10/CAD9

A9/CAD14

A7/CAD18

A6/CAD20

A5/CAD21

CE2/CAD10*

INPACK/CREQ*

WAIT/CSERR*

A4/CAD22

A3/CAD23

A2/CAD24

A1/CAD25

A0/CAD26

VPPD1

VPPD0

VCCD0* VCCD1*

IORD*/CAD13 IOWR*/CAD15

OE*/CAD11

WE*/CGNT*

CD2*/CCD2*

CD1*/CCD1*

CE1*/CC/BE0*

RDY/IREQ*/CINT*

VS1*/CVS1 VS2*/CVS2

REG*/CC/BE3*

RESET/CRST*

BVD1/CSTSCHG/STSCHG*/RI*

BVD2/SPKR*/CAUDIO

WP/IOIS16*/CCLKRUN*

RI_OUT/PME

CLK_48_RSVD/NC

TPS2211

OC

AVPP

AVCC2

AVCC1

AVCC0

GND

SHTDWN

VCCD0 VCCD1 VPPD0 VPPD1

V_5_2

V_5_1

V_3_2

V_3_1

V_12

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

PCI1510 PULL-UPS

DIFFERENTIAL_PAIR

SPACING

PHYSICAL

NET_TYPE

ELECTRICAL_CONSTRAINT_SET

TI REFERENCE SCHEMATIC DID NOT HAVE BULK ON PPVCC_CBUS_SW

NC

CLAMP FOR PC-CARD

MAKE SURE VCC AND VPP ARE WIDE PLANE/TRACES TO MINIMIZE INDUCTANCE!

0.1UF ARE USED TO INCREASE ESD DISCHARGES OF UP TO 10KV

PC CARD/CARDBUS CONNECTOR

NC

INTEGRATED PULL-UP

CLAMP FOR PCI

0.1uF

20% 10V CERM 402

2

1

C7451

402

MF-LF

1/16W

5%

10K

21

R7420

10K

402

MF-LF

1/16W

5%

21

R7421

1/16W

10K

402

MF-LF

5%

21

R7422

603

X5R

6.3V

20%

10UF

2

1

C7401

BGA-LF

PCI1510ZGU

CRITICAL

A5

D13

B6

A9

B2

L8

D4

M11

K9

L3

L12

N13

B11

N11

N7M1E1D5

C13

A7

J3

N10

L1

M9

L2

M8

D8

C2

A8

A6

G3

K3

G1

N1

G10

L10

N12

M10

K10

L9

N9

K7

K1

C11

F12

B8

F2

L11

C1

N2

M13

K8H4

F13

D1

A11

A2

J1

K2

B4

C5

H12

J10

J13

K12

K11

A3

H11

J12

K13

J11

M12

B3

C4

A4

H10

G13

H13

B5

L13

A1

J2

M3

K6

D6

C6

M2

N4

N5

L6

M6

K4

E3

D3

N6

E4

D2

B1

F4

E2

F3

C3

F1

G4

G2

L7

H2

H3

H1

J4

M4

L5

K5

N3

L4

M5

M7

N8

F11

E11

A12

C9

C8

B12

D10

B9

B10

A10

C12

D11

E10

B7

A13

E13

F10

B13

C10

D12

E12

D9

G12

G11

D7

C7

U7400

10K

402

5% 1/16W MF-LF

2

1

R7410

2.2uF

603

10%

6.3V X5R

2

1

C7490

2.2uF

603

10%

6.3V X5R

2

1

C7491

20%

6.3V CERM 805

4.7uF

2

1

C7410

10UF

20%

6.3V X5R 603

2

1

C7400

M-ST-SM

QT500806-L121-9F

CRITICAL

9

84

83 82

81

80879

78 77

76 75

74 73

72 71

70769

68 67

66 65

64 63

62 61

60

6

59

58 57

56 55

54 53

52 51

50

5

49

48 47

46 45

44 43

42 41

40

4

39

38 37

36 35

34 33

32 31

30

3

29

28 27

26 25

24 23

22 21

20

2

19

18 17

16 15

14 13

12 11

10

1

J7490

MF-LF 603

1/10W

5%

0

2

1

R7400

402

CERM-X5R

6.3V

10%

0.22UF

2

1

C7408

SM-LF

10K

5%

1/16W

5

6

7

8

4

3

2

1

RP7410

402

MF-LF

1/16W

5%

10K

21

R7411

402

MF-LF

1/16W

5%

10K

21

R7412

I192

0

5% 1/16W MF-LF

402

2

1

R7450

10%

6.3V CERM-X5R 402

0.22UF

2

1

C7411

SSOI

6

5

4

3

9

14

15

2

1

16

87

10

13

12

11

U7450

0.22UF

10%

6.3V CERM-X5R 402

2

1

C7407

402

CERM-X5R

6.3V

10%

0.22UF

2

1

C7404

402

CERM-X5R

6.3V

10%

0.22UF

2

1

C7406

402

CERM-X5R

6.3V

10%

0.22UF

2

1

C7403

47

5% 1/16W MF-LF

402

21

R7430

0.22UF

10%

6.3V CERM-X5R 402

2

1

C7402

402

CERM-X5R

6.3V

10%

0.22UF

2

1

C7405

0.1uF

20% 10V

CERM

402

2

1

C7450

402

MF-LF

1/16W

5%

22

2

1

R7423

47

5% 1/16W MF-LF

402

21

R7424

SYNC_DATE=N/A

SYNC_MASTER=N/A

C

051-6929

115

74

Cardbus

CBUS_MFUNC2_PD

CBUS_MFUNC4_PD

CBUS_MFUNC5_PD CBUS_MFUNC6_PD CBUS_MFUNC3_PD CBUS_MFUNC1_PD

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=3.3V

PP3V3_RUN_PCI1510

=PCI_CBUS_RESET_L

PCI_AD<19>

=PCI_CBUS_IDSEL

PCI_CBUS_IDSEL

PPVCC_CBUS_SW

VOLTAGE=3.3V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

=PP2V5_RUN_PCI1510

PPVCC_CBUS_SW

CBUS_ADDR<16>

=PP5V_PWRON_TPS2211

CBUS_VPPD1

CBUS_VPPD0

CBUS_VCCD1_L

CBUS_VCCD0_L

=TPS2211_SHDN_L

TPS2211_SHTDWN_L

=PP3V3_RUN_PCI1510_R

=PP3V3_PWRON_TPS2211

PCI_AD<3>

PCI_AD<2>

CBUS_DATA<11>

CBUS_DET_1_L

CBUS_BVD2_L

PCI_IRDY_L PCI_SERR_L

PCI1510_VR_EN_L

CBUS_BVD1_L

CBUS_DET_1_L CBUS_DET_2_L CBUS_IORD_L CBUS_IOWR_L CBUS_OE_L CBUS_CE1_L

CBUS_WE_L CBUS_READY CBUS_RESET_L CBUS_REG_L

CBUS_WP_L CBUS_CE2_L CBUS_INPACK_L CBUS_WAIT_L

CBUS_DATA<14>

CBUS_DATA<13>

CBUS_DATA<12>

CBUS_DATA<11>

CBUS_DATA<10>

CBUS_DATA<9>

CBUS_DATA<8>

CBUS_DATA<6>

CBUS_DATA<5>

CBUS_DATA<4>

CBUS_DATA<3>

CBUS_DATA<2>

CBUS_DATA<1>

CBUS_DATA<0>

CBUS_ADDR<25>

CBUS_ADDR<24>

CBUS_ADDR<23>

CBUS_ADDR<22>

CBUS_ADDR<21>

CBUS_ADDR<20>

CBUS_ADDR<19>

CBUS_ADDR<18>

CBUS_ADDR<17>

CBUS_ADDR_16_R

CBUS_ADDR<15>

CBUS_ADDR<14>

CBUS_ADDR<13>

CBUS_ADDR<12>

CBUS_ADDR<11>

CBUS_ADDR<10>

CBUS_ADDR<9>

CBUS_ADDR<8>

CBUS_ADDR<7>

CBUS_ADDR<6>

CBUS_ADDR<5>

CBUS_ADDR<4>

CBUS_ADDR<3>

CBUS_ADDR<2>

CBUS_ADDR<1>

CBUS_ADDR<0>

CBUS_DATA<15>

CBUS_VS1 CBUS_VS2

PCI_PERR_L PCI_FRAME_L

PCI_PAR

CBUS_MFUNC1_PD CBUS_MFUNC2_PD CBUS_MFUNC3_PD CBUS_MFUNC4_PD CBUS_MFUNC5_PD CBUS_MFUNC6_PD

PCI_DEVSEL_L

PCI_TRDY_L

PCI_STOP_L

PCI_AD<0> PCI_AD<1>

PCI_CBE_L<3>

PCI_CBE_L<2>

PCI_CBE_L<1>

PCI_CBE_L<0>

PCI_AD<10> PCI_AD<11> PCI_AD<12> PCI_AD<13> PCI_AD<14> PCI_AD<15> PCI_AD<16> PCI_AD<17> PCI_AD<18>

PCI_AD<20> PCI_AD<21> PCI_AD<22> PCI_AD<23> PCI_AD<24> PCI_AD<25>

PCI_AD<9>

PCI_AD<8>

PCI_AD<7>

PCI_AD<6>

PCI_AD<5>

PCI_AD<4>

PCI_AD<31>

PCI_AD<30>

PCI_AD<29>

PCI_AD<28>

PCI_AD<27>

PCI_AD<26>

CBUS_DATA<3> CBUS_DATA<4> CBUS_DATA<5>

CBUS_DATA<7> CBUS_CE1_L CBUS_ADDR<10> CBUS_OE_L

CBUS_ADDR<11> CBUS_ADDR<9>

CBUS_ADDR<13>

CBUS_ADDR<14> CBUS_WE_L CBUS_READY PPVCC_CBUS_SW

PPVPP_CBUS_SW

CBUS_ADDR<7> CBUS_ADDR<6> CBUS_ADDR<5> CBUS_ADDR<4>

CBUS_ADDR<3> CBUS_ADDR<2> CBUS_ADDR<1> CBUS_ADDR<0>

CBUS_DATA<0> CBUS_DATA<1> CBUS_DATA<2> CBUS_WP_L

CBUS_ADDR<8>

CBUS_ADDR<25>

CBUS_DATA<12> CBUS_DATA<13>

CBUS_DATA<14> CBUS_DATA<15> CBUS_CE2_L CBUS_VS1

CBUS_IORD_L CBUS_IOWR_L CBUS_ADDR<17> CBUS_ADDR<18>

CBUS_ADDR<19> CBUS_ADDR<20> CBUS_ADDR<21>

PPVPP_CBUS_SW CBUS_ADDR<22> CBUS_ADDR<23> CBUS_ADDR<24>

CBUS_VS2 CBUS_RESET_L CBUS_WAIT_L

CBUS_INPACK_L CBUS_REG_L CBUS_BVD2_L CBUS_BVD1_L

CBUS_DATA<8>

CBUS_DATA<10> CBUS_DET_2_L

CBUS_DATA<6>

CBUS_ADDR<16> CBUS_ADDR<15> CBUS_ADDR<12>

CBUS_DATA<9>

CBUS_DATA<7>

PCI_CBUS_RESET_L

=PCI_CBUS_INT_L

CBUS_SUSPEND_PU

=PCI_CBUS_REQ_L =PCI_CBUS_GNT_L =PCI_CLK33M_CBUS

PPVPP_CBUS_SW

VOLTAGE=3.3V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

=PCI_CLK33M_CBUS

CLOCK CLOCK

PP3V3_RUN_PCI1510

PCI_PERR_L

CBUS_SUSPEND_PU

PCI_SERR_L

62

60

62

60

62

60

62

60

62

60

59

60

59

60

62

60

59

60

59

60

59

58

59

58

59

60

59

61

11

58

11

61

10

61

10

58

61

6

61

6

59

61

59

6

58

59

58

11

58

11

59

58

61

11

61

11

61

11

61

AD1

SRMOD

NANDTEST

NTEST1

SRDTA

SRCLK

TEST

TEB AMC

SMC

LEGC

PME

PCLK

INTC

INTB

INTA

VBBRST

SMI

CRUN

SERR

REQ

STOP

TRDY

IRDY

FRAME

IDSEL DEVSEL

GNT PERR

PAR

CBE3

CBE2

CBE1

CBE0

AD31

AD30

AD29

AD28

AD24

AD23

AD22

AD21

AD20

AD19

AD18

AD25 AD26 AD27

AD14

AD13

AD12

AD11

AD10

AD9

AD8

AD15 AD16 AD17

AD7

AD6

AD0

AD2

AD5

AD4

VCCRST

AD3

VDD_PCI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

- =PP3V3_PCI_USB2 (D3cold rail)

- =PPVIO_PCI (to 3.3V or 5V)

- USB2_NEC

D3cold.

- =PCI_USB2_INT_L

- =PCI_CLK33M_USB2

- =PCI_USB2_REQ_L

- =PCI_USB2_GNT_L

Signal aliases required by this page:

AD27 (Slot "G") - USB2 (0x1033/0x0035)

PCI Devices implemented on this page:

NOTE: This USB2 implementation supports

BOM options provided by this page:

- =PCI_USB2_IDSEL

- =PCI_USB2_RESET_L

facilitate NAND-tree testing

ELECTRICAL_CONSTRAINT_SET

SPACING

NET_TYPE

PHYSICAL

Page Notes

Power aliases required by this page:

DIFFERENTIAL_PAIR

OD

(PCI RESET)

OD OD OD OD

(CHIP RESET)

IPD

IPD IPD

IPD

RP7510 & R7510-12 required to

USB2_NEC

0.1uF

10V 402

CERM

20%

2

1

C7500

USB2_NEC

MF-LF

4.7K

402

1/16W

5%

2

1

R7503

47

1/16W

5%

USB2_NEC

SM-LF

72

RP7510

1/16W

5%

47

USB2_NEC

SM-LF

63

RP7510

5%

47

1/16W

USB2_NEC

SM-LF

81

RP7510

USB2_NEC

402

47

5% 1/16W MF-LF

1 2

R7510

USB2_NEC

402

MF-LF

1/16W

5%

47

2

1

R7504

USB2_NEC

MF-LF

47

5%

1/16W

402

1 2

R7511

USB2_NEC

402

1/16W

5%

47

MF-LF

1 2

R7512

FBGA-LF

NEC_uPD720101_USB2

CRITICAL

USB2_NEC

C8M4H3

C9

B8

G1

L8

N7

G3

P9

N9

M9

L6

M7

H1

C6

D9

H2

A8

J4

M8

M10

L7

F4

A7

B7

C7

B3

D6

F3

G2

N6

C3

F1

J3

M2

P7

L1

L2

M1

N3

M3

N4

A6

B6

P4

C5

A5

C4

B5

A4

B4

C1

C2

D2

D1

N5

D3

E1

E3

F2

J1

J2

K3

K1

L3

K2

P5

M5

U7500

I6

MF-LF

1/16W

402

22

5%

USB2_NEC

2

1

R7500

USB2_NEC

MF-LF

5%

1/16W

402

10K

2

1

R7502

USB2_NEC

MF-LF

10K

1/16W

402

5%

2

1

R7501

C

051-6929

115

75

NEC USB2

SYNC_MASTER=N/A

SYNC_DATE=N/A

PCI_USB2_IDSEL

NEC_VCCRST_L

SYS_PME_L

NEC_PME_L

NEC_VBBRST_L

SYS_WARM_RESET_L

NEC_LEGC_PD

PCI_AD<27>

PCI_AD<1>

PCI_AD<4>

PCI_AD<3>

PCI_AD<2>

PCI_AD<0>

TP_NEC_NTEST1

TP_NEC_SMC

TP_NEC_TEB TP_NEC_AMC

TP_NEC_TEST

TP_NEC_SRCLK

TP_NEC_NANDTEST

TP_NEC_SRDATA TP_NEC_SRMOD

PCI_AD<6>

PCI_AD<5>

PCI_AD<7> PCI_AD<8> PCI_AD<9>

PCI_AD<11>

PCI_AD<10>

PCI_AD<12> PCI_AD<13> PCI_AD<14>

PCI_AD<17>

PCI_AD<16>

PCI_AD<15>

PCI_AD<18> PCI_AD<19> PCI_AD<20>

PCI_AD<22>

PCI_AD<21>

PCI_AD<23> PCI_AD<24> PCI_AD<25> PCI_AD<26>

PCI_AD<29>

PCI_AD<28>

PCI_AD<30> PCI_AD<31>

PCI_CBE_L<0> PCI_CBE_L<1>

PCI_CBE_L<3>

PCI_CBE_L<2>

PCI_PAR PCI_FRAME_L PCI_IRDY_L PCI_TRDY_L PCI_STOP_L

PCI_DEVSEL_L

=PCI_CLK33M_USB2

TP_NEC_SMI_L

NEC_PERR_L_PU

NEC_INTB_L

NEC_SERR_L_PU

NEC_CRUN_L_PD

CLOCKCLOCK

=PCI_CLK33M_USB2

NEC_INTA_L

NEC_INTC_L

=PCI_USB2_REQ_L =PCI_USB2_GNT_L

=PCI_USB2_INT_L

=PCI_USB2_IDSEL

=PCI_USB2_RESET_L

=PPVIO_PCI_USB2

=PP3V3_PCI_USB2

61

60

61

60

61

60

59

60

59

61

60

61

60

61

60

61

25

59

58

59

58

60

59

60

59

60

59

60

62

22

58

2

58

11

58

11

59

11

59

58

59

6

59

11

2

11

10

(11 of 14)

UATA INTERFACE

ATA_VREF_H

ATA_CHRDY_H

ATA_DMARQ_H

ATA_INTRQ_H

ATA_D_00_H ATA_D_01_H ATA_D_02_H ATA_D_03_H ATA_D_04_H

ATA_D_06_H

ATA_D_05_H

ATA_D_07_H

ATA_D_09_H

ATA_D_08_H

ATA_D_11_H ATA_D_12_H

ATA_D_10_H

ATA_D_14_H

ATA_D_13_H

ATA_D_15_H

ATA_A_0_H

ATA_A_2_H

ATA_A_1_H

ATA_RST_L

ATA_WR_L ATA_RD_L

ATA_CS0_L ATA_CS1_L

ATA_DMACK_L

BI

OUT

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

PLACE CLOSE TO I2

UATA100 SERIES TERMINATION

Signal aliases required by this page:

BOM options provided by this page:

Power aliases required by this page:

Page Notes

(NONE)

(IDE_IORDY)

(IDE_DIOW_L)

(IDE_DIOR_L)

(IDE_CS3FX_L)

(NONE)

ELECTRICAL_CONSTRAINT_SET

SPACING

PHYSICAL

DIFFERENTIAL_PAIR

One resistor for each of:

- UATA_DD<15..0>(_R)

- UATA_DA<2..0>(_R)

- UATA_CS0_L(_R) (IDE_CS1FX_L)

NET_TYPE

33

MF-LF

402

5%

1/16W

21

R8161

22

MF-LF

402

5%

1/16W

21

R8164

22

MF-LF

402

5%

1/16W

21

R8163

22

1/16W

402

MF-LF

5%

21

R8162

33

MF-LF

402

5%

1/16W

12

R8160

5%

402

CERM

10pF

50V

2

1

C8166

82

MF-LF

402

5%

1/16W

21

R8166

5%

1/16W

82

MF-LF

402

21

R8167

82

MF-LF

402

5%

1/16W

21

R8165

MF-LF 402

1/16W

1%

1K

2

1

R8100

33

1/16W

5%

SM-LF

81

RP8150

5%

1/16W

33

SM-LF

72

RP8150

5%

1/16W

33

SM-LF

63

RP8150

5%

1/16W

33

SM-LF

54

RP8150

33

1/16W

5%

SM-LF

81

RP8151

5%

1/16W

33

SM-LF

63

RP8151

5%

1/16W

33

SM-LF

72

RP8151

33

5% 1/16W SM-LF

54

RP8151

5%

1/16W

33

SM-LF

81

RP8152

33

1/16W

5%

SM-LF

63

RP8152

33

1/16W

5%

SM-LF

81

RP8153

33

1/16W

5%

SM-LF

72

RP8152

5% 1/16W

33

SM-LF

54

RP8152

5% 1/16W

33

SM-LF

72

RP8153

5%

1/16W

33

SM-LF

63

RP8153

33

1/16W

5%

SM-LF

54

RP8153

5%

1/16W

33

SM-LF

81

RP8154

33

1/16W SM-LF

5%

63

RP8154

33

5%

SM-LF

1/16W

72

RP8154

5% 1/16W

33

SM-LF

54

RP8154

1/16W

5%

402

MF-LF

10K

2

1

R8151

OMIT

BGA

I2

AB8

AA9

AE6

AA8

AB1

Y9

AA7

AB7

AD1

AA6

AD4

AE2

AD2

AE1

AB4

AD8

AE8

AE7

AD7

AD5

AD6

AB5

AB6

AA4

AE3

AA5

AB2

AB3

AC1

U2100

0

1

2

3

6

5

4

7

10

9

8

11

14

13

12

15

0

1

2

6

64 63

7

64 63

7

64 63

7

64 63

7

64 63

7

64 63

7

64 63

7

64 63

7

I2 UATA Interface

SYNC_DATE=N/A

SYNC_MASTER=N/A

115

051-6929

C

81

UATA_DD_R<15..0>

UATA_DA_R<2..0>

UATA_DSTROBE_R

UATA_DSTROBE

UATA

UATA_CS1_L_R

UATA_HOST

UATA

UATA UATA

UATA_HSTROBE

UATA UATA

UATA_RESET_L

UATA UATA

UATA_INTRQ

UATA UATA

UATA_DMACK_L

UATA UATA

UATA_STOP

UATA_DMARQ

UATA UATA

UATA_HOST_R

UATAUATA

UATA_RESET_L_R

UATA_DSTROBE

UATA UATA

UATA_DSTROBE_R UATA_DMARQ_R

UATA UATA

UATA_DEV_R

UATA UATA

UATA_INTRQ_R

UATA_DEV_R

UATA

UATA_DA_R<2..0>

UATA

UATA_HOST

UATA

UATA_DSTROBE

UATA

UATA UATA

UATA_DD_R<7>

UATA_DD7

UATA_HSTROBE

UATA

UATA_HSTROBE_R

UATA

UATA UATA

UATA_DD_R<6..0>

UATA_DD

UATA UATA

UATA_CS1_L

UATA UATA

UATA_STOP_R

UATA_HOST

UATA UATA

UATA_DMACK_L_R

UATA_HOST_R

UATA UATA

UATA_CS0_L

UATA UATA

UATA_DA<2..0>

UATA_DD<15..0>

UATAUATA

UATA UATA

UATA_CS0_L_R

UATA_HOST

UATA

UATA_DD_R<15..8>

UATA_DD

UATA

=RP8154P3

=RP8151P3

=RP8150P1

=RP8151P5

=RP8151P6

=RP8151P7

=RP8151P8

=RP8150P5

=RP8150P6

=RP8150P7

=RP8150P8

=RP8150P3

=RP8150P4

=RP8150P2

=RP8151P1

UATA_HSTROBE

UATA_STOP

UATA_INTRQ

UATA_DMARQ

UATA_DMACK_L

UATA_RESET_L

UATA_CS1_L

=RP8154P5

=RP8154P6

=RP8154P7

=RP8154P8

=RP8153P5

=RP8153P6

=RP8153P7

=RP8153P8

=RP8152P5

=RP8152P6

=RP8152P7

=RP8152P8

UATA_HSTROBE_R

=RP8154P4

=RP8153P4

=RP8154P2

=RP8152P4

=RP8153P2

=RP8152P2

UATA_DMACK_L_R

UATA_CS1_L_R

=RP8154P1

=RP8153P3

=RP8153P1

=RP8152P3

=RP8152P1

UATA_RESET_L_R

UATA_INTRQ_R

UATA_DMARQ_R

UATA_STOP_R

UATA_DMACK_L_R

UATA_CS1_L_R

UATA_CS0_L_R

UATA_HSTROBE_R

UATA_STOP_R

UATA_RESET_L_R

UATA_DSTROBE_R

UATA_INTRQ_R UATA_DMARQ_R

=RP8151P2

=RP8151P4

I2_UATA_VREF

63

64

63

64

63

64

63

6

63

6

63

6

63

7

63

6

63

2

63

7

63

2

7

6

63

2

7

63

6

2

6

63

6

63

6

63

6

63

6

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Q41C/516S0335/M-ST-SM1-LF

ATA Connectors

Q16C/516S0357/M-ST-SM2-LF

NC

HDD CONNECTOR ODD CONNECTOR

CRITICAL

M-ST-SM2-LF

9

8

7

6

50

5

49 48 47 46 45 44 43 42 41 40

4

39 38 37 36 35 34 33 32 31 30

3

29 28 27 2625

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

J8200

CRITICAL

M-ST-SM2-LF

9

8

7

6

50

5

49 48 47 46 45 44 43 42 41 40

4

39 38 37 36 35 34 33 32 31 30

3

29 28 27 2625

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

J8250

805

MF-LF

1/8W

5%

0

2

1

R8255

5% 1/16W MF-LF 402

4.7K

2

1

R8212

10K

5% 1/16W MF-LF 402

NO STUFF

2

1

R8211

402

MF-LF

1/16W

5%

0

5V_HD_LOGIC

21

R8203

3V_HD_LOGIC

MF-LF

1/16W

5%

0

402

1 2

R8202

402

MF-LF

1/16W

5%

10K

NO STUFF

2

1

R8210

402

MF-LF

1/16W

5%

20K

2

1

R8200

402

MF-LF

1/16W

5%

10K

2

1

R8201

82

115

C

051-6929

SYNC_MASTER=N/A

SYNC_DATE=N/A

HDD/ODD Connectors

UATA_DASP_L

UATA_CS0_L

UATA_DASP_L UATA_CS1_L

UATA_PDIAG

UATA_DD<1>

UATA_DA<1>

UATA_STOP

UATA_DD<0>

UATA_DD<2>

UATA_DD<3>

UATA_DA<0>

UATA_DD<4>

UATA_DD<5>

UATA_DD<6>

UATA_DD<7>

UATA_INTRQ

UATA_DSTROBE

UATA_RESET_L

UATA_DD<13> UATA_DD<14>

UATA_HSTROBE

UATA_DA<2>

UATA_DD<12>

UATA_DD<15>

UATA_DMARQ

UATA_DMACK_L

UATA_DD<8> UATA_DD<9> UATA_DD<10> UATA_DD<11>

=PP5V_RUN_HDD

=PP3V3_RUN_HDD

UATA_RESET_L

UATA_DMACK_L

=PP5V_RUN_HDD

UATA_INTRQ

UATA_DD<15>

UATA_STOP

UATA_DA<2>

UATA_DD<8> UATA_DD<9>

UATA_DD<10> UATA_DD<11>

UATA_DD<12> UATA_DD<13>

UATA_DD<14>

=PP5V_RUN_ODD

UATA_DMARQ

UATA_DD<4>

UATA_DD<5>

UATA_CS0_L

UATA_DA<0>

UATA_HSTROBE

UATA_DD<0>

UATA_DD<1>

UATA_DD<2>

UATA_DD<3>

UATA_DD<6>

UATA_DD<7>

=PP3V3_RUN_HDD

UATA_DSTROBE

MIN_NECK_WIDTH=0.15 mm

MIN_LINE_WIDTH=0.25 mm

VOLTAGE=5V

PP3V3R5V_RUN_HDD_LOGIC

PP5V_RUN_ODD

VOLTAGE=5V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

UATA_DA<1> UATA_PDIAG

UATA_CS1_L

64

63

64

63

64

63

64

63

64

63

64

63

64

63

64

63

64

63

64

63

64

63

64

7

63

7

63

7

63

7

63

7

63

7

10

64

63

10

63

7

63

7

10

63

7

63

7

64

63

7

63

64

6

64

7

64

6

7

6

7

6

7

6

7

6

7

10

7

6

7

6

7

6

7

6

10

7

6

64

7

(12 of 14)

ETHERNET INTERFACE

ETH_GREFCLK_H

ETH_CRS_H

ETH_RXER_H

ETH_RXDV_H

ETH_RXD_7_H

ETH_RXD_6_H

ETH_RXD_5_H

ETH_RXD_2_H

ETH_RXD_1_H

ETH_RXCLK_H

ETH_RXD_0_H

ETH_TXCLK_H

ETH_TXEN_H

ETH_TXD_6_H ETH_TXD_7_H

ETH_TXD_5_H

ETH_TXD_4_H

ETH_TXD_2_H

ETH_TXD_1_H

ETH_TXD_0_H

VDD25_1 VDD25_2

VDD25_6

VDD25_5

VDD25_4

VDD25_0

ETH_MDC_H

ETH_MDIO_H

ETH_GTXCLK_H

ETH_TXER_H

ETH_TXD_3_H

ETH_COL_H

VDD25_3

ETH_RXD_3_H

ETH_RXD_4_H

GPIO_16_H

EXT_05_H

ETH_PVT_H

G

SD

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Page Notes

series termination. Any

non-shared schematic page.

the PHY page or a non-shared

unique ECSet name to allow this.

lengthen net by ~250ps. Net has a

violation on I2. May want to

pull-up or pull-down resistor.

NOTE: ENET_RX_DV has a hold spec

NOTE: All I2 GPIOs should have a

BOM options provided by this page:

NOTE: This page does not provide any

termination, including clock signals, should be provided by

(NONE)

This page does not provide a

provided by the PHY page or a

schematic page.

resistor for GPIO 16. It must be

- =PP2V5R3V3_PWRON_I2_ENET

Signal aliases required by this page:

Power aliases required by this page:

These GPIOs are referenced

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

PHYSICAL

Signal

to the Ethernet I/O rail

Signal

SPACING

DIFFERENTIAL_PAIR

1uF

CERM

10%

6.3V

402

2

1

C8453

I2

OMIT

BGA

Y6

Y3

W14

V13

U9

U6

U3

AA1

Y1

T8

T7

T6

T5

T4

V5

V6

V7

V4

V8

W7

W1

W9

T3

T1

V1

V3

U1

V2

W3

W2

W8

U10

W6

W4

V9

AA2

W5

AA3

U2100

1uF

CERM 402

10%

6.3V

2

1

C8456

402

CERM

1uF

6.3V

10%

2

1

C8455

1uF

402

CERM

10%

6.3V

2

1

C8454

5% 1/16W MF-LF 402

1.5K

2

1

R8405

402

MF-LF

1/16W

5%

10K

2

1

R8410

MF-LF 402

1/16W

5%

10K

2

1

R8420

1/16W MF-LF

5%

0

402

NO STUFF

21

R8421

SOT-363

2N7002DW-X-F

1

2

6

Q8420

1uF

CERM 402

10%

6.3V

2

1

C8452

CERM 402

10%

6.3V

1uF

2

1

C8451

402

CERM

1uF

10%

6.3V

2

1

C8450

603

X5R

6.3V

10uF

20%

2

1

C8459

1K

1%

MF-LF

1/16W

402

2

1

R8400

SYNC_DATE=N/A

SYNC_MASTER=N/A

I2 Ethernet Interface

051-6929

C

115

84

ENET_RX_CLK125M

ENET_CLK125M_RX

CLOCKCLOCK

ENET_CLK25M_TX

CLOCK CLOCK

ENET_RX_CLK25M

ENETENET

ENET_RXD<3..0>

ENET_RXD3_0

=PP2V5R3V3_PWRON_I2_ENET

ENET_TXD_R<2>

ENET_TXD_R<0> ENET_TXD_R<1>

ENET_RXD<1>

ENET_CRS

ENET_COL

ENET_RXD<7>

ENET_RXD<3>

ENET_CLK125M_RX

ENET_CLK25M_TX

ENET_RXD<6>

ENET_RX_DV ENET_RX_ER

ENET_CLK125M_GBE_REF

ENET_RXD<5>

ENET_RXD<4>

ENET_RXD<2>

ENET_RXD<0>

ENET_TXD_R<5>

ENET_TXD_R<4>

ENET_TX_EN_R

ENET_CLK125M_GTX_R

ENET_MDC

ENET_TXD_R<6> ENET_TXD_R<7>

ENET_TX_ER_R

ENET_TXD_R<3>

ENET_RESET_L

ENET_ENERGYDET

=PP2V5R3V3_PWRON_I2_ENET

ENET_RX_CTL

ENET

ENET_RX_ER

ENET

I2_ENET_PVT

I2_ENET_MDIO

ENET_MDIO

ENET_GBE_REF

ENET_CLK125M_GBE_REF

CLOCK CLOCK

ENET_CLK125M_GTX_R

CLOCK CLOCK

ENET_TX_CLK

ENETENET

ENET_RXD<7..4>

ENET_RXD7_4

ENETENET

ENET_RX_DV

ENET_TXD3_0

ENET_TXD_R<3..0>

ENETENET

ENET_TXD_R<7..4>

ENET ENET

ENET_TXD7_4

ENET_TX_EN

ENET_TX_EN_R

ENET ENET

ENET_TX_ER

ENET_TX_ER_R

ENET ENET

ENETENET

ENET_COL

ENET_RX_CTL

ENETENET

ENET_CRS

ENET_MDC

ENETENET

ENET_MDC

ENET_MDIO

ENETENET

ENET_MDIO

ENET ENET

I2_ENET_MDIO

=PP3V3_VESTA

67

65

66

65

11

65

65 11

11

65

11

65

11

65

66

11

65

11

65

66

11

65

11

18

11

9

10

11

9

11

9

11

9

11

65

9

11

10

9

65

9

11

65

9

11

9

65

10

INTR*/ENERGYDET

GTXCLK

XTALGND BIASGND PLLGND1

CLK125

TXD[4]

TXD[3]

TXD[2]

TXD[1]

TXD[0]

MDIO

MDC

TX_ER

TX_EN

TXD[7]

TXD[6]

TXD[5]

LOWPWR

TXC

RXC

RXD[7]

RX_DV RX_ER

XTALO

XTALI

ER

HUB

MANMS

SPD0

F1000

FDX

RGMIIEN

EN_10B

PHYA[4]

PHYA[3]

PHYA[2]

PHYA[1]

PHYA[0]

TVCO

TEST[0] TEST[1]

COL CRS

RBC0

TRD+[0] TRD-[0]

TRD+[1] TRD-[1]

TRD+[2] TRD-[2]

TRD-[3]

TRD+[3]

RBC1

RXD[2] RXD[3] RXD[4] RXD[5] RXD[6]

RXD[1]

RXD[0]

SLAVE*/AN_EN

ACTLED*

XMTLED*

FDXLED*

LINK2*

LINK1*

QUALITY*/TXC_RXC_DELAY

RDAC1

PLLVDD1

BIASVDD1XTALVDD1

VESTA ENET

2 OF 3

OUT

OUT OUT OUT OUT OUT OUT OUT OUT

OUT OUT

OUT

IN IN IN IN IN IN IN IN

IN IN

IN

BI

BI BI

G

D

S

IN

G

D

S

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NC?

DIFFERENTIAL_PAIR

I2BORG SPECIFIC

Place close to link

(6 nets)

Sets manual master/slave configuration enable bit

Sets Hub/DTE bit and master/slave configuration value bit

1 - Rise time approx. 5 ns 0 - Rise time approx. 4 ns

(Internal Pull-down)

ER - Edge Rate Select

(Internal Pull-down)

HUB - Repeater Select

’=VESTA_’ should be replaced with ’ENET_’

Place close to PHY

Not convention-compliant,

Put crystal circuit close to PHY

CRYSTAL LOAD CAPACITANCE IS 20PF

NC?

ESR < 0.5 ohms

PLACE RESISTORS CLOSE TO PHY

NET_TYPE

(PROVIDED BY LINK PAGE)

ELECTRICAL_CONSTRAINT_SET

(PROVIDED BY LINK PAGE)

Net Spacing Type: ENET_MDI

MANMS - Manual Master/Slave Configuration Select

1 - If RGMII Mode enabled, RXC clock and

(Internal Pull-down)

TXC_RXC_DELAY

0 - No clock delay

(Internal Pull-up)

0 - Auto-negotiation disabled

1 - Auto-negotiation enabled

0 1 X Force 1000BASE-T (test use only)

1 1 1 Auto-negotiate advertise 1000BASE-T

1 1 0 Auto-negotiate advertise 10/100/1000BASE-T

1 0 1 Auto-negotiate advertise 10/100BASE-TX

1 0 0 Auto-negotiate advertise 10BASE-T

0 0 1 Force 100BASE-TX

(Internal Pull-down)

0 - GMII/RGMII Mode

(Internal Pull-down)

RGMIIEN - RGMII Enable

1 - RGMII/RTBI Mode 0 - GMII/TBI Mode

(Internal Pull-up)

Sets manual duplex mode bit

FDX - Full-Duplex Select

Vesta Config Straps:

1 - TBI/RTBI Mode

EN_10B - TBI Interface Select

PHYA<4..0> - PHY Address Select (Internal Pull-downs)

F1000 - Speed Select

(Internal Pull-up)

See table below

AN_EN F1000 SPD0 Description

See table below

0 0 0 Force 10BASE-T

SPD0 - Speed Select

(Internal Pull-down)

SPACING

Power aliases required by this page:

PHYSICAL

Page Notes

- =PP2V5_ENETFW

- =PP1V2_ENETFW

NOTE: Target differential impedance for

Signal aliases required by this page:

BOM options provided by this page:

ENET data pairs is 100 ohms.

Line To Line: 0.38 mms Length Tolerance: 50 mils Primary Max Sep: 5 mils

Secondary Length: 500 mils

Secondary Max Sep: 100 mils

(NONE)

AN_EN - Auto-Negotiation Select

GTXCLK are delayed by 1.9 ns

Circuit ensures Vesta LOWPWR signal is low when

assert when ethernet link is unpowered.

Vesta RESET* is asserted, and allows LOWPWR to

RC time constant not critical. R < 3.9K to counter internal pulldown.

Vesta Ethernet LowPwr

Disables Vesta Ethernet Circuit

1/16W

1%

402

MF-LF

49.9

2

1

R8592

49.9

1/16W

1%

402

MF-LF

2

1

R8593

1/16W

1%

402

MF-LF

49.9

2

1

R8590

1/16W

1%

402

MF-LF

49.9

2

1

R8591

0

MF-LF

402

5%

1/16W

21

R8562

8X4.5MM-SM2

25.0000M

CRITICAL

21

Y8500

49.9

MF-LF 402

1% 1/16W

2

1

R8596

49.9

MF-LF 402

1% 1/16W

2

1

R8594

1/16W

1%

402

MF-LF

49.9

2

1

R8597

49.9

MF-LF

402

1%

1/16W

2

1

R8595

16V

20%

402

CERM

0.01UF

2

1

C8590

16V

20%

402

CERM

0.01UF

2

1

C8594

16V

20%

402

CERM

0.01UF

2

1

C8596

0

MF-LF

402

5%

1/16W

21

R8561

MF-LF

1/16W

0

402

5%

21

R8560

1.24K

MF-LF

402

1%

1/16W

2

1

R8509

1/16W

5%

402

MF-LF

0

2

1

R8501

0.01UF

CERM 402

20% 16V

2

1

C8592

50V

20%

402

CERM

0.001uF

2

1

C8530

SM

FERR-EMI-600-OHM

21

L8530

10uF

6.3V

20%

1206-1

CERM

2

1

C8531

0.1uF

10V

20%

402

CERM

2

1

C8510

50V

20%

402

CERM

0.001uF

2

1

C8520

6.3V

20%

603

X5R

10UF

2

1

C8521

OMIT

FBGA-200

BCM5462

N1

P2

N2

P3

B12

C4

B4

A5

B5

C5

E6

D6

C7

C6

B6

A6

N3

R10

R11

R9

R8

R6

R7

R5

R4

M5

M4

K5

C10

C2

D2

D3

D4

D5

E3

E4

E5

F5

F4

C1

B8

R1

B3

A3

A8

M1

M2

L1

L2

L3

L4

L5

G2

G1

D9

H5

B11

A10

D10

A9

A4

B10

C8 K4

H3

K3

G3

F3

D1

P1

R2

A11

U8500

50V

5%

402

CERM

33pF

2

1

C8500

50V

5%

402

CERM

33pF

2

1

C8501

402

0

MF-LF

5%

1/16W

21

R8569

11

65

11

FERR-EMI-600-OHM

SM

21

L8510

FERR-EMI-600-OHM

SM

21

L8520

67 66

20%

402

CERM

10V

0.1uF

2

1

C8580

SOT-363

2N7002DW-X-F

4

5

3

Q8580

5%

402

MF-LF

1/16W

1K

2

1

R8580

18

2N7002DW-X-F

SOT-363

1

2

6

Q8580

85

115

051-6929

C

Vesta Ethernet PHY

SYNC_MASTER=N/A

SYNC_DATE=N/A

VESTA_RESET

VESTA_ENET_LOWPWR

=PP3V3_VESTA

=PP3V3_ENET

=ENET_TXD<3>

=ENET_TXD<5>

ENET_CLK125M_GTX

ENET_CLK125M_RX_R

CLOCKCLOCK

XTALXTAL

VESTA_CLK25M_XTAL

VESTA_CLK25M_XTALI

VESTA_CLK25M_XTALO_R

XTALXTAL

ENETCONN_3_P

ENETCONN_3

ENETCONNENETCONNENETCONN

XTALXTAL

VESTA_CLK25M_XTALO

ENETCONN_3_N

ENETCONN_3

ENETCONNENETCONNENETCONN

ENETCONN_2_P

ENETCONN

ENETCONN_2

ENETCONNENETCONN

CLOCKCLOCK

ENET_CLK25M_TX_R

ENETCONN

ENETCONN_0_N

ENETCONN_0

ENETCONNENETCONN

ENETCONN_1_N

ENETCONN

ENETCONN_1

ENETCONNENETCONN

=PP1V2_ENETFW

=PP2V5_ENETFW

ENET_MDI3ENET_MDI2ENET_MDI1ENET_MDI0

VESTA_RDAC1_PD

TP_VESTA_ACTLED_L

TP_VESTA_XMTLED_L

TP_VESTA_FDXLED_L

TP_VESTA_LINKSPD2_L

TP_VESTA_LINKSPD1_L

=ENET_RXD_R<5>

=ENET_RXD_R<3>

=ENET_RXD_R<0>

TP_VESTA_RBC1

TP_VESTA_RBC0

TP_VESTA_TEST<0> TP_VESTA_TEST<1> TP_VESTA_TVCO

TP_VESTA_ER

TP_VESTA_HUB

TP_VESTA_MANMS

TP_VESTA_F1000 TP_VESTA_SPD0

TP_VESTA_RGMIIEN TP_VESTA_FDX

TP_VESTA_PHYA<4>

TP_VESTA_EN_10B

TP_VESTA_PHYA<3>

TP_VESTA_PHYA<1>

TP_VESTA_AN_EN TP_VESTA_TXC_RXC_DELAY

=ENET_RXD_R<6>

=ENET_RX_DV_R

=ENET_COL_R

=ENET_TXD<4>

=ENET_TXD<6>

=ENET_TX_EN

ENET_CLK125M_GTX_R

VESTA_CLK25M_XTALO_R

VESTA_CLK25M_XTALO

VESTA_CLK25M_XTALI

=ENET_TXD<7>

=ENET_TX_ER

PP1V2_VESTA_PLLVDD1

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

VOLTAGE=1.2V

=ENET_RXD_R<1> =ENET_RXD_R<2>

TP_VESTA_PHYA<0>

TP_VESTA_PHYA<2>

ENETCONN_1_P

ENETCONN_1

ENETCONNENETCONNENETCONN

CLOCK CLOCK

ENET_CLK125M_GBE_REF_R

ENETCONN_0

ENETCONN

ENETCONN_0_P

ENETCONNENETCONN

ENETCONN_3_P

ENETCONN_0_P

ENETCONN_2_P

ENETCONN_1_N

ENETCONN_1_P

ENETCONN_0_N

ENETCONN_3_N

ENETCONN_2_N

=VESTA_ENERGYDET

=VESTA_MDIO

=VESTA_MDC

=ENET_TXD<0>

=ENET_CRS_R

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=2.5V

PP2V5_VESTA_BIASVDD1

=ENET_RX_ER_R

=ENET_RXD_R<7>

=ENET_RXD_R<4>

ENET_CLK125M_RX_R =VESTA_CLK125M_RX

=VESTA_CLK25M_TX

ENET_CLK125M_GBE_REF_R

ENET_CLK25M_TX_R

=VESTA_CLK125M_GBE_REF

PP2V5_VESTA_XTALVDD1

VOLTAGE=2.5V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

ENETCONN_2_N

ENETCONN_2

ENETCONNENETCONNENETCONN

=ENET_TXD<1> =ENET_TXD<2>

67 65 18

67

69

67

10

66

10

2

66

2

66

1000PF, 2000VSHIELD

PRIMARY

ENET_CTAP

MDI_2-

MDI_3-

MDI_3+

MDI_1-

MDI_1+

MDI_0-

MDI_0+

MDI_2+

ENET_CTAP

CHIP SIDE

RJ45

75 OHM

1CT:1CT

J3

J2

J1

J5 J6 J7 J8

J4

SECONDARY

CABLE SIDE

RJ45

75 OHM

1CT:1CT

G

D

S

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

PLACE CAPS AT CONNECTOR PINS 5 & 6

CERM 402

1uF

10%

6.3V

C8603

CERM 402

1uF

10%

6.3V

C8602

CERM 402

1uF

10%

6.3V

C8601

402

CERM

1uF

10%

6.3V

C8600

CRITICAL

F-RT-TH

MJRR0076

9

8

7

6

5

4

3

2

10

1

14

13

12

11

J8600

MF-LF

402

5%

1/16W

100K

2

1

R8621

NO STUFF

603

MF-LF

5%

1/10W

0

21

R8620

2N7002DW-X-F

SOT-363

4

5

3

Q8420

SI6467BDQ-E3

TSSOP

7632

4

851

Q8620

1000pF

402

X7R

25V

10%

21

C8620

Ethernet Connector

SYNC_DATE=N/A

SYNC_MASTER=N/A

051-6929

C

86

115

=PP2V5_ENET

VOLTAGE=2.5V MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

PP2V5_ENET_CTAP

ENET_CTAP_EN_L

=PP3V3_VESTA

ENETCONN_3_N

ENETCONN_3_P

ENETCONN_2_N

ENETCONN_1_N ENETCONN_2_P

ENETCONN_1_P

ENETCONN_0_N

ENETCONN_0_P

=GND_CHASSIS_ENET

66 65 18

10

66

2

FWR_PINT_L

FWR_D_1_H

FWR_D_0_H

FWR_D_2_H FWR_D_3_H FWR_D_4_H

FWR_D_6_H

FWR_D_5_H

FWR_D_7_H

FWR_CNTL_0_H FWR_CNTL_1_H

FWR_LREQ_H

FWR_LCLK_H

FWR_PCLK_H

FWR_PVT

FWR_LINKON_H

FWR_LPS_H

FW 800 SIGNALS

FIREWIRE INTERFACE

(13 of 14)

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

PHYSICAL

NET_TYPE

Page Notes

DIFFERENTIAL_PAIR

(NONE)

BOM options provided by this page:

(NONE)

Signal aliases required by this page:

(NONE)

Power aliases required by this page:

SYSCLK (Legacy)

49MHz

ELECTRICAL_CONSTRAINT_SET

SPACING

OMIT

BGA

I2

M9

K8

K7

K6

K5

M4

M5

J4

K2

N9

K3

K4

L1

M2

M3

M7

M8

U2100

1K

1% 1/16W

402

MF-LF

2

1

R8800

SYNC_DATE=N/A

SYNC_MASTER=N/A

I2 FireWire Interface

051-6929

C

115

88

I2_FW_PVT

FW_LINKON

FW_CLK98M_PCLK

FW_PINT

FW_CLK98M_LCLK_R

FW_D_R<5> FW_D_R<6>

FW_D_R<4>

FW_D_R<2>

FW_D_R<0> FW_D_R<1>

FW_PINT

FW FW

FW_PINT

FW_LCLK

CLOCK CLOCK

FW_CLK98M_LCLK_R

FW_LPS_R

FW_LREQ_R

FW_D_R<3>

FW_CTL_R<1>

FW_CTL_R<0>

FW_D_R<7>

FW_CLK98M_PCLK

CLOCK

FW_PCLK

CLOCK

FWFW

FW_LPS_R

FW_LREQ_R

FW_LREQ

FW FW

FW_D

FW_D_R<7..0>

FW FW

FW_CTL

FW_CTL_R<1..0>

FW FW

FW_LINKON

68

71

68

71

68

71

68

71

69

69 69

9

69

68

9

68

9

69

68

9

68

69

68

68 68

6

68

9

6

9

6

68

9

6

9

68

FAVDDLFAVDDMFAVDDH

TDBL[1] TDBL[2]

PLI_PCLK

TDBL[0]

TPBIAS[0]

TPAP[0] TPAN[0] TPBP[0] TPBN[0]

TPBIAS[1]

TPAP[1] TPAN[1] TPBP[1] TPBN[1]

TPAP[2] TPAN[2] TPBP[2] TPBN[2]

TPBIAS[2]

PLI_INT

PLI_LINK

SDC SDA

RDAC2

XTALVDD2

BIASVDD2

PLLVDD2

BIASGND PLLGND2

TEST_1394[0] TEST_1394[1] TVCO_24

XTALI_24 XTALO_24

CPS

ESDET1

ESDET0

ESDET2

PLI_LCLK

PLI_DATA[7]

PLI_DATA[0] PLI_DATA[1] PLI_DATA[2] PLI_DATA[3] PLI_DATA[4] PLI_DATA[5] PLI_DATA[6]

PLI_CTL[0]

PWR_CLASS

PLI_CTL[1]

PLI_LPS PLI_LREQ

LPWR_1394 DS_ONLY_EN0

3 OF 3

VESTA FW

IN

BI

IN IN

OUT

OUT OUT OUT

OUT

BI

BI BI BI

BI

BI BI BI

BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Put crystal circuit close to PHY

Place close to link

Place close to PHY

CRYSTAL LOAD CAPACITANCE IS 12PF

- =PP1V2_ENETFW

NET_TYPE

Vesta Config Straps:

DS_ONLY_EN12 - Port 1&2 Data/Strobe

1 - Port 0 Data/Strobe mode only

0 - Port 0 Bilingual mode

PORT1_ENABLE - Port 1 Enable

0 - Port 1 Disabled (saves power)

PORT2_ENABLE - Port 2 Enable

0 - Port 2 Disabled (saves power)

1 - Port 1 Enabled

(Internal Pull-up)

0 - Sets Power Class to 0x0

1 - Port 1&2 Data/Strobe mode only 0 - Port 1&2 Bilingual mode

DS_ONLY_EN0 - Port 0 Data/Strobe

(Internal Pull-down)

(Internal Pull-up)

PWR_CLASS - FireWire Power Class

1 - Sets Power Class to 0x4

1 - Port 2 Enabled

Signal aliases required by this page:

Power aliases required by this page:

- =PP2V5_ENETFW

- =PP3V3_ENETFW

(Int PU)

ESR < 0.5 ohms

(PROVIDED BY LINK PAGE)

PHYSICAL

DIFFERENTIAL_PAIR

ELECTRICAL_CONSTRAINT_SET

Page Notes

- =PPFW_PHY_CPS

- =PP3V3_FW

SPACING

(Int PD)

- NONE

BOM options provided by this page:

- VESTA_BILINGUAL_EN12 If stuffed, adds external pull-down

Net Spacing Type: FW_TP

See straps table for more information.

Primary Max Sep: 7.5 mils

NOTE: Target differential impedance for

Secondary Length: 500 mils

Secondary Max Sep: 100 mils

See straps table for more information.

- VESTA_PORT1_DISABLE

If stuffed, adds external pull-down to counter internal pull-up in Vesta.

to counter internal pull-up in Vesta.

If stuffed, adds external pull-down

Line To Line: 0.38 mms Length Tolerance: 100 mils

- VESTA_PWR_CLASS_0

to counter internal pull-up in Vesta.

FW data pairs is 110 ohms.

- VESTA_PORT2_DISABLE

See straps table for more information.

counter internal pull-down in Vesta.

If stuffed, adds external pull-up to

See straps table for more information.

to counter internal pull-up in Vesta.

- VESTA_DS_ONLY_EN0

See straps table for more information.

MF-LF

402

5%

1/16W

22

21

R8902

1/16W

1%

402

MF-LF

2.0K

2

1

R8909

0.1uF

10V

20%

402

CERM

2

1

C8913

10V

20%

402

CERM

0.1uF

2

1

C8914

10V

20%

402

CERM

0.1uF

2

1

C8915

10V

20%

402

CERM

0.1uF

2

1

C8911

10V

20%

402

CERM

0.1uF

2

1

C8909

10V

20%

402

CERM

0.1uF

2

1

C8908

10V

20%

402

CERM

0.1uF

2

1

C8907

10V

20%

402

CERM

0.1uF

2

1

C8906

0.1uF

CERM

402

20% 10V

2

1

C8903

SM

FERR-EMI-600-OHM

21

L8901

50V

20%

402

CERM

0.001uF

2

1

C8901

6.3V

10uF

20%

1206-1

CERM

2

1

C8900

SM

FERR-EMI-600-OHM

21

L8900

50V 402

CERM

20%

0.001uF

2

1

C8905

6.3V

20%

603

X5R

10UF

2

1

C8904

SM

FERR-EMI-600-OHM

21

L8902

0

MF-LF 402

5% 1/16W

2

1

R8921

CRITICAL

24.576M

8X4.5MM-SM1

21

Y8920

1/16W

1%

402

MF-LF

1K

2

1

R8903

402

5% 1/16W

390K

MF-LF

2

1

R8914

FBGA-200

BCM5462

OMIT

N15

P13

P14

N13

H15

K15

M15

H14

K14

M14

H13

J13

L13

G15

J15

L15

G14

J14

L14

J4

J5

B14

B13

A14

H1

H2

R15

A12

P15

N14

E15

D12

D11

D14

D15

D13

G11

G12

G13

F13

F12

F11

E11

E12

E13

E14

J3

M12

M11

L12

L11

N12

N11

M10

L10

K13

K12

K11

C13

C12

C11

A13

R13

R14

P12

U8500

FERR-EMI-600-OHM

SM

21

L8906

FERR-EMI-600-OHM

SM

21

L8909

FERR-EMI-600-OHM

SM

21

L8913

6.3V

20%

603

X5R

10UF

2

1

C8917

6.3V

20%

603

X5R

10UF

2

1

C8918

6.3V

20%

603

X5R

10UF

2

1

C8919

CERM

402

5%

50V

18pF

2

1

C8920

CERM

402

5%

50V

18pF

2

1

C8921

10K

MF-LF 402

1% 1/16W

2

1

R8904

402

5% 1/16W MF-LF

1K

VESTA_BILINGUAL_EN12

2

1

R8931

1/16W

5%

402

MF-LF

1K

VESTA_PORT1_DISABLE

2

1

R8933

VESTA_PORT2_DISABLE

MF-LF 402

5% 1/16W

1K

2

1

R8935

1/16W

5%

402

MF-LF

10K

2

1

R8915

10K

MF-LF

402

5%

1/16W

2

1

R8916

22

402

5% 1/16W MF-LF

21

R8905

VESTA_DS_ONLY_EN0

MF-LF 402

5% 1/16W

1K

2

1

R8911

1/16W

5%

402

MF-LF

VESTA_PWR_CLASS_0

1K

2

1

R8912

68

9 6

71

9

71

9

9 6

71

9

71

9

68

70

70 69

MF-LF

402

1%

1/16W

1K

2

1

R8906

1/16W

1%

MF-LF

402

150

2

1

R8999

402

1/16W

1%

MF-LF

150

2

1

R8998

SYNC_DATE=N/A

SYNC_MASTER=N/A

Vesta FireWire PHY

051-6929

C

89

115

TP_VESTA_TVCO_24

FW_CLK98M_LCLK

FW_D<0>

VESTA_PORT1_DISABLE_L

VESTA_BILINGUAL_EN12_L

FW_LREQ

FW_D<5>

FW_D<4>

FW_D<6>

FW_D<3>

FW_TPA1

FW_TPA1_P

FW_TP

FW_TPA1

FW_TP

FW_TPB2_P

FW_TPFW_TP

FW_TPB2 FW_TPB2

VESTA_PWR_CLASS_MSB

FW_TPA2

FW_TPA2_N

FW_TPFW_TP

FW_TPA2

FW_TPFW_TP

FW_TPA2

FW_TPA2_P

FW_TPA0_P

FW_TPA1_P

FW_TPB1_N

FW_TPB1_P

FW_TPA1_N

FW_TPA2_P

FW_TPB2_N

FW_TPB2_P

FW_TPA2_N

FW_TPB0_P FW_TPB0_N FW_TPBIAS1

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm

FW_TPBIAS2

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm

FW_TPBIAS0

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm

FW_CLK98M_PCLK

MIN_LINE_WIDTH=0.5 mm

PP1V2_VESTA_PLLVDD2

MIN_NECK_WIDTH=0.25 mm

VOLTAGE=1.2V

=PP3V3_ENETFW

=PP2V5_ENETFW

=PP1V2_ENETFW

=PP3V3_FW

VOLTAGE=2.5V MIN_LINE_WIDTH=0.5 mm

PP2V5_VESTA_FAVDDM

MIN_NECK_WIDTH=0.25 mm

VESTA_PORT2_DISABLE_L

=PP1V2_ENETFW

FW_TPA0

FW_TPA0_N

FW_TP

FW_TPA0

FW_TP

FW_TPA0

FW_TPA0_P

FW_TP

FW_TPA0

FW_TP

FW_TPB0

FW_TP

FW_TPB0_P

FW_TP

FW_TPB0

FW_TPB0_N

FW_TP

FW_TPB0

FW_TP

FW_TPB1_P

FW_TPB1 FW_TPB1

FW_TPFW_TP

FW_TPB1

FW_TP

FW_TPB1_N

FW_TPB1

FW_TP

FW_TPB2

FW_TPB2_N

FW_TP FW_TP

FW_TPB2

VESTA_CLK24M_XTAL

XTALXTAL

VESTA_CLK24M_XTALI

XTALXTAL

VESTA_CLK24M_XTALO

XTALXTAL

VESTA_CLK24M_XTALO_R

CLOCK CLOCK

FW_CLK98M_PCLK_R

CLOCK

FW_CLK98M_LCLK

CLOCK

VESTA_DS_ONLY_EN0

VESTA_PORT1_DISABLE_L

VESTA_PORT2_DISABLE_L

=PP3V3_FW

=PPFW_PHY_CPS

FW_LINKON

FW_TPA1

FW_TP

FW_TPA1

FW_TP

FW_TPA1_N

FW_CLK98M_LCLK_R

FW_D<7>

TP_VESTA_TDBL<2>

TP_VESTA_TDBL<1>

TP_VESTA_TDBL<0>

VESTA_CPS

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

VOLTAGE=3.3V

PP3V3_VESTA_FAVDDH

FW_D<1> FW_D<2>

VESTA_DS_ONLY_EN0

FW_TPA0_N

=PP2V5_ENETFW

FW_PINT

VESTA_BILINGUAL_EN12_L

VESTA_PWR_CLASS_MSB

VESTA_CLK24M_XTALO

VESTA_CLK24M_XTALO_R

VESTA_CLK24M_XTALI

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=2.5V

PP2V5_VESTA_XTALVDD2

PP2V5_VESTA_BIASVDD2

VOLTAGE=2.5V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

VOLTAGE=1.2V

PP1V2_VESTA_FAVDDL

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

FW_CLK98M_PCLK_R

I2C_VESTA_SCL I2C_VESTA_SDA

VESTA_RDAC2_PD

FW_LPS

TP_VESTA_TEST_1394<1>

TP_VESTA_TEST_1394<0>

VESTA_LPWR_1394

FW_CTL<1>

FW_CTL<0>

69

70

69

70

69

70

66

69

66

70

69

70

66

69

10

69

10

69

10

69

10

69

SYM_VER-1

VP VGND

TPI#

TPO

TPI

TPO#

SYM_VER-2

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

DRAWING

514-0255

(GND_FW_PORT1_VG)

(GND_FW_PORT2_VG)

(PPFW_PORT2_VP)

PORT 1

BILINGUAL

(PPFW_PORT1_VP)

(FW_PORT1_BREF)

Page Notes

ESD Rail

"Snapback" & "Late VG" Protection

SPACING

Termination

PROVIDED

ELECTRICAL_CONSTRAINT_SET

BY

Place close to FireWire PHY

to apply to entire TPA/TPB XNets.

properly terminate unused signals.

connected to a beta-only device,

"Snapback" & "Late VG" Protection

appropriate connectors and/or to

assumed that FireWire PHY page will

AREF needs to be isolated from

1394b implementation based on Apple FireWire Design Guide (FWDG 0.6, 5/14/03)

provide the appropriate constraints

- _PP3V3_FW

- _GND_CHASSIS_FW_PORT2

(NONE)

- _GND_CHASSIS_FW_PORT3

BOM options provided by this page:

NOTE: FireWire TPA/TPB pairs are NOT constrained on this page. It is

necessary aliases to map the FireWire TPA/TPB pairs to their

NOTE: This page is expected to contain the

Cable Power

PORT 2

(TPA+)

(TPB+)

(TPA-)

(TPB-)

logic ground for speed signaling per 1394b V1.33

there is no DC path between them

When a bilingual device is

(to avoid ground offset issue)

all local grounds per 1394b spec

BREF should be hard-connected to and connection detection currents

NC

OUTPUT

INPUT

TPBTPB<R> TPB+

TPA<R>

TPA-

NC VG

1394A

Cable Power

VP

Signal aliases required by this page:

- _GND_CHASSIS_FW_PORT1

- _PPFW_PORT3

- _PPFW_PORT2

- _PPFW_PORT1

Power aliases required by this page:

DIFFERENTIAL_PAIR

PHYSICAL

NET_TYPE

PHY

PAGE

3rd TPA/TPB pair unused

TPA+

Q41C/514S0105/1394B-Q41

Q16C/514S0106/1394B

400-OHM-EMI

SM-1

21

L9090

402

MF-LF

1/16W

1%

604

21

R9090

SM

FERR-250-OHM

21

L9020

50V

0.001uF

CERM

20%

402

2

1

C9024

1.5AMP-33V

SM-LF

21

F9020

BAV99DW-X-F

SOT-363

3

5

4

DP9020

0.001uF

402

CERM

50V

20%

2

1

C9021

0.01uF

20% CERM

50V 603

2

1

C9025

20% 16V

CERM

402

0.01uF

2

1

C9026

SOT-363

BAV99DW-X-F

3

5

4

DP9021

20%

0.001uF

402

CERM

50V

2

1

C9023

SOT-363

BAV99DW-X-F

6

2

1

DP9020

20% 50V

CERM

402

0.001uF

2

1

C9020

SOT-363

BAV99DW-X-F

6

2

1

DP9021

402

50V

20%

CERM

0.001uF

2

1

C9022

0.01uF

20% 16V

402

CERM

NO STUFF

2

1

C9019

FERR-250-OHM

SM

21

L9010

402

CERM

50V

20%

0.001uF

2

1

C9014

BAV99DW-X-F

SOT-363

3

5

4

DP9010

CERM

402

0.001uF

50V

20%

2

1

C9011

0.01uF

402

CERM

20%

NO STUFF

16V

2

1

C9018

NO STUFF

20%

CERM

0.01uF

50V 603

2

1

C9017

603-1

X7R

50V

0.1uF

10%

2

1

C9015

0.01uF

16V

20% CERM

402

NO STUFF

2

1

C9016

1M

1/16W 402

5% MF-LF

2

1

R9011

SOT-363

BAV99DW-X-F

3

5

4

DP9011

0.001uF

402

CERM

50V

20%

2

1

C9013

SOT-363

BAV99DW-X-F

6

2

1

DP9010

CERM

402

0.001uF

50V

20%

2

1

C9010

SOT-363

BAV99DW-X-F

6

2

1

DP9011

0.001uF

402

CERM

50V

20%

2

1

C9012

2012H

90-OHM-300mA

4

32

1

FL9010

2012H

90-OHM-300mA

4

32

1

FL9011

1uF

CERM 402

6.3V

10%

2

1

C9060

6.3V CERM 402

1uF

10%

2

1

C9050

56.2

1/16W

1% MF-LF

402

2

1

R9061

56.2

402

MF-LF

1%

1/16W

2

1

R9060

56.2

402

MF-LF

1/16W

1%

2

1

R9063

1/16W

402

MF-LF

1%

56.2

2

1

R9062

56.2

1% 1/16W MF-LF 402

2

1

R9051

56.2

1% 1/16W MF-LF

402

2

1

R9050

56.2

1% 1/16W MF-LF 402

2

1

R9053

56.2

1% 1/16W MF-LF

402

2

1

R9052

MF-LF

4.99K

402

1/16W

1%

2

1

R9064

270pF

402

CERM

25V

5%

2

1

C9064

402

4.99K

1% 1/16W MF-LF

2

1

R9054

25V

5%

CERM

402

270pF

2

1

C9054

1K

5%

402

MF-LF

1/16W

2

1

R9070

F-RT-TH-LF

CRITICAL

1394A

1

2

5

6

3

4

10

987

J9020

260-OHM-330MA

SM1

3

21

4

FL9020

260-OHM-330MA

SM1

3

21

4

FL9021

SM

21

XW9070

SM

21

XW9071

402

CERM

10V

20%

0.1uF

2

1

C9090

0.001uF

10% 50V CERM 402

2

1

C9092

BZX84C2V7-X-F

SOT23

3

1

D9090

0.1uF

20% 10V CERM 402

2

1

C9091

F-RT-SM-LF

CRITICAL

1394B

9

8 7 6

5 4

3

2

15

14

13

12

11

10

1

J9010

402

MF-LF

1/16W

5%

0

EMI

21

R9099

SYNC_MASTER=N/A

SYNC_DATE=N/A

FireWire Ports

115

90

C

051-6929

ABBREV=DRAWING

TITLE=PLASMA

FW_PORT2_TPB_N

MAKE_BASE=TRUE

FW_PORT2_TPB_P

MAKE_BASE=TRUE

FW_PORT2_TPA_N

MAKE_BASE=TRUE

FW_PORT2_TPA_P

MAKE_BASE=TRUE

FW_PORT1_TPB_N

MAKE_BASE=TRUE

FW_PORT1_TPB_P

MAKE_BASE=TRUE

FW_PORT1_TPA_N

MAKE_BASE=TRUE

FW_PORT1_TPA_P

MAKE_BASE=TRUE

FW_TPBIAS2

FW_TPA2_P

FW_TPA2_N

NO_TEST=YES

NC_FW_TPA_N2

MAKE_BASE=TRUE

NC_FW_TPA_P2

MAKE_BASE=TRUE NO_TEST=YES

MAKE_BASE=TRUE

NC_FW_TPBIAS2

NO_TEST=YES

=GND_CHASSIS_FW_EMI

=GND_CHASSIS_FW_PORT1

FW_PORT1_TPA_P_FL

FW_PORT1_AREF

FW_PORT1_TPA_N_FL

FW_PORT1_TPB_P_FL

FW_PORT1_TPB_N_FL

NO_TEST=YES

FW_TPB2_P

NO_TEST=YES

FW_TPB2_N

FW

FW_PORT1_TPA_FL

FW

FW_PORT1_TPA_N_FL

FW

FW_PORT1_TPB_FL

FW

FW_PORT1_TPB_P_FL

FW_TPB2_PD

=PPFW_PORT1

FW_TPA0_C

MIN_NECK_WIDTH=0.25 mm

PPFW_PORT2_VP_F

VOLTAGE=33V MIN_LINE_WIDTH=0.5 mm

FW_PORT1_TPA_P

=PPFW_PORT2

FW_TPA1_C

FW_PORT1_TPA_N

FW_PORT2_TPA_N_FL

MIN_NECK_WIDTH=0.25 mm

PPFW_PORT2_VP

VOLTAGE=33V MIN_LINE_WIDTH=0.5 mm

FW_PORT2_TPB_N_FL

FW_PORT2_TPB_P_FL

PP3V3_FW_ESD

FW_PORT1_TPB_P

FW_PORT2_TPB_N

PP3V3_FW_ESD

FW_PORT2_TPB_P

FW_PORT2_TPA_N

FW_PORT2_TPA_P

FW_TPBIAS0

FW_TPBIAS1

FW_PORT1_TPB_N

FW

FW_PORT2_TPB_FL

FW

FW_PORT2_TPB_P_FL

FW

FW_PORT2_TPA_FL

FW

FW_PORT2_TPA_N_FL

FWFW

FW_PORT2_TPA_FL

FW_PORT2_TPA_P_FL

FW FW

FW_PORT1_TPA_FL

FW_PORT1_TPA_P_FL

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

PP3V3_FW_ESD

VOLTAGE=3.3V

PP3V3_FW_ESD_F

VOLTAGE=3.3V MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

=PP3V3_FW

FW

FW_PORT2_TPB_FL

FW

FW_PORT2_TPB_N_FL

FW

FW_PORT1_TPB_FL

FW

FW_PORT1_TPB_N_FL

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=33V

PPFW_PORT1_VP

FW_TPB0_N

FW_TPB0_P

FW_TPA0_N

FW_TPA0_P

FW_TPB1_N

FW_TPB1_P

FW_TPA1_N

FW_TPA1_P

=GND_CHASSIS_FW_PORT2

FW_PORT2_TPA_P_FL

LAST_MODIFIED=Fri Sep 9 13:40:50 2005

69

70

69

2

70

69

70

10

70

10

70

69

70

70 10

70

69

2

70

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Place series terminators approximately halfway between Vesta and NB.

(They should probably be slightly closer to Vesta than the NB.).

402

MF-LF

1/16W

5%

0

21

R9100

402

MF-LF

1/16W

5%

0

21

R9101

0

5% 1/16W MF-LF

402

21

R9103

0

5% 1/16W MF-LF

402

21

R9102

0

5% 1/16W SM-LF

54

RP9101

1/16W

5%

0

SM-LF

54

RP9100

0

5% 1/16W SM-LF

81

RP9101

1/16W

5%

0

SM-LF

63

RP9100

0

5% 1/16W SM-LF

81

RP9100

1/16W

5%

0

SM-LF

63

RP9101

1/16W

5%

0

SM-LF

72

RP9100

0

5% 1/16W SM-LF

72

RP9101

SYNC_DATE=N/A

SYNC_MASTER=N/A

051-6929

C

115

91

FireWire Series Term

=RP9101P8=RP9101P1

=RP9101P6=RP9101P3

=RP9100P6=RP9100P3

=RP9100P8=RP9100P1

FW_LREQ_R

FW_LREQ

FW_LPS_R

FW_LPS

FW_CTL_R<0>

FW_CTL<0>

FW_CTL_R<1>

FW_CTL<1>

=RP9101P5=RP9101P4

=RP9101P7=RP9101P2

=RP9100P5=RP9100P4

=RP9100P7=RP9100P2

68 69

6 6

9 9

6 6

(14 of 14)

USB INTERFACE

PLLUSB_VSSA

USB_VD_0_N

USB_VD_0_P

PLLUSB_AVDD

USB_VD_1_N

USB_VD_1_P

USB_VD_2_P USB_VD_2_N

USB_VD_3_P USB_VD_3_N

USB_VD_4_N

USB_VD_4_P

USB_VD_5_P USB_VD_5_N

USB_VREF

USB_XTALOSC_HI USB_XTALOSC_LO

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Crystal load capacitance is 16pF

- =RP92xxPy (pinswappable USB pulldowns)

One pair for each port USB2_*<0..5>

USB2 data pairs is 90 ohms.

BOM options provided by this page:

- =PP3V3_PWRON_USB

Line To Line: 19.5 mils Length Tolerance: 50 mils Primary Max Sep: 7.5 mils Secondary Max Sep: 100 mils Secondary Length: 500 mils

Net Spacing Type: USB2

NOTE: Target differential impedance for

Signal aliases required by this page:

Power aliases required by this page:

Page Notes

DIFFERENTIAL_PAIR

SPACING

PHYSICAL

NET_TYPE

(USB2_I2_XTAL)

ELECTRICAL_CONSTRAINT_SET

(NONE)

Put crystal circuit close to I2

(USB2_I2_XTAL)

1uF

CERM

402

6.3V

10%

2

1

C9250

4.7

5%

MF-LF

402

1/16W

21

R9250

0

402

5% 1/16W MF-LF

2

1

R9221

30.0000M

CRITICAL

8X4.5MM-SM1

21

Y9220

22pF

5%

402

CERM

50V

2

1

C9220

22pF

50V

CERM

402

5%

2

1

C9221

1K

1% 1/16W

402

MF-LF

2

1

R9200

10M

402

MF-LF

1/16W

5%

NO STUFF

21

R9220

OMIT

I2

BGA

P10

N5

T9

R1

R2

R4

R3

N2

N1

N4

N3

N7

N6

R6

R7

R9

R8

U2100

SM-LF

5%

15K

1/16W

5

6

7

8

4

3

2

1

RP9210

SM-LF

1/16W

15K

5%

5

6

7

8

4

3

2

1

RP9211

1/16W

15K

5%

SM-LF

5

6

7

8

4

3

2

1

RP9212

402

CERM

10V

20%

0.1uF

2

1

C9251

SYNC_MASTER=N/A

SYNC_DATE=N/A

C

051-6929

92

115

I2 USB Interface

I2_CLK30M_USB2_XOUT

XTAL XTAL

USB2_I2_XTAL

XTALXTAL

I2_CLK30M_USB2_XOUT_R

USB2_I2_4

USB2_I2_N<4>

USB2USB2

USB2_4

USB2_I2_4

USB2_I2_P<4>

USB2USB2

USB2_4

USB2_I2_3

USB2_I2_N<3>

USB2USB2

USB2_3

USB2_I2_3

USB2_I2_P<3>

USB2USB2

USB2_3

=RP9212P5

=RP9212P6

=RP9212P7

=RP9212P8

=RP9211P5

=RP9211P6

=RP9211P7

=RP9211P8

=RP9210P5

=RP9210P6

=RP9210P7

=RP9210P8

USB2_I2_N<5>

USB2_I2_P<5>

USB2_I2_N<4>

USB2_I2_N<3>

USB2_I2_P<3>

USB2_I2_N<2>

USB2_I2_P<2>

USB2_I2_P<1> USB2_I2_N<1>

USB2_I2_P<0> USB2_I2_N<0>

I2_CLK30M_USB2_XOUT_R

USB2_I2_0

USB2_I2_N<0>

USB2USB2

USB2_0

USB2

USB2_I2_2

USB2_I2_P<2>

USB2_2

USB2

I2_CLK30M_USB2_XIN

XTAL XTAL

USB2_I2_1

USB2_I2_N<1>

USB2USB2

USB2_1

USB2_I2_0

USB2_I2_P<0>

USB2USB2

USB2_0

USB2_I2_1

USB2_I2_P<1>

USB2USB2

USB2_1

USB2_5

USB2_I2_5

USB2_I2_N<5>

USB2USB2

USB2_I2_5

USB2_I2_P<5>

USB2USB2

USB2_5

USB2_I2_2

USB2_I2_N<2>

USB2

USB2_2

USB2

USB2_I2_P<4>

PP1V5_PWRON_I2_PLLUSBAVDD

VOLTAGE=1.5V MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm

=PP1V5_PWRON_I2_USBPLL

I2_CLK30M_USB2_XOUT

I2_CLK30M_USB2_XIN

I2_USB2_VREF

72

11

6

11

6

11

6

11

72

11

72

6

11

6

11

10

72

DM1 DP1

DM2 DP2

RSDM2

RSDP1

RSDM1

RSDP2

AVDD

DM3 DP3

RSDM3

RSDP3

PPON1

OCI2

OCI1

OCI3 OCI4 OCI5

PPON2

PPON5

PPON4

PPON3

RSDM4

DM4 DP4

DM5 DP5

RSDP4

RSDM5

RSDP5

RREF

AVSS(R)

AVSS

NC1 NC2

XT1/SCLK

XT2

VDD

VSS

TABLE_5_ITEM

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

(USB2_NEC_N<2>)

USB2 data pairs is 90 ohms.

NOTE: Target differential impedance for

USB2_NEC

- =PP3V3_PWRON_USB2

Y9345 LOAD CAPACITANCE IS 16pF

Tie to GND at ball N11

DIFFERENTIAL_PAIR

SPACING

NET_TYPE

PHYSICAL

Page Notes

Signal aliases required by this page:

Power aliases required by this page:

Net Spacing Type: USB2

(NONE) BOM options provided by this page:

(USB2_NEC_N<1>) (USB2_NEC_P<1>)

(USB2_NEC_P<2>)

(USB2_NEC_N<3>) (USB2_NEC_P<3>)

ELECTRICAL_CONSTRAINT_SET

PROVIDED BY I2 PAGES

NC

(USB2_NEC_P<0>)

(USB2_NEC_N<0>)

402

20%

0.1uF

10V

CERM

USB2_NEC

2

1

C9337

402

1/16W

1%

MF-LF

USB2_NEC

36

21

R9304

1%

402

1/16W MF-LF

USB2_NEC

36

21

R9305

1/16W

1%

402

MF-LF

USB2_NEC

36

21

R9306

1%

1/16W

402

MF-LF

USB2_NEC

36

21

R9307

9.09K

402

1% 1/16W MF-LF

USB2_NEC

2

1

R9338

402

10V

CERM

0.1uF

20%

USB2_NEC

2

1

C9325

402

CERM

10V

20%

0.1uF

USB2_NEC

2

1

C9324

10V

0.1uF

20%

CERM

402

USB2_NEC

2

1

C9336

20% 10V

CERM

0.1uF

402

USB2_NEC

2

1

C9330

402

0.1uF

CERM

10V

20%

USB2_NEC

2

1

C9329

USB2_NEC

MF-LF

603

5%

0

1/10W

12

R9339

USB2_NEC

5% 1/16W

402

1.5K

MF-LF

2

1

R9341

USB2_NEC

FBGA-LF

CRITICAL

NEC_uPD720101_USB2

P8

L9

N2B2A2

B14

H14

N14

P10

N1

D8

F11

J11

G4

D12

H12

L12

M11

B13

N13

B1

L13

N8E2A3

A12

A13

P12

P3

D7H4G12

D13

F13

H13

J13

P2

C14

E14

G14

J12

K13

E13

F12

H11

K14

M14

P11

A9

C10

C11

A11

C12

B9

A10

B10

B11

B12

M6

P6

C13

E12

G13

J14

L14

D14

F14

G11

K12

M13

N11

M12

P13

N12

N10

U7500

1/16W

5%

100

402

MF-LF

USB2_NEC

1

2

R9345

22pF

5% CERM

402

50V

USB2_NEC

2

1

C9346

X5R

6.3V

10uF

20%

603

USB2_NEC

C9335

I30

I31

I32

I33

I34

I35

I36 I37

FERR-EMI-100-OHM

SM

USB2_NEC

21

L9335

I40

I41 I42

20% 10V

CERM

0.1uF

402

USB2_NEC

2

1

C9323

402

0.1uF

CERM

10V

20%

USB2_NEC

2

1

C9322

0.1uF

402

20% 10V

CERM

USB2_NEC

2

1

C9328

402

0.1uF

CERM

10V

20%

USB2_NEC

2

1

C9327

20% 10V

CERM

0.1uF

402

USB2_NEC

2

1

C9321

402

0.1uF

CERM

10V

20%

USB2_NEC

2

1

C9326

10K

5%

1/16W

402

MF-LF

USB2_NEC

1

2

R9310

USB2_NEC

MF-LF

603

4.7

5%

1/10W

21

R9335

10K

5% 1/16W SM-LF

USB2_NEC

5678

4321

RP9310

6.3V X5R

10uF

20%

603

USB2_NEC

2

1

C9320

USB2_NEC

5%

1/16W

1.5K

402

MF-LF

2

1

R9340

30.0000M

8X4.5MM-SM

CRITICAL

OMIT

21

Y9345

22pF

5%

50V

CERM

402

USB2_NEC

2

1

C9345

SM-LF

1/16W

15K

5%

USB2_NEC

5

6

7

8

4

3

2

1

RP9300

USB2_NEC

1/16W

15K

5%

SM-LF

5

6

7

8

4

3

2

1

RP9301

USB2_NEC

MF-LF

1/16W

1%

402

39.2

21

R9300

USB2_NEC

MF-LF

402

1/16W

1%

39.2

21

R9301

1%

402

MF-LF

1/16W

USB2_NEC

39.2

21

R9302

1%

1/16W

402

MF-LF

USB2_NEC

39.2

21

R9303

197S0087

1

CRITICAL

Y9345

XTAL,CER,30.0000MHZ,LW PROF,8X4.5MM,SMD

USB2_NEC

NEC USB2 Interface

SYNC_DATE=N/A

SYNC_MASTER=N/A

115

93

051-6929

C

USB_NEC_N<0>

USB2_NEC_N<0> USB2_NEC_P<0>

USB2_OC<1> USB2_OC<2>

NEC_CLK30M_XT1

=PP3V3_PWRON_USB2

USB2USB2

USB2_NEC_N<1>

USB2_NEC_1

USB2 USB2

USB2_NEC_N<0>

USB2_NEC_0

USB2 USB2

USB2_NEC_P<1>

USB2_NEC_1

USB2 USB2

USB2_NEC_P<0>

USB2_NEC_0

USB2USB2

USB2_NEC_N<3>

USB2_NEC_3

NEC_CLK30M_XT2_R

XTAL XTAL

NEC_CLK30M_XT2

XTAL XTAL

USB2_NEC_XTAL

NEC_CLK30M_XT1

XTAL XTAL

USB2 USB2

USB2_NEC_P<2>

USB2_NEC_2

USB2USB2

USB2_NEC_N<2>

USB2_NEC_2

USB2USB2

USB2_NEC_P<3>

USB2_NEC_3

NEC_NC2_PU

USB2_OC<3> USB2_OC<4>

NEC_CLK30M_XT2

NEC_NC1_PU

NEC_CLK30M_XT2_R

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

GND_NEC_AVSS_R

VOLTAGE=0V

TP_USB2_PWREN<0>

TP_USB2_PWREN<2>

USB2_OC<0>

TP_USB2_PWREN<4>

TP_USB2_PWREN<3>

TP_USB2_PWREN<1>

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=3.3V

PP3V3_PWRON_NEC_AVDD

NEC_RREF_PD

USB_NEC_P<3>

USB_NEC_N<3>

USB2_NEC_P<3>

USB2_NEC_N<3>

USB_NEC_P<2>

USB2_NEC_P<2>

USB_NEC_N<2>

USB_NEC_P<1>

USB2_NEC_N<2>

USB_NEC_N<1>

USB_NEC_P<0>

=RP9301P8 =RP9301P7 =RP9301P6 =RP9301P5

=RP9300P8 =RP9300P7 =RP9300P6 =RP9300P5

USB2_NEC_P<1>

USB2_NEC_N<1>

=PP3V3_PWRON_USB2

73

11

73

10

11

73

11

73

2

11

2

11

2

6

11

10

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

AUDIO BOARD & LEFT I/O

PLACE SHORTS AT POWER SUPPLY

NO STUFF

402

CERM

50V

20%

0.001uF

2

1

CA010

402

0.1uF

X5R

16V

10%

2

1

CA033

402

0.1uF

X5R

16V

10%

2

1

CA050

SM

21

XWA000

NO STUFF

402

CERM

50V

20%

0.001uF

2

1

CA011

CRITICAL

M-ST-SM2-LF

9

8

7

6

50

5

49 48 47 46 45 44 43 42 41 40

4

39 38 37 36 35 34 33 32 31 30

3

29 28 27 26 25

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

JA000

0.1uF

402

X5R

16V

10%

2

1

CA051

SM

21

XWA001

SM

21

XWA050

SM

21

XWA051

SM

21

XWA033

CASE-D2-LF

POLY

6.3V

150uF

20%

2

1

CA000

Audio Board Connector

SYNC_DATE=N/A

SYNC_MASTER=N/A

100 115

C

051-6929

AUDIO_GPIO_11

VOLTAGE=0V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

GND_AUDIO_AGND

GND_AUDIO_PGND

VOLTAGE=0V MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

=PP5V_PWRON_AUDIO_AVDD

=PP5V_PWRON_AUDIO_PVDD

=PP3V3_PWRON_AUDIO_AVDD

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=5V

PP5V_PWRON_AUDIO_PVDD

=PP5V_PWRON_LEFT_USB

AUDIO_SPDIF_RXERR_INT

MAKE_BASE=TRUE

AUDIO_EXT_MCLK_SEL

AUDIO_LO_DET_L

AUDIO_LO_OPTICAL_PLUG_L

=PP3V3_RUN_AUDIO

AUDIO_LI_DET_L

AUDIO_LI_OPTICAL_PLUG_L

=I2C_AUDIO_SDA

=I2C_AUDIO_SCL

I2S0_BITCLK

I2S0_SYNC

SYS_ADAPTER_ANALOG_AC_DET SYS_CHARGE_LED_L

I2S0_DEV_TO_SB_DTI

USB2_LEFT_PORT_N

USB2_LEFT_PORT_P

I2S0_SB_TO_DEV_DTO

I2S0_MCLK

AUDIO_SPDIFRX_RESET_L AUDIO_CODEC_RESET_L

AUDIO_I2S_DTIB_SEL AUDIO_SPKR_MUTE_L AUDIO_LO_MUTE_L

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

VOLTAGE=3.3V

PP3V3_PWRON_AUDIO_AVDD

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

VOLTAGE=5V

PP5V_PWRON_AUDIO_AVDD

22

10

22

10

22

8

7

12

24

22

11

7

22

7

10

7

6

7

6

7

TABLE_SPACING_ASSIGNMENT

TABLE_PHYSICAL_ASSIGNMENT

TABLE_SPACING_RULE

TABLE_PHYSICAL_RULE

TABLE_SPACING_RULE

TABLE_PHYSICAL_ASSIGNMENT

TABLE_SPACING_RULE

TABLE_PHYSICAL_RULE

TABLE_SPACING_RULE

TABLE_SPACING_ASSIGNMENT

TABLE_SPACING_RULE

TABLE_PHYSICAL_RULE

TABLE_SPACING_RULE

TABLE_PHYSICAL_RULE

TABLE_SPACING_RULE

TABLE_PHYSICAL_RULE

TABLE_SPACING_RULE

TABLE_PHYSICAL_RULE

TABLE_SPACING_RULE

TABLE_PHYSICAL_RULE

TABLE_SPACING_RULE

TABLE_PHYSICAL_RULE

TABLE_SPACING_RULE

TABLE_PHYSICAL_RULE

TABLE_SPACING_RULE

TABLE_PHYSICAL_RULE

TABLE_SPACING_RULE

TABLE_SPACING_ASSIGNMENT

TABLE_PHYSICAL_ASSIGNMENT

TABLE_PHYSICAL_RULE

TABLE_SPACING_RULE

TABLE_PHYSICAL_RULE

TABLE_SPACING_RULE

TABLE_PHYSICAL_RULE

TABLE_SPACING_RULE

TABLE_PHYSICAL_RULE

TABLE_SPACING_ASSIGNMENT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

TABLE_SPACING_RULE

TABLE_PHYSICAL_RULE

TABLE_SPACING_RULE

TABLE_PHYSICAL_RULE

TABLE_SPACING_ASSIGNMENT

TABLE_PHYSICAL_RULE

TABLE_SPACING_RULE

TABLE_PHYSICAL_RULE

TABLE_SPACING_RULE

FW_TP

I2S

ENETCONN

FW (FireWire Digital)

RAM

I2C

MaxBus

PCI

AUDIO

AGP

ENET (Ethernet Digital)

UATA

USB2

CLOCK

I2_FBCLK / XTAL

*

FW_SELF

FWFW

*

251 =STANDARD =STANDARD =STANDARD =STANDARD

0.25 MM

I2S

=STANDARD=STANDARDENET_SELF

*

=STANDARD =STANDARD =STANDARD =STANDARD

=STANDARD=STANDARD=STANDARD=STANDARD

*

MAXBUS 151

0.15 MM

=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF

USB2

*

=90_OHM_DIFF

*

UATA

=50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE

3.81 MM

=90_OHM_DIFF =90_OHM_DIFF=90_OHM_DIFF

USB2

*

501

0.50 MM

0.15 MM

*

=STANDARD =STANDARD =STANDARD =STANDARD

UATA

151

=STANDARD

=50_OHM_SE=50_OHM_SE=50_OHM_SE

PCI

*

201 =STANDARD =STANDARD0.2 MMRAM =STANDARD=STANDARD

*

**

I2_FBCLK

CLOCK

XTAL

CLOCK

*

0.25 MM

251

*

RAM_DIFF

2.5 MM

=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF

=50_OHM_SE =50_OHM_SE=50_OHM_SE=50_OHM_SE

RAM

*

RAM_DIFF

=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF

AUDIO

=50_OHM_SE =50_OHM_SE =50_OHM_SE

*

=50_OHM_SE

*

=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF

0.6 MM601 2.5 MM

AGP_STB

AGP

*

=STANDARD =STANDARD =STANDARD =STANDARD0.4 MM401

CLOCK

*

I2_FBCLK

FW_SELF

=STANDARD=STANDARD=STANDARD=STANDARD

*

=STANDARD =STANDARD

FW

0.2 MM201

*

=STANDARD =STANDARD =STANDARD =STANDARD

=50_OHM_SE

*

=STANDARD

=50_OHM_SE =50_OHM_SE

CLOCK

251 =STANDARD =STANDARD=STANDARD=STANDARD

*

CLOCK

0.25 MM

AGP

*

=STANDARD

=60_OHM_SE=60_OHM_SE=60_OHM_SE

CLOCK

* *

XTAL

SYNC_DATE=N/A

SYNC_MASTER=N/A

051-6929

C

115110

Spacing & Physical Constraints

FW

=50_OHM_SE=50_OHM_SE=50_OHM_SE

=STANDARD

*

=STANDARD=STANDARD=STANDARD=STANDARD

*

201 0.2 MMI2C

*

=STANDARD

=50_OHM_SE =50_OHM_SE =50_OHM_SE

I2C

*

ENET ENET

ENET_SELF

AUDIO

251

0.25 MM

=STANDARD =STANDARD =STANDARD =STANDARD

*

=STANDARD=STANDARD=STANDARDPCI

*

=STANDARD =STANDARD =STANDARD

=100_OHM_DIFF

*

AGP_STB

=100_OHM_DIFF =100_OHM_DIFF

=STANDARD

ENET

=STANDARD=STANDARD=STANDARD

*

201 0.2 MM =STANDARD

=50_OHM_SE

ENET

*

=STANDARD

=50_OHM_SE =50_OHM_SE

=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF

*

ENETCONN

=100_OHM_DIFF

FW_TP

501

*

0.50 MM 3.81 MM

=110_OHM_DIFF =110_OHM_DIFF=110_OHM_DIFF

MAXBUS

=50_OHM_SE=50_OHM_SE=50_OHM_SE

=STANDARD

*

=110_OHM_DIFF

FW_TP

*

=110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF

*

=50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE

I2S

=100_OHM_DIFF =100_OHM_DIFF=100_OHM_DIFF

3.81 MM0.50 MM

*

501

ENETCONN

TABLE_SPACING_RULE

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

TABLE_SPACING_RULE

TABLE_PHYSICAL_RULE

TABLE_SPACING_RULE

TABLE_PHYSICAL_RULE

TABLE_SPACING_RULE

TABLE_PHYSICAL_RULE

TABLE_SPACING_RULE

TABLE_PHYSICAL_RULE

TABLE_SPACING_RULE

TABLE_PHYSICAL_RULE

TABLE_SPACING_RULE

TABLE_PHYSICAL_RULE

DVO

S-VIDEO

THERM

LVDS

TMDS

VGA

=75_OHM_SE=75_OHM_SE=75_OHM_SE=75_OHM_SE

*

TV

=TV =TV =TV =TV

*

TV_CONN

=TV=TV=TV=TV=TV151

*

TV_CONN

=75_OHM_SE=75_OHM_SE=75_OHM_SE=75_OHM_SE=75_OHM_SE

*

151

TV

=75_OHM_SE=75_OHM_SE=75_OHM_SE=75_OHM_SE=75_OHM_SE

VGA

*

151

*

VGA_CONN

=VGA =VGA =VGA =VGA =VGA

*

VGA_CONN

=VGA =VGA =VGA =VGA

=75_OHM_SE=75_OHM_SE=75_OHM_SE=75_OHM_SE

VGA

*

=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF

TMDS

251

*

=100_OHM_DIFF

0.25 MM

111 115

C

051-6929

SYNC_MASTER=N/A

SYNC_DATE=N/A

Spacing & Physical Constraints 2

=100_OHM_DIFF=100_OHM_DIFF

TMDS

*

=100_OHM_DIFF=100_OHM_DIFF

TMDS_CONN

*

=TMDS =TMDS =TMDS =TMDS

TMDS_CONN

*

=TMDS =TMDS =TMDS =TMDS =TMDS=TMDS

LVDS

=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF

*

LVDS

=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF

*

151

0.25 MM

THERM

=100_OHM_DIFF =100_OHM_DIFF

* Y

251

0.25 MM

THERM

=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF

*

=50_OHM_SE=50_OHM_SE=50_OHM_SE

=STANDARD

*

DVO

=STANDARD=STANDARD=STANDARD=STANDARD

*

151

0.15 MM

DVO

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

112

*** Signal Cross-Reference for the entire design ***

1V5RUN_EN 16A6<> 26C6< 1V8RUN_EN_L 16A4<> 26B4<> 1V8_1V5PWRON_EN_L 26D4< 1V20_REF 12C7< 14C8< 1V65_REF 13A5< 1_5V_BOOST 16C6<> 1_5V_BST 16C5<> 1_5V_DH 16C6<> 1_5V_DL 16B6<> 1_5V_FB 16B7< 1_5V_ILIM 16C5<> 1_5V_LX 16B5<> 1_8V_BOOST 16C4<> 1_8V_BST 16C4<> 1_8V_DH 16C3<> 1_8V_DL 16B3<> 1_8V_FB 16B4< 1_8V_ILIM 16C5<> 1_8V_LX 16B3<> 1_8V_PVDD_STD 51C1< 2V5PWRON_EN_L 26D4< 2V5RUN_EN_L 17A5<> 26C6< 3V3RUN_EN_L 15B3<> 26C5< 3V_BG 15C4<> 3V_BOOST 15C4<> 3V_BOOST_ESR 15D3<> 3V_ITH 15C4<> 3V_ITH_RC 15C3< 3V_PMU_VTAP 14B3< 3V_RSNS 15D2< 3V_RUNSS 15C4< 3V_SNSM 15C4< 3V_SNSP 15C4< 3V_SW 15C4<> 3V_TG 15D4<> 3V_VOSNS 15C4<> 5V3V3PWRON_EN_L 26D6< 5V3VPWRON_EN_L_RC 15B6< 5VRUNHD_EN_L 15B5<> 26D5< 5VRUN_EN_L 15A5<> 26D5< 5VTPAD_EN_L 26D4< 5V_BG 15C5<> 5V_BOOST 15C5<> 5V_BOOST_ESR 15D6<> 5V_ITH 15C5<> 5V_ITH_RC 15C6< 5V_RSNS 15D7< 5V_RUNSS 15C5< 5V_SNSM 15C5< 5V_SNSP 15C5< 5V_SW 15C5<> 5V_TG 15C5<> 5V_VOSNS 15C5<> 1625_BG 14C5<> 1625_BST 14C5< 1625_BST_ESR 14C5<> 1625_COMP 13D2< 14C6< 1625_DIV 14C8< 1625_ENABLE 14D7<> 1625_ENABLE_L 14D7<> 1625_FCB 14C6< 1625_INTVCC 14C5<> 1625_RUNSS 14C6< 1625_SGND 14B7<> 1625_TG 14C5<> 1625_VFB 14B5<> 1625_VIN 14C6< 1625_VSW 14C4<> 1772_ACIN 13B5< 1772_ACOK_L 13B5<> 13C4<> 1772_BST 13B4<> 1772_BST_ESR 13C3< 1772_CCI 13B5<> 1772_CCS 13B5< 1772_CCV 13B5<> 1772_CCV_RC 13B5< 1772_CELLS 13B4< 1772_CLS 13A4< 1772_CSIN 13B4<> 1772_CSIP 13B4<> 1772_CSSN 13C5< 1772_CSSP 13C5< 1772_DCIN 13B5< 1772_DHI 13B4<> 1772_DLO 13B4<> 1772_DLOV 13B4<> 1772_GND 13A5<> 1772_ICHG 13B5<> 1772_ICTL 13B5<> 1772_IINP 13B5< 1772_LDO 13C4<> 1772_LX 13B4<> 1772_REF 13B5<> 1772_VCTL 13B5< 1778_BG 45C5<> 1778_BST 45C5<> 1778_BST_RC 45C4<> 1778_FCB 45C6< 1778_GND 45B6<> 1778_ION 45C5< 1778_ITH 45C6<> 1778_ITH_RC 2B5> 45C7< 1778_TG 45C5<> 1778_VFB 45C5< 1778_VRNG 2B5> 45C6< 3707_FCB 15C5< 3707_FSET 15C5< 3707_INTVCC 15D5<> 3707_SGND 15C7<> 3707_STBYMD 15C5<> =1V8_1V5PWRON_EN_L 16C8<> 26D3> =1V8_1V5PWRON_PGOOD 16C6> 26B8< =2V5PWRON_EN_L 17C7<> 26D3> =2V5PWRON_PGOOD 17C4> 26B8< =5V3V3PWRON_EN_L 15B6< 26D5> =5V3VPWRON_PGOOD 15C4<> 26B8< =5VPWRONTPAD_EN_L 15A8<> 26D3> =ADT7467_THERM_L 11B3> 27C2< =AGP_GPU_RESET_L 11C7> 44D4< =AGP_VREF 11C7> 44B2< =CLK33M_TBEN_SYNC 11D1> 21A5< 21D6> =CPU0_MAX1717_AB_SEL 11A3> 36A7< 36C7< =CPU0_VID_AB_SEL 11A3> 36D3<> =CPU_HRESET_L 11B3> 34A8< 34C6< 34D4< =ENET_COL_R 11A6> 66B3> =ENET_CRS_R 11A6> 66B3> =ENET_RXD_R<0> 66C3> =ENET_RXD_R<7..0> 11A6> =ENET_RXD_R<1> 66C3> =ENET_RXD_R<2> 66C3> =ENET_RXD_R<3> 66C3> =ENET_RXD_R<4> 66C3> =ENET_RXD_R<5> 66C3> =ENET_RXD_R<6> 66C3> =ENET_RXD_R<7> 66C3> =ENET_RX_DV_R 11A6> 66C3> =ENET_RX_ER_R 11A6> 66B3> =ENET_TXD<0> 66C6< =ENET_TXD<7..0> 11A6> =ENET_TXD<1> 66C6< =ENET_TXD<2> 66C6< =ENET_TXD<3> 66C6< =ENET_TXD<4> 66C6< =ENET_TXD<5> 66C6< =ENET_TXD<6> 66C6< =ENET_TXD<7> 66C6< =ENET_TX_EN 11A6> 66C6< =ENET_TX_ER 11A6> 66B6< =FTP_GND 7C5> 7C5> 7C7> 10D2> =FTP_SLEEP_LED 7C5> 30B3> =FWPWR_PWRON 18C8<> 26D3> =GND_CHASSIS_BATTCHGR_HOLE 2C2<> 2C4> =GND_CHASSIS_DVI1 2D4> 57D3<> =GND_CHASSIS_DVI2 2D4> 57C3<> =GND_CHASSIS_DVI3 2D4> 57C2< =GND_CHASSIS_DVI4 2D4> 57B2< =GND_CHASSIS_DVI_HOLE 2D2<> 2D4> =GND_CHASSIS_ENET 2D4> 67B5<> =GND_CHASSIS_FW_EMI 2D4> 70A1< =GND_CHASSIS_FW_HOLE 2D2<> 2D4> =GND_CHASSIS_FW_PORT1 2D4> 70C1<> =GND_CHASSIS_FW_PORT2 2D4> 70A2<> =GND_CHASSIS_INVERTER1 2D4> 56B3< =GND_CHASSIS_INVERTER2 2C4> 56A2< =GND_CHASSIS_INV_GND_CLIP 2C2<> 2D4> =GND_CHASSIS_LCD1 2D4> 56C5<>

=GND_CHASSIS_LCD2 2D4> 56C6< =GND_CHASSIS_LCD3 2D4> 56B6< =GND_CHASSIS_LCD4 2D4> 56A5<> =GND_CHASSIS_SLEEP_LED 2C4> 30A3< =GND_CHASSIS_TV 2D4> 57A7<> =GPUVCORE_PGOOD 26A8< 45C6> =GPU_AGP_VREF 11C7> 44B4< =I2C_ADT7467_SCL 8B1> 27C4< =I2C_ADT7467_SDA 8B1> 27C4<> =I2C_AUDIO_SCL 7A7> 8D1> 74C6<> =I2C_AUDIO_SDA 7A7> 8D1> 74C6<> =I2C_BATT_SCL 8B4> 12A5< =I2C_BATT_SDA 8B4> 12A5< =I2C_DS1775_SCL 7C5> 8B1> 30C5<> =I2C_DS1775_SDA 7C5> 8B1> 30C5<> =I2C_GPU_TMDS_SCL 8A5< 51B3<> =I2C_GPU_TMDS_SDA 8A5< 51B3<> =I2C_I2_NB_SCL 8C3< 22C2< =I2C_I2_NB_SDA 8C3< 22C2< =I2C_I2_SB_SCL 8D3< 22C2< =I2C_I2_SB_SDA 8D3< 22B2< =I2C_PMU_SCL 8C5< 25C5<> =I2C_PMU_SDA 8C5< 25C5<> =I2C_PMU_SMB_SCL 8B5< 25C5<> =I2C_PMU_SMB_SDA 8B5< 25C5<> =I2C_SI_M_SCL 8A4> 54B6< =I2C_SI_M_SDA 8A4> 54B6< =I2C_SI_S_SCL 8A4> 55B6< =I2C_SI_S_SDA 8A4> 55B6< =I2C_SODIMM_SCL 8C1> 40A6< 41A6< =I2C_SODIMM_SDA 8C1> 40A6< 41A6< =I2VCORE_PGOOD 20C4> 26B8< =I2_AGP_FBCLK_IN 21C5> 43A5< =I2_AGP_VREF 11C7> 43B5< =I2_MAXBUS_FBCLK_IN 21D1> 32A6< =I2_PCI_FBCLK_IN 21B5> 59A5< =I2_STOPCPU_L 11B3> 22A5< =I2_STOPXTAL_L 11B3> 22A5< =JTAG_BBANGER_TCK 9D8< 25B5<> =JTAG_BBANGER_TDI 9D8< 25B5<> =JTAG_BBANGER_TMS 9D8< 25B5<> =JTAG_BBANGER_TRST_L 9D8< 25C5<> =JTAG_CPU0_TCK 9D5> 34D6< =JTAG_CPU0_TDI 9D6> 34D6< =JTAG_CPU0_TDO 9D6< 34D6> =JTAG_CPU0_TMS 9D5> 34D6< =JTAG_CPU0_TRST_L 9D5> 34D6< =JTAG_I2_TCK 9B6> 22B5< =JTAG_I2_TDI 9C6> 22B5< =JTAG_I2_TDO 9C6< 22B2< =JTAG_I2_TMS 9B6> 22B5< =JTAG_I2_TRST_L 9B6> 22A5< =JTAG_VESTA_TCK 9A6> 18A6< =JTAG_VESTA_TDI 9A6> 18A6< =JTAG_VESTA_TDO 9A6< 18A6> =JTAG_VESTA_TMS 9A6> 18A6< =JTAG_VESTA_TRST_L 9A6> 18A6< =MAXBUS_CPU0_CLK 11D4> 33C1< 33D6> =PCI_AIRPORT_GNT_L 11D1> 60C3<> =PCI_AIRPORT_IDSEL 11C1> 60C7< =PCI_AIRPORT_INT_L 11C1> 60B3<> =PCI_AIRPORT_REQ_L 11D1> 60C5<> =PCI_AIRPORT_RESET_L 11C1> 60C3<> =PCI_CBUS_GNT_L 11C1> 61A7< =PCI_CBUS_IDSEL 11C1> 61B8< =PCI_CBUS_INT_L 11C1> 61A7<> =PCI_CBUS_REQ_L 11C1> 61A7> =PCI_CBUS_RESET_L 11C1> 61A7< =PCI_CLK33M_AIRPORT 11D1> 60B3<> 60D6> =PCI_CLK33M_CBUS 11C1> 61A7< 61D1> =PCI_CLK33M_USB2 11C1> 62B5< 62D6> =PCI_CLK33M_ZDBOUT_R<0> 11D4< 23B4> 23D6> =PCI_CLK33M_ZDBOUT_R<1> 11C4< 23B4> 23D6> =PCI_CLK33M_ZDBOUT_R<2> 11C4< 23B4> 23D6> =PCI_CLK33M_ZDBOUT_R<3> 11B4< 23B4> 23D6> =PCI_CLK33M_ZDB_IN 11D1> 23B5< 23D6> =PCI_USB2_GNT_L 11C1> 62B5< =PCI_USB2_IDSEL 11B1> 62B6< =PCI_USB2_INT_L 11B1> 62B7< =PCI_USB2_REQ_L 11C1> 62B5> =PCI_USB2_RESET_L 11B1> 62A7< =PP1V2_ENETFW 10D4> 66D2< 69C1< 69D5< =PP1V2_VESTA 10D4> 18B7< =PP1V2_VESTA_REG 10D6< 18C1< =PP1V05R1V3_GPU_VCORE 10A6> 46D6< =PP1V5R1V8_MAXBUS 10A1> 21C8< 32D1< 33A5< 33B8<

33C8< 34B5< 34B7< 34C4< 34C4< 34D4< =PP1V5R1V8_PWRON_I2_MAXBUS 10A4> 32A5< =PP1V5R1V8_RUN_I2_MAXBUS 10A1> 32B5< =PP1V5R3V3_DVO_VREF 47C1> 54A2< =PP1V5_AGP 10A6> 43A5< 43C1< 44B2< 44B7<

44C6< 47C2< =PP1V5_GPU 10A1> 10A8< =PP1V5_GPU_DVO 10A6> 47C2< =PP1V5_GPU_PWRSEQ 10A6> 52C4<> =PP1V5_GPU_VDD15 10A6> 46B5<> =PP1V5_I2_AGP 10A4> 43C7< =PP1V5_PWRON_I2PLL_LDO 10D3< 20B3<> =PP1V5_PWRON_I2_PLL 10D1> 19C5< =PP1V5_PWRON_I2_USBPLL 10D1> 72C7< =PP1V5_PWRON_REG 10A6<> 16B8<> =PP1V5_PWRON_RUNFET 10A4> 16A8<> =PP1V5_RUN_RUNFET 10A3< 16A6<> =PP1V8R2V5_GPU_FB_VIO 10A6> 47C8< 48A8< =PP1V8_FB_VDD 10A6> 49D5< 49D8< 50D5< 50D8< =PP1V8_FB_VDDQ 10A6> 49D5< 49D8< 50D5< 50D8< =PP1V8_GPU 10A1> 10A8< =PP1V8_GPU_AVDD 10A8< 53C2< =PP1V8_GPU_DVO 10A6> 47C2< =PP1V8_GPU_LVDS_PLL 47C2< 51D1> =PP1V8_GPU_MEMVMODE 10A6> 48A6< =PP1V8_GPU_PANEL_IO 10A6> 47B2< =PP1V8_GPU_PWRSEQ 10A6> 52D4<> =PP1V8_GPU_TPVDD 10A8< 53D4< =PP1V8_PWRON_DDR2 10A4> 40B8< 40C3< 40D4< 40D6<

41C3< 41D4< 41D6< =PP1V8_PWRON_I2_RAM 10A4> 38D3< =PP1V8_PWRON_REG 10A6<> 16C1<> =PP1V8_PWRON_RUNFET 10A4> 16B5<> =PP1V8_RAM_I2_VREF 10A1> 38A6< =PP1V8_RUN_RUNFET 10A3< 16A3<> =PP1V8_RUN_TBEN_SYNC 10A1> 21B5< =PP2V5R3V3_PWRON_I2_ENET 10B5< 65B6< 65C3< 65C7< =PP2V5_ENET 10A4> 67C7<> =PP2V5_ENETFW 10D4> 66D2< 69D1< 69D5< =PP2V5_GPU 10B1> 10B8< =PP2V5_GPU_A2VDD 10A6> 53B2< =PP2V5_GPU_LVDS_IO 10B6> 47B1< =PP2V5_GPU_PVDD 10B6> 51D3< =PP2V5_GPU_PWRSEQ 10B6> 52D4<> =PP2V5_PWRON_REG 10A6<> 17C2< =PP2V5_PWRON_RUNFET 10A4> 17B5<> =PP2V5_RUN_PCI1510 10B1> 61C8< =PP2V5_RUN_RUNFET 10B3< 17B4<> =PP2V5_VESTA 10D4> 18B2< =PP2V5_VESTA_LDO 10D6< 18D1<> =PP2V7R5V5_PWRON_I2VCORE 10B4> 20D7< =PP2V8_GPU_LVDDR_LDO 10B8< 52B1<> =PP2V8_GPU_LVDS_IO 10B6> 47A1< =PP3V3_ADT7467 10B4> 27D5< =PP3V3_AGP 10B6> 43D1< 44B4< 44C7< =PP3V3_ALL_A29_DET 10C6> 12D3<> =PP3V3_ALL_AC_DETECT 10C6> 12C7<> =PP3V3_ALL_BATT0_DET 10B6> 12B7< =PP3V3_ALL_BATT_CHGR 10C6> 13A6<> 13A8< 13C8< =PP3V3_ALL_DEBUG 10B6> 24C3<> =PP3V3_ALL_HALL_EFFECT 10C6> 30D3< =PP3V3_ALL_LTC1625_SW 10C6> 14C7<> =PP3V3_ALL_PBUS_ILIM 10C6> 13C3< 13D4< =PP3V3_ALL_PMU 10C6> 24A7< 24D7< 25B6< 25C8<

25D5< =PP3V3_ALL_PWRSEQ 10B6> 26B7<> 26D5< =PP3V3_ALL_VREG 10C8< 14A2< =PP3V3_AUDIO_MUTESEQ 10B5< 22B2< 22D7< =PP3V3_BATT_IMON 10B6> 12A5< =PP3V3_DDC_DVI 10B1> 57B4<> 57D2<> =PP3V3_DDC_LCD 7B7> 10B1> 56C7<> =PP3V3_ENET 10A5< 66B7<> =PP3V3_ENETFW 10D4> 69D1< =PP3V3_FW 10D4> 69A8< 69B2< 70A8< =PP3V3_GPU 10B1> 10B8< =PP3V3_GPU_CLOCKS 10B1> 52B8< 52C8< =PP3V3_GPU_GPIOS 10B6> 51A7< 51B8< 53C4< =PP3V3_GPU_PWRSEQ 10B6> 52D2<> =PP3V3_GPU_VDDR3 10B6> 47D3< =PP3V3_I2_PCISLOTEGPIOS 10B5< 22B7< =PP3V3_PCI 10B1> 59D1< =PP3V3_PCI_AIRPORT 10B1> 60C3<>

=PP3V3_PCI_ROM 10B5< 58B6< 58C5<> =PP3V3_PCI_USB2 10B3< 62B6< =PP3V3_PCI_ZDB 10B3< 23C5< =PP3V3_PWRON_AUDIO_AVDD 10B4> 74B2<> =PP3V3_PWRON_BT 10B4> 60C6<> =PP3V3_PWRON_CPUVCORE_OFFSET 10B3> 36B7< =PP3V3_PWRON_CPUVCORE_VID 10B4> 36C8< 36D6< =PP3V3_PWRON_DS1775 10B4> 30D7< =PP3V3_PWRON_I2_AGPPCI 10B5< 19A5< =PP3V3_PWRON_I2_IO1 10B5< 19C5< =PP3V3_PWRON_I2_IO2 10B5< 19B5< =PP3V3_PWRON_I2_MAXBUS 10B4> 19B5< =PP3V3_PWRON_I2_MISC 10B5< 22B6< 22C7< =PP3V3_PWRON_INVERTER 10B4> 56B4< =PP3V3_PWRON_JTAG_ASIC 9C8< 10B5< =PP3V3_PWRON_LCD 10B4> 56C8<> =PP3V3_PWRON_LEFT_ALS 7B5> 10B4> 31C3<> =PP3V3_PWRON_LTC3412 10B4> 17D6< =PP3V3_PWRON_MMM 10B4> 29C6< =PP3V3_PWRON_MODEM 10B4> 30B6<> =PP3V3_PWRON_PMU 10B4> 25B8< =PP3V3_PWRON_PWRSEQ 10B5< 26C5< 26C7<> =PP3V3_PWRON_REG 10B6<> 15D1< =PP3V3_PWRON_RT_ALS 10B5< 28D5< =PP3V3_PWRON_RUNFET 10B4> 15B2<> =PP3V3_PWRON_TPS2211 10B4> 61D4< =PP3V3_PWRON_USB2 10A4> 73B6< 73C6< 73D5< =PP3V3_PWRON_VDDSPD 10B5< 40A6< 41A4< 41A6< =PP3V3_PWRON_VGASYNC 10B4> 57C2< 57C2< =PP3V3_RUN_AUDIO 7A7> 10B3< 74B6<> =PP3V3_RUN_FANTACH 10B1> 27D2< =PP3V3_RUN_FWPORTPWRSW 10B1> 18C8< =PP3V3_RUN_HDD 10B1> 64B8< 64C7< =PP3V3_RUN_KEYBRD_LED 10B1> 28B6< =PP3V3_RUN_PCI1510_R 10B1> 61D7< =PP3V3_RUN_PWRSEQ 10B3< 26B7< =PP3V3_RUN_RUNFET 10B3< 15B1<> =PP3V3_RUN_SI 10B1> 54C2< 54C3< 54C5< 55C3<

55D3< 55D3<

=PP3V3_VESTA 10D4> 18A2< 18A6< 18A8< 65C2<>

66C7< 67C7<> =PP3V3_VESTA_1V2REG 10D4> 18C5< =PP3V3_VESTA_2V5REG 10D4> 18D3<> =PP3V3_VESTA_REG 10D6< 18D3< =PP4V85_ALL_A29_DET 10C6> 12D4< =PP4V85_ALL_VREG 10C8< 14B4<> =PP5V_FAN1_PWR 7C5> 10C1> 31B4<> =PP5V_FAN2_PWR 7C5> 10C1> 31B2<> =PP5V_PWRON_AUDIO_AVDD 10C4> 74B2<> =PP5V_PWRON_AUDIO_PVDD 10C4> 74B2<> =PP5V_PWRON_CPUVCORE_PWRSEQ 10C3> 36C8< =PP5V_PWRON_CPUVCORE_VDD 10C4> 36C6<> =PP5V_PWRON_GPUVCORE_PWRPLAY 10C3> 45B5< =PP5V_PWRON_INVERTER 10B4> 56C4<> =PP5V_PWRON_LEFT_USB 7B5> 10C4> 74C3<> =PP5V_PWRON_LTC1625_EXTVCC 10C4> 14D7<> =PP5V_PWRON_LTC1778_GPU_EXTVCC 10C3> 45D6< =PP5V_PWRON_LTC3707_EXTVCC 10C4> 15D5< =PP5V_PWRON_MAX1715_VDD 10C4> 16D5<> =PP5V_PWRON_PMU_SUPPLY 10C4> 14B4<> =PP5V_PWRON_PWRSEQ 10C4> 26D7< =PP5V_PWRON_REG 10C6<> 15D8< =PP5V_PWRON_RIGHT_USB 7B5> 10C4> 31C7<> =PP5V_PWRON_RUNFET 10C4> 15B5<> =PP5V_PWRON_SLEEPLED 10B4> 24B7< =PP5V_PWRON_TPS2211 10C4> 61D4< =PP5V_PWRON_TRACKPAD 10B4> 15B8<> =PP5V_RUN_DVI_DDC 10C1> 57D4< =PP5V_RUN_FANPWM 10C1> 27D2< =PP5V_RUN_HDD 7B7> 10C1> 64B5<> 64B8< =PP5V_RUN_HDDFET 10C3< 15B4<> =PP5V_RUN_KEYBRD_LED 10C1> 28B5< =PP5V_RUN_ODD 7B7> 10C1> 64C4< =PP5V_RUN_PWRSEQ 10C1> 26A7< 26C8< =PP5V_RUN_RUNFET 10C3< 15A4<> =PP5V_SUPERCAP 14A4< =PP5V_TPAD 10C1> 30D7< =PP5V_TPAD_FET 10C3< 15A6<> =PP12V8_LTC1625_VREG 10D8< 14C3<> =PP12V8_PBUSB_HOLDUP_CAPS 10D6> 31D3< =PP12V8_PBUS_PMU_SUPPLY 10D6> 14A7<> =PP14VR24V_ALL_PBUS_A 10D8< 13D5< =PP24V_ADAPTER_CONN 10C8< 31D6<> =PP24V_ADAPTER_PMU_SUPPLY 10C6> 14A7< =PP24V_ADAPTER_RAW 10C6> 12D8<> =PP24V_PBUSA_HOLDUP_CAPS 10D6> 31D3< =PPAVDD_CPU0 10C1> 35B6< =PPBUS_DVI_PWRSW 10C6> 57A4<> =PPBUS_FWPWRSW 10D6> 18D8< =PPBUS_FW_FET 10D6< 18D5<> =PPBUS_INVERTER 10D6> 56C3< =PPBU_RUN_FW 10C1> 18D6<> =PPFW_P3V3VESTA 10D4> 18D6<> =PPFW_PHY_CPS 10D4> 69C5< =PPFW_PORT1 10D4> 70D3< =PPFW_PORT2 10D4> 70B4< =PPI2C_GPU 8B5< 10B1> =PPI2C_I2_NB 8C2< 10B5< =PPI2C_I2_SB 8D2< 10B3< =PPI2C_SYS0 8B5< 10C6> =PPI2C_SYS1 8C5< 10B5< =PPJTAG_CPU 9D8< 10A1> =PPVBATT_BATT 10C6> 13D2< =PPVBATT_BATTERY_PMU_SUPPLY 10C6> 14A7< =PPVBATT_BATT_PBUSA 10D8< 13D2<> =PPVBATT_BATT_PBUSB 10D8< 13D1<> =PPVBATT_BATT_VSNS 10C8< 12B6< =PPVBATT_ISNS_N 10C8< 12B4<> =PPVCORE_CPU0 10C4> 35C4< 35C8< 35D4< =PPVCORE_CPU_ADT7467 10C4> 27C4< =PPVCORE_CPU_REG 10C6< 36C1< =PPVCORE_GPU_REG 10A8<> 45C3<> =PPVCORE_PWRON_I2 10A6> 19D6< =PPVCORE_PWRON_I2_REG 10A8<> 20C2< =PPVIN_ALL_BATT_CHGR 10D6> 13C2<> =PPVIN_ALL_LTC1625 10D6> 14D3<> =PPVIN_ALL_LTC3707 10D6> 15D5<> =PPVIN_ALL_MAX1715 10D6> 16C3<> 16C7<> 16D5< =PPVIN_BATT_CHRG_VSNS 10C6> 13A4< =PPVIN_CPU0_AVDD 10B3< 37C7< =PPVIN_CPUVCORE_MAX1717 10D6> 36D4<> =PPVIN_GPU_LVDDR_LDO 10B6> 52B4< =PPVIN_LTC1778_GPU 10D6> 45D5<> =PPVIN_PWRON_I2PLLVDD 10A4> 20B6<> =PPVIO_BU_BATT 7B5> 10D8< 31A6<> =PPVIO_PCI_USB2 10B3< 62D5< =PPVOUT_BATT_CHRG 13B1> =PPVOUT_BU_BATT 7B5> 10D8< 31A6<> =PPVOUT_CPU0_AVDD 10C3< 37C3< =PPVREF_PMU 10B6> 25B5< =RAM_VREF_A 40A6> 40D2< 40D6< =RAM_VREF_B 40A6> 41D2< 41D6< =ROM_PWD_L 11A4> 58B6< =RP1150P1 6D7> 11D8< =RP1150P2 6D7> 11D8< =RP1150P3 6D7> 11D8< =RP1150P4 6D7> 11D8< =RP1150P5 6D7< 11D7< =RP1150P6 6D7< 11D7< =RP1150P7 6D7< 11D7< =RP1150P8 6D7< 11D7< =RP1151P1 6D7> 11D8< =RP1151P2 6D7> 11C8< =RP1151P3 6D7> 11C8< =RP1151P4 6D7> 11C8< =RP1151P5 6D7< 11C7< =RP1151P6 6D7< 11C7< =RP1151P7 6D7< 11C7< =RP1151P8 6D7< 11D7< =RP3510P1 6B7> 32D2< =RP3510P2 6B7> 32D2< =RP3510P3 6B7> 32D2< =RP3510P4 6B7> 32D2< =RP3511P1 6B7> 32D2< =RP3511P2 6B7> 32C2< =RP3511P3 6B7> 32C2< =RP3511P4 6B7> 32C2< =RP3512P1 6B7> 32C2< =RP3512P2 6B7> 32C2< =RP3512P3 6B7> 32C2< =RP3512P4 6B7> 32C2< =RP3513P2 6B7> 32B2< =RP3513P3 6B7> 32B2< =RP3513P4 6B7> 32B2< =RP3514P1 6A7> 32B2< =RP3514P2 6A7> 32B2< =RP3514P3 6A7> 32B2< =RP5610P1 6B5> 43B2<

=RP5610P2 6B5> 43C2< =RP5610P3 6B5> 43C2< =RP5610P4 6B5> 43C2< =RP5611P1 6B5> 43B2< =RP5611P2 6B5> 43C2< =RP5611P3 6B5> 43C2< =RP5611P4 6B5> 43C2< =RP6720P1 6D4> 54C8< =RP6720P2 6D4> 54B8< =RP6720P3 6D4> 54B8< =RP6720P4 6D4> 54B8< =RP6720P5 6D4< 54B7< =RP6720P6 6D4< 54B7< =RP6720P7 6D4< 54B7< =RP6720P8 6D4< 54C7< =RP6721P1 6D4> 54B8< =RP6721P2 6D4> 54B8< =RP6721P3 6D4> 54B8< =RP6721P4 6D4> 54B8< =RP6721P5 6D4< 54B7< =RP6721P6 6D4< 54B7< =RP6721P7 6D4< 54B7< =RP6721P8 6D4< 54B7< =RP6722P1 6C4> 54A8< =RP6722P2 6C4> 54A8< =RP6722P3 6C4> 54A8< =RP6722P4 6C4> 54A8< =RP6722P5 6C4< 54A7< =RP6722P6 6C4< 54A7< =RP6722P7 6C4< 54A7< =RP6722P8 6C4< 54A7< =RP6723P1 6C4> 54A8< =RP6723P2 6C4> 54A8< =RP6723P3 6C4> 54A8< =RP6723P4 6C4> 54A8< =RP6723P5 6C4< 54A7< =RP6723P6 6C4< 54A7< =RP6723P7 6C4< 54A7< =RP6723P8 6C4< 54A7< =RP6821P1 6C4> 55B8< =RP6821P2 6C4> 55B8< =RP6821P3 6C4> 55B8< =RP6821P4 6C4> 55B8< =RP6821P5 6C4< 55B7< =RP6821P6 6C4< 55B7< =RP6821P7 6C4< 55B7< =RP6821P8 6C4< 55B7< =RP6822P1 6C4> 55B8< =RP6822P2 6C4> 55A8< =RP6822P3 6C4> 55A8< =RP6822P4 6C4> 55A8< =RP6822P5 6C4< 55A7< =RP6822P6 6C4< 55A7< =RP6822P7 6C4< 55A7< =RP6822P8 6C4< 55B7< =RP6823P1 6C4> 55A8< =RP6823P2 6C4> 55A8< =RP6823P3 6B4> 55A8< =RP6823P4 6B4> 55A8< =RP6823P5 6B4< 55A7< =RP6823P6 6B4< 55A7< =RP6823P7 6C4< 55A7< =RP6823P8 6C4< 55A7< =RP7250P1 6B5> 59D2< =RP7250P2 6B5> 59D2< =RP7250P3 6B5> 59D2< =RP7250P4 6B5> 59D2< =RP7251P1 6B5> 59C2< =RP7251P2 6A5> 59C2< =RP7251P3 6A5> 59C2< =RP7251P4 6A5> 59C2< =RP8150P1 6C7> 63D2< =RP8150P2 6C7> 63D2< =RP8150P3 6C7> 63D2< =RP8150P4 6C7> 63D2< =RP8150P5 6C7< 63D1<> =RP8150P6 6C7< 63D1<> =RP8150P7 6C7< 63D1<> =RP8150P8 6C7< 63D1<> =RP8151P1 6C7> 63D2< =RP8151P2 6C7> 63D2< =RP8151P3 6C7> 63D2< =RP8151P4 6C7> 63C2< =RP8151P5 6C7< 63C1<> =RP8151P6 6C7< 63D1<> =RP8151P7 6C7< 63D1<> =RP8151P8 6C7< 63D1<> =RP8152P1 6C7> 63C2< =RP8152P2 6C7> 63C2< =RP8152P3 6C7> 63C2< =RP8152P4 6C7> 63C2< =RP8152P5 6C7< 63C1<> =RP8152P6 6C7< 63C1<> =RP8152P7 6C7< 63C1<> =RP8152P8 6C7< 63C1<> =RP8153P1 6C7> 63C2< =RP8153P2 6C7> 63C2< =RP8153P3 6C7> 63C2< =RP8153P4 6C7> 63C2< =RP8153P5 6C7< 63C1<> =RP8153P6 6C7< 63C1<> =RP8153P7 6C7< 63C1<> =RP8153P8 6C7< 63C1<> =RP8154P1 6C7> 63C2< =RP8154P2 6C7> 63B2< =RP8154P3 6B7> 63B2< =RP8154P4 6B7> 63B2< =RP8154P5 6B7< 63B1> =RP8154P6 6B7< 63B1> =RP8154P7 6C7< 63B1> =RP8154P8 6C7< 63C1> =RP9100P1 6A7> 71C6< =RP9100P2 6A7> 71C6< =RP9100P3 6A7> 71C6< =RP9100P4 6A7> 71C6< =RP9100P5 6A7< 71C4< =RP9100P6 6A7< 71C4< =RP9100P7 6A7< 71C4< =RP9100P8 6A7< 71C4< =RP9101P1 6A7> 71C6< =RP9101P2 6A7> 71C6< =RP9101P3 6A7> 71C6< =RP9101P4 6A7> 71C6< =RP9101P5 6A7< 71C4< =RP9101P6 6A7< 71C4< =RP9101P7 6A7< 71C4< =RP9101P8 6A7< 71C4< =RP9210P5 6B4< 72A4< =RP9210P6 6B4< 72A4< =RP9210P7 6B4< 72A4< =RP9210P8 6B4< 72A4< =RP9211P5 6B4< 72A4< =RP9211P6 6B4< 72A4< =RP9211P7 6B4< 72A4< =RP9211P8 6B4< 72A4< =RP9212P5 6B4< 72A4< =RP9212P6 6B4< 72A4< =RP9212P7 6B4< 72A4< =RP9212P8 6B4< 72A4< =RP9300P5 6B4< 73B1< =RP9300P6 6B4< 73B1< =RP9300P7 6B4< 73B1< =RP9300P8 6B4< 73B1< =RP9301P5 6A4< 73B1< =RP9301P6 6A4< 73B1< =RP9301P7 6A4< 73B1< =RP9301P8 6A4< 73B1< =SI_TMDS_RESET_L 11C7> 54B6< 55B6< =SLEEP_LED_CONN 11A3> 30B4< =SLEEP_LED_IOUT 11A5< 24B6< =SPI_I2_CLK 22A5< =SPI_I2_MISO 22B2> =SPI_I2_MOSI 22B5< =SPI_I2_REQ 11A5< 22A7< 22C5< =SYSCLK_TBEN_SYNC 11D4> 21A5< 21D6> =TPS2211_SHDN_L 10B3< 61D5< =VCORE_PGOOD 26B5< 36B4> =VESTA_CLK25M_TX 11A6> 66C2> =VESTA_CLK125M_GBE_REF 11A6> 66C2> =VESTA_CLK125M_RX 11A6> 66C2> =VESTA_ENERGYDET 11A6> 66B3> =VESTA_MDC 11A6> 66B6< =VESTA_MDIO 11A6> 66B6<> A29_CLS_ADJ 13A5<> A29_CURRENT_ADJ 13C4<> A29_DETECT 12D1< 13A5<> 13C4<> A29_DET_L 12C2< A29_DET_REF 12C2<

AB_SEL_LOW 36A6<> AC_DET_DIV 12C7< AC_ENABLE_GATE 12D5<> AC_ENABLE_L 12C5<> AC_GTR_18V 13C3<> ADAPTER_I_REG 13D3<> ADT7467_ADR_ENABLE_L 27C2<> AGP8X_DET_PU 44B6< AGP_AD<0> 43D3< 44D6<> AGP_AD<15..0> 43D6> AGP_AD<1> 43D3< 44D6<> AGP_AD<2> 43C3< 44C6<> AGP_AD<3> 43C3< 44C6<> AGP_AD<4> 43C3< 44C6<> AGP_AD<5> 43C3< 44C6<> AGP_AD<6> 43C3< 44C6<> AGP_AD<7> 43C3< 44C6<> AGP_AD<8> 43C3< 44C6<> AGP_AD<9> 43C3< 44C6<> AGP_AD<10> 43C3< 44C6<> AGP_AD<11> 43C3< 44C6<> AGP_AD<12> 43C3< 44C6<> AGP_AD<13> 43C3< 44C6<> AGP_AD<14> 43C3< 44C6<> AGP_AD<15> 43C3< 44C6<> AGP_AD<16> 43C3< 44C6<> AGP_AD<31..16> 43D6> AGP_AD<17> 43C3< 44C6<> AGP_AD<18> 43C3< 44C6<> AGP_AD<19> 43C3< 44C6<> AGP_AD<20> 43C3< 44C6<> AGP_AD<21> 43B3< 44C6<> AGP_AD<22> 43B3< 44C6<> AGP_AD<23> 43B3< 44C6<> AGP_AD<24> 43B3< 44C6<> AGP_AD<25> 43B3< 44C6<> AGP_AD<26> 43B3< 44C6<> AGP_AD<27> 43B3< 44C6<> AGP_AD<28> 43B3< 44B6<> AGP_AD<29> 43B3< 44B6<> AGP_AD<30> 43B3< 44B6<> AGP_AD<31> 43B3< 44B6<> AGP_AD_STB0_N 43B2< 43C3< 43D6> 44B4<> AGP_AD_STB0_P 43B2< 43C3< 43D6> 44B4<> AGP_AD_STB1_N 43A2< 43B3< 43D6> 44B4<> AGP_AD_STB1_P 43B2< 43B3< 43D6> 44B4<> AGP_ATI_RESET_L 44C4< AGP_BUSY_L 43D2< 43D5< 44B4> AGP_CBE_L<0> 43C3< 44C4<> AGP_CBE_L<1..0> 43D6> AGP_CBE_L<1> 43C3< 44C4<> AGP_CBE_L<2> 43B3< 44C4<> AGP_CBE_L<3..2> 43D6> AGP_CBE_L<3> 43B3< 44C4<> AGP_CLK66M_GPU 11C7< 44C4< 44D6> AGP_CLK66M_GPU_R 11C8< 43D3< 43D6> AGP_DEVSEL_L 6B6< 43C5< 43D6> 44C4<> AGP_FRAME_L 6B6< 43D5< 43D6> 44C4<> AGP_GNT_L 6B6< 43C6> 43D3< 44C4< AGP_INT_L 22D5< 43C2< 44C4> AGP_IRDY_L 6B6< 43C5< 43C6> 44C4<> AGP_PAR 43C6> 43D5< 44C4> AGP_PIPE_L 43B2< 43C5< 43C6> AGP_RBF_L 6B6< 43C5< 43C6> 44B4> AGP_REQ_L 6B6< 43C6> 43D5< 44C4<> AGP_SBA<0> 43C5< 44B6> AGP_SBA<7..0> 43D6> AGP_SBA<1> 43C5< 44B6> AGP_SBA<2> 43C5< 44B6> AGP_SBA<3> 43C5< 44B6> AGP_SBA<4> 43C5< 44B6> AGP_SBA<5> 43C5< 44B6> AGP_SBA<6> 43C5< 44B6> AGP_SBA<7> 43C5< 44B6> AGP_SB_STB_N 43A2< 43C5< 43D6> 44B4<> AGP_SB_STB_P 43B2< 43C5< 43D6> 44B4<> AGP_ST<0> 43B3< 44B4< AGP_ST<3..0> 43D6> AGP_ST<1> 43B3< 44B4< AGP_ST<2> 43B3< 44B4< AGP_STOP_L 6B6< 43C5< 43C6> 44C4<> AGP_SUS_STAT_L_PU 44B4<> AGP_TRDY_L 6B6< 43C5< 43C6> 44C4<> AGP_VREF 11C8< AGP_WBF_L 43B2< 43C5< 43C6> 44B4> AIRPORT_CLKRUN_L_PD 60C4<> ALS_0_OUT 7B5> 25A6> 31C3<> ALS_1_OUT 25A6> 28D3< ALS_GAIN_BOOST 7B5> 25A6> 28C5<> 31C3<> ANALOG_AC_DET 12C3< ATI_AGP_FBSKEW<0> 51B5<> ATI_AGP_FBSKEW<1> 51B5<> ATI_BUS_CFG<0> 51B5<> ATI_BUS_CFG<1> 51B5<> ATI_BUS_CFG<2> 51B5<> ATI_CLK27M 51C3< 52C6< 52D6> ATI_CLK27M_R 52C6< 52D6> ATI_CLK27M_SS 51B5<> 52A5< 52D6> ATI_CLK27M_SSIN 52A6< 52C5< 52D6> ATI_CLK27M_SS_R 52A6<> 52D6> ATI_DBI_HI_PU 44B6<> ATI_DBI_LO_PU 44B6<> ATI_MEMTYPE 51A7< 51B5<> ATI_OSC_OE 52C7< ATI_PVDD_BYP 51D2<> ATI_R2SET 53B6<> ATI_RSET 53B6<> ATI_X1CLK_SKEW<0> 51B5<> ATI_X1CLK_SKEW<1> 51B5<> AUDIO_CODEC_RESET_L 7A7> 22C5< 74C4<> AUDIO_EXT_MCLK_SEL 7A7> 22C5< 74B4<> AUDIO_GPIO_11 7A7> 22C5< 74C3> AUDIO_I2S_DTIB_SEL 7A7> 22C5< 74B4<> AUDIO_LI_DET_L 7A7> 22D5< 74B6<> AUDIO_LI_OPTICAL_PLUG_L 7A7> 22D5< 74C6<> AUDIO_LO_DET_L 7A7> 22C5< 74B6<> AUDIO_LO_MUTE 22C7<> AUDIO_LO_MUTE_L 7A7> 22C6<> 74B4<> AUDIO_LO_OPTICAL_PLUG_L 7A7> 22C5< 74B6<> AUDIO_SPDIFRX_RESET_L 7A7> 22C5< 74C4<> AUDIO_SPDIF_RXERR_INT 74B4<> AUDIO_SPKR_MUTE 22B2<> AUDIO_SPKR_MUTE_L 7A7> 22B1<> 74B4<> BATT0_DET_L 12A7<> BATTV_HIGH 13B7<> BATTV_LOW 13B8<> BATT_14PBUS_EN 13C1<> BATT_14V_GATE 13C1<> BATT_24PBUS_EN 13C2<> BATT_24V_GATE 13C1<> BATT_CLK 12A7<> BATT_DATA 12A7<> BATT_DIV 13A5< BATT_ISNS 12A3< 25A3> BATT_ISNS_R 12A4<> BATT_LOW 13A6<> BATT_LOW_L 13B6<> BKFD_PROT_EN_L 13C8<> BKFD_PROT_GATE 13D8<> BRIGHT_PWM 7B7> 56B2<> BRIGHT_PWM_F 56B3<> CBUS_ADDR<0> 61B1< 61B4> CBUS_ADDR<1> 61B1< 61B4> CBUS_ADDR<2> 61B1< 61B4> CBUS_ADDR<3> 61B1< 61B4> CBUS_ADDR<4> 61B1< 61B4> CBUS_ADDR<5> 61B1< 61B4> CBUS_ADDR<6> 61B1< 61B4> CBUS_ADDR<7> 61B1< 61B4> CBUS_ADDR<8> 61B1< 61B4> CBUS_ADDR<9> 61B1< 61B4> CBUS_ADDR<10> 61B4> 61C1< CBUS_ADDR<11> 61B1< 61B4> CBUS_ADDR<12> 61B1< 61B4> CBUS_ADDR<13> 61B1< 61B4> CBUS_ADDR<14> 61B1< 61B4> CBUS_ADDR<15> 61B1< 61B4> CBUS_ADDR<16> 61B1< 61B4< CBUS_ADDR<17> 61B2< 61B4> CBUS_ADDR<18> 61B2< 61B4> CBUS_ADDR<19> 61B2< 61B4> CBUS_ADDR<20> 61B2< 61B4> CBUS_ADDR<21> 61B2< 61B4> CBUS_ADDR<22> 61A4> 61B2< CBUS_ADDR<23> 61A4> 61B2< CBUS_ADDR<24> 61A4> 61B2< CBUS_ADDR<25> 61A4> 61B2< CBUS_ADDR_16_R 61B5<>

CBUS_BVD1_L 61A2< 61C4< CBUS_BVD2_L 61B2< 61C4< CBUS_CE1_L 61C1< 61C4> CBUS_CE2_L 61B2< 61B4> CBUS_DATA<0> 61A1< 61A4<> CBUS_DATA<1> 61A1< 61A4<> CBUS_DATA<2> 61A1< 61A4<> CBUS_DATA<3> 61A4<> 61C1< CBUS_DATA<4> 61A4<> 61C1< CBUS_DATA<5> 61A4<> 61C1< CBUS_DATA<6> 61A4<> 61C1< CBUS_DATA<7> 61A4<> 61C1< CBUS_DATA<8> 61A2< 61A4<> CBUS_DATA<9> 61A2< 61A4<> CBUS_DATA<10> 61A2< 61A4<> CBUS_DATA<11> 61A4<> 61C2< CBUS_DATA<12> 61A4<> 61C2< CBUS_DATA<13> 61A4<> 61C2< CBUS_DATA<14> 61A4<> 61C2< CBUS_DATA<15> 61A4<> 61C2< CBUS_DET_1_L 61C2< 61C4< CBUS_DET_2_L 61A2< 61C4< CBUS_INPACK_L 61B2< 61B4< CBUS_IORD_L 61B2< 61C4> CBUS_IOWR_L 61B2< 61C4> CBUS_MFUNC1_PD 61A7< 61A7<> CBUS_MFUNC2_PD 61A7< 61A7<> CBUS_MFUNC3_PD 61A7< 61A7<> CBUS_MFUNC4_PD 61A7< 61A7<> CBUS_MFUNC5_PD 61A7< 61A7<> CBUS_MFUNC6_PD 61A7< 61A7<> CBUS_OE_L 61B1< 61C4> CBUS_READY 61B1< 61C4< CBUS_REG_L 61B2< 61C4> CBUS_RESET_L 61B2< 61C4> CBUS_SUSPEND_PU 61A7< 61B7< CBUS_VCCD0_L 61C5<> CBUS_VCCD1_L 61C5<> CBUS_VPPD0 61C5<> CBUS_VPPD1 61C5<> CBUS_VS1 61B2< 61C4<> CBUS_VS2 61B2< 61C4<> CBUS_WAIT_L 61B2< 61B4< CBUS_WE_L 61B1< 61C4> CBUS_WP_L 61A1< 61B4< CHARGE_DISABLE 13A7<> CLKLVDS_L_N 7C7> 53A7> 53C1> 56B5<> CLKLVDS_L_P 7C7> 53A7> 53C1> 56B5<> CLKLVDS_U_N 7C7> 53B7> 53D1> 56B5<> CLKLVDS_U_P 7C7> 53B7> 53D1> 56B5<> COMM_DTR_L 24C2<> COMM_RTS_L 24C2<> COMP_DISABLE 57A4<> COMP_ENABLE 57A3<> COMP_RC 14C6< CPU0_BMODE0_L 34C7< 34D4< CPU0_BMODE1_L 34A8< 34D4< CPU0_DFS2_L 34A8< 34D4<> CPU0_DFS4_L 34A8< 34D4<> CPU0_EXT_QUAL 34A6< 34D4< CPU0_L1TSTCLK 34A6< 34D6< CPU0_L2TSTCLK 34A8< 34D6< CPU0_LVRAM_L 34A8< 34D4<> CPU0_MAX1717_AB_SEL 11A4 CPU0_PLL_CFG<0> 34D1< 34D6< CPU0_PLL_CFG<1> 34D1< 34D6< CPU0_PLL_CFG<2> 34D1< 34D6< CPU0_PLL_CFG<3> 34D1< 34D6< CPU0_PLL_CFG<4> 34D1< 34D6< CPU0_PLL_CFG<5> 34D1< 34D4<> CPU0_PULLDOWN 33C3<> CPU0_SMI_L 34A6< 34D4< CPU0_SRESET_L 34A6< 34D4< CPU0_TEMP 25A6> CPU0_VID_AB_SEL 11A4 CPU1_TEMP 25A6> CPUVCORE_VSENSE_R 36C2<> CPU_AVDD_EN 26B5< 37C6<> CPU_BVSEL<0> 34C6< 34D6< CPU_BVSEL<1> 34B6< 34D4<> CPU_CHKSTP_OUT_L 33B1<> 34B8< CPU_LSSD_MODE_L 34B8< 34D6< CPU_MCP_L 34A8< 34D4< CPU_PMON_IN_L 34A8< 34D4< CPU_VCORE_SNUB 36B3< CURRENT_THRESHOLD 13C4< CY25811_S0 52A6< CY25811_S1 52A6< DVI_DDC_CLK 57D2<> DVI_DDC_CLK_UF 57B4<> 57C3<> DVI_DDC_DATA 57C2<> DVI_DDC_DATA_UF 57C3<> DVI_HPD 57C2<> DVI_HPD_DIV 57A4< DVI_HPD_UF 57A5< 57C3<> DVI_TURN_ON 57B4<> DVI_TURN_ON_BASE 57B2<> DVI_TURN_ON_ILIM 57B3< ENETCONN_0_N 66B1<> 66D6> 67C6<> ENETCONN_0_P 66B1<> 66D6> 67C6<> ENETCONN_1_N 66B1<> 66D6> 67B6<> ENETCONN_1_P 66B1<> 66D6> 67B6<> ENETCONN_2_N 66B1<> 66D6> 67B6<> ENETCONN_2_P 66B1<> 66D6> 67B6<> ENETCONN_3_N 66B1<> 66D6> 67B6<> ENETCONN_3_P 66B1<> 66D6> 67B6<> ENET_CLK25M_TX 11A7< 65C5< 65D6> ENET_CLK25M_TX_R 66C4<> 66D6> ENET_CLK125M_GBE_REF 11A7< 65B5< 65D6> ENET_CLK125M_GBE_REF_R 66C4<> 66D6> ENET_CLK125M_GTX 66C6< ENET_CLK125M_GTX_R 65B3< 65D6> 66C7< ENET_CLK125M_RX 11A7< 65C5< 65D6> ENET_CLK125M_RX_R 66C4<> 66D6> ENET_COL 9B3> 11A7< 65B5< 65D6> ENET_CRS 9B3> 11A7< 65B5< 65D6> ENET_CTAP_EN_L 67C7<> ENET_ENERGYDET 65B5< ENET_MDC 9B3> 11A7< 65C3< 65D6> ENET_MDI0 66A3< ENET_MDI1 66A2< ENET_MDI2 66A2< ENET_MDI3 66A2< ENET_MDIO 9B3> 11A7< 65C1<> 65D6> ENET_RESET_L 11A8< 65B3< ENET_RXD<0> 65B5< ENET_RXD<3..0> 65D6> ENET_RXD<7..0> 9B3> 11A7< ENET_RXD<1> 65B5< ENET_RXD<2> 65B5< ENET_RXD<3> 65B5< ENET_RXD<4> 65B5< ENET_RXD<7..4> 65D6> ENET_RXD<5> 65B5< ENET_RXD<6> 65B5< ENET_RXD<7> 65B5< ENET_RX_DV 9B3> 11A7< 65B5< 65D6> ENET_RX_ER 9B3> 11A7< 65B5< 65D6> ENET_TXD<7..0> 9B3> 11A7 ENET_TXD_R<0> 65B3< ENET_TXD_R<3..0> 65D6> ENET_TXD_R<7..0> 11A8< ENET_TXD_R<1> 65B3< ENET_TXD_R<2> 65B3< ENET_TXD_R<3> 65B3< ENET_TXD_R<4> 65B3< ENET_TXD_R<7..4> 65D6> ENET_TXD_R<5> 65B3< ENET_TXD_R<6> 65B3< ENET_TXD_R<7> 65B3< ENET_TX_EN 9B3> 11A7 ENET_TX_EN_R 11A8< 65B3< 65D6> ENET_TX_ER 9B3> 11A7 ENET_TX_ER_R 11A8< 65B3< 65D6> EXT_TMDS_CLK_CMF 54D2< EXT_TMDS_D0_CMF 54D1< EXT_TMDS_D1_CMF 54D2< EXT_TMDS_D2_CMF 54C1< FAN1_PWM 7C5> 27C1<> 31B4<> FAN1_TACH 7C5> 27C1< 31B4<> FAN2_PWM 7C5> 27C1<> 31B2<> FAN2_TACH 7C5> 27C1< 31B2<> FAN2558_ADJ_CPU0 37C5<> FAN2558_EN_CPU0 37C5<> FB_4_85V_BU 14A5< FB_A_ADDR<0> 49B4< 49B7< FB_A_ADDR<11..0> 48D3> 49D1> FB_A_ADDR<1> 49B4< 49B7<

FB_A_ADDR<2> 49B4< 49B7< FB_A_ADDR<3> 49B4< 49B7< FB_A_ADDR<4> 49B4< 49B7< FB_A_ADDR<5> 49B4< 49B7< FB_A_ADDR<6> 49B4< 49B7< FB_A_ADDR<7> 49B4< 49B7< FB_A_ADDR<8> 49B4< 49B7< FB_A_ADDR<9> 49B4< 49B7< FB_A_ADDR<10> 49B4< 49B7< FB_A_ADDR<11> 49B4< 49B7< FB_A_ADDR_R<11..0> 48D4< 48D6> FB_A_ADDR_R<12..0> 42D6> FB_A_BA<0> 49A4< 49A7< FB_A_BA<1..0> 48C3> 49D1> FB_A_BA<1> 49A4< 49A7< FB_A_BA_R<1..0> 48C4< 48C6> FB_A_BA_R<2..0> 42D6> FB_A_CAS_L 48B3< 49A4< 49A7< 49C1> FB_A_CAS_L_R 42D6> 48B4< 48B6> FB_A_CKE 48B3< 49A4< 49A7< 49D1> FB_A_CKE_R 42D6> 48B4< 48B6> FB_A_CLKDDR_0_N 48B3< 49A7< 49D1> FB_A_CLKDDR_0_N_R 42D6> 48B4< 48B6<> FB_A_CLKDDR_0_P 48B3< 49A7< 49D1> FB_A_CLKDDR_0_P_R 42D6> 48B4< 48B6<> FB_A_CLKDDR_1_N 48A3< 49A4< 49D1> FB_A_CLKDDR_1_N_R 42D6> 48A4< 48B6<> FB_A_CLKDDR_1_P 48B3< 49A4< 49D1> FB_A_CLKDDR_1_P_R 42D6> 48B4< 48B6<> FB_A_CS_L 48B3< 49A4< 49A7< 49D1> FB_A_CS_L_R 42D6> 48B4< 48B6> FB_A_DDRCLK_0_RC 49A7< FB_A_DDRCLK_1_RC 49A4< FB_A_DQ<0> 49A5<> FB_A_DQ<63..0> 48A3> 49C1> FB_A_DQ<1> 49A5<> FB_A_DQ<2> 49A5<> FB_A_DQ<3> 49A5<> FB_A_DQ<4> 49A5<> FB_A_DQ<5> 49A5<> FB_A_DQ<6> 49A5<> FB_A_DQ<7> 49A5<> FB_A_DQ<8> 49A5<> FB_A_DQ<9> 49A5<> FB_A_DQ<10> 49A5<> FB_A_DQ<11> 49A5<> FB_A_DQ<12> 49A5<> FB_A_DQ<13> 49A5<> FB_A_DQ<14> 49A5<> FB_A_DQ<15> 49A5<> FB_A_DQ<16> 49B5<> FB_A_DQ<17> 49B5<> FB_A_DQ<18> 49A5<> FB_A_DQ<19> 49B5<> FB_A_DQ<20> 49A5<> FB_A_DQ<21> 49B5<> FB_A_DQ<22> 49B5<> FB_A_DQ<23> 49B5<> FB_A_DQ<24> 49B5<> FB_A_DQ<25> 49B5<> FB_A_DQ<26> 49B5<> FB_A_DQ<27> 49B5<> FB_A_DQ<28> 49B5<> FB_A_DQ<29> 49B5<> FB_A_DQ<30> 49B5<> FB_A_DQ<31> 49B5<> FB_A_DQ<32> 49A3<> FB_A_DQ<33> 49B3<> FB_A_DQ<34> 49B3<> FB_A_DQ<35> 49B3<> FB_A_DQ<36> 49B3<> FB_A_DQ<37> 49A3<> FB_A_DQ<38> 49B3<> FB_A_DQ<39> 49B3<> FB_A_DQ<40> 49A3<> FB_A_DQ<41> 49A3<> FB_A_DQ<42> 49A3<> FB_A_DQ<43> 49A3<> FB_A_DQ<44> 49A3<> FB_A_DQ<45> 49A3<> FB_A_DQ<46> 49A3<> FB_A_DQ<47> 49A3<> FB_A_DQ<48> 49B3<> FB_A_DQ<49> 49B3<> FB_A_DQ<50> 49B3<> FB_A_DQ<51> 49B3<> FB_A_DQ<52> 49B3<> FB_A_DQ<53> 49B3<> FB_A_DQ<54> 49B3<> FB_A_DQ<55> 49B3<> FB_A_DQ<56> 49A3<> FB_A_DQ<57> 49A3<> FB_A_DQ<58> 49A3<> FB_A_DQ<59> 49A3<> FB_A_DQ<60> 49A3<> FB_A_DQ<61> 49A3<> FB_A_DQ<62> 49A3<> FB_A_DQ<63> 49A3<> FB_A_DQM<0> 49A7< FB_A_DQM<7..0> 48A3> 49C1> FB_A_DQM<1> 49A7< FB_A_DQM<2> 49A7< FB_A_DQM<3> 49A7< FB_A_DQM<4> 49A4< FB_A_DQM<5> 49A4< FB_A_DQM<6> 49A4< FB_A_DQM<7> 49A4< FB_A_DQM_R<0> 42C6> FB_A_DQM_R<7..0> 48A4< 48C6> FB_A_DQM_R<1> 42C6> FB_A_DQM_R<2> 42C6> FB_A_DQM_R<3> 42C6> FB_A_DQM_R<4> 42C6> FB_A_DQM_R<5> 42C6> FB_A_DQM_R<6> 42C6> FB_A_DQM_R<7> 42C6> FB_A_DQS<0> 49A7<> FB_A_DQS<7..0> 48A3> 49C1> FB_A_DQS<1> 49B7<> FB_A_DQS<2> 49B7<> FB_A_DQS<3> 49B7<> FB_A_DQS<4> 49B4<> FB_A_DQS<5> 49A4<> FB_A_DQS<6> 49B4<> FB_A_DQS<7> 49B4<> FB_A_DQS_R<0> 42D6> FB_A_DQS_R<7..0> 48A4< 48C6> FB_A_DQS_R<1> 42D6> FB_A_DQS_R<2> 42D6> FB_A_DQS_R<3> 42D6> FB_A_DQS_R<4> 42D6> FB_A_DQS_R<5> 42D6> FB_A_DQS_R<6> 42D6> FB_A_DQS_R<7> 42D6> FB_A_DQ_R<7..0> 42C6> FB_A_DQ_R<63..0> 48A4< 48D8< FB_A_DQ_R<15..8> 42C6> FB_A_DQ_R<23..16> 42C6> FB_A_DQ_R<31..24> 42C6> FB_A_DQ_R<39..32> 42C6> FB_A_DQ_R<47..40> 42C6> FB_A_DQ_R<55..48> 42C6> FB_A_DQ_R<63..56> 42C6> FB_A_RAS_L 48B3< 49A4< 49A7< 49D1> FB_A_RAS_L_R 42D6> 48B4< 48B6> FB_A_WE_L 48B3< 49A4< 49A7< 49C1> FB_A_WE_L_R 42D6> 48B4< 48B6> FB_B_ADDR<0> 50B4< 50B7< FB_B_ADDR<11..0> 48D1> 50D1> FB_B_ADDR<1> 50B4< 50B7< FB_B_ADDR<2> 50B4< 50B7< FB_B_ADDR<3> 50B4< 50B7< FB_B_ADDR<4> 50B4< 50B7< FB_B_ADDR<5> 50B4< 50B7< FB_B_ADDR<6> 50B4< 50B7< FB_B_ADDR<7> 50B4< 50B7< FB_B_ADDR<8> 50B4< 50B7< FB_B_ADDR<9> 50B4< 50B7< FB_B_ADDR<10> 50B4< 50B7< FB_B_ADDR<11> 50B4< 50B7< FB_B_ADDR_R<11..0> 48D2< 48D5> FB_B_ADDR_R<12..0> 42B6> FB_B_BA<0> 50A4< 50A7< FB_B_BA<1..0> 48C1> 50D1> FB_B_BA<1> 50A4< 50A7< FB_B_BA_R<1..0> 48C2< 48C5> FB_B_BA_R<2..0> 42B6> FB_B_CAS_L 48B1< 50A4< 50A7< 50C1>

FB_B_CAS_L_R 42B6> 48B2< 48B5> FB_B_CKE 48B1< 50A4< 50A7< 50D1> FB_B_CKE_R 42B6> 48B2< 48B5> FB_B_CLKDDR_0_N 48B1< 50A7< 50D1> FB_B_CLKDDR_0_N_R 42C6> 48B2< 48B5<> FB_B_CLKDDR_0_P 48B1< 50A7< 50D1> FB_B_CLKDDR_0_P_R 42C6> 48B2< 48B5<> FB_B_CLKDDR_1_N 48A1< 50A4< 50D1> FB_B_CLKDDR_1_N_R 42C6> 48A2< 48B5<> FB_B_CLKDDR_1_P 48B1< 50A4< 50D1> FB_B_CLKDDR_1_P_R 42C6> 48B2< 48B5<> FB_B_CS_L 48B1< 50A4< 50A7< 50D1> FB_B_CS_L_R 42B6> 48B2< 48B5> FB_B_DDRCLK_0_RC 50A7< FB_B_DDRCLK_1_RC 50A4< FB_B_DQ<0> 50B5<> FB_B_DQ<63..0> 48A1> 50C1> FB_B_DQ<1> 50B5<> FB_B_DQ<2> 50B5<> FB_B_DQ<3> 50B5<> FB_B_DQ<4> 50B5<> FB_B_DQ<5> 50B5<> FB_B_DQ<6> 50A5<> FB_B_DQ<7> 50A5<> FB_B_DQ<8> 50A5<> FB_B_DQ<9> 50A5<> FB_B_DQ<10> 50A5<> FB_B_DQ<11> 50A5<> FB_B_DQ<12> 50A5<> FB_B_DQ<13> 50A5<> FB_B_DQ<14> 50A5<> FB_B_DQ<15> 50A5<> FB_B_DQ<16> 50A5<> FB_B_DQ<17> 50A5<> FB_B_DQ<18> 50A5<> FB_B_DQ<19> 50A5<> FB_B_DQ<20> 50A5<> FB_B_DQ<21> 50A5<> FB_B_DQ<22> 50A5<> FB_B_DQ<23> 50A5<> FB_B_DQ<24> 50B5<> FB_B_DQ<25> 50B5<> FB_B_DQ<26> 50B5<> FB_B_DQ<27> 50B5<> FB_B_DQ<28> 50B5<> FB_B_DQ<29> 50B5<> FB_B_DQ<30> 50B5<> FB_B_DQ<31> 50B5<> FB_B_DQ<32> 50B3<> FB_B_DQ<33> 50B3<> FB_B_DQ<34> 50B3<> FB_B_DQ<35> 50B3<> FB_B_DQ<36> 50B3<> FB_B_DQ<37> 50B3<> FB_B_DQ<38> 50A3<> FB_B_DQ<39> 50A3<> FB_B_DQ<40> 50A3<> FB_B_DQ<41> 50A3<> FB_B_DQ<42> 50A3<> FB_B_DQ<43> 50A3<> FB_B_DQ<44> 50A3<> FB_B_DQ<45> 50A3<> FB_B_DQ<46> 50A3<> FB_B_DQ<47> 50A3<> FB_B_DQ<48> 50B3<> FB_B_DQ<49> 50B3<> FB_B_DQ<50> 50B3<> FB_B_DQ<51> 50B3<> FB_B_DQ<52> 50B3<> FB_B_DQ<53> 50B3<> FB_B_DQ<54> 50B3<> FB_B_DQ<55> 50B3<> FB_B_DQ<56> 50A3<> FB_B_DQ<57> 50A3<> FB_B_DQ<58> 50A3<> FB_B_DQ<59> 50A3<> FB_B_DQ<60> 50A3<> FB_B_DQ<61> 50A3<> FB_B_DQ<62> 50A3<> FB_B_DQ<63> 50A3<> FB_B_DQM<0> 50A7< FB_B_DQM<7..0> 48A1> 50C1> FB_B_DQM<1> 50A7< FB_B_DQM<2> 50A7< FB_B_DQM<3> 50A7< FB_B_DQM<4> 50A4< FB_B_DQM<5> 50A4< FB_B_DQM<6> 50A4< FB_B_DQM<7> 50A4< FB_B_DQM_R<0> 42B6> FB_B_DQM_R<7..0> 48A2< 48C5> FB_B_DQM_R<1> 42B6> FB_B_DQM_R<2> 42B6> FB_B_DQM_R<3> 42B6> FB_B_DQM_R<4> 42B6> FB_B_DQM_R<5> 42B6> FB_B_DQM_R<6> 42B6> FB_B_DQM_R<7> 42B6> FB_B_DQS<0> 50B7<> FB_B_DQS<7..0> 48A1> 50C1> FB_B_DQS<1> 50B7<> FB_B_DQS<2> 50A7<> FB_B_DQS<3> 50B7<> FB_B_DQS<4> 50B4<> FB_B_DQS<5> 50A4<> FB_B_DQS<6> 50B4<> FB_B_DQS<7> 50B4<> FB_B_DQS_R<0> 42B6> FB_B_DQS_R<7..0> 48A2< 48C5> FB_B_DQS_R<1> 42B6> FB_B_DQS_R<2> 42B6> FB_B_DQS_R<3> 42B6> FB_B_DQS_R<4> 42B6> FB_B_DQS_R<5> 42B6> FB_B_DQS_R<6> 42B6> FB_B_DQS_R<7> 42B6> FB_B_DQ_R<7..0> 42B6> FB_B_DQ_R<63..0> 48A2< 48D6< FB_B_DQ_R<15..8> 42A6> FB_B_DQ_R<23..16> 42A6> FB_B_DQ_R<31..24> 42A6> FB_B_DQ_R<39..32> 42A6> FB_B_DQ_R<47..40> 42A6> FB_B_DQ_R<55..48> 42A6> FB_B_DQ_R<63..56> 42A6> FB_B_RAS_L 48B1< 50A4< 50A7< 50D1> FB_B_RAS_L_R 42B6> 48B2< 48B5> FB_B_WE_L 48B1< 50A4< 50A7< 50C1> FB_B_WE_L_R 42B6> 48B2< 48B5> FB_C0_VREF 49C6< FB_C1_VREF 49C4< FB_D0_VREF 50C6< FB_D1_VREF 50C4< FP_PWR_EN_L 56C4<> FWPWR_ACIN 18B7<> FWPWR_EN 18C7<> FWPWR_EN_L 18C7< FWPWR_EN_L_DIV 18C7<> FWPWR_PWRON 26D4< FWPWR_RUN 18C7<> FW_CLK98M_LCLK 69C5< 69D6> FW_CLK98M_LCLK_R 68B3< 68D6> 69C6< FW_CLK98M_PCLK 68C5< 68D6> 69C1> FW_CLK98M_PCLK_R 69C3<> 69D6> FW_CTL<0> 69B6<> 71B4< FW_CTL<1..0> 9B3> FW_CTL<1> 69B6<> 71B4< FW_CTL_R<0> 68B3< 71B6< FW_CTL_R<1..0> 9B3> 68D6> FW_CTL_R<1> 68B3< 71B6< FW_D<0> 6A6> 69C5<> FW_D<7..0> 9B3> FW_D<1> 6A6> 69B5<> FW_D<2> 6A6> 69B5<> FW_D<3> 6A6> 69B5<> FW_D<4> 6A6> 69B5<> FW_D<5> 6A6> 69B5<> FW_D<6> 6A6> 69B5<> FW_D<7> 6A6> 69B5<> FW_D_R<0> 6A8< 68C3< FW_D_R<7..0> 9B3> 68D6> FW_D_R<1> 6A8< 68C3< FW_D_R<2> 6A8< 68C3< FW_D_R<3> 6A8< 68B3< FW_D_R<4> 6A8< 68B3< FW_D_R<5> 6A8< 68B3< FW_D_R<6> 6A8< 68B3< FW_D_R<7> 6A8< 68B3<

FW_LINKON 68C5< 68D6> 69C2> FW_LPS 9A3> 69B5< 71B4< FW_LPS_R 9B3> 68B3< 68D6> 71B6< FW_LREQ 9A3> 69B5< 71B4< FW_LREQ_R 9A3> 68B3< 68D6> 71B6< FW_PINT 68B5< 68D6> 69C2> FW_PORT1_AREF 70C2<> FW_PORT1_TPA_N 70C5> 70C5<> FW_PORT1_TPA_N_FL 70C2<> 70D6> FW_PORT1_TPA_P 70C5> 70C5<> FW_PORT1_TPA_P_FL 70C2<> 70D6> FW_PORT1_TPB_N 70C5> 70D5<> FW_PORT1_TPB_N_FL 70D2<> 70D6> FW_PORT1_TPB_P 70C5> 70D5<> FW_PORT1_TPB_P_FL 70D2<> 70D6> FW_PORT2_TPA_N 70A5<> 70C5> FW_PORT2_TPA_N_FL 70A3<> 70D6> FW_PORT2_TPA_P 70B5<> 70C5> FW_PORT2_TPA_P_FL 70A3<> 70D6> FW_PORT2_TPB_N 70A5<> 70C5> FW_PORT2_TPB_N_FL 70A3<> 70D6> FW_PORT2_TPB_P 70A5<> 70C5> FW_PORT2_TPB_P_FL 70A3<> 70D6> FW_POWERDOWN 22A7< 22C5< FW_TPA0_C 70C7< FW_TPA0_N 69B2<> 69D6> 70C7< FW_TPA0_P 69B2<> 69D6> 70C7< FW_TPA1_C 70C6< FW_TPA1_N 69B2<> 69D6> 70C7< FW_TPA1_P 69B2<> 69D6> 70C7< FW_TPA2_N 69B2<> 69D6> 70B7< FW_TPA2_P 69B2<> 69D6> 70B7< FW_TPB0_N 69B2<> 69D6> 70C7< FW_TPB0_P 69B2<> 69D6> 70C7< FW_TPB1_N 69B2<> 69D6> 70C7< FW_TPB1_P 69B2<> 69D6> 70C7< FW_TPB2_N 69B2<> 69D6> 70B7<> FW_TPB2_P 69B2<> 69D6> 70B7<> FW_TPB2_PD 70B6<> FW_TPBIAS0 69B2> 70D7< FW_TPBIAS1 69B2> 70D7< FW_TPBIAS2 69B2> 70B7< GAIN_SETTING2 28C4<> GND_AUDIO_AGND 7A7> 74B6<> GND_AUDIO_PGND 7A7> 74B6<> GND_BATT_CONN 12A7<> GND_GPU_TV1 57B8<> GND_GPU_TV2 57A8<> GND_I2VCORE 20C4<> GND_INVERTER 7B7> 56B2<> GND_NEC_AVSS_R 73A3< GND_PMU_AVSS 25A3<> 25D3< 28D3< 29B3< 31B3< GND_TV1 57B7<> GND_TV2 57A7<> GOV_RESET_L 11B4< 25C2<> GPUPVDD_EN 26A5< 51D3<> GPUVCORE_PGOOD 26A7< GPUVCORE_SHDN_L 26B5<> 45C7< GPUVDD15_EN 26A5< 46B5<> GPU_AGPTEST 44B6<> GPU_AUXWIN_PU 53B5<> 53C4< GPU_DVI_DDC_CLK 51B3<> 57D1<> GPU_DVI_DDC_DATA 51B3<> 57C1<> GPU_DVI_HPD 51B3< 57C1<> GPU_DVOD<0> 6C3> 54B6< GPU_DVOD<0..11> 54D6> GPU_DVOD<1> 6C3> 54B6< GPU_DVOD<2> 6C3> 54B6< GPU_DVOD<3> 6C3> 54B6< GPU_DVOD<4> 6D3> 54B6< GPU_DVOD<5> 6C3> 54B6< GPU_DVOD<6> 6D3> 54B6< GPU_DVOD<7> 6D3> 54B6< GPU_DVOD<8> 6C3> 54A6< GPU_DVOD<9> 6D3> 54A6< GPU_DVOD<10> 6D3> 54A6< GPU_DVOD<11> 6D3> 54A6< GPU_DVOD<12> 6C3> 55B6< GPU_DVOD<12..19> 55D6> GPU_DVOD<13> 6C3> 55B6< GPU_DVOD<14> 6C3> 55B6< GPU_DVOD<15> 6C3> 55B6< GPU_DVOD<16> 6D3> 55B6< GPU_DVOD<17> 6C3> 55B6< GPU_DVOD<18> 6B3> 55B6< GPU_DVOD<19> 6C3> 55B6< GPU_DVOD<20> 6C3> 55B6< 55D6> GPU_DVOD<21> 6C3> 55B6< GPU_DVOD<21..23> 55D6> GPU_DVOD<22> 6C3> 55B6< GPU_DVOD<23> 6B3> 55B6< GPU_DVOD_R<0> 6C4< 53C7<> GPU_DVOD_R<23..0> 53D1> GPU_DVOD_R<1> 6C4< 53C7<> GPU_DVOD_R<2> 6C4< 53C7<> GPU_DVOD_R<3> 6C4< 53C7<> GPU_DVOD_R<4> 6D4< 53C7<> GPU_DVOD_R<5> 6C4< 53C7<> GPU_DVOD_R<6> 6D4< 53C7<> GPU_DVOD_R<7> 6D4< 53C7<> GPU_DVOD_R<8> 6C4< 53C7<> GPU_DVOD_R<9> 6D4< 53C7<> GPU_DVOD_R<10> 6D4< 53C7<> GPU_DVOD_R<11> 6D4< 53C7<> GPU_DVOD_R<12> 6C4< 53C7<> GPU_DVOD_R<13> 6C4< 53C7<> GPU_DVOD_R<14> 6C4< 53C7<> GPU_DVOD_R<15> 6C4< 53B7<> GPU_DVOD_R<16> 6D4< 53B7<> GPU_DVOD_R<17> 6C4< 53B7<> GPU_DVOD_R<18> 2B5> 6B4< 53B7<> GPU_DVOD_R<19> 6C4< 53B7<> GPU_DVOD_R<20> 6C4< 53B7<> GPU_DVOD_R<21> 6C4< 53B7<> GPU_DVOD_R<22> 6C4< 53B7<> GPU_DVOD_R<23> 6B4< 53B7<> GPU_DVOVMODE 53C7< GPU_DVO_CLKP 6C3> 54A6< 54C6> 55A6< 55C6> GPU_DVO_CLKP_R 6C4< 53C7<> 53D1> GPU_DVO_DE 6C3> 54A6< 54C6> 55B6< 55C6> GPU_DVO_DE_R 6C4< 53C7<> 53D1> GPU_DVO_HSYNC 6D3> 54A6< 54D6> 55B6< GPU_DVO_HSYNC_R 6D4< 53C7<> 53D1> GPU_DVO_VSYNC 6C3> 54A6< 54C6> 55A6< 55D6> GPU_DVO_VSYNC_R 6C4< 53C7<> 53D1> GPU_HSYNC_BUF 57B1<> GPU_MEMTEST 48A5<> GPU_MEMVMODE0 48A6< GPU_MEMVMODE1 48A6< GPU_MVREFD 48A7< GPU_MVREFS 48A8< GPU_RSTB_MSK 51B4< GPU_SSIN_PD 51B4< GPU_TESTEN 51B4< GPU_TV_C 53B4< 53C1> 57A8< GPU_TV_COMP 53B4<> 53C1> 57A8< GPU_TV_Y 53B4<> 53C1> 57A8< GPU_VCORE_HI 45B4<> GPU_VCORE_HI_L 45A5< 51B8<> GPU_VCORE_HI_L_RC 45A5<> GPU_VCORE_SW 45C4<> GPU_VGA_B 53C1> 53C4<> 57C8< GPU_VGA_G 53C1> 53C4<> 57C8< GPU_VGA_HSYNC 53B5<> 57B2< GPU_VGA_R 53C1> 53C4<> 57B8< GPU_VGA_VSYNC 53B5<> 57C2< GPU_VREFG 51A5< GPU_VSYNC_BUF 57C1<> HIGH_GPU_VCORE_DIV 45B3< HIGH_GPU_VCORE_L 45B3<> HPD_4V_REF 57A4< HPD_BASE 57A2<> HPD_ON 57A3<> HPD_ON_RC 57A3< HPD_PWR_SNS_EN 51B5<> 57A4<> HPD_PWR_SW 57A4<> I2C_GPU_TMDS_SCL 8A5< 8D6> I2C_GPU_TMDS_SDA 8A5< 8D6> I2C_I2_NB_SCL 8C2< 8D6> I2C_I2_NB_SDA 8C2< 8D6> I2C_I2_SB_SCL 8D2< 8D6> I2C_I2_SB_SDA 8D2< 8D6> I2C_PMU_SCL 8C5< 8D6> I2C_PMU_SDA 8C5< 8D6> I2C_PMU_SMB_SCL 8B5< 8D6> I2C_PMU_SMB_SDA 8B5< 8D6> I2C_VESTA_SCL 69B3<> I2C_VESTA_SDA 69B3<>

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

VID_MUX_OE_L 36D3<>

VIA_SB_TO_PMU 22B2< 25B2<>

VIA_REQ_L 22B2< 25B2<> 25B7<

VIA_PMU_TO_SB 22B5< 25B2<>

VIA_CLK 22B5< 25B2<>

VIA_ACK_L 22B5< 25B2<>

VGA_VSYNC 57C1< 57C3<>

VGA_R 53C1> 57B6< 57C3<>

VGA_HSYNC 57B1< 57C4<>

VGA_G 53C1> 57C3<> 57C6<

VGA_B 53C1> 57C4<> 57C6<

VESTA_RESET_L_RC 18A7<>

VESTA_RESET_L 18A6<>

VESTA_RESET 18A7<> 66B8<

VESTA_RDAC2_PD 69B3<>

VESTA_RDAC1_PD 66A4<>

VESTA_PWR_CLASS_MSB 69A6< 69B5<

VESTA_PORT2_DISABLE_L 69A6< 69C5<

VESTA_PORT1_DISABLE_L 69A6< 69C5<

VESTA_LPWR_1394 69B5<

VESTA_ENET_LOWPWR 66B6<>

VESTA_DS_ONLY_EN0 69A6< 69B5<

VESTA_CPS 69C5<>

VESTA_CLK25M_XTALO_R 66A6<> 66D6>

VESTA_CLK25M_XTALO 66A5< 66D6>

VESTA_CLK25M_XTALI 66A6< 66D6>

VESTA_CLK24M_XTALO_R 69B5<> 69D6>

VESTA_CLK24M_XTALO 69A4< 69D6>

VESTA_CLK24M_XTALI 69B5< 69D6>

VESTA_BILINGUAL_EN12_L 69A6< 69C5<

VESTA3V3_SW 18D4<>

VESTA2V5_NOISE 18D2<>

VESTA1V2_VFB 18C3<>

VESTA1V2_SW 18C3<>

VESTA1V2_SGND 18B3<>

VESTA1V2_RT 18C4<>

VESTA1V2_MODE 18C4<>

VESTA1V2_ITH_RC 18C3<

VESTA1V2_ITH 18C3<>

VCORE_VID_B<4> 36D3< 36D3<

VCORE_VID_B<3> 36D3< 36D3<

VCORE_VID_B<2> 36D3< 36D3<

VCORE_VID_B<1> 36D3< 36D3<

VCORE_VID_A<4> 36C2< 36D3< 36D4<

VCORE_VID_A<3> 36C2< 36D3< 36D4<

VCORE_VID_A<2> 36C2< 36D3< 36D4<

VCORE_VID_A<1> 36C2< 36D3< 36D4<

VCORE_VID<4> 36A2<> 36B8< 36D1<>

VCORE_VID<3> 36A2<> 36B8< 36D1<>

VCORE_VID<2> 36A2<> 36B8< 36D1<>

VCORE_VID<1> 36A2<> 36B8< 36D1<>

VCORE_VID<0> 36A2<> 36B8<

VCORE_VCC 36C6<

VCORE_TON 36B6<

VCORE_TIME 36B4<>

VCORE_SNS 36A2<> 36D6>

VCORE_SEL_ON 36B6<>

VCORE_SEL_OFF_PU 36B6<>

VCORE_REF 36B6<>

VCORE_LX 36B5<>

VCORE_ILIM 36C6<>

VCORE_GNDSNS_TEST 36A3<>

VCORE_GNDSNS 36A2<> 36A4< 36D6>

VCORE_GNDDIV_TEST 36A3<>

VCORE_GNDDIV 36A4< 36B5<

VCORE_GNDA 36B5<>

VCORE_GND 36B5<>

VCORE_FB 36B5<

VCORE_DL 36B5<>

VCORE_DH 36B5<>

VCORE_CPU0_SHDN_L 26B4<> 36C7<>

VCORE_CC 36B6<>

VCORE_BST 36C5<>

VCORE_BOOST 36C4<>

USB_TPAD_P 7D5> 11C5< 30C6<>

USB_TPAD_N 7D5> 11C5< 30C6<>

USB_NEC_TPAD_P 6A3> 11B6< 11C4<

USB_NEC_TPAD_N 6A3> 11B6< 11C4<

USB_NEC_P<3> 73B3<>

USB_NEC_P<2> 73B3<>

USB_NEC_P<1> 2B4> 73C3<>

USB_NEC_P<0> 2B4> 73C3<>

USB_NEC_N<3> 2B4> 73B3<>

USB_NEC_N<2> 2B4> 73B3<>

USB_NEC_N<1> 2B4> 73C3<>

USB_NEC_N<0> 73C3<>

USB_NEC_BT_P 6A3> 11B6< 11D4<

USB_NEC_BT_N 2B4> 6A3> 11B6< 11C4<

USB_I2_TPAD_P 6B3> 11B8< 11C4<

USB_I2_TPAD_N 6B3> 11B8< 11C4<

USB_I2_BT_P 6B3> 11B8< 11C4<

USB_I2_BT_N 6B3> 11B8< 11C4<

USB_BT_P 11D5< 60B3<>

USB_BT_N 11C5< 60B3<>

USB2_RIGHT_PORT_P 7B5> 11C7< 31B7<>

USB2_RIGHT_PORT_N 7B5> 11C7< 31B7<>

USB2_OC<4> 73B6<

USB2_OC<3> 73B6<

USB2_OC<2> 73B6<

USB2_OC<1> 73B6<

USB2_OC<0> 73B6<

USB2_NEC_RIGHT_PORT_P 6B3> 11B6< 11C5<

USB2_NEC_RIGHT_PORT_N 6B3> 11B6< 11C5<

USB2_NEC_P<3> 11B5> 73B2<> 73D7>

USB2_NEC_P<2> 11B5> 73B2<> 73D7>

USB2_NEC_P<1> 11B5> 73C2<> 73D7>

USB2_NEC_P<0> 11B5> 73C2<> 73D7>

USB2_NEC_N<3> 11B5> 73B2<> 73D7>

USB2_NEC_N<2> 11B5> 73B2<> 73D7>

USB2_NEC_N<1> 11B5> 73C2<> 73D7>

USB2_NEC_N<0> 11B5> 73C2<> 73D7>

USB2_NEC_LEFT_PORT_P 6B3> 11B6< 11D5<

USB2_NEC_LEFT_PORT_N 6B3> 11B6< 11C5<

USB2_LEFT_PORT_P 7B5> 11D7< 74C4<>

USB2_LEFT_PORT_N 7B5> 11C7< 74C4<>

USB2_I2_RIGHT_PORT_P 6B3> 11B8< 11C5<

USB2_I2_RIGHT_PORT_N 6B3> 11B8< 11C5<

USB2_I2_P<5> 11B7> 72B4< 72D6>

USB2_I2_P<4> 11B7> 72B4< 72D6>

USB2_I2_P<3> 6B3> 72B4< 72D6>

USB2_I2_P<2> 11B7> 72C4< 72D6>

USB2_I2_P<1> 6B3> 72C4< 72D6>

USB2_I2_P<0> 11B7> 72C4< 72D6>

USB2_I2_N<5> 11B7> 72B4< 72D6>

USB2_I2_N<4> 11B7> 72B4< 72D6>

USB2_I2_N<3> 6B3> 72B4< 72D6>

USB2_I2_N<2> 11B7> 72B4< 72D6>

USB2_I2_N<1> 6B3> 72C4< 72D6>

USB2_I2_N<0> 11B7> 72C4< 72D6>

USB2_I2_LEFT_PORT_P 6B3> 11B8< 11C5<

USB2_I2_LEFT_PORT_N 6B3> 11B8< 11C5<

UATA_STOP_R 63B2< 63B3< 63D6>

UATA_STOP 7B7> 63B1> 63D6> 64B2<> 64B5<>

UATA_RESET_L_R 63B2< 63B3< 63D6>

UATA_RESET_L 7B7> 63B1> 63C6> 64C2<> 64C7<>

UATA_PDIAG 64B4<> 64B7<>

UATA_INTRQ_R 63A2< 63B5< 63D6>

UATA_INTRQ 7B7> 63A1< 63C6> 64B2<> 64B5<>

UATA_HSTROBE_R 63B2< 63B3< 63D6>

UATA_HSTROBE 7B7> 63B1> 63D6> 64B4<> 64B7<>

UATA_DSTROBE_R 63A2< 63B5< 63D6>

UATA_DSTROBE 7B7> 63A1< 63C6> 64B2<> 64B5<>

UATA_DMARQ_R 63B2< 63B5< 63D6>

UATA_DMARQ 7B7> 63B1< 63C6> 64B4<> 64B7<>

UATA_DMACK_L_R 63B2< 63B3< 63D6>

UATA_DMACK_L 7B7> 63B1> 63C6> 64B4<> 64B7<>

UATA_DD_R<15> 6C8<

UATA_DD_R<14> 6C8<

UATA_DD_R<13> 6C8<

UATA_DD_R<12> 6C8<

UATA_DD_R<11> 6C8<

UATA_DD_R<10> 2B5> 6C8<

UATA_DD_R<9> 6C8<

UATA_DD_R<15..8> 63D6>

UATA_DD_R<8> 2B5> 6C8<

UATA_DD_R<7> 6C8< 63D6>

UATA_DD_R<6> 6C8<

UATA_DD_R<5> 6C8<

UATA_DD_R<4> 6C8<

UATA_DD_R<3> 6C8<

UATA_DD_R<2> 6C8<

UATA_DD_R<1> 6B8<

UATA_DD_R<15..0> 63C3>

UATA_DD_R<6..0> 63D6>

UATA_DD_R<0> 2B5> 6C8<

UATA_DD<15> 6C6> 64B4<> 64C5<>

UATA_DD<14> 6C6> 64B4<> 64C5<>

UATA_DD<13> 6C6> 64B4<> 64C5<>

UATA_DD<12> 6C6> 64C4<> 64C5<>

UATA_DD<11> 6C6> 64C4<> 64C5<>

UATA_DD<10> 6C6> 64C4<> 64C5<>

UATA_DD<9> 6C6> 64C4<> 64C5<>

UATA_DD<8> 6C6> 64C4<> 64C5<>

UATA_DD<7> 6C6> 64C2<> 64C7<>

UATA_DD<6> 6C6> 64C2<> 64C7<>

UATA_DD<5> 6C6> 64C2<> 64C7<>

UATA_DD<4> 6C6> 64C2<> 64C7<>

UATA_DD<3> 6C6> 64C2<> 64C7<>

UATA_DD<2> 6C6> 64B2<> 64C7<>

UATA_DD<1> 6B6> 64B2<> 64C7<>

UATA_DD<15..0> 7B7> 63D6>

UATA_DD<0> 6C6> 64B2<> 64C7<>

UATA_DA_R<2> 6C8<

UATA_DA_R<1> 2B5> 6B8<

UATA_DA_R<2..0> 63B3> 63D6>

UATA_DA_R<0> 2B5> 6C8<

UATA_DASP_L 64B2<> 64B5<>

UATA_DA<2> 6C6> 64B4<> 64B5<>

UATA_DA<1> 6B6> 64B2<> 64B7<>

UATA_DA<2..0> 7B7> 63D6>

UATA_DA<0> 6C6> 64B2<> 64B7<>

UATA_CS1_L_R 63B2< 63B3< 63D6>

UATA_CS1_L 7B7> 63B1> 63D6> 64B4<> 64B5<>

UATA_CS0_L_R 6C8< 63B3< 63D6>

UATA_CS0_L 6C6> 7B7> 63D6> 64B2<> 64B7<>

TV_Y 53C1> 57A7<>

TV_COMP 53C1> 57A7<>

TV_C 53C1> 57A7<>

TP_VESTA_XMTLED_L 66A3>

TP_VESTA_TXC_RXC_DELAY 66B3<>

TP_VESTA_TVCO_24 69B5<>

TP_VESTA_TVCO 66A6<>

TP_VESTA_TEST_1394<1> 69B5<

TP_VESTA_TEST_1394<0> 69B5<

TP_VESTA_TEST<1> 66B6<

TP_VESTA_TEST<0> 66B6<

TP_VESTA_TDBL<2> 69C2>

TP_VESTA_TDBL<1> 69C2>

TP_VESTA_TDBL<0> 69C2>

TP_VESTA_SPD0 2B4> 66B6<

TP_VESTA_RGMIIEN 66B6<

TP_VESTA_REGSUP2 18A3<

TP_VESTA_REGSUP1 18A3<

TP_VESTA_REGSEN2 2B4> 18A3<

TP_VESTA_REGSEN1 18A3<

TP_VESTA_REGCTL2 18A3<

TP_VESTA_REGCTL1 18A3<

TP_VESTA_RBC1 66B3<>

TP_VESTA_RBC0 66B3<>

TP_VESTA_PHYA<4> 66B6<

TP_VESTA_PHYA<3> 66B6<

TP_VESTA_PHYA<2> 66B6<

TP_VESTA_PHYA<1> 66B6<

TP_VESTA_PHYA<0> 2B4> 66B6<

TP_VESTA_MANMS 66B6<

TP_VESTA_LINKSPD2_L 66B3>

TP_VESTA_LINKSPD1_L 66B3>

TP_VESTA_HUB 66B6<

TP_VESTA_FDXLED_L 66B3>

TP_VESTA_FDX 66B6<

TP_VESTA_F1000 2B4> 66B6<

TP_VESTA_ER 66B6<

TP_VESTA_EN_10B 66B6<

TP_VESTA_DNC_E9 2B4> 18A6<>

TP_VESTA_DNC_C9 18A6<>

TP_VESTA_DNC_B9 18A6<>

TP_VESTA_AN_EN 66B3<>

TP_VESTA_ACTLED_L 66A3>

TP_VESTA_2_5V_EN 18A3<

TP_VCORE_PGOOD 26B4>

TP_USB2_PWREN<4> 73B5>

TP_USB2_PWREN<3> 2B5> 73B5>

TP_USB2_PWREN<2> 2B5> 73B5>

TP_USB2_PWREN<1> 73B5>

TP_USB2_PWREN<0> 2B5> 73B5>

TP_RT_KYBRD_SCREW 2C3<>

TP_PMU_P7_5 11B3> 25A5< 25C2<>

TP_PMU_P7_4 11B1> 25A5< 25C2<>

TP_PMU_P7_2 25A7< 25C2<>

TP_PMU_P7_1 25A8< 25C2<>

TP_PMU_P7_0 25A8< 25C2<>

TP_PMU_P3_3 11A3> 25A5< 25B5<>

TP_PMU_P3_2 11A3> 25A5< 25B5<>

TP_PMU_P3_1 11A3> 25A5< 25B5<>

TP_PMU_P3_0 11A3> 25A5< 25B5<>

TP_PMU_AN_P10_7 25A4< 25B2<>

TP_PMU_AN_P10_6 11B3> 25A7< 25B2<>

TP_PMU_AN_P10_5 11A1> 25A7< 25B2<>

TP_PMU_AN_P10_4 25A7< 25B2<>

TP_PMU_AN_P10_3 25A7< 25B2<>

TP_PMU_AN_P10_2 25A8< 25B2<>

TP_PMU_AN_P10_1 25A8< 25B2<>

TP_PMU_AN_P10_0 25A8< 25B2<>

TP_PMU_AN_P0_7 25A8< 25C5<>

TP_PMU_AN_P0_6 25A8< 25C5<>

TP_PMU_AN_P0_5 11B1> 25C5<>

TP_PMU_AN_P0_4 11B1> 25C5<>

TP_PMU_AN_P0_3 11B1> 25C5<>

TP_PMU_AN_P0_2 11B1> 25C5<>

TP_PMU_AN_P0_1 11B1> 25C5<>

TP_PMU_AN_P0_0 11B1> 25C5<>

TP_PCI_CLK33M_ZDBOUT3 11B2>

TP_PCI_CLK33M_SLOTD_R 11D4< 59C3< 59D6>

TP_PCI_CLK33M_SLOTA_R 11D4< 59C3< 59D6>

TP_OPTICAL_DRIVE_SCREW 2C3<>

TP_NEC_TEST 62A3<

TP_NEC_TEB 62B3<

TP_NEC_SRMOD 62A3<

TP_NEC_SRDATA 62A3<>

TP_NEC_SRCLK 2B5> 62A3>

TP_NEC_SMI_L 2B5> 62A5>

TP_NEC_SMC 2B5> 62B3<

TP_NEC_NTEST1 62B3<

TP_NEC_NANDTEST 62A3<

TP_NEC_AMC 62A3<

TP_MAXBUS_TBEN_I2 32A3<

TP_MAXBUS_CPU1_QACK_L 11A5< 32D3<

TP_MAXBUS_CLK_CPU1_R 11D7< 32D3< 32D6>

TP_LVDS_U3_P 53B7>

TP_LVDS_U3_N 53B7>

TP_LVDS_L3_P 53A7>

TP_LVDS_L3_N 53A7>

TP_LEFT_KYBRD_SCREW 2C3<>

TP_JTAG_VESTA_TMS 9A5<>

TP_JTAG_VESTA_TDO 9A5>

TP_JTAG_VESTA_TDI 9A7<

TP_JTAG_VESTA_TCK 9A5<>

TP_JTAG_I2_TDO 9C5>

TP_JTAG_CPU_TDO 9D5>

TP_I2_PENDINT 22A2<

TP_GOV_RESET_L 11B3>

TP_EXTTMDS_RESET_L 11C8< 51B5<>

TP_ENET_ENERGYDET 11A7<

TP_CPU0_TEMP_CATHODE 34D4<>

TP_CPU0_TEMP_ANODE 34D4<>

TP_CPU0_SENSEVDD2 35B8<

TP_CPU0_SENSEVDD1 35B8<

TP_CPU0_SENSEGND2 35B6<

TP_CPU0_SENSEGND1 35B6<

TP_CPU0_PMON_OUT_L 34D4>

TP_CPU0_OVDDSENSE2 33B8<

TP_CPU0_OVDDSENSE1 33B8<

TP_CPU0_HPR_N 34C4<>

TP_CPU0_CLKOUT 33C1>

TP_ATI_GPIO12 51B5<>

TP_ATI_GPIO11 51B5<>

TP_ATI_GPIO10 51B5<>

TP_ATI_GPIO9 51B5<>

TP_ATI_GPIO8 51B5<>

TP_AIRPORT_PME_L 60C3<>

TP_AIRPORT_ALT_ANTENNA 60B3<>

TPS2211_SHTDWN_L 61C5<

TMDS_DP<5> 55B2< 55C1< 55C6> 57B6<>

TMDS_DP<4> 55B2< 55C6> 55D1< 57C6<>

TMDS_DP<3> 55C2< 55C6> 55D1< 57C6<>

TMDS_DP<2> 54B1> 54C2< 54D4< 57C6<>

TMDS_DP<1> 54B1> 54D3< 54D4< 57D6<>

TMDS_DP<0> 54B1> 54D2< 54D5< 57D6<>

TMDS_DN<5> 55B1< 55C6> 55D1< 57B6<>

TMDS_DN<4> 55B1< 55C6> 55D1< 57C6<>

TMDS_DN<3> 55C1< 55C6> 55D1< 57C6<>

TMDS_DN<2> 54B1> 54C1< 54D4< 57D6<>

TMDS_DN<1> 54B1> 54D2< 54D4< 57D6<>

TMDS_DN<0> 54B1> 54D1< 54D5< 57D6<>

TMDS_D5_CMF 55B1<

TMDS_D4_CMF 55C1<

TMDS_D3_CMF 55C1<

TMDS_CONN_DP<5> 57B5<> 57C4<> 57D6>

TMDS_CONN_DP<4> 57C3<> 57C5<> 57D6>

TMDS_CONN_DP<3> 57C3<> 57C5<> 57D6>

TMDS_CONN_DP<2> 57C5<> 57D3<> 57D6>

TMDS_CONN_DP<1> 57D3<> 57D5<> 57D6>

TMDS_CONN_DP<0> 57D4<> 57D5<> 57D6>

TMDS_CONN_DN<5> 57B5<> 57C4<> 57D6>

TMDS_CONN_DN<4> 57C3<> 57C5<> 57D6>

TMDS_CONN_DN<3> 57C3<> 57C5<> 57D6>

TMDS_CONN_DN<2> 57D3<> 57D5<> 57D6>

TMDS_CONN_DN<1> 57D3<> 57D5<> 57D6>

TMDS_CONN_DN<0> 57D4<> 57D5<> 57D6>

TMDS_CONN_CLKP 2B5> 57C4<> 57C5<> 57D6>

TMDS_CONN_CLKN 57C4<> 57C5<> 57D6>

TMDS_CLKP 54B1> 54D3< 54D5< 57C6<>

TMDS_CLKN 54B1> 54D2< 54D5< 57C6<>

THERM_D2_P 27B5< 27C4<> 27C5< 27D6>

THERM_D2_N 27B5< 27C4<> 27C5< 27D6>

THERM_D1_P 27B5< 27C4<> 27C5< 27D6>

THERM_D1_N 27B5< 27C4<> 27C5< 27D6>

THERM2_M_P 27C6< 27C8< 27D6>

THERM2_M_N 27B8< 27C6< 27D6>

THERM2_A_P 27B6< 27B8< 27D6>

THERM2_A_N 27A8< 27B6< 27D6>

THERM1_M_P 27C6< 27C8< 27D6>

THERM1_M_N 27C6< 27C8< 27D6>

THERM1_A_P 27B6< 27B8< 27D6>

THERM1_A_N 27B6< 27B8< 27D6>

TBEN_SYNC_F2 21B3<>

TBEN_SYNC_F1 21B4<>

TBEN_SYNC_CLR_L 21A4<>

SYS_WATCHDOG 22A2< 25B5<>

SYS_WARM_RESET_L 22A2<> 22A5< 25A7< 25C2<> 62A7<

SYS_SLEEP 25A7< 25B5<>

SYS_RESET_BUTTON_L 24B2< 25B7< 25C5<> 36A3<>

SYS_PWRSEQ_TPAD_L 11B2< 26C5<

SYS_PWRSEQ_FINAL 11A2< 26A8<>

SYS_PWRSEQ_6_LS5 26A7<>

SYS_PWRSEQ_6_L 11B2< 26A8<>

SYS_PWRSEQ_5 11B2< 26B8<>

SYS_PWRSEQ_4 11B2< 26B8<>

SYS_PWRSEQ_3_LS5 26C7<>

SYS_PWRSEQ_3_L 11B2< 26C8<>

SYS_PWRSEQ_2_L 26D6<>

SYS_PWRSEQ_2 11B2< 26D8<>

SYS_PWRSEQ_1_L 26D4<>

SYS_PWRSEQ_1 11B2< 26D8<>

SYS_POWER_UP_L 26D6<>

SYS_POWER_BUTTON_L_F 7C5> 30C5<>

36A3<> 57B1<>

SYS_POWER_BUTTON_L 24B2< 24C8<> 25B7< 25C5<> 30C3<

SYS_POWERUP 26D5<>

SYS_PMU_ANALOG_AC_DET 11B4< 12C2<

SYS_PME_L 22A2< 25B7< 25C2<> 62A7<

SYS_OVERTEMP_L 7C5> 11B4< 25B7< 25C2<> 30C6<>

SYS_ONEWIRE 24A7< 25B2<>

SYS_LID_OPEN_F 7C5> 30C5<>

SYS_LID_OPEN 25C5<> 30C2<

SYS_LED 24B8< 25C2<>

SYS_KBDLED 25C2<> 28A5<>

SYS_COLD_RESET_L 25B7< 25C2<>

SYS_CHARGE_LED_L 7C5> 24A6< 74C6<>

SYS_BATT0_DET_L 12A5< 24C8<> 25C2<>

SYS_ADAPTER_ANALOG_AC_DET 7C5> 12D4< 74C6<>

SYS_AC_DET_L 12C6<> 24D8<>

SYS_AC_DET 12C6<> 25C2<>

SYS_ACIN_L_RC 13C2<>

SYS_ACIN_L 12C5<> 13C3<>

SYS_ACIN 12C6<> 13C8<> 18B8< 25C2<>

STOP_AGP_L 43D2< 43D3< 44B4<

SPI_PMU_TO_CHGR_MOSI 25A4>

SPI_PMU_CHGR_CS 25A4>

SPI_PMU_CHGR_CLK 25A4>

SPI_CHGR_TO_PMU_MISO 25A4>

SOFTMODEM_FC_RGDT 30A7<>

SLEEP_LED_SW_L 24B7<

SLEEP_LED_L 24B7<

SLEEP_LED_IOUT 11A4

SLEEP_LED_I 24B6<

SLEEP_LED_DGND 30B4<>

SLEEP_LED_CONN 30B4<>

SI_VREF 54A3< 54A3< 55A4<

SI_TMDS_RESET_L 11C8

SI_TMDS_DP<5> 55B4< 55C2< 55C6>

SI_TMDS_DP<4> 55B4< 55C6> 55D2<

SI_TMDS_DP<3> 2B4> 55B4< 55C6> 55D2<

SI_TMDS_DP<2> 54B3< 54C6> 54D5<

SI_TMDS_DP<1> 54B3< 54C6> 54D5<

SI_TMDS_DP<0> 54B3< 54C6> 54D7<

SI_TMDS_DN<5> 2B4> 55B4< 55C6> 55D2<

SI_TMDS_DN<4> 2B4> 55B4< 55C6> 55D2<

SI_TMDS_DN<3> 55B4< 55C6> 55D2<

SI_TMDS_DN<2> 2B4> 54B3< 54C6> 54D5<

SI_TMDS_DN<1> 2B4> 54B3< 54C6> 54D5<

SI_TMDS_DN<0> 2B4> 54B3< 54C6> 54D7<

SI_TMDS_CLKP 2A4> 54B3< 54C6> 54D7<

SI_TMDS_CLKN 54B3< 54C6> 54D7<

SI_S_MSEN 55B4<>

SI_S_EXTSWING 55B4<

SI_S_A1 55B6<

SI_SYNC 54B6<> 55B6<>

SI_M_MSEN 54B3<>

SI_M_EXTSWING 54A3<

SI_M_A1 54B6<

SI_IDCK_N 54A4< 54A6< 55A6<

SI_HTPLG 54B6< 55B6<

SCCA_TXD_L 7B5> 22B2< 24C1<>

SCCA_RXD 7B5> 22B6< 24C2<>

RT_ALS_PHOTODIODE 28D5<>

RT_ALS_OUT_FB 28D4<>

RT_ALS_OP_IN 28D5<

RT_ALS_OP_COMP 28D4<

ROM_WP_L 58B5<

ROM_WE_L 58B6< 59C3< 60B3<>

ROM_ONBOARD_CS_L 58B6< 60B5<>

ROM_OE_L 58B6< 59C3< 60B3<>

ROM_CS_L 58B6< 59C3< 60B5<>

RAM_WE_L_R 38B3> 38D6> 39B8<

RAM_WE_L 39A6> 39B7< 40B6< 41B6<

RAM_VREF 40A7<

RAM_RAS_L_R 38B3> 38D6> 39B8<

RAM_RAS_L 39A6> 39B7< 40B4< 41B4<

RAM_ODT_R<1> 38B3> 38C6> 39B8<

RAM_ODT_R<0> 38B3> 38D6> 39B8<

RAM_ODT<1> 39B7< 41B4<

RAM_ODT<1..0> 39A6>

RAM_ODT<0> 39B7< 40B4<

RAM_DQS_P_R<7> 38C6>

RAM_DQS_P_R<6> 38C6>

RAM_DQS_P_R<5> 38C6>

RAM_DQS_P_R<4> 38C6>

RAM_DQS_P_R<3> 38C6>

RAM_DQS_P_R<2> 38C6>

RAM_DQS_P_R<1> 38C6>

RAM_DQS_P_R<7..0> 38C3<> 39B6<

RAM_DQS_P_R<0> 38C6>

RAM_DQS_B_P<7> 41A4<

RAM_DQS_B_P<6> 41A6<

RAM_DQS_B_P<5> 41B4<

RAM_DQS_B_P<4> 41B6<

RAM_DQS_B_P<3> 41C4<

RAM_DQS_B_P<2> 41C6<

RAM_DQS_B_P<1> 41D6<

RAM_DQS_B_P<7..0> 39B5>

RAM_DQS_B_P<0> 41D6<

RAM_DQS_B_N<7> 39A5< 41A4<

RAM_DQS_B_N<6> 39A5< 41A6<

RAM_DQS_B_N<5> 39A5< 41B4<

RAM_DQS_B_N<4> 39A5< 41B6<

RAM_DQS_B_N<3> 39A5< 41C4<

RAM_DQS_B_N<2> 39A5< 41C6<

RAM_DQS_B_N<1> 39B5< 41D6<

RAM_DQS_B_N<0> 39A5< 41D6<

RAM_DQS_A_P<7> 40A4<

RAM_DQS_A_P<6> 40A6<

RAM_DQS_A_P<5> 40B4<

RAM_DQS_A_P<4> 40B6<

RAM_DQS_A_P<3> 40C4<

RAM_DQS_A_P<2> 40C6<

RAM_DQS_A_P<1> 40D6<

RAM_DQS_A_P<7..0> 39B5>

RAM_DQS_A_P<0> 40D6<

RAM_DQS_A_N<7> 39A5< 40A4<

RAM_DQS_A_N<6> 39A5< 40A6<

RAM_DQS_A_N<5> 39A5< 40B4<

RAM_DQS_A_N<4> 39A5< 40B6<

RAM_DQS_A_N<3> 39B5< 40C4<

RAM_DQS_A_N<2> 39A5< 40C6<

RAM_DQS_A_N<1> 39A5< 40D6<

RAM_DQS_A_N<0> 39A5< 40D6<

RAM_DQS<7..0> 39A6> 39B6

RAM_DQM_R<7> 38C6>

RAM_DQM_R<6> 38C6>

RAM_DQM_R<5> 38C6>

RAM_DQM_R<4> 38C6>

RAM_DQM_R<3> 38C6>

RAM_DQM_R<2> 38C6>

RAM_DQM_R<1> 38C6>

RAM_DQM_R<7..0> 38B3> 39B6<

RAM_DQM_R<0> 38C6>

RAM_DQM_B<7> 41A6<

RAM_DQM_B<6> 41A4<

RAM_DQM_B<5> 41B6<

RAM_DQM_B<4> 41B4<

RAM_DQM_B<3> 41C6<

RAM_DQM_B<2> 41C4<

RAM_DQM_B<1> 41D4<

RAM_DQM_B<7..0> 39B5>

RAM_DQM_B<0> 41D4<

RAM_DQM_A<7> 40A6<

RAM_DQM_A<6> 40A4<

RAM_DQM_A<5> 40B6<

RAM_DQM_A<4> 40B4<

RAM_DQM_A<3> 40C6<

RAM_DQM_A<2> 40C4<

RAM_DQM_A<1> 40D4<

RAM_DQM_A<7..0> 39B5>

RAM_DQM_A<0> 40D4<

RAM_DQM<7..0> 39A6> 39B6

RAM_DATA_R<63..56> 38B6>

RAM_DATA_R<55..48> 38C6>

RAM_DATA_R<47..40> 38C6>

RAM_DATA_R<39..32> 38C6>

RAM_DATA_R<31..24> 38C6>

RAM_DATA_R<23..16> 38C6>

RAM_DATA_R<15..8> 38C6>

RAM_DATA_R<63..0> 38D6<> 39B6<

RAM_DATA_R<7..0> 38C6>

RAM_DATA_B<63> 41A6<

RAM_DATA_B<62> 41A4<

RAM_DATA_B<61> 41A6<

RAM_DATA_B<60> 41A4<

RAM_DATA_B<59> 41A6<

RAM_DATA_B<58> 41A4<

RAM_DATA_B<57> 41A4<

RAM_DATA_B<56> 41A6<

RAM_DATA_B<55> 41A6<

RAM_DATA_B<54> 41A4<

RAM_DATA_B<53> 41A4<

RAM_DATA_B<52> 41A6<

RAM_DATA_B<51> 41A6<

RAM_DATA_B<50> 41A4<

RAM_DATA_B<49> 41A6<

RAM_DATA_B<48> 41A4<

RAM_DATA_B<47> 41B6<

RAM_DATA_B<46> 41B4<

RAM_DATA_B<45> 41A4<

RAM_DATA_B<44> 41A4<

RAM_DATA_B<43> 41B6<

RAM_DATA_B<42> 41A6<

RAM_DATA_B<41> 41A6<

RAM_DATA_B<40> 41B4<

RAM_DATA_B<39> 41B4<

RAM_DATA_B<38> 41B4<

RAM_DATA_B<37> 41B6<

RAM_DATA_B<36> 41B6<

RAM_DATA_B<35> 41B6<

RAM_DATA_B<34> 41B6<

RAM_DATA_B<33> 41B4<

RAM_DATA_B<32> 41B4<

RAM_DATA_B<31> 41C4<

RAM_DATA_B<30> 41C4<

RAM_DATA_B<29> 41C6<

RAM_DATA_B<28> 41C4<

RAM_DATA_B<27> 41C6<

RAM_DATA_B<26> 41C6<

RAM_DATA_B<25> 41C6<

RAM_DATA_B<24> 41C4<

RAM_DATA_B<23> 41C4<

RAM_DATA_B<22> 41C6<

RAM_DATA_B<21> 41C4<

RAM_DATA_B<20> 41C4<

RAM_DATA_B<19> 41C6<

RAM_DATA_B<18> 41D4<

RAM_DATA_B<17> 41D6<

RAM_DATA_B<16> 41C6<

RAM_DATA_B<15> 41D4<

RAM_DATA_B<14> 41D6<

RAM_DATA_B<13> 41D6<

RAM_DATA_B<12> 41D4<

RAM_DATA_B<11> 41D4<

RAM_DATA_B<10> 41D6<

RAM_DATA_B<9> 41D4<

RAM_DATA_B<8> 41D6<

RAM_DATA_B<7> 41D6<

RAM_DATA_B<6> 41D6<

RAM_DATA_B<5> 41D4<

RAM_DATA_B<4> 41D4<

RAM_DATA_B<3> 41D4<

RAM_DATA_B<2> 41D6<

RAM_DATA_B<1> 41D6<

RAM_DATA_B<63..0> 39B5>

RAM_DATA_B<0> 41D4<

RAM_DATA_A<63> 40A6<

RAM_DATA_A<62> 40A4<

RAM_DATA_A<61> 40A6<

RAM_DATA_A<60> 40A4<

RAM_DATA_A<59> 40A6<

RAM_DATA_A<58> 40A4<

RAM_DATA_A<57> 40A4<

RAM_DATA_A<56> 40A6<

RAM_DATA_A<55> 40A6<

RAM_DATA_A<54> 40A4<

RAM_DATA_A<53> 40A4<

RAM_DATA_A<52> 40A6<

RAM_DATA_A<51> 40A6<

RAM_DATA_A<50> 40A4<

RAM_DATA_A<49> 40A6<

RAM_DATA_A<48> 40A4<

RAM_DATA_A<47> 40B6<

RAM_DATA_A<46> 40B4<

RAM_DATA_A<45> 40A4<

RAM_DATA_A<44> 40A4<

RAM_DATA_A<43> 40B6<

RAM_DATA_A<42> 40A6<

RAM_DATA_A<41> 40A6<

RAM_DATA_A<40> 40B4<

RAM_DATA_A<39> 40B4<

RAM_DATA_A<38> 40B4<

RAM_DATA_A<37> 40B6<

RAM_DATA_A<36> 40B6<

RAM_DATA_A<35> 40B6<

RAM_DATA_A<34> 40B6<

RAM_DATA_A<33> 40B4<

RAM_DATA_A<32> 40B4<

RAM_DATA_A<31> 40C4<

RAM_DATA_A<30> 40C4<

RAM_DATA_A<29> 40C6<

RAM_DATA_A<28> 40C4<

RAM_DATA_A<27> 40C6<

RAM_DATA_A<26> 40C6<

RAM_DATA_A<25> 40C6<

RAM_DATA_A<24> 40C4<

RAM_DATA_A<23> 40C4<

RAM_DATA_A<22> 40C6<

RAM_DATA_A<21> 40C4<

RAM_DATA_A<20> 40C4<

RAM_DATA_A<19> 40C6<

RAM_DATA_A<18> 40D4<

RAM_DATA_A<17> 40D6<

RAM_DATA_A<16> 40C6<

RAM_DATA_A<15> 40D4<

RAM_DATA_A<14> 40D6<

RAM_DATA_A<13> 40D6<

RAM_DATA_A<12> 40D4<

RAM_DATA_A<11> 40D4<

RAM_DATA_A<10> 40D6<

RAM_DATA_A<9> 40D4<

RAM_DATA_A<8> 40D6<

RAM_DATA_A<7> 40D6<

RAM_DATA_A<6> 40D6<

RAM_DATA_A<5> 40D4<

RAM_DATA_A<4> 40D4<

RAM_DATA_A<3> 40D4<

RAM_DATA_A<2> 40D6<

RAM_DATA_A<1> 40D6<

RAM_DATA_A<63..0> 39B5>

RAM_DATA_A<0> 40D4<

RAM_DATA<63..0> 39A6> 39B6

RAM_CS_L_R<3> 39C6<

RAM_CS_L_R<3..2> 38D6>

RAM_CS_L_R<2> 39C6<

RAM_CS_L_R<1> 39C6<

RAM_CS_L_R<3..0> 38C3>

RAM_CS_L_R<1..0> 38D6>

RAM_CS_L_R<0> 39C6<

RAM_CS_L<3> 39C4> 41B6<

RAM_CS_L<2> 39C4> 41B4<

RAM_CS_L<1> 39C4> 40B6<

RAM_CS_L<3..0> 39A6>

RAM_CS_L<0> 39C4> 40B4<

RAM_CLKDDR_3_P_R 38A3> 38D6> 39C6<

RAM_CLKDDR_3_P 39A6> 39C4> 41A4<

RAM_CLKDDR_3_N_R 38A3> 38D6> 39C6<

RAM_CLKDDR_3_N 39A6> 39C4> 41A4<

RAM_CLKDDR_2_P_R 38A3> 38D6> 39D6<

RAM_CLKDDR_2_P 39A6> 39D4> 41D4<

RAM_CLKDDR_2_N_R 38A3> 38D6> 39C6<

RAM_CLKDDR_2_N 39A6> 39C4> 41D4<

RAM_CLKDDR_1_P_R 38A3> 38D6> 39D6<

RAM_CLKDDR_1_P 39A6> 39D4> 40A4<

RAM_CLKDDR_1_N_R 38A3> 38D6> 39D6<

RAM_CLKDDR_1_N 39A6> 39D4> 40A4<

RAM_CLKDDR_0_P_R 38B3> 38D6> 39D6<

RAM_CLKDDR_0_P 39A6> 39D4> 40D4<

RAM_CLKDDR_0_N_R 38A3> 38D6> 39D6<

RAM_CLKDDR_0_N 39A6> 39D4> 40D4<

RAM_CKE_R<3> 39B6<

RAM_CKE_R<3..2> 38D6>

RAM_CKE_R<2> 39B6<

RAM_CKE_R<1> 39B6<

RAM_CKE_R<3..0> 38B3>

RAM_CKE_R<1..0> 38D6>

RAM_CKE_R<0> 39B6<

RAM_CKE<3> 39B4> 41C4<

RAM_CKE<2> 39B4> 41C6<

RAM_CKE<1> 39B4> 40C4<

RAM_CKE<3..0> 39A6>

RAM_CKE<0> 39B4> 40C6<

RAM_CAS_L_R 38B3> 38D6> 39B8<

RAM_CAS_L 39A6> 39B7< 40B6< 41B6<

RAM_BA_R<2> 39B8<

RAM_BA_R<1> 39B8<

RAM_BA_R<2..0> 38C3> 38D6>

RAM_BA_R<0> 39C8<

RAM_BA<2> 39B7< 40C6< 41C6<

RAM_BA<1> 39B7< 40B4< 41B4<

RAM_BA<2..0> 39A6>

RAM_BA<0> 39C7< 40B6< 41B6<

RAM_ADDR_R<13> 39C8<

RAM_ADDR_R<12> 39C8<

RAM_ADDR_R<11> 39C8<

RAM_ADDR_R<10> 39C8<

RAM_ADDR_R<9> 39C8<

RAM_ADDR_R<8> 39C8<

RAM_ADDR_R<7> 39C8<

RAM_ADDR_R<6> 39C8<

RAM_ADDR_R<5> 39D8<

RAM_ADDR_R<4> 39D8<

RAM_ADDR_R<3> 39D8<

RAM_ADDR_R<2> 39D8<

RAM_ADDR_R<1> 39D8<

RAM_ADDR_R<13..0> 38D3> 38D6>

RAM_ADDR_R<0> 39D8<

RAM_ADDR<13> 39C7< 40B4< 41B4<

RAM_ADDR<12> 39C7< 40C6< 41C6<

RAM_ADDR<11> 39C7< 40C4< 41C4<

RAM_ADDR<10> 39C7< 40B6< 41B6<

RAM_ADDR<9> 39C7< 40C6< 41C6<

RAM_ADDR<8> 39C7< 40C6< 41C6<

RAM_ADDR<7> 39C7< 40C4< 41C4<

RAM_ADDR<6> 39C7< 40C4< 41C4<

RAM_ADDR<5> 39D7< 40B6< 41B6<

RAM_ADDR<4> 39D7< 40B4< 41B4<

RAM_ADDR<3> 39D7< 40B6< 41B6<

RAM_ADDR<2> 39D7< 40B4< 41B4<

RAM_ADDR<1> 39D7< 40B6< 41B6<

RAM_ADDR<13..0> 39A6>

RAM_ADDR<0> 39D7< 40B4< 41B4<

PWRON_REGS_PGOOD 26B7<

PPVPP_CBUS_SW 61B1< 61B2< 61D2<>

PPVOUT_VESTA1V2 18C4<

PPVOUT_CPU0_AVDD_R 37C4<>

PPVOUT_BATT_CHRG_R 13B2<

PPVOUT_1778_VCC 45C5<>

PPVIN_VESTA3V3 18D5<>

PPVIN_CPU0_AVDD 37C6<

PPVIN_ALL_ADAPT_OR_BATT 14A6<>

PPVIN_1778_VIN 45C5<

PPVCORE_RUN_GPU 7D7> 10A7<>

PPVCORE_RUN_CPU 7C7> 10C5<>

PPVCORE_PWRON_I2_REG 10A8<

PPVCORE_PWRON_I2 10A7<>

PPVCORE_GPU_REG 10A8<

PPVCORE_CPU_ADT7467 10C4<>

PPVCC_CBUS_SW 61B1< 61B2< 61D2<>

PPVBATT_ISNS_VINP 12A5<> 12D6>

PPVBATT_ISNS_VINN 12A4<> 12D6>

PPVBATT_BATT_RAW 12B5<>

PPVBATT_BATT_PBUSB_FUSE 13D1<>

PPVBATT_BATT_PBUSA_FUSE 13B1< 13D2<>

PPVBATT_BATT_CHRG_VSNS 10C7

PPVBATT_BATTPOS_CONN 12B7<>

PPVBATT_BATT 10C7

PPFW_PORT2_VP_F 70B3<

PPFW_PORT2_VP 70B3<>

PPFW_PORT1_VP 70D2<>

PPFW_CABLE_POWER 10D5

PPBUS_INVERTER 7B7> 56C2<>

PPBUS_FW_FET_D 18D6<>

PPBUS_FWPWRSW_F 18D7<>

PPBUS_DVI_PWRSW 10D6<>

PPAVDD_CPU0 10C2

PP24V_ALL_PBUSA 7D7> 10D7

PP24V_ADAPT_PMU_ILIM 14A7<>

PP24V_ADAPTER_SW 12D4<> 13C6< 13D8<>

PP24V_ADAPTER_ILIM_P 13D7<>

PP24V_ADAPTER 7D7> 10C7

PP12V8_ALL_PBUSB 7D7> 10D7<>

PP5V_TPAD_F 7D5> 30D6<>

PP5V_TPAD 10C2

PP5V_RUN_ODD 64C3<>

PP5V_RUN_HDD 10C2

PP5V_RUN_DDC_PULLUPS 57D2<>

PP5V_RUN_DDC_FUSE 57D4<

PP5V_RUN_DDC 57B4<> 57D3<>

PP5V_RUN 7C7> 10C2

PP5V_PWRON_REG 10C6<

PP5V_PWRON_AUDIO_PVDD 7A7> 74B3<>

PP5V_PWRON_AUDIO_AVDD 7A7> 74B3<>

PP5V_PWRON 7C7> 10C5<>

PP5V_MAX1715_VCC 16D5<

PP5V_LTC1625_EXTVCC_SW 14D6<>

PP5V_INV_SW_F 56C3<>

PP5V_INV_SW 7B7> 56C2<>

PP4V85_ALL_ESR 14A4<

PP4V85_ALL 10C7

PP4V6_ALL_RAW 14B3<>

PP3V3_VESTA_FAVDDH 69D2<

PP3V3_VESTA 10D5

PP3V3_SI_S_VCC 55C5<

PP3V3_SI_S_PVCC 55D5<

PP3V3_SI_S_AVCC 55C5<

PP3V3_SI_M_VCC 54C5<

PP3V3_SI_M_PVCC 54C4<

PP3V3_SI_M_AVCC 54C4<

PP3V3_RUN_PCI1510 61C8< 61D5<

PP3V3_RUN 10B2

PP3V3_PWRON_REG 10B6<

PP3V3_PWRON_NEC_AVDD 73D4<

PP3V3_PWRON_DS1775_R 7D5> 30D6<>

PP3V3_PWRON_AUDIO_AVDD 7A7> 74B3<>

PP3V3_PWRON 7C7> 10B5<>

PP3V3_LCD_SW 56C6<>

PP3V3_LCD_CONN 7B7> 56C5<>

PP3V3_GPU_VDDR3 47D3< 51B6<

PP3V3_GPU_SS 52B6<

PP3V3_GPU_PSNECK 52D2<>

PP3V3_GPU_OSC 52C6<

PP3V3_GPU 10B7<

PP3V3_FW_ESD_F 70A7<

PP3V3_FW_ESD 70A6<> 70B5<> 70D5<>

PP3V3_ALL_PMU_AVCC 10B7< 25D3<

PP3V3_ALL_HALL_EFFECT_R 7C5> 30D5<>

PP3V3_ALL_ESR 14A2<

PP3V3_ALL 7C7> 10C7

PP3V3_ADT7467 27D3<

PP3V3R5V_RUN_HDD_LOGIC 7B7> 64B7<>

PP2V8_GPU_LVDDR 10B7

PP2V5_VESTA_XTALVDD2 69C4<

PP2V5_VESTA_XTALVDD1 66D4<

PP2V5_VESTA_FAVDDM 69D2<

PP2V5_VESTA_BIASVDD2 69D4<

PP2V5_VESTA_BIASVDD1 66D4<

PP2V5_VESTA 10D5

PP2V5_RUN 10B2

PP2V5_PWRON_REG 10A6<

PP2V5_PWRON 7C7> 10A5<>

PP2V5_GPU_PSNECK 52D3<>

PP2V5_GPU_A2VDD 53B2<

PP2V5_GPU 10B7<

PP2V5_ENET_CTAP 67C6<>

PP2V5R2V8_GPU_LVDS_IO 47B2<

PP1VR1V3_GPU_VDDCI 46C2<

PP1V8_RUN 10A2

PP1V8_PWRON_REG 10A6<

PP1V8_PWRON 7C7> 10A5<>

PP1V8_GPU_VDD_MEM_CLK 47A4<

PP1V8_GPU_VDDDI 53B2<

PP1V8_GPU_TPVDD 53C5<

PP1V8_GPU_PVDD 26A6<> 51D2<>

PP1V8_GPU_PSNECK 52D3<>

PP1V8_GPU_PLL 51C3<

PP1V8_GPU_PANEL_IO 47B1< 53C4<

PP1V8_GPU_MEMPLL 51C3<

PP1V8_GPU_LVDS_PLL 47B2<

PP1V8_GPU_AVDD 53C2<

PP1V8_GPU_A2VDDQ 53A2<

PP1V8_GPU 10A7<

PP1V8R2V5_GPU_FB_VIO 47C6<

PP1V5_RUN 10A2

PP1V5_PWRON_REG 10A6<

PP1V5_PWRON_I2_PLLUSBAVDD 72C5<

PP1V5_PWRON_I2_PLL9AVDD 19A4<

PP1V5_PWRON_I2_PLL7AVDD 19A4<

PP1V5_PWRON_I2_PLL6AVDD 19B4<

PP1V5_PWRON_I2_PLL5AVDD 19B4<

PP1V5_PWRON_I2_PLL4AVDD 19B4<

PP1V5_PWRON_I2_PLL3AVDD 19C4<

PP1V5_PWRON_I2_PLL2AVDD 19C4<

PP1V5_PWRON_I2_PLL1AVDD 19C4<

PP1V5_PWRON_I2PLL 10D2

PP1V5_PWRON 10A5<>

PP1V5_GPU_VDD15_F 46B4<>

PP1V5_GPU_VDD15 46B2<

PP1V5_GPU_PSNECK 52C3<>

PP1V5_GPU_AGP 47C3<

PP1V5_GPU 10A7<

PP1V5R3V3_GPU_VDDR4 47C3< 53C8< 53D8<

PP1V5R1V8_I2_MAXBUS 32B6<

PP1V2_VESTA_PLLVDD2 69D4<

PP1V2_VESTA_PLLVDD1 66D4<

PP1V2_VESTA_FAVDDL 69C2<

PP1V2_VESTA_AVDDL 18B6<

PP1V2_VESTA 10D5

PMU_SYS_CLK_EN 11B4< 25C5<>

PMU_SB_NMI_L 22B6< 22D5< 25B2<>

PMU_RESET_L 24B2< 24C2<> 24D6<> 25B5<

PMU_POWER_UP_L 25B5<> 25C7< 26D8<

PMU_INT_L 22B6< 22D5< 25B2<>

PMU_CUSTOMER_RESET 24C7<>

PMU_CPU_HRESET_L 11B4< 25B5<>

PMU_CPU_CLK_EN 11B4< 25C5<>

PMU_CLK32K_XOUT_R 25B3<> 25D6>

PMU_CLK32K_XOUT 25B1< 25D6>

PMU_CLK32K_XIN 25B3<> 25D6>

PMU_CLK10M_XOUT_R 25B5<> 25D6>

PMU_CLK10M_XOUT 25A6< 25D6>

PMU_CLK10M_XIN 25B5< 25D6>

PMU_CHARGE_V 11B4< 13B8<>

PMU_BOOT_TXD 24C1<> 25C2<>

PMU_BOOT_SCLK 24C2<> 25C2<>

PMU_BOOT_RXD 24C1<> 25C2<>

PMU_BOOT_RP_L 24C1<> 25C2>

PMU_BOOT_CNVSS 24C2<> 25B5<

PMU_BOOT_BUSY 24C1<> 25C2<>

PMU_BATT1_DET_L 25A4>

PMU_BATT1_CHARGE 25A4>

PMU_BATT0_CHARGE 13A8<> 25C2<>

PCI_USB2_REQ_L 11C2

PCI_USB2_INT_L 11B2

PCI_USB2_IDSEL 62B5<

PCI_USB2_GNT_L 11C2

62B5<>

PCI_TRDY_L 6B6< 59C5< 59D6> 60B3<> 61A7<>

62B5<>

PCI_STOP_L 6B6< 59C5< 59D6> 60B5<> 61B7<>

PCI_SLOTE_REQ_L 11C3< 22A7< 22C5<

PCI_SLOTE_INT_L 11B3< 22B7< 22C5<

PCI_SLOTE_GNT_L 11C3< 22B7< 22C5<

PCI_SLOTD_REQ_L 11C3< 59C5< 59C6>

PCI_SLOTD_INT_L 11C3< 22D5< 59C2<

PCI_SLOTD_GNT_L 11C3< 59C3< 59C6>

PCI_SLOTA_REQ_L 11D3< 59C5< 59C6>

PCI_SLOTA_INT_L 11C3< 22D5< 59C2<

PCI_SLOTA_GNT_L 11D3< 59C3< 59C6>

PCI_SERR_L 61B7> 61B7<

25A7< 25C2<>

PCI_RESET_L 11A5< 11B2< 11C2< 11C2< 11C8<

PCI_PERR_L 61B7<> 61C7<

PCI_PAR 59C5< 59D6> 60B5<> 61B7<> 62B5<>

62B5<>

PCI_IRDY_L 6B6< 59C5< 59D6> 60C5<> 61B7<>

62B5<>

PCI_FRAME_L 6A6< 59C5< 59D6> 60C3<> 61B7<>

62B5<>

PCI_DEVSEL_L 59C5< 59D2< 59D6> 60B5<> 61A7<>

PCI_CLK_DELAY_ADJ 23B5<>

PCI_CLK33M_ZDB_R 11D3<

PCI_CLK33M_ZDB 11D2<

PCI_CLK33M_USB2_R 11C3<

PCI_CLK33M_USB2 11C2<

PCI_CLK33M_TBEN_SYNC_R 11D3<

PCI_CLK33M_TBEN_SYNC 11D2<

PCI_CLK33M_CBUS_R 11C3<

PCI_CLK33M_CBUS 11C2<

PCI_CLK33M_AIRPORT_R 11D3<

PCI_CLK33M_AIRPORT 11D2<

PCI_CBUS_RESET_L 61A7<

PCI_CBUS_REQ_L 6B6< 11C2

PCI_CBUS_INT_L 11C2

PCI_CBUS_IDSEL 61B7<

PCI_CBUS_GNT_L 6A6< 11C2

PCI_CBE_L<3> 59A3< 60C5<> 61B7<> 62B5<>

PCI_CBE_L<2> 59B3< 60B3<> 61B7<> 62B5<>

PCI_CBE_L<1> 59B3< 60B3<> 61B7<> 62B5<>

PCI_CBE_L<3..0> 59D6>

PCI_CBE_L<0> 59B3< 60B5<> 61B7<> 62B5<>

PCI_AIRPORT_REQ_L 6A6< 11D2

PCI_AIRPORT_INT_L 11C2

PCI_AIRPORT_IDSEL 60C5<>

PCI_AIRPORT_GNT_L 6B6< 11D2

PCI_AD<31> 59A3< 60C3<> 61B7<> 62B5<>

PCI_AD<30> 59A3< 60C5<> 61B7<> 62B5<>

PCI_AD<29> 59A3< 60C5<> 61B7<> 62B5<>

PCI_AD<28> 59A3< 60C3<> 61B7<> 62B5<>

PCI_AD<27> 59A3< 60C5<> 61B7<> 62B5<>

PCI_AD<26> 59B3< 60C5<> 61B7<> 62C5<>

PCI_AD<25> 59B3< 60C5<> 61B7<> 62C5<>

PCI_AD<31..24> 58C3<> 59D6>

PCI_AD<24> 59B3< 60C3<> 61B7<> 62C5<>

PCI_AD<23> 59B3< 60C3<> 61B7<> 62C5<>

PCI_AD<23..22> 59D6>

PCI_AD<22> 59B3< 60C5<> 61B7<> 62C5<>

62C5<>

PCI_AD<21> 11B2< 59B3< 59D6> 60C5<> 61B7<>

62C5<>

PCI_AD<20> 11C2< 59B3< 59D6> 60C3<> 61B7<>

PCI_AD<19> 59B3< 60C5<> 61B7<> 62C5<>

PCI_AD<19..18> 59D6>

PCI_AD<18> 59B3< 60B5<> 61B7<> 62C5<>

62C5<>

PCI_AD<17> 11C2< 59B3< 59D6> 60C3<> 61C7<>

PCI_AD<16> 59B3< 60B5<> 61C7<> 62C5<>

PCI_AD<15> 59B3< 60B3<> 61C7<> 62C5<>

PCI_AD<14> 59B3< 60B3<> 61C7<> 62C5<>

PCI_AD<13> 59B3< 60B3<> 61C7<> 62C5<>

PCI_AD<12> 59B3< 60B5<> 61C7<> 62C5<>

PCI_AD<11> 59B3< 60B3<> 61C7<> 62C5<>

PCI_AD<10> 59B3< 60B3<> 61C7<> 62C5<>

PCI_AD<9> 59B3< 60B5<> 61C7<> 62C5<>

PCI_AD<8> 59B3< 60B5<> 61C7<> 62C5<>

PCI_AD<7> 59B3< 60B5<> 61C7<> 62C5<>

PCI_AD<6> 59C3< 60B5<> 61C7<> 62C5<>

PCI_AD<5> 59C3< 60B5<> 61C7<> 62C5<>

PCI_AD<4> 59C3< 60B3<> 61C7<> 62C5<>

PCI_AD<3> 59C3< 60B5<> 61C7<> 62C5<>

PCI_AD<2> 59C3< 60B3<> 61C7<> 62C5<>

PCI_AD<1> 59C3< 60B5<> 61C7<> 62C5<>

PCI_AD<20..0> 58C5<>

PCI_AD<16..0> 59D6>

PCI_AD<0> 59C3< 60B5<> 61C7<> 62D5<>

PCI1510_VR_EN_L 61C7<

PANEL_PWR_EN 53B8<> 56B4<> 56C8<

OVER_18V_ADJ 13C3<>

NEC_VCCRST_L 62A5<

NEC_VBBRST_L 62A5<

NEC_SERR_L_PU 62B5<>

NEC_RREF_PD 73A3<>

NEC_PME_L 62A5<>

NEC_PERR_L_PU 62B5<>

NEC_NC2_PU 73A5<>

NEC_NC1_PU 73A5<>

NEC_LEGC_PD 62A5<

NEC_INTC_L 62B5<>

NEC_INTB_L 62B5<>

NEC_INTA_L 62B5<>

NEC_CRUN_L_PD 62A5<>

NEC_CLK30M_XT2_R 73A5<> 73D7>

NEC_CLK30M_XT2 73A5< 73D7>

NEC_CLK30M_XT1 73A5< 73D7>

NC_MAXBUS_I2_TBEN 6B8<

NC_MAXBUS_CPU1_QACK_L 11A4>

NC_FW_TPBIAS2 70B6>

NC_FW_TPA_P2 70B6>

NC_FW_TPA_N2 70B6>

NB_SUSPENDREQ_L 22A5< 25A7< 25C5<>

NB_SUSPENDACK_L 22A2< 25C5<>

MUTE_CONTROL 22B1<> 22C6<>

MODEM_RING2SYS_L 22B6< 22D5< 25C5<> 30A7<>

MODEM_RESET_L 22C5< 30B5<>

MMM_Z_AXIS 25A7> 29B3<> 29D6>

MMM_Y_AXIS 25A7> 29C3<> 29D6>

MMM_X_AXIS 25A7> 29C3<> 29D6>

MMM_SIRQ_L 22B6< 22C5< 25A7>

MMM_FFIRQ_L 22B6< 22C5< 25A7>

MMM_ACC_SELFTEST 25A7> 29C6<>

MMM_ACC_PWRDOWN 25A7> 29C6<>

MM3120_SW 28B4<>

MAXBUS_WT_L 9C3> 32B5< 32C6> 33C1>

MAXBUS_TT<4> 32B5< 33C1<>

MAXBUS_TT<3> 32B5< 33C1<>

MAXBUS_TT<2> 32B5< 33C1<>

MAXBUS_TT<1> 32B5< 33C1<>

MAXBUS_TT<4..0> 9C3> 32C6>

MAXBUS_TT<0> 32B5< 33C1<>

MAXBUS_TS_L 6B8< 32D5< 32D6> 33C3<>

MAXBUS_TSIZ<2> 32B5< 33C1>

MAXBUS_TSIZ<1> 32B5< 33C1>

MAXBUS_TSIZ<2..0> 9C3> 32C6>

MAXBUS_TSIZ<0> 32B5< 33C1>

MAXBUS_TEA_L 6A8< 32A3< 32D6> 33D4<

MAXBUS_TBST_L 9C3> 32B5< 32C6> 33C1>

MAXBUS_TBEN_SYNC 21B2<>

MAXBUS_TBEN 21B2< 33C1<

MAXBUS_TA_L 6B8< 32A3< 32D6> 33D4<

MAXBUS_SHD1_L 33A5< 33C1<>

MAXBUS_SHD0_L 33A5< 33C1<>

MAXBUS_GBL_L 9C3> 32B5< 32C6> 33C1<>

MAXBUS_EDTI 33A5< 33D4<

MAXBUS_DTI<2> 32A3< 33D4<

MAXBUS_DTI<1> 32A3< 33D4<

MAXBUS_DTI<2..0> 9C3> 32C6>

MAXBUS_DTI<0> 32A3< 33D4<

MAXBUS_DATA<63> 32A3< 32D6> 33B6<>

MAXBUS_DATA<62> 21B8< 32A3< 32D6> 33B6<>

MAXBUS_DATA<61> 32A3< 33B6<>

MAXBUS_DATA<60> 32A3< 33B6<>

MAXBUS_DATA<59> 32A3< 33B6<>

MAXBUS_DATA<58> 32A3< 33B6<>

MAXBUS_DATA<57> 32A3< 33B6<>

MAXBUS_DATA<56> 32A3< 33B6<>

MAXBUS_DATA<55..61> 32D6>

MAXBUS_DATA<55> 32A3< 33B6<>

MAXBUS_DATA<54> 21B8< 32A3< 32D6> 33B6<>

MAXBUS_DATA<53> 32A3< 33B6<>

MAXBUS_DATA<52> 32A3< 33B6<>

MAXBUS_DATA<51> 32B3< 33B6<>

MAXBUS_DATA<50> 32B3< 33B6<>

MAXBUS_DATA<49> 32B3< 33B6<>

MAXBUS_DATA<48> 32B3< 33B6<>

MAXBUS_DATA<47> 32B3< 33B6<>

MAXBUS_DATA<46> 32B3< 33C6<>

MAXBUS_DATA<45..53> 32D6>

MAXBUS_DATA<45> 32B3< 33C6<>

MAXBUS_DATA<44> 21B8< 32B3< 32D6> 33C6<>

MAXBUS_DATA<43> 21B8< 32B3< 32D6> 33C6<>

MAXBUS_DATA<42> 21B8< 32B3< 32D6> 33C6<>

MAXBUS_DATA<41> 21B8< 32B3< 32D6> 33C6<>

MAXBUS_DATA<40> 32B3< 33C6<>

MAXBUS_DATA<39> 32B3< 33C6<>

MAXBUS_DATA<38> 32B3< 33C6<>

MAXBUS_DATA<37> 32B3< 33C6<>

MAXBUS_DATA<36> 32B3< 33C6<>

MAXBUS_DATA<35> 32B3< 33C6<>

MAXBUS_DATA<34> 32B3< 33C6<>

MAXBUS_DATA<33> 32B3< 33C6<>

MAXBUS_DATA<32> 32B3< 33C6<>

MAXBUS_DATA<31> 32B3< 33C6<>

MAXBUS_DATA<30> 32B3< 33C6<>

MAXBUS_DATA<29> 32B3< 33C6<>

MAXBUS_DATA<28> 32B3< 33C6<>

MAXBUS_DATA<27> 32B3< 33C6<>

MAXBUS_DATA<26> 32B3< 33C6<>

MAXBUS_DATA<25> 32C3< 33C6<>

MAXBUS_DATA<24> 32C3< 33C6<>

MAXBUS_DATA<23> 32C3< 33C6<>

MAXBUS_DATA<22> 32C3< 33C6<>

MAXBUS_DATA<21> 32C3< 33C6<>

MAXBUS_DATA<20> 32C3< 33D6<>

MAXBUS_DATA<19> 32C3< 33D6<>

MAXBUS_DATA<18> 32C3< 33D6<>

MAXBUS_DATA<17> 32C3< 33D6<>

MAXBUS_DATA<16> 32C3< 33D6<>

MAXBUS_DATA<15> 32C3< 33D6<>

MAXBUS_DATA<14> 32C3< 33D6<>

MAXBUS_DATA<13> 32C3< 33D6<>

MAXBUS_DATA<12> 32C3< 33D6<>

MAXBUS_DATA<11> 32C3< 33D6<>

MAXBUS_DATA<10> 32C3< 33D6<>

MAXBUS_DATA<9> 32C3< 33D6<>

MAXBUS_DATA<8> 32C3< 33D6<>

MAXBUS_DATA<7> 32C3< 33D6<>

MAXBUS_DATA<6> 32C3< 33D6<>

MAXBUS_DATA<5> 32C3< 33D6<>

MAXBUS_DATA<4> 32C3< 33D6<>

MAXBUS_DATA<3> 32C3< 33D6<>

MAXBUS_DATA<2> 32C3< 33D6<>

MAXBUS_DATA<1> 32C3< 33D6<>

MAXBUS_DATA<63..0> 9C3>

MAXBUS_DATA<0..40> 32D6>

MAXBUS_DATA<0> 32C3< 33D6<>

MAXBUS_CPU1_QREQ_L 32A2< 32D5<

MAXBUS_CPU1_INT_L 6B8< 32D3<

MAXBUS_CPU1_HIT_L 6B8< 32C6> 32D5<

MAXBUS_CPU1_DRDY_L 6B8< 32C6> 32D5<

MAXBUS_CPU1_DBG_L 6A8< 32C6> 32D3<

MAXBUS_CPU1_BR_L 6B8< 32C6> 32D5<

MAXBUS_CPU1_BG_L 6B8< 32C6> 32D3<

MAXBUS_CPU0_QREQ_L 32B2< 32D5< 33C1>

MAXBUS_CPU0_QACK_L 32D3< 33B1<

MAXBUS_CPU0_INT_L 6B8< 32D3< 34D4<

MAXBUS_CPU0_HIT_L 6B8< 32C6> 32D5< 33D4>

MAXBUS_CPU0_DRDY_L_R 33D4<>

MAXBUS_CPU0_DRDY_L 6B8< 32C6> 32D5< 33D3<

MAXBUS_CPU0_DBG_L 6B8< 32C6> 32D3< 33D4<

MAXBUS_CPU0_BR_L 6B8< 32C6> 32D5< 33C3>

MAXBUS_CPU0_BG_L 6B8< 32C6> 32D3< 33C3<

MAXBUS_CLK_TBEN_SYNC 11D5<

MAXBUS_CLK_CPU1_R 11D6<

MAXBUS_CLK_CPU0_R 11D6< 32D3< 32D6>

MAXBUS_CLK_CPU0 11D5<

MAXBUS_CI_L 9C3> 32B5< 32C6> 33C1>

MAXBUS_ARTRY_L 6A8< 32C6> 32D5< 33C1<>

MAXBUS_ADDR<31> 32B5< 33B3<>

MAXBUS_ADDR<30> 32B5< 33B3<>

MAXBUS_ADDR<29> 32B5< 33B3<>

MAXBUS_ADDR<28> 32B5< 33B3<>

MAXBUS_ADDR<27> 32B5< 33B3<>

MAXBUS_ADDR<26> 32B5< 33B3<>

MAXBUS_ADDR<25> 32B5< 33B3<>

MAXBUS_ADDR<24> 32C5< 33B3<>

MAXBUS_ADDR<23> 32C5< 33B3<>

MAXBUS_ADDR<22> 32C5< 33B3<>

MAXBUS_ADDR<21> 32C5< 33B3<>

MAXBUS_ADDR<20> 32C5< 33B3<>

MAXBUS_ADDR<19> 32C5< 33B3<>

MAXBUS_ADDR<18> 32C5< 33B3<>

MAXBUS_ADDR<17> 32C5< 33B3<>

MAXBUS_ADDR<16> 32C5< 33C3<>

MAXBUS_ADDR<15> 32C5< 33C3<>

MAXBUS_ADDR<14> 32C5< 33C3<>

MAXBUS_ADDR<13> 32C5< 33C3<>

MAXBUS_ADDR<12> 32C5< 33C3<>

MAXBUS_ADDR<11> 32C5< 33C3<>

MAXBUS_ADDR<10> 32C5< 33C3<>

MAXBUS_ADDR<9> 32C5< 33C3<>

MAXBUS_ADDR<8> 32C5< 33C3<>

MAXBUS_ADDR<7> 32C5< 33C3<>

MAXBUS_ADDR<6> 32C5< 33C3<>

MAXBUS_ADDR<5> 32C5< 33C3<>

MAXBUS_ADDR<4> 32C5< 33C3<>

MAXBUS_ADDR<3> 32C5< 33C3<>

MAXBUS_ADDR<2> 32C5< 33C3<>

MAXBUS_ADDR<1> 32C5< 33C3<>

MAXBUS_ADDR<31..0> 9C3> 32D6>

MAXBUS_ADDR<0> 32C5< 33C3<>

MAXBUS_AACK_L 6B8< 32D3< 32D6> 33C1<

MAX8860_FAULT_L 52B3<>

MAX8860_CC 52B3<>

MAX4172_OUT 13D5<>

MAX1715_TON 16C5<

MAX1715_SKIP 16C4<

MAX1715_REF 16B5<>

MAX1715_ON 16D6<

MAX1715_GND 16B5<> 16C5<

MAX1715_EN_L_RC 16C7<>

LVDS_U2_P 7C7> 53B7> 53D1> 56B5<>

LVDS_U2_N 7C7> 53B7> 53D1> 56B5<>

LVDS_U1_P 7C7> 53B7> 53D1> 56B5<>

LVDS_U1_N 7C7> 53B7> 53D1> 56B5<>

LVDS_U0_P 7C7> 53B7> 53D1> 56B5<>

LVDS_U0_N 7C7> 53B7> 53D1> 56B5<>

LVDS_L2_P 7C7> 53A7> 53D1> 56B5<>

LVDS_L2_N 7C7> 53A7> 53D1> 56B5<>

LVDS_L1_P 7C7> 53A7> 53D1> 56C5<>

LVDS_L1_N 7C7> 53A7> 53D1> 56C5<>

LVDS_L0_P 7C7> 53A7> 53D1> 56C5<>

LVDS_L0_N 7C7> 53A7> 53D1> 56C5<>

LVDS_DDC_DATA 7B7> 51B3<> 56C7<>

LVDS_DDC_CLK 7B7> 51B3<> 56C7<>

LTC3412_VFB_DIV 17C5<

LTC3412_VFB 17C5<>

LTC3412_SYNC 17C5<>

LTC3412_SW 17C4<>

LTC3412_RUNSS 2B5> 17C5<>

LTC3412_RT 17C5<

LTC3412_ITH_RC 17C6<

LTC3412_ITH 17C5<>

LTC3412_GND 17B5<>

LTC1625_ITH 13D3<>

LCD_PWREN_L 56C7<>

LCD_DIGON_L 56C8<

KBDLED_RETURN 7C5> 28A4<> 30C5<>

KBDLED_ANODE 7C5> 28A4< 30C5<>

JTAG_VESTA_TRST_L 9A8<

JTAG_I2_TDI 9C7<

JTAG_CPU_TRST_L 9D7<

JTAG_CPU_TMS 9D7<

JTAG_CPU_TDI 9D7<

JTAG_CPU_TCK 9D7<

JTAG_ASIC_TRST_L 9B8<

JTAG_ASIC_TMS 9B8<

JTAG_ASIC_TCK 9B8<

INV_ON_PWM 53B8<> 56B4<

IAC_RC_COMP 13D4<

IAC_FB 13D4<

I2_USB2_VREF 72B5<

I2_UATA_VREF 63B5<

I2_TST_TEI 22B5<

I2_TST_PLLEN 22B5<

I2_SD_REF 38A5<

I2_PCI_FBCLK_OUT_R 59A4< 59D6>

I2_PCI_FBCLK_OUT 21C5< 59A2< 59D6>

I2_PCI_FBCLK_MATCHED 21C3< 21D6>

I2_PCI_FBCLK_IN 21B4< 21D6>

I2_MEM_VREF 38A5<

I2_MAXBUS_FBCLK_OUT_R 32A4< 32D6>

I2_MAXBUS_FBCLK_OUT 21D6< 32A2< 32D6>

I2_MAXBUS_FBCLK_MATCHED 21D4< 21D6>

I2_MAXBUS_FBCLK_IN 21D3< 21D6>

I2_GPIO_EXT_02 11A5< 22A7< 22C5<

I2_GPIO_11 22A6< 22C5<

I2_FW_PVT 68C5<

I2_EXT_14 22C5<

I2_EXT_13 22C5<

I2_EXT_08 22D5<

I2_ENET_PVT 65B5<

I2_ENET_MDIO 65C4<> 65D6>

I2_CLK30M_USB2_XOUT_R 72B6< 72D6>

I2_CLK30M_USB2_XOUT 72B7< 72D6>

I2_CLK30M_USB2_XIN 72B6< 72D6>

I2_CLK18M_XOUT_R 22A5< 22D6>

I2_CLK18M_XOUT 22A6< 22D6>

I2_CLK18M_XIN 22A5< 22D6>

I2_AUDIO_SPKR_MUTE_L 22B2<> 22C5<

I2_AUDIO_LO_MUTE_L 22C5< 22C7<>

I2_AGP_PVTREF 43A5<

I2_AGP_FBCLK_OUT_R 43A3< 43D6>

I2_AGP_FBCLK_OUT 21C5< 43A2< 43D6>

I2_AGP_FBCLK_MATCHED 21C3< 21D6>

I2_AGP_FBCLK_IN 21C4< 21D6>

I2_ACS_REF 32A5<

I2VCORE_VFB 20C5<>

I2VCORE_SW 20C4<>

I2VCORE_RUNSS 20C5<>

I2VCORE_RT 20C5<

I2VCORE_MODE_VDIV 20C5<

I2VCORE_MODE 20C5<>

I2VCORE_ITH_RC 20C6<

I2VCORE_ITH 20C5<>

I2S1_SYNC_R 6D8< 22B2< 22D6>

I2S1_SYNC 6D6> 30B5<>

I2S1_SB_TO_DEV_DTO_R 6D8< 22B2< 22D6>

I2S1_SB_TO_DEV_DTO 6D6> 30A5<>

I2S1_MCLK_R 6D8< 22B2< 22D6>

I2S1_MCLK 6D6> 30B7<>

I2S1_DEV_TO_SB_DTI 22B5< 22D6> 30B5<>

I2S1_BITCLK_R 6D8< 22B2< 22D6>

I2S1_BITCLK 6D6> 30B7<>

I2S0_SYNC_R 6D8< 22B2< 22D6>

I2S0_SYNC 6D6> 7A7> 74C6<>

I2S0_SB_TO_DEV_DTO_R 6D8< 22B2< 22D6>

I2S0_SB_TO_DEV_DTO 6D6> 7A7> 74C4<>

I2S0_MCLK_R 6D8< 22B2< 22D6>

I2S0_MCLK 6D6> 7A7> 74C4<>

I2S0_DEV_TO_SB_DTI 7A7> 22B5< 22D6> 74C4<>

I2S0_BITCLK_R 6D8< 22B2< 22D6>

I2S0_BITCLK 6D6> 7A7> 74C6<>

I2PLLVDD_BYP 20A4<>

I2PLLVDD_ADJ 20A4<

113

113 115

C

051-6929

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

114

*** Part Cross-Reference for the entire design ***

C1200 CAP 12 C1210 CAP 12 C1220 CAP 12 C1250 CAP 12 C1252 CAP 12 C1301 CAP 13 C1302 CAP 13 C1303 CAP 13 C1305 CAP 13 C1306 CAP 13 C1307 CAP 13 C1308 CAP 13 C1309 CAP 13 C1310 CAP 13 C1311 CAP_P 13 C1312 CAP 13 C1313 CAP 13 C1314 CAP 13 C1315 CAP 13 C1316 CAP 13 C1317 CAP 13 C1319 CAP 13 C1320 CAP 13 C1321 CAP 13 C1322 CAP 13 C1323 CAP 13 C1324 CAP 13 C1325 CAP 13 C1326 CAP 13 C1327 CAP 13 C1350 CAP 13 C1352 CAP 13 C1361 CAP 13 C1370 CAP 13 C1371 CAP 13 C1380 CAP 13 C1384 CAP 13 C1386 CAP 13 C1392 CAP 13 C1400 CAP 14 C1401 CAP 14 C1402 CAP 14 C1403 CAP 14 C1404 CAP 14 C1405 CAP 14 C1406 CAP 14 C1407 CAP 14 C1408 CAP 14 C1410 CAP 14 C1411 CAP 14 C1412 CAP 14 C1420 CAP 14 C1421 CAP 14 C1425 CAP 14 C1426 CAP 14 C1427 CAP 14 C1450 CAP 14 C1451 CAP 14 C1452 CAP 14 C1453 CAP 14 C1460 CAP 14 C1461 CAP 14 C1501 CAP 15 C1502 CAP 15 C1503 CAP_P 15 C1504 CAP 15 C1510 CAP 15 C1511 CAP 15 C1512 CAP 15 C1513 CAP 15 C1514 CAP 15 C1515 CAP 15 C1520 CAP 15 C1521 CAP 15 C1522 CAP 15 C1523 CAP 15 C1530 CAP 15 C1531 CAP 15 C1532 CAP 15 C1533 CAP 15 C1536 CAP 15 C1551 CAP 15 C1552 CAP 15 C1553 CAP_P 15 C1554 CAP 15 C1560 CAP 15 C1561 CAP 15 C1562 CAP 15 C1563 CAP 15 C1564 CAP 15 C1565 CAP 15 C1570 CAP 15 C1571 CAP 15 C1572 CAP 15 C1573 CAP 15 C1580 CAP 15 C1581 CAP 15 C1582 CAP_P 15 C1585 CAP 15 C1586 CAP 15 C1587 CAP_P 15 C1590 CAP 15 C1591 CAP_P 15 C1592 CAP 15 C1601 CAP 16 C1602 CAP 16 C1603 CAP 16 C1604 CAP_P 16 C1605 CAP_P 16 C1620 CAP 16 C1621 CAP 16 C1630 CAP 16 C1631 CAP 16 C1632 CAP 16 C1640 CAP 16 C1651 CAP 16 C1652 CAP 16 C1653 CAP_P 16 C1655 CAP 16 C1670 CAP 16 C1671 CAP 16 C1680 CAP 16 C1681 CAP 16 C1682 CAP 16 C1685 CAP 16 C1686 CAP 16 C1700 CAP 17 C1701 CAP 17 C1710 CAP 17 C1711 CAP 17 C1720 CAP 17 C1721 CAP 17 C1722 CAP 17 C1730 CAP 17 C1780 CAP 17 C1781 CAP 17 C1900 CAP 18 C1901 CAP 18 C1902 CAP 18 C1903 CAP 18 C1908 CAP 18 C1910 CAP 18 C1911 CAP 18 C1912 CAP 18 C1913 CAP 18 C1920 CAP 18 C1921 CAP 18 C1922 CAP 18 C1923 CAP 18 C1924 CAP 18 C1925 CAP 18 C1930 CAP 18 C1931 CAP 18 C1940 CAP 18 C1941 CAP 18 C1942 CAP 18 C1943 CAP 18 C1950 CAP 18 C1965 CAP 18 C1970 CAP 18 C1971 CAP_P 18 C1980 CAP 18 C1981 CAP 18 C1982 CAP 18 C1990 CAP 18 C1991 CAP 18

C1992 CAP 18 C1993 CAP 18 C1994 CAP 18 C1995 CAP 18 C2101 CAP 19 C2102 CAP 19 C2103 CAP 19 C2104 CAP 19 C2105 CAP 19 C2106 CAP 19 C2107 CAP 19 C2109 CAP 19 C2120 CAP 19 C2121 CAP 19 C2122 CAP 19 C2123 CAP 19 C2124 CAP 19 C2125 CAP 19 C2126 CAP 19 C2127 CAP 19 C2128 CAP 19 C2129 CAP 19 C2130 CAP 19 C2131 CAP 19 C2132 CAP 19 C2133 CAP 19 C2134 CAP 19 C2135 CAP 19 C2136 CAP 19 C2137 CAP 19 C2138 CAP 19 C2139 CAP 19 C2140 CAP 19 C2141 CAP 19 C2142 CAP 19 C2143 CAP 19 C2144 CAP 19 C2146 CAP 19 C2147 CAP 19 C2148 CAP 19 C2149 CAP 19 C2150 CAP 19 C2151 CAP 19 C2152 CAP 19 C2153 CAP 19 C2154 CAP 19 C2155 CAP 19 C2156 CAP 19 C2157 CAP 19 C2158 CAP 19 C2159 CAP 19 C2160 CAP 19 C2161 CAP 19 C2162 CAP 19 C2163 CAP 19 C2164 CAP 19 C2165 CAP 19 C2166 CAP 19 C2167 CAP 19 C2168 CAP 19 C2169 CAP 19 C2170 CAP 19 C2171 CAP 19 C2172 CAP 19 C2173 CAP 19 C2174 CAP 19 C2175 CAP 19 C2176 CAP 19 C2177 CAP 19 C2178 CAP 19 C2179 CAP 19 C2180 CAP 19 C2181 CAP 19 C2182 CAP 19 C2183 CAP 19 C2184 CAP 19 C2185 CAP 19 C2186 CAP 19 C2187 CAP 19 C2188 CAP 19 C2189 CAP 19 C2190 CAP 19 C2191 CAP 19 C2192 CAP 19 C2193 CAP 19 C2194 CAP 19 C2195 CAP 19 C2196 CAP 19 C2197 CAP 19 C2199 CAP 19 C2200 CAP 20 C2201 CAP 20 C2205 CAP 20 C2206 CAP 20 C2207 CAP 20 C2210 CAP 20 C2215 CAP 20 C2216 CAP 20 C2250 CAP 20 C2254 CAP 20 C2259 CAP 20 C2390 CAP 21 C2391 CAP 21 C2392 CAP 21 C2410 CAP 22 C2411 CAP 22 C2500 CAP 23 C2501 CAP 23 C2502 CAP 23 C2700 CAP 25 C2701 CAP 25 C2702 CAP 25 C2705 CAP 25 C2710 CAP 25 C2720 CAP 25 C2740 CAP 25 C2741 CAP 25 C2750 CAP 25 C2751 CAP 25 C3000 CAP 27 C3001 CAP 27 C3002 CAP 27 C3003 CAP 27 C3100 CAP 28 C3101 CAP 28 C3104 CAP 28 C3105 CAP 28 C3130 CAP 28 C3131 CAP 28 C3204 CAP 29 C3205 CAP 29 C3206 CAP 29 C3220 CAP 29 C3300 CAP 30 C3320 CAP 30 C3350 CAP 30 C3352 CAP 30 C3353 CAP 30 C3354 CAP 30 C3355 CAP 30 C3400 CAP 31 C3430 CAP 31 C3450 CAP_P 31 C3460 CAP_P 31 C3550 CAP 32 C3551 CAP 32 C3552 CAP 32 C3553 CAP 32 C3554 CAP 32 C3555 CAP 32 C3556 CAP 32 C3557 CAP 32 C3558 CAP 32 C3559 CAP 32 C3560 CAP 32 C3561 CAP 32 C3562 CAP 32 C3563 CAP 32 C3564 CAP 32 C3565 CAP 32 C3566 CAP 32 C3567 CAP 32 C3568 CAP 32 C3569 CAP 32 C3570 CAP 32 C3571 CAP 32 C3572 CAP 32 C3573 CAP 32

C3574 CAP 32 C3575 CAP 32 C3576 CAP 32 C3577 CAP 32 C3578 CAP 32 C3579 CAP 32 C3580 CAP 32 C3581 CAP 32 C3582 CAP 32 C3583 CAP 32 C3584 CAP 32 C3585 CAP 32 C3586 CAP 32 C3587 CAP 32 C3588 CAP 32 C3589 CAP 32 C3590 CAP 32 C3599 CAP 32 C3600 CAP 33 C3670 CAP 33 C3671 CAP 33 C3672 CAP 33 C3673 CAP 33 C3674 CAP 33 C3675 CAP 33 C3676 CAP 33 C3677 CAP 33 C3678 CAP 33 C3679 CAP 33 C3680 CAP 33 C3681 CAP 33 C3682 CAP 33 C3683 CAP 33 C3684 CAP 33 C3685 CAP 33 C3686 CAP 33 C3687 CAP 33 C3688 CAP 33 C3689 CAP 33 C3690 CAP 33 C3691 CAP 33 C3692 CAP 33 C3693 CAP 33 C3694 CAP 33 C3695 CAP 33 C3698 CAP 33 C3699 CAP 33 C3800 CAP 35 C3801 CAP 35 C3802 CAP 35 C3803 CAP 35 C3804 CAP 35 C3805 CAP 35 C3806 CAP 35 C3807 CAP 35 C3808 CAP 35 C3809 CAP 35 C3810 CAP 35 C3811 CAP 35 C3812 CAP 35 C3813 CAP 35 C3814 CAP 35 C3815 CAP 35 C3816 CAP 35 C3817 CAP 35 C3818 CAP 35 C3819 CAP 35 C3820 CAP 35 C3821 CAP 35 C3822 CAP 35 C3823 CAP 35 C3830 CAP 35 C3831 CAP 35 C3832 CAP 35 C3833 CAP 35 C3834 CAP 35 C3835 CAP 35 C3836 CAP 35 C3837 CAP 35 C3838 CAP 35 C3839 CAP 35 C3840 CAP 35 C3841 CAP 35 C3842 CAP 35 C3843 CAP 35 C3844 CAP 35 C3845 CAP 35 C3846 CAP 35 C3847 CAP 35 C3848 CAP 35 C3849 CAP 35 C3850 CAP 35 C3851 CAP 35 C3852 CAP 35 C3853 CAP 35 C3854 CAP 35 C3855 CAP 35 C3856 CAP 35 C3857 CAP 35 C3858 CAP 35 C3859 CAP 35 C3860 CAP 35 C3861 CAP 35 C3900 CAP 36 C3901 CAP 36 C3902 CAP 36 C3903 CAP 36 C3910 CAP_P 36 C3911 CAP_P 36 C3912 CAP_P 36 C3913 CAP_P 36 C3914 CAP_P 36 C3915 CAP_P 36 C3916 CAP_P 36 C3917 CAP_P 36 C3918 CAP_P 36 C3937 CAP 36 C3938 CAP 36 C3939 CAP 36 C3940 CAP 36 C3941 CAP 36 C3942 CAP 36 C3943 CAP 36 C3944 CAP 36 C3945 CAP 36 C3946 CAP 36 C3947 CAP 36 C3948 CAP 36 C3949 CAP 36 C3950 CAP 36 C3951 CAP 36 C3960 CAP 36 C3962 CAP 36 C3963 CAP 36 C3964 CAP 36 C3990 CAP 36 C4600 CAP 37 C4610 CAP 37 C4620 CAP 37 C4625 CAP 37 C4626 CAP 37 C4627 CAP 37 C4705 CAP 38 C4706 CAP 38 C4749 CAP 38 C4750 CAP 38 C4751 CAP 38 C4752 CAP 38 C4753 CAP 38 C4754 CAP 38 C4755 CAP 38 C4756 CAP 38 C4757 CAP 38 C4758 CAP 38 C4759 CAP 38 C4760 CAP 38 C4761 CAP 38 C4762 CAP 38 C4763 CAP 38 C4764 CAP 38 C4765 CAP 38 C4766 CAP 38 C4767 CAP 38 C4768 CAP 38 C4769 CAP 38 C4770 CAP 38 C4771 CAP 38 C4772 CAP 38

C4773 CAP 38 C4774 CAP 38 C4775 CAP 38 C4776 CAP 38 C4777 CAP 38 C4778 CAP 38 C4779 CAP 38 C4780 CAP 38 C4781 CAP 38 C4782 CAP 38 C4783 CAP 38 C4784 CAP 38 C4785 CAP 38 C4786 CAP 38 C4787 CAP 38 C4788 CAP 38 C4789 CAP 38 C4790 CAP 38 C4791 CAP 38 C4792 CAP 38 C4793 CAP 38 C4794 CAP 38 C4795 CAP 38 C4796 CAP 38 C4797 CAP 38 C5001 CAP 40 C5008 CAP 40 C5009 CAP 40 C5010 CAP 40 C5011 CAP 40 C5012 CAP 40 C5013 CAP 40 C5014 CAP 40 C5015 CAP 40 C5016 CAP 40 C5017 CAP 40 C5018 CAP 40 C5019 CAP 40 C5020 CAP 40 C5021 CAP 40 C5022 CAP 40 C5023 CAP 40 C5201 CAP 41 C5208 CAP 41 C5209 CAP 41 C5210 CAP 41 C5211 CAP 41 C5212 CAP 41 C5213 CAP 41 C5214 CAP 41 C5215 CAP 41 C5216 CAP 41 C5217 CAP 41 C5218 CAP 41 C5219 CAP 41 C5220 CAP 41 C5221 CAP 41 C5222 CAP 41 C5223 CAP 41 C5649 CAP 43 C5650 CAP 43 C5651 CAP 43 C5652 CAP 43 C5653 CAP 43 C5654 CAP 43 C5655 CAP 43 C5656 CAP 43 C5657 CAP 43 C5658 CAP 43 C5659 CAP 43 C5660 CAP 43 C5661 CAP 43 C5662 CAP 43 C5663 CAP 43 C5664 CAP 43 C5665 CAP 43 C5666 CAP 43 C5667 CAP 43 C5668 CAP 43 C5669 CAP 43 C5670 CAP 43 C5671 CAP 43 C5672 CAP 43 C5673 CAP 43 C5674 CAP 43 C5731 CAP 44 C5732 CAP 44 C5801 CAP 45 C5802 CAP_P 45 C5803 CAP_P 45 C5804 CAP 45 C5805 CAP 45 C5810 CAP 45 C5811 CAP 45 C5820 CAP 45 C5822 CAP 45 C5823 CAP 45 C5824 CAP 45 C5825 CAP 45 C5830 CAP 45 C5831 CAP 45 C5882 CAP 45 C5885 CAP 45 C5900 CAP 46 C5901 CAP 46 C5902 CAP 46 C5903 CAP 46 C5904 CAP 46 C5905 CAP 46 C5906 CAP 46 C5907 CAP 46 C5908 CAP 46 C5909 CAP 46 C5910 CAP 46 C5911 CAP 46 C5912 CAP 46 C5913 CAP 46 C5914 CAP 46 C5915 CAP 46 C5916 CAP 46 C5917 CAP 46 C5918 CAP 46 C5919 CAP 46 C5920 CAP 46 C5921 CAP 46 C5922 CAP 46 C5923 CAP 46 C5924 CAP 46 C5950 CAP 46 C5951 CAP 46 C5952 CAP 46 C5953 CAP 46 C5954 CAP 46 C5955 CAP 46 C5956 CAP 46 C5957 CAP 46 C5958 CAP 46 C5959 CAP 46 C5990 CAP 46 C5991 CAP 46 C5992 CAP 46 C5993 CAP 46 C5994 CAP 46 C6000 CAP 47 C6001 CAP 47 C6002 CAP 47 C6003 CAP 47 C6004 CAP 47 C6005 CAP 47 C6006 CAP 47 C6010 CAP 47 C6011 CAP 47 C6012 CAP 47 C6013 CAP 47 C6014 CAP 47 C6015 CAP 47 C6020 CAP 47 C6021 CAP 47 C6022 CAP 47 C6023 CAP 47 C6024 CAP 47 C6025 CAP 47 C6026 CAP 47 C6027 CAP 47 C6028 CAP 47 C6029 CAP 47 C6030 CAP 47 C6031 CAP 47

C6032 CAP 47 C6033 CAP 47 C6040 CAP 47 C6041 CAP 47 C6042 CAP 47 C6043 CAP 47 C6044 CAP 47 C6045 CAP 47 C6046 CAP 47 C6047 CAP 47 C6048 CAP 47 C6049 CAP 47 C6050 CAP 47 C6051 CAP 47 C6052 CAP 47 C6053 CAP 47 C6054 CAP 47 C6055 CAP 47 C6056 CAP 47 C6057 CAP 47 C6058 CAP 47 C6059 CAP 47 C6060 CAP 47 C6061 CAP 47 C6062 CAP 47 C6063 CAP 47 C6064 CAP 47 C6065 CAP 47 C6066 CAP 47 C6067 CAP 47 C6068 CAP 47 C6069 CAP 47 C6070 CAP 47 C6071 CAP 47 C6072 CAP 47 C6073 CAP 47 C6074 CAP 47 C6075 CAP 47 C6076 CAP 47 C6077 CAP 47 C6078 CAP 47 C6079 CAP 47 C6080 CAP 47 C6081 CAP 47 C6082 CAP 47 C6083 CAP 47 C6084 CAP 47 C6085 CAP 47 C6086 CAP 47 C6087 CAP 47 C6088 CAP 47 C6089 CAP 47 C6090 CAP 47 C6091 CAP 47 C6092 CAP 47 C6093 CAP 47 C6094 CAP 47 C6095 CAP 47 C6096 CAP 47 C6097 CAP 47 C6190 CAP 48 C6191 CAP 48 C6192 CAP 48 C6193 CAP 48 C6200 CAP 49 C6201 CAP 49 C6202 CAP 49 C6203 CAP 49 C6204 CAP 49 C6210 CAP 49 C6211 CAP 49 C6212 CAP 49 C6213 CAP 49 C6214 CAP 49 C6215 CAP 49 C6216 CAP 49 C6217 CAP 49 C6218 CAP 49 C6219 CAP 49 C6220 CAP 49 C6221 CAP 49 C6241 CAP 49 C6245 CAP 49 C6250 CAP 49 C6251 CAP 49 C6252 CAP 49 C6253 CAP 49 C6254 CAP 49 C6260 CAP 49 C6261 CAP 49 C6262 CAP 49 C6263 CAP 49 C6264 CAP 49 C6265 CAP 49 C6266 CAP 49 C6267 CAP 49 C6268 CAP 49 C6269 CAP 49 C6270 CAP 49 C6271 CAP 49 C6291 CAP 49 C6295 CAP 49 C6300 CAP 50 C6301 CAP 50 C6302 CAP 50 C6303 CAP 50 C6304 CAP 50 C6310 CAP 50 C6311 CAP 50 C6312 CAP 50 C6313 CAP 50 C6314 CAP 50 C6315 CAP 50 C6316 CAP 50 C6317 CAP 50 C6318 CAP 50 C6319 CAP 50 C6320 CAP 50 C6321 CAP 50 C6341 CAP 50 C6345 CAP 50 C6350 CAP 50 C6351 CAP 50 C6352 CAP 50 C6353 CAP 50 C6354 CAP 50 C6360 CAP 50 C6361 CAP 50 C6362 CAP 50 C6363 CAP 50 C6364 CAP 50 C6365 CAP 50 C6366 CAP 50 C6368 CAP 50 C6369 CAP 50 C6370 CAP 50 C6371 CAP 50 C6391 CAP 50 C6395 CAP 50 C6400 CAP 51 C6401 CAP 51 C6402 CAP 51 C6403 CAP 51 C6404 CAP 51 C6405 CAP 51 C6410 CAP 51 C6411 CAP 51 C6421 CAP 51 C6500 CAP 52 C6501 CAP 52 C6510 CAP 52 C6511 CAP 52 C6530 CAP 52 C6531 CAP 52 C6532 CAP 52 C6600 CAP 53 C6601 CAP 53 C6605 CAP 53 C6606 CAP 53 C6607 CAP 53 C6610 CAP 53 C6611 CAP 53 C6615 CAP 53 C6616 CAP 53 C6617 CAP 53 C6620 CAP 53 C6621 CAP 53 C6622 CAP 53

C6625 CAP 53 C6626 CAP 53 C6720 CAP 54 C6721 CAP 54 C6722 CAP 54 C6723 CAP 54 C6724 CAP 54 C6725 CAP 54 C6726 CAP 54 C6727 CAP 54 C6728 CAP 54 C6729 CAP 54 C6740 CAP 54 C6760 CAP 54 C6762 CAP 54 C6764 CAP 54 C6766 CAP 54 C6800 CAP 55 C6802 CAP 55 C6804 CAP 55 C6830 CAP 55 C6831 CAP 55 C6832 CAP 55 C6833 CAP 55 C6834 CAP 55 C6835 CAP 55 C6836 CAP 55 C6837 CAP 55 C6838 CAP 55 C6839 CAP 55 C6900 CAP 56 C6901 CAP 56 C6910 CAP 56 C6911 CAP 56 C6920 CAP 56 C6921 CAP 56 C6950 CAP 56 C6951 CAP 56 C6952 CAP 56 C6953 CAP 56 C6954 CAP 56 C6955 CAP 56 C6999 CAP 56 C7010 CAP 57 C7011 CAP 57 C7013 CAP 57 C7014 CAP 57 C7040 CAP 57 C7041 CAP 57 C7042 CAP 57 C7050 CAP 57 C7051 CAP 57 C7060 CAP 57 C7061 CAP 57 C7062 CAP 57 C7063 CAP 57 C7064 CAP 57 C7065 CAP 57 C7066 CAP 57 C7067 CAP 57 C7070 CAP 57 C7079 CAP 57 C7100 CAP 58 C7101 CAP 58 C7102 CAP 58 C7400 CAP 61 C7401 CAP 61 C7402 CAP 61 C7403 CAP 61 C7404 CAP 61 C7405 CAP 61 C7406 CAP 61 C7407 CAP 61 C7408 CAP 61 C7410 CAP 61 C7411 CAP 61 C7450 CAP 61 C7451 CAP 61 C7490 CAP 61 C7491 CAP 61 C7500 CAP 62 C8166 CAP 63 C8450 CAP 65 C8451 CAP 65 C8452 CAP 65 C8453 CAP 65 C8454 CAP 65 C8455 CAP 65 C8456 CAP 65 C8459 CAP 65 C8500 CAP 66 C8501 CAP 66 C8510 CAP 66 C8520 CAP 66 C8521 CAP 66 C8530 CAP 66 C8531 CAP 66 C8580 CAP 66 C8590 CAP 66 C8592 CAP 66 C8594 CAP 66 C8596 CAP 66 C8600 CAP 67 C8601 CAP 67 C8602 CAP 67 C8603 CAP 67 C8620 CAP 67 C8900 CAP 69 C8901 CAP 69 C8903 CAP 69 C8904 CAP 69 C8905 CAP 69 C8906 CAP 69 C8907 CAP 69 C8908 CAP 69 C8909 CAP 69 C8911 CAP 69 C8913 CAP 69 C8914 CAP 69 C8915 CAP 69 C8917 CAP 69 C8918 CAP 69 C8919 CAP 69 C8920 CAP 69 C8921 CAP 69 C9010 CAP 70 C9011 CAP 70 C9012 CAP 70 C9013 CAP 70 C9014 CAP 70 C9015 CAP 70 C9016 CAP 70 C9017 CAP 70 C9018 CAP 70 C9019 CAP 70 C9020 CAP 70 C9021 CAP 70 C9022 CAP 70 C9023 CAP 70 C9024 CAP 70 C9025 CAP 70 C9026 CAP 70 C9050 CAP 70 C9054 CAP 70 C9060 CAP 70 C9064 CAP 70 C9090 CAP 70 C9091 CAP 70 C9092 CAP 70 C9220 CAP 72 C9221 CAP 72 C9250 CAP 72 C9251 CAP 72 C9320 CAP 73 C9321 CAP 73 C9322 CAP 73 C9323 CAP 73 C9324 CAP 73 C9325 CAP 73 C9326 CAP 73 C9327 CAP 73 C9328 CAP 73 C9329 CAP 73 C9330 CAP 73 C9335 CAP 73 C9336 CAP 73 C9337 CAP 73 C9345 CAP 73

C9346 CAP 73 CA000 CAP_P 74 CA010 CAP 74 CA011 CAP 74 CA033 CAP 74 CA050 CAP 74 CA051 CAP 74 D1300 DIODE_SCHOT 13 D1303 DIODE 13 D1319 DIODE 13 D1400 DIODE_SCHOT 14 D1410 DIODE_SCHOT 14 D1420 DIODE 14 D1450 DIODE_SCHOT 14 D1451 DIODE 14 D1452 DIODE_SCHOT 14 D1460 DIODE_SCHOT 14 D1461 DIODE_SCHOT 14 D1501 DIODE_SCHOT 15 D1511 DIODE_SCHOT 15 D1533 DIODE 15 D1551 DIODE_SCHOT 15 D1561 DIODE_SCHOT 15 D1601 DIODE_SCHOT 16 D1651 DIODE_SCHOT 16 D1965 DIODE_SCHOT 18 D1970 DIO_MBRM140T3_SM 18 D1975 DIODE_SCHOT_3P2 18 D2710 DIODE 25 D3354 ZENER_MMBZ15VDLT1 30 D3900 DIODE_3P_C 36 D3901 DIODE_SCHOT 36 D4610 DIODE_SCHOT 37 D5800 DIODE_SCHOT 45 D5823 DIODE_SCHOT 45 D7010 DIODE_SCHOT 57 D9090 ZENER 70 DP1390 DPAK3P 13 DP1620 DPAK3P 16 DP1960 DPAK3P 18 DP2680 DPAK3P 24 DP6590 DPAK3P 52 DP9010 DIODE_DUAL_6P 70 DP9011 DIODE_DUAL_6P 70 DP9020 DIODE_DUAL_6P 70 DP9021 DIODE_DUAL_6P 70 F1390 FUSE 13 F1395 FUSE 13 F1965 FUSE 18 F7010 FUSE 57 F9020 FUSE 70 FL7040 FILTER_LC 57 FL7041 FILTER_LC 57 FL7042 FILTER_LC 57 FL9010 FILTER_4P 70 FL9011 FILTER_4P 70 FL9020 FILTER_4P 70 FL9021 FILTER_4P 70 G6500 OSC 52 J1250 CON_M8RT_S_SM 12 J2690 CON_M16ST_D_SMA 24 J3300 CON_2RTSM_125 30 J3320 CON_M16ST_D_SMA 30 J3350 CON_M16ST_D_SMA 30 J3400 CON_M4RT_S_SM 31 J3410 CON_M16ST_D_SMA 31 J3420 CON_M3RT_S2MT_SM 31 J3430 CON_4RT_WRIB 31 J3450 CON_M4RT_S2MT_SM 31 J3460 CON_M4RT_S2MT_SM 31 J3999 CON_12 36 J5000 CON_F400RT_DDR2DIMM_SM1 40 41 J6900 CON_F30RT_S2MT_SM 56 J6950 CON_4RT_WRIB 56 J7000 CON_F30RT_T6MT_TH1 57 J7060 CON_F5RT_MINIDIN_TH 57 J7300 CON_F80ST_D4MT_SM 60 J7490 CON_M80ST_D4MT_SM 61 J8200 CON_M50SM_5MM 64 J8250 CON_M50SM_5MM 64 J8600 CON_RJ45_10RT_S4MT_TH1 67 J9010 CON_F9RT_1394B_S6MT_SMA 70 J9020 CON_F6RT_S4MT_TH1 70 JA000 CON_M50SM_5MM 74 L1250 IND 12 L1251 IND 12 L1252 IND 12 L1253 IND 12 L1254 IND 12 L1300 IND 13 L1400 IND_3P 14 L1501 IND 15 L1551 IND 15 L1601 IND 16 L1651 IND 16 L1700 IND 17 L1900 IND 18 L1970 IND 18 L1990 IND 18 L2200 IND 20 L3130 IND 28 L3300 IND 30 L3350 IND 30 L3354 IND 30 L3355 IND 30 L3900 IND_3P 36 L5800 IND_3P 45 L5950 IND 46 L5990 IND 46 L6000 IND 47 L6010 IND 47 L6011 IND 47 L6020 IND 47 L6040 IND 47 L6041 IND 47 L6043 IND 47 L6048 IND 47 L6050 IND 47 L6095 IND 47 L6403 IND 51 L6410 IND 51 L6500 IND 52 L6510 IND 52 L6600 IND 53 L6610 IND 53 L6615 IND 53 L6620 IND 53 L6625 IND 53 L6720 IND 54 L6723 IND 54 L6726 IND 54 L6830 IND 55 L6833 IND 55 L6836 IND 55 L6900 IND 56 L6950 IND 56 L6952 IND 56 L6953 IND 56 L6955 IND 56 L7000 FILTER_4P 57 L7001 FILTER_4P 57 L7002 FILTER_4P 57 L7003 FILTER_4P 57 L7004 FILTER_4P 57 L7005 FILTER_4P 57 L7006 FILTER_4P 57 L7010 IND 57 L7060 IND 57 L7061 IND 57 L7062 IND 57 L7064 IND 57 L7066 IND 57 L8510 IND 66 L8520 IND 66 L8530 IND 66 L8900 IND 69 L8901 IND 69 L8902 IND 69 L8906 IND 69 L8909 IND 69 L8913 IND 69 L9010 IND 70 L9020 IND 70 L9090 IND 70 L9335 IND 73 PD3100 PHOTODIODE_2P 28 Q1208 TRA_2N7002DW 12 Q1210 TRA_IRF7416 12

Q1215 TRA_2N7002DW 12 Q1220 TRA_2N7002 12 Q1300 TRA_RLA130 13 Q1301 TRA_IRF7811W 13 Q1330 TRA_2N7002DW 13 Q1340 TRA_2N7002DW 13 Q1347 TRA_2N7002DW 13 Q1348 TRA_2N7002DW 13 Q1360 TRA_IRF7416 13 Q1384 TRA_2N7002DW 13 Q1390 TRA_IRF7416 13 Q1392 TRA_2N7002DW 13 Q1395 TRA_SUD45P03 13 Q1400 TRA_RLA130 14 Q1401 TRA_IRF7811W 14 Q1430 TRA_FDG6324L 14 Q1501 TRA_RLA130 15 Q1502 TRA_IRF7811W 15 Q1533 TRA_2N7002 15 Q1535 TRA_SI3443DV 15 Q1551 TRA_RLA130 15 Q1552 TRA_IRF7811W 15 Q1580 TRA_SI3443DV 15 Q1585 TRA_SI3443DV 15 Q1590 TRA_SI3443DV 15 Q1601 TRA_RLA130 16 Q1602 TRA_IRF7805 16 Q1640 TRA_2N7002 16 Q1651 TRA_RLA130 16 Q1652 TRA_IRF7805 16 Q1680 TRA_SI6467BDQ 16 Q1685 TRA_SI3446DV 16 Q1740 TRA_2N7002DW 17 Q1780 TRA_SI6467BDQ 17 Q1950 TRA_2N7002DW 18 Q1960 TRA_2N7002 18 Q1965 TRA_NDS9407 18 Q2470 TRA_2N7002DW 22 Q2480 TRA_2N7002DW 22 Q2481 TRA_2N7002DW 22 Q2600 TRA_2N3906 24 Q2601 TRA_2N7002 24 Q2680 TRA_2N7002DW 24 Q2900 TRA_2N7002DW 26 Q2910 TRA_2N7002DW 26 Q2940 TRA_2N7002DW 26 Q2941 TRA_2N7002DW 26 Q2948 TRA_2N7002 26 Q3001 TRA_2N3904 27 Q3002 TRA_2N3904 27 Q3003 TRA_2N3904 27 Q3004 TRA_2N3904 27 Q3103 TRA_2N7002DW 28 Q3900 TRA_HAT2168H 36 Q3902 TRA_HAT2160H 36 Q3903 TRA_HAT2160H 36 Q3940 TRA_2N7002DW 36 Q5800 TRA_SI7860DP 45 Q5801 TRA_SI7892DP 45 Q5884 TRA_2N7002DW 45 Q5950 TRA_SI3446DV 46 Q6900 TRA_SI3443DV 56 Q6901 TRA_2N7002 56 Q6950 TRA_FDG6324L 56 Q7011 TRA_2N7002DW 57 Q7014 TRA_2N7002DW 57 Q7075 TRA_TP0610 57 Q7076 TRA_2N7002DW 57 Q7080 TRA_DUAL_MMDT3904 57 Q7081 TRA_TP0610 57 Q8420 TRA_2N7002DW 65 67 Q8580 TRA_2N7002DW 66 Q8620 TRA_SI6467BDQ 67 R0820 RES 8 R0821 RES 8 R0830 RES 8 R0831 RES 8 R0840 RES 8 R0841 RES 8 R0842 RES 8 R0843 RES 8 R0850 RES 8 R0851 RES 8 R0950 RES 9 R0980 RES 9 R0981 RES 9 R0982 RES 9 R0983 RES 9 R0984 RES 9 R0985 RES 9 R0990 RES 9 R1015 RES 10 R1018 RES 10 R1025 RES 10 R1033 RES 10 R1110 RES 11 R1111 RES 11 R1120 RES 11 R1130 RES 11 R1135 RES 11 R1136 RES 11 R1137 RES 11 R1140 RES 11 R1160 RES 11 R1161 RES 11 R1162 RES 11 R1163 RES 11 R1164 RES 11 R1165 RES 11 R1166 RES 11 R1167 RES 11 R1170 RES 11 R1171 RES 11 R1172 RES 11 R1173 RES 11 R1174 RES 11 R1175 RES 11 R1176 RES 11 R1177 RES 11 R1185 RES 11 R1201 RES 12 R1202 RES 12 R1203 RES 12 R1204 RES 12 R1205 RES 12 R1206 RES 12 R1207 RES 12 R1208 RES 12 R1209 RES 12 R1210 RES 12 R1215 RES 12 R1216 RES 12 R1221 RES 12 R1222 RES 12 R1223 RES 12 R1224 RES 12 R1225 RES 12 R1226 RES 12 R1227 RES 12 R1228 RES 12 R1250 RES 12 R1251 RES 12 R1252 RES 12 R1255 RES 12 R1256 RES 12 R1300 RES 13 R1301 RES 13 R1302 RES 13 R1303 RES 13 R1304 RES 13 R1305 RES 13 R1317 RES 13 R1318 RES 13 R1319 RES 13 R1320 RES 13 R1321 RES 13 R1322 RES 13 R1323 RES 13 R1324 RES 13 R1325 RES 13 R1328 RES 13 R1329 RES 13 R1330 RES 13 R1340 RES 13 R1341 RES 13 R1342 RES 13 R1343 RES 13 R1344 RES 13

R1345 RES 13 R1346 RES 13 R1347 RES 13 R1348 RES 13 R1351 RES 13 R1352 RES 13 R1353 RES 13 R1354 RES 13 R1360 RES 13 R1361 RES 13 R1370 RES 13 R1380 RES 13 R1381 RES 13 R1382 RES 13 R1383 RES 13 R1384 RES 13 R1385 RES 13 R1386 RES 13 R1387 RES 13 R1390 RES 13 R1391 RES 13 R1392 RES 13 R1395 RES 13 R1396 RES 13 R1401 RES 14 R1402 RES 14 R1410 RES 14 R1415 RES 14 R1416 RES 14 R1420 RES 14 R1421 RES 14 R1422 RES 14 R1425 RES 14 R1427 RES 14 R1430 RES 14 R1450 RES 14 R1451 RES 14 R1452 RES 14 R1453 RES 14 R1461 RES 14 R1501 RES 15 R1502 RES 15 R1503 RES 15 R1504 RES 15 R1505 RES 15 R1510 RES 15 R1511 RES 15 R1512 RES 15 R1530 RES 15 R1531 RES 15 R1532 RES 15 R1533 RES 15 R1535 RES 15 R1551 RES 15 R1552 RES 15 R1553 RES 15 R1554 RES 15 R1555 RES 15 R1560 RES 15 R1561 RES 15 R1562 RES 15 R1601 RES 16 R1602 RES 16 R1620 RES 16 R1621 RES 16 R1630 RES 16 R1631 RES 16 R1632 RES 16 R1633 RES 16 R1634 RES 16 R1640 RES 16 R1641 RES 16 R1651 RES 16 R1652 RES 16 R1670 RES 16 R1671 RES 16 R1680 RES 16 R1720 RES 17 R1722 RES 17 R1723 RES 17 R1724 RES 17 R1730 RES 17 R1731 RES 17 R1732 RES 17 R1733 RES 17 R1950 RES 18 R1951 RES 18 R1952 RES 18 R1960 RES 18 R1961 RES 18 R1963 RES 18 R1965 RES 18 R1966 RES 18 R1990 RES 18 R1991 RES 18 R1992 RES 18 R1993 RES 18 R1994 RES 18 R1995 RES 18 R1996 RES 18 R1997 RES 18 R1998 RES 18 R2101 RES 19 R2102 RES 19 R2103 RES 19 R2104 RES 19 R2105 RES 19 R2106 RES 19 R2107 RES 19 R2109 RES 19 R2204 RES 20 R2205 RES 20 R2207 RES 20 R2208 RES 20 R2209 RES 20 R2210 RES 20 R2211 RES 20 R2212 RES 20 R2255 RES 20 R2256 RES 20 R2300 RES 21 R2301 RES 21 R2302 RES 21 R2303 RES 21 R2304 RES 21 R2305 RES 21 R2306 RES 21 R2307 RES 21 R2308 RES 21 R2309 RES 21 R2310 RES 21 R2311 RES 21 R2340 RES 21 R2350 RES 21 R2352 RES 21 R2360 RES 21 R2365 RES 21 R2367 RES 21 R2380 RES 21 R2385 RES 21 R2387 RES 21 R2392 RES 21 R2400 RES 22 R2401 RES 22 R2410 RES 22 R2411 RES 22 R2451 RES 22 R2452 RES 22 R2455 RES 22 R2460 RES 22 R2461 RES 22 R2462 RES 22 R2463 RES 22 R2464 RES 22 R2470 RES 22 R2471 RES 22 R2472 RES 22 R2480 RES 22 R2481 RES 22 R2482 RES 22 R2490 RES 22 R2600 RES 24 R2601 RES 24 R2602 RES 24 R2610 RES 24 R2680 RES 24 R2690 RES 24 R2691 RES 24

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R2692 RES 24 R2695 RES 24 R2696 RES 24 R2705 RES 25 R2710 RES 25 R2715 RES 25 R2730 RES 25 R2740 RES 25 R2741 RES 25 R2750 RES 25 R2751 RES 25 R2760 RES 25 R2761 RES 25 R2765 RES 25 R2766 RES 25 R2767 RES 25 R2768 RES 25 R2770 RES 25 R2771 RES 25 R2772 RES 25 R2773 RES 25 R2774 RES 25 R2900 RES 26 R2901 RES 26 R2902 RES 26 R2903 RES 26 R2910 RES 26 R2911 RES 26 R2912 RES 26 R2913 RES 26 R2920 RES 26 R2921 RES 26 R2922 RES 26 R2929 RES 26 R2930 RES 26 R2935 RES 26 R2936 RES 26 R2940 RES 26 R2941 RES 26 R2943 RES 26 R2948 RES 26 R2949 RES 26 R2951 RES 26 R2958 RES 26 R2965 RES 26 R2966 RES 26 R2967 RES 26 R2969 RES 26 R3000 RES 27 R3001 RES 27 R3002 RES 27 R3003 RES 27 R3004 RES 27 R3005 RES 27 R3010 RES 27 R3011 RES 27 R3012 RES 27 R3013 RES 27 R3020 RES 27 R3021 RES 27 R3022 RES 27 R3023 RES 27 R3100 RES 28 R3101 RES 28 R3102 RES 28 R3103 RES 28 R3104 RES 28 R3105 RES 28 R3130 RES 28 R3131 RES 28 R3132 RES 28 R3220 RES 29 R3300 RES 30 R3301 RES 30 R3320 RES 30 R3321 RES 30 R3352 RES 30 R3353 RES 30 R3355 RES 30 R3500 RES 32 R3505 RES 32 R3506 RES 32 R3513 RES 32 R3514 RES 32 R3550 RES 32 R3551 RES 32 R3600 RES 33 R3601 RES 33 R3610 RES 33 R3611 RES 33 R3620 RES 33 R3702 RES 34 R3703 RES 34 R3704 RES 34 R3705 RES 34 R3706 RES 34 R3707 RES 34 R3720 RES 34 R3721 RES 34 R3722 RES 34 R3723 RES 34 R3724 RES 34 R3725 RES 34 R3726 RES 34 R3727 RES 34 R3728 RES 34 R3729 RES 34 R3730 RES 34 R3731 RES 34 R3752 RES 34 R3753 RES 34 R3756 RES 34 R3757 RES 34 R3758 RES 34 R3759 RES 34 R3761 RES 34 R3765 RES 34 R3766 RES 34 R3767 RES 34 R3769 RES 34 R3771 RES 34 R3772 RES 34 R3900 RES 36 R3901 RES 36 R3910 RES 36 R3940 RES 36 R3941 RES 36 R3942 RES 36 R3943 RES 36 R3944 RES 36 R3945 RES 36 R3946 RES 36 R3950 RES 36 R3951 RES 36 R3960 RES 36 R3961 RES 36 R3962 RES 36 R3963 RES 36 R3964 RES 36 R3965 RES 36 R3970 RES 36 R3971 RES 36 R3972 RES 36 R3973 RES 36 R3974 RES 36 R3975 RES 36 R3976 RES 36 R3977 RES 36 R3980 RES 36 R3981 RES 36 R3982 RES 36 R3983 RES 36 R3984 RES 36 R3985 RES 36 R3986 RES 36 R3987 RES 36 R3988 RES 36 R3989 RES 36 R3990 RES 36 R3998 RES 36 R3999 RES 36 R4600 RES 37 R4610 RES 37 R4611 RES 37 R4620 RES 37 R4621 RES 37 R4625 RES 37 R4700 RES 38

R4701 RES 38 R4710 RES 38 R4810 RES 39 R4811 RES 39 R4850 RES 39 R4851 RES 39 R4855 RES 39 R4856 RES 39 R4860 RES 39 R4861 RES 39 R4865 RES 39 R4866 RES 39 R5001 RES 40 R5002 RES 40 R5600 RES 43 R5605 RES 43 R5610 RES 43 R5611 RES 43 R5612 RES 43 R5613 RES 43 R5614 RES 43 R5615 RES 43 R5616 RES 43 R5617 RES 43 R5618 RES 43 R5619 RES 43 R5620 RES 43 R5700 RES 44 R5720 RES 44 R5721 RES 44 R5722 RES 44 R5725 RES 44 R5726 RES 44 R5730 RES 44 R5731 RES 44 R5820 RES 45 R5821 RES 45 R5822 RES 45 R5823 RES 45 R5826 RES 45 R5827 RES 45 R5828 RES 45 R5829 RES 45 R5830 RES 45 R5880 RES 45 R5881 RES 45 R5882 RES 45 R5883 RES 45 R5884 RES 45 R5885 RES 45 R6103 RES 48 R6104 RES 48 R6105 RES 48 R6106 RES 48 R6107 RES 48 R6108 RES 48 R6109 RES 48 R6153 RES 48 R6154 RES 48 R6155 RES 48 R6156 RES 48 R6157 RES 48 R6158 RES 48 R6159 RES 48 R6190 RES 48 R6191 RES 48 R6192 RES 48 R6193 RES 48 R6194 RES 48 R6196 RES 48 R6197 RES 48 R6198 RES 48 R6199 RES 48 R6240 RES 49 R6241 RES 49 R6245 RES 49 R6246 RES 49 R6290 RES 49 R6291 RES 49 R6295 RES 49 R6296 RES 49 R6340 RES 50 R6341 RES 50 R6345 RES 50 R6346 RES 50 R6390 RES 50 R6391 RES 50 R6395 RES 50 R6396 RES 50 R6400 RES 51 R6420 RES 51 R6421 RES 51 R6422 RES 51 R6423 RES 51 R6450 RES 51 R6451 RES 51 R6452 RES 51 R6453 RES 51 R6454 RES 51 R6455 RES 51 R6456 RES 51 R6457 RES 51 R6458 RES 51 R6459 RES 51 R6460 RES 51 R6461 RES 51 R6462 RES 51 R6463 RES 51 R6470 RES 51 R6490 RES 51 R6498 RES 51 R6499 RES 51 R6500 RES 52 R6501 RES 52 R6502 RES 52 R6503 RES 52 R6510 RES 52 R6511 RES 52 R6512 RES 52 R6513 RES 52 R6514 RES 52 R6530 RES 52 R6640 RES 53 R6641 RES 53 R6642 RES 53 R6650 RES 53 R6651 RES 53 R6660 RES 53 R6661 RES 53 R6662 RES 53 R6670 RES 53 R6671 RES 53 R6672 RES 53 R6680 RES 53 R6681 RES 53 R6690 RES 53 R6730 RES 54 R6731 RES 54 R6732 RES 54 R6733 RES 54 R6734 RES 54 R6740 RES 54 R6741 RES 54 R6742 RES 54 R6752 RES 54 R6754 RES 54 R6760 RES 54 R6761 RES 54 R6762 RES 54 R6763 RES 54 R6764 RES 54 R6765 RES 54 R6766 RES 54 R6767 RES 54 R6800 RES 55 R6801 RES 55 R6802 RES 55 R6803 RES 55 R6804 RES 55 R6805 RES 55 R6880 RES 55 R6881 RES 55 R6882 RES 55 R6900 RES 56 R6901 RES 56 R6910 RES 56 R6911 RES 56 R6950 RES 56

R6999 RES 56 R7010 RES 57 R7011 RES 57 R7012 RES 57 R7013 RES 57 R7014 RES 57 R7020 RES 57 R7021 RES 57 R7022 RES 57 R7030 RES 57 R7031 RES 57 R7040 RES 57 R7041 RES 57 R7042 RES 57 R7050 RES 57 R7051 RES 57 R7070 RES 57 R7071 RES 57 R7072 RES 57 R7073 RES 57 R7075 RES 57 R7076 RES 57 R7077 RES 57 R7078 RES 57 R7079 RES 57 R7080 RES 57 R7081 RES 57 R7082 RES 57 R7083 RES 57 R7150 RES 58 R7151 RES 58 R7152 RES 58 R7205 RES 59 R7252 RES 59 R7253 RES 59 R7254 RES 59 R7300 RES 60 R7305 RES 60 R7400 RES 61 R7410 RES 61 R7411 RES 61 R7412 RES 61 R7420 RES 61 R7421 RES 61 R7422 RES 61 R7423 RES 61 R7424 RES 61 R7430 RES 61 R7450 RES 61 R7500 RES 62 R7501 RES 62 R7502 RES 62 R7503 RES 62 R7504 RES 62 R7510 RES 62 R7511 RES 62 R7512 RES 62 R8100 RES 63 R8151 RES 63 R8160 RES 63 R8161 RES 63 R8162 RES 63 R8163 RES 63 R8164 RES 63 R8165 RES 63 R8166 RES 63 R8167 RES 63 R8200 RES 64 R8201 RES 64 R8202 RES 64 R8203 RES 64 R8210 RES 64 R8211 RES 64 R8212 RES 64 R8255 RES 64 R8400 RES 65 R8405 RES 65 R8410 RES 65 R8420 RES 65 R8421 RES 65 R8501 RES 66 R8509 RES 66 R8560 RES 66 R8561 RES 66 R8562 RES 66 R8569 RES 66 R8580 RES 66 R8590 RES 66 R8591 RES 66 R8592 RES 66 R8593 RES 66 R8594 RES 66 R8595 RES 66 R8596 RES 66 R8597 RES 66 R8620 RES 67 R8621 RES 67 R8800 RES 68 R8902 RES 69 R8903 RES 69 R8904 RES 69 R8905 RES 69 R8906 RES 69 R8909 RES 69 R8911 RES 69 R8912 RES 69 R8914 RES 69 R8915 RES 69 R8916 RES 69 R8921 RES 69 R8931 RES 69 R8933 RES 69 R8935 RES 69 R8998 RES 69 R8999 RES 69 R9011 RES 70 R9050 RES 70 R9051 RES 70 R9052 RES 70 R9053 RES 70 R9054 RES 70 R9060 RES 70 R9061 RES 70 R9062 RES 70 R9063 RES 70 R9064 RES 70 R9070 RES 70 R9090 RES 70 R9099 RES 70 R9100 RES 71 R9101 RES 71 R9102 RES 71 R9103 RES 71 R9200 RES 72 R9220 RES 72 R9221 RES 72 R9250 RES 72 R9300 RES 73 R9301 RES 73 R9302 RES 73 R9303 RES 73 R9304 RES 73 R9305 RES 73 R9306 RES 73 R9307 RES 73 R9310 RES 73 R9335 RES 73 R9338 RES 73 R9339 RES 73 R9340 RES 73 R9341 RES 73 R9345 RES 73 RP0990 RPAK4P 9 RP1150 RPAK4P 11 RP1151 RPAK4P 11 RP2450 RPAK4P 22 RP3510 RPAK4P 32 RP3511 RPAK4P 32 RP3512 RPAK4P 32 RP3513 RPAK4P 32 RP3514 RPAK4P 32 RP3990 RPAK4P 36 RP4800 RPAK4P 39 RP4801 RPAK4P 39 RP4802 RPAK4P 39 RP4803 RPAK4P 39 RP4804 RPAK4P 39 RP4870 RPAK2P 39

RP4871 RPAK2P 39 RP4872 RPAK4P 39 RP4873 RPAK4P 39 RP4875 RPAK2P 39 RP4876 RPAK2P 39 RP4877 RPAK4P 39 RP4878 RPAK4P 39 RP5610 RPAK4P 43 RP5611 RPAK4P 43 RP6100 RPAK4P 48 RP6101 RPAK4P 48 RP6102 RPAK4P 48 RP6108 RPAK2P 48 RP6109 RPAK2P 48 RP6150 RPAK4P 48 RP6151 RPAK4P 48 RP6152 RPAK4P 48 RP6158 RPAK2P 48 RP6159 RPAK2P 48 RP6707 RPAK2P 54 RP6708 RPAK2P 54 RP6709 RPAK2P 54 RP6710 RPAK2P 54 RP6720 RPAK4P 54 RP6721 RPAK4P 54 RP6722 RPAK4P 54 RP6723 RPAK4P 54 RP6811 RPAK2P 55 RP6812 RPAK2P 55 RP6813 RPAK2P 55 RP6821 RPAK4P 55 RP6822 RPAK4P 55 RP6823 RPAK4P 55 RP7250 RPAK4P 59 RP7251 RPAK4P 59 RP7410 RPAK4P 61 RP7510 RPAK4P 62 RP8150 RPAK4P 63 RP8151 RPAK4P 63 RP8152 RPAK4P 63 RP8153 RPAK4P 63 RP8154 RPAK4P 63 RP9100 RPAK4P 71 RP9101 RPAK4P 71 RP9210 RPAK4P 72 RP9211 RPAK4P 72 RP9212 RPAK4P 72 RP9300 RPAK4P 73 RP9301 RPAK4P 73 RP9310 RPAK4P 73 SH0200 SHLD_3P_EMI 2 U1200 COMPARATOR_LMC7211 12 U1220 COMPARATOR_LMC7211 12 U1250 INA138 12 U1300 MAX1772 13 U1350 COMPARATOR_LMC7211 13 U1370 AMP_MAX4172 13 U1380 OPAMP_LMC7111 13 U1400 LTC1625 14 U1420 COMPARATOR_LMC7211 14 U1450 VREG_LP2951 14 U1460 VREG_LP2951 14 U1500 LTC3707 15 U1600 MAX1715 16 U1700 LTC3412 17 U1970 VREG_LM2594 18 U1980 VREG_MM1572FN 18 U1990 LTC3411 18 U2100 I2 19 22 32 38 43 59 63 65 68 72 U2200 LTC3412 20 U2250 VREG_LT1962 20 U2390 SN74AUC1G74 21 U2391 SN74AUC1G74 21 U2392 SN74AUC1G74 21 U2500 CLK_DR_CDCVF2505 23 U2700 M30280F8 25 U3000 ADT7467 27 U3100 OPAMP_MAX4236EUTT 28 U3130 MM3120 28 U3220 KXM52 29 U3600 A8 33 34 35 U3900 MAX1717 36 U3990 PI3B3257 36 U4600 FAN2558 37 U5700 M11P 44 46 47 48 51 53 U5800 LTC1778 45 U6200 SDRAM_DDR_K4D553235F 49 U6250 SDRAM_DDR_K4D553235F 49 U6300 SDRAM_DDR_K4D553235F 50 U6350 SDRAM_DDR_K4D553235F 50 U6400 VREG_MM1571J 51 U6510 CLK_GEN_CY25811 52 U6530 MAX8860 52 U6700 SIL1178CS48 54 U6800 SIL1178CS48 55 U6953 NC7S32 56 U7050 741G32 57 U7051 741G32 57 U7070 COMPARATOR_LMC7211 57 U7100 FEPR_1MX8 58 U7400 PCI1510GGU 61 U7450 PWR_CNTRL_TPS2211 61 U7500 UPD720101_FBGA_SPLIT 62 73 U8500 BCM5462 18 66 69 XW1012 SHORT 10 XW1013 SHORT 10 XW1015 SHORT 10 XW1017 SHORT 10 XW1018 SHORT 10 XW1019 SHORT 10 XW1025 SHORT 10 XW1033 SHORT 10 XW1050 SHORT 10 XW1251 SHORT 12 XW1252 SHORT 12 XW1300 SHORT 13 XW1400 SHORT 14 XW1500 SHORT 15 XW1600 SHORT 16 XW1700 SHORT 17 XW1990 SHORT 18 XW2200 SHORT 20 XW2700 SHORT 25 XW2970 SHORT 26 XW3900 SHORT 36 XW3901 SHORT 36 XW3910 SHORT 36 XW3911 SHORT 36 XW5800 SHORT 45 XW6590 SHORT 52 XW6591 SHORT 52 XW6592 SHORT 52 XW6593 SHORT 52 XW7060 SHORT 57 XW7061 SHORT 57 XW9070 SHORT 70 XW9071 SHORT 70 XWA000 SHORT 74 XWA001 SHORT 74 XWA033 SHORT 74 XWA050 SHORT 74 XWA051 SHORT 74 Y2410 CRYSTAL 22 Y2740 CRYSTAL 25 Y2750 CRYSTAL 25 Y8500 CRYSTAL 66 Y8920 CRYSTAL 69 Y9220 CRYSTAL 72 Y9345 CRYSTAL 73 ZT0200 HOLE_VIA 2 ZT0201 HOLE_VIA 2 ZT0202 HOLE_VIA 2 ZT0203 HOLE_VIA 2 ZT0210 HOLE_VIA 2 ZT0211 HOLE_VIA 2 ZT0212 HOLE_VIA 2 ZT0221 HOLE_VIA 2 ZT0222 HOLE_VIA 2 ZT0223 HOLE_VIA 2

Apple A1138 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual