Apple A1085 Schematic

TABLE_5_ITEM
ANGLES
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
DATE
APPD
ENG
DATE
APPD
ECN
ZONE
REV
DO NOT SCALE DRAWING
X.XXX
X.XX
XX
DIMENSIONS ARE IN MILLIMETERS
THIRD ANGLE PROJECTION
D
SIZE
APPLICABLE
NOTED AS
MATERIAL/FINISH
NONE
SCALE
DESIGNER
MFG APPD
DESIGN CK
RELEASE
QA APPD
ENG APPD
DRAFTER
METRIC
OF
SHT
DRAWING NUMBER
TITLE
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
Apple Computer Inc.
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
DESCRIPTION OF CHANGE
REFERENCE DESIGNATOR(S)
BOM OPTION
TABLE_5_HEAD
QTY
DESCRIPTION
PART#
TABLE_5_ITEM
SINCLAIR Q41A
INTREPID GPIOS/SERIAL/USB INTERFACES/SSCG
BATTERY CHARGER AND CONNECTOR
MARVELL GIGABIT ETHERNET PHY
SERIAL DEBUG (JOLLY ROGER, PWR/NMI/RESET)
17
STUFF
EXT_TMDS
ATI_MEMIO_LO
ATI_MEMIO_HI
INTREPID_USB
NEC_USB
1_5V_MAXBUS
D3_HOT D3_COLD
FIREWIRE A/B CONNECTORS, PORT POWER LIMITER
25
24
5V_HD_LOGIC 3V_HD_LOGIC
NO_4XVCORE
INT_TMDS
NO_SSCG
SPIDEY - KBD,TPAD,HALL EFFECT,PWR BUTTON
DUAL-CHANNEL LVDS
CONTENTS
PAGE
INTREPID AGP 4X/PCI
INTREPID MEMORY INTERFACE / BOOT ROM
10
MPC7450 DATA
TITLE PAGE AND CONTENTS
CPU PLL AND CONFIGURATION STRAPS
200PIN DDR MEMORY SODIMM CONNECTORS
INTREPID ENET/FW/UATA/EIDE INTERFACES
2
BBANG NO_BBANG
32
30
1
4 5
13
11 12
14
9
18
SSCG
35
33
8
DDR MEMORY MUXES
INTREPID MAXBUS AND BOOT STRAPS
31
28
GPU_SS
NO STUFF
GPU_SWITCH SERIAL_DEBUG VCORE_OFFSET 1_8V_MAXBUS
BOM OPTIONS
3
SYSTEM BLOCK DIAGRAM
20
SIL1162 TMDS TRANSMITTER
39
PAGE
26 27
29
22 23
COMPONENT LOCATIONS
SIGNAL NAMES
FUNCTIONAL TEST POINTS
SIGNAL CONSTRAINTS (2 OF 3) - DIGITAL/DIFF
1.5V/ 1.8V / 2.5V SYSTEM POWER SUPPLIES
CPU CORE VOLTAGE POWER SUPPLY
3.3V / 5V SYSTEM POWER SUPPLIES
12.8V SYSTEM POWER SUPPLY / PMU POWER SUPPLY
PMU (POWER MANAGEMENT UNIT)
INTERNAL CONNECTORS - DVD,
LMU, LIGHT SENSOR, BOOTBANGER, SLEEP LED
36 37 38
40
M10 ANALOG, POWER, GND
SIGNAL CONSTRAINTS (3 OF 3) - POWER NETS
43-44
41-42
FAN CONTROLLER, MODEM, SOUND
VIDEO CONNECTORS - INVERTER, DVI, S-VIDEO
CARDSLOT, HARD DRIVE, LEFT USB/BLUETOOTH
USB 2.0
SIGNAL CONSTRAINTS (1 OF 3) - DIGITAL/CLK
REVISION HISTORY (1 OF 1)
M10 LVDS/TMDS/VGA/GPIO & GPU VCORE
M10 AGP & CLOCKS
CARDBUS CONTROLLER (PCI1510)
INTREPID DECOUPLING
INTREPID POWER RAILS
FIREWIRE A/B PHY
34
21
16
15
19
7
6
MPC7450 MAXBUS INTERFACE
PCB NOTES AND HOLES
POWER BLOCK DIAGRAM
CONTENTS
12/18/2003
1
PCB1820-1615
PCBF,MLB,Q41A
ENGINEERING RELEASED
051-6598
44
?
30806001
1
12/19/03
SCHEM,MLB,Q41A
01
SCH1
1
051-6598
SCHEM,MLB,Q41A
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
USB PORT E
2 DATA PAIRS
RIGHT USB
Connector
Modem Board
CPU PLL
Config
MEMORY BUS
I2S I2C
AGP BUS
USB PORT A
P.15
P.14P.14
USB 2.0
USB 2.0
J12
J3 (SHARE WITH BLUETOOTH)
J3 (SHARE WITH LEFT USB)
J9
U44
J20/J23
U11/U12/U13/U14
J16
J7
J17
J8
U43
J5
J21
U26
J10
CARDBUS
J15
U39
U36
J19
J25
U48/J2/J4
J14
J11
J13
U28
J22
J24
U49
J18
3.3V/5V
16/32 BITS
33MHZ
I2C
INTRPEID
PMU
167MHZ
1.8V
MAXBUS
32BIT ADDRESS
NOT USED
NOT USED
NOT USED
BACKUP BATTERY
LEFT USB
BlueTooth
I2C
I2S
EIDE
1394 OHCI
3.3V
8BIT TX/RX
@ 200MHz
@ 400MHZ
2 DATA PAIRS
PHY
FW - B
Connector
FW - A
125MHZ
8BIT RX
8BIT TX
3.3V
10/100/1000
Ethernet
PHY
32BITS
Connector
Serial Debug
SCCA
P.15
P.15
P.14
Circuit
Fan
Connector
Connector
TUBA (SOUND)
Connector
SUTRO (PWR)
Connector Connector
Power Supply
& Charger
SERIAL 5V
Connector
P.18
P.18
Connector
RGB
COMPOSITE
LCD Panel
Connector
LVDS
EDID (I2C)
S-Video
Connector
(DDC TOO)
2.5V
167MHZ 64BITS
P.15
P.15
P.15
P.15
P.15
P.14
P.14
P.15
P.13
P.10
P.9
P.12
P.5-6
P.7
PCI BUS
32BITS
3.3V
Controller
CardBus
Connector
CH. B
(INTERNAL MEM)
MEMORY
CH. D
MEMORY
(INTERNAL MEM)
CH. A
(INTERNAL MEM)
MEMORY
CH. C
MEMORY
(INTERNAL MEM)
USB PORT D
USB PORT B
MAXBUS
10/100/1000
2:1 DDR MUXES
SO-DIMM Connector
DDR SDRAM DIMM 0 DDR SDRAM DIMM 1
DDR MEMORY
UATA 100 EIDE
VIA/PMU
BOOTROM
FireWire
Inverter
USB PORT F
USB PORT C
Keyboard
TI PCI1510
OPTICAL DRIVE
TRACKPAD
PMU
LMU
I2C
I2C
Connector
Battery
SMBUS
3.3V
LED
SLEEP
LMU
U17
1M X 8
P.10
KB LED
LIGHT SENSOR
CONTROLLER
U52
U42
CPU
APOLLO
64BIT DATA
P.15
ETHERNET FIREWIRE
P.14
(MPC7457)
800 MB/S
100MHZ
P.11
G/MII
Ethernet
CARDSLOT
Connector
USB 2.0
BOOT ROM
P.14
Connector
DVI-I
TMDS
S-VIDEO
64MB
Connector
SYSTEM BLOCK DIAGRAM
AIRPOPT
33MHZ
1.5V/3.3V
66MHZ
ULTRA ATA/100
PCI
INTREPID
4X AGP
P.13
33MHZ
32BITS
Connector
UIDE
4 DATA PAIRS
P.28
P.30
P.30
P.29
P.25
P.25
P.26
P.26
P.26
P.32
P.31
P.32
P.24
P.32-36
P.26
P.24
P.27
P.25
P.18-21
P.22
P.22 P.22 P.22
P.25
P.33
P.25
P.26
P.28
ATI M11
051-6598
01
44
2
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
+1.2V/+1.0V
WHEN IT’S CONNECTED TO GND
POWER SYSTEM ARCHITECTURE
GPU_VCORE
HOWEVER, 5V SHOULD TURN ON ~2.23MS AFTER
DDR POWER
RUN/SS
HOLDS BOTH RUN/SS AT GND
REGULATOR
+PBUS
+PBUS
AND PREVENTS +PBUS AND +24V_PBUS FROM DROPPING BELOW 6V
BACKUP BATTERY CIRCUIT CHARGES OFF +PBUS
12.8V CHARGES BACKUP BATTERY
+PBUS
AC: 12.8V
+PBUS (12.8V)
PG 31
PG 30
1.9 MS
2.6 MS
+1_8V_MAIN
+1_5V_MAIN
~???MS
~11MS
2.6 MS
~13.5MS
1625 NOT RUNNING
NO AC: BATTERY VOLTAGE
RUN: RUNNING
SLEEP: RUNNING
SHUTDOWN: RUNNING
BATTERY VOLTAGE
STARTS ~4.25MSEC AFTER DCDC_EN_L BECOMES LOW
INTERNAL ZENER CLAMP TO 6V
INTERNAL ZENER CLAMP TO 6V
TURNS ON AT >1V
RUN/SS - 5V
<100UA ALLOWED
MAIN 3V/5V
(LTC3707)
DC/DC
TURNS ON AT >1V
VCC
VCC
DCDC_EN_L
DCDC_EN_L WILL PULL ON1/ON2 LOW IN SHUTDOWN
+5V_MAIN
+1.8V_MAIN
VCC
1_5V_2_5V_OK
+BATT
+BATT
+24V_PBUS
+24V_PBUS
NO INRUSH PROTECTION
WHEN ONLY BATTERY IS CONNECTED
TURNS ON OUTPUT @ 2.4V
RUN: RUNNING
SLEEP: RUNNING
SHUTDOWN: STOPPED
RUN/SS - 3V
SLEEP: RUNNING
RUN: RUNNING
SHUTDOWN: STOPPED
24V IS OUTPUT ONLY FROM
CHARGER INPUT
BATTERY
BACKUP
BACKUP BATTERY
1V20_REF
+
-
U21
FEED-IN PATH
& BOOST OUTPUT
3S 3P PRISMATIC CELLS
POWER BLOCK DIAGRAM
(UNTIL DRAINED)
AC
IN
ADAPTER
LIMITER
INRUSH
>~13.44V TURNS-ON <~13.44V SHUTS-OFF
BUCK
BATTERY
CHARGER
(MAX1772)
+3V_PMU
LDO
+3V_PMU
14V_PBUS
+5V_MAIN
WHEN ONLY BATTERY IS CONNECTED
NO INRUSH PROTECTION
WHEN IT’S OPEN
TURNS CONTROL TO RUN/SS
INVERTER
BACKLIGHT
DC/DC
(MAX1715)
PGOOD
3V_5V_OK
PGOOD
ON1/ON2
+4_6V_BU
+5V_MAIN
+1.5V_MAIN
AGP I/O
MAXBUS BROADCOM
DC/DC
(MAX1717)
+5V_MAIN
SHDN
VCC
SLEEP
DCDC_EN
MAXBUS
SEQUENCING
+5V_MAIN
RUN: RUNNING
VCC
D3_COLD
SLEEP
DCDC_EN
DCDC_EN_L OR PMU_POWERUP_L
+5V_MAIN TURNS ON
1_5V_2_5V_OK WILL NOT PULL LOW UNTIL
INTERNAL 1.2UA CURRENT SOURCE
RUN/SS
D3_HOT
D3_HOT
1_5V_2_5V_OK
DCDC_EN_L
SEQUENCING
GPU_VCORE
~5.88MS TO START SWITCHER
1M & 0.1UF @14V, IT TAKES
CPU_VCORE
(+1.4V/+1.5V)
DCDC_EN_L
DCDC_EN
+5V_MAIN
+3V_MAIN
+5V_SLEEP
+3V_SLEEP
2.4V - ??? MS
3V_5V_OK
SLEEP_L_LS5
SLEEP
+2_5V_MAIN
+2_5V_SLEEP
+1_5V_SLEEP
1_5V_2_5V_OK
(MAX1715 OUTPUT)
1_5V_2_5V_OK
(AT LTC1778 RUN/SS)
GPU_VCORE
(D3HOT)
GPU_VCORE
(D3COLD)
SLEEP
RUN
SHUT-DOWN
RUN
PG 31
PG 32
PG 32
PG 31
PG 31
PG 33
PG 32
DC/DC
(LTC1778)
SHUTDOWN: STOPPED
PG 20
SHUTDOWN: STOPPED
SLEEP: STOPPED
RUN: RUNNING
PG 35
PG 34
SLEEP: STOPPED
RUN: RUNNING
SHUTDOWN: STOPPED
MAIN 2.5V/1.5V
+5V_MAIN
INTREPID CORE
+2.5V_MAIN
MAP31 DDR I/O
RC CHARGING AT INT_VCC (5V)
TURNS ON AS LOW AS 0.8V/TYP 1.5V
EXT_VCC
AFTER PMU IS UP AND RUNNING
BECOMES ’1’; MUCH LESS THAN THE
SLEEP: D3HOT/D3COLD
+PBUS (12.8V)
SHUT-DOWN
(LTC1625)
STARTS 2.0MSEC AFTER DCDC_EN_L BECOMES LOW
(LTC3411)
PG 35
DC/DC
+3.3V_MAIN
STBYMD
<100UA ALLOWED
RC AT 1M*0.047UF @ 24V
RC AT 1M*0.1UF @ 24V
MAP31 DDR CORE
44
3
01
051-6598
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
I/O AREA
CONDUCTIVE MOUNTS
SPEAKER CLIPS
BOARD HOLES
CHASSIS MOUNTS
INVERTER
12
PREPREG (3MIL)
11
9
10
8
7
6
5
4
3
LAMINATE (4MIL)
PREPREG (3MIL)
2
1
LAMINATE (4MIL)
PCB SPECS
SIGNAL TRACE SPACING: 4 MILS
SIGNAL TRACE WIDTH: 4 MILS
SIGNAL (1/3 OZ + COPPER PLATING)
PREPREG (3MIL)
GROUND (1/2 OZ)
LAMINATE (4MIL)
SIGNAL (1/2 OZ)
PREPREG (3MIL)
LAMINATE (4MIL)
LAMINATE (3MIL)
PREPREG (2MIL)
PREPREG (2MIL)
CUT POWER PLANE(1 OZ)
CUT POWER PLANE(1 OZ)
GROUND (1/2 OZ)
GROUND (1/2 OZ)
SIGNAL (1/2 OZ)
SIGNAL (1/3 OZ + COPPER PLATING)
GROUND (1/2 OZ)
SIGNAL (1/2 OZ)
20R10 TH VIA OR VIA IN PAD
SIGNAL (1/2 OZ)
BOARD STACK-UP AND CONSTRUCTION
DIELECTRIC: FR-4
THICKNESS : 1.2 MM / 0.047 IN
1/2 OZ CU THICKNESS: 0.7 MILS
1.0 OZ CU THICKNESS: 1.4 MILS
IMPEDANCE : 50 OHMS +/- 10%
SEE PCB CAD FILES FOR MORE SPECIFIC INFO.
BOARD INFORMATION
ASICS HEATSINK MOUNTS
GROUND VIAS
LAYER COUNT: 12
PREPREG THICKNESS: 2-3 MILS
1
ZT11
255R158
OMIT
1
ZT75
HOLE-VIA-20R10
1
ZT61
HOLE-VIA-20R10
1
ZT63
HOLE-VIA-20R10
1
ZT51
HOLE-VIA-20R10
1
ZT54
HOLE-VIA-20R10
1
ZT42
HOLE-VIA-20R10
1
ZT64
HOLE-VIA-20R10
1
ZT76
HOLE-VIA-20R10
1
ZT59
HOLE-VIA-20R10
1
ZT62
HOLE-VIA-20R10
1
ZT22
HOLE-VIA-20R10
1
ZT3
HOLE-VIA-20R10
1
ZT25
HOLE-VIA-20R10
1
ZT32
HOLE-VIA-20R10
1
ZT31
HOLE-VIA-20R10
1
ZT26
HOLE-VIA-20R10
1
ZT23
HOLE-VIA-20R10
1
ZT19
HOLE-VIA-20R10
1
ZT15
HOLE-VIA-20R10
1
ZT17
HOLE-VIA-20R10
1
ZT13
HOLE-VIA-20R10
1
ZT12
HOLE-VIA-20R10
1
ZT21
HOLE-VIA-20R10
1
ZT14
HOLE-VIA-20R10
1
ZT18
HOLE-VIA-20R10
1
ZT20
HOLE-VIA-20R10
1
ZT4
235R126
OMIT
1
ZT83
OMIT
146R126
1
ZT5
OMIT
146R126
3
2
1
SH1
OG-503040
SHLD-SM
CHGND1
1
SP6
SPKR_CLIP_P84
1
SP1
SPKR_CLIP_P84
1
SP3
SPKR_CLIP_P84
1
SP5
SPKR_CLIP_P84
1
SP2
SPKR_CLIP_P84
1
BS1
STDOFF-217ODX150IDX35H-TH
1
SP4
SPKR_CLIP_P84
1
ZT6
OMIT
235R126
1
ZT16
OMIT
235R126
CHGND6
CHGND2
1
ZT10
OMIT
255R158
CHGND5
1
ZT77
HOLE-VIA-20R10
1
ZT30
HOLE-VIA-20R10
1
ZT28
HOLE-VIA-20R10
1
ZT37
HOLE-VIA-20R10
1
ZT39
HOLE-VIA-20R10
1
ZT40
HOLE-VIA-20R10
1
ZT27
HOLE-VIA-20R10
1
ZT36
HOLE-VIA-20R10
1
ZT38
HOLE-VIA-20R10
1
ZT2
OMIT
255R158
1
ZT24
HOLE-VIA-20R10
1
ZT81
HOLE-VIA-20R10
1
ZT34
HOLE-VIA-20R10
1
ZT33
HOLE-VIA-20R10
1
ZT43
HOLE-VIA-20R10
1
ZT46
HOLE-VIA-20R10
1
ZT50
HOLE-VIA-20R10
1
ZT35
HOLE-VIA-20R10
1
ZT44
HOLE-VIA-20R10
1
ZT66
HOLE-VIA-20R10
1
ZT67
HOLE-VIA-20R10
1
ZT53
HOLE-VIA-20R10
1
ZT52
HOLE-VIA-20R10
1
ZT70
HOLE-VIA-20R10
1
ZT71
HOLE-VIA-20R10
1
ZT78
HOLE-VIA-20R10
1
ZT69
HOLE-VIA-20R10
1
ZT65
HOLE-VIA-20R10
1
ZT45
HOLE-VIA-20R10
1
ZT47
HOLE-VIA-20R10
1
ZT49
HOLE-VIA-20R10
1
ZT56
HOLE-VIA-20R10
1
ZT48
HOLE-VIA-20R10
1
ZT72
HOLE-VIA-20R10
1
ZT55
HOLE-VIA-20R10
1
ZT29
HOLE-VIA-20R10
1
ZT82
HOLE-VIA-20R10
1
ZT74
HOLE-VIA-20R10
1
ZT79
HOLE-VIA-20R10
1
ZT68
HOLE-VIA-20R10
1
ZT60
HOLE-VIA-20R10
1
ZT58
HOLE-VIA-20R10
1
ZT41
HOLE-VIA-20R10
1
ZT7
HOLE-VIA-20R10
1
ZT9
HOLE-VIA-20R10
1
ZT8
HOLE-VIA-20R10
1
ZT1
HOLE-VIA-20R10
1
ZT57
HOLE-VIA-20R10
1
ZT80
HOLE-VIA-20R10
1
ZT73
HOLE-VIA-20R10
44
4
051-6598
01
QACK*
TEA*
A10
MCP*
A23
A28 A29
TRST*
PMON_OUT*
A7
SHD1* HIT*
SHD0*
ARTRY*
AACK*
CI*
WT*
GBL*
TBST*
TS*
BG*
BR*
GND
VDD
A1 A2
A11
A5
A4
A3
A6
A8 A9
A12
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A32
A31
A30
A27
A24 A25
AP1
AP4
AP2 AP3
AP0
A35
A34
A33
TT0
TT4
TSIZ1 TSIZ2
TSIZ0
TT1 TT2 TT3
DTI3
DTI2
TDI TDO TMS TCK
A26
BMODE0*
PMON_IN*
BMODE1*
DTI1
A0
DTI0
LSSD_MODE*
TA*
L2_TSTCLK
L1_TSTCLK
EXT_QUAL
CHKS*
DX*
SRW0*
IARTRY0*
SRW1*
(1 OF 3)
HRESET*
SRESET*
TBEN
QREQ*
CKSTP_IN*
CKSTP_OUT*
SYSCLK
INT* SMI*
PLL_CFG1
CLK_OUT
OVDD
PLL_CFG0
PLL_CFG3
DRDY*
DBG*
PLL_CFG2
PLL_CFG4
BVSEL
AVDD
OVDDSENSE
PG EN
VIN
ADJ
VOUT
GND
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
CPU_VCORE DECOUPLING NETWORK
470OHM FOR BOOT BANGER
MPC7447 MAXBUS
MPC7447 PULL-UPS
CPU_OVDD DECOUPLING NETWORK
PLCAE SHORT CLOSE TO CENTER OF CPU
MORE 0805 10UF CAPS ON VCORE
POWER SUPPLY PAGE (PG 33)
IN FORMER L3 AREA
PLACE BELOW CPU
NC
NC
NC
NC
NC
NC NC
CPU INTERNAL PLL FILTERING
470OHM FOR BOOT BANGER
470OHM FOR BOOT BANGER
TO UXX PIN 5 AND 6
PLACE RXXX AND RXXX CLOSE
VOUT = 0.59*(1+R1/R2)
R1
R2
21
R87
10K
5%
1/16W
MF
402
21
R139
5%
1/16W
MF
402
10K
21
R107
MF
402
1/16W
5%
10K
21
R59
MF
1/16W
470
5%
402
21
R97
5%
1/16W
MF
402
10K
2
1
R85
MF
1/16W
5%
200
402
NO_BBANG
21
R160
MF
1/16W
10K
5%
402
21
R57
1K
1/16W
MF
402
5%
21
R58
1/16W
MF
402
5%
10K
21
R129
5%
10K
1/16W
MF
402
2
1
C39
10V 402
CERM
20%
0.1uF
2
1
C203
CERM
0.1uF
20% 10V
402
2
1
C73
10V 402
CERM
20%
0.1uF
2
1
C74
20% CERM
402
10V
0.1uF
2
1
C194
20%
402
10V CERM
0.1uF
2
1
C40
402
CERM
0.1uF
10V
20%
2
1
C191
20% CERM
10V 402
0.1uF
2
1
C152
CERM
20% 10V
402
0.1uF
2
1
C138
0.1uF
10V CERM
20%
402
2
1
C113
0.1uF
402
CERM
10V
20%
2
1
C104
0.1uF
402
10V CERM
20%
2
1
C115
402
20% 10V CERM
0.1uF
2
1
C38
20% CERM
402
10V
0.1uF
2
1
C224
0.1uF
20% CERM
10V 402
2
1
C48
0.1uF
20% CERM
402
10V
2
1
C90
0.1uF
20% 10V
402
CERM
2
1
C72
10V 402
CERM
20%
0.1uF
2
1
C107
CERM
20% 10V
402
0.1uF
2
1
R206
1/16W
5% MF
402
470
2
1
C114
20% CERM
10V 402
0.1uF
2
1
C154
10V CERM 402
20%
0.1uF
2
1
C91
10V
20% CERM
402
0.1uF
2
1
C168
CERM
0.1uF
20% 10V
402
2
1
C223
402
10V CERM
20%
0.1uF
2
1
C112
CERM
0.1uF
402
10V
20%
2
1
R241
402
MF
1/16W
5%
470
21
R60
5%
1/16W
MF
402
10K
21
R61
5%
1/16W
MF
402
470
21
R148
5%
402
1/16W
MF
10K
21
R98
5%
402
MF
1/16W
1K
C25
10uF
20%
6.3V CERM 805
2
1
C346
6.3V
20% CERM
805
10uF
C342
CERM
20%
6.3V
10uF
805
2
1
C8
20%
805
6.3V CERM
10uF
21
R120
402
MF
5%
1/16W
10K
21
R109
402
MF
5%
10K
1/16W
21
R106
402
MF
1/16W
1%
10
NO STUFF
2
1
C340
805
10V
20%
2.2uF
CERM
2
1
C12
10V 805
CERM
20%
2.2uF
21
R73
1/16W
MF
402
10K
5%
21
R72
MF
402
5%
1/16W
10K
21
R702
1/16W
1_5V_MAXBUS
603
MF
5%
0
21
R693
1_8V_MAXBUS
MF
5%
0
603
1/16W
+1_5V_SLEEP
+1_8V_SLEEP
2
1
R86
402
5%
470
1/16W MF
BBANG
21
R128
470
402
MF
1/16W
5%
2
1
C103
402
10V CERM
20%
0.1uF
2
1
C149
402
20% CERM
10V
0.1uF
2
1
C151
0.1uF
10V 402
CERM
20%
2
1
C202
0.1uF
10V CERM
20%
402
2
1
C111
402
10V CERM
20%
0.1uF
2
1
C110
10V 402
CERM
20%
0.1uF
2
1
C275
0.1uF
10V 402
CERM
20%
2
1
C257
10V
20%
402
0.1uF
CERM
2
1
C273
0.1uF
402
CERM
20% 10V
2
1
C41
0.1uF
20% CERM
402
10V
2
1
C272
10V CERM 402
0.1uF
20%
2
1
C46
10V CERM 402
20%
0.1uF
21
R65
10K
5%
1/16W
MF
402
21
R130
5%
1/16W
MF
402
10K
21
R79
5%
1/16W
MF
402
10K
21
R108
5% MF
10K
402
1/16W
2
1
C190
402
10V CERM
20%
0.1uF
2
1
C150
402
10V CERM
20%
0.1uF
2
1
C201
20%
0.1uF
402
10V CERM
2
1
C193
402
0.1uF
10V CERM
20%
2
1
C153
CERM
0.1uF
402
10V
20%
2
1
C344
20% CERM
10uF
6.3V 805
2
1
C189
20% CERM
10V 402
0.1uF
2
1
C105
402
CERM
20%
0.1uF
10V
2
1
C192
10V 402
20%
0.1uF
CERM
2
1
C47
0.1UF
20% 10V CERM 402
2
1
C188
0.1UF
20% 10V CERM 402
2
1
C169
0.1UF
20% 10V CERM 402
2
1
C170
0.1UF
20% 10V CERM 402
2
1
C155
0.1UF
20% 10V CERM 402
2
1
C139
0.1UF
20% 10V CERM 402
2
1
C92
0.1UF
20% 10V CERM 402
2
1
C106
0.1UF
20% 10V CERM 402
2
1
C195
20%
6.3V CERM 805
10UF
2
1
C347
10UF
20%
6.3V CERM 805
2
1
C258
805
CERM
6.3V
20%
10UF
2
1
C345
10UF
20%
6.3V CERM 805
2
1
C156
10UF
20%
6.3V CERM 805
2
1
C341
CERM
10UF
20%
6.3V 805
2
1
C225
6.3V CERM 805
20%
10UF
2
1
C343
10UF
20%
6.3V CERM 805
21
XW31
OMIT
SM
D3
K10
K8
J13
J11
J9J7H12
H10
M12
M10
M8
L13
L11
L9L7K14
K12
H8
C5
E9
F6
E6
E5
E7
F7
G6
L4
A5
F1
L1
A4
B9
C6
F11
E1
K6
A10
E10
B10
A2
F9
H5
E4
P4 G5
A9
D9
A7
D7
C7
C8
B8
G18
E18
L5K2J5H3F2D5C12
V14
V10
V7V4U16
U12
U2C2T9T6R16
R13
R4
P11
P8P2N6
M3
B4
C9
E8
B3
G8
D4
B6
D8
B2
H7
H4
G17
F3
E17
V15
V11
V8
V5
U17
U13
U3
D13
T10
T7
R17
R14
R5
P12
P9P3N7
M13D6M11
M9M7M4
L12
L10
L8
L6
K13
K11
C3
K9K3K7
J12
J10
J8
J6
H13
H11
H9
B5
E2
A11
D10
N1
P1
K1
G1
R3
M2
H2
B1
A3
J1
A12
B7D2
F8
G9
M1
A8
N2
G7
F5
H6
E3
C1
R1
G2
C10
D1
D11
L2
F10
B11
G10
C4
B12
W1
N5
G3
U1
V2
T1
N3
P5
M5
J3
N4
K4
J2
C11
W2
K5
R2
J4
V1
F4
T2
G4
L3
D12
H1
E11
U43
1.XX-1.33GHZ
APOLLO7-1.2V-1.05V
BGA
CRITICAL
61
4
2
3 5
U6
CRITICAL
FAN2558
SOT23-6
2
1
C283
603
6.3V
2.2UF
20%
CERM1
2
1
C909
402
CERM
6.3V
10%
1UF
21
R280
10
1%
1/16W
MF
402
2
1
R275
402
MF
1/16W
5%
47K
2
1
R276
0
5%
1/10W
MF
603
2
1
R282
63.4K
1% 1/16W MF 402
2
1
R283
52.3K
1% 1/16W MF 402
+3V_SLEEP
2
1
C137
402
10V
20% CERM
0.1uF
2
1
C136
20%
2.2uF
10V CERM 805
01
051-6598
5
44
CPU_AVDD_ADJ
CPU_AVDD_VOUT
VCORE_SHDN_L
CPU_AVDD_VIN CPU_AVDD_PG
CPU_SRWX_L
CPU_PULLUP
CPU_BUS_VSEL
CPU_PLL_CFG<0>
CPU_QREQ_L
CPU_SMI_L
MPIC_CPU_INT_L
CPU_AVDD
CPU_VCORE_SLEEP
CPU_SRESET_L CPU_HRESET_L
CPU_TEA_L
CPU_PULLDOWN
CPU_PULLUP
CPU_L1TSTCLK CPU_L2TSTCLK
JTAG_CPU_TRST_L CPU_LSSD_MODE
CPU_CLKOUT_SPN
CPU_EMODE1_L
CPU_PULLDOWN
SYSCLK_CPU
CPU_TA_L
CPU_QACK_L
CPU_ADDR<7>
CPU_AACK_L
CPU_CI_L
CPU_GBL_L CPU_WT_L
CPU_TSIZ<1> CPU_TSIZ<2>
CPU_TSIZ<0>
CPU_TT<4> CPU_TBST_L
CPU_TT<2> CPU_TT<3>
CPU_TT<1>
CPU_TT<0>
CPU_ADDR<30> CPU_ADDR<31>
CPU_ADDR<29>
CPU_ADDR<28>
CPU_ADDR<27>
CPU_ADDR<26>
CPU_ADDR<25>
CPU_ADDR<23> CPU_ADDR<24>
CPU_ADDR<22>
CPU_ADDR<20>
CPU_ADDR<19>
CPU_ADDR<17>
CPU_ADDR<15>
CPU_ADDR<13> CPU_ADDR<14>
CPU_ADDR<12>
CPU_ADDR<10> CPU_ADDR<11>
CPU_ADDR<8> CPU_ADDR<9>
CPU_ADDR<5> CPU_ADDR<6>
CPU_ADDR<4>
CPU_ADDR<3>
CPU_TS_L
CPU_BG_L
CPU_BR_L
CPU_SHD1_L CPU_HIT_L
CPU_SHD0_L
CPU_ARTRY_L
JTAG_CPU_TCK
JTAG_CPU_TDO_TP
CPU_EMODE0_L
CPU_PMONIN_L
CPU_ADDR<21>
CPU_ADDR<16>
CPU_PULLDOWN
CPU_CHKS_L
CPU_ADDR<0>
CPU_ADDR<2>
CPU_PLL_CFG<2>
CPU_ADDR<18>
CPU_CHKSTP_OUT_L
CPU_MCP_L
CPU_TBEN
JTAG_CPU_TMS
JTAG_CPU_TDI
CPU_DTI<2>
CPU_DTI<1>
CPU_DTI<0>
CPU_EDTI
CPU_DRDY_L
CPU_PLL_CFG<3>
CPU_DBG_L
CPU_PLL_CFG<1>
CPU_PLL_CFG<4>
CPU_ADDR<1>
CPU_VCORE_SLEEP
ADT7460_VCORE_MON
JTAG_CPU_TRST_L
JTAG_CPU_TCK
CPU_L1TSTCLK
MPIC_CPU_INT_L
JTAG_CPU_TDI
JTAG_CPU_TMS
CPU_SMI_L
CPU_HRESET_L
CPU_SRWX_L
CPU_L2TSTCLK
CPU_PULLDOWN
CPU_EDTI
CPU_PULLUP
CPU_PMONIN_L
CPU_CHKSTP_OUT_L
CPU_LSSD_MODE
CPU_SHD0_L
CPU_TBEN
CPU_SHD1_L
CPU_CHKS_L
MAXBUS_SLEEP
MAXBUS_SLEEP
CPU_EMODE1_L
CPU_MCP_L
CPU_SRESET_L
MAXBUS_SLEEP
38
38
38
34
34
34
23
23
23
39
39
16
16
16
38
39
38
39
15
15
15
34
23
39
39
39
39
34
39
39
39
39
23
8
8
8
36
30
14
6
39
7
36
23
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
23
36
36
36
36
36
39
8
23
23
36
36
36
36
36
36
6
23
23
14
23
23
30
7
39
8
7
7
39
7
34
5
5
7
7
8
5
5
38
5
5
5
8
5
5
5
5
5
5
5
5
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
5
8
5
8
5
39
7
5
8
8
5
5
8
8
7
8
5
5
5
5
5
8
8
8
5
8
7
8
7
7
8
5
25
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
D22
D3
D2
D1
D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21
D28
D27
D23 D24 D25 D26
D29
D32
D31
D30
D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44
D48
D47
D45 D46
D49
D51
D50
D52 D53 D54 D55
D58
D57
D56
D59
DP6
DP5
DP4
DP3
DP2
DP1
DP0
DP7
D63
D62
D61
D60
D0
(2 OF 3)
VDD
N/C_1
N/C_4
N/C_8
N/C_13
N/C_17
N/C_20
N/C_22 N/C_23
N/C_31
N/C_39
N/C_30
N/C_33
N/C_35 N/C_36
N/C_38
N/C_29
N/C_28
N/C_27
N/C_25
N/C_24
N/C_21
N/C_19
N/C_18
N/C_16
N/C_15
N/C_14
N/C_12
N/C_11
N/C_10
N/C_9
N/C_7
N/C_6
N/C_5
N/C_3
N/C_2
(3 OF 3)
N/C_26
N/C_32
N/C_34
N/C_37
SENSEVDD
GND
TEMP_CATHODE
TEMP_ANODE
SENSEGND
HPR*
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
.
SEE PAGE 22
BOOT BANGER - LMU PERORMS THIS FUNCTION IF NEEDED
MPC7447/BBANG
NC
NC NC NC NC
NC
NC
NC
NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC NC
NC
NC
NC
NC
NC
NC
NC
NC NC
NC
NC
NC
.
W6
N8
V3
M6
W9
T4
W4
T3
W13
V13
P14
T8
W8
R8
P6
U15
R7
U7
U8
U4
V17
W3
T17
T18
T16
W18
T15
W17
U18
W19
U19
T19
V19
R18
V18
R19
P17
W16
V6
P7
R6
W7
U5
T5
U6
W5
V9
U9
V16
W10
R9
U10
P10
N9
R10
T11
W11
U11
R11
T14
N10
N11
V12
W12
T12
R12
W14
U14
P13
T13
W15
R15
U43
1.XX-1.33GHZ
APOLLO7-1.2V-1.05V
BGA
P18
P16
N17
N15
M18
M16
M14
H19
H17
H14
G16
G11
F19
F17
F12
E16
E13
C13
B19
B17
A18
A16
A13
N19
N18
G13
N12
G12
N13
B15
A15
G14
F14
E14
D14
L19
K19
J19
L18
K18
J18
L17
K17
J17
L16
C14
K16
J16
H16
D19
C19
D18
C18
D17
C17
D16
B14
C16
L15
K15
J15
H15
G15
F15
E15
D15
C15
A14
A6
P19
P15
N16
N14
M19
M17
M15
L14
J14
H18
G19
F18
F16
F13
E19
E12
B18
B16
B13
A19
A17
U43
1.XX-1.33GHZ
APOLLO7-1.2V-1.05V
BGA
6
44
051-6598
01
CPU_VCORE_SLEEP
CPU_THERM_DM
CPU_DATA<63>
CPU_DATA<0>
CPU_DATA<62>
CPU_DATA<61>
CPU_DATA<60>
CPU_DATA<59>
CPU_DATA<58>
CPU_DATA<57>
CPU_DATA<56>
CPU_DATA<55>
CPU_DATA<54>
CPU_DATA<53>
CPU_DATA<52>
CPU_DATA<51>
CPU_DATA<50>
CPU_DATA<49>
CPU_DATA<48>
CPU_DATA<47>
CPU_DATA<46>
CPU_DATA<45>
CPU_DATA<44>
CPU_DATA<43>
CPU_DATA<42>
CPU_DATA<41>
CPU_DATA<40>
CPU_DATA<39>
CPU_DATA<38>
CPU_DATA<37>
CPU_DATA<36>
CPU_DATA<35>
CPU_DATA<34>
CPU_DATA<33>
CPU_DATA<32>
CPU_DATA<31>
CPU_DATA<30>
CPU_DATA<29>
CPU_DATA<28>
CPU_DATA<27>
CPU_DATA<26>
CPU_DATA<25>
CPU_DATA<24>
CPU_DATA<23>
CPU_DATA<22>
CPU_DATA<21>
CPU_DATA<20>
CPU_DATA<19>
CPU_DATA<18>
CPU_DATA<17>
CPU_DATA<16>
CPU_DATA<15>
CPU_DATA<14>
CPU_DATA<13>
CPU_DATA<12>
CPU_DATA<11>
CPU_DATA<10>
CPU_DATA<9>
CPU_DATA<8>
CPU_DATA<7>
CPU_DATA<6>
CPU_DATA<5>
CPU_DATA<4>
CPU_DATA<3>
CPU_DATA<2>
CPU_DATA<1>
CPU_THERM_DP
39 38 34
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
5
25
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
25
G
D
S
G
D
S
04
G
D
S
G
D
S
S
D
G
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
R01D
TRANSISTOR ON CPU_PLL_CFG<4> IS MET.
PLL DISABLE 1 X
STATE ENCODING CPU_PLL_STOP_OC CPU_VCORE_HI_OC
R01B R00C
1417
1167
1083
1000
9.0X
11.0X
1500
R10B
MAXBUS VSEL
1.5V INTERFACE
BUSTYPE SELECT
APOLLO ONLY SUPPORTS MAXBUS
(PROCESSOR)
CPU_BUS_VSEL
SIGNAL
(PROCESSOR)
CPU_EMODE0_L
CPU_HRESET_L
CPU_HRESET_INV
CPU_HRESET_L
TIED
HIGH
LOW
1.8V INTERFACE
1.5V INTERFACE
2.5V INTERFACE
60X BUS MODE
APPLICATION
MAX BUS MODE
DESKTOP HAD PROBLEM USING
1.8V INTERFACE
933
267 400 533
867
800
733
667
0 1011 0B 0 1001 09
5.0X
5.5X
333 500 667
9.5X
8.0X
7.5X
7.0X
6.5X
6.0X
4.0X
3.0X
2.0X
1.0X
0.0X
APOLLO 7
PULLUP TO ENSURE THAT Vgs OF PASS
R10E R00ER10A R00D
LOW SPEED 0 0
R10D R01E
CPU FREQUENCY CONFIGURATION
(MHZ)
PLL OFF
133MHZ
(Bus-to-Core)
MULTIPLIER
0 1111 0F
CPU_PLL_CFG
(AT BUS FREQUENCY)
CORE FREQUENCY
167MHZ
PLL BYPASS 0 0011 03
0 0100 04 0 1000 08 0 1010 0A
0 1101 0D 0 0101 05 0 0010 02
0 1100 0C
0 0001 01
1000 1067
1 0110 16
32004000
3733466728.0X
24.0X
1 1010 1A
0 0000 00
1 1000 18 1 1001 19
1833
1667 1750
1917
1467
1333 1400
1533
1 1100 1C 1 0001 11 1 1101 1D
1 0101 15 0 1110 0E
1 0000 10 1 0010 12 1 0011 13
1 1011 1B 1 1111 1F
1 0100 14
1667
1600
2667
2400
2267
1800
1733
2133
2000
18672333 2500 2667
2083
2000
3333
3000
2833
2250
2167
3500 2800
16.0X
15.0X
14.0X
10.0X
10.5X
12.0X
11.5X
12.5X
13.0X
13.5X
17.0X
18.0X
20.0X
21.0X
1 0111 17
1200
1133
0 0110 06
1583 1267
0 0111 07
1 1110 1E
CPU CONFIGURATION
4 0123 E ABCD HEX
R10E, R01E, OR PULLUP STUFFED
STUFF PASS TRANSISTOR ONLY IF
HIGH SPEED 0 1
CPU PLL CONFIG CIRCUITRY
R00B R10C
INVERTED HRESET_L
R00A R01C
NEED TO CHARACTERIZE
INVERTER TO INVERT HRESET_L
CPU CONFIGURATION
1250 1333
833 917
8.5X
+5V_SLEEP NOW REQUIRED FOR PLL_STOP_L
R01A
2
1
R23
0
MF 402
5% 1/16W
2
1
R16
NO STUFF
5%
402
MF
1/16W
0
2
1
R9
1/16W
10K
5% MF
402
2
1
R10
1/16W
10K
402
MF
5%
2
1
R11
10K
1/16W
5% MF
402
2
1
R12
402
10K
MF
1/16W
5%
2
1
R3
402
5%
1/16W
MF
47K
2
1
R48
1/16W 402
10K
5% MF
2
1
R33
402
82K
MF
1/16W
5%
2
1
R18
0
5% 1/16W MF 402
2
1
R17
NO STUFF
5%
0
1/16W MF 402
2
1
R2
10K
5% 1/16W MF 402
4
5
3
Q2
2N7002DW
SOT-363
1
2
6
Q2
2N7002DW
SOT-363
4
5
3
2
U1
SC70-5
SN74AUC1G04
1_5V_MAXBUS
CRITICAL
2
1
R27
NO STUFF
402
MF
1/16W
5%
0
1
2
6
Q1
2N7002DW
SOT-363
4
5
3
Q1
NO STUFF
2N7002DW
SOT-363
+5V_SLEEP
1 2
R4
1/16W
MF
5%
22
402
1_5V_MAXBUS
1 2
R149
22
1/16W
MF
5%
402
2
1
R5
10
MF
5%
1/16W
402
1_8V_MAXBUS
2
1
3
Q3
2N7002
SM
2
3
1
Q4
SM
2N3904
21
R47
249K
402
MF
1/16W
1%
2
1
R19
NO STUFF
5% 1/16W MF 402
0
+3V_SLEEP
2
1
R20
1/16W
NO STUFF
402
MF
5%
0
2
1
R21
MF 402
5%
0
NO STUFF
1/16W
2
1
R22
1/16W
NO STUFF
402
MF
5%
0
2
1
R24
MF
1/16W
0
402
5%
NO STUFF
2
1
R25
1/16W MF
5%
402
0
NO STUFF
2
1
R26
0
5% 1/16W MF 402
NO STUFF
2
1
R14
402
MF
5%
0
1/16W
2
1
R13
402
5%
NO STUFF
0
MF
1/16W
2
1
R15
NO STUFF
402
MF
1/16W
5%
0
44
7
051-6598
01
CPU_PLL_CFG<0> CPU_PLL_CFG<1>
CPU_PLL_FS10
CPU_PLL_FS00
MAXBUS_SLEEP
CPU_VCORE_HI_OC
CPU_PLL_FS01
CPU_PLL_CFG<2> CPU_PLL_CFG<3>
CPU_PLL_STOP_BASE
CPU_PLL_CFGEXT CPU_PLL_CFG<4>
CPU_PLL_STOP_OC
PLL_STOP_L
CPU_PLL_STOP_OC
CPU_BUS_VSEL
MAXBUS_SLEEP
CPU_HRESET_INV
CPU_HRESET_L
CPU_HRESET_L CPU_EMODE0_L
PLL_STOP_L
38
38
34
34
23
23
16
16
15
15
39
39
8
8
23
23
7
34
30
30
7
7
7
5
5
5
30
5
5
5
7
7
7
5
5
5
5 5
7
(PLL6)
VSSA_7
(PLL6)
VDD15A_7
D_42
D_41
D_40
D_39
D_38
D_44
D_43
D_45 D_46 D_47 D_48
D_52
D_51
D_50
D_49
D_53
D_55
D_54
D_56 D_57 D_58
D_60
D_59
D_62
D_61
D_63
DBG
DRDY
DTI_0
TEA
TA
DTI_2
DTI_1
D_1
D_0
D_2
D_6
D_5
D_4
D_3
D_7
D_11
D_10
D_9
D_8
D_12
D_14
D_13
D_15 D_16 D_17
D_22
D_21
D_20
D_19
D_18
D_23 D_24 D_25 D_26 D_27
D_32
D_31
D_30
D_29
D_28
D_34
D_33
D_35 D_36 D_37
BR
(1 OF 9)
MAXBUS
INTERFACE
TS
BG
A_0 A_1 A_2 A_3 A_4 A_5
A_9
A_6 A_7 A_8
A_10
A_14
A_13
A_12
A_11
A_20
A_16 A_17 A_18 A_19
A_15
A_27
A_22
A_21
A_30
A_29
A_28
A_26
A_25
A_24
A_23
TT_2
TT_1
TT_0
A_31
TBST TSIZ_0 TSIZ_1 TSIZ_2
CI GBL
TT_4
AACK
QREQ
ARTRY
TT_3
WT
HIT
ANALYZER_CLK
SUSPENDACK
SUSPENDREQ
QACK
STOPCPUCLK
CPU_FB_OUT
CPU_FB_IN
CPU_CLK
TBEN
ACS_REF
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
PCI1 Source Clock
1: PLL4
BIT 40 TO 47
InternalSpreadEn
BIT 48 TO 55
0: PLL5
0: Inactive
1: Active low
Spare
Spare
1: Active
INTREPID BOOT STRAPS
MODE A (2.5X) IS FOR STATIC OPERATION
100: 83.20MHZ
011: 99.84MHZ (1.5X)
010: 133.12MHZ (2.0X)
PCI0 Source Clock
0: PLL5 (NO SPREAD)
BIT1
000: 166.4MHZ (2.5X) 001: 149.76MHZ
1: PLL4
0: PLL5 (NO SPREAD)
NO BUS KEEPER - PU
INPUT
IT CANNOT BE CHANGED BY SOFTWARE
IF A STRAP IS NOT LISTED, THEN
CHANGED BY SOFTWARE:
THE FOLLOWING STRAP BITS CAN BE
6/ D33 - ANALYZERCLK_EN_H - IMMEDIATE EFFECT
5/ D42 - PLL4MODESEL_NXT<2> - SLEEP/WAKE CYCLE REQUIRED
4/ D43 - PLL4MODESEL_NXT<1> - SLEEP/WAKE CYCLE REQUIRED
3/ D44 - PLL4MODESEL_NXT<0> - SLEEP/WAKE CYCLE REQUIRED
2/ D46 - SELPCI1SPREADCLK - SLEEP/WAKE CYCLE REQUIRED
1/ D47 - SELAGPSPREADCLK - SLEEP/WAKE CYCLE REQUIRED
Intrepid MaxBus
NO BUS KEEPER - PU
Spare
BIT 32 TO 39
Spare
ExtPLL_SDwn_Pol
0: Active high
0: Active high
1: Active low
DDR_TPDEn_Pol
0: Inactive
AnalyzerClk_En_h
0: Inactive
Spare
Spare
TI 1394b workaround
1: TI PHY workaround
0: Normal 1394b
1: Active
BUF_REF_CLK_OUTEnable_h
INTREPID OUTPUTS HIGH BY DEFAULT
1: Active
SelPLL4ExtSrc
1: External source
PLL4MODESEL_NXT[2:0]
MaxBus output impedance 111: 28.6 ohm 011: 33.3 ohm
110: 66.6 ohm
000: 200 ohm
100: 200 ohm
010: 100 ohm
101: 40 ohm 001: 50 ohm
BIT2 BIT0
BIT0BIT1BIT2
Vin = Intrepid Vcore (1.5V) Vout = MaxBus rail (1.8V)
NO BUS KEEPER
NO BUS KEEPER
NO BUS KEEPER - PU INPUT - PU
NO BUS KEEPER - PU
NO BUS KEEPER - PU
NO BUS KEEPER - PU
INPUT - PD
INPUT - PU
NO BUS KEEPER - ?
NO BUS KEEPER - ? NO BUS KEEPER - ? NO BUS KEEPER - ?
SHORT = 1" SHORTER THAN MATCHED LENGTH
LONG = 1" LONGER THAN MATCHED LENGTH
INTREPID BOOT STRAPS
BIT 56 TO 63
0: Max Bus (G4)
1: 60x bus (G3)
Processor Bus Mode
0: REQ/GNT
1: GPIOs
0: REQ/GNT
1: GPIOs
0: REQ/GNT
1: GPIOs
Spare
PCI1_REQ0_L / PCI1_GNT0_L
PCI1_REQ2_L / PCI1_GNT2_L
PCI1_REQ1_L / PCI1_GNT1_L
FireWire PHY interface
1: B-mode interface
0: Legacy interface
MAXBUS PULL-UPS
FB BUFFER HAS 50 OHM OUTPUT IMPEDANCE
MODE C (2.0X) IS FOR CLOCK SLEW OPERATION
Spare
Spare
Spare
Spare
1: TDI output
0: TDI input (JTAG)
DDR_TPDModeEnable_h
2
1
R137
402
MF
1/16W
1%
1K
2
1
C308
402
CERM
6.3V
20%
0.22UF
21
R227
4.7
5%
1/16W
MF
402
21
R144
0
402
MF
1/16W
5%
72
RP24
10K
5%
1/16W
SM1
2 1
R167
0
402
MF
1/16W
5%
2
1
R197
MF
1/16W
1%
402
511
2
1
R178
NO STUFF
5%
1/16W
MF
402
10K
2
1
R179
10K
402
MF
1/16W
5%
NO STUFF
2
1
R651
NO STUFF
10K
402
MF
1/16W
5%
2
1
R166
NO STUFF
5%
1/16W
MF
402
10K
2
1
R153
10K
402
MF
1/16W
5%
2
1
R123
NO STUFF
5%
1/16W
MF
402
10K
2
1
R135
NO STUFF
10K
402
MF
1/16W
5%
2
1
R674
5%
1/16W
MF
402
10K
2
1
R143
10K
402
MF
1/16W
5%
2
1
R673
5% MF
402
1/16W
10K
2
1
R664
5%
1/16W
MF
402
10K
2
1
R657
NO STUFF
10K
402
MF
5%
1/16W
2
1
R639
5%
402
10K
MF
1/16W
2
1
R643
10K
402
MF
5%
1/16W
2
1
R642
10K
402
MF
1/16W
5%
NO STUFF
2
1
R136
10K
402
MF
5%
1/16W
2
1
R165
MF
402
1/16W
5%
10K
NO_SSCG
2
1
R177
NO_SSCG
10K
402
1/16W
5% MF
2
1
R152
402
MF
1/16W
5%
NO_SSCG
10K
2
1
R184
5%
1/16W
MF
402
NO STUFF
10K
2
1
R134
402
MF
1/16W
5%
10K
SSCG
2
1
R164
NO STUFF
10K
402
MF
1/16W
5%
2
1
R142
10K
402
MF
1/16W
5%
NO STUFF
2
1
R122
10K
402
MF
1/16W
5%
NO STUFF
2
1
R666
5% MF
402
10K
SSCG
1/16W
2
1
R658
MF
5%
10K
1/16W
SSCG
402
2
1
R675
SSCG
10K
402
MF
1/16W
5%
2
1
R683
5% MF
402
10K
1/16W
2
1
R644
402
MF
1/16W
5%
10K
NO_SSCG
2
1
R665
5%
1/16W
MF
402
10K
2
1
R652
10K
402
MF
1/16W
5%
2
1
R640
10K
402
MF
1/16W
5%
2
1
R176
10K
402
MF
1/16W
5%
NO STUFF
2
1
R141
5%
1/16W
MF
402
10K
NO STUFF
2
1
R183
10K
402
MF
1/16W
5%
2
1
R162
10K
402
MF
1/16W
5%
NO STUFF
2
1
R151
5%
1/16W
MF
402
10K
NO STUFF
2
1
R163
10K
402
MF
1/16W
5%
2
1
R121
5%
1/16W
MF
402
10K
SSCG
2
1
R676
10K
402
MF
1/16W
5%
2
1
R684
NO STUFF
5%
1/16W
MF
402
10K
2
1
R653
5%
1/16W
MF
402
10K
2
1
R667
10K
402
MF
1/16W
5%
2
1
R659
5%
1/16W
MF
402
10K
2
1
R668
402
MF
1/16W
5%
NO STUFF
10K
2
1
R641
NO_SSCG
5% MF
402
10K
1/16W
2
1
R133
10K
402
MF
1/16W
5%
SSCG
2
1
R645
MF
1/16W
NO_SSCG
10K
5%
402
2
1
R182
5%
1/16W
MF
402
10K
NO STUFF
2
1
R174
10K
402
MF
1/16W
5%
2
1
R150
5%
1/16W
MF
402
10K
NO STUFF
2
1
R131
10K
402
MF
1/16W
5%
NO STUFF
2
1
R132
5%
1/16W
MF
402
10K
NO STUFF
2
1
R175
NO STUFF
10K
402
MF
1/16W
5%
2
1
R161
NO STUFF
10K
402
MF
1/16W
5%
2
1
R140
5%
1/16W
MF
402
10K
NO STUFF
2
1
R685
10K
402
MF
1/16W
5%
2
1
R660
10K
402
MF
1/16W
5%
2
1
R678
NO STUFF
5%
1/16W
MF
402
10K
2
1
R647
5%
1/16W
MF
402
10K
2
1
R646
10K
402
MF
1/16W
5%
2
1
R677
5%
1/16W
MF
402
10K
2
1
R669
10K
402
MF
1/16W
5%
2
1
R654
5%
1/16W
MF
402
10K
D28
H25
H26
J25
D27
B28
G25
E25
D26
H24
G24
B27
E28
A28
A31
E27
AK9 AM8
AH9
A32
G27
B31
A29
D11
E12
A8
G20
B20
G19
E19
A9
D19
A20
J19
B19
H19
A19
A18
D18
B18
E18
B8
B17
A17
G18
D17
H18
J18
A16
E17
B16
A15
B9
H17
B15
G17
E16
D16
A13
A14
D15
J16
E15
H11
G16
A12
B14
D14
H15
B13
G15
B12
E14
H14
E11
G14
A11
D13
B11
G13
E13
D12
A10
J13
B10
G12
D10
B30
D29
K25
G28
A30H16
J24
J15
G26
E29 E26
E23
A25
D23
A26
B26
G23
A21
D20
E24
B21
E20
A22
H21
B22
H20
A23
D21
A24
E21
A27
G21
J21
E22
B23
B24
D22
G22
H22
B25
J22
D25
D24
H23
G8
H13
B29
U45
INTREPID-REV2.1
BGA
CRITICAL
2
1
R225
402
MF
1/16W
5%
0
NO STUFF
21
R215
0
5%
1/16W
MF
402
2
1
R208
402
MF
1/16W
5%
0
21
R207
NO STUFF
0
5%
1/16W
MF
402
21
R226
402
MF
1/16W
5%
0
21
R196
NO STUFF
402
MF
1/16W
5%
0
63
RP24
1/16W
5%
10K
SM1
81
RP23
10K
5%
1/16W
SM1
54
RP23
SM1
1/16W
5%
10K
72
RP23
SM1
10K
5%
1/16W
72
RP21
1/16W
5%
10K
SM1
81
RP21
SM1
10K
5%
1/16W
63
RP21
SM1
10K
1/16W
5%
54
RP21
10K
5%
1/16W
SM1
54
RP24
1/16W
5%
10K
SM1
63
RP23
SM1
10K
1/16W
5%
01
051-6598
448
INT_CPUFB_OUT_SHORT
INT_CPUFB_OUT
SYSCLK_CPU
SYSCLK_CPU_UF
INT_CPUFB_IN
CPU_QREQ_L
MAXBUS_SLEEP
CPU_BG_L
CPU_DBG_L
CPU_TEA_L
CPU_AACK_L
CPU_HIT_L
CPU_DRDY_L
CPU_ARTRY_L
CPU_BR_L
CPU_TS_L
CPU_TA_L
CPU_DATA<56> CPU_DATA<57> CPU_DATA<58>
MAXBUS_SLEEP
CPU_DATA<59> CPU_DATA<60> CPU_DATA<61> CPU_DATA<62> CPU_DATA<63>
INT_CPUFB_LONG
INT_CPUFB_IN_NORM
INT_CPUFB_OUT_NORM
INT_CPUFB_IN
CPU_DATA<32>
CPU_DATA<48> CPU_DATA<49> CPU_DATA<50> CPU_DATA<51>
CPU_DATA<53>
CPU_DATA<40> CPU_DATA<41>
CPU_DATA<55>
CPU_DATA<33> CPU_DATA<34> CPU_DATA<35> CPU_DATA<36> CPU_DATA<37>
CPU_DATA<39>
MAXBUS_SLEEP
+1_5V_INTREPID_PLL
CPU_TEA_L
CPU_TA_L
CPU_DTI<2>
CPU_DTI<1>
CPU_DTI<0>
CPU_DRDY_L
CPU_DBG_L
CPU_DATA<63>
CPU_DATA<61> CPU_DATA<62>
CPU_DATA<60>
CPU_DATA<58> CPU_DATA<59>
CPU_DATA<57>
CPU_DATA<56>
CPU_DATA<55>
CPU_DATA<53> CPU_DATA<54>
CPU_DATA<52>
CPU_DATA<51>
CPU_DATA<48>
CPU_DATA<50>
CPU_DATA<49>
CPU_DATA<47>
CPU_DATA<46>
CPU_DATA<44> CPU_DATA<45>
CPU_DATA<43>
CPU_DATA<41> CPU_DATA<42>
CPU_DATA<40>
CPU_DATA<39>
CPU_DATA<38>
CPU_DATA<37>
CPU_DATA<36>
CPU_DATA<35>
CPU_DATA<34>
CPU_DATA<33>
CPU_DATA<32>
CPU_DATA<30> CPU_DATA<31>
CPU_DATA<29>
CPU_DATA<28>
CPU_DATA<27>
CPU_DATA<25> CPU_DATA<26>
CPU_DATA<24>
CPU_DATA<23>
CPU_DATA<22>
CPU_DATA<20> CPU_DATA<21>
CPU_DATA<19>
CPU_DATA<17> CPU_DATA<18>
CPU_DATA<16>
CPU_DATA<15>
CPU_DATA<14>
CPU_DATA<12> CPU_DATA<13>
CPU_DATA<11>
CPU_DATA<10>
CPU_DATA<7>
CPU_DATA<9>
CPU_DATA<8>
CPU_DATA<6>
CPU_DATA<5>
CPU_DATA<2>
CPU_DATA<4>
CPU_DATA<3>
CPU_DATA<0> CPU_DATA<1>
CPU_BR_L CPU_BG_L
CPU_TS_L
CPU_ADDR<1>
CPU_ADDR<0>
CPU_ADDR<2> CPU_ADDR<3> CPU_ADDR<4> CPU_ADDR<5> CPU_ADDR<6> CPU_ADDR<7> CPU_ADDR<8> CPU_ADDR<9> CPU_ADDR<10>
CPU_ADDR<12>
CPU_ADDR<11>
CPU_ADDR<14>
CPU_ADDR<13>
CPU_ADDR<15> CPU_ADDR<16> CPU_ADDR<17>
CPU_ADDR<19>
CPU_ADDR<18>
CPU_ADDR<20>
CPU_ADDR<22>
CPU_ADDR<21>
CPU_ADDR<24>
CPU_ADDR<23>
CPU_ADDR<25>
CPU_ADDR<28>
CPU_ADDR<30>
CPU_TBST_L CPU_TSIZ<0>
CPU_TSIZ<2>
CPU_TSIZ<1>
CPU_TT<1>
CPU_TT<0>
CPU_TT<2>
CPU_TT<4>
CPU_TT<3>
CPU_WT_L
CPU_AACK_L
CPU_HIT_L
CPU_ARTRY_L
CPU_QREQ_L
CPU_QACK_L INT_SUSPEND_REQ_L INT_SUSPEND_ACK_L
INT_CPUFB_OUT SYSCLK_LA_TP
CPU_CLK_EN
CPU_TBEN
INTREPID_ACS_REF
+1_5V_INTREPID_PLL7
CPU_GBL_L
CPU_DATA<44>
CPU_DATA<42>
CPU_DATA<38>
CPU_ADDR<29>
CPU_ADDR<31>
CPU_CI_L
MAXBUS_SLEEP
CPU_DATA<52>
CPU_DATA<54>
MAXBUS_SLEEP
CPU_DATA<46>
CPU_DATA<45>
CPU_DATA<47>
CPU_ADDR<27>
CPU_ADDR<26>
CPU_DATA<43>
38
38
38
38
38
34
34
34
34
34
23
23
23
23
23
16
16
16
16
16
15
15
15
15
15
36
8
36
36
36
36
36
36
36
36
36
36
36
36
36
8
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
8
38
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
8
36
36
8
36
36
36
36
36
36
36
8
7
8
8
8
8
8
8
8
8
8
8
8
8
8
7
8
8
8
8
8
36
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
7
14
8
8
36
36
36
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
8
8
8
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
8
8
8
8
36
36
36
8
8
8
36
36
36
7
8
8
7
8
8
8
36
36
8
36
8
5
36
8
5
5
5
5
5
5
5
5
5
5
5
5
6
6
6
5
6
6
6
6
6
36
36
36
8
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
5
12
5
5
5
5
5
5
5
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
30
30
8
30
5
38
5
6
6
6
5
5
5
5
6
6
5
6
6
6
5
5
6
A0 A1
A6
A2 A3 A4 A5
A9
A8
A7
A10 A11 A12 A13 A14 A15 A16
A20
A17 A18 A19
CE OE WE WP PWD
GND
DQ0 DQ1
DQ6
DQ5
DQ2 DQ3 DQ4
DQ7
VPP VCC
FEPR-1MX8
(2 OF 9)
DDR_VREF_1
DDR_VREF_0
DDR_DATA_0 DDR_DATA_1 DDR_DATA_2 DDR_DATA_3 DDR_DATA_4 DDR_DATA_5 DDR_DATA_6 DDR_DATA_7 DDR_DATA_8 DDR_DATA_9 DDR_DATA_10 DDR_DATA_11 DDR_DATA_12 DDR_DATA_13 DDR_DATA_14 DDR_DATA_15 DDR_DATA_16 DDR_DATA_17 DDR_DATA_18 DDR_DATA_19 DDR_DATA_20 DDR_DATA_21
DDR_DATA_25 DDR_DATA_26 DDR_DATA_27 DDR_DATA_28 DDR_DATA_29 DDR_DATA_30
DDR_DATA_33 DDR_DATA_34 DDR_DATA_35 DDR_DATA_36 DDR_DATA_37 DDR_DATA_38 DDR_DATA_39 DDR_DATA_40 DDR_DATA_41 DDR_DATA_42 DDR_DATA_43 DDR_DATA_44 DDR_DATA_45 DDR_DATA_46 DDR_DATA_47 DDR_DATA_48 DDR_DATA_49 DDR_DATA_50 DDR_DATA_51 DDR_DATA_52 DDR_DATA_53 DDR_DATA_54 DDR_DATA_55 DDR_DATA_56 DDR_DATA_57 DDR_DATA_58 DDR_DATA_59 DDR_DATA_60 DDR_DATA_61 DDR_DATA_62 DDR_DATA_63
DDR_DATA_22 DDR_DATA_23 DDR_DATA_24
DDR_DATA_31 DDR_DATA_32
DDR_BA_0 DDR_BA_1
DDRCS_3
DDRCS_2
DDRCS_1
DDRCS_0
DDR_DQS_7
DDR_DQS_6
DDR_DQS_5
DDR_DQS_4
DDR_DQS_3
DDR_DQS_2
DDR_DQS_1
DDR_DQS_0
DDR_DM_7
DDR_DM_6
DDR_DM_5
DDR_DM_4
DDR_DM_3
DDR_DM_2
DDR_DM_1
DDR_DM_0
DDRRAS DDRCAS
DDRWE DDRCKE0 DDRCKE1 DDRCKE2 DDRCKE3
DDR_MCLK_0_P DDR_MCLK_0_N DDR_MCLK_1_P DDR_MCLK_1_N DDR_MCLK_2_P DDR_MCLK_2_N DDR_MCLK_3_P DDR_MCLK_3_N DDR_MCLK_4_P DDR_MCLK_4_N DDR_MCLK_5_P DDR_MCLK_5_N
DDR_REF
DDR_SELHI_0 DDR_SELHI_1 DDR_SELLO_0 DDR_SELLO_1
MEMORY
DDR
INTERFACE
DDR_A_10 DDR_A_11 DDR_A_12
DDR_A_9
DDR_A_8
DDR_A_7
DDR_A_6
DDR_A_5
DDR_A_4
DDR_A_3
DDR_A_2
DDR_A_1
DDR_A_0
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
OVERRIDE ROM MODULE
PULL-DOWN RESISTORS TO ENSURE CKE STAYS LOW AFTER INTREPID
2.5V I/O SHUTS OFF
1MB BOOT ROM
INTERCEPTS ROM CHIP SELECT
MEM_VREF
’2’ & ’3’ GO TO SLOT B
’0’ & ’1’ GO TO SLOT A
’2’ & ’3’ GO TO SLOT B
’0’ & ’1’ GO TO SLOT A
’1’S ARE SAME POLARITY (ACTIVE-HI)
’0’S ARE SAME POLARITY (ACTIVE-LO)
CNTL
BA
ADDR
CKE
CS
PINS ARE SWAPABLE FOR RPAKS
CLOCKS
INT - DDR/BOOTROM
SERIES RESISTORS FOR CLOCK/CONTROL SIGNALS
2
1
R387
402
MF
1/16W
10K
5%
21
R238
402
MF
1/16W
5%
22
2
1
R199
402
MF
1/16W
1%
1K
2
1
R198
402
MF
1/16W
1%
10K
2
1
C245
402
CERM
10V
20%
0.1UF
2
1
R191
1%
1/16W
MF
402
10K
12
9
11 3130
10
24
3923
35
34
33
32
28
27
26
25
22
7
8
14
15
16
17
18
38
19
37
13
40
1
2
3
4
5
6
36
20
21
U17
OMIT
3.3V
TSOP
2
1
C460
10V CERM 805
20%
2.2UF
2
1
C470
20% 10V CERM 402
0.1UF
2
1
C479
20% 10V CERM 402
0.1UF
2
1
R386
402
MF
1/16W
10K
5%
+3V_MAIN
T22
Y22
T32
N30
AE29
AB32
AA22
W35 W36
V33 V32
W32 W33
Y30 W30
Y35 Y36
Y32 Y33
L32
N29
P32
V30
AB30
AD32
AH31
AJ31
L33
N32
T33
T35
AC35
AD33
AH33
AJ33
AG35
AG33
AJ36
K35
K36
J36
K33
AJ35
K32
J35
J33
J32
M30
N33
L36
M33
M35
L35
AJ32
M36
N35
R32
R33
R35
R36
P36
P35
R30
P33
AK36
T36
U35
U36
T30
V35
U32
U33
V36
AB33
AA32
AK35
AC36
AB35
AB36
AA33
AA35
AA36
AD35
AD36
AE33
AE35
AK31
AE36
AF36
AF35
AE32
AG31
AG32
AH32
AH36
AG36
AH35
AK33
AK32
M29
L30
H36
D36
G32
E36
E35
F35
F36
G36
D35
H33
G33
G35
H35
K30
L29
AL33
AL35
AN36
AN34
AL36
AM36
AM35
AN35
H32
U45
INTREPID-REV2.1
CRITICAL
BGA
2
1
R338
5%
10K
1/16W
MF
402
21
R357
1K
5%
1/16W
MF
402
54
RP33
SM1
1/16W
5%
22
63
RP33
1/16W
5%
22
SM1
81
RP34
SM1
1/16W
5%
22
72
RP34
1/16W
5%
22
SM1
72
RP33
22
5%
1/16W
SM1
63
RP34
22
5%
1/16W
SM1
21
R250
22
5%
1/16W
MF
402
81
RP33
22
5%
1/16W
SM1
54
RP34
22
5%
1/16W
SM1
81
RP36
22
5%
1/16W
SM1
54
RP35
22
5%
1/16W
SM1
63
RP36
22
5%
1/16W
SM1
72
RP36
SM1
1/16W
5%
22
54
RP36
SM1
1/16W
5%
22
72
RP35
22
5%
1/16W
SM1
81
RP35
SM1
1/16W
5%
22
63
RP35
SM1
1/16W
5%
22
81
RP31
22
5%
1/16W
SM1
81
RP25
22
5%
1/16W
SM1
72
RP25
22
5%
1/16W
SM1
63
RP25
SM1
1/16W
5%
22
54
RP25
22
5%
1/16W
SM1
81
RP30
SM1
1/16W
5%
22
72
RP30
SM1
1/16W
5%
22
63
RP31
SM1
1/16W
5%
22
54
RP30
SM1
1/16W
5%
22
54
RP31
SM1
1/16W
5%
22
72
RP31
SM1
1/16W
5%
22
54
RP26
SM1
1/16W
5%
22
63
RP30
22
5%
1/16W
SM1
81
RP26
22
5%
1/16W
SM1
72
RP26
22
5%
1/16W
SM1
63
RP26
22
5%
1/16W
SM1
+3V_MAIN
2
1
R500
402
MF
1/16W
10K
5%
2
1
R439
5%
10K
1/16W
MF
402
2
1
R409
402
MF
1/16W
10K
5%
9 44
051-6598
01
341S1464
BOOTROM,PROTO,Q41A
CRITICAL
1
U17
?
RAM_CKE<1>
RAM_CKE<2>
RAM_CKE<3>
+2_5V_INTREPID
MEM_RAS_L RAM_RAS_L
RAM_WE_LMEM_WE_L
MEM_CAS_L RAM_CAS_L
RAM_BA<1>MEM_BA<1>
RAM_BA<0>MEM_BA<0>
RAM_ADDR<11>MEM_ADDR<11>
RAM_ADDR<9>MEM_ADDR<9>
RAM_ADDR<12>MEM_ADDR<12>
RAM_ADDR<10>MEM_ADDR<10>
RAM_ADDR<8>MEM_ADDR<8>
RAM_ADDR<7>MEM_ADDR<7>
RAM_ADDR<5>MEM_ADDR<5>
RAM_ADDR<3>MEM_ADDR<3>
RAM_ADDR<1>MEM_ADDR<1>
RAM_ADDR<6>MEM_ADDR<6>
RAM_ADDR<4>MEM_ADDR<4>
RAM_ADDR<2>MEM_ADDR<2>
RAM_ADDR<0>MEM_ADDR<0>
RAM_CKE<3>MEM_CKE<3>
RAM_CKE<1>MEM_CKE<1>
RAM_CS_L<3>MEM_CS_L<3>
RAM_CKE<2>MEM_CKE<2>
RAM_CKE<0>MEM_CKE<0>
RAM_CS_L<2>MEM_CS_L<2>
RAM_CS_L<1>MEM_CS_L<1>
SYSCLK_DDRCLK_B0_L
SYSCLK_DDRCLK_B0_L_UF
SYSCLK_DDRCLK_B1_L
SYSCLK_DDRCLK_B1_L_UF
SYSCLK_DDRCLK_A0_L
SYSCLK_DDRCLK_A0_L_UF
RAM_CS_L<0>MEM_CS_L<0>
SYSCLK_DDRCLK_B0
SYSCLK_DDRCLK_B0_UF
SYSCLK_DDRCLK_B1
SYSCLK_DDRCLK_B1_UF
SYSCLK_DDRCLK_A1_L
SYSCLK_DDRCLK_A1_L_UF
SYSCLK_DDRCLK_A0
SYSCLK_DDRCLK_A0_UF
SYSCLK_DDRCLK_A1
SYSCLK_DDRCLK_A1_UF
INT_MEM_VREF
MEM_ADDR<12>
MEM_ADDR<11>
MEM_ADDR<10>
MEM_ADDR<9>
MEM_ADDR<8>
MEM_ADDR<7>
MEM_ADDR<6>
MEM_ADDR<5>
MEM_ADDR<4>
MEM_ADDR<3>
MEM_ADDR<2>
MEM_ADDR<1>
MEM_ADDR<0>
MEM_MUXSEL_L<1>
MEM_MUXSEL_H<1>
MEM_MUXSEL_H<0>
MEM_CKE<3>
MEM_CKE<2>
MEM_CKE<1>
MEM_CKE<0>
MEM_WE_L
MEM_CAS_L
MEM_RAS_L
MEM_DQM<7>
MEM_DQM<6>
MEM_DQM<5>
MEM_DQM<4>
MEM_DQM<3>
MEM_DQM<1>
MEM_DQM<0>
MEM_DQM<2>
MEM_DQS<7>
MEM_DQS<6>
MEM_DQS<5>
MEM_DQS<4>
MEM_DQS<3>
MEM_DQS<2>
MEM_DQS<1>
MEM_DQS<0>
MEM_CS_L<2>
MEM_CS_L<1>
MEM_CS_L<0>
MEM_CS_L<3>
MEM_BA<1>
MEM_BA<0>
MEM_DATA<54>
MEM_DATA<31>
MEM_DATA<29>
MEM_DATA<25>
MEM_DATA<24>
MEM_DATA<15>
MEM_DATA<63>
MEM_DATA<62>
MEM_DATA<61>
MEM_DATA<60>
MEM_DATA<59>
MEM_DATA<58>
MEM_DATA<57>
MEM_DATA<56>
MEM_DATA<55>
MEM_DATA<53>
MEM_DATA<52>
MEM_DATA<51>
MEM_DATA<50>
MEM_DATA<49>
MEM_DATA<48>
MEM_DATA<47>
MEM_DATA<46>
MEM_DATA<45>
MEM_DATA<44>
MEM_DATA<43>
MEM_DATA<42>
MEM_DATA<41>
MEM_DATA<40>
MEM_DATA<39>
MEM_DATA<38>
MEM_DATA<37>
MEM_DATA<36>
MEM_DATA<35>
MEM_DATA<34>
MEM_DATA<33>
MEM_DATA<32>
MEM_DATA<30>
MEM_DATA<28>
MEM_DATA<27>
MEM_DATA<26>
MEM_DATA<23>
MEM_DATA<22>
MEM_DATA<21>
MEM_DATA<20>
MEM_DATA<19>
MEM_DATA<18>
MEM_DATA<17>
MEM_DATA<16>
MEM_DATA<14>
MEM_DATA<13>
MEM_DATA<12>
MEM_DATA<11>
MEM_DATA<10>
MEM_DATA<9>
MEM_DATA<8>
MEM_DATA<7>
MEM_DATA<6>
MEM_DATA<5>
MEM_DATA<4>
MEM_DATA<3>
MEM_DATA<2>
MEM_DATA<1>
MEM_DATA<0>
MEM_MUXSEL_L<0>
INT_DDRCLK5_N_TP
SYSCLK_DDRCLK_A1_L_UF
SYSCLK_DDRCLK_A1_UF
SYSCLK_DDRCLK_A0_UF SYSCLK_DDRCLK_A0_L_UF
SYSCLK_DDRCLK_B1_L_UF
SYSCLK_DDRCLK_B1_UF
SYSCLK_DDRCLK_B0_L_UF
SYSCLK_DDRCLK_B0_UF
INT_DDRCLK5_P_TP
INT_DDRCLK2_P_TP INT_DDRCLK2_N_TP
INT_MEM_VREF
INT_MEM_REF_H
PCI_AD<31>
PCI_AD<30>
PCI_AD<29>
PCI_AD<28>
PCI_AD<27>
PCI_AD<26>
PCI_AD<25>
PCI_AD<24>
PCI_AD<9>
PCI_AD<8>
PCI_AD<7>
PCI_AD<6>
PCI_AD<5>
PCI_AD<4>
PCI_AD<3>
PCI_AD<20>
PCI_AD<2>
PCI_AD<19>
PCI_AD<18>
PCI_AD<17>
PCI_AD<16>
PCI_AD<15>
PCI_AD<14>
PCI_AD<13>
PCI_AD<12>
PCI_AD<11>
PCI_AD<10>
PCI_AD<1>
PCI_AD<0>
ROM_OE_L ROM_RW_L
INT_RESET_L
ROM_CS_L
ROM_ONBOARD_CS_L
ROM_WP_L
RAM_CKE<0>
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
38
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
36
36
36
16
36
36
36
36
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
39
39
39
36
11
11
11
15
36 36
36 36
36 36
36 36
36 36
36 36
36 36
36 36
36 36
36 36
36 36
36 36
36 36
36 36
36 36
36 36
36 36
36 36
11 36
11 36
36 36
11 36
11 36
36 36
36 36
36 36
36 36
36 36
36 36
36 36
36 36
36 36
36 36
36 36
38
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
38
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
24
24
30
24
39
11
9
9
9
10
9
11
11
9
9
11
11
9
11
9
11
9
11
9
11
9
11
9
11
9
11
9
11
9
11
9
11
9
11
9
11
9
11
9
11
9
9 9
9 9
11
9
9 9
9 9
11
9
11
9
11
9
11
9
11
9
11
9
11
9
11
9
11
9
11
9
11
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
10
10
10
9
9
9
9
9
9
9
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
9
9
9
9
9
9
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
9
9
9
9
9
9
9
9
9
38
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
13
12
24
9
GND
DA10
SEL
DH19
DH18
DH17
DH16
DH15
DH14
DH13
DH12
DH11
DH10
DH9
DH8
DH7
DH6
DH5
DH4
DH3
DH2
DH1
DH0
DA19
DA18
DA17
DA16
DA15
DA14
DA13
DA12
DA11DB0*
DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
DB19*
DB18*
DB17*
DB16*
DB15*
DB14*
DB13*
DB12*
DB11*
DB10*
DB9*
DB8*
DB7*
DB6*
DB5*
DB4*
DB3*
DB2*
DB1*
VDD
GND
DA10
SEL
DH19
DH18
DH17
DH16
DH15
DH14
DH13
DH12
DH11
DH10
DH9
DH8
DH7
DH6
DH5
DH4
DH3
DH2
DH1
DH0
DA19
DA18
DA17
DA16
DA15
DA14
DA13
DA12
DA11DB0*
DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
DB19*
DB18*
DB17*
DB16*
DB15*
DB14*
DB13*
DB12*
DB11*
DB10*
DB9*
DB8*
DB7*
DB6*
DB5*
DB4*
DB3*
DB2*
DB1*
VDD
GND
DA10
SEL
DH19
DH18
DH17
DH16
DH15
DH14
DH13
DH12
DH11
DH10
DH9
DH8
DH7
DH6
DH5
DH4
DH3
DH2
DH1
DH0
DA19
DA18
DA17
DA16
DA15
DA14
DA13
DA12
DA11DB0*
DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
DB19*
DB18*
DB17*
DB16*
DB15*
DB14*
DB13*
DB12*
DB11*
DB10*
DB9*
DB8*
DB7*
DB6*
DB5*
DB4*
DB3*
DB2*
DB1*
VDD
GND
DA10
SEL
DH19
DH18
DH17
DH16
DH15
DH14
DH13
DH12
DH11
DH10
DH9
DH8
DH7
DH6
DH5
DH4
DH3
DH2
DH1
DH0
DA19
DA18
DA17
DA16
DA15
DA14
DA13
DA12
DA11DB0*
DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
DB19*
DB18*
DB17*
DB16*
DB15*
DB14*
DB13*
DB12*
DB11*
DB10*
DB9*
DB8*
DB7*
DB6*
DB5*
DB4*
DB3*
DB2*
DB1*
VDD
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
MEM_MUXSEL_H<1> AND MEM_MUXSEL_L<1> ARE ACTIVE HIGH
ADDED 0 OHM RESISTORS IN CASE POLARITY IS WRONG
SEL = LOW; HOST = B PORT; A PORT = 100OHM TO GND SEL = HIGH; HOST = A PORT; B PORT = 100OHM TO GND
16BIT 2:1 DDR MUXES
BIT 48..63BIT 32..47
BIT 16..31
BIT 0..15
MEM_MUXSEL_H<0> AND MEM_MUXSEL_L<0> ARE ACTIVE LOW
2
1
C742
402
CERM
10V
20%
0.1UF
2
1
C748
20% 10V CERM 402
0.1UF
2
1
C753
402
CERM
10V
20%
0.1UF
2
1
C737
402
CERM
10V
20%
0.1UF
2
1
C738
20% 10V CERM 402
0.1UF
2
1
C736
402
CERM
10V
20%
0.1UF
2
1
C752
402
CERM
10V
20%
0.1UF
2
1
C747
20% 10V CERM 402
0.1UF
2
1
C741
402
CERM
10V
20%
0.1UF
2
1
C743
402
CERM
10V
20%
0.1UF
2
1
C727
402
CERM
10V
20%
0.1UF
2
1
C735
402
CERM
10V
20%
0.1UF
F8F3E8
E3
H6H5G9G2D9D2C6
C5
E2
C2
B2
B3
B5
B6
B8
B9
C9
E9
F9
H9
J9
J8
J6
J5
J3
J2
H2
F2
E1
C1
A1
A3
A4
A6
B7
A9
B10
D10
F10
H10
K10
K8
K7
K5
J4
K2
J1
G1
D1
B1
A2
B4
A5
A7
A8
A10
C10
E10
G10
J10
K9
J7
K6
K4
K3
K1
H1
F1
U13
CBTV4020
BGA
CRITICAL
F8F3E8
E3
H6H5G9G2D9D2C6
C5
E2
C2
B2
B3
B5
B6
B8
B9
C9
E9
F9
H9
J9
J8
J6
J5
J3
J2
H2
F2
E1
C1
A1
A3
A4
A6
B7
A9
B10
D10
F10
H10
K10
K8
K7
K5
J4
K2
J1
G1
D1
B1
A2
B4
A5
A7
A8
A10
C10
E10
G10
J10
K9
J7
K6
K4
K3
K1
H1
F1
U12
CBTV4020
BGA
CRITICAL
F8F3E8
E3
H6H5G9G2D9D2C6
C5
E2
C2
B2
B3
B5
B6
B8
B9
C9
E9
F9
H9
J9
J8
J6
J5
J3
J2
H2
F2
E1
C1
A1
A3
A4
A6
B7
A9
B10
D10
F10
H10
K10
K8
K7
K5
J4
K2
J1
G1
D1
B1
A2
B4
A5
A7
A8
A10
C10
E10
G10
J10
K9
J7
K6
K4
K3
K1
H1
F1
U10
CRITICAL
BGA
CBTV4020
F8F3E8
E3
H6H5G9G2D9D2C6
C5
E2
C2
B2
B3
B5
B6
B8
B9
C9
E9
F9
H9
J9
J8
J6
J5
J3
J2
H2
F2
E1
C1
A1
A3
A4
A6
B7
A9
B10
D10
F10
H10
K10
K8
K7
K5
J4
K2
J1
G1
D1
B1
A2
B4
A5
A7
A8
A10
C10
E10
G10
J10
K9
J7
K6
K4
K3
K1
H1
F1
U9
CRITICAL
BGA
CBTV4020
21
R242
NO STUFF
5%
0
402
MF
1/16W
21
R252
NO STUFF
1/16W
MF
402
0
5%
21
R243
1/16W
MF
402
0
5%
21
R239
5%
0
402
MF
1/16W
051-6598
01
10 44
+2_5V_INTREPID+2_5V_INTREPID
+2_5V_INTREPID
+2_5V_INTREPID
RAM_DATA_A<57>
MEM_DQM<7>
RAM_DATA_A<56>
RAM_DATA_A<48>
RAM_DATA_A<50> RAM_DATA_A<51>
RAM_DATA_A<49>
RAM_DATA_A<53>
RAM_DATA_A<52>
RAM_DATA_A<54> RAM_DATA_A<55> RAM_DQS_A<6> RAM_DQM_A<6>
RAM_MUXSEL_H
MEM_DATA<63>
MEM_DQS<7>
MEM_DATA<62>
MEM_DATA<60> MEM_DATA<61>
MEM_DATA<57> MEM_DATA<58> MEM_DATA<59>
MEM_DATA<56>
MEM_DQM<6>
MEM_DATA<55>
MEM_DATA<54>
MEM_DQS<6>
MEM_DATA<52> MEM_DATA<53>
MEM_DATA<50>
MEM_DATA<49>
MEM_DATA<51>
RAM_DQM_A<7>
MEM_DATA<48>
RAM_DQS_A<7>
RAM_DATA_A<62> RAM_DATA_A<63>
RAM_DATA_A<60> RAM_DATA_A<61>
RAM_DATA_A<59>
RAM_DATA_A<58>
RAM_DATA_B<59> RAM_DATA_B<60> RAM_DATA_B<61> RAM_DATA_B<62> RAM_DATA_B<63> RAM_DQS_B<7> RAM_DQM_B<7>
RAM_DATA_B<53> RAM_DATA_B<54> RAM_DATA_B<55>
RAM_DATA_B<51> RAM_DATA_B<52>
RAM_DQS_B<6> RAM_DQM_B<6> RAM_DATA_B<56> RAM_DATA_B<57> RAM_DATA_B<58>
RAM_DATA_B<50>
RAM_DATA_B<49>
RAM_DATA_B<48>RAM_DATA_A<41>
MEM_DQM<5>
RAM_DATA_A<40>
RAM_DATA_A<32>
RAM_DATA_A<34> RAM_DATA_A<35>
RAM_DATA_A<33>
RAM_DATA_A<37>
RAM_DATA_A<36>
RAM_DATA_A<38> RAM_DATA_A<39> RAM_DQS_A<4> RAM_DQM_A<4>
RAM_MUXSEL_H
MEM_DATA<47>
MEM_DQS<5>
MEM_DATA<46>
MEM_DATA<44> MEM_DATA<45>
MEM_DATA<41> MEM_DATA<42> MEM_DATA<43>
MEM_DATA<40>
MEM_DQM<4>
MEM_DATA<39>
MEM_DATA<38>
MEM_DQS<4>
MEM_DATA<36> MEM_DATA<37>
MEM_DATA<34>
MEM_DATA<33>
MEM_DATA<35>
RAM_DQM_A<5>
MEM_DATA<32>
RAM_DQS_A<5>
RAM_DATA_A<46> RAM_DATA_A<47>
RAM_DATA_A<44> RAM_DATA_A<45>
RAM_DATA_A<43>
RAM_DATA_A<42>
RAM_DATA_B<43> RAM_DATA_B<44> RAM_DATA_B<45> RAM_DATA_B<46> RAM_DATA_B<47> RAM_DQS_B<5> RAM_DQM_B<5>
RAM_DATA_B<37> RAM_DATA_B<38> RAM_DATA_B<39>
RAM_DATA_B<35> RAM_DATA_B<36>
RAM_DQS_B<4> RAM_DQM_B<4> RAM_DATA_B<40> RAM_DATA_B<41> RAM_DATA_B<42>
RAM_DATA_B<34>
RAM_DATA_B<33>
RAM_DATA_B<32>
RAM_DATA_A<25>
MEM_DQM<3>
RAM_DATA_A<24>
RAM_DATA_A<16>
RAM_DATA_A<18> RAM_DATA_A<19>
RAM_DATA_A<17>
RAM_DATA_A<21>
RAM_DATA_A<20>
RAM_DATA_A<22> RAM_DATA_A<23> RAM_DQS_A<2> RAM_DQM_A<2>
RAM_MUXSEL_L
MEM_DATA<31>
MEM_DQS<3>
MEM_DATA<30>
MEM_DATA<28> MEM_DATA<29>
MEM_DATA<25> MEM_DATA<26> MEM_DATA<27>
MEM_DATA<24>
MEM_DQM<2>
MEM_DATA<23>
MEM_DATA<22>
MEM_DQS<2>
MEM_DATA<20> MEM_DATA<21>
MEM_DATA<18>
MEM_DATA<17>
MEM_DATA<19>
RAM_DQM_A<3>
MEM_DATA<16>
RAM_DQS_A<3>
RAM_DATA_A<30> RAM_DATA_A<31>
RAM_DATA_A<28> RAM_DATA_A<29>
RAM_DATA_A<27>
RAM_DATA_A<26>
RAM_DATA_B<27> RAM_DATA_B<28> RAM_DATA_B<29> RAM_DATA_B<30> RAM_DATA_B<31> RAM_DQS_B<3> RAM_DQM_B<3>
RAM_DATA_B<21> RAM_DATA_B<22> RAM_DATA_B<23>
RAM_DATA_B<19> RAM_DATA_B<20>
RAM_DQS_B<2> RAM_DQM_B<2> RAM_DATA_B<24> RAM_DATA_B<25> RAM_DATA_B<26>
RAM_DATA_B<18>
RAM_DATA_B<17>
RAM_DATA_B<16>
RAM_DATA_A<9>
MEM_DQM<1>
RAM_DATA_A<8>
RAM_DATA_A<0>
RAM_DATA_A<2> RAM_DATA_A<3>
RAM_DATA_A<1>
RAM_DATA_A<5>
RAM_DATA_A<4>
RAM_DATA_A<6> RAM_DATA_A<7> RAM_DQS_A<0> RAM_DQM_A<0>
RAM_MUXSEL_L
MEM_DATA<15>
MEM_DQS<1>
MEM_DATA<14>
MEM_DATA<12> MEM_DATA<13>
MEM_DATA<9> MEM_DATA<10> MEM_DATA<11>
MEM_DATA<8>
MEM_DQM<0>
MEM_DATA<7>
MEM_DATA<6>
MEM_DQS<0>
MEM_DATA<4>
MEM_DATA<5>
MEM_DATA<2>
MEM_DATA<1>
MEM_DATA<3>
RAM_DQM_A<1>
MEM_DATA<0>
RAM_DQS_A<1>
RAM_DATA_A<14> RAM_DATA_A<15>
RAM_DATA_A<12> RAM_DATA_A<13>
RAM_DATA_A<11>
RAM_DATA_A<10>
RAM_DATA_B<11> RAM_DATA_B<12> RAM_DATA_B<13> RAM_DATA_B<14> RAM_DATA_B<15> RAM_DQS_B<1> RAM_DQM_B<1>
RAM_DATA_B<5> RAM_DATA_B<6> RAM_DATA_B<7>
RAM_DATA_B<3> RAM_DATA_B<4>
RAM_DQS_B<0> RAM_DQM_B<0> RAM_DATA_B<8> RAM_DATA_B<9> RAM_DATA_B<10>
RAM_DATA_B<2>
RAM_DATA_B<1>
RAM_DATA_B<0>
RAM_MUXSEL_L
MEM_MUXSEL_L<1>
RAM_MUXSEL_H
MEM_MUXSEL_H<1>
RAM_MUXSEL_L
MEM_MUXSEL_L<0>
RAM_MUXSEL_H
MEM_MUXSEL_H<0>
38 38
38
38
16 16
16
16
15 15
15
15
10 10
10
10
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36 36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36 36
36 36
36 36
36 36
9 9
9
9
11
9
11
11
11
11
11
11
11
11
11
11
11
10
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
11
9
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11 11
9
11
11
11
11
11
11
11
11
11
11
11
10
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
11
9
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
9
11
11
11
11
11
11
11
11
11
11
11
10
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
11
9
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
9
11
11
11
11
11
11
11
11
11
11
11
10
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
11
9
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
10
9
10
9
10
9
10
9
DQ58
RFU18
KEY
VDD6 VSS6 VSS8
VDD5
DQ15
DQ13
DQ14
VSS5
DM1
VDD3
VSS3
DQ7
DQ12
DQ6
DM0
DQ4 DQ5
VSS1
VREF1
VDD1
SA1 SA2
RFU19
SA0
VDD32
DQ63
DQ62
VSS32
DQ61
VDD30
DQ60
DQ55
DM7
VSS30
DQ54
DM6
VDD28
DQ53
DQ52
VDD25
CK1*
CK1
VSS28
DQ47
DQ46
VDD23
VSS25
DM5
DQ45
DQ44
DM4
DQ39
VSS23
DQ38
DQ37
RFU17
DQ36
VSS21
VDD21
VDD19
RAS*
BA1
CAS*
S1*
A6 A4 A2 A0
VSS19
A8
A11
VDD17
RFU15
CKE0
VDD15
VSS17
RFU11 VSS16
RFU9
VDD14
RFU3
VSS14
RFU5 RFU7
RFU1
VDD12
VSS12
DM3
DQ31
DQ30
DQ29
VSS10
VDD10
DQ28
DQ23
DM2
DQ20
VDD8
DQ21
DQ22
VDDSPD
SCL
SDA
VDD31
VSS31
DQ59
DQS7
DQ51
VDD29
DQ56
VSS29
DQ57
DQ48
DQS6
VDD27
DQ49
DQ50
DQ43
VSS26
VDD26
VDD24
VSS27
DQ41 DQS5 VSS24
VDD22
DQ42
DQ34 VSS22 DQ35
DQS4
DQ40
VDD20
RFU16
DQ32
VSS20
DQ33
S0*
VDD18
BA0
A10_AP
WE*
A1
A5 A3
A9
A7
VSS18
CKE1 RFU14
RFU13 VDD16
VDD13
VSS15
RFU10
RFU8
RFU12
RFU0
RFU4
VSS13
RFU2
RFU6
VSS11 DQ26 DQ27
DQS3
VDD11
DQ19 DQ24 VDD9
VSS9
DQ25
DQ18
DQ16
VDD7
DQ17
DQS2
DQ11 VDD4
VSS7
CK0*
CK0
DQS1 VSS4 DQ10
VDD2 DQ9
DQ2
DQS0
DQ8
DQ3
VSS2
VDD0
DQ0 DQ1
VSS0
VREF0
A12
DQ58
RFU18
KEY
VREF0
VDD0
DQ0 DQ1
VSS0
DQS0
VSS2
DQ3 DQ8
DQ2
VDD2
VSS4
DQS1
DQ10
DQ9
DQ11
CK0 CK0* VSS7
VDD4
DQ16
DQ18
VDD7
DQ17
DQS2
VSS9
DQ25
VDD9
DQ24
DQ19
DQS3
VDD11
DQ27
DQ26
VSS11
RFU0
VDD13
RFU4
VSS13
RFU2
RFU6
RFU13
RFU12
RFU8
RFU10 VSS15
A9
CKE1
RFU14
VDD16
A1
A5
A7
VSS18
A3
BA0
VDD18
S0*
WE*
A10_AP
DQ33
VSS20
DQ32
VDD20
RFU16
DQS4 DQ34
VSS22
DQ35 DQ40
VDD22
DQ41 DQS5
VSS24
DQ42 DQ43
DQ48
VSS26
VDD26
VDD24
VSS27
VSS29
DQ50
DQ49
DQS6
VDD27
DQS7
DQ51
VDD29
DQ56
DQ57
SDA
VDD31
VSS31
DQ59
VDDSPD
SCL
RFU19
VDD32
VSS28
CK1
DQ52
VDD28 DM6 DQ54 VSS30
DM7
DQ55 DQ60 VDD30 DQ61
DQ53
SA1 SA2
SA0
DQ63
DQ62
VSS32
VSS25
DM5
DQ45
VDD23
VDD21
VSS21 DQ36
RFU17
DQ44
DM4
DQ39
VSS23
DQ38
DQ37
RAS* CAS* S1*
DQ46 DQ47
CK1*
VDD25
RFU7
RFU5
VDD14
VSS17 VDD15
CKE0 RFU15
VDD17
A11 A8
RFU11 VSS16
RFU9
VSS19
A0
A2
A4
A6
BA1
VDD19
VDD12
VSS12
DQ31
DQ30
DM3
DQ22
DQ21 VDD8
DQ20
DQ29
VSS10
VDD10
DQ28
DQ23
DM2
VSS6 VSS8
RFU1
VSS14
RFU3
VREF1
DQ5
DQ4
DM0 DQ6
DQ12
DQ7
VSS3
VSS1
VDD1
VDD3
DM1 VSS5 DQ14
DQ13
DQ15 VDD5 VDD6
A12
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
FOR RETURN CURRENT
DDR BYPASS CAPS
SLOT "B"
SLOT "A"
ADDR=0XA2(WR)/0XA3(RD)
ADDR=0XA0(WR)/0XA1(RD)
CUSTOMER SLOT
SLOT "B"
REVERSED
STANDARD SLOT "A"
FACTORY SLOT
DDR SODIMM CONNS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC NC
NC NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC NC
NC NC
NCNC
DDR VREF
ONE 0.1UF PER SLOT
NC NC
NC NC
NC
NC
NC
NC
NC
NC
119
51
4039
38
2827
186185
174
16
173
162161
159
150149
138137
126125
15
104103
90
8887
7675
6463
52
43
21
197
57
4645
36
3433
192191
180
22
179
168167
157
156155
144143
132131
21
114113
9493
92
8281
7069
58
10
9
193 195
198
196
194
122121
8483
8079
7877
7473
200199
124123
9897
91
89
8685
7271
118
202
201
183
169
147
133
61
47
25
11
23
19
18
190
188
182
178
14
189
187
181
177
176
172
166
164
175
171
8
165
163
154
152
146
142
153
151
145
141
6
140
136
130
128
139
135
129
127
68
66
17
60
56
67
65
59
55
54
50
44
42
13
53
49
43
41
32
30
24
20
31
29
7
5
184
170
148
134
62
48
26
12
95 96
158 160
37
35
120
116
117
101 102
105 106 107 108 109 110
99
100
115
111 112
J19
CRITICAL
F-RT-SM
AS0A42-D2S
2
1
C602
CERM
6.3V
20%
805
10UF
2
1
C601
805
CERM
6.3V
20%
10UF
119
51
40 39
38
28 27
186 185
174
16
173
162 161
159
150 149
138 137
126 125
15
104 103
90
88 87
76 75
64 63
52
4 3
2 1
197
57
46 45
36
34 33
192 191
180
22
179
168 167
157
156 155
144 143
132 131
21
114 113
94 93
92
82 81
70 69
58
10
9
193 195
198
196
194
122 121
84 83
80 79
78 77
74 73
200 199
124 123
98 97
91
89
86 85
72 71
118
202
201
183
169
147
133
61
47
25
11
23
19
18
190
188
182
178
14
189
187
181
177
176
172
166
164
175
171
8
165
163
154
152
146
142
153
151
145
141
6
140
136
130
128
139
135
129
127
68
66
17
60
56
67
65
59
55
54
50
44
42
13
53
49
43
41
32
30
24
20
31
29
7
5
184
170
148
134
62
48
26
12
9596
158 160
37
35
120
116
117
101102
105106 107108 109110
99
100
115
111112
J22
AS0A42-D2R
F-RT-SM
CRITICAL
2
1
C530
CERM
6.3V
20%
805
10UF
2
1
C589
805
CERM
6.3V
20%
10UF
2
1
R449
402
MF
1/16W
1%
1K
2
1
R440
1K
1% 1/16W MF 402
2
1
C542
20% 10V CERM 402
0.1UF
2
1
C482
20% 10V CERM 402
0.1UF
+2_5V_MAIN+2_5V_MAIN
+2_5V_MAIN +2_5V_MAIN
+2_5V_MAIN
+2_5V_MAIN
+2_5V_MAIN
+3V_MAIN
2
1
C573
402
CERM
10V
20%
0.1UF
2
1
C526
402
CERM
10V
20%
0.1UF
2
1
C525
20% 10V CERM 402
0.1UF
+3V_MAIN
2
1
C490
402
CERM
10V
20%
0.1UF
2
1
C527
20% 10V CERM 402
0.1UF
2
1
C481
402
CERM
10V
20%
0.1UF
2
1
C523
20% 10V CERM 402
0.1UF
2
1
C549
402
CERM
10V
20%
0.1UF
2
1
C524
20% 10V CERM 402
0.1UF
2
1
C595
20% 10V CERM 402
0.1UF
2
1
C522
20% 10V CERM 402
0.1UF
2
1
C597
402
CERM
10V
20%
0.1UF
2
1
C489
402
CERM
10V
20%
0.1UF
+3V_MAIN
2
1
C594
20% 10V CERM 402
0.1UF
2
1
C596
20% 10V CERM 402
0.1UF
2
1
C548
402
CERM
10V
20%
0.1UF
2
1
C565
20% 10V CERM 402
0.1UF
2
1
C550
402
CERM
10V
20%
0.1UF
2
1
C551
402
CERM
10V
20%
0.1UF
2
1
C761
20% 10V CERM 402
0.1UF
4411
051-6598
01
RAM_DATA_B<19> RAM_DATA_B<24>
RAM_DATA_B<18>
RAM_DQS_B<2>
RAM_DATA_B<17>
RAM_DATA_B<16>
SYSCLK_DDRCLK_B0_L
SYSCLK_DDRCLK_B0
RAM_DATA_B<11>
RAM_DATA_B<10>
RAM_ADDR<12>
RAM_DATA_B<35>
RAM_DATA_B<34>
RAM_DQS_B<4>
RAM_DATA_B<33>
RAM_DATA_B<32>
RAM_WE_L
RAM_CS_L<2>
RAM_BA<0>
RAM_ADDR<10>
RAM_ADDR<1>
RAM_ADDR<3>
RAM_ADDR<5>
RAM_ADDR<7>
RAM_ADDR<9>
RAM_CKE<3>
RAM_DATA_B<27>
RAM_DATA_B<26>
RAM_DQS_B<3>
RAM_DATA_B<25>
RAM_DQS_B<5>
RAM_DATA_B<41>
RAM_DATA_B<40>
DDR_VREF
RAM_DATA_A<21>
RAM_DATA_A<61>
RAM_DATA_A<62>
RAM_DQM_A<7>
RAM_DATA_A<60>
RAM_DATA_A<55>
RAM_DQM_A<6> RAM_DATA_A<54>
RAM_DATA_A<53>
RAM_DATA_A<52>
SYSCLK_DDRCLK_A1
SYSCLK_DDRCLK_A1_L
RAM_DATA_A<47>
RAM_DATA_A<46>
RAM_DQM_A<5>
RAM_DATA_A<45>
RAM_DATA_A<39> RAM_DATA_A<44>
RAM_DATA_A<38>
RAM_DQM_A<4>
RAM_DATA_A<36> RAM_DATA_A<37>
RAM_CS_L<1>
RAM_RAS_L RAM_CAS_L
RAM_BA<1>
RAM_ADDR<0>
RAM_ADDR<4> RAM_ADDR<2>
RAM_ADDR<6>
RAM_ADDR<8>
RAM_ADDR<11>
RAM_CKE<0>
RAM_DATA_A<30>
RAM_DQM_A<3>
RAM_DATA_A<29>
RAM_DATA_A<28>
RAM_DATA_A<23>
RAM_DATA_A<22>
RAM_DATA_A<20>
RAM_DATA_A<15>
RAM_DATA_A<14>
RAM_DQM_A<1>
RAM_DATA_A<13>
RAM_DATA_A<7>
RAM_DATA_A<12>
RAM_DATA_A<6>
RAM_DQM_A<0>
RAM_DATA_A<5>
RAM_DATA_A<4>
DDR_VREF
INT_I2C_CLK0
INT_I2C_DATA0
RAM_DATA_A<59>
RAM_DATA_A<58>
RAM_DQS_A<7>
RAM_DATA_A<57>
RAM_DATA_A<56>
RAM_DATA_A<51>
RAM_DQS_A<6> RAM_DATA_A<50>
RAM_DATA_A<49>
RAM_DATA_A<48>
RAM_DATA_A<43>
RAM_DQS_A<5>
RAM_DATA_A<42>
RAM_DATA_A<41>
RAM_DATA_A<35> RAM_DATA_A<40>
RAM_DQS_A<4> RAM_DATA_A<34>
RAM_DATA_A<32> RAM_DATA_A<33>
RAM_CS_L<0>
RAM_BA<0> RAM_WE_L
RAM_ADDR<10>
RAM_ADDR<1>
RAM_ADDR<5> RAM_ADDR<3>
RAM_ADDR<7>
RAM_ADDR<9>
RAM_ADDR<12>
RAM_CKE<1>
RAM_DATA_A<27>
RAM_DATA_A<26>
RAM_DQS_A<3>
RAM_DATA_A<24>
RAM_DATA_A<25>
RAM_DATA_A<19>
RAM_DATA_A<18>
RAM_DQS_A<2>
RAM_DATA_A<17>
RAM_DATA_A<16>
SYSCLK_DDRCLK_A0 SYSCLK_DDRCLK_A0_L
RAM_DATA_A<11>
RAM_DQS_A<1>
RAM_DATA_A<10>
RAM_DATA_A<9>
RAM_DATA_A<3> RAM_DATA_A<8>
RAM_DATA_A<2>
RAM_DQS_A<0>
RAM_DATA_A<1>
RAM_DATA_A<0>
DDR_VREF
RAM_DATA_A<63>
RAM_DQM_A<2>
RAM_DATA_A<31>
DDR_VREF
RAM_DATA_B<0> RAM_DATA_B<1>
RAM_DQS_B<0>
RAM_DATA_B<2>
RAM_DATA_B<3> RAM_DATA_B<8>
RAM_DATA_B<9>
RAM_DQS_B<1>
RAM_DATA_B<42> RAM_DATA_B<43>
RAM_DATA_B<48> RAM_DATA_B<49>
RAM_DATA_B<50>
RAM_DQS_B<6>
RAM_DATA_B<56>
RAM_DATA_B<51>
RAM_DQS_B<7>
RAM_DATA_B<57>
RAM_DATA_B<58> RAM_DATA_B<59>
INT_I2C_DATA0
INT_I2C_CLK0
RAM_DATA_B<62>
RAM_DQM_B<7>
RAM_DATA_B<61>
RAM_DATA_B<63>
RAM_DATA_B<60>
RAM_DATA_B<55>
RAM_DQM_B<6> RAM_DATA_B<54>
RAM_DATA_B<53>
RAM_DATA_B<52>
SYSCLK_DDRCLK_B1
SYSCLK_DDRCLK_B1_L
RAM_DATA_B<45> RAM_DQM_B<5>
RAM_DATA_B<44>
RAM_DATA_B<39>
RAM_DATA_B<46> RAM_DATA_B<47>
RAM_DATA_B<38>
RAM_DQM_B<4>
RAM_DATA_B<37>
RAM_DATA_B<36>
RAM_CAS_L
RAM_RAS_L
RAM_CS_L<3>
RAM_ADDR<4>
RAM_ADDR<0>
RAM_ADDR<6>
RAM_ADDR<8>
RAM_ADDR<11>
RAM_ADDR<2>
RAM_BA<1>
RAM_CKE<2>
RAM_DATA_B<31>
RAM_DQM_B<3>
RAM_DATA_B<30>
RAM_DATA_B<29>
RAM_DATA_B<28>
RAM_DATA_B<23>
RAM_DQM_B<2> RAM_DATA_B<22>
RAM_DATA_B<21>
RAM_DATA_B<20>
RAM_DATA_B<15>
RAM_DATA_B<14>
RAM_DATA_B<13> RAM_DQM_B<1>
RAM_DATA_B<12>
RAM_DATA_B<7>
RAM_DATA_B<6>
RAM_DQM_B<0>
RAM_DATA_B<5>
RAM_DATA_B<4>
DDR_VREF
39
39
39
39
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
23
23
36
36
36
36
36
36
36
36
36
23
23
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
11
36
36
36
36
36
11
36
11
11
11
11
11
11
11
36
36
36
36
36
36
36
36
38
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
11
11
11
11
11
11
11
11
11
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
38
13
13
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
11
11
11
11
11
11
11
11
11
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
38
36
36
36
38
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
13
13
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
11
11
36
11
11
11
11
11
11
11
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
38
10
10
10
10
10
10
9
9
10
10
9
10
10
10
10
10
9
9
9
9
9
9
9
9
9
9
10
10
10
10
10
10
10
11
10
10
10
10
10
10
10
10
10
10
9
9
10
10
10
10
10
10
10
10
10
10
9
9
9
9
9
9
9
9
9
9
9
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
11
11
11
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
9
9
9
9
9
9
9
9
9
9
9
10
10
10
10
10
10
10
10
10
10
9
9
10
10
10
10
10
10
10
10
10
10
11
10
10
10
11
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
11
11
10
10
10
10
10
10
10
10
10
10
9
9
10
10
10
10
10
10
10
10
10
10
9
9
9
9
9
9
9
9
9
9
9
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
11
(PLL4)
VDD15A_6
(PLL4) VSSA_6
ROM_WE
ROM_OE
PCI_STOP PCI_DEVSEL
PCI_CBE_3
PCI_CBE_2
PCI_CBE_1
PCI_CBE_0
ROM_CS
PCI_CLK_IN
PCI_CLK_OUT
PCI_CLK2
PCI_CLK1
PCI_CLK0
PCI_FRAME
PCI_PAR
PCI_TRDY PCI_IRDY
PCI_REQ_2
PCI_REQ_1
PCI_REQ_0
PCI_GNT_0 PCI_GNT_1 PCI_GNT_2
PCI/ROM
INTERFACE
PCIAD_31
PCIAD_30
PCIAD_28
PCIAD_27
PCIAD_26
PCIAD_25
PCIAD_29
PCIAD_19
PCIAD_18
PCIAD_17
PCIAD_16
PCIAD_15
PCIAD_23 PCIAD_24
PCIAD_20 PCIAD_21 PCIAD_22
PCIAD_14
(7 OF 9)
PCIAD_11
PCIAD_10
PCIAD_12 PCIAD_13
PCIAD_9
PCIAD_6
PCIAD_5
PCIAD_7 PCIAD_8
PCIAD_4
PCIAD_3
PCIAD_1 PCIAD_2
PCIAD_0
ROM_OVRLY_EN
VSSA_5 (PLL5)
(PLL5)
VDD15A_5
STP_AGP AGPPVT AGPVREF0 AGPVREF1
AGP_BUSY AGP_CLK AGP_FB_IN AGP_FB_OUT
AGPAD0
AGPREQ AGPGNT
AGP_SBA3
AGP_SBA2
AGP_SBA1
AGP_SBA0
AGPCBE_3
AGPFRAME
AGPTRDY AGPIRDY AGPSTOP
AGPDEVSEL
AGPPAR
AGPAD31
AGPAD30
AGPCBE_0 AGPCBE_1 AGPCBE_2
AGP_ST2
AGP_AD_STB0_P AGP_AD_STB0_N AGP_AD_STB1_P AGP_AD_STB1_N
AGPPIPE
AGPRBF
AGP_ST1
AGP_SBA7
AGP_SB_STB_P AGP_SB_STB_N
AGP_ST0
AGP_WBF
AGP
INTERFACES
AGP_SBA6
AGP_SBA5
AGP_SBA4
AGPAD29
AGPAD28
AGPAD27
AGPAD26
AGPAD25
AGPAD24
AGPAD23
AGPAD22
AGPAD21
AGPAD20
AGPAD19
AGPAD18
AGPAD17
AGPAD16
AGPAD15
AGPAD14
AGPAD13
AGPAD12
AGPAD11
AGPAD10
AGPAD9
AGPAD8
AGPAD7
AGPAD6
AGPAD5
AGPAD4
AGPAD3
AGPAD2
AGPAD1
(3 OF 9)
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
PCI FEEDBACK CLOCK MATCHES LONGEST PCI CLOCK ROUTE
VIN = 1.5V (CORE)
VOUT = 3.3V
PCI PULL-UPS
NOTE: Designs using AGP slot should
use 52-ohm a resistor here.
Vout = AGPIO (1.5V)
Vin = Vcore (1.5V)
AGP PULL-UPS/PULL DOWNS
INTREPID AGP/PCI
Need divider for 3.3V slot!
OUTPUT IMPEDANCE IS ABOUT 20OHM
AGP I/O REFERENCE
(PLACE CLOSE TO INTREPID AGP BALLS)
SIMPLY PROVIDING REFERENCE TO CHIP BECAUSE SINGLE AGP PWR PLANE AND CLOSE PROXIMITY OF CHIPS
SERIES RESISTORS FOR BOOTROM CONTROL SIGNALS
PLACE CLOSE TO INTREPID SIDE
AGP_FB_CLK IS ROUTED THE SAME LENGTH AS CLK66M_GPU_AGP
USB2 AND CBUS REQ REMAINS ON +3V_MAIN BECAUSE THESE CHIPS ARE POWERED IN SLEEP
21
R146
MF
1/16W
5%
4.7
402
21
R217
0
402
5%
1/16W
MF
2
1
R209
1% 1/16W MF 402
60.4
81
RP22
SM1
10K
5%
1/16W
81
RP20
SM1
1/16W
5%
10K
81
RP19
SM1
1/16W
5%
10K
72
RP19
SM1
1/16W
5%
10K
21
R112
402
4.7
5%
1/16W
MF
2
1
C83
0.22UF
402
20%
6.3V CERM
J10
J11
AN9
AK17
AR7
AM9
AT15
AR15
AT17
AR16
AR17
AT14
AH16
AN17
AN18
AT16
AN16
AM17
AM18 AJ19
AT18
AH18
AR18
AJ15
AM16
AK16
AR14
AR9
AK13
AH13
AN11
AT8
AN10
AM15
AN15
AJ8
AK14
AT13
AN14
AH15
AK15
AR13
AM11
AT12
AJ11
AR12
AK12
AM13
AN13
AT10
AT11
AK11
AN12
AM12
AR11
AT9
AR10
AR8
AM10
U45
INTREPID-REV2.1
BGA
CRITICAL
21
R192
33
402
MF
1/16W
5%
21
R147
33
402
MF
1/16W
5%
21
R171
MF
1/16W
5%
402
33
2
1
R186
5% 1/16W MF 402
47
+3V_SLEEP
81
RP18
SM1
1/16W
5%
10K
63
RP17
SM1
1/16W
5%
10K
81
RP17
SM1
1/16W
10K
5%
72
RP17
10K
5%
1/16W
SM1
63
RP18
SM1
1/16W
5%
10K
54
RP17
SM1
10K
5%
1/16W
54
RP18
1/16W
5%
10K
SM1
72
RP18
1/16W
5%
10K
SM1
21
R77
402
MF
1/16W
5%
22
21
R82
402
MF
1/16W
5%
22
21
R103
402
MF
1/16W
5%
22
21
R169
33
402
MF
1/16W
5%
21
R157
NEC_USB
5%
1/16W
MF
402
22
+3V_MAIN
21
R187
10K
5%
1/16W
MF
402
21
R230
5%
10K
1/16W
MF
402
21
R193
402
MF
1/16W
5%
10K
21
R170
10K
5%
1/16W
MF
402
21
R194
402
MF
1/16W
5%
10K
21
R216
5%
10K
1/16W
MF
402
2
1
R185
4.99K
1%
1/16W
MF
402
2
1
R180
4.99K
1%
1/16W
MF
402
2
1
C247
0.22UF
6.3V 402
CERM
20%
54
RP20
10K
5%
1/16W
SM1
72
RP22
10K
5%
1/16W
SM1
72
RP20
1/16W
5%
10K
SM1
63
RP19
SM1
10K
5%
1/16W
54
RP19
10K
5%
1/16W
SM1
63
RP20
10K
5%
1/16W
SM1
54
RP22
10K
5%
1/16W
SM1
63
RP22
10K
5%
1/16W
SM1
V13
V14
AN19
AK30
AR30
AT30
AN29
AH25 AG25
AN30
AM30
AT31
AR31
AN31
AM31
AR32
AT32
AK25
AK27
AK28
AT19
AK21 AK22
AK20 AK19
AB21
AB20
AR29
AM28
AT33
AK24
AJ24
AJ29
AT29
AT28
AM29
AN28
AM27
AL25
AN24
AT23
AM20
AT22
AM21
AN21
AR21
AN20
AT21
AN27
AR28
AR20
AT27
AR27
AM26
AN26
AM25
AT26
AR26
AL24
AN25
AM24
AT20
AR25
AT25
AR24
AM23
AT24
AR23
AN23
AM22
AN22
AR22
AM19
AR19
U45
INTREPID-REV2.1
BGA
CRITICAL
2
1
C160
0.22UF
CERM
6.3V
20%
402
01
051-6598
12 44
CBUS_PCI_REQ_L
USB2_PCI_REQ_L
AIRPORT_PCI_REQ_L
INT_ROM_RW_L
ROM_RW_L
INT_ROM_OE_L
ROM_OE_L
INT_ROM_CS_L
ROM_CS_L
INT_AGP_VREF
+1_5V_AGP
INT_AGP_FB_OUT
INT_AGP_FB_IN
CLK66M_AGP_15V_TP
AGP_SB_STB_L
AGP_AD_STB_L<1>
AGP_SB_STB
+1_5V_AGP
AGP_AD_STB<0>
AGP_STOP_L
AGP_WBF_L
AGP_IRDY_L
AGP_AD_STB_L<0>
AGP_AD_STB<1>
AGP_PIPE_L
AGP_RBF_L
AGP_TRDY_L
AGP_DEVSEL_L
AGP_REQ_L
AGP_FRAME_L
+3V_GPU
STOP_AGP_L
AGP_GNT_L
AGP_BUSY_L
+1_5V_INTREPID_PLL
AGP_WBF_L
AGP_RBF_L
AGP_PIPE_L
AGP_AD_STB_L<0>
AGP_AD_STB<0>
AGP_AD_STB_L<1>
AGP_AD_STB<1>
AGP_ST<1> AGP_ST<2>
AGP_ST<0>
AGP_SB_STB_L
AGP_SB_STB
AGP_SBA<7>
AGP_SBA<6>
AGP_SBA<5>
AGP_SBA<4>
AGP_SBA<3>
AGP_SBA<2>
AGP_SBA<0>
AGP_DEVSEL_L
AGP_STOP_L
AGP_IRDY_L
AGP_TRDY_L
AGP_FRAME_L
AGP_PAR
AGP_CBE<3>
AGP_CBE<2>
AGP_CBE<1>
AGP_CBE<0>
AGP_AD<7>
AGP_AD<31>
AGP_AD<30>
AGP_AD<29>
AGP_AD<28>
AGP_AD<27>
AGP_AD<26>
AGP_AD<25>
AGP_AD<24>
AGP_AD<23>
AGP_AD<22>
AGP_AD<21>
AGP_AD<20>
AGP_AD<19>
AGP_AD<18>
AGP_AD<17>
AGP_AD<16>
AGP_AD<15>
AGP_AD<14>
AGP_AD<13>
AGP_AD<12>
AGP_AD<11>
AGP_AD<10>
AGP_AD<9>
AGP_AD<8>
AGP_AD<6>
AGP_AD<5>
AGP_AD<4>
AGP_AD<3>
AGP_AD<2>
AGP_AD<1>
AGP_AD<0>
INT_AGP_VREF
AGP_BUSY_L
STOP_AGP_L
AGP_GNT_L
AGP_REQ_L
AGP_SBA<1>
+1_5V_INTREPID_PLL5
INT_AGPPVT
+1_5V_AGP
PCI_FRAME_L
PCI_DEVSEL_L
PCI_IRDY_L
PCI_TRDY_L
PCI_STOP_L
+1_5V_INTREPID_PLL
PCI_AD<0>
PCI_AD<3>
PCI_AD<1> PCI_AD<2>
PCI_AD<4> PCI_AD<5> PCI_AD<6>
PCI_AD<8>
PCI_AD<7>
PCI_AD<10> PCI_AD<11>
PCI_AD<9>
PCI_AD<13>
PCI_AD<12>
PCI_AD<16>
PCI_AD<14> PCI_AD<15>
PCI_AD<18>
PCI_AD<17>
PCI_AD<20> PCI_AD<21>
PCI_AD<19>
PCI_AD<22> PCI_AD<23> PCI_AD<24> PCI_AD<25> PCI_AD<26> PCI_AD<27> PCI_AD<28> PCI_AD<29>
PCI_AD<31>
PCI_AD<30>
+1_5V_INTREPID_PLL6
AIRPORT_PCI_REQ_L CBUS_PCI_REQ_L USB2_PCI_REQ_L
USB2_PCI_GNT_L
AIRPORT_PCI_GNT_L CBUS_PCI_GNT_L
PCI_PAR
PCI_IRDY_L
PCI_FRAME_L PCI_TRDY_L
PCI_STOP_L PCI_DEVSEL_L
PCI_CBE<0> PCI_CBE<1> PCI_CBE<2> PCI_CBE<3>
INT_ROM_OE_L
INT_ROM_CS_L
INT_ROM_RW_L
CLK33M_AIRPORT_UF
CLK33M_AIRPORT
CLK33M_CBUS
INT_PCI_FB_OUT INT_PCI_FB_IN
CLK33M_USB2_UF
CLK33M_USB2
CLK66M_GPU_AGP_UF
CLK66M_GPU_AGP
CLK33M_CBUS_UF
38
38
38
21
21
21
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
19
19
19
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
39
37
39
39
37
37
37
37
37
37
37
37
39
37
37
37
37
37
39
39
39
39
18
18
38
38
18
26
26
26
26
26
38
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
37
26
37
37
26
26
26
26
26
26
26
26
37
26
26
26
26
26
37
37
37
37
39
39
39
39
38
16
37
37
37
16
37
37
37
37
37
37
37
37
37
37
21
37
14
37
37
37
37
37
37
37
37
37
37
37
37
38
37
37
16
24
24
24
24
24
14
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
26
24
26
26
24
24
24
24
24
24
24
24
39
26
24
24
24
24
24
26
26
26
26
39
17
26
24
24
24
24
18
15
18
18
18
15
18
18
18
18
18
18
18
18
18
18
18
19
18
18
12
18
18
18
18
18
18
18
18
37
37
37
37
37
37
37
18
18
18
18
18
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
18
18
18
18
37
15
17
17
17
17
17
12
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
24
17
24
24
17
17
17
17
17
17
17
17
24
17
26
39
24
17
17
17
17
17
24
24
24
24
36
36
36
36
12
12
12
12
9
12
9
12
9
12
12
36
36
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
18
12
12
12
8
12
12
12
12
12
12
12
18
18
18
12
12
18
18
18
18
18
18
18
12
12
12
12
12
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
12
12
12
12
12
18
38
12
12
12
12
12
12
8
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
17
9
17
17
9
9
9
9
9
9
9
9
38
12
12
12
26
24
17
17
12
12
12
12
12
17
17
17
17
12
12
12
36
24
17
36
36
36
26
36
18
36
CS_CE2
CS_CE1
CS_IORD CS_IOWR
ATA_CS1
ATA_CS0
IDE
IDEINTRQ
IDECHRDY
IDECS0
IDECS1
IDEDMACK IDEDMARQ
IDERD
IDEWR
IDERST
IDEA9
IDEA8
IDEA7
IDEA6
IDEA5
IDEA4
IDEA3
IDEA2
IDEA1
IDEA0
IDEDD15
IDEDD14
IDEDD13
IDEDD12
IDEDD11
IDEDD10
IDEDD9
IDEDD8
IDEDD7
IDEDD6
IDEDD5
IDEDD4
IDEDD3
IDEDD2
IDEDD1
IDEDD0
CARDSLOT
CS_WAIT
CS_OE CS_WE
ATA_INTRQ
ATA_DMARQ
ATA_CHRDY
ATA_DMACK
ATA_RD
ATA_WR
ATA_RST
ATA_VREF
UATA100
ATA_A1 ATA_A2
ATA_A0
ATA_D12
ATA_D11
ATA_D15
ATA_D14
ATA_D13
ATA_D10
ATA_D9
ATA_D3
ATA_D2
ATA_D1
ATA_D0
ATA_D4
ATA_D8
ATA_D7
ATA_D6
ATA_D5
(5 OF 9)
IICDATA_1
IICCLK_1
IICCLK_0 IICDATA_0
TST_PLLEN
TST_MONOUT
TST_MONIN
TEI
TRSTN
TMS
TCK
TDO
TDI
TEST
MDC
GBE_REFCLK
MDIO
COL
CRS
GTX_CLK
RXD_6
RXD_4 RXD_5
RXD_3
RXD_7
RXD_2
RXD_1
RX_ER
RX_DV
RX_CLK
RXD_0
FW_PINT
FW_LINKON
FWR_LCLK
TX_ER
TX_EN
TX_CLK
TXD_0
RESET
PURESET
PHY_LPS PHY_CTL0 PHY_CTL1 PHY_LREQ FWR_PCLK
(4 OF 9)
MISC
TXD_3
TXD_2
TXD_1
TXD_4 TXD_5 TXD_6 TXD_7
GB ETHERNET
FIREWIRE
PHY_DATA0 PHY_DATA1 PHY_DATA2 PHY_DATA3
PHY_DATA5
PHY_DATA7
PHY_DATA4
PHY_DATA6
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
.
CS_WAIT IS AN INPUT
PMU
U3 - PG 24
J12 - PG 24
CLOCK SLEW SSCG
U56 - PG 15
ADDR LSB INDICATES READ (’1’) OR WRITE (’0’) MODES
AC-WR AD-RD
58-WR
ATPG NORMAL
0(I)
J9 - PG 25
U36 - PG 23
U37 - PG 23
J23 - PG 12
J20 - PG 12
TEST PULL-UPS/DOWNS
I2C PULL-UPS
ENET_TXD SERIES TERMINATION
INT - ENET/FW/UATA
EIDE/I2C
NOT USING CARDSLOT INTERFACE
UDMA - DEVICEDMARDY/DSTROBE
UDMA - HOSTDMARDY/HSTROBE
UDMA - STOP
FUNCTIONAL TEST WITH
FUNCTIONAL TEST IDDQ
FUNCTIONAL TEST WITHOUT
VIEW PLLS (HARDWARE)
TEST TRI-STATE
NORMAL OPERATION VIEW PLLS (SOFTWARE)
DESCRIPTION
JTAG MODE
ANALYZER_CLK
BYPASS
SYNC/MEM DATA
(OUTPUT)
X
PLL OUTPUTS
SELECTED
SELECTED
PLL OUTPUTS
POSTSCALAR BYPASS
POSTSCALAR BYPASS
ATPG IDDQ
X(I)
X(I)
X(I)
X(I)
X(I)
MEMWE
TST_PLLEN_H
JTG_TDI_H
(I/O)
0
1(I)
0(I)
1
X
1
TPDENABLE
DDR_
(OUTPUT)
X
0(I)
(INPUT)
(OUTPUT)
TESTSEL5
JTG_TDO_H
(OUTPUT)
SHUTDOWN
1
0
HWPLL_
(I/O)
TST_TEI_H
X 0 0
X
EXTPLL
1(I)
0(I)
1
1(I) 1(I)
0
0
X
1
0(I)
1(I) 1(I) 1(I)
0(I)
0(I) 1 1 1
1
1
JTG_RSTN_L
0
0
1
0
0
0 0
0
0
0
N/A
(SLEEP)
N/A N/A N/A N/A
N/A
DASH MODEM
N/A
N/A
I2C-2
(SLEEP)
N/A
I2C-1
N/A
N/A
(MAIN)
N/A N/A N/A
N/A
N/A
N/A
SNAPPER SOUND
FAN CONTROLLER
N/A
N/A
N/A
BOOTBANG E2PROM
N/A
RAM - REVERSED
I2C-0
N/A N/A N/A
RAM - STANDARD
(MAIN)
LMU
BUS
AF-RD
AE-WR
A3-RD
A2-WR
A0-WR
85-RD
84-WR
ADDR
A1-RD
59-RD 6B-RD
6A-WR D0-WR
D1-RD
21
R629
402
MF
1/16W
5%
1K
81
RP16
10K
5%
1/16W
SM1
21
R621
10K
402
MF
1/16W
5%
2
1
R52
402
MF
1/16W
5%
10K
72
RP15
1/16W
5%
SM1
22
54
RP14
1/16W
5%
SM1
22
63
RP14
5%
1/16W
SM1
22
81
RP14
1/16W
5%
SM1
22
72
RP14
1/16W
5%
SM1
22
63
RP15
5%
1/16W
SM1
22
81
RP15
1/16W
5%
SM1
22
54
RP15
5%
1/16W
SM1
22
+3V_MAIN
12
R117
10K
MF
1/16W
5%
402
+3V_MAIN
+3V_MAIN
21
R626
402
MF
1/16W
5%
1K
72
RP12
SM1
1/16W
5%
2.2K
81
RP12
SM1
1/16W
2.2K
5%
54
RP12
SM1
1/16W
5%
2.2K
63
RP12
1/16W
5%
SM1
2.2K
63
RP16
1/16W
5%
10K
SM1
72
RP16
SM1
10K
5%
1/16W
54
RP16
1/16W
5%
10K
SM1
2
1
R154
1%
1K
1/16W MF 402
AM2
AJ4
AL2
AA7
AH7
AG8
AE5
AE4
AG2
AD5
AH1
AF2
AG1
AF1
AJ2
AJ1
AG4
AD7
AH2
AF4
AD4
AC5
AM1
AB7
AK4
AG7
AF7
AH5
AK2
AL1
AH4
AG5
AK1
AE7
AF5
AE1 AE2
AC4
AD2
AB5
AB4
AD1
AA1
Y15
Y4
AA2
AA8
AC2
AC1
W8
W2
V1
W1
V2
V4
U2
U1
Y8
W7
Y1
Y2
W5
W4
T1
V5
AB2
AA4
AA5
Y7
AB1
Y5
U45
BGA
CRITICAL
INTREPID-REV2.1
21
R51
402
5%
1/16W
MF
82
21
R92
402
82
MF
1/16W
5%
A5
A7
H9
E10
D9
G10
B7
A6
D8
E9
H10
AR6
AK10
AM7
AN6
AR5
AH10
AT5
AK8
AP5
D2
C4
J12
E8
G9
D7
A4
B4
D6
E7
D3
U5
T2
M2
M1
N4
L2
K2
K1
N5
P7
M4
L4
L1
P5
B5 B6
AM3
AN1
AK5
AN2
H12
L13
N1
N2
T7
U14 E6 C5
U45
BGA
INTREPID-REV2.1
CRITICAL
21
R145
22
5%
1/16W
MF
402
21
R34
402
MF
1/16W
5%
22
21
R624
402
MF
1/16W
5%
10
21
R630
402
MF
1/16W
10
5%
21
R124
402
MF
1/16W
5%
10
051-6598
01
13 44
CSLOT_ADDR3_SPN CSLOT_ADDR4_SPN CSLOT_ADDR5_SPN CSLOT_ADDR6_SPN CSLOT_ADDR7_SPN CSLOT_ADDR8_SPN CSLOT_ADDR9_SPN
CSLOT_CE1_L_SPN CSLOT_CE2_L_SPN CSLOT_IORD_L_SPN CSLOT_IOWR_L_SPN CSLOT_OE_L_SPN CSLOT_WE_L_SPN CSLOT_IOWAIT_L_PU
UIDE_INTRQ
HD_INTRQ
UIDE_DMARQ
HD_DMARQ
EIDE_RST_L
EIDE_RD_L
EIDE_WR_L
EIDE_DMARQ
EIDE_DMACK_L
EIDE_INT
EIDE_CS1_L
EIDE_CS0_L
EIDE_DATA<0> EIDE_DATA<1> EIDE_DATA<2> EIDE_DATA<3>
EIDE_DATA<5>
EIDE_DATA<4>
EIDE_DATA<7>
EIDE_DATA<6>
EIDE_DATA<8>
EIDE_DATA<10>
EIDE_DATA<9>
EIDE_DATA<12>
EIDE_ADDR<2>
EIDE_IOCHRDY
EIDE_ADDR<1>
EIDE_ADDR<0>
EIDE_DATA<14> EIDE_DATA<15>
EIDE_DATA<13>
EIDE_DATA<11>
UIDE_DATA<0> UIDE_DATA<1> UIDE_DATA<2> UIDE_DATA<3> UIDE_DATA<4>
UIDE_DATA<6> UIDE_DATA<7> UIDE_DATA<8> UIDE_DATA<9> UIDE_DATA<10> UIDE_DATA<11> UIDE_DATA<12> UIDE_DATA<13> UIDE_DATA<14> UIDE_DATA<15>
UIDE_DATA<5>
UIDE_ADDR<0> UIDE_ADDR<1> UIDE_ADDR<2>
UIDE_RST_L UIDE_DIOW_L UIDE_DIOR_L
UIDE_DMACK_L
UIDE_IOCHRDY UIDE_CS0_L UIDE_CS1_L
UIDE_REF
FW_PHY_LREQ
CLKFW_PHY_LCLK
ENET_PHY_TX_EN
ENET_PHY_TX_ER
CLKFW_LINK_PCLK
FW_LINK_LREQ
FW_LINK_CNTL<0> FW_LINK_CNTL<1>
FW_PHY_LPS
FW_LINK_DATA<7>
FW_LINK_DATA<6>
FW_LINK_DATA<5>
FW_LINK_DATA<4>
FW_LINK_DATA<2>
FW_LINK_DATA<0>
FW_LINK_DATA<3>
FW_LINK_DATA<1>
ENET_LINK_TXD<7>
ENET_LINK_TXD<5> ENET_LINK_TXD<6>
ENET_LINK_TXD<4>
ENET_LINK_TXD<3>
ENET_LINK_TXD<2>
ENET_LINK_TXD<0> ENET_LINK_TXD<1>
ENET_LINK_TX_EN
CLKENET_LINK_TX
ENET_LINK_TX_ER
FW_LKON FW_PINT
CLKFW_LINK_LCLK
CLKENET_LINK_RX ENET_RX_DV ENET_RX_ER
ENET_LINK_RXD<0> ENET_LINK_RXD<1>
ENET_LINK_RXD<3>
ENET_LINK_RXD<2>
ENET_LINK_RXD<4> ENET_LINK_RXD<5> ENET_LINK_RXD<6> ENET_LINK_RXD<7> CLKENET_LINK_GBE_REF
ENET_CRS ENET_COL ENET_MDIO ENET_MDC
INT_TST_MONIN_PD
INT_TST_PLLEN_PD
INT_TST_MONOUT_TP
INT_I2C_CLK0 INT_I2C_DATA0
INT_I2C_DATA1
INT_I2C_CLK1
INT_JTAG_TEI
JTAG_ASIC_TRST_L
JTAG_ASIC_TMS
JTAG_ASIC_TCK
JTAG_ASIC_TDO
JTAG_ENET_TDO
INT_RESET_L
INT_PU_RESET_L
CLKENET_LINK_GTX
CLKENET_PHY_GTX
ENET_PHY_TXD<1>
ENET_LINK_TXD<1>
ENET_PHY_TXD<0>
ENET_LINK_TXD<0>
ENET_PHY_TXD<3>
ENET_LINK_TXD<3>
ENET_PHY_TXD<4>
ENET_LINK_TXD<4>
ENET_PHY_TXD<2>
ENET_LINK_TXD<2>
ENET_PHY_TXD<5>
ENET_LINK_TXD<5>
ENET_PHY_TXD<7>
ENET_LINK_TXD<7>
ENET_PHY_TXD<6>
ENET_LINK_TXD<6>
INT_I2C_DATA0
INT_I2C_CLK0
INT_I2C_DATA1
INT_I2C_CLK1
INT_JTAG_TEI
JTAG_ASIC_TRST_L
INT_TST_MONIN_PD
INT_TST_PLLEN_PD
JTAG_ASIC_TDO
JTAG_ENET_TDO
JTAG_ASIC_TMS
JTAG_ASIC_TCK
39
39
39
39
39
39
39
39
23
23
25
25
39
39
39
39
23
23
25
25
39
39
39
39
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
36
37
37
36
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
36
37
36
37
37
37
37
37
37
37
37
37
37
36
37
37
37
37
13
13
14
14
27
27
27
14
27
30
30
36
37 37
37 37
37 37
37 37
37 37
37 37
37 37
37 37
13
13
14
14
27
14
27
27
27
37
24
37
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
38
28
28
27
27
28
37
28
28
28
28
28
28
28
28
28
28
28
13
13
13
13
13
13
13
13
37
27
37
28
28
36
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
13
13
11
11
13
13
13
13
13
13
13
13
9
25
36
27
27 13
27 13
27 13
27 13
27 13
27 13
27 13
27 13
11
11
13
13
13
13
13
13
13
13
13
13
(PLL9)
(PLL7)
(PLL3)
(PLL2)
(PLL1)
VSSA_8
VSSA4
VSSA3
VSSA2
VSSA1
(PLL9)
(PLL7)
(PLL3)
(PLL2)
(PLL1)
VDD15A_8
VDD15A_4
VDD15A_3
VDD15A_2
VDD15A_1
CPU_INT PCIPME
EXTINT12 EXTINT13 EXTINT14 EXTINT15 EXTINT16 EXTINT17
GPIO16
GPIO15
GPIO12
GPIO11
GPIO9
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
VSSU_2
VDDU33_2
VDDU33_1
(6 OF 9)
SCCRTSA
SCCTXDA
SCCDTRA
SCCRXDA SCCGPIOA SCCTRXCA
SCCTXDB
SCCGPIOB SCCTRXCB
SCCRXDB
SCCRTSB
PURPOSE
GENERAL
I/O’S
EXTINT8
EXTINT7
EXTINT6
EXTINT0
INTERRUPTS
EXTINT11
EXTINT4 EXTINT5
EXTINT10
EXTINT9
EXTINT3
EXTINT2
EXTINT1
AUD_DTO
AUD_DTI AUD_SYNC
MOD_DTO
AUD_BITCLK AUD_CLKOUT
IICCLK_2
MOD_SYNC
MOD_DTI
MOD_CLKOUT
IICDATA_2
MOD_BITCLK
IIC
AUDIO/I2S
CLOCKS
XTAL_OUT
PROCSLEEPREQ PENDPROCINT
XTAL_IN
SS_REF_CLK_IN
BUF_REF_CLK_OUT
STOPXTAL
WATCHDOG
PCI_
PCI_
PCI_
VSSU_1
PCI_
USB_VD0_P USB_VD0_N
USB_VD1_P USB_VD1_N
USB_VD2_N
USB_VD2_P
USB_PWRFLT0
USB_PRTPWR0
USB_VD3_N
USB_VD3_P
USB
USB_PRTPWR1 USB_PWRFLT1
USB_VD4_N
USB_VD4_P
USB_VD5_N
USB_VD5_P
USB_PRTPWR2 USB_PWRFLT2
ADJ
BYP GND
OUT
NC
NC
SHDN
IN
CPU0
VDDA
VDD0
VDD1
VDDC
VDDQ
VSS1
VSS0
VSSA
VSSC
VSSQ
LOCK ODSEL
PD*
SDATA
SCLK
FSEL
CLKIN
RESET*
ADDRSEL
REFERENCE DESIGNATOR(S)
BOM OPTION
TABLE_5_HEAD
QTY
DESCRIPTION
PART#
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
TABLE_5_ITEM
PORT B - UNUSED
CBUS_IREQ_L
PORT D - UNUSED
PORT C - LEFT USB
PORT F - MODEM
PORT E - BLUETOOTH
NC
NC
PORT A - RIGHT USB 1
INTERNAL 250K PULL-UP
OUTPUT IMPEDANCE ~18-20OHM
PLACE R68 CLOSE TO INTREPID SIDE
OPEN-DRAIN OUTPUT
VCORE_A/B SEL
VGATE/LOCK INTERRUPT
USB PORT ASSIGNMENTS
VIA
SCK
ACK*
MOSI
REQ*
MISO
POWERBOOK SPARE
FAN PWM
INTERNAL 250K PULL-UP
JTG_TDO_H
MOD_DTI_B_H
MOD_CLKOUT_B_H
MOD_BITCLK_B_H
SIGNAL NAME
4 3 2
0
1
MOD_SYNC_B_H
MOD_DTO_B_H
HWPLL_
TESTMUXSEL
5
OTHERWISE A LOT OF OVERSHOOT/UNDERSHOOT
USB POWER FAULT SIGNALS
CONTRAST PWM
BRIGHTNESS PWM
INT - USB/GPIOS/I2S
INTERNAL 250K PULL-DOWN
CRYSTAL LOAD CAPACITANCE IS 16PF
+3V_MAIN
2
1
C97
10UF
CERM 805
20%
6.3V
21
R111
5%
1/16W
MF
402
100K
+3V_MAIN
2
1
C85
0.1UF
CERM
20% 10V
402
2
1
C84
0.01UF
20% CERM
16V 402
21
R50
402
22
1/16W
MF
5%
21
R67
402
22
5% MF
1/16W
21
R91
402
22
5% MF
1/16W
72
RP8
47
5%
1/16W
SM1
63
RP8
1/16W
SM1
5%
47
54
RP8
47
5%
1/16W
SM1
81
RP8
47
SM1
1/16W
5%
21
R90
402
22
1/16W
MF
5%
V15
U4
AT7
R8
R9
AH29
AK18
AJ16
AJ13
AA15
U8
T8
AG29
P8 N8
K5 L5
M7 M8
H2 H1
G2 G1
L8 L7
N7
J1
K4
M5
J2
J4
AN7
K9
AR4
AF9
AM5
AT4
AG10
AG11
AL5
AN3
AP4
AG9
AF10
AT6
AN8
AJ18
AJ17
AJ12
AA16
AJ7
R1
R2 T4
P1
V8
AH8
AL4
H4
L9
H5
J8
F2
J7
K7
F1
K8
J5
E1
G5
C32
D31
G30
E31
A33
B33
D34
C33
G4
H7
E2
D1
F4
J9
E30
B32
E34
F33
D30
U15
T5
R4 R7
R5
P2
U45
INTREPID-REV2.1
BGA
CRITICAL
+3V_SLEEP
21
R614
INTREPID_USB
402
MF
1/16W
5%
24
2
1
R115
402
1/16W MF
5%
15K
21
R609
INTREPID_USB
24
5%
1/16W
MF
402
21
R89
24
5%
1/16W
MF
402
INTREPID_USB
21
R80
402
MF
1/16W
5%
24
INTREPID_USB
2
1
C198
0.22UF
CERM
6.3V
20%
402
21
R155
402
4.7
5%
1/16W
MF
2
1
C148
0.22UF
CERM
6.3V
20%
402
21
R125
MF
1/16W
5%
4.7
402
2
1
C182
0.22UF
CERM
6.3V
20%
402
21
R156
4.7
MF
1/16W
5%
402
2
1
C353
0.22UF
CERM
6.3V
20%
402
2
1
R114
402
5%
1/16W
MF
15K
2
1
C200
0.22UF
CERM
6.3V
20%
402
21
R244
MF
1/16W
5%
402
4.7
21
R168
MF
1/16W
5%
4.7
402
21
Y1
18.432M
CRITICAL
8X4.5MM-SM
2 1
R622
1/16W
10M
MF
5%
402
NO STUFF
2
1
C140
22PF
402
CERM
5% 50V
2
1
C15
402
CERM
50V
5%
22PF
21
R49
1/16W
NO STUFF
402
0
5% MF
1
2
3
J1
U.FL-R_SMT
F-ST-SM
NO STUFF
CRITICAL
2
1
R28
402
NO STUFF
5%
51
1/16W MF
2
1
R632
0
402
MF
1/16W
5%
2
1
C433
1UF
603
CERM
10V
20%
2
1
R277
402
68.1K
1%
1/16W
MF
2
1
R278
402
15.8K
1%
1/16W
MF
2
1
C419
10UF
805
20%
6.3V CERM
21
R291
603
5%
1/16W
0
MF
NO STUFF
21
R264
5%
1/16W
MF
603
0
+2_5V_MAIN
+1_8V_MAIN
5
1
7
6
8
4
3
2
U7
LT1962-ADJ
MSOP
CRITICAL
2
1
C424
CERM
0.01UF
402
20% 16V
12
R7
402
5%
1/16W
MF
10K
12
R113
402
10K
MF
1/16W
5%
1
2
R29
402
5% 1/16W MF
1K
1
2
R102
402
5% 1/16W MF
1K
36
RP48
10K
5%
1/16W
SM1
45
RP7
10K
5%
1/16W
SM1
27
RP46
10K
5%
1/16W
SM1
18
RP46
10K
5%
1/16W
SM1
18
RP47
5%
1/16W
SM1
10K
36
RP47
SM1
10K
1/16W
5%
81
RP7
5%
1/16W
SM1
10K
27
RP47
SM1
5%
1/16W
10K
81
RP48
5%
1/16W
SM1
10K
54
RP6
10K
SM1
1/16W
5%
72
RP29
SM1
5%
1/16W
10K
54
RP29
5%
1/16W
SM1
10K
72
RP51
5%
1/16W
SM1
10K
45
RP47
SM1
5%
1/16W
10K
63
RP46
5%
1/16W
10K
SM1
54
RP51
10K
SM1
1/16W
5%
81
RP51
10K
1/16W
5%
SM1
81
RP29
10K
SM1
1/16W
5%
81
RP1
5%
1/16W
SM1
10K
72
RP6
10K
SM1
1/16W
5%
54
RP48
SM1
10K
1/16W
5%
63
RP6
10K
SM1
1/16W
5%
72
RP48
10K
SM1
1/16W
5%
63
RP29
5%
1/16W
10K
SM1
81
RP24
5%
1/16W
10K
SM1
63
RP7
5%
1/16W
10K
SM1
81
RP6
5%
1/16W
10K
SM1
1
2
R100
75
SSCG
MF
1/16W
5%
402
54
RP46
10K
1/16W
5%
SM1
54
RP1
5%
10K
1/16W
SM1
63
RP1
5%
SM1
1/16W
10K
72
RP1
SM1
5%
1/16W
10K
21
R636
5%
402
0
1/16W
MF
SSCG
2
1
R638
1/16W
5%
10K
402
MF
2
1
C691
0.1UF
SSCG
20% 10V CERM 402
2
1
C692
1UF
603
20% 10V CERM
SSCG
2
1
C698
CERM
0.1UF
402
10V
20%
SSCG
2
1
L22
SSCG
SM-1
400-OHM-EMI
+3V_MAIN
2
1
L18
400-OHM-EMI
SM-1
SSCG
2
1
C686
0.1UF
SSCG
402
CERM
10V
20%
+2_5V_MAIN
21
R281
402
SSCG
MF
1/16W
0
5%
2
1
R656
402
10K
5% 1/16W MF
NO STUFF
2
1
R682
10K
MF
5%
402
1/16W
NO STUFF
63
RP51
10K
1/16W
5%
SM1
15
6
11
19
7
18
5
12
10
1
8
9
17
13
4
2
3
16
20
14
U42
CRITICAL
TSSOP
SSCG
CY28512D
21
R634
SSCG
5%
33
402
MF
1/16W
2
1
R625
402
10K
SSCG
1/16W
5% MF
2
1
R631
5%
0
MF
402
1/16W
NO STUFF
+3V_SLEEP
72
RP56
47
1/16W
SM1
5%
63
RP56
1/16W
5%
47
SM1
81
RP56
MOD_BITCLK
47
5%
SM1
1/16W
54
RP56
SM1
1/16W
5%
47
2
1
R701
NEC_USB
5%
10K
1/16W MF 402
2
1
R708
NEC_USB
402
MF
1/16W
5%
10K
2
1
R699
NEC_USB
402
MF
1/16W
10K
5%
2
1
R707
NEC_USB
5%
10K
1/16W MF 402
21
R698
0
5%
1/16W
MF
402
21
R720
402
MF
1/16W
5%
10K
21
R285
402
MF
1/16W
5%
0
NO STUFF
21
R604
0
5%
1/16W
MF
402
21
R608
402
MF
1/16W
5%
0
INT_GPIO0
1
2
L1
FERR-EMI-100-OHM
SM
Y1
ALT FOR SIWARD
197S0035197S0004
01
051-6598
14 44
R100
RES,METAL FILM,10 K OHM,5,1/16W,0402,SM
NO_SSCG
116S1104
1
CG_FSEL
SYSTEM_CLK_EN
CG_SYSCLK_EN
JTAG_ASIC_TDO
CG_SYSCLK_EN
INT_EXTINT12_PU
CLK18M_INT_XIN
CG_FSEL
CG_ADDRSEL
SND_HW_RESET_L
INT_MOD_DTO_UF
INT_MOD_BITCLK_UF INT_MOD_CLKOUT_UF
SND_SYNC
INT_MOD_SYNC_UF
INT_MOD_SYNC_UF
FW_PHY_PD_INT
CG_RESET_L
COMM_SHUTDOWN
INT_MOD_BITCLK_UF
INT_MOD_DTI_UF
INT_GPIO9_PU
INT_EXTINT10_PU
INT_EXTINT16_PU
INT_EXTINT11_PU
INT_EXTINT13_PU
INT_EXTINT3_PU
INT_MOD_DTO_UF
PMU_INT_NMI
PMU_INT_L
INT_GPIO12_PU
PMU_REQ_L
CBUS_INT_L
INT_MOD_CLKOUT_UF
INT_GPIO15_PU
INT_GPIO1_PU
INT_EXTINT14_PU
USB_OC_CD_L
COMM_RING_DET_L
INT_EXTINT8_PU
USB2_PCI_INT_L
USB_PWREN_AB_L
USB_PWREN_CD_L
USB_OC_EF_L
USB_OC_AB_L
USB_PWREN_EF_L
AIRPORT_PCI_INT_L
MAIN_RESET_L
INT_REF_CLK_IN
INT_GPIO1_PU
USB_DBP
INT_EXTINT8_PU
CG_LOCK
+1_5V_INTREPID_PLL
SND_SCLK
INT_SND_SYNC
INT_SND_TO_AUDIO
INT_SND_SCLK
INT_SND_CLKOUT
SND_CLKOUT
MOD_SYNC
MOD_CLKOUT
MOD_DTO
USB_OC_EF_L
INT_MOD_DTI
INT_AUDIO_TO_SND
USB_OC_CD_L
USB_DFM
USB_PWREN_EF_L
USB_DBM
USB_DCP
SND_TO_AUDIO
+1_5V_INTREPID_PLL4
+1_5V_INTREPID_PLL8
CLK18M_INT_XOUT
CLK18M_XTAL_IN
INT_EXTINT12_PU INT_EXTINT13_PU INT_EXTINT14_PU
INT_EXTINT16_PU USB2_PCI_INT_L
SND_HP_SENSE_L
MPIC_CPU_INT_L
PMU_PME_L
INT_ENET_RST_L
INT_GPIO15_PU
SND_AMP_MUTE_L
USB_DFP
USB_DEM
USB_DEP
USB_PWREN_CD_L
USB_DDM
USB_DDP
USB_PWREN_AB_L
USB_DCM
USB_DAP USB_DAM
PMU_TO_INT
PMU_CLK
COMM_RXD
COMM_TRXC
INT_REF_CLK_IN
INT_REF_CLK_OUT
INT_WATCHDOG_L
SYSTEM_CLK_EN
INT_PEND_PROC_INT
INT_PROC_SLEEP_REQ_L
INT_EXTINT11_PU
PMU_INT_NMI
ENET_ENERGY_DET AIRPORT_PCI_INT_L CBUS_INT_L
SND_LIN_SENSE_L
INT_EXTINT3_PU
PMU_INT_L
INT_GPIO9_PU
SND_HW_RESET_L
INT_GPIO12_PU
PMU_REQ_L
PMU_ACK_L
PMU_FROM_INT
COMM_DTR_L
COMM_GPIO_L
COMM_RTS_L
COMM_TXD_L
+1_5V_INTREPID_PLL1
+1_5V_INTREPID_PLL3
+1_5V_INTREPID_PLL2
+3V_INTREPID_USB
LT1962_INT_ADJ
LT1962_INT_BYP
INT_EXTINT10_PU
VCORE_VGATE
VCORE_VGATE
CG_CLKOUT
INT_REF_CLK_OUT
INT_I2C_DATA1
LTC1962_INT_VIN
+3V_CG_PLL_MAIN
INT_I2C_DATA2
INT_I2C_CLK2
USB_OC_AB_L
MODEM_USB_DP
MODEM_USB_DM
BT_USB_DP
USB_DEP
BT_USB_DM
USB_DEM
USB_DFP
USB_DFM
USB_DDP
USB_DDM
USB_D1P
USB_D1MUSB_DCM
USB_DBP
USB_D2P
USB_D2M
USB_DCP
USB_DBM
USB_DAM
USB_DAP
AGP_INT_L
COMM_RING_DET_L
COMM_RESET_L
SND_HP_MUTE_L
FW_PHY_PD_INT
FW_PHY_PD
+2_5V_CG_MAIN
INT_I2C_CLK1
CLK18M_INT_EXT
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