GND
DA10
SEL
DH19
DH18
DH17
DH16
DH15
DH14
DH13
DH12
DH11
DH10
DH9
DH8
DH7
DH6
DH5
DH4
DH3
DH2
DH1
DH0
DA19
DA18
DA17
DA16
DA15
DA14
DA13
DA12
DA11DB0*
DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
DB19*
DB18*
DB17*
DB16*
DB15*
DB14*
DB13*
DB12*
DB11*
DB10*
DB9*
DB8*
DB7*
DB6*
DB5*
DB4*
DB3*
DB2*
DB1*
VDD
GND
DA10
SEL
DH19
DH18
DH17
DH16
DH15
DH14
DH13
DH12
DH11
DH10
DH9
DH8
DH7
DH6
DH5
DH4
DH3
DH2
DH1
DH0
DA19
DA18
DA17
DA16
DA15
DA14
DA13
DA12
DA11DB0*
DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
DB19*
DB18*
DB17*
DB16*
DB15*
DB14*
DB13*
DB12*
DB11*
DB10*
DB9*
DB8*
DB7*
DB6*
DB5*
DB4*
DB3*
DB2*
DB1*
VDD
GND
DA10
SEL
DH19
DH18
DH17
DH16
DH15
DH14
DH13
DH12
DH11
DH10
DH9
DH8
DH7
DH6
DH5
DH4
DH3
DH2
DH1
DH0
DA19
DA18
DA17
DA16
DA15
DA14
DA13
DA12
DA11DB0*
DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
DB19*
DB18*
DB17*
DB16*
DB15*
DB14*
DB13*
DB12*
DB11*
DB10*
DB9*
DB8*
DB7*
DB6*
DB5*
DB4*
DB3*
DB2*
DB1*
VDD
GND
DA10
SEL
DH19
DH18
DH17
DH16
DH15
DH14
DH13
DH12
DH11
DH10
DH9
DH8
DH7
DH6
DH5
DH4
DH3
DH2
DH1
DH0
DA19
DA18
DA17
DA16
DA15
DA14
DA13
DA12
DA11DB0*
DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
DB19*
DB18*
DB17*
DB16*
DB15*
DB14*
DB13*
DB12*
DB11*
DB10*
DB9*
DB8*
DB7*
DB6*
DB5*
DB4*
DB3*
DB2*
DB1*
VDD
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
MEM_MUXSEL_H<1> AND MEM_MUXSEL_L<1> ARE ACTIVE HIGH
ADDED 0 OHM RESISTORS IN CASE POLARITY IS WRONG
SEL = LOW; HOST = B PORT; A PORT = 100OHM TO GND
SEL = HIGH; HOST = A PORT; B PORT = 100OHM TO GND
16BIT 2:1 DDR MUXES
BIT 48..63BIT 32..47
BIT 16..31
BIT 0..15
MEM_MUXSEL_H<0> AND MEM_MUXSEL_L<0> ARE ACTIVE LOW
2
1
C742
402
CERM
10V
20%
0.1UF
2
1
C748
20%
10V
CERM
402
0.1UF
2
1
C753
402
CERM
10V
20%
0.1UF
2
1
C737
402
CERM
10V
20%
0.1UF
2
1
C738
20%
10V
CERM
402
0.1UF
2
1
C736
402
CERM
10V
20%
0.1UF
2
1
C752
402
CERM
10V
20%
0.1UF
2
1
C747
20%
10V
CERM
402
0.1UF
2
1
C741
402
CERM
10V
20%
0.1UF
2
1
C743
402
CERM
10V
20%
0.1UF
2
1
C727
402
CERM
10V
20%
0.1UF
2
1
C735
402
CERM
10V
20%
0.1UF
F8F3E8
E3
H6H5G9G2D9D2C6
C5
E2
C2
B2
B3
B5
B6
B8
B9
C9
E9
F9
H9
J9
J8
J6
J5
J3
J2
H2
F2
E1
C1
A1
A3
A4
A6
B7
A9
B10
D10
F10
H10
K10
K8
K7
K5
J4
K2
J1
G1
D1
B1
A2
B4
A5
A7
A8
A10
C10
E10
G10
J10
K9
J7
K6
K4
K3
K1
H1
F1
U13
CBTV4020
BGA
CRITICAL
F8F3E8
E3
H6H5G9G2D9D2C6
C5
E2
C2
B2
B3
B5
B6
B8
B9
C9
E9
F9
H9
J9
J8
J6
J5
J3
J2
H2
F2
E1
C1
A1
A3
A4
A6
B7
A9
B10
D10
F10
H10
K10
K8
K7
K5
J4
K2
J1
G1
D1
B1
A2
B4
A5
A7
A8
A10
C10
E10
G10
J10
K9
J7
K6
K4
K3
K1
H1
F1
U12
CBTV4020
BGA
CRITICAL
F8F3E8
E3
H6H5G9G2D9D2C6
C5
E2
C2
B2
B3
B5
B6
B8
B9
C9
E9
F9
H9
J9
J8
J6
J5
J3
J2
H2
F2
E1
C1
A1
A3
A4
A6
B7
A9
B10
D10
F10
H10
K10
K8
K7
K5
J4
K2
J1
G1
D1
B1
A2
B4
A5
A7
A8
A10
C10
E10
G10
J10
K9
J7
K6
K4
K3
K1
H1
F1
U10
CRITICAL
BGA
CBTV4020
F8F3E8
E3
H6H5G9G2D9D2C6
C5
E2
C2
B2
B3
B5
B6
B8
B9
C9
E9
F9
H9
J9
J8
J6
J5
J3
J2
H2
F2
E1
C1
A1
A3
A4
A6
B7
A9
B10
D10
F10
H10
K10
K8
K7
K5
J4
K2
J1
G1
D1
B1
A2
B4
A5
A7
A8
A10
C10
E10
G10
J10
K9
J7
K6
K4
K3
K1
H1
F1
U9
CRITICAL
BGA
CBTV4020
21
R242
NO STUFF
5%
0
402
MF
1/16W
21
R252
NO STUFF
1/16W
MF
402
0
5%
21
R243
1/16W
MF
402
0
5%
21
R239
5%
0
402
MF
1/16W
051-6598
01
10 44
+2_5V_INTREPID+2_5V_INTREPID
+2_5V_INTREPID
+2_5V_INTREPID
RAM_DATA_A<57>
MEM_DQM<7>
RAM_DATA_A<56>
RAM_DATA_A<48>
RAM_DATA_A<50>
RAM_DATA_A<51>
RAM_DATA_A<49>
RAM_DATA_A<53>
RAM_DATA_A<52>
RAM_DATA_A<54>
RAM_DATA_A<55>
RAM_DQS_A<6>
RAM_DQM_A<6>
RAM_MUXSEL_H
MEM_DATA<63>
MEM_DQS<7>
MEM_DATA<62>
MEM_DATA<60>
MEM_DATA<61>
MEM_DATA<57>
MEM_DATA<58>
MEM_DATA<59>
MEM_DATA<56>
MEM_DQM<6>
MEM_DATA<55>
MEM_DATA<54>
MEM_DQS<6>
MEM_DATA<52>
MEM_DATA<53>
MEM_DATA<50>
MEM_DATA<49>
MEM_DATA<51>
RAM_DQM_A<7>
MEM_DATA<48>
RAM_DQS_A<7>
RAM_DATA_A<62>
RAM_DATA_A<63>
RAM_DATA_A<60>
RAM_DATA_A<61>
RAM_DATA_A<59>
RAM_DATA_A<58>
RAM_DATA_B<59>
RAM_DATA_B<60>
RAM_DATA_B<61>
RAM_DATA_B<62>
RAM_DATA_B<63>
RAM_DQS_B<7>
RAM_DQM_B<7>
RAM_DATA_B<53>
RAM_DATA_B<54>
RAM_DATA_B<55>
RAM_DATA_B<51>
RAM_DATA_B<52>
RAM_DQS_B<6>
RAM_DQM_B<6>
RAM_DATA_B<56>
RAM_DATA_B<57>
RAM_DATA_B<58>
RAM_DATA_B<50>
RAM_DATA_B<49>
RAM_DATA_B<48>RAM_DATA_A<41>
MEM_DQM<5>
RAM_DATA_A<40>
RAM_DATA_A<32>
RAM_DATA_A<34>
RAM_DATA_A<35>
RAM_DATA_A<33>
RAM_DATA_A<37>
RAM_DATA_A<36>
RAM_DATA_A<38>
RAM_DATA_A<39>
RAM_DQS_A<4>
RAM_DQM_A<4>
RAM_MUXSEL_H
MEM_DATA<47>
MEM_DQS<5>
MEM_DATA<46>
MEM_DATA<44>
MEM_DATA<45>
MEM_DATA<41>
MEM_DATA<42>
MEM_DATA<43>
MEM_DATA<40>
MEM_DQM<4>
MEM_DATA<39>
MEM_DATA<38>
MEM_DQS<4>
MEM_DATA<36>
MEM_DATA<37>
MEM_DATA<34>
MEM_DATA<33>
MEM_DATA<35>
RAM_DQM_A<5>
MEM_DATA<32>
RAM_DQS_A<5>
RAM_DATA_A<46>
RAM_DATA_A<47>
RAM_DATA_A<44>
RAM_DATA_A<45>
RAM_DATA_A<43>
RAM_DATA_A<42>
RAM_DATA_B<43>
RAM_DATA_B<44>
RAM_DATA_B<45>
RAM_DATA_B<46>
RAM_DATA_B<47>
RAM_DQS_B<5>
RAM_DQM_B<5>
RAM_DATA_B<37>
RAM_DATA_B<38>
RAM_DATA_B<39>
RAM_DATA_B<35>
RAM_DATA_B<36>
RAM_DQS_B<4>
RAM_DQM_B<4>
RAM_DATA_B<40>
RAM_DATA_B<41>
RAM_DATA_B<42>
RAM_DATA_B<34>
RAM_DATA_B<33>
RAM_DATA_B<32>
RAM_DATA_A<25>
MEM_DQM<3>
RAM_DATA_A<24>
RAM_DATA_A<16>
RAM_DATA_A<18>
RAM_DATA_A<19>
RAM_DATA_A<17>
RAM_DATA_A<21>
RAM_DATA_A<20>
RAM_DATA_A<22>
RAM_DATA_A<23>
RAM_DQS_A<2>
RAM_DQM_A<2>
RAM_MUXSEL_L
MEM_DATA<31>
MEM_DQS<3>
MEM_DATA<30>
MEM_DATA<28>
MEM_DATA<29>
MEM_DATA<25>
MEM_DATA<26>
MEM_DATA<27>
MEM_DATA<24>
MEM_DQM<2>
MEM_DATA<23>
MEM_DATA<22>
MEM_DQS<2>
MEM_DATA<20>
MEM_DATA<21>
MEM_DATA<18>
MEM_DATA<17>
MEM_DATA<19>
RAM_DQM_A<3>
MEM_DATA<16>
RAM_DQS_A<3>
RAM_DATA_A<30>
RAM_DATA_A<31>
RAM_DATA_A<28>
RAM_DATA_A<29>
RAM_DATA_A<27>
RAM_DATA_A<26>
RAM_DATA_B<27>
RAM_DATA_B<28>
RAM_DATA_B<29>
RAM_DATA_B<30>
RAM_DATA_B<31>
RAM_DQS_B<3>
RAM_DQM_B<3>
RAM_DATA_B<21>
RAM_DATA_B<22>
RAM_DATA_B<23>
RAM_DATA_B<19>
RAM_DATA_B<20>
RAM_DQS_B<2>
RAM_DQM_B<2>
RAM_DATA_B<24>
RAM_DATA_B<25>
RAM_DATA_B<26>
RAM_DATA_B<18>
RAM_DATA_B<17>
RAM_DATA_B<16>
RAM_DATA_A<9>
MEM_DQM<1>
RAM_DATA_A<8>
RAM_DATA_A<0>
RAM_DATA_A<2>
RAM_DATA_A<3>
RAM_DATA_A<1>
RAM_DATA_A<5>
RAM_DATA_A<4>
RAM_DATA_A<6>
RAM_DATA_A<7>
RAM_DQS_A<0>
RAM_DQM_A<0>
RAM_MUXSEL_L
MEM_DATA<15>
MEM_DQS<1>
MEM_DATA<14>
MEM_DATA<12>
MEM_DATA<13>
MEM_DATA<9>
MEM_DATA<10>
MEM_DATA<11>
MEM_DATA<8>
MEM_DQM<0>
MEM_DATA<7>
MEM_DATA<6>
MEM_DQS<0>
MEM_DATA<4>
MEM_DATA<5>
MEM_DATA<2>
MEM_DATA<1>
MEM_DATA<3>
RAM_DQM_A<1>
MEM_DATA<0>
RAM_DQS_A<1>
RAM_DATA_A<14>
RAM_DATA_A<15>
RAM_DATA_A<12>
RAM_DATA_A<13>
RAM_DATA_A<11>
RAM_DATA_A<10>
RAM_DATA_B<11>
RAM_DATA_B<12>
RAM_DATA_B<13>
RAM_DATA_B<14>
RAM_DATA_B<15>
RAM_DQS_B<1>
RAM_DQM_B<1>
RAM_DATA_B<5>
RAM_DATA_B<6>
RAM_DATA_B<7>
RAM_DATA_B<3>
RAM_DATA_B<4>
RAM_DQS_B<0>
RAM_DQM_B<0>
RAM_DATA_B<8>
RAM_DATA_B<9>
RAM_DATA_B<10>
RAM_DATA_B<2>
RAM_DATA_B<1>
RAM_DATA_B<0>
RAM_MUXSEL_L
MEM_MUXSEL_L<1>
RAM_MUXSEL_H
MEM_MUXSEL_H<1>
RAM_MUXSEL_L
MEM_MUXSEL_L<0>
RAM_MUXSEL_H
MEM_MUXSEL_H<0>
38 38
38
38
16 16
16
16
15 15
15
15
10 10
10
10
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36 36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36 36
36 36
36 36
36 36
9 9
9
9
11
9
11
11
11
11
11
11
11
11
11
11
11
10
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
11
9
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11 11
9
11
11
11
11
11
11
11
11
11
11
11
10
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
11
9
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
9
11
11
11
11
11
11
11
11
11
11
11
10
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
11
9
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
9
11
11
11
11
11
11
11
11
11
11
11
10
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
11
9
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
10
9
10
9
10
9
10
9