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SIZE
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NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
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67
8
12
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78
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C
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REV.
APPLE COMPUTER INC.
SCALE
NONE
PRODUCTION RELEASE(Version C)
PRODUCTION RELEASE
08/18/03 - Change CPU VCORE setting for BEST configuration to: 1.335V(High)->1.080V(Low) (p. 33)
08/07/03 - Change CPU VCORE setting for both BEST and BETTER configurations again (p. 33)
Add RC at ADT7460 power rail for noise isolation (p.25)
Change the +2_5V_sleep FET to reduce Voltage drop on the rail (p.34)
08/05/03 - Change +3V/5V ITH compensation and No-Stuff Feed Forward Caps (p. 32)
Change CPU VCORE setting for both BEST and BETTER configurations (p. 33)
07/06/03 - Change R97 & R98 to 0402 package (p.33)
07/28/03 - Change BOM option for C51,C52,C77,C78,C91,C92,C111 to 8.2uF Panasonic AL cap only (p. 34)
06/12/03 - Change CBUS & USB2 REQ LINE Pullup to +3V_MAIN (p.12)
Add SI1162 DVI transmitter to prevent leakage from DVI connector to the system (p.19&20)
Isolate THERM# signal at ADT7460 by using double inverters for THERM_L_OC (p.25)
Change U34 to Mitsumi MM1571J part for ATI PLL 1.8V rail(P 21)
Connect C847 at R160.1 (p.13)
06/06/03 - Add four 0ohm jumper, in case there is no sw support for the multi-stage VCore (p.38)
Change HD_DMACK_L pullup R213 to 10K (p.24)
Add C847, C851 & C852 at ENET CLK for EMC (p.13 & 26)
Stuff R288 for Cypress Clk chip (p.14)
Remove SH2 EMI spring at CHGND5 (p.23)
Add additional PWR/GND pins at J17 for R-USB board (p.25)
Change PWM_L Fan input (both L&R Fans) to +5V_SLEEP pull-up (p.25)
Change FW PHY to production part (P 26)
Add C853 1000pF cap at Q64 (p.30)
Remove redundant pullup R601 for THERM_L_OC (p.29)
GPU Vcore on/off timimg (p.20)
Add C848 150uF cap at J3 for +5V_MAIN USB2 power (p.25)
06/03/03 - Add CPU Core Voltage offset option circuit (p.33)
05/30/03 - Connect SLEEP_LED_DGND to digital ground instead of CHGND5 (p.23)
Change Q34 to FDS3672 (p.28)
Change Q82 pin#4 connection to system digital GND (p.33)
Add 0 ohm at USB AVSS GND (p.17)
12/20/02 - Removed LT4210 from FireWire port power (p.28)
Add Sense Resistor to Vcore power rail, remove one 220uF cap <back to EVTA design> (P 33)
04/30/03 - No stuff R676 to prevent +3V rail leakage (P 33)
04/16/03 - Add FW Port ShutDown/PowerOn Circuit (P 28)
Add 0402 Res between ATI PVDD/TPVDD rail and 10uF caps for stability purpose (P 21)
SWAP the ADT7460 Temperature Sense pair (P 25)
04/11/03 - Change FW Schottky Diode to a 3A part 371S0159 (P 28)
Changed INT_MOD_SYNC, INT_MOD_DTI and INT_MOD_BITCLK to pulldowns per ERS [LA clk not used] (p.14)
04/25/03 - Change C826 to 0.01uF 50V Cap (P 30)
05/02/03 - L45,L46,L47 is using Common Mode Choke TDK ACM2012D Part, will replace with ACM2012H Part if available (P 22)
04/24/03 - Remove +3V_CBUS_SLEEP and U5, use +3V_SLEEP directly (P 14,18,24)
04/21/03 - Add 12 ICT JTAG TEST PADs (P 39)
04/17/03 - Change 3V/5V inductors (152S0137) L61 & L62 (P 32)
04/23/03 - Invert ATI GPIO15 signal, no stuff pull-up resistor (P 20)
Add 90ohm common mode choke at TMDS data <0..2> pairs (P 22)
02/13/03 - Add C825 (p.30)
EVT ENCLOSURE RELEASE
Add circuits to prevent start-up Headphone POP (P 25)
Add Mitsumi MM1571J regulator to provide 1.8V TPVDD (P 21)
Remove D34 RS3AB (P 30)
Change all 1210 4.7uF to 1206 4.7uF Cap (138S0531) (various pages)
Separate +3V and +5V traces running from 3/5V supply to 40Pin LIO connector (P 25 & 32)
03/13/03 - Change 3-P FAN connectors to 4-P (p.25)
Add 10-Pin ELCO connector for Serial Debug Interface (P 25)
9/18/02 - Changed battery connector back to P84 part (p.29)
Added quad voltage circuit for bus slewing architecture (p.32)
8/27/02 - Changed main battery connector to BP24067-R1, which is close to final (p.29)
02/17/03 - Rename all Reference Designators
Add PU at PMU_SLEEP_LED_L for LMU (p.23)
Remove Memory MUX 0ohm Resistors (p.10)
CHGND1 & CHGND2 (P 4 & 22)
Add C826 at U3 RS- pin (P 30)
Change D3 to 1N914 PN Junction Diode(P 31)
03/31/03 - Change AGPTEST Pull-up to 47ohm (it was 40ohm) (P 20)
04/08/03 - Add SOFT MODEM support (P 14 & 25)
Change airline detect to 13.1V or greater, R40 and R690 to 97.6K ohm (P 30 & 31)
Change all 6 VCORE Caps to 220uF Al Poly Cap 128S0024 (P 33)
Change the I2C Pull-up for Sound/Modem to 1K ohm (P 14)
Added +PBUS current limiting circuit, removed battery charging current limit circuit (p.30)
Changed FW_PC_PD, FW_PC_PU resistors to 5% (p.27)
Added damping resistor option to LMU crystal (p.23)
Changed SMBus pullups to 7.15K, 1% as per iBooks/P84 [involved component net swaps] (p.29)
Removed temporary P84 constraints and finished up AGP clock changes (p.12,34)
Added 10K pullup to CG_ADDRSEL and 10K pulldown to CG_FSEL on CY28512 (p.14)
Combine Q35 and Q36 into a Dual Package Part (P 22)
Change PBUS L69 and VCORE L71 Inductor (P 31 & 33)
Change stuffing option for clock slewing & PLL5 (p.14)
Removed USB overcurrent protection [to be placed on other boards] (p.18)
9/17/02 - Numerous changes to stay in sync with P84 (all)
Change ATI M10 GPIO8 to Pull-down (p.20)
EVT RELEASE (continue)
Updated PCI source clock and internal spreading straps (p.8)
12/16/02 - Removed hole from FireWire ground pad (p.27)
Replaced all 132S1061 [1uF,0805,10V,20%] with 132S0046 [1uF,0603,10V,20%] (p.14,15,27,30,33,34)
Updated 1.5V/2.5V switcher BOM to stay in sync with P84 [FET change and current limits] (p.34)
Added caps to FW ESD circuit that were missed (p.28)
Changed MAX4172 power source to save current on battery [per P84] (p.30)
Swapped R443 and R444 values to ensure Vgs < -4.5V (p.28)
01/08/03 - Added 2N7002 circuits to ensure speakers are muted during power-up (p.25)
Renamed R2000 to R799, R2001 to R802, R2002 to R803 (p.25)
Renamed USB OCI/PPON signals for left/right ports (p.17,39)
Stuffed USB OCI RC filters for 0 time constant [due to new port current limiters] (p.17)
Renamed line-in and headphone sense lines to reflect active low signals (p.14,25.39)
Removed RC glitch filter on CPU_DRDY_L (p.5,36)
Added diodes to OR +5V_SLEEP into FW PHY power supply (p.27)
Change MATCHED_DELAY to 50 for all TMDS DIFF PAIR (p.37)
Added wireless RF_DISABLE_L pullup and AIRPORT_CLKRUN_L pulldown (p.24)
Updated GPU VCore to stay in sync with P84 ["jitter" improvement] (p.20)
Added 0 ohm Rs to make 2_5V Intrepid rail hot or cold (p.15.16,38)
Added F10,F20 as placeholders and experiment guides (p.28)
Added alternate chassis gnd connection for sleep LED (p.23)
Added decoupling cap to PMU reset OR gates (p.29)
Updated SSCG/NO_SSCG BOM options (p.14)
Added FireWire B ESD protection circuits (p.28)
Removed redundancy in DDR memory constraints (p.35)
NO STUFFed entire 1.5V LDO circuit (p.15)
11/05/02 - Added 6 decoupling caps to CPU_VCORE_SLEEP (p.5)
10/23/02 - Changed LMU/sleep LED interface per p84 (p.23)
10/16/02 - Implemented new FW power switch and current limit (p.28)
DDR memory connector renamed to J25 (p.11)
Renamed Vcore VID nets to be consistent with P84 (p.33)
Changed to P84 dual channel LVDS connector to reduce I2R cable losses(p.22)
Changed LMU JTAG/I2C pinout/pullup/pulldown strategy per P84 (p.23)
Removed unintentional extra pulldown resistor at Intrepid (p.14)
9/19/02 - Removed unnecessary battery FETs [due to 3S only design] (p.29)
Removed second fuse from FW ports [single fuse provides adequate power] (p.27)
12/26/02 - Updated CPU p/ns to production p/ns (p.5)
11/25/02 - Renamed all components (all pages)
11/26/02 - Removed chokes from 1394b data pairs (p.27,28)
11/13/02 - Removed LMU and associated circuitry (p.23)
Added ADT7460 hookups to GPU thermal diode (p.21,25)
10/31/02 - Removed MLB ALS (p.23)
10/28/02 - Added FW thermal pad ground hole back in (p.27)
Renamed FW low voltage power rails (p.27,37)
Added 2 functional test points to wireless connector (p.24,38)
Pinned out modem connector (p.25)
Pinned out right USB connector (p.25)
Pinned out audio connector (p.25)
Changed fan FETs to SI3446DV per P84 (p.25)
Changed FW PHY pin DS1 to pullup to make Port 1 1394a only (p.27)
Added A29 adapter detection circuit (p.29)
Added 1K pulldown and net FW_PD2 to FW PHY (p.27)
Changed BBANG_HRESET_L pullup to 3V_SLEEP (p.6)
Removed FW_LKON from Intrepid EXTINT3 [no longer used], pullup added (p.14)
Changed INT_TST_PLLEN_PD to pulldown only [LA clk not used] (p.13)
Added 0603 resistors as shorting pads for power up and reset (p.23)
Added stuffing options to power fans off 3V or 5V (p.25)
10/01/02 - Removed Intrepid 1.x specific circuitry (p.13)
Corrected holes and chassis gnds (p.4,all)
Changed Y6 to smaller form-factor crystal (p.26)
Modified chassis gnds on some components (all)
Changed to Q11 adpater detection scheme (p.28)
8/30/02 - Changed to low profile 32.768kHz crystal for PMU (p.28)
Added 5 bypass caps to each SO-DIMM connector (p.11)
Removed 5 bypass caps for +2_5V_MAIN at Intrepid (p.16)
Changed right USB board connector to 16 pin Hirose connector (p.26)
8/10/02 - Added USB 2.0 (p.18)
Replaced processor with 360 pin Apollo (p.5,6)
7/24/02 - Added FETs between battery and PBUS rails for airline power (p.29)
Added P59 SO-DIMM connector as placeholder (p.12)
Changed PBUS holdup caps to P59 electrolytic cans (p.30)
Changed J9 to 10 pin Elco connector for modem (p.25)
Added P59 LVDS connector as placeholder (p.22)
REVISION HISTORY
7/23/02 - Removed L3 (p.8)
Changed LIO board connector to 40 pin Molex connector (p.26)
8/20/02 - Removed spare pullup straps for Intrepid (p.9)
Added 6 bypass caps to MAXBUS_SLEEP and CPU_VCORE_SLEEP (p.5)
Removed 3 bypass caps for +1_5V_AGP at Intrepid (p.16)
Removed 4 bypass caps for MAXBUS_MAIN at Intrepid (p.16)
8/26/02 - Removed 32 bypass caps for +3V_MAIN at Intrepid (p.16)
8/29/02 - Added dedicated Boot Banger circuit (p.6)
9/03/02 - Corrected upper LVDS single pin nets (p.20)
Added LMU circuitry to eliminate extra board (p.23)
Removed LMU connector (p.23)
Corrected battery connector [same as P84] (p.29)
Removed P93 support (p.25)
9/23/02 - Replaced BCM5421 with Marvell 88E1111 (p.26)
Swapped pins on L33, L35 for layout (p.31)
9/27/02 - Corrected cpu, memory bus constraints to match manhattan lengths (p.34)
9/30/02 - Changed J19 (DC-in) to proper 4-pin connector (p.29)
10/03/02 - Numerous pin-swaps to accomodate board layout (all)
Added SSCG/NO_SSCG stuffing options for CY28512 circuit (p.14)
10/08/02 - Added page for functional test points (p.37)
10/09/02 - Changed 16 pin connectors (modem and right USB) to Foxconn parts (p.23)
Removed Zebra 15/16 support per P84 (p.27)
Removed INT_CPUFB_IN cap per P84 (p.8)
Added second FW port power fuse (p.27)
Replaced IRF7822 FETs with IRF7811W in battery charger and 14V PBUS switchers (p.29,30)
Renamed optical interface for consistency (p.24,37)
10/10/02 - Clamped NEC NC pins high per documentation (p.17)
10/11/02 - Replaced DVI EMI caps with 0201 versions (p.22)
10/15/02 - Moved FireWire connectors and port power switch to separate page (p.28)
Renamed +14V_PBUS to +PBUS (p.all)
Added full support for non-zero CPU_PLL_CFG<4> in run state (p.7)
10/21/02 - Updated CY28512 clock chip to Rev B (p.14)
10/22/02 - Mirrored wireless connector for P50 flex (p.24)
Changed keyboard ZIF to large SMK connector (p.23)
Updated PCI clock series R values per P84 (p.12)
Added TP nets to GPU for XOR-tree testing (p.19-21)
Added 3 decoupling caps to CPU_VCORE_SLEEP (p.5)
Removed XW17, jumper for CPU_VCORE_SLEEP (p.33)
Added 9 decoupling caps to each of +5V_MAIN and +3V_MAIN (p.32)
Added bulk caps to fan connectors (p.25)
11/08/02 - Changed FireWire PHY to Z17 (p.27)
Proto Release
7/22/02 - Initial acquisition of schematic (from 051-6278 Rev 01)
11/11/02 - Removed +3V_MAIN option for P50 card (p.24)
10/30/02 - Changed fan power rails to common net (p.25)
Repinned LMU pulldown for layout (p.23)
Split FW_VGND into FW_VGND0 and FW_VGND1 (p.28,37)
Added 0 ohm short and bypass cap for GPU VDDDVO per P84 (p.21,37)
Changed power rail for ALS to +3V_MAIN per P84 (p.23)
Increased MAX_VIA_COUNT by two on most nets with this constraint for uVia (p.34,35)
Replaced ADM1031 with ADT7460 [I2C Address Change!] (p.25)
Broke out quad OR-gate to discrete components for better placement (p.22,29)
12/13/02 - Added 12 pF caps to source of 33MHz PCI clocks since they can not be buried (p.12)
Replaced all 138S0351 [1uF,0603,6.3V,10%] with 132S0046 [1uF,0603,10V,20%] (p.27,30)
Renamed F10 to F1, F20 to F2 [deleted old F1,F2] (p.28)
Corrected PLL_CFG<4> for Apollo 7 [needs to always be zero] (p.5,7)
10/24/02 - Changed FW DS2 strap to pullup to shut off port 2 (p.27)
11/21/02 - Implemented D3cold for all PCI devices (p.12,14,18)
Added CKE pulldowns per P84 (p.9)
Added R800,R801 for eventual thermal diode in CPU (p.25)
Updated Ethernet series Rs per P84 [Clocks to 10 ohms, data to 22 ohms] (p.13)
Changed BootROM PWD signal to INT_RESET_L per P84 (p.9)
Changed fan PWM output pullups to +3V_SLEEP to prevent pump-up (p.25)
11/06/02 - Changed 10 uF FW current limit output cap to two 4.7 uF caps (p.28)
Added EMI caps to LVDS_DDC_CLK, INT_I2S0_SND_MCLK, INT_I2S0_SND_SCLK per P84 (p.22,25)
Changed R164 to 511 ohms to avoid low CPU clock amplitude (p.8)
Change MATCHED_DELAY to 50 for all TMDS DIFF PAIR (p.37)
01/14/03 - Add C812 - C821 (Totol 10 0.22uF caps) for 2.5V Intrepid Decoupling (p.16)
01/07/03 - Added NO_TEST nets to pads of DDR connector arms (p.11)
Updated system and power block diagrams (p.2,3)
01/03/03 - Corrected +2_5V_INTREPID connections to muxes and reference (p.9,10)
01/02/03 - Updated FireWire fuse topology to that of P84 (p.28)
01/28/03 - Remove NV31/17 components (p.19-21)
Add M10 (p.19-21)
02/07/03 - Add Power Net Constraints for M10 (p.38)
with 126S0035 (or alt. 126S0036) (p.33)
Edit I2C table for LMU (p.13)
Change Ferrite Bean of ATI power supply to correct values (p.21)
Remove C141 PBUS CAP (p.31)
02/11/03 - Add FW Power Net Constraints (p.38)
Change signal constraints for AGP signals (p.36)
Change R580 to 19.6K (p.14)
Connect Clock Slewing RESET# to MAIN_RESET_L (p.14)
Add LMU connector and components (p.23)
Add ATI Power sequencing Circuit for M10 Power-up and Power-down (p.19-22, p.32-35)
Replace Singing PBus Cap C49,C50,C67,C68,C80,C81,C95,C96,C108,C109,C120,C121
Add R810 & R811 for ALWAYS-ON FANs in Acrylic Build (p.25)
Add C822 & C823 at Wireless Card connector MAIN_RESET_L & RF_DISABLE_L_SPN (p.24)
01/13/03 - Add L53, L54, L55 for TMDS Data<0:2> Diff Pair (p.22)
01/10/03 - ZT7,ZT23,ZT61,ZT76,ZT89,ZT87,ZT22,ZT38,ZT60,ZT42 & ZT17 are changed to HOLE-VIA-20R10 (p.4)
Updated S-video filter values to those of P84 (p.22)
01/09/03 - Added required pulldown to output of DVI HPD sense comparator (p.22)
02/12/03 - Change and Rotate Keyboard Connector (p.23)
EVT RELEASE
Removed CPU_VGATE pullup to 5V to eliminate potential 3V/5V current path (p.32)
10/14/02 - Changed J18 to RJ45 with integrated magnetics (p.26)
Changed JTAG_ENET_TDI to pullup [LA clk not used] (p.13)
03/28/03 - Due to MLB outline change at DVI connector, CHGND1 has to be splitted into
R601 change from 100K to 4.7K (P 29)
Modify FAN circuit to PWM active low signal (P25)
Change C643 10uF Cap to 1206 package part (P 28)
Change Q7 from SI4435DY to SUD45P03-10 (P 30)
Add 1000pF caps at ADT7460 D_plus/minus pairs (p.25)
DVT RELEASE
Enable VCore Burst(Skip) Mode by no stuffing R67 (p.33)
Change Q49 to IRF7832 part (p.20)
Change Q62 & Q65 to SI7860DP part (p.33)
Change Q48 to SI7860DP part (p.20)
Add C838, C840, C839, C844 & C845 10pF caps near the power switchers FETs (p.20, 32 & 34)
Reduce audible noise by changing L64 to 152S0139 (p.20)
Change Q60, Q63 & Q66 to IRF7832 part and split C102 into 3 10pF caps (p.33)
Enable GPUCore Burst Mode by changing R358 to 2.2 ohm, no stuffing R344 and stuffing R343 (p.20)
Enable 3V/5V Burst Mode by changing R406 & R407 to 100K ohm (p.32)
05/27/03 - Change RP31 to 4.7K for I2C timing specification (p.13)
05/21/03 - Swap +PBUS and +24V_PBUS at Backup Battery Connector - J16 (p.31)
06/05/03 - Change FW-B connector to 514S0058 with internal shield pins (p.28)
Move CBUS_PCI_REQ_L back to +3V_SLEEP rail pull-up (p.12)
Change CPU config stuffing option at R63 and R64 (p.7)
Change the TMDS Termination Resistor values to 162ohm (p.20)
06/13/03 - New SODIMM connector with 4 through-hole mounting pins (p.11)
No Stuff R835 (p.19)
Removed current monitoring IC for firewire port power (p.28)
Edit Signal Constraints for TMDS routing and ENET routing (p.36&37)
06/16/03 - Replace C705,C707,C711,C703 & C685 with part 128S0025 (p.20&32)
Change TMDS common mode choke to TDK AMC2012-900H part (p.22)
Change R198 to 100K ohm resistor (p.23)
Remove R271 0ohm resistor (p.34)
DVT2 RELEASE
Cleaned up CY28512B circuit as per P84 [powered off main, output divider and strap tweaks] (p.14)
Changed RP52,RP53,RP56,RP57 to 22ohm for EMI (p.19)
Add Common Mode Choke L77 & L76 at FWB pairs (p.28)
C
051-6338
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