Apple 820-3588-A Schematic

DRAWING

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

II NOT TO REPRODUCE OR COPY IT

3

B

7

BRANCH

DRAWING NUMBER

SIZE

D

SHEET

R

DATE

D

A

C

PAGE

A

C

3456

D

B

8 7 6 5 4 2 1

12

APPD

CK

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

DRAWING TITLE

DESCRIPTION OF REVISION

REV ECN

REVISION

PROPRIETARY PROPERTY OF APPLE INC.

TABLE_TABLEOFCONTENTS_ITEM

J16 MLB_IG

1 OF 86

SCHEM,MLB IG,J16

051-0164

2013-03-22

1 OF 123

12.4.0

ABBREV=DRAWING

TITLE=J16 MLB_IG

LAST_MODIFIED=Fri Mar 22 11:24:26 2013

49

03/13/2013

J16_TONY

55

I and V Sense(Continued)

(.csa)

Date

Sync

Contents

Page

1

J16_MLB

12/03/2012

1

Table of Contents

Page

(.csa)

Contents

Date

Sync

50

01/11/2013

J16_FIYIN

56

Temperature Sensors

51

01/07/2013

J16_JERRY

60

System Fan

52

03/07/2013

J16_DIRK

61

AUDIO: CODEC/REGULATORS

53

03/07/2013

J16_DIRK

62

AUDIO: HEADPHONE AMP

54

03/07/2013

J16_DIRK

63

AUDIO: LEFT SPKR AMP

55

03/07/2013

J16_DIRK

64

AUDIO: RIGHT SPKR AMP

56

03/07/2013

J16_DIRK

65

AUDIO: Jack, Mikey, CHS Switch

57

03/07/2013

J16_DIRK

66

Audio: Spkr/Mic Conn.

58

03/07/2013

J16_DIRK

67

AUDIO: Detects/Grounding

59

03/07/2013

J16_DIRK

68

AUDIO: Speaker ID

60

03/04/2013

J16_ROSSANA

69

Power Connectors / VReg G3Hot

61

03/21/2013

J16_ROSSANA

70

VReg CPU VCC Cntl

62

03/21/2013

J16_ROSSANA

71

VReg CPU VCC Phases

63

03/04/2013

J16_ROSSANA

73

VReg VDDQ S3

64

03/04/2013

J16_ROSSANA

74

VREG 1V05 S0 / 1V5 S0

65

03/04/2013

J16_ROSSANA

76

VReg 3.3V S5/5V S4

66

01/22/2013

J16_LINDA

81

LCD Backlight Driver (LP8561)

67

02/11/2013

J16_MAX

84

FET-Controlled S0 and S4

68

02/21/2013

J16_AARON

85

PM Regulator Enables

69

02/21/2013

J16_AARON

86

PM Power Good

70

02/11/2013

J16_MAX

100

Power Aliases

71

02/11/2013

J16_MAX

102

Signal Aliases

72

02/11/2013

J16_MAX

104

Unused Signal Aliases

73

02/11/2013

J16_MAX

105

Functional / ICT Test

74

12/03/2012

J16_MLB

110

J16 RULE DEFINITIONS

75

01/10/2013

J16_NICK

111

DDR3 Constraints

76

01/10/2013

J16_NICK

112

CPU CONSTRAINTS

77

01/10/2013

J16_NICK

113

PCH PCIe/DMI Constaints

78

01/10/2013

J16_NICK

114

SATA/FDI/XDP Constraints

79

12/03/2012

J16_MLB

115

PCH and BR Constraints

80

12/03/2012

J16_MLB

116

USB/Ethernet/SD Constraints

81

01/10/2013

J16_NICK

117

SMBus/Sensor Constraints

82

01/10/2013

J16_NICK

118

VReg Constraints

83

12/14/2012

J16_ROSSANA

119

CPU VReg Constraints

84

12/20/2012

J16_ROSSANA

120

Platform VReg Constraints

85

12/03/2012

J16_MLB

121

TBT/DP Constraints

86

12/03/2012

J16_MLB

123

BLC Constraints

2

J16_DINI

01/29/2013

2

BOM Configuration

3

J16_MAX

02/11/2013

3

DEBUG LEDS

4

J16_MAX

02/11/2013

4

Holes/PD parts

5

J16_DINI

01/14/2013

5

CPU DMI/PEG/FDI/RSVD

6

J16_DINI

01/14/2013

6

CPU Clock/Misc/JTAG/CFG

7

J16_DINI

01/14/2013

7

CPU DDR3 Interfaces

8

J16_DINI

01/14/2013

8

CPU Power

9

J16_DINI

01/14/2013

9

CPU Ground

10

J16_DINI

01/14/2013

10

CPU Decoupling

11

J16_KENNY

01/21/2013

11

PCH RTC/HDA/JTAG/SATA/CLK

12

J16_KENNY

01/21/2013

12

PCH DMI/FDI/PM/GFX/PCI

13

J16_KENNY

01/21/2013

13

PCH PCI-E/USB

14

J16_KENNY

03/07/2013

14

PCH GPIO/MISC/NCTF

15

J16_KENNY

01/21/2013

15

PCH Power

16

J16_KENNY

01/21/2013

16

PCH Grounds

17

J16_KENNY

01/21/2013

17

PCH DECOUPLING

18

J16_KENNY

03/18/2013

18

CPU & PCH XDP

19

J16_KENNY

01/21/2013

19

Chipset Support

20

J16_KENNY

01/21/2013

20

Project Chipset Support

21

J16_NICK

12/11/2012

21

CPU Memory S3 Support

22

J16_NICK

01/10/2013

22

DDR3 VREF MARGINING

23

J16_NICK

01/10/2013

23

DDR3 SO-DIMM Connector A

25

J16_NICK

01/10/2013

24

DDR3 SO-DIMM CONNECTOR B

27

J16_NICK

01/10/2013

25

DDR3 ALIASES AND BITSWAPS

28

J16_MAX

02/11/2013

26

Thunderbolt Host (1 of 2)

29

J16_MAX

02/11/2013

27

Thunderbolt Host (2 of 2)

30

J16_MAX

02/11/2013

28

Thunderbolt Power Support

32

J16_MAX

02/11/2013

29

Thunderbolt Connector A

33

J16_MAX

02/11/2013

30

Thunderbolt Connector B

34

J16_MAX

02/11/2013

31

TBT DDC Crossbar

35

J16_FIYIN

01/11/2013

32

AIRPORT/BT

37

J16_JERRY

01/07/2013

33

SATA/SSD Connectors

38

J16_JERRY

01/07/2013

34

HDD Connector

39

J16_MAX

02/11/2013

35

ETHERNET PHY (CAESAR IV)

40

J16_MAX

02/11/2013

36

Ethernet Support & Connector

41

J16_MAX

02/11/2013

37

SD READER CONNECTOR

42

J16_MAX

02/11/2013

38

Camera Controller

43

J16_MAX

02/11/2013

39

Camera Controller Support

44

J16_MAX

02/11/2013

40

Internal DP Support

45

J16_MAX

02/11/2013

41

Internal DP MUXing

46

J16_KOSECOFF

03/18/2013

42

EXTERNAL USB PORTS A & B

47

J16_KOSECOFF

03/18/2013

43

EXTERNAL USB PORTS C & D

50

J16_TONY

03/13/2013

44 SMC

51

J16_TONY

03/13/2013

45

SMC Support

52

J16_TONY

03/13/2013

46

SPI and Debug Connector

53

J16_TONY

03/13/2013

47

SMBus Connections

54

J16_TONY

03/13/2013

48

I and V Sense

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_ALT_ITEM

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_BOMGROUP_ITEM

TABLE_5_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

ADD ’J16_PRODUCTION’ AT REVA RELEASE

Alternates

R5430

R5400,R5520,R5530

Bar Code Labels / EEEE #’s

Schematic / PCB #’s

Programmable Parts

ASIC Parts

BOM Groups

Main BOM Variants

CPUs

CPU:CTO

U0500

CRITICAL

1

337S4517

CRW,QEUX,EEU2,C0,3.2G,65W,4+3,1.3,6M,BGA

CPU:BETTER

CRITICAL

1

U0500

337S4516

CRW,QEUY,EEU2,C0,3.0G,65W,4+3,1.13,4M,BGA

CPU:GOOD

CRITICAL

U0500

1

337S4515

CRW,QEUZ,EEU2,C0,2.7G,65W,4+3,1.15,4M,BGA

AP_ISNS:Y,HDD_IVSNS:Y,TEMPSNSDEV

DEVEL_SENSORS

J16_PROGPARTS

SMC:PROG,BOOTROM:PROG,T29ROM:PROG,CIVROM:PROG,CAMROM:PROG

J16,J16_COMMON,CPU:GOOD,SSD:Y,EEEE:FF3T

PCBA,MLB_IG,J16

639-4515

PCBA,MLB_IG,BETTER,J16

J16,J16_COMMON,CPU:BETTER,SSD:Y,EEEE:FGWY

639-4704

PCBA,MLB_IG,CTO,J16

J16,J16_COMMON,CPU:CTO,SSD:Y,EEEE:FGY0

639-4705

985-0052

DEVELOPMENT,J16_DEVEL

PCBA,MLB_IG,DEV,J16

MLB LABEL,2D

EEEE_FGWY

825-7896

1

CRITICAL

EEEE:FGWY

MLB LABEL,2D

825-7896

1

CRITICAL

EEEE_FGY0 EEEE:FGY0

COMMON,ALTERNATE,J16_COMMON1,J16_COMMON2,J16_PROGPARTS

J16_COMMON

XDP,SPEAKERID,TBTHV:P12V,CPUVCC:3PHASE

J16_COMMON1

J16_DEVEL

XDP_CONN,LPCPLUS,DDRVREF_DAC,DEVEL_SENSORS,DEVEL_AUDIO

AP_ISNS:N,HDD_IVSNS:NJ16_PRODUCTION

CRITICAL337S4483

U1100

1

LYNX POINT MOBILE,C1,QS,QE99,FCBGA695

338S1113 CRITICAL

IC,TBT,CR-4C,B1,PRQ,CIO,288 12X12 FC-CSP

U2800

1

343S0616 CRITICAL

U3900IC,BCM57766A,CIV+,A0,8X8

1

338S1159

IC,SMC12-A3,40MHZ/50MIPS,SCPL FW,157BGA

U5000

SMC:BLANK

CRITICAL

1

SMC:PROG

CRITICAL

U5000

IC,SMC,PROGRMD,V2.12A30,J16

341S3781

IC,SERIAL FLASH,2MBIT,2.7V,REV F

335S0862

CRITICAL

CIVROM:BLANK

1

U3990

1

341S3735

IC,ENET SPI ROM,NYMONYX,V1.13,D7/D7I

U3990

CRITICAL

CIVROM:PROG

IC,EEPROM,SERIAL,256KB,MLP8

335S0865

CRITICAL

T29ROM:BLANK

U2890

1

341S3734

IC,EEPROM,CR,V16.2,J16

U2890

CRITICAL

T29ROM:PROG

1

BOOTROM:BLANK

U5210

CRITICAL

335S0807

IC,64 MBIT SPI SERIAL FLASH

1

BOOTROM:PROG

CRITICAL

U5210

IC,EFI,V0039,J16

341S3783

IC,LP8561,LED BLKT CTLR,LLP24,B0-F

353S3908 CRITICAL

U8100

1

U4202

CAMROM:BLANK

1

335S0852

IC,FLASH,SPI,1MBIT,3V3

CRITICAL

1

341S3778

IC,CAMERA,FLASH,V7229,J16

U4202

CRITICAL

CAMROM:PROG

J16

1

SCH

CRITICAL

SCH,MLB_IG,J16

051-0164

EEEE:FF3TEEEE_FF3T

MLB LABEL,2D

825-7896

1

CRITICAL

J16

1

PCB

CRITICAL820-3588

PCBF,MLB_IG,J16

138S0638

ALL

Taiyo 10uf 805 alt

138S0681

120OHM EMI BEAD

ALL

155S0367155S0578

ALL

USB3 diodes

377S0104377S0155

SYNC_MASTER=J16_DINI SYNC_DATE=01/29/2013

BOM Configuration

J16_COMMON2

VDDQ:P1V35

ALL

376S0975

P/NCh dual FET

376S1081

ALL

377S0126

USB2 diodes

377S0147

25MHz Xtal

197S0480

ALL

197S0481

138S0775138S0860

ALL

Single-source 1uF 402

107S0251

ALL

Sense resistor

107S0249

102S0880

ALL

Sense resistor

102S0879

341S3747

U3990

Enet ROM341S3735

197S0479 197S0478 12 MHz Cam. Xtal

Y4200

ALL

128S0365

150UF AL POLY

128S0368

Enet magnetics

ALL

157S0058157S0084

377S0124

TVSALL

377S0057

ALL

138S0859 138S0788

Single-source 10uF

ALL

138S0706 138S0739

Single-source 1uF 201

051-0164

12.4.0

2 OF 123

2 OF 86

IN

G

D

S

IN

G

D

S

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

the southbridge that indicates

VIDEO ON Led

that chipset has enumerated graphics

This LED is a GPIO driven from

ALL_SYS_PWRGD Led

S5 Led

GPU GOOD Led

1/16W

5% MF-LF

1K

402

R0302

40

SILK_PART=2

2.0X1.25MM-SM

GREEN-3.6MCD

CRITICAL

LE0302

SOT-363

CRITICAL

2N7002DW-X-G

Q0302

5% MF-LF

1/16W 402

1K

R0304

21 44 69

SILK_PART=4

2.0X1.25MM-SM

GREEN-3.6MCD

CRITICAL

LE0304

1K

1/16W 402

MF-LF

5%

R0301

2.0X1.25MM-SM

GREEN-3.6MCD

SILK_PART=1

CRITICAL

LE0301

1K

5% 1/16W MF-LF 402

R0303

SILK_PART=3

2.0X1.25MM-SM

GREEN-3.6MCD

CRITICAL

LE0303

SOT-363

2N7002DW-X-G

CRITICAL

Q0302

14 18

DEBUG LEDS

SYNC_MASTER=J16_MAX

SYNC_DATE=02/11/2013

LCD_SHOULD_ON_R

GPU_GOOD

ALL_SYS_PWRGD

=PP3V3_S4_LED

CORE_VOLTAGES_ON_R

CORE_VOLTAGES_ON

=PP3V3_S0_LED

VIDEO_ON_L

=PP3V3_S0_LED

GPU_PRESENT_R

GPU_PRESENT_DRAIN

=PP3V3_S5_LED

ITS_PLUGGED_IN

051-0164

12.4.0

3 OF 123

3 OF 86

1

2

K

A

3

5

4

1

2

K

A

1

2

K

A

1

2

K

A

6

2

1

70

3

70

3

70

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

HEATSINK STABILITY MOUNTING FEATURES

CPU HEATSINK MOUNTING FEATURES

998-4559 (Plated holes, 4mm inner diameter, 8mm pad) 998-5089 (ZH0414) near BLC has slightly larger hole to allow for grommet

998-4560 (Plated holes, 2.3mm inner diameter, 4.3mm pad)

WIRELESS CARD MTG HOLES

SSD STANDOFF

Rear Cover

APN: 860-1624

(860-1532)

STDOFF-4.5OD2.2ID-6.5H-SM

CRITICAL

SSD:Y

NUT0413

7P0R4P0-8P0B-NSP

ZH0413

7P0R4P0-8P0B-NSP

ZH0415

7P0R4P0-8P0B-NSP

ZH0416

STDOFF-4.5OD.98H-1.1-3.40-TH

CRITICAL

SH0477

STDOFF-4.5OD.98H-1.1-3.40-TH

SH0479

CRITICAL

5P5R1P9-4P3B-NSP

ZH0421

5P5R1P9-4P3B-NSP

ZH0422

ZH0414

7P0R4P6-8P0B-NSP

CRITICAL

STDOFF-4.5OD.98H-1.1-3.40-TH

SH0473

STDOFF-4.5OD.98H-1.1-3.40-TH

CRITICAL

SH0474

CRITICAL

STDOFF-4.5OD.98H-1.1-3.40-TH

SH0475

SH0476

CRITICAL

STDOFF-4.5OD.98H-1.1-3.40-TH

Holes/PD parts

SYNC_DATE=02/11/2013

SYNC_MASTER=J16_MAX

051-0164

12.4.0

4 OF 123

4 OF 86

1

1 1

1

1 1

1

IN IN IN

IN

IN IN IN IN IN

OUT OUT OUT OUT OUT

OUT

OUT OUT OUT

OUT

OUT OUT OUT OUT

OUT

OUT OUT OUT OUT OUT

OUT

SYM 10 OF 12

EDP

DIGITAL DISPLAY INTERFACES

FDI

EDP_TXN0

DDIC_TXP2

FDI_TXP1

FDI_TXN1

FDI_TXP0

FDI_TXN0

EDP_DISP_UTIL

EDP_RCOMP

DDIB_TXN0

DDIC_TXN1

DDIC_TXP0

DDIC_TXN0

DDIB_TXN3

DDIB_TXP2

EDP_TXP1

EDP_TXP0

EDP_TXN1

EDP_AUXP

EDP_HPD

EDP_AUXN

DDID_TXP1

DDID_TXN1

DDID_TXP0

DDID_TXN0

DDID_TXP3

DDID_TXN3

DDID_TXP2

DDID_TXN2

DDIC_TXP1 DDIC_TXN2

DDIC_TXN3 DDIC_TXP3

DDIB_TXP0 DDIB_TXN1 DDIB_TXP1 DDIB_TXN2

DDIB_TXP3

RESERVED

SYM 12 OF 12

DAISY_CHAIN_NCTF

RSVD132 RSVD133 RSVD134 RSVD135 RSVD136 RSVD137 RSVD138 RSVD139

DAISY_CHAIN_NCTF

TP

NC NC NC NC NC NC NC NC

IN IN IN IN

IN

OUT

IN

SYM 1 OF 12

FDI

PCI EXPRESS BASED INTERFACE SIGNALS

DMI

PEG_TX15

PEG_TX14

PEG_TX13

PEG_TX12

PEG_TX11

PEG_TX10

PEG_TX9

PEG_TX8

PEG_TX7

PEG_TX6

PEG_TX5

PEG_TX4

PEG_TX3

PEG_TX2

PEG_TX1

PEG_TX0

PEG_RX15*

PEG_RX14*

PEG_RX13*

PEG_RX12*

PEG_RX11*

PEG_RX10*

PEG_RX9*

PEG_RX8*

PEG_RX7*

PEG_RX6*

PEG_RX5*

PEG_RX4*

PEG_RX3*

PEG_RX2*

PEG_RX1*

PEG_RX0*

PEG_TX15*

PEG_TX14*

PEG_TX13*

PEG_TX12*

PEG_TX11*

PEG_TX10*

PEG_TX9*

PEG_TX8*

PEG_TX7*

PEG_TX6*

PEG_TX5*

PEG_TX4*

PEG_TX3*

PEG_TX2*

PEG_TX1*

PEG_TX0*

PEG_RCOMP

DISP_INT

FDI_CSYNC

PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8

PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15

DMI_RX0* DMI_RX1* DMI_RX2* DMI_RX3*

DMI_RX0

DMI_RX2 DMI_RX3

DMI_TX0* DMI_TX1* DMI_TX2* DMI_TX3*

DMI_TX0 DMI_TX1 DMI_TX2 DMI_TX3

DMI_RX1

IN IN IN

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

exist between both TP’s on each corner.

daisy-chain fashion. Continuity should

Each corner of CPU has two testpoints. Other corner test signals connected in

to match Intel symbol.

Port D pins out of order

NO_TEST NO_TEST

CPU Daisy-Chain Strategy:

72

BGA

OMIT_TABLE

HASWELL

U0500

24.9

402

MF-LF

1/16W

1%

R0530

402

MF-LF

1/16W

5%

10k

R0531

BGA

OMIT_TABLE

HASWELL

U0500

TP-P6

TP0500

TP-P6

TP0501

TP-P6

TP0511

TP-P6

TP0531

TP-P6

TP0510

TP-P6

TP0520

TP-P6

TP0530

TP-P6

TP0521

12 77

24.9

1%

MF-LF

1/16W

402

R0510

12 78

BGA

OMIT_TABLE

HASWELL

U0500

72

SYNC_DATE=01/14/2013SYNC_MASTER=J16_DINI

CPU DMI/PEG/FDI/RSVD

CPU_DC_BC1

CPU_DC_BF4

CPU_DC_A51

CPU_DC_D54

CPU_DC_D1

DP_IG_A_HPD_L

=PEG_R2D_C_N<12>

TP_DP_IG_D_MLN<0>

TP_DP_IG_D_MLP<1>

=PEG_D2R_P<13>

=PEG_D2R_P<8>

=PEG_D2R_P<5>

=PEG_D2R_P<3>

TP_DP_IG_A_AUXCHP

TP_DP_IG_B_MLP<3>

TP_DP_IG_B_MLN<2>

TP_DP_IG_B_MLP<1>

TP_DP_IG_B_MLN<1>

TP_DP_IG_C_MLP<3>

TP_DP_IG_C_MLN<3>

TP_DP_IG_C_MLN<2>

TP_DP_IG_C_MLP<1>

TP_DP_IG_D_MLN<2> TP_DP_IG_D_MLP<2> TP_DP_IG_D_MLN<3>

TP_DP_IG_D_MLP<0> TP_DP_IG_D_MLN<1>

TP_DP_IG_A_MLN<1>

TP_DP_IG_A_MLP<0>

TP_DP_IG_B_MLP<2> TP_DP_IG_B_MLN<3>

TP_DP_IG_C_MLN<0> TP_DP_IG_C_MLP<0> TP_DP_IG_C_MLN<1>

TP_DP_IG_B_MLN<0>

TP_EDP_DISP_UTIL

TP_DP_IG_C_MLP<2>

TP_DP_IG_A_MLN<0>

=PEG_D2R_N<4>

DMI_N2S_P<2>

DMI_N2S_P<0>

=PEG_D2R_P<1>

=PEG_R2D_C_P<5>

DMI_S2N_P<3>

DMI_S2N_N<1>

DMI_S2N_N<3>

DMI_S2N_P<0> DMI_S2N_P<1>

=PEG_D2R_N<1>

=PEG_D2R_N<3>

=PEG_D2R_N<8>

=PEG_D2R_N<11>

=PEG_D2R_N<10>

=PEG_D2R_N<12>

=PEG_D2R_N<14> =PEG_D2R_N<15>

=PEG_D2R_P<0>

=PEG_D2R_P<2>

=PEG_D2R_P<4>

=PEG_D2R_P<6> =PEG_D2R_P<7>

=PEG_D2R_P<10>

=PEG_D2R_P<9>

=PEG_D2R_P<11> =PEG_D2R_P<12>

=PEG_D2R_P<15>

=PEG_D2R_P<14>

=PEG_R2D_C_N<1> =PEG_R2D_C_N<2> =PEG_R2D_C_N<3> =PEG_R2D_C_N<4> =PEG_R2D_C_N<5> =PEG_R2D_C_N<6> =PEG_R2D_C_N<7>

=PEG_R2D_C_N<9>

=PEG_R2D_C_N<8>

=PEG_R2D_C_N<10> =PEG_R2D_C_N<11>

=PEG_R2D_C_N<13> =PEG_R2D_C_N<14> =PEG_R2D_C_N<15>

=PEG_R2D_C_P<2>

=PEG_R2D_C_P<1>

=PEG_R2D_C_P<3> =PEG_R2D_C_P<4>

=PEG_R2D_C_P<6> =PEG_R2D_C_P<7> =PEG_R2D_C_P<8>

=PEG_R2D_C_P<10> =PEG_R2D_C_P<11> =PEG_R2D_C_P<12> =PEG_R2D_C_P<13> =PEG_R2D_C_P<14> =PEG_R2D_C_P<15>

FDI_CSYNC

FDI_INT

DMI_S2N_N<2>

=PEG_D2R_N<9>

=PEG_D2R_N<0>

DMI_S2N_P<2>

DMI_N2S_P<3>

DMI_N2S_N<1>

DMI_N2S_N<0>

DMI_N2S_N<3>

DMI_N2S_P<1>

DMI_N2S_N<2>

=PEG_R2D_C_N<0>

=PEG_R2D_C_P<0>

CPU_PEG_RCOMP

=PEG_R2D_C_P<9>

=PEG_D2R_N<5> =PEG_D2R_N<6>

PPVCOMP_S0_CPU

TP_DP_IG_A_AUXCHN

PPVCCIO_S0_CPU

TP_DP_IG_D_MLP<3>

CPU_EDP_RCOMP

=PEG_D2R_N<7>

=PEG_D2R_N<13>

DMI_S2N_N<0>

CPU_DC_BF51

CPU_DC_BC54

TP_DP_IG_A_MLP<1>

PPVCOMP_S0_CPU

TP_DP_IG_B_MLP<0>

CPU_DC_A4

=PEG_D2R_N<2>

TP_DP_IG_A_MLN<2> TP_DP_IG_A_MLP<2> TP_DP_IG_A_MLN<3> TP_DP_IG_A_MLP<3>

TRUE

CPU_DC_BE53_BF53

CPU_DC_A3_B3

TRUE

CPU_DC_A3_B3

CPU_DC_B54_C54

TRUE

CPU_DC_A53_B53

TRUE

CPU_DC_A52_B52

TRUE

CPU_DC_B2_C3

TRUE

CPU_DC_A53_B53

TRUE

CPU_DC_A52_B52

TRUE

CPU_DC_BE3_BF3

TRUE

CPU_DC_BE2_BF2

TRUE

CPU_DC_BD54_BE54

TRUE

CPU_DC_BE2_BF2

TRUE

CPU_DC_BD1_BE1

TRUE

CPU_DC_BD54_BE54

TRUE

CPU_DC_BD1_BE1

TRUE

CPU_DC_B54_C54

CPU_DC_BE52_BF52

TRUE

CPU_DC_C1_C2

TRUE

CPU_DC_C1_C2

TRUE

CPU_DC_B2_C3

TRUE

CPU_DC_BE52_BF52

TRUE

CPU_DC_BE3_BF3

TRUE

CPU_DC_BE53_BF53

5 OF 86

5 OF 123

12.4.0

051-0164

C14

D20

B14

A14

D12

C12

E12

AG6

C25

A21

D21

C21

A24

D24

B12

D14

A12

F14

E14

F15

B17

A17

D17

C17

B16

A16

D16

C16

B21

C20

A20

B20

D25

A25

B25 C24

B24

1

2

1

2

BF4

BF3

BF2

C2

C3

C54

D1

D54

A3 A4

A51 A52

A53

BE52 BE53

BE54

BF52

BF53

C1

AN35 AN37

AF9 AE9

G14

G17 AD45

AG45

BF51

BE1

BD54

B2

B3

B52

B53 B54

BC54

BE2 BE3

BD1

BC1

1

2

T2

T3

R3

R1

R5

T5

J1

J4

G2

J6

E2

G5

E4

D6

B5

C6

Y2

Y3

V1

V4

V5

M2

L4

M4

L2

L5

B9

D9

E9

B10

C10

E10

T1

T4

R4

R2

R6

T6

J2

J3

G3

J5

E3

G4

D4

E6

C5

B6

AH6

F12

F11

F10 D10

A10

F9 C9

A9

M5 L1

M3

L3 M1

Y5 V3

V2

Y4 Y1

AB2 AB3

AC3

AC1

AB1

AC4

AC2

AF2

AF4 AG4

AG2

AF1

AF3

AG3 AG1

AB4

71

72

71

72

71

72

76

5 8

72

6 8

10 18 61

71

76

72

5 8

71

72

5

5 5

5

BI BI BI BI BI

IN

OUT

BI

NC

OUT

BI

SYM 2 OF 12

CLOCK

JTAG

PWR

DDR3

THERMAL

THERMTRIP*

PM_SYNC

PWRGOOD

SM_DRAMPWROK

PLTRSTIN*

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

SM_DRAMRST*

PRDY* PREQ*

TCK TMS

TRST*

TDI TDO

DBR*

BPM0* BPM1*

BPM3*

BPM2*

BPM4* BPM5* BPM6* BPM7*

PECI

PROC_DETECT*

PROCHOT*

CATERR*

DPLL_REF_CLKN DPLL_REF_CLKP

BCLKN BCLKP

SSC_DPLL_REF_CLKN SSC_DPLL_REF_CLKP

OUT

IN IN

SYM 11 OF 12

RESERVED

RSVD_TP28

RSVD_TP27

RSVD_TP39

RSVD_TP38

RSVD11

RSVD_TP1 RSVD_TP2

RSVD51 RSVD52

RSVD50

RSVD16

RSVD42

RSVD41

RSVD10

RSVD9

RSVD95

RSVD94

RSVD93

RSVD92

CFG_RCOMP

CFG16

CFG19

CFG18 CFG17

VSS_H54

VSS_H52

VSS_H51

VSS_H53

VCC_F22

VSS_G19

VSS_F52

VSS_F51

TESTLO_F21

CFG0 CFG1

CFG6

CFG5

CFG2 CFG3 CFG4

TESTLO_F20

CFG11

CFG10

CFG9

CFG8

CFG7

CFG12

CFG14

CFG13

CFG15

RSVD_TP17 RSVD_TP18

RSVD_TP37

RSVD_TP36

RSVD_TP35

RSVD_TP23

RSVD_TP3 RSVD_TP4

RSVD47 RSVD48 RSVD49

RSVD_TP26

RSVD_TP25

RSVD_TP24

NC

IN

OUT

IN IN

IN

OUT

IN

OUT

BI BI BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

CFG [4] :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED

(IPU)

(IPD)

(IPU)

(IPU) (IPU)

(IPU)

(IPU) (IPU)

(IPU)

CFG [2] :PCIE x16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

CFG [6:5] :PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4

CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS

J1800 and only for debug access

These can be placed close to

CFG [3] :PCIE x4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

NOTE: Pre-ES2 CPUs have issue with Sx cycling, must set CFG<9> low to avoid issue, but this locks CPU VR at 1.7V Vboot (CPU Sighting #4391569).

(IPU)

18 78

PLACE_NEAR=U0500.F50:157mm

402

MF-LF

1/16W

5%

10K

R0611

12 21

14 18 76

14 45 76

14 44 45 76

PLACE_NEAR=U0500.BB52:12.7mm

100

1% 1/16W MF-LF 402

R0614

75

1% 1/16W MF-LF 402

PLACE_NEAR=U0500.BB53:12.7mm

R0613

100

1% 1/16W MF-LF 402

PLACE_NEAR=U0500.BB51:12.7mm

R0612

45 76

5% 1/16W MF-LF

402

62

R0601

402

1/16W MF-LF

5%

56

R0603

44 45 61 62 76

BGA

OMIT_TABLE

HASWELL

U0500

21

11 77

BGA

HASWELL

OMIT_TABLE

U0500

MF-LF 402

1/16W

1%

49.9

R0690

49.9

1% 1/16W MF-LF

402

R0680

49.9

1% 1/16W MF-LF

402

R0685

402

MF-LF

5%

1K

NOSTUFF

1/16W

R0649

1K

NOSTUFF

5% 1/16W

402

MF-LF

R0643

402

MF-LF

1/16W

5%

1K

NOSTUFF

R0641

402

MF-LF

1/16W

5%

1K

NOSTUFF

R0640

NOSTUFF

1K

5% 1/16W MF-LF

402

R0647

1K

5% 1/16W MF-LF

402

CPUCFG6_PD

R0646

1K

5% 1/16W MF-LF 402

CPUCFG5_PD

R0645

402

MF-LF

1/16W

5%

EDP:YES

1K

R0644

402

MF-LF

1/16W

5%

1K

NOSTUFF

R0642

3.32K

402

MF-LF

1/16W

1%

PLACE_NEAR=U0500.AP48:51.562mm

R0621

1K

5% 1/16W MF-LF

402

HSW_PRE_ES2

R0648

18

18 78

18

1.82K

PLACE_NEAR=R0621.2:1mm

1% 1/16W MF-LF

402

R0620

12 76

14 18 76

18 19

18 76

18 78

CPUPEG:X8X4X4

CPUCFG6_PD,CPUCFG5_PD

CPUPEG:X8X8

CPUCFG5_PD

CPUPEG:X16

SYNC_MASTER=J16_DINI SYNC_DATE=01/14/2013

CPU Clock/Misc/JTAG/CFG

XDP_BPM_L<7>

CPU_SM_RCOMP<2>

=MEM_RESET_L

XDP_CPU_PREQ_L

XDP_CPU_TCK

PM_THRMTRIP_L

CPU_PROCHOT_R_L

CPU_CATERR_L

TP_CPU_RSVD_TP2

CPU_PECI

CPU_PROCHOT_L

PM_MEM_PWRGD

PPVCCIO_S0_CPU

=PP1V5_S3_CPU_VCCDDR

DMI_CLK100M_CPU_P

DMI_CLK100M_CPU_N

CPU_CLK135M_DPLLSS_P

CPU_CLK135M_DPLLSS_N

CPU_CLK135M_DPLLREF_P

CPU_CLK135M_DPLLREF_N

CPU_RESET_L

PM_SYNC

CPU_PWRGD

CPU_CFG<3>

CPU_CFG<9>

CPU_CFG<1> CPU_CFG<0>

CPU_SM_RCOMP<0> CPU_SM_RCOMP<1>

CPU_CFG<6>

=PPVCC_S0_CPU

TP_CPU_RSVD_TP37

TP_CPU_RSVD_TP49

TP_CPU_RSVD_TP48

TP_CPU_RSVD_TP1

TP_CPU_RSVD_TP4

TP_CPU_RSVD_TP36

CPU_CFG<15>

CPU_CFG<13> CPU_CFG<14>

CPU_CFG<12>

CPU_CFG<11>

CPU_CFG<8>

CPU_CFG<7>

CPU_CFG<6>

CPU_CFG<5>

CPU_CFG<2>

CPU_CFG<1>

CPU_CFG<4>

TP_CPU_RSVD_TP35

TP_CPU_RSVD_TP24

XDP_CPU_TRST_L

XDP_CPU_TDI XDP_CPU_TDO

XDP_BPM_L<6>

XDP_BPM_L<5>

XDP_BPM_L<4>

XDP_BPM_L<2> XDP_BPM_L<3>

XDP_BPM_L<1>

XDP_BPM_L<0>

XDP_DBRESET_L

XDP_CPU_TMS

XDP_CPU_PRDY_L

CPU_CFG<3>

CPU_CFG<17>

CPU_CFG<16>

CPU_CFG<2>

CPU_CFG<7>

CPU_CFG<10>

CPU_CFG<9>

CPU_CFG<4>

CPU_CFG<5>

CPU_CFG_RCOMP

TP_CPU_RSVD_TP3

TP_CPU_RSVD_TP23

TP_CPU_RSVD_TP47

CPU_TESTLO_F21

TP_CPU_RSVD_TP18

CPU_CFG<0>

CPU_TESTLO_F20

CPU_CFG<19>

TP_CPU_RSVD_TP27 TP_CPU_RSVD_TP28

TP_CPU_RSVD_TP26

TP_CPU_RSVD_TP25

TP_CPU_RSVD_TP38 TP_CPU_RSVD_TP39

CPU_CFG<18>

TP_CPU_RSVD_TP17

CPU_CFG<16>

051-0164

12.4.0

6 OF 123

6 OF 86

1

2

1

2

1

2

1

2

1

2

12

D53

D52

F50

AP48

L54

BB51 BB53

BB52

BE51

N53

N52

N54

M51 M53

N49

M49

F53

R51 R50

N50

P49

R49

P53 U51

P51

G51

C51

E50

G50

AC6

AE6

AB6 AA6

V6

Y6

G24

G21

F25

F24

BC4

F1

E1

L49

E5

L50

F16

F8

AL6

BD4

AU26

AU27

AM48

AH49

B50

R54

Y52

V52

V53 Y51

H54

H52

H51

H53

F22

G19

F52

F51

F21

AG49

AD49

V51

AB49

AC49

AE49

Y50

F20

W53

Y53

Y54

Y49

W51

U53

R53

V54

R52

G12

G10

L51

L53

L52

BE4

A5

A6

N51 G53

H50

G6

F6

BD3

1

2

1

2

1

2

1

2

1

2

121

2

1

2

121

2

121

2

1

2

1

2

1

2

75

76

5 8

10 18 61

70

6

18 78

6

18 78

6

18 78

6

18 78

75

6

18 78

8

10 70

18 72 78

18 78

6

18 78

6

18 78

6

18 78

6

18 78

6

18 78

6

18 78

6

18 78

6

18 78

6

18 78

6

18 78

6

18 78

6

18 78

6

18 78

76

6

18 78

18

6

18 78

OUT

NC

NC NC

NC

NC NC NC

NC

NC NC

BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

OUT OUT

OUT OUT OUT

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

SYM 3 OF 12

MEMORY CHANNEL A

SA_DQ12

SA_DQ11

SA_DQ8

SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24

SA_CKP3

SA_CKN3

SA_CKP2

SA_CKP1

SA_CKN1

SA_CKP0

SA_CKN0

SA_CKE1

SA_CS1*

SA_DQ20

SM_VREF

SA_DQSN7

SA_DQSN6

SA_DQSN5

SA_DQSN4

SA_DQSN3

SA_DQSN2

SA_DQSN1

SA_DQSN0

SA_DQS7

SA_DQS6

SA_DQS4 SA_DQS5

SA_DQS3

SA_DQS2

SA_DQS1

SA_DQS0

SA_MA13

SA_MA12

SA_MA11

SA_MA9

SA_MA8

SA_MA7

SA_MA5 SA_MA6

SA_MA4

SA_MA2 SA_MA3

SA_MA0 SA_MA1

SA_CAS*

SA_WE*

VSS_BC21

SA_RAS*

SA_BS1 SA_BS2

SA_ODT3

SA_BS0

SA_ODT2

SA_ODT1

SA_ODT0

SA_CS3*

SA_CS2*

SA_CS0*

SA_CKE3

SA_CKE2

SA_CKE0

SA_DQ30

SA_DQ0 SA_DQ1 SA_DQ2

SA_DQ9

SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19

SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29

SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44

SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58

SA_DQ61 SA_DQ62 SA_DQ63

SA_DQ4

SA_DQ3

SA_DQ10

SA_DQ7

SA_DQ5 SA_DQ6

SA_DQ47

SA_DQ46

SA_DQ45

SB_DIMM_VREFDQ

SA_DIMM_VREFDQ

RSVD25

RSVD162

RSVD165

RSVD168

SA_CKN2

SA_MA10

SA_MA14 SA_MA15

RSVD170

RSVD169

RSVD167

RSVD166

RSVD164

RSVD163

SA_DQ59 SA_DQ60

RSVD161

RSVD160

SYM 4 OF 12

MEMORY CHANNEL B

SB_DQ29

SB_DQ28

RSVD171

SB_CKN0

SB_CKE0

RSVD181

RSVD180

RSVD179

RSVD178

RSVD177

RSVD176

RSVD175

RSVD174

RSVD173

RSVD172

SB_DQSN3

SB_DQSN6

SB_DQS0 SB_DQS1

SB_DQS5

SB_DQS3 SB_DQS4

SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35

SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7

SB_CKE1 SB_DQ8 SB_DQ9 SB_DQ10

SB_CKE2 SB_DQ11

SB_DQ12 SB_DQ13 SB_DQ14 SB_CKE3 SB_DQ15 SB_DQ16 SB_CS0* SB_DQ17 SB_CS1* SB_DQ18 SB_CS2* SB_DQ19 SB_CS3* SB_DQ20

SB_ODT0 SB_DQ21

SB_ODT1 SB_DQ22

SB_ODT2 SB_DQ23

SB_ODT3 SB_DQ24

SB_DQ25

SB_BS0

SB_DQ26

SB_BS1

SB_DQ27

SB_DQ30

SB_RAS*

SB_WE*

SB_CAS*

SB_MA0 SB_MA1

SB_DQ36

SB_MA2

SB_DQ37

SB_MA3

SB_DQ38

SB_MA4

SB_DQ39

SB_MA5

SB_DQ40

SB_MA6

SB_DQ41

SB_MA7

SB_DQ42

SB_MA8

SB_DQ43

SB_MA9

SB_DQ44

SB_MA10 SB_DQ45

SB_MA11 SB_DQ46

SB_MA12 SB_DQ47

SB_MA13 SB_DQ48

SB_MA14 SB_DQ49

SB_MA15 SB_DQ50

SB_DQ51

SB_DQSN0

SB_DQ52

SB_DQSN1

SB_DQ53

SB_DQSN2

SB_DQ54 SB_DQ55

SB_DQSN4

SB_DQ56

SB_DQSN5

SB_DQ57 SB_DQ58

SB_DQSN7

SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

SB_DQS2

SB_DQS6

SB_DQS7

SB_CKP0

SB_CKN1

SB_CKP1

SB_CKN2

SB_CKP2

SB_CKN3

SB_CKP3

SB_BS2

VSS_AU30

BI

OUT

OUT OUT OUT

OUT

OUT OUT OUT

OUT

OUT OUT

OUT

OUT OUT

OUT

OUT OUT OUT OUT

OUT

OUT OUT OUT

BI

BI BI

BI

BI BI

NC

NC NC

NC NC NC

NC

NC NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

22

25 75

23 75

HASWELL

BGA

OMIT_TABLE

U0500

OMIT_TABLE

HASWELL

BGA

U0500

25 75

23 75

24 75

25 75

SYNC_DATE=01/14/2013SYNC_MASTER=J16_DINI

CPU DDR3 Interfaces

MEM_A_DQ<23>

MEM_A_DQ<22>

MEM_B_DQ<18>

MEM_B_DQ<16>

CPU_DIMM_VREFCA

MEM_B_DQS_P<6> MEM_B_DQS_P<7>

MEM_A_DQ<57> MEM_A_DQ<58> MEM_A_DQ<59>

MEM_B_DQ<52>

CPU_DIMMA_VREFDQ

CPU_DIMMB_VREFDQ

MEM_A_DQ<14>

MEM_A_DQ<17>

MEM_A_DQS_P<0> MEM_A_DQS_P<1> MEM_A_DQS_P<2> MEM_A_DQS_P<3> MEM_A_DQS_P<4> MEM_A_DQS_P<5>

MEM_A_DQS_P<7>

MEM_A_DQS_P<6>

MEM_A_DQS_N<0> MEM_A_DQS_N<1> MEM_A_DQS_N<2> MEM_A_DQS_N<3> MEM_A_DQS_N<4>

MEM_A_DQS_N<6>

MEM_A_DQS_N<5>

MEM_A_DQS_N<7>

MEM_B_DQS_P<0> MEM_B_DQS_P<1> MEM_B_DQS_P<2> MEM_B_DQS_P<3> MEM_B_DQS_P<4> MEM_B_DQS_P<5>

MEM_B_DQS_N<1>

MEM_B_DQS_N<3> MEM_B_DQS_N<4> MEM_B_DQS_N<5> MEM_B_DQS_N<6> MEM_B_DQS_N<7>

MEM_A_A<15>

MEM_A_A<14>

MEM_A_A<13>

MEM_A_A<12>

MEM_A_A<11>

MEM_A_A<10>

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<7>

MEM_A_A<6>

MEM_A_A<5>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_A<2>

MEM_A_A<1>

MEM_A_A<0>

MEM_A_CAS_L

MEM_A_WE_L

MEM_A_RAS_L

MEM_A_BA<2>

MEM_A_BA<1>

MEM_A_BA<0>

MEM_A_ODT<1>

MEM_A_ODT<0>

MEM_A_CS_L<0>

MEM_A_CKE<1>

MEM_A_CLK_P<1>

MEM_A_CLK_N<1>

MEM_B_A<15>

MEM_B_A<14>

MEM_B_A<13>

MEM_B_A<11>

MEM_B_A<10>

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<7>

MEM_B_A<3>

MEM_B_A<2>

MEM_B_A<1>

MEM_B_A<0>

MEM_B_CAS_L

MEM_B_WE_L

MEM_B_RAS_L

MEM_B_ODT<1>

MEM_B_ODT<0>

MEM_B_CS_L<0>

MEM_B_CKE<1>

MEM_B_CLK_P<1>

MEM_B_CLK_N<1>

MEM_B_CKE<0>

MEM_B_CLK_P<0>

MEM_B_CLK_N<0>

MEM_A_DQ<60>

MEM_B_DQ<62> MEM_B_DQ<63>

MEM_B_DQ<61>

MEM_B_DQ<56> MEM_B_DQ<57> MEM_B_DQ<58> MEM_B_DQ<59> MEM_B_DQ<60>

MEM_B_DQ<51>

MEM_B_DQ<53> MEM_B_DQ<54> MEM_B_DQ<55>

MEM_B_DQ<46> MEM_B_DQ<47> MEM_B_DQ<48> MEM_B_DQ<49> MEM_B_DQ<50>

MEM_B_DQ<41> MEM_B_DQ<42> MEM_B_DQ<43> MEM_B_DQ<44> MEM_B_DQ<45>

MEM_B_DQ<36> MEM_B_DQ<37> MEM_B_DQ<38> MEM_B_DQ<39> MEM_B_DQ<40>

MEM_B_DQ<31> MEM_B_DQ<32> MEM_B_DQ<33> MEM_B_DQ<34> MEM_B_DQ<35>

MEM_B_DQ<26> MEM_B_DQ<27> MEM_B_DQ<28> MEM_B_DQ<29> MEM_B_DQ<30>

MEM_B_DQ<25>

MEM_B_DQ<21> MEM_B_DQ<22> MEM_B_DQ<23> MEM_B_DQ<24>

MEM_B_DQ<20>

MEM_B_DQ<15>

MEM_B_DQ<17>

MEM_B_DQ<19>

MEM_B_DQ<10> MEM_B_DQ<11> MEM_B_DQ<12> MEM_B_DQ<13> MEM_B_DQ<14>

MEM_B_DQ<5> MEM_B_DQ<6>

MEM_B_DQ<8>

MEM_B_DQ<0>

MEM_B_DQ<2>

MEM_B_DQ<4>

MEM_A_DQ<62> MEM_A_DQ<63>

MEM_A_DQ<61>

MEM_A_DQ<56>

MEM_A_DQ<55>

MEM_A_DQ<52>

MEM_A_DQ<50>

MEM_A_DQ<49>

MEM_A_DQ<48>

MEM_A_DQ<47>

MEM_A_DQ<46>

MEM_A_DQ<44>

MEM_A_DQ<43>

MEM_A_DQ<42>

MEM_A_DQ<41>

MEM_A_DQ<40>

MEM_A_DQ<39>

MEM_A_DQ<38>

MEM_A_DQ<36> MEM_A_DQ<37>

MEM_A_DQ<35>

MEM_A_DQ<34>

MEM_A_DQ<33>

MEM_A_DQ<31> MEM_A_DQ<32>

MEM_A_DQ<30>

MEM_A_DQ<29>

MEM_A_DQ<28>

MEM_A_DQ<26> MEM_A_DQ<27>

MEM_A_DQ<25>

MEM_A_DQ<24>

MEM_A_DQ<21>

MEM_A_DQ<20>

MEM_A_DQ<19>

MEM_A_DQ<18>

MEM_A_DQ<16>

MEM_A_DQ<15>

MEM_A_DQ<13>

MEM_A_DQ<12>

MEM_A_DQ<11>

MEM_A_DQ<9>

MEM_A_DQ<8>

MEM_A_DQ<7>

MEM_A_DQ<6>

MEM_A_DQ<5>

MEM_A_DQ<4>

MEM_A_DQ<1>

MEM_A_DQ<0>

MEM_A_DQ<53>

MEM_A_DQ<51>

MEM_A_DQ<54>

MEM_A_DQ<45>

MEM_A_CS_L<1>

MEM_A_DQ<3>

MEM_A_DQ<2>

MEM_B_BA<2>

MEM_B_DQ<9>

MEM_B_DQ<7>

MEM_B_DQ<3>

MEM_B_DQ<1>

MEM_B_DQS_N<0>

MEM_B_DQS_N<2>

MEM_A_DQ<10>

MEM_A_CKE<0>

MEM_A_CLK_P<0>

MEM_A_CLK_N<0>

MEM_B_CS_L<1>

MEM_B_BA<1>

MEM_B_BA<0>

MEM_B_A<4> MEM_B_A<5> MEM_B_A<6>

MEM_B_A<12>

051-0164

12.4.0

7 OF 123

7 OF 867 OF 86

7 OF 123

12.4.0

051-0164

AN53

AR53

AN54

AV54

AY54 AY53

AY47

BC23

BD23

BF23

BC25

BD25

BF25

BE25

BF34

BC17

AV51

AM6

AT2

BA3

BE7

BD12

AY46

AW52

AP53

AJ52

AT3

BA2

BE12 BD7

BA46

AW53

AP52

AJ53

BE20

BC31

BF31

BC32

BE27

BC28

BC27

BF27

BF32

BF28

BE28

BD28 BD27

BE21

BF21

BC21

BF20

BD21

BD32

BD17

BC20

BF17

BF16

BC16

BD16

BE17

BE16

BD34

BC34

BE34

BA49

AH54 AH52

AK51

AN52

AN51

AR52 AR54

AV52

AV53 AY52

AY51

AY49 BA47

BA45

AY45 AY43

BA43 BF14

BC14 BC11

BF11

BE14 BD14

BD11

BE11

BC9

BE9

BE6 BC6

BD9

BB4

BC2

AW3 AW2

BB3

BB2 AW4

AW1 AU3

AU1

AR1

AU4 AR2

AR3

AH53

AK54

AR51

AK53

AH51

AK52

BD6

BE5

BF9

AN6

AR6

BC53

AW40

BA39

AU40

BE23

BD20

BE32 BE31

AU39

AV39

AV40

AY39

AY40

BA40

AR4

AU2

AW39

BD31

BC44

BF44

AY36

AW27

AU36

BD37

BC37

BC39

BD39

BE37

BF37

BE39

BF39

BD38

BE38

BD43

AW8

AD53

AV46

AW12

BE43

AW15

BE42 BA16

AU16 BA15

AV15

AC54 AC52

AE51

AE54 AC53

AC51

AE52 AE53 AU35

AU47

AU49 AV43

AV35

AV45 AU43

AU45

AV47 AV36 AV49

BC49 BA20

BE49 AY19 BD47 AU19

BC47 AW20

BD49

AY20

BD50

BA19

BE47

AV19

BF47

AW19

BE44

BD44 AY23 BC42 BA23

BF42

BD42

AV23

AW23

AV20

BA30 AW30

AY16

AY30

AV16

AV30

AY15

AW32

AU15

AY32

AU12

AT30

AY12

AV32

BA10

BA32

AU10

AU32

AV12

AU23

BA12

AY35

AY10

AW35

AV10

AU20

AU8

AW36

BA8

BA35

AV6 BA6

AD52

AV8

AU46

AY8

BD48

AU6

AY6

AW16

AM2

AW10

AM3

AK1

AL2

AK4

AM1

AM4 AK2

AK3

BE48

AW6 AL3

AV27

AW26

AV26

BA26

AY26

BA27

AY27

BA36

AU30

BI

OUT

IN

SYM 5 OF 12

RSVD68

VIDSOUT

VIDSCLK

VIDALERT*

RSVD79(VSS)

RSVD78 VSS_V50(RSVD)

VSS_AP50(RSVD)

VSS_AP49(RSVD)

VSS_AN49(RSVD)

VSS_AM50(RSVD)

IVR_ERROR

VSS_AK49(RSVD)

VSS_AJ49(RSVD)

VSS_AJ50(RSVD)

VSS_AG50(RSVD)

VSS_AD50(RSVD)

VSS_AB50(RSVD)

FC_F17

RSVD65

RSVD69

RSVD67

RSVD66

RSVD74

RSVD73

RSVD72

RSVD71

RSVD70

VCC_L6 VCC_M6

VCOMP_OUT

VCC_SENSE

VSS_B51

FC_D5 FC_D3

VDDQ

VCC

VCCIO_OUT

RSVD76

RSVD75

VSS_E52

PWR_DEBUG

RSVD64

SYM 6 OF 12

POWER

VCC VCC

IN

OUT

NC NC NC NC

NC NC

NC NC NC NC

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Max load: 300mA

Connections would be required for 2014 CPU support.

R0802.2:

R0800.2:

R0810.2:

Max load: 300mA

NOTE: Aliases not used on CPU supply outputs to avoid any extraneous connections.

R0812

0

5% 1/16W MF-LF

402

61 83

R0802

110

PLACE_NEAR=U0500.J50:2.54mm

402

1/16W

1%

MF-LF

R0811

0

402

5%

MF-LF

1/16W

61 83

R0810

PLACE_NEAR=U0500.J53:38mm

5%

402

MF-LF

1/16W

43

61 83

R0800

PLACE_NEAR=R0810.1:2.54mm

75

1% 1/16W MF-LF

402

U0500

OMIT_TABLE

HASWELL

BGA

U0500

OMIT_TABLE

HASWELL

BGA

18

R0860

PLACE_NEAR=U0500.C50:50.8mm

PLACE_SIDE=BOTTOM

100

1/16W MF-LF

402

5%

61 83

CPU Power

SYNC_DATE=01/14/2013SYNC_MASTER=J16_DINI

PPVCCIO_S0_CPU

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

PPVCOMP_S0_CPU

CPU_VIDSCLK

CPU_VIDSCLK_R

=PPVCC_S0_CPU

CPU_VCCSENSE_P

TP_CPU_RSVD_TP78

TP_CPU_RSVD_TP76

TP_CPU_RSVD_TP75

=PPVCC_S0_CPU

=PP1V5R1V35_S0_CPU

CPU_PWR_DEBUG

CPU_VIDSOUT

TP_CPU_FC_VCCST_PWRGD

TP_CPU_FC_VCCST

CPU_VIDALERT_L

TP_CPU_IVR_ERROR

CPU_VIDALERT_R_L

CPU_VIDSOUT_R

12.4.0

8 OF 123

8 OF 86

051-0164

1 2

1

2

1 2

1

2

AN31

BE33

BE30

BE26

BE22

BD26

J50

J52

J53

J12

W49

V50

AP50

AP49

AN49

AM50

AM49

AK49

AJ49

AJ50

AG50

AD50

AB50

F17

F31

E39

J21

AN22

J31

J26

AR49

W9

AN33

AH9

AN18

L6 M6

AK6

C50

B51

BE18

BD33

BD30

BD22

BB36

BB34

BB31

BB30

BB27

BB26

BB22

BB21

AY18

AW29

AW25

AW22

AV37

AT36

AT32

AT27

AT23

AT19

AT13

AR33

AR31

D5

D3

AR29

A36 A38

A39

A42 A43

AA47

AA8

AA9

AW33

B43

B45 B46

B48 C27

C28

C31 C32

C34

C36 C38

C39

C42 C43

C45 C46

C48

D27 D28

D31

D32 D34

D36

D38 D39

D42 D43

D45

D46 D48

E27

E28 E31

E32

E34 E36

E38

E42

E43 E45

E48 F27

F28

F32

F34 F36

F38

F39 F42

F43

F45 F46

F48

G27 G29

G31 G32

G34

G38

G39

G42 G43

G45

G46 G48

H11 H12

H13

H14 H16

H17

H18 H19

H20

H21 H23

H24 H25

H26

H27 H29

G36

D51

E46

U49

V49

E52

F19

A46

A48

AA46

A45

J17

H32

H31

H30

AR46

AR45

AR43

AR41

AR39

AR37

AR35

AP9

AP8

AP47

AP46

AP44

AP43

AP42

AP41

AP40

AP39

AP38

AP37

AP36

AP35

AP34

AP33

AP32

AP31

AP30

AP29

AP27

AP26

AP25

AP24

AP23

AP22

AP21

AP20

AP19

AP18

AP17

AP16

AP15

AP14

AP13

AP12

AP10

AN9

AN8

AN46

AN45

AN44

AN43

AN42

AB8

AD8

AC9

AC8

AE46

AC47

AC46

AB46

AB45

AD46

AG8

AF8

AE8

AH8

AH47

AH46

AG46

AE47

AJ45

AJ46

AK8

AL8

AL9

AM8

AK46

AK47

AL45

AL46

AM46

AM47

AM9

AN10

AN12

AN13

AN14

AN15

AN16

AN17

AN19

AN20

AN21

AN23

AN24

AN27

AN29

AN30

AN32

AN34

AN36

AN38

AN39

AN41

AN40

H33

H34

H36

H37

H38

H39

H40

H42

H43

H45

H46

H48H8H9

J10

J14

J19

J24

J29

J33

J36

J37

J40

J42

J43

J45

J46

J48J8J9

K38

K40

K43

K44

K45

K46

K48K8K9

L37

L38

L39

L40

L42

L43

L44

L46

L47L8M37

M38

M39

M40

M42

M43

M44

M45

M46M8M9

N37

N38

N39

N40

N42

N43

N44

N46

N47N8N9

P45

P46P8R46

R47R8R9

T45

T46

U46

U47U8U9

V45

V46

V8

J39

J38

W46

W47W8Y45

Y46Y8A27

A28

A31

A32

A34

B27

B28

B31

B32

B34

B36

B38

B39

B42

AN25

AN26

1

2

5 6

10 18 61

5

83

6 8

10 70

6 8

10 70

83

SYM 7 OF 12

GROUND

VSS VSS

SYM 8 OF 12

GROUND

VSSVSS

SYM 9 OF 12

VSS_P9(RSVD)

VSS_G18(RSVD)

VSS_AR22(RSVD)

VSS_AB48(RSVD)

VSS_NCTF

VSS_SENSE

VSS

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

U0500

HASWELL

OMIT_TABLE

BGA

U0500

HASWELL

OMIT_TABLE

BGA

U0500

HASWELL

OMIT_TABLE

BGA

61 83

R0960

PLACE_NEAR=U0500.D50:50.8mm PLACE_SIDE=BOTTOM

402

MF-LF

1/16W

5%

100

CPU Ground

SYNC_MASTER=J16_DINI SYNC_DATE=01/14/2013

CPU_VCCSENSE_N

051-0164

12.4.0

9 OF 123

9 OF 86

AP51

AP54 AP7

AR20

AN48

AN4

AN3

AM53

AM5

AL7

A11 A15

A19

A22 A26

A30

A33 A37

A40 A44

AA1

AA2 AA3

AA4

AA48

AA5

AA7

AB51

AB52 AB53

AB54

AB7 AB9

AC48

AC5

AC50

AC7

AD48 AD51

AD54

AD7

AD9

AE1 AE2

AE3

AE4

AE48

AE5

AE50

AE7

AF5 AF6

AF7

AG48

AG5

AG51

AG52 AG53

AG54

AG7 AG9

AH1 AH2

AH3

AH4

AH48

AH5

AH50

AH7

AJ48 AJ51

AJ54

AK48 AK5

AK50

AK7 AK9

AL1 AL4

AL48

AL5

AM51 AM52

AM54 AM7

AN1 AN2

AN5

AN50 AN7

AR12 AR14

AR16

AR18

AR24

AR26 AR48

AR5

AR50 AR7

AR8 AR9

AT1

AT10 AT12

AT15

AT16 AT18

AT20

AT22 AT25

AT26 AT29

AT33

AT35 AT37

AT39

AT4

AB5

AU29

AU33

AU37

BB9

BB7

BB6

BB5

BB49

BB48

BB47

BB46

BB44

BB43

BB42

BB41

BB39

BB38

BB37

BB33

BB32

BB28

BB25

BB23

BB20

BB18

BB17

BB16

BB15

BB14

BB12

BB11

BB10

BA9

BA53

BA52

BA51

BA50

BA5

BA42

BA4

BA37

BA33

BA29

BA25

BA22

BA18

BA13

B8

B30

B26

B22

B19

B15

B11

AY9

AY50

AV42

AV4

AY42

AY37

AY33

AY29

AY25

AY22

AY13

AW9

AW54

AW51

AW50

AW5

AW49

AW47

AW46

AW45

AW43

AW42

AW37

AW18

AW13

AV9

AV50

AV5

AV33

AV3

AV29

AV25

AV22

AV2

AV18

AV13

AV1

AU9

AU5

AU42

AU18

AU13

AT9

AT8

AT6

AT54

AT53

AT52

AT51

AT46

AT45

AT43

AT42

B37

B33

B44 B49

B40

AT50

AT5

AT49

AT47

AU22

AU25

AT40

P9

G18

AR22

AB48

H44

BC30

BC33

G33

G37

BC50

BC52

BC7

J51

A49

BD53

BF5

BF50

C53D2F54

G1

D50

W54

BC10

BC12

BC15

BC18

BC22

BC26

BC3

BC36

BD10

BD15

BD18

BD36

BD41

BD46

BD5

BD51

BE10

BE15

BE36

BE41

BE46

BF10

BF15

BF18

BF22

BF26

BF30

BF33

BF41

BF43

BF46

BF48

BF7

C11

C19

C22

C26

C30

C33

C37C4C40

C44

C49

C52C8D11

D15

D19

D22

D26

D30

D33

D37

D8

E11

E15

E16

E17

E19

E20

E21

E22

E24

E25

E26

E30

E33

E37

E40

E44

E49

E51

E53

E8

F3

F33

F37F4F40

F44

F49F5G11

G13

G16

D49

D44

D40

BF38

BF12

BC5

G20

G30

G40

G44

G49

G52

G54

G7G8G9

H49H7J44

J49

J54J7K1K2K3K4K5K6K7

L48L7L9

M48

M50

M52

M54M7N48N7P1P2P3P4P48P5P50

P52

P54P6P7

R48R7T48U1U2U3U4

U48U5U50

U52

U54U6U7

V48V7V9

W48

W50

W52W7Y48Y9Y7

A50A8B4

BA1

BA54

BB1

BB54

BD2

BF49

BF6

E54

C15

F30

F26

F2

G26

G25

G23

BC48

BC46

BC43

BC41

BC38

BF36

1

2

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

For noise floor mitigation of DP (C1070-C1075):

Intel recommendation: 4x 470uF 4mOhm (3 CPU-side, 1 opposite), 20x 22uF 0805 (10 CPU-side, 10 opposite near edge, 4x 10uF 0603 (2 CPU-side, 2 opposite), 20x 1uF 0402 (under CPU) Apple Implementation: 9x 210uF 6mOhm, 44x 10uF 0402, 4x 10uF 0402, 20x 1uF 0402

BULK CAPS ON REGULATOR PAGE

PLACEMENT_NOTE (C1020-C1023):

CPU VCORE Decoupling

PLACEMENT_NOTE (C1000-C1019):

PLACEMENT_NOTE (C1024-C1045):

Apple Implementation: 2x 0.01uF 0402 (second cap is on CPU VR page)

PLACEMENT_NOTE (C1046-C1067):

PLACEMENT_NOTE (C1080-C1089):

Intel recommendation: 2x 330uF, 8x 10uF 0603, 10x 1uF 0402

CPU VDDQ Decoupling

Apple Implementation: 2x 330uF, 8x 10uF 0603, 10x 1uF 0402

PLACEMENT_NOTE (C1090-C1097):

NOTE: Intel decoupling recommendations from Shark Bay Mobile Platform Power Delivery Design Guide (doc #487822, Rev 0.8 dated January 2012), Section 5.

Intel recommendation: 2x 0.01uF 0402 (1 near CPU, 1 near SVID pull-ups)

CPU VCCIO Decoupling

BULK CAPS ON REGULATOR PAGE

C1009

0402

Place on bottom side of U0500

1UF

X6S-CERM

10V

10%

C1008

0402

Place on bottom side of U0500

10% 10V X6S-CERM

1UF

C1007

Place on bottom side of U0500

10% 10V X6S-CERM

1UF

0402

C1031

Place near inductors on bottom side.

4V X6S 0402

10UF

20%

CRITICAL

C1006

1UF

10% 10V X6S-CERM 0402

Place on bottom side of U0500

C1005

0402

Place on bottom side of U0500

1UF

X6S-CERM

10V

10%

C1004

1UF

10% 10V X6S-CERM 0402

Place on bottom side of U0500

C1003

Place on bottom side of U0500

1UF

10V

10%

0402

X6S-CERM

0402

Place on bottom side of U0500

1UF

10V

10%

C1002

X6S-CERM

0402

Place on bottom side of U0500

1UF

X6S-CERM

10V

10%

C1001C1000

0402

Place on bottom side of U0500

X6S-CERM

10V

10%

1UF

0402

X6S

4V

Place near inductors on bottom side.

10UF

20%

C1030

CRITICAL

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

C1029

CRITICAL

C1027

X6S

4V

0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1026

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1020

20%

0402

10UF

X6S

4V

Place near U0500 on bottom side

C1021

20%

0402

4V X6S

10UF

Place near U0500 on bottom side

20%

0402

4V X6S

Place near U0500 on bottom side

10UF

C1022

Place near U0500 on bottom side

0402

X6S

20% 4V

10UF

C1023

C1025

4V X6S 0402

10UF

20%

CRITICAL

Place near inductors on bottom side.

C1024

4V X6S 0402

10UF

20%

CRITICAL

C1028

CRITICAL

0402

10UF

4V X6S

20%

Place near inductors on bottom side.

C1032

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1033

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1039

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1038

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1037

10UF

4V X6S 0402

20%

Place near inductors on bottom side.

CRITICAL

C1036

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1035

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1034

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1079

10%

0.01UF

16V

0402

X7R-CERM

C1089

X6S-CERM

Place on bottom side of U0500

0402

10% 10V

1UF

C1088

0402

Place on bottom side of U0500

10% 10V X6S-CERM

1UF

C1087

X6S-CERM 0402

10%

Place on bottom side of U0500

10V

1UF

C1086

1UF

10V

0402

Place on bottom side of U0500

10%

X6S-CERM

C1085

X6S-CERM

1UF

0402

Place on bottom side of U0500

10% 10V

C1084

X6S-CERM 0402

Place on bottom side of U0500

10% 10V

1UF

C1083

10V

0402

Place on bottom side of U0500

1UF

X6S-CERM

10%

C1082

1UF

X6S-CERM 0402

Place on bottom side of U0500

10V

10%

C1081

0402

Place on bottom side of U100.

1UF

X6S-CERM

10V

10%

C1080

X6S-CERM 0402

Place on bottom side of U0500

10%

1UF

10V

C1093

Place near U0500 on bottom side

20%

10UF

0603

X6S-CERM

4V

C1092

20%

Place near U0500 on bottom side

10UF

0603

X6S-CERM

4V

C1091

10UF

20% 4V

0603

Place near U0500 on bottom side

X6S-CERM

C1090

20%

Place near U0500 on bottom side

10UF

0603

4V X6S-CERM

C1097

20%

Place near U0500 on bottom side

10UF

0603

X6S-CERM

4V

C1096

20%

Place near U0500 on bottom side

10UF

X6S-CERM

4V

0603

C1095

0603

20%

Place near U0500 on bottom side

10UF

X6S-CERM

4V

C1094

20%

Place near U0500 on bottom side

10UF

0603

X6S-CERM

4V

C1043

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1042

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1041

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1040

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1019

0402

Place on bottom side of U0500

10% 10V X6S-CERM

1UF

C1018

0402

Place on bottom side of U0500

1UF

X6S-CERM

10V

10%

C1017

0402

Place on bottom side of U0500

1UF

X6S-CERM

10V

10%

C1016

0402

Place on bottom side of U0500

10% 10V X6S-CERM

1UF

C1015

0402

Place on bottom side of U0500

10% 10V X6S-CERM

1UF

C1014

0402

Place on bottom side of U0500

1UF

X6S-CERM

10V

10%

C1013

0402

Place on bottom side of U0500

X6S-CERM

10% 10V

1UF

C1012

0402

Place on bottom side of U0500

10% 10V X6S-CERM

1UF

C1011

0402

Place on bottom side of U0500

10% 10V X6S-CERM

1UF

C1010

0402

Place on bottom side of U0500

10% 10V X6S-CERM

1UF

C1065

Place near inductors on bottom side.

4V X6S 0402

10UF

20%

CRITICAL

C1064

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1063

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1062

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1061

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1060

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1059

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1058

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1057

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1056

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1055

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1054

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1053

10UF

CRITICAL

4V X6S 0402

20%

Place near inductors on bottom side.

C1052

X6S

4V

0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1051

4V X6S 0402

20%

Place near inductors on bottom side.

CRITICAL

10UF

C1050C1049

4V

20%

10UF

X6S 0402

Place near inductors on bottom side.

CRITICAL

C1048

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1047

X6S

4V

0402

10UF

20%

CRITICAL

Place near inductors on bottom side.

C1046

X6S

10UF

4V

0402

20%

CRITICAL

C1045

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1044

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1067

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1066

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1070

1.5PF

201

NP0-C0G

25V

+/-0.1PF

C1071

1.5PF

+/-0.1PF 25V NP0-C0G 201

C1072

1.5PF

+/-0.1PF 25V NP0-C0G 201 201

NP0-C0G

25V

+/-0.1PF

1.5PF

C1075C1074

1.5PF

+/-0.1PF 25V NP0-C0G 201

C1073

1.5PF

+/-0.1PF 25V NP0-C0G 201

SYNC_MASTER=J16_DINI SYNC_DATE=01/14/2013

CPU Decoupling

=PP1V5R1V35_S0_CPU

PPVCCIO_S0_CPU

=PPVCC_S0_CPU

10 OF 86

10 OF 123

12.4.0

051-0164

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

8

70

5 6 8

18 61

6 8

70

IN

OUT

IN

OUT

IN

OUT OUT

IN

OUT

NC

HDA_SDI1 HDA_SDI2

TP25 TP22

HDA_DOCK_RST*/GPIO13

SATA_RXP0

SATA_RXP5/PERP2

SATA_RXN5/PERN2

TP8

SRTCRST*

RTCX1 RTCX2

HDA_BCLK

DOCKEN*/GPIO33

SATA_RCOMP

SATA_TXN0

SATA_TXP4/PETP1

SATA_TXP1

SATA_TXN4/PETN1

SATA_TXN1

SATA0GP/GPIO21

SATALED*

SPKR

JTAG_TDI

JTAG_TDO

JTAG_TMS

TP20

JTAG_TCK

INTRUDER*

HDA_SYNC

HDA_SDI3

HDA_SDO

SATA_RXP2

SATA_RXN2

SATA_TXN2 SATA_TXP2

SATA_RXN3 SATA_RXP3 SATA_TXN3

TP9

SATA_IREF

SATA1GP/GPIO19

SATA_TXP0

SATA_RXN1 SATA_RXP1

RTCRST*

INTVRMEN

SATA_RXN0

SATA_RXP4/PERP1

SATA_RXN4/PERN1

SATA_TXP3

SATA_TXP5/PETP2

SATA_TXN5/PETN2

HDA_SDI0

HDA_RST*

JTAG

(1 OF 11)

RTC

AZALIA

SATA

CLOCKS

(2 OF 11)

PCIECLKRQ2*/GPIO20/SMI*

CLKOUT_33MHZ4

PCIECLKRQ5*/GPIO44

CLKOUT_PCIE_P1

CLKOUT_PCIE_N1

PCIECLKRQ0*/GPIO73

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_PCIE_P6

CLKOUT_PCIE_N6

CLKOUT_PCIE_N2 CLKOUT_PCIE_P2

TP18

TP19

CLKOUT_PCIE_N3 CLKOUT_PCIE_P3

PCIECLKRQ6*/GPIO45

CLKOUT_PCIE_P5

CLKOUT_PCIE_N5

PCIECLKRQ1*/GPIO18

CLKOUT_DPNS_N CLKOUT_DPNS_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKOUT_PCIE_N4 CLKOUT_PCIE_P4

PEG_A_CLKRQ*/GPIO47

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

CLKOUT_DP_P

CLKOUT_DP_N

CLKOUT_PCIE_P7

CLKOUT_PCIE_N7

XTAL25_OUT

XTAL25_IN

ICLK_IREF

DIFFCLK_BIASREF

CLKIN_GND_N CLKIN_GND_P

CLKIN_DMI_P

CLKIN_DMI_N

CLKOUT_33MHZ2

CLKIN_SATA_P

CLKIN_SATA_N

CLKOUTFLEX0/GPIO64

CLKIN_33MHZLOOPBACK

CLKOUT_33MHZ0 CLKOUT_33MHZ1

CLKOUTFLEX2/GPIO66

CLKOUTFLEX1/GPIO65

CLKOUTFLEX3/GPIO67

CLKOUT_33MHZ3

REFCLK14IN

CLKIN_DOT96_P

CLKIN_DOT96_N

PCIECLKRQ3*/GPIO25

PEG_B_CLKRQ*/GPIO56

PCIECLKRQ4*/GPIO26

PCIECLKRQ7*/GPIO46

CLKOUT_PEG_B_P

CLKOUT_PEG_B_N

CLKOUT_PCIE_N0 CLKOUT_PCIE_P0

OUT OUT

OUT

IN

IN OUT OUT

OUT OUT

IN

NC NC

NC

OUT

IN OUT

OUT

IN

OUT

IN

NC NC NC NC

OUT OUT

NC

OUT OUT

NC

OUT OUT

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

NOTE: SSC control is ganged on PCIe 0-3 and 4-7 clocks.

(IPD)

PRIMARY HDD

If HDA = S0, must also ensure that signal cannot be high in S3.

Connect to ENET_MEDIA_SENSE via alias if HDA = 3.3V. Connect to ENET_MEDIA_SENSE via 12K R if HDA = 1.5V.

(IPU-RSMRST#)

Unused clock terminations for FCIM Mode

SSD

(IPD-boot)

(IPU)

(IPU-PLTRST#)

If 2 or less devices are attached to PEG the CLKOUT_PEG outputs can be used for those devices.

(IPD-PWROK)

(IPU-RSMRST#)

(IPD-PWROK)

(IPD)

1.5V -> 1.1V

(IPD-boot)

(IPD)

(IPD-PLTRST#)

(IPD)

SATA Port assignments:

PEG-attached (CPU) PCIe devices must use one set, while PCH-attached PCIe devices use the other set.

(IPD)

(IPU)

(IPD-DOCKEN#?)

52 79

R1101

1M

MF 201

5% 1/20W

20K

MF

201

5%

1/20W

R1102

1/20W

R1103

5%

20K

201

MF

1UF

X5R 402

10% 10V

C1103

1UF

X5R 402

10% 10V

C1102

PLACE_NEAR=U1100.AY5:2.54mm

7.5K

MF

201

1%

1/20W

R1130

11 35 80

18 78

1/16W

1%

402

MF-LF

340

R1172

MF

201

1%

1/20W

1K

R1173

19 79

32 77

11 18 32

11 33

11 28

6

77

6

77

6

77

6

77

19 79

4.7K

201

5%

1/20W

MF

R1177

MF5%

1/20W

4.7K

R1178

201

R1134

1/20W

5%

201

MF

10K

1/20W

5%

201

MF

10K

R1142

5%

R1169

1/20W

201

MF

10K

1/20W

5%

201

MF

10K

R1144 R1145

1/20W

5%

201

MF

10K

1/20W

5%

201

MF

10K

R1147 R1114

1/20W

5%

201

MF

10K

2 1

5%

1/20W

201

MF

10K

R1115

R1143

10K

MF

201

5%

1/20W

10K

MF

201

5%

1/20W

R1133

1/20W

5%

201

MF

10K

R1179

10K

MF

201

5%

1/20W

R1146

10K

MF

201

5%

1/20W

R1148

52 79

1/20W

5%

201

MF

10K

R1191

1/20W

5%

201

MF

10K

R1192

201

1/20W

5% MF

10K

R1193

1/20W

5%

201

MF

10K

R1194

1/20W

5%

201

MF

10K

R1195

5%

1/20W

201

MF

10K

R1196

1/20W

5%

201

MF

10K

R1197

1/20W

10K

MF

201

5%

R1170

1/20W

5%

201

MF

10K

R1171

FCBGA

MOBILE

LYNXPOINT

OMIT_TABLE

U1100

FCBGA

OMIT_TABLE

LYNXPOINT

MOBILE

U1100

6

77

6

77

R1110

33

1/20W

5%

201

MF

PLACE_NEAR=U1100.B25:3.7MM

33

201

MF

1/20W

5%

R1113

PLACE_NEAR=U1100.A24:3.7MM

5%

33

201

1/20W

R1111

MF

PLACE_NEAR=U1100.A22:3.5MM

1/20W

5%

201

MF

33

R1112

PLACE_NEAR=U1100.C24:4.5MM

19 79

33 78

35 77

11 18 35

7.5K

201

PLACE_NEAR=U1100.AN44:2.54mm

1%

MF

1/20W

R1190

2 1

11 41 58

R1176

1/20W

5%

201

MF

10K

19 79

33 78

11 18 29 30

11 18

33 77

26 77

R1100

330K

5% 1/20W MF 201

SYNC_MASTER=J16_KENNY

SYNC_DATE=01/21/2013

PCH RTC/HDA/JTAG/SATA/CLK

=PPVRTC_G3_PCH

PCH_SRTCRST_L PCH_INTRUDER_L PCH_INTVRMEN_L

PCH_CLKRQ3_L_GPIO25

PCIE_CLK100M_AP_P

PCH_CLKRQ5_L_GPIO44

=PP3V3_S0_PCH_GPIO

=PP3V3_SUS_PCH_GPIO

HDA_SYNC

PCIE_CLK100M_PCHN PCIE_CLK100M_PCHP

PCH_CLKIN_GNDN

PCH_CLK96M_DOTP

TP_PCH_GPIO64_CLKOUTFLEX0

SYSCLK_CLK25M_SB_R

PCH_CLK100M_SATAP

TP_PCI_CLK33M_OUT2

PCH_CLK96M_DOTN

DP_TBT_SEL

CPU_CLK135M_DPLLSS_P

SATA_HDD_D2R_P

TP_PCI_CLK33M_OUT3

=PP1V5_S0_PCH_VCCVRM_BIAS

RTC_RESET_L

SYSCLK_CLK25M_SB

TP_HDA_SDIN3

PCH_CLK14P3M_REFCLK

PCH_CLKIN_GNDP

PCH_CLK100M_SATAN

TP_PCH_GPIO65_CLKOUTFLEX1 TP_PCH_GPIO66_CLKOUTFLEX2 TP_PCH_GPIO67_CLKOUTFLEX3

PCH_CLK33M_PCIIN

CPU_CLK135M_DPLLSS_N

CPU_CLK135M_DPLLREF_P

CPU_CLK135M_DPLLREF_N

PCH_PEGCLKRQB_L_GPIO56

XDP_PCH_TDO

LPC_CLK33M_SMC_R LPC_CLK33M_LPCPLUS_R

PCH_CLK33M_PCIOUT

DMI_CLK100M_CPU_P

PCH_SATALED_L

XDP_PCH_TDI

TP_HDA_SDIN2

PCH_INTVRMEN_L

PCH_SRTCRST_L

HDA_BIT_CLK

RTC_RESET_L

HDA_RST_R_L

TP_HDA_SDIN1

PCH_INTRUDER_L

PCH_CLK32K_RTCX2

PCH_CLK32K_RTCX1

SATA_HDD_D2R_N

SATA_HDD_R2D_C_P

SATA_HDD_R2D_C_N

SSD_R2D_P<0>

SSD_D2R_N<0> SSD_D2R_P<0>

SSD_D2R_P<1> SSD_R2D_N<1> SSD_R2D_P<1>

SSD_R2D_N<0>

PCH_SATA_RCOMP

SATARDRVR_EN

DP_AUXIO_EN

PCH_PEGCLKRQA_L_GPIO47

DMI_CLK100M_CPU_NPCIE_CLK100M_AP_N

PCIE_CLK100M_ENET_P

PCH_PEGCLKRQB_L_GPIO56

PCH_SATALED_L

SSD_CLKREQ_L

PCH_SPKR

DP_AUXIO_EN

PCH_CLKRQ5_L_GPIO44

TBT_CLKREQ_L

PCH_CLKRQ3_L_GPIO25

ENET_CLKREQ_L AP_CLKREQ_L

PEG_CLKREQ_L PCH_CLKRQ7_L_GPIO46

PCH_PEGCLKRQA_L_GPIO47

ENET_MEDIA_SENSE

HDA_SDOUT_R

DP_TBT_SEL ENET_MEDIA_SENSE

XDP_PCH_TCK

=PP1V5_S0_PCH_SATA

=PP1V5_S0_PCH_CLK

PCH_DIFFCLK_BIASREF

HDA_SDIN0

SSD_D2R_N<1>

XDP_PCH_TMS

SSD_CLKREQ_L

PCIE_CLK100M_ENET_N

PCIE_CLK100M_SSD_P

PCIE_CLK100M_SSD_N

SATARDRVR_EN

AP_CLKREQ_L

ENET_CLKREQ_L

TBT_CLKREQ_L

PCIE_CLK100M_TBT_P

PCIE_CLK100M_TBT_N

PCH_CLKRQ7_L_GPIO46

PEG_CLKREQ_L

HDA_BIT_CLK_R

HDA_SDOUT

PCH_SPKR

HDA_RST_L

HDA_SYNC_R

11 OF 123

11 OF 86

12.4.0

051-0164

1

2

121

2

1

2

1

2

1 2

1

2

1 2

1 2 1 2

1 2

K22 G22

F8

C26

C22

BE8

BE14

BC14

BB2

B9

B5

B4

B25

B17

AY5

AW8

AW15

AW10

AV15

AV10

AT1

AP3

AL10

AE2

AD3

AD1

AB6

AB3

A8

A22

F22

A24

BD9

BB9

AY13

AW13

BC12

BE12 AR13

BA2

BD4

AU2

AY8

BC10

BE10

D9

G10

BC8

BB13

BD13

AT13

AR15

AP15

L22

C24

AF3

A40

AA2

AA42

AA44

AB1

AB35 AB36

AB39

AB40

AB43 AB45

AD38

AD39

AD43

AD45

AE4

AE42

AE44

AF1

AF35

AF36

AF39 AF40

AF43

AF45

AF6

AH43 AH45

AJ39

AJ40

AJ42

AJ44

AL44

AM43

AM45

AN44

AR24

AT24

AW24

AY24

B42

BC6

BE6

C40

D17

D44 E44

F36

F38

F39

F41

F45

G33

H33

T3

U4

V3

Y3

Y38

Y39

Y43 Y45

1 2

1

2

12 15 70

11

12 14 28 70

12 13 14 70

72

79

72

11 41 58

72 17

11 19 45

72

11

11 33

72

11

11 19 45

79

72

11

78

11

11 33

11

11 18 29 30

11

11 28

11

11 18 35

11 18 32

11

11 35 80

19 79

70

19 70

11 18

11

79

11

79

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

DAC_IREF VGA_IRTN

VGA_VSYNC

VGA_HSYNC

PIRQH*/GPIO5

PIRQG*/GPIO4

DDPC_AUXN

EDP_BKLTEN

EDP_VDDEN

GPIO54

GPIO51

GPIO55

GPIO53

DDPC_CTRLCLK

DDPB_CTRLDATA

DDPB_CTRLCLK

DDPC_CTRLDATA

EDP_BKLTCTL

PIRQF*/GPIO3

DDPC_HPD

DDPC_AUXP DDPD_AUXP

DDPB_HPD

DDPD_HPD

PIRQE*/GPIO2

DDPD_CTRLDATA

DDPD_CTRLCLK

VGA_RED

PIRQA*

GPIO52

GPIO50

PIRQD*

PIRQC*

PIRQB*

PME*

PLTRST*

DDPB_AUXN

VGA_BLUE VGA_GREEN

DDPB_AUXP

DDPD_AUXN

VGA_DDC_DATA

VGA_DDC_CLK

CRT

PCI

DISPLAY

(5 OF 11)

EDP

OUT

IN

OUT

IN

BI

OUT

IN

SYSTEM POWER

MANAGEMENT

(4 OF 11)

DMI

FDI

SUSACK*

RI*

DPWROK

BATLOW*/GPIO72

PWRBTN*

RSMRST*

DRAMPWROK

SLP_LAN*

SLP_A*

PWROK

SLP_SUS*

ACPRESENT/GPIO31

SLP_WLAN*/GPIO29

DSWVRMEN

SLP_S4*

DMI_TXN1

DMI_TXN3

DMI_TXN2

DMI_TXP1

DMI_TXP0

TP5

PMSYNCH

DMI_RXN0

TP15

TP16

TP13

TP17

DMI_RXN1

SYS_RESET*

FDI_RXP1

FDI_RXN1

FDI_RXP0

FDI_RXN0

APWROK

TP21

SUSWARN*/SUSPWRNACK/GPIO30

DMI_TXN0

FDI_RCOMP

DMI_TXP2 DMI_TXP3

DMI_IREF

TP12

DMI_RCOMP

TP7

WAKE*

SUS_STAT*/GPIO61

SUSCLK/GPIO62

SLP_S5*/GPIO63

DMI_RXP0

DMI_RXP3

DMI_RXP2

DMI_RXP1

TP10

SLP_S3*

CLKRUN*

SYS_PWROK

DMI_RXN2

FDI_IREF

FDI_INT

FDI_CSYNC

DMI_RXN3

OUT

IN IN IN

OUT

NC NC NC

NC NC

NC

NC NC

OUT

IN

NC

IN

NC NC NC

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DG v1.0 (Table 12-18).

Redundant to pull-up on audio page

VGA DAC Disabled per SB

(IPD-DeepSx)

(IPU-RSMRST#)

(IPD-PLTRST#)

(IPU)

(IPU-PWROK&PCIRST#)

(OD)

(IPD-PLTRST#)

(IPU)

(IPD-PLTRST#)

(IPD-DeepSx)

(IPU)

Redundant to pull-up on audio page

5

77

5

78

1%

7.5K

R1200

PLACE_NEAR=U1100.AY17:12.7mm

MF

1/20W

201

5

77

5

77

5

77

5

77

5

77

5

77

5

77

5

77

5

77

5

77

5

77

5

77

5

77

5

77

5

77

FCBGA

LYNXPOINT

OMIT_TABLE

MOBILE

U1100

10K

R1205

MF

1/20W

201

5%

12

19 44

18 45 69

6

21

18 20 39 69

69

12 18 69

12 18 44

12

12 32 36

12 44 45 46

20 44 46

45 79

12 32 44 68

12 44 68

12 21 36 44 45 68 69

6

76

12 18 69

100K

R1223

2 1

MF

1/20W

201

5%

1K

R1225

MF

1/20W

201

5%

NO STUFF

10K

R1291

MF

1/20W

201

5%

100K

R1222

2 1

MF

1/20W

201

5%

100K

R1221

2 1

MF

1/20W

201

5%

100K

R1224

2 1

MF

1/20W

201

5%

FCBGA

LYNXPOINT

MOBILE

OMIT_TABLE

U1100

5

78

PLACE_NEAR=U1100.AR44:12.7mm

1%

7.5K

R1210

MF

1/20W

201

10K

R1261

MF

1/20W

201

5%

R1263

10K

MF

1/20W

201

5%

R1262

10K

MF

1/20W

201

5%

10K

R1260

MF

1/20W

201

5%

NO STUFF

10K

R1233

MF

1/20W

201

5%

R1231

10K

MF

1/20W

201

5%

R1230

10K

MF

1/20W

201

5%

100K

R1217

MF

1/20W

201

5%

10K

R1218

MF

1/20W

201

5%

12 20

10K

R1216

MF

1/20W

201

5%

12 58

12 26

12 56

20

R1286

0201

MF

1/20W

0

5%

12 20

12 32

1

3.0K

R1239

2

MF

1/20W

201

5%

45

R1226

10K

MF

1/20W

201

5%

26

12 32 36

12 37

10K

R1240

MF

1/20W

201

5%

100K

R1214

NO STUFF

MF

1/20W

201

5%

330K

R1215

MF

1/20W 201

5%

R1209

10K

MF

1/20W 201

5%

PCH DMI/FDI/PM/GFX/PCI

SYNC_MASTER=J16_KENNY

SYNC_DATE=01/21/2013

FDI_CSYNC FDI_INT

PCH_DSWVRMEN

PM_RSMRST_PCH_L

PCH_GPIO72

AUD_IP_PERIPHERAL_DET

SDCONN_OC_L

TBT_PWR_REQ_L AUD_I2C_INT_L

TP_PCH_SLP_WLAN_L

=PP3V3_SUS_PCH_GPIO

PCH_SUSACK_L

TP_PCH_SLP_LAN_L

PM_SYNC

TP_DP_IG_B_AUXCHP

TP_DP_IG_D_AUXCHP

TP_DP_IG_B_HPD

PM_PCH_SYS_PWROK

PM_PCH_APWROK

PM_SYSRST_L

PM_PCH_PWROK

DMI_S2N_P<1>

DMI_S2N_N<2>

DMI_S2N_N<1>

DMI_S2N_P<3>

DMI_N2S_N<0> DMI_N2S_N<1>

PCIE_WAKE_L

DMI_S2N_P<2>

DMI_S2N_P<0>

DMI_S2N_N<3>

DMI_S2N_N<0>

DMI_N2S_P<3>

DMI_N2S_P<1> DMI_N2S_P<2>

DMI_N2S_P<0>

DMI_N2S_N<3>

DMI_N2S_N<2>

PLT_RESET_L

TP_PCI_PME_L

TP_DP_IG_D_AUXCHN

TP_DP_IG_C_AUXCHN

TP_DP_IG_D_DDC_CLK TP_DP_IG_D_DDC_DATA

TP_DP_IG_C_DDC_CLK

TP_DP_IG_B_DDC_CLK TP_DP_IG_B_DDC_DATA

PM_SLP_S4_L

TP_DP_IG_B_AUXCHN

=PP1V5_S0_PCH_RCOMP

TP_DP_IG_C_DDC_DATA

TP_DP_IG_C_HPD

TP_DP_IG_C_AUXCHP

PM_SLP_SUS_L

PM_SLP_S5_L

PM_CLK32K_SUSCLK_R

LPC_PWRDWN_L

PCH_RI_L

PM_RSMRST_PCH_L

PM_MEM_PWRGD

PCH_SUSWARN_L

PM_SLP_S4_L

BT_PWR_RST_L

PCH_STRP_TOPBLK_SWP_L

AUD_I2C_INT_L

PCI_INTD_L

TP_DP_IG_D_HPD

PM_SLP_S3_L

PM_SLP_S5_L PM_SLP_SUS_L

TP_PCH_STRP_ESI_L

=TBT_WAKE_LPCIE_WAKE_L

MAKE_BASE=TRUE

TP_PCH_STRP_BBS1

AUD_IPHS_SWITCH_EN_PCH

ENET_LOW_PWR_PCH

PCI_INTB_L

PCI_INTA_L

PM_PWRBTN_L

TBT_PWR_REQ_L

ENET_LOW_PWR_PCH

AUD_IP_PERIPHERAL_DET

=PP1V5_S0_PCH_RCOMP

PCH_FDI_RCOMP

PCH_GPIO31

=PPVRTC_G3_PCH

PM_PWRBTN_L

PCH_GPIO72

=PP3V3_S0_PCH_GPIO

PCH_GPIO31

=PP3V3_S0_PCH_GPIO

=PP3V3_S5_PCH_GPIO

SDCONN_OC_L

BT_PWR_RST_L

PM_CLKRUN_L

AUD_IPHS_SWITCH_EN_PCH

PCI_INTC_L

TP_PM_SLP_A_L

PM_SLP_S3_L

PM_CLKRUN_L

PCH_DMI_RCOMP

12 OF 86

12 OF 123

12.4.0

051-0164

1

2

U40 U39

N44

N42

M15

L15

K43

K36

G36

C12

C10

AL6

A10

R35

R39

R40

R36

N36

F17

K38

K45

J44

K40

H39

G17

N38

N40

V45

H20

B13

A12

M20

K17

L20

AD10

Y11

H45

T45

U44

H43

J42

M45

M43

1

2

1 2

R6

N4

L13

K7

K1

J2

H3

G5

F3

F10

F1

E6

D2

C8

C6

BE20

BE18

BD17

BC20

BB21

AY45

AY3

AW22

AV45

AV43

AU44

AU42

AR20

AM1

AL36

AL35

AJ36

AJ35

AB7

AB10

J4

BD21

AR44

BB17 BC18

BE16

AW17

AY17

AV17

K3

U7

Y6

Y7

AY22

AW20

AR17

AP20

AW44

H1

AN7

AD7

AP17

AT45

AL40

AL39

AV20

1

2

1 2

1 2 1 2

1 2

1

2

1 2

1

2

1

2

12

11 13 14 70

71

12 13 70

71

12 44 68

12 56

71

12 21 36 44 45 68 69

12 32 44 68

12

12 18 44

12 26

12 20

12 58

12 13 70

78

12

11 15 70

11 12 14 28 70

12

11 12 14 28 70

70

12 37

12 32

12 44 45 46

12 20

77

BI

BI BI

BI

OC1*/GPIO40 OC2*/GPIO41

OC5*/GPIO9

OC0*/GPIO59

OC3*/GPIO42

OC6*/GPIO10

OC4*/GPIO43

OC7*/GPIO14

USB2P6

USB2N6

USB2P5

USB2N7

USB2N5

USB2N13

USB2P0

USB2P4

USB2P10

USB2P2

USB2P3

USB2P8

PETN7

PETP6

PETN4

PETN3

PETN1_USB3TN3

PCIE_IREF

USB3TP6

USB3TN5

USB3TN1

PETN8 PETP8

PETN5

PCIE_RCOMP

USB3TN6

USB3TN2

USB3TP1

PETP7

PETN6

PETP1_USB3TP3

TP11

USB3TP5

USB3TP2

PETP5

TP6

USB2N0

USB2N4

USB2N10

PERN6

PERP3

PERP1_USB3RP3

PERP6

PERN5

PERN3

PERN1_USB3RN3

USB3RN5

USB3RN2

PERP5

USB3RP5

USB3RP2

PERN7 PERP7

PERN4

PERN2_USB3RN4

PERP4

PERP2_USB3RP4

USB3RN6

USB3RN1

USB3RP6

USB3RP1

PERP8

PERN8

USB2N1

USB2N2

USB2N3

USB2N9 USB2P9

USB2N8

USB2P7

USB2N11

USB2P13

USB2P1

PETP4

USB2P11

PETP2_USB3TP4

PETN2_USB3TN4

PETP3

USB2N12 USB2P12

TP23

TP24

USBRBIAS*

USBRBIAS

(9 OF 11)

USB

PCI-E

BI

OUT

IN

OUT

IN

OUT

SML0CLK

SML1ALERT*/PCHHOT*/GPIO74

LDRQ1*/GPIO23

LAD1

TP3

TP4

TP2

TP1

SPI_CS1*

SERIRQ

SPI_CS0*

SPI_IO2

SPI_IO3

SPI_CLK

SPI_CS2*

SPI_MISO

SPI_MOSI

LAD2

SML1DATA/GPIO75

CL_RST*

SML1CLK/GPIO58

LDRQ0*

TD_IREF

CL_CLK

CL_DATA

SMBALERT*/GPIO11

SMBCLK

SMBDATA

SML0ALERT*/GPIO60

LAD0

SML0DATA

LFRAME*

LAD3

SMBUS

LPC

(3 OF 11)

SPI

C-LINK

IN

BI

OUT

BI

OUT

BI

OUT

BI BI BI

BI BI

IN

OUT

IN

OUT

NC

BI

IN

IN OUT OUT

IN

OUT OUT

IN

OUT OUT

IN

OUT OUT

IN

IN OUT OUT

IN

IN OUT

BI

IN

NC NC

IN IN

OUT OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

NC

BI

NC NC

NC

NC NC

NC

NC NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Ext C (SS)

(IPD)

Ext B (SS)

Ext D (LS/FS/HS)

USB Port Assignments:

Ext C (LS/FS/HS)

Ext A (LS/FS/HS)

Ext B (LS/FS/HS)

(IPU)

(IPU) (IPU)

(IPD)

(IPU)

(IPU-LDRQ1#?)

(IPU)

(IPU/IPD)

CAMERA

BT

Ext A (SS)

USB3 Port Assignments:

Ext D (SS)

(IPU)

AirPort

ENET

TBT

43 80

10K

MF

201

5%

1/20W

R1367

2 1

5%

1/20W

10K

MF

201

R1368

10K

1/20W

MF

201

5%

R1361

10K

MF

201

1/20W

R1362

5%

10K

MF

201

1/20W

5%

R1360

R1369

1/20W

5%

201

MF

10K

42 80

OMIT_TABLE

MOBILE

LYNXPOINT

FCBGA

U1100

42 80

32 77

46 79

MOBILE

LYNXPOINT

OMIT_TABLE

FCBGA

U1100

47

47 81

R1300

7.5K

PLACE_NEAR=U1100.BD29:12.7mm

1/20W

201

MF

1%

201

MF5%

1/20W

33

R1340

MF

201

5%

1/20W

33

R1341

MF

201

5%331/20W

R1343

MF

201

33

1/20W

R1342

5%

201

MF

1/20W

33

R1344

13 20

13 44 46

1/20W

R1350

MF5%

201

10K

44 46 79

8.2K

MF

1/20W

201

1%

R1380

32 80

35 77

R1355

10K

MF

201

5%

1/20W

R1354

10K

MF

201

5%

1/20W

R1353

10K

MF

201

5%

1/20W

5%

201

MF

10K

R1320

10K

R1321

1/20W

5%

201

MF

46 79

5%

10K

MF

201

1/20W

R1351

38 80

42 80

43 80

13 18 42

13 18 43

13 18

13 18 42

13 18 43

13 18

42 80

13 18 37

26 77

42 80

PLACE_NEAR=U1100.K24:11.4mm

1% 1/20W

201

MF

22.6

R1370

PCH PCI-E/USB

SYNC_MASTER=J16_KENNY

SYNC_DATE=01/21/2013

USB_EXTB_OC_L USB_EXTD_OC_L PCH_GPIO10 SDCONN_STATE_CHANGE

PCH_GPIO10

USB_EXTD_OC_L

USB_EXTB_OC_L

PCH_GPIO42

USB_EXTA_OC_L

LPC_SERIRQ

TBT_PWR_EN_PCH

=PP3V3_S3RS4_PCH_GPIO

PCH_GPIO42

PCH_USB_RBIAS

USB_EXTB_8_N

USB_CAMERA_P

USB_BT_N

PCH_PCIE_RCOMP

=PP3V3_S0_PCH

USB_EXTA_OC_L USB_EXTC_OC_L

PCIE_TBT_D2R_P<2>

PCIE_AP_D2R_P

PCIE_AP_D2R_N

PCIE_ENET_D2R_N

PCIE_TBT_R2D_C_P<0>

PCIE_TBT_D2R_P<0>

PCIE_TBT_D2R_N<0>

PCIE_TBT_R2D_C_N<0>

PCIE_TBT_R2D_C_P<1>

PCIE_TBT_D2R_N<1> PCIE_TBT_D2R_P<1>

PCIE_TBT_R2D_C_N<1>

PCIE_TBT_D2R_N<2>

PCIE_TBT_D2R_N<3> PCIE_TBT_D2R_P<3>

PCIE_TBT_R2D_C_N<3>

LPC_AD_R<1>

LPC_AD_R<0>

SPI_CS0_R_L

SPI_MOSI_R

SDCONN_STATE_CHANGE

PCH_GPIO41

USB_EXTC_OC_L

USB3_EXTD_TX_P

USB3_EXTD_RX_F_N

USB3_EXTC_RX_F_P

USB3_EXTC_RX_F_N

USB3_EXTC_TX_P

USB3_EXTC_TX_N

USB3_EXTD_TX_N

USB3_EXTD_RX_F_P

USB3_EXTA_RX_F_N

USB3_EXTA_TX_N

USB3_EXTA_RX_F_P

USB3_EXTA_TX_P

USB3_EXTB_TX_P

USB3_EXTB_TX_N

USB3_EXTB_RX_F_P

USB3_EXTB_RX_F_N

USB_CAMERA_N

USB_EXTB_8_P

USB_EXTD_9_N

USB_EXTA_0_N USB_EXTA_0_P

USB_EXTC_1_N USB_EXTC_1_P

PCH_SML1ALERT_L

PCH_GPIO41

SMBUS_PCH_DATA

SML_PCH_0_CLK SML_PCH_0_DATA

SML_PCH_1_CLK SML_PCH_1_DATA

PCH_SML0ALERT_L

SMBUS_PCH_CLK

PCH_SMBALERT_L

TP_CLINK_DATA

TP_CLINK_CLK

PCH_TD_IREF

TP_CLINK_RESET_L

SPI_MISO

SPI_CLK_R

LPC_SERIRQ

TBT_PWR_EN_PCH

PCH_SML1ALERT_L

LPC_AD<0>

LPC_AD<2> LPC_AD<3>

LPC_AD<1>

LPC_FRAME_L

USB_EXTD_9_P

USB_BT_P

PCIE_AP_R2D_C_P

PCIE_ENET_R2D_C_P

PCIE_ENET_D2R_P

PCIE_AP_R2D_C_N

PCIE_ENET_R2D_C_N

TP_LPC_DREQ0_L

LPC_FRAME_R_L

LPC_AD_R<3>

LPC_AD_R<2>

PCIE_TBT_R2D_C_N<2> PCIE_TBT_R2D_C_P<2>

PCIE_TBT_R2D_C_P<3>

=PP3V3_SUS_PCH_GPIO

PCH_SMBALERT_L PCH_SML0ALERT_L

=PP1V5_S0_PCH_RCOMP

13 OF 86

13 OF 123

12.4.0

051-0164

1 2

V1

U2

T1

P3

P1

N2

M3

M1

L31

K31

G31

G29

F31

F24

D37

D33

D29

C36

C34

C32

BE40

BE38

BE36

BE34

BE32

BE30

BE28

BE26

BE24

BD42

BD41

BD37

BD29

BD27

BD25

BD23

BC40

BC38

BC32

BC30

BC26

BC24

BB37

BB29

B37

B33

B29

AY38

AY33

AY31

AW38

AW36

AW33

AW31

AW29

AW26

AV36

AV29

AV26AT40

AT39

AT33

AT31

AR33

AR31

AR29

AR26

AP29

AP26

AN39

AN38

A38

A36

A34

A30 C30

A32

H29

A28

G24

C38

BC36

C28

BB33

BD33

BC34

G26

F26

L33

M33

K24 K26

U8

H6

G20

C20

BE44

BE43

BC45

BA45

AL7

AL11

AJ7

AJ4

AJ2

AJ11

AJ10

AH3

AH1

A18

N11

AF7

K6

D21

AY43

AF11

AF10

N7

R10

U11

N8

A20

R7

B21

C18

1

2

1 2 1 2

1 2

1

2

1 2

1

2

13 18 42

13 18 43

13 18

13 18 37

13 44 46

13 20

70

13 18

80

77

19 70

13 18 42

13 18 43

79

13

13 18

13

72

79

11 12 14 70

13

12 70

OUT

BI

OUT

IN

BI

ININ

OUT

IN

GPIO24

GPIO57

GPIO27

TACH4/GPIO68

SCLOCK/GPIO22

THRMTRIP*

BMBUSY*/GPIO0

SLOAD/GPIO38

GPIO35/NMI*

GPIO34

SDATAOUT1/GPIO48

SDATAOUT0/GPIO39

SATA5GP/GPIO49

SATA3GP/GPIO37

GPIO28

GPIO15

SATA4GP/GPIO16

TACH0/GPIO17

VSS

GPIO8

PLTRST_PROC*

TP14

LAN_PHY_PWR_CTRL/GPIO12

TACH3/GPIO7

TACH2/GPIO6

TACH1/GPIO1

VSS

TACH7/GPIO71

TACH6/GPIO70

TACH5/GPIO69

PECI

PROCPWRGD

RCIN*

VSS

SATA2GP/GPIO36

CPU/MISC

(6 OF 11)

GPIO

OUT

BI

OUT

IN

OUT

BI

OUT

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(IPU-Boot?)

(IPD-PLTRST#)

(IPU-Boot/SATA4GP?)

(IPU-Boot/SATA5GP?)

(IPU-Boot?)

(IPU-DeepSx)

(IPU-RSMRST#)

(IPD-PLTRST#)

(IPD)

6

18 76

21

14 46

14 20

14 18 20

14 20

46 79

6

45 76

5%

201

1/20W MF

R1474

10K

5%

201

1/20W

MF

10K

R1475

14 44 81

14 20

14 44 81

U1100

OMIT_TABLE

MOBILE

LYNXPOINT

FCBGA

5%

201

1/20W

MF

2 1

20K

R1411

5%

201

1/20W

MF

10K

R1491

5%

201

1/20W

MF

R1492

10K

5%

201

1/20W

MF

10K

R1494

201

1/20W

MF

10K

5%

R1484

5%

201

1/20W

MF

100K

R1490

5%

201

1/20W

MF

10K

R1496

5%

201

1/20W

MF

10K

R1485

5%

201

1/20W

MF

12

10K

R1412

28

14 18

5%

201

1/20W

MF

2

10K

1

R1498

201

1/20W

MF

10K

5%

R1450

5%

201

1/20W

MF

R1455

10K

5%

201

1/20W

MF

R1470

NO STUFF

43

5%01/20W MF

0201

R1440

5%

201

1/20W

MF

R1456

390

6

44 45 76

14 36

20

18 67

14 26

6

18 76

5%

201

1/20W

MF

10K

R1486

5%

201

1/20W

MF

10K

R1499

5%

201

1/20W

MF

2

10K

R1413

1

5%

201

1/20W

MF

R1489

10K

3

18

5%

R1457

NO STUFF

402

MF-LF

1/16W

1K

14 18

201

1/20W

MF1%

33.2

PLACE_NEAR=U1100.C16:10MM

R1461

201

1/20W

MF

PLACE_NEAR=U1100.D13:10MM

R1462

33.2

1%

39

5%

201

1/20W

MF

10K

R1495

201

1/20W

MF

10K

5%

R1497

5%

201

1/20W

MF

R1422

1K

5%

201

1/20W MF

1K

R1423

PCH GPIO/MISC/NCTF

SYNC_MASTER=J16_KENNY

SYNC_DATE=03/07/2013

=PP3V3_S0_PCH_GPIO

=PP3V3_SUS_PCH_GPIO

FW_PWR_EN_PCH

PCH_A20GATE

JTAG_ISP_TDO

PCH_GPIO49

PCH_RCIN_L

WOL_EN MEM_VDD_SEL_1V5_L

FW_PME_L

SMC_RUNTIME_SCI_L

PCH_GPIO16 LPCPLUS_GPIO JTAG_TBT_TMS_PCH

PCH_GPIO36

TBT_GO2SX_BIDIR

PCH_A20GATE

PCH_PECI

PCH_PROCPWRGD

PCH_CAM_EXT_BOOT_R_L

PCH_CAM_RESET_R

PCH_RCIN_L

CPU_PECI

CPU_PWRGD

PM_THRMTRIP_L

CPU_RESET_L

=PP1V05_S0_PCH_V_PROC_IO

TBT_CIO_PLUG_EVENT_ISOL

SMC_RUNTIME_SCI_L

JTAG_ISP_TDI

=PP3V3_S0_PCH_GPIO

HDD_PWR_EN

WOL_EN

MEM_VDD_SEL_1V5_L

SMC_WAKE_SCI_L

JTAG_TBT_TMS_PCH

TBT_GO2SX_BIDIR

LPCPLUS_GPIO

PCH_GPIO16

ISOLATE_CPU_MEM_L

TBT_SW_RESET_L

GPU_GOOD

PCH_GPIO36

PCH_CAM_EXT_BOOT_L

SPIROM_USE_MLB

PCH_GPIO49

DPMUX_UC_IRQ

JTAG_ISP_TCK

JTAG_ISP_TDI

SMC_WAKE_SCI_L

DPMUX_UC_IRQ

FW_PME_L

FW_PWR_EN_PCH

PCH_CAM_RESET

JTAG_ISP_TCK

JTAG_ISP_TDO

PM_THRMTRIP_L_R

PCH_GPIO71

PCH_GPIO70

PCH_CAM_RESET

PCH_CAM_EXT_BOOT_L

051-0164

12.4.0

14 OF 123

14 OF 86

121

2

Y10

U12

R11

C16

BB4

AV1

AT8

AT7

AP1

AN6

AN4

AM3

AK3

AK1

AD11

AB11

A4

E45

E1

D1

BE3

BD44

BD2

BD1

BC1

BA1

B45

B44

B2

A44

A5

AN2

C14

A43

A2

Y1

BE2

BD45

AU4

A41

AN10

K13

G15

A14

F13

C45

BE5

BE41

H15

G13

D13

AY1

AV3

AT6

N10

B1

AT3

1 2

1 2 1 2

1 2

1

2

1 2

121

2

11 12 14 28 70

11 12 13 70

14

14 20

14 18

14

14 36

14

14 44 81

14 18

14 46

14 20

14 18

14 26

14

15 17 70

11 12 14 28 70

14

14 18 20

14 20

14 44 81

14

45

14

DCPSUS1

DCPSUSBYP

VCCADAC1_5

VSS

VCCVRM

VCCIO

VCCASW

VCC3_3

DCPSUS3

VCCSUS3_3

VCCADACBG3_3

VCC

CRT

USB3

CORE

PCIE/DMI

(7 OF 11)

FDI

HVCMOS

SATA

VCCMPHY

DCPSUS2

VCCUSBPLL

VCCSPI

DCPSST

VCCRTC

VSS

VCCVRM

VCCIO

VCCCLK3_3

VCCCLK

VCCASW

VCC3_3

VCC

V_PROC_IO

DCPRTC

VCCSUSHDA

VCCSUS3_3

VCCDSW3_3

VCCSUS3_3

VCCIO

VCCCLK

THERMAL

(8 OF 11)

GPIO/LPC

USB

HDARTCCPUSPI

CLK/MISC

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

10mA Max, 1mA Idle

VCCSUS3_3: 261mA Max, 6mA Idle

VGA DAC Disabled per SB DG v1.0 (Table 12-18).

VCC3_3: 133mA Max, 3mA Idle

VCCIO: 3629mA Max, 264mA Idle

VCCVRM: 183mA Max, 68mA Idle

15 mA Max, 1mA Idle

VCC3_3: 133mA Max, 3mA Idle

VCCASW: 670mA Max, 34mA Idle

22mA Max, 1mA Idle

4mA Max, 2mA Idle

VCCSUS3_3: 261mA Max, 6mA Idle

VCCASW: 670mA Max, 34mA Idle

VCC3_3: 133mA Max, 3mA Idle

??mA Max, ??mA Idle

NOTE: Pin name is VCC but really is 3.3V

VCCIO: 3629mA Max, 264mA Idle

VCCVRM: 183mA Max, 68mA Idle

Powered in DeepSx

VCC3_3: 133mA Max, 3mA Idle

VCCSUS3_3: 261mA Max, 6mA Idle

VCCCLK3_3: 55mA Max, 11mA Idle

VCC: 1.312 A Max, 130mA Idle

VCCIO: 3629mA Max, 264mA Idle

VCCCLK: 306mA Max, 89mA Idle

VCCVRM: 183mA Max, 68mA Idle

??mA Max, ??mA Idle

Current data from LPT EDS (doc #486708, Rev 1.0).

VCCASW: 670mA Max, 34mA Idle

6uA Max (3.0V, room temperature)

VCCIO: 3629mA Max, 264mA Idle

VCCSUS3_3: 261mA Max, 6mA Idle

CERM

10V

20%

C1532

BYPASS=U1100.A6:6.35mm

402

0.1UF

1UF

402

CERM

C1531

BYPASS=U1100.A6:6.35mm

6.3V

10%

CERM

10V

BYPASS=U1100.A6:6.35mm

402

20%

C1533

0.1UF

FCBGA

CKPLUS_WAIVE=PwrTerm2Gnd

MOBILE

LYNXPOINT

OMIT_TABLE

U1100

FCBGA

OMIT_TABLE

MOBILE

LYNXPOINT

U1100

1UF

PLACE_NEAR=R1550.1:2.54mm

CERM

402

C1550

6.3V

10%

1%

MF-LF

1/20W

5.11

PLACE_NEAR=U1100.U14:2.54mm

R1550

201

0201

X5R-CERM

10V

C1580

BYPASS=U1100.AA14:6.35mm

0.1UF

10%

0201

X5R-CERM

10V

C1590

BYPASS=U1100.P14:6.35mm

0.1UF

10%

PCH Power

SYNC_DATE=01/21/2013

SYNC_MASTER=J16_KENNY

=PP3V3_SUS_PCH_VCCSUS_GPIO

=PP3V3_S5_PCH_VCCDSW

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

PPVOUT_S0_PCH_DCPRTC

=PPVRTC_G3_PCH

MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

MIN_LINE_WIDTH=0.2 mm

PPVOUT_S0_PCH_DCPSST

=PP3V3_S0_PCH_VCC3_3_GPIO

=PP3V3R1V5_S0_PCH_VCCSUSHDA

=PP1V05_S0_PCH_VCCIO_GPIO

=PP3V3_SUS_PCH_VCC_SPI

=PP3V3_SUS_PCH_VCCSUS_RTC

=PP1V05_S0M_PCH_VCCASW

=PP1V5_S0_PCH_VCCVRM_THRM

=PP3V3_S0_PCH_VCC3_3_USB

PP1V05_S0_PCH_VCC_CLK_F

=PP1V5_S0_PCH_VCCVRM_CLK

=PP1V05_S0_PCH_VCCCLK_CLK135

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

PPVOUT_S5_PCH_DCPSUSBYP_R

MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

MIN_LINE_WIDTH=0.2 mm

PPVOUT_S5_PCH_DCPSUSBYP

=PP1V05_S0_PCH_VCCCLK_SSC100

=PP1V05_S0_PCH_VCCCLK_CLK100

=PP1V05_S0_PCH_VCCCLK_SSC

=PP3V3_S0_PCH_VCCCLK3_3

=PP3V3_S0_PCH_VCC3_3_THRM

=PP3V3_S0_PCH_VCC_FUSE

=PP1V05_S0_PCH_V_PROC_IO

=PP3V3_SUS_PCH_VCCSUS_USB

=PP1V05_S0M_PCH_VCCASW

=PP1V05_S0_PCH_VCC

=PP1V05_S0_PCH_VCCIO

=PP1V5_S0_PCH_VCCVRM_USB3

=PP3V3_SUS_PCH_VCCSUS_USB3

=PP3V3_S0_PCH_VCC3_3_HVCMOS

=PP1V05_S0_PCH_VCCIO_FDI

=PP1V5_S0_PCH_VCCVRM_SATA

=PP1V5_S0_PCH_VCCVRM_PCIE

=PP1V5_S0_PCH_VCCVRM_FDI

=PP1V05_S0_PCH_VCCIO_USB2

=PP1V05_S0_PCH_VCCUSBPLL

051-0164

12.4.0

15 OF 123

15 OF 86

212

1

2

1

Y12

U14

P45

P43

BE22

BB44

AN11

AK26

AM18

AK22

AK20

AK18

AT22

AR22

AP22

AN35

AN34

AM22

AM20

V22

V20

V18

U24

U22

U20

U18

AA18

Y22

Y20

Y18

V24

R32

R30

AD26

AD20

AA26

AG24

AG22

AG18

AE26

AE24

AE22

AE20

AE18

AD28

AJ28

AD24

AJ26

AJ30

AJ32

AD22

AG20

AK28

M31

AA24

Y26

Y35

U35

AD12

AA14

A6

M24

AW40

AF34

U26

R28

R26

Y30

V30

V28

U36

V32

U32

M29

M26

L29

L26

AG30

AE32

AE30

AD36

AD35

AA32

AA30

AG32

Y32

R18

L17

AK32

AK30

AG14

AE14

L24

AP45

P20

P18

AJ14

AJ12

P16

P14

A26

K8

A16

R22

AF12

R20R24

U30

AD34

2

1

1 2

2

1

2

1

17 70

11 12 70

17 70

70

17 70

15 17 70

17

17 70

17

17 70

14 17 70

17 70

15 17 70

17 70

17

70

17 70

17

17 70

VSS

(10 OF 11)

VSSVSS

(11 OF 11)

VSS

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

U1100

MOBILE

OMIT_TABLE

LYNXPOINT

FCBGA

U1100

LYNXPOINT

MOBILE

OMIT_TABLE

FCBGA

SYNC_MASTER=J16_KENNY

SYNC_DATE=01/21/2013

PCH Grounds

16 OF 86

16 OF 123

12.4.0

051-0164

Y8

Y40

Y36

Y34

Y28

Y24

Y16

Y14

W44

W2

V43

V26

V16

V14

U6

U42

U38

U34

U28

U16

U10

T43

R8

R44

R38

R34

R16

R14

R12

P32

P30

P28

P26

P22

N6

N39

N35

N12

M22

M17

L44

K39

B15

B11

AY7

AY29

AY26

AY20

AY15

AY10

F43

AW2

AV6

AV40

BB25

AV33

AV31

AV24

AV22

AV13

D42

AT38

AT29

AT26

AT20

AT17

AT15

AT10

AK16

AR2

AP43

AP31

AP24

AP13

AN42

AN40

AN36

AM16

AM32

AM30

AM28

AM26

AM24

AM14

AL8

AL38

AL34

P24

R2

AN8

L2

AT36

BC28

K33

K29

K20

K15

K10

H7

H40

H36

H31

H26

H24

H22

H17

H13

H10

G8

G44

G38

G2

F33

F29

F20

F15

AV7

BD7

BD39

BD35

BD31

BD11

BA40

B7

B39

B35

B23

B19

BB42

BC22

AL2

AL12

AK45

AK43

AK24

AK14

AJ8

AJ6

AJ38

AJ34

AJ24

AJ22

AJ20

AJ18

AJ16

AG44

AG28

AG26

AG2

AG16

AF8

AF38

AE28

AE16

AD8

AD6

AD40

AD32

AD30

AD18

AC2

AB8

AB38

AB34

AB12

AA4

AA22

AA20

AC44 AD14

AD16

D25

AT43

AY36

BD19

BD15

BC16 D4

B31

B27

AA16

AA28

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Not documented in EDS!

(PCH 1.05V CORE PWR)

670mA Max, 34mA Idle

PCH VCCASW BYPASS (PCH 1.05V ME CORE PWR)

(PCH 3.3V SUSPEND USB PWR)

(PCH 1.05V PCIe/DMI/SATA/USB3 PWR)

PCH VCCIO BYPASS

183mA Max, 68mA Idle

PCH VCC BYPASS (PCH 3.3V FUSE PWR)

PCH VCC BYPASS

(PCH 1.05V USB2 PWR)

PCH VCCCLK3_3 BYPASS

PCH VCCVRM BYPASS

PCH VCC3_3 BYPASS

(PCH 3.3V CLK PWR)

PCH VCCSUS3_3 BYPASS

PCH VCCSUSHDA BYPASS (PCH 3.3V/1.5V HDA PWR)

(PCH 3.3V SUSPEND RTC PWR)

(PCH 1.5V VCCVRM PWR)

PCH VCC3_3 BYPASS

(PCH 3.3V SPI PWR)

PCH VCCSPI BYPASS

(PCH 3.3V DSW PWR)

PCH VCCSUS3_3 BYPASS (PCH 3.3V SUSPEND PWR)

PCH VCCDSW3_3 BYPASS

(PCH 3.3V HVCMOS PWR)

PCH VCC3_3 BYPASS

??mA Max, ??mA Idle

PCH VCCIO BYPASS

(PCH 1.05V FDI PWR)

PCH V_PROC_IO BYPASS

PCH VCCIO BYPASS

PCH VCCCLK BYPASS (PCH 1.05V SSC PWR)

(PCH 1.05V DIFFCLK PWR)

PCH VCCCLK BYPASS

(PCH 1.05V SSC100 PWR)

PCH CLK VCC BYPASS (PCH 1.05V CLK PLL PWR)

Current data from LPT EDS (doc #486708, Rev 1.0).

(PCH 3.3V GPIO/LPC PWR)

PCH VCCCLK BYPASS

PCH VCC3_3 BYPASS (PCH 3.3V USB2 PWR)

(PCH 1.05V DIFFCLK135 PWR)

(PCH 1.05V CPU I/F PWR)

PCH VCCUSBPLL BYPASS (PCH 1.05V USB2 PLL PWR)

(PCH 3.3V THERMAL PWR)

20%

1UF

0201

X5R

10V

C1720

BYPASS=U1100.L26:6.35mm

20%

1.0UF

0201-1

X5R

6.3V

C1708

BYPASS=U1100.K8:6.35mm

0201

10V X5R-CERM

C1710

BYPASS=U1100.A26:6.35mm

0.1UF

10%

20%

0402-1

C1740

10UF

10V X5R-CERM

BYPASS=U1100.AF34:12.7mm

20%

0402-1

X5R-CERM

10V

10UF

C1755

BYPASS=U1100.AG18:12.7mm

20%

10UF

10V X5R-CERM 0402-1

C1760

BYPASS=U1100.AK18:12.7mm

20%

0402-1

X5R-CERM

10V

10UF

C1790

NO STUFF

BYPASS=U1100.AP45:12.7mm

20%

PLACE_NEAR=U1100.V20:2.54mm

0402

4V

C1750

20UF

X5R-CERM

0201

6.3V

C1774

BYPASS=U1100.U30:6.35mm

CERM-X5R

0.1UF

10%

0201

6.3V

C1786

BYPASS=U1100.AJ12:6.35mm

CERM-X5R

0.1UF

10%

20%

1.0UF

0201-1

X5R

6.3V

C1758

BYPASS=U1100.AE18:6.35mm

0201

6.3V

C1787

BYPASS=U1100.AJ12:6.35mm

CERM-X5R

0.1UF

10%

0201

6.3V

C1770

BYPASS=U1100.U35:6.35mm

CERM-X5R

0.1UF

10%

20%

1.0UF

0201-1

X5R

6.3V

PLACE_NEAR=U1100.V20:2.54mm

C1752

20%

1.0UF

0201-1

X5R

6.3V

PLACE_NEAR=U1100.V20:2.54mm

C1751

20%

1.0UF

0201-1

X5R

6.3V

C1757

BYPASS=U1100.AD20:6.35mm

20%

1.0UF

0201-1

X5R

6.3V

C1756

BYPASS=U1100.AA24:6.35mm

20%

1.0UF

0201-1

X5R

6.3V

C1777

BYPASS=U1100.AG30:6.35mm

20%

1.0UF

0201-1

X5R

6.3V

C1776

BYPASS=U1100.AE30:6.35mm

20%

1.0UF

0201-1

X5R

6.3V

C1791

BYPASS=U1100.AP45:6.35mm

0603

4.7UH-170MA-0.321OHM

CRITICAL

OMIT_TABLE

L1790

20%

1.0UF

0201-1

X5R

6.3V

C1778

BYPASS=U1100.AD35:6.35mm

1

5%

402

MF-LF

1/16W

R1790

20%

1.0UF

0201-1

X5R

6.3V

C1780

BYPASS=U1100.AD34:6.35mm

20%

1UF

0201

X5R

10V

C1721

BYPASS=U1100.L29:6.35mm

20%

1UF

0201

X5R

10V

C1722

BYPASS=U1100.M29:6.35mm

20%

1.0UF

0201-1

X5R

6.3V

C1782

BYPASS=U1100.AA30:6.35mm

20%

1UF

0201

X5R

C1723

10V

BYPASS=U1100.U32:6.35mm

0201

10V X5R-CERM

C1726

BYPASS=U1100.R30:6.35mm

0.1UF

10%

0201

X5R-CERM

10V

C1730

BYPASS=U1100.L24:6.35mm

0.1UF

10%

0201

X5R-CERM

10V

C1732

BYPASS=U1100.AK30:6.35mm

0.1UF

10%

0201

X5R-CERM

10V

C1700

BYPASS=U1100.A16:6.35mm

0.1UF

10%

20%

1.0UF

0201-1

X5R

6.3V

C1702

BYPASS=U1100.AD12:6.35mm

0201

10V

C1704

BYPASS=U1100.R20:6.35mm

X5R-CERM

0.1UF

10%

0201

10V X5R-CERM

C1706

BYPASS=U1100.R26:6.35mm

0.1UF

10%

20%

1.0UF

0201-1

X5R

6.3V

C1772

BYPASS=U1100.AN34:6.35mm

0201

10V X7R-CERM

C1728

BYPASS=U1100.AE14:6.35mm

0.01UF

10%

20%

1.0UF

0201-1

X5R

6.3V

C1734

BYPASS=U1100.P18:6.35mm

20%

1.0UF

0201-1

X5R

6.3V

C1785

BYPASS=U1100.AJ12:12.7mm

20%

1.0UF

0201-1

X5R

6.3V

C1761

BYPASS=U1100.AK18:6.35mm

20%

1.0UF

0201-1

X5R

6.3V

C1762

BYPASS=U1100.AK22:6.35mm

20%

1.0UF

0201-1

X5R

6.3V

C1763

BYPASS=U1100.AK20:6.35mm

20%

1.0UF

0201-1

X5R

6.3V

C1764

BYPASS=U1100.AM18:6.35mm

SYNC_MASTER=J16_KENNY

SYNC_DATE=01/21/2013

PCH DECOUPLING

L1790

RES,FF,0 OHM,(020OHM MAX),2A,0603

1

113S0022

=PP1V05_S0_PCH_VCCUSBPLL

=PP3V3_S0_PCH_VCC3_3_USB

=PP1V05_S0_PCH_V_PROC_IO

=PP1V05_S0_PCH_VCCIO_USB2

=PP1V05_S0_PCH_VCCCLK_CLK100

=PP1V05_S0_PCH_VCCIO

=PP3V3R1V5_S0_PCH_VCCSUSHDA

=PP3V3_SUS_PCH_VCCSUS_GPIO

=PP3V3_SUS_PCH_VCCSUS_RTC

=PP3V3_SUS_PCH_VCC_SPI

=PP3V3_S0_PCH_VCC3_3_GPIO

=PP3V3_S0_PCH_VCC_FUSE

=PP1V05_S0_PCH_VCCIO_FDI

=PP1V05_S0_PCH_VCCCLK_CLK135

=PP1V05_S0_PCH_VCCCLK_SSC

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

PP1V05_S0_PCH_VCC_CLK_R

=PP1V05_S0_PCH_VCC_CLK

=PP1V5_S0_PCH_VCCVRM_PCIE

=PP1V5_S0_PCH_VCCVRM_USB3

=PP3V3_S0_PCH_VCCCLK3_3

=PP3V3_S0_PCH_VCC3_3_THRM

=PP3V3_S5_PCH_VCCDSW

=PP3V3_SUS_PCH_VCCSUS_USB

=PP1V5_S0_PCH_VCCVRM_FDI

=PP1V5_S0_PCH_VCCVRM_BIAS

=PP3V3_S0_PCH_VCC3_3_HVCMOS

=PP1V05_S0_PCH_VCCCLK_SSC100

=PP1V5_S0_PCH_VCCVRM_SATA =PP1V5_S0_PCH_VCCVRM_CLK =PP1V5_S0_PCH_VCCVRM_THRM

=PP1V5_S0_PCH_VCCVRM

=PP1V05_S0_PCH_VCC

MIN_LINE_WIDTH=0.2 MM VOLTAGE=1.05V

PP1V05_S0_PCH_VCC_CLK_F

MIN_NECK_WIDTH=0.075 MM

=PP1V05_S0M_PCH_VCCASW

17 OF 123

051-0164

12.4.0

17 OF 86

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

21

2

1

1 2

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

15 70

14 15 70

15 70

70

15

15 70

15

11

15 70

15

70

15 70

15

15 70

IN

IN IN

OUT

IN IN

IN

OUT OUT

NC

IN

OUT

IN

BI IN

OUT

IN

OUT

IN

OUT OUT OUT

IN

OUT

IN

NC

IN IN

IN

TP

IN

TP

IN

BI IN

D

SYM_VER_3

S G G

D

S G

D

S

IN

G

D

SG

D

S

D

SYM_VER_3

S G

TP

IN

NC NC

IN

IN IN IN IN

IN

OUT

IN IN IN

IN OUT OUT OUT OUT OUT OUT

IN

NC NC

NC

BI

NC NC

IN

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

WF: SB DPDG says HOOK1 is BP_PWRGD_RST#

TDI and TMS are terminated in CPU.

NC per Intel DPDG.

from PCH to J1850 and path to non-XDP

’Output’ non-XDP signals require pulls.

OBSFN_B1

signal destination (to minimize stub).

SDA

OBSDATA_A1

PCH/XDP Signal Isolation Notes:

TDI

OBSDATA_B3

TCK1

Use with 921-0133 Adapter Flex to

NOTE: This is not the standard XDP pinout.

support chipset debug.

OBSDATA_C1

OBSDATA_C0

OBSDATA_C2 OBSDATA_C3

OBSFN_C0 OBSFN_C1

OBSFN_D0

OBSFN_A1

OBSDATA_A0 OBSDATA_A1

ITPCLK#/HOOK5

RESET#/HOOK6

ITPCLK/HOOK4

OBSDATA_D0 OBSDATA_D1

OBSDATA_D3

OBSDATA_D2

VCC_OBS_CD

TMS

TDO

TDI

TRSTn

VCC_OBS_AB

OBSDATA_B2 OBSDATA_B3

PWRGD/HOOK0

OBSDATA_B1

HOOK1

SCL

HOOK3

TCK0

OBSDATA_C2

OBSDATA_C1

OBSFN_C0

XDP_PRESENT#

DBR#/HOOK7

TRSTn

TDO

TMS

OBSDATA_B2

998-2516

SCL

TCK0

HOOK1

OBSDATA_B0

OBSFN_A0

OBSFN_C1

OBSDATA_C0

HOOK2

DBR#/HOOK7

signal path needs to split between route

OBSFN_D1

OBSDATA_A3

998-2516

PCH SIGNALS

OBSFN_B0

OBSDATA_A2

OBSFN_A0

CPU Micro2-XDP

’Output’ PCH/XDP signals require pulls.

(All 18 R’s)

R187x and R189x should be placed where

RESET#/HOOK6

TCK1

NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page

XDP_PRESENT#

Extra BPM Testpoints

To link CPU and PCH JTAG pull ICT_JTAG_EN to 5V (must be in S0)

XDP SIGNALS

support chipset debug.

Use with 921-0133 Adapter Flex to

NOTE: This is not the standard XDP pinout.

OBSDATA_D1

OBSFN_D0

OBSDATA_D0

OBSDATA_D2

OBSFN_D1

OBSDATA_C3

PCH Micro2-XDP

SDA

OBSFN_A1

OBSDATA_A0

OBSDATA_A3

OBSFN_B1

OBSFN_B0

OBSDATA_B1

OBSDATA_B0

VCC_OBS_AB

HOOK2 HOOK3

OBSDATA_A2

PWRGD/HOOK0

CPU-PCH JTAG Chain Support

VCC_OBS_CD

NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page

ITPCLK#/HOOK5

ITPCLK/HOOK4

OBSDATA_D3

6

78

6

14 76

6

78

6

78

8

6

72 78

6

72 78

11 18 78

6

72 78

11 18 78

6

72 78

18 47

6

18 19

C1880

20%

402

CERM

10V

0.1UF

XDP

C1881

20%

402

CERM

10V

0.1UF

XDP

12 18 44

12 45 69

6

18 78

6

18 19

6

78

6

18

6

78

6

18 78

5%

R1830

1/16W MF-LF

402

150

5%

201

1/20W

MF

XDP

1K

R1805

5%

201

1/20W

MF

12

R1820

PLACE_NEAR=J1800.51:5MM

51

XDP

5%

201

1/20W

MF

12

R1823

51

XDP

5%

201

1/20W

MF

12

R1824

51

XDP

5%01/20W

MF

0201

R1802

XDP

5%

201

1/20W

MF

R1800

XDP

1K

PLACE_NEAR=U0500.AB35:16.5mm

6

78

5%

201

1/20W

MF

R1884

PLACE_NEAR=J1850.40:2.54mm

XDP

1K

5%01/20W

MF

0201

R1885

XDP

PLACE_NEAR=U5000.J3:2.54mm

12 69

12 18 44

J1800

M-ST-SM

DF40RC-60DP-0.4V

CRITICAL XDP_CONN

DF40RC-60DP-0.4V

CRITICAL XDP_CONN

J1850

M-ST-SM

C1801

402

20% CERM

10V

0.1UF

XDP

6

78

C1800

0.1UF

20% 10V

402

CERM

XDP

6

78

6

78

6

78

6

78

5%

R1831

1K

1/16W

402

MF-LF

XDP

6

78

6

78

TP1802

TP-P6

TP1803

TP-P6

TP1805

TP-P6

TP1804

TP-P6

6

78

6

78

TP1807

TP-P6

TP1806

TP-P6

6

78

6

78

6

PLACE_NEAR=J1850.55:5.08mm

DFN1006H4-3

DMN32D2LFB4

Q1848

Q1846

SOT-563

PLACE_NEAR=J1850.58:5.08mm

DMN5L06VK-7

Q1846

DMN5L06VK-7

SOT-563

PLACE_NEAR=J1850.57:6mm

6

76

Q1840

PLACE_NEAR=J1800.57:5.08mm

DMN5L06VK-7

SOT-563

Q1840

DMN5L06VK-7

PLACE_NEAR=J1800.58:5.08mm

SOT-563

Q1842

DMN32D2LFB4

DFN1006H4-3

PLACE_NEAR=J1800.51:5.08mm

TP1840

TP-P6

TP1841

TP-P6

5%

201

1/20W

MF

R1845

1K

TP1845

TP-P6

5%

201

1/20W

MF

R1842

1M

5%

201

1/20W MF

R1841

1M

6

76

5%

201

1/20W MF

R1840

1M

6

78

13 42

13 43

13

13 37

11 29 30

11

14

14 20

14

11 35

11 32

14 67

3

14

13 43

13 42

5%

0

R1892

MF-LF

NOSTUFF

1/16W

402

C1804

20%

402

CERM

10V

0.1UF

XDP

6

78

C1806

XDP

0.1UF

20% 10V

CERM

402

5%

201

1/20W

MF

R1804

XDP

220

5%

201

1/20W MF

R1867

XDP

J1850.51:5mm

100

5%

201

1/20W MF

U1100.W40:20MM

100

R1869

XDP

5%

201

1/20W MF

R1868

U1100.W39:21MM

XDP

100

NONE

R1890

NONE

402

SHORT

NONE

OMIT

NONE

R1893

402

NONENONE

OMIT

SHORT

R1895

NONE

402

NONE NONE

OMIT

SHORT

R1894

402

NONE NONE NONE

SHORT

OMIT

R1897

402

NONE NONE NONE

OMIT

SHORT

R1896

402

NONENONE NONE

OMIT

SHORT

R1881

402

SHORT

NONE NONENONE

OMIT

R1880

402

NONENONE

OMIT

SHORT

NONE

R1883

NONENONENONE

SHORT

402

OMIT

R1873

402

NONE NONE

OMIT

SHORT

NONE

R1872

NONE

SHORT

402

NONE NONE

OMIT

R1874

402

SHORT

NONE NONE NONE

OMIT

R1875

402

SHORT

NONE NONENONE

OMIT

R1878

402

SHORT

NONE NONENONE

OMIT

R1879

402

SHORT

NONE NONE

OMIT

NONE

R1882

NONENONENONE

SHORT

402

OMIT

R1886

NONE

SHORT

402

NONENONE

OMIT

R1887

NONENONE

SHORT

402

NONE

OMIT

18 47

201

1/20W MF

U1100.W39:4mm

210

R1861

1%

XDP

201

1/20W MF

1%

210

J1850.51:2.54mm

R1860

XDP

18 47

5%

201

1/20W MF

XDP

R1866

51

201

1/20W MF

U1100.W40:3.5mm

R1862

1%

210

XDP

12 20 39 69

5%

201

1/20W

MF

XDP

R1870

1K

6

18 78

6

14 76

6

78

6

78

SYNC_MASTER=J16_KENNY

SYNC_DATE=03/18/2013

CPU & PCH XDP

=PP3V3_S5_XDP

XDP_FC1_GPU_GOOD

XDP_DC1_SATARDRVR_EN

XDP_DC3_JTAG_ISP_TCK

XDP_DD2_ENET_CLKREQ_L

PM_PCH_PWROK

XDP_PM_PCH_PWROK

XDP_PCH_TDO

XDP_DD1_PCH_GPIO49

XDP_DD3_AP_CLKREQ_L

TP_XDP_PCH_TRST_L

XDP_DBRESET_L

XDP_PCH_TCK

VOLTAGE=3.3V

MAX_NECK_LENGTH=3MM

PP3V3_S5_XDP_R

MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.2MM

XDP_PCH_TDO XDP_PCH_TDI

=SMBUS_XDP_SCL

XDP_PCH_PWRBTN_L

XDP_PCH_S5_PWRGD

XDP_DB3_SDCONN_STATE_CHANGE_L

XDP_DB1_USB_EXTD_OC_L

XDP_DA2_PCH_GPIO41

XDP_DB2_PCH_GPIO10

XDP_PCH_TMS

XDP_DB0_USB_EXTB_OC_L

XDP_PCH_TCK

XDP_DA3_PCH_GPIO42

XDP_DA0_USB_EXTA_OC_L

XDP_DD0_PCH_GPIO16

XDP_DC2_PCH_GPIO36

XDP_DD3_AP_CLKREQ_L

XDP_FC0_HDD_PWR_EN

XDP_BPM_L<4>

ICT_JTAG_EN

CPU_RESET_L

XDP_BPM_L<5>

USB_EXTC_OC_L

PCH_GPIO42

XDP_DD0_PCH_GPIO16

XDP_DBRESET_L

XDP_CPU_TMS

XDP_CPU_TDI

XDP_CPU_TRST_L

XDP_CPU_TDO

CPU_PWR_DEBUG

XDP_CPU_PWRGD

XDP_CPU_TCK

PM_PWRBTN_L

CPU_CFG<13>

CPU_CFG<15>

XDP_CPU_TRST_L

=PP1V05_S0_XDP

XDP_PCH_TDI

PCH_GPIO36

XDP_CPU_TCK

XDP_DA0_USB_EXTA_OC_L

XDP_CPU_PWRBTN_L

PCH_GPIO16

CPU_CFG<2>

=PP1V05_S0_XDP

XDP_CPU_PRDY_L

CPU_CFG<0>

CPU_CFG<5>

CPU_CFG<7>

GPU_GOOD

SDCONN_STATE_CHANGE

PCH_GPIO49

HDD_PWR_EN

AP_CLKREQ_L

DP_AUXIO_EN SATARDRVR_EN

XDP_FC1_GPU_GOOD

XDP_FC0_HDD_PWR_EN

XDP_DB2_PCH_GPIO10

XDP_CPU_TDO

XDP_CPU_TMS

XDP_PCH_TDI

XDP_PCH_TCKXDP_CPU_TCK

XDP_PCH_TMS

XDP_CPU_PCH_TCK

XDP_CPU_PCH_TMS

CPU_CFG<12>

PM_PWRBTN_L

=SMBUS_XDP_SCL

PM_RSMRST_PCH_L

XDP_BPM_L<0>

CPU_CFG<4>

XDP_CPU_PREQ_L

XDP_BPM_L<7>

XDP_BPM_L<6>

XDP_BPM_L<3>

XDP_BPM_L<2>

CPU_CFG<17>

CPU_CFG<8>

CPU_CFG<16>

CPU_CFG<9>

CPU_CFG<10> CPU_CFG<11>

CPU_CFG<18>

CPU_CFG<19>

=SMBUS_XDP_SDA

CPU_CFG<6>

XDP_BPM_L<1>

CPU_CFG<3>

CPU_CFG<1>

USB_EXTA_OC_L

XDP_DB3_SDCONN_STATE_CHANGE_L

XDP_DC2_PCH_GPIO36

XDP_DD1_PCH_GPIO49 XDP_DD2_ENET_CLKREQ_L

XDP_DC3_JTAG_ISP_TCK

XDP_DB1_USB_EXTD_OC_L

=PP3V3_S5_XDP

ENET_CLKREQ_L

JTAG_ISP_TCK

USB_EXTD_OC_L

PCH_GPIO41

CPU_PWRGD

=SMBUS_XDP_SDA

XDP_CPU_PRESENT_L

XDP_CPU_TDO_PCH_TDI

XDP_CPURST_L

CPU_CFG<14>

XDP_DA1_USB_EXTC_OC_L

XDP_DA3_PCH_GPIO42

USB_EXTB_OC_L

PCH_GPIO10

XDP_DA2_PCH_GPIO41

XDP_DB0_USB_EXTB_OC_L

XDP_DA1_USB_EXTC_OC_L

XDP_VR_READY

PPVCCIO_S0_CPU

XDP_CPU_TDO

PM_PCH_SYS_PWROK

XDP_DC0_DP_AUXCH_ISOL_L XDP_DC1_SATARDRVR_EN

XDP_DC0_DP_AUXCH_ISOL_L

XDP_PCH_TMS

18 OF 123

18 OF 86

051-0164

12.4.0

2

1

2

1

2

1 2

53

51

43

41

35

29

23

19

17

15

11

7

5

9

3

2

13

10 12

14

16

8

1

21

27

33

37 39

45

47

49

57

55

59

6

20

22 24

26

32

30

38

42

44

48

46

50 52

54

58

56

60

28

40

18

4

34

36

25

31

61

62

6364

53

51

43

41

35

29

23

19

17

15

11

7

5

9

3

2

13

10

12 14

16

8

1

21

27

33

37

39

45 47

49

57

55

59

6

20

22

24 26

32

30

38

42

44

48

46

50 52

54

58

56

60

28

40

18

4

34 36

25

31

61

62

6364

2

1

2

1

2

1

3

1

2 1

6

2

4

3

5

4

3

5

1

6

2

3

1

2

1

2

1

121

2

1

2

1 2

2

1

2

1

1 2

1

2

1

2

1

2

1 2 1 2

1 2

1 2 1 2 1 2 1 2 1 2

1 2 1 2

1

2

1

2

1

2

1

2

1 2

18 70

18

11 18 78

18

6

18 78

6

18

18 70

18

18 70

18

6

18 78

6

18 78

11 18 78

6

18 78

11 18 78

18

18 70

18

5 6 8

10 61

6

18 78

18

11 18 78

IN

OUT

GND

VDD

25MHZ_A

VDDIO_B

VDDIO_A

VDDIO_C

25MHZ_B 25MHZ_C

THRM

XIN

XOUT

PAD

NCNC

NC

IN

OUT

IN

OUT

S

G

D

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PCH RTC Crystal

Coin-Cell Holder

If high, ME is disabled. This allows for full re-flashing of SPI ROM.

PCH ME Disable Strap

SMC controls strap enable to allow in-field control of strap setting.

SB XTAL Power

RTC Power Sources

System 25MHz Clock Generator

PCH Reset Button

PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.

511S0054

NOTE: 30 PPM crystal required

TBT XTAL Power

GreenClk 25MHz Power

VDD must be powered if any VDDIO is.

Ethernet XTAL Power

ENET > S0 > TBT, so ENET is used here.

Place TP1901-TP1903 on bottom side

Clock series termination

6

18

0

MF-LF

5%

402

1/16W

XDP

R1996

SILK_PART=SYS RESET

OMIT

0

1/16W MF-LF 402

5%

R1997

4.7K

5% 1/16W MF-LF 402

R1995

12 44

26 79

TDFN

CRITICAL

SLG3NB146V

U1900

CERM

1UF

402

C1902

6.3V

10%

CERM

10V

20%

402

C1920

0.1UF

402

CERM

20%

10V

C1922

0.1UF

402

20%

10V

CERM

C1924

0.1UF

SOT-363

BAT54DW-X-G

D1900

NOSTUFF

5% 1/16W

402

1M

MF-LF

R1906

0

5%

MF-LF

1/16W

402

R1905

1.97X2.02MM-NSP

OMIT

SMT-PAD

TP1901

OMIT

1.4-SQ-NSP

SM-PAD

TP1903

SMT-PAD

OMIT

1.97X2.02MM-NSP

TP1900

1.4-SQ-NSP

OMIT

SM-PAD

TP1902

5%

50V

PLACE_NEAR=Y1910.1:2MM

12PF

0402

C0G-CERM

C1911

CRITICAL

SM-HF

32.768K-12.5PF

Y1910

402

MF-LF

0

1/16W

5%

R1910

5%

50V

0402

C0G-CERM

12PF

C1905

3.2X2.5MM-SM

CRITICAL

25.000MHZ-20PPM-12PF-85C

Y1905

0402

C0G-CERM

50V

5%

12PF

C1906

1K

402

MF-LF

5%

1/16W

R1902

2 1

BB10201-C1403-7H

SM

J1900

5%

MF-LF

402

10M

1/16W

R1911

11 79

44 79

11 79

46 79

35 79

R1955

MF-LF

402

33

5%

1/16W

PLACE_NEAR=U1100:10MM

402

1/16W

5%

33

MF-LF

R1956

PLACE_NEAR=U1100:10MM

PLACE_NEAR=U1100:13MM

MF-LF

402

5%

1/16W

33

R1959

PLACE_NEAR=U1900.4:10MM

R1958

33

5%

1/16W

402

MF-LF

11 79

402

MF-LF1/16W

5%

330

PLACE_NEAR=R1113.2:15MM

R1921

SOT23-3-HF

NTR1P02L

Q1920

44

11 79

C0G-CERM

0402

50V

5%

12PF

PLACE_NEAR=Y1910.4:2MM

C1910

Chipset Support

SYNC_MASTER=J16_KENNY

SYNC_DATE=01/21/2013

SYSCLK_CLK25M_ENET_R

PCH_CLK33M_PCIOUT

LPC_CLK33M_LPCPLUS_R

LPC_CLK33M_SMC_R

SYSCLK_CLK25M_ENET

=PP3V3_G3H_RTC_D

PCH_CLK32K_RTCX2_R

=PP3V3_ENET_SYSCLK

LPC_CLK33M_SMC

SYSCLK_CLK25M_TBT

=PPVDDIO_TBT_CLK

=PP1V5_S0_PCH_CLK

=PPVDDIO_ENET_CLK

PP3V3_G3_RTC

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=3.3V

SYSCLK_CLK25M_X2

PCH_CLK32K_RTCX2

PPVBATT_G3_RTC

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 MM

RTC_RESET_L

PCH_CLK32K_RTCX1

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 mm

PPVBATT_G3_RTC_R

VOLTAGE=3.3V

XDP_DBRESET_L

PM_SYSRST_L

SYSCLK_CLK25M_X1

=PP3V3_S5_PCH

SPI_DESCRIPTOR_OVERRIDE_L

=PP3V3_S0_PCH

SYSCLK_CLK25M_ENET_R

SYSCLK_CLK25M_SB

SYSCLK_CLK25M_X2_R

PCH_CLK33M_PCIIN

LPC_CLK33M_LPCPLUS

SPI_DESCRIPTOR_OVERRIDE_R

HDA_SDOUT_R

051-0164

12.4.0

19 OF 123

19 OF 86

1 2

1

2

1

2

9

2

5

367

4 8

11

1

10

2

1

2

1

2

1

2

1

3

6

2

4

1

5

1

2

1 2

1

1 2

41

1 2

42

1 3

1 2

1

2

1

2

1 2

2

1

3

1 2

19 79

70

79

70

11 70

70

79

11 45

79

20 70

13 70

19 79

79

OUT

IN

OUT

IN

OUT

IN

OUT

Y

B

A

IN

08

Y1

Y2

GND

B2

VCC

A1 B1 A2

OUT

IN

08

Y1

Y2

GND

B2

VCC

A1 B1 A2

OUT

IN

D

SYM_VER_3

S G S

D

G S

D

G

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Platform Reset Connections

Unbuffered

Buffered

R2074 for current limit if PCH glitches

TBT_PWR_EN goes high for JTAG Programming

NOTE: TCK from PCH is Push-Pull CMOS

NOTE: TDO from CR is Push-Pull CMOS

JTAG GPIO Isolation due to glitch in and out of sleep

NOTE: TMS/TDI from PCH is Open Drain

GPIO Glitch Prevention

14

12

R2074

5%

MF

1/20W

1K

201

12 44 46

46

44 81

21 22

28

32

37

R2081

5%

33

MF-LF

402

1/16W

R2055

33

1/16W

5%

MF-LF

402

12

R2094

5%

33

1/16W MF-LF

402

R2088

402

1/16W MF-LF

5%

33

MF-LF

1/16W

402

33

5%

R2091

33

5%

402

R2092

MF-LF

1/16W

100K

R2080

5% 1/16W

402

MF-LF

U2080

CRITICAL

SOT23-5-HF

MC74VHC1G08

20% 10V

402

0.1UF

CERM

C2080

56

0201

CERM-X5R

C2040

6.3V

0.1UF

10%

12

5%

R2095

33

402

MF-LF

1/16W

33

EXT_GPU:YES

5%

MF-LF

R2090

33

402

1/16W

72

1

MF5%

1/20W

2

10K

R2060

201

402

5%

1/16W

33

MF-LF

R2093

32

U2040

CRITICAL

SOT665

TC7SZ08FEAPE

13

12 18 20 39 69

12

74LVC2G08GT

8

4

U2050

SOT833

CRITICAL

C2050

20%

402

CERM

10V

0.1UF

20 26

35 37

20 26

14 18

20 26

8

4

U2000

SOT833

74LVC2G08GT

CRITICAL

C2013

X5R-CERM 0201

16V

0.1UF

10%

26

14

Q2062

CRITICAL

DFN1006H4-3

DMN32D2LFB4

CRITICAL

DMN5L06VK-7

SOT-563

Q2060

R2062

10K

MF

5% 1/20W

201

R2061

10K

MF

5% 1/20W

201

SOT-563

CRITICAL

DMN5L06VK-7

Q2060 R2063

1/20W

5% MF

10K

201

26

SYNC_MASTER=J16_KENNY

SYNC_DATE=01/21/2013

Project Chipset Support

=PP3V3_S5_PCH

PM_PCH_PWROK

AUD_IPHS_SWITCH_EN

AUD_IPHS_SWITCH_EN_PCH

LPC_PWRDWN_L

PLT_RST_BUF_L

BT_RESET_MASK_L

=PP3V3_S0_RSTBUF

PLT_RESET_L

MAKE_BASE=TRUE

TBT_PLT_RST_L

MAKE_BASE=TRUE

TBT_CIO_PLUG_EVENT

SSD_RESET_L

TBT_CIO_PLUG_EVENT

=PP3V3_S5_PCH

TBT_CIO_PLUG_EVENT_BUF

TBT_CIO_PLUG_EVENT_ISOL

=PP3V3_TBT_PCH_GPIO

=PP3V3_S5_PCH

TBT_PWR_EN

ENET_SD_RESET_L

JTAG_ISP_TDO

JTAG_ISP_TDI

JTAG_TBT_TMS_PCH

JTAG_TBT_TDO

JTAG_TBT_TDI

JTAG_TBT_TMS

ENET_LOW_PWR

PM_PCH_PWROK

ENET_LOW_PWR_PCH

TBT_PWR_EN_PCH

JTAG_ISP_TCK

JTAG_TBT_TCK

MAKE_BASE=TRUE

SMC_LRESET_L

DEBUG_RESET_L

PCA9557D_RESET_L

=TBT_RESET_L

AP_RESET_L

TP_GPU_RESET_L

051-0164

12.4.0

20 OF 123

20 OF 86

1 2

1

2

5

1

2

3

4

2

1

2

1

1 2

3

5

1

4

2

3

71

2

5

6

2

1

3

71

2

5

6

2

1

3

1

2

5

4

3

1

2

1

2

1

6

1

2

19 20 70

12 18 20 39 69

70

20 26

19 20 70

70

19 20 70

OUT

IN

OUT

D

SG

D

SG

D

SG

NC

IN

D

GS

D

SG

IN

NC

08

IN

NC

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

MEM S0 "PGOOD" FOR CPU

PM_MEM_PWRGD MUST ASSERT MIN 100 NS AFTER MEM_VDDQ RAMPS 80% THIS IS GUARANTEED BY THE 2 V/MS RAMP RATE OF THE FET

MEMVTT_EN = PLT_RESET_L * PM_SLP_S3_L

PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page

ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals.

WHEN LOW: CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.

must de-assert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L.

5 0 1 1 0 (*) 1 1

1 0 1 1 1 1 1

to

6 0 1 1 1 1 1

(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO.

transition. Rails will power-up as if from S3, but MEM_RESET_L will not properly assert. Software

60mW max power

S0 to S3

S0

NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0

75mA max load @ 0.75V

0 1 1 1 1 CPU_MEM_RESET_L 1

Step ISOLATE_CPU_MEM_L PLT_RESET_L PM_SLP_S3_L CPU_MEM_RESET_L MEM_RESET_L MEMVTT_EN

MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L

7 1 1 1 1 CPU_MEM_RESET_L 1

4 0 0 1 X 1 0

3 0 0 0 X 1 0

2 0 0 1 1 1 0

WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated.

The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well

Ensures CKE signals are held low in S3

MEMVTT Clamp

as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary.

21 68

402

MF-LF

100K

1/16W

5%

R2115

23 24 75

402

1K

5%

MF-LF

1/16W

R2116

21 68

402

1/16W

100K

5%

MF-LF

R2151

0402

20%

0.001UF

CERM

50V

NOSTUFF

C2151

5%

603

10

1/10W MF-LF

R2150

6

12

16V

10%

0.1UF

X7R-CERM 0402

C2116

SOT563

CRITICAL

SSM6N15AFE

Q2115

SSM6N15AFE

SOT563

CRITICAL

Q2150

SSM6N15AFE

SOT563

CRITICAL

Q2150

SC70

74LVC1G07

CRITICAL

U2120

0.01UF

0402

X7R-CERM

16V

20%

C2121

71

VESM

CRITICAL

SSM3K15AMFVAPE

Q2116

SOT563

CRITICAL

SSM6N15AFE

Q2115

14

10K

5% 1/16W MF-LF

402

R2118

3

44 69

20 22

74LVC1G08

SOT891

U2110

0

5%

MF-LF

1/16W

402

NOSTUFF

R2112

12 36 44 45 68 69

X7R-CERM

16V

20%

0.01UF

0402

C2110

6

CPU Memory S3 Support

SYNC_MASTER=J16_NICK SYNC_DATE=12/11/2012

=PM_PGOOD_MEM_S0

CPU_MEM_RESET_L

MAKE_BASE=TRUE

=MEM_RESET_L

ALL_SYS_PWRGD

ISOLATE_CPU_MEM_L

=PP3V3_S4_MEMRESET

=PPDDRVTT_S0_CLAMP

MEMVTT_EN

PM_MEM_PWRGD

MIN_NECK_WIDTH=0.25mm

VTTCLAMP_L

MIN_LINE_WIDTH=0.25mm

VTTCLAMP_EN

=PPVDDQ_S3_MEMRESET

MEM_RESET_L

ISOLATE_MEM_5V

=PP5V_S4_MEMRESET

MEMRESET_ISOL_LS5V_L

PCA9557D_RESET_L

MEMVTT_EN

PM_SLP_S3_L

=PP3V3_S4_MEMRESET

=PP3V3_S4_PM

051-0164

12.4.0

21 OF 123

21 OF 86

1

2

1

2

1

2

1

2

1

3

4

5

6

1

2

3

4

5

4

1 3

2

5

2

1

2

3

6

1

2

1

2

3

6

2

1

4

5

12

2

1

21 70

70

22

21 70

70

OUT

V-

V+

V-

V+

IN

G

D

SG

D

SG

D

S G

D

S

IN

G

D

SG

D

SG

D

SG

D

S

IN

RESET*

A0 A1 A2

SCL SDA

P0 P1 P2

P5 P6 P7

P3 P4

THRM

VCC

GND

PAD

NC

IN

BI

VDD

VOUTD

VOUTC

VOUTB

VOUTA

SCL

SDA

A0

A1

GND

IN

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

NOTE: DDR3 assumes TPS51916 supply with 10.0k/49.9k divider

2.575mV / step @ output

+36uA - -36uA (- = sourced)

1.199V - 1.801V (+/- 301mV)

1.200V - 1.800V (+/- 300mV)

NOTE: CPU DAC output step sizes:

3.923mV / step @ output

+28uA - -29uA (- = sourced)

0.950V - 1.750V (+/- 400mV)

0.932V - 1.760V (+/- 414mV)

1.343V (DAC: 0x68 = 1.341V)1.500V (DAC: 0x74 = 1.495V) DDR3L assumes TPS51916 supply with 19.6k/57.6k divider

- DDRVREF_DAC - Stuffs DAC margining circuit.

- =PPDDR_S3_MEMVREF

0.000V - 3.004V (0x00 - 0xE9)

0.299V - 1.206V (+/- 453mV)

0.275V - 1.075V (+/- 400mV)

0.675V (DAC: 0x34 = 0.670mV)

0.000V - 2.707V (0x00 - 0xD2)

5

D

MEM VREG

MEM B VREF CAMEM A VREF CAMEM B VREF DQMEM A VREF DQ

DDR3 (1.5V)

0.750V (DAC: 0x3A = 0.747mV)

0.300V - 1.200V (+/- 450mV)

0.000V - 1.354V (0x00 - 0x69)

0.269V - 1.083V (+/- 406mV)

+811uA - -816uA (- = sourced)

7.67mV / step @ output 7.68mV / step @ output

0.000V - 1.508V (0x00 - 0x75)

+901uA - -911uA (- = sourced)

Margined range:

DAC range:

DDR3L (1.35V)

4

C

DDR3L (1.35V)

3

C

2

B

DDR3 (1.5V)

A

1

PCA9557D Pin:

DAC Channel:

Nominal value

Margined target:

Addr=0x30(WR)/0x31(RD)

RST* on ’platform reset’ so that system

NOTE: Margining will be disabled across all

and disables margining after platform reset.

DAC-Based Margining

ISOLATE_CPU_MEM_L is low

DAC margining VREFCA ensure

margining support. When

VREFCA. Split into two

soft-resets and sleep/wake cycles.

watchdog will disable margining.

Q2265 pin 6:

VRef Dividers

Power aliases required by this page:

Signal aliases required by this page:

- =I2C_VREFDACS_SDA

- =I2C_PCA9557D_SDA

- =I2C_PCA9557D_SCL

- =I2C_VREFDACS_SCL

BOM options provided by this page:

(All 4 R’s)

DAC sets voltage level, PCA9557 & FETs enable outputs

FETs for CPU isolation during S3

NOTE: MEMVREG and FRAMEBUF share

- =PP3V3_S3_VREFMRGN

to remove short due to CPU.

signals for independent DAC

NOTE: CPU has single output for

DDR3 (1.5V) 7.70mV per step DDR3L (1.35V) 6.99mV per step

(OD)

Addr=0x98(WR)/0x99(RD)

both at the same time!

Pins B1 & B4:

Page Notes

DAC step size:

VRef current:

CPU-Based Margining

R22x6 pin 2:

a DAC output, cannot enable

Q2225 pin 6:

of margining option.

Always used, regardless

EN RC’s to avoid drain glitches

63

0201

CERM-X5R

DDRVREF_DAC

C2202

6.3V

0.1UF

10%

1%

33.2K

1/16W MF-LF

402

DDRVREF_DAC

R2214

DDRVREF_DAC

MF

1/20W

100K

5%

R2213

201

DDRVREF_DAC

MF

1/20W

100K

5%

R2215

201

DDRVREF_DAC

CRITICAL

UCSP

MAX4253

CKPLUS_WAIVE=unconnected_pinsCKPLUS_WAIVE=unconnected_pins

U2204

B1

B4

MAX4253

CRITICAL DDRVREF_DAC

UCSP

U2204

B1

B4

OMIT

NONE NONE

NONE

402

SHORT

R2218

7

21

DMN5L06VK-7

CRITICAL

SOT-563

Q2260

100K

DDRVREF_DAC

MF

1/20W

5%

R2202

201

DMN5L06VK-7

CRITICAL

SOT-563

Q2220

DMN5L06VK-7

CRITICAL

SOT-563

Q2260

CRITICAL

DMN5L06VK-7

SOT-563

Q2220

7

CRITICAL DDRVREF_DAC

DMN5L06VK-7

SOT-563

Q2225

PLACE_NEAR=Q2220.6:5mm

DDRVREF_DAC

R2201

100K

1/20W

MF

5%

201

DDRVREF_DAC

100K

402

5%

MF-LF

1/16W

R2225

402

CERM

10V

20%

DDRVREF_DAC

C2225

0.1UF

CRITICAL

DMN5L06VK-7

DDRVREF_DAC

SOT-563

Q2265

PLACE_NEAR=Q2260.6:5mm

C2245

CERM

DDRVREF_DAC

20% 10V

402

0.1UF

100K

402

5%

MF-LF

1/16W

DDRVREF_DAC

R2245

100K

DDRVREF_DAC

402

5%

MF-LF

1/16W

R2265

DMN5L06VK-7

CRITICAL DDRVREF_DAC

SOT-563

Q2225

DDRVREF_DAC

402

CERM

10V

20%

C2265

0.1UF

DMN5L06VK-7

CRITICAL DDRVREF_DAC

SOT-563

Q2265

DDRVREF_DAC

20% 10V

CERM

402

C2285

0.1UF

DDRVREF_DAC

MF

1/20W

5%

100K

R2207

201

100K

5%

DDRVREF_DAC

402

MF-LF

1/16W

R2285

DDRVREF_DAC

MF

1/20W

5%

100K

R2208

201

R2226

1%

332

DDRVREF_DAC

1/16W

402

MF-LF

PLACE_NEAR=Q2225.1:5.5mm

1%

332

DDRVREF_DAC

1/16W

402

MF-LF

R2246

PLACE_NEAR=Q2265.4:5.5mm

402

MF-LF1/16W

1%

332

DDRVREF_DAC

R2266

PLACE_NEAR=Q2225.1:5.5mm

1%

332

DDRVREF_DAC

1/16W

402

MF-LF

R2286

PLACE_NEAR=Q2265.4:5.5mm

1M

DDRVREF_DAC

402

MF-LF

1/16W

5%

R2217

0201

X5R-CERM

10%

6.3V

C2280

0.022UF

PLACE_NEAR=Q2260.3:2mm

0201

X5R-CERM

10%

6.3V

C2260

PLACE_NEAR=Q2220.3:2mm

0.022UF

0201

X5R-CERM

10%

6.3V

C2240

0.022UF

PLACE_NEAR=Q2260.6:4MM

R2283

MF

1/20W

2

5%

PLACE_NEAR=C2280.1:2mm

201

24.9

1%

1/20W

MF

R2280

201

1K

402

MF-LF

1/16W

1%

PLACE_NEAR=R2281.2:1mm

R2282

2

5%

MF

1/20W

PLACE_NEAR=C2260.1:2mm

R2263

201

24.9

1%

1/20W

MF

R2260

201

PLACE_NEAR=R2283.2:1.5MM

MF-LF

1/16W

402

1%

1K

R2281

PLACE_NEAR=R2261.2:1mm

1K

MF-LF

402

1/16W

1%

R2262

24.9

1%

1/20W

MF

R2240

201

1%

1K

MF-LF

1/16W

402

PLACE_NEAR=R2263.2:1mm

R2261

PLACE_NEAR=R2241.2:1mm

MF-LF

1/16W

402

1%

1K

R2242

0201

X5R-CERM

10%

6.3V

C2220

PLACE_NEAR=Q2220.6:2mm

0.022UF

MF

1/20W

2

5%

PLACE_NEAR=C2240.1:2mm

R2243

201

MF

1/20W

5%

2

PLACE_NEAR=C2220.1:2mm

R2223

201

24.9

1%

1/20W

MF

R2220

201

1%

1K

MF-LF

1/16W

402

PLACE_NEAR=R2243.2:1mm

R2241

PLACE_NEAR=R2221.2:1mm

MF-LF

402

1/16W

1%

1K

R2222

PLACE_NEAR=R2223.2:1.5MM

MF-LF

1/16W

402

1%

1K

R2221

20 21

CRITICAL DDRVREF_DAC

PCA9557

QFN

U2201

47

DDRVREF_DAC

MSOP

DAC5574

CRITICAL

U2200

47

0201

CERM-X5R

DDRVREF_DAC

C2201

6.3V

0.1UF

10%

DDRVREF_DAC

2.2UF

402-LF

CERM

20%

C2200

6.3V

0201

CERM-X5R

DDRVREF_DAC

C2205

6.3V

0.1UF

10%

SYNC_MASTER=J16_NICK

DDR3 VREF MARGINING

SYNC_DATE=01/10/2013

VREFMRGN_DQ_A_EN

VREFMRGN_DQ_A_EN_RC

=PPDDR_S3_MEMVREF

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PPVREF_S3_MEM_VREFCA_A

CPU_MEM_VREFDQ_A_ISOL

CPU_MEM_VREFDQ_B_ISOL

VREFMRGN_DQ_B_EN_RC

=PP3V3_S3_VREFMRGN

VREFMRGN_CA_A_EN

VREFMRGN_FRAMEBUF_EN

=I2C_VREFDACS_SCL

=I2C_VREFDACS_SDA

=I2C_PCA9557D_SCL =I2C_PCA9557D_SDA

CPU_DIMMB_VREFDQ

CPU_DIMM_VREFCA

MEMRESET_ISOL_LS5V_L

CPU_DIMMA_VREFDQ

VREFMRGN_DQ_A

=PP3V3_S3_VREFMRGN

DDRREG_FB

VREFMRGN_FRAMEBUF_BUF

VREFMRGN_CA_A_EN_RC

VREFMRGN_DQ_B_EN

VREFMRGN_CA_B_EN

MEM_VREFCA_B_RC

CPU_MEM_VREFCA_B_ISOL

MEM_VREFCA_A_RC

CPU_MEM_VREFCA_A_ISOL

MEM_VREFDQ_B_RC

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PPVREF_S3_MEM_VREFCA_B

MEM_VREFDQ_A_RC

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PPVREF_S3_MEM_VREFDQ_B

PPVREF_S3_MEM_VREFDQ_A

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

VREFMRGN_DQ_B_RDIV

MIN_LINE_WIDTH=0.3 mm

PP3V3_S3_VREFMRGN

MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

PCA9557D_RESET_L

VREFMRGN_DQ_B

VREFMRGN_CA_AB

VREFMRGN_MEMVREG_FBVREF

VREFMRGN_MEMVREG_EN

VREFMRGN_DQ_A_RDIV

VREFMRGN_MEMVREG_BUF

VREFMRGN_CA_A_RDIV

VREFMRGN_CA_B_RDIV

VREFMRGN_CA_B_EN_RC

051-0164

22 OF 123

22 OF 86

12.4.0

2

1

1 2

1

2

1

2

A4

A1

A3

A2

C4

C1

C3

C2

1 2

1

6

2

1

2

4

3

5

4

3

5

1

6

2

1

6

2

1

2

1 2

2

1

6

2

1

1 2

4

3

5

2

1

4

3

5

2

1

2

1 2

1

2

1 2

1

2

1

2

1

2

1

1 2

1

2

1 2

1

2

1

2

1 2

1

2

1

2

1

1 2

1

2

1

2

1

2

15

3

4

5

1

2

6

7

9

12

13

14

16

10

11

17

8

3

5

4

2

16

7

9

10

2

1

2

1

2

1

70

23

22 70

24

23

BI BIBI

BI

IN

BI BI

BI

IN

BI

BI BI

BI

BI BI

BI

IN IN

IN

IN IN

IN

BI BI

IN

BI

BI BI

BI

BI BI

BI

OUT

BI IN

IN

IN IN

BI BI

NC

A13

VDD_14

VDD_12

BA0

A10_AP

A3

DQ54 DQ55

VSS_44

VSS_0

VSS_2

VSS_5

DQS0

DQ5

DQ4

DQ6 DQ7

VREFDQ VSS_1

VSS_3

DQ0 DQ1

DM0 VSS_4

VSS_7

DQ12

DQ20

VSS_13

DQ15

DQ14

VSS_11

VSS_9

DQ13

DM1

DQ21

VSS_15

DQ22

VSS_16

VSS_18

DQ23

DQ28

VSS_20

DQ29

DM2

VSS_23

DQS3

DQ30

VSS_25

VDD_1

CKE1

A15 A14

VDD_3

VDD_9

VDD_5

VDD_7

A7

A11

A4

A6

A2 A0

CK1

NC_1

ODT1

VDD_15

ODT0

VDD_13

VDD_11

BA1

DQ39

DQ38

VSS_30

VSS_29

DQ37

DQ36

VSS_27

VREFCA

VDD_17

DM4

VSS_32

DQ47

DQ44

DQ46

VSS_37

DQS5

VSS_39

VSS_34

DQ45

DQ52

VSS_46

DQ61

DQ60

VSS_42

VSS_41

DQ53

DM6

DQS7

VSS_51

DQ63

DQ62

VSS_49

SDA SCL

DQ2 DQ3 VSS_6 DQ8 DQ9 VSS_8

DQS1 VSS_10

DQ16

VSS_12

DQ11

DQ10

DQ17

DQ18

DQS2 VSS_17

VSS_14

VSS_21

DQ24 DQ25

DQ19 VSS_19

VSS_24

DQ27

DQ26

DM3 VSS_22

CKE0

A5

VDD_4

CK0

VDD_8

A1

VDD_6

VDD_10

DQ33

VSS_26

VDD_16 TEST

DQ32

DQ34

VSS_31

DQS4

VSS_28

DQ35

DQ41

VSS_33

VSS_35

DQ40

DM5

VSS_38

DQ43

DQ42

VSS_36

DQ48

VSS_43

DQS6

VSS_40

DQ49

DQ51

DQ50

VSS_45 DQ56 DQ57 VSS_47 DM7

DQ58

VSS_48

DQ59

SA0

SA1

VDDSPD

VSS_50

A8

A9

A12/BC*

VDD_2

BA2

NC_0

VDD_0

DQ31

DQS0*

DQS1*

RESET*

DQS2*

DQS3*

CK0* CK1*

RAS*

WE* S0* CAS*

S1*

DQS4*

DQS5*

DQS6*

DQS7*

EVENT*

VTT_0 VTT_1

MTG_PINMTG_PIN

KEY

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)

25

C2331

10V

20% 402

CERM

0.1UF

C2330

20% 402-LF

CERM

2.2UF

6.3V

25

7

75

25

21 24 75

25

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

25

7

75

25

C2336

CERM 402

10V

20%

0.1UF

C2335

20%

402-LF

CERM

2.2UF

6.3V

25

24 44 45

47

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

25

R2341

10K

MF-LF 402

5% 1/16W

R2340

10K

MF-LF 402

5% 1/16W

C2340

2.2UF

CERM 402-LF

20%

6.3V

C2300

10UF

603

20%

6.3V X5R

C2301

603

10UF

20%

6.3V X5R

C2310

CERM 402

20% 10V

0.1UF

C2311

CERM 402

20% 10V

0.1UF

C2312

CERM 402

20% 10V

0.1UF

C2313

CERM 402

20% 10V

0.1UF

C2314

CERM 402

20% 10V

0.1UF

C2315

CERM 402

20% 10V

0.1UF

C2316

CERM 402

20% 10V

0.1UF

C2317

20% 10V

402

CERM

0.1UF

C2318

20% CERM

402

10V

0.1UF

C2319

CERM

10V 402

20%

0.1UF

C2320

CERM 402

10V

20%

0.1UF

C2321

402

CERM

20% 10V

0.1UF

C2322

CERM 402

20% 10V

0.1UF

C2323

10V

20% 402

CERM

0.1UF

C2353

10V X6S-CERM

1UF

0402

10%

C2352

10V X6S-CERM

1UF

0402

10%

C2351

10V X6S-CERM

1UF

0402

10%

C2350

10V X6S-CERM

1UF

0402

10%

C2302

402

CERM

10V

20%

0.1UF

C2324

CERM 402

20% 10V

0.1UF

2-2013310-1

F-RT-SM

CRITICAL

J2300

SYNC_MASTER=J16_NICK SYNC_DATE=01/10/2013

DDR3 SO-DIMM Connector A

=PPVDDQ_S3_MEM_A

MEM_A_RAS_L

VOLTAGE=0.75V

PPVREF_S3_MEM_VREFCA_A

=MEM_A_DQ<52> =MEM_A_DQ<53>

MEM_A_SA<1> MEM_A_SA<0> =PPSPD_S0_MEM_A

=PPDDRVTT_S0_MEM_A

MEM_EVENT_L

=MEM_A_DQS_N<7>

=MEM_A_DQS_N<6>

=MEM_A_DQS_N<5>

=MEM_A_DQS_N<4>

MEM_A_CS_L<1>

MEM_A_CAS_L

MEM_A_CS_L<0>

MEM_A_WE_L

MEM_A_CLK_N<1>MEM_A_CLK_N<0>

=MEM_A_DQS_N<3>

=MEM_A_DQS_N<2>

MEM_RESET_L

=MEM_A_DQS_N<1>

=MEM_A_DQS_N<0>

=MEM_A_DQ<31>

MEM_A_BA<2>

MEM_A_A<12> MEM_A_A<9>

MEM_A_A<8>

=PPSPD_S0_MEM_A MEM_A_SA<1>

MEM_A_SA<0>

=MEM_A_DQ<59>

=MEM_A_DQ<58>

=MEM_A_DQ<57>

=MEM_A_DQ<56>

=MEM_A_DQ<50> =MEM_A_DQ<51>

=MEM_A_DQ<49>

=MEM_A_DQS_P<6>

=MEM_A_DQ<48>

=MEM_A_DQ<42> =MEM_A_DQ<43>

=MEM_A_DQ<40> =MEM_A_DQ<41>

=MEM_A_DQ<35>

=MEM_A_DQS_P<4>

=MEM_A_DQ<34>

=MEM_A_DQ<32> =MEM_A_DQ<33>

MEM_A_A<1>

MEM_A_CLK_P<0>

MEM_A_A<5>

MEM_A_CKE<0>

=MEM_A_DQ<26> =MEM_A_DQ<27>

=MEM_A_DQ<19>

=MEM_A_DQ<25>

=MEM_A_DQ<24>

=MEM_A_DQS_P<2>

=MEM_A_DQ<18>

=MEM_A_DQ<17>

=MEM_A_DQ<10> =MEM_A_DQ<11>

=MEM_A_DQ<16>

=MEM_A_DQS_P<1>

=MEM_A_DQ<9>

=MEM_A_DQ<8>

=MEM_A_DQ<3>

=MEM_A_DQ<2>

=I2C_SODIMMA_SCL

=I2C_SODIMMA_SDA

=MEM_A_DQ<62> =MEM_A_DQ<63>

=MEM_A_DQS_P<7>

=MEM_A_DQ<60> =MEM_A_DQ<61>

=MEM_A_DQ<45>

=MEM_A_DQS_P<5>

=MEM_A_DQ<46>

=MEM_A_DQ<44>

=MEM_A_DQ<47>

=MEM_A_DQ<36> =MEM_A_DQ<37>

=MEM_A_DQ<38> =MEM_A_DQ<39>

MEM_A_BA<1>

MEM_A_ODT<0>

MEM_A_ODT<1>

MEM_A_CLK_P<1>

MEM_A_A<0>

MEM_A_A<2>

MEM_A_A<6> MEM_A_A<4>

MEM_A_A<11> MEM_A_A<7>

MEM_A_A<14>

MEM_A_A<15>

MEM_A_CKE<1>

=PPVDDQ_S3_MEM_A

=MEM_A_DQ<30>

=MEM_A_DQS_P<3>

=MEM_A_DQ<29>

=MEM_A_DQ<28>

=MEM_A_DQ<23>

=MEM_A_DQ<22>

=MEM_A_DQ<21>

=MEM_A_DQ<13>

=MEM_A_DQ<14> =MEM_A_DQ<15>

=MEM_A_DQ<20>

=MEM_A_DQ<12>

=MEM_A_DQ<1>

=MEM_A_DQ<0>

=MEM_A_DQ<7>

=MEM_A_DQ<6>

=MEM_A_DQ<4> =MEM_A_DQ<5>

=MEM_A_DQS_P<0>

=MEM_A_DQ<55>

=MEM_A_DQ<54>

MEM_A_A<3>

MEM_A_A<10> MEM_A_BA<0>

MEM_A_A<13>

PPVREF_S3_MEM_VREFDQ_A

VOLTAGE=0.75V

051-0164

12.4.0

23 OF 123

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1

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2

1

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1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

119

117

111

109

107

95

174 176 178

2

8

14

12

6

4

16 18

1 3

9

5 7

11 13

20 22

40

38

36

34

32

26

24

28

42 44

50

48

54

52

56

60

58

46

66

64

68

72

76

74

78 80 82

100

88

94

86

84

92

90

96 98

102

122

120

118

116

112

106 108

142

140

138

134

132

130

128

126

124

136

144

160

146

158

156

154

162

150

148

164

184

182

180

172

168

166

170

188

196

194

192

190

200 202

15 17 19 21 23 25

29 31

39

37

35

33

41

51

47 49

43

61

57 59

53 55

71

69

67

63 65

73

91

87

101

99

97

93

105

131

127

123 125

129

141

139

137

133

143

149

145

151

147

153

161

159

157

155

163

173

171

167

165

177

175

179 181 183 185 187

191

189

193

197

201

199

195

89

85

83

81

79

77

75

70

10

27

30

45

62

103 104

110

113 114 115

121

135

152

169

186

198

203 204

206205

23 70

22

23

23 70

23

23 70

22

IN

IN IN

IN

NC

BI

BI BI

BI

IN

BI

BI BI

BI

IN

BI

BI BI

BI

IN

IN IN

IN

IN IN

IN

BI

NC

A13

VDD_14

VDD_12

BA0

A10_AP

A3

DQ54 DQ55

VSS_44

VSS_0

VSS_2

VSS_5

DQS0

DQ5

DQ4

DQ6 DQ7

VREFDQ VSS_1

VSS_3

DQ0 DQ1

DM0 VSS_4

VSS_7

DQ12

DQ20

VSS_13

DQ15

DQ14

VSS_11

VSS_9

DQ13

DM1

DQ21

VSS_15

DQ22

VSS_16

VSS_18

DQ23

DQ28

VSS_20

DQ29

DM2

VSS_23

DQS3

DQ30

VSS_25

VDD_1

CKE1

A15 A14

VDD_3

VDD_9

VDD_5

VDD_7

A7

A11

A4

A6

A2 A0

CK1

NC_1

ODT1

VDD_15

ODT0

VDD_13

VDD_11

BA1

DQ39

DQ38

VSS_30

VSS_29

DQ37

DQ36

VSS_27

VREFCA

VDD_17

DM4

VSS_32

DQ47

DQ44

DQ46

VSS_37

DQS5

VSS_39

VSS_34

DQ45

DQ52

VSS_46

DQ61

DQ60

VSS_42

VSS_41

DQ53

DM6

DQS7

VSS_51

DQ63

DQ62

VSS_49

SDA SCL

DQ2 DQ3 VSS_6 DQ8 DQ9 VSS_8

DQS1 VSS_10

DQ16

VSS_12

DQ11

DQ10

DQ17

DQ18

DQS2 VSS_17

VSS_14

VSS_21

DQ24 DQ25

DQ19 VSS_19

VSS_24

DQ27

DQ26

DM3 VSS_22

CKE0

A5

VDD_4

CK0

VDD_8

A1

VDD_6

VDD_10

DQ33

VSS_26

VDD_16 TEST

DQ32

DQ34

VSS_31

DQS4

VSS_28

DQ35

DQ41

VSS_33

VSS_35

DQ40

DM5

VSS_38

DQ43

DQ42

VSS_36

DQ48

VSS_43

DQS6

VSS_40

DQ49

DQ51

DQ50

VSS_45 DQ56 DQ57 VSS_47 DM7

DQ58

VSS_48

DQ59

SA0

SA1

VDDSPD

VSS_50

A8

A9

A12/BC*

VDD_2

BA2

NC_0

VDD_0

DQ31

DQS0*

DQS1*

RESET*

DQS2*

DQS3*

CK0* CK1*

RAS*

WE* S0* CAS*

S1*

DQS4*

DQS5*

DQS6*

DQS7*

EVENT*

VTT_0 VTT_1

MTG_PINMTG_PIN

KEY

NC

BI

BI BI

BI

BI BI

BI

OUT

IN IN

BI BI

BI

IN

BI

BI BI

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)

C2553

10V

1UF

X6S-CERM 0402

10%

47

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

25

C2531

CERM 402

20% 10V

0.1UF

7

75

25

C2530

20% 402-LF

2.2UF

CERM

6.3V

25

7

75

25

7

75

7

75

7

75

7

75

7

75

C2517

CERM 402

20% 10V

0.1UF

7

75

7

75

7

75

7

75

7

75

7

75

C2523

10V

20% 402

CERM

0.1UF

C2516

10V

20% 402

CERM

0.1UF

7

75

C2515

10V

20% 402

CERM

0.1UF

C2514

10V

20% 402

CERM

0.1UF

C2513

10V

20% CERM

402

0.1UF

C2522

CERM 402

20% 10V

0.1UF

C2521

CERM 402

20% 10V

0.1UF

C2520

CERM 402

20% 10V

0.1UF

C2519

CERM 402

20% 10V

0.1UF

C2512

20% CERM

10V 402

0.1UF

C2511

10V

20% 402

CERM

0.1UF

C2510

CERM

10V

20% 402

0.1UF

25

C2518

CERM 402

20% 10V

0.1UF

C2501

10UF

603

20%

6.3V X5R

C2500

10UF

603

20%

6.3V X5R

C2524

10V

20% 402

CERM

0.1UF

C2502

402

10V

20% CERM

0.1UF

2-2013289-1

CRITICAL

F-RT-SM

J2500

25

C2536

10V

20% 402

CERM

0.1UF

25

C2535

20%

402-LF

CERM

2.2UF

6.3V

23 44 45

7

75

7

75

7

75

7

75

7

75

7

75

25

C2552

10V X6S-CERM

1UF

0402

10%

25

C2551

10V X6S-CERM

1UF

0402

10%

25

R2541

5%

402

MF-LF

10K

1/16W

R2540

1/16W

5%

402

MF-LF

10K

C2540

20% 402-LF

CERM

2.2UF

6.3V

25

C2550

10V X6S-CERM

1UF

0402

10%

25

21 23 75

25

47

25

7

75

SYNC_DATE=01/10/2013

DDR3 SO-DIMM CONNECTOR B

SYNC_MASTER=J16_NICK

MEM_B_SA<0>

MEM_B_SA<1>

=PPSPD_S0_MEM_B

=PPDDRVTT_S0_MEM_B=PPDDRVTT_S0_MEM_B

MEM_EVENT_L

=MEM_B_DQS_N<7>

=MEM_B_DQS_N<6>

=MEM_B_DQS_N<5>

=MEM_B_DQS_N<4>

MEM_B_CS_L<1>

MEM_B_CAS_L

MEM_B_CS_L<0>

MEM_B_WE_L

MEM_B_RAS_L

MEM_B_CLK_N<1>MEM_B_CLK_N<0>

=MEM_B_DQS_N<3>

=MEM_B_DQS_N<2>

MEM_RESET_L

=MEM_B_DQS_N<1>

=MEM_B_DQS_N<0>

=MEM_B_DQ<31>

MEM_B_BA<2>

MEM_B_A<12> MEM_B_A<9>

MEM_B_A<8>

=PPSPD_S0_MEM_B MEM_B_SA<1>

MEM_B_SA<0>

=MEM_B_DQ<59>

=MEM_B_DQ<58>

=MEM_B_DQ<57>

=MEM_B_DQ<56>

=MEM_B_DQ<50> =MEM_B_DQ<51>

=MEM_B_DQ<49>

=MEM_B_DQS_P<6>

=MEM_B_DQ<48>

=MEM_B_DQ<42> =MEM_B_DQ<43>

=MEM_B_DQ<40> =MEM_B_DQ<41>

=MEM_B_DQ<35>

=MEM_B_DQS_P<4>

=MEM_B_DQ<34>

=MEM_B_DQ<32> =MEM_B_DQ<33>

MEM_B_A<1>

MEM_B_CLK_P<0>

MEM_B_A<5>

MEM_B_CKE<0>

=MEM_B_DQ<26> =MEM_B_DQ<27>

=MEM_B_DQ<19>

=MEM_B_DQ<25>

=MEM_B_DQ<24>

=MEM_B_DQS_P<2>

=MEM_B_DQ<18>

=MEM_B_DQ<17>

=MEM_B_DQ<10> =MEM_B_DQ<11>

=MEM_B_DQ<16>

=MEM_B_DQS_P<1>

=MEM_B_DQ<9>

=MEM_B_DQ<8>

=MEM_B_DQ<3>

=MEM_B_DQ<2>

=I2C_SODIMMB_SCL

=I2C_SODIMMB_SDA

=MEM_B_DQ<62> =MEM_B_DQ<63>

=MEM_B_DQS_P<7>

=MEM_B_DQ<53>

=MEM_B_DQ<60> =MEM_B_DQ<61>

=MEM_B_DQ<52>

=MEM_B_DQ<45>

=MEM_B_DQS_P<5>

=MEM_B_DQ<46>

=MEM_B_DQ<44>

=MEM_B_DQ<47>

VOLTAGE=0.75V

PPVREF_S3_MEM_VREFCA_B

=MEM_B_DQ<36> =MEM_B_DQ<37>

=MEM_B_DQ<38> =MEM_B_DQ<39>

MEM_B_BA<1>

MEM_B_ODT<0>

MEM_B_ODT<1>

MEM_B_CLK_P<1>

MEM_B_A<0>

MEM_B_A<2>

MEM_B_A<6> MEM_B_A<4>

MEM_B_A<11> MEM_B_A<7>

MEM_B_A<14>

MEM_B_A<15>

MEM_B_CKE<1>

=PPVDDQ_S3_MEM_B

=MEM_B_DQ<30>

=MEM_B_DQS_P<3>

=MEM_B_DQ<29>

=MEM_B_DQ<28>

=MEM_B_DQ<23>

=MEM_B_DQ<22>

=MEM_B_DQ<21>

=MEM_B_DQ<13>

=MEM_B_DQ<14> =MEM_B_DQ<15>

=MEM_B_DQ<20>

=MEM_B_DQ<12>

=MEM_B_DQ<0>

PPVREF_S3_MEM_VREFDQ_B

VOLTAGE=0.75V

=MEM_B_DQ<7>

=MEM_B_DQ<6>

=MEM_B_DQ<4> =MEM_B_DQ<5>

=MEM_B_DQS_P<0>

=MEM_B_DQ<55>

=MEM_B_DQ<54>

MEM_B_A<3>

MEM_B_A<10> MEM_B_BA<0>

=PPVDDQ_S3_MEM_B

MEM_B_A<13>

=MEM_B_DQ<1>

051-0164

12.4.0

25 OF 123

24 OF 86

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

119

117

111

109

107

95

174 176 178

2

8

14

12

6

4

16 18

1 3

9

5 7

11 13

20 22

40

38

36

34

32

26

24

28

42 44

50

48

54

52

56

60

58

46

66

64

68

72

76

74

78 80 82

100

88

94

86

84

92

90

96 98

102

122

120

118

116

112

106 108

142

140

138

134

132

130

128

126

124

136

144

160

146

158

156

154

162

150

148

164

184

182

180

172

168

166

170

188

196

194

192

190

200 202

15 17 19 21 23 25

29 31

39

37

35

33

41

51

47 49

43

61

57 59

53 55

71

69

67

63 65

73

91

87

101

99

97

93

105

131

127

123 125

129

141

139

137

133

143

149

145

151

147

153

161

159

157

155

163

173

171

167

165

177

175

179 181 183 185 187

191

189

193

197

201

199

195

89

85

83

81

79

77

75

70

10

27

30

45

62

103 104

110

113 114 115

121

135

152

169

186

198

203 204

206205

2

1

2

1

2

1

2

1

2

1

2

1

2

1

24

24 70

24 70 24 70

24 70

24

22

24 70

22

24 70

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

THERE ARE NO PIN SWAPS

SYNC_MASTER=J16_NICK

DDR3 ALIASES AND BITSWAPS

SYNC_DATE=01/10/2013

MEM_B_DQS_P<6>

MAKE_BASE=TRUE

=MEM_A_DQS_P<6>

=MEM_A_DQ<45>

MEM_A_DQ<15>

MAKE_BASE=TRUE

MEM_A_DQ<2>

MAKE_BASE=TRUE

MEM_A_DQ<1> MEM_A_DQ<0>

MAKE_BASE=TRUE

MEM_A_DQS_N<1>

MAKE_BASE=TRUE

MEM_A_DQS_P<1>

MAKE_BASE=TRUE

MEM_A_DQS_N<2>

MEM_A_DQ<23>

MAKE_BASE=TRUE

MEM_A_DQ<9>

MAKE_BASE=TRUE

MEM_A_DQS_P<0>

MAKE_BASE=TRUE

MEM_A_DQ<18>

MAKE_BASE=TRUE

MEM_A_DQ<6>

MAKE_BASE=TRUE

MEM_B_DQ<7>

MAKE_BASE=TRUE

MEM_B_DQS_P<5>

MEM_B_DQS_N<6>

MAKE_BASE=TRUE

MEM_A_DQS_P<7>

MEM_A_DQS_N<7>

MAKE_BASE=TRUE

MEM_A_DQS_P<6>

MAKE_BASE=TRUE

MEM_A_DQS_N<6>

MAKE_BASE=TRUE

MEM_A_DQS_P<5>

MEM_A_DQS_N<5>

MAKE_BASE=TRUE

MEM_A_DQS_P<4>

MAKE_BASE=TRUE

MEM_A_DQS_N<4>

MEM_A_DQS_P<3>

MAKE_BASE=TRUE

MEM_A_DQS_N<3>

MAKE_BASE=TRUE

MEM_A_DQS_P<2>

MEM_B_DQS_P<7>

MAKE_BASE=TRUE

MEM_B_DQS_N<7>

MAKE_BASE=TRUE

MEM_B_DQS_N<5>

MAKE_BASE=TRUE

MEM_B_DQS_P<4>

MAKE_BASE=TRUE

MEM_B_DQS_N<4>

MEM_B_DQS_P<3>

MAKE_BASE=TRUE

MEM_B_DQS_N<3>

MAKE_BASE=TRUE

MEM_B_DQS_P<2>

MAKE_BASE=TRUE

MEM_A_DQS_N<0>

MEM_B_DQS_N<1>

MAKE_BASE=TRUE MAKE_BASE=TRUE

MEM_B_DQS_P<1>

MEM_B_DQS_N<2>

MAKE_BASE=TRUE

MEM_B_DQS_N<0>

MAKE_BASE=TRUE

MEM_B_DQS_P<0>

MAKE_BASE=TRUE

MEM_B_DQ<32>

MEM_B_DQ<45>

MAKE_BASE=TRUE

MEM_B_DQ<42> MEM_B_DQ<41>

MAKE_BASE=TRUE MAKE_BASE=TRUE

MEM_B_DQ<40>

MAKE_BASE=TRUE

MEM_B_DQ<48>

MEM_B_DQ<50>

MAKE_BASE=TRUE

MEM_B_DQ<55>

MEM_B_DQ<58>

MAKE_BASE=TRUE

MEM_B_DQ<56>

MEM_A_DQ<37>

MAKE_BASE=TRUE

MEM_A_DQ<32>

MEM_A_DQ<35>

MAKE_BASE=TRUE MAKE_BASE=TRUE

MEM_A_DQ<34>

MAKE_BASE=TRUE

MEM_A_DQ<45>

MAKE_BASE=TRUE

MEM_A_DQ<41>

MAKE_BASE=TRUE

MEM_A_DQ<42>

MEM_A_DQ<48>

MAKE_BASE=TRUE

MEM_A_DQ<53>

MAKE_BASE=TRUE

MEM_A_DQ<50>

MAKE_BASE=TRUE

MEM_A_DQ<51>

MEM_A_DQ<57>

MAKE_BASE=TRUE

MEM_A_DQ<56>

MAKE_BASE=TRUE

MEM_A_DQ<60>

MAKE_BASE=TRUE

MEM_A_DQ<59>

MAKE_BASE=TRUE

MEM_A_DQ<58>

MAKE_BASE=TRUE

MEM_B_DQ<33>

MAKE_BASE=TRUE

MEM_B_DQ<34>

MAKE_BASE=TRUE

MEM_B_DQ<36> MEM_B_DQ<35>

MAKE_BASE=TRUE

MEM_B_DQ<37>

MAKE_BASE=TRUE

MEM_B_DQ<38>

MAKE_BASE=TRUE

MEM_B_DQ<24>

MEM_B_DQ<25>

MAKE_BASE=TRUE

MEM_B_DQ<27>

MAKE_BASE=TRUE

MEM_B_DQ<26>

MAKE_BASE=TRUE

MEM_B_DQ<28>

MAKE_BASE=TRUE

MEM_B_DQ<29>

MAKE_BASE=TRUE

MEM_B_DQ<30>

MEM_B_DQ<31>

MAKE_BASE=TRUE

MEM_B_DQ<23>

MAKE_BASE=TRUE

MEM_B_DQ<21>

MAKE_BASE=TRUE

MEM_B_DQ<46>

MAKE_BASE=TRUE

MEM_B_DQ<47>

MEM_B_DQ<18>

MAKE_BASE=TRUE

MEM_B_DQ<17>

MAKE_BASE=TRUE

MEM_B_DQ<20>

MAKE_BASE=TRUE

MEM_B_DQ<43>

MAKE_BASE=TRUE

MEM_B_DQ<44>

MAKE_BASE=TRUE

MEM_B_DQ<16>

MAKE_BASE=TRUE

MEM_B_DQ<19>

MAKE_BASE=TRUE

MEM_B_DQ<22>

MEM_B_DQ<14>

MAKE_BASE=TRUE

MEM_B_DQ<49>

MAKE_BASE=TRUE

MEM_B_DQ<53>

MAKE_BASE=TRUE

MEM_B_DQ<12> MEM_B_DQ<11>

MAKE_BASE=TRUE MAKE_BASE=TRUE

MEM_B_DQ<10>

MAKE_BASE=TRUE

MEM_B_DQ<51>

MAKE_BASE=TRUE

MEM_B_DQ<9>

MEM_B_DQ<15>

MAKE_BASE=TRUE

MEM_B_DQ<8>

MEM_B_DQ<62>

MAKE_BASE=TRUE

MEM_B_DQ<1>

MAKE_BASE=TRUE

MEM_B_DQ<5>

MAKE_BASE=TRUE

MEM_B_DQ<3>

MAKE_BASE=TRUE

MEM_B_DQ<57>

MAKE_BASE=TRUE

MEM_B_DQ<59>

MEM_B_DQ<60>

MAKE_BASE=TRUE

MEM_B_DQ<61>

MAKE_BASE=TRUE

MEM_B_DQ<63>

MAKE_BASE=TRUE

MEM_B_DQ<0>

MAKE_BASE=TRUE

MEM_B_DQ<2>

MAKE_BASE=TRUE

MEM_B_DQ<4>

MAKE_BASE=TRUE

MEM_B_DQ<6>

MEM_A_DQ<27>

MAKE_BASE=TRUE

MEM_A_DQ<31>

MAKE_BASE=TRUE

MEM_A_DQ<36>

MEM_A_DQ<33>

MAKE_BASE=TRUE

MEM_A_DQ<26>

MAKE_BASE=TRUE

MEM_A_DQ<30>

MAKE_BASE=TRUE

MEM_A_DQ<38>

MAKE_BASE=TRUE

MEM_A_DQ<25>

MEM_A_DQ<29>

MAKE_BASE=TRUE

MEM_A_DQ<39>

MAKE_BASE=TRUE

MEM_A_DQ<24>

MAKE_BASE=TRUE

MEM_A_DQ<28>

MAKE_BASE=TRUE

MEM_A_DQ<22>

MAKE_BASE=TRUE

MEM_A_DQ<40>

MAKE_BASE=TRUE

MEM_A_DQ<44>

MEM_A_DQ<19>

MAKE_BASE=TRUE

MEM_A_DQ<43>

MAKE_BASE=TRUE

MEM_A_DQ<46>

MEM_A_DQ<47>

MAKE_BASE=TRUE

MEM_A_DQ<16>

MAKE_BASE=TRUE

MEM_A_DQ<17>

MAKE_BASE=TRUE

MEM_A_DQ<20>

MAKE_BASE=TRUE

MEM_A_DQ<21>

MEM_A_DQ<49>

MAKE_BASE=TRUE

MEM_A_DQ<52>

MAKE_BASE=TRUE

MEM_A_DQ<14>

MAKE_BASE=TRUE

MEM_A_DQ<11> MEM_A_DQ<10>

MAKE_BASE=TRUE

MEM_A_DQ<55>

MAKE_BASE=TRUE

MEM_A_DQ<12>

MEM_A_DQ<54>

MAKE_BASE=TRUE

MEM_A_DQ<13>

MEM_A_DQ<8>

MAKE_BASE=TRUE

MEM_A_DQ<7>

MAKE_BASE=TRUE

MEM_A_DQ<61>

MEM_A_DQ<3>

MAKE_BASE=TRUE

MEM_A_DQ<62>

MEM_A_DQ<4>

MAKE_BASE=TRUE

MEM_A_DQ<63>

MAKE_BASE=TRUE

MEM_A_DQ<5>

MEM_B_DQ<13>

MAKE_BASE=TRUE

MEM_B_DQ<39>

MEM_B_DQ<52>

MAKE_BASE=TRUE

MEM_B_DQ<54>

MAKE_BASE=TRUE

=MEM_A_DQ<42>

=MEM_A_DQS_P<3>

=MEM_A_DQ<21>

=MEM_A_DQ<22>

=MEM_A_DQ<20>

=MEM_A_DQ<18> =MEM_A_DQ<17> =MEM_A_DQ<16>

=MEM_A_DQS_N<3>

=MEM_A_DQ<28>

=MEM_B_DQS_N<5>

=MEM_B_DQ<42>

=MEM_B_DQ<45>

=MEM_B_DQ<26>

=MEM_B_DQ<27>

=MEM_B_DQ<24>

=MEM_B_DQ<10>

=MEM_B_DQ<12>

=MEM_A_DQS_N<0> =MEM_A_DQS_P<0>

=MEM_A_DQ<6>

=MEM_A_DQ<0>

=MEM_A_DQ<5>

=MEM_A_DQ<63>

=MEM_A_DQ<58>

=MEM_A_DQ<4>

=MEM_A_DQ<1>

=MEM_A_DQ<62>

=MEM_A_DQ<59>

=MEM_A_DQ<3> =MEM_A_DQ<2>

=MEM_A_DQ<61> =MEM_A_DQ<60>

=MEM_A_DQ<56>

=MEM_A_DQ<57>

=MEM_A_DQ<7>

=MEM_A_DQ<8>

=MEM_A_DQ<54>

=MEM_A_DQ<51>

=MEM_A_DQ<12>

=MEM_A_DQ<55>

=MEM_A_DQ<50>

=MEM_A_DQ<10>

=MEM_A_DQ<53>

=MEM_A_DQ<14>

=MEM_A_DQ<11>

=MEM_A_DQ<52>

=MEM_A_DQ<49> =MEM_A_DQ<48>

=MEM_A_DQ<47> =MEM_A_DQ<46>

=MEM_A_DQ<43>

=MEM_A_DQ<23>

=MEM_A_DQ<19>

=MEM_A_DQ<44>

=MEM_A_DQ<40>

=MEM_A_DQ<41>

=MEM_A_DQ<34>

=MEM_A_DQ<24>

=MEM_A_DQ<39>

=MEM_A_DQ<35>

=MEM_A_DQ<29>

=MEM_A_DQ<25>

=MEM_A_DQ<38>

=MEM_A_DQ<33>

=MEM_A_DQ<30>

=MEM_A_DQ<26>

=MEM_A_DQ<32>

=MEM_A_DQ<36>

=MEM_A_DQ<31>

=MEM_A_DQ<27>

=MEM_A_DQ<37>

=MEM_B_DQ<4>

=MEM_B_DQ<6>

=MEM_B_DQ<63>

=MEM_B_DQ<61> =MEM_B_DQ<60> =MEM_B_DQ<59>

=MEM_B_DQ<57> =MEM_B_DQ<56>

=MEM_B_DQ<2>

=MEM_B_DQ<3>

=MEM_B_DQ<1>

=MEM_B_DQ<62>

=MEM_B_DQ<58>

=MEM_B_DQ<5>

=MEM_B_DQ<8>

=MEM_B_DQ<55>

=MEM_B_DQ<9>

=MEM_B_DQ<15>

=MEM_B_DQ<51> =MEM_B_DQ<50>

=MEM_B_DQ<13>

=MEM_B_DQ<11>

=MEM_B_DQ<53> =MEM_B_DQ<52>

=MEM_B_DQ<49> =MEM_B_DQ<48>

=MEM_B_DQ<54>

=MEM_B_DQ<14>

=MEM_B_DQ<22>

=MEM_B_DQ<19>

=MEM_B_DQ<16>

=MEM_B_DQ<44> =MEM_B_DQ<43>

=MEM_B_DQ<40>

=MEM_B_DQ<20>

=MEM_B_DQ<17>

=MEM_B_DQ<47> =MEM_B_DQ<46>

=MEM_B_DQ<41>

=MEM_B_DQ<18>

=MEM_B_DQ<21>

=MEM_B_DQ<23>

=MEM_B_DQ<38>

=MEM_B_DQ<32>

=MEM_B_DQ<39>

=MEM_B_DQ<37>

=MEM_B_DQ<30>

=MEM_B_DQ<31>

=MEM_B_DQ<33>

=MEM_B_DQ<34>

=MEM_B_DQ<35>

=MEM_B_DQ<36>

=MEM_B_DQ<25>

=MEM_B_DQ<28>

=MEM_B_DQ<29>

=MEM_A_DQS_N<1>

=MEM_B_DQS_N<2>

=MEM_A_DQS_P<5>

=MEM_A_DQS_P<2>

=MEM_B_DQS_P<1>

=MEM_B_DQS_N<1>

=MEM_A_DQS_P<1>

=MEM_B_DQS_P<5>

=MEM_B_DQS_N<6> =MEM_B_DQS_P<6>

=MEM_B_DQS_N<7> =MEM_B_DQS_P<7>

=MEM_A_DQS_N<2>

=MEM_A_DQS_N<4> =MEM_A_DQS_P<4>

=MEM_A_DQS_N<5>

=MEM_A_DQS_N<6>

=MEM_A_DQS_N<7> =MEM_A_DQS_P<7>

=MEM_B_DQS_P<4>

=MEM_B_DQS_N<4>

=MEM_B_DQS_P<3>

=MEM_B_DQS_N<3>

=MEM_B_DQS_P<2>

=MEM_B_DQ<7>

=MEM_B_DQS_P<0>

=MEM_B_DQS_N<0>

=MEM_B_DQ<0>

=MEM_A_DQ<9>

=MEM_A_DQ<13>

=MEM_A_DQ<15>

051-0164

12.4.0

27 OF 123

25 OF 86

7

75 23

23

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

23

24

23

24

23

24

23

24

23

24

23

24

23

OUT

IN

OUT

IN

OUT

IN

OUT

OUT OUT

IN

OUT

IN IN

OUT

BI

IN

BI

OUT IN

OUT

IN

OUT OUT

BI BI

IN

IN IN IN OUT

OUT OUT

BI BI

IN

OUT OUT OUT

OUT

PETN_3

PETN_2

PETP_2

PETP_1 PETN_1

PETP_0 PETN_0

MONOBS_N

MONDC0 MONDC1

PERN_3

PERP_3

PERN_2

PERP_2

PERN_1

PERP_1

PERP_0 PERN_0

MONOBS_P

TMU_CLK_IN

TMU_CLK_OUT

DPSRC_3_P

DPSRC_2_P

DPSRC_3_N

DPSRC_1_P

DPSRC_2_N

DPSRC_1_N

DPSRC_0_P

DPSRC_AUX_P

DPSRC_0_N

DPSRC_HPD_OD

DPSRC_AUX_N

GPIO_2/GO2SX

GPIO_15

GPIO_9/OK2GO2SX_OD*

GPIO_14

GPIO_8/EN_CIO_PWR_OD*

GPIO_7/CIO_SCL_OD

GPIO_6/CIO_SDA_OD

GPIO_5/CIO_PLUG_EVENT

GPIO_4/WAKE_N_OD

GPIO_3

PB_CIO3_TX_N/DP_SRC_2_N

PB_CONFIG2/CIO_2_LSOE

PB_CIO2_RX_N

PB_CONFIG1/CIO_2_LSEO

PB_CIO2_RX_P

PB_CIO2_TX_P/DP_SRC_0_P PB_CIO2_TX_N/DP_SRC_0_N

PB_CIO3_TX_P/DP_SRC_2_P

PB_DPSRC_3_N

PB_DPSRC_1_N

PB_DPSRC_1_P

PB_LSRX/CIO_3_LSOE

PB_CIO3_RX_N

PB_LSTX/CIO_3_LSEO

PB_CIO3_RX_P

PB_DPSRC_3_P

GPIO_11/PB_CIO_SEL/BYP1

GPIO_13/PB_DP_PWRDN/BYP2

GPIO_1/PB_HV_EN/BYP0

PB_DPSRC_HPD

PB_AUX_N

PB_AUX_P

THERMDA

EE_DI EE_DO EE_CS_N

TDI

EE_CLK

TDO

DPSNK0_2_P

DPSNK0_3_N

DPSNK0_1_P

DPSNK0_2_N

DPSNK0_0_P

DPSNK0_1_N

DPSNK0_AUX_P

DPSNK0_0_N

DPSNK0_HPD

DPSNK0_AUX_N

DPSNK1_3_N

DPSNK1_3_P

DPSNK1_2_N

DPSNK1_2_P

DPSNK1_1_N

DPSNK1_1_P

DPSNK1_0_N

DPSNK1_0_P

DPSNK1_AUX_N

DPSNK1_AUX_P

DPSNK1_HPD

PA_CIO0_TX_N/DP_SRC_0_N

PA_CIO0_TX_P/DP_SRC_0_P

PA_CIO0_RX_N

PA_CIO0_RX_P

PA_CONFIG2/CIO_0_LSOE

PA_CONFIG1/CIO_0_LSEO

PA_CIO1_TX_N/DP_SRC_2_N

PA_CIO1_TX_P/DP_SRC_2_P

PA_CIO1_RX_N

PA_CIO1_RX_P

PA_LSRX/CIO_1_LSOE

PA_LSTX/CIO_1_LSEO

PA_DPSRC_1_N

PA_DPSRC_1_P

PA_DPSRC_3_N

PA_DPSRC_3_P

PA_AUX_P

PA_DPSRC_HPD

PA_AUX_N

GPIO_10/PA_CIO_SEL/BYP1

GPIO_0/PA_HV_EN/BYP0

GPIO_12/PA_DP_PWRDN/BYP2

PETP_3

RSENSE

REFCLK_100_IN_P REFCLK_100_IN_N

XTAL_25_IN

XTAL_25_OUT

TMS TCK

TEST_EN TEST_PWR_GOOD

DPSNK0_3_P

PWR_ON_POC_RSTN

PERST_N

NC

RBIAS

PCIE_RST_0_N PCIE_RST_1_N

PCIE_RST_3_N

PCIE_RST_2_N

PCIE_CLKREQ_OD_N

EN_LC_PWR

PCIE RESET

PCIE GEN2

MISC

(SYM 1 OF 2)

CLOCKS

JTAG/TEST PORT

RECEIVE

TRANSMIT

EEPROM

SINK PORT 0SINK PORT 1

SOURCE PORT 0

PORT3 PORT2

PORT0PORT1

DISPLAYPORT

PORTS

OUT

NC

IN

IN IN

OUT

IN

D

C

Q

S*

W*

HOLD*

PAD

VSS

THM

VCC

IN

OUT

BI

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(TBT_SPI_CS_L)

(TBT_SPI_CLK)

(TBT_SPI_MOSI)

SNK0 AC Coupling

(TBT_SPI_MISO)

(TBT_EN_CIO_PWR_L)

(FORCE_PWR)

SNK1 AC Coupling

of GPIO_2/GPIO_9 if necessary.

Use AA8 GND ball for THERM_DN

For unused port, pull CONFIG1, CONFIG2, LSRX, HPD and CIO_SEL low (10k). All other port signals can be NC.

Not used in host mode.

8 - GPIO_15 9 - GPIO_11 10 - GPIO_14 11 - GPIO_0 12 - GPIO_12 13 - GPIO_10 14 - PB_LSTX 15 - PB_LSRX

NOTE: The following pins require testpoints:

3 - GPIO_3

2 - GPIO_2

1 - GPIO_1

0 - GPIO_13

4 - GPIO_5

7 - PCIE_RST_3_N

6 - PCIE_RST_2_N

5 - PCIE_RST_1_N

Divides 3.3V to 1.8V

DEBUG: For monitoring current/voltage

DEBUG: For monitoring clock

allows separation

R2881 FOR CYA,

STUFF ONE OF R2881/2.

5% 1/16W MF-LF

402

3.3K

R2890

71

5%

0

MF-LF

402

R2825

1/16W

5%

MF-LF 402

1/16W

100K

R2832

29

29 85

29

29 85

30

30 85

30

30 85

402

MF-LF

1/16W

5%

100K

R2830

5%

MF-LF

100K

402

1/16W

R2831

29 85

5%

0

402

MF-LF

1/16W

R2829

5%

402

R2893

MF-LF

1/16W

3.3K

0201

16V

X5R-CERM

C2829

0.1UF

10%

71 85

0201

16V

X5R-CERM

C2828

0.1UF

10%

0201

16V

X5R-CERM

C2827

0.1UF

10%

0201

16V

X5R-CERM

0.1UF

10%

C2826

0201

16V

X5R-CERM

C2825

0.1UF

10%

0201

16V

X5R-CERM

C2824

0.1UF

10%

0201

16V

X5R-CERM

C2823

0.1UF

10%

0201

16V

X5R-CERM

C2822

0.1UF

10%

201

1/20W MF

R2855

1K

1%

16V

X5R-CERM

0201

C2821

0.1UF

10%

X5R-CERM

0201

16V

C2820

0.1UF

10%

0201

16V

X5R-CERM

C2830

0.1UF

10%

0201

16V

X5R-CERM

C2831

0.1UF

10%

0201

16V

X5R-CERM

C2832

0.1UF

10%

0201

16V

X5R-CERM

C2833

0.1UF

10%

0201

16V

X5R-CERM

C2834

0.1UF

10%

0201

16V

X5R-CERM

C2835

0.1UF

10%

0201

16V

X5R-CERM

C2836

0.1UF

10%

0201

16V

X5R-CERM

C2837

0.1UF

10%

0201

16V

X5R-CERM

C2838

0.1UF

10%

0201

16V

X5R-CERM

C2839

0.1UF

10%

71 85

C2890

402

CERM

6.3V

10%

1UF

71 85

29

30

28

30 85

30

20

29 85

29

26 29

29

26 29

26 30

30

26 30

28

12

CACTUSRIDGE4C

CRITICAL

OMIT_TABLE

FCBGA

U2800

28

19 79

5%

10K

402

MF-LF

1/16W

R2898

1/16W MF-LF

1%

806

402

R2895

5%

1K

402

1/16W MF-LF

R2896

5%

10K

1/16W

NO STUFF

MF-LF

402

R2899

11 77

28

OMIT_TABLE

U2890

MLP

M95256-RMC6XG

CRITICAL

5%

100K

MF-LF

1/16W

402

R2897

NONE

NOSTUFF

NONE

402

NONE

OMIT

R2815

5%

10K

1/16W MF-LF

402

R2888

5% 1/16W

10K

402

MF-LF

R2887

5%

10K

1/16W

402

MF-LF

R2886

5%

10K

402

MF-LF

1/16W

R2885

5%

10K

1/16W

402

MF-LF

R2880

5%

10K

1/16W

402

MF-LF

NO STUFF

R2882

20

26 31

0402

X7R-CERM

NO STUFF

16V

C2810

0.1UF

10%

5%

1/16W

47K

402

MF-LF

R2810

20

12

5%

10K

1/16W

402

MF-LF

R2883

5%

0

402

1/16W MF-LF

R2881

14 26

5%

402

MF-LF

3.3K

1/16W

R2889

5%

3.3K

1/16W

402

MF-LF

R2894

MF 0201

R2801

0

1/20W

5%

41

0201

X5R-CERM

16V

C2801

0.1UF

10%

0201

X5R-CERM

16V

C2800

0.1UF

10%

0201

X5R-CERM

16V

C2802

0.1UF

10%

0201

X5R-CERM

16V

C2803

0.1UF

10%

5%

MF-LF

1/16W

R2892

402

3.3K

0201

X5R-CERM

16V

C2804

0.1UF

10%

0201

X5R-CERM

16V

C2805

0.1UF

10%

0201

X5R-CERM

16V

C2806

0.1UF

10%

0201

X5R-CERM

16V

C2807

0.1UF

10%

0201

16V

X5R-CERM

C2840

0.1UF

10%

0201

16V

X5R-CERM

C2841

0.1UF

10%

0201

X5R-CERM

16V

C2842

0.1UF

10%

5%

3.3K

1/16W

402

MF-LF

R2891

0201

X5R-CERM

16V

C2843

0.1UF

10%

0201

16V

X5R-CERM

C2845

0.1UF

10%

0201

16V

X5R-CERM

C2844

0.1UF

10%

0201

16V

X5R-CERM

C2846

0.1UF

10%

0201

16V

X5R-CERM

C2847

0.1UF

10%

13 77

Thunderbolt Host (1 of 2)

SYNC_MASTER=J16_MAX

SYNC_DATE=02/11/2013

DP_TBTSRC_HPD

TP_DP_TBTSRC_AUXCH_CN

TBT_GO2SX_BIDIR

=TBT_WAKE_L TBT_CIO_PLUG_EVENT

SYSCLK_CLK25M_TBT

DP_TBTSNK0_AUXCH_N

TBT_GPIO_9

TBT_DDC_XBAR_EN_L

=PP3V3_TBTLC_RTR

PCIE_TBT_D2R_N<3>

PCIE_TBT_D2R_N<2>

=PP3V3_S4_TBT

=PP3V3_TBTLC_RTR

=PP3V3_S4_TBT

PCIE_TBT_R2D_C_P<3>

PCIE_TBT_R2D_C_N<2>

DP_TBTSNK0_ML_P<3>

DP_TBTSNK0_ML_N<3>

DP_TBTSNK1_ML_N<0>

DP_TBTSNK1_ML_C_N<1>

DP_TBTSNK0_AUXCH_C_N

DP_TBTSNK0_ML_C_P<1>

DP_TBTSNK0_ML_C_N<1>

DP_TBTSNK1_ML_P<0>

PCIE_TBT_R2D_C_N<3>

DP_TBTSNK1_AUXCH_N

DP_TBTSNK0_AUXCH_P

DP_TBTSNK1_ML_C_N<2>

DP_TBTSNK1_ML_N<1>

PCIE_TBT_D2R_P<0>

PCIE_TBT_D2R_N<0>

PCIE_TBT_D2R_P<1>

PCIE_TBT_D2R_N<1>

PCIE_TBT_D2R_P<3>

DP_TBTSNK0_ML_C_P<0>

DP_TBTSNK0_ML_C_N<0>

DP_TBTSNK0_ML_C_P<2>

DP_TBTSNK0_ML_C_N<2>

DP_TBTSNK0_ML_C_P<3>

DP_TBTSNK0_ML_C_N<3>

DP_TBTSNK1_ML_C_P<0>

DP_TBTSNK1_ML_C_N<0>

DP_TBTSNK1_ML_C_P<1>

DP_TBTSNK1_ML_C_P<2>

DP_TBTSNK1_ML_C_P<3>

DP_TBTSNK1_ML_C_N<3>

DP_TBTSNK1_AUXCH_C_P

DP_TBTSNK1_AUXCH_C_N

DP_TBTSNK0_ML_N<1>

DP_TBTSNK0_ML_N<2>

DP_TBTSNK1_ML_P<1>

DP_TBTSNK1_ML_P<2>

DP_TBTSNK1_ML_P<3>

DP_TBTSNK1_ML_N<3>

DP_TBTSNK1_AUXCH_P

DP_TBTSNK1_ML_N<2>

PCIE_TBT_R2D_C_N<1>

PCIE_TBT_R2D_C_P<1>

PCIE_TBT_R2D_C_N<0>

PCIE_TBT_R2D_C_P<0>

PCIE_TBT_R2D_C_P<2>

TBT_A_HV_EN TBT_B_HV_EN

TBT_PWR_REQ_L

DP_TBTSNK0_ML_P<1>

TBT_GPIO_14

=TBT_CLKREQ_L

TP_TBT_PCIE_RESET2_L TP_TBT_PCIE_RESET3_L

TP_TBT_PCIE_RESET1_L

TP_TBT_PCIE_RESET0_L

TBT_RBIAS

DP_TBTSNK0_ML_P<3>

TBT_TEST_PWR_GOOD

JTAG_TBT_TCK

JTAG_TBT_TMS

TP_TBT_XTAL25OUT

PCIE_CLK100M_TBT_N

PCIE_CLK100M_TBT_P

TBT_RSENSE

PCIE_TBT_D2R_C_P<3>

TBT_A_DP_PWRDN

TBT_A_HV_EN TBT_A_CIO_SEL

DP_TBTPA_AUXCH_C_N

DP_TBTPA_HPD

DP_TBTPA_AUXCH_C_P

DP_TBTPA_ML_C_P<3> DP_TBTPA_ML_C_N<3>

DP_TBTPA_ML_C_P<1> DP_TBTPA_ML_C_N<1>

TBT_A_LSTX TBT_A_LSRX

TBT_A_D2R_P<1> TBT_A_D2R_N<1>

TBT_A_R2D_C_P<1> TBT_A_R2D_C_N<1>

TBT_A_CONFIG1_BUF TBT_A_CONFIG2_RC

TBT_A_D2R_P<0> TBT_A_D2R_N<0>

TBT_A_R2D_C_P<0> TBT_A_R2D_C_N<0>

DP_TBTSNK1_HPD

DP_TBTSNK1_AUXCH_P DP_TBTSNK1_AUXCH_N

DP_TBTSNK1_ML_P<0> DP_TBTSNK1_ML_N<0>

DP_TBTSNK1_ML_P<1> DP_TBTSNK1_ML_N<1>

DP_TBTSNK1_ML_P<2> DP_TBTSNK1_ML_N<2>

DP_TBTSNK1_ML_P<3> DP_TBTSNK1_ML_N<3>

DP_TBTSNK0_ML_N<0>

DP_TBTSNK0_AUXCH_P

DP_TBTSNK0_ML_N<1>

DP_TBTSNK0_ML_P<0>

DP_TBTSNK0_ML_N<2>

DP_TBTSNK0_ML_N<3>

DP_TBTSNK0_ML_P<2>

JTAG_TBT_TDO

TP_TBT_THERM_DP

DP_TBTPB_AUXCH_C_P DP_TBTPB_AUXCH_C_N

TBT_B_HV_EN

TBT_B_DP_PWRDN

TBT_B_CIO_SEL

DP_TBTPB_ML_C_P<3>

TBT_B_LSTX

TBT_B_D2R_N<1>

DP_TBTPB_ML_C_P<1> DP_TBTPB_ML_C_N<1>

DP_TBTPB_ML_C_N<3>

TBT_B_R2D_C_P<1>

TBT_B_R2D_C_N<0>

TBT_B_D2R_P<0>

TBT_B_CONFIG1_BUF

TBT_B_D2R_N<0>

TBT_B_CONFIG2_RC

TBT_B_R2D_C_N<1>

TBT_GPIO_14 TBT_DDC_XBAR_EN_L

TP_DP_TBTSRC_ML_CP<0>

TP_DP_TBTSRC_ML_CN<1>

TP_DP_TBTSRC_ML_CN<2>

TP_DP_TBTSRC_ML_CP<1>

TP_DP_TBTSRC_ML_CN<3>

TP_DP_TBTSRC_ML_CP<2>

TP_DP_TBTSRC_ML_CP<3>

TBT_TMU_CLK_OUT TBT_TMU_CLK_IN

TBT_MONOBSP

PCIE_TBT_R2D_N<1>

PCIE_TBT_R2D_N<2>

TP_TBT_MONDC1

TP_TBT_MONDC0

TBT_MONOBSN

PCIE_TBT_D2R_C_N<0>

PCIE_TBT_D2R_C_P<0>

PCIE_TBT_D2R_C_N<1>

PCIE_TBT_D2R_C_P<1>

PCIE_TBT_D2R_C_P<2>

PCIE_TBT_D2R_C_N<3>

I2C_TBTRTR_SCL

I2C_TBTRTR_SDA

DP_TBTSNK0_ML_P<1>

TBT_B_R2D_C_P<0>

DP_TBTSNK0_HPD

DP_TBTSNK0_AUXCH_N

TBT_GPIO_9

TBT_PWR_EN

TBT_GO2SX_BIDIR

I2C_TBTRTR_SDA

TBT_B_D2R_P<1>

TBT_B_LSRX

DP_TBTPB_HPD

I2C_TBTRTR_SCL

TBT_B_DP_PWRDN

TBT_A_DP_PWRDN

=PP3V3_TBTLC_RTR

MAKE_BASE=TRUE

TBT_EN_CIO_PWR_L

JTAG_TBT_TDI

PCIE_TBT_D2R_C_N<2>

TBT_PCIE_RESET_L

PCIE_TBT_R2D_N<3>

PCIE_TBT_R2D_P<2>

PCIE_TBT_R2D_P<1>

PCIE_TBT_R2D_N<0>

PCIE_TBT_R2D_P<0>

PCIE_TBT_R2D_P<3>

TBT_EN_LC_PWR

SYSCLK_CLK25M_TBT_R

PCIE_TBT_D2R_P<2>

TBT_PWR_ON_POC_RST_L

DP_TBTSNK0_ML_N<0>

=PP3V3_TBTLC_RTR

DP_TBTSNK0_ML_P<0>

DP_TBTSNK0_ML_P<2>

TBTROM_WP_L

TBTROM_HOLD_L

TBT_SPI_CLK_RES

TBT_TEST_EN

TP_DP_TBTSRC_ML_CN<0>

TP_DP_TBTSRC_AUXCH_CP

DP_TBTSNK0_AUXCH_C_P

TBT_SPI_MOSI TBT_SPI_MISO TBT_SPI_CS_L TBT_SPI_CLK

051-0164

12.4.0

28 OF 123

26 OF 86

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1 2

1

2

1 2

2

1

AD19

AD15

AD13

AD9

AD11

AD5

AD7

W16

AD23

AC24

AB19

AA18

AA16

AB15

AB13

AA12

AB9

AA10

W18

Y3

AA4

A14

A12

B15

A10

B13

B11

A8

C2

B9

V3

D3

Y1

V5

M5

T3

P3

AC2

AB1

AA2

J4

W2

U24

H5

N22

P1

R22

R24

N24

W24

B23

B21

A20

G6

U22

L6

W22

A22

L2 L4

M1

K3

E2

D1

Y7

R4

P5

AD3

V1

W4

R2

E16

D13

E18

D15

E20

D17

A6

D19

U6

B5

D5

E6

D7

E8

D9

E10

D11

E12

B3

A4

T5

E24

G24

E22

G22

G4

K1

J24

L24

J22

L22

J6

N2

B17

A16

B19

A18

F3

H1

F1

M3

G2

H3

AD17

U20

AB21 AD21

AA24

AB23

AB3

AA6

N4

AB5

E14

J2

R6

U4

W20

N6 T1

U2

Y5

W6

K5

1

2

1 2

121

2

94

5

6

2

1

3

7

8

1

2

1

2

121

2

121

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1 2

1

2

1 2

1

2

1 2

41

14 26

26 85

26

26 31

26 27 28 70

26 27 28 29 30 68 70

26 27 28 70

26 27 28 29 30 68 70

26 85

26 29

26 30

26 85

26

72

26 85

77

26 85

72

26

41

77

26 85

26

26 85

26 30

26 29

26 27 28 70

77

79

26 85

26 27 28 70

26 85

41

85

Apple 820-3588-A Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual