Apple 820-3588-A Schematic

DRAWING

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

II NOT TO REPRODUCE OR COPY IT

3

B

7

BRANCH

DRAWING NUMBER

SIZE

D

SHEET

R

DATE

D

A

C

PAGE

A

C

3456

D

B

8 7 6 5 4 2 1

12

APPD

CK

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

DRAWING TITLE

DESCRIPTION OF REVISION

REV ECN

REVISION

PROPRIETARY PROPERTY OF APPLE INC.

TABLE_TABLEOFCONTENTS_ITEM

J16 MLB_IG

1 OF 86

SCHEM,MLB IG,J16

051-0164

2013-03-22

1 OF 123

12.4.0

ABBREV=DRAWING

TITLE=J16 MLB_IG

LAST_MODIFIED=Fri Mar 22 11:24:26 2013

49

03/13/2013

J16_TONY

55

I and V Sense(Continued)

(.csa)

Date

Sync

Contents

Page

1

J16_MLB

12/03/2012

1

Table of Contents

Page

(.csa)

Contents

Date

Sync

50

01/11/2013

J16_FIYIN

56

Temperature Sensors

51

01/07/2013

J16_JERRY

60

System Fan

52

03/07/2013

J16_DIRK

61

AUDIO: CODEC/REGULATORS

53

03/07/2013

J16_DIRK

62

AUDIO: HEADPHONE AMP

54

03/07/2013

J16_DIRK

63

AUDIO: LEFT SPKR AMP

55

03/07/2013

J16_DIRK

64

AUDIO: RIGHT SPKR AMP

56

03/07/2013

J16_DIRK

65

AUDIO: Jack, Mikey, CHS Switch

57

03/07/2013

J16_DIRK

66

Audio: Spkr/Mic Conn.

58

03/07/2013

J16_DIRK

67

AUDIO: Detects/Grounding

59

03/07/2013

J16_DIRK

68

AUDIO: Speaker ID

60

03/04/2013

J16_ROSSANA

69

Power Connectors / VReg G3Hot

61

03/21/2013

J16_ROSSANA

70

VReg CPU VCC Cntl

62

03/21/2013

J16_ROSSANA

71

VReg CPU VCC Phases

63

03/04/2013

J16_ROSSANA

73

VReg VDDQ S3

64

03/04/2013

J16_ROSSANA

74

VREG 1V05 S0 / 1V5 S0

65

03/04/2013

J16_ROSSANA

76

VReg 3.3V S5/5V S4

66

01/22/2013

J16_LINDA

81

LCD Backlight Driver (LP8561)

67

02/11/2013

J16_MAX

84

FET-Controlled S0 and S4

68

02/21/2013

J16_AARON

85

PM Regulator Enables

69

02/21/2013

J16_AARON

86

PM Power Good

70

02/11/2013

J16_MAX

100

Power Aliases

71

02/11/2013

J16_MAX

102

Signal Aliases

72

02/11/2013

J16_MAX

104

Unused Signal Aliases

73

02/11/2013

J16_MAX

105

Functional / ICT Test

74

12/03/2012

J16_MLB

110

J16 RULE DEFINITIONS

75

01/10/2013

J16_NICK

111

DDR3 Constraints

76

01/10/2013

J16_NICK

112

CPU CONSTRAINTS

77

01/10/2013

J16_NICK

113

PCH PCIe/DMI Constaints

78

01/10/2013

J16_NICK

114

SATA/FDI/XDP Constraints

79

12/03/2012

J16_MLB

115

PCH and BR Constraints

80

12/03/2012

J16_MLB

116

USB/Ethernet/SD Constraints

81

01/10/2013

J16_NICK

117

SMBus/Sensor Constraints

82

01/10/2013

J16_NICK

118

VReg Constraints

83

12/14/2012

J16_ROSSANA

119

CPU VReg Constraints

84

12/20/2012

J16_ROSSANA

120

Platform VReg Constraints

85

12/03/2012

J16_MLB

121

TBT/DP Constraints

86

12/03/2012

J16_MLB

123

BLC Constraints

2

J16_DINI

01/29/2013

2

BOM Configuration

3

J16_MAX

02/11/2013

3

DEBUG LEDS

4

J16_MAX

02/11/2013

4

Holes/PD parts

5

J16_DINI

01/14/2013

5

CPU DMI/PEG/FDI/RSVD

6

J16_DINI

01/14/2013

6

CPU Clock/Misc/JTAG/CFG

7

J16_DINI

01/14/2013

7

CPU DDR3 Interfaces

8

J16_DINI

01/14/2013

8

CPU Power

9

J16_DINI

01/14/2013

9

CPU Ground

10

J16_DINI

01/14/2013

10

CPU Decoupling

11

J16_KENNY

01/21/2013

11

PCH RTC/HDA/JTAG/SATA/CLK

12

J16_KENNY

01/21/2013

12

PCH DMI/FDI/PM/GFX/PCI

13

J16_KENNY

01/21/2013

13

PCH PCI-E/USB

14

J16_KENNY

03/07/2013

14

PCH GPIO/MISC/NCTF

15

J16_KENNY

01/21/2013

15

PCH Power

16

J16_KENNY

01/21/2013

16

PCH Grounds

17

J16_KENNY

01/21/2013

17

PCH DECOUPLING

18

J16_KENNY

03/18/2013

18

CPU & PCH XDP

19

J16_KENNY

01/21/2013

19

Chipset Support

20

J16_KENNY

01/21/2013

20

Project Chipset Support

21

J16_NICK

12/11/2012

21

CPU Memory S3 Support

22

J16_NICK

01/10/2013

22

DDR3 VREF MARGINING

23

J16_NICK

01/10/2013

23

DDR3 SO-DIMM Connector A

25

J16_NICK

01/10/2013

24

DDR3 SO-DIMM CONNECTOR B

27

J16_NICK

01/10/2013

25

DDR3 ALIASES AND BITSWAPS

28

J16_MAX

02/11/2013

26

Thunderbolt Host (1 of 2)

29

J16_MAX

02/11/2013

27

Thunderbolt Host (2 of 2)

30

J16_MAX

02/11/2013

28

Thunderbolt Power Support

32

J16_MAX

02/11/2013

29

Thunderbolt Connector A

33

J16_MAX

02/11/2013

30

Thunderbolt Connector B

34

J16_MAX

02/11/2013

31

TBT DDC Crossbar

35

J16_FIYIN

01/11/2013

32

AIRPORT/BT

37

J16_JERRY

01/07/2013

33

SATA/SSD Connectors

38

J16_JERRY

01/07/2013

34

HDD Connector

39

J16_MAX

02/11/2013

35

ETHERNET PHY (CAESAR IV)

40

J16_MAX

02/11/2013

36

Ethernet Support & Connector

41

J16_MAX

02/11/2013

37

SD READER CONNECTOR

42

J16_MAX

02/11/2013

38

Camera Controller

43

J16_MAX

02/11/2013

39

Camera Controller Support

44

J16_MAX

02/11/2013

40

Internal DP Support

45

J16_MAX

02/11/2013

41

Internal DP MUXing

46

J16_KOSECOFF

03/18/2013

42

EXTERNAL USB PORTS A & B

47

J16_KOSECOFF

03/18/2013

43

EXTERNAL USB PORTS C & D

50

J16_TONY

03/13/2013

44 SMC

51

J16_TONY

03/13/2013

45

SMC Support

52

J16_TONY

03/13/2013

46

SPI and Debug Connector

53

J16_TONY

03/13/2013

47

SMBus Connections

54

J16_TONY

03/13/2013

48

I and V Sense

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_ALT_ITEM

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_BOMGROUP_ITEM

TABLE_5_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

ADD ’J16_PRODUCTION’ AT REVA RELEASE

Alternates

R5430

R5400,R5520,R5530

Bar Code Labels / EEEE #’s

Schematic / PCB #’s

Programmable Parts

ASIC Parts

BOM Groups

Main BOM Variants

CPUs

CPU:CTO

U0500

CRITICAL

1

337S4517

CRW,QEUX,EEU2,C0,3.2G,65W,4+3,1.3,6M,BGA

CPU:BETTER

CRITICAL

1

U0500

337S4516

CRW,QEUY,EEU2,C0,3.0G,65W,4+3,1.13,4M,BGA

CPU:GOOD

CRITICAL

U0500

1

337S4515

CRW,QEUZ,EEU2,C0,2.7G,65W,4+3,1.15,4M,BGA

AP_ISNS:Y,HDD_IVSNS:Y,TEMPSNSDEV

DEVEL_SENSORS

J16_PROGPARTS

SMC:PROG,BOOTROM:PROG,T29ROM:PROG,CIVROM:PROG,CAMROM:PROG

J16,J16_COMMON,CPU:GOOD,SSD:Y,EEEE:FF3T

PCBA,MLB_IG,J16

639-4515

PCBA,MLB_IG,BETTER,J16

J16,J16_COMMON,CPU:BETTER,SSD:Y,EEEE:FGWY

639-4704

PCBA,MLB_IG,CTO,J16

J16,J16_COMMON,CPU:CTO,SSD:Y,EEEE:FGY0

639-4705

985-0052

DEVELOPMENT,J16_DEVEL

PCBA,MLB_IG,DEV,J16

MLB LABEL,2D

EEEE_FGWY

825-7896

1

CRITICAL

EEEE:FGWY

MLB LABEL,2D

825-7896

1

CRITICAL

EEEE_FGY0 EEEE:FGY0

COMMON,ALTERNATE,J16_COMMON1,J16_COMMON2,J16_PROGPARTS

J16_COMMON

XDP,SPEAKERID,TBTHV:P12V,CPUVCC:3PHASE

J16_COMMON1

J16_DEVEL

XDP_CONN,LPCPLUS,DDRVREF_DAC,DEVEL_SENSORS,DEVEL_AUDIO

AP_ISNS:N,HDD_IVSNS:NJ16_PRODUCTION

CRITICAL337S4483

U1100

1

LYNX POINT MOBILE,C1,QS,QE99,FCBGA695

338S1113 CRITICAL

IC,TBT,CR-4C,B1,PRQ,CIO,288 12X12 FC-CSP

U2800

1

343S0616 CRITICAL

U3900IC,BCM57766A,CIV+,A0,8X8

1

338S1159

IC,SMC12-A3,40MHZ/50MIPS,SCPL FW,157BGA

U5000

SMC:BLANK

CRITICAL

1

SMC:PROG

CRITICAL

U5000

IC,SMC,PROGRMD,V2.12A30,J16

341S3781

IC,SERIAL FLASH,2MBIT,2.7V,REV F

335S0862

CRITICAL

CIVROM:BLANK

1

U3990

1

341S3735

IC,ENET SPI ROM,NYMONYX,V1.13,D7/D7I

U3990

CRITICAL

CIVROM:PROG

IC,EEPROM,SERIAL,256KB,MLP8

335S0865

CRITICAL

T29ROM:BLANK

U2890

1

341S3734

IC,EEPROM,CR,V16.2,J16

U2890

CRITICAL

T29ROM:PROG

1

BOOTROM:BLANK

U5210

CRITICAL

335S0807

IC,64 MBIT SPI SERIAL FLASH

1

BOOTROM:PROG

CRITICAL

U5210

IC,EFI,V0039,J16

341S3783

IC,LP8561,LED BLKT CTLR,LLP24,B0-F

353S3908 CRITICAL

U8100

1

U4202

CAMROM:BLANK

1

335S0852

IC,FLASH,SPI,1MBIT,3V3

CRITICAL

1

341S3778

IC,CAMERA,FLASH,V7229,J16

U4202

CRITICAL

CAMROM:PROG

J16

1

SCH

CRITICAL

SCH,MLB_IG,J16

051-0164

EEEE:FF3TEEEE_FF3T

MLB LABEL,2D

825-7896

1

CRITICAL

J16

1

PCB

CRITICAL820-3588

PCBF,MLB_IG,J16

138S0638

ALL

Taiyo 10uf 805 alt

138S0681

120OHM EMI BEAD

ALL

155S0367155S0578

ALL

USB3 diodes

377S0104377S0155

SYNC_MASTER=J16_DINI SYNC_DATE=01/29/2013

BOM Configuration

J16_COMMON2

VDDQ:P1V35

ALL

376S0975

P/NCh dual FET

376S1081

ALL

377S0126

USB2 diodes

377S0147

25MHz Xtal

197S0480

ALL

197S0481

138S0775138S0860

ALL

Single-source 1uF 402

107S0251

ALL

Sense resistor

107S0249

102S0880

ALL

Sense resistor

102S0879

341S3747

U3990

Enet ROM341S3735

197S0479 197S0478 12 MHz Cam. Xtal

Y4200

ALL

128S0365

150UF AL POLY

128S0368

Enet magnetics

ALL

157S0058157S0084

377S0124

TVSALL

377S0057

ALL

138S0859 138S0788

Single-source 10uF

ALL

138S0706 138S0739

Single-source 1uF 201

051-0164

12.4.0

2 OF 123

2 OF 86

IN

G

D

S

IN

G

D

S

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

the southbridge that indicates

VIDEO ON Led

that chipset has enumerated graphics

This LED is a GPIO driven from

ALL_SYS_PWRGD Led

S5 Led

GPU GOOD Led

1/16W

5% MF-LF

1K

402

R0302

40

SILK_PART=2

2.0X1.25MM-SM

GREEN-3.6MCD

CRITICAL

LE0302

SOT-363

CRITICAL

2N7002DW-X-G

Q0302

5% MF-LF

1/16W 402

1K

R0304

21 44 69

SILK_PART=4

2.0X1.25MM-SM

GREEN-3.6MCD

CRITICAL

LE0304

1K

1/16W 402

MF-LF

5%

R0301

2.0X1.25MM-SM

GREEN-3.6MCD

SILK_PART=1

CRITICAL

LE0301

1K

5% 1/16W MF-LF 402

R0303

SILK_PART=3

2.0X1.25MM-SM

GREEN-3.6MCD

CRITICAL

LE0303

SOT-363

2N7002DW-X-G

CRITICAL

Q0302

14 18

DEBUG LEDS

SYNC_MASTER=J16_MAX

SYNC_DATE=02/11/2013

LCD_SHOULD_ON_R

GPU_GOOD

ALL_SYS_PWRGD

=PP3V3_S4_LED

CORE_VOLTAGES_ON_R

CORE_VOLTAGES_ON

=PP3V3_S0_LED

VIDEO_ON_L

=PP3V3_S0_LED

GPU_PRESENT_R

GPU_PRESENT_DRAIN

=PP3V3_S5_LED

ITS_PLUGGED_IN

051-0164

12.4.0

3 OF 123

3 OF 86

1

2

K

A

3

5

4

1

2

K

A

1

2

K

A

1

2

K

A

6

2

1

70

3

70

3

70

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

HEATSINK STABILITY MOUNTING FEATURES

CPU HEATSINK MOUNTING FEATURES

998-4559 (Plated holes, 4mm inner diameter, 8mm pad) 998-5089 (ZH0414) near BLC has slightly larger hole to allow for grommet

998-4560 (Plated holes, 2.3mm inner diameter, 4.3mm pad)

WIRELESS CARD MTG HOLES

SSD STANDOFF

Rear Cover

APN: 860-1624

(860-1532)

STDOFF-4.5OD2.2ID-6.5H-SM

CRITICAL

SSD:Y

NUT0413

7P0R4P0-8P0B-NSP

ZH0413

7P0R4P0-8P0B-NSP

ZH0415

7P0R4P0-8P0B-NSP

ZH0416

STDOFF-4.5OD.98H-1.1-3.40-TH

CRITICAL

SH0477

STDOFF-4.5OD.98H-1.1-3.40-TH

SH0479

CRITICAL

5P5R1P9-4P3B-NSP

ZH0421

5P5R1P9-4P3B-NSP

ZH0422

ZH0414

7P0R4P6-8P0B-NSP

CRITICAL

STDOFF-4.5OD.98H-1.1-3.40-TH

SH0473

STDOFF-4.5OD.98H-1.1-3.40-TH

CRITICAL

SH0474

CRITICAL

STDOFF-4.5OD.98H-1.1-3.40-TH

SH0475

SH0476

CRITICAL

STDOFF-4.5OD.98H-1.1-3.40-TH

Holes/PD parts

SYNC_DATE=02/11/2013

SYNC_MASTER=J16_MAX

051-0164

12.4.0

4 OF 123

4 OF 86

1

1 1

1

1 1

1

IN IN IN

IN

IN IN IN IN IN

OUT OUT OUT OUT OUT

OUT

OUT OUT OUT

OUT

OUT OUT OUT OUT

OUT

OUT OUT OUT OUT OUT

OUT

SYM 10 OF 12

EDP

DIGITAL DISPLAY INTERFACES

FDI

EDP_TXN0

DDIC_TXP2

FDI_TXP1

FDI_TXN1

FDI_TXP0

FDI_TXN0

EDP_DISP_UTIL

EDP_RCOMP

DDIB_TXN0

DDIC_TXN1

DDIC_TXP0

DDIC_TXN0

DDIB_TXN3

DDIB_TXP2

EDP_TXP1

EDP_TXP0

EDP_TXN1

EDP_AUXP

EDP_HPD

EDP_AUXN

DDID_TXP1

DDID_TXN1

DDID_TXP0

DDID_TXN0

DDID_TXP3

DDID_TXN3

DDID_TXP2

DDID_TXN2

DDIC_TXP1 DDIC_TXN2

DDIC_TXN3 DDIC_TXP3

DDIB_TXP0 DDIB_TXN1 DDIB_TXP1 DDIB_TXN2

DDIB_TXP3

RESERVED

SYM 12 OF 12

DAISY_CHAIN_NCTF

RSVD132 RSVD133 RSVD134 RSVD135 RSVD136 RSVD137 RSVD138 RSVD139

DAISY_CHAIN_NCTF

TP

NC NC NC NC NC NC NC NC

IN IN IN IN

IN

OUT

IN

SYM 1 OF 12

FDI

PCI EXPRESS BASED INTERFACE SIGNALS

DMI

PEG_TX15

PEG_TX14

PEG_TX13

PEG_TX12

PEG_TX11

PEG_TX10

PEG_TX9

PEG_TX8

PEG_TX7

PEG_TX6

PEG_TX5

PEG_TX4

PEG_TX3

PEG_TX2

PEG_TX1

PEG_TX0

PEG_RX15*

PEG_RX14*

PEG_RX13*

PEG_RX12*

PEG_RX11*

PEG_RX10*

PEG_RX9*

PEG_RX8*

PEG_RX7*

PEG_RX6*

PEG_RX5*

PEG_RX4*

PEG_RX3*

PEG_RX2*

PEG_RX1*

PEG_RX0*

PEG_TX15*

PEG_TX14*

PEG_TX13*

PEG_TX12*

PEG_TX11*

PEG_TX10*

PEG_TX9*

PEG_TX8*

PEG_TX7*

PEG_TX6*

PEG_TX5*

PEG_TX4*

PEG_TX3*

PEG_TX2*

PEG_TX1*

PEG_TX0*

PEG_RCOMP

DISP_INT

FDI_CSYNC

PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8

PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15

DMI_RX0* DMI_RX1* DMI_RX2* DMI_RX3*

DMI_RX0

DMI_RX2 DMI_RX3

DMI_TX0* DMI_TX1* DMI_TX2* DMI_TX3*

DMI_TX0 DMI_TX1 DMI_TX2 DMI_TX3

DMI_RX1

IN IN IN

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

exist between both TP’s on each corner.

daisy-chain fashion. Continuity should

Each corner of CPU has two testpoints. Other corner test signals connected in

to match Intel symbol.

Port D pins out of order

NO_TEST NO_TEST

CPU Daisy-Chain Strategy:

72

BGA

OMIT_TABLE

HASWELL

U0500

24.9

402

MF-LF

1/16W

1%

R0530

402

MF-LF

1/16W

5%

10k

R0531

BGA

OMIT_TABLE

HASWELL

U0500

TP-P6

TP0500

TP-P6

TP0501

TP-P6

TP0511

TP-P6

TP0531

TP-P6

TP0510

TP-P6

TP0520

TP-P6

TP0530

TP-P6

TP0521

12 77

24.9

1%

MF-LF

1/16W

402

R0510

12 78

BGA

OMIT_TABLE

HASWELL

U0500

72

SYNC_DATE=01/14/2013SYNC_MASTER=J16_DINI

CPU DMI/PEG/FDI/RSVD

CPU_DC_BC1

CPU_DC_BF4

CPU_DC_A51

CPU_DC_D54

CPU_DC_D1

DP_IG_A_HPD_L

=PEG_R2D_C_N<12>

TP_DP_IG_D_MLN<0>

TP_DP_IG_D_MLP<1>

=PEG_D2R_P<13>

=PEG_D2R_P<8>

=PEG_D2R_P<5>

=PEG_D2R_P<3>

TP_DP_IG_A_AUXCHP

TP_DP_IG_B_MLP<3>

TP_DP_IG_B_MLN<2>

TP_DP_IG_B_MLP<1>

TP_DP_IG_B_MLN<1>

TP_DP_IG_C_MLP<3>

TP_DP_IG_C_MLN<3>

TP_DP_IG_C_MLN<2>

TP_DP_IG_C_MLP<1>

TP_DP_IG_D_MLN<2> TP_DP_IG_D_MLP<2> TP_DP_IG_D_MLN<3>

TP_DP_IG_D_MLP<0> TP_DP_IG_D_MLN<1>

TP_DP_IG_A_MLN<1>

TP_DP_IG_A_MLP<0>

TP_DP_IG_B_MLP<2> TP_DP_IG_B_MLN<3>

TP_DP_IG_C_MLN<0> TP_DP_IG_C_MLP<0> TP_DP_IG_C_MLN<1>

TP_DP_IG_B_MLN<0>

TP_EDP_DISP_UTIL

TP_DP_IG_C_MLP<2>

TP_DP_IG_A_MLN<0>

=PEG_D2R_N<4>

DMI_N2S_P<2>

DMI_N2S_P<0>

=PEG_D2R_P<1>

=PEG_R2D_C_P<5>

DMI_S2N_P<3>

DMI_S2N_N<1>

DMI_S2N_N<3>

DMI_S2N_P<0> DMI_S2N_P<1>

=PEG_D2R_N<1>

=PEG_D2R_N<3>

=PEG_D2R_N<8>

=PEG_D2R_N<11>

=PEG_D2R_N<10>

=PEG_D2R_N<12>

=PEG_D2R_N<14> =PEG_D2R_N<15>

=PEG_D2R_P<0>

=PEG_D2R_P<2>

=PEG_D2R_P<4>

=PEG_D2R_P<6> =PEG_D2R_P<7>

=PEG_D2R_P<10>

=PEG_D2R_P<9>

=PEG_D2R_P<11> =PEG_D2R_P<12>

=PEG_D2R_P<15>

=PEG_D2R_P<14>

=PEG_R2D_C_N<1> =PEG_R2D_C_N<2> =PEG_R2D_C_N<3> =PEG_R2D_C_N<4> =PEG_R2D_C_N<5> =PEG_R2D_C_N<6> =PEG_R2D_C_N<7>

=PEG_R2D_C_N<9>

=PEG_R2D_C_N<8>

=PEG_R2D_C_N<10> =PEG_R2D_C_N<11>

=PEG_R2D_C_N<13> =PEG_R2D_C_N<14> =PEG_R2D_C_N<15>

=PEG_R2D_C_P<2>

=PEG_R2D_C_P<1>

=PEG_R2D_C_P<3> =PEG_R2D_C_P<4>

=PEG_R2D_C_P<6> =PEG_R2D_C_P<7> =PEG_R2D_C_P<8>

=PEG_R2D_C_P<10> =PEG_R2D_C_P<11> =PEG_R2D_C_P<12> =PEG_R2D_C_P<13> =PEG_R2D_C_P<14> =PEG_R2D_C_P<15>

FDI_CSYNC

FDI_INT

DMI_S2N_N<2>

=PEG_D2R_N<9>

=PEG_D2R_N<0>

DMI_S2N_P<2>

DMI_N2S_P<3>

DMI_N2S_N<1>

DMI_N2S_N<0>

DMI_N2S_N<3>

DMI_N2S_P<1>

DMI_N2S_N<2>

=PEG_R2D_C_N<0>

=PEG_R2D_C_P<0>

CPU_PEG_RCOMP

=PEG_R2D_C_P<9>

=PEG_D2R_N<5> =PEG_D2R_N<6>

PPVCOMP_S0_CPU

TP_DP_IG_A_AUXCHN

PPVCCIO_S0_CPU

TP_DP_IG_D_MLP<3>

CPU_EDP_RCOMP

=PEG_D2R_N<7>

=PEG_D2R_N<13>

DMI_S2N_N<0>

CPU_DC_BF51

CPU_DC_BC54

TP_DP_IG_A_MLP<1>

PPVCOMP_S0_CPU

TP_DP_IG_B_MLP<0>

CPU_DC_A4

=PEG_D2R_N<2>

TP_DP_IG_A_MLN<2> TP_DP_IG_A_MLP<2> TP_DP_IG_A_MLN<3> TP_DP_IG_A_MLP<3>

TRUE

CPU_DC_BE53_BF53

CPU_DC_A3_B3

TRUE

CPU_DC_A3_B3

CPU_DC_B54_C54

TRUE

CPU_DC_A53_B53

TRUE

CPU_DC_A52_B52

TRUE

CPU_DC_B2_C3

TRUE

CPU_DC_A53_B53

TRUE

CPU_DC_A52_B52

TRUE

CPU_DC_BE3_BF3

TRUE

CPU_DC_BE2_BF2

TRUE

CPU_DC_BD54_BE54

TRUE

CPU_DC_BE2_BF2

TRUE

CPU_DC_BD1_BE1

TRUE

CPU_DC_BD54_BE54

TRUE

CPU_DC_BD1_BE1

TRUE

CPU_DC_B54_C54

CPU_DC_BE52_BF52

TRUE

CPU_DC_C1_C2

TRUE

CPU_DC_C1_C2

TRUE

CPU_DC_B2_C3

TRUE

CPU_DC_BE52_BF52

TRUE

CPU_DC_BE3_BF3

TRUE

CPU_DC_BE53_BF53

5 OF 86

5 OF 123

12.4.0

051-0164

C14

D20

B14

A14

D12

C12

E12

AG6

C25

A21

D21

C21

A24

D24

B12

D14

A12

F14

E14

F15

B17

A17

D17

C17

B16

A16

D16

C16

B21

C20

A20

B20

D25

A25

B25 C24

B24

1

2

1

2

BF4

BF3

BF2

C2

C3

C54

D1

D54

A3 A4

A51 A52

A53

BE52 BE53

BE54

BF52

BF53

C1

AN35 AN37

AF9 AE9

G14

G17 AD45

AG45

BF51

BE1

BD54

B2

B3

B52

B53 B54

BC54

BE2 BE3

BD1

BC1

1

2

T2

T3

R3

R1

R5

T5

J1

J4

G2

J6

E2

G5

E4

D6

B5

C6

Y2

Y3

V1

V4

V5

M2

L4

M4

L2

L5

B9

D9

E9

B10

C10

E10

T1

T4

R4

R2

R6

T6

J2

J3

G3

J5

E3

G4

D4

E6

C5

B6

AH6

F12

F11

F10 D10

A10

F9 C9

A9

M5 L1

M3

L3 M1

Y5 V3

V2

Y4 Y1

AB2 AB3

AC3

AC1

AB1

AC4

AC2

AF2

AF4 AG4

AG2

AF1

AF3

AG3 AG1

AB4

71

72

71

72

71

72

76

5 8

72

6 8

10 18 61

71

76

72

5 8

71

72

5

5 5

5

BI BI BI BI BI

IN

OUT

BI

NC

OUT

BI

SYM 2 OF 12

CLOCK

JTAG

PWR

DDR3

THERMAL

THERMTRIP*

PM_SYNC

PWRGOOD

SM_DRAMPWROK

PLTRSTIN*

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

SM_DRAMRST*

PRDY* PREQ*

TCK TMS

TRST*

TDI TDO

DBR*

BPM0* BPM1*

BPM3*

BPM2*

BPM4* BPM5* BPM6* BPM7*

PECI

PROC_DETECT*

PROCHOT*

CATERR*

DPLL_REF_CLKN DPLL_REF_CLKP

BCLKN BCLKP

SSC_DPLL_REF_CLKN SSC_DPLL_REF_CLKP

OUT

IN IN

SYM 11 OF 12

RESERVED

RSVD_TP28

RSVD_TP27

RSVD_TP39

RSVD_TP38

RSVD11

RSVD_TP1 RSVD_TP2

RSVD51 RSVD52

RSVD50

RSVD16

RSVD42

RSVD41

RSVD10

RSVD9

RSVD95

RSVD94

RSVD93

RSVD92

CFG_RCOMP

CFG16

CFG19

CFG18 CFG17

VSS_H54

VSS_H52

VSS_H51

VSS_H53

VCC_F22

VSS_G19

VSS_F52

VSS_F51

TESTLO_F21

CFG0 CFG1

CFG6

CFG5

CFG2 CFG3 CFG4

TESTLO_F20

CFG11

CFG10

CFG9

CFG8

CFG7

CFG12

CFG14

CFG13

CFG15

RSVD_TP17 RSVD_TP18

RSVD_TP37

RSVD_TP36

RSVD_TP35

RSVD_TP23

RSVD_TP3 RSVD_TP4

RSVD47 RSVD48 RSVD49

RSVD_TP26

RSVD_TP25

RSVD_TP24

NC

IN

OUT

IN IN

IN

OUT

IN

OUT

BI BI BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

CFG [4] :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED

(IPU)

(IPD)

(IPU)

(IPU) (IPU)

(IPU)

(IPU) (IPU)

(IPU)

CFG [2] :PCIE x16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

CFG [6:5] :PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4

CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS

J1800 and only for debug access

These can be placed close to

CFG [3] :PCIE x4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

NOTE: Pre-ES2 CPUs have issue with Sx cycling, must set CFG<9> low to avoid issue, but this locks CPU VR at 1.7V Vboot (CPU Sighting #4391569).

(IPU)

18 78

PLACE_NEAR=U0500.F50:157mm

402

MF-LF

1/16W

5%

10K

R0611

12 21

14 18 76

14 45 76

14 44 45 76

PLACE_NEAR=U0500.BB52:12.7mm

100

1% 1/16W MF-LF 402

R0614

75

1% 1/16W MF-LF 402

PLACE_NEAR=U0500.BB53:12.7mm

R0613

100

1% 1/16W MF-LF 402

PLACE_NEAR=U0500.BB51:12.7mm

R0612

45 76

5% 1/16W MF-LF

402

62

R0601

402

1/16W MF-LF

5%

56

R0603

44 45 61 62 76

BGA

OMIT_TABLE

HASWELL

U0500

21

11 77

BGA

HASWELL

OMIT_TABLE

U0500

MF-LF 402

1/16W

1%

49.9

R0690

49.9

1% 1/16W MF-LF

402

R0680

49.9

1% 1/16W MF-LF

402

R0685

402

MF-LF

5%

1K

NOSTUFF

1/16W

R0649

1K

NOSTUFF

5% 1/16W

402

MF-LF

R0643

402

MF-LF

1/16W

5%

1K

NOSTUFF

R0641

402

MF-LF

1/16W

5%

1K

NOSTUFF

R0640

NOSTUFF

1K

5% 1/16W MF-LF

402

R0647

1K

5% 1/16W MF-LF

402

CPUCFG6_PD

R0646

1K

5% 1/16W MF-LF 402

CPUCFG5_PD

R0645

402

MF-LF

1/16W

5%

EDP:YES

1K

R0644

402

MF-LF

1/16W

5%

1K

NOSTUFF

R0642

3.32K

402

MF-LF

1/16W

1%

PLACE_NEAR=U0500.AP48:51.562mm

R0621

1K

5% 1/16W MF-LF

402

HSW_PRE_ES2

R0648

18

18 78

18

1.82K

PLACE_NEAR=R0621.2:1mm

1% 1/16W MF-LF

402

R0620

12 76

14 18 76

18 19

18 76

18 78

CPUPEG:X8X4X4

CPUCFG6_PD,CPUCFG5_PD

CPUPEG:X8X8

CPUCFG5_PD

CPUPEG:X16

SYNC_MASTER=J16_DINI SYNC_DATE=01/14/2013

CPU Clock/Misc/JTAG/CFG

XDP_BPM_L<7>

CPU_SM_RCOMP<2>

=MEM_RESET_L

XDP_CPU_PREQ_L

XDP_CPU_TCK

PM_THRMTRIP_L

CPU_PROCHOT_R_L

CPU_CATERR_L

TP_CPU_RSVD_TP2

CPU_PECI

CPU_PROCHOT_L

PM_MEM_PWRGD

PPVCCIO_S0_CPU

=PP1V5_S3_CPU_VCCDDR

DMI_CLK100M_CPU_P

DMI_CLK100M_CPU_N

CPU_CLK135M_DPLLSS_P

CPU_CLK135M_DPLLSS_N

CPU_CLK135M_DPLLREF_P

CPU_CLK135M_DPLLREF_N

CPU_RESET_L

PM_SYNC

CPU_PWRGD

CPU_CFG<3>

CPU_CFG<9>

CPU_CFG<1> CPU_CFG<0>

CPU_SM_RCOMP<0> CPU_SM_RCOMP<1>

CPU_CFG<6>

=PPVCC_S0_CPU

TP_CPU_RSVD_TP37

TP_CPU_RSVD_TP49

TP_CPU_RSVD_TP48

TP_CPU_RSVD_TP1

TP_CPU_RSVD_TP4

TP_CPU_RSVD_TP36

CPU_CFG<15>

CPU_CFG<13> CPU_CFG<14>

CPU_CFG<12>

CPU_CFG<11>

CPU_CFG<8>

CPU_CFG<7>

CPU_CFG<6>

CPU_CFG<5>

CPU_CFG<2>

CPU_CFG<1>

CPU_CFG<4>

TP_CPU_RSVD_TP35

TP_CPU_RSVD_TP24

XDP_CPU_TRST_L

XDP_CPU_TDI XDP_CPU_TDO

XDP_BPM_L<6>

XDP_BPM_L<5>

XDP_BPM_L<4>

XDP_BPM_L<2> XDP_BPM_L<3>

XDP_BPM_L<1>

XDP_BPM_L<0>

XDP_DBRESET_L

XDP_CPU_TMS

XDP_CPU_PRDY_L

CPU_CFG<3>

CPU_CFG<17>

CPU_CFG<16>

CPU_CFG<2>

CPU_CFG<7>

CPU_CFG<10>

CPU_CFG<9>

CPU_CFG<4>

CPU_CFG<5>

CPU_CFG_RCOMP

TP_CPU_RSVD_TP3

TP_CPU_RSVD_TP23

TP_CPU_RSVD_TP47

CPU_TESTLO_F21

TP_CPU_RSVD_TP18

CPU_CFG<0>

CPU_TESTLO_F20

CPU_CFG<19>

TP_CPU_RSVD_TP27 TP_CPU_RSVD_TP28

TP_CPU_RSVD_TP26

TP_CPU_RSVD_TP25

TP_CPU_RSVD_TP38 TP_CPU_RSVD_TP39

CPU_CFG<18>

TP_CPU_RSVD_TP17

CPU_CFG<16>

051-0164

12.4.0

6 OF 123

6 OF 86

1

2

1

2

1

2

1

2

1

2

12

D53

D52

F50

AP48

L54

BB51 BB53

BB52

BE51

N53

N52

N54

M51 M53

N49

M49

F53

R51 R50

N50

P49

R49

P53 U51

P51

G51

C51

E50

G50

AC6

AE6

AB6 AA6

V6

Y6

G24

G21

F25

F24

BC4

F1

E1

L49

E5

L50

F16

F8

AL6

BD4

AU26

AU27

AM48

AH49

B50

R54

Y52

V52

V53 Y51

H54

H52

H51

H53

F22

G19

F52

F51

F21

AG49

AD49

V51

AB49

AC49

AE49

Y50

F20

W53

Y53

Y54

Y49

W51

U53

R53

V54

R52

G12

G10

L51

L53

L52

BE4

A5

A6

N51 G53

H50

G6

F6

BD3

1

2

1

2

1

2

1

2

1

2

121

2

1

2

121

2

121

2

1

2

1

2

1

2

75

76

5 8

10 18 61

70

6

18 78

6

18 78

6

18 78

6

18 78

75

6

18 78

8

10 70

18 72 78

18 78

6

18 78

6

18 78

6

18 78

6

18 78

6

18 78

6

18 78

6

18 78

6

18 78

6

18 78

6

18 78

6

18 78

6

18 78

6

18 78

76

6

18 78

18

6

18 78

OUT

NC

NC NC

NC

NC NC NC

NC

NC NC

BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

OUT OUT

OUT OUT OUT

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

SYM 3 OF 12

MEMORY CHANNEL A

SA_DQ12

SA_DQ11

SA_DQ8

SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24

SA_CKP3

SA_CKN3

SA_CKP2

SA_CKP1

SA_CKN1

SA_CKP0

SA_CKN0

SA_CKE1

SA_CS1*

SA_DQ20

SM_VREF

SA_DQSN7

SA_DQSN6

SA_DQSN5

SA_DQSN4

SA_DQSN3

SA_DQSN2

SA_DQSN1

SA_DQSN0

SA_DQS7

SA_DQS6

SA_DQS4 SA_DQS5

SA_DQS3

SA_DQS2

SA_DQS1

SA_DQS0

SA_MA13

SA_MA12

SA_MA11

SA_MA9

SA_MA8

SA_MA7

SA_MA5 SA_MA6

SA_MA4

SA_MA2 SA_MA3

SA_MA0 SA_MA1

SA_CAS*

SA_WE*

VSS_BC21

SA_RAS*

SA_BS1 SA_BS2

SA_ODT3

SA_BS0

SA_ODT2

SA_ODT1

SA_ODT0

SA_CS3*

SA_CS2*

SA_CS0*

SA_CKE3

SA_CKE2

SA_CKE0

SA_DQ30

SA_DQ0 SA_DQ1 SA_DQ2

SA_DQ9

SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19

SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29

SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44

SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58

SA_DQ61 SA_DQ62 SA_DQ63

SA_DQ4

SA_DQ3

SA_DQ10

SA_DQ7

SA_DQ5 SA_DQ6

SA_DQ47

SA_DQ46

SA_DQ45

SB_DIMM_VREFDQ

SA_DIMM_VREFDQ

RSVD25

RSVD162

RSVD165

RSVD168

SA_CKN2

SA_MA10

SA_MA14 SA_MA15

RSVD170

RSVD169

RSVD167

RSVD166

RSVD164

RSVD163

SA_DQ59 SA_DQ60

RSVD161

RSVD160

SYM 4 OF 12

MEMORY CHANNEL B

SB_DQ29

SB_DQ28

RSVD171

SB_CKN0

SB_CKE0

RSVD181

RSVD180

RSVD179

RSVD178

RSVD177

RSVD176

RSVD175

RSVD174

RSVD173

RSVD172

SB_DQSN3

SB_DQSN6

SB_DQS0 SB_DQS1

SB_DQS5

SB_DQS3 SB_DQS4

SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35

SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7

SB_CKE1 SB_DQ8 SB_DQ9 SB_DQ10

SB_CKE2 SB_DQ11

SB_DQ12 SB_DQ13 SB_DQ14 SB_CKE3 SB_DQ15 SB_DQ16 SB_CS0* SB_DQ17 SB_CS1* SB_DQ18 SB_CS2* SB_DQ19 SB_CS3* SB_DQ20

SB_ODT0 SB_DQ21

SB_ODT1 SB_DQ22

SB_ODT2 SB_DQ23

SB_ODT3 SB_DQ24

SB_DQ25

SB_BS0

SB_DQ26

SB_BS1

SB_DQ27

SB_DQ30

SB_RAS*

SB_WE*

SB_CAS*

SB_MA0 SB_MA1

SB_DQ36

SB_MA2

SB_DQ37

SB_MA3

SB_DQ38

SB_MA4

SB_DQ39

SB_MA5

SB_DQ40

SB_MA6

SB_DQ41

SB_MA7

SB_DQ42

SB_MA8

SB_DQ43

SB_MA9

SB_DQ44

SB_MA10 SB_DQ45

SB_MA11 SB_DQ46

SB_MA12 SB_DQ47

SB_MA13 SB_DQ48

SB_MA14 SB_DQ49

SB_MA15 SB_DQ50

SB_DQ51

SB_DQSN0

SB_DQ52

SB_DQSN1

SB_DQ53

SB_DQSN2

SB_DQ54 SB_DQ55

SB_DQSN4

SB_DQ56

SB_DQSN5

SB_DQ57 SB_DQ58

SB_DQSN7

SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

SB_DQS2

SB_DQS6

SB_DQS7

SB_CKP0

SB_CKN1

SB_CKP1

SB_CKN2

SB_CKP2

SB_CKN3

SB_CKP3

SB_BS2

VSS_AU30

BI

OUT

OUT OUT OUT

OUT

OUT OUT OUT

OUT

OUT OUT

OUT

OUT OUT

OUT

OUT OUT OUT OUT

OUT

OUT OUT OUT

BI

BI BI

BI

BI BI

NC

NC NC

NC NC NC

NC

NC NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

22

25 75

23 75

HASWELL

BGA

OMIT_TABLE

U0500

OMIT_TABLE

HASWELL

BGA

U0500

25 75

23 75

24 75

25 75

SYNC_DATE=01/14/2013SYNC_MASTER=J16_DINI

CPU DDR3 Interfaces

MEM_A_DQ<23>

MEM_A_DQ<22>

MEM_B_DQ<18>

MEM_B_DQ<16>

CPU_DIMM_VREFCA

MEM_B_DQS_P<6> MEM_B_DQS_P<7>

MEM_A_DQ<57> MEM_A_DQ<58> MEM_A_DQ<59>

MEM_B_DQ<52>

CPU_DIMMA_VREFDQ

CPU_DIMMB_VREFDQ

MEM_A_DQ<14>

MEM_A_DQ<17>

MEM_A_DQS_P<0> MEM_A_DQS_P<1> MEM_A_DQS_P<2> MEM_A_DQS_P<3> MEM_A_DQS_P<4> MEM_A_DQS_P<5>

MEM_A_DQS_P<7>

MEM_A_DQS_P<6>

MEM_A_DQS_N<0> MEM_A_DQS_N<1> MEM_A_DQS_N<2> MEM_A_DQS_N<3> MEM_A_DQS_N<4>

MEM_A_DQS_N<6>

MEM_A_DQS_N<5>

MEM_A_DQS_N<7>

MEM_B_DQS_P<0> MEM_B_DQS_P<1> MEM_B_DQS_P<2> MEM_B_DQS_P<3> MEM_B_DQS_P<4> MEM_B_DQS_P<5>

MEM_B_DQS_N<1>

MEM_B_DQS_N<3> MEM_B_DQS_N<4> MEM_B_DQS_N<5> MEM_B_DQS_N<6> MEM_B_DQS_N<7>

MEM_A_A<15>

MEM_A_A<14>

MEM_A_A<13>

MEM_A_A<12>

MEM_A_A<11>

MEM_A_A<10>

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<7>

MEM_A_A<6>

MEM_A_A<5>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_A<2>

MEM_A_A<1>

MEM_A_A<0>

MEM_A_CAS_L

MEM_A_WE_L

MEM_A_RAS_L

MEM_A_BA<2>

MEM_A_BA<1>

MEM_A_BA<0>

MEM_A_ODT<1>

MEM_A_ODT<0>

MEM_A_CS_L<0>

MEM_A_CKE<1>

MEM_A_CLK_P<1>

MEM_A_CLK_N<1>

MEM_B_A<15>

MEM_B_A<14>

MEM_B_A<13>

MEM_B_A<11>

MEM_B_A<10>

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<7>

MEM_B_A<3>

MEM_B_A<2>

MEM_B_A<1>

MEM_B_A<0>

MEM_B_CAS_L

MEM_B_WE_L

MEM_B_RAS_L

MEM_B_ODT<1>

MEM_B_ODT<0>

MEM_B_CS_L<0>

MEM_B_CKE<1>

MEM_B_CLK_P<1>

MEM_B_CLK_N<1>

MEM_B_CKE<0>

MEM_B_CLK_P<0>

MEM_B_CLK_N<0>

MEM_A_DQ<60>

MEM_B_DQ<62> MEM_B_DQ<63>

MEM_B_DQ<61>

MEM_B_DQ<56> MEM_B_DQ<57> MEM_B_DQ<58> MEM_B_DQ<59> MEM_B_DQ<60>

MEM_B_DQ<51>

MEM_B_DQ<53> MEM_B_DQ<54> MEM_B_DQ<55>

MEM_B_DQ<46> MEM_B_DQ<47> MEM_B_DQ<48> MEM_B_DQ<49> MEM_B_DQ<50>

MEM_B_DQ<41> MEM_B_DQ<42> MEM_B_DQ<43> MEM_B_DQ<44> MEM_B_DQ<45>

MEM_B_DQ<36> MEM_B_DQ<37> MEM_B_DQ<38> MEM_B_DQ<39> MEM_B_DQ<40>

MEM_B_DQ<31> MEM_B_DQ<32> MEM_B_DQ<33> MEM_B_DQ<34> MEM_B_DQ<35>

MEM_B_DQ<26> MEM_B_DQ<27> MEM_B_DQ<28> MEM_B_DQ<29> MEM_B_DQ<30>

MEM_B_DQ<25>

MEM_B_DQ<21> MEM_B_DQ<22> MEM_B_DQ<23> MEM_B_DQ<24>

MEM_B_DQ<20>

MEM_B_DQ<15>

MEM_B_DQ<17>

MEM_B_DQ<19>

MEM_B_DQ<10> MEM_B_DQ<11> MEM_B_DQ<12> MEM_B_DQ<13> MEM_B_DQ<14>

MEM_B_DQ<5> MEM_B_DQ<6>

MEM_B_DQ<8>

MEM_B_DQ<0>

MEM_B_DQ<2>

MEM_B_DQ<4>

MEM_A_DQ<62> MEM_A_DQ<63>

MEM_A_DQ<61>

MEM_A_DQ<56>

MEM_A_DQ<55>

MEM_A_DQ<52>

MEM_A_DQ<50>

MEM_A_DQ<49>

MEM_A_DQ<48>

MEM_A_DQ<47>

MEM_A_DQ<46>

MEM_A_DQ<44>

MEM_A_DQ<43>

MEM_A_DQ<42>

MEM_A_DQ<41>

MEM_A_DQ<40>

MEM_A_DQ<39>

MEM_A_DQ<38>

MEM_A_DQ<36> MEM_A_DQ<37>

MEM_A_DQ<35>

MEM_A_DQ<34>

MEM_A_DQ<33>

MEM_A_DQ<31> MEM_A_DQ<32>

MEM_A_DQ<30>

MEM_A_DQ<29>

MEM_A_DQ<28>

MEM_A_DQ<26> MEM_A_DQ<27>

MEM_A_DQ<25>

MEM_A_DQ<24>

MEM_A_DQ<21>

MEM_A_DQ<20>

MEM_A_DQ<19>

MEM_A_DQ<18>

MEM_A_DQ<16>

MEM_A_DQ<15>

MEM_A_DQ<13>

MEM_A_DQ<12>

MEM_A_DQ<11>

MEM_A_DQ<9>

MEM_A_DQ<8>

MEM_A_DQ<7>

MEM_A_DQ<6>

MEM_A_DQ<5>

MEM_A_DQ<4>

MEM_A_DQ<1>

MEM_A_DQ<0>

MEM_A_DQ<53>

MEM_A_DQ<51>

MEM_A_DQ<54>

MEM_A_DQ<45>

MEM_A_CS_L<1>

MEM_A_DQ<3>

MEM_A_DQ<2>

MEM_B_BA<2>

MEM_B_DQ<9>

MEM_B_DQ<7>

MEM_B_DQ<3>

MEM_B_DQ<1>

MEM_B_DQS_N<0>

MEM_B_DQS_N<2>

MEM_A_DQ<10>

MEM_A_CKE<0>

MEM_A_CLK_P<0>

MEM_A_CLK_N<0>

MEM_B_CS_L<1>

MEM_B_BA<1>

MEM_B_BA<0>

MEM_B_A<4> MEM_B_A<5> MEM_B_A<6>

MEM_B_A<12>

051-0164

12.4.0

7 OF 123

7 OF 867 OF 86

7 OF 123

12.4.0

051-0164

AN53

AR53

AN54

AV54

AY54 AY53

AY47

BC23

BD23

BF23

BC25

BD25

BF25

BE25

BF34

BC17

AV51

AM6

AT2

BA3

BE7

BD12

AY46

AW52

AP53

AJ52

AT3

BA2

BE12 BD7

BA46

AW53

AP52

AJ53

BE20

BC31

BF31

BC32

BE27

BC28

BC27

BF27

BF32

BF28

BE28

BD28 BD27

BE21

BF21

BC21

BF20

BD21

BD32

BD17

BC20

BF17

BF16

BC16

BD16

BE17

BE16

BD34

BC34

BE34

BA49

AH54 AH52

AK51

AN52

AN51

AR52 AR54

AV52

AV53 AY52

AY51

AY49 BA47

BA45

AY45 AY43

BA43 BF14

BC14 BC11

BF11

BE14 BD14

BD11

BE11

BC9

BE9

BE6 BC6

BD9

BB4

BC2

AW3 AW2

BB3

BB2 AW4

AW1 AU3

AU1

AR1

AU4 AR2

AR3

AH53

AK54

AR51

AK53

AH51

AK52

BD6

BE5

BF9

AN6

AR6

BC53

AW40

BA39

AU40

BE23

BD20

BE32 BE31

AU39

AV39

AV40

AY39

AY40

BA40

AR4

AU2

AW39

BD31

BC44

BF44

AY36

AW27

AU36

BD37

BC37

BC39

BD39

BE37

BF37

BE39

BF39

BD38

BE38

BD43

AW8

AD53

AV46

AW12

BE43

AW15

BE42 BA16

AU16 BA15

AV15

AC54 AC52

AE51

AE54 AC53

AC51

AE52 AE53 AU35

AU47

AU49 AV43

AV35

AV45 AU43

AU45

AV47 AV36 AV49

BC49 BA20

BE49 AY19 BD47 AU19

BC47 AW20

BD49

AY20

BD50

BA19

BE47

AV19

BF47

AW19

BE44

BD44 AY23 BC42 BA23

BF42

BD42

AV23

AW23

AV20

BA30 AW30

AY16

AY30

AV16

AV30

AY15

AW32

AU15

AY32

AU12

AT30

AY12

AV32

BA10

BA32

AU10

AU32

AV12

AU23

BA12

AY35

AY10

AW35

AV10

AU20

AU8

AW36

BA8

BA35

AV6 BA6

AD52

AV8

AU46

AY8

BD48

AU6

AY6

AW16

AM2

AW10

AM3

AK1

AL2

AK4

AM1

AM4 AK2

AK3

BE48

AW6 AL3

AV27

AW26

AV26

BA26

AY26

BA27

AY27

BA36

AU30

BI

OUT

IN

SYM 5 OF 12

RSVD68

VIDSOUT

VIDSCLK

VIDALERT*

RSVD79(VSS)

RSVD78 VSS_V50(RSVD)

VSS_AP50(RSVD)

VSS_AP49(RSVD)

VSS_AN49(RSVD)

VSS_AM50(RSVD)

IVR_ERROR

VSS_AK49(RSVD)

VSS_AJ49(RSVD)

VSS_AJ50(RSVD)

VSS_AG50(RSVD)

VSS_AD50(RSVD)

VSS_AB50(RSVD)

FC_F17

RSVD65

RSVD69

RSVD67

RSVD66

RSVD74

RSVD73

RSVD72

RSVD71

RSVD70

VCC_L6 VCC_M6

VCOMP_OUT

VCC_SENSE

VSS_B51

FC_D5 FC_D3

VDDQ

VCC

VCCIO_OUT

RSVD76

RSVD75

VSS_E52

PWR_DEBUG

RSVD64

SYM 6 OF 12

POWER

VCC VCC

IN

OUT

NC NC NC NC

NC NC

NC NC NC NC

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Max load: 300mA

Connections would be required for 2014 CPU support.

R0802.2:

R0800.2:

R0810.2:

Max load: 300mA

NOTE: Aliases not used on CPU supply outputs to avoid any extraneous connections.

R0812

0

5% 1/16W MF-LF

402

61 83

R0802

110

PLACE_NEAR=U0500.J50:2.54mm

402

1/16W

1%

MF-LF

R0811

0

402

5%

MF-LF

1/16W

61 83

R0810

PLACE_NEAR=U0500.J53:38mm

5%

402

MF-LF

1/16W

43

61 83

R0800

PLACE_NEAR=R0810.1:2.54mm

75

1% 1/16W MF-LF

402

U0500

OMIT_TABLE

HASWELL

BGA

U0500

OMIT_TABLE

HASWELL

BGA

18

R0860

PLACE_NEAR=U0500.C50:50.8mm

PLACE_SIDE=BOTTOM

100

1/16W MF-LF

402

5%

61 83

CPU Power

SYNC_DATE=01/14/2013SYNC_MASTER=J16_DINI

PPVCCIO_S0_CPU

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

PPVCOMP_S0_CPU

CPU_VIDSCLK

CPU_VIDSCLK_R

=PPVCC_S0_CPU

CPU_VCCSENSE_P

TP_CPU_RSVD_TP78

TP_CPU_RSVD_TP76

TP_CPU_RSVD_TP75

=PPVCC_S0_CPU

=PP1V5R1V35_S0_CPU

CPU_PWR_DEBUG

CPU_VIDSOUT

TP_CPU_FC_VCCST_PWRGD

TP_CPU_FC_VCCST

CPU_VIDALERT_L

TP_CPU_IVR_ERROR

CPU_VIDALERT_R_L

CPU_VIDSOUT_R

12.4.0

8 OF 123

8 OF 86

051-0164

1 2

1

2

1 2

1

2

AN31

BE33

BE30

BE26

BE22

BD26

J50

J52

J53

J12

W49

V50

AP50

AP49

AN49

AM50

AM49

AK49

AJ49

AJ50

AG50

AD50

AB50

F17

F31

E39

J21

AN22

J31

J26

AR49

W9

AN33

AH9

AN18

L6 M6

AK6

C50

B51

BE18

BD33

BD30

BD22

BB36

BB34

BB31

BB30

BB27

BB26

BB22

BB21

AY18

AW29

AW25

AW22

AV37

AT36

AT32

AT27

AT23

AT19

AT13

AR33

AR31

D5

D3

AR29

A36 A38

A39

A42 A43

AA47

AA8

AA9

AW33

B43

B45 B46

B48 C27

C28

C31 C32

C34

C36 C38

C39

C42 C43

C45 C46

C48

D27 D28

D31

D32 D34

D36

D38 D39

D42 D43

D45

D46 D48

E27

E28 E31

E32

E34 E36

E38

E42

E43 E45

E48 F27

F28

F32

F34 F36

F38

F39 F42

F43

F45 F46

F48

G27 G29

G31 G32

G34

G38

G39

G42 G43

G45

G46 G48

H11 H12

H13

H14 H16

H17

H18 H19

H20

H21 H23

H24 H25

H26

H27 H29

G36

D51

E46

U49

V49

E52

F19

A46

A48

AA46

A45

J17

H32

H31

H30

AR46

AR45

AR43

AR41

AR39

AR37

AR35

AP9

AP8

AP47

AP46

AP44

AP43

AP42

AP41

AP40

AP39

AP38

AP37

AP36

AP35

AP34

AP33

AP32

AP31

AP30

AP29

AP27

AP26

AP25

AP24

AP23

AP22

AP21

AP20

AP19

AP18

AP17

AP16

AP15

AP14

AP13

AP12

AP10

AN9

AN8

AN46

AN45

AN44

AN43

AN42

AB8

AD8

AC9

AC8

AE46

AC47

AC46

AB46

AB45

AD46

AG8

AF8

AE8

AH8

AH47

AH46

AG46

AE47

AJ45

AJ46

AK8

AL8

AL9

AM8

AK46

AK47

AL45

AL46

AM46

AM47

AM9

AN10

AN12

AN13

AN14

AN15

AN16

AN17

AN19

AN20

AN21

AN23

AN24

AN27

AN29

AN30

AN32

AN34

AN36

AN38

AN39

AN41

AN40

H33

H34

H36

H37

H38

H39

H40

H42

H43

H45

H46

H48H8H9

J10

J14

J19

J24

J29

J33

J36

J37

J40

J42

J43

J45

J46

J48J8J9

K38

K40

K43

K44

K45

K46

K48K8K9

L37

L38

L39

L40

L42

L43

L44

L46

L47L8M37

M38

M39

M40

M42

M43

M44

M45

M46M8M9

N37

N38

N39

N40

N42

N43

N44

N46

N47N8N9

P45

P46P8R46

R47R8R9

T45

T46

U46

U47U8U9

V45

V46

V8

J39

J38

W46

W47W8Y45

Y46Y8A27

A28

A31

A32

A34

B27

B28

B31

B32

B34

B36

B38

B39

B42

AN25

AN26

1

2

5 6

10 18 61

5

83

6 8

10 70

6 8

10 70

83

SYM 7 OF 12

GROUND

VSS VSS

SYM 8 OF 12

GROUND

VSSVSS

SYM 9 OF 12

VSS_P9(RSVD)

VSS_G18(RSVD)

VSS_AR22(RSVD)

VSS_AB48(RSVD)

VSS_NCTF

VSS_SENSE

VSS

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

U0500

HASWELL

OMIT_TABLE

BGA

U0500

HASWELL

OMIT_TABLE

BGA

U0500

HASWELL

OMIT_TABLE

BGA

61 83

R0960

PLACE_NEAR=U0500.D50:50.8mm PLACE_SIDE=BOTTOM

402

MF-LF

1/16W

5%

100

CPU Ground

SYNC_MASTER=J16_DINI SYNC_DATE=01/14/2013

CPU_VCCSENSE_N

051-0164

12.4.0

9 OF 123

9 OF 86

AP51

AP54 AP7

AR20

AN48

AN4

AN3

AM53

AM5

AL7

A11 A15

A19

A22 A26

A30

A33 A37

A40 A44

AA1

AA2 AA3

AA4

AA48

AA5

AA7

AB51

AB52 AB53

AB54

AB7 AB9

AC48

AC5

AC50

AC7

AD48 AD51

AD54

AD7

AD9

AE1 AE2

AE3

AE4

AE48

AE5

AE50

AE7

AF5 AF6

AF7

AG48

AG5

AG51

AG52 AG53

AG54

AG7 AG9

AH1 AH2

AH3

AH4

AH48

AH5

AH50

AH7

AJ48 AJ51

AJ54

AK48 AK5

AK50

AK7 AK9

AL1 AL4

AL48

AL5

AM51 AM52

AM54 AM7

AN1 AN2

AN5

AN50 AN7

AR12 AR14

AR16

AR18

AR24

AR26 AR48

AR5

AR50 AR7

AR8 AR9

AT1

AT10 AT12

AT15

AT16 AT18

AT20

AT22 AT25

AT26 AT29

AT33

AT35 AT37

AT39

AT4

AB5

AU29

AU33

AU37

BB9

BB7

BB6

BB5

BB49

BB48

BB47

BB46

BB44

BB43

BB42

BB41

BB39

BB38

BB37

BB33

BB32

BB28

BB25

BB23

BB20

BB18

BB17

BB16

BB15

BB14

BB12

BB11

BB10

BA9

BA53

BA52

BA51

BA50

BA5

BA42

BA4

BA37

BA33

BA29

BA25

BA22

BA18

BA13

B8

B30

B26

B22

B19

B15

B11

AY9

AY50

AV42

AV4

AY42

AY37

AY33

AY29

AY25

AY22

AY13

AW9

AW54

AW51

AW50

AW5

AW49

AW47

AW46

AW45

AW43

AW42

AW37

AW18

AW13

AV9

AV50

AV5

AV33

AV3

AV29

AV25

AV22

AV2

AV18

AV13

AV1

AU9

AU5

AU42

AU18

AU13

AT9

AT8

AT6

AT54

AT53

AT52

AT51

AT46

AT45

AT43

AT42

B37

B33

B44 B49

B40

AT50

AT5

AT49

AT47

AU22

AU25

AT40

P9

G18

AR22

AB48

H44

BC30

BC33

G33

G37

BC50

BC52

BC7

J51

A49

BD53

BF5

BF50

C53D2F54

G1

D50

W54

BC10

BC12

BC15

BC18

BC22

BC26

BC3

BC36

BD10

BD15

BD18

BD36

BD41

BD46

BD5

BD51

BE10

BE15

BE36

BE41

BE46

BF10

BF15

BF18

BF22

BF26

BF30

BF33

BF41

BF43

BF46

BF48

BF7

C11

C19

C22

C26

C30

C33

C37C4C40

C44

C49

C52C8D11

D15

D19

D22

D26

D30

D33

D37

D8

E11

E15

E16

E17

E19

E20

E21

E22

E24

E25

E26

E30

E33

E37

E40

E44

E49

E51

E53

E8

F3

F33

F37F4F40

F44

F49F5G11

G13

G16

D49

D44

D40

BF38

BF12

BC5

G20

G30

G40

G44

G49

G52

G54

G7G8G9

H49H7J44

J49

J54J7K1K2K3K4K5K6K7

L48L7L9

M48

M50

M52

M54M7N48N7P1P2P3P4P48P5P50

P52

P54P6P7

R48R7T48U1U2U3U4

U48U5U50

U52

U54U6U7

V48V7V9

W48

W50

W52W7Y48Y9Y7

A50A8B4

BA1

BA54

BB1

BB54

BD2

BF49

BF6

E54

C15

F30

F26

F2

G26

G25

G23

BC48

BC46

BC43

BC41

BC38

BF36

1

2

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

For noise floor mitigation of DP (C1070-C1075):

Intel recommendation: 4x 470uF 4mOhm (3 CPU-side, 1 opposite), 20x 22uF 0805 (10 CPU-side, 10 opposite near edge, 4x 10uF 0603 (2 CPU-side, 2 opposite), 20x 1uF 0402 (under CPU) Apple Implementation: 9x 210uF 6mOhm, 44x 10uF 0402, 4x 10uF 0402, 20x 1uF 0402

BULK CAPS ON REGULATOR PAGE

PLACEMENT_NOTE (C1020-C1023):

CPU VCORE Decoupling

PLACEMENT_NOTE (C1000-C1019):

PLACEMENT_NOTE (C1024-C1045):

Apple Implementation: 2x 0.01uF 0402 (second cap is on CPU VR page)

PLACEMENT_NOTE (C1046-C1067):

PLACEMENT_NOTE (C1080-C1089):

Intel recommendation: 2x 330uF, 8x 10uF 0603, 10x 1uF 0402

CPU VDDQ Decoupling

Apple Implementation: 2x 330uF, 8x 10uF 0603, 10x 1uF 0402

PLACEMENT_NOTE (C1090-C1097):

NOTE: Intel decoupling recommendations from Shark Bay Mobile Platform Power Delivery Design Guide (doc #487822, Rev 0.8 dated January 2012), Section 5.

Intel recommendation: 2x 0.01uF 0402 (1 near CPU, 1 near SVID pull-ups)

CPU VCCIO Decoupling

BULK CAPS ON REGULATOR PAGE

C1009

0402

Place on bottom side of U0500

1UF

X6S-CERM

10V

10%

C1008

0402

Place on bottom side of U0500

10% 10V X6S-CERM

1UF

C1007

Place on bottom side of U0500

10% 10V X6S-CERM

1UF

0402

C1031

Place near inductors on bottom side.

4V X6S 0402

10UF

20%

CRITICAL

C1006

1UF

10% 10V X6S-CERM 0402

Place on bottom side of U0500

C1005

0402

Place on bottom side of U0500

1UF

X6S-CERM

10V

10%

C1004

1UF

10% 10V X6S-CERM 0402

Place on bottom side of U0500

C1003

Place on bottom side of U0500

1UF

10V

10%

0402

X6S-CERM

0402

Place on bottom side of U0500

1UF

10V

10%

C1002

X6S-CERM

0402

Place on bottom side of U0500

1UF

X6S-CERM

10V

10%

C1001C1000

0402

Place on bottom side of U0500

X6S-CERM

10V

10%

1UF

0402

X6S

4V

Place near inductors on bottom side.

10UF

20%

C1030

CRITICAL

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

C1029

CRITICAL

C1027

X6S

4V

0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1026

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1020

20%

0402

10UF

X6S

4V

Place near U0500 on bottom side

C1021

20%

0402

4V X6S

10UF

Place near U0500 on bottom side

20%

0402

4V X6S

Place near U0500 on bottom side

10UF

C1022

Place near U0500 on bottom side

0402

X6S

20% 4V

10UF

C1023

C1025

4V X6S 0402

10UF

20%

CRITICAL

Place near inductors on bottom side.

C1024

4V X6S 0402

10UF

20%

CRITICAL

C1028

CRITICAL

0402

10UF

4V X6S

20%

Place near inductors on bottom side.

C1032

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1033

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1039

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1038

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1037

10UF

4V X6S 0402

20%

Place near inductors on bottom side.

CRITICAL

C1036

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1035

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1034

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1079

10%

0.01UF

16V

0402

X7R-CERM

C1089

X6S-CERM

Place on bottom side of U0500

0402

10% 10V

1UF

C1088

0402

Place on bottom side of U0500

10% 10V X6S-CERM

1UF

C1087

X6S-CERM 0402

10%

Place on bottom side of U0500

10V

1UF

C1086

1UF

10V

0402

Place on bottom side of U0500

10%

X6S-CERM

C1085

X6S-CERM

1UF

0402

Place on bottom side of U0500

10% 10V

C1084

X6S-CERM 0402

Place on bottom side of U0500

10% 10V

1UF

C1083

10V

0402

Place on bottom side of U0500

1UF

X6S-CERM

10%

C1082

1UF

X6S-CERM 0402

Place on bottom side of U0500

10V

10%

C1081

0402

Place on bottom side of U100.

1UF

X6S-CERM

10V

10%

C1080

X6S-CERM 0402

Place on bottom side of U0500

10%

1UF

10V

C1093

Place near U0500 on bottom side

20%

10UF

0603

X6S-CERM

4V

C1092

20%

Place near U0500 on bottom side

10UF

0603

X6S-CERM

4V

C1091

10UF

20% 4V

0603

Place near U0500 on bottom side

X6S-CERM

C1090

20%

Place near U0500 on bottom side

10UF

0603

4V X6S-CERM

C1097

20%

Place near U0500 on bottom side

10UF

0603

X6S-CERM

4V

C1096

20%

Place near U0500 on bottom side

10UF

X6S-CERM

4V

0603

C1095

0603

20%

Place near U0500 on bottom side

10UF

X6S-CERM

4V

C1094

20%

Place near U0500 on bottom side

10UF

0603

X6S-CERM

4V

C1043

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1042

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1041

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1040

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1019

0402

Place on bottom side of U0500

10% 10V X6S-CERM

1UF

C1018

0402

Place on bottom side of U0500

1UF

X6S-CERM

10V

10%

C1017

0402

Place on bottom side of U0500

1UF

X6S-CERM

10V

10%

C1016

0402

Place on bottom side of U0500

10% 10V X6S-CERM

1UF

C1015

0402

Place on bottom side of U0500

10% 10V X6S-CERM

1UF

C1014

0402

Place on bottom side of U0500

1UF

X6S-CERM

10V

10%

C1013

0402

Place on bottom side of U0500

X6S-CERM

10% 10V

1UF

C1012

0402

Place on bottom side of U0500

10% 10V X6S-CERM

1UF

C1011

0402

Place on bottom side of U0500

10% 10V X6S-CERM

1UF

C1010

0402

Place on bottom side of U0500

10% 10V X6S-CERM

1UF

C1065

Place near inductors on bottom side.

4V X6S 0402

10UF

20%

CRITICAL

C1064

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1063

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1062

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1061

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1060

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1059

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1058

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1057

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1056

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1055

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1054

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1053

10UF

CRITICAL

4V X6S 0402

20%

Place near inductors on bottom side.

C1052

X6S

4V

0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1051

4V X6S 0402

20%

Place near inductors on bottom side.

CRITICAL

10UF

C1050C1049

4V

20%

10UF

X6S 0402

Place near inductors on bottom side.

CRITICAL

C1048

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1047

X6S

4V

0402

10UF

20%

CRITICAL

Place near inductors on bottom side.

C1046

X6S

10UF

4V

0402

20%

CRITICAL

C1045

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1044

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1067

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1066

4V X6S 0402

10UF

20%

Place near inductors on bottom side.

CRITICAL

C1070

1.5PF

201

NP0-C0G

25V

+/-0.1PF

C1071

1.5PF

+/-0.1PF 25V NP0-C0G 201

C1072

1.5PF

+/-0.1PF 25V NP0-C0G 201 201

NP0-C0G

25V

+/-0.1PF

1.5PF

C1075C1074

1.5PF

+/-0.1PF 25V NP0-C0G 201

C1073

1.5PF

+/-0.1PF 25V NP0-C0G 201

SYNC_MASTER=J16_DINI SYNC_DATE=01/14/2013

CPU Decoupling

=PP1V5R1V35_S0_CPU

PPVCCIO_S0_CPU

=PPVCC_S0_CPU

10 OF 86

10 OF 123

12.4.0

051-0164

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

8

70

5 6 8

18 61

6 8

70

IN

OUT

IN

OUT

IN

OUT OUT

IN

OUT

NC

HDA_SDI1 HDA_SDI2

TP25 TP22

HDA_DOCK_RST*/GPIO13

SATA_RXP0

SATA_RXP5/PERP2

SATA_RXN5/PERN2

TP8

SRTCRST*

RTCX1 RTCX2

HDA_BCLK

DOCKEN*/GPIO33

SATA_RCOMP

SATA_TXN0

SATA_TXP4/PETP1

SATA_TXP1

SATA_TXN4/PETN1

SATA_TXN1

SATA0GP/GPIO21

SATALED*

SPKR

JTAG_TDI

JTAG_TDO

JTAG_TMS

TP20

JTAG_TCK

INTRUDER*

HDA_SYNC

HDA_SDI3

HDA_SDO

SATA_RXP2

SATA_RXN2

SATA_TXN2 SATA_TXP2

SATA_RXN3 SATA_RXP3 SATA_TXN3

TP9

SATA_IREF

SATA1GP/GPIO19

SATA_TXP0

SATA_RXN1 SATA_RXP1

RTCRST*

INTVRMEN

SATA_RXN0

SATA_RXP4/PERP1

SATA_RXN4/PERN1

SATA_TXP3

SATA_TXP5/PETP2

SATA_TXN5/PETN2

HDA_SDI0

HDA_RST*

JTAG

(1 OF 11)

RTC

AZALIA

SATA

CLOCKS

(2 OF 11)

PCIECLKRQ2*/GPIO20/SMI*

CLKOUT_33MHZ4

PCIECLKRQ5*/GPIO44

CLKOUT_PCIE_P1

CLKOUT_PCIE_N1

PCIECLKRQ0*/GPIO73

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_PCIE_P6

CLKOUT_PCIE_N6

CLKOUT_PCIE_N2 CLKOUT_PCIE_P2

TP18

TP19

CLKOUT_PCIE_N3 CLKOUT_PCIE_P3

PCIECLKRQ6*/GPIO45

CLKOUT_PCIE_P5

CLKOUT_PCIE_N5

PCIECLKRQ1*/GPIO18

CLKOUT_DPNS_N CLKOUT_DPNS_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKOUT_PCIE_N4 CLKOUT_PCIE_P4

PEG_A_CLKRQ*/GPIO47

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

CLKOUT_DP_P

CLKOUT_DP_N

CLKOUT_PCIE_P7

CLKOUT_PCIE_N7

XTAL25_OUT

XTAL25_IN

ICLK_IREF

DIFFCLK_BIASREF

CLKIN_GND_N CLKIN_GND_P

CLKIN_DMI_P

CLKIN_DMI_N

CLKOUT_33MHZ2

CLKIN_SATA_P

CLKIN_SATA_N

CLKOUTFLEX0/GPIO64

CLKIN_33MHZLOOPBACK

CLKOUT_33MHZ0 CLKOUT_33MHZ1

CLKOUTFLEX2/GPIO66

CLKOUTFLEX1/GPIO65

CLKOUTFLEX3/GPIO67

CLKOUT_33MHZ3

REFCLK14IN

CLKIN_DOT96_P

CLKIN_DOT96_N

PCIECLKRQ3*/GPIO25

PEG_B_CLKRQ*/GPIO56

PCIECLKRQ4*/GPIO26

PCIECLKRQ7*/GPIO46

CLKOUT_PEG_B_P

CLKOUT_PEG_B_N

CLKOUT_PCIE_N0 CLKOUT_PCIE_P0

OUT OUT

OUT

IN

IN OUT OUT

OUT OUT

IN

NC NC

NC

OUT

IN OUT

OUT

IN

OUT

IN

NC NC NC NC

OUT OUT

NC

OUT OUT

NC

OUT OUT

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

NOTE: SSC control is ganged on PCIe 0-3 and 4-7 clocks.

(IPD)

PRIMARY HDD

If HDA = S0, must also ensure that signal cannot be high in S3.

Connect to ENET_MEDIA_SENSE via alias if HDA = 3.3V. Connect to ENET_MEDIA_SENSE via 12K R if HDA = 1.5V.

(IPU-RSMRST#)

Unused clock terminations for FCIM Mode

SSD

(IPD-boot)

(IPU)

(IPU-PLTRST#)

If 2 or less devices are attached to PEG the CLKOUT_PEG outputs can be used for those devices.

(IPD-PWROK)

(IPU-RSMRST#)

(IPD-PWROK)

(IPD)

1.5V -> 1.1V

(IPD-boot)

(IPD)

(IPD-PLTRST#)

(IPD)

SATA Port assignments:

PEG-attached (CPU) PCIe devices must use one set, while PCH-attached PCIe devices use the other set.

(IPD)

(IPU)

(IPD-DOCKEN#?)

52 79

R1101

1M

MF 201

5% 1/20W

20K

MF

201

5%

1/20W

R1102

1/20W

R1103

5%

20K

201

MF

1UF

X5R 402

10% 10V

C1103

1UF

X5R 402

10% 10V

C1102

PLACE_NEAR=U1100.AY5:2.54mm

7.5K

MF

201

1%

1/20W

R1130

11 35 80

18 78

1/16W

1%

402

MF-LF

340

R1172

MF

201

1%

1/20W

1K

R1173

19 79

32 77

11 18 32

11 33

11 28

6

77

6

77

6

77

6

77

19 79

4.7K

201

5%

1/20W

MF

R1177

MF5%

1/20W

4.7K

R1178

201

R1134

1/20W

5%

201

MF

10K

1/20W

5%

201

MF

10K

R1142

5%

R1169

1/20W

201

MF

10K

1/20W

5%

201

MF

10K

R1144 R1145

1/20W

5%

201

MF

10K

1/20W

5%

201

MF

10K

R1147 R1114

1/20W

5%

201

MF

10K

2 1

5%

1/20W

201

MF

10K

R1115

R1143

10K

MF

201

5%

1/20W

10K

MF

201

5%

1/20W

R1133

1/20W

5%

201

MF

10K

R1179

10K

MF

201

5%

1/20W

R1146

10K

MF

201

5%

1/20W

R1148

52 79

1/20W

5%

201

MF

10K

R1191

1/20W

5%

201

MF

10K

R1192

201

1/20W

5% MF

10K

R1193

1/20W

5%

201

MF

10K

R1194

1/20W

5%

201

MF

10K

R1195

5%

1/20W

201

MF

10K

R1196

1/20W

5%

201

MF

10K

R1197

1/20W

10K

MF

201

5%

R1170

1/20W

5%

201

MF

10K

R1171

FCBGA

MOBILE

LYNXPOINT

OMIT_TABLE

U1100

FCBGA

OMIT_TABLE

LYNXPOINT

MOBILE

U1100

6

77

6

77

R1110

33

1/20W

5%

201

MF

PLACE_NEAR=U1100.B25:3.7MM

33

201

MF

1/20W

5%

R1113

PLACE_NEAR=U1100.A24:3.7MM

5%

33

201

1/20W

R1111

MF

PLACE_NEAR=U1100.A22:3.5MM

1/20W

5%

201

MF

33

R1112

PLACE_NEAR=U1100.C24:4.5MM

19 79

33 78

35 77

11 18 35

7.5K

201

PLACE_NEAR=U1100.AN44:2.54mm

1%

MF

1/20W

R1190

2 1

11 41 58

R1176

1/20W

5%

201

MF

10K

19 79

33 78

11 18 29 30

11 18

33 77

26 77

R1100

330K

5% 1/20W MF 201

SYNC_MASTER=J16_KENNY

SYNC_DATE=01/21/2013

PCH RTC/HDA/JTAG/SATA/CLK

=PPVRTC_G3_PCH

PCH_SRTCRST_L PCH_INTRUDER_L PCH_INTVRMEN_L

PCH_CLKRQ3_L_GPIO25

PCIE_CLK100M_AP_P

PCH_CLKRQ5_L_GPIO44

=PP3V3_S0_PCH_GPIO

=PP3V3_SUS_PCH_GPIO

HDA_SYNC

PCIE_CLK100M_PCHN PCIE_CLK100M_PCHP

PCH_CLKIN_GNDN

PCH_CLK96M_DOTP

TP_PCH_GPIO64_CLKOUTFLEX0

SYSCLK_CLK25M_SB_R

PCH_CLK100M_SATAP

TP_PCI_CLK33M_OUT2

PCH_CLK96M_DOTN

DP_TBT_SEL

CPU_CLK135M_DPLLSS_P

SATA_HDD_D2R_P

TP_PCI_CLK33M_OUT3

=PP1V5_S0_PCH_VCCVRM_BIAS

RTC_RESET_L

SYSCLK_CLK25M_SB

TP_HDA_SDIN3

PCH_CLK14P3M_REFCLK

PCH_CLKIN_GNDP

PCH_CLK100M_SATAN

TP_PCH_GPIO65_CLKOUTFLEX1 TP_PCH_GPIO66_CLKOUTFLEX2 TP_PCH_GPIO67_CLKOUTFLEX3

PCH_CLK33M_PCIIN

CPU_CLK135M_DPLLSS_N

CPU_CLK135M_DPLLREF_P

CPU_CLK135M_DPLLREF_N

PCH_PEGCLKRQB_L_GPIO56

XDP_PCH_TDO

LPC_CLK33M_SMC_R LPC_CLK33M_LPCPLUS_R

PCH_CLK33M_PCIOUT

DMI_CLK100M_CPU_P

PCH_SATALED_L

XDP_PCH_TDI

TP_HDA_SDIN2

PCH_INTVRMEN_L

PCH_SRTCRST_L

HDA_BIT_CLK

RTC_RESET_L

HDA_RST_R_L

TP_HDA_SDIN1

PCH_INTRUDER_L

PCH_CLK32K_RTCX2

PCH_CLK32K_RTCX1

SATA_HDD_D2R_N

SATA_HDD_R2D_C_P

SATA_HDD_R2D_C_N

SSD_R2D_P<0>

SSD_D2R_N<0> SSD_D2R_P<0>

SSD_D2R_P<1> SSD_R2D_N<1> SSD_R2D_P<1>

SSD_R2D_N<0>

PCH_SATA_RCOMP

SATARDRVR_EN

DP_AUXIO_EN

PCH_PEGCLKRQA_L_GPIO47

DMI_CLK100M_CPU_NPCIE_CLK100M_AP_N

PCIE_CLK100M_ENET_P

PCH_PEGCLKRQB_L_GPIO56

PCH_SATALED_L

SSD_CLKREQ_L

PCH_SPKR

DP_AUXIO_EN

PCH_CLKRQ5_L_GPIO44

TBT_CLKREQ_L

PCH_CLKRQ3_L_GPIO25

ENET_CLKREQ_L AP_CLKREQ_L

PEG_CLKREQ_L PCH_CLKRQ7_L_GPIO46

PCH_PEGCLKRQA_L_GPIO47

ENET_MEDIA_SENSE

HDA_SDOUT_R

DP_TBT_SEL ENET_MEDIA_SENSE

XDP_PCH_TCK

=PP1V5_S0_PCH_SATA

=PP1V5_S0_PCH_CLK

PCH_DIFFCLK_BIASREF

HDA_SDIN0

SSD_D2R_N<1>

XDP_PCH_TMS

SSD_CLKREQ_L

PCIE_CLK100M_ENET_N

PCIE_CLK100M_SSD_P

PCIE_CLK100M_SSD_N

SATARDRVR_EN

AP_CLKREQ_L

ENET_CLKREQ_L

TBT_CLKREQ_L

PCIE_CLK100M_TBT_P

PCIE_CLK100M_TBT_N

PCH_CLKRQ7_L_GPIO46

PEG_CLKREQ_L

HDA_BIT_CLK_R

HDA_SDOUT

PCH_SPKR

HDA_RST_L

HDA_SYNC_R

11 OF 123

11 OF 86

12.4.0

051-0164

1

2

121

2

1

2

1

2

1 2

1

2

1 2

1 2 1 2

1 2

K22 G22

F8

C26

C22

BE8

BE14

BC14

BB2

B9

B5

B4

B25

B17

AY5

AW8

AW15

AW10

AV15

AV10

AT1

AP3

AL10

AE2

AD3

AD1

AB6

AB3

A8

A22

F22

A24

BD9

BB9

AY13

AW13

BC12

BE12 AR13

BA2

BD4

AU2

AY8

BC10

BE10

D9

G10

BC8

BB13

BD13

AT13

AR15

AP15

L22

C24

AF3

A40

AA2

AA42

AA44

AB1

AB35 AB36

AB39

AB40

AB43 AB45

AD38

AD39

AD43

AD45

AE4

AE42

AE44

AF1

AF35

AF36

AF39 AF40

AF43

AF45

AF6

AH43 AH45

AJ39

AJ40

AJ42

AJ44

AL44

AM43

AM45

AN44

AR24

AT24

AW24

AY24

B42

BC6

BE6

C40

D17

D44 E44

F36

F38

F39

F41

F45

G33

H33

T3

U4

V3

Y3

Y38

Y39

Y43 Y45

1 2

1

2

12 15 70

11

12 14 28 70

12 13 14 70

72

79

72

11 41 58

72 17

11 19 45

72

11

11 33

72

11

11 19 45

79

72

11

78

11

11 33

11

11 18 29 30

11

11 28

11

11 18 35

11 18 32

11

11 35 80

19 79

70

19 70

11 18

11

79

11

79

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

DAC_IREF VGA_IRTN

VGA_VSYNC

VGA_HSYNC

PIRQH*/GPIO5

PIRQG*/GPIO4

DDPC_AUXN

EDP_BKLTEN

EDP_VDDEN

GPIO54

GPIO51

GPIO55

GPIO53

DDPC_CTRLCLK

DDPB_CTRLDATA

DDPB_CTRLCLK

DDPC_CTRLDATA

EDP_BKLTCTL

PIRQF*/GPIO3

DDPC_HPD

DDPC_AUXP DDPD_AUXP

DDPB_HPD

DDPD_HPD

PIRQE*/GPIO2

DDPD_CTRLDATA

DDPD_CTRLCLK

VGA_RED

PIRQA*

GPIO52

GPIO50

PIRQD*

PIRQC*

PIRQB*

PME*

PLTRST*

DDPB_AUXN

VGA_BLUE VGA_GREEN

DDPB_AUXP

DDPD_AUXN

VGA_DDC_DATA

VGA_DDC_CLK

CRT

PCI

DISPLAY

(5 OF 11)

EDP

OUT

IN

OUT

IN

BI

OUT

IN

SYSTEM POWER

MANAGEMENT

(4 OF 11)

DMI

FDI

SUSACK*

RI*

DPWROK

BATLOW*/GPIO72

PWRBTN*

RSMRST*

DRAMPWROK

SLP_LAN*

SLP_A*

PWROK

SLP_SUS*

ACPRESENT/GPIO31

SLP_WLAN*/GPIO29

DSWVRMEN

SLP_S4*

DMI_TXN1

DMI_TXN3

DMI_TXN2

DMI_TXP1

DMI_TXP0

TP5

PMSYNCH

DMI_RXN0

TP15

TP16

TP13

TP17

DMI_RXN1

SYS_RESET*

FDI_RXP1

FDI_RXN1

FDI_RXP0

FDI_RXN0

APWROK

TP21

SUSWARN*/SUSPWRNACK/GPIO30

DMI_TXN0

FDI_RCOMP

DMI_TXP2 DMI_TXP3

DMI_IREF

TP12

DMI_RCOMP

TP7

WAKE*

SUS_STAT*/GPIO61

SUSCLK/GPIO62

SLP_S5*/GPIO63

DMI_RXP0

DMI_RXP3

DMI_RXP2

DMI_RXP1

TP10

SLP_S3*

CLKRUN*

SYS_PWROK

DMI_RXN2

FDI_IREF

FDI_INT

FDI_CSYNC

DMI_RXN3

OUT

IN IN IN

OUT

NC NC NC

NC NC

NC

NC NC

OUT

IN

NC

IN

NC NC NC

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DG v1.0 (Table 12-18).

Redundant to pull-up on audio page

VGA DAC Disabled per SB

(IPD-DeepSx)

(IPU-RSMRST#)

(IPD-PLTRST#)

(IPU)

(IPU-PWROK&PCIRST#)

(OD)

(IPD-PLTRST#)

(IPU)

(IPD-PLTRST#)

(IPD-DeepSx)

(IPU)

Redundant to pull-up on audio page

5

77

5

78

1%

7.5K

R1200

PLACE_NEAR=U1100.AY17:12.7mm

MF

1/20W

201

5

77

5

77

5

77

5

77

5

77

5

77

5

77

5

77

5

77

5

77

5

77

5

77

5

77

5

77

5

77

FCBGA

LYNXPOINT

OMIT_TABLE

MOBILE

U1100

10K

R1205

MF

1/20W

201

5%

12

19 44

18 45 69

6

21

18 20 39 69

69

12 18 69

12 18 44

12

12 32 36

12 44 45 46

20 44 46

45 79

12 32 44 68

12 44 68

12 21 36 44 45 68 69

6

76

12 18 69

100K

R1223

2 1

MF

1/20W

201

5%

1K

R1225

MF

1/20W

201

5%

NO STUFF

10K

R1291

MF

1/20W

201

5%

100K

R1222

2 1

MF

1/20W

201

5%

100K

R1221

2 1

MF

1/20W

201

5%

100K

R1224

2 1

MF

1/20W

201

5%

FCBGA

LYNXPOINT

MOBILE

OMIT_TABLE

U1100

5

78

PLACE_NEAR=U1100.AR44:12.7mm

1%

7.5K

R1210

MF

1/20W

201

10K

R1261

MF

1/20W

201

5%

R1263

10K

MF

1/20W

201

5%

R1262

10K

MF

1/20W

201

5%

10K

R1260

MF

1/20W

201

5%

NO STUFF

10K

R1233

MF

1/20W

201

5%

R1231

10K

MF

1/20W

201

5%

R1230

10K

MF

1/20W

201

5%

100K

R1217

MF

1/20W

201

5%

10K

R1218

MF

1/20W

201

5%

12 20

10K

R1216

MF

1/20W

201

5%

12 58

12 26

12 56

20

R1286

0201

MF

1/20W

0

5%

12 20

12 32

1

3.0K

R1239

2

MF

1/20W

201

5%

45

R1226

10K

MF

1/20W

201

5%

26

12 32 36

12 37

10K

R1240

MF

1/20W

201

5%

100K

R1214

NO STUFF

MF

1/20W

201

5%

330K

R1215

MF

1/20W 201

5%

R1209

10K

MF

1/20W 201

5%

PCH DMI/FDI/PM/GFX/PCI

SYNC_MASTER=J16_KENNY

SYNC_DATE=01/21/2013

FDI_CSYNC FDI_INT

PCH_DSWVRMEN

PM_RSMRST_PCH_L

PCH_GPIO72

AUD_IP_PERIPHERAL_DET

SDCONN_OC_L

TBT_PWR_REQ_L AUD_I2C_INT_L

TP_PCH_SLP_WLAN_L

=PP3V3_SUS_PCH_GPIO

PCH_SUSACK_L

TP_PCH_SLP_LAN_L

PM_SYNC

TP_DP_IG_B_AUXCHP

TP_DP_IG_D_AUXCHP

TP_DP_IG_B_HPD

PM_PCH_SYS_PWROK

PM_PCH_APWROK

PM_SYSRST_L

PM_PCH_PWROK

DMI_S2N_P<1>

DMI_S2N_N<2>

DMI_S2N_N<1>

DMI_S2N_P<3>

DMI_N2S_N<0> DMI_N2S_N<1>

PCIE_WAKE_L

DMI_S2N_P<2>

DMI_S2N_P<0>

DMI_S2N_N<3>

DMI_S2N_N<0>

DMI_N2S_P<3>

DMI_N2S_P<1> DMI_N2S_P<2>

DMI_N2S_P<0>

DMI_N2S_N<3>

DMI_N2S_N<2>

PLT_RESET_L

TP_PCI_PME_L

TP_DP_IG_D_AUXCHN

TP_DP_IG_C_AUXCHN

TP_DP_IG_D_DDC_CLK TP_DP_IG_D_DDC_DATA

TP_DP_IG_C_DDC_CLK

TP_DP_IG_B_DDC_CLK TP_DP_IG_B_DDC_DATA

PM_SLP_S4_L

TP_DP_IG_B_AUXCHN

=PP1V5_S0_PCH_RCOMP

TP_DP_IG_C_DDC_DATA

TP_DP_IG_C_HPD

TP_DP_IG_C_AUXCHP

PM_SLP_SUS_L

PM_SLP_S5_L

PM_CLK32K_SUSCLK_R

LPC_PWRDWN_L

PCH_RI_L

PM_RSMRST_PCH_L

PM_MEM_PWRGD

PCH_SUSWARN_L

PM_SLP_S4_L

BT_PWR_RST_L

PCH_STRP_TOPBLK_SWP_L

AUD_I2C_INT_L

PCI_INTD_L

TP_DP_IG_D_HPD

PM_SLP_S3_L

PM_SLP_S5_L PM_SLP_SUS_L

TP_PCH_STRP_ESI_L

=TBT_WAKE_LPCIE_WAKE_L

MAKE_BASE=TRUE

TP_PCH_STRP_BBS1

AUD_IPHS_SWITCH_EN_PCH

ENET_LOW_PWR_PCH

PCI_INTB_L

PCI_INTA_L

PM_PWRBTN_L

TBT_PWR_REQ_L

ENET_LOW_PWR_PCH

AUD_IP_PERIPHERAL_DET

=PP1V5_S0_PCH_RCOMP

PCH_FDI_RCOMP

PCH_GPIO31

=PPVRTC_G3_PCH

PM_PWRBTN_L

PCH_GPIO72

=PP3V3_S0_PCH_GPIO

PCH_GPIO31

=PP3V3_S0_PCH_GPIO

=PP3V3_S5_PCH_GPIO

SDCONN_OC_L

BT_PWR_RST_L

PM_CLKRUN_L

AUD_IPHS_SWITCH_EN_PCH

PCI_INTC_L

TP_PM_SLP_A_L

PM_SLP_S3_L

PM_CLKRUN_L

PCH_DMI_RCOMP

12 OF 86

12 OF 123

12.4.0

051-0164

1

2

U40 U39

N44

N42

M15

L15

K43

K36

G36

C12

C10

AL6

A10

R35

R39

R40

R36

N36

F17

K38

K45

J44

K40

H39

G17

N38

N40

V45

H20

B13

A12

M20

K17

L20

AD10

Y11

H45

T45

U44

H43

J42

M45

M43

1

2

1 2

R6

N4

L13

K7

K1

J2

H3

G5

F3

F10

F1

E6

D2

C8

C6

BE20

BE18

BD17

BC20

BB21

AY45

AY3

AW22

AV45

AV43

AU44

AU42

AR20

AM1

AL36

AL35

AJ36

AJ35

AB7

AB10

J4

BD21

AR44

BB17 BC18

BE16

AW17

AY17

AV17

K3

U7

Y6

Y7

AY22

AW20

AR17

AP20

AW44

H1

AN7

AD7

AP17

AT45

AL40

AL39

AV20

1

2

1 2

1 2 1 2

1 2

1

2

1 2

1

2

1

2

12

11 13 14 70

71

12 13 70

71

12 44 68

12 56

71

12 21 36 44 45 68 69

12 32 44 68

12

12 18 44

12 26

12 20

12 58

12 13 70

78

12

11 15 70

11 12 14 28 70

12

11 12 14 28 70

70

12 37

12 32

12 44 45 46

12 20

77

BI

BI BI

BI

OC1*/GPIO40 OC2*/GPIO41

OC5*/GPIO9

OC0*/GPIO59

OC3*/GPIO42

OC6*/GPIO10

OC4*/GPIO43

OC7*/GPIO14

USB2P6

USB2N6

USB2P5

USB2N7

USB2N5

USB2N13

USB2P0

USB2P4

USB2P10

USB2P2

USB2P3

USB2P8

PETN7

PETP6

PETN4

PETN3

PETN1_USB3TN3

PCIE_IREF

USB3TP6

USB3TN5

USB3TN1

PETN8 PETP8

PETN5

PCIE_RCOMP

USB3TN6

USB3TN2

USB3TP1

PETP7

PETN6

PETP1_USB3TP3

TP11

USB3TP5

USB3TP2

PETP5

TP6

USB2N0

USB2N4

USB2N10

PERN6

PERP3

PERP1_USB3RP3

PERP6

PERN5

PERN3

PERN1_USB3RN3

USB3RN5

USB3RN2

PERP5

USB3RP5

USB3RP2

PERN7 PERP7

PERN4

PERN2_USB3RN4

PERP4

PERP2_USB3RP4

USB3RN6

USB3RN1

USB3RP6

USB3RP1

PERP8

PERN8

USB2N1

USB2N2

USB2N3

USB2N9 USB2P9

USB2N8

USB2P7

USB2N11

USB2P13

USB2P1

PETP4

USB2P11

PETP2_USB3TP4

PETN2_USB3TN4

PETP3

USB2N12 USB2P12

TP23

TP24

USBRBIAS*

USBRBIAS

(9 OF 11)

USB

PCI-E

BI

OUT

IN

OUT

IN

OUT

SML0CLK

SML1ALERT*/PCHHOT*/GPIO74

LDRQ1*/GPIO23

LAD1

TP3

TP4

TP2

TP1

SPI_CS1*

SERIRQ

SPI_CS0*

SPI_IO2

SPI_IO3

SPI_CLK

SPI_CS2*

SPI_MISO

SPI_MOSI

LAD2

SML1DATA/GPIO75

CL_RST*

SML1CLK/GPIO58

LDRQ0*

TD_IREF

CL_CLK

CL_DATA

SMBALERT*/GPIO11

SMBCLK

SMBDATA

SML0ALERT*/GPIO60

LAD0

SML0DATA

LFRAME*

LAD3

SMBUS

LPC

(3 OF 11)

SPI

C-LINK

IN

BI

OUT

BI

OUT

BI

OUT

BI BI BI

BI BI

IN

OUT

IN

OUT

NC

BI

IN

IN OUT OUT

IN

OUT OUT

IN

OUT OUT

IN

OUT OUT

IN

IN OUT OUT

IN

IN OUT

BI

IN

NC NC

IN IN

OUT OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

NC

BI

NC NC

NC

NC NC

NC

NC NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Ext C (SS)

(IPD)

Ext B (SS)

Ext D (LS/FS/HS)

USB Port Assignments:

Ext C (LS/FS/HS)

Ext A (LS/FS/HS)

Ext B (LS/FS/HS)

(IPU)

(IPU) (IPU)

(IPD)

(IPU)

(IPU-LDRQ1#?)

(IPU)

(IPU/IPD)

CAMERA

BT

Ext A (SS)

USB3 Port Assignments:

Ext D (SS)

(IPU)

AirPort

ENET

TBT

43 80

10K

MF

201

5%

1/20W

R1367

2 1

5%

1/20W

10K

MF

201

R1368

10K

1/20W

MF

201

5%

R1361

10K

MF

201

1/20W

R1362

5%

10K

MF

201

1/20W

5%

R1360

R1369

1/20W

5%

201

MF

10K

42 80

OMIT_TABLE

MOBILE

LYNXPOINT

FCBGA

U1100

42 80

32 77

46 79

MOBILE

LYNXPOINT

OMIT_TABLE

FCBGA

U1100

47

47 81

R1300

7.5K

PLACE_NEAR=U1100.BD29:12.7mm

1/20W

201

MF

1%

201

MF5%

1/20W

33

R1340

MF

201

5%

1/20W

33

R1341

MF

201

5%331/20W

R1343

MF

201

33

1/20W

R1342

5%

201

MF

1/20W

33

R1344

13 20

13 44 46

1/20W

R1350

MF5%

201

10K

44 46 79

8.2K

MF

1/20W

201

1%

R1380

32 80

35 77

R1355

10K

MF

201

5%

1/20W

R1354

10K

MF

201

5%

1/20W

R1353

10K

MF

201

5%

1/20W

5%

201

MF

10K

R1320

10K

R1321

1/20W

5%

201

MF

46 79

5%

10K

MF

201

1/20W

R1351

38 80

42 80

43 80

13 18 42

13 18 43

13 18

13 18 42

13 18 43

13 18

42 80

13 18 37

26 77

42 80

PLACE_NEAR=U1100.K24:11.4mm

1% 1/20W

201

MF

22.6

R1370

PCH PCI-E/USB

SYNC_MASTER=J16_KENNY

SYNC_DATE=01/21/2013

USB_EXTB_OC_L USB_EXTD_OC_L PCH_GPIO10 SDCONN_STATE_CHANGE

PCH_GPIO10

USB_EXTD_OC_L

USB_EXTB_OC_L

PCH_GPIO42

USB_EXTA_OC_L

LPC_SERIRQ

TBT_PWR_EN_PCH

=PP3V3_S3RS4_PCH_GPIO

PCH_GPIO42

PCH_USB_RBIAS

USB_EXTB_8_N

USB_CAMERA_P

USB_BT_N

PCH_PCIE_RCOMP

=PP3V3_S0_PCH

USB_EXTA_OC_L USB_EXTC_OC_L

PCIE_TBT_D2R_P<2>

PCIE_AP_D2R_P

PCIE_AP_D2R_N

PCIE_ENET_D2R_N

PCIE_TBT_R2D_C_P<0>

PCIE_TBT_D2R_P<0>

PCIE_TBT_D2R_N<0>

PCIE_TBT_R2D_C_N<0>

PCIE_TBT_R2D_C_P<1>

PCIE_TBT_D2R_N<1> PCIE_TBT_D2R_P<1>

PCIE_TBT_R2D_C_N<1>

PCIE_TBT_D2R_N<2>

PCIE_TBT_D2R_N<3> PCIE_TBT_D2R_P<3>

PCIE_TBT_R2D_C_N<3>

LPC_AD_R<1>

LPC_AD_R<0>

SPI_CS0_R_L

SPI_MOSI_R

SDCONN_STATE_CHANGE

PCH_GPIO41

USB_EXTC_OC_L

USB3_EXTD_TX_P

USB3_EXTD_RX_F_N

USB3_EXTC_RX_F_P

USB3_EXTC_RX_F_N

USB3_EXTC_TX_P

USB3_EXTC_TX_N

USB3_EXTD_TX_N

USB3_EXTD_RX_F_P

USB3_EXTA_RX_F_N

USB3_EXTA_TX_N

USB3_EXTA_RX_F_P

USB3_EXTA_TX_P

USB3_EXTB_TX_P

USB3_EXTB_TX_N

USB3_EXTB_RX_F_P

USB3_EXTB_RX_F_N

USB_CAMERA_N

USB_EXTB_8_P

USB_EXTD_9_N

USB_EXTA_0_N USB_EXTA_0_P

USB_EXTC_1_N USB_EXTC_1_P

PCH_SML1ALERT_L

PCH_GPIO41

SMBUS_PCH_DATA

SML_PCH_0_CLK SML_PCH_0_DATA

SML_PCH_1_CLK SML_PCH_1_DATA

PCH_SML0ALERT_L

SMBUS_PCH_CLK

PCH_SMBALERT_L

TP_CLINK_DATA

TP_CLINK_CLK

PCH_TD_IREF

TP_CLINK_RESET_L

SPI_MISO

SPI_CLK_R

LPC_SERIRQ

TBT_PWR_EN_PCH

PCH_SML1ALERT_L

LPC_AD<0>

LPC_AD<2> LPC_AD<3>

LPC_AD<1>

LPC_FRAME_L

USB_EXTD_9_P

USB_BT_P

PCIE_AP_R2D_C_P

PCIE_ENET_R2D_C_P

PCIE_ENET_D2R_P

PCIE_AP_R2D_C_N

PCIE_ENET_R2D_C_N

TP_LPC_DREQ0_L

LPC_FRAME_R_L

LPC_AD_R<3>

LPC_AD_R<2>

PCIE_TBT_R2D_C_N<2> PCIE_TBT_R2D_C_P<2>

PCIE_TBT_R2D_C_P<3>

=PP3V3_SUS_PCH_GPIO

PCH_SMBALERT_L PCH_SML0ALERT_L

=PP1V5_S0_PCH_RCOMP

13 OF 86

13 OF 123

12.4.0

051-0164

1 2

V1

U2

T1

P3

P1

N2

M3

M1

L31

K31

G31

G29

F31

F24

D37

D33

D29

C36

C34

C32

BE40

BE38

BE36

BE34

BE32

BE30

BE28

BE26

BE24

BD42

BD41

BD37

BD29

BD27

BD25

BD23

BC40

BC38

BC32

BC30

BC26

BC24

BB37

BB29

B37

B33

B29

AY38

AY33

AY31

AW38

AW36

AW33

AW31

AW29

AW26

AV36

AV29

AV26AT40

AT39

AT33

AT31

AR33

AR31

AR29

AR26

AP29

AP26

AN39

AN38

A38

A36

A34

A30 C30

A32

H29

A28

G24

C38

BC36

C28

BB33

BD33

BC34

G26

F26

L33

M33

K24 K26

U8

H6

G20

C20

BE44

BE43

BC45

BA45

AL7

AL11

AJ7

AJ4

AJ2

AJ11

AJ10

AH3

AH1

A18

N11

AF7

K6

D21

AY43

AF11

AF10

N7

R10

U11

N8

A20

R7

B21

C18

1

2

1 2 1 2

1 2

1

2

1 2

1

2

13 18 42

13 18 43

13 18

13 18 37

13 44 46

13 20

70

13 18

80

77

19 70

13 18 42

13 18 43

79

13

13 18

13

72

79

11 12 14 70

13

12 70

OUT

BI

OUT

IN

BI

ININ

OUT

IN

GPIO24

GPIO57

GPIO27

TACH4/GPIO68

SCLOCK/GPIO22

THRMTRIP*

BMBUSY*/GPIO0

SLOAD/GPIO38

GPIO35/NMI*

GPIO34

SDATAOUT1/GPIO48

SDATAOUT0/GPIO39

SATA5GP/GPIO49

SATA3GP/GPIO37

GPIO28

GPIO15

SATA4GP/GPIO16

TACH0/GPIO17

VSS

GPIO8

PLTRST_PROC*

TP14

LAN_PHY_PWR_CTRL/GPIO12

TACH3/GPIO7

TACH2/GPIO6

TACH1/GPIO1

VSS

TACH7/GPIO71

TACH6/GPIO70

TACH5/GPIO69

PECI

PROCPWRGD

RCIN*

VSS

SATA2GP/GPIO36

CPU/MISC

(6 OF 11)

GPIO

OUT

BI

OUT

IN

OUT

BI

OUT

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(IPU-Boot?)

(IPD-PLTRST#)

(IPU-Boot/SATA4GP?)

(IPU-Boot/SATA5GP?)

(IPU-Boot?)

(IPU-DeepSx)

(IPU-RSMRST#)

(IPD-PLTRST#)

(IPD)

6

18 76

21

14 46

14 20

14 18 20

14 20

46 79

6

45 76

5%

201

1/20W MF

R1474

10K

5%

201

1/20W

MF

10K

R1475

14 44 81

14 20

14 44 81

U1100

OMIT_TABLE

MOBILE

LYNXPOINT

FCBGA

5%

201

1/20W

MF

2 1

20K

R1411

5%

201

1/20W

MF

10K

R1491

5%

201

1/20W

MF

R1492

10K

5%

201

1/20W

MF

10K

R1494

201

1/20W

MF

10K

5%

R1484

5%

201

1/20W

MF

100K

R1490

5%

201

1/20W

MF

10K

R1496

5%

201

1/20W

MF

10K

R1485

5%

201

1/20W

MF

12

10K

R1412

28

14 18

5%

201

1/20W

MF

2

10K

1

R1498

201

1/20W

MF

10K

5%

R1450

5%

201

1/20W

MF

R1455

10K

5%

201

1/20W

MF

R1470

NO STUFF

43

5%01/20W MF

0201

R1440

5%

201

1/20W

MF

R1456

390

6

44 45 76

14 36

20

18 67

14 26

6

18 76

5%

201

1/20W

MF

10K

R1486

5%

201

1/20W

MF

10K

R1499

5%

201

1/20W

MF

2

10K

R1413

1

5%

201

1/20W

MF

R1489

10K

3

18

5%

R1457

NO STUFF

402

MF-LF

1/16W

1K

14 18

201

1/20W

MF1%

33.2

PLACE_NEAR=U1100.C16:10MM

R1461

201

1/20W

MF

PLACE_NEAR=U1100.D13:10MM

R1462

33.2

1%

39

5%

201

1/20W

MF

10K

R1495

201

1/20W

MF

10K

5%

R1497

5%

201

1/20W

MF

R1422

1K

5%

201

1/20W MF

1K

R1423

PCH GPIO/MISC/NCTF

SYNC_MASTER=J16_KENNY

SYNC_DATE=03/07/2013

=PP3V3_S0_PCH_GPIO

=PP3V3_SUS_PCH_GPIO

FW_PWR_EN_PCH

PCH_A20GATE

JTAG_ISP_TDO

PCH_GPIO49

PCH_RCIN_L

WOL_EN MEM_VDD_SEL_1V5_L

FW_PME_L

SMC_RUNTIME_SCI_L

PCH_GPIO16 LPCPLUS_GPIO JTAG_TBT_TMS_PCH

PCH_GPIO36

TBT_GO2SX_BIDIR

PCH_A20GATE

PCH_PECI

PCH_PROCPWRGD

PCH_CAM_EXT_BOOT_R_L

PCH_CAM_RESET_R

PCH_RCIN_L

CPU_PECI

CPU_PWRGD

PM_THRMTRIP_L

CPU_RESET_L

=PP1V05_S0_PCH_V_PROC_IO

TBT_CIO_PLUG_EVENT_ISOL

SMC_RUNTIME_SCI_L

JTAG_ISP_TDI

=PP3V3_S0_PCH_GPIO

HDD_PWR_EN

WOL_EN

MEM_VDD_SEL_1V5_L

SMC_WAKE_SCI_L

JTAG_TBT_TMS_PCH

TBT_GO2SX_BIDIR

LPCPLUS_GPIO

PCH_GPIO16

ISOLATE_CPU_MEM_L

TBT_SW_RESET_L

GPU_GOOD

PCH_GPIO36

PCH_CAM_EXT_BOOT_L

SPIROM_USE_MLB

PCH_GPIO49

DPMUX_UC_IRQ

JTAG_ISP_TCK

JTAG_ISP_TDI

SMC_WAKE_SCI_L

DPMUX_UC_IRQ

FW_PME_L

FW_PWR_EN_PCH

PCH_CAM_RESET

JTAG_ISP_TCK

JTAG_ISP_TDO

PM_THRMTRIP_L_R

PCH_GPIO71

PCH_GPIO70

PCH_CAM_RESET

PCH_CAM_EXT_BOOT_L

051-0164

12.4.0

14 OF 123

14 OF 86

121

2

Y10

U12

R11

C16

BB4

AV1

AT8

AT7

AP1

AN6

AN4

AM3

AK3

AK1

AD11

AB11

A4

E45

E1

D1

BE3

BD44

BD2

BD1

BC1

BA1

B45

B44

B2

A44

A5

AN2

C14

A43

A2

Y1

BE2

BD45

AU4

A41

AN10

K13

G15

A14

F13

C45

BE5

BE41

H15

G13

D13

AY1

AV3

AT6

N10

B1

AT3

1 2

1 2 1 2

1 2

1

2

1 2

121

2

11 12 14 28 70

11 12 13 70

14

14 20

14 18

14

14 36

14

14 44 81

14 18

14 46

14 20

14 18

14 26

14

15 17 70

11 12 14 28 70

14

14 18 20

14 20

14 44 81

14

45

14

DCPSUS1

DCPSUSBYP

VCCADAC1_5

VSS

VCCVRM

VCCIO

VCCASW

VCC3_3

DCPSUS3

VCCSUS3_3

VCCADACBG3_3

VCC

CRT

USB3

CORE

PCIE/DMI

(7 OF 11)

FDI

HVCMOS

SATA

VCCMPHY

DCPSUS2

VCCUSBPLL

VCCSPI

DCPSST

VCCRTC

VSS

VCCVRM

VCCIO

VCCCLK3_3

VCCCLK

VCCASW

VCC3_3

VCC

V_PROC_IO

DCPRTC

VCCSUSHDA

VCCSUS3_3

VCCDSW3_3

VCCSUS3_3

VCCIO

VCCCLK

THERMAL

(8 OF 11)

GPIO/LPC

USB

HDARTCCPUSPI

CLK/MISC

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

10mA Max, 1mA Idle

VCCSUS3_3: 261mA Max, 6mA Idle

VGA DAC Disabled per SB DG v1.0 (Table 12-18).

VCC3_3: 133mA Max, 3mA Idle

VCCIO: 3629mA Max, 264mA Idle

VCCVRM: 183mA Max, 68mA Idle

15 mA Max, 1mA Idle

VCC3_3: 133mA Max, 3mA Idle

VCCASW: 670mA Max, 34mA Idle

22mA Max, 1mA Idle

4mA Max, 2mA Idle

VCCSUS3_3: 261mA Max, 6mA Idle

VCCASW: 670mA Max, 34mA Idle

VCC3_3: 133mA Max, 3mA Idle

??mA Max, ??mA Idle

NOTE: Pin name is VCC but really is 3.3V

VCCIO: 3629mA Max, 264mA Idle

VCCVRM: 183mA Max, 68mA Idle

Powered in DeepSx

VCC3_3: 133mA Max, 3mA Idle

VCCSUS3_3: 261mA Max, 6mA Idle

VCCCLK3_3: 55mA Max, 11mA Idle

VCC: 1.312 A Max, 130mA Idle

VCCIO: 3629mA Max, 264mA Idle

VCCCLK: 306mA Max, 89mA Idle

VCCVRM: 183mA Max, 68mA Idle

??mA Max, ??mA Idle

Current data from LPT EDS (doc #486708, Rev 1.0).

VCCASW: 670mA Max, 34mA Idle

6uA Max (3.0V, room temperature)

VCCIO: 3629mA Max, 264mA Idle

VCCSUS3_3: 261mA Max, 6mA Idle

CERM

10V

20%

C1532

BYPASS=U1100.A6:6.35mm

402

0.1UF

1UF

402

CERM

C1531

BYPASS=U1100.A6:6.35mm

6.3V

10%

CERM

10V

BYPASS=U1100.A6:6.35mm

402

20%

C1533

0.1UF

FCBGA

CKPLUS_WAIVE=PwrTerm2Gnd

MOBILE

LYNXPOINT

OMIT_TABLE

U1100

FCBGA

OMIT_TABLE

MOBILE

LYNXPOINT

U1100

1UF

PLACE_NEAR=R1550.1:2.54mm

CERM

402

C1550

6.3V

10%

1%

MF-LF

1/20W

5.11

PLACE_NEAR=U1100.U14:2.54mm

R1550

201

0201

X5R-CERM

10V

C1580

BYPASS=U1100.AA14:6.35mm

0.1UF

10%

0201

X5R-CERM

10V

C1590

BYPASS=U1100.P14:6.35mm

0.1UF

10%

PCH Power

SYNC_DATE=01/21/2013

SYNC_MASTER=J16_KENNY

=PP3V3_SUS_PCH_VCCSUS_GPIO

=PP3V3_S5_PCH_VCCDSW

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

PPVOUT_S0_PCH_DCPRTC

=PPVRTC_G3_PCH

MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

MIN_LINE_WIDTH=0.2 mm

PPVOUT_S0_PCH_DCPSST

=PP3V3_S0_PCH_VCC3_3_GPIO

=PP3V3R1V5_S0_PCH_VCCSUSHDA

=PP1V05_S0_PCH_VCCIO_GPIO

=PP3V3_SUS_PCH_VCC_SPI

=PP3V3_SUS_PCH_VCCSUS_RTC

=PP1V05_S0M_PCH_VCCASW

=PP1V5_S0_PCH_VCCVRM_THRM

=PP3V3_S0_PCH_VCC3_3_USB

PP1V05_S0_PCH_VCC_CLK_F

=PP1V5_S0_PCH_VCCVRM_CLK

=PP1V05_S0_PCH_VCCCLK_CLK135

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

PPVOUT_S5_PCH_DCPSUSBYP_R

MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

MIN_LINE_WIDTH=0.2 mm

PPVOUT_S5_PCH_DCPSUSBYP

=PP1V05_S0_PCH_VCCCLK_SSC100

=PP1V05_S0_PCH_VCCCLK_CLK100

=PP1V05_S0_PCH_VCCCLK_SSC

=PP3V3_S0_PCH_VCCCLK3_3

=PP3V3_S0_PCH_VCC3_3_THRM

=PP3V3_S0_PCH_VCC_FUSE

=PP1V05_S0_PCH_V_PROC_IO

=PP3V3_SUS_PCH_VCCSUS_USB

=PP1V05_S0M_PCH_VCCASW

=PP1V05_S0_PCH_VCC

=PP1V05_S0_PCH_VCCIO

=PP1V5_S0_PCH_VCCVRM_USB3

=PP3V3_SUS_PCH_VCCSUS_USB3

=PP3V3_S0_PCH_VCC3_3_HVCMOS

=PP1V05_S0_PCH_VCCIO_FDI

=PP1V5_S0_PCH_VCCVRM_SATA

=PP1V5_S0_PCH_VCCVRM_PCIE

=PP1V5_S0_PCH_VCCVRM_FDI

=PP1V05_S0_PCH_VCCIO_USB2

=PP1V05_S0_PCH_VCCUSBPLL

051-0164

12.4.0

15 OF 123

15 OF 86

212

1

2

1

Y12

U14

P45

P43

BE22

BB44

AN11

AK26

AM18

AK22

AK20

AK18

AT22

AR22

AP22

AN35

AN34

AM22

AM20

V22

V20

V18

U24

U22

U20

U18

AA18

Y22

Y20

Y18

V24

R32

R30

AD26

AD20

AA26

AG24

AG22

AG18

AE26

AE24

AE22

AE20

AE18

AD28

AJ28

AD24

AJ26

AJ30

AJ32

AD22

AG20

AK28

M31

AA24

Y26

Y35

U35

AD12

AA14

A6

M24

AW40

AF34

U26

R28

R26

Y30

V30

V28

U36

V32

U32

M29

M26

L29

L26

AG30

AE32

AE30

AD36

AD35

AA32

AA30

AG32

Y32

R18

L17

AK32

AK30

AG14

AE14

L24

AP45

P20

P18

AJ14

AJ12

P16

P14

A26

K8

A16

R22

AF12

R20R24

U30

AD34

2

1

1 2

2

1

2

1

17 70

11 12 70

17 70

70

17 70

15 17 70

17

17 70

17

17 70

14 17 70

17 70

15 17 70

17 70

17

70

17 70

17

17 70

VSS

(10 OF 11)

VSSVSS

(11 OF 11)

VSS

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

U1100

MOBILE

OMIT_TABLE

LYNXPOINT

FCBGA

U1100

LYNXPOINT

MOBILE

OMIT_TABLE

FCBGA

SYNC_MASTER=J16_KENNY

SYNC_DATE=01/21/2013

PCH Grounds

16 OF 86

16 OF 123

12.4.0

051-0164

Y8

Y40

Y36

Y34

Y28

Y24

Y16

Y14

W44

W2

V43

V26

V16

V14

U6

U42

U38

U34

U28

U16

U10

T43

R8

R44

R38

R34

R16

R14

R12

P32

P30

P28

P26

P22

N6

N39

N35

N12

M22

M17

L44

K39

B15

B11

AY7

AY29

AY26

AY20

AY15

AY10

F43

AW2

AV6

AV40

BB25

AV33

AV31

AV24

AV22

AV13

D42

AT38

AT29

AT26

AT20

AT17

AT15

AT10

AK16

AR2

AP43

AP31

AP24

AP13

AN42

AN40

AN36

AM16

AM32

AM30

AM28

AM26

AM24

AM14

AL8

AL38

AL34

P24

R2

AN8

L2

AT36

BC28

K33

K29

K20

K15

K10

H7

H40

H36

H31

H26

H24

H22

H17

H13

H10

G8

G44

G38

G2

F33

F29

F20

F15

AV7

BD7

BD39

BD35

BD31

BD11

BA40

B7

B39

B35

B23

B19

BB42

BC22

AL2

AL12

AK45

AK43

AK24

AK14

AJ8

AJ6

AJ38

AJ34

AJ24

AJ22

AJ20

AJ18

AJ16

AG44

AG28

AG26

AG2

AG16

AF8

AF38

AE28

AE16

AD8

AD6

AD40

AD32

AD30

AD18

AC2

AB8

AB38

AB34

AB12

AA4

AA22

AA20

AC44 AD14

AD16

D25

AT43

AY36

BD19

BD15

BC16 D4

B31

B27

AA16

AA28

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Not documented in EDS!

(PCH 1.05V CORE PWR)

670mA Max, 34mA Idle

PCH VCCASW BYPASS (PCH 1.05V ME CORE PWR)

(PCH 3.3V SUSPEND USB PWR)

(PCH 1.05V PCIe/DMI/SATA/USB3 PWR)

PCH VCCIO BYPASS

183mA Max, 68mA Idle

PCH VCC BYPASS (PCH 3.3V FUSE PWR)

PCH VCC BYPASS

(PCH 1.05V USB2 PWR)

PCH VCCCLK3_3 BYPASS

PCH VCCVRM BYPASS

PCH VCC3_3 BYPASS

(PCH 3.3V CLK PWR)

PCH VCCSUS3_3 BYPASS

PCH VCCSUSHDA BYPASS (PCH 3.3V/1.5V HDA PWR)

(PCH 3.3V SUSPEND RTC PWR)

(PCH 1.5V VCCVRM PWR)

PCH VCC3_3 BYPASS

(PCH 3.3V SPI PWR)

PCH VCCSPI BYPASS

(PCH 3.3V DSW PWR)

PCH VCCSUS3_3 BYPASS (PCH 3.3V SUSPEND PWR)

PCH VCCDSW3_3 BYPASS

(PCH 3.3V HVCMOS PWR)

PCH VCC3_3 BYPASS

??mA Max, ??mA Idle

PCH VCCIO BYPASS

(PCH 1.05V FDI PWR)

PCH V_PROC_IO BYPASS

PCH VCCIO BYPASS

PCH VCCCLK BYPASS (PCH 1.05V SSC PWR)

(PCH 1.05V DIFFCLK PWR)

PCH VCCCLK BYPASS

(PCH 1.05V SSC100 PWR)

PCH CLK VCC BYPASS (PCH 1.05V CLK PLL PWR)

Current data from LPT EDS (doc #486708, Rev 1.0).

(PCH 3.3V GPIO/LPC PWR)

PCH VCCCLK BYPASS

PCH VCC3_3 BYPASS (PCH 3.3V USB2 PWR)

(PCH 1.05V DIFFCLK135 PWR)

(PCH 1.05V CPU I/F PWR)

PCH VCCUSBPLL BYPASS (PCH 1.05V USB2 PLL PWR)

(PCH 3.3V THERMAL PWR)

20%

1UF

0201

X5R

10V

C1720

BYPASS=U1100.L26:6.35mm

20%

1.0UF

0201-1

X5R

6.3V

C1708

BYPASS=U1100.K8:6.35mm

0201

10V X5R-CERM

C1710

BYPASS=U1100.A26:6.35mm

0.1UF

10%

20%

0402-1

C1740

10UF

10V X5R-CERM

BYPASS=U1100.AF34:12.7mm

20%

0402-1

X5R-CERM

10V

10UF

C1755

BYPASS=U1100.AG18:12.7mm

20%

10UF

10V X5R-CERM 0402-1

C1760

BYPASS=U1100.AK18:12.7mm

20%

0402-1

X5R-CERM

10V

10UF

C1790

NO STUFF

BYPASS=U1100.AP45:12.7mm

20%

PLACE_NEAR=U1100.V20:2.54mm

0402

4V

C1750

20UF

X5R-CERM

0201

6.3V

C1774

BYPASS=U1100.U30:6.35mm

CERM-X5R

0.1UF

10%

0201

6.3V

C1786

BYPASS=U1100.AJ12:6.35mm

CERM-X5R

0.1UF

10%

20%

1.0UF

0201-1

X5R

6.3V

C1758

BYPASS=U1100.AE18:6.35mm

0201

6.3V

C1787

BYPASS=U1100.AJ12:6.35mm

CERM-X5R

0.1UF

10%

0201

6.3V

C1770

BYPASS=U1100.U35:6.35mm

CERM-X5R

0.1UF

10%

20%

1.0UF

0201-1

X5R

6.3V

PLACE_NEAR=U1100.V20:2.54mm

C1752

20%

1.0UF

0201-1

X5R

6.3V

PLACE_NEAR=U1100.V20:2.54mm

C1751

20%

1.0UF

0201-1

X5R

6.3V

C1757

BYPASS=U1100.AD20:6.35mm

20%

1.0UF

0201-1

X5R

6.3V

C1756

BYPASS=U1100.AA24:6.35mm

20%

1.0UF

0201-1

X5R

6.3V

C1777

BYPASS=U1100.AG30:6.35mm

20%

1.0UF

0201-1

X5R

6.3V

C1776

BYPASS=U1100.AE30:6.35mm

20%

1.0UF

0201-1

X5R

6.3V

C1791

BYPASS=U1100.AP45:6.35mm

0603

4.7UH-170MA-0.321OHM

CRITICAL

OMIT_TABLE

L1790

20%

1.0UF

0201-1

X5R

6.3V

C1778

BYPASS=U1100.AD35:6.35mm

1

5%

402

MF-LF

1/16W

R1790

20%

1.0UF

0201-1

X5R

6.3V

C1780

BYPASS=U1100.AD34:6.35mm

20%

1UF

0201

X5R

10V

C1721

BYPASS=U1100.L29:6.35mm

20%

1UF

0201

X5R

10V

C1722

BYPASS=U1100.M29:6.35mm

20%

1.0UF

0201-1

X5R

6.3V

C1782

BYPASS=U1100.AA30:6.35mm

20%

1UF

0201

X5R

C1723

10V

BYPASS=U1100.U32:6.35mm

0201

10V X5R-CERM

C1726

BYPASS=U1100.R30:6.35mm

0.1UF

10%

0201

X5R-CERM

10V

C1730

BYPASS=U1100.L24:6.35mm

0.1UF

10%

0201

X5R-CERM

10V

C1732

BYPASS=U1100.AK30:6.35mm

0.1UF

10%

0201

X5R-CERM

10V

C1700

BYPASS=U1100.A16:6.35mm

0.1UF

10%

20%

1.0UF

0201-1

X5R

6.3V

C1702

BYPASS=U1100.AD12:6.35mm

0201

10V

C1704

BYPASS=U1100.R20:6.35mm

X5R-CERM

0.1UF

10%

0201

10V X5R-CERM

C1706

BYPASS=U1100.R26:6.35mm

0.1UF

10%

20%

1.0UF

0201-1

X5R

6.3V

C1772

BYPASS=U1100.AN34:6.35mm

0201

10V X7R-CERM

C1728

BYPASS=U1100.AE14:6.35mm

0.01UF

10%

20%

1.0UF

0201-1

X5R

6.3V

C1734

BYPASS=U1100.P18:6.35mm

20%

1.0UF

0201-1

X5R

6.3V

C1785

BYPASS=U1100.AJ12:12.7mm

20%

1.0UF

0201-1

X5R

6.3V

C1761

BYPASS=U1100.AK18:6.35mm

20%

1.0UF

0201-1

X5R

6.3V

C1762

BYPASS=U1100.AK22:6.35mm

20%

1.0UF

0201-1

X5R

6.3V

C1763

BYPASS=U1100.AK20:6.35mm

20%

1.0UF

0201-1

X5R

6.3V

C1764

BYPASS=U1100.AM18:6.35mm

SYNC_MASTER=J16_KENNY

SYNC_DATE=01/21/2013

PCH DECOUPLING

L1790

RES,FF,0 OHM,(020OHM MAX),2A,0603

1

113S0022

=PP1V05_S0_PCH_VCCUSBPLL

=PP3V3_S0_PCH_VCC3_3_USB

=PP1V05_S0_PCH_V_PROC_IO

=PP1V05_S0_PCH_VCCIO_USB2

=PP1V05_S0_PCH_VCCCLK_CLK100

=PP1V05_S0_PCH_VCCIO

=PP3V3R1V5_S0_PCH_VCCSUSHDA

=PP3V3_SUS_PCH_VCCSUS_GPIO

=PP3V3_SUS_PCH_VCCSUS_RTC

=PP3V3_SUS_PCH_VCC_SPI

=PP3V3_S0_PCH_VCC3_3_GPIO

=PP3V3_S0_PCH_VCC_FUSE

=PP1V05_S0_PCH_VCCIO_FDI

=PP1V05_S0_PCH_VCCCLK_CLK135

=PP1V05_S0_PCH_VCCCLK_SSC

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

PP1V05_S0_PCH_VCC_CLK_R

=PP1V05_S0_PCH_VCC_CLK

=PP1V5_S0_PCH_VCCVRM_PCIE

=PP1V5_S0_PCH_VCCVRM_USB3

=PP3V3_S0_PCH_VCCCLK3_3

=PP3V3_S0_PCH_VCC3_3_THRM

=PP3V3_S5_PCH_VCCDSW

=PP3V3_SUS_PCH_VCCSUS_USB

=PP1V5_S0_PCH_VCCVRM_FDI

=PP1V5_S0_PCH_VCCVRM_BIAS

=PP3V3_S0_PCH_VCC3_3_HVCMOS

=PP1V05_S0_PCH_VCCCLK_SSC100

=PP1V5_S0_PCH_VCCVRM_SATA =PP1V5_S0_PCH_VCCVRM_CLK =PP1V5_S0_PCH_VCCVRM_THRM

=PP1V5_S0_PCH_VCCVRM

=PP1V05_S0_PCH_VCC

MIN_LINE_WIDTH=0.2 MM VOLTAGE=1.05V

PP1V05_S0_PCH_VCC_CLK_F

MIN_NECK_WIDTH=0.075 MM

=PP1V05_S0M_PCH_VCCASW

17 OF 123

051-0164

12.4.0

17 OF 86

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

21

2

1

1 2

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

15 70

14 15 70

15 70

70

15

15 70

15

11

15 70

15

70

15 70

15

15 70

IN

IN IN

OUT

IN IN

IN

OUT OUT

NC

IN

OUT

IN

BI IN

OUT

IN

OUT

IN

OUT OUT OUT

IN

OUT

IN

NC

IN IN

IN

TP

IN

TP

IN

BI IN

D

SYM_VER_3

S G G

D

S G

D

S

IN

G

D

SG

D

S

D

SYM_VER_3

S G

TP

IN

NC NC

IN

IN IN IN IN

IN

OUT

IN IN IN

IN OUT OUT OUT OUT OUT OUT

IN

NC NC

NC

BI

NC NC

IN

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

WF: SB DPDG says HOOK1 is BP_PWRGD_RST#

TDI and TMS are terminated in CPU.

NC per Intel DPDG.

from PCH to J1850 and path to non-XDP

’Output’ non-XDP signals require pulls.

OBSFN_B1

signal destination (to minimize stub).

SDA

OBSDATA_A1

PCH/XDP Signal Isolation Notes:

TDI

OBSDATA_B3

TCK1

Use with 921-0133 Adapter Flex to

NOTE: This is not the standard XDP pinout.

support chipset debug.

OBSDATA_C1

OBSDATA_C0

OBSDATA_C2 OBSDATA_C3

OBSFN_C0 OBSFN_C1

OBSFN_D0

OBSFN_A1

OBSDATA_A0 OBSDATA_A1

ITPCLK#/HOOK5

RESET#/HOOK6

ITPCLK/HOOK4

OBSDATA_D0 OBSDATA_D1

OBSDATA_D3

OBSDATA_D2

VCC_OBS_CD

TMS

TDO

TDI

TRSTn

VCC_OBS_AB

OBSDATA_B2 OBSDATA_B3

PWRGD/HOOK0

OBSDATA_B1

HOOK1

SCL

HOOK3

TCK0

OBSDATA_C2

OBSDATA_C1

OBSFN_C0

XDP_PRESENT#

DBR#/HOOK7

TRSTn

TDO

TMS

OBSDATA_B2

998-2516

SCL

TCK0

HOOK1

OBSDATA_B0

OBSFN_A0

OBSFN_C1

OBSDATA_C0

HOOK2

DBR#/HOOK7

signal path needs to split between route

OBSFN_D1

OBSDATA_A3

998-2516

PCH SIGNALS

OBSFN_B0

OBSDATA_A2

OBSFN_A0

CPU Micro2-XDP

’Output’ PCH/XDP signals require pulls.

(All 18 R’s)

R187x and R189x should be placed where

RESET#/HOOK6

TCK1

NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page

XDP_PRESENT#

Extra BPM Testpoints

To link CPU and PCH JTAG pull ICT_JTAG_EN to 5V (must be in S0)

XDP SIGNALS

support chipset debug.

Use with 921-0133 Adapter Flex to

NOTE: This is not the standard XDP pinout.

OBSDATA_D1

OBSFN_D0

OBSDATA_D0

OBSDATA_D2

OBSFN_D1

OBSDATA_C3

PCH Micro2-XDP

SDA

OBSFN_A1

OBSDATA_A0

OBSDATA_A3

OBSFN_B1

OBSFN_B0

OBSDATA_B1

OBSDATA_B0

VCC_OBS_AB

HOOK2 HOOK3

OBSDATA_A2

PWRGD/HOOK0

CPU-PCH JTAG Chain Support

VCC_OBS_CD

NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page

ITPCLK#/HOOK5

ITPCLK/HOOK4

OBSDATA_D3

6

78

6

14 76

6

78

6

78

8

6

72 78

6

72 78

11 18 78

6

72 78

11 18 78

6

72 78

18 47

6

18 19

C1880

20%

402

CERM

10V

0.1UF

XDP

C1881

20%

402

CERM

10V

0.1UF

XDP

12 18 44

12 45 69

6

18 78

6

18 19

6

78

6

18

6

78

6

18 78

5%

R1830

1/16W MF-LF

402

150

5%

201

1/20W

MF

XDP

1K

R1805

5%

201

1/20W

MF

12

R1820

PLACE_NEAR=J1800.51:5MM

51

XDP

5%

201

1/20W

MF

12

R1823

51

XDP

5%

201

1/20W

MF

12

R1824

51

XDP

5%01/20W

MF

0201

R1802

XDP

5%

201

1/20W

MF

R1800

XDP

1K

PLACE_NEAR=U0500.AB35:16.5mm

6

78

5%

201

1/20W

MF

R1884

PLACE_NEAR=J1850.40:2.54mm

XDP

1K

5%01/20W

MF

0201

R1885

XDP

PLACE_NEAR=U5000.J3:2.54mm

12 69

12 18 44

J1800

M-ST-SM

DF40RC-60DP-0.4V

CRITICAL XDP_CONN

DF40RC-60DP-0.4V

CRITICAL XDP_CONN

J1850

M-ST-SM

C1801

402

20% CERM

10V

0.1UF

XDP

6

78

C1800

0.1UF

20% 10V

402

CERM

XDP

6

78

6

78

6

78

6

78

5%

R1831

1K

1/16W

402

MF-LF

XDP

6

78

6

78

TP1802

TP-P6

TP1803

TP-P6

TP1805

TP-P6

TP1804

TP-P6

6

78

6

78

TP1807

TP-P6

TP1806

TP-P6

6

78

6

78

6

PLACE_NEAR=J1850.55:5.08mm

DFN1006H4-3

DMN32D2LFB4

Q1848

Q1846

SOT-563

PLACE_NEAR=J1850.58:5.08mm

DMN5L06VK-7

Q1846

DMN5L06VK-7

SOT-563

PLACE_NEAR=J1850.57:6mm

6

76

Q1840

PLACE_NEAR=J1800.57:5.08mm

DMN5L06VK-7

SOT-563

Q1840

DMN5L06VK-7

PLACE_NEAR=J1800.58:5.08mm

SOT-563

Q1842

DMN32D2LFB4

DFN1006H4-3

PLACE_NEAR=J1800.51:5.08mm

TP1840

TP-P6

TP1841

TP-P6

5%

201

1/20W

MF

R1845

1K

TP1845

TP-P6

5%

201

1/20W

MF

R1842

1M

5%

201

1/20W MF

R1841

1M

6

76

5%

201

1/20W MF

R1840

1M

6

78

13 42

13 43

13

13 37

11 29 30

11

14

14 20

14

11 35

11 32

14 67

3

14

13 43

13 42

5%

0

R1892

MF-LF

NOSTUFF

1/16W

402

C1804

20%

402

CERM

10V

0.1UF

XDP

6

78

C1806

XDP

0.1UF

20% 10V

CERM

402

5%

201

1/20W

MF

R1804

XDP

220

5%

201

1/20W MF

R1867

XDP

J1850.51:5mm

100

5%

201

1/20W MF

U1100.W40:20MM

100

R1869

XDP

5%

201

1/20W MF

R1868

U1100.W39:21MM

XDP

100

NONE

R1890

NONE

402

SHORT

NONE

OMIT

NONE

R1893

402

NONENONE

OMIT

SHORT

R1895

NONE

402

NONE NONE

OMIT

SHORT

R1894

402

NONE NONE NONE

SHORT

OMIT

R1897

402

NONE NONE NONE

OMIT

SHORT

R1896

402

NONENONE NONE

OMIT

SHORT

R1881

402

SHORT

NONE NONENONE

OMIT

R1880

402

NONENONE

OMIT

SHORT

NONE

R1883

NONENONENONE

SHORT

402

OMIT

R1873

402

NONE NONE

OMIT

SHORT

NONE

R1872

NONE

SHORT

402

NONE NONE

OMIT

R1874

402

SHORT

NONE NONE NONE

OMIT

R1875

402

SHORT

NONE NONENONE

OMIT

R1878

402

SHORT

NONE NONENONE

OMIT

R1879

402

SHORT

NONE NONE

OMIT

NONE

R1882

NONENONENONE

SHORT

402

OMIT

R1886

NONE

SHORT

402

NONENONE

OMIT

R1887

NONENONE

SHORT

402

NONE

OMIT

18 47

201

1/20W MF

U1100.W39:4mm

210

R1861

1%

XDP

201

1/20W MF

1%

210

J1850.51:2.54mm

R1860

XDP

18 47

5%

201

1/20W MF

XDP

R1866

51

201

1/20W MF

U1100.W40:3.5mm

R1862

1%

210

XDP

12 20 39 69

5%

201

1/20W

MF

XDP

R1870

1K

6

18 78

6

14 76

6

78

6

78

SYNC_MASTER=J16_KENNY

SYNC_DATE=03/18/2013

CPU & PCH XDP

=PP3V3_S5_XDP

XDP_FC1_GPU_GOOD

XDP_DC1_SATARDRVR_EN

XDP_DC3_JTAG_ISP_TCK

XDP_DD2_ENET_CLKREQ_L

PM_PCH_PWROK

XDP_PM_PCH_PWROK

XDP_PCH_TDO

XDP_DD1_PCH_GPIO49

XDP_DD3_AP_CLKREQ_L

TP_XDP_PCH_TRST_L

XDP_DBRESET_L

XDP_PCH_TCK

VOLTAGE=3.3V

MAX_NECK_LENGTH=3MM

PP3V3_S5_XDP_R

MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.2MM

XDP_PCH_TDO XDP_PCH_TDI

=SMBUS_XDP_SCL

XDP_PCH_PWRBTN_L

XDP_PCH_S5_PWRGD

XDP_DB3_SDCONN_STATE_CHANGE_L

XDP_DB1_USB_EXTD_OC_L

XDP_DA2_PCH_GPIO41

XDP_DB2_PCH_GPIO10

XDP_PCH_TMS

XDP_DB0_USB_EXTB_OC_L

XDP_PCH_TCK

XDP_DA3_PCH_GPIO42

XDP_DA0_USB_EXTA_OC_L

XDP_DD0_PCH_GPIO16

XDP_DC2_PCH_GPIO36

XDP_DD3_AP_CLKREQ_L

XDP_FC0_HDD_PWR_EN

XDP_BPM_L<4>

ICT_JTAG_EN

CPU_RESET_L

XDP_BPM_L<5>

USB_EXTC_OC_L

PCH_GPIO42

XDP_DD0_PCH_GPIO16

XDP_DBRESET_L

XDP_CPU_TMS

XDP_CPU_TDI

XDP_CPU_TRST_L

XDP_CPU_TDO

CPU_PWR_DEBUG

XDP_CPU_PWRGD

XDP_CPU_TCK

PM_PWRBTN_L

CPU_CFG<13>

CPU_CFG<15>

XDP_CPU_TRST_L

=PP1V05_S0_XDP

XDP_PCH_TDI

PCH_GPIO36

XDP_CPU_TCK

XDP_DA0_USB_EXTA_OC_L

XDP_CPU_PWRBTN_L

PCH_GPIO16

CPU_CFG<2>

=PP1V05_S0_XDP

XDP_CPU_PRDY_L

CPU_CFG<0>

CPU_CFG<5>

CPU_CFG<7>

GPU_GOOD

SDCONN_STATE_CHANGE

PCH_GPIO49

HDD_PWR_EN

AP_CLKREQ_L

DP_AUXIO_EN SATARDRVR_EN

XDP_FC1_GPU_GOOD

XDP_FC0_HDD_PWR_EN

XDP_DB2_PCH_GPIO10

XDP_CPU_TDO

XDP_CPU_TMS

XDP_PCH_TDI

XDP_PCH_TCKXDP_CPU_TCK

XDP_PCH_TMS

XDP_CPU_PCH_TCK

XDP_CPU_PCH_TMS

CPU_CFG<12>

PM_PWRBTN_L

=SMBUS_XDP_SCL

PM_RSMRST_PCH_L

XDP_BPM_L<0>

CPU_CFG<4>

XDP_CPU_PREQ_L

XDP_BPM_L<7>

XDP_BPM_L<6>

XDP_BPM_L<3>

XDP_BPM_L<2>

CPU_CFG<17>

CPU_CFG<8>

CPU_CFG<16>

CPU_CFG<9>

CPU_CFG<10> CPU_CFG<11>

CPU_CFG<18>

CPU_CFG<19>

=SMBUS_XDP_SDA

CPU_CFG<6>

XDP_BPM_L<1>

CPU_CFG<3>

CPU_CFG<1>

USB_EXTA_OC_L

XDP_DB3_SDCONN_STATE_CHANGE_L

XDP_DC2_PCH_GPIO36

XDP_DD1_PCH_GPIO49 XDP_DD2_ENET_CLKREQ_L

XDP_DC3_JTAG_ISP_TCK

XDP_DB1_USB_EXTD_OC_L

=PP3V3_S5_XDP

ENET_CLKREQ_L

JTAG_ISP_TCK

USB_EXTD_OC_L

PCH_GPIO41

CPU_PWRGD

=SMBUS_XDP_SDA

XDP_CPU_PRESENT_L

XDP_CPU_TDO_PCH_TDI

XDP_CPURST_L

CPU_CFG<14>

XDP_DA1_USB_EXTC_OC_L

XDP_DA3_PCH_GPIO42

USB_EXTB_OC_L

PCH_GPIO10

XDP_DA2_PCH_GPIO41

XDP_DB0_USB_EXTB_OC_L

XDP_DA1_USB_EXTC_OC_L

XDP_VR_READY

PPVCCIO_S0_CPU

XDP_CPU_TDO

PM_PCH_SYS_PWROK

XDP_DC0_DP_AUXCH_ISOL_L XDP_DC1_SATARDRVR_EN

XDP_DC0_DP_AUXCH_ISOL_L

XDP_PCH_TMS

18 OF 123

18 OF 86

051-0164

12.4.0

2

1

2

1

2

1 2

53

51

43

41

35

29

23

19

17

15

11

7

5

9

3

2

13

10 12

14

16

8

1

21

27

33

37 39

45

47

49

57

55

59

6

20

22 24

26

32

30

38

42

44

48

46

50 52

54

58

56

60

28

40

18

4

34

36

25

31

61

62

6364

53

51

43

41

35

29

23

19

17

15

11

7

5

9

3

2

13

10

12 14

16

8

1

21

27

33

37

39

45 47

49

57

55

59

6

20

22

24 26

32

30

38

42

44

48

46

50 52

54

58

56

60

28

40

18

4

34 36

25

31

61

62

6364

2

1

2

1

2

1

3

1

2 1

6

2

4

3

5

4

3

5

1

6

2

3

1

2

1

2

1

121

2

1

2

1 2

2

1

2

1

1 2

1

2

1

2

1

2

1 2 1 2

1 2

1 2 1 2 1 2 1 2 1 2

1 2 1 2

1

2

1

2

1

2

1

2

1 2

18 70

18

11 18 78

18

6

18 78

6

18

18 70

18

18 70

18

6

18 78

6

18 78

11 18 78

6

18 78

11 18 78

18

18 70

18

5 6 8

10 61

6

18 78

18

11 18 78

IN

OUT

GND

VDD

25MHZ_A

VDDIO_B

VDDIO_A

VDDIO_C

25MHZ_B 25MHZ_C

THRM

XIN

XOUT

PAD

NCNC

NC

IN

OUT

IN

OUT

S

G

D

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PCH RTC Crystal

Coin-Cell Holder

If high, ME is disabled. This allows for full re-flashing of SPI ROM.

PCH ME Disable Strap

SMC controls strap enable to allow in-field control of strap setting.

SB XTAL Power

RTC Power Sources

System 25MHz Clock Generator

PCH Reset Button

PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.

511S0054

NOTE: 30 PPM crystal required

TBT XTAL Power

GreenClk 25MHz Power

VDD must be powered if any VDDIO is.

Ethernet XTAL Power

ENET > S0 > TBT, so ENET is used here.

Place TP1901-TP1903 on bottom side

Clock series termination

6

18

0

MF-LF

5%

402

1/16W

XDP

R1996

SILK_PART=SYS RESET

OMIT

0

1/16W MF-LF 402

5%

R1997

4.7K

5% 1/16W MF-LF 402

R1995

12 44

26 79

TDFN

CRITICAL

SLG3NB146V

U1900

CERM

1UF

402

C1902

6.3V

10%

CERM

10V

20%

402

C1920

0.1UF

402

CERM

20%

10V

C1922

0.1UF

402

20%

10V

CERM

C1924

0.1UF

SOT-363

BAT54DW-X-G

D1900

NOSTUFF

5% 1/16W

402

1M

MF-LF

R1906

0

5%

MF-LF

1/16W

402

R1905

1.97X2.02MM-NSP

OMIT

SMT-PAD

TP1901

OMIT

1.4-SQ-NSP

SM-PAD

TP1903

SMT-PAD

OMIT

1.97X2.02MM-NSP

TP1900

1.4-SQ-NSP

OMIT

SM-PAD

TP1902

5%

50V

PLACE_NEAR=Y1910.1:2MM

12PF

0402

C0G-CERM

C1911

CRITICAL

SM-HF

32.768K-12.5PF

Y1910

402

MF-LF

0

1/16W

5%

R1910

5%

50V

0402

C0G-CERM

12PF

C1905

3.2X2.5MM-SM

CRITICAL

25.000MHZ-20PPM-12PF-85C

Y1905

0402

C0G-CERM

50V

5%

12PF

C1906

1K

402

MF-LF

5%

1/16W

R1902

2 1

BB10201-C1403-7H

SM

J1900

5%

MF-LF

402

10M

1/16W

R1911

11 79

44 79

11 79

46 79

35 79

R1955

MF-LF

402

33

5%

1/16W

PLACE_NEAR=U1100:10MM

402

1/16W

5%

33

MF-LF

R1956

PLACE_NEAR=U1100:10MM

PLACE_NEAR=U1100:13MM

MF-LF

402

5%

1/16W

33

R1959

PLACE_NEAR=U1900.4:10MM

R1958

33

5%

1/16W

402

MF-LF

11 79

402

MF-LF1/16W

5%

330

PLACE_NEAR=R1113.2:15MM

R1921

SOT23-3-HF

NTR1P02L

Q1920

44

11 79

C0G-CERM

0402

50V

5%

12PF

PLACE_NEAR=Y1910.4:2MM

C1910

Chipset Support

SYNC_MASTER=J16_KENNY

SYNC_DATE=01/21/2013

SYSCLK_CLK25M_ENET_R

PCH_CLK33M_PCIOUT

LPC_CLK33M_LPCPLUS_R

LPC_CLK33M_SMC_R

SYSCLK_CLK25M_ENET

=PP3V3_G3H_RTC_D

PCH_CLK32K_RTCX2_R

=PP3V3_ENET_SYSCLK

LPC_CLK33M_SMC

SYSCLK_CLK25M_TBT

=PPVDDIO_TBT_CLK

=PP1V5_S0_PCH_CLK

=PPVDDIO_ENET_CLK

PP3V3_G3_RTC

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=3.3V

SYSCLK_CLK25M_X2

PCH_CLK32K_RTCX2

PPVBATT_G3_RTC

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 MM

RTC_RESET_L

PCH_CLK32K_RTCX1

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 mm

PPVBATT_G3_RTC_R

VOLTAGE=3.3V

XDP_DBRESET_L

PM_SYSRST_L

SYSCLK_CLK25M_X1

=PP3V3_S5_PCH

SPI_DESCRIPTOR_OVERRIDE_L

=PP3V3_S0_PCH

SYSCLK_CLK25M_ENET_R

SYSCLK_CLK25M_SB

SYSCLK_CLK25M_X2_R

PCH_CLK33M_PCIIN

LPC_CLK33M_LPCPLUS

SPI_DESCRIPTOR_OVERRIDE_R

HDA_SDOUT_R

051-0164

12.4.0

19 OF 123

19 OF 86

1 2

1

2

1

2

9

2

5

367

4 8

11

1

10

2

1

2

1

2

1

2

1

3

6

2

4

1

5

1

2

1 2

1

1 2

41

1 2

42

1 3

1 2

1

2

1

2

1 2

2

1

3

1 2

19 79

70

79

70

11 70

70

79

11 45

79

20 70

13 70

19 79

79

OUT

IN

OUT

IN

OUT

IN

OUT

Y

B

A

IN

08

Y1

Y2

GND

B2

VCC

A1 B1 A2

OUT

IN

08

Y1

Y2

GND

B2

VCC

A1 B1 A2

OUT

IN

D

SYM_VER_3

S G S

D

G S

D

G

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Platform Reset Connections

Unbuffered

Buffered

R2074 for current limit if PCH glitches

TBT_PWR_EN goes high for JTAG Programming

NOTE: TCK from PCH is Push-Pull CMOS

NOTE: TDO from CR is Push-Pull CMOS

JTAG GPIO Isolation due to glitch in and out of sleep

NOTE: TMS/TDI from PCH is Open Drain

GPIO Glitch Prevention

14

12

R2074

5%

MF

1/20W

1K

201

12 44 46

46

44 81

21 22

28

32

37

R2081

5%

33

MF-LF

402

1/16W

R2055

33

1/16W

5%

MF-LF

402

12

R2094

5%

33

1/16W MF-LF

402

R2088

402

1/16W MF-LF

5%

33

MF-LF

1/16W

402

33

5%

R2091

33

5%

402

R2092

MF-LF

1/16W

100K

R2080

5% 1/16W

402

MF-LF

U2080

CRITICAL

SOT23-5-HF

MC74VHC1G08

20% 10V

402

0.1UF

CERM

C2080

56

0201

CERM-X5R

C2040

6.3V

0.1UF

10%

12

5%

R2095

33

402

MF-LF

1/16W

33

EXT_GPU:YES

5%

MF-LF

R2090

33

402

1/16W

72

1

MF5%

1/20W

2

10K

R2060

201

402

5%

1/16W

33

MF-LF

R2093

32

U2040

CRITICAL

SOT665

TC7SZ08FEAPE

13

12 18 20 39 69

12

74LVC2G08GT

8

4

U2050

SOT833

CRITICAL

C2050

20%

402

CERM

10V

0.1UF

20 26

35 37

20 26

14 18

20 26

8

4

U2000

SOT833

74LVC2G08GT

CRITICAL

C2013

X5R-CERM 0201

16V

0.1UF

10%

26

14

Q2062

CRITICAL

DFN1006H4-3

DMN32D2LFB4

CRITICAL

DMN5L06VK-7

SOT-563

Q2060

R2062

10K

MF

5% 1/20W

201

R2061

10K

MF

5% 1/20W

201

SOT-563

CRITICAL

DMN5L06VK-7

Q2060 R2063

1/20W

5% MF

10K

201

26

SYNC_MASTER=J16_KENNY

SYNC_DATE=01/21/2013

Project Chipset Support

=PP3V3_S5_PCH

PM_PCH_PWROK

AUD_IPHS_SWITCH_EN

AUD_IPHS_SWITCH_EN_PCH

LPC_PWRDWN_L

PLT_RST_BUF_L

BT_RESET_MASK_L

=PP3V3_S0_RSTBUF

PLT_RESET_L

MAKE_BASE=TRUE

TBT_PLT_RST_L

MAKE_BASE=TRUE

TBT_CIO_PLUG_EVENT

SSD_RESET_L

TBT_CIO_PLUG_EVENT

=PP3V3_S5_PCH

TBT_CIO_PLUG_EVENT_BUF

TBT_CIO_PLUG_EVENT_ISOL

=PP3V3_TBT_PCH_GPIO

=PP3V3_S5_PCH

TBT_PWR_EN

ENET_SD_RESET_L

JTAG_ISP_TDO

JTAG_ISP_TDI

JTAG_TBT_TMS_PCH

JTAG_TBT_TDO

JTAG_TBT_TDI

JTAG_TBT_TMS

ENET_LOW_PWR

PM_PCH_PWROK

ENET_LOW_PWR_PCH

TBT_PWR_EN_PCH

JTAG_ISP_TCK

JTAG_TBT_TCK

MAKE_BASE=TRUE

SMC_LRESET_L

DEBUG_RESET_L

PCA9557D_RESET_L

=TBT_RESET_L

AP_RESET_L

TP_GPU_RESET_L

051-0164

12.4.0

20 OF 123

20 OF 86

1 2

1

2

5

1

2

3

4

2

1

2

1

1 2

3

5

1

4

2

3

71

2

5

6

2

1

3

71

2

5

6

2

1

3

1

2

5

4

3

1

2

1

2

1

6

1

2

19 20 70

12 18 20 39 69

70

20 26

19 20 70

70

19 20 70

OUT

IN

OUT

D

SG

D

SG

D

SG

NC

IN

D

GS

D

SG

IN

NC

08

IN

NC

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

MEM S0 "PGOOD" FOR CPU

PM_MEM_PWRGD MUST ASSERT MIN 100 NS AFTER MEM_VDDQ RAMPS 80% THIS IS GUARANTEED BY THE 2 V/MS RAMP RATE OF THE FET

MEMVTT_EN = PLT_RESET_L * PM_SLP_S3_L

PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page

ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals.

WHEN LOW: CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.

must de-assert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L.

5 0 1 1 0 (*) 1 1

1 0 1 1 1 1 1

to

6 0 1 1 1 1 1

(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO.

transition. Rails will power-up as if from S3, but MEM_RESET_L will not properly assert. Software

60mW max power

S0 to S3

S0

NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0

75mA max load @ 0.75V

0 1 1 1 1 CPU_MEM_RESET_L 1

Step ISOLATE_CPU_MEM_L PLT_RESET_L PM_SLP_S3_L CPU_MEM_RESET_L MEM_RESET_L MEMVTT_EN

MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L

7 1 1 1 1 CPU_MEM_RESET_L 1

4 0 0 1 X 1 0

3 0 0 0 X 1 0

2 0 0 1 1 1 0

WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated.

The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well

Ensures CKE signals are held low in S3

MEMVTT Clamp

as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary.

21 68

402

MF-LF

100K

1/16W

5%

R2115

23 24 75

402

1K

5%

MF-LF

1/16W

R2116

21 68

402

1/16W

100K

5%

MF-LF

R2151

0402

20%

0.001UF

CERM

50V

NOSTUFF

C2151

5%

603

10

1/10W MF-LF

R2150

6

12

16V

10%

0.1UF

X7R-CERM 0402

C2116

SOT563

CRITICAL

SSM6N15AFE

Q2115

SSM6N15AFE

SOT563

CRITICAL

Q2150

SSM6N15AFE

SOT563

CRITICAL

Q2150

SC70

74LVC1G07

CRITICAL

U2120

0.01UF

0402

X7R-CERM

16V

20%

C2121

71

VESM

CRITICAL

SSM3K15AMFVAPE

Q2116

SOT563

CRITICAL

SSM6N15AFE

Q2115

14

10K

5% 1/16W MF-LF

402

R2118

3

44 69

20 22

74LVC1G08

SOT891

U2110

0

5%

MF-LF

1/16W

402

NOSTUFF

R2112

12 36 44 45 68 69

X7R-CERM

16V

20%

0.01UF

0402

C2110

6

CPU Memory S3 Support

SYNC_MASTER=J16_NICK SYNC_DATE=12/11/2012

=PM_PGOOD_MEM_S0

CPU_MEM_RESET_L

MAKE_BASE=TRUE

=MEM_RESET_L

ALL_SYS_PWRGD

ISOLATE_CPU_MEM_L

=PP3V3_S4_MEMRESET

=PPDDRVTT_S0_CLAMP

MEMVTT_EN

PM_MEM_PWRGD

MIN_NECK_WIDTH=0.25mm

VTTCLAMP_L

MIN_LINE_WIDTH=0.25mm

VTTCLAMP_EN

=PPVDDQ_S3_MEMRESET

MEM_RESET_L

ISOLATE_MEM_5V

=PP5V_S4_MEMRESET

MEMRESET_ISOL_LS5V_L

PCA9557D_RESET_L

MEMVTT_EN

PM_SLP_S3_L

=PP3V3_S4_MEMRESET

=PP3V3_S4_PM

051-0164

12.4.0

21 OF 123

21 OF 86

1

2

1

2

1

2

1

2

1

3

4

5

6

1

2

3

4

5

4

1 3

2

5

2

1

2

3

6

1

2

1

2

3

6

2

1

4

5

12

2

1

21 70

70

22

21 70

70

OUT

V-

V+

V-

V+

IN

G

D

SG

D

SG

D

S G

D

S

IN

G

D

SG

D

SG

D

SG

D

S

IN

RESET*

A0 A1 A2

SCL SDA

P0 P1 P2

P5 P6 P7

P3 P4

THRM

VCC

GND

PAD

NC

IN

BI

VDD

VOUTD

VOUTC

VOUTB

VOUTA

SCL

SDA

A0

A1

GND

IN

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

NOTE: DDR3 assumes TPS51916 supply with 10.0k/49.9k divider

2.575mV / step @ output

+36uA - -36uA (- = sourced)

1.199V - 1.801V (+/- 301mV)

1.200V - 1.800V (+/- 300mV)

NOTE: CPU DAC output step sizes:

3.923mV / step @ output

+28uA - -29uA (- = sourced)

0.950V - 1.750V (+/- 400mV)

0.932V - 1.760V (+/- 414mV)

1.343V (DAC: 0x68 = 1.341V)1.500V (DAC: 0x74 = 1.495V) DDR3L assumes TPS51916 supply with 19.6k/57.6k divider

- DDRVREF_DAC - Stuffs DAC margining circuit.

- =PPDDR_S3_MEMVREF

0.000V - 3.004V (0x00 - 0xE9)

0.299V - 1.206V (+/- 453mV)

0.275V - 1.075V (+/- 400mV)

0.675V (DAC: 0x34 = 0.670mV)

0.000V - 2.707V (0x00 - 0xD2)

5

D

MEM VREG

MEM B VREF CAMEM A VREF CAMEM B VREF DQMEM A VREF DQ

DDR3 (1.5V)

0.750V (DAC: 0x3A = 0.747mV)

0.300V - 1.200V (+/- 450mV)

0.000V - 1.354V (0x00 - 0x69)

0.269V - 1.083V (+/- 406mV)

+811uA - -816uA (- = sourced)

7.67mV / step @ output 7.68mV / step @ output

0.000V - 1.508V (0x00 - 0x75)

+901uA - -911uA (- = sourced)

Margined range:

DAC range:

DDR3L (1.35V)

4

C

DDR3L (1.35V)

3

C

2

B

DDR3 (1.5V)

A

1

PCA9557D Pin:

DAC Channel:

Nominal value

Margined target:

Addr=0x30(WR)/0x31(RD)

RST* on ’platform reset’ so that system

NOTE: Margining will be disabled across all

and disables margining after platform reset.

DAC-Based Margining

ISOLATE_CPU_MEM_L is low

DAC margining VREFCA ensure

margining support. When

VREFCA. Split into two

soft-resets and sleep/wake cycles.

watchdog will disable margining.

Q2265 pin 6:

VRef Dividers

Power aliases required by this page:

Signal aliases required by this page:

- =I2C_VREFDACS_SDA

- =I2C_PCA9557D_SDA

- =I2C_PCA9557D_SCL

- =I2C_VREFDACS_SCL

BOM options provided by this page:

(All 4 R’s)

DAC sets voltage level, PCA9557 & FETs enable outputs

FETs for CPU isolation during S3

NOTE: MEMVREG and FRAMEBUF share

- =PP3V3_S3_VREFMRGN

to remove short due to CPU.

signals for independent DAC

NOTE: CPU has single output for

DDR3 (1.5V) 7.70mV per step DDR3L (1.35V) 6.99mV per step

(OD)

Addr=0x98(WR)/0x99(RD)

both at the same time!

Pins B1 & B4:

Page Notes

DAC step size:

VRef current:

CPU-Based Margining

R22x6 pin 2:

a DAC output, cannot enable

Q2225 pin 6:

of margining option.

Always used, regardless

EN RC’s to avoid drain glitches

63

0201

CERM-X5R

DDRVREF_DAC

C2202

6.3V

0.1UF

10%

1%

33.2K

1/16W MF-LF

402

DDRVREF_DAC

R2214

DDRVREF_DAC

MF

1/20W

100K

5%

R2213

201

DDRVREF_DAC

MF

1/20W

100K

5%

R2215

201

DDRVREF_DAC

CRITICAL

UCSP

MAX4253

CKPLUS_WAIVE=unconnected_pinsCKPLUS_WAIVE=unconnected_pins

U2204

B1

B4

MAX4253

CRITICAL DDRVREF_DAC

UCSP

U2204

B1

B4

OMIT

NONE NONE

NONE

402

SHORT

R2218

7

21

DMN5L06VK-7

CRITICAL

SOT-563

Q2260

100K

DDRVREF_DAC

MF

1/20W

5%

R2202

201

DMN5L06VK-7

CRITICAL

SOT-563

Q2220

DMN5L06VK-7

CRITICAL

SOT-563

Q2260

CRITICAL

DMN5L06VK-7

SOT-563

Q2220

7

CRITICAL DDRVREF_DAC

DMN5L06VK-7

SOT-563

Q2225

PLACE_NEAR=Q2220.6:5mm

DDRVREF_DAC

R2201

100K

1/20W

MF

5%

201

DDRVREF_DAC

100K

402

5%

MF-LF

1/16W

R2225

402

CERM

10V

20%

DDRVREF_DAC

C2225

0.1UF

CRITICAL

DMN5L06VK-7

DDRVREF_DAC

SOT-563

Q2265

PLACE_NEAR=Q2260.6:5mm

C2245

CERM

DDRVREF_DAC

20% 10V

402

0.1UF

100K

402

5%

MF-LF

1/16W

DDRVREF_DAC

R2245

100K

DDRVREF_DAC

402

5%

MF-LF

1/16W

R2265

DMN5L06VK-7

CRITICAL DDRVREF_DAC

SOT-563

Q2225

DDRVREF_DAC

402

CERM

10V

20%

C2265

0.1UF

DMN5L06VK-7

CRITICAL DDRVREF_DAC

SOT-563

Q2265

DDRVREF_DAC

20% 10V

CERM

402

C2285

0.1UF

DDRVREF_DAC

MF

1/20W

5%

100K

R2207

201

100K

5%

DDRVREF_DAC

402

MF-LF

1/16W

R2285

DDRVREF_DAC

MF

1/20W

5%

100K

R2208

201

R2226

1%

332

DDRVREF_DAC

1/16W

402

MF-LF

PLACE_NEAR=Q2225.1:5.5mm

1%

332

DDRVREF_DAC

1/16W

402

MF-LF

R2246

PLACE_NEAR=Q2265.4:5.5mm

402

MF-LF1/16W

1%

332

DDRVREF_DAC

R2266

PLACE_NEAR=Q2225.1:5.5mm

1%

332

DDRVREF_DAC

1/16W

402

MF-LF

R2286

PLACE_NEAR=Q2265.4:5.5mm

1M

DDRVREF_DAC

402

MF-LF

1/16W

5%

R2217

0201

X5R-CERM

10%

6.3V

C2280

0.022UF

PLACE_NEAR=Q2260.3:2mm

0201

X5R-CERM

10%

6.3V

C2260

PLACE_NEAR=Q2220.3:2mm

0.022UF

0201

X5R-CERM

10%

6.3V

C2240

0.022UF

PLACE_NEAR=Q2260.6:4MM

R2283

MF

1/20W

2

5%

PLACE_NEAR=C2280.1:2mm

201

24.9

1%

1/20W

MF

R2280

201

1K

402

MF-LF

1/16W

1%

PLACE_NEAR=R2281.2:1mm

R2282

2

5%

MF

1/20W

PLACE_NEAR=C2260.1:2mm

R2263

201

24.9

1%

1/20W

MF

R2260

201

PLACE_NEAR=R2283.2:1.5MM

MF-LF

1/16W

402

1%

1K

R2281

PLACE_NEAR=R2261.2:1mm

1K

MF-LF

402

1/16W

1%

R2262

24.9

1%

1/20W

MF

R2240

201

1%

1K

MF-LF

1/16W

402

PLACE_NEAR=R2263.2:1mm

R2261

PLACE_NEAR=R2241.2:1mm

MF-LF

1/16W

402

1%

1K

R2242

0201

X5R-CERM

10%

6.3V

C2220

PLACE_NEAR=Q2220.6:2mm

0.022UF

MF

1/20W

2

5%

PLACE_NEAR=C2240.1:2mm

R2243

201

MF

1/20W

5%

2

PLACE_NEAR=C2220.1:2mm

R2223

201

24.9

1%

1/20W

MF

R2220

201

1%

1K

MF-LF

1/16W

402

PLACE_NEAR=R2243.2:1mm

R2241

PLACE_NEAR=R2221.2:1mm

MF-LF

402

1/16W

1%

1K

R2222

PLACE_NEAR=R2223.2:1.5MM

MF-LF

1/16W

402

1%

1K

R2221

20 21

CRITICAL DDRVREF_DAC

PCA9557

QFN

U2201

47

DDRVREF_DAC

MSOP

DAC5574

CRITICAL

U2200

47

0201

CERM-X5R

DDRVREF_DAC

C2201

6.3V

0.1UF

10%

DDRVREF_DAC

2.2UF

402-LF

CERM

20%

C2200

6.3V

0201

CERM-X5R

DDRVREF_DAC

C2205

6.3V

0.1UF

10%

SYNC_MASTER=J16_NICK

DDR3 VREF MARGINING

SYNC_DATE=01/10/2013

VREFMRGN_DQ_A_EN

VREFMRGN_DQ_A_EN_RC

=PPDDR_S3_MEMVREF

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PPVREF_S3_MEM_VREFCA_A

CPU_MEM_VREFDQ_A_ISOL

CPU_MEM_VREFDQ_B_ISOL

VREFMRGN_DQ_B_EN_RC

=PP3V3_S3_VREFMRGN

VREFMRGN_CA_A_EN

VREFMRGN_FRAMEBUF_EN

=I2C_VREFDACS_SCL

=I2C_VREFDACS_SDA

=I2C_PCA9557D_SCL =I2C_PCA9557D_SDA

CPU_DIMMB_VREFDQ

CPU_DIMM_VREFCA

MEMRESET_ISOL_LS5V_L

CPU_DIMMA_VREFDQ

VREFMRGN_DQ_A

=PP3V3_S3_VREFMRGN

DDRREG_FB

VREFMRGN_FRAMEBUF_BUF

VREFMRGN_CA_A_EN_RC

VREFMRGN_DQ_B_EN

VREFMRGN_CA_B_EN

MEM_VREFCA_B_RC

CPU_MEM_VREFCA_B_ISOL

MEM_VREFCA_A_RC

CPU_MEM_VREFCA_A_ISOL

MEM_VREFDQ_B_RC

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PPVREF_S3_MEM_VREFCA_B

MEM_VREFDQ_A_RC

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PPVREF_S3_MEM_VREFDQ_B

PPVREF_S3_MEM_VREFDQ_A

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

VREFMRGN_DQ_B_RDIV

MIN_LINE_WIDTH=0.3 mm

PP3V3_S3_VREFMRGN

MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

PCA9557D_RESET_L

VREFMRGN_DQ_B

VREFMRGN_CA_AB

VREFMRGN_MEMVREG_FBVREF

VREFMRGN_MEMVREG_EN

VREFMRGN_DQ_A_RDIV

VREFMRGN_MEMVREG_BUF

VREFMRGN_CA_A_RDIV

VREFMRGN_CA_B_RDIV

VREFMRGN_CA_B_EN_RC

051-0164

22 OF 123

22 OF 86

12.4.0

2

1

1 2

1

2

1

2

A4

A1

A3

A2

C4

C1

C3

C2

1 2

1

6

2

1

2

4

3

5

4

3

5

1

6

2

1

6

2

1

2

1 2

2

1

6

2

1

1 2

4

3

5

2

1

4

3

5

2

1

2

1 2

1

2

1 2

1

2

1

2

1

2

1

1 2

1

2

1 2

1

2

1

2

1 2

1

2

1

2

1

1 2

1

2

1

2

1

2

15

3

4

5

1

2

6

7

9

12

13

14

16

10

11

17

8

3

5

4

2

16

7

9

10

2

1

2

1

2

1

70

23

22 70

24

23

BI BIBI

BI

IN

BI BI

BI

IN

BI

BI BI

BI

BI BI

BI

IN IN

IN

IN IN

IN

BI BI

IN

BI

BI BI

BI

BI BI

BI

OUT

BI IN

IN

IN IN

BI BI

NC

A13

VDD_14

VDD_12

BA0

A10_AP

A3

DQ54 DQ55

VSS_44

VSS_0

VSS_2

VSS_5

DQS0

DQ5

DQ4

DQ6 DQ7

VREFDQ VSS_1

VSS_3

DQ0 DQ1

DM0 VSS_4

VSS_7

DQ12

DQ20

VSS_13

DQ15

DQ14

VSS_11

VSS_9

DQ13

DM1

DQ21

VSS_15

DQ22

VSS_16

VSS_18

DQ23

DQ28

VSS_20

DQ29

DM2

VSS_23

DQS3

DQ30

VSS_25

VDD_1

CKE1

A15 A14

VDD_3

VDD_9

VDD_5

VDD_7

A7

A11

A4

A6

A2 A0

CK1

NC_1

ODT1

VDD_15

ODT0

VDD_13

VDD_11

BA1

DQ39

DQ38

VSS_30

VSS_29

DQ37

DQ36

VSS_27

VREFCA

VDD_17

DM4

VSS_32

DQ47

DQ44

DQ46

VSS_37

DQS5

VSS_39

VSS_34

DQ45

DQ52

VSS_46

DQ61

DQ60

VSS_42

VSS_41

DQ53

DM6

DQS7

VSS_51

DQ63

DQ62

VSS_49

SDA SCL

DQ2 DQ3 VSS_6 DQ8 DQ9 VSS_8

DQS1 VSS_10

DQ16

VSS_12

DQ11

DQ10

DQ17

DQ18

DQS2 VSS_17

VSS_14

VSS_21

DQ24 DQ25

DQ19 VSS_19

VSS_24

DQ27

DQ26

DM3 VSS_22

CKE0

A5

VDD_4

CK0

VDD_8

A1

VDD_6

VDD_10

DQ33

VSS_26

VDD_16 TEST

DQ32

DQ34

VSS_31

DQS4

VSS_28

DQ35

DQ41

VSS_33

VSS_35

DQ40

DM5

VSS_38

DQ43

DQ42

VSS_36

DQ48

VSS_43

DQS6

VSS_40

DQ49

DQ51

DQ50

VSS_45 DQ56 DQ57 VSS_47 DM7

DQ58

VSS_48

DQ59

SA0

SA1

VDDSPD

VSS_50

A8

A9

A12/BC*

VDD_2

BA2

NC_0

VDD_0

DQ31

DQS0*

DQS1*

RESET*

DQS2*

DQS3*

CK0* CK1*

RAS*

WE* S0* CAS*

S1*

DQS4*

DQS5*

DQS6*

DQS7*

EVENT*

VTT_0 VTT_1

MTG_PINMTG_PIN

KEY

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)

25

C2331

10V

20% 402

CERM

0.1UF

C2330

20% 402-LF

CERM

2.2UF

6.3V

25

7

75

25

21 24 75

25

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

25

7

75

25

C2336

CERM 402

10V

20%

0.1UF

C2335

20%

402-LF

CERM

2.2UF

6.3V

25

24 44 45

47

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

25

R2341

10K

MF-LF 402

5% 1/16W

R2340

10K

MF-LF 402

5% 1/16W

C2340

2.2UF

CERM 402-LF

20%

6.3V

C2300

10UF

603

20%

6.3V X5R

C2301

603

10UF

20%

6.3V X5R

C2310

CERM 402

20% 10V

0.1UF

C2311

CERM 402

20% 10V

0.1UF

C2312

CERM 402

20% 10V

0.1UF

C2313

CERM 402

20% 10V

0.1UF

C2314

CERM 402

20% 10V

0.1UF

C2315

CERM 402

20% 10V

0.1UF

C2316

CERM 402

20% 10V

0.1UF

C2317

20% 10V

402

CERM

0.1UF

C2318

20% CERM

402

10V

0.1UF

C2319

CERM

10V 402

20%

0.1UF

C2320

CERM 402

10V

20%

0.1UF

C2321

402

CERM

20% 10V

0.1UF

C2322

CERM 402

20% 10V

0.1UF

C2323

10V

20% 402

CERM

0.1UF

C2353

10V X6S-CERM

1UF

0402

10%

C2352

10V X6S-CERM

1UF

0402

10%

C2351

10V X6S-CERM

1UF

0402

10%

C2350

10V X6S-CERM

1UF

0402

10%

C2302

402

CERM

10V

20%

0.1UF

C2324

CERM 402

20% 10V

0.1UF

2-2013310-1

F-RT-SM

CRITICAL

J2300

SYNC_MASTER=J16_NICK SYNC_DATE=01/10/2013

DDR3 SO-DIMM Connector A

=PPVDDQ_S3_MEM_A

MEM_A_RAS_L

VOLTAGE=0.75V

PPVREF_S3_MEM_VREFCA_A

=MEM_A_DQ<52> =MEM_A_DQ<53>

MEM_A_SA<1> MEM_A_SA<0> =PPSPD_S0_MEM_A

=PPDDRVTT_S0_MEM_A

MEM_EVENT_L

=MEM_A_DQS_N<7>

=MEM_A_DQS_N<6>

=MEM_A_DQS_N<5>

=MEM_A_DQS_N<4>

MEM_A_CS_L<1>

MEM_A_CAS_L

MEM_A_CS_L<0>

MEM_A_WE_L

MEM_A_CLK_N<1>MEM_A_CLK_N<0>

=MEM_A_DQS_N<3>

=MEM_A_DQS_N<2>

MEM_RESET_L

=MEM_A_DQS_N<1>

=MEM_A_DQS_N<0>

=MEM_A_DQ<31>

MEM_A_BA<2>

MEM_A_A<12> MEM_A_A<9>

MEM_A_A<8>

=PPSPD_S0_MEM_A MEM_A_SA<1>

MEM_A_SA<0>

=MEM_A_DQ<59>

=MEM_A_DQ<58>

=MEM_A_DQ<57>

=MEM_A_DQ<56>

=MEM_A_DQ<50> =MEM_A_DQ<51>

=MEM_A_DQ<49>

=MEM_A_DQS_P<6>

=MEM_A_DQ<48>

=MEM_A_DQ<42> =MEM_A_DQ<43>

=MEM_A_DQ<40> =MEM_A_DQ<41>

=MEM_A_DQ<35>

=MEM_A_DQS_P<4>

=MEM_A_DQ<34>

=MEM_A_DQ<32> =MEM_A_DQ<33>

MEM_A_A<1>

MEM_A_CLK_P<0>

MEM_A_A<5>

MEM_A_CKE<0>

=MEM_A_DQ<26> =MEM_A_DQ<27>

=MEM_A_DQ<19>

=MEM_A_DQ<25>

=MEM_A_DQ<24>

=MEM_A_DQS_P<2>

=MEM_A_DQ<18>

=MEM_A_DQ<17>

=MEM_A_DQ<10> =MEM_A_DQ<11>

=MEM_A_DQ<16>

=MEM_A_DQS_P<1>

=MEM_A_DQ<9>

=MEM_A_DQ<8>

=MEM_A_DQ<3>

=MEM_A_DQ<2>

=I2C_SODIMMA_SCL

=I2C_SODIMMA_SDA

=MEM_A_DQ<62> =MEM_A_DQ<63>

=MEM_A_DQS_P<7>

=MEM_A_DQ<60> =MEM_A_DQ<61>

=MEM_A_DQ<45>

=MEM_A_DQS_P<5>

=MEM_A_DQ<46>

=MEM_A_DQ<44>

=MEM_A_DQ<47>

=MEM_A_DQ<36> =MEM_A_DQ<37>

=MEM_A_DQ<38> =MEM_A_DQ<39>

MEM_A_BA<1>

MEM_A_ODT<0>

MEM_A_ODT<1>

MEM_A_CLK_P<1>

MEM_A_A<0>

MEM_A_A<2>

MEM_A_A<6> MEM_A_A<4>

MEM_A_A<11> MEM_A_A<7>

MEM_A_A<14>

MEM_A_A<15>

MEM_A_CKE<1>

=PPVDDQ_S3_MEM_A

=MEM_A_DQ<30>

=MEM_A_DQS_P<3>

=MEM_A_DQ<29>

=MEM_A_DQ<28>

=MEM_A_DQ<23>

=MEM_A_DQ<22>

=MEM_A_DQ<21>

=MEM_A_DQ<13>

=MEM_A_DQ<14> =MEM_A_DQ<15>

=MEM_A_DQ<20>

=MEM_A_DQ<12>

=MEM_A_DQ<1>

=MEM_A_DQ<0>

=MEM_A_DQ<7>

=MEM_A_DQ<6>

=MEM_A_DQ<4> =MEM_A_DQ<5>

=MEM_A_DQS_P<0>

=MEM_A_DQ<55>

=MEM_A_DQ<54>

MEM_A_A<3>

MEM_A_A<10> MEM_A_BA<0>

MEM_A_A<13>

PPVREF_S3_MEM_VREFDQ_A

VOLTAGE=0.75V

051-0164

12.4.0

23 OF 123

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1

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2

1

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1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

119

117

111

109

107

95

174 176 178

2

8

14

12

6

4

16 18

1 3

9

5 7

11 13

20 22

40

38

36

34

32

26

24

28

42 44

50

48

54

52

56

60

58

46

66

64

68

72

76

74

78 80 82

100

88

94

86

84

92

90

96 98

102

122

120

118

116

112

106 108

142

140

138

134

132

130

128

126

124

136

144

160

146

158

156

154

162

150

148

164

184

182

180

172

168

166

170

188

196

194

192

190

200 202

15 17 19 21 23 25

29 31

39

37

35

33

41

51

47 49

43

61

57 59

53 55

71

69

67

63 65

73

91

87

101

99

97

93

105

131

127

123 125

129

141

139

137

133

143

149

145

151

147

153

161

159

157

155

163

173

171

167

165

177

175

179 181 183 185 187

191

189

193

197

201

199

195

89

85

83

81

79

77

75

70

10

27

30

45

62

103 104

110

113 114 115

121

135

152

169

186

198

203 204

206205

23 70

22

23

23 70

23

23 70

22

IN

IN IN

IN

NC

BI

BI BI

BI

IN

BI

BI BI

BI

IN

BI

BI BI

BI

IN

IN IN

IN

IN IN

IN

BI

NC

A13

VDD_14

VDD_12

BA0

A10_AP

A3

DQ54 DQ55

VSS_44

VSS_0

VSS_2

VSS_5

DQS0

DQ5

DQ4

DQ6 DQ7

VREFDQ VSS_1

VSS_3

DQ0 DQ1

DM0 VSS_4

VSS_7

DQ12

DQ20

VSS_13

DQ15

DQ14

VSS_11

VSS_9

DQ13

DM1

DQ21

VSS_15

DQ22

VSS_16

VSS_18

DQ23

DQ28

VSS_20

DQ29

DM2

VSS_23

DQS3

DQ30

VSS_25

VDD_1

CKE1

A15 A14

VDD_3

VDD_9

VDD_5

VDD_7

A7

A11

A4

A6

A2 A0

CK1

NC_1

ODT1

VDD_15

ODT0

VDD_13

VDD_11

BA1

DQ39

DQ38

VSS_30

VSS_29

DQ37

DQ36

VSS_27

VREFCA

VDD_17

DM4

VSS_32

DQ47

DQ44

DQ46

VSS_37

DQS5

VSS_39

VSS_34

DQ45

DQ52

VSS_46

DQ61

DQ60

VSS_42

VSS_41

DQ53

DM6

DQS7

VSS_51

DQ63

DQ62

VSS_49

SDA SCL

DQ2 DQ3 VSS_6 DQ8 DQ9 VSS_8

DQS1 VSS_10

DQ16

VSS_12

DQ11

DQ10

DQ17

DQ18

DQS2 VSS_17

VSS_14

VSS_21

DQ24 DQ25

DQ19 VSS_19

VSS_24

DQ27

DQ26

DM3 VSS_22

CKE0

A5

VDD_4

CK0

VDD_8

A1

VDD_6

VDD_10

DQ33

VSS_26

VDD_16 TEST

DQ32

DQ34

VSS_31

DQS4

VSS_28

DQ35

DQ41

VSS_33

VSS_35

DQ40

DM5

VSS_38

DQ43

DQ42

VSS_36

DQ48

VSS_43

DQS6

VSS_40

DQ49

DQ51

DQ50

VSS_45 DQ56 DQ57 VSS_47 DM7

DQ58

VSS_48

DQ59

SA0

SA1

VDDSPD

VSS_50

A8

A9

A12/BC*

VDD_2

BA2

NC_0

VDD_0

DQ31

DQS0*

DQS1*

RESET*

DQS2*

DQS3*

CK0* CK1*

RAS*

WE* S0* CAS*

S1*

DQS4*

DQS5*

DQS6*

DQS7*

EVENT*

VTT_0 VTT_1

MTG_PINMTG_PIN

KEY

NC

BI

BI BI

BI

BI BI

BI

OUT

IN IN

BI BI

BI

IN

BI

BI BI

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)

C2553

10V

1UF

X6S-CERM 0402

10%

47

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

25

C2531

CERM 402

20% 10V

0.1UF

7

75

25

C2530

20% 402-LF

2.2UF

CERM

6.3V

25

7

75

25

7

75

7

75

7

75

7

75

7

75

C2517

CERM 402

20% 10V

0.1UF

7

75

7

75

7

75

7

75

7

75

7

75

C2523

10V

20% 402

CERM

0.1UF

C2516

10V

20% 402

CERM

0.1UF

7

75

C2515

10V

20% 402

CERM

0.1UF

C2514

10V

20% 402

CERM

0.1UF

C2513

10V

20% CERM

402

0.1UF

C2522

CERM 402

20% 10V

0.1UF

C2521

CERM 402

20% 10V

0.1UF

C2520

CERM 402

20% 10V

0.1UF

C2519

CERM 402

20% 10V

0.1UF

C2512

20% CERM

10V 402

0.1UF

C2511

10V

20% 402

CERM

0.1UF

C2510

CERM

10V

20% 402

0.1UF

25

C2518

CERM 402

20% 10V

0.1UF

C2501

10UF

603

20%

6.3V X5R

C2500

10UF

603

20%

6.3V X5R

C2524

10V

20% 402

CERM

0.1UF

C2502

402

10V

20% CERM

0.1UF

2-2013289-1

CRITICAL

F-RT-SM

J2500

25

C2536

10V

20% 402

CERM

0.1UF

25

C2535

20%

402-LF

CERM

2.2UF

6.3V

23 44 45

7

75

7

75

7

75

7

75

7

75

7

75

25

C2552

10V X6S-CERM

1UF

0402

10%

25

C2551

10V X6S-CERM

1UF

0402

10%

25

R2541

5%

402

MF-LF

10K

1/16W

R2540

1/16W

5%

402

MF-LF

10K

C2540

20% 402-LF

CERM

2.2UF

6.3V

25

C2550

10V X6S-CERM

1UF

0402

10%

25

21 23 75

25

47

25

7

75

SYNC_DATE=01/10/2013

DDR3 SO-DIMM CONNECTOR B

SYNC_MASTER=J16_NICK

MEM_B_SA<0>

MEM_B_SA<1>

=PPSPD_S0_MEM_B

=PPDDRVTT_S0_MEM_B=PPDDRVTT_S0_MEM_B

MEM_EVENT_L

=MEM_B_DQS_N<7>

=MEM_B_DQS_N<6>

=MEM_B_DQS_N<5>

=MEM_B_DQS_N<4>

MEM_B_CS_L<1>

MEM_B_CAS_L

MEM_B_CS_L<0>

MEM_B_WE_L

MEM_B_RAS_L

MEM_B_CLK_N<1>MEM_B_CLK_N<0>

=MEM_B_DQS_N<3>

=MEM_B_DQS_N<2>

MEM_RESET_L

=MEM_B_DQS_N<1>

=MEM_B_DQS_N<0>

=MEM_B_DQ<31>

MEM_B_BA<2>

MEM_B_A<12> MEM_B_A<9>

MEM_B_A<8>

=PPSPD_S0_MEM_B MEM_B_SA<1>

MEM_B_SA<0>

=MEM_B_DQ<59>

=MEM_B_DQ<58>

=MEM_B_DQ<57>

=MEM_B_DQ<56>

=MEM_B_DQ<50> =MEM_B_DQ<51>

=MEM_B_DQ<49>

=MEM_B_DQS_P<6>

=MEM_B_DQ<48>

=MEM_B_DQ<42> =MEM_B_DQ<43>

=MEM_B_DQ<40> =MEM_B_DQ<41>

=MEM_B_DQ<35>

=MEM_B_DQS_P<4>

=MEM_B_DQ<34>

=MEM_B_DQ<32> =MEM_B_DQ<33>

MEM_B_A<1>

MEM_B_CLK_P<0>

MEM_B_A<5>

MEM_B_CKE<0>

=MEM_B_DQ<26> =MEM_B_DQ<27>

=MEM_B_DQ<19>

=MEM_B_DQ<25>

=MEM_B_DQ<24>

=MEM_B_DQS_P<2>

=MEM_B_DQ<18>

=MEM_B_DQ<17>

=MEM_B_DQ<10> =MEM_B_DQ<11>

=MEM_B_DQ<16>

=MEM_B_DQS_P<1>

=MEM_B_DQ<9>

=MEM_B_DQ<8>

=MEM_B_DQ<3>

=MEM_B_DQ<2>

=I2C_SODIMMB_SCL

=I2C_SODIMMB_SDA

=MEM_B_DQ<62> =MEM_B_DQ<63>

=MEM_B_DQS_P<7>

=MEM_B_DQ<53>

=MEM_B_DQ<60> =MEM_B_DQ<61>

=MEM_B_DQ<52>

=MEM_B_DQ<45>

=MEM_B_DQS_P<5>

=MEM_B_DQ<46>

=MEM_B_DQ<44>

=MEM_B_DQ<47>

VOLTAGE=0.75V

PPVREF_S3_MEM_VREFCA_B

=MEM_B_DQ<36> =MEM_B_DQ<37>

=MEM_B_DQ<38> =MEM_B_DQ<39>

MEM_B_BA<1>

MEM_B_ODT<0>

MEM_B_ODT<1>

MEM_B_CLK_P<1>

MEM_B_A<0>

MEM_B_A<2>

MEM_B_A<6> MEM_B_A<4>

MEM_B_A<11> MEM_B_A<7>

MEM_B_A<14>

MEM_B_A<15>

MEM_B_CKE<1>

=PPVDDQ_S3_MEM_B

=MEM_B_DQ<30>

=MEM_B_DQS_P<3>

=MEM_B_DQ<29>

=MEM_B_DQ<28>

=MEM_B_DQ<23>

=MEM_B_DQ<22>

=MEM_B_DQ<21>

=MEM_B_DQ<13>

=MEM_B_DQ<14> =MEM_B_DQ<15>

=MEM_B_DQ<20>

=MEM_B_DQ<12>

=MEM_B_DQ<0>

PPVREF_S3_MEM_VREFDQ_B

VOLTAGE=0.75V

=MEM_B_DQ<7>

=MEM_B_DQ<6>

=MEM_B_DQ<4> =MEM_B_DQ<5>

=MEM_B_DQS_P<0>

=MEM_B_DQ<55>

=MEM_B_DQ<54>

MEM_B_A<3>

MEM_B_A<10> MEM_B_BA<0>

=PPVDDQ_S3_MEM_B

MEM_B_A<13>

=MEM_B_DQ<1>

051-0164

12.4.0

25 OF 123

24 OF 86

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

119

117

111

109

107

95

174 176 178

2

8

14

12

6

4

16 18

1 3

9

5 7

11 13

20 22

40

38

36

34

32

26

24

28

42 44

50

48

54

52

56

60

58

46

66

64

68

72

76

74

78 80 82

100

88

94

86

84

92

90

96 98

102

122

120

118

116

112

106 108

142

140

138

134

132

130

128

126

124

136

144

160

146

158

156

154

162

150

148

164

184

182

180

172

168

166

170

188

196

194

192

190

200 202

15 17 19 21 23 25

29 31

39

37

35

33

41

51

47 49

43

61

57 59

53 55

71

69

67

63 65

73

91

87

101

99

97

93

105

131

127

123 125

129

141

139

137

133

143

149

145

151

147

153

161

159

157

155

163

173

171

167

165

177

175

179 181 183 185 187

191

189

193

197

201

199

195

89

85

83

81

79

77

75

70

10

27

30

45

62

103 104

110

113 114 115

121

135

152

169

186

198

203 204

206205

2

1

2

1

2

1

2

1

2

1

2

1

2

1

24

24 70

24 70 24 70

24 70

24

22

24 70

22

24 70

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

THERE ARE NO PIN SWAPS

SYNC_MASTER=J16_NICK

DDR3 ALIASES AND BITSWAPS

SYNC_DATE=01/10/2013

MEM_B_DQS_P<6>

MAKE_BASE=TRUE

=MEM_A_DQS_P<6>

=MEM_A_DQ<45>

MEM_A_DQ<15>

MAKE_BASE=TRUE

MEM_A_DQ<2>

MAKE_BASE=TRUE

MEM_A_DQ<1> MEM_A_DQ<0>

MAKE_BASE=TRUE

MEM_A_DQS_N<1>

MAKE_BASE=TRUE

MEM_A_DQS_P<1>

MAKE_BASE=TRUE

MEM_A_DQS_N<2>

MEM_A_DQ<23>

MAKE_BASE=TRUE

MEM_A_DQ<9>

MAKE_BASE=TRUE

MEM_A_DQS_P<0>

MAKE_BASE=TRUE

MEM_A_DQ<18>

MAKE_BASE=TRUE

MEM_A_DQ<6>

MAKE_BASE=TRUE

MEM_B_DQ<7>

MAKE_BASE=TRUE

MEM_B_DQS_P<5>

MEM_B_DQS_N<6>

MAKE_BASE=TRUE

MEM_A_DQS_P<7>

MEM_A_DQS_N<7>

MAKE_BASE=TRUE

MEM_A_DQS_P<6>

MAKE_BASE=TRUE

MEM_A_DQS_N<6>

MAKE_BASE=TRUE

MEM_A_DQS_P<5>

MEM_A_DQS_N<5>

MAKE_BASE=TRUE

MEM_A_DQS_P<4>

MAKE_BASE=TRUE

MEM_A_DQS_N<4>

MEM_A_DQS_P<3>

MAKE_BASE=TRUE

MEM_A_DQS_N<3>

MAKE_BASE=TRUE

MEM_A_DQS_P<2>

MEM_B_DQS_P<7>

MAKE_BASE=TRUE

MEM_B_DQS_N<7>

MAKE_BASE=TRUE

MEM_B_DQS_N<5>

MAKE_BASE=TRUE

MEM_B_DQS_P<4>

MAKE_BASE=TRUE

MEM_B_DQS_N<4>

MEM_B_DQS_P<3>

MAKE_BASE=TRUE

MEM_B_DQS_N<3>

MAKE_BASE=TRUE

MEM_B_DQS_P<2>

MAKE_BASE=TRUE

MEM_A_DQS_N<0>

MEM_B_DQS_N<1>

MAKE_BASE=TRUE MAKE_BASE=TRUE

MEM_B_DQS_P<1>

MEM_B_DQS_N<2>

MAKE_BASE=TRUE

MEM_B_DQS_N<0>

MAKE_BASE=TRUE

MEM_B_DQS_P<0>

MAKE_BASE=TRUE

MEM_B_DQ<32>

MEM_B_DQ<45>

MAKE_BASE=TRUE

MEM_B_DQ<42> MEM_B_DQ<41>

MAKE_BASE=TRUE MAKE_BASE=TRUE

MEM_B_DQ<40>

MAKE_BASE=TRUE

MEM_B_DQ<48>

MEM_B_DQ<50>

MAKE_BASE=TRUE

MEM_B_DQ<55>

MEM_B_DQ<58>

MAKE_BASE=TRUE

MEM_B_DQ<56>

MEM_A_DQ<37>

MAKE_BASE=TRUE

MEM_A_DQ<32>

MEM_A_DQ<35>

MAKE_BASE=TRUE MAKE_BASE=TRUE

MEM_A_DQ<34>

MAKE_BASE=TRUE

MEM_A_DQ<45>

MAKE_BASE=TRUE

MEM_A_DQ<41>

MAKE_BASE=TRUE

MEM_A_DQ<42>

MEM_A_DQ<48>

MAKE_BASE=TRUE

MEM_A_DQ<53>

MAKE_BASE=TRUE

MEM_A_DQ<50>

MAKE_BASE=TRUE

MEM_A_DQ<51>

MEM_A_DQ<57>

MAKE_BASE=TRUE

MEM_A_DQ<56>

MAKE_BASE=TRUE

MEM_A_DQ<60>

MAKE_BASE=TRUE

MEM_A_DQ<59>

MAKE_BASE=TRUE

MEM_A_DQ<58>

MAKE_BASE=TRUE

MEM_B_DQ<33>

MAKE_BASE=TRUE

MEM_B_DQ<34>

MAKE_BASE=TRUE

MEM_B_DQ<36> MEM_B_DQ<35>

MAKE_BASE=TRUE

MEM_B_DQ<37>

MAKE_BASE=TRUE

MEM_B_DQ<38>

MAKE_BASE=TRUE

MEM_B_DQ<24>

MEM_B_DQ<25>

MAKE_BASE=TRUE

MEM_B_DQ<27>

MAKE_BASE=TRUE

MEM_B_DQ<26>

MAKE_BASE=TRUE

MEM_B_DQ<28>

MAKE_BASE=TRUE

MEM_B_DQ<29>

MAKE_BASE=TRUE

MEM_B_DQ<30>

MEM_B_DQ<31>

MAKE_BASE=TRUE

MEM_B_DQ<23>

MAKE_BASE=TRUE

MEM_B_DQ<21>

MAKE_BASE=TRUE

MEM_B_DQ<46>

MAKE_BASE=TRUE

MEM_B_DQ<47>

MEM_B_DQ<18>

MAKE_BASE=TRUE

MEM_B_DQ<17>

MAKE_BASE=TRUE

MEM_B_DQ<20>

MAKE_BASE=TRUE

MEM_B_DQ<43>

MAKE_BASE=TRUE

MEM_B_DQ<44>

MAKE_BASE=TRUE

MEM_B_DQ<16>

MAKE_BASE=TRUE

MEM_B_DQ<19>

MAKE_BASE=TRUE

MEM_B_DQ<22>

MEM_B_DQ<14>

MAKE_BASE=TRUE

MEM_B_DQ<49>

MAKE_BASE=TRUE

MEM_B_DQ<53>

MAKE_BASE=TRUE

MEM_B_DQ<12> MEM_B_DQ<11>

MAKE_BASE=TRUE MAKE_BASE=TRUE

MEM_B_DQ<10>

MAKE_BASE=TRUE

MEM_B_DQ<51>

MAKE_BASE=TRUE

MEM_B_DQ<9>

MEM_B_DQ<15>

MAKE_BASE=TRUE

MEM_B_DQ<8>

MEM_B_DQ<62>

MAKE_BASE=TRUE

MEM_B_DQ<1>

MAKE_BASE=TRUE

MEM_B_DQ<5>

MAKE_BASE=TRUE

MEM_B_DQ<3>

MAKE_BASE=TRUE

MEM_B_DQ<57>

MAKE_BASE=TRUE

MEM_B_DQ<59>

MEM_B_DQ<60>

MAKE_BASE=TRUE

MEM_B_DQ<61>

MAKE_BASE=TRUE

MEM_B_DQ<63>

MAKE_BASE=TRUE

MEM_B_DQ<0>

MAKE_BASE=TRUE

MEM_B_DQ<2>

MAKE_BASE=TRUE

MEM_B_DQ<4>

MAKE_BASE=TRUE

MEM_B_DQ<6>

MEM_A_DQ<27>

MAKE_BASE=TRUE

MEM_A_DQ<31>

MAKE_BASE=TRUE

MEM_A_DQ<36>

MEM_A_DQ<33>

MAKE_BASE=TRUE

MEM_A_DQ<26>

MAKE_BASE=TRUE

MEM_A_DQ<30>

MAKE_BASE=TRUE

MEM_A_DQ<38>

MAKE_BASE=TRUE

MEM_A_DQ<25>

MEM_A_DQ<29>

MAKE_BASE=TRUE

MEM_A_DQ<39>

MAKE_BASE=TRUE

MEM_A_DQ<24>

MAKE_BASE=TRUE

MEM_A_DQ<28>

MAKE_BASE=TRUE

MEM_A_DQ<22>

MAKE_BASE=TRUE

MEM_A_DQ<40>

MAKE_BASE=TRUE

MEM_A_DQ<44>

MEM_A_DQ<19>

MAKE_BASE=TRUE

MEM_A_DQ<43>

MAKE_BASE=TRUE

MEM_A_DQ<46>

MEM_A_DQ<47>

MAKE_BASE=TRUE

MEM_A_DQ<16>

MAKE_BASE=TRUE

MEM_A_DQ<17>

MAKE_BASE=TRUE

MEM_A_DQ<20>

MAKE_BASE=TRUE

MEM_A_DQ<21>

MEM_A_DQ<49>

MAKE_BASE=TRUE

MEM_A_DQ<52>

MAKE_BASE=TRUE

MEM_A_DQ<14>

MAKE_BASE=TRUE

MEM_A_DQ<11> MEM_A_DQ<10>

MAKE_BASE=TRUE

MEM_A_DQ<55>

MAKE_BASE=TRUE

MEM_A_DQ<12>

MEM_A_DQ<54>

MAKE_BASE=TRUE

MEM_A_DQ<13>

MEM_A_DQ<8>

MAKE_BASE=TRUE

MEM_A_DQ<7>

MAKE_BASE=TRUE

MEM_A_DQ<61>

MEM_A_DQ<3>

MAKE_BASE=TRUE

MEM_A_DQ<62>

MEM_A_DQ<4>

MAKE_BASE=TRUE

MEM_A_DQ<63>

MAKE_BASE=TRUE

MEM_A_DQ<5>

MEM_B_DQ<13>

MAKE_BASE=TRUE

MEM_B_DQ<39>

MEM_B_DQ<52>

MAKE_BASE=TRUE

MEM_B_DQ<54>

MAKE_BASE=TRUE

=MEM_A_DQ<42>

=MEM_A_DQS_P<3>

=MEM_A_DQ<21>

=MEM_A_DQ<22>

=MEM_A_DQ<20>

=MEM_A_DQ<18> =MEM_A_DQ<17> =MEM_A_DQ<16>

=MEM_A_DQS_N<3>

=MEM_A_DQ<28>

=MEM_B_DQS_N<5>

=MEM_B_DQ<42>

=MEM_B_DQ<45>

=MEM_B_DQ<26>

=MEM_B_DQ<27>

=MEM_B_DQ<24>

=MEM_B_DQ<10>

=MEM_B_DQ<12>

=MEM_A_DQS_N<0> =MEM_A_DQS_P<0>

=MEM_A_DQ<6>

=MEM_A_DQ<0>

=MEM_A_DQ<5>

=MEM_A_DQ<63>

=MEM_A_DQ<58>

=MEM_A_DQ<4>

=MEM_A_DQ<1>

=MEM_A_DQ<62>

=MEM_A_DQ<59>

=MEM_A_DQ<3> =MEM_A_DQ<2>

=MEM_A_DQ<61> =MEM_A_DQ<60>

=MEM_A_DQ<56>

=MEM_A_DQ<57>

=MEM_A_DQ<7>

=MEM_A_DQ<8>

=MEM_A_DQ<54>

=MEM_A_DQ<51>

=MEM_A_DQ<12>

=MEM_A_DQ<55>

=MEM_A_DQ<50>

=MEM_A_DQ<10>

=MEM_A_DQ<53>

=MEM_A_DQ<14>

=MEM_A_DQ<11>

=MEM_A_DQ<52>

=MEM_A_DQ<49> =MEM_A_DQ<48>

=MEM_A_DQ<47> =MEM_A_DQ<46>

=MEM_A_DQ<43>

=MEM_A_DQ<23>

=MEM_A_DQ<19>

=MEM_A_DQ<44>

=MEM_A_DQ<40>

=MEM_A_DQ<41>

=MEM_A_DQ<34>

=MEM_A_DQ<24>

=MEM_A_DQ<39>

=MEM_A_DQ<35>

=MEM_A_DQ<29>

=MEM_A_DQ<25>

=MEM_A_DQ<38>

=MEM_A_DQ<33>

=MEM_A_DQ<30>

=MEM_A_DQ<26>

=MEM_A_DQ<32>

=MEM_A_DQ<36>

=MEM_A_DQ<31>

=MEM_A_DQ<27>

=MEM_A_DQ<37>

=MEM_B_DQ<4>

=MEM_B_DQ<6>

=MEM_B_DQ<63>

=MEM_B_DQ<61> =MEM_B_DQ<60> =MEM_B_DQ<59>

=MEM_B_DQ<57> =MEM_B_DQ<56>

=MEM_B_DQ<2>

=MEM_B_DQ<3>

=MEM_B_DQ<1>

=MEM_B_DQ<62>

=MEM_B_DQ<58>

=MEM_B_DQ<5>

=MEM_B_DQ<8>

=MEM_B_DQ<55>

=MEM_B_DQ<9>

=MEM_B_DQ<15>

=MEM_B_DQ<51> =MEM_B_DQ<50>

=MEM_B_DQ<13>

=MEM_B_DQ<11>

=MEM_B_DQ<53> =MEM_B_DQ<52>

=MEM_B_DQ<49> =MEM_B_DQ<48>

=MEM_B_DQ<54>

=MEM_B_DQ<14>

=MEM_B_DQ<22>

=MEM_B_DQ<19>

=MEM_B_DQ<16>

=MEM_B_DQ<44> =MEM_B_DQ<43>

=MEM_B_DQ<40>

=MEM_B_DQ<20>

=MEM_B_DQ<17>

=MEM_B_DQ<47> =MEM_B_DQ<46>

=MEM_B_DQ<41>

=MEM_B_DQ<18>

=MEM_B_DQ<21>

=MEM_B_DQ<23>

=MEM_B_DQ<38>

=MEM_B_DQ<32>

=MEM_B_DQ<39>

=MEM_B_DQ<37>

=MEM_B_DQ<30>

=MEM_B_DQ<31>

=MEM_B_DQ<33>

=MEM_B_DQ<34>

=MEM_B_DQ<35>

=MEM_B_DQ<36>

=MEM_B_DQ<25>

=MEM_B_DQ<28>

=MEM_B_DQ<29>

=MEM_A_DQS_N<1>

=MEM_B_DQS_N<2>

=MEM_A_DQS_P<5>

=MEM_A_DQS_P<2>

=MEM_B_DQS_P<1>

=MEM_B_DQS_N<1>

=MEM_A_DQS_P<1>

=MEM_B_DQS_P<5>

=MEM_B_DQS_N<6> =MEM_B_DQS_P<6>

=MEM_B_DQS_N<7> =MEM_B_DQS_P<7>

=MEM_A_DQS_N<2>

=MEM_A_DQS_N<4> =MEM_A_DQS_P<4>

=MEM_A_DQS_N<5>

=MEM_A_DQS_N<6>

=MEM_A_DQS_N<7> =MEM_A_DQS_P<7>

=MEM_B_DQS_P<4>

=MEM_B_DQS_N<4>

=MEM_B_DQS_P<3>

=MEM_B_DQS_N<3>

=MEM_B_DQS_P<2>

=MEM_B_DQ<7>

=MEM_B_DQS_P<0>

=MEM_B_DQS_N<0>

=MEM_B_DQ<0>

=MEM_A_DQ<9>

=MEM_A_DQ<13>

=MEM_A_DQ<15>

051-0164

12.4.0

27 OF 123

25 OF 86

7

75 23

23

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

7

75

23

24

23

24

23

24

23

24

23

24

23

24

23

OUT

IN

OUT

IN

OUT

IN

OUT

OUT OUT

IN

OUT

IN IN

OUT

BI

IN

BI

OUT IN

OUT

IN

OUT OUT

BI BI

IN

IN IN IN OUT

OUT OUT

BI BI

IN

OUT OUT OUT

OUT

PETN_3

PETN_2

PETP_2

PETP_1 PETN_1

PETP_0 PETN_0

MONOBS_N

MONDC0 MONDC1

PERN_3

PERP_3

PERN_2

PERP_2

PERN_1

PERP_1

PERP_0 PERN_0

MONOBS_P

TMU_CLK_IN

TMU_CLK_OUT

DPSRC_3_P

DPSRC_2_P

DPSRC_3_N

DPSRC_1_P

DPSRC_2_N

DPSRC_1_N

DPSRC_0_P

DPSRC_AUX_P

DPSRC_0_N

DPSRC_HPD_OD

DPSRC_AUX_N

GPIO_2/GO2SX

GPIO_15

GPIO_9/OK2GO2SX_OD*

GPIO_14

GPIO_8/EN_CIO_PWR_OD*

GPIO_7/CIO_SCL_OD

GPIO_6/CIO_SDA_OD

GPIO_5/CIO_PLUG_EVENT

GPIO_4/WAKE_N_OD

GPIO_3

PB_CIO3_TX_N/DP_SRC_2_N

PB_CONFIG2/CIO_2_LSOE

PB_CIO2_RX_N

PB_CONFIG1/CIO_2_LSEO

PB_CIO2_RX_P

PB_CIO2_TX_P/DP_SRC_0_P PB_CIO2_TX_N/DP_SRC_0_N

PB_CIO3_TX_P/DP_SRC_2_P

PB_DPSRC_3_N

PB_DPSRC_1_N

PB_DPSRC_1_P

PB_LSRX/CIO_3_LSOE

PB_CIO3_RX_N

PB_LSTX/CIO_3_LSEO

PB_CIO3_RX_P

PB_DPSRC_3_P

GPIO_11/PB_CIO_SEL/BYP1

GPIO_13/PB_DP_PWRDN/BYP2

GPIO_1/PB_HV_EN/BYP0

PB_DPSRC_HPD

PB_AUX_N

PB_AUX_P

THERMDA

EE_DI EE_DO EE_CS_N

TDI

EE_CLK

TDO

DPSNK0_2_P

DPSNK0_3_N

DPSNK0_1_P

DPSNK0_2_N

DPSNK0_0_P

DPSNK0_1_N

DPSNK0_AUX_P

DPSNK0_0_N

DPSNK0_HPD

DPSNK0_AUX_N

DPSNK1_3_N

DPSNK1_3_P

DPSNK1_2_N

DPSNK1_2_P

DPSNK1_1_N

DPSNK1_1_P

DPSNK1_0_N

DPSNK1_0_P

DPSNK1_AUX_N

DPSNK1_AUX_P

DPSNK1_HPD

PA_CIO0_TX_N/DP_SRC_0_N

PA_CIO0_TX_P/DP_SRC_0_P

PA_CIO0_RX_N

PA_CIO0_RX_P

PA_CONFIG2/CIO_0_LSOE

PA_CONFIG1/CIO_0_LSEO

PA_CIO1_TX_N/DP_SRC_2_N

PA_CIO1_TX_P/DP_SRC_2_P

PA_CIO1_RX_N

PA_CIO1_RX_P

PA_LSRX/CIO_1_LSOE

PA_LSTX/CIO_1_LSEO

PA_DPSRC_1_N

PA_DPSRC_1_P

PA_DPSRC_3_N

PA_DPSRC_3_P

PA_AUX_P

PA_DPSRC_HPD

PA_AUX_N

GPIO_10/PA_CIO_SEL/BYP1

GPIO_0/PA_HV_EN/BYP0

GPIO_12/PA_DP_PWRDN/BYP2

PETP_3

RSENSE

REFCLK_100_IN_P REFCLK_100_IN_N

XTAL_25_IN

XTAL_25_OUT

TMS TCK

TEST_EN TEST_PWR_GOOD

DPSNK0_3_P

PWR_ON_POC_RSTN

PERST_N

NC

RBIAS

PCIE_RST_0_N PCIE_RST_1_N

PCIE_RST_3_N

PCIE_RST_2_N

PCIE_CLKREQ_OD_N

EN_LC_PWR

PCIE RESET

PCIE GEN2

MISC

(SYM 1 OF 2)

CLOCKS

JTAG/TEST PORT

RECEIVE

TRANSMIT

EEPROM

SINK PORT 0SINK PORT 1

SOURCE PORT 0

PORT3 PORT2

PORT0PORT1

DISPLAYPORT

PORTS

OUT

NC

IN

IN IN

OUT

IN

D

C

Q

S*

W*

HOLD*

PAD

VSS

THM

VCC

IN

OUT

BI

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(TBT_SPI_CS_L)

(TBT_SPI_CLK)

(TBT_SPI_MOSI)

SNK0 AC Coupling

(TBT_SPI_MISO)

(TBT_EN_CIO_PWR_L)

(FORCE_PWR)

SNK1 AC Coupling

of GPIO_2/GPIO_9 if necessary.

Use AA8 GND ball for THERM_DN

For unused port, pull CONFIG1, CONFIG2, LSRX, HPD and CIO_SEL low (10k). All other port signals can be NC.

Not used in host mode.

8 - GPIO_15 9 - GPIO_11 10 - GPIO_14 11 - GPIO_0 12 - GPIO_12 13 - GPIO_10 14 - PB_LSTX 15 - PB_LSRX

NOTE: The following pins require testpoints:

3 - GPIO_3

2 - GPIO_2

1 - GPIO_1

0 - GPIO_13

4 - GPIO_5

7 - PCIE_RST_3_N

6 - PCIE_RST_2_N

5 - PCIE_RST_1_N

Divides 3.3V to 1.8V

DEBUG: For monitoring current/voltage

DEBUG: For monitoring clock

allows separation

R2881 FOR CYA,

STUFF ONE OF R2881/2.

5% 1/16W MF-LF

402

3.3K

R2890

71

5%

0

MF-LF

402

R2825

1/16W

5%

MF-LF 402

1/16W

100K

R2832

29

29 85

29

29 85

30

30 85

30

30 85

402

MF-LF

1/16W

5%

100K

R2830

5%

MF-LF

100K

402

1/16W

R2831

29 85

5%

0

402

MF-LF

1/16W

R2829

5%

402

R2893

MF-LF

1/16W

3.3K

0201

16V

X5R-CERM

C2829

0.1UF

10%

71 85

0201

16V

X5R-CERM

C2828

0.1UF

10%

0201

16V

X5R-CERM

C2827

0.1UF

10%

0201

16V

X5R-CERM

0.1UF

10%

C2826

0201

16V

X5R-CERM

C2825

0.1UF

10%

0201

16V

X5R-CERM

C2824

0.1UF

10%

0201

16V

X5R-CERM

C2823

0.1UF

10%

0201

16V

X5R-CERM

C2822

0.1UF

10%

201

1/20W MF

R2855

1K

1%

16V

X5R-CERM

0201

C2821

0.1UF

10%

X5R-CERM

0201

16V

C2820

0.1UF

10%

0201

16V

X5R-CERM

C2830

0.1UF

10%

0201

16V

X5R-CERM

C2831

0.1UF

10%

0201

16V

X5R-CERM

C2832

0.1UF

10%

0201

16V

X5R-CERM

C2833

0.1UF

10%

0201

16V

X5R-CERM

C2834

0.1UF

10%

0201

16V

X5R-CERM

C2835

0.1UF

10%

0201

16V

X5R-CERM

C2836

0.1UF

10%

0201

16V

X5R-CERM

C2837

0.1UF

10%

0201

16V

X5R-CERM

C2838

0.1UF

10%

0201

16V

X5R-CERM

C2839

0.1UF

10%

71 85

C2890

402

CERM

6.3V

10%

1UF

71 85

29

30

28

30 85

30

20

29 85

29

26 29

29

26 29

26 30

30

26 30

28

12

CACTUSRIDGE4C

CRITICAL

OMIT_TABLE

FCBGA

U2800

28

19 79

5%

10K

402

MF-LF

1/16W

R2898

1/16W MF-LF

1%

806

402

R2895

5%

1K

402

1/16W MF-LF

R2896

5%

10K

1/16W

NO STUFF

MF-LF

402

R2899

11 77

28

OMIT_TABLE

U2890

MLP

M95256-RMC6XG

CRITICAL

5%

100K

MF-LF

1/16W

402

R2897

NONE

NOSTUFF

NONE

402

NONE

OMIT

R2815

5%

10K

1/16W MF-LF

402

R2888

5% 1/16W

10K

402

MF-LF

R2887

5%

10K

1/16W

402

MF-LF

R2886

5%

10K

402

MF-LF

1/16W

R2885

5%

10K

1/16W

402

MF-LF

R2880

5%

10K

1/16W

402

MF-LF

NO STUFF

R2882

20

26 31

0402

X7R-CERM

NO STUFF

16V

C2810

0.1UF

10%

5%

1/16W

47K

402

MF-LF

R2810

20

12

5%

10K

1/16W

402

MF-LF

R2883

5%

0

402

1/16W MF-LF

R2881

14 26

5%

402

MF-LF

3.3K

1/16W

R2889

5%

3.3K

1/16W

402

MF-LF

R2894

MF 0201

R2801

0

1/20W

5%

41

0201

X5R-CERM

16V

C2801

0.1UF

10%

0201

X5R-CERM

16V

C2800

0.1UF

10%

0201

X5R-CERM

16V

C2802

0.1UF

10%

0201

X5R-CERM

16V

C2803

0.1UF

10%

5%

MF-LF

1/16W

R2892

402

3.3K

0201

X5R-CERM

16V

C2804

0.1UF

10%

0201

X5R-CERM

16V

C2805

0.1UF

10%

0201

X5R-CERM

16V

C2806

0.1UF

10%

0201

X5R-CERM

16V

C2807

0.1UF

10%

0201

16V

X5R-CERM

C2840

0.1UF

10%

0201

16V

X5R-CERM

C2841

0.1UF

10%

0201

X5R-CERM

16V

C2842

0.1UF

10%

5%

3.3K

1/16W

402

MF-LF

R2891

0201

X5R-CERM

16V

C2843

0.1UF

10%

0201

16V

X5R-CERM

C2845

0.1UF

10%

0201

16V

X5R-CERM

C2844

0.1UF

10%

0201

16V

X5R-CERM

C2846

0.1UF

10%

0201

16V

X5R-CERM

C2847

0.1UF

10%

13 77

Thunderbolt Host (1 of 2)

SYNC_MASTER=J16_MAX

SYNC_DATE=02/11/2013

DP_TBTSRC_HPD

TP_DP_TBTSRC_AUXCH_CN

TBT_GO2SX_BIDIR

=TBT_WAKE_L TBT_CIO_PLUG_EVENT

SYSCLK_CLK25M_TBT

DP_TBTSNK0_AUXCH_N

TBT_GPIO_9

TBT_DDC_XBAR_EN_L

=PP3V3_TBTLC_RTR

PCIE_TBT_D2R_N<3>

PCIE_TBT_D2R_N<2>

=PP3V3_S4_TBT

=PP3V3_TBTLC_RTR

=PP3V3_S4_TBT

PCIE_TBT_R2D_C_P<3>

PCIE_TBT_R2D_C_N<2>

DP_TBTSNK0_ML_P<3>

DP_TBTSNK0_ML_N<3>

DP_TBTSNK1_ML_N<0>

DP_TBTSNK1_ML_C_N<1>

DP_TBTSNK0_AUXCH_C_N

DP_TBTSNK0_ML_C_P<1>

DP_TBTSNK0_ML_C_N<1>

DP_TBTSNK1_ML_P<0>

PCIE_TBT_R2D_C_N<3>

DP_TBTSNK1_AUXCH_N

DP_TBTSNK0_AUXCH_P

DP_TBTSNK1_ML_C_N<2>

DP_TBTSNK1_ML_N<1>

PCIE_TBT_D2R_P<0>

PCIE_TBT_D2R_N<0>

PCIE_TBT_D2R_P<1>

PCIE_TBT_D2R_N<1>

PCIE_TBT_D2R_P<3>

DP_TBTSNK0_ML_C_P<0>

DP_TBTSNK0_ML_C_N<0>

DP_TBTSNK0_ML_C_P<2>

DP_TBTSNK0_ML_C_N<2>

DP_TBTSNK0_ML_C_P<3>

DP_TBTSNK0_ML_C_N<3>

DP_TBTSNK1_ML_C_P<0>

DP_TBTSNK1_ML_C_N<0>

DP_TBTSNK1_ML_C_P<1>

DP_TBTSNK1_ML_C_P<2>

DP_TBTSNK1_ML_C_P<3>

DP_TBTSNK1_ML_C_N<3>

DP_TBTSNK1_AUXCH_C_P

DP_TBTSNK1_AUXCH_C_N

DP_TBTSNK0_ML_N<1>

DP_TBTSNK0_ML_N<2>

DP_TBTSNK1_ML_P<1>

DP_TBTSNK1_ML_P<2>

DP_TBTSNK1_ML_P<3>

DP_TBTSNK1_ML_N<3>

DP_TBTSNK1_AUXCH_P

DP_TBTSNK1_ML_N<2>

PCIE_TBT_R2D_C_N<1>

PCIE_TBT_R2D_C_P<1>

PCIE_TBT_R2D_C_N<0>

PCIE_TBT_R2D_C_P<0>

PCIE_TBT_R2D_C_P<2>

TBT_A_HV_EN TBT_B_HV_EN

TBT_PWR_REQ_L

DP_TBTSNK0_ML_P<1>

TBT_GPIO_14

=TBT_CLKREQ_L

TP_TBT_PCIE_RESET2_L TP_TBT_PCIE_RESET3_L

TP_TBT_PCIE_RESET1_L

TP_TBT_PCIE_RESET0_L

TBT_RBIAS

DP_TBTSNK0_ML_P<3>

TBT_TEST_PWR_GOOD

JTAG_TBT_TCK

JTAG_TBT_TMS

TP_TBT_XTAL25OUT

PCIE_CLK100M_TBT_N

PCIE_CLK100M_TBT_P

TBT_RSENSE

PCIE_TBT_D2R_C_P<3>

TBT_A_DP_PWRDN

TBT_A_HV_EN TBT_A_CIO_SEL

DP_TBTPA_AUXCH_C_N

DP_TBTPA_HPD

DP_TBTPA_AUXCH_C_P

DP_TBTPA_ML_C_P<3> DP_TBTPA_ML_C_N<3>

DP_TBTPA_ML_C_P<1> DP_TBTPA_ML_C_N<1>

TBT_A_LSTX TBT_A_LSRX

TBT_A_D2R_P<1> TBT_A_D2R_N<1>

TBT_A_R2D_C_P<1> TBT_A_R2D_C_N<1>

TBT_A_CONFIG1_BUF TBT_A_CONFIG2_RC

TBT_A_D2R_P<0> TBT_A_D2R_N<0>

TBT_A_R2D_C_P<0> TBT_A_R2D_C_N<0>

DP_TBTSNK1_HPD

DP_TBTSNK1_AUXCH_P DP_TBTSNK1_AUXCH_N

DP_TBTSNK1_ML_P<0> DP_TBTSNK1_ML_N<0>

DP_TBTSNK1_ML_P<1> DP_TBTSNK1_ML_N<1>

DP_TBTSNK1_ML_P<2> DP_TBTSNK1_ML_N<2>

DP_TBTSNK1_ML_P<3> DP_TBTSNK1_ML_N<3>

DP_TBTSNK0_ML_N<0>

DP_TBTSNK0_AUXCH_P

DP_TBTSNK0_ML_N<1>

DP_TBTSNK0_ML_P<0>

DP_TBTSNK0_ML_N<2>

DP_TBTSNK0_ML_N<3>

DP_TBTSNK0_ML_P<2>

JTAG_TBT_TDO

TP_TBT_THERM_DP

DP_TBTPB_AUXCH_C_P DP_TBTPB_AUXCH_C_N

TBT_B_HV_EN

TBT_B_DP_PWRDN

TBT_B_CIO_SEL

DP_TBTPB_ML_C_P<3>

TBT_B_LSTX

TBT_B_D2R_N<1>

DP_TBTPB_ML_C_P<1> DP_TBTPB_ML_C_N<1>

DP_TBTPB_ML_C_N<3>

TBT_B_R2D_C_P<1>

TBT_B_R2D_C_N<0>

TBT_B_D2R_P<0>

TBT_B_CONFIG1_BUF

TBT_B_D2R_N<0>

TBT_B_CONFIG2_RC

TBT_B_R2D_C_N<1>

TBT_GPIO_14 TBT_DDC_XBAR_EN_L

TP_DP_TBTSRC_ML_CP<0>

TP_DP_TBTSRC_ML_CN<1>

TP_DP_TBTSRC_ML_CN<2>

TP_DP_TBTSRC_ML_CP<1>

TP_DP_TBTSRC_ML_CN<3>

TP_DP_TBTSRC_ML_CP<2>

TP_DP_TBTSRC_ML_CP<3>

TBT_TMU_CLK_OUT TBT_TMU_CLK_IN

TBT_MONOBSP

PCIE_TBT_R2D_N<1>

PCIE_TBT_R2D_N<2>

TP_TBT_MONDC1

TP_TBT_MONDC0

TBT_MONOBSN

PCIE_TBT_D2R_C_N<0>

PCIE_TBT_D2R_C_P<0>

PCIE_TBT_D2R_C_N<1>

PCIE_TBT_D2R_C_P<1>

PCIE_TBT_D2R_C_P<2>

PCIE_TBT_D2R_C_N<3>

I2C_TBTRTR_SCL

I2C_TBTRTR_SDA

DP_TBTSNK0_ML_P<1>

TBT_B_R2D_C_P<0>

DP_TBTSNK0_HPD

DP_TBTSNK0_AUXCH_N

TBT_GPIO_9

TBT_PWR_EN

TBT_GO2SX_BIDIR

I2C_TBTRTR_SDA

TBT_B_D2R_P<1>

TBT_B_LSRX

DP_TBTPB_HPD

I2C_TBTRTR_SCL

TBT_B_DP_PWRDN

TBT_A_DP_PWRDN

=PP3V3_TBTLC_RTR

MAKE_BASE=TRUE

TBT_EN_CIO_PWR_L

JTAG_TBT_TDI

PCIE_TBT_D2R_C_N<2>

TBT_PCIE_RESET_L

PCIE_TBT_R2D_N<3>

PCIE_TBT_R2D_P<2>

PCIE_TBT_R2D_P<1>

PCIE_TBT_R2D_N<0>

PCIE_TBT_R2D_P<0>

PCIE_TBT_R2D_P<3>

TBT_EN_LC_PWR

SYSCLK_CLK25M_TBT_R

PCIE_TBT_D2R_P<2>

TBT_PWR_ON_POC_RST_L

DP_TBTSNK0_ML_N<0>

=PP3V3_TBTLC_RTR

DP_TBTSNK0_ML_P<0>

DP_TBTSNK0_ML_P<2>

TBTROM_WP_L

TBTROM_HOLD_L

TBT_SPI_CLK_RES

TBT_TEST_EN

TP_DP_TBTSRC_ML_CN<0>

TP_DP_TBTSRC_AUXCH_CP

DP_TBTSNK0_AUXCH_C_P

TBT_SPI_MOSI TBT_SPI_MISO TBT_SPI_CS_L TBT_SPI_CLK

051-0164

12.4.0

28 OF 123

26 OF 86

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1 2

1

2

1 2

2

1

AD19

AD15

AD13

AD9

AD11

AD5

AD7

W16

AD23

AC24

AB19

AA18

AA16

AB15

AB13

AA12

AB9

AA10

W18

Y3

AA4

A14

A12

B15

A10

B13

B11

A8

C2

B9

V3

D3

Y1

V5

M5

T3

P3

AC2

AB1

AA2

J4

W2

U24

H5

N22

P1

R22

R24

N24

W24

B23

B21

A20

G6

U22

L6

W22

A22

L2 L4

M1

K3

E2

D1

Y7

R4

P5

AD3

V1

W4

R2

E16

D13

E18

D15

E20

D17

A6

D19

U6

B5

D5

E6

D7

E8

D9

E10

D11

E12

B3

A4

T5

E24

G24

E22

G22

G4

K1

J24

L24

J22

L22

J6

N2

B17

A16

B19

A18

F3

H1

F1

M3

G2

H3

AD17

U20

AB21 AD21

AA24

AB23

AB3

AA6

N4

AB5

E14

J2

R6

U4

W20

N6 T1

U2

Y5

W6

K5

1

2

1 2

121

2

94

5

6

2

1

3

7

8

1

2

1

2

121

2

121

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1 2

1

2

1 2

1

2

1 2

41

14 26

26 85

26

26 31

26 27 28 70

26 27 28 29 30 68 70

26 27 28 70

26 27 28 29 30 68 70

26 85

26 29

26 30

26 85

26

72

26 85

77

26 85

72

26

41

77

26 85

26

26 85

26 30

26 29

26 27 28 70

77

79

26 85

26 27 28 70

26 85

41

85

VSSPE VSSPE

VSSPE

VSSPE VSSPE

VSSPE

VSSPE VSSPE

VSSPE VSSPE VSSPE

VSSPE VSSPE

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VCC1P0_DPAUX

VCC3P3_POC

VSSPE

VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE

VCC1P0_PE

VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE

VCC1P0 VCC1P0

VCC3P3_DP VCC3P3_DP

VCC3P3_DP

VCC3P3_CIO

VCC3P3

VCC1P0

VCC1P0 VCC1P0

VCC1P0

VCC1P0_ON

VCC3P3

VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE

VSSPE

VSSPE VSSPE VSSPE VSSPE

VSSPE

VSSPE VSSPE VSSPE

VSSPE

VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE

VSSPE

VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE

VSSPE

VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE

VSSPE

VCC3P3_DP

VCC3P3_DPAUX

(SYM 2 OF 2)

VCCGND

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

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THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

EDP: 10 mA

??? mW (Single-Port)

EDP: 240 mA

250 mW (Dual-Port)

EDP: 3000 mA

2700 mW (Dual-Port)

???? mW (Single-Port)

??? mW (Single Port) 250 mW (Dual Port) EDP: 1000 mA

EDP current / power consumption figures from CR DG v0.57, IBL doc #472455.

20%

1.0UF

0201-1

X5R

6.3V

C2945

20%

1.0UF

0201-1

X5R

6.3V

C2916

20%

6.3V

0402-1

CERM-X5R

10UF

C2905

20%

1.0UF

0201-1

X5R

6.3V

C2973

20%

1.0UF

0201-1

X5R

6.3V

C2974

20%

1.0UF

0201-1

X5R

6.3V

C2917

20%

1.0UF

0201-1

X5R

6.3V

C2913

20%

6.3V

0402-1

CERM-X5R

10UF

C2900

20%

6.3V

0402-1

CERM-X5R

10UF

C2901

20%

1.0UF

0201-1

X5R

6.3V

C2914

20%

1.0UF

0201-1

X5R

6.3V

C2915

OMIT_TABLE

CACTUSRIDGE4C

FCBGA

CRITICAL

U2800

20%

6.3V

0402-1

CERM-X5R

10UF

C2960

20%

1.0UF

0201-1

X5R

6.3V

C2972

20%

1.0UF

0201-1

X5R

6.3V

C2971

20%

1.0UF

0201-1

X5R

6.3V

C2910

20%

1.0UF

0201-1

X5R

6.3V

C2970

20%

1.0UF

0201-1

X5R

6.3V

C2990

20%

1.0UF

0201-1

X5R

6.3V

C2911

20%

1.0UF

0201-1

X5R

6.3V

C2912

20%

1.0UF

0201-1

X5R

6.3V

C2944

20%

1.0UF

0201-1

X5R

6.3V

C2943

20%

1.0UF

0201-1

X5R

6.3V

C2942

20%

1.0UF

0201-1

X5R

6.3V

C2941

20%

1.0UF

0201-1

X5R

6.3V

C2940

Thunderbolt Host (2 of 2)

SYNC_MASTER=J16_MAX

SYNC_DATE=02/11/2013

=PP3V3_TBTLC_RTR

=PP1V05_TBTLC_RTR

=PP1V05_TBTCIO_RTR

=PP3V3_S4_TBT

051-0164

12.4.0

29 OF 123

27 OF 86

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

212

1

2

1

C18

C20

C14

C16

C12

C10

B7

B1

AC8

AC6

AC4

AC22

AC18 AC20

AC16

AC14

AC12

AB7

AB17

AC10

AA8

AB11

AA14 AA20

AA22

A2

A24

U8

V9

U12

U16

T9

T13

T17

R8

R16

R12

P9

P17

P13

N16

N8

M9

N12

M17

L8

M13

L16

L12

K13

AD1

K9

H9

G8

K7

Y9

G10

G12

G14 G16

H19

G18

K19

M19 P19

T19

V15 V19

W12

W14

K11 K15

H13 H15

H11

R18

N18

L18

P7

M7

W10

V11

U10

T11

R14

R10

P15

N14

P11

N10

M15

M11

L14

L10

W8

T15

V7

U14

K17

J8

J16

J14

J12

J10

T7

C22 C24

C4

C6 C8

D21

E4

D23

F11 F13

F15

F17

F21

F19

F23 F5

F7

G20

F9

H21 H23

J18

J20 K21

K23

L20

M23

M21

N20

P21

P23 R20

T21

T23 U18

V17

V13

V21

V23 Y11

Y13

Y15 Y17

Y19

Y23

Y21

H17

H7

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

26 28 70

70

26 28 29 30 68 70

GND

VOUT

ON

VIN

OUT

IN

RESET*

OUT

EN

MR*

GND

THRM

IN

VDD

SENSE

+

-

PAD

(OD)

0.7V

DLY

VOUT

GND

ON

VIN

GND

VOUT

ON

VIN

SENSE

THRM

RESET*

CT

GND

MR*

VDD

PAD

OUT

IN

D

SG

IN

D

S G

OUT

D

GS

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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D

8 7 6 5 4 3

C

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A

NOTICE OF PROPRIETARY PROPERTY:

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12

D

A

C

PAGE TITLE

SHEET

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DRAWING NUMBER

REVISION

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THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

U3020

U3015

U3010

Pull-up: R2810

Intel investigating whether RC is sufficient.

TBT "POC" Power-up Reset

Vt = 2.33V +/- 2% Delay = 27.3ms

@ 1.0V

28.6 mOhm Max

TPS22924C

BOM options provided by this page:

- =TBT_CLKREQ_L

Signal aliases required by this page:

- =PP1V05_TBT_FET (1.05V FET Output)

- =PP1V05_TBT_P1V05TBTFET (1.05V FET Input)

- =PP3V3_S0_TBTPWRCTL

- =PP3V3_TBT_FET (3.3V FET Output)

- =PP3V3_TBT_P3V3TBTFET (3.3V FET Input)

DLY = 60 ms +/- 20%

1.05V TBT "CIO" Switch

TPS3808G25

(IPU)

Max Current = 4A (85C)

@ 1.05V

R(on)

Type

Part

Load Switch

11.5 mOhm Max

8 mOhm Typ

TPS22920

- =PPVIN_SW_TBTBST (8-13V Boost Input)

TBTBST:Y - Stuffs 15V boost circuitry.

- =PP15V_TBT_REG (15V Boost Output)

Power aliases required by this page:

- =TBT_RESET_L

Page Notes

Supervisor & CLKREQ# Isolation

Platform(PCIe) Reset

18.5 mOhm Typ

Load Switch

25.8 mOhm Max

3.3V TBT "LC" Switch

Part

R(on) @ 2.5V

Type

Max Current = 2A (85C)

20.3 mOhm Typ

Load Switch

TPS22924C

R(on)

Part

Type

Max Current = 2A (85C)

1.05V TBT "LC" Switch

Pull-up provided by SB page.

CRITICAL

CSP

TPS22924

U3010

26

10%

0.1UF

X5R

25V

402

C3000

20

26

10%

6.3V

402

1UF

CERM

C3010

10%

6.3V

1UF

CERM

402

C3015

TDFN

SLG4AP016V

CRITICAL

U3000

402

MF-LF

100K

5% 1/16W

R3007

10%

6.3V

NOSTUFF

CERM

402

1UF

C3016

5%

0

402

MF-LF

1/16W

R3016

CSP

CRITICAL

TPS22920

U3020

CSP

CRITICAL

TPS22924

U3015

10%

6.3V

402

CERM

1UF

C3020

QFN

CRITICAL

TPS3808

U3030

10%

0.1UF

X5R

25V 402

C3030

26

10% CERM

0.0047UF

25V 0402

C3031

14

SSM6N37FEAPE

SOT563

Q3025

26

5%

402

1/16W MF-LF

100K

R3020

SSM6N37FEAPE

SOT563

Q3025

100K

MF-LF

1/16W

402

5%

R3030

11

VESM

SSM3K15AMFVAPE

Q3040

26

MF-LF

5%

402

10K

1/16W

R3040

10%

0402

X7R-CERM

50V

330PF

C3025

44 45 69

10%

6.3V

1UF

CERM

402

C3011

402

1%

36.5K

1/16W MF-LF

R3011

Thunderbolt Power Support

SYNC_MASTER=J16_MAX

SYNC_DATE=02/11/2013

=PP1V05_S0_P1V05TBTFET

=TBT_RESET_L

=PP3V3_S0_P3V3TBTFET

TBT_EN_LC_RC1V05

=PP1V05_TBTLC_FET

=TBT_CLKREQ_L

TBT_EN_LC_RC3V3

=PP3V3_TBTLC_FET

TBT_CLKREQ_ISOL_L

MAKE_BASE=TRUE

TBT_CLKREQ_L

=PP3V3_S0_TBTPWRCTL

TBT_EN_LC_PWR

SMC_DELAYED_PWRGD

=PP3V3_S0_PCH_GPIO

=PP3V3_TBTLC_RTR

=PP3V3_S4_TBT

=PP1V05_S0_P1V05TBTFET

TBTPOCRST_CT

TBT_EN_CIO_PWR_L

TBT_PCIE_RESET_L

PP1V05_TBTLC

TBT_SW_RESET_L

=PP1V05_TBTCIO_FET

TBT_EN_LC_ISOL

=PP3V3_TBTLC_RTR

TBTPOCRST_MR_L

TBT_EN_CIO_PWR

TBT_PWR_ON_POC_RST_L

28 OF 86

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12.4.0

051-0164

C1

A1

B1

C2

B2

A2

2

1

2

1

2

1

4

8

6

3

5

9

7

1

2

1

2

1

1 2

A1

D1

D2

A2

B2 C2

B1 C1

C1

A1 B1

C2

B2

A2

2

1

2

7

6

3

5

4

1

2

1

2

1

6

1

2

1

2

3

4

5

1

2

1

2

3

1

2

1

2

1

1 2

28 70

70

11 12 14 70

26 27 28 70

26 27 29 30 68 70

28 70

70 82

70

26 27 28 70

IN IN

OUT

IN IN

ISET_S3

V3P3OUT

ISET_S0

EN

S0

HV_EN

RSVD

GND

THRM

OUT

VHV

ISET_V3P3

RSVD

V3P3

PAD

IN

DPMLO+ DPMLO-

VDD

DP-

DP+

DDC_CLK

AUX+

AUX-

AUXIO_EN

AUXIOAUXIO+

THMPAD

GND

BIASIN

BIASOUT

DDC_DAT

CA_DETOUT

CA_DET

DP_PD

LSTX LSRX

HPDOUT

HPD

OUT

BI IN

IN

OUT

OUT OUT

OUT

IN IN

BI BI

IN IN

OUT

ML_LANE1N

CONFIG1

SHLD

GND4

DP_PWR

CONFIG2

AUX_CHN

HPD

AUX_CHP

GND2

ML_LANE3N

GND1

ML_LANE3P

ML_LANE0N

ML_LANE1P

GND3

GND0

ML_LANE0P

SHLD

RETURN

ML_LANE2N

ML_LANE2P

PORT A

NC

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

For 12V systems:

for single-fault protection(S0,S3 only)

Nominal Min Max

Thunderbolt Connector A

down HPD input with

NOTE: Polarity Swapped for layout!

3.3V/HV Power MUX

IHVS3 890mA 830mA 930mA (assumes 3S, 9-12.6V, 7.5-11.7W)

Nominal Min Max IV3P3 1100mA 1030mA 1200mA IHVS0 890mA 830mA 930mA (assumes 15V, 12W minimum)

TBT Dir

TBT: TX_0

below

12V: See

V3P3 must be S4 to support wake from Thunderbolt devices.

(0-18.9V)

(Both C’s)

TBT: LSX_A_R2P/P2R (P/N)

TBT: LSX_R2P/P2R (P/N)

DP Dir

(Both C’s)

greater than or equal

Sink HPD range:

to 100K (DPv1.1a).

High: 2.0 - 5.0V Low: 0 - 0.8V

(Both C’s)

TBT: RX_1 Bias Sink

TBT: TX_1

(0-18.9V)

on AC-coupled signals.

470k R’s for ESD protection

18.9V Max

TBT: Terminated

(Both D’s)

Two Rs in series required by CD3210

NOTE: Polarity Swapped for layout!

(Both C’s)

NOTE: Polarity Swapped for layout!

DP Dir

DP Source must pull

IHVS0/S3 1120mA 1090mA 1170mA (12W minimum)

J16:514-0824 / J17:514-0831

10% 50V

0.01UF

X7R-CERM

0402

C3200

26 85

10%

0201

X5R-CERM

0.01UF

C3202

25V

201

MF

12

1/20W

R3201

5%

10%

0.01UF

50V X7R-CERM 0402

C3201

201

1/20W

MF

GND_VOID=TRUE

NO_XNET_CONNECTION=TRUE

1K

R3294

5%

201

1/20W MF

GND_VOID=TRUE

1K

NO_XNET_CONNECTION=TRUE

R3295

5%

50V

30PF

C0G-NP0

0402

C3298

5%

30PF

50V C0G-NP0 0402

C3299

5%

201

1/20W MF

100K

R3241

5%

NO_XNET_CONNECTION=TRUE

CRITICAL

650NH-5%-0.430MA-0.52OHM

GND_VOID=TRUE

0603

L3298

0603

CRITICAL

NO_XNET_CONNECTION=TRUE

650NH-5%-0.430MA-0.52OHM

GND_VOID=TRUE

L3299

0.1UF

10V

20%

CERM

C3281

402

6.3V

22UF

20%

X5R-CERM-1

603

CRITICAL

C3280

6.3V

100UF

POLY-TANT

CRITICAL

20%

CASE-B2-SM

C3287

201

1/20W

MF

1M

R3252

5%

201

1/20W MF

1M

R3251

5%

10%

330PF

16V

X7R-CERM

0201

C3294

10%

330PF

16V X7R-CERM 0201

C3295

201

1/20W

MF

GND_VOID=TRUE

2.2K

R3298

5%

201

1/20W MF

GND_VOID=TRUE

2.2K

R3299

5%

FERR-120-OHM-3A

0603

L3200

26

10%

0.1UF

603-1

50V X7R

C3210

GND_VOID=TRUE

TSLP-2-7

CRITICAL

BAR90-02LRH

D3299

GND_VOID=TRUE

CRITICAL

TSLP-2-7

BAR90-02LRH

D3298

201

GND_VOID=TRUE

MF

470K

1/20W

R3270

5%

201

470K

GND_VOID=TRUE

MF

1/20W

R3271

5%

X5R

6.3V

0.22UF

20%

GND_VOID=TRUE

0201

C3271

X5R

6.3V

20%

0.22UF

GND_VOID=TRUE

0201

C3270

26 85

X5R

6.3V

GND_VOID=TRUE

20%

0.22UF

0201

C3272

X5R

6.3V

0.22UF

GND_VOID=TRUE

20%

0201

C3273

201

470K

GND_VOID=TRUE

MF

1/20W

R3273

5%

201

MF

1/20W

GND_VOID=TRUE

470K

R3272

5%

10%

0.01UF

0201

X5R-CERM

C3205

25V

10%

0201

0.01UF

X5R-CERM

C3206

25V

CD3210A0RGP

CRITICAL

QFN

U3210

26

68

30 68

TBTHV:P15V

MF-LF

1/16W

22.6K

1%

R3210

402

1% 1/16W MF-LF

22.6K

R3211

TBTHV:P15V

402

1/16W

1% MF-LF

36.5K

R3212

402

10%

0.1UF

X7R 603-1

50V

C3211

HVQFN

CBTL05023

CRITICAL

U3220

201

1/20W

MF

100K

R3229

5%

201

1/20W MF

100K

R3228

5%

10%

0.1UF

6.3V

C3220

CERM-X5R

0201

10%

0.1UF

6.3V

C3221

CERM-X5R

0201

26

31

11 18 30

26

201

1M

MF

1/20W

R3226

5%

201

10K

MF

1/20W

R3227

5%

10%

0.1UF

6.3V

C3225

CERM-X5R 0201

26

201

0.47UF

4V

CERM-X5R-1

20%

GND_VOID=TRUE

C3277

201

GND_VOID=TRUE

4V

CERM-X5R-1

20%

0.47UF

C3276

26 85

201

4V

0.47UF

20% CERM-X5R-1

GND_VOID=TRUE

C3275

201

GND_VOID=TRUE

0.47UF

4V

CERM-X5R-1

20%

C3274

26 85

X5R

6.3V

0.22UF

20%

0201

C3232

X5R

6.3V

0.22UF

20%

0201

C3233

26 85

10%

0.1UF

0201

CERM-X5R

6.3V

C3230

10%

0.1UF

0201

CERM-X5R

6.3V

C3231

26 85

X5R

6.3V

20%

0201

0.22UF

C3278

X5R

6.3V

20%

0.22UF

0201

C3279

26 85

201

1/20W

MF

470K

R3279

5%

201

MF

470K

1/20W

R3278

5%

10%

X5R-CERM

4.7UF

0603

C3215

25V

TBTHV:P15V

22.6K

1/16W MF-LF

1%

R3213

402

22.6K

TBTHV:P15V

1% 1/16W MF-LF

R3214

402

CRITICAL

74AUP1T97GM

SOT886

U3260

26

10%

0.1UF

0201

X5R-CERM

16V

C3260

DUAL-MDP-K70

CRITICAL

F-ANG-TH

J3200

65

SYNC_DATE=02/11/2013

SYNC_MASTER=J16_MAX

Thunderbolt Connector A

ALL

128S0398 128S0220

3.3V INPUT CAP

ALL

TI Alternate

311S0593311S0596

R3211,R3214

2

TBTHV:P12V

114S0338

RES,MTL FILM,1/16W,17.8K,1,0402,SMD,LF

R3210,R3213

2

TBTHV:P12V

RES,MTL FILM,1/16W,17.8K,1,0402,SMD,LF

114S0338

MIN_NECK_WIDTH=0.20 MM

PPHV_SW_TBTAPWR

MIN_LINE_WIDTH=0.38 MM

VOLTAGE=15V

TBTAPWRSW_ISET_V3P3

DP_TBTPA_ML_N<3>

TBT_A_D2R1_AUXDDC_N

TBT_A_D2R_C_P<0> TBT_A_D2R_C_N<0>

TBTACONN_7_C

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=18.9V

TBT_A_R2D_N<0>

TBT_A_R2D_P<0>

TBT_A_HPD

TBT_A_LSRX_UNBUF

TBT_A_D2R_C_P<1>

DP_A_AUXCH_DDC_P

TBT_A_CONFIG2_RC

DP_A_AUXCH_DDC_N

TBT_A_D2R_C_N<1>

TBT_A_R2D_N<1>

TBT_A_R2D_P<1>

VOLTAGE=18.9V

MIN_LINE_WIDTH=0.38 MM

TBTACONN_1_C

MIN_NECK_WIDTH=0.20 MM

DP_TBTPA_HPD

TBT_A_DP_PWRDN

DP_TBTPA_AUXCH_P

DP_TBTPA_AUXCH_N

TBTAPWRSW_ISET_S0

DP_TBTPA_ML_C_N<3>

DP_TBTPA_ML_C_P<3>

TBTAPWRSW_ISET_S0_R

TBTAPWRSW_ISET_S3

=PP3V3_S4_TBTAPWRSW

=TBTAPWRSW_EN

=PP3V3_S4_TBT

TBT_A_LSRX

DP_TBTPA_ML_C_N<1>

DP_TBTPA_AUXCH_C_P

=PPHV_SW_TBTAPWRSW

TBT_A_LSTX

DP_AUXIO_EN

DP_A_AUXCH_DDC_P

TBT_A_CONFIG1_RC

DP_TBTPA_DDC_CLK

TBT_A_HPD

TBT_A_R2D_C_N<1> TBT_A_R2D_C_P<1>

DP_TBTPA_ML_P<1>

DP_A_LSX_ML_P<1> DP_A_LSX_ML_N<1>

DP_TBTPA_DDC_DATA

TBT_A_CONFIG1_BUF

TBT_A_R2D_C_N<0>

TBT_A_R2D_C_P<0>

DP_TBTPA_ML_C_P<1>

DP_A_AUXCH_DDC_N

TBT_A_CIO_SEL

=PP3V3_S4_TBT

DP_TBTPA_ML_N<1>

DP_A_LSX_ML_P<1>

TBT_A_D2R1_AUXDDC_P

DP_A_LSX_ML_N<1>

VOLTAGE=3.3V

TBT_A_BIAS

TBT_A_D2R_P<0>

TBT_A_CONFIG1_RC

TBT_A_BIAS

DP_TBTPA_AUXCH_C_N

TBT_A_D2R_N<0>

VOLTAGE=15V

MIN_NECK_WIDTH=0.20 MM

PP3V3RHV_SW_TBTAPWR

MIN_LINE_WIDTH=0.38 MM

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MM

VOLTAGE=18.9V

TBTACONN_20_RC

DP_TBTPA_ML_P<3>

TBT_A_D2R_N<1> TBT_A_D2R_P<1>

=TBT_S0_EN

TBT_A_HV_EN

TBTAPWRSW_ISET_S3_R

051-0164

12.4.0

32 OF 123

29 OF 86

2

1

2

1

1 2

2

1

121

2

212

1

2

2 1

2

1

2

11

2

121

2

212

1

121

2

21

2

1

A K

1

2

1

2

1 2

1

2

1

2

1 2

9

18

10

5

17

11

16

123

4

13

21

12

14

7

6

8

15

20

19

121

2

1

2

1

19

20

15

3

10

11

5

8

7

2

23

22

25

21

9

1

24

4

16 18

6

14

13

12 17

1

2

1

2

1

2

1

2

1

2

1

1 2

2

1

121

2

6

3

4

2

1

5

2

1

11

4

515049

47

464544

43

14

20

6

18

2

16

8

12

42

7

10

5

9

13

1 3

48

41

52

19

17

15

85

29

85

29 85

85

70

26 27 28 29 30 68 70

70

29 85

29

85

29 85

26 27 28 29 30 68 70

85

29 85

85

29 85

29

85

IN IN

OUT

IN IN

ISET_S3

V3P3OUT

ISET_S0

EN

S0

HV_EN

RSVD

GND

THRM

OUT

VHV

ISET_V3P3

RSVD

V3P3

PAD

IN

DPMLO+ DPMLO-

VDD

DP-

DP+

DDC_CLK

AUX+

AUX-

AUXIO_EN

AUXIOAUXIO+

THMPAD

GND

BIASIN

BIASOUT

DDC_DAT

CA_DETOUT

CA_DET

DP_PD

LSTX LSRX

HPDOUT

HPD

OUT

BI IN

IN

OUT

OUT OUT

OUT

IN IN

BI BI

IN IN

OUT

GND1

ML_LANE0N

ML_LANE1P

AUX_CHN

AUX_CHP

CONFIG1 CONFIG2

DP_PWR

GND2

HPD

ML_LANE3N

ML_LANE3P

SHLD

GND4

ML_LANE0P

GND0

RETURN

ML_LANE2N

ML_LANE2P

GND3

ML_LANE1N

PORT B

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

J16:514-0824 / J17:514-0831

DP Dir

Nominal Min Max

IHVS0/S3 1120mA 1090mA 1170mA (12W minimum)

12V: See

NOTE: Polarity Swapped for Layout!

wake from Thunderbolt devices.

3.3V/HV Power MUX

Nominal Min Max

IHVS3 890mA 830mA 930mA (assumes 3S, 9-12.6V, 7.5-11.7W)

Two Rs in series required by CD3210 for single-fault protection(S0,S3 only)

V3P3 must be S4 to support

IHVS0 890mA 830mA 930mA (assumes 15V, 12W minimum)

below

18.9V Max

IV3P3 1100mA 1030mA 1200mA

(Both C’s)

TBT: TX_1

NOTE: Polarity Swapped for Layout!

down HPD input with

DP Source must pull

DP Dir

TBT: TX_0

TBT: Terminated

(Both D’s)

to 100K (DPv1.1a).

Sink HPD range:

greater than or equal

(Both C’s)

TBT Dir

(0-18.9V)

TBT: RX_1 Bias Sink

(Both C’s)

on AC-coupled signals.

470k R’s for ESD protection

Low: 0 - 0.8V

High: 2.0 - 5.0V

TBT: LSX_R2P/P2R (P/N)

TBT Dir

For 12V systems:

NOTE: Polarity Swapped for Layout!

(Both C’s)

Thunderbolt Connector B

TBT: LSX_B_R2P/P2R (P/N)

C3300

50V

0.01UF

X7R-CERM

0402

10%

26 85

25V

C3302

0201

X5R-CERM

0.01UF

10%

5%

R3301

MF

12

1/20W

201

C3301

0.01UF

50V X7R-CERM 0402

10%

5%

R3394

1/20W

MF

1K

GND_VOID=TRUE

NO_XNET_CONNECTION=TRUE

201

5%

R3395

1/20W MF

NO_XNET_CONNECTION=TRUE

1K

GND_VOID=TRUE

201

5%

C3398

C0G-NP0

30PF

50V

0402

5%

C3399

0402

C0G-NP0

30PF

50V

5%

R3341

100K

MF

1/20W

201

L3398

650NH-5%-0.430MA-0.52OHM

CRITICAL

0603

NO_XNET_CONNECTION=TRUE

GND_VOID=TRUE

L3399

GND_VOID=TRUE

CRITICAL

0603

650NH-5%-0.430MA-0.52OHM

NO_XNET_CONNECTION=TRUE

402

C3381

CERM

10V

20%

0.1UF

C3380

X5R-CERM-1

22UF

603

20%

CRITICAL

6.3V

C3387

100UF

CASE-B2-SM

POLY-TANT

20%

CRITICAL

6.3V

5%

R3352

1/20W

MF

1M

201

5%

R3351

1/20W MF

1M

201

C3394

330PF

16V

X7R-CERM

0201

10%

C3395

330PF

16V X7R-CERM 0201

10%

5%

R3398

MF

2.2K

GND_VOID=TRUE

1/20W

201

5%

R3399

1/20W MF

2.2K

GND_VOID=TRUE

201

L3300

0603

FERR-120-OHM-3A

26

C3310

50V X7R 603-1

0.1UF

10%

D3399

BAR90-02LRH

TSLP-2-7

CRITICAL

GND_VOID=TRUE

D3398

TSLP-2-7

BAR90-02LRH

CRITICAL

GND_VOID=TRUE

5%

R3370

GND_VOID=TRUE

470K

MF

1/20W

201

5%

R3371

470K

MF

1/20W

GND_VOID=TRUE

201

C3371

GND_VOID=TRUE

0.22UF

20%

0201

6.3V

X5R

C3370

20%

GND_VOID=TRUE

0201

0.22UF

6.3V

X5R

26 85

C3372

GND_VOID=TRUE

20%

0.22UF

0201

6.3V

X5R

C3373

GND_VOID=TRUE

20%

0.22UF

0201

6.3V

X5R

5%

R3373

GND_VOID=TRUE

470K

MF

1/20W

201

5%

R3372

470K

MF

1/20W

GND_VOID=TRUE

201

25V

C3305

0201

0.01UF

X5R-CERM

10%

25V

C3306

0201

0.01UF

X5R-CERM

10%

U3310

CD3210A0RGP

CRITICAL

QFN

26

68

29 68

402

R3310

1%

MF-LF

1/16W

TBTHV:P15V

22.6K

402

R3311

1/16W

TBTHV:P15V

MF-LF

1%

22.6K

402

R3312

1/16W

36.5K

MF-LF

1%

C3311

X7R

50V

603-1

0.1UF

10%

U3320

CRITICAL

CBTL05023

HVQFN

5%

R3329

1/20W

MF

100K

201

5%

R3328

1/20W MF

100K

201

0201

CERM-X5R

C3320

6.3V

0.1UF

10%

0201

CERM-X5R

C3321

6.3V

0.1UF

10%

26

31

11 18 29

26

5%

R3326

1/20W

MF

1M

201

5%

R3327

1/20W MF

10K

201

0201

CERM-X5R

C3325

6.3V

0.1UF

10%

26

C3377

0.47UF

GND_VOID=TRUE

4V

CERM-X5R-1

20%

201

C3376

0.47UF

GND_VOID=TRUE

4V

CERM-X5R-1

20%

201

26 85

C3375

0.47UF

GND_VOID=TRUE

4V

20% CERM-X5R-1

201

C3374

0.47UF

GND_VOID=TRUE

4V

CERM-X5R-1

20%

201

26 85

C3332

20%

0201

0.22UF

6.3V

X5R

C3333

0.22UF

20%

0201

6.3V

X5R

26 85

C3330

6.3V

CERM-X5R

0201

0.1UF

10%

C3331

6.3V

CERM-X5R

0201

0.1UF

10%

26 85

C3378

0.22UF

20%

0201

6.3V

X5R

C3379

20%

0.22UF

0201

6.3V

X5R

26 85

5%

R3379

MF

470K

1/20W

201

5%

R3378

1/20W

MF

470K

201

402

R3313

22.6K

1%

MF-LF

1/16W

TBTHV:P15V

402

R3314

TBTHV:P15V

1%

MF-LF

1/16W

22.6K

25V

C3315

X5R-CERM

4.7UF

0603

10%

U3360

CRITICAL

74AUP1T97GM

SOT886

C3360

X5R-CERM

16V

0201

0.1UF

10%

26

65

J3200

F-ANG-TH

DUAL-MDP-K70

CRITICAL

2

TBTHV:P12V

114S0338

RES,MTL FILM,1/16W,17.8K,1,0402,SMD,LF

R3310,R3313

114S0338

2

RES,MTL FILM,1/16W,17.8K,1,0402,SMD,LF

TBTHV:P12V

R3311,R3314

Thunderbolt Connector B

SYNC_MASTER=J16_MAX

SYNC_DATE=02/11/2013

DP_B_LSX_ML_P<1>

TBT_B_HPD

DP_B_LSX_ML_N<1>

TBT_B_CONFIG1_RC

TBT_B_D2R_C_N<1>

TBT_B_CONFIG2_RC

TBT_B_D2R_N<0>

DP_TBTPB_ML_C_P<3>

=PP3V3_S4_TBT

DP_TBTPB_AUXCH_C_N

TBT_B_R2D_N<0>

DP_B_LSX_ML_P<1>

TBT_B_R2D_P<0>

TBTBCONN_1_C

MIN_LINE_WIDTH=0.38 MM

VOLTAGE=18.9V

MIN_NECK_WIDTH=0.20 MM

TBT_B_R2D_N<1>

TBT_B_R2D_P<1>

DP_B_LSX_ML_N<1>

TBT_B_BIAS

TBT_B_CIO_SEL

TBT_B_D2R_P<0>

TBT_B_CONFIG1_RC

DP_TBTPB_HPD

TBT_B_DP_PWRDN

TBT_B_CONFIG1_BUF

DP_TBTPB_DDC_DATA DP_TBTPB_DDC_CLK

DP_B_AUXCH_DDC_P

DP_B_AUXCH_DDC_N

TBT_B_BIAS

VOLTAGE=3.3V

DP_TBTPB_AUXCH_C_P

TBT_B_R2D_C_N<1>

DP_B_AUXCH_DDC_P

TBT_B_D2R_P<1>

DP_TBTPB_AUXCH_N

TBT_B_LSTX

DP_TBTPB_ML_P<1>

DP_TBTPB_ML_C_P<1> DP_TBTPB_ML_C_N<1>

DP_B_AUXCH_DDC_N

TBT_B_R2D_C_N<0>

TBT_B_R2D_C_P<0>

TBT_B_R2D_C_P<1>

TBT_B_D2R_C_P<1>

DP_AUXIO_EN

DP_TBTPB_ML_N<1>

DP_TBTPB_AUXCH_P

TBT_B_D2R_N<1>

TBT_B_LSRX_UNBUF

=PP3V3_S4_TBT

TBT_B_LSRX

VOLTAGE=18.9V

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MM

TBTBCONN_7_C

=PP3V3_S4_TBTBPWRSW

TBTBPWRSW_ISET_S0

=TBTBPWRSW_EN

=TBT_S0_EN

=PPHV_SW_TBTBPWRSW

VOLTAGE=15V

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM

PPHV_SW_TBTBPWR

TBTBPWRSW_ISET_V3P3

TBT_B_HV_EN

TBTBPWRSW_ISET_S0_R

TBTBPWRSW_ISET_S3_R

TBTBPWRSW_ISET_S3

DP_TBTPB_ML_C_N<3>

DP_TBTPB_ML_N<3>

TBT_B_HPD

DP_TBTPB_ML_P<3>

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MM VOLTAGE=15V

PP3V3RHV_SW_TBTBPWR

TBT_B_D2R_C_P<0> TBT_B_D2R_C_N<0>

MIN_LINE_WIDTH=0.38 MM

TBTBCONN_20_RC

VOLTAGE=18.9V

MIN_NECK_WIDTH=0.20 MM

TBT_B_D2R1_AUXDDC_P TBT_B_D2R1_AUXDDC_N

051-0164

12.4.0

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30 OF 86

2

1

2

1

1 2

2

1

121

2

212

1

2

2 1

2

1

2

11

2

121

2

212

1

121

2

21

2

1

A K

1

2

1

2

1 2

1

2

1

2

1 2

9

18

10

5

17

11

16

123

4

13

21

12

14

7

6

8

15

20

19

121

2

1

2

1

19

20

15

3

10

11

5

8

7

2

23

22

25

21

9

1

24

4

16 18

6

14

13

12 17

1

2

1

2

1

2

1

2

1

2

1

1 2

121

2

1

6

3

4

2

1

5

2

1

27

25

29

38

36

24 26

40

28

22

32

30

53

54

565758

59

6061626364

55

34

23

21

39

37

35

33

31

30 85

30

30 85

30

85

26 27 28 29 30 68 70

85

30 85

85

30 85

30

30 85

30

30 85

85

30 85

85

26 27 28 29 30 68 70

70

85

30

85

IN

OUT

IN

BI

IN BI

SBI

INB+

VCC

OUTA1+ OUTA1-

OUTA0+ OUTA0-

SAO

OUTB1+ OUTB1-

OUTB0-

OUTB0+

SBO

ENA

INA-

INA+

SAI

INB-

GND

THRM

ENB

PAD

OUT BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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D

8 7 6 5 4 3

C

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A

NOTICE OF PROPRIETARY PROPERTY:

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12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Dual-Port Host DDC Crossbar

71

30

26

30

201

MF

1/20W

1%

R3401

2.2K

201

1%

2.2K

1/20W MF

R3402

201

R3403

2.2K

1%

1/20W

MF

201

R3404

MF

1/20W

2.2K

1%

71

C3400

0.1UF

20%

402

10V CERM

QFN

U3400

TS3DS10224

CRITICAL

29

SYNC_MASTER=J16_MAX

SYNC_DATE=02/11/2013

TBT DDC Crossbar

DP_TBTPA_DDC_CLK

TBT_DDC_XBAR_EN_L

=PP3V3_S0_DP

DP_TBTPB_DDC_DATA

DP_TBTPA_DDC_DATA

DP_TBTSNK1_DDC_CLK DP_TBTSNK1_DDC_DATA

DP_TBTSNK0_DDC_DATA

DP_TBTSNK0_DDC_CLK

DP_TBTPB_DDC_CLK

051-0164

12.4.0

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1

2

1

2

1

2

1

2

1

12

3

13

20 19

18 17

15

6 7

9

8

11

16

2

1

14

4

5

21

10

40 47 70

IN

OUT

IN

OUT OUT

IN IN

IN

BI

OUT

IN

VDD

GND

DM

DP

OE*

S

DP_1

DM_1

DM_2

DP_2

BI

IN

VINONVOUT

GND

D

S

G

N-CHN

G

D

S

P-CHN

D

GS

D

GS

OUT

EN

MR*

GND

THRM

IN

VDD

SENSE

RESET*

+

-

PAD

(OD)

DLY

VREF

NC

GND

VOUT

ON

VIN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Wake from BT in G3H circuit

2 A (EDP)

BT_RESET_MASK_L GATES BT_PWR_RST_L until after S0 GPIO is guranteed stable

Supervisor & CLKREQ# Isolation

N-TYPE

AP & BT Load Switch

TPS22924B

18.4 MOHM @3.3V

SWITCH

CHANNEL

LOADING

RDS(ON)

BLUETOOTH

514S0335

AIRPORT

Delay = 130 ms +/- 20%

20

32 45

11 18

20% 402

CERM

10V

C3530

0.1uF

232K

402

1% 1/16W MF-LF

R3531

100K

1/16W

1%

402

MF-LF

R3532

100K

402

1% 1/16W MF-LF

R3530

32 45

10UF

20%

C3508

603

6.3V X5R

X7R-CERM

16V

0402

C3507

0.1UF

10%

13 77

CRITICAL

SSD-K99

F-RT-SM1

J3500

11 77

PLACE_NEAR=J3500.4:7mm

C3505

6.3VCERM-X5R0201

0.1UF

10%

PLACE_NEAR=J3500.5:7mm

C3506

6.3VCERM-X5R

0201

0.1UF

10%

13 77

44 45

0402

X7R-CERM

16V

C3502

0.1UF

10%

0402

X7R-CERM

16V

C3503

0.1UF

10% 20%

10UF

603

C3504

6.3V X5R

402

1/16W

5%

10K

MF-LF

R3570

44 45

R3501

15K

1%

1/20W

MF

201

12 44 68

402

CERM

10V

20%

0.1UF

C3500

U3501

USB3740

DFN

SIGNAL_MODEL=SWI_USB3740_DFN_USB3740_MOJO

CRITICAL

13 80

12

10K

402

MF-LF

1/16W

5%

R3542

MF-LF

1/16W

5%

10K

402

R3543

CRITICAL

TPS22924B

U3540

CSP

DMC2400UV

SOT563

Q3540

CRITICAL

SOT563

Q3540

DMC2400UV

FERR-220-OHM-2.5A

CRITICAL

0603

L3502

CRITICAL

FERR-220-OHM-2.5A

L3501

0603

CRITICAL

VESM

SSM3K15AMFVAPE

Q3570

SSM3K15AMFVAPE

VESM

Q3501

CRITICAL

TDFN

SLG4AP041V

CRITICAL

U3530

CRITICAL

CSP

TPS22924

U3510

402

C3541

20% 16V

CERM

0.01UF

SYNC_MASTER=J16_FIYIN

SYNC_DATE=01/11/2013

AIRPORT/BT

PCIE_AP_R2D_N PCIE_AP_R2D_P

AP_EVENT_L

PCIE_AP_R2D_C_P

AP_CLKREQ_Q_L

BT_PWR_EN

AP_RESET_CONN_L

P3V3AP_VMON

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

PP3V3_S4_AP_FLT

VOLTAGE=3.3V

PP3V3_G3H_BT_FET

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.5MM

PP3V3_G3H_BT_FLT

MIN_LINE_WIDTH=0.5MM

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2MM

AP_CLKREQ_L

AP_PWR_EN

AP_RESET_L

=PP3V3_S4_AP

PP3V3_S4_AP_FLT

PCIE_WAKE_L

PP3V3_S4_AP_FLT

PCIE_CLK100M_AP_P

USB_BT_P

USB_BT_N

USB_BT_MUX_P

PCIE_AP_D2R_P

PCIE_AP_R2D_C_N

AP_WAKE_L AP_RESET_CONN_L

USB_BT_MUX_N

PCIE_CLK100M_AP_N

USB_BT_MUX_P

PCIE_AP_D2R_N

AP_WAKE_L

AP_CLKREQ_Q_L

BT_RESET_MASK_L

SMC_G3_WAKESRC_EN

=PP3V3_G3H_BT

PM_SLP_S5_L

AP_PWR_EN

MIN_LINE_WIDTH=0.6 mm VOLTAGE=3.3V

PP3V3_S4_AP_FET

MIN_NECK_WIDTH=0.2 mm

=PP3V3_S4_AP

SMC_PME_S4_WAKE_L

USB_BT_WAKEN

USB_BT_MUX_N

=PP3V3_G3H_BT

BT_PWR_RST_L

BT_PWR_RST

051-0164

12.4.0

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2

1

2

1

2

1

2

1

2

1

18

21

19 20

10 11 12

13

16

15

14

17

9

1 2 3 4 5 6 7 8

1 2

2

1

2

1

2

1

2

1

2

1

58

9

10

3

4

2

1

7

6

1

2

1

2

A2 B2

C2

B1

A1

C1

1

2

6

3 4

5

21

1

2

3

1

2

3

8

6

3

5

9

7

1

2

4

C1

A1 B1

C2

B2

A2

2

1

77

32

32 45 70

32

12 36

32

32 80

32

32 80

32

20

44 45

32 70

45

32 45 70

32 80

32 70

OUT

IN

OUT

IN IN

OUT

IN

OUT

NCNC NCNC

IN

NC

NC NC

NC

A A A A

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

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8 7 6 5 4 3

C

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NOTICE OF PROPRIETARY PROPERTY:

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12

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A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

518S0893

PCIE TX2

SATA_PCIE_SEL DEVSLP

Polarity Reversed

PCIEx2 SSD requires AC coupling caps on TX side

Polarity Reversed

POR:514S0457 (tall)

PCIE RX2

PCIE TX3

PP3V3_AUX

PCIE RX3

PFW_L

SATA=H,PCIE=L

MFG_RSVD

HDD SIGNAL CONNECTOR

SATA Activity LED

DC R =0.01-ohm

PCIE RX1

PCIE RX0

GS3 SSD

(POLARITY REVERSED)

PCIE TX0

PCIE TX1

0603

FERR-26-OHM-6A

L3700

CRITICAL

SSD:Y

PLACE_NEAR=J3700.1:10MM

402

20% 10V

SSD:Y

0.1UF

C3701

CERM

C3700

SSD:Y

0.1UF

402

CERM

10V

20%

45 81

C3721

0.01UF

402

X7R10% 25V

GND_VOID=TRUE

C3722

0.01UF

GND_VOID=TRUE

10% 25V X7R

402

C3723

402

X7R

0.01UF

25V10%

GND_VOID=TRUE

C3724

10% 25V X7R

0.01UF

GND_VOID=TRUE

402

11 78

11 77

11 78

R3717

SSD:Y

5%

1/16W

MF-LF

402

0

20

11

11 78

C3710

0.1UF

10%

0201

16V

X5R-CERM

GND_VOID=TRUE

SSD:Y

PLACE_NEAR=J3700.19:5MM

C3711

X5R-CERM

0.1UF

16V

0201

10%

SSD:Y

PLACE_NEAR=J3700.18:5MM

GND_VOID=TRUE

C3713

0.1UF

SSD:Y

10%

0201

16V

GND_VOID=TRUE

X5R-CERM

PLACE_NEAR=J3700.21:5MM

C3712

0.1UF

0201X5R-CERM

16V10%

GND_VOID=TRUE

SSD:Y

PLACE_NEAR=J3700.22:5MM

11 78

R3712

MF-LF

1/16W

5%

100K

402

R3713

MF-LF

1/16W

5%

100K

402

J3700

SSD-J90

F-RT-SM

CRITICAL

SILK_PART=SSD

SSD:Y

GND_VOID=TRUE GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE GND_VOID=TRUE

GND_VOID=TRUE

BP01

TP-BP-P19XP55SMP14X45O

BP02

TP-BP-P19XP55SMP14X45O

BP03

TP-BP-P19XP55SMP14X45O

BP04

TP-BP-P19XP55SMP14X45O

M-ST-SM

GND_VOID=TRUE

CRITICAL

SILK_PART=HDD

J3720

PSA127-0747-A01-1H

DEVELOPMENT

330

1/10W MF-LF

603

5%

R3799

2.0X1.25MM-SM

GREEN-3.6MCD

DEVELOPMENT

SILK_PART=SATA ACTIVE

DS3799

SYNC_DATE=01/07/2013

SYNC_MASTER=J16_JERRY

SATA/SSD Connectors

SSD_D2R_P<1> SSD_D2R_N<1>

SSD_D2R_N<0>

SSD_R2D_N<1>

SSD_R2D_P<1>

SSD_R2D_N<0>

=PP3V3_S0_LED_SATA

PP3V3_S0_SSD_FLT

SSD_R2D_P<0>

=PP3V3_S0_SSD

SATA_HDD_R2D_C_N

SATA_HDD_D2R_P

SATA_HDD_R2D_C_P

SSD_CLKREQ_L

SSD_R2D_C_P<0>

SSD_R2D_C_N<0>

PCIE_CLK100M_SSD_N PCIE_CLK100M_SSD_P

SMC_OOB2_D2R_L

SMC_OOB2_R2D_L

SSD_EN

SSD_RESET_L

PCH_SATALED_L

SATALED_R_L

=PP3V3_S0_LED_SATA

SSD_D2R_P<0>

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.4mm

MIN_LINE_WIDTH=0.6mm

PP3V3_S0_SSD_FLT

SSD_R2D_C_N<1>

SSD_R2D_C_P<1>

SATA_HDD_D2R_N

SATA_HDD_D2R_C_P

SATA_HDD_R2D_N

SATA_HDD_D2R_C_N

SATA_HDD_R2D_P

051-0164

12.4.0

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2 1

2

1

2

1

1 2

121

2

20

2

1

4

3

5 6

8

14

13

16

47

53

46 11 12

10

9

48

49

50

52

51

7

35

34

29

30

31

32

33

36

38

37

39

40

41

42

43

45

44

15

17

19

18

21 22 23 24 25

54

28

27

26

63

64 65 66 67 68

55 56 57 58 59

61 62

60

1

8

2

4 5

9

7

3

6

1

2

K

A

33 70

33

70

78

11

33 70

33

78

OUT

VCC+

GND

IN

G

DS

D

SG

D

SG

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

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NOTICE OF PROPRIETARY PROPERTY:

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SHEET

R

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DRAWING NUMBER

REVISION

BRANCH

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THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Drive active: Valid signal protocol Drive asleep: HDD drives HDD_OOB_TEMP low Drive disconnected: Pulled high

0.0V to 0.3V

1.2V to 2.0V

Low:

High:

Notes:

HDD Out-of-Band Temperature Sensing

HDD POWER/OOB CONNECTOR

Trip is 1.0V

518S0864

Node is at 1.5V

From drive:

safety isolation

C3830

603

10UF

20%

6.3V X5R

C3807

16V X7R-CERM 0402

0.1UF

10%

44 81

R3805

1K

5% 1/16W MF-LF 402

U3800

CRITICAL

LMV331

SC70-5

C3806

16V X7R-CERM 0402

0.1UF

10%

R3800

MF-LF

49.9K

402

1/16W

1%

R3801

MF-LF

1% 1/16W

402

100K

R3803

402

MF-LF

1/16W

5%

3.3K

R3802

100K

5%

402

1/16W MF-LF

L3830

FERR-220-OHM

0402

44 81

R3808

523

1/16W

1%

MF-LF

402

R3814

MF-LF

5% 1/16W

402

10K

J3830

CRITICAL

M-ST-SM

78047-0483

Q3801

SSD:Y

CRITICAL

NTR1P02L

SOT23-3-HF

Q3800

SSM6N15AFE

SOT563

SSD:Y

CRITICAL

Q3800

SSM6N15AFE

SOT563

CRITICAL

SSD:Y

R3816

SSD:Y

10K

402

MF-LF

1/16W

5%

R3815

5% 1/16W MF-LF 402

0

SSD:N

HDD Connector

SYNC_MASTER=J16_JERRY

SYNC_DATE=01/07/2013

SMC_OOB1_R2D_L

P3V3_S0_OOB

MIN_LINE_WIDTH=0.3mm MIN_NECK_WIDTH=0.15mm VOLTAGE=3.3V

=PP3V3_S0_SENSE

HDD_OOB1_D2R_L

HDD_OOB1_D2R_F_L

SMC_OOB1_R2D_R_L

SATA_PWR_L

=PP3V3_S0_SENSE

SMC_OOB1_D2R_L

=PP3V3_S0_SENSE

=PP3V3_S0_SENSE=PP1V5_S0_SENSE

=PP5V_S0_SATA

HDD_OOB_1V00_REF

=PP5V_S0_SATA

HDD_OOB1_D2R_R_L

051-0164

12.4.0

38 OF 123

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2

1

2

1

2

5

4

2

3

1

2

1

2

1

2

1 2

1

2

21

1 2

1

2

1 2 3 4

32

1

6

1

2

3

4

5

1

2

1

2

34 48 49 50 70

81

34 48 49 50 70

34 48 49 50 70 70

34 70

81

IN

OUT

IN

OUT

IN

BI

BI BI

BI BI BI BI BI

BI

BI BI

OUT

IN

OUT

IN

OUT

IN

OUT

BI

BI BI

IN

BI

BI BI

NC

RESET*

CS*

SCK

SO

WP*

SI

GND

VCC

IN

NC

WAKE*

CR_DATA4 CR_DATA5

CR_LED*/CR_BUS_PWR

MS_INS*

CR_DATA7

CR_DATA6

CR_DATA0

CR_WP*

CR_CLK

TRD3_N

TRD3_P

GPIO_0/CR_ACT_LED*

GPIO_1/LR_OUT

GPIO_2/MEDIA_SENSE

SD_DETECT

CR_CMD

PCIE_TXD_P

PCIE_RXD_P

CR_DATA3

CR_DATA2

CR_DATA1

SR_DISABLE

SCLK_SPD1000LED*

SO_LINKLED* CS*/EECLK

LOW_PWR

SI/EEDATA

BIASVDDH

XTALVDDH

VDDO

SMB_DATA

PERST*

SMB_CLK

PCIE_TXD_N

PCIE_REFCLK_N

AVDDH

VDDC

SR_LX

SR_VFB

SR_VDDP

SR_VDD

SPD100LED*/SERIAL_DO TRAFFICLED*/SERIAL_DI

TRD0_P

TRD1_P

TRD0_N

TRD1_N

TRD2_N

VMAIN_PRSNT

PCIE_RXD_N

PCIE_REFCLK_P

CLKREQ*

THRM_PAD

XTALI XTALO

RDAC

AVDDL

PCIE_PLLVDDL

GPHY_PLLVDDL

TRD2_P

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

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C

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NOTICE OF PROPRIETARY PROPERTY:

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A

C

PAGE TITLE

SHEET

R

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DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

used, this pin should have a 1K pull-down to GND

NOTE: "IPx" == Programmable pull-up/down

SD_DETECT can only be used active low due to errata.

ENET 1.2V SR IS ENABLED IF FLOATING.

If ENET switching regulator is

ENET_SR_DISABLE

BCM requests SD CR[0:7], CMD, CLK termination.

(IPU-ENET)

ENET_CR Signals

(IPD-ENET)

Control signal to light LED or control SD bus power.

No MS (Memory Stick) Insert feature needed.

(IPx-ENET)

VDD for Card Reader I/O

If enabled: VDD/VDDP connect to =PP3V3_S3_ENET_PHY (add bypassing), LX connects to inductor.

Special Star routing needed on these pins. Decoupling on Pg 37.

(OD)

NOTE: ENETM requires SI pull-down instead of SO.

ROM contains MAC address, PCIe config

BCM57765 ENET SR pins are internal 1.2V switching regulator. See note for SR_DISABLE below.

281mA (1000base-T max power, Caesar IV)

N-channel FET isolation suggested. If PHY is always powered then alias

is powered-down in S3/S5. Standard

Must isolate from PCIe WAKE# if PHY

(NO IPU OR IPD-ENET)

(IPU-ENET)

(Required ROM size 1 Mbit)

Current

Resistor

ROM is used then the straps must change.

o

ENET supports both active-levels for WP.

(OD)

Atmel AT45DB011D (1Mbit) ROM. If a different

(IPU)

396mA (1000base-T, Caesar II)

(See note)

WAKE#

(See note)

(OD)

Limiting

=ENET_WAKE_L to PCIE_WAKE_L.

(IPU-ENET)

other 3 SPI pins configures ENET for the

NOTE: Pull-down on SO plus internal pull-ups on

info as well as code for Bonjour proxy. Avoids need for EFI to program at startup.

(IPU-ENET)

(IPD-ENETM)

Internal 1.2V Switching Regulator pins.

Connect only to U3900 pin 20.

LR_OUT/GPIO1 is used as a 3.3V/1.8V internal LDO out for the card reader on-chip I/O.

(IPU-ENET)

(OD)

(IPD)

PHY Non-Volatile Memory

If disabled: Okay to float VDD, VDDP & LX pin. VFB must always connect to =PP1V2_S3_ENET_PHY.

(IPD)

20% X5R

6.3V 603

10UF

C3935

402

X5R-CERM1

4.7UF

C3925

6.3V

20%

FERR-600-OHM-0.5A

CRITICAL

SM

L3925

6.3V

4.7UF

20%

402

X5R-CERM1

C3920

402

1K

MF-LF

5% 1/16W

R3942

11 77

11 18

36

20 37

MF-LF 402

1% 1/16W

1.24K

R3965

13 77

36 80

402

4.7K

MF-LF

1/16W

5%

R3941

MF-LF

402

5%

1/16W

4.7K

R3940

37 80

NOSTUFF

4.7K

MF-LF 402

5% 1/16W

R3990

37 80

37

11 80

4.7K

MF-LF

402

5%

1/16W

R3910

36

35 80

37

35 80

37 80

5%

1K

MF-LF

402

1/16W

R3981

OMIT_TABLE

AT45DB011D

SOIC-8S1

U3990

37

19 79

201

33

1/20W

PLACEMENT_NOTE=PLACE R3961 NEAR U3900

5% MF

R3961

10%

0.1UF

X5R-CERM

0201

16V

C3905

10%

0.1UF

X5R-CERM

16V 0201

C3910

10%

0.1UF

0201

16V X5R-CERM

C3911

10%

0.1UF

16V X5R-CERM 0201

C3916

10%

0.1UF

16V

0201

X5R-CERM

C3921

10%

0.1UF

16V

X5R-CERM

0201

C3926

10%

0.1UF

0201

16V

X5R-CERM

C3931

X5R-CERM

10%

0.1UF

0201

16V

C3936

10%

0.1UF

X5R-CERM

0201

16V

C3950

10%

0.1UF

0201

16V

X5R-CERM

C3951

10%

0.1UF

X5R-CERM

0201

16V

C3955

10%

0.1UF

X5R-CERM

16V

0201

C3956

10%

0.1UF

X5R-CERM 0201

16V

C3990

201

33

PLACEMENT_NOTE=PLACE R3979 NEAR U3900

MF5%

1/20W

R3979

201

PLACEMENT_NOTE=PLACE R3971 NEAR U3900

33

MF5%

1/20W

R3971

201

1/20W

PLACEMENT_NOTE=PLACE R3972 NEAR U3900

33

5% MF

R3972

2015%

PLACEMENT_NOTE=PLACE R3973 NEAR U3900

33

MF

1/20W

R3973 R3974

201

PLACEMENT_NOTE=PLACE R3974 NEAR U3900

33

MF5%

1/20W

201

PLACEMENT_NOTE=PLACE R3975 NEAR U3900

33

MF5%

1/20W

R3975 R3976

201

PLACEMENT_NOTE=PLACE R3976 NEAR U3900

33

MF5%

1/20W

R3977

201

PLACEMENT_NOTE=PLACE R3977 NEAR U3900

33

MF5%

1/20W

33

201

PLACEMENT_NOTE=PLACE R3978 NEAR U3900

MF

1/20W

5%

R3978

FERR-600-OHM-300MA-0.85OHM

CRITICAL

0402

L3900

0402

FERR-600-OHM-300MA-0.85OHM

CRITICAL

L3905

FERR-600-OHM-300MA-0.85OHM

CRITICAL

0402

L3910

FERR-600-OHM-300MA-0.85OHM

CRITICAL

0402

L3920

0402

CRITICAL

FERR-600-OHM-300MA-0.85OHM

L3930

BCM57766C0KMLG

U3900

OMIT_TABLE

QFN-8X8

10%

0.1UF

X5R-CERM

0201

16V

C3900

4.7UF

6.3V X5R-CERM1

20% 402

C3930

6.3V

X5R-CERM1

402

20%

4.7UF

C3915

1/16W

5%

402

MF-LF

4.7K

R3997

SYNC_MASTER=J16_MAX

SYNC_DATE=02/11/2013

ETHERNET PHY (CAESAR IV)

PCIE_CLK100M_ENET_N

ENET_CLKREQ_L

SYSCLK_CLK25M_ENET

ENET_RDAC

ENET_TRAFFICLED_L

ENET_CS_L

ENET_MOSI

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.15 mm

PP3V3R1V8_ENET_LR_OUT

ENET_MEDIA_SENSE

SMB_ENET_SDA

=ENET_WAKE_L

SMB_ENET_SCL

ENET_SCLK

PCIE_CLK100M_ENET_P

MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 mm MIN_LINE_WIDTH=0.4 mm

VOLTAGE=3.3V

ENET_XTALVDDH

MIN_NECK_WIDTH=0.2 mm

ENET_SR_LX

PP1V2_ENET_PHY_AVDDL

MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.2V

MIN_LINE_WIDTH=0.4 mm

ENET_VMAIN_PRSNT

ENET_MISO

ENET_RESET_L

PCIE_ENET_R2D_N

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm

PP3V3_ENET_PHY_AVDDH

PP3V3_ENET_PHY_BIASVDDH

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm

=ENET_SR_VFB

ENETCONN_MDI_P<2>

VOLTAGE=1.2V

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm

PP1V2_ENET_PHY_PCIEPLL

ENETCONN_MDI_N<1>

SDCONN_CLK

SDCONN_DATA<2>

SDCONN_DATA<7>

SDCONN_DATA<3>

PCIE_ENET_D2R_N

ENET_MOSIENET_SCLK

ENET_CS_L

PCIE_ENET_R2D_C_N

SDCONN_CMD

SDCONN_DATA<0> SDCONN_DATA<1>

SDCONN_DATA<4> SDCONN_DATA<5> SDCONN_DATA<6>

=PP3V3_ENET_PHY

=PP3V3_S0_ENET

PCIE_ENET_R2D_C_P

ENET_LOW_PWR

ENET_SR_DISABLE

ENET_CR_DATA<2>

ENET_CR_PWREN

PCIE_ENET_D2R_P

PCIE_ENET_R2D_P

=PP3V3_ENET_PHY

=PP3V3R1V8_CR_VDDIO

PCIE_ENET_D2R_C_P

ENET_MISO

PCIE_ENET_D2R_C_N

ENET_CR_DATA<7>

ENET_CR_DATA<6>

ENET_CR_DATA<4>

ENET_CR_DATA<3>

ENET_CR_DATA<1>

ENETCONN_MDI_N<3>

ENETCONN_MDI_N<2>

=PP1V2_ENET_PHY

MIN_LINE_WIDTH=0.4 mm

PP1V2_ENET_PHY_GPHYPLL

VOLTAGE=1.2V

MIN_NECK_WIDTH=0.15 mm

ENET_CR_DATA<0>

ENET_SD_CLK

ENET_SD_CMD

ENET_SD_DETECT_L

ENETCONN_MDI_P<3>

ENETCONN_MDI_P<1>

ENETCONN_MDI_N<0>

ENETCONN_MDI_P<0>

ENET_CR_DATA<5>

SDCONN_WP

39 OF 123

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12.4.0

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2

8

5

1

1 2

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

1 2

2

1

1 2

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

21

3

52 53

60

59

55

54

25

57

21

49

50

5 8 9

1

26

28

33

22

23

24

68

66

65 63

4

64

20

37177

10

11

6

27

30

48

42

35

161315

14

2

67

40

44

41

43

47

58

34

31

12

69

18 19

38

56

395129

326136

45

62

46

2

1

2

1

2

1

2

80

36

77

36

35 36 70

70

80

77

35 36 70

36

77

80

36

80

BI BI BI BI

BI

G

DS

IN

G

D

S

G

D

S

IN

BI

D

GS

ENET_MDI_TRAN2+

ENET_MDI_TRAN1+

ENET_MDI_TRAN3-

SHIELD

ENET_MDI_TRAN0-

ENET_MDI_TRAN0+

ENET_MDI_TRAN2-

ENET_MDI_TRAN1-

ENET_MDI_TRAN3+

ENET_MDI

PINS

TX

RX

TX

RX

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

CAESAR IV 1.2V INT.VR CMPTS

SILKSCREEN:ENET ACT

514-0822

3.3V ENET FET

Power decoupling

CAESAR IV ACTIVITY LED

ENET Enable Generation

157S0058

CAESAR IV WAKE# ISOLATION

Feedback loop

"ENET" = "S0" || ("S4" && "WOL_EN")

36 80

10%

0.01UF

50V

X7R-CERM

0402

C4021

CRITICAL

NTR4101P

SOT-23-HF

Q4020

10% X5R

402

16V

0.033UF

C4020

402

MF-LF

5%

1/16W

100K

R4021

MF-LF

402

1/16W

10K

5%

R4020

14

CRITICAL

2N7002DW-X-G

SOT-363

Q4021

CRITICAL

2N7002DW-X-G

SOT-363

Q4021

12 21 44 45 68 69

10%

0.1UF

0402

X7R-CERM

16V

C4011

6.3V X5R-CERM1 402

20%

4.7UF

C4010

1/16W MF-LF 402

5%

10K

R4070

DEVELOPMENT

402

MF-LF

1/16W

5%

330

R4050

2.0X1.25MM-SM

GREEN-3.6MCD

DEVELOPMENT

LED4050

4.7UH-0.8A

CRITICAL

PCAA031B-SM

L4010

X5R

6.3V

20%

10UF

603

C4012

10%

0.1UF

0402

X7R-CERM

16V

C4013

36 80

MF-LF 402

1/16W

5%

75

R4003

36 80

75

1/16W MF-LF 402

5%

R4002

MF-LF

75

5% 1/16W

402

R4001

75

5% MF-LF

1/16W 402

R4000

10%

1206

NOSTUFF

2KV

1000PF

CERM

C4000

35 80

0.1UF

10V

20%

402

CERM

C4004

0.1UF

10V CERM

20%

402

C4003

35 80

0.1UF

CERM

10V

20%

402

C4002

0.1UF

CERM

10V

20%

402

C4001

VESM

SSM3K15AMFVAPE

Q4070

K70-K72

F-ANG-TH

CRITICAL

J4000

10%

0.1UF

16V 0201

X5R-CERM

C4032

10%

0.1UF

X5R-CERM

16V 0201

C4031

6.3V 402

X5R-CERM1

20%

4.7UF

C4030

CRITICAL

LFE8904CF

SM

T4000

LFE8904CF

CRITICAL

SM

T4010

Ethernet Support & Connector

SYNC_DATE=02/11/2013

SYNC_MASTER=J16_MAX

MAKE_BASE=TRUE

PP1V2_ENET_INTREG

VOLTAGE=1.2V

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

PM_EN_ENET_L

=PP1V2_ENET_PHY

ENETCONN_MCT3

ENETCONN_MDI_T_N<3>

ENETCONN_MDI_T_N<1>

ENETCONN_MDI_N<1>

ENETCONN_MDI_T_P<0>

ENETCONN_MCT2

ENETCONN_MDI_P<0>

ENETCONN_MDI_N<0>

ENETCONN_MDI_T_P<0>

ENETCONN_MDI_T_N<0>

ENETCONN_MCT0

ENETCONN_MDI_T_P<2>

ENETCONN_MDI_T_N<2>

ENETCONN_TCT

ENETCONN_MDI_P<2>

ENETCONN_MDI_N<2>

ENETCONN_MCT1

ENETCONN_MDI_N<3>

ENETCONN_MDI_P<3>

ENETCONN_MDI_T_N<3>

ENETCONN_MDI_T_P<3>

ENETCONN_MDI_T_P<1>

ENETCONN_MDI_P<1>

WOL_EN

ENET_ACT

ENET_WAKE_L

MAKE_BASE=TRUE

=PP3V3_ENET_PHY

ENET_TRAFFICLED_L

ENETCONN_MDI_T_P<3>

=PP3V3_ENET_PHY

PCIE_WAKE_L

=ENET_WAKE_L

=PP3V3_ENET_PHY

P3V3ENET_SS

ENETCONN_MDI_T_N<1>

ENETCONN_MDI_T_N<0>

ENETCONN_MDI_T_P<1>

ENETCONN_MDI_T_P<2>

MIN_LINE_WIDTH=0.4 MM

ENETCONN_MCT_BS

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6MM

DIDT=TRUE

VOLTAGE=1.2V

ENET_SR_LX

MIN_NECK_WIDTH=0.2MM SWITCH_NODE=TRUE

=PP3V3_S4_FET_ENET

ENETCONN_MDI_T_N<2>

PM_SLP_S3_L

PP1V2_ENET_INTREG

=ENET_SR_VFB

PP3V3_ENET_FET

=PP3V3R1V8_CR_VDDIO

VOLTAGE=3.3V MIN_NECK_WIDTH=0.15 mm

MIN_LINE_WIDTH=0.3 mm

PP3V3R1V8_ENET_LR_OUT

MAKE_BASE=TRUE

051-0164

12.4.0

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2

K

A

21

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

3

4 3

8

9

2 1

10 11 12 13 14

5

6

7

2

1

2

1

2

1

10

6

5

7

8

9

11

12

4

3

2

1

10

6

5

7

8

9

11

12

4

3

2

1

36

35

80

35 36 70

35

35 36 70

12 32 35

35 36 70

80

35

70

36

35

70

35 35

OUT

IN

OUT

IN

LOW_PWR

GND

THRM

VDD

RST_OUT*

DET_OUT

DET_CHNGD*

DET_LVL

DET_IN

RST_IN*

DET_CH_EN*

DLY

RST

LOGIC

XOR

(IPU)

XOR

(OD)

PAD

BI BI BI

BI

BI BI BI BI

THRML

OUT

GND

FAULT*

ILIM

EN

IN

PAD

IN

SHLD_PIN

CRD_DETECT_SWITCH

SHLD_PIN

DAT6

DAT5

DAT7

DAT2

DAT1

DAT0

DAT4

VSS

CMD

CLK

VDD

VSS

CD/DAT3

WRITE_PROTECT_SWITCH

SHLD_PIN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

FROM SD CONN ->

When ENET_LOW_PWR deasserts, RST_OUT# deasserts for >80ms, then asserts for 10ms regradless of RST_IN# state. Otherwise RST_OUT# follows RST_IN#

DLY block is 20ms nominal

SD switch is normally connected (i.e. gnd)

-> TO ENET CHIP

-> TO PCH GPIO

353S2548

SD CARD CONNECTOR

J16:516-0249 / J17:512-0038

SDCONN DETECT DEBOUNCE. ENET_RESET AND DETECT-CHANGED PCH GPIO PULSE GENERATION.

SD CARD 3.3V OVERCURRENT PROTECTION CHIP

35 80

35

35 80

X5R

6.3V

10UF

603

20%

C4102

10%

0.1UF

16V X7R-CERM 0402

C4103

5% MF-LF

1/16W 402

47K

R4100

20%

C4100

22UF

6.3V

X5R-CERM1

0603

10% 16V

0402

X7R-CERM

0.1UF

C4101

35

5%

0

MF-LF

402

1/16W

R4114

13 18

35 80

10% X5R

10V

402-1

1UF

C4110

20 35

NOSTUFF

5%

10K

402

MF-LF

1/16W

R4110

20

50V CERM

5%

NOSTUFF

0402

22PF

C4171

NOSTUFF

CERM

15PF

5% 50V

402

C4170

TDFN

SLG4AP026V

CRITICAL

U4111

402

5%

10K

MF-LF

1/16W

R4115

35 80

SON

TPS2553

CRITICAL

U4100

35

F-ANG-TH

SD-CARD-D7

J4100

MF-LF

1%

13K

402

1/16W

R4118

402

1% 1/16W

R4119

MF-LF

13K

47NH-1.3OHM

CRITICAL

0402

L4102

SYNC_MASTER=J16_MAX

SD READER CONNECTOR

SYNC_DATE=02/11/2013

SDCONN_OC_L

MIN_LINE_WIDTH=0.4 mm VOLTAGE=3.3V

MAKE_BASE=TRUE

PP3V3_S0_SW_SD_PWR

MIN_NECK_WIDTH=0.2 mm

SDCONN_ILIM

=PP3V3_S0_SDCARD

=PP3V3_S0_SW_SD_PWR

SDCONN_CLK_R

SDCONN_DATA<1> SDCONN_DATA<2>

ENET_CR_PWREN

=PP3V3_S0_SW_SD_PWR

ENET_SD_DETECT_L

SDCONN_STATE_CHANGE

ENET_LOW_PWR

SLG_ENET_RESET_R_L

=PP3V3_S4_SDCARD

SDCONN_ILIM_R

SDCONN_DATA<7>

ENET_RESET_L

SDCONN_DATA<0>

SDCONN_CLK

SDCONN_DATA<6>

SDCONN_DATA<3> SDCONN_CMD

SDCONN_DATA<4> SDCONN_DATA<5>

SDCONN_DETECT_L SDCONN_WP

SD_DETECT_LVL

SDCONN_DETECT_L

ENET_SD_RESET_L

051-0164

12.4.0

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7

3

6

1

2

7

1

5

3

2

4

6

27

26

25

24

22

21

20

23

14

19

18

17

12

11

13

9

8

7

10

6

2

5

4

3

1

15

16

1

2

1

2

21

12

70

37

80

37

70

37

OVDD2

OVDD1

USB_VDDA0

MAVSS

DVSS6

DVSS4

USB_VSSA0

GPIO0 GPIO1 GPIO3 GPIO9

MRXDATAINP

MRXCLKINP MRXCLKINN

CLKIN

MRXDATAINN

SF_DOUT

SF_DIN

CS_PWDB

SF_CLK

MIPI_RESISTOR

USB_VSDL0

OVSS2

CS_SCK

USB_PADM

USB_PADP

LED_FIXED

CS_SDA

SF_CS*

VSSA_PLL

DVDD4

DVDD6

VDDA_PLL

CS_CLK

CS_RSTB

TEST

USB_VRES

RST*

UART1_RX UART1_TX

THRM

SF_WP*

OVSS1

DVSS3

USB_VDDL0

CLKOUT

NC

MAVDD33

DVDD3

PAD

NC

HOLD*

SCLK

WP*

CS*

VCC

THRM

GND

SO/SIO1

SI/SIO0

PAD

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

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NOTICE OF PROPRIETARY PROPERTY:

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12

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PAGE TITLE

SHEET

R

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SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

GPIO3 CAN BE CONFIGED AS

337S4151

Use 100 ohms and 150pF for 10MHz filter

STITCH THERMAL PAD TO INNER GROUND

UART1_TX is strap for selection

GENERAL GPIO AFTER POWER ON

’1’= EXT FW ’0’= INT FW

335S0852

SERIAL FLASH

’0’ = NEGATIVE EDGE

of pos/neg edge sampling of SPI clock during power-on. ’1’ = POSITIVE EDGE

GPIO3, EXT/IN FIRMWARE BOOT SEL

USB CAMERA CONTROLLER

CRYSTAL

Camera/ALS/DMIC connector

APN:518S0879

10%

0.1UF

6.3V

C4218

CERM-X5R 0201

6.3V

1.0UF

20%

C4216

X5R 0201-1

X5R

6.3V 0201-1

1.0UF

20%

C4221

201

1%

24K

1/20W MF

PLACE_NEAR=U4200:5mm

R4204

201

1% MF

1/20W

47

R4216

201

8.2K

MF

1% 1/20W

PLACE_NEAR=U4200:5mm

R4213

X5R

6.3V 0201-1

20%

1.0UF

C4222

SHORT-0201

XW4202

SHORT-0201

XW4203

10%

0.1UF

6.3V

C4223

CERM-X5R 0201

10%

0.1UF

6.3V

PLACE_NEAR=U4200:5mm

C4226

CERM-X5R 0201

10%

0.1UF

6.3V

C4219

CERM-X5R 0201

10%

0.1UF

6.3V

C4215

CERM-X5R 0201

10%

0.1UF

6.3V

C4224

CERM-X5R 0201

10%

0.1UF

6.3V

C4217

CERM-X5R 0201

10%

0.1UF

6.3V

C4214

CERM-X5R 0201

10%

0.1UF

6.3V

C4213

CERM-X5R 0201

FQFN

CRITICAL

U4200

VC0359

201

1%

1K

1/20W MF

R4218

201

MF

1% 1/20W

1K

R4219

0402

FERR-1000-OHM

L4200

0

R4260

0

R4264

201

MF

1%

1M

1/20W

R4214

18PF

0201

NP0-C0G-CERM

C4227

25V

5%

201

MF

1%

47

1/20W

R4215

18PF

NP0-C0G-CERM

0201

C4225

25V

5%

10%

0.1UF

6.3V

C4228

CERM-X5R 0201

201 1/20W

10K

MF 1%

R4211

201

10K

MF

1/20W

1%

R4210

0402

FERR-600-OHM-300MA-0.85OHM

L4220

10%

0.1UF

6.3V

C4220

CERM-X5R 0201

0402

L4210

FERR-1000-OHM

201

1/20W

MF

10

R4220

5%

10% X5R

1UF

16V

C4262

402

FERR-1000-OHM

0402

L4202

10% X5R

1UF

16V

C4264

402

0402

FERR-1000-OHM

L4204

0402

FERR-1000-OHM

L4206

10% X5R

1UF

16V

C4266

402

1/20W

0201

MF

0

R4267

5%

150PF

NOSTUFF

50V CERM

C4267

402

5%

0

0201

MF

1/20W

R4268

5%

150PF

NOSTUFF

50V CERM

C4268

402

5%

CRITICAL

1MBIT-104MHZ

OMIT_TABLE

USON

MX25L1006EZUI-10G

U4202

201

1/20W

10K

1% MF

R4206

201

1/20W

MF

33

1%

PLACE_NEAR=U4200:5mm

R4203

201

1/20W

33

1%MF

PLACE_NEAR=U4200:5mm

R4205

201

MF

33

1/20W

1%

PLACE_NEAR=U4202:5mm

R4209

201

1% 1/20W MF

10K

R4207

201

4.7K

1/20W MF

R4208

5%

10% X5R

16V

1UF

C4265

402

3.2X2.5MM-SM

CRITICAL

12.000MHZ-30PPM-10PF-85C

Y4200

J4200

20455-A20E-32

F-RT-SM

Camera Controller

SYNC_MASTER=J16_MAX

SYNC_DATE=02/11/2013

GND_AUDIO_DMIC

PP3V3_S4_ALS_F

SMIA_DATA_N SMIA_DATA_P

SMIA_CLK_P

SMIA_CLK_N

VOLTAGE=1.2V

MIN_NECK_WIDTH=0.15 MM

PP1V2_S4_F_R

MIN_LINE_WIDTH=0.6 MM

=PP3V3_S4_CAMERA

PP1V8_S4_CAMERA

PP1V2_S4_CAMERA

CAM_AGND

SMB_ALS_F_SCL

I2C_CAMSENSOR_SCL

PP5V_S4_CAMERA_F

PP1V8_S4_CAMERA_F

AUD_DMIC_CLK

MIN_LINE_WIDTH=0.4MM VOLTAGE=3.3V

MIN_NECK_WIDTH=0.15MM

PP3V3_DMIC_CONN

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.15 MM MIN_LINE_WIDTH=0.6 MM

PP1V8_S4_CAMERA_F

MIN_NECK_WIDTH=0.15 MM VOLTAGE=3.3V

MIN_LINE_WIDTH=0.6 MM

PP3V3_S4_ALS_F

SMIA_CLK_N

SMIA_CLK_P

SMIA_DATA_N

MIN_LINE_WIDTH=0.6 MM

MIN_NECK_WIDTH=0.15 MM VOLTAGE=3.3V

PP3V3_S4_CAMFILT

CAM_XTAL_IN

CAM_XTAL_OUT_R

VOLTAGE=5V

MIN_LINE_WIDTH=0.6 MM

MIN_NECK_WIDTH=0.15 MM

PP5V_S4_CAMERA_F

VOLTAGE=1.2V

PP1V2_S4_CAMFILT

MIN_LINE_WIDTH=0.6 MM

MIN_NECK_WIDTH=0.15 MM

USB_CAMERA_P

CAM_SF_HOLD_L

CAM_XTAL_OUT

CAM_TX

CAM_XTAL_IN

CAM_SF_DOUT

TP_CS_PWD_L

CAM_SF_CLK

CAM_XTAL_OUT

CAM_SF_CS_L

TP_ISM_CLK

TP_ISM_RST_L

CAM_RX

CAM_SF_WP_L

CAM_PLLGND

CAM_AGND

=PP3V3_S4_CAMERA

CAM_SF_CS_L

CAM_SF_CLK_R

CAM_SF_DIN

CAM_SF_DIN_R

CAM_SF_DOUT_R

CAM_SF_DOUT

CAM_SF_WP_L

PP1V8_S4_CAMERA

SMB_ALS_F_SCL

=SMB_ALS_SDA

SMB_ALS_F_SDA

CAM_EXT_BOOT

CAM_SF_DIN

MIPI_RESISTOR

CAM_SF_CLK

=PP5V_S4_CAMERA

USB_CAMERA_N

CAM_AGND

AUD_DMIC_SDA1

TP_CAM_GPIO1

CAM_PROC_RESET_L

CAM_USB_VRES

CAM_TEST

=PP3V3_S4_ALS

=SMB_ALS_SCL

CAM_PLLGND

=PP3V3_S4_CAMERA

I2C_CAMSENSOR_SCL I2C_CAMSENSOR_SDA

SMIA_DATA_P

I2C_CAMSENSOR_SDA

AUD_DMIC_CLK_CONN

AUD_DMIC_SDA1_CONN

=PP3V3_S0_AUDIO

SMB_ALS_F_SDA

051-0164

12.4.0

42 OF 123

38 OF 86

2

1

2

1

2

1

2

1

2

1

2

1

1 2

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

40

7

23

31

443522

48 47 46 12

28

30 29

927

4

5

37

6

33

18

39

41

21

20

17

42

3

25

34

43

26

38 36

11

24

1

14 13

49

2

8

15

19

10

45

32

16

1

2

1

2

21

1 2

1

2

1 2

2

1

2

1

2

21

2

1

21

1 2

2

1

21

2

1

21

2

1

1 2

2

1

1 2

2

1

7

6

3

1

8

9

4

2

5

1

2

1 2 12

1 2

1

2

1

2

1

42

1 3

24

23

15 16 17 18 19

14

11

7 8

20

13

12

22

1 2

5

4

6

10

9

21

25

26

3

52

38

38 80

38 39 70 38 39

38 39

38

38 80

38

52

38

38 80

38

13 80

38

38 80

38

38 80

38

38 39 70

38 80

80

38 80

80

38 80

38 39

38

47 38

39

38 80

70

13 80

38

52

39

70

47

38

38 39 70

38 80

52 54 55 58 70

38

NC

EN

NC

VO

VIN

GND

NC

EN

NC

VO

VIN

GND

D

G S

Y

A

B

08

Y

A

B

08

D

G S

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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8 7 6 5 4 3

C

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NOTICE OF PROPRIETARY PROPERTY:

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12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PP1V2_S4_CAMERA Vreg

Camera Processor ExtBoot Cntl

PP1V8_S4_CAMERA Vreg

Camera Processor Reset

10%

0.1UF

6.3V

C4300

CERM-X5R 0201

6.3V 402

X5R-CERM1

20%

4.7UF

C4314

10% X5R

402

16V

1UF

C4310

ISL9021AIRUCZ-T

CRITICAL

DFN

U4310

6.3V 402

20%

4.7UF

X5R-CERM1

C4324

ISL9021AIRUWZ-T

DFN

CRITICAL

U4320

10% X5R

1UF

16V 402

C4320

201

51K

MF

1/20W

5%

R4300

402

2.2UF

20% X5R-CERM

10V

C4301

SSM3K15AMFVAPE

VESM

CRITICAL

Q4300

CRITICAL

SOT902

74LVC2G08

U4300

4

8

CRITICAL

74LVC2G08

SOT902

U4300

4

8

SSM3K15AMFVAPE

CRITICAL

VESM

Q4302

201

1/20W MF

10K

5%

R4302

10% 10V

1UF

X5R-CERM 0402

C4312

201

1/20W

5% MF

4.7K

R4310

201

MF

1/20W

5%

4.7K

R4320

10%

1UF

0402

X5R-CERM

10V

C4322

MMDT3904-X-G

SOT-363-LF

Q4310

MMDT3904-X-G

SOT-363-LF

Q4310

201

5% 1/20W

10K

MF

R4306

201

MF

1/20W

5%

1K

R4304

Camera Controller Support

SYNC_DATE=02/11/2013

SYNC_MASTER=J16_MAX

CAM_P1V2_RST_HOLDOFF

=PP3V3_S4_CAMERA

CAM_PROC_RESET_L

PCH_CAM_EXT_BOOT_R_L

=PP3V3_S4_CAMERA

P1V8_S4_EN

PP1V2_S4_CAMERA

CAM_PROC_RESET

CAM_P1V2_RST_HOLDOFF_L

PP1V8_S4_CAMERA

=PP3V3_S4_CAMERA

CAM_EXT_BOOT_L

CAM_EXT_BOOT

P1V2_S4_EN

VOLTAGE=1.8V

PP1V8_S4_CAMERA

MIN_NECK_WIDTH=0.15 MM MIN_LINE_WIDTH=0.6 MM MIN_LINE_WIDTH=0.6 MM

MIN_NECK_WIDTH=0.15 MM VOLTAGE=1.2V

PP1V2_S4_CAMERA

PM_PCH_PWROK

PCH_CAM_RESET_R

=PP3V3_S4_CAMERA

PM_PCH_PWROK

051-0164

12.4.0

43 OF 123

39 OF 86

2

1

2

1

2

1

3

5

2

6

1

4

2

1

3

5

2

6

1

4

2

1

2

1

2

3

5

2

3

1

6

7

1

2

3

1

2

1

2

1

2

1

6

2

4

3

5

1

2

1

2

38 39 70

38

14

38 39 70

38 39

38 39 70

38

38 39 38 39

12 18 20 39 69

14

38 39 70

12 18

20

39

69

OUT

BI

IN IN

IN

BI

OUT OUT

BI BI

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

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NOTICE OF PROPRIETARY PROPERTY:

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A

C

PAGE TITLE

SHEET

R

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SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Delay applies only on a L->H transition on VIDEO_ON. This guarantees video is valid before the backlight is enabled. On a H->L transition, output follows with standard logic propagation delay. This ensures the backlight is off immediately after loss of video

518S0829

Internal DP Connector

To Diag LED

Backlight Control

To BLC

Display TCon Slave

Display TCon Master

0.001UF

0402

50V

20% CERM

C4401

10%

0805

X5R-CERM

16V

10UF

C4420

L4400

FERR-220-OHM

0805

47 81

41 85

47

52 85

41

41 85

66

20525-130E-01

CRITICAL

F-RT-SM

J4400

74AUP2G14GM

SOT886

U4450

2

5

74AUP2G14GM

SOT886

U4450

2

5

3

66

6.3V CERM-X5R

20%

10UF

0402-1

C4451

201

30.1K

1%

1/20W

MF

R4450

10%

0.1UF

6.3V

C4450

CERM-X5R 0201

BAT54XV2T1

SOD-523

D4450

201

MF

1/20W

5%

100K

R4451

F4400

3AMP-32V-467

603-HF

SYNC_DATE=02/11/2013

SYNC_MASTER=J16_MAX

Internal DP Support

=PP12V_S0_LCD

VOLTAGE=12V MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.1 mm

PP12V_LCD_F

VOLTAGE=12V MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.1 mm

PP12V_LCD

VIDEO_ON

=PP3V3_S0_DP

VIDEO_ON_L

VIDEO_ON_L_DLY BKLT_EN

DP_INTPNL_ML_P<1>

DP_INTPNL_ML_N<0>

DP_INTPNL_AUX_N

DP_INTPNL_HPD

DP_INT_SPDIF_AUDIO

DP_INTPNL_ML_P<0>

DP_INTPNL_AUX_P

SMB_DP_TCON_SDA SMB_DP_TCON_SCL SMB_DP_TCON_SLA_SDA SMB_DP_TCON_SLA_SCL

BKLT_VSYNC

DP_INTPNL_ML_N<1>

VIDEO_ON

051-0164

12.4.0

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1

2

1

21

31

35 36

33 34

1 2

5

4

3

6 7

10

9

8

20

19

17 18

16

14

13

12

11

21 22 23

30

29

28

27

26

25

24

15

32

37 38 39 40 41

1 6 3 4

2

1

1 2

2

1

A K

1

2

21

70

40

31 47 70

40

OUT

IN IN

OUT OUT

BI

OUT

IN

BI

IN

BI

AUX-

AUX+

D1+ D1-

HPD_SEL

GND

THMPAD

SEL

HPD_B

AUX-B

AUX+B

D1-B

D1+B

D0-B

HPD_A

AUX-A

AUX+A

D1-A

D0-

D0+A D0-A

D1+A

HPD

D0+

D0+B

VDD

AUX_SEL

IN

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

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12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

NC aliases

PD is on the CR page

TP to DP aliases

10%

0.1UF

6.3V

C4568

CERM-X5R 0201

10%

0.1UF

6.3V

C4569

CERM-X5R 0201

41 71

10%

X5R

6.3V

0201

0.15UF

C4500

10%

X5R

6.3V

0201

0.15UF

C4501

10%

X5R

6.3V

0201

0.15UF

C4502

10%

X5R

6.3V

0201

0.15UF

C4503

71 85

40 85

10%

0.1UF

0201

CERM-X5R6.3V

C4508

10%

0.1UF

0201

CERM-X5R6.3V

C4509

40 85

71 85

10%

0.1UF

0201

CERM-X5R6.3V

C4511

10%

0.1UF

0201

CERM-X5R6.3V

C4510

41 85

201

1/20W

R4500

100K

5% MF

26

11 58

40 85

40

201

5% 1/20W MF

R4502

100K

201

MF

1/20W

100K

R4503

5%

26

U4500

CRITICAL

PI3VEDP212

TQFN

71

26

41 85

201

5% 1/20W MF

2.7K

R4512

201

2.7K

1/20W

5% MF

R4513

201

5% 1/20W MF

2.7K

R4514

201

2.7K

MF

1/20W

5%

R4515

X5R

6.3V 0201

20%

0.22UF

C4512

X5R

6.3V 0201

20%

0.22UF

C4513

X5R

6.3V 0201

20%

0.22UF

C4514

X5R

6.3V

0.22UF

20%

0201

C4515

71

201

1/20W

1%

2.2K

MF

R4505

201

1/20W

1%

2.2K

MF

R4504

SYNC_DATE=02/11/2013

Internal DP MUXing

SYNC_MASTER=J16_MAX

DP_TBTSRC_ML_C_N<1>

DP_INT_HPD

DP_INT_AUX_P

DP_TBTSRC_AUX_C_P

DP_TBTSRC_ML_C_N<1>

DP_TBT_SEL

DP_TBTSRC_ML_C_P<0>

DP_INTPNL_ML_C_N<0>

DP_INTPNL_ML_C_P<0>

DP_INTPNL_ML_C_P<1>

DP_TBTSRC_ML_N<1>

DP_TBTSRC_ML_P<1>

DP_TBTSRC_ML_C_P<1>

DP_TBTSRC_ML_N<0>

DP_TBTSRC_ML_C_N<0>

DP_TBTSRC_ML_P<0>

MAKE_BASE=TRUE

DP_TBTSRC_ML_P<1>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_DP_TBTSRC_ML_P<2>

NO_TEST=TRUE

NC_DP_TBTSRC_ML_N<3>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_DP_TBTSRC_ML_P<3>

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_DP_TBTSRC_ML_N<2>

MAKE_BASE=TRUE

DP_TBTSRC_AUXCH_N

MAKE_BASE=TRUE

DP_TBTSRC_ML_N<1>

MAKE_BASE=TRUE

DP_TBTSRC_AUXCH_P

MAKE_BASE=TRUE

DP_TBTSRC_ML_N<0>

DP_TBTSRC_ML_P<0>

MAKE_BASE=TRUE

DP_TBTSRC_ML_C_P<0> DP_TBTSRC_ML_C_N<0>

DP_TBTSRC_ML_C_P<1>

DP_INT_ML_N<0>

DP_INT_ML_P<1> DP_INT_ML_N<1>

TP_DP_TBTSRC_AUXCH_CP

TP_DP_TBTSRC_ML_CP<2>

TP_DP_TBTSRC_ML_CP<3>

TP_DP_TBTSRC_ML_CN<2>

TP_DP_TBTSRC_AUXCH_CN

TP_DP_TBTSRC_ML_CN<1>

TP_DP_TBTSRC_ML_CP<1>

TP_DP_TBTSRC_ML_CN<0>

TP_DP_TBTSRC_ML_CP<0>

DP_INTPNL_ML_C_N<1>

=PP3V3_S0_INTDPMUX

DP_INTPNL_HPD

DP_INT_AUX_C_N

DP_INT_AUX_N

DP_TBTSRC_AUXCH_N

DP_INT_HPD

DP_INTPNL_AUX_N

DP_INT_AUX_C_P

DP_INTPNL_ML_P<0>

DP_INTPNL_ML_P<1> DP_INTPNL_ML_N<1>

DP_TBTSRC_AUXCH_P

DP_TBTSRC_HPD

DP_TBTSRC_AUX_C_N

DP_INTPNL_AUX_P

DP_INTPNL_ML_N<0>

=PP3V3_S0_INTDPMUX

DP_INT_DDC_CLK

DP_INT_DDC_DATA

DP_INT_ML_N<3>

DP_INT_ML_P<3>

NC_DP_INT_ML_P<2>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_DP_INT_ML_N<2>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_DP_INT_ML_N<3>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_DP_INT_ML_P<3>

NO_TEST=TRUE

MAKE_BASE=TRUE

DP_INT_ML_N<2>

DP_INT_ML_P<2>

TP_DP_TBTSRC_ML_CN<3>

DP_INT_ML_P<0>

051-0164

12.4.0

45 OF 123

41 OF 86

2

1

2

1

1 2

1

2

1

2

1

2

7

6

4 5

11

213328

10

13

14

15

22

23

24

17

18

19

26

292016

12

2

31 30

27

8

1

25

9

3

32

1

2

1

2

1

2

1

2

1 2

1

2

1

2

41 85

41 71

85

41 85

85

41 85

85

41 70

85

41 70

GND

THRM

OUT2

OUT1

ILIM

IN_0 IN_1

EN2

FAULT1* FAULT2*

EN1

PAD

IN

BI

L2

L1

L2

L1

L2

L1

L2

L1

SYM_VER-1

IN

OUT

BI BI

STDA_SSTX+

STDA_SSTX-

STDA_SSRX+

GND

DD+

GND_DRAIN

VBUS

STDA_SSRX-

SHIELD

STDA_SSTX+

STDA_SSTX-

STDA_SSRX+

GND

DD+

GND_DRAIN

VBUS

STDA_SSRX-

SHIELD

NC

GND

VBUS

IO

BI

IN

VCC

GND

SELOE*

D+ D-

Y+ Y-

M+ M-

OUT

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

EXT PORT A

514-0817

514-0825

EXT PORT B

SON

CRITICAL

TPS2561DR

U4600

402

20% 10V

CERM

C4601

0.1UF

C4605

0402

16V

20%

X7R-CERM

0.01UF

C4615

16V

20%

X7R-CERM

0402

0.01UF

13 80

CRITICAL

0504

80OHM-25%-100MA

L4603

GND_VOID=TRUE

L4604

80OHM-25%-100MA

CRITICAL

0504

L4613

CRITICAL

0504

80OHM-25%-100MA

GND_VOID=TRUE

CRITICAL

0504

80OHM-25%-100MA

GND_VOID=TRUE

L4614

CRITICAL

L4602

DLP0NS

120-OHM-90MA

L4612

CRITICAL

DLP0NS

120-OHM-90MA

0201

0.1UF

6.3V

10%

CERM-X5R

C4608

C4609

0.1UF

02016.3VCERM-X5R

10%

0.1UF

0201

C4618

CERM-X5R 6.3V

10%

C4619

0201

0.1UF

6.3VCERM-X5R

10%

330UF-25MOHM

C4602

CRITICAL

CASE-D2E

TANT

20%

6.3V

C4606

20% 10V

402

CERM

0.1UF

44 45

13 80

J4600

USB-NO1-K70

F-ANG-TH

CRITICAL

J4610

F-ANG-TH

USB-NO2-K70

CRITICAL

RCLAMP0582N

CRITICAL

SLP1210N6

D4611

ESD0P2RF-02LS

TSSLP-2-1

D4604

CRITICAL

D4605

CRITICAL

TSSLP-2-1

ESD0P2RF-02LS

TSSLP-2-1

D4602

ESD0P2RF-02LS

CRITICAL

D4603

TSSLP-2-1

ESD0P2RF-02LS

D4615

TSSLP-2-1

ESD0P2RF-02LS

CRITICAL

D4614

ESD0P2RF-02LS

TSSLP-2-1

CRITICAL

D4613

ESD0P2RF-02LS

TSSLP-2-1

D4612

ESD0P2RF-02LS

CRITICAL

TSSLP-2-1

R4603

11.5K

1% 1/16W MF-LF

402

13 80

100K

R4605

1/16W

5%

402

MF-LF

FERR-120-OHM-3A

0603

L4611

44

CKPLUS_WAIVE=pdifpr_badterm

TQFN

CKPLUS_WAIVE=ndifpr_badterm

CKPLUS_WAIVE=pdifpr_badterm

PI3USB102EZLE

SIGNAL_MODEL=PI3USB102_TQFN_PI3USB102ZLE_MOJO

CKPLUS_WAIVE=ndifpr_badterm

CRITICAL

U4610

CRITICAL

D4606

ESD0P2RF-02LS

TSSLP-2-1

CRITICAL

D4601

ESD0P2RF-02LS

C4617

10V CERM

20%

402

0.1UF

13 18

13 80

FERR-120-OHM-3A

L4601

0603

10V

20%

402

C4607

0.1UF

CERM

R4602

402

MF-LF

1/16W

1%

11.5K

13 18

SYNC_MASTER=J16_KOSECOFF

EXTERNAL USB PORTS A & B

SYNC_DATE=03/18/2013

USB3_EXTB_TX_C_N

USB3_EXTB_TX_N

USB3_EXTB_RX_P

USB2_EXTB_P

USB2_EXTB_N

PP5V_S4_EXTB_F

MIN_NECK_WIDTH=0.2MM

VOLTAGE=5V MIN_LINE_WIDTH=0.6MM

USB3_EXTA_TX_F_N

USB3_EXTA_TX_N

USB3_EXTA_TX_C_N

USB3_EXTA_TX_P

USB3_EXTA_RX_F_P

USB3_EXTA_RX_P

USB3_EXTA_RX_N

USB3_EXTA_TX_F_P

USB2_EXTA_MUXED_N

USB2_EXTA_MUXED_P

SMC_DEBUGPRT_EN_L

USB_EXTB_OC_L

USB3_EXTB_TX_F_N USB3_EXTB_TX_F_P

=PP5V_S4_USB

USB_EXTA_OC_L

USB3_EXTB_RX_F_P

USB3_EXTB_RX_F_N

USB3_EXTA_TX_C_P

USB3_EXTB_TX_P

USB3_EXTB_TX_C_P

PM_EN_USB_PWR

USB_ILIM1_R

USB_EXTB_8_P

USB_EXTB_8_N

USB3_EXTB_RX_N

USB_ILIM1

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

VOLTAGE=5V

PP5V_S4_EXTB_ILIM

USB3_EXTA_RX_F_N

USB2_EXTA_N USB2_EXTA_P

PP5V_S4_EXTA_F

VOLTAGE=5V MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

=PP3V3_G3H_SMC_USBMUX

SMC_DEBUGPRT_TX_L

PP5V_S4_EXTA_ILIM

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

VOLTAGE=5V

USB_EXTA_0_P

USB_EXTA_0_N

SMC_DEBUGPRT_RX_L

051-0164

12.4.0

46 OF 123

42 OF 86

1

11

8

9

7

2 3

5

10

6

4

2

1

2

1

2

1

4

3

2

1

4

3

2

1

4

3

2

1

4

3

2

1

4 3

1 2

4 3

1 2

1

2

1

9

8

6

4

14 15 16

2 3

11 12 13

17

21

7

1

5

22

10

18 19 20

9

8

6

4

14 15 16

2 3

11 12 13

17

21

7

1

5

22

10

18 19 20

32

1

6

5 4

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

21

93

10

8

7 6

1 2

5 4

1

2

1

2

1

21

2

1

2

80

43 70

80

43 68

80

70

OUT

L2

L1

L2

L1

SYM_VER-1

L2

L1

IN

L2

L1

IN

STDA_SSTX+

STDA_SSTX-

STDA_SSRX+

GND

DD+

GND_DRAIN

VBUS

STDA_SSRX-

SHIELD

STDA_SSTX+

STDA_SSTX-

STDA_SSRX+

GND

DD+

GND_DRAIN

VBUS

STDA_SSRX-

SHIELD

NC

GND

VBUS

IO

NC

GND

VBUS

IO

BI

GND

THRM

OUT2

OUT1

ILIM

IN_0 IN_1

EN2

FAULT1* FAULT2*

EN1

PAD

OUT OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

EXT PORT D

EXT PORT C

J17:514-0841

J16:514-0826

J17:514-0842

J16:514-0827

13 80

L4703

0504

80OHM-25%-100MA

CRITICAL

GND_VOID=TRUE

L4713

GND_VOID=TRUE

0504

80OHM-25%-100MA

CRITICAL

L4702

DLP0NS

120-OHM-90MA

CRITICAL

L4712

120-OHM-90MA

DLP0NS

CRITICAL

L4704

0504

CRITICAL

80OHM-25%-100MA

GND_VOID=TRUE

0201

0.1UF

C4708

6.3VCERM-X5R

10%

0.1UF

0201

C4709

6.3V

10%

CERM-X5R

13 80

L4714

GND_VOID=TRUE

0504

80OHM-25%-100MA

CRITICAL

C4718

0201

0.1UF

10%

CERM-X5R 6.3V

C4719

6.3V 0201

0.1UF

10%

CERM-X5R

13 80

L4701

0603

FERR-120-OHM-3A

C4702

20%

CRITICAL

TANT CASE-D2E

330UF-25MOHM

6.3V

J4700

USB-NO3-K70

F-ANG-TH

CRITICAL

J4710

CRITICAL

USB-NO4-K70

F-ANG-TH

D4701

RCLAMP0582N

SLP1210N6

CRITICAL

D4711

CRITICAL

RCLAMP0582N

SLP1210N6

D4705

ESD0P2RF-02LS

TSSLP-2-1

CRITICAL

D4704

ESD0P2RF-02LS

TSSLP-2-1

CRITICAL

D4703

CRITICAL

ESD0P2RF-02LS

TSSLP-2-1

D4702

TSSLP-2-1

ESD0P2RF-02LS

CRITICAL

D4715

ESD0P2RF-02LS

TSSLP-2-1

CRITICAL

D4714

ESD0P2RF-02LS

CRITICAL

TSSLP-2-1

D4713

ESD0P2RF-02LS

TSSLP-2-1

CRITICAL

D4712

ESD0P2RF-02LS

TSSLP-2-1

CRITICAL

R4703

1/16W

1%

402

MF-LF

11.5K

13 80

L4711

0603

FERR-120-OHM-3A

13 80

C4707

20% 10V CERM 402

0.1UF

C4705

16V

20%

X7R-CERM

0402

0.01UF

C4717

20% 10V

402

CERM

0.1UF

C4715

16V

20%

0402

X7R-CERM

0.01UF

R4702

1/16W

1%

402

MF-LF

11.5K

U4700

SON

TPS2561DR

CRITICAL

C4701

10V

CERM

20%

402

0.1UF

13 18

SYNC_MASTER=J16_KOSECOFF

SYNC_DATE=03/18/2013

EXTERNAL USB PORTS C & D

USB3_EXTC_TX_C_P

USB2_EXTD_N

USB_EXTD_9_N

USB2_EXTC_P

PP5V_S4_EXTC_F

VOLTAGE=5V MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

USB_ILIM2_R

PM_EN_USB_PWR

=PP5V_S4_USB

PP5V_S4_EXTD_F

MIN_LINE_WIDTH=0.6MM

VOLTAGE=5V MIN_NECK_WIDTH=0.2MM

USB3_EXTD_RX_F_N

USB3_EXTC_TX_N

USB_EXTD_OC_L

USB3_EXTD_RX_F_P

USB_EXTC_OC_L

USB3_EXTC_TX_P

USB3_EXTD_TX_C_N

USB3_EXTD_TX_C_P

USB3_EXTD_TX_N

USB3_EXTD_TX_P

USB3_EXTC_RX_F_P

USB_ILIM2

USB3_EXTC_TX_C_N

USB2_EXTD_P

USB3_EXTC_RX_N USB3_EXTC_RX_P

USB3_EXTC_TX_F_P

USB3_EXTD_TX_F_P

USB3_EXTD_TX_F_N

USB3_EXTD_RX_P

USB3_EXTD_RX_N

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

VOLTAGE=5V

PP5V_S4_EXTD_ILIM

VOLTAGE=5V

PP5V_S4_EXTC_ILIM

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

USB3_EXTC_TX_F_N

USB3_EXTC_RX_F_N

USB2_EXTC_N

USB_EXTC_1_P

USB_EXTC_1_N

USB_EXTD_9_P

051-0164

12.4.0

47 OF 123

43 OF 86

4

3

2

1

4

3

2

1

4 3

1 2

4 3

1 2

4

3

2

1

1 2

4

3

2

1

1 2

21

1

2

9

8

6

4

14 15 16

2 3

11 12 13

17

21

7

1

5

22

10

18 19 20

9

8

6

4

14 15 16

2 3

11 12 13

17

21

7

1

5

22

10

18 19 20

32

1

6

5 4

32

1

6

5 4

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

21

2

1

2

1

2

1

2

1

2

1

11

8

9

7

2 3

5

10

6

4

2

1

80

42 68

42 70

80

LPC0AD3 LPC0CLK LPC0FRAME*

LPC0AD1 LPC0AD2

AIN08

AIN07 LPC0CLKRUN* LPC0PD*

AIN13

AIN14

PM7/FAN0TACH0

PM6/FAN0PWM0

AIN04

C1-

I2C2SDA

AIN05

AIN09

AIN11

AIN21

AIN23

PK7/FAN0TACH1

AIN15

AIN06

AIN10

AIN20

AIN22

T1CCP1/PJ1

PK5

LPC0AD0

AIN12

PECI0RX PECI0TX

PK6/FAN0PWM1

LPC0RESET*

PQ0/IRQ124

PP6/IRQ122

PN3/FAN0TACH2

I2C0SDA

AIN01

AIN00

PQ1/IRQ125

I2C0SCL

U1TX/PB1

USB0DP

USB0DM

AIN03

AIN02

T0CCP1/PB7

T0CCP0/PB6

PQ2/IRQ126

U1RX/B0

LPC0SCI*

AIN17

AIN16

PN2/FAN0PWM2

WT4CCP1/PH7

AIN18

AIN19

WT4CCP0/PH6

WT3CCP1/PH5

WT5CCP1/PM3

LPC0SERIRQ

PH3/FAN0TACH5

WT3CCP0/PH4

PH2/FAN0PWM5

PP3/IRQ119 PP4/IRQ120

C0-

WT2CCP0/PH0 WT2CCP1/PH1

PQ5/IRQ129

PP7/IRQ123

WT0CCP0/PG4

I2C3SDA

SSI1FSS/PF3

PC5/C1+

U0RX

SSI0RX/PA4

PP5/IRQ121

PQ7/IRQ131

WT0CCP1/PG5

I2C3SCL

SSI1CLK/PF2

PN4/FAN0PWM3

PP1/IRQ117

U0TX

SSI0CLK/PA2 SSI0FSS/PA3

I2C1SCL

PP2/IRQ118

PQ6/IRQ130

I2C4SDA

SSI1RX/PF0

PN7/FAN0TACH4

PP0/IRQ116

SSI0TX/PA5

I2C1SDA

I2C5SDA

PQ3/IRQ127 PQ4/IRQ128

I2C4SCL

I2C2SCL

SSI1TX/PF1

PN6/FAN0PWM4

PN5/FAN0TACH3

I2C5SCL

T3CCP0/PJ4/C2+

T3CCP1/PJ5/C2-

PF4 PF5

T1CCP0/PJ0

T2CCP0/PJ2 T2CCP1/PJ3

C0+

(1 OF 2)

VDDC

VREFA-

SWO/TDO

TDI

RST*

HIB*

WAKE*

XOSC0

VREFA+

VDDA

GNDA

PK4/RTCCLK

GND

NC

OSC0

XOSC1

SWCLK/TCK SWDIO/TMS

OSC1

VBAT

VDD

(2 OF 2)

IN

BI BI BI BI

IN IN

IN BI OUT

IN OUT

BI BI BI BI BI BI BI BI BI BI BI BI

IN IN IN

IN

OUT OUT OUT OUT

OUT

IN

OUT

OUT OUT OUT

IN

OUT

IN

OUT

OUT OUT OUT

NC

OUT

IN OUT

BI BI

OUT

IN

OUT

IN

OUT

IN

IN OUT

OUT

BI

OUT OUT

IN

IN OUT

IN

OUT

IN

OUT

IN

OUT

IN IN

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

arch

proj

arch

od

int

those designated as inputs require pull-ups.

arch

pwm

arch

analog

int

arch

arch arch

arch

(OD)

arch

int

arch

arch arch arch

arch

proj

arch

arch arch

pins designed as outputs can be left floating,

arch

proj

od

arch

int

proj

analog

arch

od

arch

proj

arch

od

analog

od

int

arch

proj

arch

proj

od

int

arch

proj

arch

analog

proj

analog

int

arch

od

analog

proj

analog

proj

analog

proj

analog

proj

analog

proj

analog analog

analog

proj

analog

arch

proj

arch

od

arch

proj

int

arch

proj

arch

proj

NOTE: Unused pins have "SMC_Pxx" names. Unused

proj

arch

proj

arch

proj

analog

proj

analog

od

analog

arch

int

arch

analog

proj

arch

arch arch arch

arch

proj

analog

proj

od

arch

int

arch

proj

arch

arch arch

proj

analog

U5000

OMIT_TABLE

BGA

LM4FSXAH5BB

U5000

BGA

OMIT_TABLE

LM4FSXAH5BB

XW5000

PLACE_NEAR=U5000.A1:4MM

SM

45 46

45 79

R5002

1M

MF

1/20W

5%

201

20%

1UF

C5002

0603-1

X5R-CERM

10V

13 46 79

19 79

13 46 79

20 81

13 46

12 45 46

12 20 46

14 81

47 81

45

45 81

45

45 60

45 69

28 45 69

45

42 45

45

46 79

42

45

3

21 69

45

12 18

12 19

23 24 45

14 81

6

14 45 76

45 76

45 46

45

51

45

51 81

45

32 45

45

12 21 36 45 68 69

12 68

12 32 68

45

32 45

45

32 45

45

69

19

L5001

0402

30-OHM-1.7A

6

45 61 62 76

34 81

45

34 81

45

0201

6.3V CERM-X5R

C5017

0.1UF

10%

0201

6.3V CERM-X5R

C5013

0.1UF

10%

0201

6.3V CERM-X5R

C5014

0.1UF

10%

0201

6.3V CERM-X5R

C5015

0.1UF

10%

0201

6.3V CERM-X5R

C5016

0.1UF

10%

0201

6.3V CERM-X5R

C5003

0.1UF

10%

0201

6.3V CERM-X5R

C5004

0.1UF

10%

0201

6.3V CERM-X5R

C5005

0.1UF

10%

0201

6.3V CERM-X5R

C5006

0.1UF

10%

0201

6.3V CERM-X5R

C5009

0.1UF

10%

0201

6.3V CERM-X5R

C5008

0.1UF

10%

0201

6.3V CERM-X5R

C5007

0.1UF

10%

0201

6.3V CERM-X5R

C5001

0.1UF

10%

45

0201

C5021

PLACE_NEAR=U5000.D2:4mm

10V X5R-CERM

0.01UF

10%20%

1.0UF

0201-1

X5R

6.3V

C5020

PLACE_NEAR=U5000.D1:4mm

1UF

6.3V

C5010

402

CERM

10%

1UF

6.3V

C5011

402

CERM

10%

1UF

6.3V

C5012

402

CERM

10%

SYNC_MASTER=J16_TONY

SMC

SYNC_DATE=03/13/2013

SMC_GFX_THROTTLE_L

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.25 MM

PP3V3_G3H_SMC_VDDA

MIN_NECK_WIDTH=0.1 MM

NC_SMC_XOSC1

NO_TEST=TRUE

NC_SMC_HIB_L

NO_TEST=TRUE

MIN_NECK_WIDTH=0.1 MM VOLTAGE=1.2V

MIN_LINE_WIDTH=0.25 MM

PP1V2_G3H_SMC_VDDC

SMBUS_SMC_1_S0_SCL SMBUS_SMC_1_S0_SDA SMBUS_SMC_2_S4_SCL

SMBUS_SMC_3_SDA SMBUS_SMC_4_ASF_SCL SMBUS_SMC_4_ASF_SDA

SMC_ADC10

SMC_PM_PCH_SYS_PWROK

SMC_DEBUGPRT_EN_L

LPC_CLK33M_SMC

LPC_AD<3>

LPC_AD<2>

SMC_RUNTIME_SCI_L

SMC_ADC11

LPC_AD<0>

SMC_ADC5

SMC_TDO

CPU_PROCHOT_L

SMBUS_SMC_5_G3H_SCL

SMC_ADC18

SMC_ADC23

SMC_TX_L

SMC_FAN_1_CTL

SMC_ADC7

SMC_ADC12

SMC_ADC19

SMC_RESET_L

SMC_WAKE_L

SMC_EXTAL

AP_EVENT_L

SMC_CLK32K

SMC_ADC0

SMC_ADC21 SMC_ADC22

PM_CLKRUN_L LPC_PWRDWN_L

SMC_ADC8

SMBUS_SMC_0_S0_SDA

SMC_ADC6

SMC_FAN_0_TACH

SMC_FAN_0_CTL

SMC_ADC14

SMC_ADC13

SMC_ADC3

SMC_XTAL

SMC_ADC2

SMC_ADC9

SMC_ADC4

SMC_ADC1

LPC_AD<1>

SMC_FAN_1_TACH

SPI_SMC_CS_L

PM_SLP_S3_L

SMC_THRMTRIP

ALL_SYS_PWRGD

SMC_PJ3

SMC_LRESET_L LPC_SERIRQ

SMC_WAKE_SCI_L

G3_POWERON_L

SMC_PN7 SMC_PH2 SMC_PH3

SMC_PECI_L

CPU_PECI

PM_SLP_S5_L

SMC_PP0

SMS_INT_L SMC_BC_ACOK

PM_SLP_S4_L

SMC_RX_L

SMBUS_SMC_0_S0_SCL

SMC_TOPBLK_SWP_L SMC_PN3

SMC_PP5

SMC_DP_HPD_L SMC_PME_S4_WAKE_L SMC_PME_S4_DARK_L SMC_PP4

SMC_PP7

SMC_TDI

=PP3V3_G3H_SMC

SMC_TMS

SMC_TCK

PP3V3_G3H_AVREF_SMC

GND_SMC_AVSS

SMC_ADC15

LPC_FRAME_L

SPI_SMC_MISO

PM_PWRBTN_L

SMC_PJ2

SMC_OOB1_D2R_L

SMC_PP6

MEM_EVENT_L

SMC_OOB1_R2D_L

ENET_ASF_GPIO

SMC_ONOFF_L

SMBUS_SMC_5_G3H_SDA

SMC_VCCIO_CPU_DIV2 SMC_S5_PWRGD_VIN

SPI_DESCRIPTOR_OVERRIDE_L

SMC_ADC20

SMC_ADC17

SMC_ADC16

SMC_PH7

SMC_PROCHOT

CPU_THRMTRIP_3V3

SMC_PM_G2_EN

SMC_DELAYED_PWRGD

SMC_DEBUGPRT_RX_L SMC_DEBUGPRT_TX_L SMC_SYS_LED

SPI_SMC_MOSI SPI_SMC_CLK

S5_PWRGD

SMC_GFX_OVERTEMP

PM_DSW_PWRGD

SMC_CPU_CATERR_L

SMBUS_SMC_3_SCL

SMBUS_SMC_2_S4_SDA

SMC_PN5 SMC_G3_WAKESRC_EN

SMC_BATLOW_L

SMC_PL6

SMC_PL7

PM_SYSRST_L

SMC_PN4

051-0164

12.4.0

50 OF 123

44 OF 86

D11 H12 D12

A13 C12

B5

A4 G11 F13

C2

B1

L13

H11

B3

L2

M8

A3

A5

A6

A7

A8

A12

B2

B4

B6

B7

B8

B9

B12

B13

C1

C4 C6

C11

C13

D4

D8

D10

D13

E1

E2

E4

E10

E11

E12

E13

F1

F2

F3

F4

F5

F11

F12

G1

G2

G3

G4

H1

H2

H3

H4

H10

H13

J2

J3

J4

J12

J13

K2

K3

K4

K5

K6

K7

K8

K10

L1

L3

L4

L5

L6

L7

L8

L10

L11

L12

M1

M2

M3

M4

M5

M6

M7

M9

M11

M13

N1

N2

N3

N5

N6

N7

N8

N9

N11

N12

N4

D5

C5

L9

K9

C9

A9

C8

K1

K13

J1

J9

J7

F10

D1

C7

A11 B10

G10

M12

N13

M10

D2

D3

C3

B11

A1

A2

E3

E5 F9

G12

H5 H9 J5

E6 E8

D9

J10

E9

N10

J8

C10 A10

G13

K12

D7

K11

J11

D6

J6

12

1

2

1

21

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

45 46

45 81

45 46

45 51 70

45 46

45

45 48 49 81

SN0903049

PAD

REFOUT

MR1*

THRM

GND

RESET*

DELAY

MR2*

VIN

V+

NC NC

OUT

IN

BI

IN

BI

OUT

IN

OUT

IN

OUT

IN

OUT

D

SG

D

SG

IN

OUT

IN

D

G S

D

G S

D

G S

OUT

IN

D

G S

IN

OUT

Y

B

A

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Platform Thermal Control

This passes CPU’s TRHMTRIP to SMC so shutdown reason can be recorded.

This allows SMC to shutdown system.

Unused ADC Channels

Unused Project-specific

TP for access if ZPB re-intstated

SMC Controlled RTC Reset

ADC Channel Aliases

SMC control for AirPort power

Level-shifter that allows SMC to drive PROCHOT

case when SMC is initializing in S5,

and ACDC_BURST_EN_L could be floating.

Note: For SMC recovery mode

SMC 32KHz Clock

NOTE: SMC team wants 12MHz for this Xtal

(ipu)

Note: IPU are pulled to VIN rail

Power Button

SMC Crystal

SMC Supervisor and AVREF Supply

Note:

To absorb current from discharging RTC Reset CAP

PECI Support

PROCHOT Support

Serial/JTAG Interface Pull-ups

Place this circuit near the Tee point to minimize reflections

Arch Pull Up/Down

and chip is not yet configured.

Level-shifter that allows SMC to drive PECI

Open-drain stage on S4 to account

AC/DC Burst Mode Enable

Project-specific Aliases

Comparator Reference

DFN

CRITICAL

VREF-3.3V-VDET-3.0V

U5100

402

0.47UF

CERM-X5R

C5100

6.3V

10%

16V

X7R-CERM

0402

0.01UF

C5101

10%

10V

0603-1

1UF

20%

X5R-CERM

C5105

X7R-CERM

16V

0.01UF

0402

C5106

10%

402

1/16W MF-LF

100K

R5105

5%

NTC020AA1JB260T

SM

SILK_PART=PwrBtn

J5120

DEVELOPMENT

44

C0G-CERM

50V

12PF

C5165

0402

5%

C0G-CERM

12PF

0402

50V

C5166

5%

402

MF-LF

1/16W

R5165

0

5%

44

6

44 61 62 76

100K

R5178

MF

1/20W

201

5%

402

R5135

MF-LF

1/16W

0

5%

44 76

402

NONE

NOSTUFF

NONE

OMIT

R5136

402

1/16W MF-LF

330

R5137

5%

6

14 44

76

402

10K

1% 1/16W MF-LF

PLACE_NEAR=U5000.K1:5MM

R5130

402

1/16W

10K

1%

PLACE_NEAR=U5000.K1:5MM

MF-LF

R5131

44

10K

R5185

MF

1/20W 201

5%

R5175

10K

MF

1/20W 201

5%

R5180

10K

MF

1/20W 201

5%

44 79

402

PLACE_NEAR=U1100.W36:10MM

MF-LF

22

1/16W

R5160

5%

12 79

10K

R5120

MF

1/20W

201

5%

60

100K

R5179NOSTUFF

MF

1/20W 201

5%

10K

R5190

MF

1/20W 201

5%

100K

R5191

MF

1/20W 201

5%

10K

R5195

MF

1/20W 201

5%

10K

R5196

MF

1/20W 201

5%

10K

R5197

MF

1/20W 201

5%

10K

R5198

MF

1/20W 201

5%

20K

R5193

MF

1/20W 201

5%

20K

R5192

MF

1/20W 201

5%

100K

R5187

MF

1/20W 201

5%

R5176

10K

MF

1/20W 201

5%

R5148

0201

MF

1/20W

0

5%

12 18 69 44

44

R5149

0201

MF

1/20W

0

5%

6

76

R5126

10K

MF

1/20W

201

5%

46

44

R5125

1K

MF

1/20W

201

5%

14

Q5140

SSM6N15AFE

CRITICAL

SOT563

10K

R5140

MF

1/20W

201

5%

SSM6N15AFE

SOT563

CRITICAL

Q5140

45

R5141

10K

MF

1/20W

201

5%

60 65

402

1/16W

43

MF-LF

R5138

5%

DFN1006H4-3

Q5127

BC846BLP

CRITICAL

R5127

3.3K

MF

1/20W

201

5%

6

14 76

10K

R5128

MF

1/20W

201

5%

VESM

SSM3K15AMFVAPE

Q5135

CRITICAL

VESM

SSM3K15AMFVAPE

Q5125

X7R-CERM

16V 0402

PLACE_NEAR=U5000.K1:3MM

C5131

0.1UF

10%

VESM

CRITICAL

SSM3K15AMFVAPE

Q5199

11 19

402

R5199

MF-LF

10K

1/16W

5%

1.0UF

C5199

NOSTUFF

0402

20% X5R-CERM

6.3V

402

330

MF-LF

1/16W

R5194

5%

R5170

10K

MF

1/20W 201

5%

R5171

10K

MF

1/20W 201

5%

402

MF-LF

1/16W

1M

NOSTUFF

R5166

5%

402

R5184

100K

1/16W

MF-LF

5%

402

R5186

1/16W

MF-LF

100K

5%

10K

R5181

MF

1/20W 201

5%

44

5X3.2X1.2-SM

12.000MHZ-50PPM-8PF-100OHM

CRITICAL

Y5165

402

1/16W MF-LF

47

R5102

5%

402

20% X5R-CERM1

4.7UF

C5102

6.3V

R5103

0201MF

1/20W

0

5%

44 46

1000PF

0402

CERM

25V

NOSTUFF

C5103

5%

R5154

1K

MF

1/20W

201

5%

12 44

0201

CERM-X5R

C5140

6.3V

0.1UF

10%

100K

R5118

MF

1/20W 201

5%

Q5123

SSM3K15AMFVAPE

VESM

CRITICAL

45 32

100K

R5142

MF

1/20W

201

5%

CRITICAL

TC7SZ08FEAPE

SOT665

U5140

SYNC_MASTER=J16_TONY

SMC Support

SYNC_DATE=03/13/2013

=PP3V3_S5_SMC

PM_SLP_S3_L

PM_SLP_S3_BUF_L

ACDC_BURST

ACDC_BURST_EN_L

SMC_ADC16

SMC_PJ3

SMC_PN5

SMC_PJ2

SMC_PP0

SMC_PH2

SMC_PL6

SMC_S5_PWRGD_VIN

=PP3V3_S4_SMC

BURSTMODE_EN_L

=PP3V3_S4_AP

SMC_VCCIO_CPU_DIV2

=PP1V05_S0_SMC

SMC_ADC18

SMC_ADC22

SMC_THRMTRIP

SMC_ADC0

CPU_CATERR_L

G3_POWERON_L

SMC_PME_S4_WAKE_L

SMC_TOPBLK_SWP_L

PM_PCH_SYS_PWROK

SMC_CPU_CATERR_L

SMC_PM_PCH_SYS_PWROK

PCH_STRP_TOPBLK_SWP_L

SMC_PROCHOT

CPU_PROCHOT_L

SMC_PECI_L

CPU_PECI

CPU_PECI_R

SMC_PECI_L_R

=PP1V05_S0_SMC

PM_THRMTRIP_L

=PP3V3_S5_SMC

=PP3V3_G3H_SMC

SMC_ADC23

SMC_ADC2

=PP3V3_S5_SMC

=PP3V3_S0_SMC

SMS_INT_L

SMC_SYS_LED

SMBUS_SMC_4_ASF_SDA

SMC_ADC15

PM_CLKRUN_L

ENET_ASF_GPIO

SMC_BC_ACOK

PP3V3_S4_AP_FET

SMC_PP6

SMC_PP5

=PP3V3_G3H_SMC

SMC_DEBUGPRT_TX_L SMC_DEBUGPRT_RX_L

SMC_RX_L

SMC_TCK SMC_TDI SMC_TDO SMC_TMS

=PP3V3_G3H_SMC

SMC_TX_L

SMC_CLK32K

SMC_PN3

SMC_XTAL_R

SMC_XTAL

PWR_BTN

RTC_RESET_L

RTC_RESET_L_R

=PP3V3_G3H_SMC

PM_CLK32K_SUSCLK_R

=PP3V3_G3H_SMC

SMC_MANUAL_RST_L

SMC_PN4

SMC_ADC4

SMC_ADC5

SMC_ADC7

SMC_ADC6

SMC_ADC10

SMC_ADC11

SMC_ADC17

SMC_PH3

SMC_ADC1

SMC_ADC14

SMC_ADC20

SMC_ADC3

SMC_ADC8

SMC_ADC9

SMC_ADC13

SMC_ADC12

SMC_PN7

SMC_PP4

SMBUS_SMC_5_G3H_SDA

SMBUS_SMC_4_ASF_SCL

SMC_DP_HPD_L

SMC_PP7

SMC_RESET_R_L

MEM_EVENT_L

SMC_ASSERT_RTCRST

SMC_WIFI_PWR_EN

SMC_PME_S4_DARK_L

SMC_PH7

SMC_PL7

SMC_RESET_L

=PPVIN_G3H_SMCVREF

SMC_EXTAL

SMC_ROMBOOT

SMC_BATLOW_L

SMC_ADC21

SMC_ADC19

SMC_GFX_OVERTEMP

SMC_GFX_THROTTLE_L

SMBUS_SMC_5_G3H_SCL

AP_EVENT_L

SMC_G3_WAKESRC_EN

SMC_PM_G2_EN

PM_DSW_PWRGD

SMC_DELAYED_PWRGD

NO_TEST=TRUE

NC_SMBUS_SMC_4_ASF_SDA

MAKE_BASE=TRUE

NC_VSNS_P12VS0_GPUCORE

NO_TEST=TRUE

NC_ISNS_P12VS0_FBVDDQ

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SMC_GFX_THROTTLE_L

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SMC_GFX_OVERTEMP

NC_SMC_BATLOW_L

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

VSNS_PVDDQS0

NC_SMC_S5_PWRGD_VIN

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SMC_PP5

MAKE_BASE=TRUE

NC_SMC_PP7

NO_TEST=TRUE

MAKE_BASE=TRUE

ISNS_VDDQS3_DDR

SMC_ONOFF_L

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SMC_ADC23

NC_SMC_ADC22

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_VSNS_P12VS0_FBVDDQ

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SMBUS_SMC_5_G3H_SDA

NO_TEST=TRUE

MAKE_BASE=TRUE

VOLTAGE=0V

GND_SMC_AVSS

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.1MM

MAKE_BASE=TRUE

ISNS_PVDDQS0

MAKE_BASE=TRUE

VSNS_VDDQS3_DDR

NC_ISNS_GPUCORE_ALT

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_ISNS_P12VS0_GPUCORE

NC_VSNS_GPUCORE_ALT

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

ISNS_P3V3S4_AP

ISNS_SSDS0

MAKE_BASE=TRUE

VSNS_P1V05S0_PCH

ISNS_HDDS0

MAKE_BASE=TRUE

VSNS_HDDS0

ISNS_CPUVCC

MAKE_BASE=TRUE

VSNS_CPUVCC

MAKE_BASE=TRUE

NC_SMC_PP6

NO_TEST=TRUE

VOLTAGE=3.42V

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.1MM

PP3V42_G3H_SMC_SPVSR

NC_SMBUS_SMC_4_ASF_SCL

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SMC_PME_S4_DARK_L

MAKE_BASE=TRUE

NC_SMC_DP_HPD_L

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SMC_PN7

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SMC_S4_WAKESRC_EN

NO_TEST=TRUE

MAKE_BASE=TRUE

ISNS_P12VG3H

NC_SMBUS_SMC_5_G3H_SCL

MAKE_BASE=TRUE

NO_TEST=TRUE

VSNS_P3V3S5

MAKE_BASE=TRUE

NC_SMC_PH3

MAKE_BASE=TRUE

NO_TEST=TRUE

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.1MM

PP3V3_G3H_AVREF_SMC

MIN_LINE_WIDTH=0.4MM

MAKE_BASE=TRUE

NC_SMC_ADC16

NO_TEST=TRUE

TP_SMC_PH7

MAKE_BASE=TRUE

NO_TEST=TRUE

VSNS_P12VG3H

MAKE_BASE=TRUE

NC_SMC_ADC18

NO_TEST=TRUE

AP_PWR_EN

MAKE_BASE=TRUE

NC_SMC_PN4

NO_TEST=TRUE

NC_SMC_PN3

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SMC_PL7

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

SMC_WIFI_PWR_EN

MAKE_BASE=TRUE

SMC_ASSERT_RTCRST

MAKE_BASE=TRUE

SMC_ACDC_ID

MAKE_BASE=TRUE

SMC_OOB2_D2R_L

SMC_OOB2_R2D_L

MAKE_BASE=TRUE

ACDC_BURST_EN_L

MAKE_BASE=TRUE

CPU_TT_OC_L

CPU_THRMTRIP_3V3

PM_THRMTRIP_L_R

051-0164

12.4.0

51 OF 123

45 OF 86

8

6

9

2

5

4

7

3

1

2

1

2

1

212

1

2

132

4

2

1

2

1

12

1 2

1

2

1

2

1

2

1

2

1

2

1 2

12

1

2

1 2

1 2 1 2

1 2 1 2 1 2 1 2

1 2

12

1

2

12

6

1

2

1

2

3

4

5

1

2

12

3

2

1

12

1

2

1

2

3

1

2

3

2

1

2

3

1

2

1

1 2

1 2 1 2

1

2

1 2

21

1 2

2

1

12

2

1

1 2

2

1

1 2

1

2

3

1

2

3

5

1

4

2

45 70

12 21 36 44 68 69

44

70

32 70

45 70

44

32 44

45 70

45 70 44 45 51 70

44

45 70

70

44

12 44 46

44

32

44

44 45 51 70

42 44

44 46

44 45 51 70

44 46

44

44 81

44 45 51 70

44

44 81

44

23 24 44

45

44

70

44 81

44

44 81

32 44

44 60

44 69

28 44 69

49 81

44 48 49 81

49 81

48 81

49 81

48 81

49 81 44

48 81

45

60

33 81

45

IN

OUT

IN

OUT

BI

IN

OUT

IN

BI

IN

OUT

IN

OUT

WP*

SI

HOLD*

VSS

SCK

CE*

VDD

SO

IN

OUT

IN

OUT

IN

BI BI BI

IN

OUT

IN

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SMC SPI Support

SPI Series Termination

LPC+SPI Connector

MATT CONNECTOR

516s1039

SPI BootROM

44 45

20

14

13 44 79

19 79

44 45

45

44 45

12 20 44

13 44

46 79

12 44 45

46 79

CERM

402

1UF

C5210

6.3V

10%

OMIT_TABLE

SST25VF064C

64MBIT

CRITICAL

SOIC

U5210

1/16W

5%

3.3K

402

MF-LF

R5211

46 79

R5223

1/16W MF-LF 402

5%

24

PLACE_NEAR=J5200.11:5mm

PLACE_NEAR=J5200.9:5mm

43

402

1/16W

5% MF-LF

R5224

13 79

46 79

1/16W

15

MF-LF

5%

402

R5221

PLACE_NEAR=U1100.AJ11:12.5MM

1/16W MF-LF

402

5%

15

R5222

PLACE_NEAR=U1100.AH1:18.5MM

14 46 79

13 79

15

5%

402

MF-LF

1/16W

R5220

PLACE_NEAR=U1100.AJ7:11MM

13 79

MF-LF

1/16W

5%

402

100K

R5212

CRITICAL

LPCPLUS

M-ST-SM

DF40C-30DP-0.4V

J5200

13 44 79

46 79

14 46 79

13 44 79

PLACE_NEAR=J5200.12:10mm

43

5%

402

MF-LF

1/16W

R5225

5%

43

402

1/16W MF-LF

PLACE_NEAR=J5200.14:5mm

R5226

PLACE_NEAR=R5226.2:5mm

43

1/16W MF-LF

402

5%

R5227

402

5%

PLACE_NEAR=R5225.2:5mm

43

MF-LF

1/16W

R5228

PLACE_NEAR=R5224.2:5mm

5%

MF-LF

1/16W

402

43

R5229

PLACE_NEAR=U5210.2:5MM

R5230

1/16W

5%

24

402

MF-LF

PLACE_NEAR=U5000.L10:15MM

R5252

MF-LF

1/16W

15

402

5%

PLACE_NEAR=U5000.K10:12.7MM

R5253

MF-LF

15

1/16W

5%

402

R5251

402

PLACE_NEAR=U5000.N9:8.5MM

5%

MF-LF

43

1/16W

PLACE_NEAR=U5210.2:5MM

24

MF-LF

5%

1/16W

402

R5250

44 79

SPI and Debug Connector

SYNC_DATE=03/13/2013SYNC_MASTER=J16_TONY

SPI_CS0_R_L

SPI_CLK_R

SPI_MOSI_R

SPI_MOSI

SPI_MISO

SPI_CLK

SPI_CS0_L

SPI_SMC_MOSI

SMC_TX_L

SPI_ALT_MOSI

SPI_MLB_CLK

SPI_MLB_MOSI

SPI_MLB_CS_L

SPI_ALT_MOSI

SPI_SMC_CS_L

SPI_SMC_CLK

SPI_ALT_CS_L

SPI_ALT_MISO

SPI_ALT_CLK

SPI_ALT_MISO

=PP5V_S0_LPCPLUS

LPCPLUS_GPIO DEBUG_RESET_L

TP_SMC_MD1

LPC_AD<3>

LPC_AD<1>

SPI_ALT_CLK

PM_CLKRUN_L

SPI_ALT_CS_L

SMC_RX_L

SMC_ROMBOOT

SMC_RESET_L

SMC_TCK

SMC_TDI

LPC_PWRDWN_L

LPC_SERIRQ

SPI_MLB_MOSI

SPI_WP_L

SPIROM_USE_MLB

SPI_MLB_CS_L

SPI_MLB_CLK

=PP3V3_G3H_LPCPLUS

LPC_AD<0>

LPC_AD<2>

SPIROM_USE_MLB

SMC_TDO

SMC_TMS

LPC_CLK33M_LPCPLUS

LPC_FRAME_L

TP_SMC_TRST_L

=PP3V3_S5_ROM

SPI_SMC_MISO

SPI_MLB_MISO

051-0164

12.4.0

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2

1

4

7

8

5

1 3

2

6

1

2

1

2

1

2

1 2

1

2

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30

3

1

5

9

7

15

11 13

17 19 21 23 25 27 29

31

32

33

34

1

2

1

2

1 2

12

79

46 79

70

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

0x30 Write 0x31 Read

These are needed in addition to TCON PU

U8100

0x88 Write

PCH (SML 1)

U1100

0x59 Read

0x58 Write

Unused PCH SM Link

U1100

U5000

SMC multi-master experiment

U5000

ALS

J4200U5000

U5000

SMC (SMBus 0)

Mikey

J1800,J1850

0x94 Write 0x95 Read

Memory Channel A

LCD Temp IRemote (Dev)

J6500

0x59 Read

0x58 Write

Memory Channel B

DIMM 2:

J2500

J2300

SMC (SMBus 1)

U2200

U5650

U2201

EMC1414 (Prod):

Vref Control

XDP

0x52 Write 0x53 Read

TMP421: 0x9E Write 0x9F Read

0x1A Write 0x1B Read

U5690

0x8A Write

U5690 TMP006 (Prod):

U5600 0x98 Write

U5600

0xA1 Read

0xA0 Write

0xA5 Read

0xA4 Write

0x72 Write 0x73 Read

Slave

Master

Line Legend

U8100

0x76 Write 0x77 Read

CHS

Backlight Control

DIMM 0:

0x89 Read

Display TCon

J4400

Mux

U6551

SMC (SMBus 2)

PCH (SMBus)

SMC (SMBus 3)

BLC Control from TCon

Panel/Vendor ID:

Temp Sensors "T2"

0x9B Read

0x9A Write

U5650 EMC1428-7:

0x93 Read

0x92 Write

U5650

For J16:

For J17:

TMP423B (Dev):

U1100

0x99 Read

VRef DAC

Display TCon

0x98 Write 0x99 Read

0x8B Read

Temp Sensors "T1"

5% 1/16W

402

MF-LF

2.2K

R5361R5360

2.2K

402

MF-LF

1/16W

5%

R5365

1/16W

8.2K

5%

MF-LF 402

5%

402

MF-LF

1/16W

8.2K

R5364

2.2K

R5301

402

1/16W

5%

MF-LF

2.2K

1/16W

402

5%

MF-LF

R5300

R5311

4.7K

402

MF-LF

5% 1/16W

R5310

4.7K

402

MF-LF

5%

1/16W

5% MF-LF

1/16W 402

R5321

4.7K

5%

1/16W

402

4.7K

MF-LF

R5320

MF-LF

4.7K

402

5%

R5331

1/16W

4.7K

5%

MF-LF

402

R5330

1/16W

1/16W MF-LF

5%

402

R5391

2.2K

1/16W MF-LF

402

5%

R5390

2.2K

SMBus Connections

SYNC_MASTER=J16_TONY SYNC_DATE=03/13/2013

=SMB_SNS1_SCL

=I2C_VREFDACS_SCL

SML_PCH_1_DATA

=I2C_BKLT_SCL

=SMBUS_XDP_SDA

=PP3V3_S0_SMBUS_SMC_3

=I2C_BKLT_SDA

=SMBUS_XDP_SCL

=PP3V3_S0_DP

SMBUS_SMC_3_SCL

SMBUS_SMC_3_SDA

=I2C_CHS_SCL

=I2C_MIKEY_SCL

=I2C_PCA9557D_SCL

=I2C_CHS_SDA

=I2C_MIKEY_SDA

=I2C_PCA9557D_SDA

=I2C_SODIMMA_SDA

=I2C_SODIMMB_SDA

=PP3V3_S0_SMBUS_SMC_0

=SMB_SNS3_SDA

=SMB_SNS3_SCL

=SMB_SNS2_SDA

=SMB_SNS2_SCL

=I2C_VREFDACS_SDA

SMBUS_SMC_2_S4_SCL

SMB_DP_TCON_SLA_SDA

SMB_DP_TCON_SLA_SCL

=I2C_SODIMMB_SCL

=SMB_SNS1_SDA

=PP3V3_S0_SMBUS_SMC_1

SMBUS_SMC_1_S0_SDA SMBUS_SMC_1_S0_SCL

=I2C_SODIMMA_SCL

SML_PCH_1_CLK

=PP3V3_S0_SMBUS

=SMB_ALS_SDA

SMBUS_SMC_2_S4_SDA

=SMB_ALS_SCL

=PP3V3_S0_SMBUS

=SMB_DP_BLC_SCL

=SMB_DP_BLC_SDA

MAKE_BASE=TRUE

SMB_DP_TCON_SCL

SML_PCH_0_CLK

MAKE_BASE=TRUE

SMB_3_DATA

SML_PCH_0_DATA

MAKE_BASE=TRUE

SMB_2_S4_DATA

SMB_1_S0_CLK

MAKE_BASE=TRUE

SMB_1_S0_DATA

SMB_3_CLK

MAKE_BASE=TRUE

SMB_2_S4_CLK

MAKE_BASE=TRUE

SMB_DP_TCON_SDA

MAKE_BASE=TRUE

SMB_0_S0_DATA

SMB_0_S0_CLK

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_0_S0_SDA

=PP3V3_S4_SMBUS_SMC_2

MAKE_BASE=TRUE

SMBUS_PCH_DATA

SMBUS_PCH_CLK

MAKE_BASE=TRUE

051-0164

12.4.0

53 OF 123

47 OF 86

121

2

121

2

121

2

121

2

121

2

121

2

121

2

50

22

13

66

18

70

66

18

31 40 70

44 81

56

22

56

22

23

24

70

50

22

44 81

40

24

50

70

44 81

23

13

47 70

38

44 81

38

47 70

66

40 81

13 81

40 81

44 81

70

13 81

OUT

IN

OUT

IN-

IN+ REF

V+

GND

IN+ IN-

OUT

V+

REFIN+

IN-

OUT

GND

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_5_ITEM

REFERENCE DESIGNATOR(S)

BOM OPTION

TABLE_5_HEAD

QTY

DESCRIPTION

PART#

TABLE_5_ITEM

REFERENCE DESIGNATOR(S)

BOM OPTION

TABLE_5_HEAD

QTY

DESCRIPTION

PART#

Voltage sense and IMON amp (VC0C, IC0C)

353S2208

Airport supply current sense

Range: 0-1.65A

Gain: 200 V/V

353S3597

VMax = 0.9V

Gain: 100 V/V

I/V-sense for PP1V05_S0_PCH

353S2073

CPU Core (VC0C:ADC10/IC0C:ADC11)

Range: 0-16.5A

Place R5476 over PP1V05_S0 power plane shape.

PP1V05_S0_PCH (VN1R:ADC17)

I/V-sense for HDD (Development, but need R5420)

HDD S0 (VH05:ADC14/IH05:ADC15)

NOTE:VSNS on S5 to avoid burning G3H Power

12V G3H (VD2R:ADC0/ID2R:ADC1)

PP3V3_S4_AP (IW0R:ADC19)

AC/DC lowside sense (System total)

Gain: 200 V/V

Range: 0-3.3A

45 81

C5402

U5000.E2:10mm

20%

0.22UF

0201

6.3V X5R

45 81

20%

0.22UF

U5000.E1:10mm

C5405

0201

6.3V X5R

402

MF-LF

1/16W

1%

18.2K

R5401

70

U5000.E1:10mm

4.53K

1%

402

1/16W MF-LF

R5405

C5400

20%

0.22UF

0201

6.3V X5R

TFT

R5400

0.002

1% 1W

CRITICAL

0612

U5000.E2:10mm

6.04K

1/16W MF-LF

R5402

1%

402

SC70-5

OPA348

U5460

CRITICAL

SIGNAL_MODEL=

C5460

16V

20%

0.01UF

0402

X7R-CERM

402

2.0K

R5464

MF-LF

1%

1/16W

R5462

1/16W

1%

10K

402

MF-LF

C7050.1:10mm

R5465

MF-LF

5.1K

402

1/16W

5%

U5000.A6:10mm

C5465

0.22UF

20%

0201

6.3V X5R

R5463

1/16W MF-LF 402

1%

10K

45 81

61 83

45 81

U5000.B6:10mm

C5461

20%

0.22UF

0201

6.3V X5R

1%

R5461

MF-LF

402

4.53K

1/16W

45 81

0201

0.22UF

20%

C5422

OMIT_TABLE

U5000.B1:10mm

6.3V X5R

1/16W 402

R5422

6.04K

MF-LF

1%

HDD_IVSNS:Y

1/16W

1%

MF-LF

402

HDD_IVSNS:Y

R5425

4.53K

4.02K

1/16W MF-LF

HDD_IVSNS:Y

R5421

402

1%

70

0201

20%

OMIT_TABLE

0.22UF

U5000.B2:10mm

C5425

6.3V X5R

0.010

0805-2

MF

1%

1/4W

R5420

CRITICAL

HDD_IVSNS:Y

CDZ3.0B

SM

DZ5420

SC70

CRITICAL

U5400

INA214

INA216A4YFFX

U5420

WCSP-4

CRITICAL

HDD_IVSNS:Y

AP_ISNS:Y

U5430

INA210

SC70

CRITICAL

45 81

0.22UF

20%

0201

C5435

OMIT_TABLE

U5000.H2:10mm

6.3V X5R

AP_ISNS:Y

MF

1/20W

R5435

4.53K

1%

201

70

0201

0.22UF

20%

C5430

AP_ISNS:Y

6.3V X5R

1206-1

1/2W

0.010

MF

CRITICAL

R5430

1%

45 81

C1760.1:15mm

R5476

MF

1/20W

1%

4.53K

201

U5000.G1:10mm

20%

0201

0.22UF

C5476

6.3V X5R

R5406

5%

20K

1/20W MF 201

AP_ISNS:Y

R5436

5%

20K

1/20W MF 201

RES,0 ohm,201

AP_ISNS:N

C5435

1

117S0002

AP_ISNS:Y

C5435

1

CAP,0.22uF,201

132S0304

C5422,C5425

2

HDD_IVSNS:Y

CAP,0.22UF,201

C5422,C5425

2

HDD_IVSNS:N

RES,0 OHM,201

117S0002

SYNC_MASTER=J16_TONY SYNC_DATE=03/13/2013

I and V Sense

ISNS_P12VG3H

GND_SMC_AVSS

ISNS_HDDS0

SNS_HDD_N

SNS_HDD_P

SNS_P12VG3H_P

ISNS_P3V3S4_AP_R

=PP3V3_S0_SENSE

ISNS_P12VG3H_R

GND_SMC_AVSS

ISNS_P3V3S4_AP

ISNS_CPUVCC_FB_R

ISNS_CPUVCC_FB

GND_SMC_AVSS

=PPCPUVCC_S0_CPU

PP3V3_S4_SNS

SNS_P3V3S4_AP_P

=PP5V_S0_ISENSE

ISNS_CPUVCC

=PP3V3_S5_SENSE

VSNS_P12VG3H

=PP1V05_S0_SNS

REG_CPUVCC_IMON_R

REG_CPUVCC_IMON

VSNS_HDDS0

SNS_P12VG3H_N

PP12V_G3H_SNS

=PP12V_G3H_SNS_R

GND_SMC_AVSS

=PP12V_S5_SNS

GND_SMC_AVSS

PPHDD_S0_SNS

GND_SMC_AVSS

VSNS_CPUVCC

=PP3V3_S4_SNS_R

=PPHDD_S0_SNS_R

ISNS_HDDS0_R

VSNS_P1V05S0_PCH

SNS_P3V3S4_AP_N

051-0164

12.4.0

54 OF 123

48 OF 86

2

1

2

1

1 2

2

1

43

21

1

2

4

1

3

5

2

1

1 2

2

1

2

1

1 2

2

1

2

1 2

2

1

43

21

A

K

6

5

4 1

3

2

B2

B1

A1

A2

2

3

14

5

6

2

1

1 2

2

1

43

21

1 2

2

1

2

1

2

44 45 48 49 81

81

34 49 50 70

81

44 45 48 49 81

81

44 45 48 49 81

61 70

81

70

81

70

44 45 48 49 81

70

44 45 48 49 81

70

81

OUT

V+

REFIN+

IN-

OUT

GND

OUT

GND

IN+ IN-

OUT

V+

REFIN+

IN-

OUT

GND

OUT

TABLE_5_ITEM

REFERENCE DESIGNATOR(S)

BOM OPTION

TABLE_5_HEAD

QTY

DESCRIPTION

PART#

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Range: 0-8.25A

Gain: 200 V/V

353S2216

Range: 0-13.2A

353S2216

353S3597

Gain: 500 V/V

VDDQ lowside sense for SO-DIMM modules

Range: 0-2.5A

PPVDDQ_S0 (VC0M:ADC4/IC0M:ADC5)

lowside sense for CPU mem rail (2.5A max draw, 3.3A max sense capability)

SSD S0 (IH1R:ADC20/VR3R:ADC21)

I-sense for SSD / V-sense for PP3V3_S5)

VDDQ S3 (VM0R:ADC6/IM0R:ADC7)

45 81

X5R

6.3V

20%

U5000.B4:10mm

C5541

0.22UF

0201

45 81

X5R

6.3V

U5000.A4:10mm

0.22UF

C5545

20%

0201

201

MF

4.53K

R5545

1%

1/20W

70

201

1/20W

1%

4.53K

R5541

MF

X5R

6.3V

C5540

0.22UF

0201

20%

U5540

CRITICAL

INA211

SC70

1%

MF

1W

0612

R5540

CRITICAL

0.0005

45 81

201

1/20W

MF

1%

4.53K

R5525

SSD:Y

70

X5R

6.3V

20%

OMIT_TABLE

0201

0.22UF

C5525

U5000.B7:12.7mm

0612

TFT

SSD:Y

R5520

1W

1%

0.002

CRITICAL

WCSP-4

INA216A4YFFX

U5520

SSD:Y

INA211

CRITICAL

SC70

U5530

45 81

201

1/20W

MF

4.53K

R5531

1%

X5R

6.3V

U5000.B3:12.7mm

20%

0.22UF

C5531

0201

X5R

6.3V

20%

C5535

U5000.A3:10mm

0.22UF

0201

201

1/20W

1%

R5535

MF

4.53K

70

1W

1%

0612

R5530

CRITICAL

0.002

TFT

X5R

6.3V

0.22UF

C5530

20%

0201

45 81

201

U5000.A7:10mm

MF

1%

4.53K

1/20W

R5526

SSD:Y

X5R

6.3V

20%

0.22UF

C5526

U5000.A7:10mm

0201

OMIT_TABLE

201

MF

1/20W

5%

20K

R5546

I and V Sense(Continued)

SYNC_MASTER=J16_TONY SYNC_DATE=03/13/2013

SSD:Y

C5525,C5526

CAP,0.22UF,201

2

132S0304

SSD:N

2

RES,0 OHM,201

C5525,C5526

117S0002

ISNS_PVDDQS0_R

PPVDDQ_S3_SNS_DDR

ISNS_VDDQS3_DDR_R

=PP3V3_S0_SENSE

PPVDDQ_S0_SNS

GND_SMC_AVSS

SNS_VDDQS3_DDR_N

SNS_PVDDQS0_P

SNS_PVDDQS0_N

VSNS_VDDQS3_DDR

=PP3V3_S5_SNS

PPSSD_S0_SNS

SNS_SSD_N

GND_SMC_AVSS

ISNS_VDDQS3_DDR

GND_SMC_AVSS

=PPSSD_S0_SNS_R

GND_SMC_AVSS

VSNS_P3V3S5

=PPVDDQ_S3_SNS_DDR_R

SNS_VDDQS3_DDR_P

ISNS_SSDS0_R

ISNS_SSDS0

SNS_SSD_P

VSNS_PVDDQS0

ISNS_PVDDQS0

=PPVDDQ_S0_SNS_R

051-0164

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2

1

2

1

1 2

2

1

2

3

14

5

6

43

21

1 2

2

1

4 3

2 1

B2

B1

A1

A2

2

3

14

5

6

1 2

2

1

2

1

1 2

43

21

2

1

1 2

2

1

2

81

34 48 49 50 70

44 45 48 49 81

81

70

81

44 45 48 49 81

70

44 45 48 49 81

70

81

70

IN IN

GND

V+

SCL SDA

DXP1 DXP2 DXP3 DXN

IN

BI

NC

ALERT*

THERM*/ADDR

DP1

SMCLK

SMDATA

VDD

DN1

DP2/DN3

DN2/DP3

GND

BI

IN

AGNDDGND

SCL

SDA

ADR0 ADR1

DRDY*

V+

IN

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

REFERENCE DESIGNATOR(S)

BOM OPTION

TABLE_5_HEAD

QTY

DESCRIPTION

PART#

TABLE_ALT_ITEM

TABLE_5_ITEM

MLB Proximity

Temperature Sensor T2

MLB Proximity

MLB Prox 2 (Tm2p)

0x99 (Read)

0x98 (Write)

MLB Prox 1 (Tm1p)

0x9B (Read)

AC/DC

SO-DIMM Proximity

Added to board BOM (DEV only) to clean up PD BOM

Temperature Sensor T1

CPU Prox

BLC Proximity

Place U5600 at the coolest location

Internal sensor of the EMC 1414

NOTE - Follow TI layout guide(SBOU108.pdf) for this part!!!

on the MLB.

Note:

0x9A (Write)

CPU Proximity

AC/DC

Diode on supply

will be used as the ambient sensor.

I2C Address (TMP432B):

I2C Address (EMC1414-1):

SO-DIMM

0x8B (Read)

0x8A (Write)

Filter Caps: Stuff if needed for PSU sensor SI

BLC Prox

I2C Address (TMP006):

This PD part is a rubber bumper to protect TMP006

Temperature Sensor T3: LCD Remote Sensor(Dev Only)

201

+/-0.1PF NP0

25V

Q5610.3:2MM

C5610

2.2PF

402-1

10% 10V X5R

1UF

C5600

402

50V CERM

10%

C5614

L5614.2:2MM

0.0022UF

FERR-220-OHM

0402

L5614

0402

L5615

FERR-220-OHM

60 81

1UF

10%

402-1

10V X5R

C5650

U5650.4:2MM

XW5651

NO_XNET_CONNECTION=TRUE

SM

OMIT

U5650

CRITICAL

TMP423

SOT23-8

U5650.4:2MM

SM

XW5652

NO_XNET_CONNECTION=TRUE

OMIT

U5650.4:2MM

NO_XNET_CONNECTION=TRUE

OMIT

XW5653

SM

201

+/-0.1PF NP0

25V

NO_XNET_CONNECTION=TRUE Q5660.3:2MM

C5660

2.2PF

201

+/-0.1PF NP0

25V

C5664

NO_XNET_CONNECTION=TRUE

2.2PF

Q5664.3:2MM

402

MF-LF

1/16W

5%

10K

R5600

47

TEMPSNSDEV NO_XNET_CONNECTION=TRUE

C5662

CERM

10%

0.0022UF

Q5665.3:2MM

50V 402

201

+/-0.1PF NP0

25V

Q5612.3:2MM

C5612

2.2PF

CRITICAL

MSOP

EMC1414-1-AIZL

U5600

47

U5690

TMP0006AIYZER

TEMPSNSDEV

WCSP

CRITICAL

0402

X7R-CERM

10%

0.01UF

16V

TEMPSNSDEV

C5690

47

402

1/16W

10K

R5690

TEMPSNSDEV

MF-LF

5%

402

50V

U5600.5:2MM

NOSTUFF

C5605

5%

47PF

CERM

402

50V

C5604

U5600.4:2MM

NOSTUFF

5%

47PF

CERM

PLACEMENT_NOTE=Place Q5612 between CPU socket and CPU Power supply components

CRITICAL

DFN1006H4-3

BC846BLP

Q5612

BC846BLP

CRITICAL

Q5610

DFN1006H4-3

PLACEMENT_NOTE=Place Q6010 near CPU

PLACEMENT_NOTE=Place Q5660 near SO-DIMM connectors

BC846BLP

Q5660

CRITICAL

DFN1006H4-3

BC846BLP

CRITICAL

Q5664

DFN1006H4-3

PLACEMENT_NOTE=Place Q5554 near BLC controller

PLACEMENT_NOTE=PLACE Q565 SOUTH OF SO-DIMM CONNECTORS NEAR DDR VR

Q5665

BC846BLP

CRITICAL

DFN1006H4-3

BUMPER,U5690,D7

BUMPER_U5690

TEMPSNSDEV875-6433

1

372S0186 372S0185

Alternate Temp Diode

ALL

SYNC_DATE=01/11/2013

Temperature Sensors

SYNC_MASTER=J16_FIYIN

SNS_T1_2_N

SNS_T1_2_P

=PP3V3_S0_SENSE

=SMB_SNS3_SDA

=SMB_SNS3_SCL

SNS_T1_3_N

TMP006_DRDY

SNS1_ALERT_L

=PP3V3_S0_SENSE

=SMB_SNS1_SDA

=SMB_SNS2_SDA

SNS_T1_3_P

SNS_T2_1_N

SNS_ACDC_P

=SMB_SNS1_SCL

SNS_T2_3_N

SNS_ACDC_N

SNS_T2_2_N

SNS_T2_2_P

SNS_T2_3_P

SNS_T1_1_N

=SMB_SNS2_SCL

=PP3V3_S0_SENSE

SNS_T2_2_N

SNS_T2_DXN

SNS_T2_2_P

SNS_T1_1_N

SNS_T1_1_P

SNS_T1_3_P

MAKE_BASE=TRUE

SNS_T1_2_P

MAKE_BASE=TRUE

SNS_T1_2_N

SNS_T1_3_N

SNS_T2_1_N

SNS_T2_3_N

SNS_T2_1_P

SNS_T2_3_P

SNS_T2_1_P

SNS_T1_1_P

051-0164

12.4.0

56 OF 123

50 OF 86

2

1

2

1

2

1

21

2

1

1 2

5

8

7 6

1 2 3 4

1 2

2

1

2

1

2

1

2

1

8

72

10

9

1

3

4

5

6

A2

A1

B3

C3 C1

B1

C2

A3

2

1

2

1

2

1

3

2

1

3

2

1

3

2

1

3

2

1

3

2

1

50 81

34 48 49 50 70

50 81

34 48 49 50 70

50 81

34 48 49 50 70

50 81

IN

OUT

D

GS

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SEE RADAR:12960082 J16/J17 CONNECT GATE OF FAN PWM FET TO PP3V42_G3H

See RADAR: 10565825- D7: Need scematic and PCB file of fan(All Vendors).

there is a pull-up, going to a Hi-Z

definition, the drain of Q6010 is

Add C6020 1000pF Cap, Change R6020 to 47K -- Radar 11661918 D8 Proto1 Fan Tach instability.

at common and the SMC sinks current

present on the SMC pin! Then by

turns on, there would be 5V/12V

12V DC

Tach GND

when Q6010 is on.

It is assumed there is a pull-up to 5V/12V inside the fan, otherwise when the SMC PWM goes low and Q6010

the fan acts as a non-inverting

This resembles an open-drain if

level-shifter to protect the SMC.

The circuit for the PWM input to

FET input.

Note:

518S0730

SMC Fan 1 (Unused)

SMC Fan 0 (System)

Otherwise, this is simply a pass-FET.

L6000

CRITICAL

0603

220-OHM-1.4A

C6001

0.01UF

16V

20% X7R-CERM

0402

C6000

16V

20%

4.7UF

X7R-CERM 1206

44 81

J6000

M-RT-SM

53780-8604

CRITICAL

44

L6021

CRITICAL

FERR-220-OHM

0402

L6010

FERR-220-OHM

0402

CRITICAL

C6021

5%

100PF

CERM

50V 0402

C6010

CERM

50V

5%

0402

100PF

R6026

5% 1/16W

47K

MF-LF 402

44 81

R6010

402

10K

5% 1/16W MF-LF

Q6010

VESM

CRITICAL

SSM3K15AMFVAPE

D6020

BAS316DG

SOD323-SM

R6020

402

47K

1/16W MF-LF

5%

C6020

PLACE_NEAR=U5000.L13:5MM

0201

X7R-CERM

10% 16V

1000PF

SYNC_DATE=01/07/2013

System Fan

SYNC_MASTER=J16_JERRY

=PP12V_S0_FAN

VOLTAGE=12V MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM

PP12V_S0_FAN_0_FILT

FAN_0_TACH_FILT

SMC_FAN_1_TACH

SMC_FAN_1_CTL

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SMC_FAN_1_TACH

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SMC_FAN_1_CTL

FAN_0_PWM_FET

MIN_NECK_WIDTH=0.25MM

FAN_0_PWM_FILT

MIN_LINE_WIDTH=0.5MM

SMC_FAN_0_CTL

=PP3V3_S0_FAN

FAN_0_TACH_FET

SMC_FAN_0_TACH

=PP3V3_G3H_SMC

=PP3V3_S0_FAN

=PP3V3_G3H_SMC

051-0164

12.4.0

60 OF 123

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21

2

1

2

1

5

1 2

4

6

3

21

2

1

2

1

2

1

2

1

2

3

A

K

1 2

2

1

70

51 70 44 45 51 70

51 70

44 45 51 70

OUT

/SPDIF_OUT2

VL_HD

SENSE_A

GPIO1/DMIC_SDA2

GPIO0/DMIC_SDA1

VHP_FILT+

GPIO2

RESET*

LINEOUT_L1-

VBIAS_DAC

FLYP

VA_REF

VD

GPIO3

VHP_FILT-

LINEOUT_R1-

LINEOUT_R1+

LINEOUT_R2-

SPDIF_OUT

LINEIN_C-

FLYC FLYN

SPDIF_IN

LINEOUT_L1+

THRM_PAD

VA_HP

HPOUT_R

HPREF

VCOM

AGND

VA

LINEIN_R+

LINEIN_L+

MICIN_L+ MICIN_L-

MICBIAS

SYNC

DGND

DMIC_SCL

HPOUT_L

SDI SDO

VL_IF

BITCLK

MICIN_R-

MICIN_R+

VREF+_ADC

LINEOUT_L2+ LINEOUT_L2LINEOUT_R2+

OUT

IN

OUT

NC NC

OUT

G

D

S

P-CHN

D

S

G

N-CHN

G

D

S

P-CHN

NC NC

D

S

G

N-CHN

IN

OUT

IN

OUT

NR/FB

NC

IN

EN

GND

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

NC

PLACE C6100 AS CLOSE TO PIN 9 AS POSSIBLE

NC

MAC SPKR AMP CNTRL

HP AMP CNTRL

RESERVE SPACE FOR POSSIBLE LATCH CIRCUIT

HP AMP/LINE OUT

WOOFERS

NC

WIN SPKR AMP CNTRL

DMICS 1 & 2

NC

TWEETERS

DMICS SHOULD HAVE OWN GND ON CONNECTOR SHARED WITH CAMERA

APPLE P/N 353S2456

PLACE XW6110 BENEATH U6101, BETWEEN PINS 2 & 5

4.5V POWER SUPPLY FOR CODEC

SE FSINPUT= 1.22VRMS DAC1 FSOUTPUT= 1.34VRMS DAC2/3 FSOUTPUTDIFF= 2.67VRMS DAC2/3 FSOUTPUTSE= 1.34VRMS

DIFF FSINPUT= 2.45VRMS

VD MUST BE LESS THAN OR EQUAL TO VL_HD

APPLE P/N 353S2592

AUDIO CODEC

NC NC

NC

PLACE TP FOR ALL HDA SIGNALS NEAR CODEC

56 79

52 54

U6101

CS4206B

QFN

CRITICAL

C6101

4V

20%

X5R-1

402

4.7UF

53

38

52 54

38

D6100

BAT54XV2T1

SOD-523

XW6110

SM

R6171

MF-LF

1/16W 402

0

5%

DEVEL_AUDIO

C6107

20%

10UF

0402-1

X5R-CERM

10V

CRITICAL

XW6100

SM

38

Q6170

SOT563

CRITICAL

DMC2400UV

DEVEL_AUDIO

R6170

0

402

MF-LF

1/16W

5%

DEVEL_AUDIO

Q6170

DEVEL_AUDIO CRITICAL

SOT563

DMC2400UV

DEVEL_AUDIO

Q6171

DMC2400UV

CRITICAL

SOT563

R6172

DEVEL_AUDIO

5% 1/16W MF-LF 402

0

R6173

DEVEL_AUDIO

5%

0

402

1/16W MF-LF

R6102

1/16W

5%

22

402

MF-LF

Q6171

DEVEL_AUDIO CRITICAL

DMC2400UV

SOT563

C6123

16V

X7R-CERM

0402

0.1UF

10%

C6100

0402

0.47UF

10V X5R

10%

C6102

0.47UF

0402

10V X5R

10%

C6104

0.47UF

0402

10V X5R

10%

C6106

0.47UF

0402

10V X5R

10%

0.47UF

X5R

10%

C6115

10V 0402

R6106

1/16W

1%

100K

402

MF-LF

R6111

402

1%

100K

1/16W MF-LF

R6101

22

1/16W

402

MF-LF

5%

R6107

100K

1% 1/16W MF-LF

402

MF-LF

R6108

402

100K

1/16W

1%

R6109

402

100K

1/16W

1%

MF-LF

1/16W

R6110

402

100K

MF-LF

1%

R6104

402

5%

1/16W

0

MF-LF

R6103

100K

402

MF-LF

1/16W

1%

C6111

402-LF

2.2UF

20% CERM

6.3V

11 79

C6112

402-LF

2.2UF

CERM

20%

6.3V

52 56 58

R6100

2.67K

1/16W

1% MF-LF

402

C6109

402-LF

CERM

2.2UF

20%

6.3V

C6110

402-LF

2.2UF

CERM

20%

6.3V

C6108

POLY-TANT

CASE-B2-SM

16V

20%

10UF

CRITICAL

CASE-P3-HF

TANT

20V

10%

1UF

C6113

11 79

C6114

CASE-B2-SM

10UF

POLY-TANT

20%

CRITICAL

16V

56 59

40 85

55 59

54 59

53 55 59

53 54 59

C6103

POLY-TANT

16V

20%

10UF

CASE-B2-SM

11 79

C6105

1UF

402-1

10V X5R

10%

53 54 59

R6105

402

MF-LF

0

1/16W

5%

11 79

52 56 58

38 52 54 55 58 70

52 53

38 52 54 55 58 70

59 70

11 79

MF-LF

0

1/16W

5%

402

R6120

XW6111

SM

C6122

1UF

10V

402-1

X5R

10%

VR6101

CRITICAL

SON

TPS71745

L6110

0402

FERR-220-OHM

L6111

0402

FERR-220-OHM

C6124

402-1

1UF

10V X5R

10%

58 59

52 53

52 56 58

54

AUDIO: CODEC/REGULATORS

SYNC_DATE=03/07/2013SYNC_MASTER=J16_DIRK

AUD_GPIO_2

TP_DMIC_SDA2

AUD_DMIC_SDA1

AUD_SENSE_A

AUD_GPIO_3

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM

CS4206_VREF_ADC

AUD_CODEC_MICBIAS

AUD_MIC_INL_N AUD_MIC_INP_R

NO_TEST=TRUE

AUD_MIC_INN_R

NO_TEST=TRUE

DP_INT_SPDIF_AUDIO

HDA_RST_L

HDA_BIT_CLK HDA_SYNC

CS4206_FN

AUD_SPDIF_CHIP

NO_TEST=TRUE

AUD_LI_P_R

=PP1V5_S0_AUD_DIG

VBIAS_DAC

=PP3V3_S0_AUDIO

AUD_MIC_INL_P

CS4206_FLYC

CS4206_FLYP

AUD_SDI_R

HDA_SDOUT

CS4206_FLYN

AUD_LO2_L_N

AUD_LO2_L_P

AUD_LO2_R_N

AUD_LO2_R_P

GND_AUDIO_CODEC

HDA_SDIN0

MIN_LINE_WIDTH=0.1MM MIN_NECK_WIDTH=0.1MM

TP_AUD_HP_L

PP5V_AUDIO_HPAMP

AUD_LO1_L_N

GND_AUDIO_CODEC

PP4V5_AUDIO_ANALOG

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.4MM

4V5_NR

VOLTAGE=0V

MIN_LINE_WIDTH=0.5MM

GND_AUDIO_CODEC

MIN_NECK_WIDTH=0.2MM

VOLTAGE=4.5V

PP4V5_AUDIO_ANALOG

MIN_LINE_WIDTH=0.40MM MIN_NECK_WIDTH=0.15MM

Q6170_P_S

Q6170_P_G

Q6170_N_G

Q6170_N_S

Q6171_N_S

Q6171_N_G

Q6171_P_G

Q6171_P_S

4V5_REG_EN

MIN_LINE_WIDTH=0.40MM MIN_NECK_WIDTH=0.20MM VOLTAGE=4.5V

PP5V_AUDIO_HPAMP

MIN_NECK_WIDTH=0.20MM VOLTAGE=4.5V

MIN_LINE_WIDTH=0.40MM

4V5_REG_IN

MIN_NECK_WIDTH=0.15MM

GND_AUDIO_DMIC

MIN_LINE_WIDTH=0.20MM VOLTAGE=0V

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.2MM VOLTAGE=0V

GND_AUDIO_HPAMP

=PP5V_S0_AUDIO

AUD_SPDIF_OUT

=PP3V3_S0_AUDIO

AUD_LO1_R_P

PP4V5_AUDIO_ANALOG

AUD_LO1_L_P

AUD_LO1_R_N

MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM

CS4206_HPREF

MIN_LINE_WIDTH=0.1MM MIN_NECK_WIDTH=0.1MM

TP_AUD_HP_R

GND_AUDIO_CODEC

CS4206_FP

AUD_CODEC_MICBIAS

MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.20MM

CS4206_VCOM

GND_AUDIO_CODEC

AUD_DMIC_CLK

CS4206_DMIC_SCL

AUD_LI_COM

NO_TEST=TRUE

AUD_LI_P_L

NO_TEST=TRUE

051-0164

12.4.0

61 OF 123

52 OF 86

3

13

12

2

44

14

11

34

29

45

24

9

15

41

37

36

33

48

22

43 42

47

35

49

46

40

39

28

26

25

23

21

18 17

16

10

7

4

38

8 5

1

6

20

19

27

31 30 32

2

1

A K

2

1

2

1

2

1

3 4

5

1

2

1

2

6

3 4

5

1

2

1

2

1 2

1

2

6

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1 2

1

2

1

2

1

2

1

2

1 2

1

2

212

1

2

212

1

2

1

2

1

2

1

2

1

2

1 2

2

1

2

1

3

5

2

6

4

21

2

1

79

70

79

52 56 58 59

53

52 56 58 59

PGND

SGND

PVSS

THM_PAD

PVDD

SVDD

BIAS

OUTL

OUTR

C1P C1N

SVDD2 INLINL+

INR-

INR+

SHDN*

IN

IN IN

OUT

IN

G

D

S

G

D

S

D

SG

D

SG

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

NC

R & L CHANNELS SWAPPED TO MAKE LAYOUT MORE LOGICAL

NC

R & L CHANNELS SWAPPED TO MAKE LAYOUT MORE LOGICAL

C6252

10V

10%

1UF

X5R

402-1

C6256

1UF

X5R

10% 10V

402-1

TQFN

MAX97220AETE

U6250

CRITICAL

52 55 59

52 54 59

53 59

53 56

53 59

53 56

C6253

402-1

10% 10V

1UF

X5R

C6261

TANT

CASE-A

33UF

CRITICAL

20%

6.3V

C6263

33UF

CASE-A

CRITICAL

TANT

20%

6.3V

C6273

TANT

33UF

CASE-A

20%

CRITICAL

6.3V

C6271

6.3V TANT

CASE-A

33UF

CRITICAL

20%

402

1/16W

5%

33

MF-LF

R6252

33

402

MF-LF

1/16W

5%

R6251

C6251

10UF

20% 10V X5R-CERM 0402-1

0402

FERR-220-OHM

L6250

R6250

201

1/20W

MF

5%

100K

52

R6253

402

MF-LF

5%

2.0K

1/16W

R6254

1/16W

2.0K

402

MF-LF

5%

402

0

R6255

MF-LF

1/16W

R6256

1/16W MF-LF

5%

0

402

NOSTUFF

R6262

NO_XNET_CONNECTION=TRUE

201

MF

19.6K

1%

1/20W

R6264

19.6K

MF

1%

201

NO_XNET_CONNECTION=TRUE

1/20W

R6274

MF

19.6K

1%

1/20W

201

NO_XNET_CONNECTION=TRUE

1/20W

NO_XNET_CONNECTION=TRUE

201

MF

1%

19.6K

R6272

C6262

5%

50V CERM 0402

100PF

NO_XNET_CONNECTION=TRUE

C6264

5% 50V CERM 0402

100PF

NO_XNET_CONNECTION=TRUE

C6274

CERM

50V

5%

0402

C6272

100PF

CERM

50V

5%

0402

NO_XNET_CONNECTION=TRUE

C6250

10%

0.1UF

0402

X7R-CERM

16V

10%

0.1UF

0402

X7R-CERM

16V

C6257

X7R-CERM 0402

10%

0.1UF

16V

C6258

C6254

25V

20%

0402-1

X5R-CERM

2.2UF

C6255

2.2UF

20% X5R-CERM

25V 0402-1

R6261

MF

1/20W

201

26.1K

1%

R6263

MF

1/20W

201

26.1K

1%

R6273

1%

201

1/20W

MF

26.1K

R6271

1%

26.1K

201

1/20W

MF

52 53

CRITICAL

Q6250

DMN2015UFDE

UDFN

CRITICAL

Q6251

DMN2015UFDE

UDFN

SSM6N15AFE

Q6252

SOT563

R6258

100K

5% MF

1/20W

201

SSM6N15AFE

Q6252

SOT563

1/20W

MF

5%

R6257

201

100K

1/20W

MF

5%

100K

R6259

201

AUDIO: HEADPHONE AMP

SYNC_DATE=03/07/2013SYNC_MASTER=J16_DIRK

MAX97220_OUTR_ZOBEL

GND_AUDIO_HPAMP

MAX97220_INL_N

MUTE_SWITCH

GND_AUDIO_HPAMP

MAX97220_INL_N

MUTE_CONTROL

MAX97220_PVSS

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.5MM

MIN_NECK_WIDTH=0.2MM

MAX97220_OUTR

MIN_LINE_WIDTH=0.4MM

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM

MAX97220_BIAS

MAX97220_SHDN_L

PP5V_AUDIO_HPAMP

AUD_GPIO_2

MAX97220_INR_P

AUD_LO1_R_C_P

MAX97220_INL_P

AUD_HP_PORT_REF

MAX97220_INL_P

MAX97220_C1N

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.4MM

MAX97220_OUTL_ZOBEL

MAX97220_C1P

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM

MAX97220_OUTL

AUD_LO1_L_P

MAX97220_INR_P

AUD_LO1_R_N

AUD_LO1_R_P

AUD_LO1_L_N

GND_AUDIO_HPAMP

MAX97220_INR_N

AUD_LO1_R_C_N

AUD_LO1_L_C_P

AUD_LO1_L_C_N

GND_AUDIO_HPAMP

MAX97220_OUTR

MAX97220_INR_N

PP5V_AUDIO_HPAMP

MIN_NECK_WIDTH=0.2MM

MAX97220_OUTL

MIN_LINE_WIDTH=0.4MM

051-0164

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1 2

1

2

1

2

1

21

1

2

121

2

1 2

1

2

1 2

1

2

1

2

1 2

2

1

2

1

1 2

2

1

2

1

2

1

2

1

2

1

1 2

3

1

47

3

1

4 7

6

1

2

1

2

3

4

5

1

2

1

2

52 53

53

59

56

52 53

59

52 53

IN

OUT

REGEN

VREG/AVDD

PGND

THRM_PAD

PVDD

THERM

NC

AGND

EDGEINL-

INR+

GAIN

INL+

BOOTL-

INR-

MONO

OUTR-

OUTL+

BOOTR+

OUTL-

SDNR*

OUTR+

BOOTR-

BOOTL+

TEST

SDNL*

IN

OUT

NC NC

SYM_VER-2

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

FC_HPF, WOOFERS = ~4 HZ (1.0 UF)

MAKE LAYOUT MORE LOGICAL

OUTPUT POLARITY FLIP TO

OUTPUT POLARITY FLIP TO MAKE LAYOUT MORE LOGICAL

PINS 14 & 15 ARE TEST PINS AND

LEFT CH SPEAKER AMP

APPLE P/N 353S3163

SPEAKER AMP GAIN = +9 DB SPEAKER AMP RIN = 40K NOMINAL FC_HPF, TWEETERS = ~847 HZ (4700 PF)

SHOULD BE TIED TO GND

NC

+9 DB NOSTUFF 0 OHM

GAIN R6306 R6307 +12 DB NOSTUFF 47 KOHM

+15 DB NOSTUFF NOSTUFF +18 DB 47 KOHM NOSTUFF +24 DB 0 OHM NOSTUFF

INPUT POLARITY FLIP OK -- TRUE DIFF INPUTS

EDGE RATE

OFF NOSTUFF 0 OHM

ON 0 OHM NOSTUFF

CONTROL R6304 R6305

AUD_RAMP_MONO NET: HIGH = MONO OPERATION LOW = STEREO OPERATION

WOOFERS & TWEETERS ON UNDER MAC OS

ONLY WOOFERS ON UNDER WINDOWS

X5R-CERM

2.2UF

10V

20%

C6317

402

54 55

52 53 59

55 70

0402

FERR-1000-OHM

L6303

52 59

X5R

10%

805

10UF

C6300

25V

10%

805

X5R

10UF

C6301

25V

0.22UF

603

20% X5R

C6316

25V

20%

0.22UF

603

X5R

C6315

25V

0.22UF

20%

603

X5R

C6314

25V

603

0.22UF

20% X5R

C6313

25V

CRITICAL

NO_XNET_CONNECTION=TRUE

C6319

25V CERM 0402

1000PF

5%

52 59

NO_XNET_CONNECTION=TRUE

CRITICAL

C6320

25V CERM 0402

1000PF

5%

NO_XNET_CONNECTION=TRUE

CRITICAL

C6321

25V CERM 0402

1000PF

5%

NO_XNET_CONNECTION=TRUE

CRITICAL

C6322

25V CERM 0402

1000PF

5%

X5R

10%

0.1UF

C6302

25V 402

603-1

1UF

10% X5R

C6303

25V

0.1UF

X5R

10%

C6304

25V 402

52 53 59

57 59

603-1

10%

1UF

X5R

C6305

25V

SSM3302

CRITICAL

LFCSP

U6300

MF-LF

1/16W

0

NOSTUFF

R6305

402

5%

MF-LF

0

1/16W

R6304

402

5%

0402

FERR-1000-OHM

L6301

1/16W

0

MF-LF

R6303

402

5%

MF-LF

1/16W

0

NOSTUFF

R6306

402

5%

52

1/16W MF-LF

0

R6308

402

5%

0402

FERR-1000-OHM

L6300

52

100K

1/16W MF-LF

R6309

402

5%

54 55

1/16W

100K

MF-LF

R6301

402

5%

54 55

NO_XNET_CONNECTION=TRUE CRITICAL

C6323

25V CERM 0402

1000PF

5%

FERR-1000-OHM

0402

L6302

NO_XNET_CONNECTION=TRUE CRITICAL

C6324

25V CERM 0402

1000PF

5%

20%

470UF

SM

POLY

16V

CRITICAL

C6306

FERR-1000-OHM

0402

L6308

110-OHM-3A

DLY5ATN111SQ2

CRITICAL

NO_XNET_CONNECTION=TRUE

L6305

NO_XNET_CONNECTION=TRUE

DLY5ATN111SQ2

110-OHM-3A

CRITICAL

L6307

47K

1/16W MF-LF

R6307

402

5%

4700PF

50V

0805

NPO-C0G-CERM

C6308

5%

0805

NPO-C0G-CERM

50V

4700PF

C6309

5%

X5R

1UF

10%

0402

C6310

25V

1UF

X5R

10%

0402

C6311

25V

0402

100PF

CERM

50V

NOSTUFF

C6312

5%

NOSTUFF

0402

100PF

CERM

50V

C6318

5%

SYNC_MASTER=J16_DIRK SYNC_DATE=03/07/2013

AUDIO: LEFT SPKR AMP

AUD_LAMP_GAIN

AUD_LAMP_OUTPR

MIN_NECK_WIDTH=0.25MM

AUD_LAMP_OUTPR

MIN_LINE_WIDTH=0.6MM

AUD_LAMP_OUTNR

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

=PP3V3_S0_AUDIO

MIN_NECK_WIDTH=0.15MM VOLTAGE=5V

MIN_LINE_WIDTH=0.20MM

AUD_LAMP_AVDD

AUD_LAMP_LIN_P

AUD_LAMP_RIN_N

AUD_LAMP_LIN_N

AUD_SPKRAMP_WIN_SHDN_L

AUD_LAMP_MONO

=PP12V_S0_AUDIO_SPKRAMP

AUD_LAMP_RIN_P

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

AUD_LAMP_OUTNL

AUD_LAMP_OUTPL

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

AUD_LAMP_BOOTLN

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM

AUD_SPKRAMP_WIN_SHDN_L

AUD_GPIO_3

AUD_LAMP_RINC_N

AUD_LAMP_RINC_P

AUD_LAMP_AVDD

AUD_LAMP_GAIN

AUD_LAMP_BOOTRP

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM

AUD_SPKR_LWFR_OUT_P

AUD_LAMP_OUTNR

AUD_LO2_L_N

AUD_LAMP_MONO

AUD_LO1_L_P

AUD_LO2_L_P

AUD_LAMP_EDGE

MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.20MM

AUD_LAMP_BOOTRN

AUD_SPKR_LTWT_OUT_N

AUD_SPKR_LTWT_OUT_P

AUD_SPKR_LWFR_OUT_N

AUD_LAMP_BOOTLP

MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.20MM

AUD_SPKRAMP_MAC_SHDN_L

AUD_LO1_L_N

TP_AUD_LAMP_THERM

AUD_LAMP_LINC_P

AUD_LAMP_LINC_N

AUD_LAMP_EDGE

AUD_SPKRAMP_MAC_SHDN_L

AUD_CODEC_MICBIAS

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1

2

1

394038

33

23

8

31

41

37

35

34

32

24

17

13

7

10

36

12

20

21

11

6

19

3

16

27

2

30

5

22

28

26

4

29

25

1

18

15

14

9

1

2

1

2

21

1

2

1

2

1 2

21

1

2

1

2

1

21

2

1

2

21

4 3

1 2

4 3

1 2

1

2

1 2

2

1

2

1

54

38 52 55 58 70

54

59

54

59

54

59

54

IN

REGEN

VREG/AVDD

PGND

THRM_PAD

PVDD

THERM

NC

AGND

EDGEINL-

INR+

GAIN

INL+

BOOTL-

INR-

MONO

OUTR-

OUTL+

BOOTR+

OUTL-

SDNR*

OUTR+

BOOTR-

BOOTL+

TEST

SDNL*

IN

NC NC

SYM_VER-2

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

MAKE LAYOUT MORE LOGICAL

OUTPUT POLARITY FLIP TO

SHOULD BE TIED TO GND

PINS 14 & 15 ARE TEST PINS AND

OFF NOSTUFF 0 OHM

EDGE RATE

FC_HPF, TWEETERS = ~847 HZ (4700 PF)

SPEAKER AMP RIN = 40K NOMINAL

SPEAKER AMP GAIN = +9 DB

APPLE P/N 353S3163

ONLY WOOFERS ON UNDER WINDOWS

RIGHT CH SPEAKER AMP

NC

+12 DB NOSTUFF 47 KOHM +15 DB NOSTUFF NOSTUFF +18 DB 47 KOHM NOSTUFF +24 DB 0 OHM NOSTUFF

+9 DB NOSTUFF 0 OHM

AUD_RAMP_MONO NET: HIGH = MONO OPERATION

FC_HPF, WOOFERS = ~4 HZ (1.0 UF)

ON 0 OHM NOSTUFF

CONTROL R6404 R6405

INPUT POLARITY FLIP OK -- TRUE DIFF INPUTS

WOOFERS & TWEETERS ON UNDER MAC OS

GAIN R6406 R6407

LOW = STEREO OPERATION

54 70

CRITICAL

NO_XNET_CONNECTION=TRUE

C6421

25V CERM 0402

1000PF

5%

CRITICAL

NO_XNET_CONNECTION=TRUE

C6419

25V CERM 0402

1000PF

5%

CRITICAL

NO_XNET_CONNECTION=TRUE

C6420

25V CERM 0402

1000PF

5%

CRITICAL

NO_XNET_CONNECTION=TRUE

C6422

25V CERM 0402

1000PF

5%

603

20%

0.22UF

X5R

C6415

25V

52 53 59

52 59

20%

0.22UF

X5R 603

C6416

25V

X5R

20%

603

0.22UF

C6413

25V

X5R

0.22UF

20%

603

C6414

25V

LFCSP

CRITICAL

SSM3302

U6400

20% 10V

X5R-CERM

2.2UF

C6417

402

54

10UF

X5R 805

10%

C6401

25V

1/16W

0

MF-LF

R6404

402

5%

0

1/16W MF-LF

NOSTUFF

R6405

402

5%

MF-LF

0

1/16W

R6403

402

5%

0

MF-LF

NOSTUFF

1/16W

R6406

402

5%

10% X5R

805

10UF

C6400

25V

NO_XNET_CONNECTION=TRUE CRITICAL

C6423

25V CERM 0402

1000PF

5%

CRITICAL

NO_XNET_CONNECTION=TRUE

C6424

25V CERM 0402

1000PF

5%

20%

470UF

SM

POLY

16V

CRITICAL

C6406

CRITICAL

NO_XNET_CONNECTION=TRUE

DLY5ATN111SQ2

110-OHM-3A

L6405

NO_XNET_CONNECTION=TRUE

DLY5ATN111SQ2

CRITICAL

110-OHM-3A

L6407

47K

1/16W MF-LF

R6407

402

5%

4700PF

0805

NPO-C0G-CERM

50V

C6410

5%

NPO-C0G-CERM

0805

4700PF

50V

C6411

5%

0402

X5R

10%

1UF

C6408

25V

1UF

0402

10% X5R

C6409

25V

FERR-1000-OHM

0402

L6400

0.1UF

10% X5R

C6404

25V 402

FERR-1000-OHM

0402

L6401

FERR-1000-OHM

0402

L6402

0402

FERR-1000-OHM

L6403

X5R

10%

0.1UF

C6402

25V 402

603-1

X5R

10%

1UF

C6403

25V

10%

603-1

X5R

1UF

C6405

25V

52 59

52 53 59

57 59

SYNC_DATE=03/07/2013SYNC_MASTER=J16_DIRK

AUDIO: RIGHT SPKR AMP

AUD_RAMP_LIN_N

AUD_RAMP_LIN_P

AUD_RAMP_OUTNR

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

AUD_RAMP_OUTPR

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.6MM

AUD_RAMP_OUTNL

AUD_RAMP_OUTNR

AUD_RAMP_OUTPL

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.6MM

=PP3V3_S0_AUDIO

AUD_RAMP_MONO

AUD_RAMP_GAIN

AUD_RAMP_LINC_P

AUD_LO1_R_N

AUD_RAMP_RIN_N

AUD_SPKR_RTWT_OUT_N

AUD_RAMP_EDGE

=PP12V_S0_AUDIO_SPKRAMP

AUD_RAMP_RINC_N

AUD_RAMP_RINC_P

AUD_RAMP_RIN_P

AUD_LO1_R_P

AUD_LO2_R_P

AUD_RAMP_LINC_N

AUD_LO2_R_N

AUD_RAMP_AVDD

AUD_RAMP_GAIN

AUD_SPKR_RTWT_OUT_P

AUD_SPKR_RWFR_OUT_P

AUD_SPKR_RWFR_OUT_N

AUD_SPKRAMP_MAC_SHDN_L

AUD_SPKRAMP_WIN_SHDN_L

MIN_NECK_WIDTH=0.15MM VOLTAGE=5V

MIN_LINE_WIDTH=0.20MM

AUD_RAMP_AVDD

AUD_RAMP_EDGE

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM

AUD_RAMP_BOOTRP

TP_AUD_RAMP_THERM

AUD_RAMP_MONO

MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.20MM

AUD_RAMP_BOOTRN

MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.20MM

AUD_RAMP_BOOTLP

MIN_NECK_WIDTH=0.25MM

AUD_RAMP_OUTPR

MIN_LINE_WIDTH=0.6MM

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM

AUD_RAMP_BOOTLN

051-0164

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32

24

17

13

7

10

36

12

20

21

11

6

19

3

16

27

2

30

5

22

28

26

4

29

25

1

18

15

14

9

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

4 3

1 2

4 3

1 2

1

2

1 2

21

2

1

21

2

1

2

1

2

1

59

55

38 52 54 58 70

55

59

55

59

59 59

59

55

OUT

IN

BI

OUT

IN

CS

HDET

ENABLE

INT*

SDA

SCL

AGND

MICBIAS

DETECT

BYPASS

AVDD

DGND

IN

OUT

IN

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PORT B LEFT(HEADSET MIC)

MIKEY READ 0111 0011 0X73

CHS WRITE 0111 0110 0X76

CHS READ 0111 0111 0X77

MIKEY WRITE 0111 0010 0X72

PLACE XWS 6500 & 6501 AT J6500 PINS

MIKEY RECEIVER CKT

(SEE RADAR # 6210118)

R/C6750 FILTER TO ADDRESS OUT-OF-BAND

APN 516S0687

I2C PULLUPS ON SOUTHBRIDGE PAGE

NOISE ISSUE SEEN ON EARLY HEADSETS

MIKEY 1A

INTENTIONALLY

OPPOSIDE

POLARITY

HP=80HZ, LP=10.63KHZ

WRITE: 0X72 READ: 0X73

AUDIO JACK: HP CONNECTOR WITH MIKEY

I2C ADDRESSES

APN 353S2640

MIKEY ADDRESS: WRITE=72H, READ=73H

APN:353S2640

52 59

47

12

20

58

NOSTUFF

47K

5%

402

MF-LF

1/16W

R6561

MQFN-RSV

CD3285A0

CRITICAL

U6551

100K

1/20W

201

5% MF

R6556

2.2K

MF-LF

402

1/16W

5%

R6550

1K

402

MF-LF

1/16W

5%

R6554

NO_XNET_CONNECTION=TRUE

10% X7R

402

0.01UF

25V

C6556

X5R-CERM

0402

4.7UF

10V

20%

CRITICAL

C6555

56 59

FERR-1000-OHM

0402

L6505

52 56 58 59

58

FERR-1000-OHM

0402

L6501

FERR-1000-OHM

0402

L6500

58

56 59

FERR-1000-OHM

0402

L6510

58

5% 1/16W MF-LF

402

0

R6551

1K

MF-LF

402

5%

1/16W

NOSTUFF

NO_XNET_CONNECTION=TRUE

R6553

54722-0224

NO_XNET_CONNECTION=TRUE

CRITICAL

F-ST-SM

J6500

0402

CRITICAL

FERR-120-OHM-2.0A

L6507

52 79

0402

FERR-1000-OHM

L6502

FERR-120-OHM-2.0A

CRITICAL

0402

L6509

53

47

FERR-120-OHM-2.0A

CRITICAL

0402

L6503

47

53

56 59

5%

402

1/16W MF-LF

0

R6506

201

MF

1/20W

5%

10K

R6562

201

MF

1/20W

5%

100K

R6555

0402

FERR-120-OHM-2.0A

CRITICAL

L6508

0402-1

27PF

CRITICAL

5% 50V CERM

C6558

0402

0.0082UF

X7R-CERM

CRITICAL

25V

10%

C6550

16V

0402

10%

X7R-CERM

0.1UF

C6552

X7R-CERM

10% 16V

0.1UF

0402

C6553

0402

X7R-CERM

16V

10%

0.1UF

C6560

SOD882

ESDALC5-1BM2

NOSTUFF

DZ6501

NOSTUFF

SOD882

ESDALC5-1BM2

DZ6500

SOD882

ESDALC5-1BM2

NOSTUFF

DZ6503

SOD882

ESDALC5-1BM2

NOSTUFF

DZ6504

SOD882

ESDALC5-1BM2

NOSTUFF

DZ6502

SOD882

ESDALC5-1BM2

NOSTUFF

DZ6505

FERR-120-OHM-2.0A

CRITICAL

0402

L6511

52 58

SYNC_MASTER=J16_DIRK

AUDIO: Jack, Mikey, CHS Switch

SYNC_DATE=03/07/2013

AUD_TIPDET2_R

AUD_MIC_INL_P

AUD_MIC_INL_N

AUD_HS_MIC_RC_P

AUD_PORTD_DET_L

HS_RX_BP

HS_SW_DET

AUD_SPDIF_OUT

MAX97220_OUTL

AUD_HP_PORT_REF

MAX97220_OUTR

AUD_TIPDET1_R

AUD_J1_TIPDET1_R

AUD_HS_MIC_RC_N

=I2C_CHS_SCL

=I2C_CHS_SDA

AUD_HS_MIC_N

AUD_J1_MIC_BIAS

MIN_LINE_WIDTH=0.25MM MIN_NECK_WIDTH=0.20MM

HS_HDET

AUD_HS_MIC_P

HS_MIC_BIAS

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.25MM

GND_AUDIO_CODEC

AUD_J1_MIC_P

=I2C_MIKEY_SDA

PP4V5_AUDIO_ANALOG

GND_AUDIO_CODEC

AUD_IPHS_SWITCH_EN

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.25MM

AUD_J1_HP_OUTL

MIN_LINE_WIDTH=0.25MM MIN_NECK_WIDTH=0.20MM

AUD_J1_HP_OUTR

AUD_J1_GND_ANALOG

MIN_NECK_WIDTH=0.20MM VOLTAGE=0V

MIN_LINE_WIDTH=0.50MM

AUD_J1_HP_PORT_REF

AUD_I2C_INT_L

=PP3V3_S0_AUDIO_DIG

=I2C_MIKEY_SCL

AUD_HS_MIC_N

AUD_J1_TIPDET2_R

AUD_TYPEDET_R

GND_AUDIO_CODEC

AUD_HS_MIC_P

AUD_J1_MIC_N

HS_MIC_BIAS

AUD_J1_TYPEDET_R

AUD_J1_PP3V3_S0

MIN_LINE_WIDTH=0.25MM MIN_NECK_WIDTH=0.20MM

=PP3V3_S4_AUDIO_DIG

051-0164

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1

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678

12

10

11

9

15

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5

1

2

1 2

1

2

1

2

1

21

1 2

1

2

1 3

7

5

9 11 13 15

19

17

21

2 4 6 8

14

10 12

18

16

20 22

21

1 2

1

2

1

2

21

2

1

2

1

1 2

2

1

1 2

12

1 2

21

59

56

52 56 58 59

59

52 56 58 59

70

59

56

70

OUT

IN

IN IN

OUT

IN IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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C

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NOTICE OF PROPRIETARY PROPERTY:

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DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TWEETER (FR)

APPLE P/N 518S0862

TWEETER (FL)

WOOFER (BR)WOOFER (BL)

SPEAKER CABLE CONNECTORS

59

54 59

59

55 59

M-RT-SM

504050-0691

CRITICAL

J6603

M-RT-SM

504050-0691

CRITICAL

J6602

Audio: Spkr/Mic Conn.

SYNC_MASTER=J16_DIRK SYNC_DATE=03/07/2013

AUD_SPKR_VENDOR_ID_R

AUD_SPKR_RWFR_OUT_N

AUD_SPKR_RWFR_OUT_P

AUD_SPKR_LTWT_OUT_N

AUD_SPKR_LWFR_OUT_N

AUD_SPKR_LWFR_OUT_P

AUD_SPKR_LTWT_OUT_P

AUD_SPKR_VENDOR_ID_L

AUD_SPKR_RTWT_OUT_P AUD_SPKR_RTWT_OUT_N

051-0164

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1 2

4

3

5 6

8

7

1 2

4

3

5 6

8

7

OUT

IN

NC

IN

OUT

IN

OUT

IN

D

SG

D

SG

D

SG

D

SG

D

S

G

N-CHN

G

D

S

P-CHN

IN

D

SG

D

SG

D

SG

D

S

G

D

S

G

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Target Display Mode Detect

TBT/DP Audio Enable

PORT B DETECT(SPDIF DELEGATE)

AUD_SENSE_A 1 20K/2.67K RDIV 39.2K/2.67K RDIV

PORT D DETECT (HEADPHONES)

AUD_J1_TYPEDET_R 1 1 0

AUD_OUTJACK_INSERT_L 1 0 0

NC

NOTHING SPDIF HEADPHONE

AUD_J1_TIPDET_R 0 1 1

NC

APN:376S1032

AUDIO CONNECTOR DETECT STATES

PLACE C6700 CLOSE TO Q6700 PIN 4

IPHS HS Detect Debounce CKT

12

R6745

0

MF-LF

402

1/16W

5%

C6741

0402

X7R-CERM

NOSTUFF

10%

0.1UF

16V

52 58 59

R6744

100K

5% MF

1/20W

201

L6743

FERR-1000-OHM

0402

56

52 58 59

R6792

402

47K

5%

MF-LF

1/16W

C6791

CERM

20%

10V 402

0.1UF

R6796

402

MF-LF

1/16W

1%

20.0K

R6730

5%

10K

MF

1/20W

201

L6732

0402

FERR-1000-OHM

11 41

56

R6795

1%

402

MF-LF

5.11K

1/16W

R6731

1%

39.2K

MF-LF 402

1/16W

56

Q6797

SSM6N15AFE

SOT563

Q6796

SOT563

SSM6N15AFE

Q6741

SOT563

SSM6N15AFE

Q6741

SSM6N15AFE

SOT563

Q6700

DMC2400UV

SOT563

Q6700

DMC2400UV

SOT563

56

R6701

270K

1/20W

5% MF

201

R6702

100K

5%

1/20W

MF

201

R6703

MF

5%

201

1/20W

100K

Q6797

SSM6N15AFE

SOT563

Q6796

SOT563

SSM6N15AFE

Q6800

SSM6N15AFE

SOT563

Q6740

NTZD3152P

SOT-563-HF

Q6740

NTZD3152P

SOT-563-HF

R6741

1/20W

201

MF

5%

47K

R6742

5%

1/20W

47K

MF

201

R6791

100K

1/20W

201

MF

5%

R6743

5%

47K

201

MF

1/20W

C6700

10%

0.1UF

0402

X7R-CERM

16V

52 56 58

PP4V5_AUDIO_ANALOG

52 56 58

AUDIO: Detects/Grounding

SYNC_MASTER=J16_DIRK SYNC_DATE=03/07/2013

GND_AUDIO_CODEC

AUD_TYPEDET_OD

AUD_SENSE_A

PP4V5_AUDIO_ANALOG

AUD_TIPDET2_R

AUD_TIPDET_INV

GND_AUDIO_CODEC

AUD_J1_DET_RC

AUD_PORTD_DET_L

AUD_TIPDET1_R

AUD_IP_PERPH_DET_R

AUD_IP_PERPH_DET_DB

AUD_IP_PERIPHERAL_DET

=PP3V3_S0_AUDIO

AUD_PORTB_DET_L

AUD_LI_TIPDET

GND_AUDIO_CODEC

AUD_TYPEDET_R

DP_TBT_SEL

GND_AUDIO_CODEC

AUD_OUTJACK_INSERT_L

AUD_TYPEDET_OD_INV

AUD_J1_DET_RC

AUD_PORTA_DET_L

AUD_SENSE_A

AUD_OUTJACK_INSERT

051-0164

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2

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1 2

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1

2

1

2

3

4

5

3

4

5

3

4

5

6

1

2

1

2

6

34

5

1

2

1

2

1

2

6

1

2

6

1

2

3

4

5

1

6

2

4

3

5

1

2

1

2

1

2

1

2

1

52 56 58 59

58

38 52 54 55 70

52 56 58 59

58

OUT

IN IN

D

SG

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

CODEC INPUT SIGNAL PATHS

0x0F (15) 0X12 (18,LEFT)

0X0D (13,V22,B,LEFT)

ENABLE/CONTROL

0X06 (6)

INTERNAL MIC ARRAY EXTERNAL MIC Lynx POINT GPIO 16

Lynx POINT GPIO 3 (PERIPH DET)

N/A

Lynx POINT GPIO 5 (RCVR INT)

N/A

0X0E (14,LEFT & RIGHT)

PIN COMPLEX

CONVERTER

0X07 (7) 0X06 (6)

0X05 (5)

SPDIF IN

FUNCTION

SPDIF OUT

SECONDARY SPKRS (TWT)

PRIMARY SPKRS (WFR)

HP/LINE OUT

N/A

PIN COMPLEX

FUNCTION

CODEC OUTPUT SIGNAL PATHS

NC

VOLUME/MUTE

0X04 (4)

OTHER DETECT

CONVERTER

N/A

PHYSICAL

NET_TYPE

SPACING

ELECTRICAL_CONSTRAINT_SET

N/A

MULTIPLE SPKR VENDORS

0X03 (3) 0X03 (3)

0X08 (8)

0X04 (4)

GPIO_3

0X03 (3)

0X0A (10,V24)

N/AN/A

MICBIAS

N/A

GPIO_2

FUNCTION

PIN COMPLEX

0X0A (10,D)

MICBIAS

N/A

WIN SHDN

0X0B (11)

DET ASSIGNMENT

N/A N/A

ENABLE/CONTROL

PORT C DETECT(SPEAKER MISMATCH)

N/A

0X0C (DET C)

CONVERTER

0X0D (DET B)

DET ASSIGNMENT

0X09 (DET A)

DET ASSIGNMENT

0X03 (3)

MAC SHDN

GPIO_2 0X0A (DET D)

0x10 (16)

I203

I204

I205

I206

I207

I208

I209

I210

I211

I212

I215

I216

I217 I218

I219

I220

I221

I222

I223

I224

I225

I226

I227

I228

I229

I230

I236

I237

I238

I239

I240 I241

I242 I243

I244

I245

I246

I247

I254

I255

I263

I264

R6812

100K

SPEAKERID

1% 1/16W MF-LF

402

R6813

1% 1/16W

SPEAKERID

100K

MF-LF 402

R6810

MF-LF

402

100K

1%

SPEAKERID

1/16W

R6811

402

SPEAKERID

1% MF-LF

1/16W

100K

R6816

SPEAKERID

100K

1% 1/16W MF-LF

402

52 58

U6800

MAX9119EXK-T

CRITICAL

SC70-5

SPEAKERID

57 57

L6802

SPEAKERID

0402

FERR-1000-OHM

R6820

402

MF-LF

33

1/16W

5%

SPEAKERID

R6894

SPEAKERID

MF-LF

402

10K

1/16W

1%

C6811

10%

2.2UF

805

X7R-CERM

16V

SPEAKERID

R6815

402

MF-LF

1/16W

1%

75K

SPEAKERID

R6817

1%

37.4K

402

1/16W MF-LF

SPEAKERID

R6814

402

MF-LF

1/16W

1%

226K

SPEAKERID

I324 I325

I326

I327 I328

I329

Q6800

SOT563

SSM6N15AFE

C6810

SPEAKERID

16V X7R-CERM 0402

0.1UF

10%

AUDIODIFF

*

AUDIODIFF

0.2 MM

SPKROUT

*

?

*

0.1 MM

AUDIO

SPKROUTDIFF

*

SPKROUTDIFF

AUDIODIFF

Y

*

0.1 MM

10 MM

0.1 MM

0.1 MM0.1 MM

*

Y

10 MM

0.2 MM

0.25 MM

0.6 MM

0.2 MM

SPKROUTDIFF

SYNC_MASTER=J16_DIRK SYNC_DATE=03/07/2013

AUDIO: Speaker ID

MAX9119_OUT

SPKR_MATCH_DRV

AUD_SENSE_A

=PP5V_S0_AUDIO

SPKR_MATCH_DRV_R

AUDIO_DIFFPAIR

AUDIO

AUDIODIFF

MAX97220_INL_N

AUDIO_DIFFPAIR

AUDIO

AUD_LAMP_LINC_N

AUDIODIFF

AUDIO

AUD_LAMP_LIN_P

AUDIODIFF

AUDIO_DIFFPAIR

AUDIO

AUDIODIFF

AUD_RAMP_RINC_P

AUDIO

AUDIODIFF

AUDIO_DIFFPAIR

AUD_LO1_L_C_P

AUDIO_DIFFPAIR

AUDIO

AUDIODIFF

AUD_LO1_L_C_N

AUDIODIFF

AUDIO

AUDIO_DIFFPAIR

AUD_LO1_R_P

AUDIO_DIFFPAIR

AUDIO

AUDIODIFF

AUD_LO1_R_N

AUDIODIFF

AUDIO

AUDIO_DIFFPAIR

AUD_LO1_R_C_P

AUDIO_DIFFPAIR

AUDIODIFF

AUDIO

AUD_LO1_L_P

AUDIO_DIFFPAIR

AUDIODIFF

AUDIO

AUD_LO1_L_N

AUDIODIFF

AUDIO

AUDIO_DIFFPAIR

AUD_LO1_R_C_N

AUDIO_DIFFPAIR

AUDIO

AUDIODIFF

AUD_LO2_L_P

AUDIO_DIFFPAIR

AUDIODIFF

AUDIO

AUD_LO2_L_N

AUDIO_DIFFPAIR

AUDIO

AUDIODIFF

AUD_LO2_R_P

AUDIO

AUDIODIFF

AUDIO_DIFFPAIR

AUD_LO2_R_N

AUDIO

AUD_LAMP_RIN_N

AUDIODIFF

AUDIO_DIFFPAIR

AUDIO

AUDIODIFF

AUD_RAMP_LINC_N

AUDIO_DIFFPAIR

AUDIO

AUDIODIFF

AUD_RAMP_LINC_P

AUDIO

AUDIODIFF

AUDIO_DIFFPAIR

MAX97220_INR_N

=PP5V_S0_AUDIO

MAX9119_NEG

AUD_SPKR_VENDOR_ID_L AUD_SPKR_VENDOR_ID_R

MAX9119_POS

AUDIO

AUDIODIFF

AUD_RAMP_RINC_N

AUDIO_DIFFPAIR

AUDIO

AUDIODIFF

AUD_RAMP_LIN_P

AUDIO_DIFFPAIR

AUDIO

AUDIODIFF

AUD_RAMP_LIN_N

AUDIO_DIFFPAIR

AUDIODIFF

AUDIO

AUD_RAMP_RIN_P

AUDIO_DIFFPAIR

AUDIO

AUDIODIFF

AUD_RAMP_RIN_N

AUDIO_DIFFPAIR

AUDIODIFF

AUDIO

AUD_LAMP_LINC_P

AUDIO_DIFFPAIR

AUDIO

AUDIODIFF

AUD_LAMP_RINC_P

AUDIODIFF

AUDIO

AUD_LAMP_RINC_N

AUDIO_DIFFPAIR

AUD_LAMP_RIN_P

AUDIO

AUDIODIFF

AUDIO_DIFFPAIR

AUDIO

AUD_LAMP_LIN_N

AUDIODIFF

AUDIO_DIFFPAIR

AUDIO

AUDIODIFF

AUDIO_DIFFPAIR

MAX97220_INL_P

AUDIO

AUDIODIFF

AUDIO_DIFFPAIR

MAX97220_INR_P

SPKROUT_DIFFPAIR

SPKROUT

SPKROUTDIFF

AUD_SPKR_RWFR_OUT_P

SPKROUT_DIFFPAIR

SPKROUT

AUD_SPKR_RWFR_OUT_N

SPKROUTDIFF

SPKROUT

AUD_SPKR_RTWT_OUT_P

SPKROUTDIFF

SPKROUT_DIFFPAIR

AUD_SPKR_LWFR_OUT_P

SPKROUT

SPKROUTDIFF

SPKROUT_DIFFPAIR

AUD_SPKR_LTWT_OUT_N

SPKROUT_DIFFPAIR

SPKROUT

SPKROUTDIFF

SPKROUT_DIFFPAIR

SPKROUT

AUD_SPKR_LTWT_OUT_P

SPKROUTDIFF

AUD_SPKR_RTWT_OUT_N

SPKROUT

SPKROUTDIFF

SPKROUT_DIFFPAIR

AUD_SPKR_LWFR_OUT_N

SPKROUT

SPKROUTDIFF

SPKROUT_DIFFPAIR

AUDIODIFF

AUDIO_DIFFPAIR

AUDIO

AUD_MIC_INL_N

AUDIO

AUDIODIFF

AUDIO_DIFFPAIR

AUD_J1_MIC_N

AUDIODIFF

AUDIO_DIFFPAIR

AUDIO

AUD_J1_MIC_P

AUDIO_DIFFPAIR

AUDIODIFF

AUDIO

AUD_HS_MIC_RC_P

AUDIO

AUDIO_DIFFPAIR

AUD_HS_MIC_P

AUDIODIFF

AUDIO_DIFFPAIR

AUDIO

AUD_HS_MIC_N

AUDIODIFF

AUDIO_DIFFPAIR

AUDIO

AUD_HS_MIC_RC_N

AUDIO_DIFFPAIR

AUDIODIFF

AUDIO

AUD_MIC_INL_P

GND_AUDIO_CODEC

AUD_PORTC_DET_L

=PP5V_S0_AUDIO

051-0164

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1

2

1

2

1

2

1

2

1 2

3

1

2

4

5

21

1 2

1

2

1

2

1 2

1

2

6

1

2

1

52 59 70

53

54

55

53

52 53 55

53

52 53 54

53

52 54

52 55

54

55

53

52 59 70

55

54

53

55 57

54 57

55 57

54 57

52 56

56

52 56

52 56 58

52 59 70

SW

BOOST

VIN

BIAS

SHDN*

GND

NC

FB

PAD

THRM

NC

OUT

NC

IN

G

D

S

ON

NC

S

VCC

D

PG

G

GND

THRM

PAD

OUT

OUT OUT

OUT

IN

OUT

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

3.425V "G3Hot" Regulator

Vout = 3.425 250mA max output

<Ra>

Input: 2.4V to 5.5V

Switching freq:

409 kHz =

13.5 L6901

Vout = 1.25V * (1 + Ra / Rb)

<Rb>

(Switcher limit)

MLB to AC-DC Supplemental Signal Connector

MLB to AC-DC Connector

12V S5 FET

SMC_PM_G2_EN IS PULLED DOWN ON SMC PAGE

U6900

LT3470AED

DFN

CRITICAL

402

R6904

MF-LF

1% 1/16W

200K

10%

C6902

10UF

0805

X6S

25V

402

R6901

1%

150K

1/16W MF-LF

402

R6902

1% MF-LF

1/16W

49.9K

70

CDPH4D19FHF-SM

33UH

L6901

CRITICAL

10%

0.1UF

0402

X7R-CERM

16V

C6970

44 45

402

10% 16V

0.22UF

CERM

C6903

Q6970

IRFH3702TRPBF

PQFN

CRITICAL

1UF

10%

C6906

0402

X6S-CERM

25V

1UF

10%

C6907

0402

X6S-CERM

25V

402

R6972

MF-LF

1/16W

1%

49.9K

U6970

TDFN

CRITICAL

SLG5AP022-200030V

68

50V 0402

22PF

CERM

5%

C6904

402

R6913

1/16W

10K

MF-LF

5%

1UF

6.3V 402

10%

C6916

CERM

J6901

SILK_PART=PwrSig

53780-8606

CRITICAL

M-RT-SM

50 81

45 60

402

100

R6911

MF-LF

1/16W

5%

402

D6911

6.8V-100PF

402

R6912

1/16W

1K

MF-LF

5%

402

D6912

6.8V-100PF

10%

0.1UF

C6915

0402

16V

X7R-CERM

1UF

6.3V 402

10%

C6914

CERM

45 65

45

C6913

J6900.4:4mm

EMC

25V CERM 0402

1000PF

5%

C6912

EMC

J6900.5:3mm

25V CERM 0402

1000PF

5%

10%

C6911

J6900.4:3mm

10UF

X5R-CERM

16V 0805

J6900

F-RT-TH

43650-0603

CRITICAL

20%

6.3V

C6905

X5R-CERM1

22UF

0603

C6901

NOSTUFF

25V CERM 0402

1000PF

5%

402

R6903

348K

MF-LF

1% 1/16W

Power Connectors / VReg G3Hot

SYNC_MASTER=J16_ROSSANA

SYNC_DATE=03/04/2013

C6905

138S0676 138S0691

SMC_ACDC_ID

PP12V_G3H_ACDC

SMC_ACDC_ID

=PP3V3_S0_VRD

PWR_BTN

BURSTMODE_EN_R_L

BURSTMODE_EN_L

SNS_ACDC_P

SNS_ACDC_N

FET_EN_P12V_S5_R

PP12V_S5_FET

FET_EN_P12V_S5

PM_PGOOD_FET_P12V_S5

P3V42G3H_BOOST

P3V42G3H_SHDN_L

P3V42G3H_FB

P3V42G3H_SW

PWR_BTN_R

SMC_PM_G2_EN

=PP12V_G3H_FET_P12V_S5

PP3V42_G3H_REG

=PP12V_G3H_REG_3V42_G3H

051-0164

12.4.0

69 OF 123

60 OF 86

4

3

6

2

8

5

7

1

9

1

2

1

2

1

2

21

2

1

2

1

5

1

4

2

1

2

1

2

3

6

1

5

8

7

4

9

2

1

2

1

1 2

4

3

5 6

8

7

1 2

1

2

1 2

1

2

1

2

1

2

1

2

1

2

1

1 2 3

5

4

6

2

1

2

1

2

70

45 60

61 64 70

84

70

OUT

IN

BI

OUT

NC NC NC

GND

RSET

THRM_PAD

OPEN3

OPEN1 OPEN2

ISEN4+

ISEN4-

ISEN3+

ISEN3-

ISEN2+

ISEN1+

ISEN2-

PWM4

ISEN1-

PWM3

PWM2

PWM1

VINVIN+

EN_PWR_OVP

FS_FDVID

TM_EN_OTP

VR_HOT*

IMON

AUTO_NPSI

COMP

HFCOMP

PSICOMP

FB

DVC_MEM

RGND

VSEN

SVDATA

SVALERT*

SVCLK

MEMVRSEL

VR_RDY

VCC

IMADR_BTRM

TMX_DRP_DE_TC

OUT

IN IN

OUT

IN

IN IN

IN

TABLE_5_ITEM

REFERENCE DESIGNATOR(S)

BOM OPTION

TABLE_5_HEAD

QTY

DESCRIPTION

PART#

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_5_ITEM

REFERENCE DESIGNATOR(S)

BOM OPTION

TABLE_5_HEAD

QTY

DESCRIPTION

PART#

Sense from CPU

Per Intel Shark Bay PDG

Temp measurement

(vr hot out)

403 kHz =

VRHot to ProcHot

To sense amps

(psi comp)

OC trip point:

CPU VCC S0 Regulator

To feedback

(hf comp)

Pull-ups 2

Compensation and feedback

To PSI comp

To VSense

(comp out)

(pu 1)

(pgood)

(imon out)

(pu 1)

(straps)

(pu 2)

(vsen in)

(straps)

Power goods

Voltage sense input

To voltage sense

114 A

Pull-ups 1

(pu 1)

(fb in)

5 E10

Straps

To HF comp

Switching freq:

IMON output

R7003

J17: 4PHASE

J16: 3PHASE

Tie to GND for VR12.5

OMIT

SM

U7000.41:6MM

XW7000

0603

6.8K

RT7090

16V

C7090

X7R-CERM

0.1UF

10%

0402

R7090

402

MF-LF

1K

1/16W

5%

2.2

R7000

1/16W 402

MF-LF

5%

C7000

16V

10UF

20%

0603

X6S-CERM

8

61 83

8

61 83

8

61 83

R7009

402

1/16W MF-LF

0

5%

R7019

1%

110

402

MF-LF

1/16W

PLACE_NEAR=U7000.13:12.7mm

R7018

NOSTUFF

90.9

MF-LF

1%

402

1/16W

R7017

402

MF-LF

1/16W

54.9

1%

PLACE_NEAR=U7000.15:12.7mm

0402

C7017

16V

X7R-CERM

10%

0.1UF

MF-LF

402

1/16W

R7093

0

5%

6

44 45 62 76

48 61 83

R7098

10K

MF-LF

1/16W 402

5%

69

R7026

MF-LF

402

1/16W

0

5%

R7027

402

MF-LF

1/16W

0

5%

R7028

MF-LF

402

1/16W

0

5%

1M

R7014

1%

402

MF-LF

1/16W

1/16W MF-LF

R7016

12.7K

402

1%

OMIT_TABLE

150K

1%

R7005

MF

1/20W 201

R7006

147K

1% MF

1/20W 201

124K

1%

R7003

MF

1/20W 201

R7004

NOSTUFF

0201

MF

1/20W

0

5%

R7007

NOSTUFF

0201

MF

1/20W

0

5%

R7008

249K

1% MF

1/20W 201

OMIT_TABLE

R7001

1%

340K

MF

1/20W 201

OMIT_TABLE

R7002

1%

95.3K

MF

1/20W 201

16V X5R 0201

10%

0.047UF

C7001

1/16W

R7039

NOSTUFF

402

MF-LF

0

5%

1/16W

R7037

MF-LF

1%

1.82K

402

C7037

0.0012UF

50V

10%

0402

CERM

0.0012UF

C7038

0402

50V CERM

10%

NOSTUFF

402

1/16W MF-LF

1%

R7038

3.83K

U7000

QFN

CRITICAL

ISL6372

50V

47PF

CERM 402

C7091

5%

R7029

1/16W

MF-LF

402

CPUVCC:4PHASE

0

5%

72

71

72

62 83

1/16W

R7021

402

MF-LF

NOSTUFF

0

5%

R7022

1/16W 402

MF-LF

NOSTUFF

0

5%

R7023

402

1/16W MF-LF

NOSTUFF

0

5%

R7024

MF-LF

1/16W

CPUVCC:3PHASE

402

0

5%

62 83

MF

0402

2.49M

1%

R7052

1/16W

402

CERM

C7050

33NF

10% 25V

OMIT_TABLE

R7050

1%

1/16W

402

MF-LF

402

30.9K

R7051

1%

MF-LF

1/16W

62 83

CERM

50V

C7030

10%

0.0012UF

0402

1%

R7030

7.15K

1/16W MF-LF 402

C7031

68PF

0402

50V COG-CERM

5%

1%

402

R7033

249

MF-LF

1/16W

R7031

1K

MF-LF

1%

402

390PF

X7R-CERM

50V 0402

10%

C7033

1% 1/16W

402

MF-LF

OMIT_TABLE

R7032

750

MF-LF

1%

402

1/16W

787

R7034

C7034

10%

X5R-CERM

0201

10V

2.2NF

10

R7035

1/16W

1%

MF-LF

402

62 83

2.67K

R7036

1/16W MF-LF

402

1%

0402

NOSTUFF

C7035

20%

0.01UF

16V X7R-CERM

R7040

402

1/16W MF-LF

0

5%

NO_XNET_CONNECTION=TRUE

402

R7041

MF-LF

1/16W

10

5%

MF-LF

R7042

1K

1/16W

402

5%

XW7042

SM

R7150.1:25MM

OMIT

8

83

C7048

0.0012UF

10% CERM

50V 0402

NOSTUFF

C7041

0402

10% 50V CERM

0.0012UF

C7046

0.0012UF

10% 50V

0402

CERM

R7046

MF-LF

10

1/16W

402

NO_XNET_CONNECTION=TRUE

5%

R7045

1/16W

402

MF-LF

0

5%

9

83

R7047

1K

402

1/16W MF-LF

5%

XW7042.2:3MM

OMIT

SM

XW7047

CPUVCC:3PHASE

118S0311

1

R7001

RES,340K,201

CPUVCC:4PHASE

118S0116

1

R7001

RES,158K,201

R7032

1

CPUVCC:3PHASE

114S0206

RES,750 OHM,402

1

RES,44.2K,201

R7002

118S0380

CPUVCC:4PHASE

118S0575

RES,95.3K,201

R7002

1

CPUVCC:3PHASE

R7032

1

CPUVCC:4PHASE

114S0211

RES,845 OHM,402

CPUVCC:3PHASE

R7050

RES,402 OHM,402

1

114S0179

R7050

1

CPUVCC:4PHASE

RES,453 OHM,402

114S0184

SYNC_MASTER=J16_ROSSANA

VReg CPU VCC Cntl

SYNC_DATE=03/21/2013

1

CPUVCC:4PHASE

R7016

RES,10.2K,402

114S0316

1

R7016

RES,12.7K,402

114S0324

CPUVCC:3PHASE

REG_CPUVCC_IMON

AGND_CPU

CPU_VIDALERT_L

AGND_CPU

CPUVCC_COMP_RC

REG_CPUVCC_DVC

AGND_CPU

CPU_VIDSOUT

PP12V_S0_CPUVCC_FLT

REG_CPUVCC_PSICOMP

CPU_VIDSCLK

REG_CPUVCC_MEMVRSEL

REG_VCC_U7000

REG_PWM_CPUVCC_4_R

REG_PWM_CPUVCC_2_R

REG_PWM_CPUVCC_1_R

CPUVCC_FB_R_2

CPUVCC_FB_R_1

=PP5V_S0_REG_CPUVCC_S0

REG_ISENVCC_3_NR

REG_ISENVCC_2_P

REG_VCC_U7000

AGND_CPU

PM_EN_REG_CPUVCC_S0

REG_PWM_CPUVCC_1_R

REG_CPUVCC_IMX

AGND_CPU

REG_CPUVCC_IMX

REG_CPUVCC_VRHOT_L

REG_CPUVCC_HFCOMP

REG_CPUVCC_PSICOMP

REG_CPUVCC_TMX

REG_CPUVCC_PGOOD

REG_CPUVCC_IMON

CPUVCC_FB_RC_2

SNS_VCC_XW_P

MAKE_BASE=TRUE

PM_PGOOD_REG_CPUVCC_S0

REG_CPUVCC_PGOOD

=PP3V3_S0_VRD

CPUVCC_DVC_RC

REG_VCC_U7000

REG_CPUVCC_VSEN

CPUVCC_PSICOMP_RC

REG_CPUVCC_TM

CPU_VIDSOUT

REG_VCC_U7000

CPU_VCCSENSE_N

CPU_VCCSENSE_P

CPU_VCCSENSE_R_N

CPU_VCCSENSE_R_P

=PPCPUVCC_S0_CPU

REG_PWM_CPUVCC_3_R

AGND_CPU

REG_CPUVCC_DVC

AGND_CPU

REG_CPUVCC_VIN

REG_PWM_CPUVCC_3_R

REG_PWM_CPUVCC_4

REG_PWM_CPUVCC_3

REG_PWM_CPUVCC_1_R

REG_PWM_CPUVCC_2

REG_PWM_CPUVCC_1

REG_CPUVCC_HFCOMP

AGND_CPU

REG_CPUVCC_RGND

REG_CPUVCC_VSEN

REG_CPUVCC_DVC

SNS_VCC_XW_N

CPU_VIDSCLK

REG_PWM_CPUVCC_2_R

CPUVCC_FB_RC

REG_CPUVCC_COMP

PPVCCIO_S0_CPU

REG_PWM_CPUVCC_4_R

REG_CPUVCC_FDVID

REG_ISENVCC_2_NR

REG_PWM_CPUVCC_4_R

REG_CPUVCC_MEMVRSEL

CPU_VIDALERT_L

REG_ISENVCC_4_NR

REG_ISENVCC_1_NR

REG_CPUVCC_RSET

REG_CPUVCC_FB

REG_ISENVCC_4_P

REG_CPUVCC_RGND

REG_ISENVCC_1_P

REG_ISENVCC_3_P

REG_CPUVCC_VRHOT_L

REG_PWM_CPUVCC_2_R

REG_CPUVCC_TM

REG_CPUVCC_NPSI

REG_CPUVCC_COMP

CPUVCC_IMON_R

CPU_PROCHOT_L

REG_CPUVCC_VSEN

REG_VCC_U7000

REG_CPUVCC_FB

AGND_CPU

REG_CPUVCC_FDVID REG_CPUVCC_TMX REG_CPUVCC_NPSI

051-0164

12.4.0

70 OF 123

61 OF 86

1 2

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

1 2

1

2

1 2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

312341

32

17 19

36

35

40

39

34

38

33

28

37

30

27

29

1 2

3

24

21

16

12

22

9

6

7

8

10

4

5

13

14

15

26

11

25

20

18

2

1

1 2

1

2

1

2

1

2

1

2

1

2

11

2

1

2

1

2

1

2

1

2

1

2

1 2

1 2 1 2

2

1

1 2 1 2

1 21 2

2

1

2

1

2

1

1 21 2

61 62 71 83

8

61 83

61 62 71 83

83

61 83

61 62 71 83

8

61 83

62 83

61 83

8

61 83

61

61 83

83

62 70

61 83

61 62 71 83

68

61 83

61 62 71 83

61 83

61

61 83

61

48 61 83

83

61

60 64 70

83

61 83

83

61 83

83

48 70

61 83

61 62 71 83

61 83

61 62 71 83

83

61 83

61 62 71 83

61 83

83

61 83

83

61 83

5 6 8

10 18

61

61 83

61

61 83

83

61 83

61

61 83

83

61 83

61 62 71 83

61 83

OUT

IN

PWM

VCIN

VDRV

CGND

NC

VIN

VSWH

PGND

BOOT

DISB*

GL

GH

PHASE

ZCD_EN*

THWN*

NC

PWM

VCIN

VDRV

CGND

NC

VIN

VSWH

PGND

BOOT

DISB*

GL

GH

PHASE

ZCD_EN*

THWN*

PWM

VCIN

VDRV

CGND

NC

VIN

VSWH

PGND

BOOT

DISB*

GL

GH

PHASE

ZCD_EN*

THWN*

IN

NC

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Acoustics E-noise Components

Filtered 12V Rail

CPU Phase 2

CPU Phase 3

CPU Phase 1

CPU Output Decoupling

61 83

0.1UF

10% 16V

C7140

C7141.1:2MM

NO_XNET_CONNECTION=TRUE

0402

X7R-CERM

NO_XNET_CONNECTION=TRUE

1%

MF-LF

1.02K

1/16W

C7141.2:2MM

R7141

402

NO_XNET_CONNECTION=TRUE

0402

220PF

X7R-CERM

50V

10%

U7000.34:3MM

C7141

61 83

0612

1W

0.0005

1% MF

CRITICAL

R7130

61 83

62 70

U7150.3:3MM

0603

X7R

16V

10%

1.0UF

C7165

U7150.11:3MM

C7158

EMC

25V CERM 0402

1000PF

5%

NOSTUFF

R7157

1

1/8W MF-LF 805

5%

C7161.1:2MM

NO_XNET_CONNECTION=TRUE

0402

X7R-CERM

0.1UF

10% 16V

C7160

NO_XNET_CONNECTION=TRUE

C7161.2:2MM

1.02K

1% 1/16W MF-LF

R7161

402

NO_XNET_CONNECTION=TRUE U7000.40:3MM

0402

220PF

X7R-CERM

50V

10%

C7161

61 83

1%

0612

0.0005

1W MF

CRITICAL

R7150

61 83

62 70

CRITICAL

0.36UH-30A-0.6MOHM

SDP110808MR36MF-TH

L7100

C7116

0.22UF

X7R

0603

10% 25V

C7119

EMC U7110.11:3MM

25V CERM 0402

1000PF

5%

U7130.11:3MM

EMC

C7138

25V CERM 0402

1000PF

5%

C7139

EMC U7130.11:3MM

25V CERM 0402

1000PF

5%

C7118

EMC U7110.11:3MM

25V CERM 0402

1000PF

5%

U7150.11:3MM

C7159

EMC

25V CERM 0402

1000PF

5%

C7114

1UF

10%

0402

X6S-CERM

EMC CRITICAL

U7110.11:3MM

25V

10% X6S-CERM

1UF

0402

C7115

EMC CRITICAL

U7110.11:3MM

25V

X6S-CERM

1UF

10%

0402

C7135

EMC CRITICAL

U7130.11:3MM

25V

0402

10%

1UF

X6S-CERM

C7134

U7130.11:3MM

EMC CRITICAL

25V

10%

0402

X6S-CERM

1UF

C7155

EMC CRITICAL

U7150.11:3MM

25V

0402

X6S-CERM

10%

1UF

C7154

EMC CRITICAL

U7150.11:3MM

25V

C7112

10UF

20% X6S-CERM

0603

16V

CRITICAL

R7116

1/10W

0

MF-LF

603

5%

CRITICAL

X6S-CERM

10UF

0603

16V

20%

C7113

X6S-CERM

16V

20%

10UF

0603

CRITICAL

C7132

10UF

16V 0603

X6S-CERM

20%

CRITICAL

C7133

C7152

CRITICAL

X6S-CERM

16V

20%

10UF

0603

X6S-CERM

20%

CRITICAL

16V

10UF

0603

C7153

NOSTUFF

0.0022UF

10% 50V CERM

C7117

402

NOSTUFF

CERM

50V

10%

0.0022UF

C7137

402

C7157

10% CERM

50V

0.0022UF

NOSTUFF

402

R7137

805

NOSTUFF

1

MF-LF

1/8W

5%

NOSTUFF

1/8W

1

MF-LF 805

R7117

5%

C7110

180UF

POLY

20% 16V

TH1

CRITICAL CRITICAL

16V POLY TH1

180UF

20%

C7111

180UF

CRITICAL

TH1

POLY

16V

20%

C7130

POLY

16V

C7150

20%

CRITICAL

180UF

TH1

CRITICAL

180UF

20% 16V

TH1

POLY

C7131

CRITICAL

C7151

20% 16V POLY TH1

180UF

61 83

230NH-10%-45A-0.00031OHM

CTX01-SM

L7110

CRITICAL

230NH-10%-45A-0.00031OHM

L7130

CTX01-SM

CRITICAL

CTX01-SM

230NH-10%-45A-0.00031OHM

L7150

CRITICAL

PQFN

FDMF6808N

U7110

CRITICAL

U7130

FDMF6808N

PQFN

603

R7136

MF-LF

0

1/10W

5%

C7136

0.22UF

X7R

10%

0603

25V

FDMF6808N

U7150

PQFN

CRITICAL

603

MF-LF

0

1/10W

R7156

5%

0603

10% X7R

0.22UF

C7156

25V

61 83

1/20W

R7115

0

MF

0201

NOSTUFF

5%

NOSTUFF

R7135

1/20W

0201

MF

0

5%

R7155

0

0201

MF

1/20W

NOSTUFF

5%

1K

1%

MF-LF

R7180

1/16W

402

NOSTUFF

R7181

MF-LF

1/16W

1%

1K

402

6

44 45 61 76

2.5V

CRITICAL

TANT

20%

CASE-D2

270UF-0.006OHM

C7180

CASE-D2

20%

270UF-0.006OHM

TANT

CRITICAL

2.5V

C7181

CASE-D2

20%

270UF-0.006OHM

TANT

CRITICAL

2.5V

C7182

270UF-0.006OHM

TANT

CRITICAL

20%

CASE-D2

2.5V

C7185

CASE-D2

20%

270UF-0.006OHM

TANT

CRITICAL

2.5V

C7184

270UF-0.006OHM

CASE-D2

20% TANT

CRITICAL

2.5V

C7183

U7110.3:3MM

C7125

16V 0603

X7R

10%

1.0UF

CRITICAL

R7110

0612

MF

1W

1%

0.0005

NO_XNET_CONNECTION=TRUE

1.02K

1/16W MF-LF

1%

C7121.2:2MM

R7121

402

0.1UF

NO_XNET_CONNECTION=TRUE

C7120

0402

X7R-CERM

16V

10%

C7121.1:2MM

U7000.38:3MM

NO_XNET_CONNECTION=TRUE

10% 50V

220PF

0402

X7R-CERM

C7121

61 83

62 70

U7130.3:3MM

C7145

16V

10%

1.0UF

0603

X7R

SYNC_MASTER=J16_ROSSANA

SYNC_DATE=03/21/2013

VReg CPU VCC Phases

REG_PHASE_CPUVCC_3

=PP5V_S0_REG_CPUVCC_S0

REG_PHASE_CPUVCC3

REG_ZCDEN

PP12V_S0_CPUVCC_FLT

PPCPUVCC_S0_REG

REG_PWM_CPUVCC_2

=PP12V_S0_REG_CPUVCC_S0

=PP5V_S0_REG_CPUVCC_S0

PPCPUVCC_S0_SENSE_3

REG_SNUBBER_CPUVCC_3

PPCPUVCC_S0_REG

REG_ISENVCC_3_P

REG_PHASE_CPUVCC1

REG_THWN_3

REG_THWN_1

REG_BOOT_CPUVCC_1

REG_PHASE_CPUVCC_1

REG_PWM_CPUVCC_1

REG_BOOT_CPUVCC_1_RC

REG_PHASE_CPUVCC2

REG_THWN_2

REG_BOOT_CPUVCC_2

REG_BOOT_CPUVCC_2_RC

REG_BOOT_CPUVCC_3_RC

REG_BOOT_CPUVCC_3

REG_PWM_CPUVCC_3

REG_SNUBBER_CPUVCC_1

PP12V_S0_CPUVCC_FLT

AGND_CPU

REG_ISENVCC_3_NR

AGND_CPU

REG_ISENVCC_2_NR

REG_SNUBBER_CPUVCC_2

REG_ISENVCC_1_NR

AGND_CPU

PPCPUVCC_S0_SENSE_1

PPCPUVCC_S0_SENSE_2

REG_ISENVCC_2_N

PPCPUVCC_S0_REG

REG_ISENVCC_1_P

REG_ISENVCC_1_N

REG_ISENVCC_3_N

REG_PHASE_CPUVCC_2

=PP5V_S0_REG_CPUVCC_S0

REG_ISENVCC_2_P

PPCPUVCC_S0_REG

CPU_PROCHOT_L

051-0164

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40

2

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15 29 30 31 32 33 34 35 43

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252627

28

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212223

24

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15 29 30 31 32 33 34 35 43

18

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1

38

1 2

40

2

3

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5

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8

252627

28

17

212223

24

9 10 11 12 13 14 42

15 29 30 31 32 33 34 35 43

18

16

4

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36

6

7

1

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1

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1

83

61 62 70

83

61 62 83

62 70

70

61 62 70

83

83 83

83

61 62 83

61 62 71 83

83

61 62 71 83

83

61 62 70

V5IN

REFIN

S5

VREF

S3

MODE TRIP

SW

DRVL

PGOOD

VDDQSNS

VTT

VTTSNS

VTTREF

DRVH

VBST

VLDOIN

THRM

VTT

GND

PGND

PADGND

IN

OUT

VSW

PGND

TGR

TG

BG

VIN

IN

TABLE_5_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

REFERENCE DESIGNATOR(S)

BOM OPTION

TABLE_5_HEAD

QTY

DESCRIPTION

PART#

TABLE_5_ITEM

Vout = 1.8 * (Rb / (Ra + Rb))

Margining support

500 kHz

3 A VTT (FIXED)

30.4 A VDDQ = 8 E5 * Rds(Q7310)

R7336

+

L7310 * f(switch)

0.65625

<Ra>

<Rb>

Need copper around Q7310 to sink heat

Critical:

10 mA VTTREF (FIXED)

VDDQ (1.5V / 1.35V) S3 Regulator

OC trip point:

Switching freq:

J17: 1.5V

J16: 1.35V

U7300

QFN

TPS51916

CRITICAL

1.0UH-27A-1.05MOHM

SDP1182-SM

CRITICAL

L7310

5%

1000PF

0402

CERM

25V

NOSTUFF

C7317

1% 1/10W

603

MF

NOSTUFF

R7317

0.499

25V X6S 0402

C7316

0.1UF

10%

5%

603

0

MF-LF

1/10W

R7316

OMIT

SM

L7310.2:10MM

XW7310

X5R-CERM-1 603

20%

22UF

CRITICAL

C7325

6.3V

OMIT

SM

C7325.1:6MM

XW7325

20%

CRITICAL

C7326

22UF

X5R-CERM-1

603

6.3V

U7300.21:4MM

SM

OMIT

XW7300

402

0.22UF

16V

CERM

C7327

10%

402

1/16W

R7335

1% MF-LF

1K

402

49.9K

R7331

1% 1/16W MF-LF

402

OMIT_TABLE

R7330

1/16W MF-LF

1%

10K

X7R-CERM

50V

0.01UF

0402

C7331

10%

X7R-CERM

16V

0402

C7330

0.1UF

10%

68

CRITICAL

330UF-0.009OHM

CASE-D2-HF

POLY

2V

20%

C7321

20%

CASE-D2-HF

POLY

2V

CRITICAL

330UF-0.009OHM

C7320

5%

1000PF

0402

CERM

25V

L7310.2:8MM

EMC

C7340

10UF

20%

603

C7301

6.3V X5R

2.2UF

16V 603

C7300

X5R

10%

5%

805

1/8W

MF-LF

R7300

2.2

68

5%

402

1/16W MF-LF

20K

R7340

70

10UF

603

20%

C7322

6.3V X5R

5%

1000PF

0402

CERM

25V

L7310.2:8MM

EMC

C7341

CRITICAL

Q7310

CSD58872Q5D

SON5X6

25V X6S-CERM

1UF

0402

C7342

10%

25V X6S-CERM

1UF

0402

C7343

10%

68

TH1

180UF

POLY

20% 16V

CRITICAL

C7310

POLY

CRITICAL

TH1

180UF

16V

20%

C7311

5%

0

1/10W MF-LF

R7311

603

402

MF-LF

1%

R7336

44.2K

1/16W

16V 0603

X6S-CERM

20%

10UF

C7344

X6S-CERM

16V

20%

10UF

0603

C7345

25V

EMC Q7310.1:3MM

1UF

0402

X6S-CERM

C7347

10%

25V

Q7310.1:3MM

EMC

1UF

X6S-CERM 0402

C7346

10%

22

VDDQ:P1V35114S0335

1

R7330

RES,16.5K,402

VReg VDDQ S3

SYNC_MASTER=J16_ROSSANA

SYNC_DATE=03/04/2013

VDDQ:P1V5

1

R7330

RES,10K,402

114S0315

=PP3V3_S4_PWRCTL

REG_VDDQS3_VDDQSNS

MAKE_BASE=TRUE

PM_PGOOD_REG_VDDQ_S3

REG_UGATE_VDDQS3

REG_VDDQS3_TRIP

REG_VDDQS3_REFIN

=PP5V_S4_REG_VDDQ_S3

REG_VDDQS3_VREF

AGND_VDDQS3

PM_EN_LDO_DDRVTT_S0

REG_PHASE_VDDQS3

REG_PHASE_VDDQS3_L

REG_SNUBBER_VDDQS3

REG_BOOT_VDDQS3_RC

REG_LGATE_VDDQS3

LDO_DDRVTTS0_SNS

REG_BOOT_VDDQS3

REG_UGATE_VDDQS3_R

REG_V5IN_U7300

REG_VDDQS3_PGOOD

REG_VDDQS3_VTTREF

PM_EN_REG_VDDQ_S3

REG_VDDQS3_MODE

=PPVDDQ_S3_LDO_DDRVTT

=PP12V_S5_REG_VDDQ_S3

PPVDDQ_S3_REG

PPDDRVTT_S0_LDO

MAKE_BASE=TRUE

REG_VDDQS3_REFIN

DDRREG_FB

REG_VDDQS3_PGOOD

051-0164

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1

2

11

2

1 2

2

1

1 2

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

6

9

4

3

5

8

7

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

67 70

82

63 82

70

82

63

82

70

63 82

63

OUT

BOOT

UGATE

LGATE

PHASE

RTN

FSEL

PGOOD

OCSET

VO

SREF

VCC

PVCC

GND

PGND

EN

FB

IN

OUT

IN

VSW

PGND

TGR

TG

BG

VIN

SS

ENABLE

GND

THRM

VIN

PG

VOUT

ADJ

ISET

PAD

OUT

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

To regulator:

1.5V S0 REGULATOR

Vout = 0.5 * (1 + Ra / Rb)

<Ra>

<Rb>

Vout = 0.5 * (1 + Ra / Rb)

500 kHz

1 MHz

FSEL STRAP

<Rb>

a minimum load to

audio frequencies

prevent noise in the

R7450 * 8.5 E-6

<Rb>

500 kHz

300 kHz

SW FREQ

<Ra>

Switching freq:

600 kHz

<Ra>

Note:

Regulator requires

VCC

GND

FLOAT

100k to GND

DCR(L7410)

OC trip point:

12.4 A =

PCH/TBT (1.05V) S0 REGULATOR

DCR(L7410) = 7.5 +/- 10% MOHM

64 70

402

11K

L7410.2:6MM

MF-LF

1/16W

1%

R7451

603-1

0.015UF

50V X7R

C7450

R7450.2:3MM

10%

402

11K

1/16W

1%

MF-LF

R7450

L7410.1:3MM

5%

R7417

2.2

NOSTUFF

603

1/10W MF-LF

10UF

603

20%

C7423

6.3V X5R

50V

0402

NOSTUFF

0.001UF

X7R-CERM

C7417

10%

16V 0402

X7R-CERM

C7416

0.1UF

10%

5%

R7416

1/10W

0

603

MF-LF

C7401

2.2UF

603

16V X5R

10%

5%

805

MF-LF

2.2

1/8W

R7401

5%

MF-LF

R7400

10

1/8W

805

402

C7400

16V

1UF

X5R

10%

UTQFN

CRITICAL

U7400

ISL95870

5%

402

R7460

0

NOSTUFF

1/16W MF-LF

402

MF-LF

1% 1/16W

3.01K

R7435

NO_XNET_CONNECTION=TRUE

402

MF-LF

R7430

3.01K

1/16W

1%

NO_XNET_CONNECTION=TRUE

68

0402

C7440

0.047UF

16V

X7R-CERM

10%

402

2.74K

R7436

MF-LF

1/16W

1%

5%

C0G-CERM

0402

C7430

10PF

50V

402

MF-LF

1/16W

R7431

2.74K

1%

SM

XW7400

U7400.1:1MM

68 69

5%

402

R7480

20K

1/16W MF-LF

64 70

CASE-D2-HF

POLY

330UF-0.009OHM

CRITICAL

2V

20%

C7421

POLY

2V CASE-D2-HF

20%

CRITICAL

330UF-0.009OHM

C7422

5%

R7411

1/10W

603

MF-LF

0

CRITICAL

SON5X6

CSD58872Q5D

Q7410

PIC0605H-SM

L7410

CRITICAL

1.2UH-14A-0.0075OHM

25V

Q7410.1:3MM

1UF

0402

C7480

X6S-CERM

EMC

10%

25V

EMC

C7481

Q7410.1:3MM

1UF

X6S-CERM 0402

10%

CRITICAL

C7411

0603

16V X6S-CERM

20%

10UF

C7412

10UF

20% X6S-CERM

16V 0603

CRITICAL

C7420

330UF-0.009OHM

CASE-D2-HF

20% POLY

2V

CRITICAL

20%

TH1

POLY

180UF

16V

C7410

5%

0402

10PF

C7435

50V C0G-CERM

ISL80101A

DFN

U7450

CRITICAL

10UF

X6S-CERM 0603

16V

20%

C7490

CRITICAL

C7493

20%

10UF

16V

CRITICAL

0603

X6S-CERM

0402

X7R-CERM

50V

4700PF

C7491

10%

402

MF-LF

1% 1/16W

20.0K

R7490

5% MF-LF

1/10W 603

200

R7418

5%

402

10K

R7493

1/16W MF-LF

402

2.61K

R7491

1% 1/16W MF-LF

402

1.3K

R7492

1% 1/16W MF-LF

5% C0G-CERM

150PF

0402

50V

C7492

68

70

XW7410

SM

NO_XNET_CONNECTION=TRUE

5%

1000PF

0402

CERM

25V

C7418

XW7411

SM

NO_XNET_CONNECTION=TRUE

C7495

20%

CRITICAL

X6S-CERM 0603

16V

10UF

C7494

20%

10UF

16V

CRITICAL

0603

X6S-CERM

VREG 1V05 S0 / 1V5 S0

SYNC_MASTER=J16_ROSSANA

SYNC_DATE=03/04/2013

REG_PHASE_P1V05S0_L

REG_BOOT_P1V05S0

PP1V05_S0_REG

REG_SNUBBER_P1V05S0

REG_P1V05S0_VO

PP1V05_S0_REG

REG_P1V05S0_FB

REG_P1V05S0_SREF

REG_P1V05S0_OCSET

REG_P1V05S0_PGOOD

REG_P1V05S0_FB_R

=PP3V3_S0_REG_P1V5_S0

REG_P1V5S0_ISET

PM_EN_FET_REG_P1V5_S0

REG_P1V5S0_SS

REG_P1V05S0_RTN_R

REG_UGATE_P1V05S0_R

=PP12V_S0_REG_P1V05_S0

REG_P1V05S0_FSEL

PM_EN_REG_P1V05_S0

REG_UGATE_P1V05S0

PM_PGOOD_REG_P1V05_S0 MAKE_BASE=TRUE

REG_PVCC_U7400

REG_P1V05S0_PGOOD

REG_LGATE_P1V05S0

=PP3V3_S0_VRD

REG_BOOT_P1V05S0_RC

REG_VCC_U7400

=PP5V_S0_REG_P1V05_S0

REG_P1V5S0_PGOOD

=PP3V3_S0_VRD

MAKE_BASE=TRUE

PM_PGOOD_FET_REG_P1V5_S0

REG_P1V5S0_ADJ

AGND_P1V05S0

REG_P1V5S0_PGOOD

REG_PHASE_P1V05S0

PP1V5_S0_REG

REG_P1V05S0_RTN

REG_P1V05S0_VO

REG_P1V05S0_OCSET

051-0164

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2

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1

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1

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2

1

2

1

2

1

12

11

15

10

2

5

9

7

8

4

13

14

1

16

3

6

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

6

9

4

3

5

8

7

1

21

2

1

2

1

2

1

2

1

2

1

2

1

6

7

5

11

9

4

2

1

10

3

8

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

82

64 82

82

64 82

64

70

84

82

70

82

64

82

60 61 64 70

82

70

64

60 61 64 70

84

82

64

82

64 82

PGOOD2

FCCM

VIN

FB1

FSET1

EN2

FSET2

BOOT2

THRM

PGND

EN1

FB2

VOUT2VOUT1

ISEN2ISEN1

OCSET1

OCSET2

LGATE1

LGATE2

PHASE2

BOOT1

UGATE1

LDO5

PGOOD1

VCC1

VCC2

UGATE2

PHASE1

PAD

OUT

IN

OUT

OUTOUT

IN

PHASE

S

G

S

D

N-CH

P-CH

IN

G

D

S

G

D

S

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

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A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

5V S4 Regulator

OC trip point:

Switching freq:

14.1 A =

DCR(L7650) = 6.2 MOHM (TYP) / 6.9 MOHM (MAX)

DCR(L7650)

170 E-12 * R7673

R7658 * 10 E-6

356 kHz =

1

R7618 * 10 E-6

DCR(L7610)

1

OC trip point:

12.5 A =

Switching freq:

356 kHz =

DCR(L7610) = 11.2 MOHM (TYP) / 12.5 MOHM (MAX)

(reg_p5vs4_isen)

3.3V S5 Regulator

(reg_phase_p3v3s5)

(reg_p5vs4_ocset)

This circuit toggles the Vreg

modes based on load requirements

DCM

PWM

0 1

Vreg Mode

BURSTMODE_EN_L

Vout = 0.6 * (1 + Ra / Rb)

<Rb>

<Ra>

(reg_p3v3s4_ocset)

<Ra>

<Rb>

(reg_p5vs4_vout)

Vout = 0.6 * (1 + Ra / Rb)

(reg_phase_p5vs4)

between PWM and ultrasonic DCM

(reg_p3v3s4_isen)

(reg_p3v3s4_vout)

170 E-12 * R7633

U7600

ISL62383CRTZ

QFN

CRITICAL

5%

R7656

1/10W 603

0

MF-LF

25V

C7656

X6S 0402

0.1UF

10%

C7657

NOSTUFF

0.001UF

50V X7R-CERM 0402

10%

R7657

603

MF

1/10W

1%

NOSTUFF

0.499

402

R7658

9.76K

1% 1/16W MF-LF

402

C7658

27.0NF

10V X5R

10%

402

R7659

MF-LF

1%

1/16W

9.76K

XW7650

L7650.2:3MM

OMIT

SM

C7675

NOSTUFF

0.001UF

50V X7R-CERM 0402

10%

402

R7670

MF-LF

1/16W

1%

75K

402

R7671

10K

1/16W MF-LF

1%

402

R7672

MF-LF

1/16W

976

1%

5%

1000PF

0402

CERM

25V

C7672

402

R7673

MF-LF

1/16W

1%

16.5K

402

R7633

1/16W MF-LF

16.5K

1%

402

R7630

1%

45.3K

MF-LF

1/16W

5%

1000PF

0402

CERM

25V

C7632

402

R7632

976

1%

MF-LF

1/16W

402

R7631

MF

1/16W

10.0K

0.5%

XW7610

L7610.1:6MM

SM

OMIT

L7610

CRITICAL

PAB0705AR-SM

2.2UH-10A-12.5MOHM

C7618

0402

16V

0.01UF

X7R-CERM

10%

402

R7618

1/16W MF-LF

1%

15.8K

402

R7619

1% MF-LF

1/16W

15.8K

5%

R7616

603

1/10W

0

MF-LF

25V

C7616

0402

X6S

0.1UF

10%

402

C7600

1UF

16V X5R

10%

402

C7602

16V

1UF

X5R

10%

402

C7603

1UF

16V X5R

10%

5%

R7602

2.2

1/8W MF-LF 805

70

C7601

CERM

20%

603

4.7UF

6.3V

5%

R7603

MF-LF

1/8W 805

1

68

5%

1000PF

0402

CERM

25V

C7640

L7610.1:8MM

EMC

402

C7617

CERM

0.001UF

NOSTUFF

50V

10%

R7617

0.499

603

1%

NOSTUFF

MF

1/10W

68

5%

402

R7680

20K

MF-LF

1/16W

5%

402

R7640

1/16W MF-LF

20K

69

70 70

68

5%

1000PF

0402

CERM

25V

C7680

L7650.2:4MM

EMC

C7620

B1A-SM-1

CRITICAL

20%

POLY

150UF

6.3V

C7621

B1A-SM-1

20%

CRITICAL

POLY

150UF

6.3V

C7622

20%

603

10UF

6.3V X5R

Q7610

CRITICAL

FDMS3602S

POWER56

C7662

20%

10UF

603

6.3V X5R

C7660

CRITICAL

20% POLY-TANT

330UF

CASE-D3L-SM

6.3V

L7650

2.2UH+/-20%-0.0069OHM-16A

PIC1005H-SM

CRITICAL

5%

1000PF

0402

CERM

25V

C7641

L7610.1:8MM

EMC

5%

1000PF

0402

CERM

25V

C7681

L7650.2:4MM

EMC

C7661

CASE-D3L-SM

330UF

POLY-TANT

20%

CRITICAL

6.3V

25V

C7682

EMC Q7650.5:3MM

X6S-CERM

1UF

0402

10%

25V

C7683

1UF

EMC Q7650.5:3MM

X6S-CERM 0402

10%

25V

C7643

1UF

EMC

Q7610.2:3MM

X6S-CERM

0402

10%

25V

C7642

Q7610.2:3MM

1UF

X6S-CERM

EMC

0402

10%

Q7600

SSM6L36FE

SOT563

NOSTUFF

45 60

5%

402

R7601

10K

MF-LF

NOSTUFF

1/16W

5%

402

R7600

1/16W MF-LF

1K

NOSTUFF

Q7655

FDMC0223S

CRITICAL

MLP3.3X3.3

Q7650

CRITICAL

MLP3.3X3.3

FDMC0225

C7610

TH1

CRITICAL

POLY

180UF

20% 16V

C7650

TH1

20% 16V POLY

180UF

CRITICAL

C7651

TH1

180UF

POLY

CRITICAL

20% 16V

C7633

0.01UF

X7R-CERM

16V 0402

10%

C7673

16V X7R-CERM

0.01UF

0402

10%

VReg 3.3V S5/5V S4

SYNC_DATE=03/04/2013

SYNC_MASTER=J16_ROSSANA

PP3V3_S5_REG

=PP12V_S5_REG_P3V3P5V_S5

REG_BOOT_P3V3S5_RC

REG_PHASE_P3V3S5

REG_P5VS4_FB

REG_P3V3S5_ISEN

REG_P3V3S5_OCSET

REG_BOOT_P3V3S5

REG_VCC1_U7600

MAKE_BASE=TRUE

PM_PGOOD_REG_P5V_S4

PM_PGOOD_REG_P3V3_S5

MAKE_BASE=TRUE

REG_VCC2_U7600

REG_BOOT_P5VS4

=PP5V_S5_PWRCTL

REG_U7600_FCCM

REG_SNUBBER_P5VS4

REG_P5VS4_VOUT_R

REG_P5VS4_PGOOD

REG_U7600_FCCM

=PP3V3_S5_VRD

REG_P3V3S5_PGOOD

REG_LGATE_P3V3S5

=PP5V_S5_PWRCTL

BURSTMODE_EN

BURSTMODE_EN_L

REG_P3V3S5_VOUT_R

REG_U7600_FCCM_R

BURSTMODE_EN

REG_BOOT_P5VS4_RC

REG_UGATE_P5VS4

REG_VIN_U7600

REG_P3V3S5_FSET

PP5V_S5_LDO

REG_P5VS4_PGOOD

REG_UGATE_P3V3S5

REG_P3V3S5_PGOOD

REG_LGATE_P5VS4

PP5V_S4_REG

REG_SNUBBER_P3V3S5

REG_P5VS4_ISEN

PM_EN_REG_P5V_S4

REG_P5VS4_FSET

PM_EN_REG_P3V3_S5

REG_PHASE_P5VS4

REG_P5VS4_OCSET

REG_P5VS4_VOUT

REG_P3V3S5_FB

REG_P3V3S5_VOUT

051-0164

12.4.0

76 OF 123

65 OF 86

1

3

17

8

6

24

2

21

29

19

12

28

279

26

10

11 25

16 20

23

15

14

18

7

5

4

22

13

1

2

1

2

1

2

1 2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

21

1 2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

22

1

6

1

345

7

2

11

2

21

2

1

2

1

2

1

2

1

2

1

2

1

4

5

2

1

3

6

1

2

12

5

1 2 3

4

5

1 2 3

4

1

2

1

2

1

2

1

2

1

70

84

65 67 70

65

84

65

65 70

65

84

65 67 70

65

84

65

84

65

84

65

84

S

G

D

PAD

ISENSE_GND

GD

VLDO

VDDIO

VIN

SD

VSYNC

SCLK

SDA

PWM

EN

OUT1

OUT2

OUT4

OUT3

OUT5

OUT6

ISENSE

FB

GND_S

GND_GD

GND_L

THRM

FILTER

ISET

IN

D

G S

IN

G

D

SYM-VER-2

S

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_5_ITEM

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

ACOUSTICS E-NOISE COMPONENTS

OMIT/table L8100 due to late sourcing change, did not want footprint change

Add 152s1668 (Cyntec) directly for next program

Q8100

DIRECTFET-SJ

CRITICAL

IRF6645PBF

50V

100PF

NOSTUFF

5% CERM

0402

C8137

C8131

0603

1UF

25V X7R

10%

0603

C8134

1UF

25V X7R

10%

50V CERM 603

4700PF

C8129

5%

0.01UF

C8132

16V

X7R-CERM

0402

10%

C8133

0.1UF

X7R-CERM

0402

16V

10%

0402

X7R-CERM

C8136

0.1UF

16V

10%

402

MF-LF

1/16W

1%

1M

R8110

R8111

330K

MF

1/8W

1%

0402

402

12.4K

1/16W

1% MF-LF

R8105

402

71.5K

1% 1/16W MF-LF

R8121

402

MF-LF

1/16W

1%

147K

R8120

NOSTUFF

1206

FB8108

FERR-600-OHM-3A

C0G-CERM

100PF

5%

0603-1

NOSTUFF

C8127

100V

5%

R8107

1/10W MF-LF

603

0

C0G-CERM

50V 603

5%

C8126

NOSTUFF

1000PF

C0G-CERM 0603

5%

100PF

C8120

100V

C0G-CERM 0603

C8121

5%

100PF

100V

C0G-CERM 0603

5%

C8122

100PF

100V

50V

330PF

C8130

0402

X7R-CERM

10%

402

1/16W

270K

5%

R8103

MF-LF

402

50V

NOSTUFF

CERM

5%

33PF

C8128

C0G-CERM

100V

5%

100PF

0603

C8123

C0G-CERM

C8124

0603

5%

100PF

100V

C0G-CERM

5%

0603

100PF

C8125

100V

1UF

805

25V

C8151

X7R

10%

C8152

25V 805

1UF

X7R

10%

C8153

1UF

25V 805

X7R

10%

C8154

25V 805

1UF

X7R

10%

402

MF-LF

5% 1/16W

0

R8122

SM

XW8102

402

1/16W MF-LF

10K

1%

R8123

OMIT_TABLE

U8100

LLP

LP8561B0SQ

CRITICAL

R8106

0

5%

1/8W

MF-LF

805

SM

XW8101

402

R8130

1/16W

1

MF-LF

5%

402

1

5% 1/16W MF-LF

R8131

402

R8101

MF-LF

5%

1/16W

0

402

R8100

1/16W

0

5%

MF-LF

402

0

MF-LF

5%

1/16W

R8140 NOSTUFF

40205%

R8141

1/16W MF-LF

NOSTUFF

47

0402

X6S

25V

0.1UF

C8171

NOSTUFF

10%

0

5% 1/10W MF-LF 603

R8124

XW8103

SM

XW8104

XW8105

SM

1/16W

0402 MF

R8104

1%

0.05

CRITICAL

R8108

0.05

2512

CRITICAL

MF

1W

1%

MF-LF

1%

1/10W

603

100K

R8150

5%

1206

MF-LF

1/4W

NOSTUFF

4.7

R8109

402

1/16W

R8152

5%

MF-LF

0

Q8101

NOSTUFF

SSM3K15AMFVAPE

VESM

40 66

X7R

100V

CRITICAL

C8140

1000PF

10%

0603

1206

CRITICAL

C8108

2.2UF

100V X7R

10%

CRITICAL

1206

2.2UF

C8109

100V X7R

10%

C8110

1206

2.2UF

CRITICAL

100V X7R

10%

C8111

CRITICAL

1206

2.2UF

100V X7R

10%

CRITICAL

C8112

1206

2.2UF

100V X7R

10%

1206

C8113

2.2UF

CRITICAL

100V X7R

10%

C8114

CRITICAL

1206

2.2UF

100V X7R

10%

C8115

CRITICAL

1206

2.2UF

100V X7R

10%

CRITICAL

C8116

1206

2.2UF

100V X7R

10%

1206

2.2UF

C8117

CRITICAL

100V X7R

10%

1206

CRITICAL

2.2UF

C8118

100V X7R

10%

C8119

CRITICAL

1206

2.2UF

100V X7R

10%

C8193

2.2UF

CRITICAL

1206

100V X7R

10%

2.2UF

CRITICAL

1206

C8194

100V X7R

10%

CRITICAL

TSOP

SI3440DVT1GE3

Q8105 Q8106

SI3440DVT1GE3

TSOP

CRITICAL

Q8107

CRITICAL

TSOP

SI3440DVT1GE3

TSOP

SI3440DVT1GE3

CRITICAL

Q8108 Q8109

TSOP

CRITICAL

SI3440DVT1GE3

CRITICAL

TSOP

Q8110

SI3440DVT1GE3

C0G-CERM

100V 0603

5%

C8160

33PF

F-RT-SM

CRITICAL

J8100

504050-1091

C8197

CRITICAL

1206

2.2UF

100V X7R

10%

2.2UF

1206

CRITICAL

C8190

100V X7R

10%

10% X7R

100V

2.2UF

CRITICAL

1206

C8191 C8192

2.2UF

1206

CRITICAL

100V X7R

10%

CRITICAL

1206

MF

0.005

1/4W

1%

R8112

0.01UF

16V

X7R-CERM

C8135

0402

10%

1206

CRITICAL

C8195

100V X7R

10%

2.2UF

NOSTUFF

1206

100V

10%

CRITICAL

C8199

2.2UF

X7R

C8198

2.2UF

10% 100V

NOSTUFF

CRITICAL

1206

X7R

10%

2.2UF

C8196

CRITICAL

1206

100V X7R

X7R

100V

CRITICAL

C8141

10%

1000PF

0603

X7R

100V

CRITICAL

C8142

10%

1000PF

0603

X7R

100V

C8143

CRITICAL

10%

1000PF

0603

X7R

100V

C8144

CRITICAL

10%

1000PF

0603

X7R

100V

CRITICAL

C8145

10%

1000PF

0603

DFN5X6

CRITICAL

AON6407_001

Q8102

0603-1

6AMP-32V

F8100

CRITICAL

SOD-323

D8101

SBR130S3

CRITICAL

0603

FB8100

CRITICAL

600-OHM-25%-0.5A-0.40OHM

CRITICAL

FB8101

600-OHM-25%-0.5A-0.40OHM

0603

FB8102

CRITICAL

600-OHM-25%-0.5A-0.40OHM

CRITICAL

0603

600-OHM-25%-0.5A-0.40OHM

FB8103

0603

FB8104

CRITICAL

600-OHM-25%-0.5A-0.40OHM

FB8105

0603

600-OHM-25%-0.5A-0.40OHM

CRITICAL

0603

600-OHM-25%-0.5A-0.40OHM

FB8106

0603

CRITICAL

600-OHM-25%-0.5A-0.40OHM

FB8107

402

NOSTUFF

R8153

MF-LF

1/16W

1%

10K

IHLP6767GZ-IHLP4040DZ11-SM

L8100

33UH-20%-10A-0.0351OHM

CRITICAL

OMIT_TABLE

C8100

10UF

0805

X6S

25V

10%

0805

X6S

10UF

C8101

25V

10%

0805

X6S

25V

C8102

10UF

10%

C8103

0805

X6S

10UF

25V

10%

25V X6S 0402

C8104

0.1UF

10%

C8105

25V X6S 0402

0.1UF

10%

NOSTUFF

C8106

0.1UF

X6S 0402

25V

10%

NOSTUFF

C8107

0402

X6S

25V

0.1UF

10%

D8100

POWERDI5-TO277A

PDS5100H

CRITICAL

371S0731371S0748

D8101

INPUT DIODE

138S0839 138S0745

2.2UF_CAP

BLC OUTPUT CAPS

138S0745138S0810

2.2UF_CAP

BLC OUTPUT CAPS

155S0797

ALL

155S0831

FB8100 to FB8107

376S1073

ALL

376S1071

Short Protection FET

CRITICAL152S1668

L8100

1

IND,PWR,33UH,20%,10A,35MOHM

BLC Fuse

F8100

740S0146740S0145

BLC Inrush FET

Q8102

376S1116376S1121

371S0694

BLC Switch Diode

D8100

371S0648

LCD Backlight Driver (LP8561)

SYNC_DATE=01/22/2013

SYNC_MASTER=J16_LINDA

PGND_BKLT

BKLT_ISET

BKLT_SCL

BKLT_ISEN3_RBKLT_ISEN2_R

=PP12V_S0_BKLT

BKLT_BOOST_1

LED_RETURN_4

LED_RETURN_5

LED_RETURN_6

PGND_BKLT

BKLT_FB

BKLT_SW_P

BKLT_GATE

BKLT_PHASE

LED_RETURN_3

PP12V_BKLT_FUSED

BKLT_BOOST_2

PGND_BKLT

PP12V_S0_BKLT_FILT

PP12V_S0_BKLT_PWR

BKLT_EN_DIV

PGND_BKLT

PP12V_S0_BKLT_PWR

BKLT_GATE_R

PP3V3_S0_BKLT_VDDIO_R

PP5V_S0_BKLT_R

GND

BKLT_ISEN6

DGND_BKLT

LVDS_BKLT_PWM_RC

BKLT_VSYNC

PP5V_S0_BKLT_R

=PP5V_S0_BKLT

BKLT_VSYNC_R

BKLT_FLT

BKLT_ISEN4

BKLT_ISEN3

BKLT_ISEN2

BKLT_ISEN5

BKLT_ISEN1

BKLT_ISEN1_R BKLT_ISEN4_R BKLT_ISEN5_R BKLT_ISEN6_R

BKLT_FLT_RC

DGND_BKLT

PGND_BKLT

=I2C_BKLT_SDA

LGND_BKLT

BKLT_EN

=I2C_BKLT_SCL

BKLT_BOOST

LGND_BKLT

BKLT_SW_N

LED_RETURN_1

BKLT_ISEN1_R

BKLT_ISEN5_R

BKLT_SW_R

PGND_BKLT

PP12V_BKLT_SNS

BKLT_EN_L

PP12V_S0_BKLT_PWR

BKLT_SHUTDOWN

=PP3V3_S0_BKLT_VDDIO

BKLT_ISEN4

PGND_BKLT

=SMB_DP_BLC_SDA

BKLT_ISEN1 BKLT_ISEN3 BKLT_ISEN5 BKLT_ISEN6

BKLT_SHUTDOWN

BKLT_SCL

BKLT_ISEN1

DGND_BKLT

BKLT_SW_N

BKLT_ISEN4

BKLT_VSYNC_R

BKLT_FB_R

PP3V3_S0_BKLT_VDDIO_R

BKLT_EN

PGND_BKLT

BKLT_SDA

PP12V_S0_BKLT_PWR_R

=SMB_DP_BLC_SCL

BKLT_ISEN2_R

BKLT_SNUBBER

BKLT_FB_XW

BKLT_ISEN2

PGND_BKLT

DGND_BKLT

BKLT_ISEN3_R

BKLT_SDA

PP12V_S0_BKLT_PWR_R

LED_RETURN_2

DGND_BKLT

BKLT_ISEN4_R

DGND_BKLT

BKLT_ISEN6_R

BKLT_BOOST

PGND_BKLT

PP12V_S0_BKLT_PWR

BKLT_BOOST

BKLT_ISEN6

BKLT_ISEN5

BKLT_ISEN2

BKLT_ISEN3

BKLT_BOOST

PGND_BKLT

PP12V_S0_BKLT_PWR

051-0164

12.4.0

81 OF 123

66 OF 86

6 71 2

43

5

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1 2

21

2

1

1 2

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

12

1

2

1

6

22823

7

19

10

11

2

4

12

13

16

14

17

18

24

21

9

5

15

25

20

3

1

2

12

1 2

2

1

2

12

1 2

1

2

1

2

1

2

1 2

1

2

3

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

5 63

4

2

1

5 63

4

2

1

5 63

4

2

1

5 63

4

2

1

5 63

4

2

1

5 63

4

2

1

11

1

4

3

2

5 6

9

8

7

10

12

2

1

2

1

2

1

2

1

1 2

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

4

5

3 2

21

K

A

21

1

2

21

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

3

2

66 86

86

66 86

70

86

66 86

86

66 86

86

66 86

86

66 86

40

66 86

70

66

86

66 86

86

66 86

86

66 86

86

66

86

66 86

66

70

66 86

66 86 66 86 66 86 66 86

66

66 86

66

86

66 86

86

66 86

86

66 86

66

86

66 86

IN

OUT

NC

OUT

NC

IN

GND

THRM

ON_MOS1

CAP_MOS1

5_VDD

MOS2_D

MOS2_S

CAP_MOS2

ON_MOS2

MOS1_D

MOS1_S

PAD

D

S

G

D

S

G

IN IN

ININ

OUT

G

PG

THRM

GND

NC

D

VCC

S

ON

PAD

OUT

IN

08

Y1

Y2

GND

B2

VCC

A1 B1 A2

IN

OUT

GND

VDD

D

SON

CAP

GND

VDD

D

SON

CAP

IN

GND

VDD

D

SON

CAP

OUT

ON

NC

S

VCC

D

PG

G

GND

THRM

PAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

12V S0 FET

VDDQ S0 FET

2.2V / ms ramp rate

4nF corresponds to

3.3V S0 FET3.3V S4 FET

3V3 S0 SSD

5V S0 FET

5V HDD FET

5V / 3V3 S0 PGOODs

Input: 2.4V to 5.5V

16V

10%

0.1UF

X7R-CERM 0402

C8420

67 68

67 70

10% X7R-CERM

0.1UF

16V 0402

C8400

70

X7R-CERM

16V 0402

C8430

0.1UF

10%

5% MF-LF

22K

R8430

1/16W 402

68 71

0.1UF

10% X7R-CERM

0402

16V

C8450

47K

402

MF-LF

1/16W

5%

R8452

5% 1/16W MF-LF 402

R8451

100K

70

68

CRITICAL

TDFN

SLG5AP439

U8400

649135PBF

CRITICAL

DIRECTFET_S3C

Q8450

CRITICAL

Q8430

649135PBF

DIRECTFET_S3C

68 67 68

0.0022UF

402

50V

10%

C8402

CERM

25V

10%

C8401

CERM 0402

0.0047UF

67 70 70

67 70

U8430

DFN

SLG5AP004

CRITICAL

25V

10%

0.0047UF

CERM 0402

C8421

70

10%

0.1UF

SSD:Y

16V X7R-CERM 0402

C8410

67 68

68

SOT833

U8440

4

8

74LVC2G08GT

CRITICAL

67 68

68

C8440

0402

10%

0.1UF

16V X7R-CERM

SSD:Y

SLG5AP304V

TDFN

CRITICAL

U8410

CRITICAL

TDFN

SLG5AP304V

U8420

10% 16V

0.1UF

X7R-CERM 0402

C8460

14 18

CRITICAL

TDFN

SLG5AP304V

U8460

70

C8411

0402

CERM

10% 25V

SSD:Y

0.0047UF

25V

10%

0.0047UF

CERM 0402

C8461

402

0

MF-LF

5% 1/16W

R8453

C8451

10%

0.022UF

X7R 50V

0402

CRITICAL

U8450

TDFN

SLG5AP036

FET-Controlled S0 and S4

SYNC_DATE=02/11/2013

SYNC_MASTER=J16_MAX

=PP12V_G3H_FET_P12V_S0

P12V_S0_FET_GATE_R

PM_EN_FET_P12V_S0

PP12V_S0_FET

PM_PGOOD_FET_P12V_S0

P12V_S0_FET_GATE

=PP12V_S5_PWRCTL

PPVDDQ_S0_FET

PM_EN_FET_P3V3_S0

=PP3V3_S4_PWRCTL

PM_PGOOD_FET_P5V_S0

P5V_S0_HDD_FET_RAMP

HDD_PWR_EN

PM_EN_FET_P3V3_S0

=PP5V_S4_FET_P5V_S0

PP5V_S0_FET

=PP3V3_S5_FET_P3V3_S4

PP3V3_S4_FET

PM_EN_FET_P3V3_S0

PP3V3_S0_SSD_FET

=PP5V_S0_FET_P5V_HDD

=PP3V3_S5_PWRCTL

PM_EN_FET_P3V3_S4

=PP5V_S4_PWRCTL

FET_RAMP_P3V3_S4

=PP3V3_S5_PWRCTL

P5V_S0_FET_RAMP

PM_EN_FET_P5V_S0

P3V3_S0_SSD_FET_RAMP

=PP3V3_S5_FET_P3V3_S0

PM_EN_FET_P5V_S0

PM_EN_FET_P1V35_S0

PM_PGOOD_FET_P3V3_S0

=PP3V3_S0_PWRCTL

PM_PGOOD_FET_P1V35_S0

P1V5_S0_FET_GATE

=PPVDDQ_S3_FET_VDDQ_S0

PP5V_S0_FET

PP3V3_S0_FET

=PP5V_S0_FET_P5V_HDD

PP5V_S0_HDD_FET

FET_RAMP_P3V3_S0

=PP3V3_S5_FET_P3V3_S0

PP3V3_S0_FET

=PP5V_S5_PWRCTL

051-0164

12.4.0

84 OF 123

67 OF 86

2

1

2

1

2

1

2

1

2

1

2

11

15

3

12

4

6

8

10

5

1

13

1

2

8

3

5

6

7

4

1

2

8

3

5

6

7

4

2

1

2

1

7

8

9

4

3

5

1

6

2

1

2

1

3

71 2 5 6

2

1

8 1

3

52

7

8 1

3

52

7

2

1

8 1

3

52

7

2

1

2

1

2

1

2

3

6

1

5

8

7

4

9

70

68 70

63 70

70

67 70

67 68 69 70 70

67 68 69 70

67 70

70

67 70

65 70

OUT

08

IN

08

IN

OUT

IN

OUT

08

IN

OUT

IN

08

OUT

IN

OUT

IN

OUT

IN

D

G S

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

08

OUT

IN

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_5_ITEM

REFERENCE DESIGNATOR(S)

BOM OPTION

TABLE_5_HEAD

QTY

DESCRIPTION

PART#

Remove Q8500 to circumvent

S4 Enables

Note:

or short gate to source.

S5 Enable

5. PEX_VDD with IFPC/D/E/F_IOVDD (1.05V) must ramp after VDDQ

S0 Enables

1. No hard specification on platform rails

2. SMC guarantees timing on PCH DPWROK and PWROK

3. VCC3_3 may power up before VCC, VCC must ramp to 0.6V within 25ms of VCC3V3 ramping to 2.6V

5. VCC may power down before VCC3_3, VCC3_3 must ramp down to 2.6V within 35ms

6. VCC may power down before VCC1_5, VCC1_5 must ramp down to 1.35V within 35ms

4. VCC1_5 may power up before VCC, VCC must ramp to 0.6V within 25ms of VCC1V5 ramping to 1.35V

All processor non-Core and non-Graphics (5 V, 3.3 V, 1.5 V, 1.05V for PCH/TBT/GPU)

0.0

Halt power sequencing at S5 if there is no processor.

0.0

VDDQ

NVIDIA:

Uncore:

Intel:

1. 3V3_S0 must ramp first

Platform:

tau (RC delay, ms):

S4 USB Enable

Notes on sequencing requirements

4. VDDQ MUST RAMP AFTER GPU_CORE

6. All rails must reach their target voltages in more than 40 uS

Rail definitions

S3 VDDQ Enable

S4 TBT S4 Port Enable

S0 PCH Sequencing

S0 GPU SEQUENCING(J17 ONLY)

1/16W MF-LF 402

5%

68K

R8590

1/16W

33K

5%

402

MF-LF

R8591

10%

0.1UF

0402

X7R-CERM

16V

C8500

67

10%

6.3V

0.47UF

CERM-X5R 402

NOSTUFF

C8510

10%

6.3V 402

CERM-X5R

0.47UF

NOSTUFF

C8511

14

7

U8500

74LVC08

TSSOP-HF

402

MF-LF

33K

1/16W

5%

R8502

10%

6.3V

C8501

0.47UF

NOSTUFF

402

CERM-X5R

67

74LVC08

TSSOP-HF

U8500

7

14

12 44

65 68

63

1/16W

5%

0

402

MF-LF

R8520

65 68 42 43

10%

6.3V

0.47UF

NOSTUFF

402

C8520

CERM-X5R

R8510

33

5% MF-LF

402

1/16W

R8511

402

33

1/16W

5% MF-LF

65

72

67

U8500

TSSOP-HF

74LVC08

7

14

63

12 21 36 44 45 69

R8530

1/16W MF-LF

402

100

5%

67

12 32 44

71

1/16W

402

5%

R8501

10K

MF-LF

J17

100K

402

5%

R8500

MF-LF

1/16W

74LVC08

TSSOP-HF

PLACE_SIDE=BOTTOM

U8500

7

14

29 30

J17

402

0

R8537

5% 1/16W MF-LF

67 68

64

OMIT_TABLE

R8533

1.5K

MF-LF

5%

1/16W

402

67 68

61 68

R8535

1/16W MF-LF

5%

0

402

64 69

VESM

SSM3K15AMFVAPE

J17

Q8500

PLACE_SIDE=BOTTOM

72

1/16W

0

5%

402

MF-LF

R8538

J17

72

67

R8531

0

MF-LF

402

5%

1/16W

67

63 21

29

30

26 27 28 29 30 70

68

61 68

R8534

402

MF-LF

1/16W

5%

0

NOSTUFF

64

CKPLUS_WAIVE=UNCONNECTED_PINS

TSSOP-HF

74LVC08

CKPLUS_WAIVE=UNCONNECTED_PINS

U8600

7

14

10%

6.3V 402

NOSTUFF

CERM-X5R

0.47UF

C8522

64

C8523

CERM-X5R

NOSTUFF

402

0.47UF

6.3V

10%

5% 1/16W MF-LF

0

402

R8536

68

65

67

MF-LF

5%

J16

0

402

1/16W

R8513

72

R8515

402

1/16W

5%

MF-LF

0

J17

R8514

0

J16

402

MF-LF

1/16W

5%

67 71

J16

C8524

1UF

X6S-CERM 0402

10% 10V

RES,0OHM,0402,5%

1

116S0004

R8533

J17

RES,1.5K,0402,5%

116S0070

1

R8533

J16

PM Regulator Enables

SYNC_DATE=02/21/2013

SYNC_MASTER=J16_AARON

PM_EN_REG_GPUCORE_S0

PM_EN_REG_GPU_VDDQ_S0

PM_PGOOD_FET_P3V3_S0

PM_EN_FET_REG_P1V5_S0

PM_EN_FET_P1V35_S0

PM_PGOOD_FET_P3V3_S0

=TBTAPWRSW_EN

PM_PGOOD_FET_REG_P1V5_S0

PM_PGOOD_REG_GPU_VDDQ_S0

PM_PGOOD_FET_P1V35_S0

PM_PGOOD_REG_GPU_P1V35_S0

PM_EN_REG_P1V05_S0_R

MEMVTT_EN

MAKE_BASE=TRUE

PM_EN_LDO_DDRVTT_S0

PM_EN_REG_CPUVCC_S0

PM_EN_S0_R

=TBT_S0_EN

PU_U8500

PM_EN_FET_P5V_S0

MAKE_BASE=TRUE

=PP3V3_S5_PWRCTL

PM_EN_REG_P1V05_S0

=PP3V3_S5_PWRCTL

PM_EN_REG_VDDQ_S3

PM_PGOOD_REG_P5V_S4

PM_SLP_S4_L

CPU_SKTOCC_L

=PP3V3_S5_PWRCTL

PM_SLP_S5_L

=PP12V_S5_PWRCTL

PM_PGOOD_FET_P12V_S5

PM_SLP_S3_L

PM_EN_FET_P12V_S0

PM_PGOOD_REG_P5V_S4

MAKE_BASE=TRUE

PM_EN_REG_P3V3_S5

PM_EN_FET_P3V3_S4

=TBTBPWRSW_EN

=PP3V3_S4_TBT

=PP3V3_S5_PWRCTL

PM_EN_USB_PWR

=PP3V3_S5_PWRCTL

PM_PGOOD_REG_VDDQ_S3

PM_EN_REG_CPUVCC_S0

PM_PGOOD_REG_P1V05_S0

PM_EN_REG_P5V_S4

PM_EN_S4

CPU_SKTOCC

PM_EN_REG_P1V05_S0_R

PM_PGOOD_FET_P12V_S0

PM_EN_FET_P3V3_S0

PM_PGOOD_FET_P5V_S0

PM_PGOOD_REG_GPUCORE_S0

051-0164

12.4.0

85 OF 123

68 OF 86

1

2

1

2

1

2

1

2

1

11

12

13

1

2

1

6

5

4

1 2

2

1

2

1

2

8

9

10

1 2

1

2

1

2

3

2

1

1 2

1

2

3

1 2

8

9

10

2

1

2

1

1 2

2

1

67 68 69 70

67 70

60

67 68 69 70

OUT

IN

OUT

08

IN

OUT

08

OUT

B

Y

A

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Delay=10ms

5ms minimum after all rails are valid

ALL_SYS_PWRGD must remain low for

To SMC, for 99ms delay

Third

To PCH

Second

To PCH

Second

event AC is lost. Power good de-assertion should happen quickly enough

RSMRST# is asserted when power good from regulator is de-asserted in the

PCH Power Goods

To SMC

The SMC guarantees proper assertion and de-assertion of RSMRST# for

To PCH

Intel Doc# 29517 Maho Bay PDG, Section 22.13

to allow PCH to switch suspend well to battery without excessive loading

Note:

Resume Reset

Power on:

Asserted at least 10 ms after all suspend well power is valid

RSMRST# signals are shorted together

The iMac J16/J17 designs does not support Deep Sx modes so both DPWROK and

Requirements:

From SMC

to meet Intel spec.

Intel Doc# 29562 Panther Point EDS, Section 8.7 and 8.8

Method:

Power off or loss of AC:

Transition to 0.8V or less before VccSUS3_3 drops to 2.90 V

normal operation via PM_DSW_PWRGD.

ALL_SYS_PWRGD,PCH_PWROK & SYS_PWROK Generation

44 65 69

44 45

65 69

12 18

MF-LF

1/16W

402

0

5%

R8635

CKPLUS_WAIVE=UNCONNECTED_PINS

TSSOP-HF

74LVC08

U8600

7

14

CKPLUS_WAIVE=UNCONNECTED_PINS

0.1UF

CERM

BYPASS=U8600:5MM

20% 10V

402

C8620

61

28 44 45

12

12 18 20 39

10%

0.1UF

16V X7R-CERM 0402

NO STUFF

C8621

R8624

10K

MF-LF

1/16W

5%

402

14

7

U8600

TSSOP-HF

74LVC08

PLACE_SIDE=BOTTOM

14

7

CKPLUS_WAIVE=UNCONNECTED_PINS

74LVC08

U8600

TSSOP-HF

10%

X5R

6.3V

402

2.2UF

BYPASS=U8600:5MM

C8622

3

21 44

402

MF-LF

R8622

1/16W

5%

NO STUFF

0

R8621

MF-LF

5%

1/16W

402

0

201

R8625

1/20W

MF

5%

PLACE_NEAR=U1100.W31:7MM

1K

12 18 45

U8601

PLACE_SIDE=BOTTOM

74LVC1G08GW

SOT353

64 68

12 21 36 44 45 68

0.1UF

402

CERM

10V

20%

BYPASS=U8601:5MM

C8605

SYNC_DATE=02/21/2013

PM Power Good

SYNC_MASTER=J16_AARON

PM_RSMRST_PCH_L_R

PM_DSW_PWRGD

PM_PGOOD_REG_P3V3_S5

PM_RSMRST_PCH_L

S5_PWRGD

PM_PGOOD_REG_P3V3_S5

MAKE_BASE=TRUE

PM_PCH_PWROK

PM_PGOOD_ALL

SMC_DELAYED_PWRGD

PM_PCH_APWROK

PM_PCH_SYS_PWROK

PM_PCH_SYS_PWROK_R

PM_PGOOD_REG_CPUVCC_S0

MAKE_BASE=TRUE

ALL_SYS_PWRGD

=PP3V3_S5_PWRCTL

PM_PGOOD_SLP_S3_P1V05_S0

PM_PGOOD_REG_P1V05_S0

PM_SLP_S3_L

=PP3V3_S5_PWRCTL

051-0164

12.4.0

86 OF 123

69 OF 86

1 2

3

2

1

2

1

2

1

2

6

5

4

11

12

13

2

1

121

2

1 2

4

3

1

2

5

2

1

67 68 69 70

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

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PAGE

12

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C

PAGE TITLE

SHEET

R

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SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Thunderbolt Rails (S0)

Enabled when system is in run

S0 Rails

S4 Rails

Enabled when system has AC and is in run or sleep

S5 Rails

Enabled when system has AC and is in S5

Enabled when system is in run or sleep

S3 Rails

Ground/Common

G3 Rails

Always on: Keeps the PCH RTC alive

G3H Rails

Enabled when Thunderbolt cable is plugged in

Power Aliases

SYNC_MASTER=J16_MAX

SYNC_DATE=02/11/2013

=PP3V3_S0_PCH_GPIO

=PP3V3_S4_AUDIO_DIG

PPVDDQ_S0_FET =PPVDDQ_S0_SNS_R

PPVDDQ_S0_SNS =PP1V5_S3_CPU_VCCDDR

MAKE_BASE=TRUE

PPVDDQ_S0_CPU

PPVDDQ_S0

MAKE_BASE=TRUE

PP3V3_S0

MAKE_BASE=TRUE

=PP3V3_S0_REG_P1V5_S0

=PP3V3_S0_ENET

=PP3V3_S0_INTDPMUX

=PP3V3_S0_PCH

=PP3V3_S0_PCH_VCC3_3_GPIO

=PP3V3_S0_VRD

=PP3V3_S0_FAN

=PP3V3_S0_LED =PP3V3_S0_LED_SATA

=PP3V3_S4_LED

=PP3V3_S4_PWRCTL

=PP3V3_S4_FET_ENET

PP3V3_S4_FET

=PP12V_S0_LCD

=PP12V_S0_FAN

=PP12V_S0_BKLT

=PP12V_S0_AUDIO_SPKRAMP

PP12V_S0

MAKE_BASE=TRUE

=PP5V_S0_REG_CPUVCC_S0

=PP5V_S0_AUDIO

=PP5V_S0_REG_P1V05_S0

=PPHDD_S0_SNS_R

=PP5V_S0_SATA

=PP5V_S4_CAMERA

PP5V_S5_LDO

=PP3V3_G3H_BT

PP3V42_G3H_REG

=PP5V_S4_FET_P5V_S0

=PP5V_S4_REG_VDDQ_S3

PP5V_S4_REG

PP12V_G3H

MAKE_BASE=TRUE

=PP12V_G3H_FET_P12V_S0

=PP3V3_G3H_SMC

PPVDDQ_S3

MAKE_BASE=TRUE

=PPVDDQ_S3_SNS_DDR_R

=PP1V05_S0_P1V05TBTFET

PP1V05_S0_REG

=PP1V05_S0_PCH_VCC

=PP1V05_S0M_PCH_VCCASW

MAKE_BASE=TRUE

PP1V05_TBTCIO

=PP3V3_TBTLC_RTR =PPVDDIO_TBT_CLK

=PP1V05_TBTLC_FET =PP1V05_TBTLC_RTR

=PP1V05_TBTCIO_FET =PP1V05_TBTCIO_RTR

PP3V3_G3_RTC

MAKE_BASE=TRUE

PP3V3_S4_AP

PP3V3_ENET

MAKE_BASE=TRUE

PPVDDQ_S3_DDR

MAKE_BASE=TRUE

PP3V3_S4_SNS =PP3V3_S4_AP

PP3V3_ENET_FET

=PP3V3_ENET_SYSCLK

=PP3V3_ENET_PHY

=PPVDDIO_ENET_CLK

=PPVDDQ_S3_FET_VDDQ_S0

PPVDDQ_S3_REG

=PPVDDQ_S3_LDO_DDRVTT

PPVDDQ_S3_SNS_DDR

=PPVDDQ_S3_MEM_A

=PPDDR_S3_MEMVREF

=PPVDDQ_S3_MEM_B =PPVDDQ_S3_MEMRESET

PP5V_S4

MAKE_BASE=TRUE

=PP5V_S4_MEMRESET

=PP5V_S4_USB

=PP3V3_S4_PM =PP3V3_S4_SDCARD =PP3V3_S4_SMC

=PP3V3_S4_TBT

=PP3V3_S4_SMBUS_SMC_2

=PP3V3_S4_CAMERA

=PP3V3_S3_VREFMRGN

=PP3V3_S4_SNS_R

PP12V_ACDC

MAKE_BASE=TRUE

=PP12V_G3H_SNS_R

=PP12V_G3H_REG_3V42_G3H =PP12V_G3H_FET_P12V_S5

=PP3V3_G3H_RTC_D =PPVIN_G3H_SMCVREF =PP3V3_G3H_SMC_USBMUX =PP3V3_G3H_LPCPLUS

=PP3V3_S0_P3V3TBTFET

=PP3V3_S0_AUDIO =PP3V3_S0_AUDIO_DIG

PPSSD_S0_SNS

MAKE_BASE=TRUE

PPSSD_S0

=PP3V3_S0_SSD

PP3V3_S0_SSD_FET

PP3V3_S0_SSD

MAKE_BASE=TRUE

=PPSSD_S0_SNS_R

PP3V3_S4

MAKE_BASE=TRUE

PP12V_G3H_SNS

=PPVRTC_G3_PCH

MAKE_BASE=TRUE

PP3V3_G3

=PP3V3_S3RS4_PCH_GPIO

=PP3V3_S4_MEMRESET

=PP3V3_S4_ALS

MAKE_BASE=TRUE

PP12V_S5 PP12V_S5_FET

=PP12V_S5_REG_P3V3P5V_S5 =PP12V_S5_REG_VDDQ_S3 =PP12V_S5_PWRCTL =PPHV_SW_TBTAPWRSW

=PP12V_S5_SNS

=PPHV_SW_TBTBPWRSW

=PP5V_S5_PWRCTL

=PP3V3_S5_FET_P3V3_S4

=PP3V3_S5_LED =PP3V3_SUS_PCH_VCCSUS_GPIO

=PP3V3_SUS_PCH_VCC_SPI =PP3V3R1V5_S0_PCH_VCCSUSHDA =PP3V3_SUS_PCH_VCCSUS_USB

=PP3V3_SUS_PCH_VCCSUS_USB3

=PP3V3_SUS_PCH_VCCSUS_RTC

=PP3V3_S5_PCH =PP3V3_S5_ROM =PP3V3_S5_SENSE =PP3V3_S5_SMC

=PP3V3_S4_TBTAPWRSW

=PP3V3_S5_XDP

=PP3V3_S5_PWRCTL =PP3V3_S5_VRD

=PP3V3_S5_PCH_VCCDSW

PP3V3_S5_REG

=PP3V3_S5_PCH_GPIO

=PP3V3_S4_TBTBPWRSW

MAKE_BASE=TRUE

PP3V3_S5

=PP3V3_S5_SNS =PP3V3_SUS_PCH_GPIO

PPDDRVTT_S0

MAKE_BASE=TRUE

PP5V_S5

MAKE_BASE=TRUE

=PP3V3_S5_FET_P3V3_S0

=PP5V_S4_PWRCTL

=PP12V_S0_REG_P1V05_S0

=PP12V_S0_REG_CPUVCC_S0

PP12V_S0_FET

PP5V_S0

MAKE_BASE=TRUE

PP5V_S0_FET

=PP5V_S0_LPCPLUS

=PP5V_S0_FET_P5V_HDD

=PPSPD_S0_MEM_B

=PPSPD_S0_MEM_A

=PP3V3_S0_BKLT_VDDIO

=PP3V3_S0_TBTPWRCTL

=PP3V3_S0_SMC

=PP3V3_S0_SMBUS_SMC_3

=PP3V3_S0_SMBUS_SMC_1

=PP3V3_S0_SMBUS_SMC_0

=PP3V3_S0_SMBUS

=PP3V3_S0_SENSE

=PP3V3_S0_SDCARD

=PP3V3_S0_RSTBUF

=PP3V3_S0_PCH_VCC3_3_USB

=PP3V3_S0_PCH_VCC_FUSE

=PP3V3_S0_PCH_VCC3_3_HVCMOS

=PP3V3_S0_PCH_VCCCLK3_3

=PP3V3_S0_PCH_VCC3_3_THRM

=PP1V5_S0_AUD_DIG

MAKE_BASE=TRUE

PP1V5_S0

=PP1V5R1V35_S0_CPU

=PP5V_S0_BKLT

=PP5V_S0_ISENSE

PP3V42_G3H

MAKE_BASE=TRUE

PP12V_G3H_ACDC

PP5V_S0_HDD_FET

MAKE_BASE=TRUE

PPHDD_S0

MAKE_BASE=TRUE

PP5V_S0_HDD

PP3V3_S0_FET

=PP3V3_S0_PWRCTL

=PP3V3_S0_DP

PP1V05_TBTLC

MAKE_BASE=TRUE

=PP3V3_TBT_PCH_GPIO

=PP3V3_TBTLC_FET

PPCPUVCC_S0_REG =PPCPUVCC_S0_CPU =PPVCC_S0_CPU

MAKE_BASE=TRUE

PP3V3_TBTLC

MAKE_BASE=TRUE

PPCPUVCC_S0_CPU

PPHDD_S0_SNS

=PP1V05_S0_PCH_VCCIO

=PP1V05_S0_PCH_VCCCLK_CLK100

=PP1V5_S0_PCH_CLK

=PP1V5_S0_PCH_SATA

=PP1V5_S0_PCH_RCOMP

=PP1V5_S0_PCH_VCCVRM

=PP1V5_S0_SENSE

PP1V5_S0_REG

=PP1V05_S0_PCH_VCCIO_GPIO

=PP1V05_S0_PCH_VCCIO_USB2

=PP1V05_S0_PCH_VCCCLK_CLK135

=PP1V05_S0_PCH_VCCCLK_SSC100

=PP1V05_S0_PCH_VCCUSBPLL

=PP1V05_S0_PCH_VCCCLK_SSC

=PP1V05_S0_PCH_VCCIO_FDI

=PP1V05_S0_PCH_VCC_CLK

=PPDDRVTT_S0_MEM_B

=PPDDRVTT_S0_MEM_A

=PPDDRVTT_S0_CLAMP

PPDDRVTT_S0_LDO

PP1V05_S0

MAKE_BASE=TRUE

=PP1V05_S0_PCH_V_PROC_IO =PP1V05_S0_SNS

=PP1V05_S0_XDP

=PP1V05_S0_SMC

GND

MAKE_BASE=TRUE

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36

67

40

51

66

54 55

84

61 62

52 59

64

48

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38

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32

60

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67

44 45 51

82

49

28

64

15 17

82

26 27 28

19

28

27

28

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82

48

32 45

36

19

35 36

19

67

63

49

23

22

24

21

84

21

42 43

21

37

45

26 27 28 29 30 68

47

38 39

22

48

84

48

60

19

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42

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56

49 84

33

67 84

49

84

48

11 12 15

84

13

21

38

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65

63

67 68

29

48

30

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67

3

15 17

15

15 17

19 20

46

48

45

29

18

67 68 69

65

15 17

65

12

30

84

49

11 12 13 14

82

84

67

64

62

67

84 67

46

67

24

23

66

28

45

47

34 48 49 50

37

20

15 17

52

84

8

10

66

48

84

60

67 84

84

67

31 40 47

28 82

20

28

62

48 61

6 8

10

84

83

48

15 17

11 19

11

12 13

17

34

64

15

15 17

17

24

23

21

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45

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

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THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

UNUSED CPU SOCKET

MEMORY PGOOD

Display Aliases

Signal Aliases

SYNC_MASTER=J16_MAX

SYNC_DATE=02/11/2013

DP_TBTSNK0_ML_C_N<3..0>

MAKE_BASE=TRUE

DP_INT_DDC_DATA

MAKE_BASE=TRUE

DP_INT_ML_P<3..0>

MAKE_BASE=TRUE

DP_TBTSNK1_AUXCH_C_P

DP_TBTSNK1_ML_C_N<3..0>

MAKE_BASE=TRUE

=PM_PGOOD_MEM_S0

MAKE_BASE=TRUE

CPU_SKTOCC_L_ALIAS

CPU_SKTOCC_L

TP_DP_IG_B_MLP<3..0>

DP_INT_ML_N<3..0>

MAKE_BASE=TRUE

TP_DP_IG_B_AUXCHP

TP_DP_IG_B_AUXCHN

TP_DP_IG_B_MLN<3..0>

REG_ISENVCC_4_NR

MAKE_BASE=TRUE

AGND_CPU

TP_DP_IG_D_MLP<3..0>

TP_DP_IG_C_MLN<3..0>

MAKE_BASE=TRUE

DP_TBTSNK1_HPD

TP_DP_IG_D_HPD

TP_DP_IG_D_AUXCHN

TP_DP_IG_D_AUXCHP

TP_DP_IG_D_MLN<3..0>

TP_DP_IG_C_AUXCHP

TP_DP_IG_B_DDC_CLK

DP_TBTSNK0_AUXCH_C_N

MAKE_BASE=TRUE

TP_DP_IG_C_DDC_DATA

TP_DP_IG_C_DDC_CLK

TP_DP_IG_D_DDC_CLK

TP_DP_IG_D_DDC_DATA

DP_INT_HPD

MAKE_BASE=TRUE

DP_INT_DDC_CLK

MAKE_BASE=TRUE

DP_INT_AUX_P

MAKE_BASE=TRUE

TP_DP_IG_B_HPD

TP_DP_IG_C_MLP<3..0>

TP_DP_IG_C_HPD

TP_DP_IG_B_DDC_DATA

MAKE_BASE=TRUE

DP_TBTSNK0_AUXCH_C_P

DP_INT_AUX_N

MAKE_BASE=TRUE

TP_DP_IG_C_AUXCHN

DP_TBTSNK0_DDC_DATA

MAKE_BASE=TRUE

DP_TBTSNK0_ML_C_P<3..0>

MAKE_BASE=TRUE

DP_TBTSNK0_HPD

MAKE_BASE=TRUE

PM_PGOOD_FET_P1V35_S0

MAKE_BASE=TRUE

DP_TBTSNK0_DDC_CLK

MAKE_BASE=TRUE

DP_TBTSNK1_ML_C_P<3..0>

DP_TBTSNK1_DDC_DATA

MAKE_BASE=TRUE

DP_TBTSNK1_DDC_CLK

MAKE_BASE=TRUE

DP_TBTSNK1_AUXCH_C_N

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41 85

12

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THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

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THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PCH Miscellaneous

PCH PCI

UNUSED IG DISPLAY

PCH GPIO

UNUSED VREG ALIASES

UNUSED GPU ALIASES

CPU Memory

CPU Reserved

UNUSED PEG ALIASES

UNUSED GRAPHICS ALIASES

UNUSED THUNDERBOLT ALIASES

SYNC_MASTER=J16_MAX

Unused Signal Aliases

SYNC_DATE=02/11/2013

TP_CPU_CFG<15..12>

MAKE_BASE=TRUE

TP_TBT_PCIE_RESET2_L

TP_TBT_PCIE_RESET1_L

TP_GPU_RESET_L

NC_TBT_PCIE_RESET1_L

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PM_PGOOD_REG_GPUCORE_S0

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_TBT_PCIE_RESET0_L

PM_PGOOD_REG_GPU_VDDQ_S0

PM_EN_REG_GPU_VDDQ_S0

CPU_CFG<15..12>

PM_PGOOD_REG_GPUCORE_S0

PM_EN_REG_GPUCORE_S0

=PEG_R2D_C_P<0..15>

=PEG_R2D_C_N<0..15>

MAKE_BASE=TRUE

NC_PEG_R2D_C_P<0..15>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PM_EN_REG_GPU_VDDQ_S0

NC_PM_EN_REG_GPUCORE_S0

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PM_PGOOD_REG_GPU_VDDQ_S0

MAKE_BASE=TRUE

NO_TEST=TRUE

TP_TBT_PCIE_RESET3_L

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_REG_ISENVCC_4P

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_REG_PWM_CPUVCC_4

REG_PWM_CPUVCC_4

TP_TBT_THERM_DP

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_TBT_THERM_DP

NC_TBT_PCIE_RESET2_L

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_TBT_PCIE_RESET0_L

MAKE_BASE=TRUE

NC_TP_GPU_RESET_L

NO_TEST=TRUE

=PEG_D2R_P<0..15>

=PEG_D2R_N<0..15>

NO_TEST=TRUE

NC_PEG_D2R_P<0..15>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PEG_D2R_N<0..15>

REG_ISENVCC_4_P

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PEG_R2D_C_N<0..15>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_TBT_PCIE_RESET3_L

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_MEM_A_CLKP<2..3>

MEM_A_CLK_P<2..3>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_MEM_A_CS_L<2..3>

MEM_A_CS_L<2..3>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_MEM_A_CLKN<2..3>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MEM_B_CLKN<2..3>

MEM_B_CLK_N<2..3>

NC_MEM_B_CLKP<2..3>

MAKE_BASE=TRUE

NO_TEST=TRUE

MEM_B_CLK_P<2..3>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MEM_B_CS_L<2..3>

MEM_B_CS_L<2..3>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_MEM_A_CKE<2..3>

MEM_A_CKE<2..3>

MAKE_BASE=TRUE

NC_MEM_B_CKE<2..3>

NO_TEST=TRUE

MEM_B_CKE<2..3>

NC_MEM_A_ODT<2..3>

NO_TEST=TRUE

MAKE_BASE=TRUE

MEM_A_ODT<2..3>

NO_TEST=TRUE

NC_MEM_B_ODT<2..3>

MAKE_BASE=TRUE

MEM_B_ODT<2..3>

MEM_A_CLK_N<2..3>

NC_PCH_GPIO64_CLKOUTFLEX0

MAKE_BASE=TRUE

NO_TEST=TRUE

TP_PCH_GPIO64_CLKOUTFLEX0

NC_PCH_GPIO66_CLKOUTFLEX2

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_PCH_GPIO66_CLKOUTFLEX2

NO_TEST=TRUE

NC_PCH_GPIO67_CLKOUTFLEX3

MAKE_BASE=TRUE

TP_PCH_GPIO67_CLKOUTFLEX3

NC_PCH_GPIO65_CLKOUTFLEX1

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_PCH_GPIO65_CLKOUTFLEX1

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_DP_IG_A_MLP<3..0>TP_DP_IG_A_MLP<3..0>

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_DP_IG_A_MLN<3..0>TP_DP_IG_A_MLN<3..0>

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_DP_IG_A_AUXCHPTP_DP_IG_A_AUXCHP

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_DP_IG_A_AUXCHNTP_DP_IG_A_AUXCHN

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_HDA_SDIN2TP_HDA_SDIN2

NO_TEST=TRUE

NC_LPC_DREQ0_L

MAKE_BASE=TRUE

TP_LPC_DREQ0_L

NO_TEST=TRUE

NC_HDA_SDIN1

MAKE_BASE=TRUE

TP_HDA_SDIN1

NC_PCI_CLK33M_OUT3

MAKE_BASE=TRUE

NO_TEST=TRUE

TP_PCI_CLK33M_OUT3

NC_PCI_CLK33M_OUT2

MAKE_BASE=TRUE

NO_TEST=TRUE

TP_PCI_CLK33M_OUT2

NC_HDA_SDIN3

MAKE_BASE=TRUE

NO_TEST=TRUE

TP_HDA_SDIN3

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I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Functional / ICT Test

SYNC_DATE=02/11/2013

SYNC_MASTER=J16_MAX

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I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_BOARD_INFO

VERSION

ALLEGRO

(MIL or MM)

BOARD UNITS

BOARD LAYERS

BOARD AREAS

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

Default

Power and Common

Fixed and Dielectric

BGA Area Constraints

BGA

0.127 mm

0.435 mm

1 oz

0.5 oz

0.076 mm 1 oz

0.5 oz (Cu plated)

1 oz

0.435 mm

0.071 mm 1 oz

0.076 mm

0.5 oz

0.071 mm

Prepreg

Board Stack-up

Finished board thickness: 1.58 mm

Plane

Signal

Top

2

Plane

Signal

Core

5

4

3

2

6

Signal

Btm

0.5 oz (Cu plated)

General Spacing DefinitionsGeneral Physical Rule Definitions

J16 BOARD SPECIFIC PHYSICAL AND SPACING CONSTRAINTS

=STANDARD

50_OHM_SE

TOP,BOTTOM

0.110 MM

Y

0.085 MM

=STANDARD

55_OHM_SE

*

=STANDARD

0.085 MM0.085 MM

Y =STANDARD

0.140 MM

0.180 MM

68_OHM_DIFF

=STANDARD

* Y

0.085 MM

0.1 MM

=STANDARD

0.110 MM

* Y

50_OHM_SE

=STANDARD

0.085 MM

0.138 MM

45_OHM_SE

=STANDARD

0.085 MM

Y =STANDARD

TOP,BOTTOM

=STANDARD

55_OHM_SE

TOP,BOTTOM

Y

=STANDARD

=STANDARD=STANDARD

0.085 MM0.085 MM

0.125 MM

0.1 MM

0.085 MM

=STANDARD

85_OHM_DIFF

Y*

0.190 MM

0.160 MM

0.1 MM

0.085 MM

80_OHM_DIFF

Y

0.135 MM

=STANDARD

*

0.160 MM

0.085 MM

0.1 MM

=STANDARD

80_OHM_DIFF

Y

0.135 MM

TOP,BOTTOM

Y

=STANDARD

0.085 MM

0.220 MM

0.1 MM*

0.089 MM

100_OHM_DIFF

0.1 MM

TOP,BOTTOM

0.089 MM

Y

0.085 MM

=STANDARD

0.220 MM

100_OHM_DIFF

0.1 MM

0.085 MM

90_OHM_DIFF

Y*

=STANDARD

0.200 MM

0.111 MM

Y 0.1 MM

90_OHM_DIFF

0.200 MM

=STANDARD

0.085 MM0.111 MM

TOP,BOTTOM

?

*

0.1 MM

1:1_SPACING

0.076 MM

*

?

1X_DIELECTRIC

BGA_P1MM

**

BGA

0.085 MM0.170 MM

39_OHM_SE =STANDARD

=STANDARDY

TOP,BOTTOM

=STANDARD

TOP,BOTTOM

=STANDARDY

0.085 MM

=STANDARD

42_OHM_SE

0.145 MM

0.138 MM

45_OHM_SE

=STANDARD =STANDARD* Y

0.085 MM

=STANDARD

0.1 MM

0.125 MM 0.085 MM

=STANDARD

85_OHM_DIFF

Y

0.190 MM

TOP,BOTTOM

0.071 MM

TOP,BOTTOM

?

1X_DIELECTRIC

*

=2:1_SPACING

1000

GND_P2MM

*

GND

=STANDARD

?

=STANDARD

0.085 MM

Y* =STANDARD=STANDARD

42_OHM_SE

0.145 MM

0.170 MM

39_OHM_SE

0.085 MM

=STANDARDY*

=STANDARD

TOP,BOTTOM

0.140 MM

0.180 MM

68_OHM_DIFF

Y

=STANDARD

0.1 MM

0.085 MM

1100

=2:1_SPACING

*

PWR_P2MM

*

?

=STANDARD

BGA_P1MM

0.215 MM

34_OHM_SE =STANDARD

TOP,BOTTOM

Y

0.085 MM

=STANDARD =STANDARD

DEFAULT

*

0.1 MM

?

STANDARD =DEFAULT

?

*

=STANDARD

0.215 MM

34_OHM_SE

0.085 MM

Y* =STANDARD

12.7 MM

=DEFAULT=DEFAULT

Y*

=DEFAULT=DEFAULTSTANDARD

12.7 MM

=50_OHM_SE

0 MM0 MM

DEFAULT

* Y

0.1 MM

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,BOTTOM

MM

16.2

NO_TYPE,BGA

SYNC_MASTER=J16_MLB

SYNC_DATE=12/03/2012

J16 RULE DEFINITIONS

051-0164

12.4.0

110 OF 123

74 OF 86

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DDR3

Spacing

Channel A

Physical

DDR3-specific Physical Rules

DDR3

Minimum diff spacing is 4 mil

Electrical Contraint Set

Table 4-5, Intel Doc# 486712

Channel B

Reset

DQ or DQS to other signals not in the same bytelane (but not ch)

DQ to DQS in the same bytelane of the same channel

DDR3 to any other signal not DDR3

CLK trace spacing controlled by =68_OHM_DIFF

DQ to DQ in the same bytelane of the same channel

DQ or DQS in different channels

DQ or DQS in different bytelanes of the same channel

See Note (1)

See Note (3)

See Note (1)

Main Segment Min Spacing Rules (mils) (Shark Bay PDG, Intel Doc# 486712)

DDR3 Power-specific Spacing Definitions

Physical Net Type to Rule Map

13.78

19.69

Design

13.78

Comments

11.81

25.59

Iso

Data: DQS[7:0], DQS#[7:0], DQ[63:0]

12

126

8.5

7.87

9.84

Trace

15

12

(diff)

Design

4

8

Table 4-2

4-3

4-4

4-5

25

10

12

-

20 mA per trace with edge rates in the 100s of ps. The main

one rule per channel is needed by trading off a little space.

complexity to contraints, even though it can be less. Only

Deliberately set DQ to DQS spacing to 3:1 to avoid adding

coupling mechanism is capacitive. A 0.65 mm spacing is used for power nets, which draw far more current (inductive coupling however). These rules are far too conservative.

In order for the constraints DDR_*_DQ_BYTE* to =SAME to win out over DDR_{A,B}_DQ_BYTE* to DDR_{A,B}_DQ_BYTE* so that

To meet these rules, the spacing must be applied to the net.

DDR_DQ2DQ must have a weight greater than DDR_BL2BL.

the small intra-bytelane spacing is used, the spacing rule

and via to pad to two different channels. DDR3 draws about

Intel suggests 25 mil (0.65 mm) spacing for via to channel,

Note (2):

Note (1):

Note (3):

Command: MA[15:0], RAS#, CAS#, WE# BS[2:0]

Control: CS#[3:0], CKE[3:0], ODT[3:0]

DDR3-specific Spacing Definitions

Clocks: CK[3:0], CK#[3:0]

Constraints

SM COMP

See Note (2)

I178

I179

I180

I181

I182

I183

I184

I185 I186

I187

I188

I189

I190

I191

I192 I193

I194 I195

I196

I197

I198 I199

I200

I201

I202

I203

I204

I205

I206 I207

I208

I209 I210

I211

I212 I213

I214 I215

I216

I217 I218

I219

I220 I221

I222

I223

I224

I225

I226

I227 I228

I229

I230 I231

I232

I233 I234

I235

I236

I237

I238 I239

I240

I241 I242

I243

I244 I245

I246

I247

I248

I249

I250 I251

I252

I253

I254

I255 I256

I257

DDR3 Constraints

SYNC_DATE=01/10/2013SYNC_MASTER=J16_NICK

DDR_B_DQ_BYTE*

*

DDR_DQ2DQSDDR_B_DQS*

*

DDR_B_DQ_BYTE*DDR_B_DQ_BYTE*

DDR_BL2BL

DDR_COMP_ISO

DDR_COMP

* *

DDR_CLK

**

DDR_CLK_ISO

DDR_COMP_ISO

0.381 MM

?

*

=6.5:1_SPACING

DDR_CH2CH

*

?

DDR_COMP_PHY

DDR_COMP

*

DDR_42S_D

DDR_DQS_PHY

=39_OHM_SE

DDR_39S

=STANDARD* =STANDARD

=39_OHM_SE=39_OHM_SE =39_OHM_SE

=50_OHM_SE =50_OHM_SE

=STANDARD=STANDARD

DDR_50S

=50_OHM_SE*=50_OHM_SE

=68_OHM_DIFF =68_OHM_DIFF=68_OHM_DIFF

* =68_OHM_DIFF

DDR_68D

=68_OHM_DIFF

0.105 MM

=STANDARD=STANDARD

=STANDARD

0.305 MM

Y

DDR_COMP

*

DDR_CMD2CMD

DDR_CMD DDR_CMD

**

DDR_CMD_ISO

DDR_CMD

DDR_CTRL2CTRL

*

DDR_CTRL DDR_CTRL

**

DDR_CTRL_ISO

DDR_CTRL

=3:1_SPACING

?

*

DDR_DQ2DQS

=3:1_SPACING

*

DDR_BL2BL

?

900

DDR_DQ2DQ

*

=2:1_SPACING

=3:1_SPACING

?

*

DDR_DATA_ISO

=2:1_SPACING

?

*

DDR_CMD2CMD

?

=3.5:1_SPACING

*

DDR_CMD_ISO

=2.5:1_SPACING

*

DDR_CTRL2CTRL

?

=5:1_SPACING

?

*

DDR_CLK_ISO

?

*

DDR_CTRL_ISO

=3.5:1_SPACING

DDR_68D

*

DDR_CLK_PHY

DDR_39S

*

DDR_CTRL_PHY

DDR_34S

*

DDR_CMD_PHY

DDR_42S

*

DDR_DQ_PHY

POWER_DDR_P4MM

POWER_DDR

*

DDR_CH2CH

DDR_B_*DDR_A_*

*

DDR_DQ2DQS

*

DDR_A_DQS*

DDR_A_DQ_BYTE*

*

DDR_BL2BL

DDR_A_DQ_BYTE*DDR_A_DQ_BYTE*

DDR_DQ2DQ

*

DDR_*_DQ_BYTE*

=SAME

DDR_DATA_ISO

**

DDR_B_DQ_BYTE*

DDR_DATA_ISO

**

DDR_B_DQS*

DDR_DATA_ISO

*

DDR_A_DQS*

*

DDR_DATA_ISO

**

DDR_A_DQ_BYTE*

POWER_DDR

?

=2:1_SPACING

*

POWER_DDR_P4MM

0.100 MM0.400 MM

3.0 MM

=STANDARDY =STANDARD*

=42_OHM_SE =42_OHM_SE

=STANDARD =STANDARD

=42_OHM_SE

DDR_42S

*

=42_OHM_SE

=34_OHM_SE

DDR_34S

=STANDARD*

=34_OHM_SE =34_OHM_SE

=STANDARD

=34_OHM_SE

=42_OHM_SE =42_OHM_SE

DDR_42S_D

0.1016 MM0.1016 MM

=42_OHM_SE

*

=42_OHM_SE

DDR_DQS_PHY

DDR_B_DQS5

MEM_B_DQS_P<5>

DDR_B_DQS5

DDR_DQS_PHY

DDR_B_DQS7

MEM_B_DQS_P<7>

DDR_B_DQS7

MEM_RESET_L

DDR_50S

DDR_COMP

DDR_COMP_PHY

CPU_SM_RCOMP<0..2>

DDR_DQS_PHY

DDR_B_DQS7

MEM_B_DQS_N<7>

DDR_B_DQS7

DDR_B_DQS6

DDR_DQS_PHY

DDR_B_DQS6

MEM_B_DQS_N<6>

DDR_DQS_PHY

DDR_B_DQS6

MEM_B_DQS_P<6>

DDR_B_DQS6

DDR_DQS_PHY

DDR_B_DQS5

MEM_B_DQS_N<5>

DDR_B_DQS5

DDR_DQS_PHY

DDR_B_DQS4

MEM_B_DQS_P<4>

DDR_B_DQS4

DDR_DQS_PHY

DDR_B_DQS3DDR_B_DQS3

MEM_B_DQS_N<3>

DDR_DQS_PHY

MEM_B_DQS_P<3>

DDR_B_DQS3 DDR_B_DQS3

DDR_B_DQS2

DDR_DQS_PHY

DDR_B_DQS2

MEM_B_DQS_P<2>

DDR_B_DQS0

DDR_DQS_PHY

DDR_B_DQS0

MEM_B_DQS_N<0>

DDR_DQ_PHY

DDR_B_DQ_BYTE5

MEM_B_DQ<47..40>

DDR_B_DQ_BYTE5

DDR_DQ_PHY

DDR_B_DQ_BYTE4

MEM_B_DQ<39..32>

DDR_B_DQ_BYTE4

DDR_CMD_PHY

DDR_B_CMD

MEM_B_RAS_L

DDR_CMD

DDR_CTRL_PHY

MEM_B_CKE<1..0>

DDR_B_CTRL0

DDR_CTRL

DDR_A_DQS0

DDR_DQS_PHY

MEM_A_DQS_P<0>

DDR_A_DQS0

DDR_DQ_PHY

DDR_A_DQ_BYTE5 DDR_A_DQ_BYTE5

MEM_A_DQ<47..40>

DDR_A_DQS2

DDR_DQS_PHY

MEM_A_DQS_P<2>

DDR_A_DQS2

DDR_DQS_PHY

DDR_A_DQS2

MEM_A_DQS_N<2>

DDR_A_DQS2

DDR_DQS_PHY

MEM_A_DQS_P<3>

DDR_A_DQS3DDR_A_DQS3

DDR_DQS_PHY

MEM_A_DQS_N<4>

DDR_A_DQS4DDR_A_DQS4

DDR_B_DQS2

DDR_DQS_PHY

DDR_B_DQS2

MEM_B_DQS_N<2>

DDR_DQS_PHY

DDR_B_DQS4

MEM_B_DQS_N<4>

DDR_B_DQS4

DDR_DQS_PHY

DDR_B_DQS1DDR_B_DQS1

MEM_B_DQS_P<1>

DDR_B_DQS1

DDR_DQS_PHY

DDR_B_DQS1

MEM_B_DQS_N<1>

DDR_DQS_PHY

DDR_B_DQS0DDR_B_DQS0

MEM_B_DQS_P<0>

DDR_DQ_PHY

MEM_B_DQ<63..56>

DDR_B_DQ_BYTE7 DDR_B_DQ_BYTE7

DDR_DQ_PHY

DDR_B_DQ_BYTE6 DDR_B_DQ_BYTE6

MEM_B_DQ<55..48>

DDR_DQ_PHY

DDR_B_DQ_BYTE3

MEM_B_DQ<31..24>

DDR_B_DQ_BYTE3

DDR_DQ_PHY

DDR_B_DQ_BYTE2

MEM_B_DQ<23..16>

DDR_B_DQ_BYTE2

DDR_DQ_PHY

DDR_B_DQ_BYTE0

MEM_B_DQ<7..0>

DDR_B_DQ_BYTE0

DDR_DQ_PHY

DDR_B_DQ_BYTE1 DDR_B_DQ_BYTE1

MEM_B_DQ<15..8>

DDR_CMD_PHY

DDR_B_CMD

MEM_B_CAS_L

DDR_CMD

DDR_CMD_PHY

DDR_CMD

DDR_B_CMD

MEM_B_WE_L

DDR_CMD_PHY

DDR_B_CMD

MEM_B_BA<2..0>

DDR_CMD

DDR_CMD_PHY

DDR_B_CMD

MEM_B_A<15..0>

DDR_CMD

DDR_CTRL_PHY

DDR_B_CTRL1

MEM_B_ODT<3..2>

DDR_CTRL

DDR_CTRL_PHY

DDR_B_CTRL1

MEM_B_CS_L<3..2>

DDR_CTRL

DDR_CTRL_PHY

MEM_B_ODT<1..0>

DDR_B_CTRL0

DDR_CTRL

DDR_B_CTRL1

DDR_CTRL_PHY

MEM_B_CKE<3..2>

DDR_CTRL

DDR_CLK_PHY

DDR_CLK

DDR_B_CLK0

MEM_B_CLK_N<1..0>

DDR_CLK_PHY

DDR_CLK

DDR_B_CLK1

MEM_B_CLK_P<3..2>

MEM_B_CLK_P<1..0>

DDR_CLK_PHY

DDR_CLK

DDR_B_CLK0

DDR_DQS_PHY

DDR_A_DQS7

MEM_A_DQS_N<7>

DDR_A_DQS7

DDR_DQS_PHY

DDR_A_DQS5

MEM_A_DQS_N<5>

DDR_A_DQS5

DDR_DQS_PHY

DDR_A_DQS5

MEM_A_DQS_P<5>

DDR_A_DQS5

DDR_DQS_PHY

MEM_A_DQS_N<3>

DDR_A_DQS3DDR_A_DQS3

DDR_DQS_PHY

DDR_A_DQS4

MEM_A_DQS_P<4>

DDR_A_DQS4

DDR_A_DQS1

DDR_DQS_PHY

DDR_A_DQS1

MEM_A_DQS_N<1>

DDR_DQ_PHY

DDR_A_DQ_BYTE4 DDR_A_DQ_BYTE4

MEM_A_DQ<39..32>

DDR_DQ_PHY

MEM_A_DQ<23..16>

DDR_A_DQ_BYTE2DDR_A_DQ_BYTE2

DDR_DQ_PHY

DDR_A_DQ_BYTE3

MEM_A_DQ<31..24>

DDR_A_DQ_BYTE3

DDR_DQ_PHY

DDR_A_DQ_BYTE0

MEM_A_DQ<7..0>

DDR_A_DQ_BYTE0

DDR_CMD_PHY

DDR_A_CMD

MEM_A_CAS_L

DDR_CMD

DDR_CMD_PHY

DDR_A_CMD

MEM_A_WE_L

DDR_CMD

DDR_A_CTRL1

DDR_CTRL_PHY

DDR_CTRL

MEM_A_CS_L<3..2>

DDR_CTRL_PHY

DDR_A_CTRL1

DDR_CTRL

MEM_A_ODT<3..2>

DDR_A_CTRL1

DDR_CTRL_PHY

DDR_CTRL

MEM_A_CKE<3..2>

DDR_CLK_PHY

DDR_A_CLK0

MEM_A_CLK_P<1..0>

DDR_CLK

DDR_CLK_PHY

DDR_A_CLK0

MEM_A_CLK_N<1..0>

DDR_CLK

DDR_CLK_PHY

DDR_A_CLK1

MEM_A_CLK_N<3..2>

DDR_CLK

DDR_CLK_PHY

DDR_A_CLK1

MEM_A_CLK_P<3..2>

DDR_CLK

DDR_A_DQS1

DDR_DQS_PHY

MEM_A_DQS_P<1>

DDR_A_DQS1

DDR_DQS_PHY

MEM_A_DQS_P<6>

DDR_A_DQS6DDR_A_DQS6

DDR_DQS_PHY

DDR_A_DQS7 DDR_A_DQS7

MEM_A_DQS_P<7>

DDR_CTRL_PHY

MEM_B_CS_L<1..0>

DDR_B_CTRL0

DDR_CTRL

DDR_CLK_PHY

DDR_CLK

DDR_B_CLK1

MEM_B_CLK_N<3..2>

DDR_A_DQS0

DDR_DQS_PHY

MEM_A_DQS_N<0>

DDR_A_DQS0

DDR_DQ_PHY

DDR_A_DQ_BYTE1

MEM_A_DQ<15..8>

DDR_A_DQ_BYTE1

DDR_A_CTRL0

DDR_CTRL_PHY

DDR_CTRL

MEM_A_CS_L<1..0>

DDR_A_DQ_BYTE7

DDR_DQ_PHY

MEM_A_DQ<63..56>

DDR_A_DQ_BYTE7

DDR_DQ_PHY

DDR_A_DQ_BYTE6

MEM_A_DQ<55..48>

DDR_A_DQ_BYTE6

DDR_A_CTRL0

DDR_CTRL_PHY

DDR_CTRL

MEM_A_ODT<1..0>

DDR_CTRL_PHY

DDR_A_CTRL0

DDR_CTRL

MEM_A_CKE<1..0>

DDR_CMD_PHY

DDR_A_CMD

MEM_A_RAS_L

DDR_CMD

DDR_CMD_PHY

DDR_A_CMD

MEM_A_BA<2..0>

DDR_CMD

DDR_CMD_PHY

DDR_A_CMD

MEM_A_A<15..0>

DDR_CMD

DDR_DQS_PHY

DDR_A_DQS6

MEM_A_DQS_N<6>

DDR_A_DQS6

051-0164

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111 OF 123

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7

25

7

25

21 23 24

6

7

25

7

25

7

25

7

25

7

25

7

25

7

25

7

25

7

25

7

25

7

25

7

24

7

24

7

25

7

25

7

25

7

25

7

25

7

25

7

25

7

25

7

25

7

25

7

25

7

25

7

25

7

25

7

25

7

25

7

25

7

24

7

24

7

24

7

24

72

7

24

72

7

24

72

7

24

7

25

7

25

7

25

7

25

7

25

7

25

7

25

7

25

7

25

7

25

7

23

7

23

72

7

23

7

23

72

7

25

7

25

7

25

7

24

72

7

25

7

25

7

23

7

25

7

25

7

23

7

23

7

23

7

23

7

23

7

25

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

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SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PCIe-specific Physical Rules

PCI Express/DMI

PCIe. Impedance inferred from Table 4-7.

Spacing Constraints

PCIe-specific Spacing Definitions

Physical Net Type to Rule Map

PCIe (CPU)

Electrical Contraint Set CPU PCIe Compensation

CPU eDP Compensation

Spacing

PhysicalPhysical

Spacing

Electrical Contraint Set

Table

504-5

4-7

5050

50

Imp

Design

15.75

Iso 15

15.75

8

Design

PCIe and DMI Compensation Rules (mils)

Comments

DMI. Numbers based on Intel stack-up.

Section

Imp 80 80

4.2.1

Design Design

16

15.75

Iso

PCIe Gen3. Allow looser spacing for same direction on stripline per Anil

Comments

PEG Min Spacing Rules (mils) (Maho Bay PDG, Intel Doc# 473718)

CPU ASYNCHRONOUS

I570

I571

I572

I573

I574 I575

I576

I577

I578

I579

I580

I581

I582

CPU CONSTRAINTS

SYNC_DATE=01/10/2013SYNC_MASTER=J16_NICK

CLK_PCIE_ISO

CLK_PCIE

**

COMP_PCIE_ISO

* *

COMP_PCIE

CPU_ASYNC_ISO

* *

CPU_ASYNC

* *

CPU_ASYNC_MS

CPU_MS_ISO

?

CPU_ASYNC_ISO

*

=3:1_SPACING

CLK_PCIE_ISO

?

*

=5:1_SPACING

*

?

=4:1_SPACING

COMP_PCIE_ISO

*

CLK_PCIE_PHY

PCIE_90D

?

=4.5:1_SPACING

TOP,BOTTOMCPU_MS_ISO

COMP_PCIE_PHY

PCIE_COMP

*

CPU_50S

*

CPU_ASYNC_PHY

?

*

=3:1_SPACING

CPU_MS_ISO

CPU_50S

=STANDARD=STANDARD

=50_OHM_SE=50_OHM_SE=50_OHM_SE=50_OHM_SE

*

=STANDARDY

0.105 MM

=STANDARD*

0.305 MM

=STANDARDPCIE_COMP

PCIE_90D

=90_OHM_DIFF

* =90_OHM_DIFF

=90_OHM_DIFF=90_OHM_DIFF

PCIE_85D

=85_OHM_DIFF

*

=85_OHM_DIFF

=85_OHM_DIFF =85_OHM_DIFF

CPU_PECI

CPU_ASYNC_PHY

PECI

CPU_ASYNC_MS

CPU_ASYNC_PHY

CPU_ASYNC

PM_SYNC

CPU_RESET_L

CPU_ASYNC_PHY

CPU_ASYNC

CPU_ASYNC_PHY

CPU_ASYNC

PM_THRMTRIP_L

CPU_ASYNC_PHY

SMC_PECI_L

CPU_ASYNC_MS CPU_ASYNC

CPU_ASYNC_PHY

CPU_CATERR_L CPU_PWRGD

CPU_ASYNC

CPU_ASYNC_PHY

CPU_ASYNC

CPU_ASYNC_PHY

CPU_PROCHOT_R_L

CPU_PROCHOT_L

CPU_ASYNC

CPU_ASYNC_PHY COMP_PCIE_PHY

COMP_PCIE

CPU_PEG_RCOMP

CPU_EDP_RCOMP

COMP_PCIE

COMP_PCIE_PHY

COMP_PCIE

CPU_CFG_RCOMP

XDP_BPM_L

CPU_ASYNC_PHY

XDP_BPM_L<1..0>

CPU_ASYNC

051-0164

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14 44 45

6

12

6

14 18

6

14 45

44 45

6

45

6

14 18

6

44 45 61 62

5

6

18

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_SPACING_ASSIGNMENT_ITEM

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

PCIe-specific Spacing Definitions

Electrical Contraint Set

PCH PCIE Compensation

DMI Compensation

PCIe (PCH)

Electrical Contraint Set

DMI x4 PCIE Spacing Constraints

TBT x4 PCIE Spacing Constraints

Spacing

CPU DP REF CLK

Physical

Spacing

Electrical Contraint Set

DMI

Spacing

Physical

DMI

x4 Thunderbolt

x2 SSD

Physical

DMI-specific Spacing Definitions

PCH x1 PCIE Constraints

Physical Net Type to Rule Map

x1 AirPort

x1 Caesar IV

I132

I133

I134 I135

I136

I137 I138

I139

I140

I141

I142

I143 I144

I145

I146

I147

I148

I149

I150

I151

I152

I153

I154

I155

I156 I157

I158

I159

I165

I166

I167 I168

I169

I170

I171

I172 I173

I174

I175

I176

I177

I178

PCIE_ALT_DIRPCIE_TBT_R2DPCIE_TBT_D2R

*

PCIE_SAME_DIR

PCIE_TBT_D2R*PCIE_TBT_D2R

PCIE_TBT_D2R

* *

PCIE_ISO

PCIE_TBT_R2D

PCIE_ISO

* *

*

PCIE_ISO

PCIE

*

DMI_SAME_DIR

DMI_N2SDMI_N2S

*

DMI_ISO

?

*

=4X_DIELECTRIC

PCIE_TBT_R2D

PCIE_SAME_DIR

*

PCIE_TBT_R2D

DMI_ISODMI_N2S

**

=4X_DIELECTRIC

?

*

DMI_SAME_DIR

DMI_ISODMI_S2N

**

DMI_SAME_DIR

TOP,BOTTOM

=5X_DIELECTRIC

?

=5X_DIELECTRIC

DMI_ALT_DIR

?

*

=5X_DIELECTRIC

TOP,BOTTOM

?

PCIE_SAME_DIR

PCIE_85DPCIE_PHY

*

DMI_COMP

COMP_DMI_PHY

*

=3.5X_DIELECTRIC

PCIE_SAME_DIR

*

?

DMI_COMP

Y* =STANDARD

3 MM

=STANDARD

0.2032 MM0.2032 MM

=4:1_SPACING

*

?

PCIE_ISO

=7X_DIELECTRIC

*

?

PCIE_ALT_DIR

DMI_SAME_DIR

DMI_S2NDMI_S2N

*

DMI_ALT_DIR

DMI_S2NDMI_N2S

*

SYNC_MASTER=J16_NICK SYNC_DATE=01/10/2013

PCH PCIe/DMI Constaints

PCIE_AP_D2R_N

PCIE_PHY

PCIE_GEN2_D2R_CONN_AP

PCIE

PCIE_CLK100M_AP_N

CLK_PCIE_PHY

CLK_PCIE

PCIE_REF_CLK

PCIE_CLK100M_AP_P

CLK_PCIE_PHY

CLK_PCIE

PCIE_REF_CLK

PCIE_GEN2_D2R_CONN_AP

PCIE_PHY

PCIE_AP_D2R_P

PCIE

PCIE_GEN2_R2D

PCIE

PCIE_PHY

PCIE_ENET_R2D_P

PCIE_ENET_D2R_P

PCIE_GEN2_D2R

PCIE

PCIE_PHY

PCIE_AP_R2D_C_N

PCIE

PCIE_AP_R2D_C_P

PCIE_PHY

PCIE

PCIE_PHY

PCIE_AP_R2D_P

PCIE_GEN2_R2D_CONN_AP

PCIE_TBT_R2D

PCIE_TBT_R2D_C_P<3..0>

PCIE_PHY

PCIE_TBT_R2D

PCIE_GEN2_R2D

PCIE_PHY

PCIE_TBT_R2D_P<3..0>

PCIE_CLK100M_ENET_P

CLK_PCIE_PHY

CLK_PCIE

PCIE_REF_CLK

PCIE_CLK100M_ENET_N

CLK_PCIE_PHY

CLK_PCIE

PCIE_REF_CLK

PCIE_TBT_D2R_C_P<3..0>

PCIE_TBT_D2R

PCIE_PHY

PCIE_TBT_D2R_C_N<3..0>

PCIE_PHY

PCIE_TBT_D2R

PCIE_TBT_D2R_P<3..0>

PCIE_GEN2_D2R

PCIE_TBT_D2R

PCIE_PHY

CLK_PCIE_PHY

DMI_CLK100M_CPU_N

CLK_PCIE

PCIE_REF_CLK

DMI_CLK100M_CPU_P

CLK_PCIE

PCIE_REF_CLK CLK_PCIE_PHY

DMI_N2S

DMI_N2S_P<3..0>

DMI_N2S

PCIE_PHY

DMI_N2S_N<3..0>

DMI_N2S DMI_N2S

PCIE_PHY

DMI_S2N

DMI_S2N_P<3..0>

DMI_S2N

PCIE_PHY PCIE_PHY

DMI_S2N_N<3..0>

DMI_S2NDMI_S2N

CPU_CLK135M_DPLLSS_N

CLK_PCIEPCIE_PHY

CPU_CLK135_PLL

CPU_CLK135M_DPLLREF_P

CLK_PCIEPCIE_PHY

CPU_CLK135_PLL

CPU_CLK135M_DPLLREF_N

CLK_PCIEPCIE_PHY

CPU_CLK135_PLL

PCIE_REF_CLK_CONN

CLK_PCIE

CLK_PCIE_PHY

PCIE_CLK100M_SSD_N

CLK_PCIE

CLK_PCIE_PHY

PCIE_CLK100M_SSD_P

PCIE_REF_CLK_CONN

CLK_PCIE

CPU_CLK135M_DPLLSS_P

PCIE_PHY

CPU_CLK135_PLL

PCIE_ENET_D2R_C_P

PCIE_PHY

PCIE

PCIE_TBT_D2R

PCIE_TBT_D2R_N<3..0>

PCIE_PHY

PCIE_GEN2_D2R

PCIE_TBT_R2D_N<3..0>

PCIE_PHY

PCIE_TBT_R2D

PCIE_GEN2_R2D

PCIE_TBT_R2D_C_N<3..0>

PCIE_TBT_R2D

PCIE_PHY

PCIE_CLK100M_TBT_P

CLK_PCIE_PHY

CLK_PCIE

PCIE_REF_CLK_CONN

CLK_PCIE

CLK_PCIE_PHY

PCIE_CLK100M_TBT_N

PCIE_REF_CLK_CONN

PCH_DMI_RCOMP

COMP_PCIE

COMP_DMI_PHY

PCH_PCIE_RCOMP

COMP_DMI_PHY

COMP_PCIE

PCIE_GEN2_D2R

PCIE_ENET_D2R_N

PCIE

PCIE_PHY

PCIE

PCIE_ENET_R2D_C_N

PCIE_GEN2_R2D

PCIE

PCIE_ENET_R2D_N

PCIE_PHY

PCIE_GEN2_R2D_CONN_AP

PCIE

PCIE_PHY

PCIE_AP_R2D_N

PCIE

PCIE_ENET_R2D_C_P

PCIE_PHY

PCIE_ENET_D2R_C_N

PCIE

PCIE_PHY

051-0164

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11 32

13 32

35

13 35

13 32

32

13 26

26

11 35

26

13 26

6

11

6

11

5

12

5

12

5

12

5

12

6

11

6

11

6

11

11 33

6

11

35

13 26

26

13 26

11 26

12

13

13 35

35

32

13 35

35

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

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D

A

C

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SHEET

R

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SIZE

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REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

FDI

FDI Compensation

PCH SATA Compensation

PCH SATA Port 0 (HDD)

PCH XDP

Electrical Contraint Set

Physical

Design

Comments

FDI-specific Spacing Definitions

PCH SATA Port 1 (SSD)

Desktop Debug Design Guide (Intel Doc# 430883)

FDI Min Spacing Rules (mils) (Maho Bay PDG, Intel Doc# 473718)

XDP-specific Spacing Definitions

Electrical Contraint Set

Spacing

FDI

50

Constraints

1.5

Section

45-65

55

Design

Imp

-

Iso

Design

15.75

Comments Isolation is for JTAG clocks.

Physical Net Type to Rule Map

CPU XDP

Physical

Comments FDI main length

Design

XDP

XDP-specific Physical Rules

Constraints

Table

10

Design

Trace

11.81

8585

Design

12

-

FDI Compensation Rules (mils)

Iso

Comments

15.75

11.81

Design

15-3

50

15.75

Table

Imp

SATA

Spacing

Physical

XDP

6-4

Imp

Using PCIe guidelines

6-1/6-2

All signals default are 50 Ohm SE.

Electrical Contraint Set

Spacing

23.62

95

15.2.1

15

Imp

SATA Min Spacing Rules (mils) (Maho Bay PDG, Intel Doc# 473718)

Design

Iso 20

Physical Net Type to Rule Map

FDI

FDI-specific Physical Rules

Constraints

SATA Gen2, SATA Gen3

90

Section

SATA-specific Spacing Definitions

Design

Iso

SATA Gen2, SATA Gen3

Comments

Design

SATA Compensation Rules (mils)

Physical Net Type to Rule Map

SATA-specific Physical Rules

SATA

I102

I103

I104

I112

I113

I114

I115

I116

I117 I118

I37

I38

I45

I46 I47

I48

I49 I50

I51

I52

I88 I89

I90

I91

I92

I93

I94

I95

I96

I98

=STANDARD =STANDARD

=50_OHM_SE=50_OHM_SE =50_OHM_SE

SATA_50S

*

=50_OHM_SE

SATA_85D

=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

=85_OHM_DIFF =85_OHM_DIFF*

=85_OHM_DIFF

SATA_PHY

*

SATA_85D

*

SATA_PHY_90

SATA_90D

SATA_50S

*

COMP_SATA_PHY

=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF

=90_OHM_DIFF=90_OHM_DIFF

SATA_90D

*

* *

SATA

SATA_ISO

* *

COMP_SATA

COMP_SATA_ISO

=4:1_SPACING

*

?

COMP_SATA_ISO

=6:1_SPACING

SATA_ISO

*

?

FDI_SE_PHY

FDI_50S

*

COMP_FDI_PHY

COMP_FDI

*

=3:1_SPACING

FDI_ISO

*

?

**

COMP_FDI

COMP_FDI_ISO

*

FDI

FDI_ISO

*

CLK_JTAG_ISO

CLK_JTAG

**

XDP_PHY

*

XDP_55S

=2:1_SPACING

?

*

XDP_ISO

=4:1_SPACING

?

*

CLK_JTAG_ISO

**

XDP

XDP_ISO

=55_OHM_SE

=STANDARD*

=55_OHM_SE =55_OHM_SE =55_OHM_SE

XDP_55S

=STANDARD

COMP_FDI_ISO

*

?

=4:1_SPACING

=STANDARD

FDI_50S

=50_OHM_SE

*

=50_OHM_SE

=STANDARD

=50_OHM_SE=50_OHM_SE

3 MM

0.25 MM

=STANDARD* Y

COMP_FDI

0.25 MM

=STANDARD

SYNC_MASTER=J16_NICK

SATA/FDI/XDP Constraints

SYNC_DATE=01/10/2013

CPU_CFG<17..4>

XDP_PHY

XDP_CPU_CFG

XDP

SSD_D2R_P<0..1>

SATA_PHY

SATA

SATA_SSD_D2R

SATA_PHY

SATA

SSD_D2R_N<0..1>

SATA_SSD_D2R

SATA

SATA_SSD_R2D

SATA_PHY

SSD_R2D_C_P<0..1> SSD_R2D_C_N<0..1>

SATA

SATA_SSD_R2D

SATA_PHY

SATA_D2R

SATA

SATA_HDD_D2R_P

SATA_PHY_90

XDP_BPM_L<7..2>

XDP

XDP_PHY

XDP_BPM_L

SATA_HDD_R2D_C_P

SATA

SATA_PHY_90

SATA

SATA_HDD_R2D_P

SATA_R2D

SATA_PHY_90

SATA

SATA_HDD_R2D_N

SATA_R2D

SATA_PHY_90

SATA_HDD_R2D_C_N

SATA

SATA_PHY_90

SATA_HDD_D2R_C_P

SATA

SATA_PHY_90

SATA_D2R

SATA

SATA_HDD_D2R_N

SATA_PHY_90

CPU_CFG<2..0>

XDP

XDP_PHY

XDP_CPU_CFG

CPU_CFG<3>

XDP

XDP_PHY

XDP_CPU_CFG_3

SSD_R2D_P<0..1>

SATA_SSD_R2D

SATA

SATA_PHY

SATA_SSD_R2D

SATA

SATA_PHY

SSD_R2D_N<0..1>

XDP_PHY

XDP_CPU_TCK

CLK_JTAG

XDP_CPU_TMS

XDP

XDP_PHY

XDP_CPU_TDI

XDP

XDP_PHY

XDP_CPU_TDO

XDP_PHY

XDP

XDP_PCH_TCK

CLK_JTAG

XDP_PHY

XDP_PCH_TMS

XDP

XDP_PHY

XDP_PCH_TDI

XDP

XDP_PHY

XDP_PCH_TDO

XDP

XDP_PHY

SATA

SATA_HDD_D2R_C_N

SATA_PHY_90

COMP_SATA

COMP_SATA_PHY

PCH_SATA_RCOMP

FDI

FDI_SE_PHY

FDI_CSYNC

FDI

FDI_SE_PHY

FDI_INT

COMP_FDI_PHY

COMP_FDI

PCH_FDI_RCOMP

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TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

SPI

SPI-specific Physical Rules

SPI-specific Spacing Definitions

Crystal

25 MHz Reference Clocks

SPI Bootrom

Electrical Contraint Set

LPC-specific Physical Rules

HDA-specific Spacing Definitions

HDA

HDA-specific Physical Rules

Physical

SPI ROM

Crystal-specific Physical Rules

Electrical Contraint Set

25M Reference Crystal

PCH Reference Clock

Physical

Spacing Spacing

HDA

PCH

Electrical Contraint Set

PCI

Spacing

Physical

LPC

Physical

25M Reference Clocks

Electrical Contraint Set

PCH-specific Physical Rules

PCH Clocks

Physical

SPDIF

Spacing

SMC 32K

PCH-specific Spacing Definitions

PCI Clock

HDA

PCI

Crystal-specific Spacing Definitions

LPC

Electrical Contraint Set

LPC-specific Spacing Definitions

PCH RTC 32K

PCI-specific Physical Rules

PCI-specific Spacing Definitions

Spacing

Electrical Contraint Set

LPC Clocks

Spacing

I333

I334

I335

I336

I337

I338

I339 I340

I341

I342

I347 I348

I349

I350

I352

I353

I361

I362

I363

I364

I365

I366

I367

I368

I369

I370

I371

I379

I380

I381

I384

I385

I386

I387

I388

I391 I392

I393

I394

I395 I396

I397

I399 I400

I401

I403

I404

I405

I406

I407

I408

I409

I410 I411

I412

I413

=55_OHM_SE=55_OHM_SE

CLK_LPC_55S

=55_OHM_SE =55_OHM_SE

* =STANDARD =STANDARD

SYNC_MASTER=J16_MLB

PCH and BR Constraints

SYNC_DATE=12/03/2012

=2:1_SPACING

?

*

CLK_PCI

=2:1_SPACING

*

?

COMP_PCH

=1.5:1_SPACING

*

?

LPC

=STANDARD =STANDARD

=55_OHM_SE =55_OHM_SE

*

=55_OHM_SE

CLK_PCI_55S

=55_OHM_SE

*

=4:1_SPACING

?

CLK_PCH

=2:1_SPACING

*

?

CLK_LPC

=STANDARD*

=55_OHM_SE

PCH_55S

=55_OHM_SE=55_OHM_SE

=STANDARD

=55_OHM_SE

=55_OHM_SE=55_OHM_SE=55_OHM_SE

=STANDARD =STANDARD*

CLK_PCH_55S

=55_OHM_SE

?

*

XTAL

=4X_DIELECTRIC

=2x_DIELECTRIC

?

*

HDA

=STANDARD

HDA_55S

=55_OHM_SE=55_OHM_SE =55_OHM_SE

*

=55_OHM_SE

=STANDARD

=55_OHM_SE

LPC_55S

=55_OHM_SE

=STANDARD*

=55_OHM_SE

=STANDARD

=55_OHM_SE

=100_OHM_DIFF=100_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFF=100_OHM_DIFF

*

CLK_XTAL

=100_OHM_DIFF

=2:1_SPACING

SPI

*

?

=55_OHM_SE=55_OHM_SE=55_OHM_SE=55_OHM_SE

SPI_55S

=STANDARD* =STANDARD

SPI_50S

=50_OHM_SE=50_OHM_SE=50_OHM_SE=50_OHM_SE

=STANDARD* =STANDARD

CLK_PCI_55S

CLK_PCI

PCH_CLK33M_PCIIN

CLK_PCI_55S

CLK_PCI

PCH_CLK33M_PCIOUT

LPC

LPC_55S

LPC_AD_R<3..0>

LPC_55S

LPC

LPC_FRAME_L

LPC_55S

LPC

LPC_FRAME_R_L

CLK_LPC_55S

LPC_CLK33M_LPCPLUS

CLK_LPC

XTAL

CLK_XTAL

PCH_CLK32K_RTCX1

CLK_PCH

CLK_PCH_55S

SMC_CLK32K

CLK_PCH_55S

CLK_PCH

PM_CLK32K_SUSCLK_R

XTAL

CLK_XTAL

PCH_CLK32K_RTCX2

XTAL

PCH_CLK32K_RTCX2_R

CLK_XTAL

CLK_LPC_55S

CLK_LPC

LPC_CLK33M_LPCPLUS_R

CLK_PCH

CLK_PCH_55S

SYSCLK_CLK25M_TBT_R

CLK_PCH

CLK_PCH_55S

SYSCLK_CLK25M_TBT

SYSCLK_CLK25M_ENET_R

CLK_PCH

CLK_PCH_55S

CLK_PCH

CLK_PCH_55S

SYSCLK_CLK25M_ENET

SYSCLK_CLK25M_X2_R

XTAL

CLK_XTAL

SPIROM_USE_MLB

SPI

SPI_50S

SPI

SPI_MLB_MISO

SPI_50S

SPI

SPI_SMC_MISO

SPI_50S

SPI

SPI_ALT_MOSI

SPI_50S

SPI_MOSI

SPI

SPI_50S

SPI

SPI_MLB_CS_L

SPI_50S

HDA

HDA_55S

HDA_SDIN0 AUD_SDI_R

HDA

HDA_55S

CLK_LPC_55S

LPC_CLK33M_SMC_R

CLK_LPC

LPC_CLK33M_SMC

CLK_LPC_55S

CLK_LPC

HDA

HDA_55S

HDA_SDOUT_R

HDA

HDA_BIT_CLK

HDA_55S

HDA

HDA_55S

HDA_SYNC

SYSCLK_CLK25M_X1

CLK_XTAL

XTAL

HDA_BIT_CLK_R

HDA

HDA_55S

SYSCLK_CLK25M_X2

XTAL

CLK_XTAL

LPC_55S

LPC

LPC_AD<3..0>

HDA_55S

HDA

HDA_SYNC_R

SPI_ALT_CLK

SPI

SPI_50S

SPI_CLK

SPI

SPI_50S

SPI

SPI_SMC_CS_L

SPI_50S

SPI

SPI_CS0_R_L

SPI_50S

SPI_SMC_CLK

SPI

SPI_50S

SPI_CLK_R

SPI

SPI_50S

SPI_ALT_MISO

SPI

SPI_50S

SPI_MISO

SPI

SPI_50S

SPI

SPI_MLB_MOSI

SPI_50S

SPI_SMC_MOSI

SPI

SPI_MOSI_R

SPI_50S

SPI_ALT_CS_L

SPI

SPI_50S

SPI

SPI_CS0_L

SPI

SPI_MLB_CLK

SPI_50S

AUD_SPDIF_CHIP

HDA HDA

AUD_SPDIF_OUT

HDA_55S

HDA

HDA_SDOUT

HDA_RST_R_L

HDA

HDA_55S

HDA_RST_L

HDA

HDA_55S

CLK_PCH_55S

SYSCLK_CLK25M_SB

CLK_PCH

CLK_PCH_55S

CLK_PCH

SYSCLK_CLK25M_SB_R

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TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

Electrical Contraint Set

Physical

Ethernet

Et tu Brute?

USB-specific Physical Rules

USB Min Spacing Rules (mils) (Maho Bay PDG, Intel Doc# 473718)

SD

Camera Processor-to-Camera Sensor I/F (SMIA/MIPI)

Camera Processor’s SMIA Interface Physical Rules

SD

External Port C (J4700)

Constraints

PCH USB Compensation

Physical

Section

12.2.1

85

13.3.1

85

90

Imp90Design12Iso20Design

11.81

21.65

USB 2.0

Comments

USB

Spacing

Caesar IV (Ethernet/SD)

CIV-specific Physical Rules

Physical Net Type to Rule Map

USB-specific Spacing Definitions

Constraints EthernetEthernet

CIV-specific Spacing Definitions

Camera (J3510)

Spacing

CIV SPI

Spacing

Physical

Camera Processor’s SMIA Interface Spacing Definitions

Electrical Contraint Set

Camera Processor-Camera Sensor I/F

Physical Net Type to Rule Map

USB 3.0 and USB 2.0 Trixies Muxing

External Port B (J4610)

Physical

External Port A (J4600)

Electrical Contraint Set

SD

USB 3.0

Spacing

Electrical Contraint Set

RMH Love

External Port D (J4710)

2 kV isolation

I320

I321

I324

I326

I384

I391 I392

I393

I394

I409

I410 I413

I414

I415 I416

I417

I418

I419 I420

I421 I422

I423 I424

I425

I426

I427

I428

I429 I430

I433

I434

I437

I438

I439

I440

I441 I442

I443

I444

I445

I446

I450

I452

I453

I454

I455

I456

I457 I458

I459

I460

I461

I462

I466

I468

I474

I475

I476

I477

I478

I479

I480

I481

I482

I483

I484

I485

I486

I488

I489

I490

I491

I492

I493

I494

I495

I496

I497

I498

I499

I500

I501

I502

I503

I504

I505

I506

I507

I508

I509

I510

I511

I512

I513

I514

I516

I517

I518

I519

I520

I521

I522

I523

SD_50S

*

=50_OHM_SE

=STANDARD =STANDARD

=50_OHM_SE=50_OHM_SE =50_OHM_SE

ENET_100D

*

=100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF

SYNC_DATE=12/03/2012

USB/Ethernet/SD Constraints

SYNC_MASTER=J16_MLB

*

=50_OHM_SE=50_OHM_SE

=STANDARD

ENET_50S

=50_OHM_SE

=STANDARD

=50_OHM_SE

?

TOP,BOTTOM

USB3_ISO

=5.5:1_SPACING

USB3_ISO

*

?

=3:1_SPACING

?

USB2_ISO

TOP,BOTTOM

USB3_PHY

USB_85D

*

USB_90D

USB2_PHY

*

=3:1_SPACING

*

?

USB2_ISO

COMP_ENET

*

COMP_ENET_ISO

*

* *

USB2

USB2_ISO

=3:1_SPACING

ENET_DIFF2DIFF

*

?

*

ENET_DIFF

ENET_DIFF2DIFF

ENET_DIFF

**

ENET_TRANS_ISO

ENET_TRANS

ENET_TRANS ENET_TRANS

ENET_DIFF2DIFF

*

SD **

SD_ISO

=100_OHM_DIFF

*

=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF

SMIA_100D

=6:1_SPACING

?

SMIA_DIFF_ISO

* *

SMIA_DIFF

*

SMIA_DIFF_ISO

USB3_ISO

USB3

* *

ENET_DIFF_PHY

*

ENET_100D

SD_PHY

*

SD_50S

USB_85D

=85_OHM_DIFF

=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

* =85_OHM_DIFF

=85_OHM_DIFF

ENET_DIFF_ISO

* *

ENET_DIFF

1.27 MM

*

ENET_TRANS_ISO

?

=6:1_SPACING

?

*

ENET_DIFF_ISO

=4:1_SPACING

*

COMP_ENET_ISO

?

SMIA_DIFF_PHY

*

SMIA_100D

=3:1_SPACING

?

*

SMIA_DIFF2DIFF

CIV_SPI

*

SPI_55S

ENET_COMP_PHY

*

ENET_50S

*

SMIA_DIFF2DIFF

SMIA_DIFF SMIA_DIFF

=3:1_SPACING

*

?

SD_ISO

USB_90D

=90_OHM_DIFF

=90_OHM_DIFF =90_OHM_DIFF

=90_OHM_DIFF

=90_OHM_DIFF=90_OHM_DIFF

*

ENETCONN_MCT_BS

ENET_TRANS

ENET_COMP_PHY

COMP_ENET

ENET_RDAC

SD_PHY

ENET_SD_CMD

SD_CMD

SD

SDCONN_CMD

SD_PHY

SD

SDCONN_DATA<7..0>

SD

SD_PHY

SD

ENET_CR_DATA<7..0>

SD_DATA

SD_PHY

USB3_EXTB_TX_C_N

USB3

USB3_PHY

USB3

USB3_PHY

USB3_EXTB_TX_C_P

ENETCONN_MCT0

ENET_TRANS

ENETCONN_MCT3

ENET_TRANS

SDCONN_CMD_R

SD_PHY

SD

ENET_SD_CLK

SD_CLK SD_PHY

SD

USB3_PHY

USB3

USB3_EXTD_RX_F_N

USB3_EXTD_TX_C_N

USB3_PHY

USB3

USB3_PHY

USB3

USB3_EXTD_TX_C_P

USB3

USB3_PHY

USB3_EXTD_TX_F_N

USB2

USB2_EXTC_N

USB2_PHY

USB3_PHY

USB3_EXTB_RX_F_P

USB3

USB3_RX_CONN

USB3_EXTB_RX_P

USB3_PHY

USB3

USB3_PHY

USB3

USB3_EXTA_RX_N

USB3_RX_CONN

USB2

USB2_PHY

USB2_EXTA_N

USB3_PHY

USB3_RX_CONN

USB3_EXTB_RX_N

USB3

USB3_EXTB_TX_P

USB3_TX_CONN

USB3_PHY

USB3

USB3_PHY

USB3_TX_CONN

USB3_EXTB_TX_N

USB3

USB3_EXTB_TX_F_P

USB3_PHY

USB3 USB3

USB3_EXTB_TX_F_N

USB3_PHY

USB_BT_P

USB2

USB2_PHY

USB2_MUXED_BT

USB2

USB_BT_N

USB2_PHY

USB2_MUXED_BT

USB2

USB_BT_MUX_P

USB2_PHY

USB2_MUXED_BT

USB2_PHY

USB2

USB2_EXTA_MUXED_P

USB2

USB2_PHY

USB_BT_MUX_N

USB2_MUXED_BT

USB2_MUXED_MOJO_CONN

USB2

USB_EXTA_0_P

USB2_PHY

USB2

USB2_PHY

USB2_EXTA_MUXED_N

USB3_TX_CONN

USB3_EXTD_TX_P

USB3_PHY

USB3

USB2_PHY

USB2_MUXED_MOJO_CONN

USB2

USB_EXTA_0_N

USB3_EXTA_TX_F_N

USB3_PHY

USB3

USB3_EXTA_TX_F_P

USB3_PHY

USB3

USB3_EXTA_TX_N

USB3_PHY

USB3_TX_CONN

USB3

USB3_PHY

USB3

USB3_EXTA_TX_C_N

USB3

USB3_EXTD_RX_F_P

USB3_PHY

USB2_PHY

USB2_EXTC_P

USB2

USB_EXTC_1_N

USB2_CONN

USB2

USB2_PHY

USB3

USB3_PHY

USB3_EXTC_RX_F_N

USB3_PHY

USB3_EXTA_RX_F_P

USB3

USB2_PHY

USB2_EXTB_N

USB2

CAM_SF_DIN_R

SPI

SPI_50S

SPI

CAM_SF_CLK_R

SPI_50S

USB2_PHY

USB2

USB2_EXTD_N

USB2_EXTD_P

USB2_PHY

USB2

USB3_RX_CONN

USB3

USB3_PHY

USB3_EXTD_RX_P

USB2_PHY

USB2

USB_EXTB_8_N

USB2_CONN

USB3_EXTC_RX_F_P

USB3

USB3_PHY

USB3

USB3_EXTC_TX_P

USB3_TX_CONN

USB3_PHY

USB3

USB3_PHY

USB3_EXTC_TX_F_N

USB3

USB3_PHY

USB3_EXTC_TX_F_P

USB3

USB3_TX_CONN

USB3_PHY

USB3_EXTC_TX_N

USB2_PHY

USB2

USB2_EXTB_P

USB3_EXTA_TX_P

USB3_TX_CONN

USB3

USB3_PHY

ENET_MDI

ENETCONN_MDI_N<3..0>

ENET_DIFF

ENET_DIFF_PHY

USB_EXTC_1_P

USB2_CONN

USB2_PHY

USB2

USB3_EXTC_TX_C_N

USB3_PHY

USB3

SD_PHY

SD

ENET_MEDIA_SENSE

SD

ENET_SD_DETECT_L

SD_PHY

SD

SDCONN_CLK_R

SPI

CIV_SPI

ENET_SCLK

SDCONN_CLK

SD_PHY

SD

USB2_CONN

USB_EXTD_9_N

USB2_PHY

USB2

USB3

USB3_PHY

USB3_EXTD_TX_F_P

USB3_TX_CONN

USB3_EXTD_TX_N

USB3_PHY

USB3

SPI

SPI_50S

CAM_SF_CLK

SPI

SPI_50S

CAM_SF_WP_L

ENET_CS_L

SPI

CIV_SPI

SMIA_DIFF

SMIA_DATA_N

SMIA_DP

SMIA_DIFF_PHY

SMB_PHY

SMB

I2C_CAMSENSOR_SCL

USB2_CONN_INT

USB2

USB2_PHY

USB_CAMERA_P

USB2

USB2_PHY

USB2_CONN_INT

USB_CAMERA_N

SPI

CAM_SF_DOUT

SPI_50S

SPI

CAM_SF_DOUT_R

SPI_50S

SMB

SMB_PHY

I2C_CAMSENSOR_SDA

SMIA_DIFF_PHY

SMIA_DP

SMIA_DIFF

SMIA_CLK_N

SMIA_DIFF

SMIA_DP

SMIA_DIFF_PHY

SMIA_CLK_P

SMIA_DATA_P

SMIA_DIFF

SMIA_DP

SMIA_DIFF_PHY

ENET_MISO

CIV_SPI

SPI

ENET_MOSI

SPI

CIV_SPI

SPI_50S

SPI

CAM_SF_DIN

SPI

SPI_50S

CAM_SF_CS_L

USB3_PHY

USB3_RX_CONN

USB3

USB3_EXTD_RX_N

ENET_TRANS

ENETCONN_MCT1

ENET_TRANS

ENETCONN_MDI_T_N<3..0>

ENET_DIFF_PHY

ENET_TRANS

ENETCONN_MDI_T_P<3..0>

USB3_PHY

USB3

USB3_EXTC_TX_C_P

USB3_EXTC_RX_N

USB3

USB3_RX_CONN

USB3_PHY

USB3

USB3_EXTC_RX_P

USB3_PHY

USB3_RX_CONN

USB2_PHY

USB2

USB_EXTB_8_P

USB2_CONN

PCH_USB_RBIAS

COMP_PCH

PCH_55S

USB2_CONN

USB_EXTD_9_P

USB2

USB2_PHY

USB3_RX_CONN

USB3_PHY

USB3

USB3_EXTA_RX_P

ENET_TRANS

ENETCONN_MCT2

USB3_PHY

USB3_EXTA_RX_F_N

USB3

ENETCONN_MDI_P<3..0>

ENET_DIFF

ENET_DIFF_PHY

ENET_MDI

USB3

USB3_PHY

USB3_EXTB_RX_F_N

USB2_PHY

USB2

USB2_EXTA_P

USB3

USB3_PHY

USB3_EXTA_TX_C_P

051-0164

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80 OF 86

36

35

35 37

35

42

36

35

13 43

43

13 42

42

13 42

42

13 32

32

42

32

13 42

42

13 43

13 42

42

13 42

42

13 43

43

13 43

13 42

42

38

43

13 42

13 43

43

13 43

42

13 42

35 36

13 43

43

11 35

35 37

37

35

35 37

13 43

43

13 43

38

35

38

13 38

38

35

38

43

36

43

13 42

13

13 43

42

36

13 42

35 36

13 42

42

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TMP423 (Development)

Electrical Contraint Set

Spacing

PCH

Electrical Contraint Set

Current/Voltage Sense

Electrical Contraint Set

Physical Net Type to Rule Map

Sensor-specific Spacing Definitions

SMC Generic Control Line Spacing Definitions

Constraints

SMBus-specific Spacing Definitions

Physical Net Type to Rule Map

SMBus-specific Physical Rules

SMBus

SMC

CPU Core

HDD

SSD

12V S5 (System Total)

SMC

PP1V05_S0_PCH

PP1V5_S0

Spacing

Physical

Airport

Constraints

Physical

Sensor

Sensor-specific Physical Rules

Spacing

Common

Spacing

SMBus

Display TCon

SSD Out-of-Band

HDD Out-of-Band

EMC1414-1 (Production)

Constraints

SMC

SMC Generic Control Line Physical Rules

Physical Net Type to Rule Map

Electrical Contraint Set

VDDQ S3 (DDR)

Physical

Temperature Sense

I1

I10

I102 I103

I104

I105

I11

I110

I111

I112

I113

I114

I115

I116

I117

I12

I123

I124

I13

I14

I15

I16

I19

I2

I20

I21

I3

I32

I33

I34

I35

I36

I4

I42

I43

I44 I45

I46

I5

I52

I53

I54

I55

I56

I57

I58

I59

I6

I60

I65

I66

I67

I68

I69

I7

I70

I71

I72

I73

I74

I75

I76

I77

I78

I8

I80

I81

I82

I83

I84

I85

I86

I87

I88

I89

I9

I90

I91

I92

I93

I94

GND

*

GND_P2MM

SENSE

=50_OHM_SE=50_OHM_SE

=STANDARD=STANDARD

SMC_50S

=50_OHM_SE=50_OHM_SE

*

SENSE

SENSE_ISO

* *

SMBus/Sensor Constraints

SYNC_DATE=01/10/2013SYNC_MASTER=J16_NICK

SMC_GEN

*

SMC_50S

SMC_CTRL

* *

SMC_ISO

SMB_55SSMB_PHY

*

=2x_DIELECTRIC

*

?

SMB_ISO

=1:1_SPACING

?

*

SMC_ISO

SMB_ISO

* *

SMB

SMB_55S

=55_OHM_SE

=STANDARD

=55_OHM_SE

*

=55_OHM_SE =55_OHM_SE

=STANDARD

PWR_P2MM

SENSE

*

POWER

=1.5:1_SPACING

SENSE_ISO

?

*

1:1_DIFFPAIR

*

SNS_DIFF_PHY

1:1_DIFFPAIR

*

=STANDARD

Y

=STANDARD

0.1 MM

0.085 MM

=STANDARD

ISNS_CPUVCC

SENSE

VSNS_CPUVCC

SENSE

SNS_CURRENT

SENSE

SNS_DIFF_PHY

ISNS_CPUVCC_FB_R

SNS_CURRENT

SENSE

SNS_DIFF_PHY

REG_CPUVCC_IMON_R

VSNS_VDDQS3_DDR

SENSE

SNS_TEMP

SENSE

SNS_T1_1_P

SNS_DIFF_PHY

VSNS_P12VG3H

SENSE

SNS_DIFF_PHY

SNS_CURRENT

SENSE

SNS_SSD_P SNS_SSD_N

SENSE

SNS_DIFF_PHY

SNS_CURRENT

SMBUS_SMC_5_G3H_SDA

SMB

SMB_PHY

SMBUS_SMC_5_G3H_SCL

SMB

SMB_PHY

ISNS_VDDQS3_DDR_R

SENSE

SNS_T2_1_N

SNS_DIFF_PHY

SNS_TEMP

SNS_DIFF_PHY

SNS_T1_2_P

SENSE

SML_PCH_0_DATA

SMB

SMB_PHY

TBT_I2C_55S

SMBUS_PCH_DATA

TBT_I2C

TBT_I2C_55S

SMBUS_PCH_CLK

TBT_I2C

SMB_DP_TCON_SCL

SMB_PHY

SMB

SMB_PHY

SMB

SMB_DP_TCON_SDA

SENSE

VSNS_P1V05S0_PCH

SNS_CURRENT

SNS_DIFF_PHY

SENSE

SNS_PVDDQS0_P

SNS_CURRENT

SENSE

SNS_DIFF_PHY

SNS_PVDDQS0_N

SENSE

ISNS_PVDDQS0_R

SENSE

VSNS_PVDDQS0

ISNS_P3V3S4_AP

SENSE

HDD_OOB1_D2R_L

SENSE

SMC_CTRL

SMC_GEN

SMC_LRESET_L

SMB_PHY

SMBUS_SMC_3_SCL

SMB

SNS_CURRENT

SNS_DIFF_PHY

SENSE

SNS_P3V3S4_AP_P

SENSE

ISNS_P3V3S4_AP_R

SMC_OOB2_R2D_L

SENSE

SMC_OOB1_R2D_L

SENSE

SNS_TEMP

SNS_T2_3_N

SNS_DIFF_PHY

SENSE

SNS_CURRENT

SNS_VDDQS3_DDR_P

SMB_PHY

SMBUS_SMC_1_S0_SCL

SMB

SMB_PHY

SMBUS_SMC_1_S0_SDA

SMB

SMBUS_SMC_2_S4_SCL

SMB_PHY

SMB

VSNS_HDDS0

SENSE

SMC_CTRL

SMC_GEN

SMC_RUNTIME_SCI_L

SMC_CTRL

SMC_GEN

SMC_WAKE_SCI_L

SMC_CTRL

SMC_GEN

SMC_FAN_0_CTL

ISNS_P12VG3H_R

SENSE

SNS_P12VG3H_P

SNS_CURRENT

SNS_DIFF_PHY

SENSE

GND_SMC_AVSS

SENSE

SMB_PHY

SMBUS_SMC_0_S0_SDA

SMB

SMB_PHY

SMBUS_SMC_2_S4_SDA

SMB

SMBUS_SMC_0_S0_SCL

SMB_PHY

SENSE

ISNS_SSDS0_R

VSNS_P3V3S5

SENSE

ISNS_SSDS0

ISNS_P12VG3H

SENSE

SNS_CURRENT

SENSE

SNS_DIFF_PHY

SNS_P3V3S4_AP_N

SMC_CTRL

SMC_GEN

SMC_FAN_0_TACH

SNS_VDDQS3_DDR_N

SNS_DIFF_PHY

SENSE

SNS_CURRENT

SENSE

ISNS_PVDDQS0

ISNS_VDDQS3_DDR

SENSE

SMB

SMB_PHY

SMBUS_SMC_3_SDA

SMB

SML_PCH_0_CLK

SMB_PHY

SNS_T1_3_P

SNS_TEMP

SENSE

SNS_DIFF_PHY

SMC_OOB2_D2R_L

SENSE

SNS_DIFF_PHY

SENSE

SNS_T2_3_P

SNS_TEMP

HDD_OOB1_D2R_F_L

SENSE SENSE

HDD_OOB1_D2R_R_L SMC_OOB1_D2R_L

SENSE

SMC_OOB1_R2D_R_L

SENSE

SNS_T1_1_N

SENSE

SNS_DIFF_PHY

SNS_TEMP

SNS_T1_3_N

SENSE

SNS_TEMP

SNS_DIFF_PHY

SNS_TEMP

SNS_DIFF_PHY

SENSE

SNS_ACDC_P

ISNS_HDDS0

SENSE

ISNS_HDDS0_R

SENSE

SNS_DIFF_PHY

SNS_CURRENT

SNS_HDD_N

SENSE

SNS_CURRENT

SNS_HDD_P

SENSE

SNS_DIFF_PHY

SNS_P12VG3H_N

SNS_DIFF_PHY

SNS_CURRENT

SENSE

SMC_XTAL

CLK_XTAL

XTAL

SMC_EXTAL

CLK_XTAL

XTAL

SENSE

ISNS_CPUVCC_FB

SNS_DIFF_PHY

SNS_T1_2_N

SENSE

SNS_TEMP

SNS_DIFF_PHY

SNS_ACDC_N

SENSE

SNS_T2_2_P

SENSE

SNS_TEMP

SNS_DIFF_PHY

SNS_T2_2_N

SENSE

SNS_TEMP

SNS_DIFF_PHY

SNS_TEMP

SENSE

SNS_DIFF_PHY

SNS_T2_1_P

051-0164

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81 OF 86

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48

45 49

50

45 48

49

44 45

49

50

13 47

40 47

45 48

49

45 49

45 48

34

20 44

44 47

48

33 45

34 44

50

49

44 47

45 48

14 44

44 51

48

44 45 48 49

44 47

49

45 49

45 48

48

44 51

49

45 49

44 47

13 47

50

33 45

50

34

34 44

34

50

50 60

45 48

48

44 45

48

50

50 60

50

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

Electrical Contraint Set

1.05V S0

VDDQ S3 (1.35V)/VTT S0

Power-specific Physical Rules

Physical Net Type to Rule Map

DC-DC Control

DC-DC

Local Ground

PCH/GPU/TBT 1.05V S0

Spacing

VDDQ S3

Input Bus

Voltage

DIDT

NO_TEST

Output Bus

NO_TEST

Physical

Voltage

DIDT

Input Bus

Sensed

Power and Common

DC-DC Control

DC-DC Baddies

Constraints

Power-specific Spacing Definitions

Physical

Local Ground

Spacing

FET Switched

DC-DC Baddies

Power and Common

Output Bus

FET Switched

I1

I10

I11

I12

I14

I18

I19

I2

I20

I21

I22

I23

I3

I4

I43

I44

I45

I46

I47

I48

I49

I5

I50

I51

I52

I53

I55 I56

I57

I58

I59

I6

I60

I61

I62

I63

I64

I66

I67

I7

I8

I9

VR_VID_ISO

* *

VR_VID

SWNODE_SW2GND

GND

*

VR_SWITCH

POWER

VR_SWITCH

*

SWNODE_SW2PWR

*

VR_SWITCH

BGA_P1MM

BGA

POWER_ISO

*

POWER

*

=STANDARD

*

?

GND_ISO

VR_CTL

VR_CTL_ISO

* *

=1:1_SPACINGSWNODE_SW2SW

*

?

1000

=8:1_SPACING

SWNODE_ISO

*

VR_VID_ISO

=4X_DIELECTRIC

?

=2:1_SPACING

*

?

SWNODE_SW2PWR

*

GND

*

GND_ISO

SWNODE_ISO

**

VR_SWITCH

VR_SWITCH VR_SWITCH

*

SWNODE_SW2SW

POWER_P3MM

*

VR_CTL_PHY

VR_VID_PHY

POWER_50S

*

VR_CTL_PHY

STANDARD

BGA

=2:1_SPACING

*

?

SWNODE_SW2GND

=3:1_SPACING

?

*

VR_CTL_ISO

STANDARD

VR_DIDT_PHY

BGA

POWER_P6MM

VR_DIDT_PHY

*

0.150 MM

=STANDARD*

0.600 MM

=STANDARDY

POWER_P6MM

12.7 MM

=STANDARD

0.300 MM 0.150 MM

Y =STANDARD*

POWER_P3MM

12.7 MM

*

=50_OHM_SE

POWER_50S

=50_OHM_SE

=STANDARD

=50_OHM_SE

=STANDARD

=50_OHM_SE

=STANDARD

0.500 MM 0.150 MM

=STANDARD* Y

GND_P5MM

12.7 MM

0.300 MM 0.150 MM

=STANDARD

GND_P3MM

=STANDARDY*

12.7 MM

=STANDARD

*

?

POWER_ISO

BGA

POWER POWER_P3MM

POWER_P6MMPOWER

*

BGA

GND_P3MM

GND

*

GND_P5MM

SYNC_MASTER=J16_NICK SYNC_DATE=01/10/2013

VReg Constraints

1.35V

PPVDDQ_S0_CPU

POWER POWER

0.675VPOWER_DDR POWER_DDR

PPDDRVTT_S0

REG_VDDQS3_MODE

VR_CTL

VR_CTL_PHY

1.35V

PPVDDQ_S0

POWER POWER

REG_VDDQS3_VREF

VR_CTL

VR_CTL_PHY

REG_VDDQS3_TRIP

VR_CTL

VR_CTL_PHY

VR_CTL

LDO_DDRVTTS0_SNS

REG_VCC_U7400

POWER

5V

POWER

GND GND

0V

AGND_P1V05S0

VR_CTL

VR_CTL_PHY

REG_P1V05S0_SREF

AGND_VDDQS3

GND

0V

GND

VR_CTL

VR_CTL_PHY

REG_VDDQS3_REFIN

1.35VPOWER

PPVDDQ_S3_DDR

POWER

TRUE

12VVR_SWITCH

VR_DIDT_PHY

REG_BOOT_VDDQS3

SENSE

REG_P1V05S0_RTN

VR_DIDT_PHY

VR_SWITCH

TRUE

12V

REG_PHASE_P1V05S0_L REG_BOOT_P1V05S0

VR_SWITCH

TRUE

VR_DIDT_PHY

12V

TRUETRUE

12V

VR_DIDT_PHY

VR_SWITCH

REG_BOOT_P1V05S0_RC

REG_UGATE_P1V05S0_R

VR_SWITCH

VR_DIDT_PHY

12V

TRUE TRUE

REG_LGATE_P1V05S0

12VVR_SWITCH

VR_DIDT_PHY

VR_CTL_PHY

VR_CTL

REG_VDDQS3_VTTREF

1.35VPOWER POWER

PPVDDQ_S3

REG_VDDQS3_VDDQSNS

VR_CTL

VR_CTL_PHY

VR_DIDT_PHY

VR_SWITCH

TRUE

12V

REG_UGATE_VDDQS3_R

VR_DIDT_PHY

REG_PHASE_VDDQS3

TRUE

VR_SWITCH 12V

TRUE

VR_DIDT_PHY

VR_SWITCH

TRUE

12V

REG_BOOT_VDDQS3_RC

TRUE

VR_SWITCH 12V

VR_DIDT_PHY

REG_UGATE_VDDQS3

REG_SNUBBER_VDDQS3

TRUE

12VVR_SWITCH

VR_DIDT_PHY

VR_SWITCH

TRUE

12V

VR_DIDT_PHY

REG_LGATE_VDDQS3

REG_PHASE_VDDQS3_L

TRUE

12VVR_SWITCH

VR_DIDT_PHY

REG_V5IN_U7300

POWERPOWER

5V

VR_DIDT_PHY

TRUE

12V

REG_PHASE_P1V05S0

VR_SWITCH

TRUE

VR_SWITCH

VR_DIDT_PHY

12V

REG_UGATE_P1V05S0

REG_P1V05S0_OCSET

VR_CTL_PHY

VR_CTL

5V

POWERPOWER

REG_PVCC_U7400

REG_SNUBBER_P1V05S0

VR_SWITCH

VR_DIDT_PHY

TRUE

12V

1.05VPOWER POWER

PP1V05_S0

POWERPOWER

PP1V05_TBTCIO

1.05V

POWER 1.05VPOWER

PP1V05_TBTLC

VR_CTL_PHY

VR_CTL

REG_P1V05S0_FSEL

SENSE

REG_P1V05S0_FB

REG_P1V05S0_VO

VR_CTL_PHY

VR_CTL

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Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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PAGE

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PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

CPU VCC Phases

Output Bus

Local Ground

Input Bus

NO_TESTVoltage NO_TEST

DIDT

Spacing

ISL6372

Electrical Contraint Set

Spacing

Physical DIDT

Electrical Contraint Set

Voltage

Physical

CPU VCC Controller

Phase 1

Phase 2

Phase 3

I1020

I1021

I1022

I1026

I1027

I1028

I1029 I1030

I1031

I1032

I1033

I1034

I1035

I1036

I1037

I1038

I1039 I1040

I1041

I1042

I1043

I1045 I1046

I1050

I1051

I1052

I1054

I1055

I1056

I1060

I1061

I1062

I1063

I1064

I1065

I1066

I1068

I1136

I1138

I1140 I1141

I1142

I1143

I1145

I1146

I1148

I1149

I1150

I1151

I1152

I1155

I1156

I1157

I1158

I1159

I1162

I1163

I1164 I1165

I1166

I1264

I1265

I1266

I1267

I836

I883

I884 I885

I887

I888

I890

I892

I893

I894

I895 I896

CPU VReg Constraints

SYNC_MASTER=J16_ROSSANA

SYNC_DATE=12/14/2012

SENSE

REG_ISENVCC_3_NR

ISNS_CPU_CORE

SENSE

SNS_DIFF_PHY

REG_ISENVCC_3_N

ISNS_CPU_CORE

SENSE

SNS_DIFF_PHY

REG_ISENVCC_3_P

1.8V

POWERPOWER

PPCPUVCC_S0_SENSE_3

VR_CTL_PHY

VR_SWITCH 12V

TRUE

REG_SNUBBER_CPUVCC_3

ISNS_CPU_CORE

SENSE

REG_ISENVCC_2_N

SNS_DIFF_PHY

SENSE

REG_ISENVCC_2_NR

1.8V

POWER

PPCPUVCC_S0_SENSE_2

POWER

SNS_DIFF_PHY

REG_ISENVCC_2_P

SENSE

ISNS_CPU_CORE

12V

VR_DIDT_PHY

VR_SWITCH

TRUE

REG_SNUBBER_CPUVCC_2

SENSE

REG_ISENVCC_1_NR

ISNS_CPU_CORE

SNS_DIFF_PHY

SENSE

REG_ISENVCC_1_N

ISNS_CPU_CORE

SENSE

SNS_DIFF_PHY

REG_ISENVCC_1_P

PPCPUVCC_S0_SENSE_1

POWER

1.8V

POWER

TRUE

12VVR_SWITCH

VR_DIDT_PHY

REG_SNUBBER_CPUVCC_1

REG_THWN_1

VR_CTL_PHY

VR_CTL

VR_CTL_PHY

REG_PWM_CPUVCC_1_R

VR_CTL_PHY

REG_PWM_CPUVCC_1

VR_CTL

TRUE

12VVR_SWITCH

VR_DIDT_PHY

REG_BOOT_CPUVCC_1

12VVR_SWITCH

VR_DIDT_PHY

REG_BOOT_CPUVCC_1_RC

TRUETRUE

REG_BOOT_CPUVCC_3_RC

TRUETRUE

12VVR_SWITCH

VR_DIDT_PHY

REG_BOOT_CPUVCC_3

VR_SWITCH

TRUE

12V

VR_DIDT_PHY

REG_PHASE_CPUVCC_2

12V

TRUE

VR_DIDT_PHY

VR_SWITCH

REG_PHASE_CPUVCC2

VR_SWITCH

VR_DIDT_PHY

TRUE

12V

REG_BOOT_CPUVCC_2_RC

TRUE

12V

TRUE

VR_SWITCH

VR_DIDT_PHY

REG_BOOT_CPUVCC_2

12V

TRUE

VR_SWITCH

VR_DIDT_PHY

GND

0V

AGND_CPU

GND

VR_CTL

VR_CTL_PHY

REG_PWM_CPUVCC_2

VR_CTL_PHY

VR_CTL

REG_PWM_CPUVCC_2_R

VR_CTL

CPUVCC_FB_RC

VR_CTL_PHY

VR_CTL

CPUVCC_FB_R_1

VR_CTL_PHY

VR_CTL

REG_CPUVCC_HFCOMP

VSNS_CPU_CORE

SENSE

SNS_DIFF_PHY

CPU_VCCSENSE_P

SNS_DIFF_PHY

SENSE

VSNS_CPU_CORE

CPU_VCCSENSE_N

SNS_DIFF_PHY

SENSE

CPU_VCCSENSE_R_P

SNS_DIFF_PHY

SENSE

CPU_VCCSENSE_R_N

1.8V

SNS_DIFF_PHY

SENSE

SNS_VCC_XW_P

SENSE

REG_CPUVCC_VSEN

SENSE

REG_CPUVCC_RGND

VR_CTL_PHY

VR_CTL

REG_CPUVCC_PSICOMP

VR_VID

VR_VID_PHY

CPU_VIDSOUT

VR_VID

VR_VID_PHY

CPU_VIDALERT_L

VR_VID_PHY

VR_VID

CPU_VIDSCLK

VR_VID_PHY

VR_VID

CPU_VIDSCLK_R

VR_VID

VR_VID_PHY

CPU_VIDALERT_R_L

VR_VID

VR_VID_PHY

CPU_VIDSOUT_R

REG_THWN_2

VR_CTL

VR_CTL_PHY

VR_CTL

REG_CPUVCC_COMP

VR_CTL_PHY

VR_CTL

REG_CPUVCC_FB

SENSE

SNS_DIFF_PHY

0V

SNS_VCC_XW_N

SENSE

REG_CPUVCC_VIN

VR_CTL

VR_CTL_PHY

REG_CPUVCC_IMON

VR_CTL

VR_CTL_PHY

CPUVCC_IMON_R

VR_CTL_PHY

VR_CTL

REG_CPUVCC_RSET

1.8V

POWER POWER

PPCPUVCC_S0_CPU

VR_CTL

VR_CTL_PHY

REG_CPUVCC_DVC

VR_CTL

VR_CTL_PHY

CPUVCC_FB_RC_2

VR_CTL

VR_CTL_PHY

REG_CPUVCC_TM

VR_CTL_PHY

VR_CTL

REG_CPUVCC_IMX

VR_CTL

VR_CTL_PHY

CPUVCC_DVC_RC

VR_CTL_PHY

VR_CTL

REG_CPUVCC_TMX

VR_CTL

VR_CTL_PHY

REG_CPUVCC_NPSI

VR_CTL_PHY

VR_CTL

REG_CPUVCC_MEMVRSEL

VR_CTL

VR_CTL_PHY

REG_CPUVCC_FDVID

REG_PHASE_CPUVCC_3

VR_DIDT_PHY

TRUE

12VVR_SWITCH

TRUE

12V

VR_DIDT_PHY

VR_SWITCH

REG_PHASE_CPUVCC1

VR_CTL_PHY

VR_CTL

CPUVCC_COMP_RC

VR_CTL_PHY

CPUVCC_FB_R_2

VR_CTL

CPUVCC_PSICOMP_RC

VR_CTL

VR_CTL_PHY

REG_PHASE_CPUVCC_1

TRUE

12VVR_SWITCH

VR_DIDT_PHY

REG_PHASE_CPUVCC3

VR_SWITCH 12V

TRUE

VR_DIDT_PHY

VR_CTL

REG_PWM_CPUVCC_3_R

VR_CTL_PHY

VR_CTL

REG_PWM_CPUVCC_3

REG_THWN_3

VR_CTL

VR_CTL_PHY

POWER

12V

POWER

PP12V_S0_CPUVCC_FLT

POWER

5V

POWER

REG_VCC_U7000

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61 62

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8

61

9

61

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61

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61

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61

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Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DIDT

FET Switched

Spacing Voltage

OUTPUT BUS

Physical

12V

Ground/Common

Spacing

Physical

1V5 S0

FET Switched

NO_TEST

NO_TESTVoltage

DIDT

Spacing

Physical

HDD S0

Sensed

Input Bus

Sensed

Physical

Spacing Voltage

DIDT

NO_TEST

Physical

Output Bus

3.3V G3

Spacing Voltage

3.42V G3H

Physical

Spacing Voltage

DIDT

NO_TEST

Sensed

FET Switched

Output Bus

5V S3

3.3V S5

Input Bus

Physical

Spacing

3.3V S5/5V S4

Voltage

DIDT

NO_TEST

NO_TESTVoltage

DIDT

Common

I1071

I1072

I1077

I1078

I1082

I1136

I1137 I1138

I1139

I1140 I1141

I1142

I1143

I1144

I1145

I1146

I1147

I1148

I1149

I1151

I1153

I1218

I1219

I1233

I1236

I1254 I1255

I1382

I1390

I1392

I1443

I1444

I1445

I1446

I1447

I1448

I1449

I1451

I1452

I1453

I1454

I1460

I1475

I1476

I1477

I1481 I1482

I1483

I843

I847

I848

I849

I850

I851

I852

SYNC_DATE=12/20/2012

Platform VReg Constraints

SYNC_MASTER=J16_ROSSANA

VR_CTL

VR_CTL_PHY

REG_P3V3S5_VOUT

REG_P1V5S0_ADJ

VR_CTL_PHY

VR_CTL

REG_P1V5S0_ISET

VR_CTL

VR_CTL_PHY

REG_P3V3S5_VOUT_R

VR_CTL

VR_CTL_PHY

REG_P3V3S5_FB

VR_CTL

VR_CTL_PHY

TRUE

VR_SWITCH 12V

REG_PHASE_P3V3S5

VR_DIDT_PHY

VR_SWITCH

VR_DIDT_PHY

12V

TRUE

REG_BOOT_P3V3S5

VR_DIDT_PHY

TRUE

VR_SWITCH

REG_LGATE_P3V3S5

12V

VR_DIDT_PHY

REG_BOOT_P5VS4

VR_SWITCH 12V

TRUE

REG_UGATE_P5VS4

TRUE

12VVR_SWITCH

VR_DIDT_PHY

VR_SWITCH

REG_LGATE_P5VS4

TRUE

12V

VR_DIDT_PHY

12V

TRUE

VR_SWITCH

VR_DIDT_PHY

REG_SNUBBER_P3V3S5

VR_SWITCH

REG_BOOT_P3V3S5_RC

TRUE

12V

TRUE

VR_DIDT_PHY

POWER

REG_VCC2_U7600

POWER

5V

REG_P3V3S5_FSET

VR_CTL

VR_CTL_PHY

REG_P3V3S5_OCSET

VR_CTL_PHY

VR_CTL

REG_P3V3S5_ISEN

VR_CTL_PHY

VR_CTL

REG_BOOT_P5VS4_RC

TRUE

VR_SWITCH 12V

TRUE

VR_DIDT_PHY

VR_SWITCH

REG_UGATE_P3V3S5

VR_DIDT_PHY

12V

TRUE

VR_SWITCH

VR_DIDT_PHY

REG_PHASE_P5VS4

12V

TRUE

REG_SNUBBER_P5VS4

VR_SWITCH 12V

VR_DIDT_PHY

VR_CTL

REG_P5VS4_ISEN

VR_CTL_PHY VR_CTL_PHY

VR_CTL

REG_P5VS4_OCSET

VR_CTL

VR_CTL_PHY

REG_P5VS4_FSET

REG_P5VS4_VOUT

VR_CTL

VR_CTL_PHY

VR_CTL

REG_P5VS4_VOUT_R

VR_CTL_PHY

POWER

PP5V_S5

5V

POWER

REG_P5VS4_FB

VR_CTL_PHY

VR_CTL

POWER

3.3V

POWER

PP3V3_S5

POWER

PP3V3_S4

3.3V

POWER

3.3V

PP3V3_TBTLC

POWERPOWER

PP3V3_S0_SSD

3.3V

POWERPOWER

POWER POWER

PP3V3_S0

3.3V

PP3V3_ENET

POWER POWER

3.3V

TRUE

VR_SWITCH

POWER

12V

P3V42G3H_SW

VR_CTL_PHY

VR_CTL

P3V42G3H_SHDN_L

PP12V_ACDC

12V

POWER POWER

POWER

12V

POWER

PP12V_G3H

5V

PP5V_S0_HDD

POWER POWER

POWER

5V

POWER

PPHDD_S0

GND

0V

GNDGND

POWER

REG_VIN_U7600

POWER

12V

POWER

REG_VCC1_U7600

POWER

5V

POWER POWER

5V

PP5V_S4

PP5V_S0

5V

POWERPOWER

POWER

PPSSD_S0

3.3V

POWER POWER POWER

3.3V

PP3V3_S4_AP

REG_P1V5S0_SS

VR_CTL

VR_CTL_PHY

POWER POWER

1.5V

PP1V5_S0

3.425V

PP3V42_G3H

POWER POWER

POWER

12V

PP12V_S5

POWER

PP12V_S0

12V

POWERPOWER

3.3V

PP3V3_G3

POWERPOWER

TRUE

P3V42G3H_BOOST

12V

POWER

VR_SWITCH

VR_CTL_PHY

VR_CTL

P3V42G3H_FB

051-0164

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64

65

70

65

70

60

70

65

70

64

70

60

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

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A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

*: Only used on hosts supporting T29 video-in

Graphics Source

Electrical Contraint Set

DisplayPort

Physical

DP-specific Spacing Definitions

Pairs should be within 100 mils of clock length.

DisplayPort AUX channel intra-pair matching should be 5 ps. No relationship to other signals.

Electrical Contraint Set

Physical

Spacing

Internal Panel

Internal DP SPDIF

Spacing

Thunderbolt

Thunderbolt-specific Spacing Definitions

Max length of DisplayPort traces: 12 inches

DP-specific Physical Rules

DisplayPort

DisplayPort intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps.

*

Port A

Electrical Contraint Set

TBT/DP Net Properties

Port B

Spacing

Thunderbolt-specific Physical Rules

Physical

TBT IC Net Properties

SOURCE: Bill Cornelius’s T29 Routing Notes

I511

I512

I513

I514

I515

I516

I517

I518

I519

I520

I521

I522

I523

I524

I525

I526

I529 I530

I531 I532

I533 I534

I535

I538

I541

I542

I543

I544

I545

I546

I547

I548

I549

I550

I563

I564

I565

I566

I595

I596

I599 I600

I601 I602

I603

I604

I605

I606 I607

I608

I609 I610

I611

I642

I643 I644

I645

I646 I647

I648

I649

I650 I651

I652

I653

I654

I655

I656

I657

I658

I659

I660

I661

I662

I663

I664

I665

I666

I667

I668

I669 I670

I671

I672

I673

I674

I675

I676

I677

I678

I679

I680 I681

I682

I683

I684

I685

I686

I687

I688

I689

I690

I691

=55_OHM_SE

=STANDARD

=55_OHM_SE =55_OHM_SE

* =STANDARD

TBT_I2C_55S

=55_OHM_SE

TOP,BOTTOM?=7x_DIELECTRIC

TBTDP

*

=2x_DIELECTRIC

?

TBT_I2C

=90_OHM_DIFF

*

=90_OHM_DIFF=90_OHM_DIFF

=90_OHM_DIFF

TBTDP_90D

=90_OHM_DIFF

*

?

=5x_DIELECTRIC

TBTDP

?

=2x_DIELECTRIC

*

TBT_SPI

=55_OHM_SE

*

=55_OHM_SE =55_OHM_SE

=STANDARD

=55_OHM_SE

=STANDARD

TBT_SPI_55S

=85_OHM_DIFF

0.08MM

*

=85_OHM_DIFF

DP_85D

=85_OHM_DIFF

TBT/DP Constraints

SYNC_DATE=12/03/2012

SYNC_MASTER=J16_MLB

DISPLAYPORT

*

=3:1_SPACING

?

TBTDP_90D

TBTDP

TBT_B_D2R_P<1>

TBT_B_D2R1

DP_TBTPA_AUXCH_C_N

TBT_A_AUXCH

DP_85D

DISPLAYPORT

DP_TBTPA_AUXCH_N

DP_85D

DISPLAYPORT

DP_A_AUXCH_DDC

DISPLAYPORT

DP_85D

DP_A_AUXCH_DDC_N

TBTDP

TBTDP_90D

TBT_A_D2R1_AUXDDC_P

TBTDP_90D

TBTDP

TBT_A_D2R1_AUXDDC_N

DP_A_AUXCH_DDC

DISPLAYPORT

DP_85D

DP_A_AUXCH_DDC_P

DP_TBTPA_AUXCH_P

DISPLAYPORT

DP_85D

TBT_A_D2R0

TBTDP

TBT_A_D2R_P<0>

TBTDP_90D

DP_85D

DP_TBTSNK0_ML_C_P<3..0>

DISPLAYPORT

TBT_B_D2R_C_P<1..0>

TBTDP

TBTDP_90D

TBT_B_D2R_C_N<1..0>

TBTDP

TBTDP_90D

TBT_B_AUXCH

DP_TBTPB_AUXCH_C_P

DISPLAYPORT

DP_85D

DP_TBTPB_AUXCH_P

DISPLAYPORT

DP_85D

DISPLAYPORT

DP_TBTPB_AUXCH_N

DP_85D

DP_B_AUXCH_DDC

DP_B_AUXCH_DDC_N

DISPLAYPORT

DP_85D

TBT_B_D2R1_AUXDDC_N

TBTDP_90D

TBTDP

TBT_B_D2R1_AUXDDC_P

TBTDP_90D

TBTDP

TBTDP_90D

TBTDP

TBT_B_D2R1

TBT_B_D2R_N<1>

TBT_B_D2R0

TBTDP

TBTDP_90D

TBT_B_D2R_P<0>

TBTDP_90D

TBT_B_D2R0

TBTDP

TBT_B_D2R_N<0>

DP_TBTSNK0_ML

DP_85D

DISPLAYPORT

DP_TBTSNK0_ML_N<3..0>

DISPLAYPORT

DP_85D

DP_TBTSNK0_ML_C_N<3..0>

TBTDP

TBTDP_90D

TBT_B_R2D_C_N<0>

TBT_B_R2D0

TBTDP

TBTDP_90D

TBT_B_R2D0

TBT_B_R2D_C_P<0>

TBTDP_90D

TBTDP

TBT_B_R2D1

TBT_B_R2D_C_P<1>

TBTDP_90D

TBTDP

TBT_B_R2D1

TBT_B_R2D_C_N<1>

DISPLAYPORT

DP_B_AUXCH_DDC

DP_B_AUXCH_DDC_P

DP_85D

DP_TBTPB_AUXCH_C_N

DISPLAYPORT

DP_85D

TBT_B_AUXCH

DP_B_LSX

DISPLAYPORT

DP_85D

DP_B_LSX_ML_P<1>

DP_B_LSX

DP_85D

DISPLAYPORT

DP_B_LSX_ML_N<1>

DP_TBTPB_ML_N<3>

DISPLAYPORT

DP_85D

DP_TBTPB_ML_P<3>

DP_85D

DISPLAYPORT

DP_TBTPB_ML_N<1>

DP_85D

DISPLAYPORT

DP_TBTPB_ML_P<1>

DISPLAYPORT

DP_85D

DP_TBTPB_ML3

DP_TBTPB_ML_C_N<3>

DP_85D

DISPLAYPORT

DP_TBTPB_ML3

DP_TBTPB_ML_C_P<3>

DP_85D

DISPLAYPORT

DP_TBTPB_ML1

DP_TBTPB_ML_C_N<1>

DISPLAYPORT

DP_85D

DP_TBTPB_ML_C_P<1>

DP_TBTPB_ML1

DISPLAYPORT

DP_85D

TBT_B_R2D_N<1..0>

TBTDP

TBTDP_90D

TBT_B_R2D_P<1..0>

TBTDP_90D

TBTDP

TBT_A_AUXCH

DP_85D

DP_TBTPA_AUXCH_C_P

DISPLAYPORT

TBT_A_D2R0

TBTDP

TBT_A_D2R_N<0>

TBTDP_90D

TBTDP

TBT_A_D2R_P<1>

TBT_A_D2R1

TBTDP_90D

TBT_A_D2R1

TBTDP

TBT_A_D2R_N<1>

TBTDP_90D

TBTDP

TBT_A_D2R_C_N<1..0>

TBTDP_90D

TBTDP

TBT_A_D2R_C_P<1..0>

TBTDP_90D

DP_A_LSX

DISPLAYPORT

DP_A_LSX_ML_N<1>

DP_85D

DP_A_LSX

DP_A_LSX_ML_P<1>

DISPLAYPORT

DP_85D

DISPLAYPORT

DP_TBTPA_ML_N<3>

DP_85D

DISPLAYPORT

DP_TBTPA_ML_P<3>

DP_85D

DISPLAYPORT

DP_TBTPA_ML_N<1>

DP_85D

DISPLAYPORT

DP_TBTPA_ML_P<1>

DP_85D

DISPLAYPORT

DP_85D

DP_TBTPA_ML3

DP_TBTPA_ML_C_P<3>

DISPLAYPORT

DP_TBTPA_ML3

DP_TBTPA_ML_C_N<3>

DP_85D

DISPLAYPORT

DP_85D

DP_TBTPA_ML1

DP_TBTPA_ML_C_N<1>

TBTDP

TBTDP_90D

TBT_A_R2D_N<1..0>

DP_85D

DISPLAYPORT

DP_TBTPA_ML1

DP_TBTPA_ML_C_P<1>

TBTDP

TBTDP_90D

TBT_A_R2D_P<1..0>

TBTDP

TBTDP_90D

TBT_A_R2D_C_N<0>

TBT_A_R2D0

TBTDP

TBTDP_90D

TBT_A_R2D_C_P<0>

TBT_A_R2D0

TBTDP_90D

TBTDP

TBT_A_R2D_C_P<1>

TBT_A_R2D1

TBTDP_90D

TBTDP

TBT_A_R2D_C_N<1>

TBT_A_R2D1

TBT_SPI

TBT_SPI_MISO

TBT_SPI_55S

TBT_SPI_MISO

TBT_SPI

TBT_SPI_55S

TBT_SPI_CS_L

DP_85D

DISPLAYPORT

DP_INT_AUX_C_P

DISPLAYPORT

DP_85D

DP_INT_AUX_C_N

DP_INT_SPDIF_AUDIO

HDA

DISPLAYPORT

DP_85D

DP_TBTSNK0_AUXCH_C_P DP_TBTSNK0_AUXCH_C_N

DISPLAYPORT

DP_85D

DP_TBTSNK0_ML

DISPLAYPORT

DP_85D

DP_TBTSNK0_ML_P<3..0>

DP_TBTSNK0_AUXCH_N

DP_TBTSNK0_AUX

DP_85D

DISPLAYPORT

DP_85D

DISPLAYPORT

DP_INTPNL_ML_CONN

DP_INTPNL_ML_P<3..0>

DP_85D

DP_INTPNL_ML_CONN

DP_INTPNL_ML_N<3..0>

DISPLAYPORT

DP_85D

DP_INTPNL_ML_C_N<3..0>

DP_INTPNL_AUX_CONN

DISPLAYPORT

DP_INTPNL_AUX_P

DP_85D

DISPLAYPORT

DP_INTPNL_AUX_CONN

DP_INTPNL_AUX_N

DP_85D

DISPLAYPORT

DP_INTPNL_ML_C_P<3..0>

DP_85D

DISPLAYPORT

DP_INTPNL_EG_AUX_MUX

DP_INT_AUX_N

DISPLAYPORT

DP_TBTSNK1_ML

DP_85D

DP_TBTSNK1_ML_N<3..0>

DP_85D

DP_TBTSRC_AUXCH_N

DP_INTPNL_TBT_AUX_MUX

DISPLAYPORT

TBT_SPI_MOSI

TBT_SPI

TBT_SPI_55S

TBT_SPI_CLK

TBT_SPI

TBT_SPI_55S

DP_85D

DISPLAYPORT

DP_TBTSNK1_ML_C_N<3..0>

DP_TBTSNK0_AUX

DP_85D

DISPLAYPORT

DP_TBTSNK0_AUXCH_P

DP_TBTSRC_AUX_C_N

DP_85D

DISPLAYPORT

DP_85D

DP_TBTSRC_AUX_C_P

DISPLAYPORT

DP_TBTSNK1_AUXCH_P

DP_TBTSNK1_AUX

DP_85D

DISPLAYPORT

DP_TBTSNK1_AUXCH_C_P

DP_85D

DISPLAYPORT

DP_85D

DP_TBTSNK1_ML_C_P<3..0>

DISPLAYPORT

DP_85D

DP_TBTSNK1_AUXCH_N

DP_TBTSNK1_AUX

DISPLAYPORT

DP_INTPNL_TBT_ML_MUX

DISPLAYPORT

DP_85D

DP_TBTSRC_ML_P<3..0>

DISPLAYPORT

DP_TBTSNK1_AUXCH_C_N

DP_85D

DP_TBTSNK1_ML

DP_85D

DISPLAYPORT

DP_TBTSNK1_ML_P<3..0>

TBT_I2C

TBT_I2C_55S

I2C_TBTRTR_SDA

TBT_I2C_55S

TBT_I2C

I2C_TBTRTR_SCL

DISPLAYPORT

DP_85D

DP_TBTSRC_AUXCH_P

DP_INTPNL_TBT_AUX_MUX

DP_TBTSRC_ML_C_N<3..0>

DISPLAYPORT

DP_85D

DP_INTPNL_TBT_ML_MUX

DP_TBTSRC_ML_C_P<3..0>

DP_85D

DISPLAYPORT

DP_INTPNL_TBT_ML_MUX

DP_TBTSRC_ML_N<3..0>

DISPLAYPORT

DP_85D

DP_INTPNL_EG_AUX_MUX

DP_85D

DISPLAYPORT

DP_INT_AUX_P

DP_85D

DP_INTPNL_EG_ML_MUX

DISPLAYPORT

DP_INT_ML_N<1..0>

DP_INTPNL_EG_ML_MUX

DISPLAYPORT

DP_85D

DP_INT_ML_P<1..0>

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Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

Is it chel’oh or sel’oh?

Cello Miscellaneous

Local Ground

NO_TEST

BLC High Voltage Output

Physical

Input Bus

Voltage

DIDT

BLC-specific Spacing Definitions

Physical Net Type to Rule Map

BLC-specific Physical Rules

Backlight Controller

BLC Control

BLC BaddiesBLC Baddies

BLC Control

Constraints

Backlight

Output Bus

Physical

Spacing

Electrical Contraint Set

SPI

BLC High Voltage Output

Spacing

I563

I564

I749

I750

I751

I752

I753 I754

I755 I757

I759

I762

I763

I764

I765

I770

I772

I773 I774

I775

I776

I777

I778

I779

I780

I782

I783

I784

I785

I786 I787

I788

I789

I790

I791 I792

I793

I794 I795

I796

I797

I798

I799 I800

I801

I802

*

BLC_HV_ISO

0.45mm

1000

PHASE_SW2GND =2:1_SPACING

*

?

*

BLC_HV

BLC_CTL

BLC_CTL_ISO

*

BLC_HV

BLC_CTL_ISO

BLC_HV

*

BLC_HV

BLC_HV_ISO

*

=3:1_SPACING

?

BLC_CTL_ISO

PHASE_SW2PWR =2:1_SPACING

*

?

PHASE_SW2SW

*

?

=1:1_SPACING

=8:1_SPACING

*

2000

PHASE_ISO

**

BLC_CTL_ISO

BLC_CTL

PHASE_SW2SW

BLC_PHASEBLC_PHASE

*

BLC_PHASE

GND

*

PHASE_SW2GND

PHASE_SW2PWR

POWER

BLC_PHASE

*

BLC_P6MM

POWER_BLC

*

BLC_P3MM

POWER_BLC_RET

*

BLC_P3MM

BLC_CTL_PHY

*

BLC_P6MM

*

3.0 MM

Y =STANDARD=STANDARD

0.100 MM0.600 MM

* =STANDARD=STANDARD

BLC_P3MM 0.300 MM

3.0 MM

Y

0.100 MM

**

BLC_PHASE PHASE_ISO

SYNC_MASTER=J16_MLB

SYNC_DATE=12/03/2012

BLC Constraints

BKLT_ISEN1_R

POWER_BLC_RET

BLC_HV

POWER_BLC_RET

BKLT_ISEN3_R

BLC_HV BLC_HV

BKLT_ISEN4_R

POWER_BLC_RET

PP12V_S0_BKLT_PWR_R

12V

POWER POWER

80V

BLC_CTL_PHY

TRUE

BLC_PHASE

BKLT_GATE_R

BLC_CTL

BLC_CTL_PHY

BKLT_ISET

BLC_CTL

BLC_CTL_PHY

BKLT_FLT

80VBLC_PHASE

BLC_CTL_PHY

TRUE

BKLT_SNUBBER

TRUE

BKLT_PHASE

POWER_BLC BLC_PHASE 80V

0V

BLC_PHASE

LGND_BKLT

BLC_CTL_PHY

3.3V

PP3V3_S0_BKLT_VDDIO_R

POWER POWER

PP12V_S0_BKLT_PWR

POWER

12V

POWER

PP12V_BKLT_FUSED

12V

POWER POWER

SMB

SMB_PHY

BKLT_SDA

POWER_BLC 67VBLC_HV

BKLT_BOOST_2

POWER_BLC BLC_HV 67V

BKLT_BOOST

LED_RETURN_6

POWER_BLC_RET

BLC_HV

LED_RETURN_4

POWER_BLC_RET

BLC_HV

POWER_BLC_RET

BLC_HV

LED_RETURN_5

LED_RETURN_3

POWER_BLC_RET

BLC_HV

POWER_BLC_RET

BLC_HV

LED_RETURN_2

POWER_BLC_RET

LED_RETURN_1

BLC_HV

POWER_BLC_RET

BKLT_ISEN5_R

BLC_HV

BKLT_ISEN6_R

POWER_BLC_RET

BLC_HV

BKLT_ISEN2_R

BLC_HV

POWER_BLC_RET

BKLT_ISEN6

POWER_BLC_RET

BLC_CTL

POWER_BLC_RET

BLC_CTL

BKLT_ISEN4

POWER_BLC_RET

BLC_CTL

BKLT_ISEN5

BLC_CTL

BKLT_ISEN1

POWER_BLC_RET

SENSE

BKLT_FB

SNS_DIFF_PHY

SENSE

BKLT_SW_N

BLC_CTL

BKLT_FLT_RC

BLC_CTL_PHY

BKLT_SW_P

SNS_DIFF_PHY

SENSE

12V

TRUE

BLC_PHASE

BLC_CTL_PHY

BKLT_SW_R

BKLT_GATE

BLC_PHASE 80V

BLC_CTL_PHY

TRUE

BLC_CTL_PHY

BLC_PHASE

PGND_BKLT

0V

POWER

12V

PP12V_S0_BKLT_FILT

POWER

5V

PP5V_S0_BKLT_R

POWER POWER

BKLT_FB_R

67VBLC_HV

BKLT_FB_XW

67VBLC_HV

BKLT_SCL

SMB

SMB_PHY

POWER_BLC 67VBLC_HV

BKLT_BOOST_1

BLC_CTL

BKLT_ISEN3

POWER_BLC_RET

BLC_CTL

BKLT_ISEN2

PP12V_BKLT_SNS

12V

POWER POWER

0V

BLC_PHASE

DGND_BKLT

BLC_CTL_PHY

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