Apple 820-3024 Schematic

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DRAWING

TABLE_TABLEOFCONTENTS_HEADTABLE_TABLEOFCONTENTS_HEAD

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

3

B

7

ECNREV

BRANCH

DRAWING NUMBER

REVISION

SIZE

D

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

DRAWING TITLE

THE POSESSOR AGREES TO THE FOLLOWING:

Apple Inc.

SHEET

R

DATE

D

A

C

THE INFORMATION CONTAINED HEREIN IS THE

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

C

3456

D

B

8 7 6 5 4 2 1

12

APPD

CK

DESCRIPTION OF REVISION

K78 MLB SCHEMATIC

Schematic / PCB #’s

NUMBER, UL PCB MATERIAL DESIGNATION, 130-C TEMP. RATING AND V-0 FLAME RATING.

PCB TO BE SILK-SCREENED WITH UL/CUL RECOGNITION MARK, MANUFACTURER’S UL FILE

PCB, UL RECOGNIZED, MIN. 130-C TEMP. RATING AND V-0 FLAME RATING PER UL 796 & UL 94.

PRODUCT SAFETY REQUIREMENTS:

04/08/11

1 OF 74

051-8871

2.5.0

1 OF 109

2011-04-08

High Side Current Sensing

54

12/13/2010

45

K21_MLB

Voltage & Load Side Current Sensing

53

12/13/2010

44

K21_MLB

SMBus Connections

52

12/13/2010

43

K21_MLB

LPC+SPI Debug Connector

51

12/13/2010

42

K21_MLB

SMC Support

50

12/13/2010

41

K21_MLB

SMC

49

12/13/2010

40

K21_MLB

LIO CONNECTORS

47

N/A

39 N/A

External USB Connectors

46

12/13/2010

38

K21_MLB

SATA CONNECTOR

45

12/13/2010

37

K21_MLB

X21 WIRELESS CONNECTOR

40

12/13/2010

36

K21_MLB

T29 Power Support

38

12/13/2010

35

K21_MLB

T29 Host (2 of 2)

37

12/13/2010

34

K21_MLB

T29 Host (1 of 2)

36

12/13/2010

33

K21_MLB

DDR3 DRAM Channel B (32-63)

34

12/13/2010

32

K21_MLB

FSB/DDR3/FRAMEBUF Vref Margining

33

12/13/2010

31

K21_MLB

DDR3 DRAM CHANNEL B (32-63)

32

12/13/2010

30

K21_MLB

DDR3 DRAM CHANNEL B (0-31)

31

12/13/2010

29

K21_MLB

DDR3 DRAM CHANNEL A (32-63)

30

12/13/2010

28

K21_MLB

DDR3 DRAM CHANNEL A (0-31)

29

12/13/2010

27

K21_MLB

CPU Memory S3 Support

28

12/13/2010

26

K21_MLB

Clock (CK505) and Chipset Support

27

11/30/2010

25

K21_MLB

USB HUBS

26

12/13/2010

24

K21_MLB

CPU & PCH XDP

25

12/13/2010

23

K21_MLB

PCH DECOUPLING

24

12/13/2010

22

K21_MLB

PCH GROUNDS

23

12/13/2010

21

K21_MLB

PCH POWER

22

12/13/2010

20

K21_MLB

PCH MISC

21

12/13/2010

19

K21_MLB

PCH PCI/FLASHCACHE/USB

20

12/13/2010

18

K21_MLB

PCH DMI/FDI/GRAPHICS

19

12/13/2010

17

K21_MLB

PCH SATA/PCIE/CLK/LPC/SPI

18

12/13/2010

16

K21_MLB

CPU DECOUPLING-II

17

12/13/2010

15

K21_MLB

CPU DECOUPLING-I

16

12/13/2010

14

K21_MLB

CPU GROUNDS

14

12/13/2010

13

K21_MLB

CPU POWER

13

12/13/2010

12

K21_MLB

CPU DDR3 INTERFACES

12

12/13/2010

11

K21_MLB

CPU CLOCK/MISC/JTAG

11

12/13/2010

10

K21_MLB

CPU DMI/PEG/FDI/RSVD

10

12/13/2010

9

K21_MLB

Signal Aliases

9

05/15/2010

8

K91_MLB

Power Aliases

8

05/15/2010

7

K91_MLB

Functional Test / No Test

7

(02/16/2010)

6 (K99_MLB)

BOM Configuration

5

11/16/2010

5

K21_MLB

K78 BOM Variants

4

11/16/2010

4

K21_MLB

Power Block Diagram

3

19/01/2011

3

System Block Diagram

2

12/11/2009

2 K6_MLB

PCB Rule Definitions

CONSTRAINTS

04/06/2011

74

109

Project Specific Constraints

CONSTRAINTS

04/06/2011

73

108

SMC Constraints

CONSTRAINTS

04/06/2011

72

106

T29 Constraints

CONSTRAINTS

04/06/2011

71

105

Ethernet/FW Constraints

CONSTRAINTS

04/06/2011

70

104

PCH Constraints 2

CONSTRAINTS

04/06/2011

69

103

PCH Constraints 1

CONSTRAINTS

04/06/2011

68

102

Memory Constraints

CONSTRAINTS

04/06/2011

67

101

CPU Constraints

CONSTRAINTS

04/06/2011

66

100

LCD Backlight Driver

K21_MLB

12/13/2010

65

97

DisplayPort/T29 A Connector

K21_MLB

12/13/2010

64

94

DisplayPort/T29 A MUXing

K21_MLB

12/13/2010

63

93

Internal DisplayPort Connector

K21_MLB

12/13/2010

62

90

Power Control 1/ENABLE

K21_MLB

12/13/2010

61

79

Power FETs

K21_MLB

12/13/2010

60

78

Misc Power Supplies

K21_MLB

12/13/2010

59

77

CPU VCCIO (1.05V) Power Supply

K21_MLB

12/13/2010

58

76

CPU IMVP7 & AXG VCore Output

K21_MLB

12/13/2010

57

75

CPU IMVP7 & AXG VCore Regulator

K21_MLB

12/13/2010

56

74

1.5V DDR3 Supply

K21_MLB

12/13/2010

55

73

5V / 3.3V Power Supply

K21_MLB

11/30/2010

54

72

System Agent Supply

K21_MLB

12/13/2010

53

71

PBus Supply & Battery Charger

K21_MLB

11/30/2010

52

70

DC-In & Battery Connectors

K21_MLB

11/11/2010

51

69

AUDI0: SPEAKER AMP

K21_MLB

12/13/2010

50

62

SPI ROM

K21_MLB

12/13/2010

49

61

IPD / KBD Backlight

K21_MLB

12/13/2010

48

57

Fan

K21_MLB

12/13/2010

47

56

Table of Contents

1

MASTER

1 MASTER

Thermal Sensors

K21_MLB

12/13/2010

46

55

SCHEM,MLB,K78

051-8871

1

SCH

CRITICAL

PCBF,MLB,K78

820-3024

1

PCB

CRITICAL

LAST_MODIFIED=Fri Apr 8 10:21:51 2011

ABBREV=DRAWING

TITLE=MLB

Page

Contents

(.csa)

Date

Sync

Contents

Date

Page

(.csa)

Sync

SCHEM,MLB,K78

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

DISPLAY

CONN

PG 16

INTEL PCH

JTAG

U6620

PG 10

PG 29,30

SANDYBRIDGE SFF

DMI

PG 19

USB

J4700

PG 11

LINE IN

PG 8

FILTER

AMP

FILTER

HEADPHONE

LINE INSPEAKER

SPEAKER

LEFT

USB

XDP CONN

PCIE

0

DDR3-1066/1333MHZ

SERIAL

SMB_B/0

ADC

FAN0

PG 52

J5100

JTAG

J2500

XDP CONN

RIGHT

64-Bit

PG 16

MISC

CTRL

DP OUT

3

PG 23

DMI

PM_SLP S3/S4

PORT

MEMORY

U3100,3230

SPI

PG 9

64-Bit

BOOTROM

J5700

EXT

USBUSB

CAM

10

PG 24

HUB-2

USB

U2650

5 1

U1800

U2600

USB

PG 24

PWR

B

A

U1000

PG 9

MEMORY

LID

J6903

RIGHT

SMB_A

U4900

MEMORY

U6100

PG 15

GPIO

PG 11

J4610

PCH

PG 23

J4001

T29

1

U9390

DISPLAY PORT+

MUX

J9400

DP

U3600

T29 ROUTER

PG 9

LVDS OUT

PG 16

I2C

SPK

J6702

PG 9

CONN

PG 10

U6201

J6700

JACK

HEADPHONE/

HDA

J4702

CONN

4

FDI

PG 9

FDI

PG 10

CPU

1.6 GHZ

PG 17

SMB

PG 16

CLOCK

PCI

PG 18PG 16

PG16

PG 17PG 17

PG 18

13

EDP OUT

TMDS OUT

RGB OUT

PG 27,38

PG 25

9

HDA

67 2

PG 52-60

POWER CIRCUITRY

TEMP SENSOR

1G/2GB

SATA

RTC

BUFFER

PG 17

12

8

DVI OUT

U2700

J4501

J9000

PCIE

1G/2GB

U2900,U3030

EDP

LPC

INTERNAL

SPEAKER

EFFECT

PG 51

HALL

J6955

SMC

SMB_BSA

DDR3-1066/1333MHZ

CONN

WIRELESS

X21

11

PG 36

HDMI OUT

COUGAR POINT

0

HUB-1

J4600

EXT USB

CONN

PG 37

PG 38

PG 39

PG 40

PG 42

VOLTAGE/CURRENT SENSOR

PG 45

FAN CONN

PG 46

U7000

CHARGER

J5600

CONN

PG 47

CONN

LPC+SPI

PG 48

IPD FLEX

U6210

SPEAKER

AMP

PG 49

CONN

PG 50

EXT USB

LEFT

J4610

PG 51

SYSTEM

CLOCK

SSD

CONN

PCIE

PG 34,35

PG 62

CONN

PG 63

PG 64

PG 5

LIO BOARD

PG 6

LEFT I/O CONN

PG 16

AUDIO CODEC

CAMERA+ALS

PG 7

INTEL CPU

SYNC_DATE=12/11/2009

System Block Diagram

SYNC_MASTER=K6_MLB

2 OF 109

2.5.0

051-8871

2 OF 74

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

K78/K21 POWER SYSTEM ARCHITECTURE

PPVIN_S5_P5VP3V3

EN2

TPS51980

PP3V3_SUS_FET

PPDCIN_G3H_OR_PBUS

AC

2S3P

(6 TO 8.4V)

PPVBATT_G3H_CONN

14-1

P5VS3_PGOOD

P5V_3V3_SUS_EN

P3V3S3_EN

PG 17

P5VS3_EN

P3V3S3_EN

DDRREG_EN

DELAY

RC

SLP_S4#(H4)

(PAGE 17~21)

P5VS0_EN

P3V3S5_PGOOD

P1V8S0_PGOOD

CPUIMVP_AXG_PGOOD

CPUVCCIOS0_PGOOD

PVCCSA_PGOOD

ALL_SYS_PWRGD

10-3

8

14

P5VS3_PGOOD

PP1V05_S0_LDO.

PP1V5S0_EN

EN

TPS72015

U7780

(PAGE 60)

Q7840

VIN

2

R5400

PP5V_S0_CPUVCCIOS0.

1.05V

22

25-1

(PAGE 59)

P3V3S5_PGOOD

VIN

PPVCCSA_S0_REG

23

PPVTT_S0_DDR_LDO

VOUT1

27

DDRREG_PGOOD

U7801

16

VOUT

9

14-1

Q9706

13-1

P3V3S5_EN

U7201

(PAGE 55)

PP5V_S3_REG

PP5V_SUS_FET

Q7810

U7740

CPU_VCCSA_VID<1>

23-1

V

U7100

PVCCSA_PGOOD

PP3V3_S5

PP3V3_S5_REG

S3

PP5V_S0_FET

10-4

PP1V05_S0_VMON

A

SMC_BATT_ISENSE

PPVBAT_G3H

15

CPUVCCIOS0_EN

ISL6259HRTZ

T29BST_EN_UVLO

EN/UVLO

DELAY

RC

CPUVCCIOS0_EN

21

P3V3S0_EN

14-1

PPBUS_SW_LCDBKLT_PWR

Q3880

PBUSVSENS_EN

(PAGE 36)

(PAGE 60)

PM_SLP_S3_L

RC

14

14-1

BKLT_PLT_RST_L

7

13

P5VS3_EN

PG62

13-2

LCD_BKLT_EN

P5V_3V3_SUS_EN

PG62

15

VIN

PG 17

VOUT2

P5V_3V3_SUS_EN

Q7820

(PAGE 66)

U9701

F7040

24

DELAY

R7978

SMC_RESET_L

F6905 6A FUSE

SMC_CPU_VSENSE

22-1

V

U7960

ISL88042IRTEZ

V3MON

V2MON

R7962

VDD

4

6

V4MON

(PAGE 62)

PP1V5_S3RS0_VMON

PP5V_S0_VMON

PPVCORE_S0_CPU_REG

25

U1800

RESET*

S5_PWRGD

SLP_S5_L(P95)

SMC

25

15

P17(BTN_OUT)

A

26

12

PLT_RERST_L

PM_DSW_PWRGD

CPUIMVP_VR_ON

Q7860

SLP_S3#(F4)

1V05_S0_LDO_EN

P1V8S0_EN

P1V5S0_EN

PVCCSA_EN

U3890

LT3957

T29_A_HV_EN

PP15V_T29_REG

LP8550

VIN

5V

(R/H)

VOUT1

VOUT

SLP_SUS#

(L/H)

29

PM_RSMRST_L

PM_PWRBTN_L

PM_MEM_PWRGD

CPU_PWRGD

30

10

P15

(PAGE 17~21)

RSMRST#

SYS_RERST#

COUGAR-POINT

PWRBTN#

SYSRST(PA2)

PROCPWRGD

RES*

PLTRST#

DRAMPWROK

SM_DRAMPWROK

UNCOREPWRGOOD

4

PP1V05_T29_FET

T29_PWR_EN

SMC POWER

SN0903048

R5330

R5320

ENABLE

PP3V42_G3H_REG

PGOOD

3.425V G3HOT

VOUT

VCC

U7400

U7600

EN

21

D6905

R6920

(PCH)

26-1

RSMRST_IN(P13)

PWRGD(P12)

(PAGE 41)

SLP_S3_L(P93)

SLP_S4_L(P94)

9

PM_SLP_S5_L

PGOOD

VIN

(PAGE 56)

EN

VCC

PVCCSA_EN

Q7830

PGOOD

PPVIN_G3H_P3V42G3H

VOUT

PBUS SUPPLY/

R6905

J6900

EN1

Q7055

7

11

PG 17

PG61

EN

VOUT

VIN

F9700

&&

PG62

13

PG62

PBUSVSENS_EN

PM_SLP_S4_L

SMC

U4900

6

U7940

RC

DELAY

PM_SLP_SUS_L

(PAGE 41)

P60

(PCH)

COUGAR-POINT

U1800

PM_SLP_S3_R_L

P5VS0_EN

22

21

19

17

DELAY

RC

DELAY

RC

DELAY

SMC_RESET_L

PP3V3_S0_VMON

Q5300

PP3V3_S3_FET

18

U7770

TPS720105

EN

ISL8014A

TPS22924

U7720

PP3V3_S0

P1V8_S0_EN

17

U3810

14

P3V3S0_EN

T29_PWR_EN

19

(PAGE 36)

PM_SYSRST_L

PM_DSW_PWRGD

28

CHGR_BGATE

SMC_DCIN_ISENSE

VIN

4

U7000

1

PPVBAT_G3H_CHGR_R

(PAGE 53)

DCIN(14.5V)

ADAPTER

IN

J6950

BATTERY CHARGER

R7020

R7050

1

3

LT3470A

U6990

U5010

(PAGE 42)

CPU

5

IMVP_VR_ON(P16)

RSMRST_OUT(P15)

CPUIMVP_VR_ON

PM_SYSRST_L

4

PM_PWRBTN_L

PWR_BUTTON(P90)

SMC_ONOFF_L

99ms DLY

PM_RSMRST_L

6-1

PM_SLP_S4_L

PM_SLP_S3_L

PM_SLP_S5_L

SMC_PM_G2_EN

P3V3S5_EN

3.3V

PPVOUT_SW_LCDBKLT

SMC_PBUS_VSENSE

EN

TPS720105

(PAGE 60)

PP1V05_SUS_LDO

VOUT

ISL95870

(PAGE 52)

(PAGE 9~15)

VR_ON

10-1

SLP_S5#(E4)

16-1

VOUT2

SMC_RESET_L

22

10-2

16

PP3V3_T29_FET

EN

PP1V5_S0_REG

PP1V5_S3RS0_FET

U2850

U1000

PM_PCH_PWRGD

R7140

P1V5CPU_EN

PGOOD

ISL95870A

(PAGE 54)

PGOOD

VID1

MAX15092GTL

CPU VCORE

VLDOIN

PGOODG

CPUIMVP_AXG_PGOOD

1.5V

0.75V

TPS51916

U7300

CPUIMVP_PGOOD

SMC_GFX_VSENSE

PPVCORE_S0_AXG_REG

26

R7350

A

(PAGE 60)

1V05_S0_LDO_EN

PP1V8_S0_REG

A

CPUVCCIOS0_PGOOD

(PAGE 57)

S5

PP5V_S0_VCCSA

DPWROK

TPS22924

U3816/U3815

(PAGE 36)

EN

R7640

SMC_CPU_FSB_ISENSE

PPCPUVCCIO_S0_REG

PPDDR_S3_REG

DDRVTT_EN

DDRREG_EN

PPBUS_G3H

A

U4900

P1V8S0_PGOOD

Power Block Diagram

SYNC_DATE=19/01/2011

3 OF 109

2.5.0

051-8871

3 OF 74

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

Bar Code Labels / EEEE #’s

BOM Variants

Sub-BOMs

LABEL,LIO,K99

825-7563 CRITICAL

1

EEEE:DK9L

[EEEE_DK9L]

LABEL,LIO,K99

825-7563 CRITICAL

1

[EEEE_DLCL]

EEEE:DLCL

LABEL,LIO,K99

825-7563

[EEEE_DLCQ]

CRITICAL

1

EEEE:DLCQ

LABEL,LIO,K99

825-7563

1

CRITICAL

[EEEE_DLCR]

EEEE:DLCR

LABEL,LIO,K99

825-7563

1

CRITICAL

[EEEE_DLCT]

EEEE:DLCT

SYNC_MASTER=K21_MLB

SYNC_DATE=11/16/2010

K78 BOM Variants

LABEL,LIO,K99

825-7563 CRITICAL

1

[EEEE_DLCM]

EEEE:DLCM

LABEL,LIO,K99

825-7563

1

CRITICAL

[EEEE_DLCN]

EEEE:DLCN

LABEL,LIO,K99

825-7563 CRITICAL

1

[EEEE_DLCP]

EEEE:DLCP

639-1808

PCBA,MLB,K78

K78_CMNPTS,CPU:1.6GHZ,EEEE:DK9L,DDR3:HYNIX_2GB

639-1990

PCBA,MLB,1.6GHZ,SA 2GB,K78

K78_CMNPTS,CPU:1.6GHZ,EEEE:DLCT,DDR3:SAMSUNG_2GB

639-1987

PCBA,MLB,1.6GHZ,MI 2GB,K78

K78_CMNPTS,CPU:1.6GHZ,EEEE:DLCP,DDR3:MICRON_2GB

639-1999

PCBA,MLB,1.6GHZ,SA 4GB,K78

K78_CMNPTS,CPU:1.6GHZ,EEEE:DLD6,DDR3:SAMSUNG_4GB

639-1995

PCBA,MLB,1.6GHZ,EL 4GB,K78

K78_CMNPTS,CPU:1.6GHZ,EEEE:DLD1,DDR3:ELPIDA_4GB

639-1998

PCBA,MLB,1.5GHZ,HY 2GB,K78

K78_CMNPTS,CPU:1.5GHZ,EEEE:DLD4,DDR3:HYNIX_2GB

PCBA,MLB,1.5GHZ,HY 4GB,K78

639-1991

K78_CMNPTS,CPU:1.5GHZ,EEEE:DLCV,DDR3:HYNIX_4GB

639-1986

PCBA,MLB,1.5GHZ,SA 2GB,K78

K78_CMNPTS,CPU:1.5GHZ,EEEE:DLCN,DDR3:SAMSUNG_2GB

639-1985

PCBA,MLB,1.5GHZ,SA 4GB,K78

K78_CMNPTS,CPU:1.5GHZ,EEEE:DLCM,DDR3:SAMSUNG_4GB

PCBA,MLB,1.5GHZ,MI 2GB,K78

639-1992

K78_CMNPTS,CPU:1.5GHZ,EEEE:DLCW,DDR3:MICRON_2GB

639-1993

PCBA,MLB,1.5GHZ,EL 4GB,K78

K78_CMNPTS,CPU:1.5GHZ,EEEE:DLCY,DDR3:ELPIDA_4GB

PCBA,MLB,1.4GHZ,HY 2GB,K78

639-1994

K78_CMNPTS,CPU:1.4GHZ,EEEE:DLD0,DDR3:HYNIX_2GB

PCBA,MLB,1.4GHZ,HY 4GB,K78

639-1988

K78_CMNPTS,CPU:1.4GHZ,EEEE:DLCQ,DDR3:HYNIX_4GB

639-1997

PCBA,MLB,1.4GHZ,SA 2GB,K78

K78_CMNPTS,CPU:1.4GHZ,EEEE:DLD3,DDR3:SAMSUNG_2GB

639-1984

PCBA,MLB,1.4GHZ,SA 4GB,K78

K78_CMNPTS,CPU:1.4GHZ,EEEE:DLCL,DDR3:SAMSUNG_4GB

607-8084

K78_COMMON

CMN PTS,PCBA,MLB,K78

639-2000

PCBA,MLB,1.4GHZ,MI 2GB,K78

K78_CMNPTS,CPU:1.4GHZ,EEEE:DLD5,DDR3:MICRON_2GB

LABEL,LIO,K99

825-7563

1

CRITICAL

[EEEE_DLCV]

EEEE:DLCV

LABEL,LIO,K99

825-7563

1

CRITICAL

[EEEE_DLD0]

EEEE:DLD0

LABEL,LIO,K99

825-7563

1

CRITICAL

[EEEE_DLD2]

EEEE:DLD2

LABEL,LIO,K99

825-7563

1

CRITICAL

[EEEE_DLD4]

EEEE:DLD4

LABEL,LIO,K99

825-7563

1

CRITICAL

[EEEE_DLD6]

EEEE:DLD6

LABEL,LIO,K99

825-7563

1

CRITICAL

[EEEE_DLD5]

EEEE:DLD5

LABEL,LIO,K99

825-7563

1

CRITICAL

[EEEE_DLD3]

EEEE:DLD3

LABEL,LIO,K99

825-7563

1

CRITICAL

[EEEE_DLD1]

EEEE:DLD1

LABEL,LIO,K99

825-7563

1

CRITICAL

[EEEE_DLCY]

EEEE:DLCY

LABEL,LIO,K99

825-7563

1

CRITICAL

[EEEE_DLCW]

EEEE:DLCW

639-1989

PCBA,MLB,1.6GHZ,HY 4GB,K78

K78_CMNPTS,CPU:1.6GHZ,EEEE:DLCR,DDR3:HYNIX_4GB

DEVEL_BOM

K78 MLB DEVELOPMENT BOM

1

DEVEL

CRITICAL085-2714

K78_CMNPTS

CMN PTS,PCBA,MLB,K78

CRITICAL

1

607-8084

CMNPTS

639-1996

PCBA,MLB,1.4GHZ,EL 4GB,K78

K78_CMNPTS,CPU:1.4GHZ,EEEE:DLD2,DDR3:ELPIDA_4GB

085-2714

K78 MLB DEVELOPMENT BOM

K78_DEVEL:ENG

4 OF 109

2.5.0

051-8871

4 OF 74

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_ALT_ITEM

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

TABLE_ALT_ITEM

Programmable Parts

K78 BOM GROUPS

Module Parts

DRAM CFG CHART

MICRON

ELPIDA

SAMSUNG

VENDOR

2GB

SIZE

HYNIX

4GB

0

1

CFG 2

1

0

CFG 1

1

0

CFG 0

B

A

1

DIE REV

0

CFG 3

1

0

Alternate Parts

FDMS0349 alt to RJK0305DPB

376S0617

ALL

376S1018

376S0972 376S0612

ALL

Rohm alt to Toshiba

Murata alt to Samsung

138S0691

ALL

138S0676

Panasonic alt to Cyntec

104S0011

ALL

104S0035

152S1295

ALL

152S1462

Toko alt to NEC inductor

128S0333

ALL

128S0294

Sanyo alt to Sanyo/Frederick

337S4093

EARLY 1.4GHZ CPU SAMPLES

ALL

337S4101

IC,T29-MCU,K78

T29MCU:PROG

1

U9330

CRITICAL341T0355

U3690

335S0550

T29ROM:BLANK

1

CRITICAL

EEPROM,32KBIT,2X3QFN

377S0107

ONsemi alt to Semtech

377S0066

ALL

138S0671

Taiyo alt to Murata

138S0673

ALL

BOOTROM_PROG,SMC_PROG,T29ROM:PROG,T29MCU:PROG

K78_PROGPARTS

K78_DEVEL:ENG

BKLT:ENG,BMON:ENG,XDP_CONN,XDP_CPU:BPM,XDP_PCH,LPCPLUS,VREFMRGN,S0PGOOD_ISL,S3_S0_LED,VCCIOISNS_ENG,AIRPORTISNS_ENG,HDDISNS_ENG,LCDBKLTISNS_ENG

LPCPLUS,XDP_CONN,XDP_PCH

K78_DEVEL:PVT

DEVEL_BOM,SMC_DEBUG_YES,XDP

K78_DEBUG:ENG

K78_DEBUG:PVT

DEVEL_BOM,BKLT:PROD,BMON:PROD,SMC_DEBUG_YES,XDP,VREFMRGN_NOT

K78_DEBUG:PROD

BKLT:PROD,BMON:PROD,SMC_DEBUG_YES,XDP,VREFMRGN_NOT,LPCPLUS,VCCIOISNS_PROD,AIRPORTISNS_PROD,HDDISNS_PROD,LCDBKLTISNS_PROD

DDR3:HYNIX_2GB

DRAM_CFG0:L,DRAM_CFG1:L,DRAM_CFG2:L,DRAM_CFG3:L,DRAM_TYPE:HYNIX_2GB

DRAM_CFG0:L,DRAM_CFG1:H,DRAM_CFG2:L,DRAM_CFG3:L,DRAM_TYPE:SAMSUNG_2GB

DDR3:SAMSUNG_2GB

DRAM_CFG0:H,DRAM_CFG1:H,DRAM_CFG2:H,DRAM_CFG3:L,DRAM_TYPE:ELPIDA_4GB

DDR3:ELPIDA_4GB

DRAM_CFG0:L,DRAM_CFG1:H,DRAM_CFG2:H,DRAM_CFG3:L,DRAM_TYPE:SAMSUNG_4GB

DDR3:SAMSUNG_4GB

K78_MISC

PCH:B3,CPUMEM_S0,HUB1_2NONREM,HUB2_2NONREM,T29:YES,SDRVI2C:MCU,SDRV_PD,KB_BL

U1000 CPU:1.3GHZ

SNB,QALV,QS,J1,1.3,17W,2+2,1.05,3M,BGA

337S4098 CRITICAL

1

ALTERNATE,COMMON,K78_MISC,K78_DEBUG:ENG,K78_PROGPARTS,USBHUB_2513B,T29BST:Y,EDP

K78_COMMON

SNB,QAM1,QS,J1,1.6,17W,2+2,1.1,4M,BGA

337S4101

1

U1000

CRITICAL

CPU:1.6GHZ

COUGAR POINT,B3,SLJ4K,PRQ,BD82QS67

U1800

PCH:B3

337S4091

1

CRITICAL

IC,SDRAM,1GBIT,DDR3-1333,78P FBGA,T-DIE,HYNIX

U2900,U2910,U2920,U2930

CRITICAL

4

DRAM_TYPE:HYNIX_2GB

333S0585

DRAM_TYPE:HYNIX_2GB

333S0585

U3000,U3010,U3020,U3030

CRITICAL

4

IC,SDRAM,1GBIT,DDR3-1333,78P FBGA,T-DIE,HYNIX

IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,B-DIE,HYNIX

CRITICAL

U2900,U2910,U2920,U2930

333S0586

DRAM_TYPE:HYNIX_4GB

4

IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,B-DIE,HYNIX

U3200,U3210,U3220,U3230

4

333S0586

DRAM_TYPE:HYNIX_4GB

CRITICAL

4

333S0590

IC,SDRAM,1GBIT,DDR3-1333,78P FBGA,V68A-D,MICRON

DRAM_TYPE:MICRON_2GB

U2900,U2910,U2920,U2930

U3000,U3010,U3020,U3030

CRITICAL

4

333S0590

IC,SDRAM,1GBIT,DDR3-1333,78P FBGA,V68A-D,MICRON

DRAM_TYPE:MICRON_2GB

CRITICAL

U3200,U3210,U3220,U3230

4

333S0590

IC,SDRAM,1GBIT,DDR3-1333,78P FBGA,V68A-D,MICRON

DRAM_TYPE:MICRON_2GB

U3100,U3110,U3120,U3130

CRITICAL

4

333S0590

IC,SDRAM,1GBIT,DDR3-1333,78P FGBA,V68A-D,MICRON

DRAM_TYPE:MICRON_2GB

4

333S0589

DRAM_TYPE:ELPIDA_4GB

CRITICAL

U2900,U2910,U2920,U2930

IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,C-DIE,ELPIDA

4

333S0589

DRAM_TYPE:ELPIDA_4GB

U3200,U3210,U3220,U3230

CRITICAL

IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,C-DIE,ELPIDA

4

333S0589

DRAM_TYPE:ELPIDA_4GB

CRITICAL

U3100,U3110,U3120,U3130

IC,SDRAM,2GBIT,DDR3-1333,78P FGBA,C-DIE,ELPIDA

4

333S0589

DRAM_TYPE:ELPIDA_4GB

CRITICAL

U3000,U3010,U3020,U3030

IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,C-DIE,ELPIDA

ASSEMBLY,SUBASSY,PCBA,HALL EFFECT,K99

1

607-6811

CRITICAL

J6955

IC,ISL6259,BATCHARGER,3%,4C4MM,QFN28

1

353S2929

CRITICAL

U7000

DRAM_CFG0:L,DRAM_CFG1:L,DRAM_CFG2:H,DRAM_CFG3:L,DRAM_TYPE:HYNIX_4GB

DDR3:HYNIX_4GB

DRAM_CFG0:H,DRAM_CFG1:L,DRAM_CFG2:L,DRAM_CFG3:L,DRAM_TYPE:MICRON_2GB

DDR3:MICRON_2GB

IC,T29, FCBGA,PRQ 8x9MM

338S0976

1

U3600

T29:YES

CRITICAL

COUGAR POINT,SLHAG,PRQ,BD82QS67

PCH:B2

U1800

CRITICAL

1

337S4080

IC,SDRAM,1GBIT,DDR3-1333,78P FGBA,T-DIE,HYNIX

U3100,U3110,U3120,U3130

CRITICAL

333S0585

4

DRAM_TYPE:HYNIX_2GB

CRITICAL

4

333S0588

IC,SDRAM,2GBIT,DDR3-1333,78P FGBA,D-DIE,SAMSUNG

DRAM_TYPE:SAMSUNG_4GB

U3100,U3110,U3120,U3130

CRITICAL

4

333S0588

IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,D-DIE,SAMSUNG

DRAM_TYPE:SAMSUNG_4GB

U3200,U3210,U3220,U3230

CRITICAL

4

333S0588

IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,D-DIE,SAMSUNG

DRAM_TYPE:SAMSUNG_4GB

U3000,U3010,U3020,U3030

CRITICAL

U2900,U2910,U2920,U2930

4

333S0588

IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,D-DIE,SAMSUNG

DRAM_TYPE:SAMSUNG_4GB

4

CRITICAL

333S0587

IC,SDRAM,1GBIT,DDR3-1333,78P FBGA,G-DIE,SAMSUNG

DRAM_TYPE:SAMSUNG_2GB

U3200,U3210,U3220,U3230

IC,SDRAM,1GBIT,DDR3-1333,78P FGBA,G-DIE,SAMSUNG

CRITICAL

U3100,U3110,U3120,U3130

4

333S0587

DRAM_TYPE:SAMSUNG_2GB

U3000,U3010,U3020,U3030

IC,SDRAM,1GBIT,DDR3-1333,78P FBGA,G-DIE,SAMSUNG

4

333S0587

CRITICAL

DRAM_TYPE:SAMSUNG_2GB

4

IC,SDRAM,1GBIT,DDR3-1333,78P FBGA,G-DIE,SAMSUNG

U2900,U2910,U2920,U2930

333S0587

CRITICAL

DRAM_TYPE:SAMSUNG_2GB

U3100,U3110,U3120,U3130

IC,SDRAM,2GBIT,DDR3-1333,78P FGBA,B-DIE,HYNIX

CRITICAL

4

333S0586

DRAM_TYPE:HYNIX_4GB

U3000,U3010,U3020,U3030

CRITICAL

4

333S0586

DRAM_TYPE:HYNIX_4GB

IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,B-DIE,HYNIX

333S0585

CRITICAL

U3200,U3210,U3220,U3230

4

IC,SDRAM,1GBIT,DDR3-1333,78P FBGA,T-DIE,HYNIX

DRAM_TYPE:HYNIX_2GB

SNB,QAM3,QS,J1,1.4,17W,2+2,1.05,3M,BGA

337S4099

CPU:1.4GHZ

1

CRITICAL

U1000

SNB,QAM2,QS,J1,1.5,17W,2+2,1.1,4M,BGA

337S4100

1

U1000

CRITICAL

CPU:1.5GHZ

341T0354

1

T29ROM:PROG

U3690

IC,T29-ROM,K78

CRITICAL

337S3997

1

U9330

IC,MCU,32B,LPC1112A,16KB/2KB,HVQFN25

T29MCU:BLANK

CRITICAL

338S0895

U4900

1

IC,SMC,RENESAS,H8S/2117RP,9MM,TLP,HF

CRITICAL

SMC_BLANK

341T0349 CRITICAL

U6100

1

BOOTROM_PROG

IC,EFI ROM,K21 K78

U6100

CRITICAL335S0809

1

BOOTROM_BLANK

64 MBIT SPI SERIAL DUAL I/O FLASH,8X6X0.8

Diodes alt to Toshiba

ALL

376S0859376S0977

376S0855 376S0613

ALL

Diodes alt to Toshiba

341T0350

1

IC,SMC,K78

CRITICAL

U4900

SMC_PROG

U6100

CRITICAL335S0803

1

BOOTROM_BLANK

64 MBIT SPI SERIAL DUAL I/O FLASH,8X6X0.8

ALL

371S0652

NXP alt to NXP

371S0679

138S0679 138S0678

ALL

Murata/Samsung alt to Taiyo

ALL

NXP ALT TO PERICOM

353S3055353S3312

152S1085

Toko alt to Cyntec

152S1307

ALL

337S4100337S4092

EARLY 1.5GHZ CPU SAMPLES

ALL

FDMC0202S alt to RJK03E0DNS

376S0895376S0874

SYNC_DATE=11/16/2010

BOM Configuration

SYNC_MASTER=K21_MLB

ALL

376S0826 376S0917

RJK0332DPB alt to FDMS0355

ALL

514-0744 998-3941

mDP connector alt

5 OF 109

2.5.0

051-8871

5 OF 74

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

J9000: Internal DP Connector

(Need to add 27 GND TPs)

J5100: LPC+SPI Connector

J6955: HALL EFFECT Connector

FUNC_TEST

J5715: KB BKLT Connector

FUNC_TEST

(Need to add 2 GND TPs)

FUNC_TEST

Misc Voltages & Control Signals

(Need to add 5 GND TPs)

(Need 3 TPs)

(Need 4 TPs)

(Need to add 3 GND TPs)

(Need to add 5 GND TPs)

(Need 5 TPs)

(Need 6 TPs)

(Need to add 8 GND TPs)

FUNC_TEST

J4001: AirPort / BT Connector

FUNC_TEST

J4700: LIO Connector

J6903: Speaker Connector

J5700: IPD Flex Connector

FUNC_TEST

(Need to add 5 GND TPs)

(Need to add 6 GND TPs)

(Need to add 5 GND TPs)

(Need to add 6 GND TPs)

FUNC_TEST

J5600: Fan Connector

FUNC_TEST

(Need to add 1 GND TP)

FUNC_TEST

(Need 2 TPs) (Need 2 TPs)

FUNC_TEST

Functional Test Points

NO_TEST

NO_TEST Nets

(Need 4 TPs)

FUNC_TEST

J6900: DC-In Connector

J4501: SATA SSD Connector

J6950 and 1 for shield)

(Need to add 4 GND TPs near

J6950: Battery Connector

FUNC_TEST

I499

I500

I501

I502

I503

I504

I505

I506

I566

I567

I568

I569

I570

I571

SYNC_DATE=(02/16/2010)

SYNC_MASTER=(K99_MLB)

Functional Test / No Test

TP_CLINK_RESET_L

TP_CLINK_DATA

TRUE

I2C_TCON_SDA_R

TRUE

PP3V3_SW_LCD

TRUE

SMC_BC_ACOK

TRUE

SYS_ONEWIRE

=PP3V3R1V5_S0_AUDIO

TRUE

PP0V75_S0_DDRVTT

TRUE

PP15V_T29

TRUE

PP3V3_T29

TRUE

PP1V05_T29

PP1V05_S0

TRUE

PP1V05_S0_PCH_VCCADPLL

TRUE

PPVCORE_S0_CPU

TRUE

PPVCORE_S0_AXG

TRUE

PP1V5_S3_CPU_VCCDQ

TRUE

PP1V05_S0_CPU_VCCPQE

TRUE

PP1V8_S0_CPU_VCCPLL_R

TRUE

PP1V05_SUS

TRUE

PPVCCSA_S0_CPU

TRUE

PPVTTDDR_S3

PP1V5_S0

TRUE

PP1V5_S3RS0

TRUE

=PP3V42_G3H_HALL

TRUE

SMC_LID_R

TRUE

KBDLED_ANODE

TRUE

KBDLED_FB

TRUE

PPBUS_G3H

TRUE

PPVIN_SW_T29BST

TRUE

PP3V42_G3H

TRUE

PPVRTC_G3H

TRUE

PP5V_SUS

TRUE

PP3V3_SUS

TRUE

PP3V3_S3

TRUE

PP3V3_S0

TRUE

PP1V5_S3

TRUE

PPBUS_S5_HS_COMPUTING_ISNS

WIFI_EVENT_L

TRUE

PCIE_AP_R2D_P

TRUE

PCIE_AP_R2D_N

TRUE

LED_RETURN_1

TRUE

I2C_TCON_SCL_R

=PP3V3_S3_BT

TRUE

=PP3V3_S0_AUDIO

TRUE

HDA_SYNC

TRUE

HDA_RST_L

SPKRAMP_R_P_OUT

TRUE

SPKRAMP_R_N_OUT

TRUE

=PP5V_S0_FAN

TRUE

PP5V_TPAD_FILT

TRUE

SMC_PME_S4_WAKE_L

TRUE

FAN_RT_PWM

TRUE

=PP3V42_G3H_TPAD

TRUE

AP_CLKREQ_Q_L

TRUE

PP3V3_S0_HDD_R

TRUE

SATA_HDD_D2R_C_P

TRUE

SATA_HDD_D2R_C_N

TRUE

SMC_HDD_TEMP_CTL_CONN

TRUE

SATA_HDD_R2D_P

TRUE

SATA_HDD_R2D_N

TRUE

MAKE_BASE=TRUE

NC_PCI_CLK33M_OUT3

TRUE MAKE_BASE=TRUE

NC_PCIE_CLK100M_PEBP

TRUE MAKE_BASE=TRUE

NC_PCIE_CLK100M_PEBN

MAKE_BASE=TRUE

TRUE

NC_CLINK_DATA

TRUE MAKE_BASE=TRUE

NC_PCI_PME_L

MAKE_BASE=TRUE

TRUE

NC_CLINK_CLK

NC_CLINK_RESET_L

TRUE

MAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE

NC_HDA_SDIN2

MAKE_BASE=TRUE

TRUE

NC_HDA_SDIN3

TRUE MAKE_BASE=TRUE

NC_HDA_SDIN1

NC_PCH_LVDS_VBG

MAKE_BASE=TRUE

TRUE

NC_LVDS_IG_CTRL_DATA

MAKE_BASE=TRUE

TRUE

NC_LVDS_IG_CTRL_CLK

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_CRT_IG_VSYNC

TRUE

NC_CRT_IG_DDC_CLK

TRUE MAKE_BASE=TRUE

NC_CRT_IG_DDC_DATA

MAKE_BASE=TRUE

TRUE

NC_CRT_IG_HSYNC

TRUE MAKE_BASE=TRUE

NC_CRT_IG_GREEN

TRUE MAKE_BASE=TRUE

NC_CRT_IG_BLUE

TRUE MAKE_BASE=TRUE

NC_CRT_IG_RED

TRUE MAKE_BASE=TRUE

NC_SDVO_INTN

TRUE MAKE_BASE=TRUE

NC_SDVO_TVCLKINN

MAKE_BASE=TRUE

TRUE

NC_SDVO_TVCLKINP

MAKE_BASE=TRUE

TRUE

NC_SDVO_INTP

TRUE MAKE_BASE=TRUE

NC_SDVO_STALLN

MAKE_BASE=TRUE

TRUE

NC_SDVO_STALLP

TRUE MAKE_BASE=TRUE

NC_TP_XDP_PCH_OBSFN_D<0..1>

TRUE MAKE_BASE=TRUE

NC_TP_XDPPCH_HOOK3

MAKE_BASE=TRUE

TRUE

NC_TP_XDP_PCH_OBSFN_B<0..1>

MAKE_BASE=TRUE

TRUE

NC_TP_XDPPCH_HOOK2

MAKE_BASE=TRUE

TRUE

NC_TP_XDP_PCH_OBSFN_A<0..1>

NC_TP_XDP_PCH_HOOK4

MAKE_BASE=TRUE

TRUE

NC_TP_XDP_PCH_HOOK5

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

NC_PCH_GPIO64_CLKOUTFLEX0

MAKE_BASE=TRUE

TRUE

NC_PCH_GPIO65_CLKOUTFLEX1

TRUE MAKE_BASE=TRUE

NC_PCH_GPIO66_CLKOUTFLEX2

TRUE MAKE_BASE=TRUE

NC_PCH_GPIO67_CLKOUTFLEX3

TRUE

PCH_VSS_NCTF<12>

TRUE

PCH_VSS_NCTF<11>

TRUE

PCH_VSS_NCTF<9>

PCH_VSS_NCTF<2>

TRUE

PCH_VSS_NCTF<5>

TRUE

PCH_VSS_NCTF<1>

TRUE

MAKE_BASE=TRUE

TRUE

NC_SMC_BS_ALRT_L

MAKE_BASE=TRUE

TRUE

NC_LVDS_IG_BKL_PWM

MAKE_BASE=TRUE

TRUE

NC_LVDS_IG_B_CLKP

TRUE

MAKE_BASE=TRUE

NC_LVDS_IG_B_CLKN

PCH_VSS_NCTF<29>

TRUE

PCH_VSS_NCTF<27>

TRUE

PCH_VSS_NCTF<21>

TRUE

PCH_VSS_NCTF<25>

TRUE

PCH_VSS_NCTF<19>

TRUE

PCH_VSS_NCTF<19>

TRUE

PCH_VSS_NCTF<17>

TRUE

NC_PCH_TP1

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_PCH_TP2

NC_PCH_TP3

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

NC_PCH_TP4

TRUE

PCH_VSS_NCTF<15>

MAKE_BASE=TRUE

TRUE

NC_PCH_TP5

MAKE_BASE=TRUE

TRUE

NC_PCH_TP6

TRUE

MAKE_BASE=TRUE

NC_PCH_TP7

MAKE_BASE=TRUE

NC_PCH_TP8

TRUE

NC_PCH_TP9

TRUE

MAKE_BASE=TRUE

NC_PCH_TP10

TRUE

MAKE_BASE=TRUE

NC_PCH_TP12

TRUE

MAKE_BASE=TRUE

NC_PCH_TP13

TRUE

MAKE_BASE=TRUE

TRUE

NC_PCH_TP14

MAKE_BASE=TRUE

NC_PCH_TP15

TRUE

MAKE_BASE=TRUE

NC_PCH_TP16

TRUE

MAKE_BASE=TRUE

NC_PCH_TP18

TRUE

MAKE_BASE=TRUE

NC_PCH_TP17

TRUE

NC_SATA_E_D2RP

TRUE MAKE_BASE=TRUE

NC_SATA_E_R2D_CN

TRUE

MAKE_BASE=TRUE

NC_SATA_E_D2RN

MAKE_BASE=TRUE

TRUE

NC_SATA_F_D2RP

TRUE

MAKE_BASE=TRUE

NC_SATA_E_R2D_CP

TRUE

MAKE_BASE=TRUE

NC_SATA_F_D2RN

MAKE_BASE=TRUE

TRUE

NC_SATA_F_R2D_CN

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_SATA_F_R2D_CP

MAKE_BASE=TRUE

TRUE

NC_SATA_D_D2RP

MAKE_BASE=TRUE

TRUE

NC_SATA_D_D2RN

NC_SATA_D_R2D_CN

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_SATA_D_R2D_CP

TRUE

MAKE_BASE=TRUE

NC_SATA_B_R2D_CP

MAKE_BASE=TRUE

TRUE

NC_SATA_B_D2RP

MAKE_BASE=TRUE

TRUE

NC_SATA_B_D2RN

MAKE_BASE=TRUE

NC_PSOC_P1_3

TRUE

NC_PCIE_CLK100M_PE7P

TRUE MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_SATA_B_R2D_CN

NC_PCIE_CLK100M_PE4P

MAKE_BASE=TRUE

TRUE

NC_PCIE_CLK100M_PE4N

MAKE_BASE=TRUE

TRUE

NC_PCIE_CLK100M_PE5N

MAKE_BASE=TRUE

TRUE

NC_PCIE_CLK100M_PE7N

MAKE_BASE=TRUE

TRUE

NC_PCIE_CLK100M_PE5P

TRUE MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE6P

NC_PCIE_CLK100M_PE6N

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_PEG_D2RN<15..4>

TRUE

MAKE_BASE=TRUE

NC_CPU_RSVD<8..27>

NC_CPU_RSVD<30..45>

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_CPU_THERMDC

TRUE

MAKE_BASE=TRUE

NC_EDP_AUXN

TRUE

MAKE_BASE=TRUE

NC_CPU_THERMDA

TRUE

MAKE_BASE=TRUE

NC_EDP_TXN<0..3>

TRUE

MAKE_BASE=TRUE

NC_EDP_AUXP

TRUE

MAKE_BASE=TRUE

NC_EDP_TXP<0..3>

TRUE

PCIE_WAKE_L

USB_BT_N

TRUE

USB_BT_P

TRUE

FAN_RT_TACH

TRUE

SMC_ONOFF_L

TRUE

=I2C_TPAD_SDA

TRUE

USB_TPAD_CONN_N

USB_TPAD_CONN_P

TRUE

SMC_TPAD_RST_L

TRUE

SMC_LID

TRUE

=PP18V5_DCIN_CONN =PP5V_S3_LIO_CONN

TRUE

=SMBUS_BATT_SCL

TRUE

PP3V3_WLAN_F

PCIE_CLK100M_AP_N

TRUE

PCIE_CLK100M_AP_P

PCIE_AP_D2R_P

TRUE

PCIE_AP_D2R_N

TRUE

AP_RESET_CONN_L

TRUE

=PP3V3_S5_LPCPLUS

TRUE

SPI_ALT_MOSI

TRUE

LPC_FRAME_L

TRUE

SPI_ALT_MISO

TRUE

SMC_TMS

TRUE

PM_CLKRUN_L

TRUE

LPCPLUS_RESET_L

TRUE

SMC_TDO

TRUE

SMC_TRST_L

TRUE

SMC_TX_L

TRUE

SMC_MD1

TRUE

LPC_CLK33M_LPCPLUS

TRUE

SPIROM_USE_MLB

TRUE

SPI_ALT_CLK

TRUE

LPC_SERIRQ

TRUE

SPI_ALT_CS_L

TRUE

LPC_PWRDWN_L

TRUE

SMC_TCK

TRUE

SMC_TDI

TRUE

SMC_RESET_L

TRUE

SMC_RX_L

TRUE

SMC_NMI

TRUE

LPCPLUS_GPIO

TRUE

=PP5V_S0_LPCPLUS

TRUE

LPC_AD<3..0>

AUD_IP_PERIPHERAL_DET

TRUE

AUD_IPHS_SWITCH_EN

TRUE

AUD_I2C_INT_L

TRUE

SPKRAMP_INR_N

AUD_GPIO_3

TRUE

USB_EXTD_N

SPKRAMP_INR_P

TRUE

USB_EXTD_P

TRUE

USB_CAMERA_P

TRUE

USB_CAMERA_N

TRUE

HDA_SDOUT

TRUE

HDA_SDIN0

TRUE

HDA_BIT_CLK

USB_EXTD_OC_L

TRUE

=USB_PWR_EN

TRUE

=I2C_LIO_SDA

TRUE

=I2C_MIKEY_SCL

TRUE

=I2C_LIO_SCL

TRUE

=I2C_MIKEY_SDA

=PP3V42_G3H_ONEWIRE

TRUE

PPDCIN_G3H

TRUE

PP5V_S5

TRUE

LED_RETURN_5

TRUE

LED_RETURN_4

TRUE

LED_RETURN_2

TRUE

LED_RETURN_3

TRUE

DP_INT_HPD_CONN

TRUE

DP_INT_AUX_CH_C_N

TRUE

DP_INT_AUX_CH_C_P

TRUE

DP_INT_ML_F_P<0>

TRUE

DP_INT_ML_F_N<0>

TRUE

DP_INT_ML_F_P<1>

LED_RETURN_6

TRUE

DP_INT_ML_F_N<1>

TRUE

TP_EDP_TX_P<0..3>

TP_EDP_AUX_P

TP_EDP_TX_N<0..3>

TP_CPU_THERMDA

TP_EDP_AUX_N

TP_CPU_THERMDC

TP_CPU_RSVD<30..45>

TP_CPU_RSVD<8..27>

=PEG_R2D_C_P<15..4>

=PEG_D2R_P<15..4>

=PEG_R2D_C_N<15..4>

=PEG_D2R_N<15..4>

TP_PCIE_CLK100M_PE6N

TP_PCIE_CLK100M_PE6P

TP_PCIE_CLK100M_PE5P

TP_PCIE_CLK100M_PE7N

TP_SATA_B_R2D_CN

TP_PCIE_CLK100M_PE7P

TP_PSOC_P1_3

TP_SATA_B_D2RN

TP_SATA_B_D2RP

TP_SATA_B_R2D_CP

TP_SATA_D_R2D_CP

TP_SATA_D_R2D_CN

TP_SATA_D_D2RN

TP_SATA_D_D2RP

TP_SATA_F_R2D_CP

TP_SATA_F_R2D_CN

TP_SATA_F_D2RN

TP_SATA_E_R2D_CP

TP_SATA_F_D2RP

TP_SATA_E_D2RN

TP_SATA_E_R2D_CN

TP_SATA_E_D2RP

TP_PCH_TP17

TP_PCH_TP18

TP_PCH_TP16

TP_PCH_TP15

TP_PCH_TP14

TP_PCH_TP13

TP_PCH_TP12

TP_PCH_TP10

TP_PCH_TP9

TP_PCH_TP8

TP_PCH_TP7

TP_PCH_TP6

TP_PCH_TP5

TP_PCH_TP4

TP_PCH_TP3

TP_PCH_TP2

TP_PCH_TP1

TP_LVDS_IG_B_CLKN

TP_LVDS_IG_B_CLKP

TP_LVDS_IG_BKL_PWM

SMC_BS_ALRT_L

TP_PCH_GPIO65_CLKOUTFLEX1

TP_PCH_GPIO66_CLKOUTFLEX2

TP_PCH_GPIO67_CLKOUTFLEX3

TP_PCH_GPIO64_CLKOUTFLEX0

TP_XDP_PCH_HOOK5

TP_XDP_PCH_HOOK4

TP_XDP_PCH_OBSFN_A<0..1>

TP_XDPPCH_HOOK2

TP_XDP_PCH_OBSFN_B<0..1>

TP_XDPPCH_HOOK3

TP_XDP_PCH_OBSFN_D<0..1>

TP_SDVO_STALLP

TP_SDVO_INTN

TP_SDVO_INTP

TP_SDVO_STALLN

TP_SDVO_TVCLKINN

TP_SDVO_TVCLKINP

TP_CRT_IG_BLUE

TP_CRT_IG_DDC_DATA

TP_LVDS_IG_CTRL_DATA

TP_HDA_SDIN3

TP_PCI_PME_L

TP_CLINK_CLK

TP_PCI_CLK33M_OUT3

TP_PCIE_CLK100M_PEBN

TP_PCIE_CLK100M_PEBP

TP_HDA_SDIN2

TP_HDA_SDIN1

TP_PCH_LVDS_VBG

TP_LVDS_IG_CTRL_CLK

TP_CRT_IG_VSYNC

TP_CRT_IG_DDC_CLK

TP_CRT_IG_RED

TP_CRT_IG_GREEN

TP_CRT_IG_HSYNC

TRUE

=I2C_TPAD_SCL

TRUE

PP3V3_TPAD_CONN

TRUE

MAKE_BASE=TRUE

NC_PEG_R2D_CN<15..4>

TRUE

MAKE_BASE=TRUE

NC_PEG_R2D_CP<15..4>

TP_PCIE_CLK100M_PE5N

TP_PCIE_CLK100M_PE4P

TP_PCIE_CLK100M_PE4N

TRUE

MAKE_BASE=TRUE

NC_PEG_D2RP<15..4>

TRUE

SMC_HDD_OOB_TEMP_CONN

TRUE

PP3V3_S5

TRUE

PP1V8_S0

PPVOUT_SW_LCDBKLT

TRUE

PPVBAT_G3H_CONN

TRUE

SYS_DETECT_L

TRUE

=SMBUS_BATT_SDA

TRUE

7 OF 109

2.5.0

051-8871

6 OF 74

16

62

39 40 41

39 40

7

39

7

35

7

67

7

51

48

7

51

7

35

7

73

7

67

7

36 40

36 69

62 65

62

7

36

7

39

16 39 69

50 51 73

7

47

48

40 41 48

47

7

48

36

37

37 68

37

37 68

69

6

69

6

69

17 36

24 36 68

47

40 41 48

43 48

48 73

41 48

40 41 48 51

7

51

7

51

43 51

36

16 36 69

36

7

42

16 40 42 69

42

40 41 42

17 40 42

25 42

40 41 42

40 42

38 40 41 42

40 42

25 42 69

19 42 49

42

16 40 42

42

17 40 42

40 41 42

40 41 42 52

38 40 41 42

40 42

19 42

7

42

16 40 42 69

18 39

19 39

18 39

39 50 73

39 50

24 39 68

39 50 73

24 39 68

18 39 68

16 39 69

24 39

38 39 61

39 43

7

39

7

62 65

62

62 69

62 65

62 69

9

16

8

16

23

17

16

18

16

18

16

17

43 48

48

16

37

7

73

7

62 65

51 52

51

43 51

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

5V Rails

1.8V/1.5V/1.2V/1.05V Rails

T29 Rails (off when no cable)

"G3Hot" (Always-Present) Rails

2A max supply

3.3V Rails

? mA

Chipset "VCore" Rails

1V05 S0 LDO

SYNC_DATE=05/15/2010

Power Aliases

SYNC_MASTER=K91_MLB

MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM

PP3V3_S3

VOLTAGE=3.3V MAKE_BASE=TRUE

=PP3V3_S3_SMBUS_SMC_MGMT

=PP3V3_S3_USB_HUB

=PP3V3_S3_PCH_GPIO

=PP3V3_S3_1V5S3ISNS =PP3V3_S3_DBGLEDS

=PP3V3_S3_FET

=PP3V3_S3_SMBUS_SMC_A_S3

=PP3V3_S3_VREFMRGN

=PP3V3_S0_CPUVCCIOISNS =PP3V3_S0_AUDIO

=PP3V3_S0_CPUTHMSNS

=PP3V3_S0_DP_DDC =PP3V3_S0_FAN

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.20MM

VOLTAGE=3.3V

PP3V3_S0

MIN_LINE_WIDTH=0.5 MM

=PP5V_S5_LDO

=PP3V3_S0_FET

=PP3V3_S0_BKL_VDDIO

=PP3V3_S0_HS_COMPUTING_ISNS

=PP3V3_S0_P3V3T29FET

=PP3V3_S0_P1V8S0

=PP3V3_S0_PCH =PP3V3_S0_PCH_GPIO =PP3V3_S0_PCH_VCC3_3_CLK =PP1V05_S0_PCH_VCCIO_USB

=PP1V05_S0_PCH_VCC_CORE

=PP1V05_S0_PCH_VCCDIFFCLK =PP1V05_S0_PCH_VCCSSC

VOLTAGE=1.05V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PP1V05_S0

=PP1V05_S0_PCH_VCCIO_PLLPCIE

=PP1V05_S0_CPU_VCCIO

=PP3V3_S3_WLANISNS

=PP3V3_S3_WLAN

=PP3V3_S5_SMC

=PPDCIN_S5_CHGR

=PP3V3_S0_SMBUS_SMC_B_S0 =PP3V3_S0_SMC

=PP3V3_S0_P1V5S0

=PP3V3_S0_PCH_STRAPS

=PP3V3_S0_PCH_VCC3_3_SATA

=PP3V3_S0_PCH_VCC3_3_PCI

=PP3V3_S0_PCH_VCC3_3_HVCMOS

=PP3V3_S0_PCH_VCC3_3_GPIO

=PP3V3_S0_PCH_VCCADAC

=PP1V5_S0_REG

=PP3V3_SUS_PWRCTL

=PP3V3_SUS_GPIO

=PP3V3_SUS_PCH_VCCSUS_USB

=PP3V3_S0_BKLTISNS

=PP3V3_S0_P1V05S0LDO

=PP3V3_S0_T29PWRCTL =PP3V3_S0_DPSDRVA

=PP3V3_S0_VMON

=PP3V3_S0_HDDISNS

=PP3V3_S0_HDD

=PP3V3_S0_SMBUS_SMC_0_S0

=PP3V3_S0_SMBUS_PCH

=PP3V3_S0_SB_PM

=PP3V3_S0_RSTBUF

=PP3V3_S0_PWRCTL

=PP3V3_S0_CPU_VCCIO_SEL

=PP0V75_S0_MEM_VTT_B

MIN_LINE_WIDTH=2 mm

MAKE_BASE=TRUE

PP0V75_S0_DDRVTT

MIN_NECK_WIDTH=0.17 mm VOLTAGE=0.75V

=PPVTT_S0_VTTCLAMP

VOLTAGE=1.05V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

PP1V05_SUS

MIN_LINE_WIDTH=0.4 MM

=PPVTT_S0_DDR_LDO

=PPVTT_S3_DDR_BUF

=PP5V_S5_TPAD

=PPVRTC_G3_OUT

=PP5V_S5_P1V5DDRFET

=PP5V_SUS_PCH

VOLTAGE=3.3V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50MM

PP5V_SUS

=PPVRTC_G3_PCH

=PP3V42_G3H_ONEWIRE

=PP5V_S0_FAN

=PP5V_S0_BKL

=PP5V_S3_REG

=PP1V05_S0_PCH_VCCIO_SATA

=PP3V3_S5_PCH

=PP1V05_S0_PCH_VCCASW

=PPVIN_S0_DDRREG_LDO

=PP1V5_S3_P1V5S3RS0_FET

=PP3V3_S5_SMCBATLOW

=PP3V3_S4_SMC

=PP3V3_S3_P3V3S3FET

=PPVBAT_G3_SYSCLK

=PPVIN_S5_SMCVREF

=PP3V42_G3H_TPAD

=PPVIN_S0_CPUIMVP

=PP18V5_DCIN_CONN

=PP1V5_S3_MEM_B

=PP1V5_S3_MEM_A

=PP1V5_S3_MEMRESET

MIN_NECK_WIDTH=0.2 MM

PP1V5_S3RS0

VOLTAGE=1.5V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

VOLTAGE=1.5V

MIN_LINE_WIDTH=0.8 MM MIN_NECK_WIDTH=0.1 MM

PP1V5_S3

=PP1V05_T29_FET

=PPVIN_S5_P5VP3V3

PPBUS_G3H

MAKE_BASE=TRUE

VOLTAGE=12.8V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

=PPVCCIO_S0_CPUIMVP

=PP3V3_S5_P3V3SUSFET

=PP1V8_S0_CPU_VCCPLL_R

=PP1V05_S0_CPU_VCCPQE

=PP1V5_S3_CPU_VCCDQ

=PPGFXVCORE_S0_VSENSE

=PPVCORE_S0_CPU_VCCAXG

=PPVCORE_S0_AXG_REG

=PPVCORE_S0_CPU =PPCPUVCORE_S0_VSENSE

=PP1V05_S0_LDO

=PP1V05_S0_PCH_VCCADPLL

=PP1V05_T29_RTR

=PP3V3_T29_FET

=PP3V3_T29_PCH_GPIO

=PP3V3_T29_RTR

=PP15V_T29_REG

=PP1V05_S0_P1V05T29FET

=PPVCCIO_S0_SMC

=PPVCCIO_S0_XDP

=PP1V05_S0_PCH_VCCDMI_FDI

=PP1V05_S0_PCH_VCC_DMI =PP1V05_S0_PCH_VCCIO_PLLFDI

=PP1V05_S0_PCH_VCCIO_CLK

=PP1V05_S0_VMON

=PP1V05_S0_PCH_VCCIO_PCIE

=PP1V05_S0_PCH_VCCIO

=PP1V05_S0_PCH

=PP5V_SUS_FET

=PPVIN_S5_HS_COMPUTING_ISNS_R

=PPVIN_SW_T29BST

=PPBUS_S0_VSENSE

=PPBUS_S0_LCDBKLT

=PP5V_S0_FET

=PP3V3_S5_USB_RESET

=PP3V3_S5_ROM

=PP3V3_S5_PCHPWRGD

=PP3V3_S5_LCD

=PP0V75_S0_MEM_VTT_A

=PP1V05_SUS_PCH_JTAG

=PPCPUVCCIO_S0_REG

=PP1V8_S0_CPU_VCCPLL

=PP1V8_S0_REG

=PPBUS_G3H

=PP3V3_S5_CPU_VCCDDR

=PP3V3_S5_REG

=PP3V3_S0_P3V3S0FET

=PP3V3_S5_XDP

=PP3V3_S5_LPCPLUS

=PP3V42_G3H_REG

=PPVIN_S5_HS_COMPUTING_ISNS

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.8V

PPBUS_S5_HS_COMPUTING_ISNS

MIN_LINE_WIDTH=0.6 MM

PPVCCSA_S0_CPU

MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

VOLTAGE=0.9V

PPVIN_SW_T29BST

VOLTAGE=12.8V

VOLTAGE=3.3V

PP3V3_T29

MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 MM

PPVCORE_S0_CPU

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.6 MM

VOLTAGE=1.25V MAKE_BASE=TRUE

MAKE_BASE=TRUE

PPVCORE_S0_AXG

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

VOLTAGE=1.05V

MAKE_BASE=TRUE

VOLTAGE=1.5V

MIN_NECK_WIDTH=0.2 MM

PP1V5_S3_CPU_VCCDQ

MIN_LINE_WIDTH=0.6 MM

PP1V05_S0_CPU_VCCPQE

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

VOLTAGE=1.05V

PP1V8_S0_CPU_VCCPLL_R

MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

VOLTAGE=1.8V

MIN_LINE_WIDTH=0.6 MM

=PPVCORE_S0_CPU_REG

=PPVDDIO_T29_CLK

=PP1V5_S3_CPU_VCCDDR =PP1V5_S3RS0_VMON

MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM

PP1V05_S0_PCH_VCCADPLL

MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

PP1V05_T29

MIN_LINE_WIDTH=0.4 MM

MAKE_BASE=TRUE

=PPHV_SW_DPAPWRSW

VOLTAGE=17.8V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

MAKE_BASE=TRUE

PP15V_T29

=PP1V05_SUS_LDO

=PP5V_S3_AUDIO_AMP =PP5V_S3_DDRREG

=PP5V_S3_MEMRESET

=PP5V_S3_P5VS0FET

=PP5V_S3_RTUSB

PP5V_S3

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

VOLTAGE=5V

=PP5V_S3_LIO_CONN

=PP5V_S0_CPUVCCIOS0

=PP5V_S0_CPUIMVP

PP5V_S0

MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 MM

VOLTAGE=5V

=PP5V_S0_LPCPLUS

=PP5V_S0_VCCSA =PP5V_S0_PCH =PP5V_S0_VMON =PP5V_S0_KBDLED

=PP1V8_S0_PCH_VCC_DFTERM

=PP1V8R1V5_S0_PCH_VCCVRM

=PP1V8_S0_P1V5S0

=PPVDDIO_S0_SBCLK

=PP1V8_S0_P1V05S0LDO

MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.8V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 MM

PP1V8_S0

=PPDDR_S3_REG

=PP1V5_S3RS0_FET

VOLTAGE=3V

MIN_LINE_WIDTH=0.2 MM

PPVRTC_G3H

MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

PP3V42_G3H

MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.42V

MIN_LINE_WIDTH=0.3 MM

=PP3V42_G3H_SMCUSBMUX

=PP3V42_G3H_SMBUS_SMC_BSA

=PP3V42_G3H_PWRCTL

=PP3V42_G3H_CHGR

=PP3V42_G3H_HALL

MAKE_BASE=TRUE

PPVTTDDR_S3

VOLTAGE=0.75V

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM

=PP3V3R1V5_S0_PCH_VCCSUSHDA

MAKE_BASE=TRUE

VOLTAGE=1.5V

PP1V5_S0

MIN_NECK_WIDTH=0.17 mm

MIN_LINE_WIDTH=2 mm

=PP3V3R1V5_S0_AUDIO

=PPVIN_S0_CPUAXG

=PPVIN_S0_VCCSAS0

=PP3V3_SUS_FET

=PPVIN_S0_CPUVCCIOS0

=PPVIN_S3_DDRREG

=PP3V3_S5_TPAD

=PP3V3_S5_PCH_VCCDSW =PP3V3_S5_SYSCLK =PP3V3_S5_VMON =PP3V3_S5_PWRCTL =PP3V3_S5_PCH_VCC_SPI

=PP3V3_SUS_PCH_VCCSUS_GPIO =PP3V3_SUS_PCH_VCCSUS

=PP3V3_SUS_P1V05SUSLDO

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

PPDCIN_G3H

MIN_NECK_WIDTH=0.25 MM VOLTAGE=18.5V

=PPDCIN_S5_VSENSE

=PP3V3_S3_BT

=PP3V3_S3_MEMRESET

=PP3V3_SUS_PCH

=PP3V3_S4_DPAPWRSW

MIN_NECK_WIDTH=0.2 MM

PP3V3_S5

MIN_LINE_WIDTH=0.6 MM

VOLTAGE=3.3V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.20MM

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.50MM

PP3V3_SUS

VOLTAGE=3.3V

=PP3V3_SUS_SMC

=PP3V3_S3_BMON_ISNS

=PP3V3_S3_USB_RESET

=PPVCCSA_S0_REG

=PPVCCSA_S0_CPU

=PP1V05_S0_PCH_VCCIO_PLLUSB

=PP1V05_S0_PCH_V_PROC_IO

=PP5V_S5_P5VSUSFET

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

MAKE_BASE=TRUE

VOLTAGE=5V

PP5V_S5

=PP3V3_S0_SYSCLKGEN

=PP3V3_S0_T29I2C

=PP3V3_S0_XDP

=PP3V3_S0_IMVPISNS

8 OF 109

2.5.0

051-8871

7 OF 74

6

43

8

24

18 19

45

51

60

43

31

44

6

39

46

8

47

6

73

54

60

65

45

35

59

16 19 22

18

22 20 22

20 22

16 20 22

20 22

6

20

9

10 12 14

45

36

40 41

52

43

41

59

16 17 19

20 22

22

59

61

16 17 18 19

20 22

45

59

35

63

61

45

37

43

25

61

12

32

6

26

6

55

31 55

48

25

60

22

6

16 17 20

6

39

6

47

65

54

16 20 22

17 19

20 22

55

60

41

60

25

41

6

48

56 57

6

51 29 30 32

27 28 32

26

6

67

6

67

35

54

6

51

56

60

12 14

12 15

44

9

12 15

57

9

12 14

44

59

20

34

35

16 19

33 34 35

8

35

40

23

20

20 22

20

20 22

61

17

20 22

16 22

60

45

8

35

44

65

60

24

49

25

62

32

23

58

14

59

52

26

54

60

23

6

42

51

45

6

35

6

57

25

10 12 15 26

61

6

35

64

6

59

50

55

26

60

38

6

51

58

56

6

42

53

22

61

48

18 20 22

20

59

25

59

6

55

60

6

38

43

61

52

6

51

6

16 20 22

6

39

57

53

60

58

55

48

20 22

25

61

20 22

20

59

6

44

6

36

26

22

64

6

73

6

41

45

24

53

12 15

20

20 22

60

6

25

43

23

44

IN

OUT

IN

OUT

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

870-1938 870-1938

870-2015

4x 860-1327

T29 DP Ports

CPU signals

SSD Boss

860-1327860-1327

T29_A_BIAS caps

Unused USB ports

T29 Aliases

DP_A_BIAS caps

SATA Aliases

Unused SATA ODD Signals

UNUSED SDCARD USB Aliases

LVDS Aliases

T29_A_BIAS caps

T29 JTAG

Unused PGOOD signal

806-1176

X21 Boss

CPU Heat Sink Mounting Bosses

DisplayPort PCB Stiffener

870-1940

USB/SD Card Pogo

EMI I/O Pogo Pins

860-1327

998-2691

DisplayPort Pogo

Fan Boss

T29 Can Slots

(Provides PCB support for small finger above J9400)

Digital Ground

60

55

33

19 23

19

21

R0917

NO STUFF

0

5%

MF

1/20W

201

21

R0918

201

1/20W

MF

0

NO STUFF

5%

16 68

43

21

R0910

0.5%

1W MF

0.01

CRITICAL

0612-1

45 73

1

Z0910

STDOFF-4.5OD1.8H-SM

1

Z0912

STDOFF-4.5OD1.8H-SM

1

Z0913

STDOFF-4.5OD1.8H-SM

1

Z0911

STDOFF-4.5OD1.8H-SM

1

Z0915

STDOFF-4.5OD1.9H-SM

1

ZS0906

SM

CRITICAL

POGO-2.0OD-3.6H-K86-K87

1

Z0914

STDOFF-4.5OD1.9H-SM

1

Z0905

STDOFF-4.5OD1.8H-SM

1

ZS0905

POGO-2.0OD-3.6H-K86-K87

CRITICAL

SM

1

MT0900

SM-SP

STIFFENER-K16-K99

NO STUFF

2

1

C0964

201

10%

0.01UF

X5R

10V

2

1

C0962

0.01UF

201

10%

X5R

10V

21

R0960

5%

1/8W

805

MF-LF

0

T29BST:N

2

1

C0960

0.01UF

10% 10V X5R 201

2

1

R0920

2.2K

5%

1/20W

MF

201

2

1

R0921

2.2K

1/20W

201

MF

5%

2

1

R0922

201

MF

1/20W

5%

2.2K

2

1

R0923

2.2K

5%

MF

201

1/20W

2

1

R0924

2.2K

5%

1/20W

MF

201

2

1

R0925

2.2K

5%

1/20W

MF

201

2

1

R0908

100K

1/20W

MF

201

5%

2

1

R0915

5%

1/20W

10K

MF

201

2

1

R0916

1/20W

201

MF

5%

10K

2

1

C0906

SIGNAL_MODEL=EMPTY

10%

0.01UF

201

10V X5R

21

R0926

SIGNAL_MODEL=EMPTY

201

51

5%

1/20W

MF

2

1

C0907

10V

10%

0.01UF

201

X5R

SIGNAL_=EMPTY

21

R0927

201

SIGNAL_MODEL=EMPTY

51

1/20W

5%

MF

2

1

C0908

SIGNAL_MODEL=EMPTY

X5R

0.01UF

10V

10%

201

2

1

C0905

0.01UF

201

X5R

10V

10%

SIGNAL_MODEL=EMPTY

2

1

C0901

SIGNAL_MODEL=EMPTY

X5R

0.01UF

10% 10V

201

2

1

C0902

SIGNAL_MODEL=EMPTY

0.01UF

10V

201

10%

X5R

2

1

C0903

SIGNAL_MODEL=EMPTY

10V

201

10%

X5R

0.01UF

2

1

C0904

SIGNAL_MODEL=EMPTY

0.01UF

10V

201

10%

X5R

21

R0931

201

MF

1/20W

5%

51

SIGNAL_MODEL=EMPTY

21

R0932

SIGNAL_MODEL=EMPTY

51

5%

1/20W

201

MF

21

R0933

SIGNAL_MODEL=EMPTY

1/20W

5%

51

201

MF

21

R0934

SIGNAL_MODEL=EMPTY

5%

1/20W

MF

51

201

24 68

1

ZS0904

POGO-2.0OD-2.95H-K86-K87

CRITICAL

SM

1

ZS0907

1.4DIA-SHORT-SILVER-K99

CRITICAL

SM

2

1

R0902

10K

5%

MF

1/20W

201

2

1

R0901

10K

1/20W

5%

MF

201

2

1

R0909

MF

1/20W

5%

100K

201

21

R0990

0

201

1/20W

5%

MF

1

SL0901

TH-NSP

SL-1.1X0.4-1.4x0.7

1

SL0902

TH-NSP

SL-1.1X0.4-1.4x0.7

SYNC_DATE=05/15/2010

Signal Aliases

SYNC_MASTER=K91_MLB

GND

VOLTAGE=0V

MIN_LINE_WIDTH=0.6MM

MIN_NECK_WIDTH=0.075MM

ISNS_LCDBKLT_N

=USB_HUB1_OCS4

=USB_HUB2_OCS4

MAKE_BASE=TRUE

PPBUS_SW_LCDBKLT_PWR

MAKE_BASE=TRUE

VOLTAGE=12.6V

MIN_NECK_WIDTH=0.375 MM

MIN_LINE_WIDTH=0.5 MM

PPBUS_SW_BKL

NC_PEG_CLK100MP

MAKE_BASE=TRUE

DPLL_REF_CLKN

MAKE_BASE=TRUE

DPLL_REF_CLK_N

DPLL_REF_CLKP

MAKE_BASE=TRUE

DPLL_REF_CLK_P

TP_PCH_CLKOUT_DPP

TP_PCH_CLKOUT_DPN

PCIE_CLK100M_EXCARD_N PCIE_CLK100M_EXCARD_P

PEG_CLK100M_N

PEG_CLK100M_P

TP_MEM_A_CLKP<1>

MAKE_BASE=TRUE

TP_MEM_A_CLKN<1>

MAKE_BASE=TRUE

NC_MEM_A_CKE<1>

MAKE_BASE=TRUE

NC_MEM_A_ODT<1>

MAKE_BASE=TRUE

NC_PEG_CLK100MN

MAKE_BASE=TRUE

PCIE_EXCARD_R2D_C_P

DP_IG_ML_N<3..0>

TP_DP_IG_B_MLP<3..0>

DP_IG_ML_P<3..0>

=DDRVTT_EN

PCIE_EXCARD_D2R_N

PCIE_EXCARD_R2D_C_N

PEG_D2R_N<3..0>

PCIE_T29_D2R_P<3..0>

MAKE_BASE=TRUE

PEG_D2R_P<3..0>

=PPBUS_SW_BKL

NC_USB_HUB2_OCS4

MAKE_BASE=TRUE

USB_SDCARD_N

USB_SDCARD_P

=PP3V3_S3_USB_HUB

USB_T29A_N USB_T29A_P

MAKE_BASE=TRUE

NC_USB_HUB1_OCS4

MAKE_BASE=TRUE

TP_MEM_B_A<15>

MEM_A_A<15>

NC_MEM_B_ODT<1>

MAKE_BASE=TRUE

NC_MEM_B_CS_L<1>

MAKE_BASE=TRUE

MEM_A_CLK_N<1>

MAKE_BASE=TRUE

DP_EXTA_ML_C_P<3..0>

MAKE_BASE=TRUE

TP_P1V5S3RS0_RAMP_DONE

MAKE_BASE=TRUE

DP_EXTA_DDC_DATA

TP_DP_IG_D_CTRL_CLK

=PP3V3_S0_DP_DDC

DP_IG_B_HPD

MAKE_BASE=TRUE

MEMVTT_EN

DP_EXTA_ML_C_N<3..0>

MAKE_BASE=TRUE

DP_EXTA_DDC_CLK

MAKE_BASE=TRUE

PCIE_T29_R2D_C_P<3..0>

MAKE_BASE=TRUE

PCIE_T29_R2D_C_N<3..0>

=PEG_D2R_P<3..0>

TP_DP_IG_B_MLN<3..0>

DP_IG_B_AUX_P

DP_IG_B_AUX_N

DP_IG_AUX_CH_N

DP_IG_AUX_CH_P

T29_A_BIAS

PCIE_T29_D2R_N<3..0>

MAKE_BASE=TRUE

=PEG_R2D_C_N<3..0>

=PEG_R2D_C_P<3..0>

=PEG_D2R_N<3..0>

TP_DP_IG_C_CTRL_CLK

MAKE_BASE=TRUE

DP_IG_D_CTRL_CLK

DP_IG_B_DDC_DATA

MAKE_BASE=TRUE

DP_EXTA_HPD

T29_A_BIAS_D2RP1

T29_A_BIAS_D2RN1

DP_A_BIAS_P_0DP_A_BIAS_P_2

T29_A_RSVD_P

T29_A_RSVD_N

P1V5S3RS0_RAMP_DONE

MAKE_BASE=TRUE

DP_IG_C_CTRL_CLK

TP_DP_IG_C_CTRL_DATA

TP_DP_IG_D_CTRL_DATA

MAKE_BASE=TRUE

DP_IG_C_CTRL_DATA

T29_A_BIAS_R

DP_IG_B_DDC_CLK

T29_A_BIAS_R2DP0

T29_A_BIAS_R2DN0

T29_A_BIAS_R2DP1

T29_A_BIAS_R2DN1

T29_A_BIAS_R

DP_EXTA_AUXCH_C_N

MAKE_BASE=TRUE

DP_EXTA_AUXCH_C_P

MEM_B_CLK_P<1>

PCIE_EXCARD_D2R_P

NC_PCIE_EXCARD_D2RP

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_PCIE_EXCARD_R2D_CP

MAKE_BASE=TRUE

TRUE

NC_PCIE_CLK100M_EXCARDP

MAKE_BASE=TRUE

TRUE

NC_PCIE_CLK100M_EXCARDN

NC_PCIE_EXCARD_R2D_CN

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_PCIE_EXCARD_D2RN

DDRREG_PGOOD

MAKE_BASE=TRUE

TP_DDRREG_PGOOD

DP_A_BIAS_N_2

MEM_A_CLK_P<1>

MAKE_BASE=TRUE

TP_MEM_A_A<15>

ISNS_LCDBKLT_P

DP_A_BIAS_N_0

MAKE_BASE=TRUE

DP_IG_D_CTRL_DATA

PEG_R2D_C_N<3..0>

PEG_R2D_C_P<3..0>

MAKE_BASE=TRUE

TP_LVDS_IG_B_CLKP

LVDS_IG_B_CLK_N

MAKE_BASE=TRUE

TP_LVDS_IG_B_CLKN

LVDS_IG_B_DATA_P<0..3>

NO_TEST=TRUE

NC_LVDS_IG_B_DATAP<0..3>

MAKE_BASE=TRUE

LVDS_IG_B_DATA_N<0..3>

NO_TEST=TRUE

NC_LVDS_IG_B_DATAN<0..3>

MAKE_BASE=TRUE

LVDS_IG_A_DATA_P<3>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_IG_A_DATAP<3>

LVDS_IG_BKL_PWM

MAKE_BASE=TRUE

LCD_BKLT_PWM

LVDS_IG_A_DATA_N<3>

NC_LVDS_IG_A_DATAN<3>

NO_TEST=TRUE

MAKE_BASE=TRUE

LVDS_IG_PANEL_PWR

MAKE_BASE=TRUE

LCD_IG_PWR_EN

LVDS_IG_BKL_ON

LCD_BKLT_EN

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SATA_ODD_R2DCN

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SATA_ODD_R2DCP

NC_SATA_ODD_D2RP

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SATA_ODD_D2RN

MAKE_BASE=TRUE

NO_TEST=TRUE

SATA_ODD_R2D_C_P

SATA_ODD_R2D_C_N

SATA_ODD_D2R_P

SATA_ODD_D2R_N

DP_T29SNK0_ML_C_N<3..0>

MAKE_BASE=TRUE

DP_T29SNK0_ML_C_P<3..0>

MAKE_BASE=TRUE

TP_DP_IG_C_MLP<3..0>

DP_T29SNK0_AUXCH_C_P

MAKE_BASE=TRUE

TP_DP_IG_C_AUXP

DP_T29SNK0_AUXCH_C_N

MAKE_BASE=TRUE

TP_DP_IG_C_AUXN

TP_DP_IG_C_HPD

MAKE_BASE=TRUE

DP_T29SNK0_HPD

TP_DP_IG_C_MLN<3..0>

MAKE_BASE=TRUE

DP_IG_D_HPD

LVDS_IG_B_CLK_P

TP_DP_IG_D_HPD

NC_MEM_A_CS_L<1>

MAKE_BASE=TRUE

TP_MEM_B_CLKN<1>

TP_MEM_B_CLKP<1>

MAKE_BASE=TRUE

NC_MEM_B_CKE<1>

=PPVIN_SW_T29BST

MEM_B_ODT<1>

MEM_A_ODT<1>

MEM_B_A<15>

MEM_B_CS_L<1>

=PP15V_T29_REG

MEM_B_CLK_N<1>

MEM_A_CS_L<1>

MEM_A_CKE<1>

MEM_B_CKE<1>

JTAG_T29_TDIJTAG_ISP_TDI

MAKE_BASE=TRUE

JTAG_ISP_TCK

MAKE_BASE=TRUE

JTAG_T29_TDOJTAG_ISP_TDO

MAKE_BASE=TRUE

JTAG_T29_TCK

JTAG_T29_TCK_R

9 OF 109

2.5.0

051-8871

8 OF 74

24

65

10 66

10 66 16

16

16 69

16

68

17

68

26 55

16

66

33 69

66

65

7 8

24

7 8

24

24 68

11 67

63 69

63

17

7 8

17

26

63 69

63

33 69

9

17

68

63 64

33 69

9

17

63

64

63 63

63 68

17

8

64

8

64

17

63

8

64

8

64

8

64

8

64

63 69

11 67

16

63 63

66

6

68

6

68

17 65

68

17 62

17 65

33 71

33 71 17

17 33

17

68

17

7

35

11 67

7

35

11 67

IN

OUT

IN

OUT

IN

OUT

IN

NC

EDP_TX_3

EDP_TX_0 EDP_TX_1 EDP_TX_2

EDP_TX_2* EDP_TX_3*

EDP_TX_0* EDP_TX_1*

EDP_AUX

EDP_AUX*

EDP_COMPIO

EDP_HPD

EDP_ICOMPO

FDI1_LSYNC

DMI_TX_3*

FDI0_LSYNC

FDI0_TX_3

FDI1_TX_1

FDI1_TX_0

FDI1_TX_2 FDI1_TX_3

FDI0_FSYNC FDI1_FSYNC

FDI_INT

FDI1_TX_3*

FDI1_TX_2*

FDI0_TX_1

FDI0_TX_0

FDI0_TX_2

FDI1_TX_1*

FDI0_TX_3*

FDI1_TX_0*

FDI0_TX_2*

FDI0_TX_1*

DMI_TX_1* DMI_TX_2*

DMI_TX_0

DMI_TX_2

DMI_TX_1

DMI_TX_3

FDI0_TX_0*

DMI_RX_2*

DMI_RX_0 DMI_RX_1 DMI_RX_2 DMI_RX_3

DMI_TX_0*

DMI_RX_3*

DMI_RX_1*

DMI_RX_0*

PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO

PEG_RX_2*

PEG_RX_0* PEG_RX_1*

PEG_RX_3* PEG_RX_4* PEG_RX_5*

PEG_RX_7*

PEG_RX_6*

PEG_RX_8* PEG_RX_9*

PEG_RX_10*

PEG_RX_12*

PEG_RX_11*

PEG_RX_14*

PEG_RX_13*

PEG_RX_15*

PEG_RX_0 PEG_RX_1

PEG_RX_3

PEG_RX_2

PEG_RX_4

PEG_RX_6

PEG_RX_5

PEG_RX_7 PEG_RX_8

PEG_RX_10

PEG_RX_9

PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15

PEG_TX_1* PEG_TX_2*

PEG_TX_0*

PEG_TX_3* PEG_TX_4* PEG_TX_5*

PEG_TX_7*

PEG_TX_6*

PEG_TX_10*

PEG_TX_8* PEG_TX_9*

PEG_TX_11* PEG_TX_12* PEG_TX_13* PEG_TX_14* PEG_TX_15*

PEG_TX_1

PEG_TX_0

PEG_TX_2 PEG_TX_3 PEG_TX_4

PEG_TX_6

PEG_TX_5

PEG_TX_7 PEG_TX_8

PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12

PEG_TX_14

PEG_TX_13

PEG_TX_15

(1 OF 9)

PCI EXPRESS BASED INTERFACE SIGNALS

DMI

INTEL FLEXIBLE DISPLAY INTERFACE SIGNALS

EMBEDDED DISPLAY PORT

VSS_VAL_SENSE

VAXG_VAL_SENSE VSSAXG_VAL_SENSE

VCC_VAL_SENSE

CFG_17

CFG_16

CFG_15

CFG_10 CFG_11 CFG_12 CFG_13 CFG_14

CFG_5 CFG_6 CFG_7 CFG_8 CFG_9

CFG_0 CFG_1 CFG_2 CFG_3 CFG_4

RSVD_28 RSVD_29

RSVD_30

RSVD_32

RSVD_31

RSVD_34

RSVD_33

RSVD_35 RSVD_36 RSVD_37 RSVD_38

RSVD_40

RSVD_39

RSVD_42 RSVD_43

RSVD_41

RSVD_44

RSVD_45

DC_TEST_A4 DC_TEST_C4

DC_TEST_D1

DC_TEST_D3

DC_TEST_A58

DC_TEST_C59

DC_TEST_A59

DC_TEST_C61

DC_TEST_A61

DC_TEST_D61

DC_TEST_BE61

DC_TEST_BD61

DC_TEST_BG61

DC_TEST_BE59

DC_TEST_BG59 DC_TEST_BG58

DC_TEST_BG4

DC_TEST_BE3

DC_TEST_BG3

DC_TEST_BE1 DC_TEST_BD1

DC_TEST_BG1

VCC_DIE_SENSE

RSVD_7

RSVD_6

RSVD_8 RSVD_9 RSVD_10

RSVD_12

RSVD_11

RSVD_13 RSVD_14 RSVD_15

RSVD_17

RSVD_16

RSVD_18 RSVD_19 RSVD_20 RSVD_21 RSVD_22

RSVD_24

RSVD_23

RSVD_25

RSVD_27

RSVD_26

RESERVED

(5 OF 9)

OUT

NC

IN

D

GS

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

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Apple Inc.

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8 7 5 4 2 1

to SO-DIMM connectors directly. FETs are needed in order to avoid potential leakage while system is in S3 state.

NOTE: Intel is investigating future processor VREF_DQ generation to replace M1 and M2.

to low voltage signals for the processor

even if internal Graphics is disabled since they are

Intel Doc 438297 Huron River SFF DG rev1.0 section 2.2.1 recommendation.

NOTE: eDP_COMPIO and eDP_ICOMPO can not be left floating shared with other interfaces.

Note. VOLTAGE=0V

Note. VOLTAGE=1.25V

doc 439028 rev1.0 HR_PPDG sections 6.2.1 and 6.3.1.

NOTE: Intel validation sense lines per

Note. VOLTAGE=0V

FOR SANDYBRIDGE PROCESSOR

NOTE: Intel provides an internal pull-up OF 5-15k to VCCIO on all CFG signals.

Note. VOLTAGE=1.05V

This would require routing processor signal balls BE7 and BG7 for Sandy Bridge 2-core

Therefore, an inverting level shifter is required on the motherboard

NOTE: The EDP_HPD processor input is a low voltage active low signal.

FIXME: Pin should be EDP_HPD*

connect it to CPU VCCIo via a 10-kOhm pull-up resistor on the motherboard.

CFG [2] :PCIE x16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

If HPD is disabled while eDP interface is still enabled,

CFG [3] :PCIE x4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

CFG [4] :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED

CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS

CFG [6:5] :PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4

These can be Placed close to J2500 and Only for debug access

This signal can be left as no-connect if entire eDP interface is disabled.

(refer to latest Processor EDS for DC specifications).

to convert the active high signal from Embedded DisplayPort sink device

17 66

8

6

8

6

8

6

8

6

8

6

8

6

21

R1010

24.9

201

1%

1/20W

MF

PLACE_NEAR=U1000.G3:12.7MM

9

23 66

9

23 66

9

23 66

9

23 66

9

23 66

9

23 66

9

23 66

9

23

17 66

A15

C15

F14

E14

F17

G17

K15

K17

C17

B18

H19

G19

F21

E21

D23

D24

J4

K4

D9

D8

F10

G10

M10

K10

H13

G13

J14

K13

C23

A23

G22

F22

B10

C9

A11

C11

D13

D12

B14

C13

D17

D16

A19

C19

D21

D19

B22

C21

K7

K6

E5

F6

H8

H6

B6

C5

A8

C8

G8

F8

J21

K19

H22

K22

G4

G1

G3

U11

AC9

AC8

Y2

AA3

V4

T4

W6

W7

AG8

AC12

AA6

AA7

W1

W3

W11

W10

U7

U6

AA10

AA11

AE7

AE6

AE11

AE10

AC4

AA4

AC3

AC1

AD2

AG11

AF3

AG4 AF4

R2

T3

N4

P4

M8

M7

K1

K3

P10

P11

P1

P3

P6

P7

M2

N3

U1000

MOBILE-2C-35W

BGA

CRITICAL

OMIT_TABLE

SANDY-BRIDGE

K45

K43

H43

F48

H45

W14

U14

P13

N50

N42

M14

M13

L47

L45

L42

K48

K24

H48

BG7

BG26

BG22

BF23

BE7

BE26

BE24

BE22

BD26

BD25

BD22

BD21

BB21 BB19

BA22

BA19

AY22

AY21

AV19

AU21

AU19

AT49

AT21

AM15

AM14

AH2 AG13

D61

D3 D1

C61

C59

C4

BG61 BG59 BG58 BG4 BG3

BG1

BE61 BE59

BE3

BE1

BD61

BD1

A61

A59

A58

A4

H51

A55

H49

C55

C53

A51

D53

B54

L53

D52

F51

L51

G53

F53

K53

K49

C51

B50

U1000

SANDY-BRIDGE

MOBILE-2C-35W

OMIT_TABLE

CRITICAL

BGA

46 73

2

1

R1044

EDP

1K

5%

MF-LF

1/16W

402

9

23 66

2

1

R1064

201

MF

1/20W

1%

49.9

NOSTUFF

2

1

R1070

PLACE_NEAR=U1000.H45:50.8MM PLACE_SIDE=BOTTOM

201

MF

1/20W

1%

49.9

NOSTUFF

2

1

R1065

NOSTUFF

49.9

1%

1/20W

MF

201

PLACE_NEAR=U1000.K43:50.8MM

PLACE_SIDE=BOTTOM

2

1

R1071

PLACE_NEAR=U1000.K45:50.8MM

PLACE_SIDE=BOTTOM

NOSTUFF

49.9

1% 1/20W MF 201

21

R1021

1/20W

5%

0

MF

201

NOSTUFF

2

1

R1020

NOSTUFF

1K

1% 1/20W MF 201

21

R1030

PLACE_NEAR=U1000.AF3:12.7MM

MF

201

1/20W

1%

24.9

2

1

R1045

5%

1K

MF-LF

1/16W

402

2

1

R1046

NOSTUFF

1K

5%

MF-LF

1/16W

402

2

1

R1047

5%

1K

NOSTUFF

MF-LF

1/16W

402

2

1

R1042

NOSTUFF

1K

5%

MF-LF

1/16W

402

2

1

R1040

5%

1K

NOSTUFF

1/16W

MF-LF

402

2

1

R1041

1K

MF-LF

1/16W

5%

402

NOSTUFF

2

1

R1043

NOSTUFF

MF-LF

1/16W

1K

402

5%

2

1

R1049

5%

1K

NOSTUFF

MF-LF

1/16W

402

2

1

R1031

201

1K

MF

1/20W

5%

PLACE_NEAR=U1000.AG11:12.7MM

2

1

3

Q1031

SOD-VESM-HF

SSM3K15FV

CPU DMI/PEG/FDI/RSVD

EDP_HPD_L

CPU_CFG<16>

CPU_CFG<3>

=PEG_R2D_C_N<5>

=PEG_R2D_C_N<4>

FDI_DATA_P<1>

=PP1V05_S0_CPU_VCCIO

CPU_CFG<1>

CPU_CFG<6>

CPU_MEM_VREFDQ_A

PP0V75_S3_MEM_VREFDQ_A

CPU_AXG_VALSENSE_N

CPU_VCC_VALSENSE_N

=PPVCORE_S0_CPU_VCCAXG

CPU_AXG_VALSENSE_P

CPU_VCC_VALSENSE_P

=PPVCORE_S0_CPU

CPU_CFG<4>

CPU_THERMD_N

CPU_CFG<7>

CPU_CFG<6>

CPU_CFG<5>

CPU_CFG<3>

CPU_CFG<1>

CPU_CFG<0>

CPU_CFG<9>

CPU_CFG<8>

CPU_CFG<12>

CPU_CFG<11>

CPU_CFG<10>

CPU_CFG<14>

CPU_CFG<13>

CPU_CFG<15> CPU_CFG<16> CPU_CFG<17>

=PP1V05_S0_CPU_VCCIO

CPU_THERMD_P

TP_CPU_VCC_DIE_SENSE

TP_CPU_DC_TEST_BD1

CPU_DC_TEST_C4_BE1_BG1

CPU_DC_TEST_C4_BE3_BG3

TP_CPU_DC_TEST_BG4

TP_CPU_DC_TEST_BG58

CPU_DC_TEST_BG59_BG61

TP_CPU_DC_TEST_BD61

CPU_DC_TEST_BE59_BE61

TP_CPU_DC_TEST_D61

CPU_DC_TEST_C61_A61

CPU_DC_TEST_C59_A59

TP_CPU_DC_TEST_A58

TP_CPU_DC_TEST_D1

CPU_DC_TEST_C4_D3

TP_CPU_DC_TEST_A4

CPU_MEM_VREFDQ_A

=PP1V05_S0_CPU_VCCIO

CPU_CFG<2>

DP_INT_HPD

=PEG_R2D_C_P<15>

=PEG_R2D_C_P<13> =PEG_R2D_C_P<14>

=PEG_R2D_C_P<12>

=PEG_R2D_C_P<11>

=PEG_R2D_C_P<10>

=PEG_R2D_C_P<9>

=PEG_R2D_C_P<8>

=PEG_R2D_C_P<7>

=PEG_R2D_C_P<5> =PEG_R2D_C_P<6>

=PEG_R2D_C_P<4>

=PEG_R2D_C_P<3>

=PEG_R2D_C_P<2>

=PEG_R2D_C_P<0> =PEG_R2D_C_P<1>

=PEG_R2D_C_N<13>

=PEG_R2D_C_N<9>

=PEG_R2D_C_N<8>

=PEG_R2D_C_N<10>

=PEG_R2D_C_N<7>

=PEG_R2D_C_N<3>

=PEG_R2D_C_N<0>

=PEG_R2D_C_N<2>

=PEG_R2D_C_N<1>

=PEG_D2R_P<15>

=PEG_D2R_P<14>

=PEG_D2R_P<13>

=PEG_D2R_P<12>

=PEG_D2R_P<11>

=PEG_D2R_P<9> =PEG_D2R_P<10>

=PEG_D2R_P<8>

=PEG_D2R_P<7>

=PEG_D2R_P<5> =PEG_D2R_P<6>

=PEG_D2R_P<4>

=PEG_D2R_P<2> =PEG_D2R_P<3>

=PEG_D2R_P<1>

=PEG_D2R_P<0>

=PEG_D2R_N<15>

=PEG_D2R_N<13> =PEG_D2R_N<14>

=PEG_D2R_N<11> =PEG_D2R_N<12>

=PEG_D2R_N<10>

=PEG_D2R_N<9>

=PEG_D2R_N<8>

=PEG_D2R_N<6> =PEG_D2R_N<7>

=PEG_D2R_N<5>

=PEG_D2R_N<4>

=PEG_D2R_N<1> =PEG_D2R_N<2>

CPU_PEG_COMP DMI_S2N_N<0> DMI_S2N_N<1>

DMI_S2N_N<3>

DMI_N2S_N<0>

DMI_S2N_P<3>

DMI_S2N_P<2>

DMI_S2N_P<1>

DMI_S2N_P<0>

DMI_S2N_N<2>

DMI_N2S_P<3>

DMI_N2S_P<1> DMI_N2S_P<2>

DMI_N2S_P<0>

DMI_N2S_N<2>

DMI_N2S_N<1>

FDI_DATA_N<2>

FDI_DATA_N<4>

FDI_DATA_N<3>

FDI_DATA_N<5>

FDI_DATA_P<2>

FDI_DATA_P<0>

FDI_DATA_N<6> FDI_DATA_N<7>

FDI_INT

FDI_FSYNC<1>

FDI_FSYNC<0>

FDI_DATA_P<7>

FDI_DATA_P<6>

FDI_DATA_P<4> FDI_DATA_P<5>

FDI_DATA_P<3>

FDI_LSYNC<0>

DMI_N2S_N<3>

FDI_LSYNC<1>

EDP_HPD_L

EDP_COMP

DP_INT_AUX_CH_N DP_INT_AUX_CH_P

DP_INT_ML_N<1>

DP_INT_ML_N<0>

TP_EDP_TX_N<3>

TP_EDP_TX_N<2>

TP_EDP_TX_P<2>

DP_INT_ML_P<1>

DP_INT_ML_P<0>

TP_EDP_TX_P<3>

=PEG_R2D_C_N<14> =PEG_R2D_C_N<15>

FDI_DATA_N<0> FDI_DATA_N<1>

=PEG_D2R_N<3>

=PEG_D2R_N<0>

=PEG_R2D_C_N<11> =PEG_R2D_C_N<12>

=PEG_R2D_C_N<6>

CPU_CFG<5> CPU_CFG<4>

CPU_CFG<7>

CPU_CFG<2>

CPU_CFG<0>

10 OF 109

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9

23

9

23 66

7 9

10 12 14

9

23 66

9

23 66

9

27 28 29 30 31 67

7

12

15

7

12 14

7 9

10 12 14

9

7 9

10 12 14

62

66

9

66

62 69

6

62 69

6

9

23 66

9

23 66

9

23 66

9

23 66

9

23 66

BI

IN

OUT

IN

OUT

BI

NC

OUT

SM_RCOMP_2

SM_RCOMP_1

SM_RCOMP_0

SM_DRAMRST*

BCLK_ITP

BCLK_ITP*

DPLL_REF_CLK*

DPLL_REF_CLK

BCLK*

BCLK

RESET*

SM_DRAMPWROK

UNCOREPWRGOOD

PM_SYNC

PROC_SELECT*

PROC_DETECT*

PREQ*

TMS

TRST*

TDI TDO

DBR*

BPM_0* BPM_1* BPM_2* BPM_3* BPM_4* BPM_5* BPM_6* BPM_7*

TCK

PRDY*

THERMTRIP*

CATERR*

PROCHOT*

PECI

(2 OF 9)

CLOCKS

THERMAL

PWR MGMT

JTAG & BPM

DDR3 MISC

IN

OUT

IN

OUT

IN

OUT

BI

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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Apple Inc.

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8 7 5 4 2 1

(IPU) (IPU)

(IPU) (IPU) (IPU) (IPU) (IPU) (IPU)

(IPU)

23 66

17 26 66

19 23 66

26

16 66

18

19 66

41 56 66

19 40 66

66

B46

J58

L55

D45

L59

M60

L56

BG43

BE43

BF44

AT30

BE45

D44

C45

F49

C57

N55

N53

C48

A48

AG1

AG3

K58

C49

J61

J59

H60

G59

G55

E59

E55

G58

N58

N59

H2

J3

U1000

OMIT_TABLE

CRITICAL

SANDY-BRIDGE

MOBILE-2C-35W

BGA

2

1

R1101

62

5% 1/20W MF 201

2

1

R1104

201

MF

1/20W

5%

51

NOSTUFF

2

1

R1100

1K

5%

1/20W

MF

201

NOSTUFF

2

1

R1102

NOSTUFF

1K

5% 1/20W MF 201

21

R1103

201

MF

1/20W

5%

56

2

1

R1120

200

1%

1/20W

MF

201

21

R1121

1%

1/20W

MF

201

130

2

1

R1114

1%

MF

1/20W

200

201

2

1

R1113

1% 1/20W

201

MF

25.5

2

1

R1112

140

1% 1/20W MF 201

2

1

R1111

10K

201

MF

1/20W

5%

2

1

R1126

75

1%

1/20W

MF

201

21

R1125

43.2

1%

MF

1/20W

201

2

1

R1115

1/20W MF

4.99K

1%

201

NOSTUFF

8

66

8

66

23 66

16 66

17 66

23 25

23 25 66

23 66

CPU CLOCK/MISC/JTAG

DMI_CLK100M_CPU_N

DMI_CLK100M_CPU_P

PLT_RESET_LS1V1_L

=MEM_RESET_L

CPU_PWRGD

PM_MEM_PWRGD_R

CPU_SM_RCOMP<0>

CPU_SM_RCOMP<2>

XDP_BPM_L<1>

PM_MEM_PWRGD

=PP1V5_S3_CPU_VCCDDR

CPU_PROCHOT_R_L

CPU_PROCHOT_L

CPU_CATERR_L

XDP_CPU_PREQ_L

ITPCPU_CLK100M_N

ITPCPU_CLK100M_P

CPU_PECI

CPU_RESET_L

=PP1V05_S0_CPU_VCCIO

CPU_SM_RCOMP<1>

PM_THRMTRIP_L

CPU_PROC_SEL_L

XDP_CPU_TRST_L

XDP_CPU_TDI

XDP_CPU_TCK

XDP_BPM_L<7>

XDP_BPM_L<6>

XDP_BPM_L<5>

XDP_BPM_L<4>

XDP_BPM_L<3>

XDP_BPM_L<2>

XDP_CPU_TDO

PM_SYNC

=PP1V05_S0_CPU_VCCIO

XDP_BPM_L<0>

XDP_DBRESET_L

XDP_CPU_TMS

XDP_CPU_PRDY_L

DPLL_REF_CLKP DPLL_REF_CLKN

11 OF 109

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66

7

12 15 26

7 9

10 12 14

66

7 9

10 12 14

BI

OUT

BI

OUT

BI

OUT

BI

OUT

SA_MA_14 SA_MA_15

SA_MA_12 SA_MA_13

SA_MA_11

SA_MA_9

SA_MA_10

SA_MA_8

SA_MA_7

SA_MA_6

SA_MA_5

SA_MA_4

SA_MA_3

SA_MA_2

SA_MA_1

SA_MA_0

SA_DQS_7

SA_DQS_5 SA_DQS_6

SA_DQS_3 SA_DQS_4

SA_DQS_2

SA_DQS_0 SA_DQS_1

SA_DQS_7*

SA_DQS_6*

SA_DQS_5*

SA_DQS_4*

SA_DQS_3*

SA_DQS_2*

SA_DQS_0* SA_DQS_1*

SA_ODT_1

SA_ODT_0

SA_CS_1*

SA_CS_0*

SA_CKE_1

SA_CK_1*

SA_CK_1

SA_CKE_0

SA_CK_0*

SA_CK_0

SA_WE*

SA_RAS*

SA_CAS*

SA_BS_0 SA_BS_1 SA_BS_2

SA_DQ_62 SA_DQ_63

SA_DQ_61

SA_DQ_60

SA_DQ_59

SA_DQ_58

SA_DQ_57

SA_DQ_56

SA_DQ_55

SA_DQ_54

SA_DQ_53

SA_DQ_52

SA_DQ_50 SA_DQ_51

SA_DQ_49

SA_DQ_48

SA_DQ_47

SA_DQ_46

SA_DQ_45

SA_DQ_44

SA_DQ_42 SA_DQ_43

SA_DQ_41

SA_DQ_39 SA_DQ_40

SA_DQ_38

SA_DQ_37

SA_DQ_36

SA_DQ_34 SA_DQ_35

SA_DQ_31

SA_DQ_33

SA_DQ_32

SA_DQ_29 SA_DQ_30

SA_DQ_26

SA_DQ_28

SA_DQ_27

SA_DQ_24 SA_DQ_25

SA_DQ_23

SA_DQ_22

SA_DQ_21

SA_DQ_19 SA_DQ_20

SA_DQ_18

SA_DQ_17

SA_DQ_16

SA_DQ_13 SA_DQ_14 SA_DQ_15

SA_DQ_11 SA_DQ_12

SA_DQ_9 SA_DQ_10

SA_DQ_8

SA_DQ_7

SA_DQ_6

SA_DQ_5

SA_DQ_4

SA_DQ_3

SA_DQ_2

SA_DQ_1

SA_DQ_0

(3 OF 9)

MEMORY CHANNEL A

SB_MA_15

SB_MA_14

SB_MA_12 SB_MA_13

SB_MA_11

SB_MA_10

SB_MA_9

SB_MA_7 SB_MA_8

SB_MA_6

SB_MA_5

SB_MA_4

SB_MA_3

SB_MA_2

SB_MA_1

SB_MA_0

SB_DQS_7

SB_DQS_6

SB_DQS_5

SB_DQS_4

SB_DQS_3

SB_DQS_2

SB_DQS_1

SB_DQS_0

SB_DQS_7*

SB_DQS_6*

SB_DQS_5*

SB_DQS_4*

SB_DQS_3*

SB_DQS_2*

SB_DQS_1*

SB_DQS_0*

SB_ODT_0 SB_ODT_1

SB_CS_1*

SB_CS_0*

SB_CKE_1

SB_CK_1

SB_CK_1*

SB_CK_0*

SB_CKE_0

SB_CK_0

SB_DQ_37

SB_DQ_36

SB_DQ_34 SB_DQ_35

SB_DQ_33

SB_DQ_31 SB_DQ_32

SB_DQ_30

SB_DQ_29

SB_DQ_26 SB_DQ_27 SB_DQ_28

SB_DQ_24 SB_DQ_25

SB_DQ_21 SB_DQ_22 SB_DQ_23

SB_DQ_20

SB_DQ_19

SB_DQ_18

SB_DQ_17

SB_DQ_16

SB_DQ_15

SB_DQ_14

SB_DQ_13

SB_DQ_12

SB_DQ_11

SB_DQ_10

SB_DQ_8 SB_DQ_9

SB_DQ_7

SB_DQ_6

SB_DQ_4 SB_DQ_5

SB_DQ_3

SB_DQ_2

SB_DQ_1

SB_DQ_0

SB_DQ_39

SB_DQ_38

SB_DQ_40 SB_DQ_41 SB_DQ_42

SB_DQ_44

SB_DQ_43

SB_DQ_46

SB_DQ_45

SB_DQ_47

SB_DQ_49

SB_DQ_48

SB_DQ_51

SB_DQ_50

SB_DQ_52

SB_DQ_54

SB_DQ_53

SB_DQ_56

SB_DQ_55

SB_DQ_57

SB_DQ_59

SB_DQ_58

SB_DQ_61

SB_DQ_60

SB_DQ_62

SB_BS_0

SB_DQ_63

SB_BS_2

SB_BS_1

SB_RAS*

SB_CAS*

SB_WE*

(4 OF 9)

MEMORY CHANNEL B

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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8 7 5 4 2 1

27 67

28 67

27 28 32 67

29 67

30 67

29 30 32 67

27 28 32 67

27 67

28 67

27 67

28 67

27 28 32 67

8

67

29 30 32 67

29 67

30 67

29 67

30 67

29 30 32 67

8

67

AT41

BD39

BA41

AY40

AV32

AY32

AT32

BB32

AU34

AT34

BD35

BE35

AU26

AY28

AW41

BC30

BA30

BE37

BB34

BG35

AK55

AK54

AT55

AT56

AY51

AV51

AV45

AW45

AT17

AU17

AV11

AY11

AR8

AR10

AL11

AJ11

AP6

AR11

AL7

AK56

AG55

AN52

AN55

AL8

AG53

AG56

AN53

AN57

AP52

AP56

AT54

AV54

AP53

AP50

AJ8

AV56

BA55

BB55

BA53

AU49

BB49

AY53

BB51

AV49

BA49

AJ10

AY48

AT48

AR45

BC45

BC48

AW48

AR43

BA45

BB17

BB14

AL6

AU14

BA14

AR19

AY17

AR14

AV14

AY13

BB9

BA9

BA7

AP11

BB11

BA13

BB7

BC7

AU13

AT13

AP8

AR6

AV9

AU6

AJ6

AG6

BC41

BB40

BB26

AY26

AU40

AT40

AV36

AU36

BE39

BA28

BF36

BD37

U1000

SANDY-BRIDGE

MOBILE-2C-35W

CRITICAL

BGA

OMIT_TABLE

BD45

BF40

BG47

AT43

BE28

BE30

BD29

BG30

AV30

BD30

AU30

BD33

AU22

AT26

BD46

AV28

AT28

BD43

BE33

BF32

AK59

AK61

AT60

AR59

BA59

BA61

BG51

BE51

BD17

BD18

BG11

BE11

AV3

AV1

AL3

AM2

AT2

AU4

AR1

AH60

AF61

AL59

AM60

AN4

AG59

AG58

AL58

AK58

AR58

AN58

AU61

AU59

AN59

AN61

AK3

AU58

AW58

AW59

BA58

BG54

BE54

AY60

BC59

BE57

BF56

AK4

BE53

BD54

BE49

BD49

BF52

BD53

BF48

BD50

BF19

BG18

AR4

BG14

BE14

BE21

BE18

BE17

BF16

BE13

BD14

BD10

BF8

AN3

BF12

BD13

BD9

BE9

BA3

AY2

AR3

AU3

BA4

AV4

AL1

AL4

BE47

BE41

BF27

AR22

BB36

BA36

AY34

BA34

AV43

AT22

BD42

BG39

U1000

MOBILE-2C-35W

SANDY-BRIDGE

OMIT_TABLE

CRITICAL

BGA

8

67

8

67

8

67

8

67

8

67

8

67

8

67

8

67

8

67

8

67

SYNC_DATE=12/13/2010

CPU DDR3 INTERFACES

MEM_B_DQ<27>

MEM_B_A<7>

MEM_A_DQ<46>

MEM_B_RAS_L MEM_B_WE_L

MEM_B_CAS_L

MEM_B_BA<2>

MEM_B_BA<1>

MEM_B_DQ<63>

MEM_B_BA<0>

MEM_B_DQ<62>

MEM_B_DQ<60> MEM_B_DQ<61>

MEM_B_DQ<58> MEM_B_DQ<59>

MEM_B_DQ<57>

MEM_B_DQ<55> MEM_B_DQ<56>

MEM_B_DQ<53> MEM_B_DQ<54>

MEM_B_DQ<52>

MEM_B_DQ<50> MEM_B_DQ<51>

MEM_B_DQ<48> MEM_B_DQ<49>

MEM_B_DQ<47>

MEM_B_DQ<45> MEM_B_DQ<46>

MEM_B_DQ<43> MEM_B_DQ<44>

MEM_B_DQ<42>

MEM_B_DQ<41>

MEM_B_DQ<40>

MEM_B_DQ<38> MEM_B_DQ<39>

MEM_B_DQ<0> MEM_B_DQ<1> MEM_B_DQ<2> MEM_B_DQ<3>

MEM_B_DQ<5>

MEM_B_DQ<4>

MEM_B_DQ<6>

MEM_B_DQ<9> MEM_B_DQ<10> MEM_B_DQ<11> MEM_B_DQ<12> MEM_B_DQ<13> MEM_B_DQ<14> MEM_B_DQ<15> MEM_B_DQ<16> MEM_B_DQ<17> MEM_B_DQ<18> MEM_B_DQ<19> MEM_B_DQ<20>

MEM_B_DQ<23>

MEM_B_DQ<22>

MEM_B_DQ<21>

MEM_B_DQ<25>

MEM_B_DQ<24>

MEM_B_DQ<28>

MEM_B_DQ<26>

MEM_B_DQ<29> MEM_B_DQ<30>

MEM_B_DQ<32>

MEM_B_DQ<31>

MEM_B_DQ<33>

MEM_B_DQ<35>

MEM_B_DQ<34>

MEM_B_DQ<36> MEM_B_DQ<37>

MEM_B_CLK_N<0>

MEM_B_ODT<0>

MEM_B_DQS_N<1> MEM_B_DQS_N<2> MEM_B_DQS_N<3> MEM_B_DQS_N<4> MEM_B_DQS_N<5> MEM_B_DQS_N<6> MEM_B_DQS_N<7>

MEM_B_DQS_P<0> MEM_B_DQS_P<1> MEM_B_DQS_P<2> MEM_B_DQS_P<3> MEM_B_DQS_P<4> MEM_B_DQS_P<5> MEM_B_DQS_P<6> MEM_B_DQS_P<7>

MEM_B_A<0> MEM_B_A<1> MEM_B_A<2> MEM_B_A<3> MEM_B_A<4> MEM_B_A<5> MEM_B_A<6>

MEM_B_A<8> MEM_B_A<9> MEM_B_A<10> MEM_B_A<11>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_A<14> MEM_B_A<15>

MEM_A_DQS_P<1>

MEM_A_DQ<1>

MEM_A_DQ<4> MEM_A_DQ<5> MEM_A_DQ<6> MEM_A_DQ<7> MEM_A_DQ<8>

MEM_A_DQ<10>

MEM_A_DQ<9>

MEM_A_DQ<12>

MEM_A_DQ<11>

MEM_A_DQ<14>

MEM_A_DQ<13>

MEM_A_DQ<16> MEM_A_DQ<17> MEM_A_DQ<18>

MEM_A_DQ<20>

MEM_A_DQ<19>

MEM_A_DQ<21> MEM_A_DQ<22> MEM_A_DQ<23>

MEM_A_DQ<25>

MEM_A_DQ<24>

MEM_A_DQ<27> MEM_A_DQ<28>

MEM_A_DQ<26>

MEM_A_DQ<30>

MEM_A_DQ<29>

MEM_A_DQ<32> MEM_A_DQ<33>

MEM_A_DQ<31>

MEM_A_DQ<35>

MEM_A_DQ<34>

MEM_A_DQ<36> MEM_A_DQ<37> MEM_A_DQ<38>

MEM_A_DQ<40>

MEM_A_DQ<39>

MEM_A_DQ<41>

MEM_A_DQ<43>

MEM_A_DQ<42>

MEM_A_DQ<44> MEM_A_DQ<45>

MEM_A_DQ<47> MEM_A_DQ<48> MEM_A_DQ<49>

MEM_A_DQ<51>

MEM_A_DQ<50>

MEM_A_DQ<52> MEM_A_DQ<53> MEM_A_DQ<54> MEM_A_DQ<55> MEM_A_DQ<56> MEM_A_DQ<57> MEM_A_DQ<58> MEM_A_DQ<59> MEM_A_DQ<60> MEM_A_DQ<61>

MEM_A_DQ<63>

MEM_A_DQ<62>

MEM_A_BA<2>

MEM_A_BA<1>

MEM_A_BA<0>

MEM_A_CAS_L MEM_A_RAS_L MEM_A_WE_L

MEM_A_DQS_N<5> MEM_A_DQS_N<6>

MEM_A_DQS_P<0>

MEM_A_DQS_P<2>

MEM_A_DQS_P<6>

MEM_A_DQS_P<5>

MEM_A_DQS_P<7>

MEM_A_A<0>

MEM_A_A<2> MEM_A_A<3> MEM_A_A<4>

MEM_A_A<8>

MEM_A_A<10>

MEM_A_A<9>

MEM_A_A<11>

MEM_A_A<13>

MEM_A_A<12>

MEM_A_A<14> MEM_A_A<15>

MEM_B_DQS_N<0>

MEM_B_CS_L<0>

MEM_B_CLK_P<0>

MEM_A_DQS_N<7>

MEM_B_DQ<8>

MEM_B_DQ<7>

MEM_B_CKE<0>

MEM_A_DQS_N<4>

MEM_A_DQS_N<3>

MEM_A_DQS_N<2>

MEM_A_DQS_N<1>

MEM_A_DQS_N<0>

MEM_A_DQ<15>

MEM_A_CLK_P<0>

MEM_A_ODT<0>

MEM_A_CS_L<0>

MEM_A_CKE<0>

MEM_A_DQS_P<4>

MEM_A_DQS_P<3>

MEM_A_A<1>

MEM_A_A<5> MEM_A_A<6> MEM_A_A<7>

MEM_A_DQ<3>

MEM_A_DQ<2>

MEM_A_DQ<0>

MEM_A_CLK_N<0>

MEM_A_CLK_N<1>

MEM_A_CKE<1>

MEM_A_CS_L<1>

MEM_A_ODT<1>

MEM_A_CLK_P<1> MEM_B_CLK_P<1>

MEM_B_CLK_N<1>

MEM_B_CKE<1>

MEM_B_CS_L<1>

MEM_B_ODT<1>

12 OF 109

2.5.0

051-8871

11 OF 74

OUT

IN

BI

OUT

VCCIO_29

VCCIO_28

VCCIO_27

VCCIO_26

VCCIO_25

VCCIO_24

VCCIO_23

VCCIO_22

VCCIO_21

VCCIO_20

VCCIO_19

VCCIO_18

VCCIO_17

VCCIO_16

VCCIO_15

VCCIO_14

VCCIO_13

VCCIO_12

VCCIO_11

VCCIO_10

VCCIO_9

VCCIO_8

VCCIO_7

VCCIO_6

VCCIO_49

VCCIO_48

VCCIO_5

VCCIO_4

VCCIO_3

VCCIO_47

VCCIO_46

VCCIO_45

VCCIO_44

VCCIO_43

VCCIO_1

VCCIO_42

VCCIO_41

VCCIO_40

VCCIO_39

VCCIO_38

VCCIO_37

VCCIO_36

VCCIO_35

VCCIO_34

VCCIO_33

VCCIO_32

VCCIO_31

VCCIO_30

VCCIO_51

VCCIO_50

VCC_76

VCC_75

VCC_74

VCC_73

VCC_72

VCC_71

VCC_70

VCC_69

VCC_68

VCC_67

VCC_66

VCC_64

VCC_63

VCC_62

VCC_61

VCC_60

VCC_59

VCC_58

VCC_57

VCC_56

VCC_55

VCC_54

VCC_53

VCC_52

VCC_51

VCC_50

VCC_49

VCC_48

VCC_47

VCC_46

VCC_45

VCC_44

VCC_43

VCC_42

VCC_41

VCC_40

VCC_39

VCC_38

VCC_37

VCC_36

VCC_35

VCC_34

VCC_33

VCC_32

VCC_31

VCC_30

VCC_29

VCC_28

VCC_27

VCC_26

VCC_25

VCC_24

VCC_23

VCC_22

VCC_21

VCC_20

VCC_19

VCC_18

VCC_17

VCC_16

VCC_15

VCC_14

VCC_13

VCC_12

VCC_11

VCC_10

VCC_9

VCC_8

VCC_7

VCC_6

VCC_5

VCC_4

VCC_3

VCC_2

VCC_1

VCCIO_SEL

VCCPQE_1 VCCPQE_2

VIDALERT*

VIDSCLK VIDSOUT

VCC_SENSE VSS_SENSE

VCCIO_SENSE

VSS_SENSE_VCCIO

LINES

SENSE SVID QUIET

RAIL

PEG AND DDR

CORE SUPLLY

(6 OF 9)

(7 OF 9)

SENSE

LINE

1.8V

RAIL

SA RAIL

QUIET

RAIL

SENSE

LINE

DDR3-1.5V RAILS

GRPHICS

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8

VDDQ_10

VDDQ_9

VDDQ_11 VDDQ_12 VDDQ_13 VDDQ_14 VDDQ_15 VDDQ_16 VDDQ_17 VDDQ_18

VDDQ_20

VDDQ_19

VDDQ_21 VDDQ_22 VDDQ_23 VDDQ_24 VDDQ_25 VDDQ_26

VCCDQ_1 VCCDQ_2

VDDQ_SENSE

VSS_SENSE_VDDQ

VCCSA_SENSE

VCCSA_VID_0 VCCSA_VID_1

SM_VREF

VAXG_1 VAXG_2

VAXG_4

VAXG_3

VAXG_5 VAXG_6 VAXG_7 VAXG_8 VAXG_9 VAXG_10 VAXG_11 VAXG_12 VAXG_13 VAXG_14 VAXG_15 VAXG_16 VAXG_17 VAXG_18 VAXG_19 VAXG_20 VAXG_21 VAXG_22 VAXG_23 VAXG_24 VAXG_25

VAXG_28

VAXG_26 VAXG_27

VAXG_30

VAXG_29

VAXG_33

VAXG_31 VAXG_32

VAXG_35

VAXG_34

VAXG_36 VAXG_37 VAXG_38 VAXG_39 VAXG_40 VAXG_41 VAXG_42 VAXG_43

VAXG_45

VAXG_44

VAXG_46 VAXG_47 VAXG_48 VAXG_49 VAXG_50 VAXG_51 VAXG_52 VAXG_53 VAXG_54 VAXG_55 VAXG_56

VAXG_SENSE VSSAXG_SENSE

VCCPLL_1 VCCPLL_2 VCCPLL_3

VCCSA_2

VCCSA_1

VCCSA_3 VCCSA_4 VCCSA_5 VCCSA_6 VCCSA_7 VCCSA_8 VCCSA_9 VCCSA_10 VCCSA_11 VCCSA_12 VCCSA_13

VCCSA_15

VCCSA_14

VCCSA_16

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side.

Note. VOLTAGE=1.25V

Note. VOLTAGE=1.05V

Note. VOLTAGE=0V

PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side.

Fixed at 1.05V

(IPU)

(NOT controlled by VCCIO_SEL)

For Future Compatibility

(IPU)

Note. VOLTAGE=1.05V

Note. VOLTAGE=0V

Note. VOLTAGE=1.05V

Note. VOLTAGE=0V

PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side.

56 66

58 66

53

56 66

53

AN17

G43

C44

B43

A44

AN22

AM25

W17

W16

AN16

BC22

AN48

AN45

AN42

AN20

AM47

AM43

AM21

AM17

AM16

AL48

AL45

AL26

AL22

AL20

AL16

AL15

AL14

AK51

AK50

AJ47

AJ43

AJ25

AJ21

AJ17

AJ15

AJ14

AG51

AG50

AG48

AG21

AG20

AG17

AG16

AG15

AF46

AF20

AF18

AF16

AE15

AE14

AD21

AD18

AD16

AC13

AB20

AB17

AA15

AA14

F43

N38

N34

N30

N26

L40

L36

L33

L28

L25

K42

K39

K37

K35

K34

K32

K29

K27

K26

J42

J40

J38

J37

J35

J34

J32

J29

J28

J26

J25

H40

H38

H37

H35

H34

H32

H29

H28

H26

H25

G42

F42

F38

F37

F34

F32

F28

F26

F25

E38

E37

E34

E32

E28

E26

D42

D39

D37

D34

D32

D27

C42

C39

C37

C34

C32

C27

C26

A42

A39

A38

A35

A34

A31

A29

A26

U1000

BGA

CRITICAL

OMIT_TABLE

MOBILE-2C-35W

SANDY-BRIDGE

G45

BA43

BC43

BG33

BB28

BA40

AW26

AV41

AR40

AR36

AR34

AR32

AR30

AR28

AR26

AN38

AN34

AN30

AM40

AM36

AM33

AL42

AL38

AL34

AL30

AJ40

AJ36

AJ33

AJ28

W20

D49

D48

V21

V18

V17

V16

U15

U10

R21

R18

R16

P20

P17

N22

N20

N16

L21

L17

BC4

BC1

BB3

AN26

AM28

Y61

Y48

W61

W56

W55

W53

W52

W51

W50

V59

V58

V56

V55

V53

V52

V51

V50

V48

V47

U46

T61

T59

T58

T48

F45

P61

P56

P55

P53

P52

P51

P50

P48

P47

N45

AE46

AD59

AD58

AD56

AD55

AD53

AD52

AD51

AD50

AD48

AD47

AC61

AB59

AB58

AB56

AB55

AB53

AB52

AB51

AB50

AB47

AA46

AY43

U1000

SANDY-BRIDGE

MOBILE-2C-35W

BGA

CRITICAL

OMIT_TABLE

21

R1311

MF05%

1/20W

201

21

R1312

MF05%

1/20W

201

21

R1310

43

201

1/20W

5% MF

2

1

R1302

PLACE_NEAR=U1000.C44:2.54mm

201

MF

1/20W

1%

130

2

1

R1320

10K

1/20W

5%

MF

201

2

1

R1300

201

MF

1/20W

1%

75

PLACE_NEAR=R1310.2:2.54mm

2

1

R1370

PLACE_NEAR=U1000.F45:50.8mm

PLACE_SIDE=BOTTOM

NOSTUFF

100

1% 1/20W MF 201

2

1

R1371

PLACE_SIDE=BOTTOM

NOSTUFF

100

1%

1/20W

MF

201

PLACE_NEAR=U1000.G45:50.8mm

2

1

R1382

PLACE_NEAR=U1000.U10:50.8mm

201

MF

1/20W

1%

100

2

1

R1380

PLACE_SIDE=BOTTOM

PLACE_NEAR=U1000.BC43:50.8mm

100

1%

1/20W

MF

201

2

1

R1381

PLACE_SIDE=BOTTOM

PLACE_NEAR=U1000.BA43:50.8mm

201

1/20W

1%

100

MF

2

1

R1314

201

MF

5%

1/20W

10K

2

1

R1313

201

MF

5% 1/20W

10K

2

1

R1330

SM_VREF_EXT

5%

201

MF

1/20W

100

PLACE_NEAR=U1000.AY43:2.54mm

2

1

R1331

SM_VREF_EXT

100

1/20W

MF

201

5%

PLACE_NEAR=U1000.AY43:2.54mm

2

1

C1330

10% 16V X5R-CERM 0201

0.1UF

SM_VREF_EXT

PLACE_NEAR=U1000.AY43:2.54mm

2

1

R1362

PLACE_NEAR=U1000.AN16:50.8mm PLACE_SIDE=BOTTOM

201

MF

1/20W

1%

100

NOSTUFF

2

1

R1360

PLACE_NEAR=U1000.F43:50.8mm

NOSTUFF

100

1%

1/20W

MF

201

PLACE_SIDE=BOTTOM

2

1

R1361

100

1%

1/20W

MF

201

PLACE_NEAR=U1000.G43:50.8mm

PLACE_SIDE=BOTTOM

NOSTUFF

2

1

R1363

201

MF

1/20W

1%

100

NOSTUFF

PLACE_SIDE=BOTTOM

PLACE_NEAR=U1000.AN17:50.8mm

SYNC_DATE=12/13/2010

CPU POWER

SYNC_MASTER=K21_MLB

CPU_AXG_SENSE_N

=PP1V8_S0_CPU_VCCPLL_R

CPU_AXG_SENSE_P

=PP3V3_S0_CPU_VCCIO_SEL

=PP1V05_S0_CPU_VCCIO

CPU_VCCSENSE_N

CPU_VCCIOSENSE_N

=PPVCORE_S0_CPU

CPU_VCCSENSE_P

CPU_VCCIOSENSE_P

=PP1V05_S0_CPU_VCCIO

=PPVCORE_S0_CPU_VCCAXG

CPU_DDR_VREF

VOLTAGE=0.75V

CPU_DDR_VREF

=PP1V5_S3_CPU_VCCDDR

CPU_VCCSA_VID<0> CPU_VCCSA_VID<1>

CPU_VDDQ_SENSE_N

=PP1V5_S3_CPU_VCCDDR

CPU_VDDQ_SENSE_P

CPU_VCCSASENSE

=PPVCCSA_S0_CPU

=PP1V05_S0_CPU_VCCIO

CPU_VIDALERT_L

CPU_VIDALERT_L_R

CPU_VIDSOUT

CPU_VIDSCLK

CPU_VCCIO_SEL

CPU_VIDSOUT_R

CPU_VIDSCLK_R

=PP1V05_S0_CPU_VCCPQE

=PP1V5_S3_CPU_VCCDQ

=PPVCCSA_S0_CPU

=PPVCORE_S0_CPU

=PP1V5_S3_CPU_VCCDDR

=PPVCORE_S0_CPU_VCCAXG

13 OF 109

2.5.0

051-8871

12 OF 74

7

14

7

7 9

12 14

7 9

10 12 14

7 9

12 15

12

7

10 12 15 26

7

10 12 15 26

7

12 15

7 9

10 12 14

7

14

7

15

7

12 15

7 9

12 14

7 9

12 15

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS

VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS

VSS

VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS

VSS_NCTF VSS_NCTF

VSS_NCTF

VSS_NCTF VSS_NCTF

(9 OF 9)

VSS

(8 OF 9)

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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REVISION

DRAWING NUMBER

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D

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SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Y59

Y58

Y47

Y4

W8

W46

W21

W18

W15

W13

V61

V20

U8

U13

T56

T55

T53

T52

T51

T50

T47

T1

R46

R4

R20

R17

P9

P59

P58

P21

P18

P16

P14

E61

E1

D59

C58

C3

BG57

BG5

BE58

BE4

BD59

BD3

BC61

A57

A5

N61

N56

N52

N51

N48

N47

N43

N40

N36

N33

N28

N25

N21

N17

N1

M6

M58

M4

M15

M11

L61

L48

L43

L38

L34

L30

L26

L22

L20

L16

K8

K51

K21

K11

J55

J49

J1

H58

H53

H4

H21

H17

H14

H10

G61

G6

G51

G48

F55

F40

F35

F29

F19

F15

F13

E40

E35

E3

E29

E25

D6

D58

D54

D50

D46

D43

D40

D4

D35

D29

D26

D22

D18

D14

D10

C40

C35

C29

BG53

BG49

BG45

BG41

BG37

BG28

BG24

BG21

BG17

BG13

U1000

OMIT_TABLE

CRITICAL

SANDY-BRIDGE

MOBILE-2C-35W

BGA

BG9

BE5

BD8

BD56

BD52

BD48

BD44

BD40

BD36

BD32

BD27

BD23

BD19

BD16

BD12

BC57

BC5

BC13

BB53

BA51

BA48

BA32

BA26

BA21

BA17

BA11

BA1

AY9

AY58

AY55

AY49

AY45

AY41

AY4

AY36

AY30

AY19

AY14

AW7

AW61

AW43

AW13

AV55

AV48

AV40

AV34

AV22

AV21

AV17

AU7

AU51

AU32

AU28

AU11

AU1

AT58

AT52

AT45

AT4

AT36

AT19

AT14

AR7

AR61

AR48

AR41

AR21

AR17

AR13

AP7

AP55

AP51

AP10

AN54

AN50

AN47

AN43

AN40

AN36

AN33

AN28

AN25

AN21

AN1

AM58

AM48

AM45

AM42

AM4

AM38

AM34

AM30

AM26

AM22

AM20

AM13

AL61

AL47

AL43

AL40

AL36

AL33

AL28

AL25

AL21

AL17

AL13

AL10

AK52

AK1

AJ7

AJ48

AJ45

AJ42

AJ38

AJ34

AJ30

AJ26

AJ22

AJ20

AJ16

AJ13

AH58

AH4

AG7

AG61

AG52

AG47

AG18

AG14

AG10

AF59

AF58

AF56

AF55

AF53

AF52

AF51

AF50

AF48

AF47

AF21

AF17

AF1

AE8

AE13

AD61

AD4

AD20

AD17

AC6

AC46

AC14

AC10

AB61

AB48

AB21

AB18

AB16

AA8

AA56

AA55

AA53

AA52

AA51

AA50

AA13

AA1

A9

A53

A49

A45

A40

A37

A33

A28

A25

A21

A17

A13

U1000

OMIT_TABLE

CRITICAL

MOBILE-2C-35W

SANDY-BRIDGE

BGA

CPU GROUNDS

14 OF 109

2.5.0

051-8871

13 OF 74

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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REVISION

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PAGE TITLE

C

A

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21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PLACEMENT_NOTE (C1640-C1645):

Intel recommendation (Section 6.5): 26x 1uF, 10x 10uF, 2x 330uF

CPU VCCIO/VCCPQ DECOUPLING

PLACEMENT_NOTE (C1655-C1666):

CPU VCCPLL Low pass filter

Processor Load Line : -2.9 mOhms

Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

Note:The smallest 10mOhm available in the library are 0805s

PLACEMENT_NOTE (C1667-C1679):

Intel recommendation (Table 7-1): 16x 2.2uF, 12x 22uF, 3x 330uF

CPU VCORE DECOUPLING

PLACEMENT_NOTE (C1646-C1671):

Intel recommendation (section 6.4): 2x 1uF, 1x 330uF

CPU VCCPLL DECOUPLING

PLACEMENT_NOTE (C1672-C1681):

PLACEMENT_NOTE (C1684-C167F):

All INTEL recommendations from Intel doc #4439028 Huron River Platform Power Design Guide

21

R1601

0.010

MF

0603

1%

1/4W

2

1

C160Y

PLACE_NEAR=U1000.BC1:2.54 mm:NO_VIA

1UF

X5R 402

10% 10V

2

1

C1607

2.2UF

X5R 402

4V

20%

CRITICAL

2

1

C1608

CRITICAL

2.2UF

X5R 402

4V

20%

2

1

C1609

CRITICAL

2.2UF

X5R 402

20% 4V

2

1

C1610

CRITICAL

2.2UF

X5R 402

20% 4V

2

1

C1698

X5R 402

10% 10V

1UF

2

1

C1611

CRITICAL

2.2UF

402

20% 4V X5R

2

1

C1612

CRITICAL

2.2UF

402

20% 4V X5R

2

1

C1613

CRITICAL

2.2UF

402

20% 4V X5R

2

1

C1614

CRITICAL

2.2UF

402

20% 4V X5R

2

1

C1615

CRITICAL

2.2UF

402

20% 4V X5R

2

1

C1699

1UF

X5R 402

10% 10V

2

1

C161E

10UF

6.3V

20%

Place near U1000 on bottom side

CERM-X5R 0402-1

2

1

C162A

Place near U1000 on bottom side

10UF

CERM-X5R 0402-1

20%

6.3V 2

1

C162B

Place near U1000 on bottom side

10UF

CERM-X5R 0402-1

20%

6.3V 2

1

C162C

Place near U1000 on bottom side

10UF

CERM-X5R 0402-1

20%

6.3V 2

1

C162D

Place near U1000 on bottom side

10UF

CERM-X5R 0402-1

20%

6.3V

2

1

C169A

1UF

X5R 402

10% 10V

2

1

C162E

Place near U1000 on bottom side

10UF

CERM-X5R 0402-1

20%

6.3V 2

1

C167A

Place near U1000 on bottom side

10UF

CERM-X5R 0402-1

20%

6.3V 2

1

C167B

Place near U1000 on bottom side

10UF

CERM-X5R 0402-1

20%

6.3V 2

1

C167C

Place near U1000 on bottom side

10UF

CERM-X5R 0402-1

20%

6.3V

2

1

C167D

20% 2V

CASE-B2-SM

TANT

270UF

2

1

C1680

2V CASE-B2-SM

TANT

20%

270UF

2

1

C169B

1UF

X5R 402

10% 10V

2

1

C1657

X5R 402

4V

20%

22UF

CRITICAL

2

1

C1658

X5R

4V

20%

402

22UF

CRITICAL

2

1

C1659

CRITICAL

4V

20%

402

X5R

22UF

2

1

C1660

4V

20%

402

X5R

22UF

CRITICAL

2

1

C1661

4V

20%

402

X5R

22UF

CRITICAL

2

1

C1662

20% 4V

402

X5R

22UF

CRITICAL

2

1

C1663

4V

20%

402

X5R

22UF

CRITICAL

2

1

C1664

20% 4V

402

X5R

22UF

CRITICAL

2

1

C1665

4V

20%

402

X5R

22UF

CRITICAL

2

1

C1666

X5R

4V

20%

402

22UF

CRITICAL

2

1

C1681

20%

CASE-B2-SM

270UF

2V TANT

2

1

C1682

TANT

20% 2V

CASE-B2-SM

270UF

2

1

C1683

CASE-B2-SM

2V

20% TANT

270UF

2

1

C167E

270UF

TANT CASE-B2-SM

20% 2V

2

1

C167G

270UF

TANT CASE-B2-SM

20% 2V

2

1

C167H

270UF

TANT CASE-B2-SM

20% 2V

2

1

C160Z

2V

20% TANT

PLACE_NEAR=U1000.BC2:5mm

CASE-B2-SM

270UF

2

1

C1679

CASE-B2-SM

2V

20% TANT

270UF

2

1

C169C

1UF

X5R 402

10% 10V

2

1

C1684

X5R

10% 10V

402

1UF

Place on bottom side of U1000

2

1

C1685

Place on bottom side of U100.

1UF

X5R 402

10% 10V

2

1

C1686

Place on bottom side of U1000

X5R 402

10% 10V

1UF

2

1

C1655

CRITICAL

4V

20%

402

X5R

22UF

Place close to U1000 on top side.

2

1

C1656

22UF

4V

20%

402

X5R

CRITICAL

2

1

C1687

Place on bottom side of U1000

1UF

X5R 402

10% 10V

2

1

C1688

1UF

X5R 402

10% 10V

2

1

C1689

1UF

X5R 402

10% 10V

2

1

C167F

1UF

X5R 402

10% 10V

2

1

C1600

2.2UF

X5R

20% 4V

402

CRITICAL

2

1

C1601

2.2UF

X5R

20% 4V

402

CRITICAL

2

1

C1602

2.2UF

20% 4V

402

X5R

CRITICAL

2

1

C1603

402

20% X5R

4V

CRITICAL

2.2UF

2

1

C1604

X5R

4V

20%

402

2.2UF

CRITICAL

2

1

C1605

X5R 402

4V

20%

CRITICAL

2.2UF

2

1

C1606

CRITICAL

2.2UF

402

20% X5R

4V

2

1

C169D

1UF

X5R 402

10% 10V

2

1

C169E

1UF

X5R 402

10% 10V

2

1

C169F

1UF

X5R 402

10% 10V

2

1

C161A

1UF

X5R 402

10% 10V

2

1

C161B

1UF

X5R 402

10% 10V

2

1

C161C

1UF

X5R 402

10% 10V

2

1

C161D

1UF

X5R 402

10% 10V

2

1

C1690

1UF

X5R 402

10% 10V

2

1

C1691

1UF

X5R 402

10% 10V

2

1

C1692

1UF

X5R 402

10% 10V

2

1

C1693

1UF

X5R 402

10% 10V

2

1

C1697

1UF

X5R 402

10% 10V

2

1

C1694

1UF

X5R 402

10% 10V

2

1

C1695

1UF

X5R 402

10% 10V

2

1

C1696

1UF

X5R 402

10% 10V

2

1

C161F

Place near U1000 on bottom side

10UF

CERM-X5R

20%

6.3V 0402-1

21

R1600

0

402

5%

MF-LF

1/16W

2

1

C160X

PLACE_NEAR=U1000.BB3:2.54 mm:NO_VIA

1UF

X5R 402

10% 10V

Place near U1000 on top side

CPU DECOUPLING-I

SYNC_MASTER=K21_MLB

SYNC_DATE=12/13/2010

=PP1V05_S0_CPU_VCCIO

=PPVCORE_S0_CPU

=PP1V05_S0_CPU_VCCPQE

=PP1V8_S0_CPU_VCCPLL

=PP1V8_S0_CPU_VCCPLL_R

16 OF 109

2.5.0

051-8871

14 OF 74

7 9

10 12

7 9

12

7

12

7

12

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Intel recommendation (Section 6.6): 3x 1uf, 3x 10uf, 1x 330uf

Intel recommendation (section 6.3): 18x 1uF(9 no-stuff), 10x 104F(2 no-stuff), 8x 22uF(2 no stuff), 4x 470uF(2 no-stuff)

VAXG DECOUPLING

PLACEMENT_NOTE (C1700-C1710):

Graphics Load Line : -3.9 mOhms

PLACEMENT_NOTE (C1717-C1722):

PLACEMENT_NOTE (C1711-C1716):

PLACEMENT_NOTE (C1738-C1747):

PLACEMENT_NOTE (C1758-C1762):

CPU VCCSA DECOUPLING

Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

Intel recommendation (Section 6.13): 10x 1uF, 8x 10uF, 1x 330uF

CPU VDDQ/VCCDQ DECOUPLING

PLACEMENT_NOTE (C1723-C1724):

21

R1702

0603

0.010

1%

1/4W

MF

2

1

C1740

Place on bottom side of U1000

402

X5R

10V

10%

1UF

2

1

C1756

CASE-B2-SM

270UF

TANT

20% 2V

2

1

C1768

CASE-B2-SM

20% 2V TANT

270UF

2

1

C1711

CRITICAL

10UF

0402-1

CERM-X5R

6.3V

20%

2

1

C1712

CRITICAL

10UF

20%

6.3V

0402-1

CERM-X5R

2

1

C1713

CRITICAL

6.3V

10UF

20%

0402-1

CERM-X5R

2

1

C1714

CRITICAL

10UF

CERM-X5R

20%

0402-1

6.3V

2

1

C1715

CRITICAL

10UF

CERM-X5R

6.3V

20%

0402-1

2

1

C1716

CRITICAL

0402-1

20%

6.3V

CERM-X5R

10UF

2

1

C1748

Place close to U1000 on bottom side

10UF

20%

CERM-X5R

6.3V

0402-1

2

1

C1717

6.3V

22UF

20%

CRITICAL

X5R-CERM1 0603

2

1

C1749

6.3V

Place close to U1000 on bottom side

10UF

CERM-X5R

20%

0402-1

2

1

C1751

0402-1

20%

6.3V

CERM-X5R

10UF

Place close to U1000 on bottom side

2

1

C1752

Place close to U1000 on bottom side

10UF

CERM-X5R

6.3V

20%

0402-1

2

1

C1753

0402-1

20%

6.3V

CERM-X5R

10UF

Place close to U1000 on bottom side

2

1

C1755

Place close to U1000 on bottom side

10UF

CERM-X5R

6.3V

20%

0402-1

2

1

C1763

10UF

CERM-X5R

6.3V

20%

0402-1

2

1

C1764

0402-1

10UF

CERM-X5R

6.3V

20%

2

1

C1765

10UF

CERM-X5R

6.3V

20%

0402-1

2

1

C1718

20%

6.3V

22UF

CRITICAL

X5R-CERM1 0603

2

1

C1766

10UF

CERM-X5R

6.3V

20%

0402-1

2

1

C1767

0402-1

20%

6.3V

CERM-X5R

10UF

2

1

C1723

270UF

20% 2V TANT CASE-B2-SM

2

1

C1724

270UF

20% 2V TANT CASE-B2-SM

2

1

C1725

270UF

20% 2V TANT CASE-B2-SM

2

1

C1754

Place close to U1000 on bottom side

10UF

CERM-X5R

6.3V

20%

0402-1

2

1

C1750

6.3V

20%

Place close to U1000 on bottom side

10UF

CERM-X5R

0402-1

2

1

C1719

22UF

20%

6.3V

CRITICAL

X5R-CERM1 0603

2

1

C1741

10V

10%

1UF

402

X5R

Place on bottom side of U1000

2

1

C1742

1UF

X5R 402

10% 10V

2

1

C1743

10V

402

1UF

10%

X5R

2

1

C1744

X5R

1UF

10% 10V

402

2

1

C1720

22UF

20%

6.3V

CRITICAL

X5R-CERM1 0603

2

1

C1721

22UF

20%

6.3V

CRITICAL

X5R-CERM1 0603

2

1

C1722

22UF

20%

6.3V

CRITICAL

X5R-CERM1 0603

2

1

C1745

1UF

402

10V X5R

10%

2

1

C1746

10% 10V X5R

1UF

402

2

1

C1747

1UF

10%

X5R 402

10V

2

1

C1700

Place on bottom side of U1000

402

CRITICAL

10V X5R

10%

1UF

2

1

C1701

1UF

10%

CRITICAL

402

10V

Place on bottom side of U100.

X5R

2

1

C1702

CRITICAL

X5R 402

10V

10%

1UF

Place on bottom side of U1000

2

1

C1704

CRITICAL

1UF

402

10%

X5R

10V

2

1

C1705

1UF

CRITICAL

10% 10V

402

X5R

2

1

C1706

CRITICAL

10V

10%

1UF

X5R 402

2

1

C1757

X5R

10%

10V

402

1UF

2

1

C1707

402

CRITICAL

1UF

10% 10V X5R

2

1

C1708

CRITICAL

1UF

402

X5R

10V

10%

2

1

C1709

CRITICAL

1UF

10% 10V X5R 402

2

1

C1758

402

10V

10%

1UF

Place on bottom side of U1000

X5R

2

1

C1759

1UF

Place on bottom side of U100.

10V

402

X5R

10%

2

1

C1760

Place on bottom side of U1000

402

10V

10%

1UF

X5R

2

1

C1761

1UF

Place on bottom side of U1000

10V

402

10%

X5R

2

1

C1762

402

1UF

10%

X5R

10V

2

1

C1710

CRITICAL

1UF

402

X5R

10% 10V

2

1

C1703

CRITICAL

10V

10%

402

1UF

X5R

Place on bottom side of U1000

2

1

C1738

1UF

10V

Place on bottom side of U1000

10%

X5R 402

2

1

C1739

1UF

402

X5R

Place on bottom side of U100.

10V

10%

SYNC_MASTER=K21_MLB

CPU DECOUPLING-II

SYNC_DATE=12/13/2010

=PP1V5_S3_CPU_VCCDQ

=PPVCCSA_S0_CPU

=PP1V5_S3_CPU_VCCDDR

=PPVCORE_S0_CPU_VCCAXG

17 OF 109

2.5.0

051-8871

15 OF 74

7

12

7

12

7

10 12 26

7 9

12

IN

OUT

IN

BI

IN

OUT

IN

OUT

IN

OUT

BI

OUT

BI

IN

OUT

BI

IN

OUT

IN

OUT

NC

IN

OUT

SRTCRST*

SATA1RXN

SATA0TXP

SATA0TXN

SATA2RXN SATA2RXP

SATA5RXP

SATA0RXP

LDRQ0*

RTCRST*

INTRUDER*

INTVRMEN

HDA_BCLK

HDA_SYNC

HDA_RST*

SPKR

HDA_SDIN0 HDA_SDIN1

HDA_SDIN3

HDA_SDIN2

HDA_SDO

HDA_DOCK_EN*/GPIO33 HDA_DOCK_RST*/GPIO13

JTAG_TCK

JTAG_TMS

JTAG_TDI

JTAG_TDO

SPI_CS0*

SPI_CLK

SPI_CS1*

SPI_MOSI

SPI_MISO

FWH0/LAD0

RTCX1 RTCX2

SATA1TXP

SATA0RXN

SERIRQ

LDRQ1*/GPIO23

FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

FWH4/LFRAME*

SATA1RXP SATA1TXN

SATA2TXN SATA2TXP

SATA3RXN SATA3RXP SATA3TXN SATA3TXP

SATA4RXN SATA4RXP SATA4TXN SATA4TXP

SATA5RXN

SATA5TXN SATA5TXP

SATAICOMPO SATAICOMPI

SATALED*

SATA0GP/GPIO21 SATA1GP/GPIO19

SATA3COMPI

SATA3RCOMP0

SATA3RBIAS

RTC

IHDA

JTAG

SPI

SATA

LPC

(1 OF 10)

SMBDATA

SML0CLK

SML0ALERT*/GPIO60

SML0DATA

SML1ALERT*/PCHHOT*/GPIO74

SML1CLK/GPIO58

SML1DATA/GPIO75

PETP1

PERP2

PERN2

PERP3 PETN3

PERN4

PETP3

PERP4 PETN4

PERN5

PETP4

PERP5 PETN5 PETP5

PERN6 PERP6

PETP6

PETN6

PERN7 PERP7 PETN7

PERN8

PETP7

PETN8

PERP8

PETP8

SMBALERT*/GPIO11

SMBCLK

PERN1

PETN1

CLKOUT_PCIE0P

CLKOUT_PCIE0N

PERP1

PETN2 PETP2

PERN3

PCIECLKRQ0*/GPIO73

CLKOUT_PCIE1N CLKOUT_PCIE1P

PCIECLKRQ1*/GPIO18

CLKOUT_PCIE2N CLKOUT_PCIE2P

PCIECLKRQ2*/GPIO20

CLKOUT_PCIE3P

CLKOUT_PCIE3N

PCIECLKRQ3*/GPIO25

CLKOUT_PCIE4N CLKOUT_PCIE4P

PCIECLKRQ4*/GPIO26

CLKOUT_PCIE5N CLKOUT_PCIE5P

PCIECLKRQ5*/GPIO44

CLKOUT_PEG_B_N CLKOUT_PEG_B_P

PEG_B_CLKRQ*/GPIO56

CLKOUT_PCIE6N CLKOUT_PCIE6P

PCIECLKRQ6*/GPIO45

CLKOUT_PCIE7N CLKOUT_PCIE7P

PCIECLKRQ7*/GPIO46

CLKOUT_ITPXDP_P

CLKOUT_ITPXDP_N

CL_DATA1

CL_CLK1

CL_RST1*

PEG_A_CLKRQ*/GPIO47

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_P

CLKOUT_DMI_N

CLKOUT_DP_N CLKOUT_DP_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_GND1_N CLKIN_GND1_P

CLKIN_DOT_96P

CLKIN_DOT_96N

CLKIN_SATA_P

CLKIN_SATA_N

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0/GPIO64

CLKOUTFLEX1/GPIO65

CLKOUTFLEX2/GPIO66

CLKOUTFLEX3/GPIO67

CLK

FLEX CLOCK

LINK

CNTRL

SMBUS

PCI-E*

(2 OF 10)

IN

OUT

IN

OUT

BI

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

1.5V -> 1.1V

DOES THIS NEED LENGTH MATCH???

PLACE THIS RESISTOR NEAR THE PCH PIN

(IPU)

TIE THEM TOGETHER VERY CLOSE TO PINS. PLACE THE RESISTOR LESS THAN 200MILS FROM THE PINS

Pullup needed for SPI_DESCRIPTOR_OVERRIDE_L? PD needed for BCM_MEDIA_SENSE?

25 69

6

39 69

42 69

6

40 42

37 68

6

36 69

6

36 69

6

36 69

6

36 69

10 66

8

69

8

69

8

25 68

43 69

8

43 69

16 33

16 36

16

8

69

8

69

16 35

16

23

33 69

25 69

8

68

8

68

8

68

8

68

19

A23

N1

W8

Y2

AB6

AB8

AD12

Y4

W10

AB10 AB12

AJ1

AJ3

AC1

AC3

AH6

AH8

AE1

AE3

AG1

AG3

AD6

AD8

AF10

AH4

AF12

AL1

AL3

AD2

AD4

AR1

AR3

AN8

AN6

R1

AU1

AU3

AN1

AN3

M2

C19

A19

F19

F37

H40

M15

M12

U12

M17

C21

K22

H37

K37

A35

C35

B36

D36

F35

M35

K35

H35

K40

C37

C39

A39

A37

U1800

OMIT_TABLE

COUGAR-POINT

MOBILE-SFF

FCBGA

W51

W49

AC49

C11

D12

C9

A9

K12

H22

F10

F17

H12

J49

BB40

BB37

BF37

BB35

BF35

BD33

AY33

AY30

AY40

AY37

BD37

AY35

BD35

BF33

BB33

BB30

BL43

BL41

BK40

BL39

BL37

BK36

BL35

BL33

BJ43

BJ41

BH40

BJ39

BJ37

BH36

BJ35

BJ33

C4

R8

H4

J3

K8

M19

B8

T4

U8

M4

J51

G49

D48

H50

AF42

AF40

AF46

AF44

W46

W44

AB46

AB44

AB42

AB40

Y50

Y48

AA51

AA49

AD42

AD40

AE51

AE49

AD50

AD48

AR10

AR12

AN12

AN10

AY24

BB24

AK6

AK8

E51

AY26

BB26

K24

M24

BF17

BD17

M8

J1

L3

U1800

FCBGA

MOBILE-SFF

COUGAR-POINT

OMIT_TABLE

16

2

1

R1876

10K

MF

201

5%

1/20W

21

R1811

33

MF

201

5%

1/20W

PLACE_NEAR=U1800.H37:1.27mm

21

R1810

PLACE_NEAR=U1800.H35:1.27mm

33

MF

201

5%

1/20W

21

R1813

33

MF

201

5%

1/20W

PLACE_NEAR=U1800.K37:1.27mm

21

R1812

33

MF

201

5%

1/20W

PLACE_NEAR=U1800.F35:1.27mm

2

1

R1842

1/20W

MF

5%

201

10K

2

1

R1834

10K

201

5%

1/20W

MF

2

1

R1844

10K

5%

1/20W

201

MF

2

1

R1833

NOSTUFF

10K

5%

201

MF

1/20W

2

1

R1847

MF

201

5%

1/20W

10K

2

1

R1849

10K

5%

NOSTUFF

1/20W

201

MF

2

1

R1845

MF

1/20W

5%

10K

201

2

1

R1846

10K

201

1/20W

5% MF

2

1

R1848

1/20W

201

MF

10K

5%

2

1

R1866

NOSTUFF

10K

MF

201

5%

1/20W

40

2

1

R1800

330K

5%

201

MF

1/20W

21

R1880

0

MF

201

5%

1/20W

NOSTUFF

PLACE_NEAR=R1813.1:2.54mm

2

1

R1853

10K

MF 201

5% 1/20W

2

1

R1855

1/20W

5%

201

MF

10K

2

1

R1854

1/20W

5%

201

MF

10K

21

R1888

NOSTUFF

0

MF

201

5%

1/20W

19 40

21

R1841

0

5%

1/20W

MF

201

NOSTUFF

21

R1840

0

5%

1/20W

MF

201

NOSTUFF

6

39 69

6

39 69

6

39 69

6

39 69

2

1

R1850

10K

MF

201

5%

1/20W

2

1

R1851

1/20W

5%

201

MF

10K

21

R1860

5%

1/20W

MF

201

33

6

40

42 69

6

40

42 69

21

R1864

201

MF

1/20W

5%

33

6

40

42 69

21

R1861

5%

1/20W

MF

201

33

6

40

42 69

21

R1862

201

MF

1/20W

5%

33

6

40

42 69

21

R1863

5%

1/20W

MF

201

33

2

1

R1820

10K

MF 201

5% 1/20W

2

1

R1830

MF

PLACE_NEAR=U1800.AB10:2.54mm

37.4

201

1%

1/20W

2

1

R1899

10K

MF

201

5%

1/20W

2

1

R1877

1/20W

5%

201

MF

4.7K

2

1

R1878

5%

1/20W

4.7K

201

MF

2

1

R1831

PLACE_NEAR=U1800.AF12:2.54mm

49.9

MF

201

1%

1/20W

2

1

R1832

PLACE_NEAR=U1800.AH4:2.54mm

750

MF

201

1%

1/20W

2

1

R1803

20K

MF 201

5% 1/20W

2

1

R1802

MF

5%

1/20W

20K

201

2

1

R1801

1M

MF 201

5% 1/20W

2

1

C1803

6.3V

20%

1.0UF

X5R 0201-MUR

2

1

C1802

6.3V X5R

0201-MUR

20%

1.0UF

2

1

R1871

201

MF

1/20W

5%

10K

2

1

R1870

10K

1/20W

MF

201

5%

21

R1885

1/20W

1%201 MF

604

PLACE_NEAR=U1800.W49:5.1mm

2

1

R1886

PLACE_NEAR=R1885.1:2.54mm

1K

MF 201

1% 1/20W

2

1

R1890

PLACE_NEAR=U1800.W49:2.54mm

90.9

MF

201

1%

1/20W

SYNC_DATE=12/13/2010

SYNC_MASTER=K21_MLB

PCH SATA/PCIE/CLK/LPC/SPI

PCH_INTVRMEN_L

PCH_INTRUDER_L

SPI_MOSI_R

PCH_SPKR

SMC_SCI_L

HDA_SYNC_R

TP_SATA_B_D2RN TP_SATA_B_D2RP

SATA_HDD_D2R_P

LPC_SERIRQ

TP_SATA_B_R2D_CP

PCH_SATA3RBIAS

PCH_SATA3COMP

PCH_SATAICOMP

SPI_MISO

PCIECLKRQ5_L_GPIO44

HDA_SDOUT_R

JTAG_T29_TMS ENET_MEDIA_SENSE

TP_SATA_F_D2RP TP_SATA_F_R2D_CN TP_SATA_F_R2D_CP

PCH_SATALED_L

TP_SATA_E_R2D_CP

TP_SATA_D_R2D_CN

PCH_SRTCRST_L

SATA_HDD_R2D_C_P

SATA_HDD_R2D_C_N

RTC_RESET_L

PCH_INTRUDER_L

PCH_INTVRMEN_L

HDA_BIT_CLK_R

HDA_SYNC_R

HDA_RST_R_L

HDA_SDIN0 TP_HDA_SDIN1 TP_HDA_SDIN2

XDP_PCH_TCK

SPI_CS0_R_L

SPI_CLK_R

SYSCLK_CLK32K_RTC

SATA_HDD_D2R_N

TP_SATA_E_D2RN TP_SATA_E_D2RP TP_SATA_E_R2D_CN

TP_SATA_F_D2RN

DP_AUXCH_ISOL SATARDRVR_EN

HDA_SDOUT_R

HDA_SYNC

HDA_BIT_CLK

HDA_SDOUT

HDA_RST_R_L

HDA_RST_L

ITPCPU_CLK100M_N

ITPXDP_CLK100M_P ITPCPU_CLK100M_P

HDA_SDOUT_R

TP_HDA_SDIN3

XDP_PCH_TMS

XDP_PCH_TDO

TP_SPI_CS1_L

HDA_BIT_CLK_R

TP_SATA_D_R2D_CP

TP_SATA_D_D2RP

=PP3V3_S0_PCH

=PP1V05_S0_PCH_VCCIO_SATA

ENET_MEDIA_SENSE

=PP1V05_S0_PCH

SPI_DESCRIPTOR_OVERRIDE_L

PCH_GPIO11

XDP_PCH_TDI

PCH_SRTCRST_L

=PP1V05_S0_PCH_VCCDIFFCLK

DP_AUXCH_ISOL

SATA_ODD_D2R_P SATA_ODD_R2D_C_N SATA_ODD_R2D_C_P

TP_SATA_D_D2RN

TP_SATA_B_R2D_CN

T29_PWR_EN_PCH

TP_LPC_DREQ0_L

TP_PCH_GPIO67_CLKOUTFLEX3

TP_PCH_GPIO66_CLKOUTFLEX2

TP_PCH_GPIO65_CLKOUTFLEX1

TP_PCH_GPIO64_CLKOUTFLEX0

PCH_XCLK_RCOMP

PCH_CLK33M_PCIIN

PCH_CLK100M_SATA_N PCH_CLK100M_SATA_P

PCH_CLK96M_DOT_N PCH_CLK96M_DOT_P

PCH_CLKIN_GNDP1

PCH_CLKIN_GNDN1

PCIE_CLK100M_PCH_P

PCIE_CLK100M_PCH_N

TP_PCH_CLKOUT_DPP

TP_PCH_CLKOUT_DPN

DMI_CLK100M_CPU_N DMI_CLK100M_CPU_P

PEG_CLK100M_P

PEG_CLK100M_N

PEG_CLKREQ_L

TP_CLINK_RESET_L

TP_CLINK_CLK

TP_CLINK_DATA

ITPXDP_CLK100M_N ITPXDP_CLK100M_P

PCH_GPIO46

TP_PCIE_CLK100M_PE7P

TP_PCIE_CLK100M_PE6P

TP_PCIE_CLK100M_PE6N

PEG_B_CLKRQ_L_GPIO56

TP_PCIE_CLK100M_PEBP

TP_PCIE_CLK100M_PEBN

PCIECLKRQ5_L_GPIO44

TP_PCIE_CLK100M_PE5P

TP_PCIE_CLK100M_PE5N

T29_CLKREQ_L

PCIE_CLK100M_T29_P

PCIE_CLK100M_T29_N

EXCARD_CLKREQ_L

PCIE_CLK100M_EXCARD_N PCIE_CLK100M_EXCARD_P

PCIECLKRQ2_L_GPIO20

TP_PCIE_CLK100M_PE2P

TP_PCIE_CLK100M_PE2N

AP_CLKREQ_L

PCIE_CLK100M_AP_P

PCIE_CLK100M_AP_N

PCIECLKRQ0_L_GPIO73

NC_PCIE_3_D2RN

PCIE_AP_R2D_C_P

PCIE_AP_R2D_C_N

NC_PCIE_1_D2RP

TP_PCIE_CLK100M_PE0N TP_PCIE_CLK100M_PE0P

NC_PCIE_1_R2D_CN

NC_PCIE_1_D2RN

SMBUS_PCH_CLK

PCH_GPIO11

NC_PCIE_8_R2D_CP

NC_PCIE_8_D2RP NC_PCIE_8_R2D_CN

NC_PCIE_7_R2D_CP

NC_PCIE_8_D2RN

NC_PCIE_7_R2D_CN

NC_PCIE_7_D2RP

NC_PCIE_7_D2RN

NC_PCIE_6_R2D_CN NC_PCIE_6_R2D_CP

NC_PCIE_6_D2RP

NC_PCIE_6_D2RN

NC_PCIE_5_R2D_CP

NC_PCIE_5_R2D_CN

NC_PCIE_5_D2RP

PCIE_EXCARD_R2D_C_P

NC_PCIE_5_D2RN

PCIE_EXCARD_R2D_C_N

PCIE_EXCARD_D2R_P

NC_PCIE_3_R2D_CP

PCIE_EXCARD_D2R_N

NC_PCIE_3_R2D_CN

NC_PCIE_3_D2RP

PCIE_AP_D2R_N PCIE_AP_D2R_P

NC_PCIE_1_R2D_CP

SML_PCH_1_DATA

SML_PCH_1_CLK

SML_PCH_1_ALERT_L

SML_PCH_0_DATA

SML_PCH_0_ALERT_L

SML_PCH_0_CLK

SMBUS_PCH_DATA

PCH_CLK14P3M_REFCLK

SYSCLK_CLK25M_SB_R

SYSCLK_CLK25M_SB

SML_PCH_0_ALERT_L

=PP3V3_SUS_GPIO

SML_PCH_1_ALERT_L

=PP3V3_S0_PCH_STRAPS

SATARDRVR_EN

PCIECLKRQ0_L_GPIO73

PEG_B_CLKRQ_L_GPIO56

=PPVRTC_G3_PCH

RTC_RESET_L

LPC_R_AD<0>

LPC_AD<0>

LPC_R_AD<1>

LPC_AD<1>

LPC_R_AD<2>

LPC_AD<2>

LPC_R_AD<3>

LPC_AD<3>

LPC_FRAME_R_L

LPC_FRAME_L

SATA_ODD_D2R_N

JTAG_T29_TMS PCH_SPKR AP_CLKREQ_L PCH_SATALED_L EXCARD_CLKREQ_L

=PP3V3_T29_PCH_GPIO

T29_CLKREQ_L PEG_CLKREQ_L

=PP3V3_S0_PCH_STRAPS

PCIECLKRQ2_L_GPIO20

WOL_EN

TP_PCIE_CLK100M_PE7N

ITPXDP_CLK100M_N

=PP3V3_SUS_GPIO

HDA_SYNC_R

=PP3V3R1V5_S0_PCH_VCCSUSHDA

HDA_SDOUT_R

18 OF 109

2.5.0

051-8871

16 OF 74

16

16 69

6

68

16

16 69

6

16

6

16

16 69

6

16 23 63

16 23

16 69

10 66

16 23 66 10 66

16 69

6

16 69

6

7

19 22

7

20 22

16

7

22

16

7

20 22

16 23 63

6

16 23 66

19

6

16

6

16

6

16

69

16

7

16 17 18 19

16

7

16 17 19

16 23

16

7

17 20

16

16 33

16

16 36

16

7

19

16 35

16

7

16 17 19

16

19

6

16 23 66

7

16 17 18 19

16 69

7

20 22

16 69

IN

OUT

IN

BI

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

ACPRESENT/GPIO31

SUSWARN*/SUSPWRDNACK/GPIO30

DPWROK

DMI3RXP

DMI2RXP

DMI1RXP

DMI0RXP

RSMRST*

APWROK

PWRBTN*

SLP_S3*

DMI_IRCOMP

DMI0TXN

DMI2RXN

DRAMPWROK

FDI_RXN6 FDI_RXN7

FDI_RXP0

FDI_RXP3

FDI_RXP1 FDI_RXP2

FDI_RXP5

FDI_RXP4

FDI_RXP7

FDI_INT

FDI_FSYNC0

FDI_LSYNC0

FDI_FSYNC1

FDI_LSYNC1

WAKE*

CLKRUN*/GPIO32

SUSCLK/GPIO62

SUS_STAT*/GPIO61

SLP_S5*/GPIO63

SLP_S4*

SLP_A*

SLP_LAN*/GPIO29

PMSYNCH

DSWVRMEN

SLP_SUS*

SUSACK*

DMI2TXN

DMI1TXN

DMI0TXP

DMI3TXN

DMI1TXP DMI2TXP DMI3TXP

DMI_ZCOMP

SYS_RESET*

SYS_PWROK

PWROK

BATLOW*/GPIO72

RI*

FDI_RXN0 FDI_RXN1

FDI_RXN3

FDI_RXN2

FDI_RXN4 FDI_RXN5

DMI0RXN

DMI3RXN

FDI_RXP6

DMI2RBIAS

DMI1RXN

FDI

DMI

SYSTEM POWER

MANAGEMENT

(3 OF 10)

L_VDD_EN

L_DDC_DATA

L_DDC_CLK

L_CTRL_DATA

L_CTRL_CLK

L_BKLTEN

L_BKLTCTL

LVD_VREFL

LVD_VREFH

LVD_VBG

LVD_IBG

LVDSB_DATA_3*

LVDSB_DATA_2*

LVDSB_DATA_1*

LVDSB_DATA_0*

LVDSB_DATA3

LVDSB_DATA2

LVDSB_DATA1

LVDSB_DATA0

LVDSB_CLK* LVDSB_CLK

LVDSA_DATA_3*

LVDSA_DATA_2*

LVDSA_DATA_1*

LVDSA_DATA_0*

LVDSA_DATA3

LVDSA_DATA2

LVDSA_DATA1

LVDSA_DATA0

LVDSA_CLK* LVDSA_CLK

SDVO_TVCLKINP

SDVO_TVCLKINN

SDVO_STALLP

SDVO_STALLN

SDVO_INTP

SDVO_INTN

SDVO_CTRLDATA

SDVO_CTRLCLK

DDPB_AUXN DDPB_AUXP

DDPB_0N

DDPB_HPD

DDPB_0P DDPB_1N DDPB_1P

DDPB_2P

DDPB_2N

DDPB_3N DDPB_3P

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN DDPC_AUXP

DDPC_HPD

DDPC_0N

DDPC_1P

DDPC_0P DDPC_1N

DDPC_2P

DDPC_2N

DDPC_3P

DDPC_3N

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXP

DDPD_AUXN

DDPD_HPD

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N

DDPD_3N

DDPD_2P

DDPD_3P

CRT_BLUE CRT_GREEN CRT_RED

CRT_DDC_CLK CRT_DDC_DATA

CRT_HSYNC

DAC_IREF

CRT_VSYNC

CRT_IRTN

LVDS

CRT

DIGITAL DISPLAY INTERFACE

(4 OF 10)

NC NC

NC

NC NC NC NC

NC

NC NC

OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Set to Vcc when High

.

DF_TVS:DMI & FDI Term Voltage

Set to Vss when Low

9

66

9

66

9

66

9

66

9

66

9

66

6

17 36

6

17 40 42

41

40 61

26 40 48 61

26 40 61

10 26 66

61

17 23 40

17 41

25

40

23 25

25 40

9

66

9

66

9

66

9

66

9

66

9

66

9

66

9

66

9

66

9

66

9

66

9

66

9

66

9

66

9

66

10 66

6

40 42

40 41 61

17

19 25

17

D8L1

M10

C13

D3

F15

G6

A15

F6

K10

D4

A7

C7

B20

F12

M22

K19

BB8

BD10

BL9

BB12

BB15

BL11

BF12

BL15

BJ13

BF10

BJ9

AY12

AY15

BJ11

BD12

BJ15

BL13

BH8

BK12

BB10

BK8

BH12

F22

B12

A21

BF19 BD19

AY17

BB17

BJ17

BL17

AY19

BB19

BL19

BJ19

BK20

AY22

BB22

BJ23

BL23

BF22

BD22

BJ21

BL21

T2

H10

G3

H19

U1800

OMIT_TABLE

COUGAR-POINT

MOBILE-SFF

FCBGA

AU42

AU40

AR49

AR51

AT48

AT50

R44

W42

AH50

AJ51

AL49

AM50

AH48

AJ49

AL51

AM48

AH46 AH44

AK40

AN44

AN49

AR46

AK42

AN46

AN51

AR44

AK44 AK46

AG49

AG51

AH40

AH42

M42

K46

L51

M40

R42

M44

L49

BK44

U42

M48

AU44

AU46

BJ45

BL45

BL47

BJ47

BD42

BF42

BG49

BG51

BE46

U44

T50

AU49

AU51

BE51

BE49

BF45

BF46

BD50

BD48

BC51

BC49

AY42

AW49

AW51

BA51

BA49

BB46

BB44

AY46

AY44

AY50

AY48

R51

N51

U46

T48

M50

R46

N49

R49

M46

U1800

OMIT_TABLE

COUGAR-POINT

MOBILE-SFF

FCBGA

21

R1986

0

MF

201

5%

1/20W

2

1

R1984

10K

MF

201

5%

1/20W

NOSTUFF

2

1

R1925

201

1K

1/20W

1% MF

2

1

R1985

1K

MF 201

1% 1/20W

2

1

R1905

10K

MF

201

5%

1/20W

2

1

R1900

PLACE_NEAR=U1800.BF19:12.7mm

49.9

MF 201

1% 1/20W

2

1

R1920

750

MF 201

1% 1/20W

PLACE_NEAR=U1800.BK20:2.54mm

2

1

R1909

100K

MF 201

5% 1/20W

2

1

R1915

390K

MF

201

5%

1/20W

2

1

R1983

1/20W

5%

201

MF

10K

2

1

R1982

MF

201

1/20W

10K

5%

2

1

R1991

MF

1/20W

5%

8.2K

201

2

1

R1951

PLACE_NEAR=U1800.R51:2.54mm

1K

MF 201

5% 1/20W

8

2

1

R1955

201

1/20W

100K

5% MF

63

PCH DMI/FDI/GRAPHICS

TP_DP_IG_D_MLP<1>

FDI_DATA_N<5>

FDI_DATA_N<4>

FDI_DATA_N<3>

PM_CLKRUN_L

PM_PWRBTN_L

PM_SLP_SUS_L

PCH_DSWVRMEN

=PP3V3_S0_PCH_STRAPS

PCH_DMI_COMP

=PP1V05_S0_PCH_VCCIO_PCIE

=T29_WAKE_L

MAKE_BASE=TRUE

PCIE_WAKE_L

PCH_SUSACK_L

FDI_FSYNC<0>

FDI_LSYNC<0> FDI_LSYNC<1>

PM_CLKRUN_L

PM_CLK32K_SUSCLK_R

PM_SLP_S5_L

PM_SLP_S4_L

PCH_SUSACK_L

FDI_DATA_P<1>

LVDS_IG_BKL_PWM

PM_PCH_SYS_PWROK

FDI_DATA_P<4> FDI_DATA_P<5> FDI_DATA_P<6>

FDI_INT

FDI_DATA_P<2>

TP_SDVO_TVCLKINP

TP_SDVO_TVCLKINN

TP_SDVO_STALLP

TP_SDVO_STALLN

TP_SDVO_INTP

TP_SDVO_INTN

DP_IG_B_DDC_DATA

DP_IG_B_DDC_CLK

DP_IG_B_AUX_N DP_IG_B_AUX_P

TP_DP_IG_B_MLN<0>

DP_IG_B_HPD

TP_DP_IG_B_MLP<0> TP_DP_IG_B_MLN<1> TP_DP_IG_B_MLP<1>

TP_DP_IG_B_MLP<2>

TP_DP_IG_B_MLN<2>

TP_DP_IG_B_MLN<3> TP_DP_IG_B_MLP<3>

TP_DP_IG_C_CTRL_CLK TP_DP_IG_C_CTRL_DATA

TP_DP_IG_C_AUXN TP_DP_IG_C_AUXP TP_DP_IG_C_HPD

TP_DP_IG_C_MLN<0>

TP_DP_IG_C_MLP<1>

TP_DP_IG_C_MLP<0> TP_DP_IG_C_MLN<1>

TP_DP_IG_C_MLP<2>

TP_DP_IG_C_MLN<2>

TP_DP_IG_C_MLP<3>

TP_DP_IG_C_MLN<3>

TP_DP_IG_D_CTRL_CLK TP_DP_IG_D_CTRL_DATA

TP_DP_IG_D_AUXP

TP_DP_IG_D_AUXN

TP_DP_IG_D_HPD

TP_DP_IG_D_MLN<0> TP_DP_IG_D_MLP<0> TP_DP_IG_D_MLN<1>

TP_DP_IG_D_MLN<2>

TP_DP_IG_D_MLN<3>

TP_DP_IG_D_MLP<2>

TP_DP_IG_D_MLP<3>

TP_CRT_IG_BLUE TP_CRT_IG_GREEN TP_CRT_IG_RED

TP_CRT_IG_DDC_CLK TP_CRT_IG_DDC_DATA

TP_CRT_IG_HSYNC

PCH_DAC_IREF

TP_CRT_IG_VSYNC

=PPVRTC_G3_PCH

FDI_FSYNC<1>

LPC_PWRDWN_L

PM_DSW_PWRGD

PM_BATLOW_L

PCH_DMI2RBIAS

PM_SYNC

GPIO29_SLP_LAN_L

FDI_DATA_P<7>

FDI_DATA_P<3>

FDI_DATA_N<2>

FDI_DATA_N<1>

FDI_DATA_N<0>

FDI_DATA_N<7>

FDI_DATA_N<6>

FDI_DATA_P<0>

SMC_ADAPTER_EN

PCH_SUSWARN_L

DMI_N2S_P<2>

DMI_N2S_P<1>

DMI_N2S_P<0>

PM_RSMRST_L

PM_PCH_APWROK

PM_PWRBTN_L

DMI_N2S_N<2>

PM_MEM_PWRGD

DMI_S2N_N<2>

DMI_S2N_P<0>

DMI_S2N_N<3>

PM_SYSRST_L

PM_PCH_PWROK

DMI_N2S_N<0>

DMI_N2S_N<3>

DMI_N2S_N<1>

=PP3V3_S5_PCH

LVDS_IG_BKL_ON LVDS_IG_PANEL_PWR

TP_PM_SLP_A_L

PM_SLP_S3_L

DMI_S2N_P<2>

DMI_S2N_P<1>

PCH_RI_L

DMI_N2S_P<3>

DMI_S2N_N<0> DMI_S2N_N<1>

DMI_S2N_P<3>

=PP3V3_SUS_GPIO

GPIO29_SLP_LAN_L PM_BATLOW_L

=PP3V3_SUS_GPIO

PCH_SUSWARN_L

=PP3V3_SUS_GPIO

PCIE_WAKE_L

PCH_SUSWARN_L

19 OF 109

2.5.0

051-8871

17 OF 74

9

66

9

66

9

66

6

17 40 42

17 23 40

61

7

16 19

17

9

66

9

66

9

66

9

66

9

66

6

8

6

7

16 20

17

9

66

9

66

9

66

9

66

9

66

9

66

9

66

9

66

7

19

7

16 17 18 19

17

17 41

7

16 17 18 19

17

7

16 17 18 19

6

17 36

17

IN

BI

IN

TP20

TP19

TP18

TP17

TP16

TP15

TP14

TP13

TP12

TP11

TP10

TP9

TP8

TP7

TP6

TP5

TP4

TP3

TP2

TP1

RSVD_BE3 RSVD_BE1 RSVD_AU8 RSVD_BJ7

RSVD_BH3

RSVD_BA3

RSVD_AU6

RSVD_AW1

RSVD_AW3

RSVD_AY6 RSVD_AY2 RSVD_AY4

RSVD_BC1

RSVD_BC3

RSVD_BG1 RSVD_BG3 RSVD_BE6

RSVD_BF7

RSVD_BH4

RSVD_BJ4 RSVD_BJ5 RSVD_BK6

DF_TVS

RSVD_AY8

RSVD_BL5

RSVD_BB6

RSVD_BD2 RSVD_BD4

RSVD_BF6

RSVD_BA1

USBP0N

USBP1N

USBP0P

USBP1P

USBP2N USBP2P

USBP3N USBP3P

USBP4N USBP4P

USBP5N USBP5P

USBP6N USBP6P

USBP7N USBP7P

USBP8N USBP8P

USBP9N USBP9P

USBP10N USBP10P

USBP11P

USBP11N

USBP12N USBP12P

USBP13P

USBP13N

USBRBIAS*

USBRBIAS

TP22

TP21

TP23 TP24 TP41 TP42

TP25 TP26 TP27 TP28 TP29

TP31

TP30

TP32 TP33 TP34 TP35 TP36 TP37 TP38

TP40

TP39

PIRQB*

PIRQA*

PIRQC*

REQ1*/GPIO50

PIRQD*

REQ2*/GPIO52 REQ3*/GPIO54

GNT1*/GPIO51 GNT2*/GPIO53

PIRQE*/GPIO2

GNT3*/GPIO55

PIRQH*/GPIO5

PIRQG*/GPIO4

PIRQF*/GPIO3

PME*

CLKOUT_PCI0

PLTRST*

CLKOUT_PCI2 CLKOUT_PCI3

CLKOUT_PCI1

CLKOUT_PCI4

OC1*/GPIO40

OC0*/GPIO59

OC2*/GPIO41 OC3*/GPIO42 OC4*/GPIO43

OC5*/GPIO9 OC6*/GPIO10 OC7*/GPIO14

TP

RSVD

PCI

USB

(5 OF 10)

NC NC

NC

NC NC

NC NC NC

NC

NC NC

NC

NC NC

NC

NC NC

NC NC NC NC

NC

NC NC

NC

NC NC

NC

BI

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

ON AP_PWR_EN IF ISOLATION RESISTOR R2090 IS UNSTUFFED

NOTE: PULLUP IS REQUIRED

FIXME: NEED INTEL APPROVAL OF NC ON TPS

PUs TO S0 INSTEAD?

USB HUB 1

Unused

USB HUB 2

Unused

Camera

Unused

6

39

6

39 68

6

39 68

63

6

39

C33 A33

A29

C29

K28

M28

B32

D32

F26

H26

B28

D28

K26

M26

F28

H28

A27

C27

A25

C25

K33

M33

F30

H30

F33

H33

A31

C31

H24

F24

AR42

AR40

AN40

AN42

BH16

BB42

BH49

BD30

BK16

BD28

AY28

BD26

BF30

BF28

BB28

BF26

BL29

BL31

BL27

BH20

BL25

BJ29

BJ31

BJ27

BJ25

K30

W40

BL7

BJ48

AD46

BK24

AD44

D24

B24

AD10

AT2

AT4

AM4

E3

M30

D20

BH24

BL5

BK6

BJ7

BJ5

BJ4

BH4

BH3

BG3

BG1

BF7

BF6

BE6

BE3 BE1

BD4

BD2

BC3 BC1

BB6

BA3

BA1

AY8

AY6

AY4

AY2

AW3 AW1

AU8

AU6

F46

K44

G46

H2

F7

F40

F45

C41

A47

C45

C47

C48

D49

H15

C23

B16

A11

D16

A13

A17

C17

D44

H42

F42

BC7

G45

J43

H48

E49

G51

U1800

FCBGA

MOBILE-SFF

COUGAR-POINT

OMIT_TABLE

2

1

R2054

1/20W

5%

201

MF

10K

NOSTUFF

2

1

R2053

1/20W

5%

201

MF

10K

NOSTUFF

2

1

R2052

10K

MF

201

5%

1/20W

NOSTUFF

2

1

R2068

10K

1/20W

5%

201

MF

2

1

R2069

1/20W

5%

201

MF

10K

2

1

R2065

1/20W

5%

201

MF

10K

2

1

R2067

1/20W

5%

201

MF

10K

2

1

R2064

5%

201

MF

10K

1/20W

2

1

R2062

1/20W

5%

201

MF

10K

2

1

R2061

1/20W

5%

201

MF

10K

2

1

R2060

1/20W

5%

201

MF

10K

2

1

R2081

1/20W

5%

201

MF

2.2K

2

1

R2070

1/20W

1%

201

MF

22.6

PLACE_NEAR=U1800.C33:2.54mm

21

R2015

NOSTUFF

1/20W

5%

10K

201 MF

2 1

R2031

1/20W

5% MF

10K

201

21

R2030

5%201 MF

10K

1/20W

21

R2018

1/20W

5%201 MF

10K

21

R2017

1/20W

5%201 MF

10K

21

R2016

1/20W

5%201 MF

10K

21

R2013

1/20W

5%201 MF

10K

21

R2012

1/20W

5%201 MF

10K

21

R2011

1/20W

5%201 MF

10K

21

R2010

1/20W

5%201 MF

10K

21

R2090

0

5%

MF

1/20W

201

21

R2080

201

5%

MF

1/20W

1K

24 68

25 26

25

25 69

25

SYNC_DATE=12/13/2010

PCH PCI/FLASHCACHE/USB

SYNC_MASTER=K21_MLB

PCH_GPIO59_OC0_L

USB_HUB_SOFT_RESET_L

ENET_PWR_EN

PCH_GPIO14_OC7_L

PCH_GPIO43_OC4_L SDCONN_STATE_CHANGE PCH_GPIO10_OC6_L

PCH_PCI_GNT1_L

PCH_PCI_GNT2_L

T29_MCU_INT_L

=PP3V3_S0_PCH_GPIO

=PP1V8_S0_PCH_VCC_DFTERM

CPU_PROC_SEL_L

PCH_DF_TVS

TP_PM_TEST_RST_L

USB_HUB1_UP_N

NC_USB_1N

USB_HUB1_UP_P

NC_USB_1P

NC_USB_2N NC_USB_2P

NC_USB_3N NC_USB_3P

NC_USB_4N NC_USB_4P

NC_USB_5N NC_USB_5P

NC_USB_6N NC_USB_6P

NC_USB_7N NC_USB_7P

USB_HUB2_UP_P

USB_CAMERA_N USB_CAMERA_P

NC_USB_10N NC_USB_10P

NC_USB_11P

NC_USB_11N

NC_USB_12N NC_USB_12P

NC_USB_13P

NC_USB_13N

PCH_USB_RBIAS

PCI_INTB_L

PCI_INTA_L

PCI_INTC_L

JTAG_GMUX_TMS

PCI_INTD_L

T29_A_HV_EN_L PCI_REQ3_L

PCH_PCI_GNT1_L PCH_PCI_GNT2_L

PCI_INTE_L

PCH_PCI_GNT3_L

AUD_I2C_INT_L

AUD_IP_PERIPHERAL_DET

TP_PCI_PME_L

LPC_CLK33M_SMC_R

PLT_RESET_L

TP_PCI_CLK33M_OUT2 TP_PCI_CLK33M_OUT3

LPC_CLK33M_LPCPLUS_R

PCH_CLK33M_PCIOUT

SDCONN_STATE_RST_L

USB_HUB2_UP_N

PCH_PCI_GNT3_L

=PP3V3_S3_PCH_GPIO

=PP3V3_SUS_GPIO

AP_PWR_EN

20 OF 109

2.5.0

051-8871

18 OF 74

23

23 24

23

18

7

68

18

6

23

18

7

19

7

16 17 19

36 61

OUT

BI

IN

OUT

IN

BI

IN

INIT3_3V*

PROCPWRGD THRMTRIP*

RCIN*

PECI

TACH1/GPIO1 TACH2/GPIO6

BMBUSY*/GPIO0

TACH7/GPIO71

TACH6/GPIO70

GPIO57

TACH4/GPIO68

SDATAOUT1/GPIO48 SATA5GP/GPIO49

SDATAOUT0/GPIO39

SLOAD/GPIO38

SATA2GP/GPIO36

GPIO35

GPIO28

GPIO27

SCLOCK/GPIO22 GPIO24/MEM_LED

TACH0/GPIO17

GPIO8 LAN_PHY_PWR_CTRL/GPIO12

TACH3/GPIO7

A20GATE

SATA4GP/GPIO16

GPIO15

STP_PCI*/GPIO34

TACH5/GPIO69

SATA3GP/GPIO37

VSS_NCTF_A4

VSS_NCTF_A48

VSS_NCTF_A5

VSS_NCTF_A49

VSS_NCTF_BH51

VSS_NCTF_A51 VSS_NCTF_BH1

VSS_NCTF_BJ3

VSS_NCTF_BJ1

VSS_NCTF_BJ49

VSS_NCTF_BL1

VSS_NCTF_BJ51

VSS_NCTF_BL3 VSS_NCTF_BL4

VSS_NCTF_BL48

VSS_NCTF_BL51

VSS_NCTF_BL49

VSS_NCTF_C3 VSS_NCTF_C49 VSS_NCTF_C51

VSS_NCTF_D51

VSS_NCTF_D1

VSS_NCTF_E1

TS_VSS1 TS_VSS2 TS_VSS3 TS_VSS4

NC_1

NCTF

GPIO

CPU

MISC

(6 OF 10)

Y

A

B

08

Y

A

B

08

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

GPIO[68:71] have 15K-45K internal PUs

ALL RSVD TPs NC-ed per INTEL approval

(IPU)

This has internal pull up and should not pulled low.

(NC-ed per Intel chklist)

(PU necessary?)

THIS SIGNAL IS INTENDED FOR FIRMWARE HUB AND WE ARE NOT USING IT.

(PUs necessary?)

(PU necessary?)

10 23 66

19 23 26

6

42

19 23

19

19 23

19

8

19 23

8

19

6

19 42 49

10 66

16 19 40

19 40 41

E1

D51

D1

C51

C49

C3

BL51

BL49

BL48

BL4

BL3

BL1

BJ51

BJ49

BJ3

BJ1

BH51

BH1

A51

A5

A49

A48

A4

AH10

AK12

AH12

AK10

BC9

A41

D40

A43

K42

A45

C43

B40

B44

R3

N3

U1

U10

W3

AA1

AA3

M6

W6

U6 AU10

AU12

U40

C5 R6

H17

K17

W12

G1

C15

K15

K6

W1 U3

U1800

OMIT_TABLE

COUGAR-POINT

MOBILE-SFF

FCBGA

2

1

R2186

10K

MF

201

5%

1/20W

2

1

R2185

10K

MF

201

5%

1/20W

2

1

R2184

1/20W

5%

201

MF

10K

2

1

R2115

1/20W

5%

201

MF

10K

2

1

R2114

10K

MF

201

5%

1/20W

2

1

R2172

1/20W

5%

201

MF

10K

DRAM_CFG3:H

2

1

R2173

MF

1/20W

5%

201

10K

DRAM_CFG2:H

2

1

R2174

1/20W

5%

201

MF

10K

DRAM_CFG1:H

2

1

R2160

10K

MF

201

5%

1/20W

2

1

R2175

10K

MF

201

5%

1/20W

DRAM_CFG0:H

2

1

R2113

1/20W

5%

201

MF

10K

2

1

R2112

10K

MF

201

5%

1/20W

2

1

R2194

1/20W

5%

201

MF

10K

2

1

R2193

1/20W

5%

201

MF

100K

2

1

R2192

10K

MF

201

5%

1/20W

2

1

R2191

1/20W

201

MF

10K

5%

2

1

R2130

NOSTUFF

1K

MF

201

5%

1/20W

2

1

R2197

NOSTUFF

10K

MF

201

5%

1/20W

2

1

R2110

NOSTUFF

10K

MF

201

5%

1/20W

2

1

R2196

1/20W

5%

201

MF

10K

2

1

R2198

1/20W

5%

201

MF

10K

2

1

R2111

1/20W

5% MF

20K

201

2

1

R2190

100K

5%

1/20W

MF

201

2

1

R2150

10K

MF

201

5%

1/20W

2

1

R2155

1/20W

5%

201

MF

10K

21

R2140

201MF1/20W

5%

0

21

R2156

1/20W

5%

201

MF

390

21

R2170

MF

201

5%

1/20W

NOSTUFF

43

2

1

R2199

1/20W

5%

201

MF

10K

2

1

R2165

201

1K

MF

1/20W

5%

DRAM_CFG0:L

2

1

R2164

201

5%

1/20W

MF

1K

DRAM_CFG1:L

2

1

R2163

DRAM_CFG2:L

201

1K

5% 1/20W MF

2

1

R2162

201

1K

MF

1/20W

5%

DRAM_CFG3:L

3

8

4

6

5

U2150

74LVC2G08GT

SOT833

7

8

4

2

1

U2150

74LVC2G08GT

SOT833

16

19 23

35

6

39

2

1

C2152

0.1UF

10%

0201

X5R-CERM

16V

2

1

R2195

NOSTUFF

10K

201

MF

5%

1/20W

21

R2152

0

201

5%

MF

1/20W

PCH MISC

SYNC_MASTER=K21_MLB

SYNC_DATE=12/13/2010

MLB_RAM_CFG1

T29_PWR_EN

AUD_IPHS_SWITCH_EN_PCH

AUD_IPHS_SWITCH_EN_PCH_R

MLB_RAM_CFG2

MLB_RAM_CFG3

MLB_RAM_CFG1

PCH_GPIO46

WOL_EN

=PP3V3_SUS_GPIO

ENET_LOW_PWR

T29_SW_RESET_L

PCH_INIT3V3_L

MLB_RAM_CFG2

PCH_GPIO12

FW_PWR_EN

MLB_RAM_CFG3

MLB_RAM_CFG0

SMC_IG_THROTTLE_L FW_PME_L

PCH_INIT3V3_L

T29_PWR_EN_PCH

SPIROM_USE_MLB

=PP3V3_S0_PCH

JTAG_ISP_TCK

PCH_GPIO36_SATA2GP

PCH_GPIO35

ENET_LOW_PWR

PM_PCH_PWROK

AUD_IPHS_SWITCH_EN

ISOLATE_CPU_MEM_L

ODD_PWR_EN_L

LPCPLUS_GPIO

AUD_IPHS_SWITCH_EN_PCH

PCH_GPIO15

NC_GPIO8

SMC_RUNTIME_SCI_L

GMUX_INT

PCH_GPIO12

=PP3V3_S5_PCH

=PP3V3_T29_PCH_GPIO

SMC_SCI_L

PCH_GPIO24

SMC_SCI_L

T29_SW_RESET_L

JTAG_ISP_TDO JTAG_ISP_TDI

=PP3V3_SUS_GPIO

ODD_PWR_EN_L

MLB_RAM_CFG3 MLB_RAM_CFG2 MLB_RAM_CFG1

=PP3V3_S0_PCH_STRAPS

MLB_RAM_CFG0

FW_PME_L

=PP3V3_S3_PCH_GPIO

=PP3V3_S0_PCH_STRAPS

SMC_RUNTIME_SCI_L

PM_THRMTRIP_L

CPU_PWRGD

PCH_PROCPWRGD PM_THRMTRIP_L_R

PCH_RCIN_L

PCH_PECI CPU_PECI

=PP3V3_S0_PCH

PCH_A20GATE

JTAG_ISP_TCK

GMUX_INT

SPIROM_USE_MLB

PCH_GPIO24

ISOLATE_CPU_MEM_L

JTAG_ISP_TDO

FW_PWR_EN

=PP3V3_S0_PCH_STRAPS

SMC_IG_THROTTLE_L

MLB_RAM_CFG0

PCH_GPIO36_SATA2GP

=PP3V3_T29_PCH_GPIO

JTAG_ISP_TDI

21 OF 109

2.5.0

051-8871

19 OF 74

19

16

7

16 17 18 19

19 23

19 35

19

7

16 19 22

19 23

23

19 23

17 19 25

23

19

7

17

7

16 19

16 19 40

19

19 35

8

19

7

16 17 18 19

19

7

16 17 19

19

7

18

7

16 17 19

19 40 41

41

7

16 19 22

8

19 23

19

6

19 42 49

19

19 23 26

8

19

7

16 17 19

19 23

19

19 23

7

16 19

8

19

NC

VCCTX_LVDS_AG37

VSSALVDS_AC33

VCCALVDS_AG33

VCCALVDS_AF33

VSSADAC

VCCADAC

VCCDFTERM_AL13

VCCDFTERM_AK15

VCCSPI

VCCDFTERM_AJ15

VCCDFTERM_AJ13

VCCDMI_AM23

VCCCLKDMI

VCCVRM_AW21

VCCVRM_AU21

VCC3_3_U37

VCC3_3_T39

VCCTX_LVDS_AJ37

VCCTX_LVDS_AG39

VCCDMI_AU15 VCCDMI_AW16

VCCIO_AK21

VCCAFDIPLL_AP13 VCCAFDIPLL_AP15

VCCVRM_AW18

VCCVRM_AU19

VCCIO_AW34

VCC3_3_BK28

VCCIO_AU35

VCCIO_AU29

VCCIO_AU27

VCCIO_AU25

VCCIO_AU23

VCCIO_AR27 VCCIO_AR29

VCCIO_AR25

VCCIO_AR23

VCCIO_AR15 VCCIO_AT13

VCCIO_AM21

VCCAPLLEXP

VCCCORE_AM33 VCCCORE_AM35

VCCCORE_AK33

VCCCORE_AK31

VCCCORE_AK29

VCCCORE_AJ29 VCCCORE_AJ31

VCCCORE_AJ27

VCCCORE_AJ25

VCCCORE_AJ23

VCCCORE_AG27 VCCCORE_AJ21

VCCCORE_AG25

VCCCORE_AG23

VCCCORE_AG21

VCCCORE_AF21 VCCCORE_AF23

VCCCORE_AE23

VCCCORE_AE21

VCCCORE_AB21

VCCTX_LVDS_AF37

VSSALVDS_AE33

VCCCORE_AC23

VCCCORE_AC21

VCCCORE_AB23

(7 OF 10)

VCC CORE

VCCIO

FDI

NAND/SPI

DMI

HVCMOS

LVDS

CRT

NC

VCCACLK

VCCDSW3_3

DCPSUSBYP

VCC3_3_V37 VCC3_3_V39

VCCAPLLDMI2

VCCIO_AP27

DCPSUS_V13

DCPSUS_AR33 DCPSUS_AU33

VCCASW_AB27

VCCASW_AB31

VCCASW_AB29

VCCASW_AC27 VCCASW_AC29 VCCASW_AC31 VCCASW_AE27 VCCASW_AE29 VCCASW_AE31

VCCASW_V21

VCCASW_U21

VCCASW_V23 VCCASW_V25 VCCASW_Y21

VCCASW_Y25

VCCASW_Y23

VCCASW_Y27 VCCASW_Y29 VCCASW_Y31

DCPRTC_R15 DCPRTC_U15

VCCVRM_AC39

VCCADPLLA VCCADPLLB

VCCIO_AJ17

VCCDIFFCLKN_AC37 VCCDIFFCLKN_AE37 VCCDIFFCLKN_AE39

VCCSSC DCPSST

V_PROC_IO

VCCRTC

VCCSUSHDA

VCCASW_V19

VCCASW_R19

VCCASW_U19

VCCIO_AC15

VCCIO_AC13

VCCIO_AB15

VCCVRM_AF17

VCCVRM_AE19

VCCAPLLSATA

VCCIO_AF15

VCCIO_AG15

VCCIO_AG13

VCCIO_AA13

VCC3_3_AF6

VCC3_3_R40

VCC3_3_AC19

VCC3_3_AB19

VCCSUS3_3_U35

VCCSUS3_3_U33

VCCSUS3_3_R35

VCCSUS3_3_R33

V5REF

VCCSUS3_3_AM27

DCPSUS_AU31

V5REF_SUS

VCCIO_N18

VCCSUS3_3_N27

VCCSUS3_3_U29

VCCSUS3_3_U27

VCCSUS3_3_R29

VCCSUS3_3_R27

VCCIO_U25

VCCIO_U23

VCCIO_R25

VCCIO_R23

PCI/GPIO/LPC

SATA

CLOCK/MISC

USB

FUSE

HDA

RTC CPU

(8 OF 10)

NC

NC NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

VCCACLK pin left as NC per DG

AL24 left as NC per DG

1.44 A Max, 474mA Idle

55mA Max, 5mA Idle

VCCAPLLDMI2 pin left as NC per DG

(PCH DPLLA PWR)

(PCH DPLLB PWR)

69 mA

VCCAFDIPLL pin left as NC per DG

PCH VCCADPLLA Filter

68 mA

VCCAPLLSATA pin left as NC per DG

NC-ed per DG

PCH VCCADPLLB Filter

PCH output, for decoupling only

10 mA Max, 1mA Idle

2

1

C2232

0.1UF

16V X5R-CERM 0201

10%

PLACE_NEAR=U1800.N16:2.54mm

2

1

C2231

CERM

6.3V

10%

402

1UF

PLACE_NEAR=U1800.N16:2.54mm

2

1

C2222

10%

0201

X5R-CERM

16V

PLACE_NEAR=U1800.U17:2.54mm

0.1UF

2

1

C2210

10%

0201

X5R-CERM

16V

PLACE_NEAR=U1800.R15:2.54mm

0.1UF

21

R2260

1/16W

5%

402

MF-LF

0

21

R2265

1/16W

5%

402

MF-LF

0

2

1

C2233

0.1UF

16V X5R-CERM 0201

10%

PLACE_NEAR=U1800.N16:2.54mm

2

1

C2261

6.3V

10%

402

CERM

1UF

PLACE_NEAR=U1800.BF40:2.54MM

2

1

C2266

6.3V

10%

402

CERM

1UF

PLACE_NEAR=U1800.BF40:2.54MM

2

1

C2260

16V X5R-CERM 0201

10%

0.1UF

2

1

C2265

16V X5R-CERM 0201

10%

0.1UF

AE33

AC33

V50

AW21

AW18

AU21

AU19

AJ37

AG39

AG37

AF37

Y19

AW34

AU35

AU29

AU27

AU25

AU23

AT13

AR29

AR27

AR25

AR23

AR15

AM21

AK21

AW16

AU15

AM23

AL13

AK15

AJ15

AJ13

AM35

AM33

AK33

AK31

AK29

AJ31

AJ29

AJ27

AJ25

AJ23

AJ21

AG27

AG25

AG23

AG21

AF23

AF21

AE23

AE21

AC23

AC21

AB23

AB21

AP39

AP19

AG33

AF33

AP15

AP13

U51

U37

T39

BK28

U1800

FCBGA

MOBILE-SFF

COUGAR-POINT

OMIT_TABLE

AF17

AE19

AC39

V31

U35

U33

U29

U27

R35

R33

R29

R27

N27

AM27

AC35

N16

U25

U23

R25

R23

N18

AP27

AJ17

AG15

AG13

AF15

AC15

AC13

AB15

AA13

R12

AE39

AE37

AC37

Y31

Y29

Y27

Y25

Y23

Y21

V25

V23

V21

V19

U21

U19 R19

AE31

AE29

AE27

AC31

AC29

AC27

AB31

AB29

AB27

AM2

AW31

BD40

BF40

AC51

V39

V37

R40

AF6

AC19

AB19

AM17

M37

N36

R10

V13

AU33

AU31

AR33

U17

U15

R15

U1800

FCBGA

MOBILE-SFF

COUGAR-POINT

OMIT_TABLE

PCH POWER

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM VOLTAGE=1.05V

PP1V05_S0_PCH_VCCADPLLB

PP1V05_S0_PCH_VCCADPLLA

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM VOLTAGE=1.05V

PP1V05_S0_PCH_VCCADPLLA

=PP3V3_S5_PCH_VCCDSW

TP_PPVOUT_PCH_DCPSUSBYP

PP3V3_S0_PCH_VCC3_3_CLK_F

=PP1V05_S0_PCH_VCCIO_CLK

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mm VOLTAGE=3.3V

PPVOUT_G3_PCH_DCPRTC

=PP1V8R1V5_S0_PCH_VCCVRM

PP1V05_S0_PCH_VCCADPLLB

=PP1V05_S0_PCH_VCCIO_CLK

=PP1V05_S0_PCH_VCCDIFFCLK

=PP1V05_S0_PCH_VCCSSC

MIN_LINE_WIDTH=0.2 mm

VOLTAGE=3.3V

PPVOUT_S0_PCH_DCPSST

MIN_NECK_WIDTH=0.2 mm

=PP1V05_S0_PCH_V_PROC_IO

=PP1V05_S0_PCH_VCCASW

=PP1V05_S0_PCH_VCCIO_SATA

=PP1V8R1V5_S0_PCH_VCCVRM

=PP1V05_S0_PCH_VCCIO_SATA

=PP3V3_S0_PCH_VCC3_3_SATA

=PP3V3_S0_PCH_VCC3_3_GPIO

=PP3V3_SUS_PCH_VCCSUS_GPIO

=PP5V_S0_PCH_V5REF

=PP3V3_SUS_PCH_VCCSUS

=PP5V_SUS_PCH_V5REFSUS

=PP1V05_S0_PCH_VCCIO_PLLUSB

=PP3V3_SUS_PCH_VCCSUS_USB

=PP1V05_S0_PCH_VCCIO_USB

=PP3V3_S0_PCH_VCC3_3_PCI

=PP1V8R1V5_S0_PCH_VCCVRM

=PP1V05_S0_PCH_VCCDMI_FDI

=PP1V05_S0_PCH_VCCIO

=PP1V05_S0_PCH_VCCIO_PLLPCIE

TP_1V05_S0_PCH_VCCAPLLEXP

=PP1V05_S0_PCH_VCC_CORE

=PP1V05_S0_PCH_VCC_DMI

=PP3V3_S5_PCH_VCC_SPI

=PP3V3_S0_PCH_VCC3_3_HVCMOS

=PP1V8R1V5_S0_PCH_VCCVRM

PP1V05_S0_PCH_VCCCLKDMI_F

=PP1V8_S0_PCH_VCC_DFTERM

PP3V3_S0_PCH_VCCA_DAC_F

=PP1V05_S0_PCH_VCCASW

=PP1V05_S0_PCH_VCCIO_PLLFDI

=PP3V3R1V5_S0_PCH_VCCSUSHDA

=PPVRTC_G3_PCH

=PP1V05_S0_PCH_VCCADPLL

22 OF 109

2.5.0

051-8871

20 OF 74

20

7

22

7

20 22

7

20

7

20 22

7

16 22

7

22

7

22

7

20 22

7

16 20 22

7

20

7

16 20 22

7

22

7

22

7

22

7

22

7

22

7

22

7

22

7

20

7

22

7

22

7

22

7

22

7

22

7

20

22

7

18 22

22

7

20 22

7

16 22

7

16 17

7

VSS_G7

VSS_BA7

VSS_B46

VSS_B42

VSS_B38

VSS_B34

VSS_B30

VSS_B26

VSS_B22

VSS_B18

VSS_B14

VSS_B10

VSS_B6

VSS_AY10

VSS_AW45

VSS_AW43

VSS_AW41

VSS_AW39

VSS_AW36

VSS_AW29

VSS_AW27

VSS_AW25

VSS_AW23

VSS_AW13

VSS_AW11

VSS_AW9

VSS_AW7

VSS_AV50

VSS_AV48

VSS_AV4

VSS_AV2

VSS_AU37

VSS_AU17

VSS_AT45

VSS_AT43

VSS_AT41

VSS_AT39

VSS_AT11

VSS_AT9

VSS_AT7

VSS_AR37

VSS_AR35

VSS_AR31

VSS_AR21

VSS_AR19

VSS_AR17

VSS_AR8

VSS_AR6

VSS_AP50

VSS_AP48

VSS_AP45

VSS_AP43

VSS_AP41

VSS_AP37

VSS_AP35

VSS_AP33

VSS_AP31

VSS_AP29

VSS_AP25

VSS_AP23

VSS_AP21

VSS_AP17

VSS_AP11

VSS_AP9

VSS_AP7

VSS_AP4

VSS_AP2

VSS_AM37

VSS_AM31

VSS_AM29

VSS_AM25

VSS_AM19

VSS_AM15

VSS_AL45

VSS_AL43

VSS_AL41

VSS_AL39

VSS_AL11

VSS_AL9

VSS_AL7

VSS_AK50

VSS_AK48

VSS_AK37

VSS_AK35

VSS_AK27

VSS_AK25

VSS_AK23

VSS_AK19

VSS_AK17

VSS_AK4

VSS_AK2

VSS_AJ45

VSS_AJ43

VSS_AJ41

VSS_AJ39

VSS_AJ35

VSS_AJ33

VSS_AJ19

VSS_AJ11

VSS_AJ9

VSS_AJ7

VSS_AH2

VSS_AG45

VSS_AG43

VSS_AG41

VSS_AG35

VSS_AG31

VSS_AG29

VSS_AG19

VSS_AG17

VSS_AG11

VSS_AG9

VSS_AG7

VSS_AF50

VSS_AF48

VSS_AF35

VSS_AF31

VSS_AF29

VSS_AF27

VSS_AF25

VSS_AF19

VSS_AF8

VSS_AF4

VSS_AF2

VSS_AE45

VSS_AE43

VSS_AE41

VSS_AE35

VSS_AE25

VSS_AE17

VSS_AE15

VSS_AE13

VSS_AE11

VSS_AE9

VSS_AE7

VSS_AC45

VSS_AC43

VSS_AC41

VSS_AC25

VSS_AC17

VSS_AC11

VSS_AC9

VSS_AC7

VSS_AB50

VSS_AB48

VSS_AB37

VSS_AB35

VSS_AB33

VSS_AB25

VSS_AB17

VSS_AB4

VSS_AB2

VSS_AA45

VSS_AA43

VSS_AA39

VSS_AA11

VSS_AA9

VSS_AA7

VSS_BB48 VSS_BA31 VSS_BA34 VSS_BA36 VSS_BA39 VSS_BA41 VSS_BA43 VSS_BA45

VSS_BB4 VSS_BB2

VSS_BA11 VSS_BA13 VSS_BA16 VSS_BA18 VSS_BA21 VSS_BA23 VSS_BA25 VSS_BA27 VSS_BA29 VSS_BA9

VSS_AA41

VSS

(9 OF 10)

VSS_G9

VSS_F50

VSS_F48

VSS_F4

VSS_F2

VSS_D46

VSS_D42

VSS_D38

VSS_D34

VSS_D30

VSS_D26

VSS_D22

VSS_D18

VSS_BK46

VSS_BK42

VSS_BK38

VSS_BK34

VSS_BK32

VSS_BK30

VSS_BK26

VSS_D14

VSS_D10

VSS_D6

VSS_BK22

VSS_BK18

VSS_BK14

VSS_BK10

VSS_BH48

VSS_BH46

VSS_BH44

VSS_BH42

VSS_BH38

VSS_BH34

VSS_BH32

VSS_BH30

VSS_BH28

VSS_BH26

VSS_BH22

VSS_BH18

VSS_BH14

VSS_BH10

VSS_BF50

VSS_BF48

VSS_BH6

VSS_BF24

VSS_BF15

VSS_BE45

VSS_BE43

VSS_BE41

VSS_BE39

VSS_BE36

VSS_BE34

VSS_BF4

VSS_BF2

VSS_BE31

VSS_BE29

VSS_BE27

VSS_BE25

VSS_BE23

VSS_BE21

VSS_BE18

VSS_BE16

VSS_BE13

VSS_BE11

VSS_BE9

VSS_BD24

VSS_BD15

VSS_BC45

VSS_BC43

VSS_BC41

VSS_BC39

VSS_BC36

VSS_BE7

VSS_BC31

VSS_BC29

VSS_BC27

VSS_BC25

VSS_BC23

VSS_BC21

VSS_BC18

VSS_BC16

VSS_BC13

VSS_BC11

VSS_BB50

VSS_Y37

VSS_Y35

VSS_Y33

VSS_V45

VSS_V43

VSS_V41

VSS_V35

VSS_V33

VSS_V29

VSS_V27

VSS_V48 VSS_Y15 VSS_Y17

VSS_V7

VSS_V4

VSS_V2

VSS_U49

VSS_U31

VSS_T45

VSS_V9 VSS_V11 VSS_V15 VSS_V17

VSS_T43

VSS_T11

VSS_T9

VSS_T7

VSS_R37

VSS_R31

VSS_R21

VSS_R17

VSS_T13 VSS_T41

VSS_P50

VSS_N45

VSS_N43

VSS_N41

VSS_N39

VSS_N34

VSS_N31

VSS_N29

VSS_P2

VSS_P4 VSS_P48

VSS_N13

VSS_N11

VSS_N9

VSS_N7

VSS_L45

VSS_L43

VSS_L41

VSS_N21 VSS_N23 VSS_N25

VSS_L29

VSS_L27

VSS_L25

VSS_L23

VSS_L21

VSS_L18

VSS_L31 VSS_L34 VSS_L36 VSS_L39

VSS_L16

VSS_L9

VSS_L7

VSS_K50

VSS_K48

VSS_K4

VSS_K2

VSS_J45

VSS_L11 VSS_L13

VSS_J41

VSS_J29

VSS_J27

VSS_J25

VSS_J23

VSS_J21

VSS_J18

VSS_J34 VSS_J36 VSS_J39

VSS_J9

VSS_J7

VSS_G43

VSS_G41

VSS_G39

VSS_G36

VSS_G34

VSS_J11 VSS_J13 VSS_J16

VSS_G25

VSS_G23

VSS_G21

VSS_G18

VSS_G16

VSS_G13

VSS_G11

VSS_G27 VSS_G29 VSS_G31

VSS_J31

VSS_BC34

VSS

(10 OF 10)

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

G7

BB48

BB4 BB2BA9

BA7

BA45

BA43

BA41

BA39

BA36

BA34

BA31

BA29

BA27

BA25

BA23

BA21

BA18

BA16

BA13

BA11

B6

B46

B42

B38

B34

B30

B26

B22

B18

B14

B10

AY10

AW9

AW7

AW45

AW43

AW41

AW39

AW36

AW29

AW27

AW25

AW23

AW13

AW11

AV50

AV48

AV4

AV2

AU37

AU17

AT9

AT7

AT45

AT43

AT41

AT39

AT11

AR8

AR6

AR37

AR35

AR31

AR21

AR19

AR17

AP9

AP7

AP50

AP48

AP45

AP43

AP41

AP4

AP37

AP35

AP33

AP31

AP29

AP25

AP23

AP21

AP2

AP17

AP11

AM37

AM31

AM29

AM25

AM19

AM15

AL9

AL7

AL45

AL43

AL41

AL39

AL11

AK50

AK48

AK4

AK37

AK35

AK27

AK25

AK23

AK2

AK19

AK17

AJ9

AJ7

AJ45

AJ43

AJ41

AJ39

AJ35

AJ33

AJ19

AJ11

AH2

AG9

AG7

AG45

AG43

AG41

AG35

AG31

AG29

AG19

AG17

AG11

AF8

AF50

AF48

AF4

AF35

AF31

AF29

AF27

AF25

AF2

AF19

AE9

AE7

AE45

AE43

AE41

AE35

AE25

AE17

AE15

AE13

AE11

AC9

AC7

AC45

AC43

AC41

AC25

AC17

AC11

AB50

AB48

AB4

AB37

AB35

AB33

AB25

AB2

AB17

AA9

AA7

AA45

AA43

AA41

AA39

AA11

U1800

FCBGA

COUGAR-POINT

MOBILE-SFF

OMIT_TABLE

Y37

Y35

Y33

Y17

Y15

V9

V7

V48

V45

V43

V41

V4

V35

V33

V29

V27

V2

V17

V15

V11

U49

U31

T9

T7

T45

T43

T41

T13

T11

R37

R31

R21

R17

P50

P48

P4

P2

N9

N7

N45

N43

N41

N39

N34

N31

N29

N25

N23

N21

N13

N11

L9

L7

L45

L43

L41

L39

L36

L34

L31

L29

L27

L25

L23

L21

L18

L16

L13

L11

K50

K48

K4

K2

J9

J7

J45

J41

J39

J36

J34

J31

J29

J27

J25

J23

J21

J18

J16

J13

J11

G9

G43

G41

G39

G36

G34

G31

G29

G27

G25

G23

G21

G18

G16

G13

G11

F50

F48

F4

F2

D6

D46

D42

D38

D34

D30

D26

D22

D18

D14

D10

BK46

BK42

BK38

BK34

BK32

BK30

BK26

BK22

BK18

BK14

BK10

BH6

BH48

BH46

BH44

BH42

BH38

BH34

BH32

BH30

BH28

BH26

BH22

BH18

BH14

BH10

BF50

BF48

BF4

BF24

BF2

BF15

BE9

BE7

BE45

BE43

BE41

BE39

BE36

BE34

BE31

BE29

BE27

BE25

BE23

BE21

BE18

BE16

BE13

BE11

BD24

BD15

BC45

BC43

BC41

BC39

BC36

BC34

BC31

BC29

BC27

BC25

BC23

BC21

BC18

BC16

BC13

BC11

BB50

U1800

FCBGA

COUGAR-POINT

MOBILE-SFF

OMIT_TABLE

SYNC_MASTER=K21_MLB

SYNC_DATE=12/13/2010

PCH GROUNDS

23 OF 109

2.5.0

051-8871

21 OF 74

NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PCH VCC3_3 BYPASS

(PCH PCI 3.3V PWR)

(PCH Reference for 5V Tolerance on USB)

(PCH HD Audio 3.3V/1.5V PWR)

(PCH USB 1.05V PWR)

PCH VCCIO BYPASS

PCH VCCCORE BYPASS

(PCH SUSPEND USB 3.3V PWR)

(PCH 1.05V CORE PWR)

<1 MA

1 mA

PCH VCCSUS3_3 BYPASS

<1 MA S0-S5

PCH V5REF_SUS Filter & Follower

NEED PWR CONSTRAINT

PCH VCCIO BYPASS

1 mA S0-S5

(PCH Reference for 5V Tolerance on PCI)

PCH V5REF Filter & Follower

PCH VCCSUSHDA BYPASS

NEED PWR CONSTRAINT

2

1

C2439

PLACE_NEAR=U1800.N36:2.54mm

X5R 402

10V

10%

1UF

2 1

R2405

100

MF

201

5%

1/20W

2

1

C2438

0.1UF

CERM

402

20% 10V

PLACE_NEAR=U1800.M37:2.54mm

6

1

D2400

BAT54DW-X-G

SOT-363

2 1

R2404

10

MF

5%

1/20W

201

3

4

D2400

BAT54DW-X-G

SOT-363

2

1

C2423

0.1UF

X5R-CERM 0201

10% 16V

PLACE_NEAR=U1800.AF6:2.54mm

2

1

C2440

PLACE_NEAR=U1800.AJ15:2.54mm

0.1UF

X5R-CERM 0201

10% 16V

2

1

C2441

PLACE_NEAR=U1800.V31:2.54mm

0.1UF

X5R-CERM 0201

10% 16V

2

1

C2419

PLACE_NEAR=U1800.AM23:2.54mm

1UF

X5R 0201

20%

6.3V

2

1

C2421

0.1UF

X5R-CERM 0201

10% 16V

PLACE_NEAR=U1800.BK28:2.54mm

2

1

C2413

PLACE_NEAR=U1800.U27:2.54mm

0.1UF

X5R-CERM 0201

10% 16V

2

1

C2417

PLACE_NEAR=U1800.AM17:2.54mm

0.1UF

X5R-CERM 0201

10% 16V

2

1

C2416

PLACE_NEAR=U1800.AM17:2.54mm

4.7UF

X5R 402

20%

6.3V

2

1

C2484

PLACE_NEAR=U1800.R27:2.54mm

0.1UF

X5R-CERM 0201

10% 16V

2

1

C2485

0.1UF

X5R-CERM 0201

10% 16V

PLACE_NEAR=U1800.R40:2.54mm

2

1

C2463

PLACE_NEAR=U1800.AU25:2.54mm

1UF

X5R 0201

20%

6.3V

2

1

C2475

PLACE_NEAR=U1800.AC35:2.54mm

1UF

X5R 0201

20%

6.3V

2

1

C2434

PLACE_NEAR=U1800.AE37:2.54mm

1UF

X5R 0201

20%

6.3V

2

1

C2469

PLACE_NEAR=U1800.AJ17:2.54mm

1UF

X5R 0201

20%

6.3V

2

1

C2414

PLACE_NEAR=U1800.AU25:2.54mm

6.3V

20%

0201

X5R

1UF

2

1

C2401

PLACE_NEAR=U1800.AU25:2.54mm

10UF

CERM-X5R

0402

20%

6.3V

2

1

C2452

PLACE_NEAR=U1800.AC13:2.54mm

1UF

X5R 0201

20%

6.3V

2

1

C2499

PLACE_NEAR=U1800.R12:2.54mm

0.1UF

X5R-CERM

0201

10% 16V

2

1

C2442

PLACE_NEAR=U1800.Y19:2.54mm

1UF

X5R 0201

20%

6.3V

2

1

C2486

0.1UF

X5R-CERM 0201

10% 16V

PLACE_NEAR=U1800.AC19:2.54mm

2

1

C2444

PLACE_NEAR=U1800.AG13:2.54mm

1UF

X5R 0201

20%

6.3V

2

1

C2446

PLACE_NEAR=U1800.U23:2.54mm

1UF

X5R 0201

20%

6.3V

2

1

C2424

0.1UF

X5R-CERM 0201

10% 16V

PLACE_NEAR=U1800.T39:2.54mm

2

1

C2460

PLACE_NEAR=U1800.AK33:2.54mm

10UF

CERM-X5R

0402

20%

6.3V

2

1

C2482

PLACE_NEAR=U1800.AF23:2.54mm

1UF

X5R 0201

20%

6.3V

2

1

C2481

PLACE_NEAR=U1800.AC21:2.54mm

1UF

X5R 0201

20%

6.3V 2

1

C2483

PLACE_NEAR=U1800.AJ25:2.54mm

1UF

X5R 0201

20%

6.3V

2

1

C2407

PLACE_NEAR=U1800.AU25:2.54mm

6.3V

20%

0201

X5R

1UF

2

1

C2429

PLACE_NEAR=U1800.AU25:2.54mm

1UF

X5R 0201

20%

6.3V

2

1

C2420

X5R-CERM1

0603

22UF

6.3V

PLACE_NEAR=U1800.AC27:2.54mm

20%

2

1

C2496

1UF

PLACE_NEAR=U1800.AC27:2.54mm

X5R 0201

20%

6.3V

2

1

C2456

PLACE_NEAR=U1800.AC27:2.54mm

1UF

X5R 0201

20%

6.3V

2

1

C2426

PLACE_NEAR=U1800.AC27:2.54mm

1UF

X5R 0201

20%

6.3V

21

R2415

1

MF

201

5%

1/20W

2

1

C2411

PLACE_NEAR=U1800.AP39:2.54mm

10UF

CERM-X5R 0402-1

20%

6.3V

2

1

C2430

PLACE_NEAR=U1800.AM17:2.54mm

0.1UF

X5R-CERM 0201

10% 16V

2

1

C2428

22UF

20%

6.3V 0603

X5R-CERM1

PLACE_NEAR=U1800.AC27:2.54mm

21

R2450

0

MF

201

5%

1/20W

2

1

C2455

PLACE_NEAR=U1800.U51:2.54mm

0.01UF

X5R-CERM

0201

10% 16V

2

1

C2451

X5R-CERM

PLACE_NEAR=U1800.U51:2.54mm

0.1UF

0201

10% 16V

21

R2451

1/16W

5%

MF-LF

1

402

2

1

C2454

PLACE_NEAR=U1800.V37:2.54mm

6.3V

20%

0201

X5R

1UF

21

L2451

0603

10UH-0.12A-0.36OHM

2

1

C2476

PLACE_NEAR=U1800.U33:2.54mm

1UF

X5R 0201

20%

6.3V

21

L2406

10UH-0.12A-0.36OHM

0603

2

1

C2450

PLACE_NEAR=U1800.U51:2.54mm

10UF

CERM-X5R

0402

20%

6.3V

2

1

C2453

PLACE_NEAR=U1800.V37:2.54mm

10UF

CERM-X5R

0402-1

20%

6.3V

PCH DECOUPLING

SYNC_DATE=12/13/2010

SYNC_MASTER=K21_MLB

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.5MM VOLTAGE=1.05V

MAKE_BASE=TRUE

PP1V05_S0_PCH_VCCCLKDMI_F

=PP1V05_S0_PCH_VCCASW

PP3V3_S0_PCH_VCCA_DAC_F

VOLTAGE=3.3V

MAKE_BASE=TRUE MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM

PP1V05_S0_PCH_VCCCLKDMI_R

=PP3V3_S0_PCH_VCCADAC

=PP3V3_S0_PCH_VCC3_3_HVCMOS

=PP3V3_S5_PCH_VCCDSW

=PP1V05_S0_PCH_VCCDIFFCLK

=PP1V8_S0_PCH_VCC_DFTERM

=PP1V05_S0_PCH_VCC_DMI

=PP1V05_S0_PCH_VCCIO_SATA

=PP3V3_SUS_PCH_VCCSUS_GPIO

=PP1V05_S0_PCH_VCCIO_USB

=PP5V_SUS_PCH

=PP3V3_SUS_PCH

=PP5V_S0_PCH_V5REF

=PP3V3_S0_PCH =PP5V_S0_PCH

PP5V_S0_PCH_V5REF

MAKE_BASE=TRUE

VOLTAGE=5V

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.25MM

=PP3V3_S0_PCH_VCC3_3_PCI

=PP3V3_SUS_PCH_VCCSUS_USB

=PP3V3_S5_PCH_VCC_SPI

=PP3V3R1V5_S0_PCH_VCCSUSHDA

=PP1V05_S0_PCH_V_PROC_IO

=PP1V05_S0_PCH

=PP3V3_S0_PCH_VCC3_3_SATA

=PP1V05_S0_PCH_VCCSSC

=PP1V05_S0_PCH_VCCIO_CLK

=PP1V05_S0_PCH_VCC_CORE

=PP3V3_S0_PCH_VCC3_3_GPIO

PP5V_SUS_PCH_V5REFSUS

VOLTAGE=5V

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.25MM

MAKE_BASE=TRUE

=PP5V_SUS_PCH_V5REFSUS

PP3V3_S0_PCH_VCC3_3_CLK_F

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP3V3_S0_PCH_VCC3_3_CLK_R

=PP3V3_S0_PCH_VCC3_3_CLK

=PP1V05_S0_PCH_VCCIO

24 OF 109

2.5.0

051-8871

22 OF 74

5

2

20

7

20

7

20

7

20

7

16 20

7

18 20

7

20

7

16 20

7

20

7

20

7

20

7

16 19

7

20

7

20

7

20

7

16 20

7

20

7

16

7

20

7

20

7

20

7

20

7

20

7

20

IN

OUT

IN

OUT

NC

IN

OUT

IN

BI

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

NC

BI

IN

BI

IN

OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PLACEMENT NOTE:

TMS

OBSDATA_C1

DESIGN NOTE:

TRSTn

TDI

OBSDATA_C3

OBSFN_D0

PLACEMENT NOTE:

PLACE TCK/TDI/TMS/TRST* TERM NEAR CPU

TERM NEAR PCH

TDO

ODT AVAILABLE ON JTAG

HOOK1

OBSFN_B0

OBSFN_D1

OBSDATA_D2

OBSDATA_B0

SCL

OBSDATA_D3

XDP_PRESENT#

HOOK2

SDA

OBSDATA_B1

OBSFN_C0

TCK1

PLACEMENT NOTE:

ITPCLK#/HOOK5

ITPCLK/HOOK4

OBSDATA_B3

PWRGD/HOOK0

HOOK3

NOTE: XDP_DBRESET_L pulled-up to 3.3V on P. 28

OBSFN_B1

SNB XDP CONN

PLACE TDO TERM NEAR

PLACE TCK/TDI/TMS/TRST*

OBSFN_A0

OBSDATA_D1

OBSDATA_D0

DBR#/HOOK7

RESET#/HOOK6

VCC_OBS_CD

OBSDATA_A2

OBSDATA_A3

OBSFN_A1 OBSFN_C1

NOTE: XDP_DBRESET_L pulled-up to 3.3V on P. 28

OBSDATA_A0

OBSDATA_A1

TCK0

PCH XDP CONN

PLACE TDO TERM NEAR

PLACEMENT NOTE:

VCC_OBS_AB

OBSDATA_B2

OBSDATA_C0

OBSDATA_C2

Even pins should be facing edge of the board

1K series R on PCH Support P. 28

OBSFN_A0

OBSFN_A1

OBSDATA_A0

OBSDATA_A1

OBSDATA_A2

OBSDATA_A3

OBSFN_B0

OBSFN_B1

OBSDATA_B0

OBSDATA_B1

OBSDATA_B2

OBSDATA_B3

PWRGD/HOOK0

HOOK1

VCC_OBS_AB

HOOK2

HOOK3

SCL

SDA

TCK1

TCK0

XDP_PRESENT#

TMS

TDI

TRSTn

TDO

DBR#/HOOK7

RESET#/HOOK6

VCC_OBS_CD

ITPCLK#/HOOK5

ITPCLK/HOOK4

OBSDATA_D3

OBSDATA_D2

OBSDATA_D1

OBSDATA_D0

OBSFN_D1

OBSFN_D0

OBSDATA_C3

OBSDATA_C2

OBSDATA_C1

OBSDATA_C0

OBSFN_C1

OBSFN_C0

Use with 920-0782 Adapter Flex to support chipset debug

NOTE: This is not the standard XDP pinout

PCH MICRO2-XDP CONNECTOR

Use with 920-0782 Adapter Flex to support chipset debug

NOTE: This is not the standard XDP pinout

PROCESSOR MICRO2-XDP CONNECTOR

998-2516

9

10 25

10 66

9

66

10 66

9

66

9

66

9

66

21

R2501

201

1/20W

MF

PLACE_NEAR=U1000.B50:2.54MM

XDP

5%

1K

9

23 66

9

66

19

16

21

R2579

XDP

PLACE_NEAR=U1800.AA3:2.54MM

1/20W

201

MF

0

5%

8

19

9

66

25

16 23

9

66

21

R2580

PLACE_NEAR=U1800.A17:2.54MM

5%

MF

201

XDP

1/20W

0

18

16 23

9

66

18 24

2

1

R2556

201

1/20W

MF

51

XDP

5%

PLACE_NEAR=U1800.M17:2.54MM

23 43

10 23 25 66

2

1

C2580

0.1UF

16V

10%

XDP

X5R

402

2

1

C2581

10%

0.1UF

16V

X5R

XDP

402

19

21

R2502

201

XDP

1/20W

MF

0

5%

PLACE_NEAR=U4900.D10:2.54MM

17 23 40

21

R2585

201

1/20W

XDP

MF

0

5%

PLACE_NEAR=U4900.D10:2.54MM

17 23 40

21

R2504

910

XDP

5%

1/16W

MF-LF

402

17 25

18

21

R2584

PLACE_NEAR=J2550.39:2.54MM

1K

XDP

5% MF-LF

1/16W

402

25 40 51 61

21

R2581

201

1/20W

MF

XDP

0

5%

PLACE_NEAR=U1800.B16:2.54MM

18

10 23 66

10 23 25 66

21

R2582

PLACE_NEAR=U1800.H4:2.54MM

201

5%

MF

1/20W

0

XDP

18

21

R2578

PLACE_NEAR=U1800.G1:2.54MM

5%

0

XDP

MF

1/20W

201

19 26

21

R2586

PLACE_NEAR=U1800.A13:2.54MM

XDP

1/20W

201

MF

0

5%

21

R2587

MF

201

1/20W

5%

0

XDP

PLACE_NEAR=U1800.D16:2.54MM

18

9

10 23 66

16 66

21

R2515

201

1/20W

MF

0

PLACE_NEAR=R1841.1:2.54MM

XDP

5%

21

R2516

201

XDP

1/20W

MF

PLACE_NEAR=R1840.1:2.54MM

5%

0

21

R2505

1/20W

201

MF

XDP

1K

5%

PLACE_NEAR=R1125.1:2.54MM

16 63

2

1

R2550

PLACE_NEAR=J2550.52:2.54MM.

MF-LF

51

1/16W

5%

402

XDP

10 23 66

2

1

R2551

51

PLACE_NEAR=U1800.U12:2.54MM

201

1/20W

MF

XDP

5%

2

1

R2552

201

1/20W

MF

PLACE_NEAR=U1800.M15:2.54MM

5%

XDP

51

21

R2560

XDP_CPU:BPM

5%

0

MF-LF

1/16W

402

21

R2561

5%

1/16W

402

XDP_CPU:BPM

MF-LF

0

21

R2562

XDP_CPU:BPM

5%

MF-LF

1/16W

0

402

21

R2563

XDP_CPU:BPM

0

5%

MF-LF

1/16W

402

21

R2564

5%

XDP_CPU:CFG

0

MF-LF

1/16W

402

10 23 66

21

R2566

1/16W

402

5%

0

XDP_CPU:CFG

MF-LF

21

R2567

MF-LF

XDP_CPU:CFG

0

5%

1/16W

402

21

R2565

XDP_CPU:CFG

0

5%

MF-LF

1/16W

402

2

1

R2540

402

NOSTUFF

1/16W

MF-LF

1K

5%

2

1

C2500

16V

10%

X5R

XDP

0.1UF

402

9

87

64 63

62

61

60659

58 57

56 55

54 53

52 51

50549

48 47

46 45

44 43

42 41

40439

38 37

36 35

34 33

32 31

30329

28 27

26 25

24 23

22 21

20219

18 17

16 15

14 13

12 11

10

1

J2500

XDP_CONN CRITICAL

DF40RC-60DP-0.4V

M-ST-SM

9

87

64 63

62

61

60659

58 57

56 55

54 53

52 51

50549

48 47

46 45

44 43

42 41

40439

38 37

36 35

34 33

32 31

30329

28 27

26 25

24 23

22 21

20219

18 17

16 15

14 13

12 11

10

1

J2550

DF40RC-60DP-0.4V

M-ST-SM

XDP_CONN CRITICAL

19

9

23 66

2

1

C2501

10%

XDP

0.1UF

X5R

16V

402

9

66

10 66

9

66

9

66

9

66

9

66

23 43

10 23 66

21

R2500

1/20W

PLACE_NEAR=U1000.B46:1MM

XDP

201

MF

1K

5%

9

66

10 19 66

9

66

2

1

R2510

PLACE_NEAR=J2500.52:2.54MM

51

5%

XDP

MF-LF

1/16W

402

2

1

R2511

5%

51

XDP

PLACE_NEAR=U1000.M60

MF-LF

1/16W

402

2

1

R2512

51

5%

XDP

PLACE_NEAR=U1000.L55:2.54MM

MF-LF

1/16W

402

2

1

R2513

201

1/20W

MF

51

XDP

5%

PLACE_NEAR=U1000.J58:2.54MM

2

1

R2514

201

MF

1/20W

5%

PLACE_NEAR=U1000.L56:2.54MM

XDP

51

10 66

SYNC_MASTER=K21_MLB

SYNC_DATE=12/13/2010

CPU & PCH XDP

PCH_GPIO59_OC0_L

USB_HUB_SOFT_RESET_L

XDP_PCH_ENET_PWR_EN

ALL_SYS_PWRGD

SDCONN_STATE_CHANGE

SDCONN_STATE_RST_L

XDP_PCH_SDCONN_DET_L

XDP_BPM_L<6>

CPU_PWRGD

ITPXDP_CLK100M_P

ITPXDP_CLK100M_N

=PPVCCIO_S0_XDP

XDP_BPM_L<4>

PM_PWRBTN_L

=PP1V05_SUS_PCH_JTAG

PM_PCH_SYS_PWROK

XDP_CPU_TRST_L

XDP_CPU_TDO

XDP_BPM_L<7>

XDP_BPM_L<5>

XDP_CPU_TMS

XDP_PCH_TDO

CPU_CFG<0>

=PP3V3_S0_XDP

=SMBUS_XDP_SCL

XDP_CPU_PWRBTN_L

XDP_CPU_TDI XDP_CPU_TMS

XDP_BPM_L<0>

CPU_CFG<1>

CPU_CFG<7>

XDP_CPU_TDO XDP_CPU_TRST_L

PCH_GPIO14_OC7_L

PCH_GPIO10_OC6_L

PCH_GPIO43_OC4_L

=SMBUS_XDP_SCL

=SMBUS_XDP_SDA

TP_XDPPCH_HOOK3

TP_XDP_PCH_OBSFN_B<1>

TP_XDP_PCH_OBSFN_B<0>

XDP_PCH_TMS

XDP_DBRESET_L

TP_XDP_PCH_TRST_L XDP_PCH_TDI

XDP_PCH_TDO

TP_XDP_PCH_HOOK4

TP_XDP_PCH_OBSFN_D<1>

TP_XDP_PCH_HOOK5

CPU_CFG<5>

XDP_CPU_PWRGD

XDP_OBSDATA_B<2> XDP_OBSDATA_B<3>

XDP_CPU_PRDY_L

XDP_CPU_PREQ_L

XDP_BPM_L<3>

CPU_CFG<10> CPU_CFG<11>

XDP_BPM_L<2>

XDP_VR_READY

PM_PWRBTN_L

CPU_CFG<14>

XDP_BPM_L<1>

ENET_PWR_EN

XDP_PCH_SDCONN_STATE_RST_L

XDP_PCH_PWRBTN_L

AUD_IPHS_SWITCH_EN_PCH

CPU_CFG<6>

XDP_CPU_TDI

XDP_CPU_TCK

XDP_PCH_TDI XDP_PCH_TMS XDP_PCH_TCK

CPU_CFG<12>

=SMBUS_XDP_SDA

CPU_RESET_L

CPU_CFG<16>

CPU_CFG<0>

XDP_DBRESET_L

XDP_CPURST_L

CPU_CFG<4>

CPU_CFG<9>

CPU_CFG<8>

CPU_CFG<3>

XDP_CPU_TCK

XDP_OBSDATA_B<0> XDP_OBSDATA_B<1>

XDP_PCH_USB_HUB_SOFT_RST_L

XDP_PCH_GPIO59_OC0_L

XDP_PCH_S5_PWRGD

TP_XDPPCH_HOOK2

XDP_PCH_TCK

XDPPCH_PLTRST_L

XDP_PCH_AUD_IPHS_SWITCH_EN

JTAG_ISP_TCK

PCH_GPIO36_SATA2GP

TP_XDP_PCH_OBSFN_A<0> TP_XDP_PCH_OBSFN_A<1>

=PPVCCIO_S0_XDP

CPU_CFG<17>

CPU_CFG<2>

XDP_CPU_CLK100M_P XDP_CPU_CLK100M_N

ENET_LOW_PWR

TP_XDP_PCH_OBSFN_D<0>

SMC_IG_THROTTLE_L

PCH_GPIO15

=PP3V3_S5_XDP

SATARDRVR_EN

DP_AUXCH_ISOL

PCH_GPIO35

XDP_PCH_ISOLATE_CPU_MEM_L

ISOLATE_CPU_MEM_L

XDP_CPU_CFG<0>

CPU_CFG<15>

CPU_CFG<13>

25 OF 109

2.5.0

051-8871

23 OF 74

7

23

7

10 23 66

16 23

7

6

10 23 66

16 23

66

6

7

23

66

6

7

G

D

S

G

D

S

BI

IN

BI

IN

VDD33

PLLFILT

CRFILT

SUSP_IND/LOCAL_PWR/NON_REM0

SDA/SMBDATA/NON_REM1

SCL/SMBCLK/CFG_SEL0

HS_IND/CFG_SEL1

XTALIN/CLKIN XTALOUT

TEST

RESET*

THRM_PAD

USBDP_UP

NC

OSC3*

OCS1* OCS2*

USBDM_UP

RBIAS

VBUS_DET

NC

NC NC

USBDP_DN3/PRT_DIS_P3

USBDM_DN3/PRT_DIS_M3

USBDP_DN2/PRT_DIS_P2

USBDM_DN2/PRT_DIS_M2

USBDP_DN1/PRT_DIS_P1

USBDM_DN1/PRT_DIS_M1

PRTPWR3/BC_EN3*

PRTPWR1/BC_EN1* PRTPWR2/BC_EN2*

SYM VER 1

VDD33

PLLFILT

CRFILT

SUSP_IND/LOCAL_PWR/NON_REM0

SDA/SMBDATA/NON_REM1

SCL/SMBCLK/CFG_SEL0

HS_IND/CFG_SEL1

XTALIN/CLKIN XTALOUT

TEST

RESET*

THRM_PAD

USBDP_UP

NC

OSC3*

OCS1* OCS2*

USBDM_UP

RBIAS

VBUS_DET

NC

NC NC

USBDP_DN3/PRT_DIS_P3

USBDM_DN3/PRT_DIS_M3

USBDP_DN2/PRT_DIS_P2

USBDM_DN2/PRT_DIS_M2

USBDP_DN1/PRT_DIS_P1

USBDM_DN1/PRT_DIS_M1

PRTPWR3/BC_EN3*

PRTPWR1/BC_EN1* PRTPWR2/BC_EN2*

SYM VER 1

BI

NC NC

NC

TABLE_BOMGROUP_ITEM

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_5_ITEM

TABLE_BOMGROUP_ITEM

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

IPU

1 0 Port 1 and 2 are non removable

BOM TABLE

0 0 All ports are removable

NON_REM1 NON_REM0 DESCRIPTION

0 1 Port 1 is non removable

IPU

1 1 Port 1, 2, and 3 are non removable

T29

Trackpad/Keyboard

Right USB A

IPU

LIO External D

SDCARD(NA to K78)

BlueTooth

2

1

R2641

201

1/20W MF

10K

5%

4

5

3

Q2640

SOT-363

2N7002DW-X-G

21

R2640

20K

MF

1/20W

5%

201

1

2

6

Q2640

2N7002DW-X-G

SOT-363

2

1

C2641

NOSTUFF

201

25V

100PF

CERM

5%

2

1

C2640

6.3V

0.47UF

CERM-X5R 402

10%

2

1

C2619

201

25V

NP0-C0G

5%

CRITICAL

18PF

21

R2630

MF

1/20W

5%

1M

CRITICAL

201

2

1

C2620

201

NP0-C0G

25V

5%

18PF

CRITICAL

2

1

C2607

4.7UF

20%

6.3V

X5R-CERM1

402

BYPASS=U2600.23::5mm

2

1

R2600

201

1/20W

12K

1%

MF

CRITICAL

6

39 68

18 68

6

39 68

8

68

8

68

2

1

C2615

0201

0.1UF

X5R-CERM

16V

10%

2

1

C2616

0201

20%

6.3V X5R

1UF

2

1

R2620

201

1/20W MF

10K

5%

2

1

C2617

X5R-CERM

0.1UF

10% 16V

0201

2

1

C2618

0201

20%

6.3V X5R

1UF

2

1

C2608

0201

BYPASS=U2600.29::2mm

16V

10%

X5R-CERM

0.1UF

2

1

C2602

BYPASS=U2600.5::5mm

20%

4.7UF

6.3V

402

X5R-CERM1

2

1

C2609

0.1UF

10%

0201

X5R-CERM

16V

BYPASS=U2600.5::2mm

2

1

C2610

X5R-CERM

0201

16V

0.1UF

10%

BYPASS=U2600.10::2mm

2

1

C2603

BYPASS=U2600.34::2mm

0.1UF

16V

10%

0201

X5R-CERM

18 23

2

1

R2642

201

5%

MF

1/20W

100K

8

6

39

21

R2605

201

1/20W

MF

100

5%

21

D2600

SOD-523

BAT54XV2T1

2

1

R2606

5% 1/20W MF

10K

201

2

1

R2607

201

10K

MF

5% 1/20W

2

1

R2604

10K

HUB1_NONREM0_0

5% 1/20W MF 201

2

1

R2603

5%

10K

1/20W MF 201

HUB1_NONREM0_1

2

1

R2601

5%

HUB1_NONREM1_1

10K

1/20W

MF

201

2

1

R2602

5%

10K

HUB1_NONREM1_0

1/20W

MF

201

2

1

C2668

0201

X5R

20%

6.3V

1UF

2

1

C2667

0201

X5R-CERM

0.1UF

10% 16V

2

1

C2666

0201

6.3V

1UF

X5R

20%

2

1

C2665

0201

X5R-CERM

10% 16V

0.1UF

2

1

C2660

10%

X5R-CERM

0201

16V

0.1UF

BYPASS=U2650.5::2mm

2

1

R2670

201

10K

5% 1/20W MF

2

1

R2650

201

MF

1/20W

1%

12K

CRITICAL

18 68

2

1

C2661

0201

16V

X5R-CERM

10%

0.1UF

BYPASS=U2650.34::2mm

2

1

C2652

BYPASS=U2650.5::5mm

20%

6.3V

4.7UF

402

X5R-CERM1

2

1

C2659

0201

0.1UF

10% 16V

X5R-CERM

BYPASS=U2650.29::2mm

2

1

C2658

0.1UF

10%

0201

X5R-CERM

BYPASS=U2650.10::2mm

16V

2

1

C2657

20%

6.3V

BYPASS=U2650.23::5mm

X5R-CERM1

4.7UF

402

21

R2655

201

MF

5%

100

1/20W

2

1

R2657

1/20W MF 201

10K

5%

2

1

R2656

1/20W

201

5%

10K

MF

2

1

R2653

HUB2_NONREM0_1

10K

5%

MF

1/20W

201

2

1

R2651

10K

5%

HUB2_NONREM1_1

MF

1/20W

201

2

1

R2654

5%

10K

HUB2_NONREM0_0

1/20W MF 201

2

1

R2652

10K

5%

HUB2_NONREM1_0

1/20W

MF

201

48

6

36 68

6

36 68

38 68

8

38

32

33

3629231510

5

27

31

7

4

2

30

6

3

1

37

11

28

22

24

26

35

18

16

12

34

19

17

13

21

20

9

8

25

14

U2600

QFN

USB2513B

OMIT_TABLE

32

33

3629231510

5

27

31

7

4

2

30

6

3

1

37

11

28

22

24

26

35

18

16

12

34

19

17

13

21

20

9

8

25

14

U2650

USB2513B

QFN

OMIT_TABLE

2

1

C2611

0201

0.1UF

16V

10%

BYPASS=U2600.23::2mm

X5R-CERM

2

1

C2612

16V

10%

0.1UF

BYPASS=U2600.15::2mm

0201

X5R-CERM

2

1

C2662

0201

0.1UF

10% 16V

X5R-CERM

BYPASS=U2650.15::2mm

2

1

C2653

X5R-CERM

0201

0.1UF

10% 16V

BYPASS=U2650.23::2mm

8

68

8

68

21

Y2600

24.000M-150PPM-6PF

2X1.6X0.65-SM

CRITICAL

21

Y2650

24.000M-150PPM-6PF

2X1.6X0.65-SM

CRITICAL

2

1

C2670

201

NP0-C0G

25V

5%

18PF

CRITICAL

21

R2680

201

MF

1/20W

5%

1M

CRITICAL

2

1

C2669

18PF

201

25V

NP0-C0G

5%

CRITICAL

21

R2690

201

5%

1/20W

MF

0

HUB2_NONREM1_1,HUB2_NONREM0_1

HUB2_3NONREM

HUB1_NONREM1_0,HUB1_NONREM0_0

HUB1_ALLREM

HUB1_NONREM1_1,HUB1_NONREM0_0

HUB1_2NONREM

HUB1_NONREM1_1,HUB1_NONREM0_1

HUB1_3NONREM

U2600,U2650

USBHUB_2514

CRITICAL

SMSC USB2514

2

338S0720

HUB1_NONREM1_0,HUB1_NONREM0_1

HUB1_1NONREM

SMSC USX2513B

USBHUB_2513B

338S0923

2

CRITICAL

U2600,U2650

338S0824

2

U2600,U2650

USBHUB_2514B

CRITICAL

SMSC USB2514B

HUB2_2NONREM

HUB2_NONREM1_1,HUB2_NONREM0_0

HUB2_NONREM1_0,HUB2_NONREM0_1

HUB2_1NONREM

HUB2_NONREM1_0,HUB2_NONREM0_0

HUB2_ALLREM

SYNC_MASTER=K21_MLB

SYNC_DATE=12/13/2010

USB HUBS

USB_HUB_SOFT_RESET_L_R

PPUSB_HUB2_CRFILT

MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.8V

MIN_LINE_WIDTH=0.4MM

USB_HUB2_XTAL2

USB_HUB2_XTAL1

USB_TPAD_HUB_P

PPUSB_HUB2_PLLFILT

MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.8V

MIN_LINE_WIDTH=0.4MM

USB_HUB2_NONREM0

USB_HUB2_NONREM1

USB_HUB2_CFG_SEL0

USB_HUB2_CFG_SEL1

USB_HUB2_TEST

USB_HUB_RESET_L

USB_HUB2_UP_P

NC_USB_HUB2_PRTPWR4

USB_EXTA_OC_L

TP_USB_HUB2_OCS1 NC_USB_HUB2_OCS2

USB_HUB2_UP_N

USB_HUB2_RBIAS

USB_HUB2_VBUS_DET

=USB_HUB2_OCS4

USB_EXTA_P

USB_EXTA_N

USB_TPAD_HUB_N

USB_BT_P

USB_BT_N

NC_USB_HUB2_PRTPWR3

TP_USB_HUB2_PRTPWR1 NC_USB_HUB2_PRTPWR2

P3V3S3_EN_RC

=PP3V3_S3_USB_HUB

USB_HUB_RESET_L

=PP3V3_S5_USB_RESET

USB_HUB_RESET

=PP3V3_S3_USB_RESET

=PP3V3_S3_USB_HUB

NC_USB_HUB1_PRTPWR2

TP_USB_HUB1_PRTPWR1

NC_USB_HUB1_PRTPWR3

USB_T29A_N USB_T29A_P

USB_SDCARD_N USB_SDCARD_P

USB_EXTD_N USB_EXTD_P

=USB_HUB1_OCS4

USB_HUB1_VBUS_DET

USB_HUB1_RBIAS

USB_HUB1_UP_N

NC_USB_HUB1_OCS2

TP_USB_HUB1_OCS1

USB_EXTD_OC_L

NC_USB_HUB1_PRTPWR4

USB_HUB1_UP_P

USB_HUB_RESET_L

USB_HUB1_TEST

USB_HUB1_CFG_SEL1

USB_HUB1_CFG_SEL0

USB_HUB1_NONREM1

USB_HUB1_NONREM0

MIN_LINE_WIDTH=0.4MM

PPUSB_HUB1_CRFILT

MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.4MM

PPUSB_HUB1_PLLFILT

USB_HUB1_XTAL2

USB_HUB1_XTAL1

=PP3V3_S3_USB_HUB

USB_HUB_SOFT_RESET_L

26 OF 109

2.5.0

051-8871

24 OF 74

24

7 8

24

7

7 8

24

7 8

24

7 8

24

OUT

PAD

+3.42V

VDD_25M

+V3.3A

VDDIO_25M_C

VDDIO_25M_B

VDDIO_25M_A

25MHZ_C

25MHZ_B

25MHZ_A

X1

X2

VDD_RTC_OUT

THRM

GND

32KHZ_A

NC NC

OUT

IN

NC

OUT

IN

OUT

IN

BIIN

NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Buffered

VTT voltage divider on CPU page

System RTC Power Source & 32kHz / 25MHz Clock Generator

Powered in S0

GreenClk 25MHz Power

For SB RTC Power

create VDD_RTC_OUT.

available ~3.3V power

Platform Reset Connections

Series R is R3803

No bypass necessary

internally ORed to

+V3.3A should be first

to reduce VBAT draw.

SB XTAL Power

T29 XTAL Power

Unbuffered

No Coin-Cell: 3.3V S5

Coin-Cell & No G3Hot: 3.3V S5

Coin-Cell & G3Hot: 3.42V G3Hot

No Coin-Cell: 3.42V G3Hot (no RC)

Coin-Cell: VBAT (300-ohm & 10uF RC)

UNUSED clock terminations for FCIM MODE

CLOCK (CK505)

VBAT and +V3.3A are

outputs for power savings

Ground VDDIO of unused CLK

PCH Reset Button

PCH S0 PWRGD

NOTE: 30 PPM crystal required

2

1

R2757

201

MF

1/20W

5%

10K

16 69

33 69

2

1

C2702

1UF

10%

10V

X5R

402-1

2

1

C2710

402-1

X5R

10%

1UF

10V

3

4

14

6

11

1

5172

13

16107

12

15

8

9

U2700

SLG3NB148V

CRITICAL

TQFN

31

42

Y2705

CRITICAL

25.000MHZ-12PF-20PPM

SM-3.2X2.5MM

21

C2705

5%

25V

NP0-C0G

201

12PF

21

C2706

12PF

5%

25V

NP0-C0G

201

69

6

42

40

36

31

23

35

65

10 23

21

R2783

201

5%

33

1/20W

MF

21

R2788

5%

0

1/20W

MF

201

21

R2781

201

MF

1/20W

33

5%

21

R2771

5%

0

1/20W

MF

201

18 26

21

R2789

1K

5%

XDP

1/20W

MF

201

21

R2793

0

5%

MF

201

1/20W

2

1

R2780

100K

5% 1/20W

201

MF

4

5

3

2

U2780

SC70

74LVC1G07

2

1

C2780

0.1UF

16V

X5R-CERM

0201

10%

40 69

6

42 69

16 68

21

R2727

201

MF

1/20W

PLACE_NEAR=U1800.G51:5.1mm

5%

22

21

R2726

201

MF

1/20W

22

5%

PLACE_NEAR=U1800.E49:5.1mm

21

R2729

201

MF

1/20W

5%

22

PLACE_NEAR=U1800.G45:2.54MM:5.1mm

18 69

18

17 23

17 19

17

2

1

R2761

201

5%

1/20W

MF

0

NO STUFF

PLACE_NEAR=U1800.M10:5.54mm

21

R2763

201

5%

1/20W

MF

0

NO STUFF

21

R2762

201

5%

1/20W

MF

3.0K

21

R2760

201

5%

1/20W

MF

0

2

1

C2760

0201

16V X5R-CERM

10%

0.1UF

5

4

1

2

3

U2760

MC74VHC1G08

SC70-HF

2

1

C2750

0201

0.1UF

10%

X5R-CERM

16V

5

4

1

2

3

U2750

MC74VHC1G08

SC70-HF

2

1

R2750

201

MF

1/20W

1K

5%

23 40 51 61

56

17 40

2

1

R2797

OMIT

SILK_PART=SYS RESET

MF-LF

1/16W

5%

0

402

2

1

R2795

5%

1/16W

MF-LF

10K

402

21

R2796

XDP

5%

0

MF-LF

1/16W

402

10 23 66

2

1

C2722

0201

X5R-CERM

0.1UF

10%

16V

2

1

C2724

16V

10%

0.1UF

X5R-CERM

0201

21

R2705

201

0

5%

MF

1/20W

2

1

R2706

201

1/20W

5%

NO STUFF

1M

MF

2

1

R2751

10K

5%

1/20W

MF

201

2

1

R2752

10K

5%

1/20W

MF

201

2

1

R2753

5%

1/20W

MF

201

10K

2

1

R2754

10K

5%

1/20W

MF

201

2

1

R2755

10K

5%

1/20W

MF

201

2

1

R2756

201

MF

1/20W

5%

10K

SYNC_MASTER=K21_MLB

SYNC_DATE=11/30/2010

Clock (CK505) and Chipset Support

PCIE_CLK100M_PCH_P

PCH_CLK14P3M_REFCLK

BKLT_PLT_RST_L

CPU_RESET_L

=PPVBAT_G3_SYSCLK

ALL_SYS_PWRGD

CPUIMVP_PGOOD

=PPVRTC_G3_OUT

SYSCLK_CLK25M_T29

SYSCLK_CLK25M_SB

SYSCLK_CLK32K_RTC

SMC_LRESET_L

LPC_RESET_L

LPC_CLK33M_LPCPLUS

LPC_CLK33M_SMC

PCH_CLK33M_PCIIN

PCH_CLK33M_PCIOUT

SYS_PWROK_R

=PP3V3_S5_PCHPWRGD

PM_PCH_SYS_PWROK

PM_PCH_APWROK

PCH_CLK96M_DOT_P

=PP3V3_S0_RSTBUF

LPCPLUS_RESET_L

MAKE_BASE=TRUE

PLT_RST_BUF_L

=PP3V3_S5_SYSCLK

=PPVDDIO_S0_SBCLK

=PPVDDIO_T29_CLK

=PP3V3_S0_SYSCLKGEN

=PP3V3_S0_SB_PM

=PP3V3_S5_PCHPWRGD

PM_S0_PGOOD

SMC_DELAYED_PWRGD

SYSCLK_CLK25M_X2_R

PM_PCH_PWROK

MAKE_BASE=TRUE

=PP3V3_S0_SB_PM

LPC_CLK33M_SMC_R

LPC_CLK33M_LPCPLUS_R

PCH_CLK96M_DOT_N

PCH_CLK100M_SATA_P

PCH_CLK100M_SATA_N

PCIE_CLK100M_PCH_N

=T29_RESET_L

XDPPCH_PLTRST_L

PCA9557D_RESET_L

AP_RESET_L

PLT_RESET_L

MAKE_BASE=TRUE

XDP_DBRESET_L

PM_SYSRST_L

SYSCLK_CLK25M_X1

SYSCLK_CLK25M_X2

27 OF 109

2.5.0

051-8871

25 OF 74

1

16 68

7

25

16 68

7

25

7

25

35 40

7

25

16 68

IN

D

SG

D

SG

D

SG

D

SG

OUT

D

SG

D

SG

IN

OUT

G

D

S

D

SG

IN

D

SG

IN

D

SG

D

SG

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

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PAGE TITLE

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

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345678

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8 7 5 4 2 1

Step ISOLATE_CPU_MEM_L PLT_RESET_L PM_SLP_S3_L PM_SLP_S4_L CPU_MEM_RESET_L MEM_RESET_L MEMVTT_EN P1V5CPU_EN

0 1 1 1 1 1 CPU_MEM_RESET_L 1 1

1 0 1 1 1 1 1 1 1

2 0 0 1 1 1 1 0 1

MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L

The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well

WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated.

as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary.

ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals.

WHEN LOW: CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.

MEMVTT_EN = (ISOLATE_CPU_MEM_L + PLT_RST_L) * PM_SLP_S3_L

P1V5CPU_EN = (ISOLATE_CPU_MEM_L + PM_SLP_S3_L) * PM_SLP_S4_L

6 0 1 1 1 1 1 1 1

(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO.

NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0

5 0 1 1 1 0 (*) 1 1 1

must deassert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L.

transition. Rails will power-up as if from S3, but MEM_RESET_L will not properly assert. Software

7 1 1 1 1 1 CPU_MEM_RESET_L 1 1

4 0 0 1 1 X 1 0 1

3 0 0 0 1 X 1 0 0

S0

to

S3

to

S0

1V5 S0 "PGOOD" for CPU

PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page

75mA max load @ 0.75V

60mW max power

Ensures CKE signals are held low in S3

MEMVTT Clamp

17 40 48 61

2

1

R2810

CPUMEM_S0

10K

5% 1/20W MF 201

18 25

1

2

6

Q2810

CPUMEM_S0

SSM6N37FEAPE

SOT563

4

5

3

Q2810

SOT563

SSM6N37FEAPE

CPUMEM_S0

2

1

R2801

201

MF

5%

100K

CPUMEM_S0

1/20W

4

5

3

Q2800

CPUMEM_S0

SSM6N37FEAPE

SOT563

2

1

R2802

CPUMEM_S0

100K

5%

1/20W

MF

201

1

2

6

Q2800

CPUMEM_S0

SSM6N37FEAPE

SOT563

60

2

1

R2816

1/20W

20K

MF

CPUMEM_S0

5%

201

27 28 29 30

4

5

3

Q2815

SOT563

SSM6N37FEAPE

CPUMEM_S0

21

R2817

0

MF

5%

1/20W

201

CPUMEM_S3

1

2

6

Q2815

CPUMEM_S0

SSM6N37FEAPE

SOT563

19 23

2

1

R2815

100K

5% MF

201

CPUMEM_S0

1/20W

10

10 17 66

2

1

R2805

CPUMEM_S0

10K

5% 1/20W MF 201

2

1

R2850

CPUMEM_S0

10

MF-LF

603

5%

1/10W

1

2

6

Q2820

CRITICAL

DMB53D0UV

SOT-563

2

1

R2822

10K

5% 1/20W MF 201

4

3

5

Q2820

CRITICAL

DMB53D0UV

SOT-563

2

1

C2820

10%

1000PF

201

X7R

16V

NO STUFF

1

2

6

Q2850

SSM6N37FEAPE

CPUMEM_S0

SOT563

2

1

C2851

NO STUFF

10%

1000PF

201

X7R

16V

2

1

R2851

CPUMEM_S0

100K

5%

1/20W

MF

201

17 40 61

4

5

3

Q2850

CPUMEM_S0

SSM6N37FEAPE

SOT563

2

1

R2820

27.4K

1%

1/20W

MF

201

2

1

R2821

33.2K

1%

1/20W

MF

201

8

55

21

R2890

CPUMEM_S0

0

201

5%

MF

1/20W

2

1

C2817

402

10% 16V X7R

0.047UF

2

1

C2816

NO STUFF

0.1UF

0201

X5R-CERM

16V

10%

1

2

6

Q2805

CPUMEM_S0

SSM6N37FEAPE

SOT563

4

5

3

Q2805

CPUMEM_S0

SSM6N37FEAPE

SOT563

8

SYNC_DATE=12/13/2010

SYNC_MASTER=K21_MLB

CPU Memory S3 Support

CPU_MEM_RESET_L

MAKE_BASE=TRUE

PLT_RESET_L

PM_SLP_S4_L

P1V5CPU_EN

PM_SLP_S3_L

MEMVTT_EN_L

PM_MEM_PWRGD

=PP3V3_S5_CPU_VCCDDR

=PP1V5_S3_CPU_VCCDDR

VTTCLAMP_L

PM_MEM_PWRGD_L

=PP5V_S3_MEMRESET

VTTCLAMP_EN

=DDRVTT_EN

P1V5_S0_DIV

=PPVTT_S0_VTTCLAMP

=PP3V3_S3_MEMRESET

=PP5V_S3_MEMRESET

MEMVTT_EN

P1V5CPU_EN_L

ISOLATE_CPU_MEM_L

ISOLATE_CPU_MEM_L_R

=MEM_RESET_L

MEMRESET_ISOL_LS5V_L

=PP1V5_S3_MEMRESET

MEM_RESET_L

28 OF 109

2.5.0

051-8871

26 OF 74

7

10 12 15

7

26

7

26

7

VSS

A5

A1

A0

VSSQ

DQ0 DQ1 DQ2

A9

A8

A14

ZQ

RESET*

ODT

DQS*

DQS

DM/TDQS

A6

A12/BC*

NF/DQ7

NF/DQ6

NF/DQ5

NF/DQ4

DQ3

NF/TDQS*

NC

VREFCA

BA1

CK

CKE

CK*

CS*

WE*

RAS*

A2 A3 A4

A7

A10/AP

A13

BA0

BA2

CAS*

VDD

VDDQ

A11

VREFDQ

VSS

A5

A1

A0

VSSQ

DQ0 DQ1 DQ2

A9

A8

A14

ZQ

RESET*

ODT

DQS*

DQS

DM/TDQS

A6

A12/BC*

NF/DQ7

NF/DQ6

NF/DQ5

NF/DQ4

DQ3

NF/TDQS*

NC

VREFCA

BA1

CK

CKE

CK*

CS*

WE*

RAS*

A2 A3 A4

A7

A10/AP

A13

BA0

BA2

CAS*

VDD

VDDQ

A11

VREFDQ

VSS

A5

A1

A0

VSSQ

DQ0 DQ1 DQ2

A9

A8

A14

ZQ

RESET*

ODT

DQS*

DQS

DM/TDQS

A6

A12/BC*

NF/DQ7

NF/DQ6

NF/DQ5

NF/DQ4

DQ3

NF/TDQS*

NC

VREFCA

BA1

CK

CKE

CK*

CS*

WE*

RAS*

A2 A3 A4

A7

A10/AP

A13

BA0

BA2

CAS*

VDD

VDDQ

A11

VREFDQ

VSS

A5

A1

A0

VSSQ

DQ0 DQ1 DQ2

A9

A8

A14

ZQ

RESET*

ODT

DQS*

DQS

DM/TDQS

A6

A12/BC*

NF/DQ7

NF/DQ6

NF/DQ5

NF/DQ4

DQ3

NF/TDQS*

NC

VREFCA

BA1

CK

CKE

CK*

CS*

WE*

RAS*

A2 A3 A4

A7

A10/AP

A13

BA0

BA2

CAS*

VDD

VDDQ

A11

VREFDQ

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

NC

NC NC

A14/A15 FOR 2G/4G MONO ONLY

NCNC

NC

CS1 IS FOR 2G DDP RANK CONTROL

NC

NC NC

NCNC

NC

NC NC

NC

NC NC NC

NC

2

1

C2932

0.47UF

4V CERM-X5R-1 201

20%

21

R2930

240

MF

1%

1/20W

201

21

R2920

240

MF

1%

1/20W

201

2

1

C2912

4V

201

20%

CERM-X5R-1

0.47UF

2

1

C2911

4V

CERM-X5R-1

201

0.47UF

20%

2

1

C2910

0.47UF

4V

CERM-X5R-1

201

20%

2

1

C2902

4V CERM-X5R-1 201

0.47UF

20%

2

1

C2901

20%

CERM-X5R-1

4V

201

0.47UF

2

1

C2900

CERM-X5R-1

4V

201

20%

0.47UF

2

1

C2931

4V

CERM-X5R-1

201

0.47UF

20%

21

R2910

240

201

1/20W

1%

MF

21

R2900

240

MF

1%

1/20W

201

H9

H4

D10

C10

B9D2B3

J10

F9

D9A9F3N2L2

J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

J8

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3

G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

N8

N4

K8

M8

H8

L8

K4

U2900

DDR3-1333

FBGA

OMIT_TABLE

H9

H4

D10

C10

B9D2B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9

D8

A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

J8

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3

G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

N8

N4

K8

M8

H8

L8

K4

U2910

FBGA

OMIT_TABLE

DDR3-1333

H9

H4

D10

C10

B9D2B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

J8

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3

G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

N8

N4

K8

M8

H8

L8

K4

U2920

DDR3-1333

FBGA

OMIT_TABLE

H9

H4

D10

C10

B9D2B3

J10

F9

D9A9F3N2L2

J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

J8

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3

G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

N8

N4

K8

M8

H8

L8

K4

U2930

DDR3-1333

FBGA

OMIT_TABLE

2

1

C2930

4V

CERM-X5R-1

201

0.47UF

20%

2

1

C2922

4V

201

CERM-X5R-1

20%

0.47UF

2

1

C2921

4V

CERM-X5R-1

201

20%

0.47UF

2

1

C2920

4V

CERM-X5R-1

201

0.47UF

20%

DDR3 DRAM CHANNEL A (0-31)

SYNC_DATE=12/13/2010

SYNC_MASTER=K21_MLB

PP0V75_S3_MEM_VREFCA_A

PP0V75_S3_MEM_VREFDQ_A

MEM_A_A<11>

MEM_A_CAS_L

MEM_A_BA<2>

MEM_A_BA<0>

MEM_A_A<13>

MEM_A_A<10>

MEM_A_A<7>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_A<2>

MEM_A_CLK_N<0>

MEM_A_CKE<0>

MEM_A_CLK_P<0>

MEM_A_BA<1>

PP0V75_S3_MEM_VREFCA_A

MEM_A_DQ<12>

MEM_A_DQ<10>

MEM_A_DQ<11>

MEM_A_DQ<13>

MEM_A_DQ<15>

MEM_A_A<12>

MEM_A_A<6>

MEM_A_DQS_P<1>

MEM_A_DQS_N<1>

MEM_A_ODT<0>

MEM_RESET_L

MEM_A_ZQ1

MEM_A_A<14>

MEM_A_A<8>

MEM_A_A<9>

MEM_A_DQ<9>

MEM_A_DQ<14>

MEM_A_DQ<8>

MEM_A_A<0>

MEM_A_A<1>

MEM_A_A<5>

=PP1V5_S3_MEM_A

PP0V75_S3_MEM_VREFDQ_A

MEM_A_A<11>

MEM_A_CAS_L

MEM_A_BA<2>

MEM_A_BA<0>

MEM_A_A<13>

MEM_A_A<10>

MEM_A_A<7>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_A<2>

MEM_A_RAS_L

MEM_A_WE_L

MEM_A_CS_L<0>

MEM_A_CLK_N<0>

MEM_A_CKE<0>

MEM_A_CLK_P<0>

MEM_A_BA<1>

PP0V75_S3_MEM_VREFCA_A

MEM_A_DQ<20>

MEM_A_DQ<22>

MEM_A_DQ<16>

MEM_A_DQ<18>

MEM_A_DQ<21>

MEM_A_A<12>

MEM_A_A<6>

MEM_A_DQS_P<2>

MEM_A_DQS_N<2>

MEM_A_ODT<0>

MEM_RESET_L

MEM_A_ZQ2

MEM_A_A<14>

MEM_A_A<8>

MEM_A_A<9>

MEM_A_DQ<23>

MEM_A_DQ<17>

MEM_A_DQ<19>

MEM_A_A<0>

MEM_A_A<1>

MEM_A_A<5>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_A<11>

MEM_A_CAS_L

MEM_A_BA<2>

MEM_A_BA<0>

MEM_A_A<13>

MEM_A_A<10>

MEM_A_A<7>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_A<2>

MEM_A_WE_L

MEM_A_CS_L<0>

MEM_A_CLK_N<0>

MEM_A_CKE<0>

MEM_A_CLK_P<0>

MEM_A_BA<1>

PP0V75_S3_MEM_VREFCA_A

MEM_A_DQ<26>

MEM_A_DQ<29>

MEM_A_DQ<24>

MEM_A_DQ<30>

MEM_A_DQ<31>

MEM_A_A<12>

MEM_A_A<6>

MEM_A_DQS_P<3>

MEM_A_DQS_N<3>

MEM_A_ODT<0>

MEM_RESET_L

MEM_A_ZQ3

MEM_A_A<14>

MEM_A_A<8>

MEM_A_A<9>

MEM_A_DQ<27>

MEM_A_DQ<25>

MEM_A_DQ<28>

MEM_A_A<0>

MEM_A_A<1>

MEM_A_A<5>

=PP1V5_S3_MEM_A=PP1V5_S3_MEM_A

MEM_A_RAS_L

MEM_A_CS_L<0>

MEM_A_WE_L

MEM_A_RAS_L

MEM_A_A<5>

MEM_A_A<1>

MEM_A_A<0>

MEM_A_DQ<7>

MEM_A_DQ<1>

MEM_A_DQ<0>

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<14>

MEM_RESET_L

MEM_A_ODT<0>

MEM_A_DQS_N<0>

MEM_A_DQS_P<0>

MEM_A_A<6>

MEM_A_A<12>

MEM_A_DQ<6>

MEM_A_DQ<5>

MEM_A_DQ<2>

MEM_A_DQ<4>

MEM_A_DQ<3>

MEM_A_BA<1>

MEM_A_CLK_P<0>

MEM_A_CKE<0>

MEM_A_CLK_N<0>

MEM_A_CS_L<0>

MEM_A_WE_L

MEM_A_RAS_L

MEM_A_A<2>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_A<7>

MEM_A_A<10>

MEM_A_A<13>

MEM_A_BA<0>

MEM_A_BA<2>

MEM_A_CAS_L

MEM_A_A<11>

PP0V75_S3_MEM_VREFDQ_A

=PP1V5_S3_MEM_A

MEM_A_ZQ0

27 OF 74

051-8871

2.5.0

29 OF 109

27 28 29 30 31 67

9

27 28 29 30 31 67

11 27 28 32 67

27 28 29 30 31 67

11 67

11 27 28 32 67

11 67

11 27 28 32 67

26 27 28 29 30

11 27 28 32 67

11 67

11 67 11 27 28 32 67

11 27 28 32 67

7

27 28 32

9

27 28 29 30 31 67

11 27 28 32 67

27 28 29 30 31 67

11 67

11 27 28 32 67

11 67

11 27 28 32 67

26 27 28 29 30

11 27 28 32 67

11 67

11 67 11 27 28 32 67

11 27 28 32 67

9

27 28 29 30 31 67

11 27 28 32 67

27 28 29 30 31 67

11 67

11 27 28 32 67

11 67

11 27 28 32 67

26 27 28 29 30

11 27 28 32 67

11 67

11 67 11 27 28 32 67

11 27 28 32 67

7

27 28 32

7

27 28 32

11 27 28 32 67

11 27 28 32 67 11 67

11 67

11 27 28 32 67

26 27 28 29 30

11 27 28 32 67

11 67

11 27 28 32 67

11 67

11 27 28 32 67

9

27 28 29

30 31 67

7

27 28 32

VSS

A5

A1

A0

VSSQ

DQ0 DQ1 DQ2

A9

A8

A14

ZQ

RESET*

ODT

DQS*

DQS

DM/TDQS

A6

A12/BC*

NF/DQ7

NF/DQ6

NF/DQ5

NF/DQ4

DQ3

NF/TDQS*

NC

VREFCA

BA1

CK

CKE

CK*

CS*

WE*

RAS*

A2 A3 A4

A7

A10/AP

A13

BA0

BA2

CAS*

VDD

VDDQ

A11

VREFDQ

VSS

A5

A1

A0

VSSQ

DQ0 DQ1 DQ2

A9

A8

A14

ZQ

RESET*

ODT

DQS*

DQS

DM/TDQS

A6

A12/BC*

NF/DQ7

NF/DQ6

NF/DQ5

NF/DQ4

DQ3

NF/TDQS*

NC

VREFCA

BA1

CK

CKE

CK*

CS*

WE*

RAS*

A2 A3 A4

A7

A10/AP

A13

BA0

BA2

CAS*

VDD

VDDQ

A11

VREFDQ

VSS

A5

A1

A0

VSSQ

DQ0 DQ1 DQ2

A9

A8

A14

ZQ

RESET*

ODT

DQS*

DQS

DM/TDQS

A6

A12/BC*

NF/DQ7

NF/DQ6

NF/DQ5

NF/DQ4

DQ3

NF/TDQS*

NC

VREFCA

BA1

CK

CKE

CK*

CS*

WE*

RAS*

A2 A3 A4

A7

A10/AP

A13

BA0

BA2

CAS*

VDD

VDDQ

A11

VREFDQ

VSS

A5

A1

A0

VSSQ

DQ0 DQ1 DQ2

A9

A8

A14

ZQ

RESET*

ODT

DQS*

DQS

DM/TDQS

A6

A12/BC*

NF/DQ7

NF/DQ6

NF/DQ5

NF/DQ4

DQ3

NF/TDQS*

NC

VREFCA

BA1

CK

CKE

CK*

CS*

WE*

RAS*

A2 A3 A4

A7

A10/AP

A13

BA0

BA2

CAS*

VDD

VDDQ

A11

VREFDQ

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

NC

CS1 IS FOR 2G DDP RANK CONTROL

A14/A15 FOR 2G/4G MONO ONLY

NC

NC NC

NC

NC NC

NC

NC NC

NC

NC NC NC NC NC

NC NC

NC

NC NC NC NC NC NC NC NC NC NC

NC

2

1

C3022

0.47UF

4V CERM-X5R-1 201

20%

2

1

C3021

4V

CERM-X5R-1

201

0.47UF

20%

2

1

C3020

4V

CERM-X5R-1

201

0.47UF

20%

21

R3020

240

MF

1%

1/20W

201

2

1

C3012

0.47UF

4V CERM-X5R-1 201

20%

2

1

C3032

4V CERM-X5R-1 201

0.47UF

20%

2

1

C3011

4V

CERM-X5R-1

201

0.47UF

20%

2

1

C3010

4V

CERM-X5R-1

201

0.47UF

20%

21

R3010

201

240

MF

1%

1/20W

2

1

C3002

0.47UF

4V CERM-X5R-1 201

20%

2

1

C3001

4V

CERM-X5R-1

201

0.47UF

20%

2

1

C3000

4V

CERM-X5R-1

201

0.47UF

20%

21

R3000

201

1/20W

1%

MF

240

2

1

C3031

CERM-X5R-1

4V

201

0.47UF

20%

H9

H4

D10

C10

B9D2B3

J10

F9

D9A9F3N2L2

J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

J8

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3

G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

N8

N4

K8

M8

H8

L8

K4

U3000

OMIT_TABLE

FBGA

DDR3-1333

H9

H4

D10

C10

B9D2B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9

D8

A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

J8

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3

G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

N8

N4

K8

M8

H8

L8

K4

U3010

DDR3-1333

FBGA

OMIT_TABLE

H9

H4

D10

C10B9

D2

B3

J10F9

D9A9F3

N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

J8

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3

G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

N8

N4

K8

M8

H8

L8

K4

U3020

DDR3-1333

FBGA

OMIT_TABLE

H9

H4

D10

C10B9

D2

B3

J10F9

D9A9F3N2L2

J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

J8

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3

G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

N8

N4

K8

M8

H8

L8

K4

U3030

OMIT_TABLE

DDR3-1333

FBGA

2

1

C3030

4V

CERM-X5R-1

201

0.47UF

20%

21

R3030

240

MF

1%

1/20W

201

SYNC_DATE=12/13/2010

SYNC_MASTER=K21_MLB

DDR3 DRAM CHANNEL A (32-63)

PP0V75_S3_MEM_VREFDQ_A

MEM_A_A<11>

MEM_A_CAS_L

MEM_A_BA<2>

MEM_A_BA<0>

MEM_A_A<13>

MEM_A_A<10>

MEM_A_A<7>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_A<2>

MEM_A_RAS_L

MEM_A_WE_L

MEM_A_CS_L<0>

MEM_A_CLK_N<0>

MEM_A_CKE<0>

MEM_A_CLK_P<0>

PP0V75_S3_MEM_VREFCA_A

MEM_A_DQ<47>

MEM_A_DQ<42>

MEM_A_A<12>

MEM_A_A<6>

MEM_A_DQS_P<5>

MEM_A_DQS_N<5>

MEM_A_ODT<0>

MEM_RESET_L

MEM_A_ZQ9

MEM_A_A<14>

MEM_A_A<8>

MEM_A_A<9>

MEM_A_DQ<41>

MEM_A_A<1>

MEM_A_A<5>

MEM_A_A<0>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_A<11>

MEM_A_CAS_L

MEM_A_BA<2>

MEM_A_BA<0>

MEM_A_A<13>

MEM_A_A<10>

MEM_A_A<7>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_A<2>

MEM_A_RAS_L

MEM_A_WE_L

MEM_A_CS_L<0>

MEM_A_CLK_N<0>

MEM_A_CKE<0>

MEM_A_CLK_P<0>

MEM_A_BA<1>

PP0V75_S3_MEM_VREFCA_A

MEM_A_DQ<56>

MEM_A_DQ<58>

MEM_A_DQ<61>

MEM_A_DQ<62>

MEM_A_DQ<60>

MEM_A_A<12>

MEM_A_A<6>

MEM_A_DQS_P<7>

MEM_A_DQS_N<7>

MEM_RESET_L

MEM_A_ZQ11

MEM_A_A<14>

MEM_A_A<8>

MEM_A_A<9>

MEM_A_DQ<63>

MEM_A_DQ<57>

MEM_A_DQ<59>

MEM_A_A<0>

MEM_A_A<1>

MEM_A_A<5>

=PP1V5_S3_MEM_A

MEM_A_ODT<0>

=PP1V5_S3_MEM_A

MEM_A_BA<1>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_A<11>

MEM_A_CAS_L

MEM_A_BA<2>

MEM_A_BA<0>

MEM_A_A<13>

MEM_A_A<10>

MEM_A_A<7>

MEM_A_A<4>

MEM_A_A<2>

MEM_A_RAS_L

MEM_A_WE_L

MEM_A_CS_L<0>

MEM_A_CLK_N<0>

MEM_A_CKE<0>

MEM_A_CLK_P<0>

MEM_A_BA<1>

PP0V75_S3_MEM_VREFCA_A

MEM_A_DQ<35>

MEM_A_DQ<36>

MEM_A_DQ<37>

MEM_A_DQ<38>

MEM_A_DQ<32>

MEM_A_A<12>

MEM_A_A<6>

MEM_A_DQS_P<4>

MEM_A_DQS_N<4>

MEM_A_ODT<0>

MEM_RESET_L

MEM_A_ZQ8

MEM_A_A<14>

MEM_A_A<8>

MEM_A_A<9>

MEM_A_DQ<34>

MEM_A_DQ<33>

MEM_A_DQ<39>

MEM_A_A<0>

MEM_A_A<1>

MEM_A_A<5>

=PP1V5_S3_MEM_A

MEM_A_A<3>

MEM_A_DQ<40>

MEM_A_A<5>

MEM_A_A<1>

MEM_A_A<0>

MEM_A_DQ<50>

MEM_A_DQ<49>

MEM_A_DQ<55>

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<14>

MEM_A_ZQ10

MEM_RESET_L

MEM_A_ODT<0>

MEM_A_DQS_N<6>

MEM_A_DQS_P<6>

MEM_A_A<6>

MEM_A_A<12>

MEM_A_DQ<52>

MEM_A_DQ<54>

MEM_A_DQ<53>

MEM_A_DQ<48>

MEM_A_DQ<51>

PP0V75_S3_MEM_VREFCA_A

MEM_A_BA<1>

MEM_A_CLK_P<0>

MEM_A_CKE<0>

MEM_A_CLK_N<0>

MEM_A_CS_L<0>

MEM_A_WE_L

MEM_A_RAS_L

MEM_A_A<2>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_A<7>

MEM_A_A<10>

MEM_A_A<13>

MEM_A_BA<0>

MEM_A_BA<2>

MEM_A_CAS_L

MEM_A_A<11>

PP0V75_S3_MEM_VREFDQ_A

=PP1V5_S3_MEM_A

MEM_A_DQ<43>

MEM_A_DQ<45>

MEM_A_DQ<44>

MEM_A_DQ<46>

30 OF 109

2.5.0

051-8871

28 OF 74

9

27 28 29 30 31 67

11 27 28 32 67

27 28 29 30 31 67

11 67

11 27 28 32 67

11 67

11 27 28 32 67

26 27 28 29 30

11 27 28 32 67

11 67

11 27 28 32 67

9

27 28 29 30 31 67

11 27 28 32 67

27 28 29 30 31 67

11 67

11 27 28 32 67

11 67

26 27 28 29 30

11 27 28 32 67

11 67

11 67 11 27 28 32 67

11 27 28 32 67

7

27 28 32

11 27 28 32 67

7

27 28 32

11 27 28 32 67

9

27 28 29 30

31 67

11 27 28 32 67

27 28 29 30 31 67

11 67

11 27 28 32 67

11 67

11 27 28 32 67

26 27 28 29 30

11 27 28 32 67

11 67

11 67 11 27 28 32

67

11 27 28 32 67

7

27 28 32

11 27 28 32 67

11 67

11 27 28 32 67

11 27 28 32 67 11 67

11 67

11 27 28 32 67

26 27 28 29 30

11 27 28 32 67

11 67

11 27 28 32 67

11 67

27 28 29 30 31 67

11 27 28 32 67

9

27 28 29 30 31 67

7

27 28 32

11 67

VSS

A5

A1

A0

VSSQ

DQ0 DQ1 DQ2

A9

A8

A14

ZQ

RESET*

ODT

DQS*

DQS

DM/TDQS

A6

A12/BC*

NF/DQ7

NF/DQ6

NF/DQ5

NF/DQ4

DQ3

NF/TDQS*

NC

VREFCA

BA1

CK

CKE

CK*

CS*

WE*

RAS*

A2 A3 A4

A7

A10/AP

A13

BA0

BA2

CAS*

VDD

VDDQ

A11

VREFDQ

VSS

A5

A1

A0

VSSQ

DQ0 DQ1 DQ2

A9

A8

A14

ZQ

RESET*

ODT

DQS*

DQS

DM/TDQS

A6

A12/BC*

NF/DQ7

NF/DQ6

NF/DQ5

NF/DQ4

DQ3

NF/TDQS*

NC

VREFCA

BA1

CK

CKE

CK*

CS*

WE*

RAS*

A2 A3 A4

A7

A10/AP

A13

BA0

BA2

CAS*

VDD

VDDQ

A11

VREFDQ

VSS

A5

A1

A0

VSSQ

DQ0 DQ1 DQ2

A9

A8

A14

ZQ

RESET*

ODT

DQS*

DQS

DM/TDQS

A6

A12/BC*

NF/DQ7

NF/DQ6

NF/DQ5

NF/DQ4

DQ3

NF/TDQS*

NC

VREFCA

BA1

CK

CKE

CK*

CS*

WE*

RAS*

A2 A3 A4

A7

A10/AP

A13

BA0

BA2

CAS*

VDD

VDDQ

A11

VREFDQ

VSS

A5

A1

A0

VSSQ

DQ0 DQ1 DQ2

A9

A8

A14

ZQ

RESET*

ODT

DQS*

DQS

DM/TDQS

A6

A12/BC*

NF/DQ7

NF/DQ6

NF/DQ5

NF/DQ4

DQ3

NF/TDQS*

NC

VREFCA

BA1

CK

CKE

CK*

CS*

WE*

RAS*

A2 A3 A4

A7

A10/AP

A13

BA0

BA2

CAS*

VDD

VDDQ

A11

VREFDQ

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

NC NC NC

NC

NCNC

NC

NC NC

A14/A15 FOR 2G/4G MONO ONLY CS1 IS FOR 2G DDP RANK CONTROL

NC

NC NC

NC

2

1

C3132

4V CERM-X5R-1 201

0.47UF

20%

21

R3130

240

201

1/20W

1%

MF

21

R3120

240

MF

1%

1/20W

201

2

1

C3112

CERM-X5R-1

4V

201

0.47UF

20%

2

1

C3111

4V

CERM-X5R-1

201

0.47UF

20%

2

1

C3110

0.47UF

4V

CERM-X5R-1

201

20%

2

1

C3102

0.47UF

CERM-X5R-1

4V

201

20%

2

1

C3101

CERM-X5R-1

4V

0.47UF

20%

201

2

1

C3100

0.47UF

4V

201

CERM-X5R-1

20%

2

1

C3131

4V

CERM-X5R-1

201

0.47UF

20%

21

R3110

1%MF201

1/20W

240

21

R3100

240

201

MF

1%

1/20W

H9

H4

D10

C10

B9D2B3

J10

F9D9A9

F3N2L2

J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

J8

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3

G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

N8

N4

K8

M8

H8

L8

K4

U3100

OMIT_TABLE

FBGA

DDR3-1333

H9

H4

D10

C10

B9D2B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9

D8

A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

J8

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3

G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

N8

N4

K8

M8

H8

L8

K4

U3110

OMIT_TABLE

DDR3-1333

FBGA

H9

H4

D10

C10

B9D2B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

J8

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3

G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

N8

N4

K8

M8

H8

L8

K4

U3120

DDR3-1333

FBGA

OMIT_TABLE

H9

H4

D10

C10

B9D2B3

J10

F9

D9A9F3N2L2

J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

J8

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3

G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

N8

N4

K8

M8

H8

L8

K4

U3130

DDR3-1333

FBGA

OMIT_TABLE

2

1

C3130

4V

CERM-X5R-1

201

0.47UF

20%

2

1

C3122

4V CERM-X5R-1 201

0.47UF

20%

2

1

C3121

4V

CERM-X5R-1

201

0.47UF

20%

2

1

C3120

4V

CERM-X5R-1

201

0.47UF

20%

DDR3 DRAM CHANNEL B (0-31)

SYNC_DATE=12/13/2010

SYNC_MASTER=K21_MLB

PP0V75_S3_MEM_VREFCA_A

MEM_RESET_L

=PP1V5_S3_MEM_B

MEM_B_A<5>

MEM_B_A<1>

MEM_B_A<0>

MEM_B_DQ<30>

MEM_B_DQ<29>

MEM_B_DQ<24>

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<14>

MEM_B_ZQ3

MEM_B_ODT<0>

MEM_B_DQS_N<3>

MEM_B_DQS_P<3>

MEM_B_A<6>

MEM_B_A<12>

MEM_B_DQ<26>

MEM_B_DQ<31>

MEM_B_DQ<25>

MEM_B_DQ<27>

MEM_B_DQ<28>

PP0V75_S3_MEM_VREFCA_A

MEM_B_BA<1>

MEM_B_CLK_P<0>

MEM_B_CKE<0>

MEM_B_CLK_N<0>

MEM_B_CS_L<0>

MEM_B_WE_L

MEM_B_RAS_L

MEM_B_A<2>

MEM_B_A<3>

MEM_B_A<4>

MEM_B_A<7>

MEM_B_A<10>

MEM_B_A<13>

MEM_B_BA<0>

MEM_B_BA<2>

MEM_B_CAS_L

MEM_B_A<11>

PP0V75_S3_MEM_VREFDQ_A

=PP1V5_S3_MEM_B

MEM_B_A<5>

MEM_B_A<1>

MEM_B_A<0>

MEM_B_DQ<16>

MEM_B_DQ<22>

MEM_B_DQ<21>

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<14>

MEM_B_ZQ2

MEM_RESET_L

MEM_B_ODT<0>

MEM_B_DQS_N<2>

MEM_B_DQS_P<2>

MEM_B_A<6>

MEM_B_A<12>

MEM_B_DQ<23>

MEM_B_DQ<17>

MEM_B_DQ<18>

MEM_B_DQ<19>

MEM_B_DQ<20>

PP0V75_S3_MEM_VREFCA_A

MEM_B_BA<1>

MEM_B_CLK_P<0>

MEM_B_CKE<0>

MEM_B_CLK_N<0>

MEM_B_CS_L<0>

MEM_B_WE_L

MEM_B_RAS_L

MEM_B_A<2>

MEM_B_A<3>

MEM_B_A<4>

MEM_B_A<7>

MEM_B_A<10>

MEM_B_A<13>

MEM_B_BA<0>

MEM_B_BA<2>

MEM_B_CAS_L

MEM_B_A<11>

PP0V75_S3_MEM_VREFDQ_A

=PP1V5_S3_MEM_B

MEM_B_A<5>

MEM_B_A<1>

MEM_B_A<0>

MEM_B_DQ<14>

MEM_B_DQ<9>

MEM_B_DQ<8>

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<14>

MEM_B_ZQ1

MEM_RESET_L

MEM_B_ODT<0>

MEM_B_DQS_N<1>

MEM_B_DQS_P<1>

MEM_B_A<6>

MEM_B_A<12>

MEM_B_DQ<15>

MEM_B_DQ<11>

MEM_B_DQ<13>

MEM_B_DQ<10>

MEM_B_DQ<12>

PP0V75_S3_MEM_VREFCA_A

MEM_B_BA<1>

MEM_B_CLK_P<0>

MEM_B_CKE<0>

MEM_B_CLK_N<0>

MEM_B_CS_L<0>

MEM_B_WE_L

MEM_B_RAS_L

MEM_B_A<2>

MEM_B_A<3>

MEM_B_A<4>

MEM_B_A<7>

MEM_B_A<10>

MEM_B_A<13>

MEM_B_BA<0>

MEM_B_BA<2>

MEM_B_CAS_L

MEM_B_A<11>

PP0V75_S3_MEM_VREFDQ_A

=PP1V5_S3_MEM_B

MEM_B_A<5>

MEM_B_A<1>

MEM_B_A<0>

MEM_B_DQ<1>

MEM_B_DQ<4>

MEM_B_DQ<2>

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<14>

MEM_B_ZQ0

MEM_RESET_L

MEM_B_ODT<0>

MEM_B_DQS_N<0>

MEM_B_DQS_P<0>

MEM_B_A<6>

MEM_B_A<12>

MEM_B_DQ<7>

MEM_B_DQ<6>

MEM_B_DQ<5>

MEM_B_DQ<0>

MEM_B_DQ<3>

MEM_B_BA<1>

MEM_B_CLK_P<0>

MEM_B_CKE<0>

MEM_B_CLK_N<0>

MEM_B_CS_L<0>

MEM_B_WE_L

MEM_B_RAS_L

MEM_B_A<2>

MEM_B_A<3>

MEM_B_A<4>

MEM_B_A<7>

MEM_B_A<10>

MEM_B_A<13>

MEM_B_BA<0>

MEM_B_BA<2>

MEM_B_CAS_L

MEM_B_A<11>

PP0V75_S3_MEM_VREFDQ_A

31 OF 109

2.5.0

051-8871

29 OF 74

27 28 29 30 31 67

26 27 28 29 30

7

29 30 32

11 29 30 32 67

11 29 30 32 67 11 67

11 67

11 29 30 32 67

11 67

11 29 30 32 67

11 67

27 28 29 30 31 67

11 29 30 32 67

9

27 28 29 30 31 67

7

29 30 32

11 29 30 32 67

11 29 30 32 67 11 67

11 67

11 29 30 32 67

26 27 28 29 30

11 29 30 32 67

11 67

11 29 30 32 67

11 67

27 28 29 30 31 67

11 29 30 32 67

9

27 28 29 30 31 67

7

29 30 32

11 29 30 32 67

11 29 30 32 67 11 67

11 67

11 29 30 32 67

26 27 28 29 30

11 29 30 32 67

11 67

11 29 30 32 67

11 67

27 28 29 30 31 67

11 29 30 32 67

9

27 28 29 30 31 67

7

29 30 32

11 29 30 32 67

11 67

11 29 30 32 67

26 27 28 29 30

11 29 30 32 67

11 67

11 29 30 32 67

11 67

11 29 30 32 67

9

27 28 29 30

31 67

VSS

A5

A1

A0

VSSQ

DQ0 DQ1 DQ2

A9

A8

A14

ZQ

RESET*

ODT

DQS*

DQS

DM/TDQS

A6

A12/BC*

NF/DQ7

NF/DQ6

NF/DQ5

NF/DQ4

DQ3

NF/TDQS*

NC

VREFCA

BA1

CK

CKE

CK*

CS*

WE*

RAS*

A2 A3 A4

A7

A10/AP

A13

BA0

BA2

CAS*

VDD

VDDQ

A11

VREFDQ

VSS

A5

A1

A0

VSSQ

DQ0 DQ1 DQ2

A9

A8

A14

ZQ

RESET*

ODT

DQS*

DQS

DM/TDQS

A6

A12/BC*

NF/DQ7

NF/DQ6

NF/DQ5

NF/DQ4

DQ3

NF/TDQS*

NC

VREFCA

BA1

CK

CKE

CK*

CS*

WE*

RAS*

A2 A3 A4

A7

A10/AP

A13

BA0

BA2

CAS*

VDD

VDDQ

A11

VREFDQ

VSS

A5

A1

A0

VSSQ

DQ0 DQ1 DQ2

A9

A8

A14

ZQ

RESET*

ODT

DQS*

DQS

DM/TDQS

A6

A12/BC*

NF/DQ7

NF/DQ6

NF/DQ5

NF/DQ4

DQ3

NF/TDQS*

NC

VREFCA

BA1

CK

CKE

CK*

CS*

WE*

RAS*

A2 A3 A4

A7

A10/AP

A13

BA0

BA2

CAS*

VDD

VDDQ

A11

VREFDQ

VSS

A5

A1

A0

VSSQ

DQ0 DQ1 DQ2

A9

A8

A14

ZQ

RESET*

ODT

DQS*

DQS

DM/TDQS

A6

A12/BC*

NF/DQ7

NF/DQ6

NF/DQ5

NF/DQ4

DQ3

NF/TDQS*

NC

VREFCA

BA1

CK

CKE

CK*

CS*

WE*

RAS*

A2 A3 A4

A7

A10/AP

A13

BA0

BA2

CAS*

VDD

VDDQ

A11

VREFDQ

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

NC

NC NC NC

NC

NC NC NC NC

NC NC

NC

NC NC

NC

A14/A15 FOR 2G/4G MONO ONLY CS1 IS FOR 2G DDP RANK CONTROL

NC

NC NC NC NC NC

2

1

C3222

20%

0.47UF

201

CERM-X5R-1

4V

2

1

C3221

20%

0.47UF

201

CERM-X5R-1

4V

2

1

C3220

20%

0.47UF

201

CERM-X5R-1

4V

21

R3220

240

201

1/20W

1%

MF

2

1

C3212

20%

0.47UF

201

CERM-X5R-1

4V

2

1

C3232

20%

0.47UF

201

CERM-X5R-1

4V

2

1

C3211

4V

20%

0.47UF

201

CERM-X5R-1

2

1

C3210

20%

0.47UF

201

CERM-X5R-1

4V

21

R3210

1%MF1/20W

201

240

2

1

C3202

20%

0.47UF

201

CERM-X5R-1

4V

2

1

C3201

20%

0.47UF

201

CERM-X5R-1

4V

2

1

C3200

0.47UF

20%

201

CERM-X5R-1

4V

21

R3200

201

1/20W

1%

MF

240

2

1

C3231

20%

0.47UF

201

CERM-X5R-1

4V

H9

H4

D10

C10

B9D2B3

J10

F9D9A9

F3N2L2

J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

J8

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3

G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

N8

N4

K8

M8

H8

L8

K4

U3200

DDR3-1333

FBGA

OMIT_TABLE

H9

H4

D10

C10

B9D2B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9

D8

A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

J8

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3

G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

N8

N4

K8

M8

H8

L8

K4

U3210

DDR3-1333

FBGA

OMIT_TABLE

H9

H4

D10

C10

B9D2B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

J8

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3

G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

N8

N4

K8

M8

H8

L8

K4

U3220

DDR3-1333

FBGA

OMIT_TABLE

H9

H4

D10

C10

B9D2B3

J10

F9

D9A9F3N2L2

J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

J8

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3

G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

N8

N4

K8

M8

H8

L8

K4

U3230

DDR3-1333

FBGA

OMIT_TABLE

2

1

C3230

20%

0.47UF

201

CERM-X5R-1

4V

21

R3230

MF

1%

1/20W

201

240

DDR3 DRAM CHANNEL B (32-63)

SYNC_MASTER=K21_MLB

SYNC_DATE=12/13/2010

PP0V75_S3_MEM_VREFDQ_A

MEM_B_A<11>

MEM_B_CAS_L

MEM_B_BA<2>

MEM_B_BA<0>

MEM_B_A<13>

MEM_B_A<10>

MEM_B_A<7>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_A<2>

MEM_B_RAS_L

MEM_B_WE_L

MEM_B_CS_L<0>

MEM_B_CLK_N<0>

MEM_B_CKE<0>

MEM_B_CLK_P<0>

MEM_B_BA<1>

PP0V75_S3_MEM_VREFCA_A

MEM_B_DQ<32>

MEM_B_DQ<36>

MEM_B_DQ<34>

MEM_B_DQ<39>

MEM_B_A<12>

MEM_B_A<6>

MEM_B_DQS_P<4>

MEM_B_DQS_N<4>

MEM_B_ODT<0>

MEM_RESET_L

MEM_B_ZQ8

MEM_B_A<14>

MEM_B_A<8>

MEM_B_A<9>

MEM_B_DQ<35>

MEM_B_DQ<33>

MEM_B_DQ<38>

MEM_B_A<0>

MEM_B_A<1>

MEM_B_A<5>

=PP1V5_S3_MEM_B

MEM_B_DQ<37>

PP0V75_S3_MEM_VREFDQ_A

MEM_B_A<11>

MEM_B_CAS_L

MEM_B_BA<2>

MEM_B_BA<0>

MEM_B_A<13>

MEM_B_A<10>

MEM_B_A<7>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_A<2>

MEM_B_RAS_L

MEM_B_WE_L

MEM_B_CS_L<0>

MEM_B_CLK_N<0>

MEM_B_CKE<0>

MEM_B_CLK_P<0>

MEM_B_BA<1>

PP0V75_S3_MEM_VREFCA_A

MEM_B_DQ<47>

MEM_B_DQ<44>

MEM_B_DQ<45>

MEM_B_DQ<46>

MEM_B_A<12>

MEM_B_A<6>

MEM_B_DQS_P<5>

MEM_B_DQS_N<5>

MEM_B_ODT<0>

MEM_RESET_L

MEM_B_ZQ9

MEM_B_A<14>

MEM_B_A<8>

MEM_B_A<9>

MEM_B_DQ<42>

MEM_B_DQ<41>

MEM_B_DQ<43>

MEM_B_A<0>

MEM_B_A<1>

MEM_B_A<5>

=PP1V5_S3_MEM_B

MEM_B_DQ<40>

PP0V75_S3_MEM_VREFDQ_A

MEM_B_A<11>

MEM_B_CAS_L

MEM_B_BA<2>

MEM_B_BA<0>

MEM_B_A<13>

MEM_B_A<10>

MEM_B_A<7>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_A<2>

MEM_B_RAS_L

MEM_B_WE_L

MEM_B_CS_L<0>

MEM_B_CLK_N<0>

MEM_B_CKE<0>

MEM_B_CLK_P<0>

MEM_B_BA<1>

PP0V75_S3_MEM_VREFCA_A

MEM_B_DQ<48>

MEM_B_DQ<50>

MEM_B_DQ<51>

MEM_B_DQ<54>

MEM_B_DQ<52>

MEM_B_A<12>

MEM_B_A<6>

MEM_B_DQS_P<6>

MEM_B_DQS_N<6>

MEM_B_ODT<0>

MEM_RESET_L

MEM_B_ZQ10

MEM_B_A<14>

MEM_B_A<8>

MEM_B_A<9>

MEM_B_DQ<55>

MEM_B_DQ<53>

MEM_B_DQ<49>

MEM_B_A<0>

MEM_B_A<1>

MEM_B_A<5>

=PP1V5_S3_MEM_B

PP0V75_S3_MEM_VREFDQ_A

MEM_B_A<11>

MEM_B_CAS_L

MEM_B_BA<2>

MEM_B_BA<0>

MEM_B_A<13>

MEM_B_A<10>

MEM_B_A<7>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_A<2>

MEM_B_RAS_L

MEM_B_WE_L

MEM_B_CS_L<0>

MEM_B_CLK_N<0>

MEM_B_CKE<0>

MEM_B_CLK_P<0>

MEM_B_BA<1>

PP0V75_S3_MEM_VREFCA_A

MEM_B_DQ<56>

MEM_B_DQ<59>

MEM_B_DQ<60>

MEM_B_DQ<62>

MEM_B_DQ<63>

MEM_B_A<12>

MEM_B_A<6>

MEM_B_DQS_P<7>

MEM_B_DQS_N<7>

MEM_B_ODT<0>

MEM_RESET_L

MEM_B_ZQ11

MEM_B_A<14>

MEM_B_A<8>

MEM_B_A<9>

MEM_B_DQ<58>

MEM_B_DQ<57>

MEM_B_DQ<61>

MEM_B_A<0>

MEM_B_A<1>

MEM_B_A<5>

=PP1V5_S3_MEM_B

32 OF 109

2.5.0

051-8871

30 OF 74

9

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31 67

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11 29 30 32 67

11 67

11 67 11 29 30 32

67

11 29 30 32 67

7

29 30 32

11 67

9

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11 29 30 32 67

27 28 29 30 31 67

11 67

11 29 30 32 67

11 67

11 29 30 32 67

26 27 28 29 30

11 29 30 32 67

11 67

11 67 11 29 30 32 67

11 29 30 32 67

7

29 30 32

11 67

9

27 28 29 30 31 67

11 29 30 32 67

27 28 29 30 31 67

11 67

11 29 30 32 67

11 67

11 29 30 32 67

26 27 28 29 30

11 29 30 32 67

11 67

11 67 11 29 30 32 67

11 29 30 32 67

7

29 30 32

9

27 28 29 30 31 67

11 29 30 32 67

27 28 29 30 31 67

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11 29 30 32 67

11 67

11 29 30 32 67

26 27 28 29 30

11 29 30 32 67

11 67

11 67 11 29 30 32 67

11 29 30 32 67

7

29 30 32

OUT

V-

V+

V-

V+

V-

V+

V-

V+

IN

NC

RESET*

A0 A1 A2

SCL SDA

P0 P1 P2

P5 P6 P7

P3 P4

THRM

VCC

GND

PAD

NC

IN

BI

VDD

VOUTD

VOUTC

VOUTB

VOUTA

SCL

SDA

A0

A1

GND

IN

BI

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

MEM A VREF DQ

Nominal value

soft-resets and sleep/wake cycles.

6

0.75V (DAC: 0x3A)

MEM VREG

D

DAC Channel:

PCA9557D Pin:

DAC range:

DAC step size:

VRef current:

Margined target:

B

21

A

MEM B VREF DQ

0.300V - 1.200V (+/- 450mV)

7.69mV / step @ output

C

3

MEM A VREF CA

4

- =PP3V3_S3_VREFMRGN

- =I2C_VREFDACS_SCL

- =I2C_VREFDACS_SDA

- =I2C_PCA9557D_SDA

Circuitry.

- =PPVTT_S3_DDR_BUF

Page Notes

Power aliases required by this page:

VREFMRGN - Stuffs VREF Margining

VREFMRGN_NOT - Bypasses VREF Margining

Signal aliases required by this page:

(OD)

+3.4mA - -3.4mA (- = sourced)

0.000V - 1.501V (0x00 - 0x74)

C

MEM B VREF CA

Addr=0x98(WR)/0x99(RD)

Required zero ohm resistors when no VREF margining circuit stuffed

BOM options provided by this page:

5

1.5V (DAC: 0x3A)

1.998V - 1.002V (+/- 498mV)

0.000V - 1.501V (0x00 - 0x74)

+33uA - -33uA (- = sourced)

8.59mV / step @ output

1.056V - 1.442V (+/- 180mV)

1.267V (DAC: 0x8B)

D

0.000V - 3.300V (0x00 - 0xFF)

+6.0mA - -5.0mA (- = sourced)

1.51mV / step @ output

10mA max load

Addr=0x30(WR)/0x31(RD)

- =I2C_PCA9557D_SCL

GPU Frame Buffer (1.8V, 70% VRef)

unused buffer

NOTE: Must not enable more than two SO-DIMM margining

buffers at once or VRef source may be overloaded.

both at the same time!

a DAC output, cannot enable

NOTE: MEMVREG and FRAMEBUF share

RST* on ’platform reset’ so that system

watchdog will disable margining.

NOTE: Margining will be disabled across all

55

2

1

C3302

VREFMRGN

0.1UF

6.3V X5R 201

10%

21

R3314

33.2K

VREFMRGN

1%

PLACE_NEAR=R7315.2:1mm

1/20W

MF

201

2

1

R3313

VREFMRGN

100K

5%

1/20W

MF

201

2

1

R3315

100K

5%

VREFMRGN

1/20W

MF

201

B4

B1

C4

C1

C2

C3

U3302

UCSP

VREFMRGN

MAX4253

B4

B1

A4

A1

A2

A3

U3302

VREFMRGN

UCSP

MAX4253

B4

B1

A4

A1

A2

A3

U3304

MAX4253

UCSP

VREFMRGN

B4

B1

C4

C1

C2

C3

U3304

MAX4253

VREFMRGN

UCSP

21

R3309

1%

200

VREFMRGN

1/20W

MF

201

PLACE_NEAR=J2900.126:2.54mm

21

R3318

OMIT

NONE

402

NONE

SHORT

21

R3319

NONE

OMIT

SHORT

NONE

402

NONE

25

21

R3303

VREFMRGN

1%

200

MF

201

PLACE_NEAR=U2900.E1:2.54mm

1/20W

21

R3304

PLACE_NEAR=U2900.J8:1mm

VREFMRGN

1%

133

1/20W

MF

201

2

1

R3307

MF

1/20W

100K

VREFMRGN

5%

201

2 1

R3301

5%

VREFMRGN

100K

1/20W

MF

201

21

R3310

133

PLACE_NEAR=R3309.2:1mm

VREFMRGN

1%

1/20W

MF

201

16

17

2

1

15

14

13

12

11

10

9

7

6

8

5

4

3

U3301

CRITICAL

QFN

PCA9557

VREFMRGN

43

5

4

2

1

8

7

6

3

10

9

U3300

MSOP

DAC5574

CRITICAL

VREFMRGN

43

2

1

C3301

0201

X5R-CERM

16V

10%

VREFMRGN

0.1UF

2

1

C3300

VREFMRGN

2.2UF

CERM

402-LF

20%

6.3V

2

1

C3305

10%

0201

X5R-CERM

16V

0.1UF

VREFMRGN

2

1

C3303

0201

X5R-CERM

16V

10%

0.1UF

VREFMRGN

VREFMRGN_NOT

2

RES,MTL FILM,0,5%,0402,SM,LF

116S0004

R3303

FSB/DDR3/FRAMEBUF Vref Margining

SYNC_DATE=12/13/2010

SYNC_MASTER=K21_MLB

2

116S0004

RES,MTL FILM,0,5%,0402,SM,LF

VREFMRGN_NOT

R3309

VREFMRGN_CA_SODIMMA_BUF

MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V

MIN_LINE_WIDTH=0.3 mm

PP0V75_S3_MEM_VREFCA_A

VREFMRGN_SODIMMA_DQ

VREFMRGN_DQ_SODIMMA_BUF

DDRREG_FB

=I2C_PCA9557D_SDA

=I2C_PCA9557D_SCL

=I2C_VREFDACS_SDA

PCA9557D_RESET_L

=I2C_VREFDACS_SCL

VREFMRGN_FRAMEBUF_BUF

VREFMRGN_FRAMEBUF_EN

PP3V3_S3_VREFMRGN_CTRL

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

MIN_LINE_WIDTH=0.3 mm

PP3V3_S3_VREFMRGN_DAC

MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

VREFMRGN_MEMVREG_EN

=PPVTT_S3_DDR_BUF

VREFMRGN_MEMVREG_FBVREF

VREFMRGN_CA_SODIMMA_EN

VOLTAGE=0.75V

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

PP0V75_S3_MEM_VREFDQ_A

=PP3V3_S3_VREFMRGN

VREFMRGN_MEMVREG_BUF

VREFMRGN_DQ_SODIMMA_EN

VREFMRGN_SODIMMS_CA

33 OF 109

2.5.0

051-8871

31 OF 74

27 28 29 30 67

7

55

9

27 28 29 30 67

7

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

JEDEC recommends 30 Ohm term to VTT for CS,CKE,ODT and 36 Ohm for BA,A,RAS,CAS,WE

COLUMN OF THREE CAPS BETWEEN PACKAGES

2 CAPS ALONG PACKAGE EDGE

COLUMN OF THREE CAPS BETWEEN PACKAGES

2 CAPS ALONG PACKAGE EDGE

COLUMN OF THREE CAPS BETWEEN PACKAGES

2 CAPS ALONG PACKAGE EDGE

COLUMN OF THREE CAPS BETWEEN PACKAGES

2 CAPS ALONG PACKAGE EDGE

Place RC end termination after last DRAM Place Source Cterm at neckdown at first DRAM

MEM CLOCK TERMINATION

2

1

C3467

20%

0.47UF

201

CERM-X5R-1

4V

2

1

C3461

20%

0.47UF

201

CERM-X5R-1

4V

2

1

C3463

20%

0.47UF

201

CERM-X5R-1

4V

2

1

C3465

20%

0.47UF

201

CERM-X5R-1

4V

2

1

C3466

20%

0.47UF

201

CERM-X5R-1

4V

63

RP3408

5%361/32W

4X0201

54

RP3410

36

1/32W

5%

4X0201

2

1

C3424

CERM 402-LF

20%

2.2UF

6.3V

81

RP3408

36

4X0201

5%

1/32W

72

RP3410

36

4X0201

1/32W

5%

72

RP3414

4X0201

1/32W

5%

36

72

RP3413

4X0201

36

1/32W

5%

81

RP3414

4X0201

36

5%

1/32W

11 29 30 67

2

1

C3425

6.3V

2.2UF

CERM

20%

402-LF

11 29 30 67

2

1

C3483

20%

CERM-X5R-1

0.47UF

201

4V

2

1

C3485

20%

0.47UF

201

CERM-X5R-1

4V

2

1

C3480

0.47UF

4V CERM-X5R-1

20%

201

2

1

C3482

4V

201

CERM-X5R-1

20%

0.47UF

2

1

C3484

CERM-X5R-1 201

20% 4V

0.47UF

2

1

C3414

402-LF

2.2UF

6.3V

20%

CERM

2

1

C3415

402-LF

2.2UF

6.3V

20%

CERM

2

1

C3487

20%

0.47UF

201

CERM-X5R-1

4V

2

1

C3486

20%

0.47UF

201

CERM-X5R-1

4V

2

1

C3488

20%

0.47UF

201

CERM-X5R-1

4V

2

1

C3416

2.2UF

6.3V

20%

402-LF

CERM

2

1

C3489

20%

0.47UF

201

CERM-X5R-1

4V

11 27 28 67

2

1

C3404

20%

2.2UF

402-LF

CERM

6.3V

11 27 28 67

2

1

C3420

2.2UF

20%

CERM

6.3V

402-LF

2

1

C3405

2.2UF

20%

402-LF

CERM

6.3V

11 27 28 67

2

1

C3469

0.1UF

MEM_A_CLK_TERM_R

10% X5R

6.3V

201

2

1

C3479

0.1UF

201

10% X5R

6.3V

21

R3468

30

5%

1/20W

MF

201

2

1

C3468

CERM

25V

5%

3.3PF

201

21

R3469

1/20W

5%

30

MF

201

21

R3478

30

201

5%

1/20W

MF

2

1

C3478

201

CERM

25V

5%

3.3PF

21

R3479

30

201

1/20W

MF

5%

2

1

C3450

6.3V

2.2UF

20%

402-LF

CERM

2

1

C3451

6.3V

2.2UF

20%

402-LF

CERM

54

RP3401

4X0201

5%

1/32W

36

72

RP3402

4X0201

5%

1/32W

36

72

RP3406

4X0201

36

5%

1/32W

81

RP3403

36

4X0201

1/32W

5%

81

RP3402

36

4X0201

1/32W

5%

72

RP3401

4X0201

36

1/32W

5%

72

RP3403

36

4X0201

1/32W

5%

2

1

C3440

CERM 402-LF

6.3V

20%

2.2UF

63

RP3407

36

4X0201

5%

1/32W

81

RP3406

4X0201

36

5%

1/32W

54

RP3406

36

5%

1/32W

4X0201

63

RP3402

4X0201

1/32W365%

63

RP3404

36

4X0201

5%

1/32W

54

RP3403

4X0201

1/32W

5%

36

81

RP3404

4X0201

5%

1/32W

36

72

RP3407

4X0201

36

5%

1/32W

54

RP3402

4X0201

36

1/32W

5%

63

RP3403

4X0201

1/32W

5%

36

2

1

C3441

20%

2.2UF

6.3V

402-LF

CERM

81

RP3407

4X0201

5%

1/32W

36

72

RP3404

36

5%

1/32W

4X0201

54

RP3404

4X0201

5%

1/32W

36

63

RP3401

4X0201

5%

1/32W

36

81

RP3401

4X0201

1/32W

5%

36

63

RP3406

4X0201

36

5%

1/32W

81

RP3413

4X0201

36

5%

1/32W

81

RP3410

36

5%

4X0201

1/32W

81

RP3409

4X0201

36

5%

1/32W

63

RP3413

4X0201

5%361/32W

2

1

C3442

CERM 402-LF

20%

2.2UF

6.3V

54

RP3413

4X0201

1/32W365%

54

RP3409

4X0201

1/32W

5%

36

72

RP3408

4X0201

1/32W365%

72

RP3409

4X0201

36

5%

1/32W

54

RP3414

4X0201

36

5%

1/32W

81

RP3411

36

5%

1/32W

4X0201

2

1

C3430

CERM

6.3V

2.2UF

20%

402-LF

63

RP3414

4X0201

36

5%

1/32W

2

1

C3408

2.2UF

6.3V

402-LF

20%

CERM

2

1

C3409

CERM

6.3V

20%

2.2UF

402-LF

2

1

C3418

6.3V

20%

2.2UF

402-LF

CERM

2

1

C3419

CERM

6.3V

20%

2.2UF

402-LF

2

1

C3428

6.3V

2.2UF

20%

CERM 402-LF

2

1

C3429

402-LF

20%

6.3V CERM

2.2UF

2

1

C3438

6.3V

20%

CERM 402-LF

2.2UF

2

1

C3439

20%

2.2UF

6.3V

402-LF

CERM

11 27 28 67

54

RP3407

5%

1/32W

36

4X0201

11 27 28 67

11 29 30 67

54

RP3411

4X0201

5%

1/32W

36

11 29 30 67

2

1

C3431

6.3V

2.2UF

20%

402-LF

CERM

2

1

C3421

6.3V

2.2UF

20%

402-LF

CERM

2

1

C3454

402-LF

CERM

20%

2.2UF

6.3V

2

1

C3455

6.3V

2.2UF

20%

CERM 402-LF

2

1

C3444

402-LF

2.2UF

20%

6.3V CERM

2

1

C3445

402-LF

CERM

6.3V

2.2UF

20%

2

1

C3446

6.3V

2.2UF

20%

402-LF

CERM

2

1

C3434

20%

6.3V

402-LF

CERM

2.2UF

2

1

C3435

CERM 402-LF

20%

2.2UF

6.3V

2

1

C3410

2.2UF

402-LF

6.3V

20%

CERM

2

1

C3422

2.2UF

20%

6.3V CERM 402-LF

2

1

C3423

20%

2.2UF

6.3V CERM 402-LF

2

1

C3470

402-LF

CERM

6.3V

20%

2.2UF

2

1

C3471

20%

CERM 402-LF

6.3V

2.2UF

2

1

C3472

6.3V

20%

CERM

2.2UF

402-LF

C3402

20%

6.3V CERM 402-LF

2.2UF

2

1

C3403

CERM 402-LF

20%

6.3V

2.2UF

2

1

C3411

CERM

20%

2.2UF

6.3V

402-LF

2

1

C3426

2.2UF

6.3V CERM 402-LF

20%

2

1

C3427

6.3V

2.2UF

20%

402-LF

CERM

2

1

C3474

2.2UF

20%

CERM 402-LF

6.3V

2

1

C3475

CERM 402-LF

20%

2.2UF

6.3V

2

1

C3476

CERM 402-LF

20%

2.2UF

6.3V

2

1

C3406

CERM 402-LF

20%

2.2UF

6.3V

2

1

C3412

CERM

20%

2.2UF

6.3V

402-LF

2

1

C3407

6.3V

2.2UF

20%

402-LF

CERM

2

1

C3452

CERM 402-LF

20%

2.2UF

6.3V

2

1

C3453

2.2UF

CERM 402-LF

20%

6.3V

2

1

C3490

2.2UF

6.3V

20%

402-LF

CERM

2

1

C3491

CERM

6.3V

20%

402-LF

2.2UF

2

1

C3492

6.3V

2.2UF

20%

402-LF

CERM

2

1

C3432

20%

6.3V

2.2UF

CERM 402-LF

2

1

C3433

CERM

20%

6.3V

2.2UF

402-LF

2

1

C3456

6.3V

2.2UF

402-LF

20%

CERM

2

1

C3457

6.3V

2.2UF

20%

402-LF

CERM

2

1

C3494

CERM 402-LF

20%

2.2UF

6.3V

2

1

C3495

2.2UF

CERM 402-LF

20%

6.3V

2

1

C3496

CERM 402-LF

20%

2.2UF

6.3V

2

1

C3436

6.3V

2.2UF

20%

CERM 402-LF

2

1

C3400

2.2UF

402-LF

6.3V

20%

CERM

2

1

C3437

6.3V

20%

402-LF

CERM

2.2UF

2

1

C3481

0.47UF

201

4V

20%

CERM-X5R-1

2

1

C3460

CERM-X5R-1

20%

0.47UF

201

4V

63

RP3410

36

5%

1/32W

4X0201

63

RP3409

36

5%

1/32W

4X0201

2

1

C3401

2.2UF

6.3V

402-LF

CERM

20%

72

RP3411

36

4X0201

5%

1/32W

54

RP3408

4X0201

36

5%

1/32W

63

RP3411

4X0201

1/32W365%

2

1

C3462

20%

0.47UF

201

CERM-X5R-1

4V

2

1

C3464

20%

0.47UF

201

CERM-X5R-1

4V

DDR3 DRAM Channel B (32-63)

SYNC_MASTER=K21_MLB

SYNC_DATE=12/13/2010

=PP1V5_S3_MEM_B

=PP1V5_S3_MEM_A=PP1V5_S3_MEM_A

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_A_CLK_N<0>

MEM_A_CLK_P<0>

MEM_A_A<5>

MEM_A_ODT<0>

MEM_A_A<10> MEM_A_A<1> MEM_A_A<0> MEM_A_A<4>

MEM_A_BA<2> MEM_A_BA<1>

MEM_B_A<9> MEM_B_A<0> MEM_B_A<10>

MEM_B_A<11>

MEM_B_CAS_L

MEM_B_CS_L<0> MEM_B_A<14> MEM_B_A<4> MEM_B_A<12>

MEM_B_A<2> MEM_B_A<1> MEM_B_ODT<0>

MEM_B_A<3>

VOLTAGE=0V

MEM_B_CLK_TERM_R

VOLTAGE=0V

MEM_B_WE_L

MEM_B_A<5>

MEM_A_A<8>

MEM_A_A<6>

MEM_A_CAS_L MEM_A_RAS_L

MEM_A_WE_L

MEM_A_CKE<0>

MEM_A_A<3>

MEM_B_A<13>

MEM_B_BA<1>

MEM_B_A<6>

MEM_B_A<8>

MEM_B_RAS_L

MEM_B_BA<2> MEM_B_BA<0>

MEM_B_CKE<0> MEM_B_A<7>

=PP0V75_S0_MEM_VTT_B

=PP1V5_S3_MEM_B

MEM_A_A<9>

MEM_A_A<7>

MEM_A_A<13>

MEM_A_BA<0>

MEM_A_A<12>

=PP0V75_S0_MEM_VTT_A

MEM_A_A<14> MEM_A_A<2>

MEM_A_A<11>

MEM_A_CS_L<0>

34 OF 109

2.5.0

051-8871

32 OF 74

7

29 30

32

7

27 28 32

7

27 28 32

11 29 30 67

11 27 28 67

7

29 30 32

7

OUT

BI

IN

D

VCC

THM

VSS

PAD

Q

C

S_L

W_L

HOLD_L

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

PETP_0

PETP_3

PERP_1

PERP_0

DPSRC0_ML_LANE_0N_OUT0_HDMI_TMDS_CLK_N

DPSRC0_ML_LANE_0P_OUT0_HDMI_TMDS_CLK_P

DPSRC0_ML_LANE_3P_OUT0_HDMI_TMDS_2_P DPSRC0_ML_LANE_3N_OUT0_HDMI_TMDS_2_N

DPSNK0_HDMI_IN_HOT_PLUG_DET

DPSNK0_AUX_CHN

DPSNK0_AUX_CHP

DPSNK0_ML_LANE_0N_IN0_HDMI_TMDS_2_N

DPSNK0_ML_LANE_0P_IN0_HDMI_TMDS_2_P

DPSNK0_ML_LANE_1N_IN0_HDMI_TMDS_1_N

DPSNK0_ML_LANE_1P_IN0_HDMI_TMDS_1_P

DPSNK0_ML_LANE_2P_IN0_HDMI_TMDS_O_P DPSNK0_ML_LANE_2N_IN0_HDMI_TMDS_0_N

DPSNK0_ML_LANE_3P_IN0_HDMI_TMDS_CLK_P

TEST_PWR_GOOD

PERP_3

TMU_CLK_IN

TMU_CLK_OUT

XTAL_25_IN

REFCLK_100_IN_N

TDO

TCK

TDI TMS

PCIE_RST_1*

PCIE_RST_0*

THERM_DP

EE_CS*

EE_DO

EE_DI

MONDC1

RBIAS

PETN_0

MONOBSP

PERN_0

PERN_3

MONDC0

MONOBSN

PETP_1 PETN_1

PETN_2

PETP_2

PETN_3

WAKE*

PERST*

CIO_PLUG_EVENT

CIO_1_LSOE

CIO_1_LSEO

PRT1_CIOR_P PRT1_CIOR_N

PRT1_CIOT_P

CIO_0_LSEO CIO_0_LSOE

PRT0_CIOR_P PRT0_CIOR_N

PRT0_CIOT_P PRT0_CIOT_N

HDMI_5V_OUT

HDMI_OUT_HOT_PLUG_DET

HDMI_SDA_IN

HDMI_SCL_IN

DP_RES

DP_ATEST

DPSRC0_HOT_PLUG_DET

TEST_EN

PCIE_CLKREQ_0*

EE_CLK

PERN_2

XTAL_25_OUT

RSENSE

REFCLK_100_IN_P

PCIE_RST_2* PCIE_RST_3*

DPSNK0_ML_LANE_3N_IN0_HDMI_TMDS_CLK_N

PERN_1

PERP_2

CIO_MDIO

CIO_MDC

PRT1_CIOT_N

PORT1 PORT0

PORTS

SINK PORT 0

SOURCE PORT 0

MISC

DISPLAYPORT

HDMI/

HDMI

CLK REQUEST

JTAG

POWER ON RESET

HDMI

TEST PORT

CLOCKS

EEPROM

PCIE GEN2

RECEIVE

TRANSMIT

(1 OF 2)

BI

OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

100pF SRF > 40MHz

NOTE: All unused LSOE/EO pairs should be aliased

Not used in host mode.

(T29_SPI_CS_L)

SNK0 AC Coupling

(T29_SPI_CLK)

Use B1 GND ball for THERM_DN

DEBUG: For monitoring current/voltage

(T29_SPI_MISO)

together. Other signals okay to float (TP/NC).

DEBUG: For monitoring clock

(T29_SPI_MOSI)

8

43 71

8

71

8

71

8

71

8

71

8

71

8

71

8

71

8

71

8

71

8

71

3

489

1

2

7

5

6

U3690

2KX8-1.8V

OMIT_TABLE

CRITICAL

MLP

M95160

8

69

8

69

8

69

8

69

8

69

8

69

8

69

8

69

25 69

35

8

16 69

8

16

63 71

63

63 71

63

C11

D11

M2

U5 M1

T5

B2

D1

E2

U4

T3

R2

C8

A12 B12

C7

B10 A10

A8 B8

A6 B6

A4 B4

D14

H14

M14

T14

D15

H15

M15

T15

C2

B15

F14

K14

P14

B14

F15

K15

P15

G2

L2

L1

R1

P1

A13

B13

A15

A14

A2

B1

F3

U1

P2

U6

U3 N1

T12 U12

N12 R12

T6

T8 U8

T9 U9

T10 U10

T11 U11

T4

T7 U7

U14

U15

H1

F1

C1

K2

J1

K1

H2

U3600

FCBGA

OMIT_TABLE

CRITICAL

EAGLE_RIDGE-192

43 71

21

C3600

X5R10%

6.3V

201

0.1UF

21

C3601

0.1UF

20110%

6.3V

X5R

21

C3602

10% X5R

6.3V

0.1UF

201

21

C3603

20110%

6.3V

X5R

0.1UF

21

C3604

10% 201

0.1UF

X5R

6.3V

21

C3605

0.1UF

10%

6.3V

X5R 201

21

C3606

201

0.1UF

10%

6.3V

X5R

21

C3607

6.3V

0.1UF

10% X5R 201

21

R3610

0

NO STUFF

1/20W

5% MF

201

21

R3611

NO STUFF

201

0

1/20W

5% MF

21

C3615

20110%

6.3V

0.1UF

X5R

21

C3616

0.1UF

X5R

6.3V

10% 201

2

1

R3655

402

TF

1/16W

0.1%

1.0K

2

1

R3698

MF

10K

5% 1/20W

201

2

1

R3625

201

5%

MF

1/20W

0

2

1

R3629

0

5%

201

MF

1/20W

2

1

R3699

1/20W

NO STUFF

201

MF

5%

10K

2

1

R3690

201

MF

1/20W

5%

3.3K

2

1

R3691

201

MF

1/20W

5%

3.3K

2

1

R3692

201

MF

5%

1/20W

3.3K

2

1

R3693

3.3K

1/20W

201

MF

5%

2

1

C3690

0201-MUR

20%

X5R

1.0UF

6.3V

2

1

R3630

201

5%

1/20W

MF

100K

2

1

R3632

MF

5%

201

100K

1/20W

2

1

C3686

10%

X5R

0.01UF

10V

201

2

1

R3696

201

MF

1K

5%

1/20W

21

R3695

201

MF

1/20W

1%

806

2

1

R3685

14K

MF

201

1/20W

1%

2

1

C3685

5%

201

CERM

25V

100PF

35

21

C3640

0201

16V10%

X5R-CERM

0.1UF

21

C3641

0.1UF

0201

16V10%

X5R-CERM

21

C3642

10%

0201

16V

X5R-CERM

0.1UF

21

C3643

0201

16V10%

X5R-CERM

0.1UF

21

C3644

0201

16V10%

X5R-CERM

0.1UF

21

C3645

0201

16V10%

X5R-CERM

0.1UF

21

C3646

0.1UF

10%

0201

16V

X5R-CERM

21

C3647

10%

0.1UF

X5R-CERM

16V

0201

21

R3651

201

1/20W

MF5%

10K

21

C3620

10% 16V

0201

X5R-CERM

0.1UF

21

C3621

10% 16V

0.1UF

0201

X5R-CERM

21

C3622

10% 16V

0.1UF

0201

X5R-CERM

21

C3623

10% 16V

0.1UF

0201

X5R-CERM

21

C3624

10% 16V

0.1UF

0201

X5R-CERM

21

C3625

10% 16V

0201

X5R-CERM

0.1UF

21

C3626

X5R-CERM

10% 16V

0.1UF

0201

21

C3627

X5R-CERM

10% 16V

0.1UF

0201

21

C3628

0.1UF

10% 16V

0201

X5R-CERM

21

C3629

10% 16V

0.1UF

0201

X5R-CERM

2

1

R3670

201

5%

10K

MF

1/20W

2

1

R3671

10K

5%

201

1/20W

MF

2

1

R3673

MF

10K

5% 1/20W

201

2

1

R3674

MF

10K

5% 1/20W

201

21

R3661

201

5%

1/20W

MF

0

21

R3662

201

0

MF5%

1/20W

21

R3663

201

5%01/20W

MF

21

R3664

201

1/20W0MF5%

8

69

8

69

8

69

8

69

8

69

8

69

8

69

8

69

T29 Host (1 of 2)

SYNC_DATE=12/13/2010

SYNC_MASTER=K21_MLB

=PP3V3_T29_RTR

T29_DP_ATEST

T29_LSOE<1>

T29_HDMI_OUT_HPD

PCIE_T29_D2R_C_P<0>

PCIE_T29_D2R_C_P<3>

PCIE_T29_R2D_P<1>

PCIE_T29_R2D_P<0>

DP_T29SNK0_HPD

DP_T29SNK0_AUXCH_N

DP_T29SNK0_AUXCH_P

DP_T29SNK0_ML_N<0>

DP_T29SNK0_ML_P<0>

DP_T29SNK0_ML_N<1>

DP_T29SNK0_ML_P<1>

DP_T29SNK0_ML_N<2>

DP_T29SNK0_ML_P<3>

T29_TEST_POINT_3

PCIE_T29_R2D_P<3>

T29_TMU_CLK_IN

SYSCLK_CLK25M_T29_R

PCIE_CLK100M_T29_N

T29_SPI_MISO

T29_MONDC1

T29_RBIAS

PCIE_T29_D2R_C_N<0>

T29_MONOBSP

PCIE_T29_R2D_N<0>

PCIE_T29_R2D_N<3>

T29_MONDC0

T29_MONOBSN

PCIE_T29_D2R_C_P<1> PCIE_T29_D2R_C_N<1>

PCIE_T29_D2R_C_N<2>

PCIE_T29_D2R_C_P<2>

PCIE_T29_D2R_C_N<3>

T29_PCIE_WAKE_L

T29_RESET_L

T29_CIO_PLUG_EVENT

T29_LSEO<1>

T29_D2R_P<1>

T29_R2D_C_P<1>

T29_R2D_C_P<0> T29_R2D_C_N<0>

T29_HDMI_SDA_IN

T29_HDMI_SCL_IN

DP_T29SRC_HPD

=T29_CLKREQ_L

PCIE_T29_R2D_N<2>

TP_T29_XTAL25OUT

T29_RSENSE

DP_T29SNK0_ML_N<3>

PCIE_T29_R2D_N<1>

PCIE_T29_R2D_P<2>

I2C_T29_SDA

I2C_T29_SCL

T29_R2D_C_N<1>

=PP3V3_T29_RTR

DP_T29SNK0_AUXCH_N

DP_T29SNK0_AUXCH_C_P

DP_T29SNK0_ML_C_P<2>

DP_T29SNK0_ML_P<2>

DP_T29SNK0_ML_C_N<2>

DP_T29SNK0_ML_C_P<3>

DP_T29SNK0_ML_C_N<3>

DP_T29SNK0_ML_N<3>

DP_T29SNK0_ML_C_P<0>

DP_T29SNK0_ML_C_N<0>

DP_T29SNK0_ML_C_P<1>

DP_T29SNK0_ML_P<1>

DP_T29SNK0_ML_C_N<1>

DP_T29SNK0_ML_N<1>

=PP3V3_T29_RTR

PCIE_T29_D2R_N<3>

PCIE_T29_D2R_P<3>

PCIE_T29_D2R_N<2>

PCIE_T29_D2R_P<2>

PCIE_T29_D2R_N<1>

PCIE_T29_D2R_P<1>

PCIE_T29_D2R_N<0>

PCIE_T29_D2R_P<0>

TP_T29_MONOBSP

TP_T29_MONDC0

T29ROM_HOLD_L

PCIE_T29_R2D_C_P<3>

SYSCLK_CLK25M_T29

T29ROM_WP_L

PCIE_T29_R2D_C_P<1>

PCIE_T29_R2D_C_N<1>

PCIE_T29_R2D_C_P<0>

PCIE_T29_R2D_C_N<0>

PCIE_T29_R2D_C_P<2>

PCIE_T29_R2D_C_N<3>

DP_T29SNK0_ML_N<0>

DP_T29SNK0_ML_N<2>

DP_T29SNK0_ML_P<3>

DP_T29SNK0_AUXCH_P

PCIE_T29_R2D_C_N<2>

T29_HDMI_SDA_IN T29_CIO_PLUG_EVENT

=PP3V3_T29_RTR

T29_HDMI_OUT_HPD

T29_HDMI_SCL_IN

DP_T29SNK0_AUXCH_C_N

T29_D2R_N<1>

T29_D2R_P<0> T29_D2R_N<0>

T29_LSEO<0> T29_LSOE<0>

DP_T29SNK0_ML_P<0>

TP_T29_HDMI_5V_OUT

TP_T29_MONOBSN

T29_DP_RES

TP_T29_MONDC1

T29_SPI_CS_L

JTAG_T29_TMS

TP_T29_PCIE_RESET1_L

TP_T29_PCIE_RESET0_L

JTAG_T29_TDI

TP_T29_PCIE_RESET2_L TP_T29_PCIE_RESET3_L

JTAG_T29_TCK JTAG_T29_TDO

PCIE_CLK100M_T29_P

T29_TEST_EN

TP_T29_THERM_DP

DP_T29SRC_ML_CN<3>

DP_T29SRC_ML_CP<0>

T29_TMU_CLK_OUT

DP_T29SRC_ML_CN<0>

DP_T29SRC_ML_CP<3>

T29_SPI_CLK

T29_SPI_MOSI

=PP3V3_T29_RTR

DP_T29SNK0_ML_P<2>

36 OF 109

2.5.0

051-8871

33 OF 74

7

33 34 35

33

69

33 71

69

71

69 69

69

33

69

33 71

69

7

33 34 35

33 71

7

33 34 35

33 71

33

7

33 34 35

33

33 71

71

46

71

7

33 34 35

33 71

VSSDP

VSS

VSSPE

VCC1P0_PE

VCC3P3

VCC3P3_CIO

VCC3P3_DP

VDD1P0_DP

VCC1P0

GPIO_0 GPIO_4

GPIO_6

GPIO_5

GPIO_7 GPIO_8

GPIO_9 GPIO_10 GPIO_11

GND

VCC

(2 OF 2)

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

2100 mA (Single Port)

EDP: 3000 mA

2100 mA (Single Port)

Current numbers from Vendor slide (<REDACTED> power measure 1.ppt), emailed 6/21/2010, TDP @ 90C.

EDP: 200 mA

152 mA (Dual-Port)

135 mA (Single-Port)

0-ohms are placeholders for now, replace with proper values after characterization.

2250 mA (Dual Port)

EDP: 3000 mA

2250 mA (Dual Port)

2

1

C3707

0201-MUR

20%

1.0UF

X5R

6.3V

2

1

C3708

0201-MUR

1.0UF

20%

X5R

6.3V

2

1

C3709

0201-MUR

20%

1.0UF

X5R

6.3V

2

1

C3710

6.3V

1.0UF

0201-MUR

20%

X5R

2

1

C3711

20%

0201-MUR

1.0UF

X5R

6.3V

2

1

C3712

0201-MUR

1.0UF

20%

6.3V X5R

2

1

C3713

0201-MUR

20%

1.0UF

X5R

6.3V

2

1

C3714

0201-MUR

6.3V

20%

1.0UF

X5R

2

1

C3744

0201-MUR

20%

1.0UF

X5R

6.3V

2

1

C3743

0201-MUR

20%

X5R

6.3V

1.0UF

2

1

C3745

0201-MUR

6.3V X5R

1.0UF

20%

2

1

C3746

0201-MUR

1.0UF

20%

6.3V X5R

2

1

C3747

0201-MUR

6.3V X5R

1.0UF

20%

2

1

C3753

0201-MUR

20%

1.0UF

X5R

6.3V

2

1

C3752

0201-MUR

1.0UF

20%

X5R

6.3V

2

1

C3751

0201-MUR

6.3V

20%

1.0UF

X5R

2

1

C3750

0201-MUR

6.3V X5R

1.0UF

20%

2

1

C3720

0201-MUR

6.3V

20%

1.0UF

X5R

2

1

C3721

0201-MUR

20%

1.0UF

X5R

6.3V

2

1

C3722

0201-MUR

6.3V X5R

1.0UF

20%

21

R3750

201

MF

1/20W

5%

0

21

R3720

MF

5%01/20W

201

2

1

C3701

CERM-X5R

0402

6.3V

20%

10UF

2

1

C3700

6.3V

CERM-X5R

10UF

20%

0402

2

1

R3723

MF

1/20W

5%

10K

201

2

1

R3722

10K

5% 1/20W MF 201

2

1

R3721

201

MF

1/20W

5%

10K

2

1

R3724

10K

5%

201

1/20W MF

2

1

R3734

201

MF

1/20W

5%

10K

2

1

R3730

10K

5% 1/20W MF 201

2

1

R3731

201

MF

1/20W

5%

10K

2

1

R3732

10K

5% 1/20W MF 201

2

1

R3733

1/20W

5%

10K

201

MF

2

1

C3748

20%

6.3V

10UF

CERM-X5R 0402

2

1

C3749

20%

6.3V

10UF

CERM-X5R 0402

B11

B9

B7

B5

B3

A11

A9

R15

R14

N15

N14

L15

L14

L12

L11

J15

J14

A7

J12

J11

H12

H11

G15

G14

E15

E14

C15

C14

A5

A3

U13

T13

R11

R7

R3

N11

N7

N3

G7

G6

G5

G3

F10

F8

F7

M12

M11

M10

M8

M7

M6

F6

M5

M3

L10

L8

L7

L6

L5

L3

G10

G8

F5

A1

R6

R5

N6

N5

R10

R8

N10

N8

D6

D5

C6

C5

D3

C3

G12

G11

F12

F11

D12

D10

D8

D7

C12

C10

J7

J6

J5

J3

H10

H8

H7

H6

J10

J8

H5

H3

G1

F2

E1

D2

U2

N2

T1

T2

J2

U3600

CRITICAL

OMIT_TABLE

EAGLE_RIDGE-192

FCBGA

2

1

C3705

0201-MUR

20%

1.0UF

X5R

6.3V

2

1

C3706

0201-MUR

20%

1.0UF

X5R

6.3V

T29 Host (2 of 2)

SYNC_DATE=12/13/2010

SYNC_MASTER=K21_MLB

T29_GPIO<0>

T29_GPIO<11>

T29_GPIO<10>

T29_GPIO<9>

T29_GPIO<8>

T29_GPIO<7>

T29_GPIO<5> T29_GPIO<6>

T29_GPIO<4>

PP1V05_T29_VDD_DP

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

=PP1V05_T29_RTR

PP3V3_T29_DP

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

=PP3V3_T29_RTR

37 OF 109

2.5.0

051-8871

34 OF 74

7

34

7

34

7

33 35

GND

VOUT

ON

VIN

GND

VOUT

ON

VIN

OUT

IN

RESET*

OUT

EN

MR*

GND

THRM

IN

VDD

SENSE

+

-

PAD

(OD)

0.7V

DLY

IN

GND

VOUT

ON

VIN

IN

D

GS

D

SG

D

SG

IN

SGD

NC

VIN

FBX

EN/UVLO

INTVCC

VC

RT

SS

SYNC

SW

SGND

GND

NC

SNS1

SNS2

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

- =PP1V05_T29_P1V05T29FET (1.05V FET Input)

UVLO(rising) = UVLO(falling) + (2uA * R1)

<R1>

Vout = 15.1V

DLY = 60 ms +/- 20%

T29 18V Boost Regulator

for 2S.

Max Current = 1.0A

Freq = 300KHz

18 mOhm Typ

<Rb>

U3810 & U3815/U3816

add property on another page.

Max Vgs: 10V

50 mOhm Max

TPS22924C

Max Output: 2A per IC

Max Current = 3.4A (85C)

Max Current = 1.7A (85C)

R(on)

Part

Type

Pull-up provided by SB page.

Open-Drain GPIO

Rds(on): 46mOhm @ 4.5V Vgs

Vds(max): -30V

Vgs(th): -1.4V

<R2>

Signal aliases required by this page:

- =T29_RESET_L

- =T29_CLKREQ_L

- =PP3V3_S0_T29PWRCTL

BOM options provided by this page:

U3816.A2:

Load Switch

Vgs(max): +/-12V

SI8409DB:

Id(max): 3.7A @ 70C

SGND shorted to

- =PP1V05_T29_FET (1.05V FET Output)

1.05V T29 Switch

3.3V T29 Switch

no XW necessary.

GND inside package,

Voltage not specified here,

Changes required

8-13V Input

Supervisor & CLKREQ# Isolation

Page Notes

Power aliases required by this page:

- =PP18V_T29_REG (18V Boost Output)

- =PP3V3_T29_P3V3T29FET (3.3V FET Input)

- =PPVIN_SW_T29BST (8-13V Boost Input)

- =PP3V3_T29_FET (3.3V FET Output)

Pull-up provided by SB page.

T29BST:Y - Stuffs 18V boost circuitry.

UVLO(falling) = 1.22 * (R1 + R2) / R2

UVLO = 4.55V (falling), 4.95 (rising)

Platform (PCIe) Reset

<Ra>

Vout = 1.6V * (1 + Ra / Rb)

B1

A1

B2

A2

C2

C1

U3810

TPS22924

CSP

CRITICAL

B1

A1

B2

A2

C2

C1

U3815

TPS22924

CSP

CRITICAL

33

2 1

R3803

201

10K

1/20W

MF

5%

16

2

1

C3800

0201

X5R-CERM

16V

10%

0.1UF

25

33

2

1

C3810

6.3V

10%

1UF

CERM

402

2

1

C3815

1UF

10%

6.3V CERM

402

1

9

2

4

8

3

7

5

6

U3800

SLG4AP016V

CRITICAL

TDFN

2

1

R3807

201

1/20W MF

100K

5%

19

B1

A1

B2

A2

C2

C1

U3816

TPS22924

CRITICAL

CSP

PLACE_NEAR=U3815.B2:3 mm

19

63 64

2

1

R3880

T29BST:Y

470K

1/20W

MF

5%

201

2

1

C3880

0.1UF

T29BST:Y

X5R 402

10% 25V

2

1

3

Q3805

T29BST:Y

SOD-VESM-HF

SSM3K15FV

2

1

R3892

1/20W MF 201

1%

T29BST:Y

73.2K

2

1

R3887

330K

5%

T29BST:Y

MF

1/20W

201

4

5

3

Q3888

SSM6N37FEAPE

T29BST:Y

SOT563

1

2

6

Q3888

T29BST:Y

SOT563

SSM6N37FEAPE

2

1

R3894

T29BST:Y

1/20W

MF

41.2K

1%

201

2

1

C3894

402

10%

CERM-X5R

0.33UF

T29BST:Y

6.3V

2

1

R3888

1/20W MF

T29BST:Y

5%

330K

201

25 40

2

1

C3889

NO STUFF

100PF

402

CERM

50V

5%

2

1

R3896

T29BST:Y

15.8K

1/16W MF-LF

402

1%

2

1

C3895

10%

X7R-CERM

4.7UF

50V

T29BST:Y

1206

2

1

C3896

10% 50V

1206

4.7UF

X7R-CERM

T29BST:Y

2

1

C3897

50V

10%

4.7UF

X7R-CERM 1206

T29BST:Y

2

1

C3887

201

NP0-C0G

25V

5%

47PF

2

1

C3892

805

X5R

10% 10V

T29BST:Y

4.7UF

4

1

32

Q3880

BGA

SI8409DB

CRITICAL T29BST:Y

2

1

R3891

T29BST:Y

201

1/20W

MF

200K

1%

2

1

C3890

10UF

T29BST:Y

25V

805

X5R

10%

2

1

C3891

10UF

805

X5R

10% 25V

T29BST:Y

2

1

C3888

402

10PF

5% 50V CERM

27

30

34

382120

9

8

32

372423

4

3

6

33

36

35

10

2

1

28

1716151413

12

31

25

U3890

QFN

LT3957

CRITICAL

T29BST:Y

2 1

XW3895

SM

PLACE_NEAR=C3895.1:2 mm

2

1

R3889

T29BST:Y

MF

0

5%

1/20W

201

2

1

D3895

POWERDI-123

CRITICAL T29BST:Y

DFLS230L

2

1

C3898

4.7UF

1206

10%

X7R-CERM

50V

T29BST:Y

2

1

C3899

402

50V

10%

0.001UF

X7R

T29BST:Y

2

1

C3893

201

X7R

10V

10%

3300PF

T29BST:Y

2

1

R3881

T29BST:Y

150K

1/20W

MF

201

5%

2

1

R3893

T29BST:Y

201

1%

10K

MF

1/20W

2

1

R3895

402

MF-LF

1/16W

1%

133K

T29BST:Y

21

R3820

0.010

805

MF

1/4W

1%

21

L3895

PIMB062D-SM

CRITICAL

T29BST:Y

6.8UH-4.0A

SYNC_DATE=12/13/2010

SYNC_MASTER=K21_MLB

T29 Power Support

T29BST_PWREN_L

T29_RESET_L

T29BST_BOOST

DIDT=TRUE

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

PPVIN_SW_T29BST_R

T29BST_SNS1

T29_A_HV_EN

T29BST_SHDN_DIV

=PP3V3_T29_RTR

=PP3V3_S0_T29PWRCTL

=PP1V05_T29_FET

=PP1V05_S0_P1V05T29FET

=T29_CLKREQ_L

=T29_RESET_L

T29BST_SS

SMC_DELAYED_PWRGD

=PP3V3_S0_P3V3T29FET

T29_CLKREQ_L

T29_SW_RESET_L

T29_CLKREQ_ISOL_L

MAKE_BASE=TRUE

PP1V05_T29

=PP3V3_T29_FET

T29_PWR_EN

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

PPVIN_SW_T29BST

T29BST_VSNS

=PPVIN_SW_T29BST

T29BST_PWREN_DIV_L

T29BST_SNS2

=PP15V_T29_REG

T29BST_FBX

T29BST_VC_RC

GND_T29BST_SGND

VOLTAGE=0V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

T29BST_EN_UVLO

T29BST_RT

T29BST_VC

T29BST_INTVCC

38 OF 109

2.5.0

051-8871

35 OF 74

7

33 34

7

7 7

7

6 7

7

6 7

7 8

OUT

IN

BI

OUT

S

G

D

RESET*

OUT

EN

MR*

GND

THRM

IN

VDD

SENSE

+

-

PAD

(OD)

0.7V

DLY

OUT

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

BLUETOOTH

AIRPORT

RDS(ON)

LOADING

MOSFET

20-30 MOHM @2.5V

TPCP8102

3V S3 WLAN FET

P-TYPE

0.750 A (EDP)

CHANNEL

514S0335

DLY = 60 MS +/- 20%

6

17

61

21

C4030

0.1UF

X5R20110%

6.3V

PLACEMENT_NOTE=Place close to J4001.

16 69

21

C4031

0.1UF

PLACEMENT_NOTE=Place close to J4001.

6.3V

10% 201X5R

6

16 69

6

16 69

2

1

C4021

0.1UF

X5R

PLACEMENT_NOTE=Place close to Q4050.

6.3V

10%

201

6

24 68

6

24 68

6

16 69

6

16 69

43

21

R4052

CRITICAL

0.020

1%

0.25W 805

MF-LF

45 73

321

4

8765

Q4050

CRITICAL

23V1K-SM

TPCP8102

1

9

2

4

8

3

7

5

6

U4002

SLG4AP016V

TDFN

CRITICAL

2

1

C4053

201

6.3V

10% X5R

0.1UF

16

25

18 61

2

1

R4053

5%

201

MF

100K

1/20W

2

1

R4055

100K

MF

201

1%

1/20W

2

1

R4054

201

1/20W

1% MF

232K

2

1

C4032

0.1UF

X5R 201

10%

6.3V

PLACE_NEAR=J4001.18:1.5mm

9

8

7

6

5

4

3

2

18

17

16

15

14

13

12

11

10

1

21

20

19

J4001

SSD-K99

CRITICAL

F-RT-SM1

6

40

2

1

C4020

PLACEMENT_NOTE=Place close to Q4050.

603

10UF

20% 10V X5R

21

C4050

0.1UF

0201

X5R-CERM

16V

10%

21

R4090

5%

0

201

MF

1/20W

2

1

C4051

16V

10%

402

0.033UF

X5R

21

R4050

1/20W

5%

201

MF

100K

2

1

R4051

5% 1/20W

201

MF

10K

SYNC_DATE=12/13/2010

SYNC_MASTER=K21_MLB

X21 WIRELESS CONNECTOR

=PP3V3_S3_WLAN

WIFI_EVENT_L

PCIE_CLK100M_AP_P

=PP3V3_S3_BT

PCIE_AP_R2D_P

ISNS_AIRPORT_P

PM_WLAN_EN_L

AP_PWR_EN

=PP3V3_S3_WLAN

USB_BT_P

PCIE_AP_R2D_N

PCIE_AP_R2D_C_N

PCIE_WAKE_L

AP_CLKREQ_Q_L

PCIE_CLK100M_AP_N

ISNS_AIRPORT_N

PCIE_AP_D2R_P

PP3V3_WLAN_F

MIN_LINE_WIDTH=1 mm

MIN_NECK_WIDTH=0.25 mm

VOLTAGE=3.3V

P3V3WLAN_SS

PP3V3_WLAN_R

MIN_NECK_WIDTH=0.25 mm

VOLTAGE=3.3V

MIN_LINE_WIDTH=1 mm

PCIE_AP_R2D_C_P

PCIE_AP_D2R_N

AP_RESET_CONN_L

USB_BT_N

AP_RESET_L

P3V3WLAN_VMON

AP_CLKREQ_L_R

AP_CLKREQ_L

40 OF 109

2.5.0

051-8871

36 OF 74

7

36

6 7

6

69

7

36

6

69

6

OUT

NC NC

OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

SATA SSD

43

21

R4599

CRITICAL

1%

0.003

1W MF

0612

45 73

9

8

7

6

5

4

3

2

18

17

16

15

14

13

12

11

10

1

21

20

19

J4501

GND_VOID=TRUE

SSD-K99

F-RT-SM1

CRITICAL

21

R4510

1/20W

0

MF

5%

201

21

R4511

5%

MF

1/20W

0

201

2

1

C4501

0201

PLACE_NEAR=J4501.1:1.5mm

0.1UF

10% 16V X5R-CERM

16 68

21

C4516

10%

0.01UF

20110V X5R

PLACE_NEAR=J4501.3:1.5MM

21

C4510

PLACE_NEAR=J4501.8:1.5MM

0.01UF

X5R10% 20110V

21

C4511

0.01UF

X5R10% 10V 201

PLACE_NEAR=J4501.7:1.5MM

21

C4515

X5R10% 10V

0.01UF

201

PLACE_NEAR=J4501.4:1.5MM

SYNC_MASTER=K21_MLB

SATA CONNECTOR

SYNC_DATE=12/13/2010

PP3V3_S0_HDD_R

VOLTAGE=5V

MIN_NECK_WIDTH=0.25mm

MIN_LINE_WIDTH=0.6mm

SMC_HDD_TEMP_CTL_CONN

SMC_HDD_OOB_TEMP_CONN

SATA_HDD_R2D_P

SATA_HDD_R2D_N

SATA_HDD_D2R_C_P

SATA_HDD_D2R_C_N

TP_SSD_RSRVD

SATA_HDD_D2R_P

SMC_HDD_TEMP_CTL

SMC_HDD_OOB_TEMP

SATA_HDD_R2D_C_P

SATA_HDD_R2D_C_N

=PP3V3_S0_HDD

ISNS_HDD_P

ISNS_HDD_N

SATA_HDD_D2R_N

45 OF 109

2.5.0

051-8871

PLACEMENT_NOTE=PLACE C4501 CLOSE TO J4501

37 OF 74

6

68

6

68

6

68

6

68

40

7

GND

THRM

OUT2

OUT1

ILIM

IN_0 IN_1

EN2

FAULT1* FAULT2*

EN1

PAD

NC

BI

SYM_VER-1

IN

OUT

IN

OUT

IOIONC

GND

VBUS

NC

VCC

GND

SELOE*

D+ D-

Y+ Y-

M+ M-

VBUS

D-

D+

GND

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

USB Port Power Switch

Right USB Port A

We can add protection to 5V if we want, but leaving NC for now

Place L4605 at connector pin

USB/SMC Debug Mux

SEL=0 Choose SMC

SEL=1 Choose USB

Current limit (R4600): 2.17-2.59A

2

1

R4650

5%

10K

SMC_DEBUG_YES

MF 201

1/20W

2

1

R4600

1%

23.2K

MF-LF

1/16W

402

21

R4651

0

201

1/20W

MF

5%

SMC_DEBUG_NO

21

R4652

5%

SMC_DEBUG_NO

1/20W

MF

201

0

2

1

C4605

0201

X5R-CERM

16V

10%

0.01UF

2

1

C4698

6.3V

20%

2012-LLP

POLY-TANT

47UF

CRITICAL

2

1

C4697

20%

6.3V POLY-TANT

47UF

2012-LLP

CRITICAL

2

1

C4699

20%

2012-LLP

CRITICAL

6.3V

47UF

POLY-TANT

11

8

9

3

2

7

1

6

10

5

4

U4600

TPS2561DR

CRITICAL

SON

21

L4605

CRITICAL

FERR-120-OHM-3A

0603

2

1

R4601

1/20W

0

5%

MF

201

24 68

4 3

21

L4600

CRITICAL

DLP11S

90-OHM-100MA

6

40 41 42

6

40 41 42

40

24

6

45

1

D4600

RCLAMP0502N

CRITICAL

SLP1210N6

1

2

9

10

8

5

4

3

7

6

U4650

SMC_DEBUG_YES

CRITICAL

TQFN

PI3USB102ZLE

2

1

C4696

20%

6.3V

2012-LLP

POLY-TANT

47UF

CRITICAL

1

6

5

4

3

2

J4600

CRITICAL

F-RT-TH

USB-RIGHT-K99

2

1

C4690

CERM-X5R

0402

10UF

20%

6.3V

2

1

C4695

CERM-X5R

6.3V

10UF

20%

0402

2

1

C4691

10%

0.1UF

16V

0201

X5R-CERM

2

1

C4650

0201

X5R-CERM

16V

10%

0.1UF

SMC_DEBUG_YES

External USB Connectors

SYNC_DATE=12/13/2010

SYNC_MASTER=K21_MLB

PP5V_S3_RTUSB_A_ILIM

MIN_NECK_WIDTH=0.375 mm VOLTAGE=5V

MIN_LINE_WIDTH=0.5 mm

USB_ILIM

USB2_LT1_N

SMC_RX_L

USB_EXTA_P

SMC_TX_L

=PP3V42_G3H_SMCUSBMUX

USB_DEBUGPRT_EN_L

MIN_NECK_WIDTH=0.375 mm

PP5V_S3_RTUSB_A_F

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=5V

USB2_LT1_P

USB2_EXTA_MUXED_P

USB2_EXTA_MUXED_N

USB_EXTA_N

USB_EN2

=USB_PWR_EN

USB_EXTA_OC_L

=PP5V_S3_RTUSB

46 OF 109

2.5.0

051-8871

38 OF 74

2 3

73

7

73 73

73

6

39 61

7

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

516S0862

LIO CONNECTOR

2

1

C4720

0201

X5R-CERM

16V

PLACE_NEAR=J4700.32:1.5mm

0.1UF

10%

2

1

C4710

0201

X5R-CERM

16V

10%

0.1UF

PLACE_NEAR=J4700.30:1.5mm

2

1

C4700

PLACE_NEAR=J4700.20:1.5mm

0201

X5R-CERM

16V

0.1UF

10%

9

8

7

6

5

4

38

37

36

35

34

33

32

31

30

3

29

28

27

26

25

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

J4700

AXK736327G

F-ST-SM

LIO CONNECTORS

SYNC_DATE=N/A

SYNC_MASTER=N/A

AUD_GPIO_3 HDA_RST_L

AUD_IPHS_SWITCH_EN

=I2C_LIO_SCL =I2C_LIO_SDA AUD_I2C_INT_L AUD_IP_PERIPHERAL_DET

HDA_BIT_CLK HDA_SDOUT

=I2C_MIKEY_SCL

=I2C_MIKEY_SDA

HDA_SYNC HDA_SDIN0

=PP3V3_S0_AUDIO

USB_EXTD_OC_L

=PP3V3R1V5_S0_AUDIO

=PP3V42_G3H_ONEWIRE

=USB_PWR_EN SMC_BC_ACOK SYS_ONEWIRE

USB_CAMERA_P USB_CAMERA_N

SPKRAMP_INR_P

SPKRAMP_INR_N

USB_EXTD_N

USB_EXTD_P

47 OF 109

2.5.0

051-8871

39 OF 74

6

50

6

16 69

6

19

6

43

6

43

6

18

6

18

6

16 69

6

16 69

6

43

6

43

6

16 69

6

16 69

6 7

6

24

6 7

6

38 61

6

40 41

6

40

6

18 68

6

18 68

6

50

73

6

50 73

6

24 68

6

24 68

IN

OUT

IN

OUT

IN

OUT

IN

OUT

BI

IN

OUT

BI

OUT

IN

OUT

IN

OUT

IN

BI

OUT

IN

OUT

IN

BI

OUT

IN

OUT

NC

OUT

NC

NC NC NC

NC

NC NC

NC NC NC

NC

NC NC

NC

IN

P11

P82 P83

P35

P96

P95

P94

P93

P92

P91

P90

P86

P85

P84

P81

P80

P77

P67

P52

P51

P50

P47

P46

P45

P44

P43

P42

P41

P40

P37

P36

P34

P33

P32

P31

P30

P27

P26

P25

P24

P23

P21

P17

P12

P66P16

P15

P14

P13

P22

P20

P63

P61

P60

P65

P64

P62

P70 P71 P72 P73 P74 P75 P76

P97

P10

(1 OF 3)

PEVREF/PH4

PECI/PH3

PH2

PG5

PG4

PG3

PG2

PG1

PG0

PF7

PF6

PF5

PF4

PF3

PF2

PF1

PF0

PE4

PE3

PE2

PE1

PE0

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

PA7

PA6

PA3

PA2

PA1

PA0

PA4 PA5

PG6 PG7

PH0 PH1

PEVSTP/PH5

(2 OF 3)

EXTAL

XTAL

RES*

VSS

AVSS

ETRST*

NMI

MD2

MD1

NC

AVCC

VCC

VCL

AVREF

(3 OF 3)

OUT

NC

INBI

OUT

IN

OUT

NC

OUT

IN

NC

BI

IN

OUT

BI

IN

BI

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

NOTE: Unused pins have "SMC_Pxx" names. Unused pins designed as outputs can be left floating, those designated as inputs require pull-ups.

(OC)

(OC) (OC) (OC)

NOTE: SMS Interrupt can be active high or low, rename net accordingly. If SMS interrupt is not used, pull up to SMC rail.

(OC)

2

1

C4902

X5R-CERM

10V

22UF

805

20%

6

17 42

6

41 42 52

6

41 48

2

1

C4903

0.1UF

CERM

10V

20%

402

2

1

C4920

PLACE_NEAR=U4900.M12:3mm

0.1UF

CERM

402

20% 10V

2

1

C4904

10V

20%

402

CERM

0.1UF

2 1

XW4900

SM

PLACE_NEAR=U4900.L3:4mm

17 23

25 35

2

1

C4905

10V

20%

402

CERM

0.1UF

17

61

23 25 51 61

41

2

1

C4906

10V

20%

402

CERM

0.1UF

41

6

39 41

6

38 40 41 42

6

38 40 41 42

61

43

6

42

6

42

38

6

39

41 61

41

47

41

47

41

6

41 42

41

6

41 42

6

41 42

6

41 42

6

41 48 51

43

41

6

38 40 41 42

6

38 40 41 42

41

6

16 42

41

17 25

6

42

16 19

6

17 42

41

17 41 61

41

F1

F4

G4

H4

G1

H2

G3

J4

C6

B5

A6

D5

C7

B6

A7

L12

N13

M13

N12

N11

L10

M11

N10

H12

J11

J10

K13

J12

K11

K12

L13

E4

F3

G2

C3

C1

B2

C2

A1

B4

A5

D4

D6

D7

D8

A8

B7

C8

D9

A9

E10

F13

E12

E13

F11

D12

E11

D13

D10

C12

C13

D11

B13

A12

A13

B12

U4900

OMIT_TABLE

DF2117RVPLP20HV

TLP-145V

J2

F2

E2

L6

M7

N6

K6

K7

K8

N7

M8

M4

L4

N4

M5

L5

M6

N5

K5

C4

B3

A4

K4

J1

K2

J3

K1

L7

K9

N8

M9

L8

K10

N9

M10

J13

H11

G12

G10

H13

F12

G13

G11

A11

C11

B10

C10

A10

B9

C9

B8

L2

K3

L1

N2

M2

M3

N1

N3

U4900

OMIT_TABLE

TLP-145V

DF2117RVPLP20HV

A3

C5

B11

F10

L3

D2

E1

H10

M1

B1

D3

E3

H1

D1

A2

H3

L9

L11

M12

U4900

OMIT_TABLE

TLP-145V

DF2117RVPLP20HV

16

41

6

36

21

R4910

201

MF

1/20W

5%

43

21

R4911

201

MF

1/20W

0

5%

21

R4912

201

MF

1/20W

5%

0

2

1

C4910

10V

CERM

0.1UF

20%

402

41 61

6

41 48

19 41

37

2

1

R4909

1/20W

10K

5%

MF

201

2

1

R4901

5% 1/20W MF

10K

201

2

1

R4903

NO STUFF

0

5%

MF

1/20W

201

2

1

R4998

10K

5% 1/20W MF 201

2

1

R4902

5%

10K

1/20W MF 201

2

1

C4907

20%

0.47UF

CERM-X5R-1

4V

BYPASS=U4900.E1:D2:3 mm

201

21

R4999

4.7

5%

1/20W

MF

PLACE_NEAR=U4900.M12:3mm

201

6

16 42 69

6

16 42 69

6

16 42 69

6

16 42 69

6

16 42 69

25

25 69

48

43

17 26 61

17 26 48 61

17 61

41

43

41

SMC

SYNC_MASTER=K21_MLB

SYNC_DATE=12/13/2010

ALL_SYS_PWRGD S5_PWRGD

PM_DSW_PWRGD

PM_PWRBTN_L

SMC_ADC7

SMC_SCI_L

SMC_PROCHOT

MIN_NECK_WIDTH=0.1 MM

PP3V3_S5_SMC_AVCC

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.25 MM

SMC_PF5

SMB_BSA_DATA

=SMC_SMS_INT

SMB_B_S0_DATA

SMB_BSA_CLK

SMC_LID

SMB_A_S3_DATA

SMC_ADC6

PP3V3_S5_AVREF_SMC

SMC_RSTGATE_L

PM_SLP_S4_L

SMC_PA0_PU

USB_DEBUGPRT_EN_L

SMC_RUNTIME_SCI_L

SMC_FAN_1_TACH SMC_FAN_2_TACH

SMC_ADC8 SMC_ADC9 SMC_ADC10 SMC_ADC11 SMC_ADC12 SMC_ADC13 SMC_ADC14

GND_SMC_AVSS

SMC_FAN_3_CTL

SMC_FAN_1_CTL

SMC_TMS

SMC_FAN_2_CTL

SMB_B_S0_CLK

SMC_TDO

G3_POWERON_L

SMC_THRMTRIP

CPU_PECI_R

PM_PECI_PWRGD_R

SMC_EXTAL

SMC_XTAL

SMC_RESET_L

CPU_PECI

SMC_ADC15

SMB_A_S3_CLK

PVCCIO_S0_SMC_R

PM_PECI_PWRGD

=PPVCCIO_S0_SMC

SMC_FAN_3_TACH

SMC_FAN_0_TACH

SMC_GFX_OVERTEMP_L

PM_SYSRST_L

SMC_FAN_0_CTL

SMC_DP_HPD_L

SMC_PB4

SMC_S4_WAKESRC_EN

SMC_P10

SMC_ADC5

SMC_ADC4

SMC_ADC3

SMC_ADC2

SMC_ADC1

SMC_ADC0

SMC_ADAPTER_EN

SMC_PM_G2_EN

SMC_P20

SMC_DELAYED_PWRGD SMC_PROCHOT_3_3_L

SMC_P24

SMC_P26

LPC_AD<0>

LPC_CLK33M_SMC

SMC_SYS_KBDLED

SMC_BIL_BUTTON_L

SMC_TX_L SMC_RX_L SMB_MGMT_CLK

SMC_ONOFF_L SMC_BC_ACOK SMC_PME_S4_WAKE_L PM_SLP_S3_L

LPC_PWRDWN_L

PM_CLKRUN_L

SMC_P43

LPC_SERIRQ

SMC_LRESET_L

LPC_FRAME_L

LPC_AD<3>

LPC_AD<2>

LPC_AD<1>

SMC_HDD_TEMP_CTL

SMC_GFX_THROTTLE_L

MEM_EVENT_L WIFI_EVENT_L SYS_ONEWIRE SMC_BATLOW_L

SPI_DESCRIPTOR_OVERRIDE_L

SMB_0_S0_CLK

SMB_MGMT_DATA

SMC_HDD_OOB_TEMP

SMC_TRST_L

SMC_KBC_MDE

SMC_NMI

SMC_MD1

SMC_VCL

=PP3V3_S5_SMC

SMC_CLK32K

PM_SLP_S5_L

SMB_0_S0_DATA

SMC_RX_L

SMC_TX_L

SMC_TDI

SMC_TCK

SMC_CASE_OPEN

49 OF 109

2.5.0

051-8871

40 OF 74

E5

41

41 44 45

41

10 19 66

61

7

41

7

41

D

SG

IN

OUT

BI

IN

D

SG

G

D

S

OUT

IN

REFOUT

MR1*

THRM

GND

RESET*

DELAY

MR2*

VIN

V+

SN0903048

PAD

OUT

IN

OUT

IN

OUT

D

GS

OUT

D

GS

IN

NC NC

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

SMC Reset "Button", Supervisor & AVREF Supply

Below connections are different from K91

Debug Power "Buttons"

Used on mobiles to support SMC reset via keyboard.

MR1* and MR2* must both be low to cause manual reset.

Check with SMC pullup S0

Internal 20K pull-up on PM_BATLOW_L in PCH.

SMC Crystal Circuit

Desktops: 5V Mobiles: 3.42V

TO SMC

(IPU)

TO CPU

PROCHOT Level Shifting to 3V3

NOTE: Internal pull-ups are to VIN, not V+.

BATLOW# Isolation

4

5

3

Q5059

SSM6N37FEAPE

SOT563

21

R5070

201

MF

1/20W

10K

5%

21

R5071

201

MF

1/20W

100K

5%

21

R5073

201

MF

1/20W

5%

10K

21

R5074

201

MF

1/20W

5%

100K

21

R5077

10K

201

MF

1/20W

5%

21

R5078

201

MF

1/20W

10K

5%

21

R5079

201

MF

1/20W

10K

5%

21

R5080

201

MF

1/20W

5%

10K

21

R5085

MF

201

5%

10K

1/20W

21

R5086

201

MF

1/20W

10K

5%

21

R5088

5%

1/20W

10K

MF

201

40

19

2

1

R5015

5%

603

OMIT

0

MF-LF

1/10W

PLACE_SIDE=TOP

SILK_PART=PWR_BTN

21

R5062

201

MF

1/20W

3.3K

5%

10 56 66

40

1

2

6

Q5059

SOT563

SSM6N37FEAPE

21

R5091

201

MF

1/20W

5%

100K

NOSTUFF

21

R5081

201

MF

1/20W

5%

10K

21

R5010

201

MF

1/20W

5%

0

21

C5010

5%

15PF

201

NPO

25V

21

R5087

5%

201

MF

1/20W

470K

21

R5093

5%

10K

1/20W

MF

201

21

R5072

201

MF

1/20W

10K

5%

4

3

5

Q5060

SOT-563

DMB53D0UV

2

1

R5061

201

MF

1/20W

100K

5%

1

2

6

Q5060

SOT-563

DMB53D0UV

2

1

R5060

201

MF

1/20W

5%

10K

40

2

1

R5016

SILK_PART=PWR_BTN

0

5%

1/10W

603

MF-LF

OMIT

PLACE_SIDE=BOTTOM

2

1

R5001

SILK_PART=SMC_RST

1/10W

603

0

MF-LF

5%

OMIT

PLACEMENT_NOTE=Place R5001 on BOTTOM side

6

40 41 48

6

48

2

1

C5001

0.01UF

10% 10V X5R 201

2

1

C5020

CERM-X5R

402

10%

6.3V

0.47UF

3

1

9

5

8

7

6

2

4

U5010

VREF-3.3V-VDET-3.0V

DFN

2

1

C5025

603

6.3V X5R

20%

10uF

2

1

C5026

0.01UF

10% 10V X5R 201

6

40 42 52

17

21

R5012

201

22

5%

PLACE_NEAR=U1800.N14:5.1mm

1/20W

MF

40

21

R5095

201

MF

1/20W

5%

10K

63

40

2

1

R5020

5%

201

MF

1/20W

100K

2

1

3

Q5020

SOD-VESM-HF

SSM3K15FV

21

R5090

100K

1/20W

MF5%

201

2

1

R5076

1/20W

201

MF

5%

100K

6

40 48

2

1

R5011

1M

201

MF

1/20W

NO STUFF

5%

21

R5094

201

MF

1/20W

100K

5%

NOSTUFF

17

2

1

R5040

100K

1/20W

201

MF

5%

21

R5041

NOSTUFF

201

MF

1/20W

5%

0

2

1

3

Q5040

SSM3K15FV

CRITICAL

SOD-VESM-HF

40 61

31

42

Y5010

CRITICAL

20MHZ

SM-2.5X2.0MM

21

C5011

25V NPO

5%

15PF

201

21

R5075

MF

201

1/20W

5%

10K

2

1

R5000

201

100K

5% 1/20W MF

6

40 41 48

SMC Support

SYNC_MASTER=K21_MLB

SYNC_DATE=12/13/2010

=PP3V3_S5_SMC

MAKE_BASE=TRUE

SMC_HS_COMPUTING_ISENSE

MAKE_BASE=TRUE

TP_SMC_GFX_THROTTLE_L

SMC_TDI SMC_TCK SMC_BIL_BUTTON_L SMC_BC_ACOK

SMS_INT_L

SMC_RUNTIME_SCI_L

SMC_PA0_PU

SMC_TDO

=PP3V3_S5_SMC

SMC_TMS

SMC_TX_L

SMC_LID

SMC_ONOFF_L

SMC_HDD_ISENSE

MAKE_BASE=TRUE

SMC_ADC6

SMC_ADC7

SMC_ADC8

SMC_ADC9

SMC_ADC10

SMC_ADC11

MAKE_BASE=TRUE

TP_SMC_P43

TP_SMC_RSTGATE_L

MAKE_BASE=TRUE

SMC_MANUAL_RST_L

SMC_ADC2

SMC_ADC12

MAKE_BASE=TRUE

SMC_CPUVCCIO_ISENSE

CPU_PROCHOT_L

MAKE_BASE=TRUE

SMC_DCIN_ISENSE

MAKE_BASE=TRUE

SMC_DCIN_VSENSE

MAKE_BASE=TRUE

TP_SMC_P20

SMC_DP_HPD_L

MEM_EVENT_L

SMC_ADC0

SMC_PF5

SMC_P43

MAKE_BASE=TRUE

TP_SMC_ADC15

DP_A_EXT_HPD

SMC_ONOFF_L

=PP3V3_SUS_SMC

SMC_CASE_OPEN

SMC_FAN_2_CTL

=PP3V3_S0_SMC

SMC_PROCHOT_3_3_L

CPU_PROCHOT_BUF

SMC_FAN_2_TACH

SMC_XTAL

=PP3V3_S4_SMC

SMC_FAN_1_TACH

SMC_GFX_THROTTLE_L

SMC_BATLOW_L

SMC_FAN_3_TACH

=CHGR_ACOK

SMC_P26

SMC_FAN_3_CTL

SMC_ADC1

SMC_ADC4

MAKE_BASE=TRUE

SMC_WLAN_ISENSE

SMC_LCDBKLT_ISENSE

MAKE_BASE=TRUE

SMC_1V5S3_ISENSE

MAKE_BASE=TRUE

SMC_BMON_ISENSE

NC_SMC_FAN_1_TACH

MAKE_BASE=TRUE

NC_SMC_FAN_3_TACH

MAKE_BASE=TRUE

NC_SMC_FAN_3_CTL

SMC_CPU_VSENSE

MAKE_BASE=TRUE

TP_SMC_P24

MAKE_BASE=TRUE

SMC_BC_ACOK

NC_SMC_FAN_2_TACH

MAKE_BASE=TRUE

PM_THRMTRIP_L_R

G3_POWERON_L

SMC_GFX_OVERTEMP_L

PM_BATLOW_L

=PP3V3_S5_SMCBATLOW

SMC_RX_L

CPU_PROCHOT_L_R

=SMC_SMS_INT

SMC_ADC5

VOLTAGE=3.3V

PP3V3_S5_AVREF_SMC

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.1 mm

PM_CLK32K_SUSCLK_R

NC_SMC_FAN_2_CTL

MAKE_BASE=TRUE

SMS_INT_L

MAKE_BASE=TRUE

SMC_CPU_ISENSE

MAKE_BASE=TRUE

SMC_GFX_ISENSE

MAKE_BASE=TRUE

SMC_GFX_VSENSE

SMC_ADC3

=PPVIN_S5_SMCVREF

=PP3V3_S4_SMC

=PP3V3_S0_SMC

SMC_P20

SMC_PBUS_VSENSE

MAKE_BASE=TRUE

SMC_BMON_MUX_SEL

SMC_P24

SMC_ADC15

SMC_P10

MAKE_BASE=TRUE

TP_SMC_P10

TP_SMC_PF5

MAKE_BASE=TRUE

SMC_PME_S4_WAKE_L

MAKE_BASE=TRUE

SMC_S4_WAKESRC_EN

SMC_ADAPTER_EN

SMC_PB4

SMC_FAN_1_CTL

SMC_PA0_PU

MAKE_BASE=TRUE

NC_SMC_FAN_1_CTL

HISIDE_ISENSE_OC

MAKE_BASE=TRUE

SMC_ADC13

MAKE_BASE=TRUE

TP_SMC_ADC13

SMC_CLK32K

SMC_RSTGATE_L

SMC_ADC14

SMC_TPAD_RST_L SMC_ONOFF_L

MIN_NECK_WIDTH=0.1 mm VOLTAGE=0V

GND_SMC_AVSS

MIN_LINE_WIDTH=0.4 mm

=PP3V3_S5_SMC

SMC_THRMTRIP

SMC_EXTAL

SMC_XTAL_R

SMC_RESET_L

SMC_PROCHOT

50 OF 109

2.5.0

051-8871

41 OF 74

7

40 41

45

6

40 42

6

40 42

40

6

39 40 41

41

19 40

40 41

6

40 42

7

40 41

6

40 42

6

38 40 42

6

40 48 51

6

40 41 48

45

40

44

45

44

40

7

40

7

41

40

7

41

40

44 52

40

45

44

6

39 40 41

40

7

6

38 40 42

40

41

44

40

7

41

7

41

40

44

45

40

40 61

17 40 61

40

40 41 45

40

40 44 45

7

40 41

40

OUT

IN

OUT

IN

OUT

IN

OUT

IN

BI

OUT

IN

BI

IN

OUT

BI

IN

OUT

IN

OUT

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

SPI Bus Series Termination

LPC+SPI Connector

516S0573

2

1

R5126

47

MF

LPCPLUS

1/20W

5%

201

PLACE_NEAR=J5100.12:5mm

49 69

21

R5122

201

47

5%

1/20W

MF

PLACE_NEAR=R5127.2:5mm

21

R5112

15

MF

5%

201

1/20W

PLACE_NEAR=U1800.W8:5mm

16 69

2

1

R5127

MF

1/20W

5%

47

LPCPLUS

201

PLACE_NEAR=J5100.9:5mm

2

1

R5128

MF

1/20W

5%

LPCPLUS

201

0

PLACE_NEAR=J5100.11:5mm

6

38 40 41

6

40

6

40

6

40 41

9

8

7

6

5

4

34

33

32

31

30

3

29

28

27

26

25

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

J5100

55909-0374

CRITICAL

LPCPLUS

M-ST-SM

6

19

6

38 40 41

6

40

6

40 41 52

6

40 41

6

40 41

6

25

6

42

6

16 40 69

6

17 40

6

42

6

16 40 69

6

16 40 69

6

40 41

6

17 40

6

16 40

6

42

6

42

6

19 49

6

16 40 69

6

16 40 69

6

25 69

49 69

21

R5110

15

MF

1/20W

5%

201

PLACE_NEAR=U1800.AB8:5mm

16 69

49 69

21

R5111

15

MF

201

1/20W

5%

PLACE_NEAR=U1800.AD12:5mm

16 69

49 69

21

R5123

201

5%

15

MF

PLACE_NEAR=U6100.2:5mm

1/20W

16 69

21

R5120

201

5%

1/20W

47

MF

PLACE_NEAR=R5125.2:5mm

2

1

R5125

MF

5%

47

LPCPLUS

1/20W

201

PLACE_NEAR=J5100.14:5mm

21

R5121

201

47

5%

MF

PLACE_NEAR=R5126.2:5mm

1/20W

LPC+SPI Debug Connector

SYNC_DATE=12/13/2010

SYNC_MASTER=K21_MLB

SPI_MLB_MOSI

=PP3V3_S5_LPCPLUS =PP5V_S0_LPCPLUS

LPC_CLK33M_LPCPLUS LPC_AD<2> LPC_AD<3>

SPI_ALT_CS_L LPC_SERIRQ LPC_PWRDWN_L SMC_TDI SMC_TCK SMC_RESET_L SMC_NMI SMC_RX_L LPCPLUS_GPIO

LPC_AD<0> LPC_AD<1>

SPI_ALT_MOSI SPI_ALT_MISO

PM_CLKRUN_L

LPC_FRAME_L

SMC_TMS LPCPLUS_RESET_L

SMC_MD1

SMC_TRST_L

SMC_TX_L

SPIROM_USE_MLB

SPI_ALT_CLK

SMC_TDO

SPI_ALT_MISO SPI_ALT_MOSI SPI_ALT_CLK SPI_ALT_CS_L

SPI_MLB_CS_L

SPI_MLB_CLK

SPI_MOSI_R

SPI_CLK_R

SPI_MOSI

SPI_CLK

SPI_MISO

SPI_CS0_R_L

SPI_MLB_MISO

SPI_CS0_L

51 OF 109

2.5.0

051-8871

42 OF 74

6 7

6

42

6

42

6

42

6

42

69

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Finstack Temp - (Write: 0x92 Read: 0x93)

Left I/O Board

ALS - (write: 0x72 Read: 0x73)

SMC "A" SMBus Connections

NOTE: SMC RMT bus remains powered and may be active in S3 state

DVR - (Write: 0x4E Read: 0x4F) Y Y Y Y N

Analogix T-con - (Write: 0x7B/0x87 Read: 0x7C/0x88) N Y * Y *

Cougar-Point

J9000

(See Table)

Internal DP

Samsung LGD Samsung LGD AUO

T29 & Inlet Temp

(Write: 0x98 Read: 0x99)

EMC1704: U5400

Trackpad

J5700

(Write: 0x90 Read: 0x91)

U3300

Parade T-con - (0x10-0x1F or 0x30-0x3F) Y N * N *

(Write: 0x98 Read: 0x99)

U9330

(Write: 0xA0 Read: 0xA1)

U3301

J2600 & J2650

Internal DP

(MASTER)

PCH SMBus "0" Connections

SMC

Battery Charger

Cougar-Point

(Write: 0x88 Read: 0x89)

SMLink 1 is slave port to

XDP Connectors

(MASTER)

SMC

T29 Plug uC

T29 IC

U3600

(Write: 0x98 Read: 0x99)

Margin Control

(MASTER)

U4900

access PCH & CPU via PECI.

Cougar-Point

U1800

(MASTER)

SMC

U4900

(MASTER)

(See Table)

SMC

U1800

Battery

(MASTER)

U4900

J6955

Battery

U1800

SMC

VRef DACs

(MASTER)

U9310

(Write: 0x94 Read: 0x95)

DP Re-driver

U4900

PCH "SMLink 1" Connections

SMC "Battery A" SMBus Connections

CPU Temp

PCH "SMLink 0" Connections

Battery Temp - (Write: 0x90 Read: 0x91)

SMC "Management" SMBus Connections

(Write: 0x30 Read: 0x31)

(MASTER)

J4700

(See Table)

Left I/O Board

LED BACKLIGHT

(WRITE: 0x58 READ: 0x59)

SMC "B" SMBus Connections

U9701

Mikey

U6800

EMC1414-A: U5570

(Write: 0x12 Read: 0x13)

ISL6258 - U7000

Battery LED Driver - (Write: 0x36 Read: 0x37)

Microcontroller abstracts

Battery Manager - (Write: 0x16 Read: 0x17)

(Write: 0x72 Read: 0x73)

K21 K78

(* = Multiple options)

SMC "0" SMBus Connections

T29 I2C Connections

For Compliance Testing

actual CDR(s) in plug.

2

1

R5261

MF

1/20W

5%

4.7K

201

2

1

R5260

1/20W

5%

201

4.7K

MF

2

1

R5280

5%

201

MF

1/20W

2.0K

2

1

R5281

201

1/20W

5%

MF

2.0K

2

1

R5270

MF

5%

201

1K

1/20W

2

1

R5271

1K

MF

1/20W

5%

201

2

1

R5251

4.7K

1/20W

5%

MF 201

2

1

R5250

5%

1/20W

MF

4.7K

201

2

1

R5210

8.2K

5%

1/20W

MF

201

2

1

R5211

5% 1/20W

8.2K

MF 201

2

1

R5221

NO STUFF

8.2K

5%

MF

1/20W

201

2

1

R5220

NO STUFF

8.2K

5%

1/20W

MF

201

21

R5223

5%

1/20W

MF

0

201

21

R5222

MF

1/20W

5%

0

201

2

1

R5201

1/20W

1K

5%

MF 201

2

1

R5200

1K

MF

5%

201

1/20W

2

1

R5230

4.7K

MF

1/20W

201

5%

2

1

R5231

201

MF

1/20W

5%

4.7K

2

1

R5235

SDRVI2C:MCU

0

5% 1/20W MF 201

2

1

R5234

SDRVI2C:MCU

5%

1/20W

0

201

MF

21

R5236

MF

SDRVI2C:SB

0

5%

1/20W

201

21

R5237

MF

5%

SDRVI2C:SB

0

1/20W

201

2

1

R5291

2.0K

5% 1/20W MF 201

2

1

R5290

201

MF

5%

1/20W

2.0K

SMBus Connections

SYNC_DATE=12/13/2010

SYNC_MASTER=K21_MLB

MAKE_BASE=TRUE

SMBUS_SMC_A_S3_SCL

MAKE_BASE=TRUE

SMBUS_SMC_A_S3_SDA

=I2C_T29_INLET_THMSNS_SCL

=PP3V3_S3_SMBUS_SMC_A_S3

SMBUS_PCH_CLK

MAKE_BASE=TRUE

SMBUS_SMC_MGMT_SCL

SMBUS_SMC_MGMT_SDA

MAKE_BASE=TRUE

=I2C_BKL_1_SCL

SMBUS_PCH_DATA

MAKE_BASE=TRUE

I2C_DPSDRVA_SDA

=I2C_TCON_SCL

=I2C_TCON_SDA

SMBUS_SMC_0_S0_SDA

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SCL

MAKE_BASE=TRUE

I2C_DPSDRVA_SCL

MAKE_BASE=TRUE

I2C_T29_SCL

MAKE_BASE=TRUE

I2C_T29_SDA

=PP3V3_S0_T29I2C

=I2C_TPAD_SDA

=I2C_T29_INLET_THMSNS_SDA

=I2C_TPAD_SCL

=I2C_CPUTHMSNS_SCL

=I2C_T29AMCU_SDA

=I2C_T29AMCU_SCL

=I2C_PCA9557D_SDA

SMB_B_S0_DATA

SMB_B_S0_CLK

=SMBUS_XDP_SDA

=I2C_VREFDACS_SDA

=SMBUS_XDP_SCL

SMB_A_S3_CLK

SMB_BSA_DATA

=SMBUS_CHGR_SDA

=I2C_VREFDACS_SCL

=I2C_PCA9557D_SCL

SMB_MGMT_CLK

SMB_0_S0_CLK

MAKE_BASE=TRUE

SML_PCH_0_CLK

=PP3V3_S0_SMBUS_PCH

=PP3V42_G3H_SMBUS_SMC_BSA

=SMBUS_BATT_SCL

=SMBUS_BATT_SDA

SMBUS_SMC_BSA_SDA

MAKE_BASE=TRUE

SMB_BSA_CLK

SMBUS_SMC_BSA_SCL

MAKE_BASE=TRUE

SMBUS_SMC_B_S0_SCL

MAKE_BASE=TRUE

SMBUS_SMC_B_S0_SDA

SML_PCH_1_DATA

MAKE_BASE=TRUE

SML_PCH_1_CLK

=PP3V3_S0_SMBUS_PCH

MAKE_BASE=TRUE

SML_PCH_0_DATA

=I2C_DPSDRVA_SDA

=I2C_DPSDRVA_SCL

SMB_MGMT_DATA

=PP3V3_S3_SMBUS_SMC_MGMT

=I2C_BKL_1_SDA

=PP3V3_S0_SMBUS_SMC_B_S0

=PP3V3_S0_SMBUS_PCH

SMB_0_S0_DATA

=I2C_CPUTHMSNS_SDA

=SMBUS_CHGR_SCL

=I2C_LIO_SCL

=I2C_LIO_SDA

=I2C_MIKEY_SDA

=I2C_MIKEY_SCL

SMB_A_S3_DATA

=PP3V3_S0_SMBUS_SMC_0_S0

52 OF 109

2.5.0

051-8871

43 OF 74

72

45

7

16 69

72

65

16 69

62

72

33 71

7

6

48

45

6

48

46

63

31

40

23

31

23

40

40 52

31

40

16 69

7

43

7

6

51

6

51

72

40

72

16 69

7

43

16 69

63

40

7

65

7

43

40

46

52

6

39

6

39

6

39

6

39

40

7

OUT

IN

OUT

S

D

N-CHANNEL

G

D

G

P-CHANNEL

OUT

IN

V+

REFIN+

IN-

OUT

GND

OUT

IN

V+

V-

THRM

V+

V-

THRM

OUT

S

D

N-CHANNEL

G

D

G

P-CHANNEL

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Max VOut: 2.18V at 27.2A

CPU 1.05V VCCIO Current Sense / Filter

GFX/IG VCore Load Side Current Sense / Filter

PBUS Voltage Sense Enable & Filter

DC-In Voltage Sense Enable & Filter

GFX/IG Vcore Voltage Sense / Filter

CPU Vcore Voltage Sense / Filter

Scale: 8.24A / V

Sense R is R7550

Max VOut: 3.3V at 19.77V Input

Sense R is R7510

divider when in S0.

Enables PBUS VSense

RTHEVENIN = 4573 Ohms

Sense R is 0.75mOhm

Gain:161.765x

Sense R is 0.75mOhm

Max VOut: 3.3V at 19.77V Input

Gain: 200x

(200V/V)

CPU VCore Load Side Current Sense / Filter

EDP: 18A TDP: 15.3A

Sense R is R7640, 2mOhm

EDP: 8.5A TDP :7.225A

Scale: 2.5A / V Max VOut: 3.3V at 8.25A

Enables DC-In VSense divider when AC present.

RTHEVENIN = 4573 Ohms

EDP: 33A TDP :28.05A

Gain:110.181x

Scale: 12.1A / V Max VOut: 2.73V at 39.934A

41

2

1

C5330

PLACE_NEAR=U4900.N12:5MM

0201

6.3V

20% X5R

0.22UF

21

R5330

201

1%

1/20W

MF

4.53K

PLACE_NEAR=U4900.N12:5MM

61

2

1

R5302

1%

1/20W

MF

201

100K

2

1

R5301

100K

1%

1/20W

MF

201

41

2

1

C5304

0201

0.22UF

PLACE_NEAR=U4900.L8:5MM

X5R

20%

6.3V

2

1

R5303

1/20W

27.4K

MF

201

1%

PLACE_NEAR=U4900.L8:5MM

2

1

R5304

PLACE_NEAR=U4900.L8:5MM

5.49K

1% MF

201

1/20W

4

1

5

2

3

6

Q5300

SOT-963

NTUD3169CZ

41

21

R5361

1%

4.53K

MF

201

VCCIOISNS_ENG

PLACE_NEAR=U4900.L12:5MM

1/20W

2

1

C5361

PLACE_NEAR=U4900.L12:5MM

0.22UF

VCCIOISNS_ENG

X5R

6.3V

20%

0201

2

1

C5360

6.3V X5R

0.1UF

10%

201

VCCIOISNS_ENG

58 73

3

1

6

4

5

2

U5360

INA210

PLACE_NEAR=R7640.4:5MM

SC70

CRITICAL

VCCIOISNS_ENG

21

R5341

1%

4.53K

MF

1/20W

201

PLACE_NEAR=U4900.M11:5MM

41

2

1

C5341

PLACE_NEAR=U4900.M11:5MM

0.22UF

6.3V

20% X5R

0201

2

1

C5351

0.22UF

20% X5R

6.3V

PLACE_NEAR=U4900.M13:5MM

0201

2

1

C5340

10% X5R

6.3V 201

PLACE_NEAR=U5340.8:3MM

0.1UF

21

R5343

4.42K

1/16W

MF

0.1%

0402

PLACE_NEAR=R7510.4:5MM

21

R5351

1%

4.53K

201

1/20W

MF

PLACE_NEAR=U4900.M13:5MM

2

1

R5344

487K

MF

0.1% 1/16W

0402

57 73

21

R5342

PLACE_NEAR=R7510.3:5MM

1/16W

0402

0.1% MF

4.42K

21

R5352

MF

0402

0.1%

4.42K

1/16W

21

R5353

1/16W

0.1%

0402

MF

4.42K

2

1

R5354

MF

1/16W 402

715K

0.1%

21

R5355

SIGNAL_MODEL=EMPTY

MF

402

0.1%

715K

1/16W

56 57 73

57 73

8

4

9

1

2

3

U5340

OPA2333

DFN

CRITICAL

8

4

9

7

6

5

U5340

DFN

OPA2333

CRITICAL

2

1

C5344

X5R-X7R

16V

470PF

10%

NOSTUFF

201

21

R5345

SIGNAL_MODEL=EMPTY

MF

487K

1/16W

0.1%

0402

21

C5345

201

10%

NOSTUFF

470PF

16V

X5R-X7R

SIGNAL_MODEL=EMPTY

2

1

C5354

201

16V

X5R-X7R

470PF

10%

NOSTUFF

21

C5355

470PF

201

10%

X5R-X7R

16V

SIGNAL_MODEL=EMPTY

NOSTUFF

41

2

1

R5313

27.4K

1/20W

201

MF

1%

PLACE_NEAR=U4900.N9:5MM

2

1

C5314

0201

0.22UF

PLACE_NEAR=U4900.N9:5MM

6.3V

20%

X5R

2

1

R5314

PLACE_NEAR=U4900.N9:5MM

201

5.49K

1/20W

MF

1%

2

1

R5312

201

1/20W

MF

1%

100K

4

1

5

2

3

6

Q5310

SOT-963

NTUD3169CZ

2

1

R5311

1/20W

201

100K

MF

1%

41 52

21

XW5330

PLACE_NEAR=R7550.2:5 MM

SM

41

21

R5320

PLACE_NEAR=U4900.N10:5MM

201

MF

1/20W

4.53K

1%

2

1

C5320

0201

20%

6.3V X5R

0.22UF

PLACE_NEAR=U4900.N10:5MM

21

XW5320

PLACE_NEAR=R7510.2:5 MM

SM

SYNC_DATE=12/13/2010

SYNC_MASTER=K21_MLB

Voltage & Load Side Current Sensing

GND_SMC_AVSS

SMC_GFX_ISENSE

CPUIMVP_ISUMG_R_P

PBUSVSENS_EN_L_DIV

=PP3V3_S0_CPUVCCIOISNS

GND_SMC_AVSS

CPUVSENSE_IN

GND_SMC_AVSS

SMC_PBUS_VSENSE

CPUIMVP_ISUMG_R_N

PDCINVSENS_EN_L_DIV

CPUIMVP_ISUM_IOUT

CPUIMVP_ISNS1_N

CPUVCCIOS0_CS_P

CPUIMVP_ISNS1G_P

SMC_CPU_ISENSE

PBUSVSENS_EN_L

PBUS_S0_VSENSE

=PPBUS_S0_VSENSE

CPUVCCIOS0_CS_N

SMC_CPUVCCIO_ISENSE

GND_SMC_AVSS

CPUIMVP_ISNS1G_N

CPUIMVP_ISUMG_IOUT

GND_SMC_AVSS

CPUVCCIO_IOUT

CPUIMVP_ISUM_R_N

CPUIMVP_ISUM_R_P

CPUIMVP_ISNS1_P

=PP3V3_S0_IMVPISNS

=CHGR_ACOK

GFXVSENSE_IN

=PPGFXVCORE_S0_VSENSE

=PPCPUVCORE_S0_VSENSE

SMC_GFX_VSENSE

SMC_CPU_VSENSE

DCIN_S5_VSENSE

DCINVSENS_EN_L

SMC_DCIN_VSENSE

GND_SMC_AVSS

=PPDCIN_S5_VSENSE

=PBUSVSENS_EN

53 OF 109

2.5.0

051-8871

44 OF 74

40 41 44 45

73

7

40 41 44 45

73

7

40 41 44 45

73

7

40 41 44 45

7

V+

REFIN+

IN-

OUT

GND

IN

OUT

VER 1

VCC

A

1

0

B1

GND

B0

SEL

IN

OUT

IN

OUT

IN

V+

REFIN+

IN-

OUT

GND

V+

REFIN+

IN-

OUT

GND

V+

REFIN+

IN-

OUT

GND

IN

DUR_SEL

DP1

VDD

THERM*

ALERT*

SMDATA

SMCLK

ADDR_SEL

GPIO

THRM_PAD

GND

TH_SEL

SENSE-

SENSE+

DN2/DP3

DP2/DN3

DN1

OUT

IN

BI

OUT

IN

OUT

IN-

IN+ REF

V+

GND

OUT

IN-

IN+ REF

V+

GND

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

MAX VOUT: 3.1V at 16.5A

AirPort Current Sense / Filter

(For R and C)

Max Vdiff: 15 mV

EDP Current: 0.750 A

(For R and C)

PLACEMENT_NOTEs:

SCALE: 5A/ V

PLACEMENT_NOTEs:

HDD Current Sense / Filter

CHARGER BMON High Side (BATTERY DISCHAEGE) Current Sense, MUX & Filter

MAX VOUT: 3.3V AT 0.66A

Max Vdiff: 6.7 mV

EDP Current: 0.67 A

Sense R is R0910, 10mOhm

SCALE: 0.2A / V

Max Vdiff: 7.0 mV

EDP Current: 2.36A

Sense R is R4599, 3mOhm

MAX VOUT: 3V AT 0.825A

Sense R is R4052, 20mOhm

Scale: 0.25A / V

Gain: 200x

MAX VOUT: 2.4V AT 16.5A

DDR3 1V5R1V35 Current Sense / Filter

DC-IN (AMON) Current Sense Filter

PLACEMENT_NOTEs:

SCALE: 5A / V

GAIN: 100X

(100V/V)

Max Vdiff: 24 mV

EDP Current: 12 A

(For R and C)

COMPUTING High Side Current Sense / Filter

LCD Backlight Driver Input Current Sense / Filter

From charger

Charger/Load side

Battery side

PLACEMENT_NOTEs:

(500V/V)

(For R and C)

GAIN: 500X

(For R and C)

PLACEMENT_NOTEs:

across R7050

NOTE: Monitoring current from

battery to PBUS (battery discharge)

Sense R is R7050, 10mOhm

(50V/V)

For production, stuff BMON_PROD

For engineering, stuff BMON_ENG

ISL6259 Gain: 36x

Scale: 2.78A / V

Max VOut: 3.3V at 9.167A

Charger BMON (Production) Solution

Max VOut: 1.4V at 8.25A

EDP Current: 310A

(100V/V)

EDP Current: 10A

Max VOut: 3.3V at 6.6A

Scale: 2A / V

Gain: 50x

Max Vdiff: 31 mV

(200V/V)

(500V/V)

GAIN: 500X

INA (Engineering) Solution

GAIN: 100X

Sense R is R5400, 2mOhm

EDP: 15.5A TDP :13.175A

Sense R is R7020, 20mOhm

COMPUTING High Side Current Sense / Filter & T29/Inlet Temp Sensor

EDP Current: 15.5 A

SCALE: 0.667A / V MAX VOUT: 3.3V AT 2.2A

Sense R is R5400, 2mOhm

EDP Current: 3.5A

Scale: 2.5A / V

DC-In AMON

ISL6259 Gain: 20x

Sense R is R7350, 2mOhm

Read Address: 0x99

Write Address: 0x98

2

1

C5420

BMON:ENG

0.1UF

X5R 201

10%

6.3V

3

1

6

4

5

2

U5420

PLACE_NEAR=R7050.4:5MM

SC70

INA213

CRITICAL

BMON:ENG

52

21

R5420

PLACE_NEAR=U5421.3:5MM

201

1/20W

MF

0

5%

BMON:PROD

2

1

C5421

BMON:ENG

0.1UF

201

6.3V X5R

10%

41

5

6

2

1

3 4

U5421

BMON:ENG

SC70

NC7SB3157P6XG

41

52 73

41

2

1

C5431

0.22UF

20%

6.3V X5R

PLACE_NEAR=U4900.K10:5MM

0201

21

R5431

MF

1%

201

1/20W

4.53K

PLACE_NEAR=U4900.K10:5MM

52

2

1

R5423

201

5% 1/20W

100K

MF

BMON:ENG

432

1

R5400

CRITICAL

1%

0.002

0612

MF

1W

2

1

C5401

0.1UF

0201

10% 16V

X5R-CERM

41

2

1

C5465

Place close to SMC

X5R

20%

6.3V

0.22UF

0201

21

R5465

Place close to SMC

1%

4.53K

201

MF

1/20W

2

1

C5460

0.1UF

201

6.3V X5R

10%

55 73

2

1

C5475

Place close to SMC

0.22UF

X5R

20%

6.3V

AIRPORTISNS_ENG

0201

21

R5475

Place close to SMC

1%

1/20W

MF

201

4.53K

AIRPORTISNS_ENG

2

1

C5485

HDDISNS_ENG

Place close to SMC

6.3V

20%

0.22UF

X5R 0201

21

R5485

1/20W

HDDISNS_ENG

201

Place close to SMC

1%

4.53K

MF

2

1

C5470

X5R 201

10%

0.1UF

6.3V

AIRPORTISNS_ENG

3

1

6

4

5

2

U5470

INA210

SC70

AIRPORTISNS_ENG

3

1

6

4

5

2

U5480

INA211

SC70

HDDISNS_ENG

2

1

C5495

LCDBKLTISNS_ENG

6.3V

0.22UF

Place close to SMC

20%

X5R 0201

21

R5495

4.53K

1%

1/20W

MF

201

LCDBKLTISNS_ENG

2

1

C5490

201

6.3V X5R

10%

0.1UF

LCDBKLTISNS_ENG

3

1

6

4

5

2

U5490

SC70

INA211

LCDBKLTISNS_ENG

36 73

37 73

8

73

8

73

21

R5422

201

1%

300K

MF

1/20W

PLACE_NEAR=U4900.M9:5MM

2

1

C5422

X7R

3300PF

PLACE_NEAR=U4900.M9:5MM

10%

201

10V

1

17

9

14

11

12

16 15

7

8

13

4

2

5

3 10

6

U5400

CRITICAL

EMC1704-2

QFN

7

2

1

R5408

1/20W

5%

MF

10K

NOSTUFF

201

2

1

R5409

10K

5% 1/20W

201

MF

43

2

1

R5411

201

MF

1/20W

0

5%

2

1

R5405

82

5%

201

1/20W

MF

2

1

R5406

201

130

1%

1/20W

MF

HS_TH_SEL

2

1

R5413

5%

NOSTUFF

MF

0

1/20W

201

2

1

R5412

NOSTUFF

MF

0

5%

201

1/20W

41

2

1

C5455

0.22UF

X5R

20%

6.3V

Place close to SMC

0201

21

R5455

4.53K

1/20W

Place close to SMC

1%

MF

201

2

1

C5450

6.3V

10%

X5R

0.1UF

201

45 73

3

1

6

4

5

2

U5450

SC70

INA214

3

1

6

4

5

2

U5460

INA214

SC70

2

1

C5480

402

HDDISNS_ENG

0.1UF

10% 16V X5R

High Side Current Sensing

SYNC_MASTER=K21_MLB

SYNC_DATE=12/13/2010

=PP3V3_S0_HS_COMPUTING_ISNS

ISNS_1V5_S3_P

ISNS_HDD_N

=PP3V3_S3_WLANISNS

GND_SMC_AVSS

SMC_BMON_MUX_SEL

GND_SMC_AVSS

BMON_AMUX_OUT

T29THMSNS_ALERT_L

GND_SMC_AVSS

ISNS_AIRPORT_N

SMC_1V5S3_ISENSE

ISNS_1V5_S3_N

ISNS_1V5S3_IOUT

=PP3V3_S3_1V5S3ISNS

ISNS_HS_COMPUTING_P

=T29THMSNS_D2_P

=T29THMSNS_D2_N

HISIDE_ISENSE_OC

=I2C_T29_INLET_THMSNS_SDA

=PP3V3_S3_BMON_ISNS

CHGR_BMON

SMC_HS_COMPUTING_ISENSE

CHGR_AMON

=PP3V3_S0_BKLTISNS

ISNS_LCDBKLT_IOUT

SMC_WLAN_ISENSE

HS_DUR_SEL

GND_SMC_AVSS

CHGR_CSO_R_N

SMC_BMON_ISENSE

ISNS_LCDBKLT_N

ISNS_LCDBKLT_P

SMC_HDD_ISENSE

SMC_LCDBKLT_ISENSE

CHGR_CSO_R_P BMON_INA_OUT

GND_SMC_AVSS

HS_ADDR_SEL

SMC_DCIN_ISENSE

ISNS_HS_COMPUTING_N

ISNS_P5VWLAN_IOUT

ISNS_AIRPORT_P

ISNS_P5VHDD_IOUT

ISNS_HDD_P

ISNS_HS_COMPUTING_IOUT

ISNS_HS_COMPUTING_P

ISNS_HS_COMPUTING_N

INLET_THMSNS_D1_N

=PPVIN_S5_HS_COMPUTING_ISNS

HS_GPIO

=I2C_T29_INLET_THMSNS_SCL

=PP3V3_S0_HS_COMPUTING_ISNS

=PPVIN_S5_HS_COMPUTING_ISNS_R

INLET_THMSNS_D1_P

GND_SMC_AVSS

=PP3V3_S0_HDDISNS

54 OF 109

2.5.0

051-8871

45 OF 74

7

45

7

40 41 44 45

7

45 73

46

41

7

40 41 44 45

45 73

46

7

45

46

40 41 44 45

7

BI

THRM_PAD

DN2/DP3

DP2/DN3

VDD

SMDATA

SMCLK

GND

DN1

DP1

THERM*/ADDR

ALERT*

BI

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

T29,MLB Bottom & Inlet Proximity Sensors

Placement note:

Detect DDR/5V/3.3V Proximity Temperature

Use GND pin B1 on U3600 for N leg

Place Q5530 between near rear vent on bottom side

Detect T29 Die Temperature

T29 Die

Detect CPU Die Temperature

CPU Proximity Sensor

Place Q5510 next to DDR/5V/3.3V supply on TOP side

Read Address: 0x99

Placement note:

Place U5510 under CPU

Write Address: 0x98

Placement note:

Place Q5520 close to T29 on TOP side

Place Q5540 on MLB bottom side opposite U5400

Placement note:

Replacing caps with 100K PD on ISENSE SMC inputs

2

1

R5512

201

5% 1/20W MF

10K

2

1

R5511

201

10K

5%

1/20W

MF

2

3

1

Q5510

BC846BMXXH

SOT732-3

2

1

C5511

0201

2200PF

X7R-CERM

10V

10%

SIGNAL_MODEL=EMPTY

PLACE_NEAR=U5510.3:5mm

PLACE_NEAR=U5510.2:5mm

9

73

9

73

1

11

7

9

10

6

4

2

5

3 8

U5510

EMC1413

CRITICAL

DFN

2

3

1

Q5520

BC846BMXXH

SOT732-3

33

2

1

C5522

SIGNAL_MODEL=EMPTY

10V

0201

10%

2200PF

X7R-CERM

21

XW5520

PLACE_NEAR=U3600.B1:2mm

SM

2

1

R5523

402

NOSTUFF

10K

5% 1/16W MF-LF

PLACE_SIDE=BOTTOM

2

3

1

Q5530

SOT732-3

BC846BMXXH

2

1

C5523

SIGNAL_MODEL=EMPTY

2200PF

10V

0201

X7R-CERM

10%

2

3

1

Q5540

BC846BMXXH

SOT732-3

43

2

1

C5510

10%

0.1UF

X5R

6.3V

201

21

R5510

201

1/20W

MF

5%

47

2

1

C5512

0201

10V

10%

PLACE_NEAR=U5510.5:5mm

PLACE_NEAR=U5510.4:5mm

SIGNAL_MODEL=EMPTY

X7R-CERM

2200PF

Thermal Sensors

SYNC_DATE=12/13/2010

SYNC_MASTER=K21_MLB

AIRPORTISNS_PROD

RES,MF,1/20W,100K OHM,5,0201,SMD

C5475

1

117S0008

C5495

LCDBKLTISNS_PROD

117S0008

RES,MF,1/20W,100K OHM,5,0201,SMD

1

C5485

HDDISNS_PROD

1

RES,MF,1/20W,100K OHM,5,0201,SMD

117S0008

RES,MF,1/20W,100K OHM,5,0201,SMD

1

VCCIOISNS_PROD

C5361

=MLBBOT_THMSNS_D3_N

=T29THMSNS_D2_P

=MLBBOT_THMSNS_D3_P

=T29THMSNS_D2_N

=T29THMSNS_D2_P

=PP3V3_S0_CPUTHMSNS

CPU_THERMD_P

TP_T29_THERM_DP

T29_THERMD_N

T29_THERMD_P

MAKE_BASE=TRUE

=I2C_CPUTHMSNS_SCL

=I2C_CPUTHMSNS_SDA

CPUTHMSNS_THM_L

CPUTHMSNS_ALERT_L

CPUTHMSNS_D2_P

CPUTHMSNS_D2_N

CPU_THERMD_N

MIN_NECK_WIDTH=0.25 mm

PP3V3_S0_CPUTHMSNS_R

MIN_LINE_WIDTH=0.25 mm

VOLTAGE=3.3V

INLET_THMSNS_D1_P

INLET_THMSNS_D1_N

=T29THMSNS_D2_N

T29_MLBBOT_THMSNS_P

MAKE_BASE=TRUE

T29_MLBBOT_THMSNS_N

=MLBBOT_THMSNS_D3_P

=MLBBOT_THMSNS_D3_N

55 OF 109

2.5.0

051-8871

46 OF 74

46

45 46

46

45 46

7

73

45

45 46

73

46

D

GS

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

518S0793

FAN CONNECTOR

NC

5V DC TACH

MOTOR CONTROL GND

NC

21

R5665

47K

201

MF

1/20W

5%

2

1

R5660

201

47K

1/20W

5% MF

2

1

R5661

100K

MF

1/20W

5%

201

2

1

3

Q5660

SOD-VESM-HF

SSM3K15FV

4

3

2

1

6

5

J5600

FF14A-4C-R11DL-B-3H

F-RT-SM

CRITICAL

SYNC_MASTER=K21_MLB

SYNC_DATE=12/13/2010

Fan

=PP5V_S0_FAN =PP3V3_S0_FAN

SMC_FAN_0_TACH

SMC_FAN_0_CTL

FAN_RT_TACH

FAN_RT_PWM

56 OF 109

2.5.0

051-8871

47 OF 74

6 7

7

40

6

IN

BI

VIN

SW

OUT

FB

EN

NC

THRM

GND

PAD

NC

BI

OUT

IN

OUT

SYM_VER-1

BI

OUT

BI

VCC

GND

SELOE*

D+ D-

Y+ Y-

M+ M-

BI

BIBI

BI

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

tristate and read SMC_SYS_KBDLED:

If LOW, keyboard backlight present If HIGH, keyboard backlight not present

on keyboard backlight flex

R5853 always stuffed, R5854 only

518S0794

SEL=1 Choose USB

IPD Flex Connector

grounded when KB BL flex connected.

SEL=0 Choose pull up/down

518S0793

Keyboard Backlight Connector

J5815 pin 1 is grounded

Keyboard Backlight Driver & Detection

To detect Keyboard backlight, SMC will

2

1

C5710

0.1uF

402

10V

CERM

20%

PLACE_NEAR=J5700.10:1.5MM

17 26 40 61

21

R5704

201

1/20W

5% MF

0

24

4

3

2

1

6

5

J5715

CRITICAL

KB_BL

F-RT-SM

FF14A-4C-R11DL-B-3H

2

1

C5704

NOSTUFF

X5R-CERM

10% 16V

0.1UF

0201

2

9

7

1

8

4

6

3

U5750

CRITICAL

KB_BL

MIC2292

MLF

2

1

R5703

402

MF-LF

1/16W

5%

10K

2

1

R5702

402

MF-LF

1/16W

5%

10K

2

1

C5756

OMIT_TABLE

X5R

50V

0.33UF

10%

0603

2

1

C5720

0.1UF

PLACE_NEAR=J5700.13:1.5MM

10%

201

X5R

6.3V

6

43 48

9

8

7

6

5

4

3

2

14

13

12

11

10

1

16

15

J5700

CRITICAL

F-RT-SM

FF14A-14C-R11DL-B-3H

2

1

C5700

0.1UF

PLACE_NEAR=J5700.1:1.5MM

6.3V X5R

10%

201

6

43 48

6

40 41 48

6

40 41 48 51

6

41 48

2

1

C5732

25V

100PF

201

5%

CERM

PLACE_NEAR=J5700.8:1.5MM

2

1

C5733

25V

100PF

201

PLACE_NEAR=J5700.9:1.5mm

CERM

5%

2

1

C5734

25V

100PF

201

PLACE_NEAR=J5700.11:1.5MM

CERM

5%

2

1

C5735

100PF

25V

201

PLACE_NEAR=J5700.12:1.5MM

CERM

5%

2

1

C5736

25V

100PF

201

PLACE_NEAR=J5700.14:1.5MM

CERM

5%

4 3

21

L5710

DLP0NS

90-OHM

48 68

6

48 73

6

48 73

21

L5720

0402-LF

FERR-120-OHM-1.5A

PLACE_NEAR=J5700.10:1.5MM

21

R5730

0

MF5%

1/20W

201

6

40 41

2

1

C5755

OMIT_TABLE

10%

50V

0.33UF

X5R 0603

2

1

R5755

4.7

KB_BL

MF-LF

1/16W

5%

402

21

L5750

CRITICAL

1098AS-SM

KB_BL

10UH-0.58A-0.35OHM

2

1

C5750

KB_BL

1UF

X5R

10%

10V

BYPASS=U5750.1:2:2 MM

402-1

40

1 2

9

10

8

5 4

3

7 6

U5700

PI3USB102ZLE

TQFN

CRITICAL

2

1

C5701

10% 16V

X5R-CERM

0.1UF

0201

6

48 73

6

48 73 48 68

48 68

2

C5756,C5755

KB_BL

CAP,CER,0.22UF,10%,50V,X5R,0603

138S0704

SYNC_MASTER=K21_MLB

IPD / KBD Backlight

SYNC_DATE=12/13/2010

KBDLED_ANODE

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM

SMC_SYS_KBDLED

SMC_TPAD_RST_L

USB_TPAD_M_N

=PP3V3_S5_TPAD

USB_TPAD_M_P

=PP3V42_G3H_TPAD

=PP5V_S0_KBDLED

USB_TPAD_HUB_P USB_TPAD_HUB_N

SMC_ONOFF_L

SMC_LID

SMC_ONOFF_L

SMC_TPAD_RST_L

=I2C_TPAD_SCL

=I2C_TPAD_SDA

USB_TPAD_CONN_P

USB_TPAD_CONN_N

USB_TPAD_P

USB_TPAD_N

=PP5V_S5_TPAD

SMC_PME_S4_WAKE_L

SMC_LID

=I2C_TPAD_SCL

USB_TPAD_CONN_P

=PP3V3_S5_TPAD

USB_TPAD_P

USB_TPAD_MUX_SEL

USB_TPAD_N

MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.20mm

PP3V3_TPAD_CONN

VOLTAGE=3.3V

USB_TPAD_CONN_N

=I2C_TPAD_SDA

MIN_NECK_WIDTH=0.20mm MIN_LINE_WIDTH=0.5 mm

VOLTAGE=5V

PP5V_TPAD_FILT

KBDLED_SW

MIN_LINE_WIDTH=0.3 MM

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.25 MM

PM_SLP_S4_L

KBDLED_FB

MIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.2 MM

2.5.0

051-8871

48 OF 74

57 OF 109

5

6

7

48

6 7

7

6

40 41 48 51

6

40 41 48

6

41 48

6

43 48

6

43 48

7

48

6

OUT

IN

IN IN

IN

RST*/HOLD*

CE* WP*

SCK

VSS

THRM_PAD

SI/SIO0

SO/SOI1

VDD

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

NOTE: If HOLD* is asserted ROM will ignore SPI cycles.

2

1

C6100

201

10%

0.1UF

X5R

6.3V

2

1

R6101

MF

1/20W

201

5%

3.3K

42 69

42 69 42 69

6

19 42

3

489

2

5

6

7

1

U6100

CRITICAL

WSON

64MBIT

OMIT_TABLE

SST25VF064C

SYNC_DATE=12/13/2010

SYNC_MASTER=K21_MLB

SPI ROM

SPI_MLB_MOSI

SPIROM_USE_MLB

SPI_MLB_CS_L

SPI_MLB_CLK

SPI_MLB_MISO

=PP3V3_S5_ROM

SPI_WP_L

61 OF 109

2.5.0

051-8871

49 OF 74

7

IN

IN-

IN+

OUT+ OUT-

GAINSHDN*

PVDD

NC

PGND

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

SPEAKER AMPLIFIERS

80 HZ < FC < 132 HZ

APN:353S2888

GAIN

SPEAKER LOWPASS

6DB

ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.50MM, MIN_NECK_WIDTH=0.25MM

21

C6210

0.1UF

CRITICAL

6.3V

10%

201

X5R

6

39 73

2

1

C6207

201

6.3V

10%

X5R

0.1UF

2

1

C6201

47UF

6.3V

20%

2012-LLP

POLY-TANT

CRITICAL

21

R6210

1/20W

5%

201

MF

0

6

39

6

39 73

C2

A1

A2

B1

C1

A3

B3

C3

U6210

MAX98300

WLP

2

1

R6212

1/20W

5%

201

MF

100K

21

C6211

CRITICAL

0.1UF

X5R 201

10%

6.3V

2

1

R6211

1/20W

5%

201

MF

100K

2

1

R6213

MF

100K

5%

NOSTUFF

1/20W

201

21

R6214

0

5%

1/20W

MF

201

SYNC_MASTER=K21_MLB

SYNC_DATE=12/13/2010

AUDI0: SPEAKER AMP

SPKRAMP_R_P_OUT

MIN_LINE_WIDTH=0.10 mm

MIN_NECK_WIDTH=0.10 MM

R_AMP_GAIN

AUD_GPIO_3

SPKRAMP_INR_P

MAX98300_R_P

SPKRAMP_INR_N

=PP5V_S3_AUDIO_AMP

MAX98300_R_N

R_SPKRAMP_SHDN

MIN_NECK_WIDTH=0.25 mm

VOLTAGE=5V

MIN_LINE_WIDTH=0.5 mm

PP5V_S3_U6210

SPKRAMP_R_N_OUT

MIN_LINE_WIDTH=0.10 mm

MIN_NECK_WIDTH=0.10 MM

62 OF 109

2.5.0

051-8871

50 OF 74

B2

6

51 73

73

7

73

6

51 73

SW

BOOST

VIN

BIAS

SHDN*

GND

NC

FB

PAD

THRM

NC

IN

BI

D

GS

IN

SHLD_PIN

NEG

POS

NEG

SYS_DETECT

SDA

SCL

POS

NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

K99-Specific

Battery Connector

518S0508

MLB to LIO Power Cable Connector

60MA MAX OUTPUT

Vout = 3.425V

<Ra>

Supply needs to guarantee 3.31V delivered to SMC VRef generator

3.425V "G3Hot" Supply

518-0369

518S0519

Right Speaker Connector

(Switcher limit)

<Rb>

Vout = 1.25V * (1 + Ra / Rb)

(For development only)

Debug LEDs

2

1

C6999

22UF

CRITICAL

6.3V

20%

X5R-CERM-1 603

21

L6995

33UH-20%-0.39A-0.435OHM

CRITICAL

DP418C-SM

2

1

C6994

402

CERM

10V

0.22UF

10%

2

1

C6990

10% 25V

X5R-CERM

603

2.2UF

6

9

48

5

1

3

2

U6990

DFN

LT3470A

CRITICAL

3

2

1

D6905

BAT30CWFILM

SOT-323

CRITICAL

21

R6905

1/8W

5%

805

MF-LF

10

6

43

6

43

2

1

3

D6950

CRITICAL

RCLAMP2402B

SC-75

NO STUFF

2

1

R6950

201

MF

1/20W

5%

10K

2

1

C6950

10% 25V X5R 402

0.1UF

2

1

C6951

1UF

10% 16V

402

X5R

2

1

R6941

S3_S0_LED

MF-LF

1/16W

5%

1K

402

2

1

R6940

201

S3_S0_LED

1K

5%

1/20W

MF

2

1

3

Q6940

S3_S0_LED

SOD-VESM-HF

SSM3K15FV

K

A

D6920

GREEN-3.6MCD

2.0X1.25MM-SM

S3_S0_LED

K

A

D6910

2.0X1.25MM-SM

GREEN-3.6MCD

S3_S0_LED

23 25 40 61

2

1

4

3

J6903

M-RT-SM

78171-0002

CRITICAL

6

50 73

6

50 73

2

1

C6906

0.01UF

201

X5R

10V

10%

2

1

C6905

0.01UF

603

CERM

50V

20%

6

5

4

3

2

1

J6900

WTB-PWR-M82

CRITICAL

M-RT-SM

9

8

7

6

5

4

3

2

1

13

12

11

10

J6950

CRITICAL

F-RT-TH

BAT-K99

8 7 6 54

3

2

1

J6955

SM

HALL-SENSOR-MLB-PADS-K99

OMIT_TABLE

2

1

C6955

10%

NO STUFF

0.001UF

50V

CERM

402

21

R6920

805

4.7

1/8W

5%

MF-LF

2

1

R6995

MF-LF

1/16W

348K

402

1%

2

1

R6996

200K

1% 1/16W MF-LF

402

21

R6961

402

0

5% 1/16W MF-LF

2

1

C6995

402

22PF

5% 50V CERM

DC-In & Battery Connectors

SYNC_DATE=11/11/2010

SYNC_MASTER=K21_MLB

PPBUS_G3H_R

PPBUS_G3H

=PP5V_S3_LIO_CONN

PPVBAT_G3H_CONN

SYS_DETECT_L

=SMBUS_BATT_SDA

DBGLED_S0

DBGLED_S3

=PP18V5_DCIN_CONN

PPDCIN_G3H_OR_PBUS

SPKRAMP_R_N_OUT

SPKRAMP_R_P_OUT

DBGLED_S0_D

MIN_LINE_WIDTH=0.6 mm

PPDCIN_G3H_OR_PBUS_R

VOLTAGE=18.5V

MIN_NECK_WIDTH=0.25 mm

P3V42G3H_BOOST

DIDT=TRUE

=PP3V42_G3H_HALL

ALL_SYS_PWRGD

=SMBUS_BATT_SCL

VOLTAGE=18.5V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

PPVIN_G3H_P3V42G3H

P3V42G3H_SW

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm SWITCH_NODE=TRUE DIDT=TRUE

SMC_LID

SMC_LID_R

=PP3V3_S3_DBGLEDS

=PP3V42_G3H_REG

P3V42G3H_FB

69 OF 109

2.5.0

051-8871

51 OF 74

7

6 7

6

52

6

6 7

52

6 7

6

40 41 48

6

7

OUT

IN

BI

OUT

AMON BMON ACOK

LGATE

PHASE

BOOT

SGATE AGATE

CSIP CSIN

DCIN

VNEG CSOP CSON

THRM_PAD

PGND

VDDP

VDD

BGATE

UGATE ICOMP VCOMP

ACIN

SDA VFRQ CELL

VHST

SCL

SMB_RST_N

IN

S

G

D

IN

G

D

S

G

D

S

G

D

S

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

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SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

f = 400 kHz

Reverse-Current Protection

sparkitecture requirements

FIXME: C7001 SAME AS C7000?

TO/FROM BATTERY

DUE TO DIFFERENT CURRENT ON _P AND _N. (FROM INTERSIL)

(PPVBAT_G3H_CHGR_R)

TO SYSTEM

Max Current = 8A

Inrush Limiter

through body diodes:

* PBUS through Q7085, Charger TOP FETs and

(CHGR_AGATE)

Q7055.

This node is powered

* DCIN through Q7080.

(AGND)

20V/V

36V/V

(OD)

(CHGR_DCIN)

(CHGR_SGATE)

30mA max load

(GND)

(CHGR_CSO_P)

(CHGR_CSO_N)

(PPVBAT_G3H_CHGR_R)

(CHGR_BGATE)

ACIN pin threshold is 3.2V, +/- 50mV

Input impedance of ~40K meets

FROM ADAPTER

Float CELL for 1S

* R7051 HAS 2.2OHM TO COMPENSATE UNBALANCED VOLTAGE

DIVIDER SETS ACIN THRESHOLD AT 12.18V

2

1

R7011

201

MF

1/20W

1%

10.5K

2

1

C7042

10%

6.3V X5R 201

0.1UF

2

1

C7016

10% 16V X5R-X7R 201

470PF

2

1

R7016

MF

220

1/20W

1%

201

2

1

C7015

10% 16V

X5R-X7R

201

470PF

2

1

R7015

1%

MF

1/20W

201

255K

2

1

C7002

10% 10V X5R 402

1UF

2

1

C7000

10% 10V X5R 402-1

1UF

21

R7001

1/16W MF-LF

5%

402

4.7

2

1

R7010

201

MF

1/20W

1%

30.1K

21

XW7000

PLACE_NEAR=U7000.29:1mm

SM

PLACE_NEAR=U7000.22:1mm

2

1

C7001

10% 10V X5R 402

1UF

2

1

C7021

0.1UF

10%

402

25V X5R

2

1

C7022

0.1UF

10% 25V X5R 402

2

1

C7020

10% 16V X7R

0.047UF

402

2

1

C7025

PLACE_NEAR=U7000.25:2mm

10% 10V CERM 402

0.22UF

321

4

5

Q7035

RJK0305DPB

LFPAK-HF

CRITICAL

21

R7022

201

5%

1/20W

10

MF

21

R7021

10

MF

5%

201

1/20W

2

1

C7030

25V

CASE-D3L

POLY-TANT

20%

33UF-0.06OHM

CRITICAL

2

1

C7031

25V

20%

CASE-D3L

CRITICAL

33UF-0.06OHM

POLY-TANT

21

F7040

1206

8AMP-24V

CRITICAL

2

1

R7081

201

MF

1/20W

5%

62K

2

1

C7005

20% 25V X5R 603

0.22UF

45

43

2

1

C7011

10% 10V X5R 201

0.01UF

2

1

C7050

10% 10V X5R 402

0.47UF

2

1

C7026

10% 16V X7R 201

1000PF

41 44

34

12

R7050

0.01

0.5%

1W

MF

0612-3

432

1

R7020

MF-LF 0612

1W

0.5%

CRITICAL

0.020

2

1

C7037

10% 50V X7R 402

0.001UF

PLACE_NEAR=Q7030.5:1.5mm

2

1

C7045

1000PF

10%

201

X7R

16V

PLACE_NEAR=L7030.2:1.5mm

8

12

4

20

19

7

24

29

13

26

10

11

23

22

21

5

2

18

17

28

27

6

25

15

16

9

1

14

3

U7000

CRITICAL OMIT_TABLE

ISL6259HRTZ

TQFN

2

1

R7002

NO STUFF

100K

5%

1/20W

MF

201

61

321

4

5

Q7055

CRITICAL

SI7615DN

PWRPK-1212-8

2

1

R7013

201

1%

100

MF

1/20W

3

2

1

D7005

BAT30CWFILM

SOT-323

CRITICAL

2

1

C7085

10%

0.1UF

402

X5R

25V

2

1

R7080

201

MF

1/20W

5%

100K

2

1

C7041

CRITICAL

CASE-B2

62UF

20% 11V

ELEC

21

R7005

201

5%

MF

1/20W

20

2

1

C7035

10% 25V X5R 603-1

1UF

2

1

C7036

10% 25V X5R 603-1

1UF

21

R7000

0

1/20W

MF

5%

201

6

40 41 42

5A

5

4

1

Q7080

SI5419DU

POWERPAK

CRITICAL

5A

5

4

1

Q7085

POWERPAK

SI5419DU

CRITICAL

2

1

C7043

CRITICAL

11V

CASE-B2

ELEC

20%

62UF

2

1

C7040

ELEC

11V

CASE-B2

62UF

CRITICAL

20%

2

1

C7014

25V X5R 603-1

1UF

10%

2

1

C7013

10% 25V X5R 402

0.1UF

2

1

C7012

0.01UF

10% 25V X7R 402

2

1

C7017

10% 25V X5R 805

10UF

21

R7051

201

MF

1/20W

5%

2.2

21

R7052

201

MF

1/20W

5%

0

3

2

1

L7030

CRITICAL

4.7UH-13.1A

FDA1240F-SM

2

1

R7085

402

470K

1% 1/16W MF-LF

2

1

R7086

402

332K

1% 1/16W MF-LF

321

4

5

Q7030

CRITICAL

FDMS0355S

POWER56

SYNC_MASTER=K21_MLB

PBus Supply & Battery Charger

SYNC_DATE=11/30/2010

CHGR_CSI_N

CHGR_CSI_P

DIDT=TRUE

SWITCH_NODE=TRUE

CHGR_PHASE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

CHGR_UGATE

GATE_NODE=TRUE

DIDT=TRUE

MIN_NECK_WIDTH=0.4 mm VOLTAGE=18.5V

MIN_LINE_WIDTH=0.6 mm

PPDCIN_G3H_CHGR

CHGR_BOOT

DIDT=TRUE

CHGR_DCIN

=PP3V42_G3H_CHGR

PP5V1_CHGR_VDD

VOLTAGE=5.1V

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.2 mm

CHGR_AGATE_DIV

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.25 mm

VOLTAGE=18.5V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

PPDCIN_G3H_OR_PBUS

CHGR_ACIN

=PPBUS_G3H

CHGR_SGATE

CHGR_BGATE

VOLTAGE=8.4V

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm

PPVBAT_G3H_CONN

CHGR_CSO_R_N

CHGR_CSI_R_P

CHGR_SGATE_DIV

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

PP5V1_CHGR_VDDP

VOLTAGE=5.1V

VOLTAGE=18.5V

MIN_LINE_WIDTH=0.6 mm

PPDCIN_G3H_INRUSH

MIN_NECK_WIDTH=0.4 mm

CHGR_VFRQ

CHGR_CSI_R_N

SMC_RESET_L

CHGR_VCOMP_R

CHGR_CSO_R_P

CHGR_VNEG_R

CHGR_RST_L =SMBUS_CHGR_SCL

CHGR_CELL

=SMBUS_CHGR_SDA

CHGR_VCOMP CHGR_VNEG

=CHGR_ACOK

CHGR_BMON

CHGR_AMON

CHGR_DCIN_D_R

VOLTAGE=8.4V

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.6 mm

PPVBAT_G3H_CHGR_REG

=PPDCIN_S5_CHGR

VOLTAGE=8.4V

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 MM

PPVBAT_G3H_CHGR_R

CHGR_CSO_N

CHGR_CSO_P

CHGR_ICOMP

GND_CHGR_AGND

VOLTAGE=0V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

DIDT=TRUE

GATE_NODE=TRUE

CHGR_LGATE

CHGR_AGATE

70 OF 109

2.5.0

051-8871

52 OF 74

72

7

51

7

6

51

45 73

73

45 73

7

72

OUT

IN

FB

EN

PVCC

VCC

SREF

VO

OCSET

PGOOD

FSEL

RTN

PHASE

LGATE

UGATE

BOOT

PGND

GND

SET0

SET1

VID0

VID1

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

6A Max Output

f = 300 kHz

0 0 0.9V

OCP = R7141 x 8.5uA / R7140

OCP = 8.5A

VID1 VID0 Voltage

1 0 0.8V

(VCCSAS0_VO)

(VCCSAS0_OCSET)

61

21

XW7100

PLACE_NEAR=U7100.3:1mm

SM

2

1

R7101

2.2

5%

402

1/16W MF-LF

2

1

C7101

CRITICAL

603

10V X5R

20%

10UF

2

1

R7130

MF-LF

5%

1/10W

0

603

2

1

C7130

10V

402

10%

CERM

0.22UF

21

C7140

25V

5%

402

NP0-C0G

1000PF

2

1

R7141

201

1K

1%

1/20W

MF

2

1

R7142

201

1/20W MF

1K

1%

2

1

C7122

PLACE_NEAR=Q7100.2:1.5mm

1000PF

25V

NP0-C0G

5%

402

43

21

R7140

CRITICAL

1W

0612

MF-1

1%

0.001

21

L7100

CRITICAL

1.0UH-7.7A

FDV0630H-SM

2

1

C7120

10% 16V

0805

CRITICAL

10UF

X5R-CERM

2

1

C7121

X7R-CERM

16V

402

0.1UF

10%

12

5

6

19

17

7

9

8

4

20

16

14

2

11

1

3

13

10

15 18

U7100

UTQFN

ISL95870AH

CRITICAL

2

1

R7147

113K

1%

MF

1/20W

201

2

1

R7148

140K

1%

MF

1/20W

201

2

1

R7149

MF

1/20W

1%

47.5K

201

12

2

1

C7119

CRITICAL

10% 16V

X5R-CERM

10UF

0805

2

1

C7103

0.022UF

402

16V

10%

CERM-X5R

2

1

XW7101

PLACE_NEAR=C1763.2:3mm

SM

8

732

54

6

1

Q7100

POWERPAK-6X3.7

CRITICAL

SIZ710DT

2

1

C7141

20% 2V TANT CASE-B2-SM

270UF

2

1

C7123

ELEC

CASE-B2

11V

20%

62UF

CRITICAL

2

1

C7105

201

47PF

5% 25V NP0-C0G

2

1

R7103

0

5%

MF

1/20W

201

2

1

C7102

603

10% 16V

2.2UF

X5R

System Agent Supply

SYNC_MASTER=K21_MLB

SYNC_DATE=12/13/2010

=PPVIN_S0_VCCSAS0

=PVCCSA_EN

=PPVCCSA_S0_REG

VCCSAS0_CS_P

=PP5V_S0_VCCSA

VCCSAS0_CS_N

PVCCSA_PGOOD

VCCSAS0_FSEL

PPVCCSA_S0_REG_R

MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

VCCSAS0_BOOT_RC

DIDT=TRUE

VCCSAS0_VBST

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

VCCSAS0_DRVL

DIDT=TRUE

CPU_VCCSA_VID<1>

VCCSAS0_SET0

VCCSAS0_OCSET

VCCSAS0_RTN

MIN_LINE_WIDTH=0.6 mm

PP5V_S0_VCCSAS0_VCC

VOLTAGE=5V

MIN_NECK_WIDTH=0.2 mm

CPU_VCCSASENSE

VCCSAS0_SREF

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

SWITCH_NODE=TRUE

VCCSAS0_LL

DIDT=TRUE

VCCSAS0_DRVH

MIN_NECK_WIDTH=0.2 mm GATE_NODE=TRUE

MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V

VCCSAS0_AGND

VCCSAS0_VO

VCCSAS0_SET1

71 OF 109

2.5.0

051-8871

53 OF 74

7

73

7

73

OUT

IN IN

EN

EN2EN1

DRVL2

SKIPSEL1 SKIPSEL2

DRVL1

V5SW

VBST2VBST1

VREG5

VREF2

VIN

THRM_PAD

SW2SW1

RF

PGOOD2PGOOD1

GND

DRVH2DRVH1

CSP2 CSN2CSN1

COMP2COMP1

VREG3

VFB1 VFB2

OCSEL

MODE

CSP1

OUT

IN

G

D

S

G

D

S

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

F=400KHZ

353S2678

Vout = 3.3V

6.5A MAX OUTPUT7.2A MAX OUTPUT

Vout = 5.0V

F=400KHZ

2

1

C7200

1UF

10%

X5R

16V

402

21

L7260

CRITICAL

PCMC063T-SM

2.5UH-14A

2

1

C7241

1UF

X5R

10% 16V

402

2

1

C7264

X5R

402

10% 25V

0.1UF

2

1

C7224

0.1UF

X5R

25V

402

10%

2

1

C7252

20%

POLY-TANT

150UF

6.3V

CRITICAL

CASE-B2-SM

2

1

C7281

X5R

10%

1UF

16V

402

2

1

C7203

CERM

6.3V

10%

402

1UF

2

1

C7205

0603

10V

20%

10UF

X5R

2

1

R7206

249K

1/20W

1%

MF

201

61

2

1

XW7261

SM

PLACE_NEAR=L7260.2:3mm

2

1

C7201

10V

10%

402

CERM

0.22UF

2

1

R7260

1%

201

1/20W MF

23.2K

2

1

R7261

1%

10K

201

1/20W MF

2

1

R7220

1%

41.2K

MF 201

1/20W

2

1

R7221

1%

10K

201

MF

1/20W

2

1

C7240

CRITICAL

ELEC

62UF

11V

CASE-B2

20%

21

XW7200

PLACE_NEAR=U7201.28:1mm

SM

2

1

R7216

4.42K

201

1% 1/20W MF

21

R7246

1/20W

201

1%

1.54K

MF

2

1

XW7260

PLACE_NEAR=L7260.1:3mm

SM

21

C7218

0.1UF

402

16V

10%

X5R

21

R7247

201

1/20W

MF

1.33K

1%

2

1

R7256

1%

201

4.22K

1/20W

MF

2

1

XW7220

PLACE_NEAR=L7220.1:3mm

SM

2

1

XW7221

PLACE_NEAR=L7220.2:3mm

SM

2

1

R7236

201

1%

1/20W

MF

7.5K

2

1

R7237

201

20K

MF

1%

NO STUFF

1/20W

2

1

XW7262

SM

PLACE_NEAR=L7260.2:3mm

2

1

XW7222

PLACE_NEAR=L7220.1:3mm

SM

2

1

C7292

150UF-0.018OHM-1.8A

CRITICAL

TANT

20%

6.3V

CASE-B2-SM

2

1

R7239

NO STUFF

20K

1%

201

MF

1/20W

2

1

C7239

220PF

201

10%

X7R-CERM

25V

2

1

R7238

201

1/20W

MF

7.5K

1%

2

1

C7238

201

4700PF

X7R

10V

10%

61 61

21

R7248

NO STUFF

5%0201MF1/20W

2

1

R7249

0

201

1/20W

MF

5%

2

1

C7272

1000PF

PLACE_NEAR=L7260.2:1.5mm

X7R

10% 16V

201

2

1

C7283

201

1000PF

10%

X7R

PLACE_NEAR=Q7260.2:1.5mm

16V

2

1

C7270

PLACE_NEAR=Q7220.5.2:1.5mm

201

10%

X7R

16V

1000PF

2

1

C7271

X7R 201

16V

10%

PLACE_NEAR=L7220.1.2:1.5mm

1000PF

29

22

13

23

16

9

26

31

2

33

25

32

19

6

3

20

5

14

11

28

21

4

12

27

30

24

1

18

7

17

8

15

10

U7201

CRITICAL

QFN

TPS51980

2

1

C7282

ELEC

CRITICAL

CASE-B2

11V

20%

62UF

2

1

R7245

0

5%

MF-LF

402

1/16W

2

1

R7251

PLACE_NEAR=U7201.4:2mm

0

5% 1/20W MF 201

2

1

R7252

PLACE_NEAR=U7201.21:2mm

0

MF

1/20W

5%

201

61

2

1

C7236

201

X7R

4700PF

10V

10%

2

1

C7237

0201

270PF

16V

X7R-CERM

10%

21

C7288

10%

X5R 402

16V

0.1UF

1

2

R7264

0

5%

MF-LF 402

1/16W

321

4

5

Q7225

CRITICAL

RJK03E0DNS

HWSON-8

321

4

5

Q7220

HWSON-8

RJK03E0DNS

CRITICAL

2

1

C7254

62UF

20%

6.3V

CASE-B2S

ELEC

CRITICAL

2

1

C7253

CASE-B2-SM

6.3V

20%

POLY-TANT

CRITICAL

150UF

8

732

54

6

1

Q7260

POWERPAK-6X3.7

CRITICAL

SIZ710DT

21

L7220

PCMC063T-SM

1.5UH-20%-18A-15MOHM

CRITICAL

2

1

C7242

CRITICAL

62UF

20%

11V

ELEC

CASE-B2

2

1

C7284

CRITICAL

62UF

11V

ELEC

CASE-B2

20%

2

1

C7290

10UF

20%

10V X5R 603

2

1

C7250

10UF

20%

10V X5R 603

5V / 3.3V Power Supply

SYNC_DATE=11/30/2010

SYNC_MASTER=K21_MLB

P3V3S5_COMP2

P5VS3_EN_R

P5VS3_PGOOD

P5VS3_VFB1

=PP5V_S5_LDO

=PP5V_S3_REG

P5VP3V3_VREF2

=P3V3S5_EN

=P5VS3_EN

P5VS3_VFB1-R

P5VP3V3_VREG3

P3V3S5_VFB2_R

=P5V3V3_REG_EN

MIN_NECK_WIDTH=0.2 mm

P3V3S5_DRVL

GATE_NODE=TRUE

DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm

P3V3S5_DRVH

GATE_NODE=TRUE

DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm

P5VS3_DRVH

DIDT=TRUE

GATE_NODE=TRUE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

P5VS3_COMP1

P5VS3_COMP1_R

P5VS3_CSN1

P5VP3V3_VREF2

P5VS3_FUNC

P5VP3V3_VREG3

P3V3S5_VBST_R MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm DIDT=TRUE

P3V3S5_RF

P3V3S5_PGOOD

P3V3S5_EN_R

P3V3S5_COMP2_R

VOLTAGE=0V

MIN_LINE_WIDTH=0.6 mm

GND_P5VP3V3_SGND

MIN_NECK_WIDTH=0.2 mm

P5VP3V3_VREF2

P3V3S5_LL

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.6 mm

P3V3S5_CSP2

P3V3S5_VFB2

P3V3S5_CSP2_R

P3V3S5_CSN2

MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm

P5VS3_VBST_R

MIN_LINE_WIDTH=0.6 mm

P5VS3_VBST

MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

P5VS3_CSP1_R

MIN_LINE_WIDTH=0.6 mm

GATE_NODE=TRUE

DIDT=TRUE

P5VS3_DRVL

MIN_NECK_WIDTH=0.2 mm

P5VS3_CSP1

SWITCH_NODE=TRUE

DIDT=TRUE

P5VS3_LL MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

P3V3S5_VBST

=PP3V3_S5_REG

=PP5V_S3_REG

=PPVIN_S5_P5VP3V3

54 OF 74

72 OF 109

2.5.0

051-8871

7

54

7 7

54

7

IN

V5IN

REFIN

S5

VREF

S3

MODE TRIP

SW

DRVL

PGOOD

VDDQSNS

VTT

VTTSNS

VTTREF

DRVH

VBST

VLDOIN

THRM

VTT

GND

PGND

PADGND

OUT

IN

OUT

G

D

S

G

D

S

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(Q7335 limit)

14.1A max output

f = 400 kHz

Vout = 1.5V

C7360, C7361 close to memory

VTT Enable

VDDQ/VTTREF Enable

(DDRREG_LL)

(DDRREG_DRVL)

10mA max load

(DDRREG_VDDQSNS)

(DDRREG_DRVH)

2

1

C7300

PLACE_NEAR=U7300.12:1mm

10V

603

20%

X5R

10UF

2

1

C7332

1UF

25V X5R 603-1

10%

21

C7325

402

25V X5R

0.1UF

10%

2

1

C7333

0.001UF

402

X7R

50V

10%

2

1

C7345

6.3V

603

X5R

10UF

20%

2

1

C7346

X7R 402

10% 50V

0.001UF

2

1

XW7301

PLACE_NEAR=C7340.1:1mm

SM

61

1

5

4

3

6

2

9

1512

18

21

13

16

17

8

20

10

19

7

11

14

U7300

CRITICAL

QFN

TPS51916

8

21

XW7360

PLACE_NEAR=C7361.1:3mm

SM

2

1

XW7300

SM

PLACE_NEAR=U7300.21:1mm

2

1

C7350

10V

CERM

0.22UF

402

10%

2

1

C7360

X5R

10UF

20%

6.3V

CRITICAL

603

PLACE_NEAR=C3101.1:1mm

8

26

2

1

C7315

402

X5R

0.1UF

10%

PLACE_NEAR=U7300.6:1mm

16V

2

1

C7361

PLACE_NEAR=C3101.1:3mm

CRITICAL

10UF

603

X5R

6.3V

20%

2

1

R7317

PLACE_NEAR=U7300.19:3mm

201

MF

1/20W

1%

200K

2

1

R7315

1%

PLACE_NEAR=U7300.8:5mm

20K

1/20W

MF

201

2

1

R7316

PLACE_NEAR=U7300.8:5mm

MF

100K

1%

1/20W

201

2

1

C7316

402

CERM

16V

0.01UF

10%

PLACE_NEAR=U7300.8:1mm

2

1

C7301

PLACE_NEAR=U7300.2:1mm

10V

20%

603

10UF

X5R

21

R7325

0

402

MF-LF

5%

1/16W

21

L7330

MPCG1040LR88-SM

0.88UH-20%-19A-2.3MOHM

CRITICAL

43

21

R7350

CRITICAL

1%

1/4W

0.002

MF-LF

1206

45 73

321

4

5

Q7330

PQFN3.3X3.3

IRFHM831PBF

CRITICAL

321

4

5

Q7335

CRITICAL

PQFN3.3X3.3

IRFHM830DPBF

2

1

C7330

20% 11V ELEC CASE-B2

CRITICAL

62UF

2

1

C7331

20% 11V ELEC

62UF

CASE-B2

CRITICAL

2

1

C7334

ELEC

11V

20%

62UF

CRITICAL

CASE-B2

2

1

R7318

201

MF

1/20W

1%

68K

PLACE_NEAR=U7300.18:3mm

2

1

C7340

B2-SM

POLY-TANT

2.0V

20%

330UF

CRITICAL

2

1

C7341

B2-SM

POLY-TANT

2.0V

20%

330UF

CRITICAL

1.5V DDR3 Supply

SYNC_MASTER=K21_MLB

SYNC_DATE=12/13/2010

MIN_LINE_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.17 mm

DDRREG_VDDQSNS

DIDT=TRUE

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.17 mm

DDRREG_LL

=PPVTT_S0_DDR_LDO

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.17 mm

VOLTAGE=0V

GND_DDRREG_SGND

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.17 mm

DIDT=TRUE

GATE_NODE=TRUE

DDRREG_DRVL

=PPVIN_S3_DDRREG

ISNS_1V5_S3_P

=PPDDR_S3_REG

DDRREG_TRIP

MIN_NECK_WIDTH=0.17 mm

MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

DDRREG_DRVH

GATE_NODE=TRUE

DIDT=TRUE

DDRREG_VBST_RC

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.17 mm

DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm

DDRREG_VBST

MIN_NECK_WIDTH=0.17 mm

PPDDR_S3_REG_R

=DDRREG_EN

=PPVTT_S3_DDR_BUF

DDRREG_VTTSNS

DDRREG_PGOOD

ISNS_1V5_S3_N

=PPVIN_S0_DDRREG_LDO

=PP5V_S3_DDRREG

=DDRVTT_EN

DDRREG_FB

DDRREG_1V8_VREF

DDRREG_MODE

73 OF 109

2.5.0

051-8871

55 OF 74

7

31

7

31

IN

OUT

IN

OUT

IN

OUT

NC

OUT

NC

IMAXA

SR

IMAXB

ALERT*

THERMA THERMB

VDIO

POKB

CLK

EN

POKA

CSPA3 VRHOT*

DRVPWMA

GNDSB

GNDSA

THRM

CSPB1

DHB LXB

BSTB

DLA2

DLB

CSNB

FBB

LXA1

DHA1

BSTA1

TON

DLA1

CSPA1

CSPAAVE

FBA

CSNA

BSTA2

CSPA2

DHA2 LXA2

VCC

VDDA

VDDB

PAD

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

21

R7401

1/16W MF-LF

5%

10

402

2

1

C7401

X5R-CERM

2.2UF

402

10V

20%

2

1

C7402

PLACE_NEAR=U7400.24:2mm

402

10V X5R-CERM

20%

2.2UF

12 66

2

1

C7414

NO STUFF

100PF

CERM 201

25V

5%

21

R7406

1/20W

300

MF

5%

201

21

R7410

5%

1

MF

1/20W

201

21

C7408

NO STUFF

0402

X5R-CERM

10% 10V

0.039UF

25

61

10 41 66

57

57 73

2 1

XW7400

SM

2

1

C7403

PLACE_NEAR=U7400.15:2mm

402

2.2UF

20% 10V X5R-CERM

2

1

R7464

1%

200K

1/20W

NO STUFF

MF 201

2

1

C7415

201

25V

5%

100PF

CERM

NO STUFF

21

R7440

201

1/20W

MF

5%

10

21

R7441

201

10

1/20W

MF

5%

12 66

2

1

C7440

1000PF

16V

10%

X7R 201

2

1

C7441

201

16V X7R

10%

1000PF

2

1

C7412

201

X7R

10% 16V

1000PF

21

R7413

5%

MF

1/20W

10

201

12 66

2

1

C7422

201

10%

X7R

16V

1000PF

21

R7423

5%

10

MF

1/20W

201

44 57 73

2

1

C7419

201

5%

NO STUFF

25V CERM

100PF

2

1

C7418

201

5% 25V CERM

100PF

NO STUFF

57 73

2

1

C7442

NO STUFF

0.01UF

X5R

10%

201

10V

2

1

R7479

1%

54.9

201

MF

PLACE_NEAR=U7400.18:2mm

1/20W

2

1

R7480

PLACE_NEAR=U7400.16:2mm

1/20W

201

MF

1%

130

57

2

1

R7460

MF

1/20W

201

215K

1%

2

1

R7461

201

137K

1%

MF

1/20W

21

R7402

402

1/16W

1%

MF-LF

90.9K

2

1

R7468

1% 1/20W MF 201

5.76K

2

1

R7466

5.76K

1%

MF

1/20W

201

2

1

C7407

10%

0.0022UF

CERM

50V

402

2

1

C7404

10%

2200PF

10V X7R-CERM 0201

2

1

R7469

CRITICAL

0603

100KOHM-1%-100MW

2

1

R7467

100KOHM-1%-100MW

CRITICAL

0603

21

C7409

470PF

402

50V

NP0-C0G

5%

2

1

C7443

10V X5R

10%

201

0.01UF

NO STUFF

2

1

R7462

1/20W

201

1%

MF

215K

2

1

R7463

201

137K

1% 1/20W MF

2

1

R7465

201

10K

1% 1/20W MF

21

R7412

1%

1/20W

MF

201

6.34K

2

1

C7444

47PF

5%

201

NP0-C0G

25V

NO STUFF

5

16

15

24

40

2

41

34

33

32

10

19

12

27

21

30

29

7

3

6

4

1

31

14

25

23

13

26

22

8

35

39

38

36

9

37

18

11

28

20

17

U7400

QFN

MAX15092GTL

CRITICAL

21

R7403

5%

2.2

1/16WMF-LF

402

21

R7422

MF

1/20W

1%

8.25K

201

CPU IMVP7 & AXG VCore Regulator

SYNC_DATE=12/13/2010

SYNC_MASTER=K21_MLB

CPUIMVP_UGATE1_R

CPUIMVP_UGATE1

CPUIMVP_LGATE1 CPUIMVP_ISUM1_P

CPUIMVP_TON

CPUIMVP_PHASE1

CPUIMVP_ISUM_N

CPUIMVP_BOOT1

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

GND_CPUIMVP_SGND

VOLTAGE=0V

CPUIMVP_IMAXA

CPUIMVP_SLEW

CPUIMVP_IMAXB

CPU_VIDALERT_L

CPUIMVP_NTC CPUIMVP_NTCG

CPU_VIDSOUT

CPUIMVP_AXG_PGOOD

CPU_VIDSCLK

CPUIMVP_VR_ON

CPUIMVP_PGOOD

CPU_PROCHOT_L

VOLTAGE=0V

CPU_VCCSENSE_R

CPUIMVP_ISUMG_P

CPUIMVP_UGATE1G CPUIMVP_PHASE1G

CPUIMVP_ISUMG_N CPUIMVP_FBB

CPUIMVP_ISUM

CPUIMVP_FBA

=PP5V_S0_CPUIMVP

=PPVCCIO_S0_CPUIMVP

CPU_VCCSENSE_P

CPUIMVP_ISNS1_P

CPU_AXG_SENSE_P

CPU_VCCSENSE_N

CPUIMVP_ISUM_R

CPU_AXG_SENSE_N

=PPVIN_S0_CPUIMVP

CPUIMVP_FBA

VOLTAGE=5V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

P5V_S0_CPUIMVP_VDD

CPUIMVP_BOOT1G

CPUIMVP_LGATE1G

VOLTAGE=0V

CPU_AXG_SENSE_R

CPUIMVP_FBA_R

CPUIMVP_FBB_R

CPUIMVP_FBB

74 OF 109

2.5.0

051-8871

56 OF 74

56

7

57

56

IN

VSW

PGND

TGR

TG

BG

VIN

IN

OUT

S

G

D

G

S

NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

AXG PHASE

CPU=Sandy Bridge ULV, AXG=GT2

376S0985

PHASE 1

376S0984

THESE TWO CAPS ARE FOR EMC

376S0906

152S1323

THESE TWO CAPS ARE FOR EMC

152S1323

21

L7510

0.36UH-20%-30A-1.2MOHM

PIMB104T-SM

CRITICAL

2

1

C7515

0603

25V X5R-CERM

10UF

20%

CRITICAL

2

1

C7517

10%

X5R

1UF

402

16V

2

1

C7518

X7R

10% 50V

0.001UF

402

2

1

C7519

402

0.001UF

50V

10%

X7R

56

2

1

R7511

1/16W

0

5%

MF-LF

402

2

1

C7511

CERM

10V

0.22UF

402

10%

2

1

C7559

10%

X7R

50V

0.001UF

402

2

1

C7558

X7R

0.001UF

50V

10%

402

2

1

C7557

1UF

X5R

16V

402

10%

2

1

R7552

MF-LF

NOSTUFF

603

1/10W

2.2

5%

2

1

C7552

NOSTUFF

50V CERM

10%

402

0.001UF

2

1

C7551

402

10%

CERM

10V

0.22UF

56

2

1

R7514

201

1/20W

1%

10

MF

2

1

R7554

201

1%

10

1/20W MF

8

7

6

1

4

3

9

5

Q7550

CSD58864Q5D

CRITICAL

SON5X6

56

56 73

44 56 73

21

R7555

4.7

5%

MF-LF

402

1/16W

43

21

R7510

MF

0612

1%

0.00075

1W

CRITICAL

43

21

R7550

0.00075

0612

MF

1W

1%

CRITICAL

2

1

R7553

1/20W

MF

201

1%

46.4

2

1

R7513

201

46.4

MF

1%

1/20W

2

1

C7571

0201

2200PF

X7R-CERM

10V

NO STUFF

10%

2

1

C7574

201

1000PF

16V

10%

X7R

NO STUFF

2

1

C7513

CASE-B2

CRITICAL

ELEC

11V

20%

62UF

2

1

C7514

ELEC CASE-B2

CRITICAL

11V

20%

62UF

2

1

C7540

20%

CRITICAL

CASE-B2

11V ELEC

62UF

2

1

C7541

62UF

20% 11V

CASE-B2

ELEC

CRITICAL

2

1

C7560

62UF

20% 11V ELEC

CRITICAL

CASE-B2

2

1

C7553

ELEC

11V

20%

62UF

CASE-B2

CRITICAL

2

1

C7554

CRITICAL

ELEC

11V

20%

62UF

CASE-B2

21

L7550

PIMB104T-SM

0.36UH-20%-30A-1.2MOHM

CRITICAL

3

46

5

2

1

Q7510

CRITICAL

SQ

IRF6811STRPBF

2

1

C7510

CRITICAL

CASE-B2

62UF

20% 11V ELEC

2

1

C7520

CASE-B2

62UF

20% 11V ELEC

CRITICAL

2

1

C7516

0603

X5R-CERM

10UF

20% 25V

CRITICAL

2

1

C7555

0603

10UF

X5R-CERM

25V

20%

CRITICAL

2

1

C7556

0603

X5R-CERM

25V

CRITICAL

10UF

20%

43

5

7621

Q7520

CRITICAL

DIRECTFET-MX

IRF6894MTRPBF

2

1

R7551

402

MF-LF

1/16W

5%

10

SYNC_DATE=12/13/2010

SYNC_MASTER=K21_MLB

CPU IMVP7 & AXG VCore Output

CPUIMVP_BOOT1G

MIN_LINE_WIDTH=0.7 MM MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

CPUIMVP_BOOT1G_RC

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.7 MM

CPUIMVP_UGATE1G

DIDT=TRUE

GATE_NODE=TRUE

=PPVIN_S0_CPUAXG

VOLTAGE=1.25V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

DIDT=TRUE

CPUIMVP_AXG_SNUB

CPUIMVP_UGATE1

MIN_LINE_WIDTH=0.7 MM

MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

GATE_NODE=TRUE

CPUIMVP_ISNS1_N

=PPVCORE_S0_CPU_REG

CPUIMVP_ISNS1_P

CPUIMVP_ISUM1_P

CPUIMVP_ISUM_N

CPUIMVP_LGATE1

GATE_NODE=TRUE

DIDT=TRUE

MIN_LINE_WIDTH=0.7 MM MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

CPUIMVP_BOOT1_RC

CPUIMVP_ISUMG_P

MIN_NECK_WIDTH=0.2 MM

CPUIMVP_LGATE1G

DIDT=TRUE

GATE_NODE=TRUE

MIN_LINE_WIDTH=0.7 MM

CPUIMVP_ISUMG_N

CPUIMVP_ISNS1G_NCPUIMVP_ISNS1G_P

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.25 MM

SWITCH_NODE=TRUE

DIDT=TRUE

CPUIMVP_VSWG

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.5 MM

CPUIMVP_UGATE1G_R

DIDT=TRUE

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

CPUIMVP_PHASE1G

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.7 MM

=PPVCORE_S0_AXG_REG

=PPVIN_S0_CPUIMVP

MIN_NECK_WIDTH=0.2 MM

CPUIMVP_BOOT1

MIN_LINE_WIDTH=0.7 MM

DIDT=TRUE

CPUIMVP_PHASE1

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.7 MM

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

PPVCORE_S0_CPU_PH1

MIN_NECK_WIDTH=0.25 MM

VOLTAGE=1.25V

MIN_LINE_WIDTH=0.5 MM

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.25 MM

PPVCORE_S0_AXG_R

75 OF 109

2.5.0

051-8871

57 OF 74

7

44 73

7

44 73 44 73

7

56

OUT

IN

BOOT

UGATE

LGATE

PHASE

RTN

FSEL

PGOOD

OCSET

VO

SREF

VCC

PVCC

GND

PGND

EN

FB

VSW

PGND

TGR

TG

BG

VIN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

f = 300 kHz

Vout = 1.05V

21A Max Output

CPU VCCIO (1.05V S0) Regulator

Vout = 0.5V * (1 + Ra / Rb)

OCP = R7641 x 8.5uA / R7640

(CPUVCCIOS0_OCSET)

(CPUVCCIOS0_VO)

OCP = 25.6A

<Ra>

<Rb>

2

1

R7644

1/20W MF

1%

3.01K

201

61

2

1

C7602

10%

603

X5R

16V

2.2UF

2

1

R7603

1/20W MF

5%

0

201

21

XW7600

PLACE_NEAR=U7600.1:1mm

SM

8

13

11

4

2

14

10

9

16

7

15

1

5

6

3

12

U7600

CRITICAL

UTQFN

ISL95870

2

1

C7601

CRITICAL

10UF

603

10V X5R

20%

2

1

C7630

402

16V

10%

1UF

X5R

2

1

R7642

3.01K

1% 1/20W MF 201

2

1

R7641

1%

3.01K

MF

1/20W

201

21

C7640

5%

402

NP0-C0G

25V

1000PF

2

1

C7623

1000PF

5%

NP0-C0G

402

25V

PLACE_NEAR=L7630.2:1.5mm

2

1

C7622

25V

1000PF

5%

402

PLACE_NEAR=Q7630.1:1.5mm

NP0-C0G

4 3

2 1

R7640

CRITICAL

1W

1%

0.001

MF

0612

2

1

C7604

47PF

5%

25V

NP0-C0G

201

2

1

R7630

0

5%

MF-LF

603

1/10W

21

R7631

1/16W

MF-LF

402

5%

0

8

7

6

1

4

3

9

5

Q7630

CSD58864Q5D

SON5X6

2

1

C7648

270UF

20% 2V TANT

CRITICAL

CASE-B2-SM

2

1

C7605

47PF

5% 25V NP0-C0G 201

2

1

C7649

CRITICAL

CASE-B2-SM

TANT

2V

20%

270UF

2

1

C7619

20% 11V

CASE-B2

ELEC

CRITICAL

62UF

2

1

C7621

11V

20%

62UF

CASE-B2

CRITICAL

ELEC

2

1

C7620

11V

20%

CASE-B2

ELEC

62UF

CRITICAL

2

1

R7601

201

2.2

5%

1/20W

MF

21

L7630

CRITICAL

PIMB104T-SM

0.68UH-22A-2.7MOHM

2

1

C7603

402

0.047UF

16V

10%

X7R

2

1

R7645

2.74K

MF

1/20W

201

1%

2

1

R7605

201

1/20W

MF

2.74K

1%

2

1

R7604

201

1/20W

MF

3.01K

1%

SYNC_MASTER=K21_MLB

SYNC_DATE=12/13/2010

CPU VCCIO (1.05V) Power Supply

CPUVCCIOS0_CS_N

CPUVCCIOS0_CS_P

=PPCPUVCCIO_S0_REG

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 mm

PPCPUVCCIO_S0_REG_R

MIN_NECK_WIDTH=0.2 mm DIDT=TRUE

CPUVCCIOS0_BOOT_RC

MIN_LINE_WIDTH=0.3 mm

PPCPUVCCIO_S0_REG

=PPVIN_S0_CPUVCCIOS0

DIDT=TRUE

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

CPUVCCIOS0_LL

=PP5V_S0_CPUVCCIOS0

CPUVCCIOS0_VO

CPUVCCIOS0_OCSET

CPUVCCIOS0_RTN

CPUVCCIOS0_FB

CPUVCCIOS0_SREF

CPUVCCIOS0_AGND

VOLTAGE=0V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

CPUVCCIOS0_PGOOD

CPU_VCCIOSENSE_P

CPU_VCCIOSENSE_N

CPUVCCIOS0_FSEL

=CPUVCCIOS0_EN

CPUVCCIOS0_R

CPUVCCIOS0_DRVH

DIDT=TRUE

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm DIDT=TRUE

MIN_LINE_WIDTH=0.3 mm

CPUVCCIOS0_VBST

PP5V_S0_CPUVCCIOS0_VCC

VOLTAGE=5V

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm GATE_NODE=TRUE DIDT=TRUE

CPUVCCIOS0_DRVL

76 OF 109

2.5.0

051-8871

58 OF 74

44 73

7

12 66

IN

BIAS

NC

OUT

THRM

EN

PADGND

NC

IN

BIAS

NC

OUT

THRM

EN

PADGND

NC NC NC

LX

VDD

VIN

THRM_PAD

PGND

SGND

EN

PG

SYNCH

LX

VFB

NC

IN

OUT

NC

IN

BIAS

NC

OUT

THRM

EN

PADGND

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Vout = 1.5V

Max Current = 1.8A

Vout = 1.794V

Vout = 0.8V * (1 + Ra / Rb)

<Rb>

1.05V S0 LDO

dividers (200/100) to 3.3V S5, which burns 100mW in all S-states.

1.8V S0 Regulator

152S1302

<Ra>

Vout = 1.05V

Max Current = 0.35A

Max Current = 0.02A

1.5V S0 LDO

Freq = 1 MHz

Vout = 1.05V

Max Current = 0.020A

70mA is required to support pull-ups. Alternative is strong voltage

Pull-ups (3) must be 51 ohms to support XDP (not required in production).

1.05V SUS LDO

Cougar Point requires JTAG pull-ups to be powered at 1.05V when SUS suspend well is active.

2

1

C7740

XDP_PCH

10%

6.3V CERM

402

1UF

7

1

6

5

3

4

U7740

XDP_PCH

TPS720105

CRITICAL

SON

2

1

C7741

10%

6.3V

2.2UF

402

X5R

XDP_PCH

2

1

C7781

X5R 402

6.3V

10%

2.2UF

7

1

6

5

3

4

U7780

CRITICAL

TPS720105

SON

2

1

C7780

6.3V CERM

402

1UF

10%

PLACE_NEAR=U7780.6:1mm

2

1

C7782

1UF

402

CERM

6.3V

10%

PLACE_NEAR=U7780.4:1mm

2

1

C7721

603

X5R-CERM-1

6.3V

20%

CRITICAL

22UF

2

1

C7722

603

X5R-CERM-1

CRITICAL

20%

6.3V

22UF

2

1

C7723

201

NP0-C0G

25V

47PF

5%

2

1

R7720

1%

113K

MF

1/20W

201

21

L7720

PIMB042T-SM

1.0UH-20%-4.5A-24MOHM

CRITICAL

2

1

C7720

603

X5R-CERM-1

20%

22UF

CRITICAL

6.3V

2

1

8

3

17

4

10912

11

7

13

16

6

15

14

5

U7720

CRITICAL

ISL8014A

QFN

2

1

C7724

16V X7R

1000PF

10%

201

61

2

1

R7721

1%

90.9K

MF

1/20W

201

2

1

C7772

402

X5R

6.3V

10%

2.2UF

7

1

6

5

3

4

U7770

CRITICAL

TPS72015

SON

2

1

C7771

PLACE_NEAR=U7770.6:1mm

402

6.3V CERM

1UF

10%

2

1

C7770

PLACE_NEAR=U7770.4:1mm

402

1UF

CERM

6.3V

10%

7

61

Misc Power Supplies

SYNC_DATE=12/13/2010

SYNC_MASTER=K21_MLB

=PP3V3_S0_P1V8S0

P1V8S0_PGOOD

=PP3V3_SUS_P1V05SUSLDO

=PP1V8_S0_REG

=P1V8S0_EN

SWITCH_NODE=TRUE DIDT=TRUE

P1V8S0_SW

=1V05_S0_LDO_EN

=PP3V3_S0_P1V05S0LDO

=PP1V8_S0_P1V05S0LDO

=PP1V05_S0_LDO

=PP3V3_S0_P1V5S0

=PP1V8_S0_P1V5S0

=P1V5S0_EN

=PP1V5_S0_REG

P1V8S0_FB

=PP1V05_SUS_LDO

77 OF 109

2.5.0

051-8871

59 OF 74

2

7

61

7

IN

D

SG

D

SG

IN

S

G

D

THRM

GND

G

PG

SHDN*

D

VCC

S

ON

PAD

OUT

IN

D

SG

D

SG

D

SG

D

S

G

D

S

G

D

S

G

D

S

G

S

D

G

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

3.3V_SUS FET

3.2 A (EDP)

3.3V S3 FET

PQFN2X2

9.4 mOhm @4.5V

N-TYPE

1.5V S3/S0 FET

MOSFET

LOADING

RDS(ON)

CHANNEL

5 A (EDP)

3.3V S3 FET

P-TYPE 8V/5V

5.0V S0 FET

5V_SUS FET

3.3V SUS FET

5V SUS FET

MOSFET

3.3V S0 FET

18 MOHM @4.5V

P-TYPE

TPCP8102MOSFET

5.0V S0 FET

LOADING

CHANNEL

LOADING

RDS(ON)

1.678 A (EDP)

CHANNEL

MOSFET

P-TYPE 8V/5V

RDS(ON)

3.3V S0 FET

1.608 A (EDP)

RDS(ON)

MOSFET SiA427

SiA427

31 mOhm @1.8V

P-TYPE 8V/5V

100? mA (EDP)

RDS(ON)

CHANNEL

LOADING

RDS(ON)

CHANNEL

MOSFET

SiA427

26 mOhm @1.8V

SiA427

26 mOhm @1.8V

LOADING

100? mA (EDP)

P-TYPE 12V/8V 29 mOhm @4.5V

CHANNEL

APN 376S0981

26

21

C7810

0.01UF

10% 10V X5R 201

2

1

C7811

16V X5R

10%

402

0.033UF

21

R7810

201

1/20W

MF

47K

5%

21

C7830

0.01UF

X5R

10V

10%

201

2

1

C7831

402

16V

0.033UF

10%

X5R

61

1

2

6

Q7812

SOT563

SSM6N37FEAPE

4

5

3

Q7812

SOT563

SSM6N37FEAPE

61

21

R7860

201

5%

1/20W

MF

10K

2

1

C7861

402

16V

0.033UF

X5R

10%

21

C7860

0.01UF

10%

402

CERM

16V

321

4

8765

Q7860

CRITICAL

TPCP8102

23V1K-SM

1

9

3

6

8

2

4

7

5

U7801

TDFN

CRITICAL

SLG5AP020

2

1

C7801

20%

0.1UF

10V

CERM

402

21

R7801

1/16W

402

0

5%

MF-LF

2

1

C7802

4.7UF

10%

X5R-CERM

6.3V

603

NO STUFF

8

60 61

1

2

6

Q7822

SOT563

SSM6N37FEAPE

2

1

C7841

402

10% 16V X5R

0.033UF

2

1

C7821

10% 16V

402

X5R

0.033UF

21

C7840

0.01UF

10% 16V

CERM

402

21

C7820

10% 10V X5R

0.01UF

201

4

5

3

Q7822

SOT563

SSM6N37FEAPE

4

5

3

Q7802

SOT563

SSM6N37FEAPE

2

1

R7812

201

1/20W MF

5%

100K

21

R7820

201

5%

1/20W

MF

12K

21

R7840

3.3K

MF

1/20W

5%

201

2

1

R7862

201

1/20W MF

5%

220K

74

3

1

Q7830

SC70-6L

SIA427DJ

CRITICAL

74

3

1

Q7820

SIA427DJ

SC70-6L

CRITICAL

74

3

1

Q7810

SIA427DJ

SC70-6L

CRITICAL

21

R7830

201

91K

1/20W

MF

5%

2

1

R7832

10K

MF

1/20W

5%

201

2

1

R7842

220K

MF

1/20W

5%

201

2

1

R7822

100K

5% 1/20W MF 201

74

3

1

Q7840

CRITICAL

SIA413DJ

SC70-6L

74

3

86521

Q7801

CRITICAL

IRLHS6242TRPBF

PQFN2X2

21

R7850

CRITICAL

0

5%

1/4W

1206

MF-LF

SYNC_DATE=12/13/2010

SYNC_MASTER=K21_MLB

Power FETs

P3V3S0_SS

=PP3V3_SUS_FET

=PP3V3_S5_P3V3SUSFET

P3V3S3_SS

=PP3V3_S3_P3V3S3FET

=PP3V3_S3_FET

P1V5S3RS0_RAMP_DONE

P1V5S0FET_GATE_R

P3V3S3_EN_L

P1V5S0FET_GATE

=PP5V_S5_P1V5DDRFET

P1V5CPU_EN

P5V0S0_EN_L

P5VSUS_EN_L

P3V3SUS_EN_L

=PP3V3_S0_P3V3S0FET

=P5V_3V3_SUS_EN

=P3V3S0_EN

=P3V3S3_EN

=P5VS0_EN

=P5V_3V3_SUS_EN

=PP3V3_S0_FET

P5V0S0_SS

P3V3S0_EN_L

=PP5V_S0_FET

P3V3SUS_SS

=PP5V_SUS_FET

=PP5V_S3_P5VS0FET

=PP5V_S5_P5VSUSFET

P5VSUS_SS

=PP1V5_S3_P1V5S3RS0_FET

=PP1V5_S3RS0_FET

PP1V5_S3RS0_FET_R

78 OF 109

2.5.0

051-8871

60 OF 74

7

G

D

S

IN

G

D

S

OUT

IN

OUT

D

GS

IN

OUT

IN

NC

Q3

Q2

Q4

Q1

IN

SENSE

CT

VDD

GND

RESET*

MR*

IN

G

D

S

OUT

VDD

MR*

RST*V4MON

V3MON

V2MON

GND

THRM_PAD

OUT

IN

VDD

OUT_A*

OUT_A

THRM

GND

IN_A

DLY_1C

IN_B

OUT_B

DLY

(OD,IPU)

(IPD)

1.3V

PAD

2:1

-

+

OUT

IN

OUT

NC

VCC

A

Y

GND

B

C

IN

OUT

IN

G

D

S

NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PM_RSMRST_L goes to U1800.C21

3.3V SUS Detect

Delete R when pull-down added to PCH page

3.3V,5V S3 ENABLE

0

(90K IPU)

CHGR VFRQ Generation

threhold is 3.07V

Min delay time

(AC_EN_L)

S0 ENABLE

Delete R when pull-down added to PCH page

PSOC USB Power Enable

(IPU)

S0 Rail PGOOD Circuitry

(ISL Version in development)

P1V5S0_PGOOD from U7710

S0 Rail PGOOD (BJT Version)

Worst-Case Thresholds:

Q2: 0.XXXV

Q4: 0.660V

353S2809

(PM_SLP_S3_R_L)

PM_SLP_S4_L

No stuff C7931, 12ms

U7930 Sense input

DP S4 Power Enable

3.3V w/Divider: 2.345V

V2MON: 2.815V-3.099V V3MON: 0.572V-0.630V V4MON: 0.572V-0.630V

Thresholds:

1

Sleep (S3)

1

0

1

VFRQ Low: Fix Frequency

Q3: 0.640V

SMC_PM_G2_ENABLE

PM_SLP_S5_L PM_SLP_S3_L

0

11

0

1

0

Deep Sleep (S5)

Run (S0)

State

Battery Off (G3Hot)

PP1V5_S3RS0

Deep Sleep (S4)

353S2310

VFRQ High: Variable Frequency

0 0

VDD: 2.734V-3.010V

(PM_SLP_S3_L)

"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))

WLAN Enable Generation

NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.

Unused fet

SMC_BATLOW_L:100K pull up on SMC page

3.3V/5.0V Sus ENABLE

3.3V S4 ENABLE

Delete R when pull-down added to PCH page

DLY > 10 ms

S5_PWRGD (old name RSMRST_PWRGD)-->SMC SMC-->PM_DSW_PWRGD

Threshold: ??

CPUVCORE ENABLE

343S0497

Internal pull-ups 100K +/- 20%

S5 Rail Enables & PGOOD

1

2

6

Q7920

2N7002DW-X-G

SOT-363

17 40 41

17 26 40 61

1

2

6

Q7925

SOT-363

2N7002DW-X-G

36

54

55

60

2

1

C7912

PLACE_NEAR=Q7812.2:6mm

CERM-X5R

10%

402

0.47UF

6.3V

56

21

R7974

PLACE_NEAR=U7400.1:5mm

201

1/20W

0

MF

5%

60

44

58

59

53

2

1

R7911

PLACE_NEAR=U7300.16:6mm

201

MF

1/20W

5%

5.1K

2

1

C7910

PLACE_NEAR=U7300.16:6mm

0.47UF

402

CERM-X5R

6.3V

10%

17 26 40 48

2

1

C7986

PLACE_NEAR=U7720.5:6mm

0.47UF

10%

CERM-X5R 402

6.3V

2

1

R7986

PLACE_NEAR=U7720.5:6mm

201

1/20W

MF

5.1K

5%

2

1

C7981

PLACE_NEAR=U7600.3:6mm

402

CERM-X5R

0.47UF

10%

6.3V

2

1

C7987

0.47UF

PLACE_NEAR=U7100.15:6mm

CERM-X5R

6.3V

10%

402

2

1

R7987

PLACE_NEAR=U7100.15:6mm

201

MF

1/20W

5%

33K

2

1

R7979

201

1/20W

MF

5%

PLACE_NEAR=U1800.D4:5mm

100K

21

R7931

5%

10K

MF

1/20W

201

52

2

1

3

Q7931

SSM3K15FV

SOD-VESM-HF

17 26 40 61

64

21

R7975

PLACE_NEAR=U7400.1:5mm

0

MF

1/20W

5%

201

40

21

R7976

PLACE_NEAR=U7400.1:5mm

NO STUFF

5% MF

1/20W

0

201

2

1

R7929

NO STUFF

5%

0

MF

1/20W

201

2

1

R7967

5%

10K

MF

1/20W

201

23 25 40 51 61

2

1

R7957

201

5%

100

1/20W

MF

21

R7966

5%

MF

1/20W

100

201

21

R7964

5%

MF

1/20W

100

201

21

R7901

100

MF

1/20W

5%

201

59

54

21

R7963

5%

100

MF

1/20W

201

21

R7962

5%

S0PGOOD_ISL

MF

1/20W

330

201

58 61

53

2

1

R7956

201

1/20W

MF

1%

150K

2

1

C7960

201

S0PGOOD_ISL

6.3V X5R

0.1UF

10%

2

1

R7951

201

1/20W MF

15K

1%

2

1

R7952

201

7.15K

1/20W MF

1%

3

2

8

4

6

1

7

5

Q7950

CRITICAL

ASMCC0179

DFN2015H4-8

21

R7954

5%

1K

1/20W

MF

201

21

R7955

201

1/20W

1K

MF

5%

17 40

6

5 1

3

2

4

U7930

CRITICAL

SOT23-6

TPS3808G33DBVRG4

2

1

C7931

NO STUFF

16V X7R

1000PF

10%

201

2

1

R7933

201

1/20W

MF

100K

5%

2

1

C7930

6.3V X5R

0.1UF

10%

PLACE_NEAR=U7930.6:2.3mm

201

21

R7968

5%

MF

1/20W

NO STUFF

100

201

56

4

5

3

Q7920

SOT-363

2N7002DW-X-G

21

R7978

201

1/20W

MF

100

5%

59

2

1

C7988

PLACE_NEAR=U7770.3:6mm

0.47UF

6.3V CERM-X5R

10%

402

17

2

1

R7910

201

MF

1/20W

100K

5%

2

1

R7915

201

1/20W

MF

5%

100K

7

2

6

5

3

9

8

1

4

U7960

ISL88042IRTEZ

S0PGOOD_ISL

CRITICAL

TDFN

2

1

R7973

15K

201

1/20W

MF

S0PGOOD_ISL

1%

2

1

R7971

201

MF

1/20W

10K

S0PGOOD_ISL

1%

2

1

R7961

201

MF

15K

1/20W

S0PGOOD_ISL

1%

2

1

R7970

S0PGOOD_ISL

1/20W

201

10K

MF

1%

2

1

R7972

6.04K

1/20W

201

1%

MF

S0PGOOD_ISL

2

1

R7960

201

S0PGOOD_ISL

1/20W

MF

6.04K

1%

54

2

1

C7942

X5R 402

NO STUFF

10%

0.033UF

16V

21

R7941

100

MF

5%

1/20W

201

40

2

1

C7940

0.1UF

201

10% X5R

6.3V

40

1

9

8

4

3

6

2

5

7

U7941

SLG4AP012

CRITICAL

TDFN

2

1

C7941

220PF

X7R-CERM 201

10% 25V

6

38 39

21

R7913

201

5%

1/20W

MF

0

2

1

C7913

NO STUFF

10V

402

10%

0.068UF

CERM

40 41

59

2

1

R7981

20K

PLACE_NEAR=U7600.3:6mm

201

1/20W MF

5%

21

R7917

0

5%

NO STUFF

MF

1/20W

201

4

5

2

6

3

1

U7940

74AUP1G3208

SOT891

2

1

C7943

6.3V

0.1UF

201

10%

X5R

PLACE_NEAR=U7940.5:2.3mm

17

40 41

2

1

R7918

PLACE_NEAR=U1800.A15:5mm

MF

5%

100K

201

1/20W

60

2

1

R7988

PLACE_NEAR=U7770.3:6mm

201

1/20W MF

39K

5%

2

1

R7912

PLACE_NEAR=Q7812.2:6mm

201

MF

1/20W

5%

9.1K

21

R7965

5%

100

MF

1/20W

201

54

18 36

4

5

3

Q7925

SOT-363

2N7002DW-X-G

21

R7953

5%

1K

1/20W

MF

201

SYNC_MASTER=K21_MLB

SYNC_DATE=12/13/2010

Power Control 1/ENABLE

=PP3V3_S5_PWRCTL

ALL_SYS_PWRGD

MAKE_BASE=TRUE

PM_SLP_S4_L

P3V3S3_EN

MAKE_BASE=TRUE

P5VS3_EN

MAKE_BASE=TRUE

=P5VS3_EN

PM_SUS_EN

MAKE_BASE=TRUE

PM_SLP_S3_R_L

CPUIMVP_VR_ON

AP_PWR_EN

=P5V_3V3_SUS_EN

P1V5S0_EN

MAKE_BASE=TRUE

DDRREG_EN

MAKE_BASE=TRUE

PM_RSMRST_L

ALL_SYS_PWRGD

P1V8S0_PGOOD

CPUVCCIOS0_PGOOD

=PP3V3_S0_VMON

P5V_DIV_VMON

P1V5_DIV_VMON

=PP5V_S0_VMON

=PP1V05_S0_VMON

VMON_3V3_DIV VMON_Q2_BASE

=PP3V3_S5_VMON

S0PGD_C

VMON_Q4_BASE

S0PGD_BJT_GND_R

PM_PECI_PWRGD

PM_SLP_SUS_L

S4_PGOOD_CT

=PP3V3_SUS_PWRCTL

=DPAPWRSW_EN

=P5V3V3_REG_EN

CPUVCCIOS0_PGOOD

=P3V3S3_EN

=USB_PWR_EN

=DDRREG_EN

=1V05_S0_LDO_EN

=P5VS0_EN

=P3V3S0_EN

=P1V8S0_EN

P1V05_DIV_VMON

CHGR_VFRQ

=PVCCSA_EN

=PP1V5_S3RS0_VMON

SMC_ADAPTER_EN

=PBUSVSENS_EN

=CPUVCCIOS0_EN

=P1V5S0_EN

=PP3V42_G3H_PWRCTL

=P3V3S5_EN

=PP3V3_S0_VMON

VMON_Q3_BASE

=PP1V5_S3RS0_VMON

=PP1V05_S0_VMON

ALL_SYS_PWRGD_R

=PP3V3_S0_PWRCTL

P5VS3_PGOOD

P3V3S5_PGOOD

PVCCSA_PGOOD

SMC_BATLOW_L

CPUIMVP_AXG_PGOOD

PM_SLP_S3_L

AC_EN_L

PM_WLAN_EN_L

PVCCSA_EN

MAKE_BASE=TRUE

P1V8S0_EN

CPUVCCIOS0_EN

MAKE_BASE=TRUE

SMC_S4_WAKESRC_EN

MAKE_BASE=TRUE

=PP3V3_SUS_PWRCTL

MAKE_BASE=TRUE

S5_PWRGD

S5PGOOD_DLY

P5V3V3_REG_EN

MAKE_BASE=TRUE

=PP3V3_S5_PWRCTL

PM_SLP_S5_L

PM_SLP_S3_L

ALL_SYS_PWRGD

=PP3V3_S5_PWRCTL

SMC_PM_G2_EN

MAKE_BASE=TRUE

=PP3V42_G3H_PWRCTL

P3V3S5_EN

MAKE_BASE=TRUE

79 OF 109

2.5.0

051-8871

61 OF 74

7

61

23 25 40 51 61

7

61

7

61

7

61

58 61

7

61

7 61

7

61

7

61

7

61

7

61

23 25 40 51 61

7

61

7

61

GND

THRM

ON

VIN_1

VIN_2

VOUT_1

VOUT_2

PAD

NC

OUT

IN

BI

IN

SYM_VER-2

NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(DP_INT_AUX_CH_C_P)

CHECK IF LVDS_IG_PANEL_PWR GLITCHES ON POWER UP

Pull-ups on panel side,

DisplayPort I/F

LCD Connector

Internal DP Connector: 518S0787

(DP_INT_AUX_CH_C_N)

LED Backlight I/F

4.7 kOhm to 3.3V

2

1

C9012

20%

6.3V X5R 603

10UF

2

1

C9011

0.1UF

201

X5R

6.3V

10%

2

1

R9014

201

MF

1/20W

5%

1K

2

1

C9009

10%

6.3V X5R 201

0.1UF

5

4

3

2

7

1

6

U9000

FPF1009

CRITICAL

MFET-2X2-8IN

2

1

C9017

PLACE_NEAR=J9000.3:2mm

1000PF

603

C0G-CERM

50V

5%

2

1

C9015

1000PF

201

X7R

16V

10%

21

C9024

0201

X5R-CERM

16V

10%

0.1UF

21

C9025

0.1UF

0201

X5R-CERM

10% 16V

21

C9020

0.1UF

0201

X5R-CERM

10% 16V

21

C9021

0.1UF

0201

X5R-CERM

16V

10%

21

C9022

0.1UF

0201

X5R-CERM

16V

10%

21

C9023

0.1UF

0201

X5R-CERM

10% 16V

9

8

7

6

5

41

40

4

39

38

37

36

35

34

33

32

31

30

3

29

28

27

26

25

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

J9000

CRITICAL

CABLINE-CA

F-RT-SM

2

1

R9050

100K

5%

1/20W

MF

201

21

R9060

201

MF

1/20W

0

5%

2

1

R9080

201

MF

1/20W

5%

100K

2

1

R9070

5% 1/20W

201

MF

100K

9

6

65

6

65

6

65

6

65

6

65

6

65

9

69

9

69

9

69

9

69

8

9

69

9

69

43

4

32

1

FL9000

CRITICAL

12-OHM-100MA-8.5GHZ

TCM0806-4SM

4

32

1

FL9001

12-OHM-100MA-8.5GHZ

TCM0806-4SM

CRITICAL

21

R9061

1/20W

MF

0

5%

201

21

R9062

1/20W

MF

0

5%

201

2

1

R9018

PLACE_NEAR=J9000.24:1mm

201

1M

MF

1/20W

5%

2

1

R9017

PLACE_NEAR=J9000.25:1mm

201

1M

MF

1/20W

5%

21

L9004

FERR-120-OHM-1.5A

0402-LF

Internal DisplayPort Connector

SYNC_MASTER=K21_MLB

SYNC_DATE=12/13/2010

DP_INT_ML_C_N<1>

DP_INT_ML_C_P<1>

DP_INT_ML_C_P<0>

LCD_IG_PWR_EN

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.30 MM

PP3V3_SW_LCD_UF

MIN_NECK_WIDTH=0.20 MM

DP_INT_ML_C_N<0>

DP_INT_AUX_CH_P

DP_INT_AUX_CH_N

DP_INT_ML_P<0>

DP_INT_HPD_CONN

LED_RETURN_5

DP_INT_ML_N<0>

DP_INT_ML_P<1>

DP_INT_ML_N<1>

LED_RETURN_2

=PP3V3_S5_LCD

LED_RETURN_4 LED_RETURN_3

LED_RETURN_6

PPVOUT_SW_LCDBKLT

LED_RETURN_1

=I2C_TCON_SDA

=I2C_TCON_SCL

I2C_TCON_SDA_R

DP_INT_AUX_CH_C_P

DP_INT_HPD

DP_INT_ML_F_N<1>

DP_INT_ML_F_P<1>

DP_INT_ML_F_N<0>

DP_INT_ML_F_P<0>

DP_INT_AUX_CH_C_N

VOLTAGE=3.3V

PP3V3_SW_LCD

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.30 MM

I2C_TCON_SCL_R

90 OF 109

2.5.0

051-8871

62 OF 74

69

6

7

6

65

6

69

6

69

6

69

6

69

6

69

6

69

6

OUT

BI

OUT

IN

OUT

IN

BI

NC

IN

BI

THMPAD

GND

VDD

OUT_D0P OUT_D0N

OUT_D1P

OUT_D2P

OUT_D1N

OUT_D3P

OUT_D2N

OUT_D3N

AC_AUXP AC_AUXN

OUT_HPD

CEXT

IN_D0P IN_D0N

IN_D1N

IN_D2N

IN_D3P

IN_SDA

IN_AUXP IN_AUXN

IN_HPD

I2C_CTL_EN

I2C_ADDR0 I2C_ADDR1

SCL_CTL SDA_CTL

REXT

AUXDDC_OFF

PD

CA_DET

IN_SCL

IN_D3N

IN_D2P

IN_D1P

OUT_AUXN_SDA

OUT_AUXP_SCL

BI

IN

BI

OUT

IN

OUT

VDD

PIO1_8/CT16B1_CAP0

PIO1_7/TXD

XTALIN

PIO1_4/AD5/WAKEUP

PIO1_6/RXD

SWDIO/PIO1_3/AD4

R/PIO1_2/AD3

R/PIO1_1/AD2

R/PIO1_0/AD1

RESET#/PIO0_0 PIO0_1/CLKOUT

SWCLK/PIO0_10/SCK/CT16B0_MAT2

PIO0_9/MOSI/CT16B0_MAT1

PIO0_8/MISO/CT16B0_MAT0

PIO0_2/SSEL/CT16B0_CAP0

R/PIO0_11/AD0

PIO0_7/CTS#

PIO0_6/SCK

PIO0_4/SCL PIO0_5/SDA

VSS

THRM

PAD

BI

OUT

IN

OUT

IN

OUT

IN

OUT

IN

AUX-

AUX+

D1+ D1-

HPD_SEL

GND

THMPAD

SEL

HPD_B

AUX-B

AUX+B

D1-B

D1+B

D0-B

HPD_A

AUX-A

AUX+A

D1-A

D0-

D0+A D0-A

D1+A

HPD

D0+

D0+B

VDD

AUX_SEL

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

to prevent spikes when U9310 AUXDDC_OFF

footprint-compatible parts with

HI=Port B

Note: Other Parade

used by PS8301

CBTL04DP081 (353S3151) and

similar pinouts. NXP uses pin 10 for ML and HPD, Pericom uses pin 10 for ML and pin 11 for HPD.

PI3vEDP212 (353S3055) are

P/N-swapped after AC

PS8301 I2C Addresses:

(IPU)

(IPD)

(All 4 D’s)

(D9360/D9361)

(D9361.2)

1 0 0x94/0x95

Must be 3.3V DP A port power

(DP_SDRVA_AUXCH_N)

(DP_SDRVA_AUXCH_P)

R9308/R9309 maintain bias on C9308/C9309

D9364/D9365:

D9372/D9373:

LO=Port A

(D9360.2)

T29: TX_1

T29: TX_0

(D9364.2)

I2C Addr:

SWDIO

SWCLK

detection of DP Source.

P2R = Plug to Receptacle R2P = Receptacle to Plug

0x26/0x27 (Wr/Rd)

(IPU)

(OD)

pull-ups on ML<3>. U9390 AUX defaults to DP mode because 100-ohm pull-downs would defeat DP Sink’s

(IPD)

A1 A0 Addr (W/R)

0 1 0xB6/0xB7

(IPD)

(D9365.2)

(T29_A_LSX_R2P)

(D9372/D9373)

(OD)

(D9382/D9383)

(IPD)

(DP_SDRVA_HPD)

R9330 provides pads for programming/debug of MCU, please make accessible.

=T29_WAKE_L:

Desktops use PCIe WAKE# Mobiles use S4 WAKE#

so only 94/B4 are

devices use 96/B6,

1 1 0xB4/0xB5

transitions from high to low.

during training.

DP Path Biasing

Display can detect host T29 support using I2C

Note: U9390 ML/HPD defaults to T29 mode so that DP/T29

and DDC, alias nets together at GPU.

(IPD)

(All 4 D’s)

Port A MCU

If project has space for 10-pin programming header it should be used.

0 0 0x96/0x97

used for this part.

(OD)

If GPU uses common pins for AUX_CH

Must be 3.3V DP A port power

DP A Super-Driver

T29: LSX_A_R2P/P2R (P/N)

T29: Unused

T29: RX_1 Bias Sink

(T29_A_LSX_P2R)

AUXCH Snoop Port,

PS8301 has internal

Parade (pin is 5V-tolerant).

~150K pull-down on PD pin. Okay to drive this pin even when VCC=0V per

(D9382/D9383)

T29 A High-Speed Signals

Biasing

T29 signals are

caps to improve layout.

T29 Path

(C9370/C9371)

(C9372.2)

(C9373.2)

(C9382.2)

high while Vcc = 0V.

DP/T29 A Low-Speed MUX

IC supports input

(C9383.2)

(C9380/C9381)

33 71

64 71

2

1

R9312

5%

1K

MF

1/20W

201

2

1

R9319

201

1% 1/20W MF

4.99K

8

2

1

R9311

201

1/20W

MF

5%

1K

NO STUFF

2

1

R9310

5%

201

1/20W MF

1K

2

1

C9311

0.1UF

16V X5R-CERM 0201

10%

2

1

C9312

0.1UF

16V X5R-CERM 0201

10%

2

1

C9319

PLACE_NEAR=U9310.11:2 mm

2.2UF

20%

6.3V CERM

402-LF

33 71

8

69

8

69

8

69

8

69

8

69

8

69

21

C9300

10% X5R-CERM

16V

0.1UF

0201

8

69

8

69

43

8

69

8

69

2

1

R9399

5%

100K

MF

1/20W

201

2

1

R9398

100K

5%

MF

1/20W

201

8

40

21

41

37

38

12

34

31

23

22

25

24

28

27

30

29

18

17

13

14

3

9

10

7

8

4

5

1

2

16

15

26

35

36

33

6

11

32

39

20

19

U9310

PS8301TQFN40GTR-A2

QFN

CRITICAL

2

1

C9310

20%

CERM

402-LF

6.3V

2.2UF

64 71

63

64 71

41 63

18

17

33

4

21

3

22

5

25

19

14

1

18

17

16

15

6

24

23

20

13

12

11

10

9

8

7

2

U9330

OMIT_TABLE

CRITICAL

LPC1112A

HVQFN25

43

8

63 64

33

43

33

2

1

R9335

5%

1K

1/20W MF 201

2

1

R9336

MF

1/20W

5%

10K

201

2

1

C9330

0.1UF

16V X5R-CERM 0201

10%

33

64

2

1

C9331

0.1UF

16V X5R-CERM 0201

10%

2 1

R9397

1K

MF

1/20W

5%

201

2 1

R9396

5%

1K

MF

1/20W

201

2

1

R9339

201

1/20W MF

1M

5%

2

1

R9338

201

10K

5%

1/20W

MF

64

2

1

R9330

201

1/20W

MF

5%

OMIT

0

2

1

R9393

201

1/20W MF

51

5%

2

1

R9392

1/20W

MF

5%

51

201

35 64

21

R9334

10K

5%

201

1/20W

MF

16 23

2 1

R9318

201

0

5%

1/20W

MF

SDRV_PD

21

R9308

201

5%MF1/20W

1M

21

R9309

201

1/20W

MF

1M

5%

64 71

21

D9364

SIGNAL_MODEL=EMPTY

CRITICAL

GND_VOID=TRUE

TSLP-2-7

BAR90-02LRH

21

D9373

SIGNAL_MODEL=T29PIN

BAR90-02LRH

CRITICAL

GND_VOID=TRUE

TSLP-2-7

21

D9372

CRITICAL

TSLP-2-7

GND_VOID=TRUE

SIGNAL_MODEL=T29PIN

BAR90-02LRH

21

D9365

BAR90-02LRH

CRITICAL

GND_VOID=TRUE

SIGNAL_MODEL=EMPTY

TSLP-2-7

21

D9360

CRITICAL

SIGNAL_MODEL=EMPTY

TSLP-2-7

GND_VOID=TRUE

BAR90-02LRH

21

D9382

SIGNAL_MODEL=T29PIN

GND_VOID=TRUE

BAR90-02LRH

TSLP-2-7

CRITICAL

21

D9383

BAR90-02LRH

CRITICAL

TSLP-2-7

GND_VOID=TRUE

SIGNAL_MODEL=T29PIN

21

D9361

GND_VOID=TRUE

TSLP-2-7

CRITICAL

SIGNAL_MODEL=EMPTY

BAR90-02LRH

21

C9370

201

4V

CERM-X5R-1

20%

GND_VOID=TRUE

0.47UF

21

R9372

1/20W

SIGNAL_MODEL=EMPTY

MF

201

5%

1.5K

GND_VOID=TRUE

21

R9373

1.5K

SIGNAL_MODEL=EMPTY

MF

201

GND_VOID=TRUE

5%

1/20W

21

R9382

SIGNAL_MODEL=EMPTY

201

GND_VOID=TRUE

5%

1/20W

1.5K

MF

21

R9383

SIGNAL_MODEL=EMPTY

1.5K

GND_VOID=TRUE

201

MF

1/20W

5%

21

C9371

GND_VOID=TRUE

0.47UF

CERM-X5R-1

20%

4V

201

21

C9364

0201

0.22UF

X5R

20%

6.3V

21

R9385

GND_VOID=TRUE

1/20W

MF5%201

1.5K

21

R9384

1.5K

GND_VOID=TRUE

MF

201

1/20W

5%

64 71

21

R9375

1/20W

201

5% MF

GND_VOID=TRUE

1.5K

21

R9374

201

1/20W

5% MF

GND_VOID=TRUE

1.5K

21

R9354

201

1/20W

5% MF

30

2

1

C9390

0.1UF

16V

10%

X5R-CERM 0201

2

1

C9391

0.1UF

10% 16V

0201

X5R-CERM

21

R9360

1.5K

1/20W

5% MF

201

21

R9361

MF

201

1/20W

5%

1.5K

21

R9364

1/20W

MF

201

5%

1.5K

21

R9365

1/20W

201

5% MF

1.5K

4

5

3

2

U9359

CRITICAL

74LVC1G04DBDCK

SC70

2

1

C9359

0.1UF

10%

X5R

6.3V

201

21

C9365

20%

0.22UF

6.3V

X5R

0201

21

C9360

6.3V

0.22UF

X5R

20%

0201

21

C9361

0.22UF

20% X5R

0201

6.3V

21

C9380

CERM-X5R-1

0.47UF

201

GND_VOID=TRUE

20%

4V

21

C9381

GND_VOID=TRUE

CERM-X5R-1

201

0.47UF

4V

20%

2

1

R9352

MF

1/20W

5%

201

270

2

1

R9353

1/20W

201

270

MF

5%

21

R9355

201

30

1/20W

MF5%

21

R9350

MF5%201

1/20W

30

21

R9351

201

30

1/20W

MF

5%

8

21

R9362

PLACE_NEAR=C9361.1:2mm

MF

201

1/20W515%

2 1

R9363

PLACE_NEAR=C9361.1:2mm

51

MF 5%

201

1/20W

2 1

R9366

PLACE_NEAR=C9361.1:2mm

51

MF

1/20W

5%

201

2 1

R9367

MF 5%

51

201

1/20W

PLACE_NEAR=C9361.1:2mm

21

C9301

10% 16V

0.1UF

X5R-CERM

0201

21

C9302

0201

10% 16V

0.1UF

X5R-CERM

21

C9303

10% 16V

0.1UF

X5R-CERM

0201

21

C9304

10% 16V

0201

0.1UF

X5R-CERM

21

C9305

X5R-CERM

0201

10% 16V

0.1UF

21

C9306

0.1UF

10% 16V

0201

X5R-CERM

21

C9307

0.1UF

10% 16V X5R-CERM

0201

21

C9308

X5R-CERM

0.1UF

10% 16V

0201

21

C9309

X5R-CERM

0201

0.1UF

16V10%

21

C9363

0201

10% 16V

0.1UF

X5R-CERM

21

C9362

X5R-CERM

10% 16V

0.1UF

0201

21

C9367

16V

0.1UF

0201

10% X5R-CERM

21

C9366

10% 16V X5R-CERM

0201

0.1UF

21

C9369

10% 16V

0.1UF

X5R-CERM

0201

21

C9368

0201

X5R-CERM

0.1UF

16V10%

292016129

3

33

10

11

13

17

8

28

21

23 22

27 26

4

5 25 24

31 30

1

2

15 14

19 18

32

6

7

U9390

PI3VEDP212

TQFN

CRITICAL

21

R9390

1/20W

MF

5%

201

0

21

C9372

GND_VOID=TRUE

0.47UF

201

4V

CERM-X5R-1

20%

21

C9373

201

20%

GND_VOID=TRUE

4V

CERM-X5R-1

0.47UF

21

C9382

GND_VOID=TRUE

201

4V

CERM-X5R-1

20%

0.47UF

21

C9383

GND_VOID=TRUE

201

0.47UF

4V

CERM-X5R-1

20%

DisplayPort/T29 A MUXing

SYNC_DATE=12/13/2010

SYNC_MASTER=K21_MLB

T29_A_LSX_R2P

T29_A_RSVD_N

DP_A_EXT_AUXCH_N

T29DPA_ML_N<3>

DP_SDRVA_ML_C_P<2>

DP_EXTA_ML_N<3>

=PP3V3_S0_DPSDRVA

T29_LSEO<0>

=I2C_T29AMCU_SCL =I2C_T29AMCU_SDA T29DPA_HPD T29_A_BIAS T29_LSOE<0> T29_LSOE<1>

T29_MCU_INT_L

DP_SDRVA_AUXCH_C_N

DP_EXTA_ML_P<0>

DP_A_BIAS_N_0

VOLTAGE=3.3V

DP_A_BIAS_P_0

VOLTAGE=3.3V

DP_A_BIAS_N_2

DP_A_BIAS_P_2

VOLTAGE=3.3V

DP_EXTA_ML_P<3>

T29_A_HV_EN

DP_A_CA_DET

DP_EXTA_ML_P<2>

DP_EXTA_AUXCH_P

DP_EXTA_DDC_DATA

T29_A_UC_ADDR

T29_LSEO<1>

T29DPA_CONFIG2_RC

T29DPA_CONFIG1_RC

DP_EXTA_AUXCH_N

DP_EXTA_HPD

=I2C_DPSDRVA_SCL

DP_EXTA_ML_N<0>

DP_EXTA_ML_N<1>

T29DPA_ML_C_P<0>

DP_A_PWRDWN

=I2C_DPSDRVA_SDA

T29DPA_ML_C_N<0>

DP_A_EXT_HPD

T29_A_UC_ADDR

T29_A_HV_EN_R

DPSDRVA_I2C_CTL_EN

DP_EXTA_ML_N<0>

DP_EXTA_ML_P<1>

DP_EXTA_ML_C_P<1>

DP_EXTA_ML_N<2>

DP_EXTA_ML_C_P<0>

DP_EXTA_ML_P<3>

DP_EXTA_ML_C_N<1>

DP_EXTA_ML_C_P<2>

DP_EXTA_ML_P<2>

DP_EXTA_ML_C_P<3>

DP_EXTA_ML_C_N<3>

DP_SDRVA_ML_C_N<3>

DP_SDRVA_AUXCH_C_P

DP_EXTA_DDC_CLK

DP_EXTA_AUXCH_P

DP_SDRVA_ML_C_P<3>

DPSDRVA_CEXT

DP_A_CA_DET

DP_EXTA_ML_P<0>

DP_EXTA_ML_N<2>

DP_EXTA_ML_P<1>

DP_EXTA_ML_C_N<0>

PP3V3_SW_DPAPWR

DP_EXTA_ML_N<1>

DP_EXTA_AUXCH_C_N

DP_EXTA_AUXCH_C_P

=T29_WAKE_L

DPSDRVA_I2C_ADDR0 DPSDRVA_I2C_ADDR1

DP_EXTA_ML_C_N<2>

T29_A_BIAS

DP_A_EXT_HPD

DP_SDRVA_ML_P<3>

PP3V3_SW_DPAPWR

DP_SDRVA_AUXCH_P

DP_SDRVA_HPD

T29_A_RSVD_P

T29_D2R1_BIASP T29_D2R1_BIASN

DP_A_PWRDWN

T29DPA_ML_N<1>

T29_D2R_C_N<0>

T29DPA_ML_P<3>

T29DPA_ML_P<1>

DP_A_EXT_AUXCH_P

T29_A_LSX_P2R

DP_SDRVA_ML_N<3>

DP_SDRVA_ML_C_N<0>

DP_SDRVA_ML_C_N<1>

DP_SDRVA_ML_N<1>

DP_SDRVA_AUXCH_N

DPSDRVA_REXT

DP_A_PWRDWN_R

DP_A_PWRDWN

DP_AUXCH_ISOL_R

DP_AUXCH_ISOL

DP_SDRVA_ML_P<1>

T29DPA_ML_C_P<2> T29DPA_ML_C_N<2>

T29_D2R_C_P<0>

T29_A_BIAS_R2DP0

DP_SDRVA_ML_R_P<0>

DP_EXTA_AUXCH_N

DP_EXTA_ML_N<3>

=PP3V3_S0_DPSDRVA

DP_SDRVA_ML_C_P<0>

DP_SDRVA_ML_C_N<2>

DP_SDRVA_ML_C_P<1>

DP_SDRVA_ML_R_P<2>

T29_R2D_P<0> T29_R2D_N<0>

T29_R2D_P<1> T29_R2D_N<1>

T29_D2R_C_N<1>

T29_D2R_C_P<1>

T29_A_BIAS_R2DN0

DP_A_BIAS

T29_A_BIAS_R2DN1

T29_R2D_C_P<1>

T29_R2D_C_N<1>

T29_A_BIAS_R2DP1

T29_D2R_P<0>

T29_D2R_N<1> T29_D2R_P<1>

DP_SDRVA_ML_R_N<0>

DP_SDRVA_ML_R_N<2>

=PP3V3_S0_DPSDRVA

DP_SDRVA_ML_N<2>

DP_SDRVA_ML_P<2>

DP_SDRVA_ML_N<0>

DP_SDRVA_ML_P<0>

T29_R2D_C_P<0>

T29_R2D_C_N<0>

T29_D2R_N<0>

93 OF 109

2.5.0

051-8871

63 OF 74

8

68

71

63 69

7

63

71

63 69

8

63 69

63

63 69

63

63 69

63

41 63

63

63 69

71

63 69

71

63 69

63 64

63 69

8

63 64

71

63 64

71

8

68

63

71

63

71

63 69

7

63

71

7

63

71

OUT

IN

BI

IN

OUT

BI

IN

OC*

OUT

EN

GND

IN

D

SG

D

SG

G

D

S

D

GS

OUT

BI

IN

GND

PGND

OUT

FB

IN

SGD

GND

PGND

OUT

FB

IN

OUT

IN

CT

EN*

RTRY*

VIN

THRM

GND

IFLT

ILIM

FLT*

VOUT

PAD

DP_PWR

AUX_CHP

ML_LANE3P

ML_LANE3N

CONFIG1

AUX_CHN

RETURN

GND

ML_LANE0N

ML_LANE0P

CONFIG2

HOT_PLUG_DETECT

GND

ML_LANE1P ML_LANE1N

ML_LANE2P ML_LANE2N

SHIELD PINS

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

DisplayPort/T29 A Connector

ZXRE060A REF range: 0.595-0.605V (0.600V nominal)

IFLT = 200k / RFLT = 2A

DP Dir

Circuit threshold range: 3.363-3.439V (3.395V nominal)

T29: TX_0

T29 Dir

2.5V / 249 ohm = 10mA

(IPU-Weak!)

Port A HV Power Switch

TFLT = CCT * 38900

Bleeder Resistor

ILIM = 201k / RLIM = 957mA

T29 Dir

T29: LSX_R2P/P2R (P/N)

Nominal Min Max IFLT 885mA 876mA 894mA (*)

when Source >3.4V

Circuit threshold range: 2.877-2.941V (2.903V nominal)

3.3V/HV MUXed

(Both C’s)

is LOW.

470k R’s for ESD protection

20V Max

(Both C’s)

<CT>

Low: 0 - 0.8V

on AC-coupled signals.

(Both L’s)

Sink HPD range: High: 2.0 - 5.0V

to 100K (DPv1.1a).

greater than or equal

T29: Unused

SI8409DB:

Rds(on): 65mOhm @ 2.5V Vgs

wake from T29 devices.

Note: Bleeder active when

HIGH and T29_A_HV_EN

Vgs(max): +/-12V

or HV_EN high.

Blocking FET, off

3.3V Always

3.3V/HV Power MUX

DP_PWR must be S4/S5 to support

Port A 3.3V Power Switch

Id(max): 3.7A @ 70C

Vgs(th): -1.4V

Vds(max): -30V

(*) U9410 tolerance unknown

TFLT 18.3ms 13.4ms 26.7ms TSD 470ms 235ms 724ms

ILIM 935mA 925mA 1A (*)

down HPD input with

DP Source must pull

DP Dir

TSD = CCT * 1000000

P = ~27mW

T29: TX_1

DPAPWRSW_HV_DET is

2

1

C9400

0.01UF

X7R

10% 50V

402

63 71

21

R9403

GND_VOID=TRUE

201

12

MF

1/20W

5%

2

1

C9402

X7R 402

50V

10%

0.01UF

21

L9408

0603

FERR-120-OHM-3A

21

R9402

201

5%

1/20W

MF

12

21

R9401

1/20W

12

MF

5%

201

2

1

C9401

10% 50V

0.01UF

402

X7R

2

1

R9494

GND_VOID=TRUE

SIGNAL_MODEL=EMPTY

1K

5%

1/20W

MF

201

2

1

R9495

1/20W MF 201

GND_VOID=TRUE

1K

5%

SIGNAL_MODEL=EMPTY

2

1

C9498

30PF

50V

5%

402

CERM

2

1

C9499

402

30PF

5%

CERM

50V

2

1

R9441

5% 1/20W MF

100K

201

2 1

L9498

650NH-5%-0.430MA-0.052OHM

GND_VOID=TRUE

CRITICAL

0603

SIGNAL_MODEL=EMPTY

2 1

L9499

CRITICAL

GND_VOID=TRUE

650NH-5%-0.430MA-0.052OHM

0603

SIGNAL_MODEL=EMPTY

63 71

2

1

R9425

201

MF

1/20W

5%

4.7K

2

1

C9486

603

20%

6.3V X5R

10UF

1

3

5

2

4

U9480

TPS2051B

CRITICAL

SOT23

2

1

C9485

0.1UF

16V X5R-CERM 0201

10%

2

1

C9481

0.1UF

16V

X5R-CERM

0201

10%

2

1

C9480

CRITICAL

6.3V

603

20%

X5R-CERM-1

22UF

2

1

C9487

6.3V

CASE-B2-SM

20%

CRITICAL

POLY-TANT

100UF

4

1

3

6

5

2

Q9426

SOT363

MMDT3946XG

2

1

R9430

201

MF

1/20W

4.7K

5%

2

1

R9426

201

1K

1/20W MF

5%

2

1

R9432

5%

10K

MF

1/20W

201

2

1

R9429

4.7K

MF

1/20W

5%

201

2

1

R9427

201

1/20W

MF

100K

1%

2

1

R9428

201

MF

1/20W

1%

21.5K

61

4

5

3

Q9430

SSM6N37FEAPE

SOT563

1

2

6

Q9430

SOT563

SSM6N37FEAPE

2

1

R9452

201

1/20W

MF

1M

5%

2

1

R9451

201

1/20W MF

1M

5%

2

1

C9494

201

X7R

16V

330PF

10%

2

1

C9495

330PF

201

X7R

16V

10%

2

1

R9498

SIGNAL_MODEL=EMPTY

GND_VOID=TRUE

1/20W

5%

2.2K

MF

201

2

1

R9499

SIGNAL_MODEL=EMPTY

GND_VOID=TRUE

5%

MF

1/20W

201

2.2K

2

1

R9416

201

1/20W

5%

MF

470K

4

3

5

Q9419

SOT-563

DMB53D0UV

21

R9418

1K

5%

MF

1/20W

201

1

2

6

Q9419

SOT-563

DMB53D0UV

2

1

3

Q9415

SSM3K15FV

SOD-VESM-HF

21

R9419

249

1%

MF

1/20W

201

21

L9400

FERR-120-OHM-3A

0603

63

63 71

35 63 64

1

5

3

2

4

U9426

CRITICAL

SOT353

ZXRE060A

4

1

32

Q9425

SI8409DB

CRITICAL

BGA

2

1

C9429

0.1UF

X5R-CERM 0201

10% 16V

NO STUFF

2

1

C9426

0.1UF

16V

X5R-CERM

0201

10%

1

5

3

2

4

U9435

CRITICAL

SOT353

ZXRE060A

8

63 64

2

1

C9435

0.1UF

16V X5R-CERM 0201

10%

2

1

R9435

1/20W

1%

100K

MF

201

NO STUFF

2

1

R9433

1/20W

5%

220

MF

201

2

1

R9410

MF

100K

201

1/20W

5%

2

1

R9411

1% 1/20W MF

210K

201

2

1

C9410

603-1

X7R

0.1UF

10% 50V

2

1

C9411

0.1UF

603-1

X7R

10% 50V

21

D9499

TSLP-2-7

BAR90-02LRH

SIGNAL_MODEL=T29PIN

GND_VOID=TRUE

CRITICAL

21

D9498

SIGNAL_MODEL=T29PIN

BAR90-02LRH

GND_VOID=TRUE

CRITICAL

TSLP-2-7

2

1

R9470

201

1/20W

470K

5%

MF

GND_VOID=TRUE

63 71

21

C9472

0.47UF

4V

201

20%

GND_VOID=TRUE

CERM-X5R-1

2

1

R9471

470K

5% 1/20W MF 201

GND_VOID=TRUE

2

1

R9472

5%

201

1/20W

470K

GND_VOID=TRUE

MF

2

1

R9473

MF

1/20W

201

GND_VOID=TRUE

5%

470K

21

C9473

CERM-X5R-1

201

20%

4V

GND_VOID=TRUE

0.47UF

21

C9470

CERM-X5R-1

201

20%

0.47UF

4V

GND_VOID=TRUE

21

C9471

CERM-X5R-1

0.47UF

201

20%

GND_VOID=TRUE

4V

21

R9408

MF

201

12

5%

1/20W

2

1

R9490

MF

5% 1/20W

51

201

PLACE_NEAR=C9490.1:2mm

21

C9490

201

0.1UF

X5R

6.3V

10%

8

21

D9410

SM

CRITICAL

STPS2L30AF

21

C9424

0.47UF

402

10%

CERM-X5R

6.3V

2

1

R9424

201

MF

22

5%

1/20W

21

D9425

CRITICAL

POWERDI-123

DFLS1100

2

1

R9436

1%

24.9K

MF

1/20W

201

2

1

R9437

5%

82

MF

1/20W

201

2

1

C9436

402

X5R

10V

10%

1UF

21

C9405

201

X5R

6.3V

10%

0.1UF

GND_VOID=TRUE

2

1

R9412

5%

402

0

1/16W MF-LF

21

C9406

10%

6.3V X5R

0.1UF

201

GND_VOID=TRUE

12

11

10

4

3

2

1

17

6 7

8

14

13

5

1516

9

U9410

SN1010017

QFN

21

R9406

1/20W

MF

5%

12

201

19

10 12

15 17

9 11

3 5

28272625242322

21

2

14 8

13 7

1

20

6

4

16 18

J9400

F-RT-TH

CRITICAL

MDP-K21-K78

DisplayPort/T29 A Connector

SYNC_DATE=12/13/2010

SYNC_MASTER=K21_MLB

VOLTAGE=15V

PP3V3RHV_SW_DPAPWR

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MM

T29DPA_D2R1_AUXCH_P

T29DPA_ML_P<3> T29DPA_ML_N<3>

T29_D2R_C_P<0>

T29DPA_D2R1_AUXCH_N

VOLTAGE=0V

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MM

GND_DPACONN_19

GND_DPACONN_8

MIN_NECK_WIDTH=0.20 MM VOLTAGE=0V

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM

GND_DPACONN_7

VOLTAGE=0V

MIN_LINE_WIDTH=0.38 MM

T29DPA_ML_N<0>

T29DPA_ML_P<0>

T29_D2R_C_N<0>

T29DPA_HPD_R

VOLTAGE=0V

GND_DPACONN_1

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MM

T29DPA_ML_P<1> T29DPA_ML_N<1>

T29DPA_ML_P<2> T29DPA_ML_N<2>

MIN_LINE_WIDTH=0.38 MM

VOLTAGE=15V

MIN_NECK_WIDTH=0.20 MM

PP3V3RHV_SW_DPAPWR_UF

DP_A_EXT_AUXCH_P DP_A_EXT_AUXCH_N

T29_A_HV_EN

GND_DPA7_R

=PPHV_SW_DPAPWRSW

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM

PP3V3_SW_DPAPWR

DPAPWRSW_CT

DPAPWRSW_HVEN_L_R

DPAPWRSW_IFLT

DPAPWRSW_ILIM

TP_DPAPWRSW_FLT_L

VOLTAGE=15V

MIN_LINE_WIDTH=0.4 MM

PPHV_SW_DPAPWR

MIN_NECK_WIDTH=0.2 MM

T29DPA_CONFIG2_RC

DPAPWR_FB_DIV

DPAPWRSW_HV_DET

DPAPWRSW_NPN_E

DPAPWRSW_HV_DET_L

DPAPWR_BLDR_B

DPAPWR_ON_L_C

DPAPWRSW_VREF

DPAPWRSW_HV_DET_R_L

DPAPWRSW_P3V3_ON_L

DPAPWRSW_P3V3_ON

T29_A_HV_EN

T29_A_BIAS

DPAPWRSW_ON_C

T29_A_HV_EN

T29DPA_ML_C_P<0> T29DPA_ML_C_N<0>

MIN_LINE_WIDTH=0.20 MM

DPAPWR_BLDR_E

MIN_NECK_WIDTH=0.20 MM

T29_A_BIAS_R

VOLTAGE=3.3V

T29DPA_ML_C_P<2> T29DPA_ML_C_N<2>

=DPAPWRSW_EN

T29_D2R_C_N<1>

T29_A_BIAS_D2RP1

T29_A_BIAS

T29_A_BIAS_D2RN1

=PP3V3_S4_DPAPWRSW

T29DPA_HPD

T29DPA_CONFIG1_RC

T29_D2R_C_P<1>

DPACONN_20_RC

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=15V

94 OF 109

2.5.0

051-8871

64 OF 74

71

7

63

35 63 64

8

63 64

35 63 64

7

VDDIO

VIN

VLDO

SW_0 SW_1

FB

OUT3

OUT2

OUT1

OUT4 OUT5 OUT6

GND_SW

GND_S

GND_L

GND_SW

VSYNC

ISET

FILTER

FSET

SCLK

PWM

SDA

FAULT

EN

IN

D

SG

D

SG

OUT

IN

BI

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PPBUS_SW_LCDBKLT_PWR

*LCD_BKLT_PWM SHOULD BE AWAY FROM BOOST CIRCUIT

ON THE SENSOR PAGE

I_LED=20.3mA

*PPBUS_SW_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE.

*C9797 AND C9799 SHOULD BE PLACED IN T-BONE FOR ACOUSTICS

RDS(ON)

43 mOhm @4.5V

FDC638APZ

CHANNEL

MOSFET

P-TYPE

0.65 A (EDP)

LOADING

THERE IS A SENSE RESISTOR BETWEEN

AND PPBUS_SW_BKL

10.2 ohm resistors for current

measurement on LED strings.

I_LED=369/Riset (EEPROM should set EN_I_RES=1)

Addr: 0x58(Wr)/0x59(Rd)

PPBUS S0 LCDBkLT FET

Fpwm=9.62kHz

see spec for others

2

1

C9799

PLACE_NEAR=D9701.2:5mm

1210-1

50V X5R

CRITICAL

10%

10UF

2

1

C9797

1210-1

10UF

10% 50V

CRITICAL

X5R

PLACE_NEAR=D9701.2:3mm

21

L9701

CRITICAL

15UH-2.8A

PIMB053T-SM

D2

D1

C1

C4

B2

B1

D4

D3

A4

E1

E2

E3

C5

D5

E5

B3

A2

A1B5E4

B4

C2

A5

C3

A3

U9701

25-BUMP-MICRO

LP8550

25

8

4

5

3

Q9707

SOT563

SSM6N15FEAPE

2

1

R9789

1%

147K

MF

1/20W

201

1

2

6

Q9707

SOT563

SSM6N15FEAPE

21

F9700

603-HF

3AMP-32V-467

BOTTOM

2

1

R9788

1%

301K

MF

1/20W

201

2

1

C9782

10% 16V

0.1UF

402

X5R

4

3

6521

Q9706

CRITICAL

FDC638APZ_SBMS001

SSOT6-HF

21

XW9720

SM

PLACE_NEAR=C9797.1:5mm

2

1

R9714

201

MF

1/20W

1%

18.2K

21

R9731

200K

1/20W

1%

201

MF

2

1

R9715

1% 1/20W

201

100K

MF

21

R9741

201

5%

MF

10K

1/20W

21

R9753

5%

201

1/20W

MF

0

21

R9757

0

MF

1/20W

5%

201

21

R9704

5%

1/20W

MF

201

33

2

1

C9704

33PF

201

5% 25V NP0-C0G

2

1

R9716

1/20W

90.9K

201

MF

1%

2

1

R9755

201

MF

1/20W

5%

10K

2

1

C9711

PLACE_NEAR=U9701.C4:4mm

10%

X5R 201

6.3V

0.1UF

2

1

C9714

PLACE_NEAR=U9701.D1:3mm

201

X5R

0.01UF

10V

10%

2

1

C9712

CRITICAL

10UF

805

X5R

10% 25V

PLACE_NEAR=L9701.1:3mm

2

1

C9713

PLACE_NEAR=L9701.1:3mm

25V

10%

402

0.1UF

X5R

2

1

C9796

10% 50V

402

PLACE_NEAR=U9701.A5:3mm

X7R-CERM

220PF

21

D9701

RB160M-60G

PLACE_NEAR=L9701.2:3mm

SOD-123

CRITICAL

21

R9722

0

1/16W MF-LF

5%

402

BKLT:PROD

PLACE_NEAR=U9701.E1:10mm

BOTTOM

21

R9721

0

1/16W MF-LF

5%

402

BKLT:PROD

PLACE_NEAR=U9701.E2:10mm

BOTTOM

21

R9720

402

5%

MF-LF

1/16W

BKLT:PROD

0

BOTTOM

PLACE_NEAR=U9701.E3:10mm

6

62

6

62

6

62

6

62

6

62

6

62

21

R9718

0

5%

MF-LF

402

1/16W

BKLT:PROD

PLACE_NEAR=U9701.D5:10mm

BOTTOM

21

R9719

BKLT:PROD

1/16W MF-LF

402

5%

0

PLACE_NEAR=U9701.C5:10mm

BOTTOM

21

R9717

0

1/16W

5%

402

MF-LF

BKLT:PROD

PLACE_NEAR=U9701.E5:10mm

BOTTOM

2

1

C9710

603-1

10% 25V X5R

PLACE_NEAR=U9701.D1:5mm

1UF

21

XW9710

SM

PLACEMENT_NOTE=Keep away from noise nodes(E4, A1, A2, B1, B2 pins)

8

43

BKLT:ENG

3

R9717,R9718,R9719

103S0198

RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM

BKLT:ENG

RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM

3

R9720,R9721,R9722

103S0198

SYNC_DATE=12/13/2010

SYNC_MASTER=K21_MLB

LCD Backlight Driver

=PP5V_S0_BKL

=PPBUS_SW_BKL

LCDBKLT_EN_DIV

=PPBUS_S0_LCDBKLT

BKL_PWM

=PP3V3_S0_BKL_VDDIO

BKL_FSET

LCD_BKLT_PWM

=I2C_BKL_1_SDA BKL_SDA

=I2C_BKL_1_SCL

BKL_SCL

BKL_EN

PPBUS_SW_LCDBKLT_PWR

BKL_ISET

LCDBKLT_EN_L

BKLT_PLT_RST_L

LCD_BKLT_EN

LCDBKLT_DISABLE

MIN_LINE_WIDTH=0.5 mm

LED_RETURN_5

MIN_NECK_WIDTH=0.20 mm

LED_RETURN_4

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

LED_RETURN_1

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

LED_RETURN_2

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

LED_RETURN_3

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

LED_RETURN_6

VOLTAGE=12.6V

PPBUS_SW_LCDBKLT_PWR

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm

VOLTAGE=50V

MIN_NECK_WIDTH=0.375 MM

PPVOUT_SW_LCDBKLT

MIN_LINE_WIDTH=0.5 MM

TP_BKL_FAULT

PLACE_SIDE=BOTTOM

PPVOUT_SW_LCDBKLT_FB

VOLTAGE=50V

MIN_NECK_WIDTH=0.1 MM

MIN_LINE_WIDTH=0.1 MM

GND_BKL_SGND

VOLTAGE=0V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

VOLTAGE=12.6V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.4 mm

PPBUS_S0_LCDBKLT_FUSED

DIDT=TRUE

SWITCH_NODE=TRUE

VOLTAGE=50V

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.375 MM

PPBUS_SW_LCDBKLT_PWR_SW

BKL_ISEN6

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

BKL_ISEN5

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

BKL_VSYNC_R

BKL_FLTR

BKL_ISEN1

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

BKL_ISEN2

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

BKL_ISEN3

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

BKL_ISEN4

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

97 OF 109

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051-8871

65 OF 74

7

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II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

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PAGE TITLE

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

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8 7 5 4 2 1

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

NOTE: CPU_XDP_BPM physical constraint is to prevent routing on outer layers.

SOURCE: Huron River SFF DG (DG-438297_v1.0), Section 4.18 and Huron River Platform Power Delivery DG v1.0 Section 2.7

Some signals require 27.4-ohm single-ended impedance.

PCI-Express

Most CPU signals with impedance requirements are 50-ohm single-ended.

SOURCE: Huron River SFF DG (DG-438297_v1.0), Section 4.18 and Huron River Platform Power Delivery DG v1.0 Section 2.7

NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.

CPU Net Properties

(FSB_CPURST_L)

NET_TYPE

PHYSICAL

SPACING

ELECTRICAL_CONSTRAINT_SET

CPU_VCCSA_VID<0>

CPU Signal Constraints

CPU_VCCSA_VID<1>

CPU Constraints

SYNC_DATE=04/06/2011

SYNC_MASTER=CONSTRAINTS

?

TOP,BOTTOM

CPU_AGTL

=2x_DIELECTRIC

*

CPU_XDP_BPM

=CPU_50S =CPU_50S=CPU_50S=CPU_50S =CPU_50S =CPU_50S

CPU_XDP_BPM

TOP,BOTTOM

100 MIL 100 MIL 100 MIL

=STANDARD

100 MIL

=STANDARD

7 MIL7 MIL

=27P4_OHM_SE=27P4_OHM_SE=27P4_OHM_SE

*

CPU_27P4S

=27P4_OHM_SE

CPU_55S

*

=55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE

=STANDARD =STANDARD

=50_OHM_SE

*

CPU_50S

=50_OHM_SE =50_OHM_SE=50_OHM_SE

=STANDARD=STANDARD

=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF

*

PCIE_85D

=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF

*

CLK_PCIE_90D

?

20 MIL

*

CLK_PCIE

?

=3X_DIELECTRIC

*

PCIE

?

=4X_DIELECTRIC

TOP,BOTTOM

PCIE

?

=2:1_SPACING

CPU_ITP

*

?

25 MIL

*

CPU_VCCSENSE

?

20 MIL

*

CPU_COMP

?

=STANDARD

*

CPU_AGTL

?

8 MIL

*

CPU_8MIL

PCIE_85D PCIE

PEG_R2D_N<15..0>

PCIE_85D PCIE

PEG_R2D_C_P<15..0>

PCIE_85D PCIE

PEG_R2D_C_N<15..0>

CPU_50S

CPU_COMPCPU_SVIDSOUT

CPU_VIDSOUT

CPU_50S

CPU_COMPCPU_SVIDSCLK

CPU_VIDSCLK

CPU_50S

CPU_COMP

CPU_SVIDALERT_L

CPU_VIDALERT_L

CPU_27P4S

CPU_VALSENSE

CPU_VCC_VALSENSE_N

CPU_VCCSENSE

CPU_27P4S

CPU_VALSENSE

CPU_VDDQ_SENSE_N

CPU_VCCSENSE

CPU_AXG_SENSE_N

CPU_VCCAXG_SENSE

CPU_27P4S

CPU_VCCSENSE

CPU_27P4S

CPU_VALSENSE

CPU_VDDQ_SENSE_P

CPU_27P4S

CPU_VALSENSE

CPU_VCC_VALSENSE_P

CPU_VCCSENSE

CPU_VALSENSE

CPU_27P4S

CPU_AXG_VALSENSE_P

CPU_VCCSENSE

CPU_AXG_SENSE_P

CPU_VCCAXG_SENSE

CPU_27P4S

CPU_VCCSENSE

CPU_VCCIOSENSE_N

CPU_27P4S

CPU_VCCSENSE CPU_VCCSENSE

CPU_27P4S

CPU_VCCSENSE_N

CPU_VCCSENSE

CPU_VCCAXG_SENSE

CPU_27P4S

CPU_VCCSENSE

CPU_VCCSENSE_P

PCIE_85D PCIE

PEG_D2R_N<15..0>

PCIE_85D PCIE

PEG_D2R_P<15..0>

PCIE_85D PCIE

PEG_R2D_P<15..0>

PCIE_85D PCIE

PEG_D2R_C_P<15..0>

PCIE_85D PCIE

PEG_D2R_C_N<15..0>

CPU_50S

CPU_AGTL

FDI_FSYNC<1..0>

PM_SYNC CPU_50S

CPU_AGTL

PM_SYNC

CPU_50S

CPU_AGTLPM_MEM_PWRGD

PM_MEM_PWRGD

CPU_27P4S

CPU_VALSENSE

CPU_AXG_VALSENSE_N

CPU_VCCSENSE

CPU_27P4S

CPU_VCCSENSE

CPU_VCCIOSENSE_P

CPU_VCCSENSE

PCIE_85D

DMI_S2N

PCIE

DMI_S2N_N<3:0>

PCIE_85D

DMI_S2N

PCIE

DMI_S2N_P<3:0>

XDP_BPM_L

CPU_ITP

CPU_XDP_BPM

XDP_BPM_L<7..0>

XDP_CPU_TDO

CPU_50S CPU_ITPXDP_TDO

PCIE_85D

DMI_N2S

PCIE

DMI_N2S_P<3:0>

PCIE_85D

DMI_N2S

DMI_N2S_N<3:0>

PCIE

FDI_DATA PCIE_85D PCIE

FDI_DATA_P<7:0>

PCIE_85D PCIEFDI_DATA

FDI_DATA_N<7:0>

CPU_AGTL

FDI_LSYNC<1..0>

CPU_50S

CPU_AGTL

FDI_INT

CPU_50S

PCIE

CPU_PECI

CPU_27P4S

CPU_COMP

EDP_COMP

ITPCPU_CLK100M

CLK_PCIE_90D CLK_PCIE

ITPXDP_CLK100M_N

CLK_PCIE_90D

XDP_CPU_CLK100M_P

CLK_PCIE

ITPCPU_CLK100M

CLK_PCIE_90D CLK_PCIE

ITPXDP_CLK100M_P

CLK_PCIECLK_PCIE_90D

XDP_CPU_CLK100M_N

ITPCPU_CLK100M

XDP_TDI CPU_50S CPU_ITP

XDP_CPU_TDI

XDP_CPU_PREQ_L

CPU_50S CPU_ITP

DPLL_REF_CLK120M

CLK_PCIE_90D CLK_PCIE

DPLL_REF_CLKP

DPLL_REF_CLK120M

CLK_PCIECLK_PCIE_90D

DPLL_REF_CLKN

CPU_ITP

XDP_DBRESET_L

CPU_50S

CPU_AGTL

CPU_VCCIO_SEL

CPU_50S

CPU_CATERR_L

CPU_CATERR_L CPU_AGTL

CPU_50S

CPU_CFG<11..0>

CPU_ITP

CPU_SM_RCOMP

CPU_SM_RCOMP<2>

CPU_COMP

CPU_27P4S

CPU_COMP

CPU_SM_RCOMP<0>

CPU_SM_RCOMP

PM_EXT_TS_L<0>

CPU_AGTL

CPU_50S

CPU_PWRGD

CPU_AGTL

CPU_PWRGD

ITPCPU_CLK100M

CLK_PCIECLK_PCIE_90D

ITPCPU_CLK100M_P

ITPCPU_CLK100M

CLK_PCIECLK_PCIE_90D

ITPCPU_CLK100M_N

CLK_PCIECLK_PCIE_90D

DMI_CLK100M

DMI_CLK100M_CPU_N

CPU_50S

XDP_CPU_PRDY_L

CPU_ITP

CPU_PEG_COMP

CPU_COMP

CPU_27P4S

CPU_PROCHOT_L

CPU_AGTL

CPU_PROCHOT_L

CPU_50S

PM_EXT_TS_L<1>

CPU_AGTL

CPU_ITPCPU_50S

XDP_CPURST_L

CPU_50S CPU_ITP

XDP_BPM_R_L

CPU_CFG<15..12>

XDP_TRST_L

CPU_50S CPU_ITP

XDP_CPU_TRST_L

CPU_50S CPU_ITPXDP_TCK

XDP_CPU_TCK

CPU_50SXDP_TMS CPU_ITP

XDP_CPU_TMS

CLK_PCIE_90D

DMI_CLK100M

CLK_PCIE

DMI_CLK100M_CPU_P

PM_THRMTRIP_L

CPU_50S

CPU_8MIL

PM_THRMTRIP_L

CPU_27P4S

CPU_SM_RCOMP<1>

CPU_COMPCPU_SM_RCOMP

100 OF 109

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051-8871

66 OF 74

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12 56

9

12

12 56

12

9

12 56

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12 56

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9

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10 17

10 17 26

9

12 58

9

17

9

17

10 23

9

17

9

17

9

17

9

17

9

17

9

17

10 19 40

9

16 23

23

16 23

23

10 23

8

10

8

10

10 23 25

12

10

9

23

10

10 19 23

10 16

10 23

9

10 41 56

23

9

23

10 23

10 16

10 19

10

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEMTABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

Memory to GND Spacing

Memory Bus Spacing Group Assignments

ELECTRICAL_CONSTRAINT_SET

Need to support MEM_*-style wildcards!

SOURCE: Huron River Platform DG, Rev 1.01 (#436735), Section 2.5

SPACING

Memory Net Properties

PHYSICAL

NET_TYPE

per Huron River SFF DG rev1.0 (#438297).

DQS intra-pair matching should be within 0.127mm, no inter-pair matching requirement.

DQ to DQS matching per byte lane should be within 0.127mm.

DQS to clock matching should be within [CLK-63.5mm] and [CLK+38.1mm].

DDR3:

Maximum length of any signal from die pad to SODIMM pad is 119.83mm, from procesor ball to SODIMM pad is 88.9mm.

DQ/DQS/A/BA/cmd signal spacing is 4x dielectric, CLK is 5x dielectric.

A/BA/CMD signals should be matched within [CLK-12.7mm] to [CLK+12.7mm] of CLK pairs A/BA/CMD signals to each other should match within 5.08mm.

CONTROL signals should be matched within [CLK-2.54mm] to [CLK+0.0mm] of CLK pairs.

Sandybridge SFF 2C when routed on Type-3 (Through hole) should follow rPGA guidelines

Memory Bus Constraints

Memory to Power Spacing

CLK intra-pair matching should be within 0.127mm, inter-pair matching should be within 0.0508mm.

Spacing Rule Sets

*

MEM_DQS

GND

MEM_2GND

*

MEM_CMD

MEM_CTRL

MEM_CMD2CTRL

*

MEM_CMD MEM_CMD

MEM_CMD2CMD

MEM_DATA2DATA

*

MEM_DATA MEM_DATA

*

MEM_DATA

MEM_DQS

MEM_MEM2OTHERMEM

MEM_CLK

* *

MEM_2OTHER

MEM_CTRL

* *

MEM_2OTHER

MEM_CMD

* *

MEM_2OTHER

*

MEM_2PWRMEM_DATA

MEM_PWR

MEM_2PWR

=PWR_P2MM

?*

MEM_2OTHER

?

0.6 MM

*

=GND_P2MM

?

MEM_2GND

*

MEM_CLKMEM_CLK

*

MEM_CLK2CLK

MEM_CLK

*

MEM_DATA

MEM_MEM2OTHERMEM

MEM_CMD

MEM_CTRL

*

MEM_CMD2CTRL

MEM_CTRLMEM_CTRL

MEM_CTRL2CTRL

*

MEM_CLK

MEM_CTRL

*

MEM_MEM2OTHERMEM

MEM_DQS

MEM_2PWR

*

MEM_PWR

*

MEM_DQS MEM_DQS

MEM_DQS2DQS

MEM_DQS

*

MEM_2OTHER

*

MEM_2OTHER

MEM_DATA

* *

*

MEM_2PWRMEM_CTRL

MEM_PWR

=85_OHM_DIFF=85_OHM_DIFF

MEM_85D

=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF

Y

TOP,BOTTOM

Y

=50_OHM_SE=50_OHM_SE

ISL3,ISL4,ISL9,ISL10

=STANDARD

MEM_50S

=50_OHM_SE

=STANDARD

=50_OHM_SE =50_OHM_SE

=STANDARD=STANDARD

=50_OHM_SE

Y

MEM_50S

TOP,BOTTOM

MEM_72D

*

=72_OHM_DIFF =72_OHM_DIFF =72_OHM_DIFF =72_OHM_DIFF=72_OHM_DIFF=72_OHM_DIFF

=40_OHM_SE =40_OHM_SE

=STANDARD=STANDARD

=40_OHM_SE=40_OHM_SE

*

MEM_40S

*

=37_OHM_SE

=STANDARD =STANDARD

=37_OHM_SE =37_OHM_SE=37_OHM_SE

MEM_37S

MEM_CMD

*

MEM_CLK

MEM_MEM2OTHERMEM

=STANDARD=STANDARD

*

=55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE

MEM_55S

=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF

Y

MEM_85D

ISL3,ISL4,ISL9,ISL10

*

MEM_DATA

MEM_DQS

MEM_MEM2OTHERMEM

*

MEM_CMDMEM_DQS

MEM_MEM2OTHERMEM

MEM_CTRL

MEM_DQS

*

MEM_MEM2OTHERMEM

*

GND

MEM_2GNDMEM_DATA

*

GND

MEM_2GNDMEM_CTRL

*

MEM_CLK

MEM_2PWR

MEM_PWR

MEM_CLKMEM_DQS

*

MEM_MEM2OTHERMEM

MEM_DQS

MEM_CTRL

*

MEM_MEM2OTHERMEM

MEM_DATAMEM_CTRL

*

MEM_MEM2OTHERMEM

MEM_DATA

*

MEM_CMD

MEM_MEM2OTHERMEM

*

MEM_DATA MEM_CTRL

MEM_MEM2OTHERMEM

*

MEM_CLK

MEM_DATA

MEM_MEM2OTHERMEM

MEM_DATA

*

MEM_CMD

MEM_MEM2OTHERMEM

*

MEM_DQSMEM_CMD

MEM_MEM2OTHERMEM

*

MEM_DQSMEM_CLK

MEM_MEM2OTHERMEM

MEM_CLK MEM_CMD

*

MEM_MEM2OTHERMEM

MEM_CLK

*

MEM_CTRL

MEM_MEM2OTHERMEM

*

GND

MEM_2GND

MEM_CMD

*

MEM_2PWR

MEM_PWRMEM_CMD

MEM_CLK

MEM_2GND

GND

*

Memory Constraints

SYNC_MASTER=CONSTRAINTS

SYNC_DATE=04/06/2011

?

0.6 MM

*

MEM_CLK2CLK

?

MEM_CTRL2CTRL

0.2 MM

*

?

MEM_CMD2CMD

0.2 MM

*

0.2 MM

* ?

MEM_CMD2CTRL

?

MEM_DATA2DATA

0.14 MM

*

?

0.4 MM

*

MEM_MEM2OTHERMEM

*

MEM_DQS2DQS

0.4 MM

?

MEM_B_DQ<39..32>

MEM_50S

MEM_DATA

MEM_B_DQ_BYTE4

MEM_50S

MEM_B_DQ<7..0>

MEM_DATA

MEM_B_DQ_BYTE0

MEM_55S MEM_CMD

MEM_B_CMD

MEM_B_RAS_L

MEM_55S MEM_CMD

MEM_B_CMD

MEM_B_BA<2..0>

MEM_B_CAS_L

MEM_55S

MEM_B_CMD

MEM_CMD

MEM_50S

MEM_DATA

MEM_B_DQ<15..8>

MEM_B_DQ_BYTE1

MEM_B_DQS0

MEM_B_DQS_N<0>

MEM_DQSMEM_85D

MEM_B_DQS_N<1>

MEM_B_DQS1

MEM_85D MEM_DQS

MEM_B_DQS_P<3>

MEM_B_DQS3

MEM_85D MEM_DQS

MEM_B_DQS_N<3>

MEM_85D

MEM_B_DQS3

MEM_DQS

MEM_B_DQS_P<5>

MEM_DQSMEM_85D

MEM_B_DQS5

MEM_B_DQS_P<6>

MEM_85D

MEM_B_DQS6

MEM_DQS

MEM_PWR

PP1V5_S3RS0 PP1V5_S3

MEM_PWR

MEM_72D

MEM_B_CLK_N<5..0>

MEM_B_CLK

MEM_CLK

MEM_55S

MEM_A_RAS_L

MEM_CMD

MEM_A_CMD

MEM_55S

MEM_A_BA<2..0>

MEM_CMD

MEM_A_CMD

MEM_55S

MEM_A_CTRL

MEM_A_ODT<3..0>

MEM_CTRL

MEM_B_DQS_N<2>

MEM_85D

MEM_B_DQS2

MEM_DQS

MEM_B_DQS_P<2>

MEM_B_DQS2

MEM_85D MEM_DQS

MEM_55S

MEM_B_A<15..0>

MEM_CMD

MEM_B_CMD

MEM_85D

MEM_A_DQS_N<6>

MEM_A_DQS6

MEM_DQS

MEM_85D

MEM_A_DQS_N<3>

MEM_A_DQS3

MEM_DQS

MEM_85D

MEM_A_DQS_P<3>

MEM_A_DQS3

MEM_DQS

MEM_85D

MEM_A_DQS_P<1>

MEM_A_DQS1

MEM_DQS

MEM_B_DQS_P<7>

MEM_85D

MEM_B_DQS7

MEM_DQS

MEM_B_DQS_N<6>

MEM_B_DQS6

MEM_85D MEM_DQS

MEM_55S

MEM_CTRL

MEM_B_CKE<3..0>

MEM_B_CTRL

MEM_B_DQ<47..40>

MEM_50S

MEM_DATA

MEM_B_DQ_BYTE5 MEM_B_DQ_BYTE6

MEM_B_DQ<55..48>

MEM_50S

MEM_DATA

MEM_B_DQ_BYTE7

MEM_B_DQ<63..56>

MEM_50S

MEM_DATA

MEM_DQS

MEM_B_DQS0

MEM_B_DQS_P<0>

MEM_85D

MEM_B_DQS_P<4>

MEM_DQSMEM_85D

MEM_B_DQS4

MEM_B_DQS_N<4>

MEM_85D MEM_DQS

MEM_B_DQS4

MEM_B_DQS_N<7>

MEM_B_DQS7

MEM_DQSMEM_85D

PP0V75_S3_MEM_VREFDQ_A

MEM_PWR

PP0V75_S3_MEM_VREFCA_A

MEM_PWR

MEM_B_DQS_P<1>

MEM_B_DQS1

MEM_DQSMEM_85D

MEM_85D

MEM_A_DQS_P<7>

MEM_A_DQS7

MEM_DQS

MEM_50SMEM_A_DQ_BYTE3

MEM_A_DQ<31..24>

MEM_DATA

MEM_55S

MEM_A_CKE<3..0>

MEM_CTRL

MEM_A_CTRL

MEM_55S

MEM_A_CTRL

MEM_A_CS_L<3..0>

MEM_CTRL

MEM_A_CLK_P<5..0>

MEM_72D MEM_CLK

MEM_A_CLK

MEM_72D

MEM_A_CLK_N<5..0>

MEM_CLK

MEM_A_CLK

MEM_50SMEM_A_DQ_BYTE5

MEM_A_DQ<47..40>

MEM_DATA

MEM_50SMEM_A_DQ_BYTE2

MEM_A_DQ<23..16>

MEM_DATA

MEM_50SMEM_A_DQ_BYTE1

MEM_A_DQ<15..8>

MEM_DATA

MEM_50SMEM_A_DQ_BYTE4

MEM_A_DQ<39..32>

MEM_DATA

MEM_50SMEM_A_DQ_BYTE6

MEM_A_DQ<55..48>

MEM_DATA

MEM_50SMEM_A_DQ_BYTE7

MEM_A_DQ<63..56>

MEM_DATA

MEM_85D

MEM_A_DQS_P<0>

MEM_A_DQS0

MEM_DQS

MEM_85D MEM_DQS

MEM_A_DQS_N<0>

MEM_A_DQS0

MEM_85D

MEM_A_DQS_N<1>

MEM_A_DQS1

MEM_DQS

MEM_85D

MEM_A_DQS_P<2>

MEM_A_DQS2

MEM_DQS

MEM_85D

MEM_A_DQS_N<2>

MEM_A_DQS2

MEM_DQS

MEM_85D

MEM_A_DQS_P<4>

MEM_A_DQS4

MEM_DQS

MEM_85D

MEM_A_DQS_N<4>

MEM_A_DQS4

MEM_DQS

MEM_85D

MEM_A_DQS_P<5>

MEM_A_DQS5

MEM_DQS

MEM_85D

MEM_A_DQS_N<5>

MEM_A_DQS5

MEM_DQS

MEM_85D

MEM_A_DQS_P<6>

MEM_A_DQS6

MEM_DQS

MEM_85D

MEM_A_DQS_N<7>

MEM_A_DQS7

MEM_DQS

MEM_72D

MEM_B_CLK_P<5..0>

MEM_CLK

MEM_B_CLK

MEM_55S

MEM_B_CS_L<3..0>

MEM_B_CTRL

MEM_CTRL

MEM_55S

MEM_B_ODT<3..0>

MEM_B_CTRL

MEM_CTRL

MEM_55S

MEM_B_WE_L

MEM_CMD

MEM_B_CMD

MEM_50S

MEM_B_DQ<23..16>

MEM_DATA

MEM_B_DQ_BYTE2

MEM_B_DQ<31..24>

MEM_50S

MEM_DATA

MEM_B_DQ_BYTE3

MEM_55S

MEM_A_A<15..0>

MEM_CMD

MEM_A_CMD

MEM_55S

MEM_A_CMD

MEM_A_CAS_L

MEM_CMD

MEM_55S

MEM_A_CMD

MEM_A_WE_L

MEM_CMD

MEM_A_DQ_BYTE0

MEM_A_DQ<7..0>

MEM_50S

MEM_DATA

MEM_B_DQS_N<5>

MEM_85D MEM_DQS

MEM_B_DQS5

101 OF 109

2.5.0

051-8871

67 OF 74

11 30

11 29

11 29 30 32

11 29

11 30

6 7

8

11 29 30 32

11 27 28 32

8

11 27 28 32

11 29

8

11 29 30 32

11 28

11 27

11 30

8

11 29 30 32

11 30

11 29

11 30

9

27 28 29 30 31

11 29

11 28

11 27

8

11 27 28 32

8

11 27 28 32

8

11 27 28 32

8

11 27 28 32

11 28

11 27

11 28

11 27

11 28

8

11 29 30 32

8

11 29 30 32

8

11 29 30 32

11 29

8

11 27 28 32

11 27

11 30

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4.

SATA Interface Constraints

PCH Net Properties

ELECTRICAL_CONSTRAINT_SET

DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps.

LVDS intra-pair matching should be 5 mils. Pairs should be within 100 mils of clock length.

Digital Video Signal Constraints

SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.8

USB 2.0 Interface Constraints

DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals.

NET_TYPE

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.7.1.

Max length of LVDS/DisplayPort/TMDS traces: 12 inches.

SPACING

PHYSICAL

SYNC_MASTER=CONSTRAINTS

SYNC_DATE=04/06/2011

PCH Constraints 1

?

=3x_DIELECTRIC

TOP,BOTTOM

SATA

=STANDARD=STANDARD=STANDARD

8 MIL8 MIL

=STANDARD

*

PCH_USB_RBIAS

=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF

LVDS_90D

*

?

=4x_DIELECTRIC

TOP,BOTTOM

DISPLAYPORT

=85_OHM_DIFF =85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF

*

DP_85D

=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF

*

SATA_90D

=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF

USB_85D

*

?

=2x_DIELECTRIC

*

USB

?

=4x_DIELECTRIC

*

SATA

?

8 MIL

*

SATA_ICOMP

?

=4x_DIELECTRIC

TOP,BOTTOM

LVDS

?

=3x_DIELECTRIC

*

DISPLAYPORT

=3x_DIELECTRIC

?

LVDS

*

?

=4x_DIELECTRIC

TOP,BOTTOM

USB

SATA_HDD_D2R_RC_P

SATA_90D SATA

SATA_HDD_R2D_RC_P

SATASATA_90D

SATA_HDD_D2R_RC_N

SATASATA_90D

USB

USB_85D

USB_TPAD_N USB_IR_P

USB_IR

USB

USB_85D

USB_SDCARD_P

USB_SDCARD

USB

USB_85D

LVDS_IG_B_CLK_P

LVDSLVDS_90D

SATA_HDD_R2D SATA_90D

SATA_HDD_R2D_P

SATA

SATA_HDD_R2D SATA_90D

SATA_HDD_R2D_N

SATA

SATA_HDD_D2R_P

SATA_HDD_D2R SATASATA_90D

SATA

SATA_HDD_D2R_C_N

SATA_90D

USB_BT_N

USB

USB_85D

USB_BT

CLK_PCIE_90D

PCIE_CLK100M_PCH_N

PCH_DIFFCLK_UNUSED_

CLK_PCIE

PCH_CLK100M_SATA_P

PCH_DIFFCLK_UNUSED_

CLK_PCIECLK_PCIE_90D

PCH_CLK100M_SATA_N

PCH_DIFFCLK_UNUSED_

CLK_PCIECLK_PCIE_90D

PCH_CLK14P3M_REFCLK

CLK_PCIE

CPU_50S

PCH_CLK33M_PCIIN

LPC_CLK33M

CLK_PCIE

CPU_50S

GFX_CLK120M_DPLLSS_P

GFX_CLK_DPLLSS

CLK_PCIECLK_PCIE_90D

GFX_CLK120M_DPLLSS_N

GFX_CLK_DPLLSS

CLK_PCIECLK_PCIE_90D

PCH_DIFFCLK_UNUSED_

PCH_CLK96M_DOT_N

CLK_PCIECLK_PCIE_90D

LVDS_IG_A_CLK_P

LVDS_IG_A_CLK

LVDSLVDS_90D

DP_IG_ML_P<3..0>

DP_ML

DISPLAYPORT

DP_85D

DP_IG_ML_N<3..0>

DP_ML

DISPLAYPORT

DP_85D

DP_IG_AUX_CH_N

DP_EXTA_AUXCH

DISPLAYPORT

DP_85D

LVDS_IG_A_DATA_P<3>

LVDSLVDS_90D

LVDS_IG_A_DATA_P<2..0>

LVDS_IG_A_DATA

LVDSLVDS_90D

DP_IG_AUX_CH_P

DP_EXTA_AUXCH

DISPLAYPORT

DP_85D

CLK_PCIE_90D

PCIE_CLK100M_PCH_P

PCH_DIFFCLK_UNUSED_

CLK_PCIE

PCH_USB_RBIAS

LVDS_IG_A_CLK_N

LVDS_IG_A_CLK

LVDSLVDS_90D

LVDS_IG_A_DATA_N<2..0>

LVDS_IG_A_DATA

LVDSLVDS_90D

LVDS_IG_A_DATA_N<3>

LVDSLVDS_90D

LVDS_IG_B_DATA_P<3..0>

LVDSLVDS_90D

LVDS_IG_B_DATA_N<3..0>

LVDSLVDS_90D

SATA_90DSATA_HDD_D2R

SATA_HDD_D2R_N

SATA

SATA_HDD_D2R_C_P

SATASATA_90D

SATA_ODD_R2D_C_P

SATASATA_90D

SATA_ODD_R2D_C_N

SATASATA_90D

SATA_HDD_R2D_RC_N

SATASATA_90D

SATA_ODD_D2R_P

SATA_ODD_D2R SATASATA_90D

SATA_ODD_R2D_P

SATA_ODD_R2D SATASATA_90D

SATA_90D

SATA_HDD_R2D_C_N

SATA

USB

USB_85D

USB_CAMERA_CONN_N

USB_CAMERA_CONN_P

USB_CAMERA

USB

USB_85D

USB_T29A_N

USB_85D

USB

USB_T29A_P

USB_85D

USB

USB_EXTD

PCH_SATAICOMP

PCH_SATA_ICOMP

SATA_ICOMP

USB_85D

USB_HUB2_UP_P

USB_HUB2_UP

USB

USB_HUB1_UP_N

USB

USB_85D

PCH_DIFFCLK_UNUSED_

PCH_CLK96M_DOT_P

CLK_PCIECLK_PCIE_90D

CLK_PCIE_90D

FSB_CLK133M_PCH_N

CLK_PCIE

CLK_PCIE_90D

FSB_CLK133M_PCH_P

CLK_PCIE

USB_BRCRYPT_N

USB

USB_85D

USB_BRCRYPT_P

USB_BRCRYPT

USB

USB_85D

USB_SDCARD_N

USB

USB_85D

USB_EXTD_N

USB

USB_85D

USB_EXTB_P

USB_EXTB

USB

USB_HUB2_UP_N

USB

USB_85D

USB_HUB1_UP_P

USB_HUB1_UP

USB

USB_85D

SATA_ODD_D2R_N

SATA_ODD_D2R SATASATA_90D

SATA_ODD_R2D_N

SATA_ODD_R2D SATASATA_90D

SATA_HDD_R2D_C_P

SATASATA_90D

LVDS_IG_B_CLK_N

LVDSLVDS_90D

USB_85D

USB_TPAD_P

USB

USB_TPAD

USB_BT_P

USB_BT

USB

USB_85D

USB_CAMERA_N

USB_85D

USB

USB_CAMERA_P

USB_CAMERA

USB

USB_85D

T29_A_RSVD_N

USB_85D

USB

T29_A_RSVD_P

USB

USB_85D

USB_EXTD_P

USB

USB_EXTD

USB_EXTA_P

USB_EXTA

USB

USB_85D

USB_EXTA

USB_85D

USB_EXTA_N

USB

USB_85D

USB_EXTC_N

USB

USB_85D

USB_EXTC_P

USB_EXTC

USB

USB_EXTB_N

USB

USB_85D

USB_IR_N

USB

USB_85D

102 OF 109

2.5.0

051-8871

68 OF 74

48

8

24

8

6

37

6

37

16 37

6

37

6

24 36

16 25

8

16 25

18

8

16 37

6

37

8

16

8

16

8

16

16 37

8

24

8

24

16

18 24

16 25

8

24

6

24 39

18 24

8

16

16 37

8

48

6

24 36

6

18 39

6

18 39

8

63

8

63

6

24 39

24 38

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.15

LPC Bus Constraints

NOTE: 25MHz system clocks very sensitive to noise.

System Clock Signal Constraints

SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.15

SPACING

Clock Net Properties

SIO Signal Constraints

ELECTRICAL_CONSTRAINT_SET

SPACING

PHYSICAL

PCH Net Properties

PHYSICAL

NET_TYPE

PCI-Express Signal Constraints

DisplayPort Signal Constraints

SPI Interface Constraints

HD Audio Interface Constraints

Chipset Net Properties

NET_TYPE

SPACING

PHYSICAL

ELECTRICAL_CONSTRAINT_SET

SMBus Interface Constraints

LPC

*

6 MIL

?

*

CLK_LPC

8 MIL

?

PCH Constraints 2

SYNC_DATE=04/06/2011

SYNC_MASTER=CONSTRAINTS

=55_OHM_SE

=STANDARD

CLK_SLOW_55S

*

=55_OHM_SE =55_OHM_SE =55_OHM_SE

=STANDARD

HDA_50S

*

=50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE

=STANDARD =STANDARD

PCIE

*

=3X_DIELECTRIC

?

SPI_55S

*

=55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE

=STANDARD =STANDARD

*

SMB_50S

=50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE

=STANDARD =STANDARD

*

HDA

=2x_DIELECTRIC

?

CLK_SLOW

*

=2x_DIELECTRIC

?

CLK_SLOW_55S

*

=55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE

=STANDARD =STANDARD

*

PCIE_85D

=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

CLK_25M_55S

*

=55_OHM_SE =55_OHM_SE =55_OHM_SE=55_OHM_SE

=STANDARD =STANDARD

DISPLAYPORT

TOP,BOTTOM

=4x_DIELECTRIC

?

LPC_50S

*

=50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE

=STANDARD =STANDARD

CLK_PCIE_90D

*

=90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF

CLK_PCIE

*

20 MIL

?

CLK_25M

*

=5x_DIELECTRIC

?

CLK_SLOW

* ?

8 MIL

*

=50_OHM_SE

CLK_LPC_50S

=50_OHM_SE =50_OHM_SE =50_OHM_SE

=STANDARD =STANDARD

PCIE

TOP,BOTTOM

=4X_DIELECTRIC

?

*

DISPLAYPORT

=3x_DIELECTRIC

?

*

DP_85D

=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

*

SPI

8 MIL

?

SMB

*

=2x_DIELECTRIC

?

HDA

HDA_50S

HDA_SDOUT

SPI_55S

SPI_CLK

SPI

SPI_CLK_R

SPI_CLK

SPI

SPI_55S

SPI_MOSI_R

SPI_MOSI

SPI

PCIE_PEG_R2D_LANE2

PCIE_85D

PCIE_T29_R2D_N<2>

PCIE

PCIE_PEG_R2D_LANE1

PCIE_85D

PCIE_T29_R2D_N<1>

PCIE

PCIE_85D

PCIE_T29_D2R_C_N<3..0>

PCIE

CLK_PCIE_90D

PCIE_CLK100M_T29_P

PCIE_CLK100M_T29

CLK_PCIE

PCIEPCIE_85D

PCIE_ENET_R2D_N

PCIE_85D PCIE

PCIE_ENET_R2D_P

SPI_MLB_CS_L

SPI_55S

SPI

SPI_CS0_L

SPI

SPI_55S

SPI_CS0_R_L

SPI_CS0

SPI

SPI_55S

PCIE_85D

PCIE_T29_R2D_C_N<3..0>

PCIE

PCIE_85D

PCIE_T29_R2D_C_P<3..0>

PCIE

DISPLAYPORT

DP_INT_AUX_CH_N

DP_85D

DISPLAYPORT

DP_INT_AUX_CH_P

DP_85D

PCIE_85D

PCIE_T29_D2R_N<0>

PCIE_PEG_D2R_LANE0

PCIE

PCIE_85D

PCIE_PEG_R2D_LANE3

PCIE_T29_R2D_P<3>

PCIE

PCIE_85D

PCIE_PEG_R2D_LANE2

PCIE

PCIE_T29_R2D_P<2>

PCIE_85D

PCIE_PEG_R2D_LANE0

PCIE

PCIE_T29_R2D_P<0>

PCIE_85D

PCIE_PEG_R2D_LANE3

PCIE_T29_R2D_N<3>

PCIE

SMB

SMB_50S

SMBUS_PCH_0_DATA

SML_PCH_0_DATA

HDA_RST_L

HDA_50S

HDA HDA

HDA_50S

HDA_SDIN0

HDA_SDIN0 AUD_SDI_R

HDA_50S

HDA

DP_85D

DISPLAYPORT

DP_INT_ML_N<3..0>

DP_EXTA_ML_C_N<3..0>

DP_85D

DISPLAYPORT

DP_EXTA_ML

SPI_MISO

SPI

SPI_55S

SPI

SPI_MOSI

SPI_55S

SPI

SPI_MLB_CLK

HDA_50S

HDA

HDA_SDOUT_R

PCIE_85D PCIE

PCIE_AP_R2D_P

PCIEPCIE_85D

PCIE_ENET_D2R_C_N

PCIEPCIE_85D

PCIE_ENET_D2R_C_P

PCIEPCIE_85D

PCIE_ENET_D2R_N

LPC_FRAME_L

LPC_50S

LPC

LPC_FRAME_L

CLK_LPC_50S

CLK_LPC

LPC_CLK33M

LPC_CLK33M_SMC_R

PCIE_85D PCIE

PCIE_FW_D2R_C_N

PCIEPCIE_85D

PCIE_FW_D2R_C_P

PCIE_FW_D2R

PCIEPCIE_85D

PCIE_FW_D2R_P

PCIE_T29_D2R_C_P<3..0>

PCIEPCIE_85D

PCIE_85D

PCIE_PEG_R2D_LANE1

PCIE

PCIE_T29_R2D_P<1>

PCIE_T29_D2R_N<1>

PCIE_85D PCIE

PCIE_PEG_D2R_LANE1

CLK_PCIECLK_PCIE_90D

PCIE_CLK100M_ENET_N

SMBUS_PCH_1_DATA

SML_PCH_1_DATA

SMB_50S

SMB

HDA_50S

HDA_BIT_CLK

HDA

HDA_BIT_CLK

DP_INT_AUXCH

DISPLAYPORT

DP_85D

DP_INT_AUX_CH_C_N

SMB_50S

SMB

SMBUS_PCH_CLK

CLK_LPC_50S

CLK_LPC

LPC_CLK33M

LPC_CLK33M_LPCPLUS

CLK_LPC_50S

LPC_CLK33M_SMC

CLK_LPC

LPC_CLK33M

SMB_50S

SMB

SMBUS_PCH_DATA

SMBUS_PCH_0_CLK

SML_PCH_0_CLK

SMB_50S

SMB

SML_PCH_1_CLK

SMB_50S

SMB

SMBUS_PCH_1_CLK

DP_EXTA_ML_C_P<3..0>

DP_85D

DISPLAYPORT

DP_EXTA_ML

PM_CLK32K_SUSCLK

CLK_SLOW_55S CLK_SLOW

PM_SUS_CLK

HDA_RST_R_L

HDA_RST_L

HDA_50S

HDA

PCIE_ENET_R2D

PCIEPCIE_85D

PCIE_ENET_R2D_C_P

PCIE_ENET_D2R

PCIE_85D PCIE

PCIE_ENET_D2R_P

PCIEPCIE_85D

PCIE_ENET_R2D_C_N

PCIE_AP_R2D_C_N

PCIEPCIE_85D

PCIE_FW_R2D_P

PCIEPCIE_85D

PCIE_FW_R2D_N

PCIE_FW_R2D

PCIEPCIE_85D

PCIE_FW_R2D_C_P

PCIEPCIE_85D

PCIE_FW_R2D_C_N

PCIE

PCIE_FW_D2R_N

PCIE_85D

PCIE_AP_D2R

PCIE_85D PCIE

CONN_PCIE_AP_D2R_P

CLK_PCIECLK_PCIE_90D

PEG_CLK100M_P

CLK_PCIE

PEG_CLK100M_N

CLK_PCIE_90D

MCP_PE1_REFCLK

CLK_PCIECLK_PCIE_90D

PCIE_CLK100M_AP_P

MCP_PE2_REFCLK

CLK_PCIE_90D CLK_PCIE

PCIE_CLK100M_FW_P

CLK_PCIECLK_PCIE_90D

PCIE_CLK100M_AP_N

CLK_PCIE_90D CLK_PCIE

PCIE_CLK100M_FW_N

CLK_PCIECLK_PCIE_90D

PCIE_CLK100M_EXCARD_P

CPU_27P4S

CPU_COMP

PCH_VSS_NCTF<19>

CPU_27P4S

CPU_COMP

PCH_VSS_NCTF<15>

CPU_27P4S

CPU_COMP

PCH_VSS_NCTF<17>

CPU_27P4S

CPU_COMP

PCH_VSS_NCTF<21>

CPU_27P4S

CPU_COMP

PCH_VSS_NCTF<22>

CPU_27P4S

CPU_COMP

PCH_VSS_NCTF<25>

CPU_27P4S

CPU_COMP

PCH_VSS_NCTF<27>

CPU_27P4S

CPU_COMP

PCH_VSS_NCTF<29>

CPU_COMP

CPU_27P4S

PCH_VSS_NCTF<12>

PCH_VSS_NCTF<11>

CPU_27P4S

CPU_COMP

PCH_VSS_NCTF<2>

CPU_27P4S

CPU_COMP

PCIE_CLK100M_EXCARD_N

CLK_PCIECLK_PCIE_90D

PCH_VSS_NCTF<1>

CPU_27P4S

CPU_COMP

PCH_VSS_NCTF<5>

CPU_27P4S

CPU_COMP

TP_PCH_VSS_NCTF<7>

CPU_27P4S

CPU_COMP

CPU_27P4S

CPU_COMP

PCH_VSS_NCTF<9>

CPU_COMP

PCH_VSS_NCTF<9>

CPU_27P4S

DP_EXTA_ML_P<3..0>

DP_85D

DISPLAYPORT

DP_EXTA_ML_N<3..0>

DP_85D

DISPLAYPORT

DP_EXTA_AUXCH_C_P

DP_EXTA_AUXCH

DP_85D

DISPLAYPORT

DP_INT_ML_C_P<3..0>

DISPLAYPORT

DP_85D

DP_INT_ML

DP_INT_ML_C_N<3..0>

DISPLAYPORT

DP_85D

DP_INT_ML

DP_85D

DP_INT_ML_P<3..0>

DISPLAYPORT

DP_85D

DISPLAYPORT

DP_INT_ML_F_P<3..0>

DP_85D

DISPLAYPORT

DP_INT_ML_F_N<3..0>

DP_INT_AUXCH

DP_85D

DISPLAYPORT

DP_INT_AUX_CH_C_P

CLK_PCIE_90D

PCIE_CLK100M_T29_N

PCIE_CLK100M_T29

CLK_PCIE

SYSCLK_CLK25M_SB

CLK_25M_55S

CLK_25M

SYSCLK_CLK32K_RTC

CLK_SLOW_55S CLK_SLOW

SYSCLK_CLK32K_RTC

SYSCLK_CLK25M_SB_R

CLK_25M_55S

CLK_25M

SYSCLK_CLK25M_ENET

CLK_25M_55S

CLK_25M

SYSCLK_CLK25M_ENET_R

CLK_25M_55S

CLK_25M

SYSCLK_CLK25M_T29_R

CLK_25M_55S

CLK_25M

SYSCLK_CLK25M_T29

CLK_25M_55S

CLK_25M

DP_85D

DP_EXTA_AUXCH_N

DISPLAYPORT

DP_85D

DP_EXTA_AUXCH_P

DISPLAYPORT

DP_EXTA_AUXCH_C_N

DP_85D

DISPLAYPORT

DP_EXTA_AUXCH

SPI_MLB_MOSI

SPI

SPI_55S SPI_55S

SPI

SPI_MLB_MISO

LPC_RESET_L

LPC_50S

LPC

LPC_RESET_L

LPC_50S

LPC

LPC_AD

LPC_AD<3..0>

HDA_SYNC_R

HDA_50S

HDA

HDA_SYNC

HDA_50S

HDA

HDA_SYNC

HDA_50S

HDA_BIT_CLK_R

HDA

PCIE_PEG_R2D_LANE0

PCIE_T29_R2D_N<0>

PCIEPCIE_85D

PCIE_T29_D2R_N<3>

PCIE_PEG_D2R_LANE3

PCIE_85D PCIE

PCIE_T29_D2R_N<2>

PCIE_PEG_D2R_LANE2

PCIE_85D PCIE

CLK_PCIE

PCIE_CLK100M_ENET

CLK_PCIE_90D

PCIE_CLK100M_ENET_P

PCIE_85D PCIE

CONN_PCIE_AP_R2D_N

PCIE_AP_R2D

PCIEPCIE_85D

CONN_PCIE_AP_R2D_P

PCIEPCIE_85D

CONN_PCIE_AP_D2R_N

PCIEPCIE_85D

PCIE_AP_D2R_N

PCIE_AP_D2R

PCIE_AP_D2R_P

PCIEPCIE_85D

PCIE_AP_R2D_N PCIE_AP_R2D_C_P

PCIE_AP_R2D

PCIEPCIE_85D

PCIE_T29_D2R_P<3>

PCIE_85D PCIE

PCIE_PEG_D2R_LANE3

PCIE_T29_D2R_P<2>

PCIEPCIE_85D

PCIE_PEG_D2R_LANE2

PCIE_T29_D2R_P<1>

PCIE_85D PCIE

PCIE_PEG_D2R_LANE1

PCIE_T29_D2R_P<0>

PCIE_85D PCIE

PCIE_PEG_D2R_LANE0

103 OF 109

2.5.0

051-8871

69 OF 74

6

16 39

42

16 42

33

16 33

42 49

42

16 42

8

33

8

33

9

62

9

62

8

33

16 43

6

16 39

6

16 39

9

62

8

63

16 42

42

42 49

16

6

36

6

16 40 42

18 25

33

8

33

16 43

6

16 39

6

62

16 43

6

25 42

25 40

16 43

8

63

16

16 36

8

16

8

16

6

16 36

6

16 36

8

16

6

8

16

6

69

6

69

63

8

63

62

9

62

6

62

6

62

6

62

16 33

16 25

16

33

25 33

63

8

63

42 49

25

6

16 40 42

16

6

16 39

16

33

8

33

8

33

6

16 36

6

16 36

6

36

16 36

8

33

8

33

8

33

8

33

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

SOURCE: Broadcom 5764-DS04-RDS Page 38

FireWire Interface Constraints

CAESAR IV (Ethernet) Constraints

ELECTRICAL_CONSTRAINT_SET

Ethernet Net Properties

SOURCE: Broadcom 5764-DS04-RDS Page 38

CAESAR IV (Ethernet PHY) Constraints

SPACING

PHYSICAL

NET_TYPE

SPACING

NET_TYPE

PHYSICAL

Port 2 Not Used

FireWire Net Properties

I158

I159

I160

I161

I162

I163

I164

I165

I166

I167

I168

I169

I170

I171

?

FW_TP

*

=3:1_SPACING

=110_OHM_DIFF=110_OHM_DIFF=110_OHM_DIFF =110_OHM_DIFF=110_OHM_DIFF=110_OHM_DIFF

FW_110D

*

?

0.6 MM

ENET_MDI

*

=100_OHM_DIFF =100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF

ENET_100D

*

?

8MIL

*

ENET_CR_DATA

?

=3:1_SPACING

ENET_3X

*

=STANDARD =STANDARD

=50_OHM_SE =50_OHM_SE=50_OHM_SE

ENET_50S

=50_OHM_SE

*

SYNC_DATE=04/06/2011

SYNC_MASTER=CONSTRAINTS

Ethernet/FW Constraints

SDCONN_CMD

CR_DATA

ENET_CR_DATAENET_50S

SDCONN_CLK

CR_CLK

ENET_CR_DATAENET_50S

ENET_CR_CLK

CR_CLK

ENET_CR_DATAENET_50S

ENET_MDI_P<3..0>

ENET_MDI ENET_MDI

ENET_100D

ENET_RESET_L

ENET_3X

ENET_50S

ENET_MDI_N<3..0>

ENET_MDI

ENET_100D

FW_P0_TPA_P

FW_P0_TPA

FW_TP

FW_110D

FW_P0_TPA_N

FW_P0_TPA

FW_TP

FW_110D

FW_P0_TPB_P

FW_P0_TPB

FW_TP

FW_110D

FW_P1_TPA_P

FW_P1_TPA

FW_TP

FW_110D

FW_P1_TPA_N

FW_P1_TPA

FW_TP

FW_110D

FW_P1_TPB_P

FW_P1_TPB

FW_TP

FW_110D

FW_P1_TPB_N

FW_P1_TPB

FW_TP

FW_110D

FW_P0_TPB_N

FW_P0_TPB

FW_TP

FW_110D

BCM5764_CLK25M_XTALO

ENET_3X

ENET_50S

BCM5764_CLK25M_XTALI

ENET_3X

ENET_50S

ENET_CR_DATA<7..0>

CR_DATA

ENET_CR_DATAENET_50S

ENET_CR_CMD

CR_DATA

ENET_CR_DATAENET_50S

SDCONN_DATA<7..0>

CR_DATA

ENET_CR_DATAENET_50S

104 OF 109

2.5.0

051-8871

70 OF 74

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

TABLE_SPACING_RULE_ITEMTABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

T29 IC Net Properties

DisplayPort Signal Constraints

T29 I2C Signal Constraints

NOTE: DisplayPort Physical/Spacing Constraints provided by Chipset or GPU page.

ELECTRICAL_CONSTRAINT_SET

T29 Net Properties

DP/T29 Connector Signal Constraints

SPACING

NET_TYPE

PHYSICAL

SOURCE: Bill Cornelius’s T29 Routing Notes

T29 SPI Signal Constraints

T29/DP Net Properties

I262

I263

I264

I265

I266

I267

I268

I269

I270

I271

I272

I273

I274

I275

I276

I277

I282

I283

I284

I285

I286

I287

I288

I289

I290

I291

I292

I293

I294

I295

I296

I297

I298

I299

I300

I301

I302

I303

I304

I305

I306

I307

I308

I309

I310

I311

I312

I313

I314

I315

I316

I317

I318

I319

I320

I321

I322

I323

I324

I325

I326

I327

I328

I329

SYNC_DATE=04/06/2011

T29 Constraints

SYNC_MASTER=CONSTRAINTS

?

=7x_DIELECTRIC

TOP,BOTTOMT29DP

?

=5x_DIELECTRIC

T29DP

*

=80_OHM_DIFF=80_OHM_DIFF=80_OHM_DIFF=80_OHM_DIFF=80_OHM_DIFF=80_OHM_DIFF

*

T29DP_80D

=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF

*

T29DP_100D

?

=2x_DIELECTRICT29_SPI

*

=STANDARD=STANDARD

=55_OHM_SE=55_OHM_SE=55_OHM_SE=55_OHM_SE

*

T29_SPI_55S

?

=2x_DIELECTRICT29_I2C

*

=STANDARD=STANDARD

=55_OHM_SE=55_OHM_SE=55_OHM_SE=55_OHM_SE

T29_I2C_55S

*

DP_T29SNK1_ML_C_N<3..0>

DISPLAYPORT

DP_85D

DP_T29SNK1_ML_C_P<3..0>

DISPLAYPORT

DP_85D

T29_R2D_P<0>

T29DP

T29DP_80D

T29_R2D0

T29_R2D_N<1>

T29_R2D1

T29DP

T29DP_80D

T29_D2R_C_P<0>

T29_D2R0

T29DP

T29DP_80D

T29DP

T29DPA_ML_N<3..0>

T29DP_80D

T29DP

T29DP_80D

T29DPA_ML_P<3..0>

T29DPA_ML_P<3>

T29DPA_ML_ODD

DP_SDRVA_AUXCH_C_N

T29DP_80D

T29DP

DP_T29SNK1_ML_P<3..0>

DP_T29SNK1_ML

DISPLAYPORT

DP_85D

DP_T29SNK1_ML_N<3..0>

DP_T29SNK1_ML

DISPLAYPORT

DP_85D

T29_D2R_P<3..0>

T29DP

T29DP_80D

T29_R2D_P<1>

T29_R2D1

T29DP

T29DP_80D

DP_T29SNK0_ML_C_P<3..0>

DISPLAYPORT

DP_85D

DP_T29SNK0_ML_P<3..0>

DP_T29SNK0_ML

DISPLAYPORT

DP_85D

DP_T29SNK0_AUXCH_C_P

DISPLAYPORT

DP_85D

T29_R2D_C_F_P<1..0>

T29DP

T29DP_80D

T29DP

T29DP_80D

DP_SDRVA_ML_P<0>

DP_SDRVA_ML_EVEN

T29_D2R_N<3..0>

T29DP

T29DP_80D

T29_D2R1

T29DP

T29DP_80D

T29_D2R_C_P<1>

T29_R2D_N<0>

T29_R2D0

T29DP

T29DP_80D

T29_R2D_C_F_N<1..0>

T29DP

T29DP_80D

DP_SDRVA_AUXCH_P

T29DP

T29DP_80D

DP_SDRVA_AUXCH

T29DP

T29DP_80D

DP_SDRVA_ML_EVEN

DP_SDRVA_ML_N<0>

T29DP

T29DP_80D

DP_SDRVA_ML_ODD

DP_SDRVA_ML_P<1>

DP_SDRVA_ML_R_P<3..0>

T29DP

T29DP_80D

T29DP

T29DP_80D

DP_SDRVA_ML_C_P<3..0>

DP_T29SNK1_AUXCH_C_N

DISPLAYPORT

DP_85D

DP_T29SNK1_AUXCH_P

DP_T29SNK1_AUXCH

DISPLAYPORT

DP_85D

DP_T29SNK1_AUXCH_N

DP_T29SNK1_AUXCH

DISPLAYPORT

DP_85D

DP_T29SNK1_AUXCH_C_P

DISPLAYPORT

DP_85D

DP_T29SNK0_AUXCH_P

DP_T29SNK0_AUXCH

DISPLAYPORT

DP_85D

DP_T29SNK0_AUXCH_N

DP_T29SNK0_AUXCH

DISPLAYPORT

DP_85D

DP_T29SNK0_AUXCH_C_N

DISPLAYPORT

DP_85D

DP_T29SNK0_ML_N<3..0>

DP_T29SNK0_ML

DISPLAYPORT

DP_85D

DP_T29SNK0_ML_C_N<3..0>

DISPLAYPORT

DP_85D

T29DP

T29DP_80D

DP_SDRVA_ML_N<3>

DP_SDRVA_ML_ODD

T29DP_80D

T29DP

DP_SDRVA_ML_N<2>

DP_SDRVA_ML_EVEN

T29DP

T29DP_80D

T29DPA_D2R1_AUXCH_P

T29DP

T29DP_80D

DP_SDRVA_ML_R_N<3..0>

T29DP

T29DP_80D

DP_SDRVA_ML_C_N<3..0>

T29_D2R0

T29DP

T29DP_80D

T29_D2R_C_N<0>

T29_D2R1

T29DP

T29DP_80D

T29_D2R_C_N<1>

T29DP_80D

T29DP

T29DPA_D2R1_AUXCH_N

T29DP

T29DP_80D

DP_SDRVA_AUXCH_C_P

DP_SDRVA_ML_P<2>

T29DP

T29DP_80D

DP_SDRVA_ML_EVEN

T29DP

T29DP_80D

DP_SDRVA_ML_ODD

DP_SDRVA_ML_N<1>

DP_SDRVA_AUXCH_N

T29DP

T29DP_80D

DP_SDRVA_AUXCH

DP_SDRVA_ML_P<3>

T29DP

T29DP_80D

DP_SDRVA_ML_ODD

T29DPA_ML_N<3>

T29DPA_ML_ODD

T29DPA_ML_N<1>

T29DPA_ML_ODD

T29DPA_ML_P<1>

T29DPA_ML_ODD

DP_A_EXT_AUXCH

T29DP

T29DP_80D

DP_A_EXT_AUXCH_N

T29DP_80D

T29DP

T29DPA_ML_C_N<3..0>

T29DP_80D

T29DP

T29DPA_ML_C_P<3..0>

DP_A_EXT_AUXCH

T29DP

T29DP_80D

DP_A_EXT_AUXCH_P

T29DP_80D

T29DP

T29_R2D_C_P<3..0>

T29DP_80D

T29DP

T29_R2D_C_N<3..0>

T29_SPI_CS_L

T29_SPI

T29_SPI_55S

T29_SPI_MISO

T29_SPI

T29_SPI_55S

T29_SPI_MOSI

T29_SPI

T29_SPI_55S

T29_SPI_CLK

T29_SPI

T29_SPI_55S

I2C_T29_SDA

T29_I2C

T29_I2C_55S

I2C_T29_SCL

T29_I2C

T29_I2C_55S

105 OF 109

2.5.0

051-8871

71 OF 74

63

63 64

63 64 71

63

33 63

63

8

33

8

33

63

33 63

63 64

63

33

8

33

8

33

63

64

63

63 64

64

63

63 64 71

63 64

33 63

33

33 43

TABLE_PHYSICAL_RULE_ITEM

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

ELECTRICAL_CONSTRAINT_SET

SMBus Charger Net Properties

NET_TYPE

PHYSICAL

SPACING

SMC SMBus Net Properties

SPACING

PHYSICAL

NET_TYPE

0.1 MM0.1 MM

=STANDARD=STANDARD=STANDARD=STANDARD

*

1TO1_DIFFPAIR

SYNC_DATE=04/06/2011

SYNC_MASTER=CONSTRAINTS

SMC Constraints

SMBUS_SMC_B_S0_SDA

SMB

SMB_50S

SMBUS_SMC_0_S0_SCL

SMB

SMB_50S

SMBUS_SMC_0_S0_SDA

SMB

SMB_50S

SMBUS_SMC_BSA_SCL

SMB

SMB_50S

SMBUS_SMC_MGMT_SCL

SMB

SMB_50S

SMBUS_SMC_MGMT_SDA

SMB

SMB_50S

SMBUS_SMC_BSA_SDA

SMB

SMB_50S

CHGR_CSI_N

1TO1_DIFFPAIR

CHGR_CSI_P

CHGR_CSI

1TO1_DIFFPAIR

CHGR_CSO_P

CHGR_CSO

1TO1_DIFFPAIR

CHGR_CSO_N

1TO1_DIFFPAIR

SMBUS_SMC_B_S0_SCL

SMB

SMB_50S

SMBUS_SMC_A_S3_SDA

SMB

SMB_50S

SMBUS_SMC_A_S3_SCL

SMB

SMB_50S

106 OF 109

2.5.0

051-8871

72 OF 74

43

52

43

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

ELECTRICAL_CONSTRAINT_SET

Audio Net Properties

PHYSICAL

NET_TYPE

SPACING

(USB_TPAD)

K21/K78 Specific Net PropertiesK21/K78 Specific Net Properties

ELECTRICAL_CONSTRAINT_SET

(USB_TPAD)

(USB_EXTA)

PHYSICAL

NET_TYPE

SPACING SPACING

NET_TYPE

PHYSICAL

(USB_EXTA)

Allow 0.127 mm necks for >0.127 mm lines for ARD fanout.

SPACING

NET_TYPE

PHYSICAL

(USB_EXTA)

ELECTRICAL_CONSTRAINT_SET

Memory Constraint Relaxations

Misc Net Properties

I249

I250

I251

I252

I253

I254

I255

I256

I281

I282

I283

I284

I285

I286

I287

I288

I291

I292

I293

I294

I295

I296

I297

I298

I299

I300

I301

I302

I303

I304

I305

I306

I307

I308

I309

I310

I311

I312

I313

I314

I315

I316

I317

I318

I319

I320

I322

I324

I325

I326

I327

I328

I329

I330

I331

I332

I333

I334

I335

I336

400 MIL

TOP

0.09 MM

CPU_27P4S

TOP

0.1 MM

USB_85D 500 MIL

*

0.076 MMPCIE_85D

10 mm

400 MIL

CLK_PCIE_90D

TOP

0.09 MM

SYNC_MASTER=CONSTRAINTS

SYNC_DATE=04/06/2011

Project Specific Constraints

6.35 MM

0.1 MMTOP

MEM_85D

PWR_P2MM

*

SB_POWER

SATA

GND_P2MM

*

GND

CLK_PCIE

PWR_P2MM

*

SB_POWERCLK_PCIE

PWR_P2MM

*

SB_POWER

USB

1000

0.20 MM

GND_P2MM

*

?

=STANDARD

*

GND

GND_P2MM

GND

*

ENET_MDI

?

25 MILS

*

ENETCONN

GND_P2MM

GND

*

CPU_VCCSENSE

GND_P2MM

GND

*

CPU_COMP

?

=2:1_SPACING

AUDIO

*

=1:1_DIFFPAIR=1:1_DIFFPAIR

=55_OHM_SE=55_OHM_SE=55_OHM_SE

*

THERM_1TO1_55S

=1:1_DIFFPAIR

=1:1_DIFFPAIR=1:1_DIFFPAIR=1:1_DIFFPAIR

*

DIFFPAIR

=1:1_DIFFPAIR

GND_P2MM

*

GNDUSB

?

=2:1_SPACING

*

THERM

?

=2:1_SPACING

*

SENSE

=1:1_DIFFPAIR =1:1_DIFFPAIR =1:1_DIFFPAIR

=55_OHM_SE =55_OHM_SE=55_OHM_SE

SENSE_1TO1_55S

*

GND_P2MM

*

GND

LVDS

GND_P2MM

*

GND

PCIE

GND_P2MM

*

GND

SATA

*

GND

MEM_CTRL GND_P2MM

*

GND

MEM_DATA GND_P2MM

*

GND

MEM_CMD

GND_P2MM

*

GND

MEM_DQS

GND_P2MM

0.127 MM

6.35 MM

BOTTOM

MEM_72D

MEM_40S

*

400 MIL0.09 MM

400 MIL

*

0.09 MMMEM_37S

*

MEM_85D 0.09 MM 400 MIL

*

MEM_72D 400 MIL0.09 MM

*

GND

MEM_CLK

GND_P2MM

1000

0.20 MM

PWR_P2MM

*

SB_POWER

PP3V3_S5

USB_TPAD_R_P

USB

USB_85D

SPKRAMP_INSUB_N

1TO1_DIFFPAIR

AUDIO

AUD_DIFF

SPKRAMP_INSUB_P

1TO1_DIFFPAIR

AUDIO

AUD_DIFF

SPKRAMP_INR_N

DIFFPAIR

AUDIO

AUD_DIFF

SPKRAMP_INR_P

DIFFPAIR

AUDIO

SPKRAMP_INR

1TO1_DIFFPAIR

AUDIO

AUD_DIFF

SSM2315_SUB_N

AUD_DIFF

1TO1_DIFFPAIR

AUDIO

SSM2315_SUB_P

1TO1_DIFFPAIR

AUDIO

AUD_DIFF

SSM2315_L_N

1TO1_DIFFPAIR

AUDIO

AUD_DIFF

SSM2315_L_P

1TO1_DIFFPAIR

AUDIO

AUD_DIFF

SSM2315_R_P

1TO1_DIFFPAIR

AUDIO

SPKRAMP_INL_P

AUD_DIFF

DIFFPAIR

AUDIO

MAX98300_R_N

DIFFPAIR

AUDIO

SPKRAMP_INR

SPKRAMP_INR_P

DIFFPAIR

AUDIO

SPKRAMP_INR_N

SMB_55S

SMB

I2C_TCON_SCL

SENSE

SENSE_1TO1_55SSENSE_DIFFPAIR

CPUIMVP_ISNS1G_P CPUIMVP_ISNS1G_N

SENSE

SENSE_1TO1_55S

CPUIMVP_ISUM_R_P

SENSE

SENSE_DIFFPAIR SENSE_1TO1_55S

CPUIMVP_ISNS_N

SENSE_1TO1_55S

SENSE

SENSE_1TO1_55S

SENSE

VCCSAS0_CS_N CPUIMVP_ISUMG_P

SENSE_1TO1_55SSENSE_DIFFPAIR

SENSE

LVDS_CONN_A_CLK_F_P

LVDSLVDS_90D

SENSE

SENSE_1TO1_55S

ISNS_ODD_R_P

SENSE

SENSE_DIFFPAIR SENSE_1TO1_55S

ISNS_ODD_R_N

SENSE

SENSE_1TO1_55S

ISNS_1V5_S3_P

SENSE_DIFFPAIR SENSE_1TO1_55S

SENSE

ISNS_P1V8GPU_R_N

SENSE_1TO1_55S

SENSE

ISNS_P1V8GPU_R_P

SENSE

CPUIMVP_ISUMG_R_N

SENSE_1TO1_55S

SENSE

CPUIMVP_ISUMG_R_P

SENSE_1TO1_55SSENSE_DIFFPAIR

CPUIMVP_ISNS_P

SENSE_1TO1_55S

SENSE

SENSE_DIFFPAIR

CPUIMVP_ISUMG_N

SENSE_1TO1_55S

SENSE

ISNS_CPU_N

SENSE_1TO1_55SSENSE_DIFFPAIR

SENSE

ISNS_CPU_P

SENSE_1TO1_55S

SENSE

VCCSAS0_CS_P

SENSE_1TO1_55SSENSE_DIFFPAIR

SENSE

CPUIMVP_ISNS2_N

SENSE_1TO1_55S

SENSE

ISNS_HDD_P

SENSE_1TO1_55S

SENSE

SENSE_DIFFPAIR SENSE_1TO1_55S

ISNS_1V5_S3_N

SENSE

ISNS_ODD_P

SENSE_1TO1_55S

CPUIMVP_ISUM_R_N

SENSE

CPUIMVP_ISNS1_N

SENSE_1TO1_55S

CPUVCCIOS0_CS_P

SENSE_1TO1_55S

SENSE

SENSE_DIFFPAIR

ISNS_HS_COMPUTING_N

SENSE_1TO1_55S

SATA_90D SATA

SATA_HDD_R2D_RDRVR_IN_N

SATA_90D SATA

SATA_HDD_R2D_RDRVR_IN_P

CPU_THERMD_N

THERM_1TO1_55S

THERM

CPU_THERMD

THERM

THERM_1TO1_55S

CPU_THERMD_P

SENSE_DIFFPAIR

THERM

THERM_1TO1_55S

T29_MLBBOT_THMSNS_P

THERM

THERM_1TO1_55S

T29_MLBBOT_THMSNS_N

SENSE_1TO1_55SSENSE_DIFFPAIR

ISNS_HS_OTHER_N

SENSE

CPUIMVP_ISNS2_P

SENSE_DIFFPAIR SENSE_1TO1_55S

SENSE

SENSE_DIFFPAIR

ISNS_LCDBKLT_N

SENSE_1TO1_55S

SENSE

SENSE_DIFFPAIR

ISNS_HDD_N

SENSE_1TO1_55S

SENSE

ISNS_HDD_R_P

SENSE_1TO1_55S

SATA_90D SATA

SATA_HDD_R2D_RDRVR_OUT_N

SENSE

CPUIMVP_ISNS1_P

SENSE_DIFFPAIR SENSE_1TO1_55S

SENSE

SENSE_DIFFPAIR

ISNS_ODD_N

SENSE_1TO1_55S

SENSE_DIFFPAIR SENSE_1TO1_55S

SENSE

ISNS_AIRPORT_N

SENSE_1TO1_55S

SENSE

ISNS_AIRPORT_P

LVDS_CONN_A_CLK_F_N

LVDSLVDS_90D

ENET_100D

ENETCONN

ENETCONN_P<3..0>

SATA_90D SATA

SATA_HDD_D2R_RDRVR_OUT_P

CPUVCCIOS0_CS_N

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_55S

ISNS_HS_OTHER_P

SENSE

SATA_90D SATA

SATA_ODD_D2R_UF_P

ENET_100D

ENETCONN

ENETCONN_N<3..0>

SMB_55S

SMB

I2C_TCON_SDA_CONN

SMB_55S

SMB

I2C_TCON_SCL_CONN

SMB_55S

SMB

I2C_TCON_SDA

SMBUS_SMC_MGMT_SCL

SMB_55S

SMB

I2C_SMC_SMS_SCL_R

SMB_55S

SMB

SMBUS_SMC_MGMT_SDA

I2C_SMC_SMS_SDA_R

USB_85D

USB

USB_TPAD_CONN_N

USB_85D

USB

USB_TPAD_CONN_P

AUD_DIFF

1TO1_DIFFPAIR

AUDIO

AUD_LO2_P_L

USB_85D

USB

USB_LT1_N

SENSE

SENSE_1TO1_55S

ISNS_LCDBKLT_P

SENSE

SENSE_DIFFPAIR

ISNS_HDD_R_N

SENSE_1TO1_55S

USB_85D

USB

USB_LT1_P

USB_85D

USB

USB_EXTA_MUXED_P

CLK_PCIE_90D CLK_PCIE

PCIE_CLK100M_AP_CONN_N

1TO1_DIFFPAIR

CHGR_CSI_R_N

1TO1_DIFFPAIR

CHGR_CSI_R_P

1TO1_DIFFPAIR

CHGR_CSO_R_P

AUD_DIFF

1TO1_DIFFPAIR

AUDIO

AUD_LO1_N_R

1TO1_DIFFPAIR

AUDIO

AUD_DIFF

AUD_LO2_N_R

AUD_DIFF

1TO1_DIFFPAIR

AUDIO

AUD_LO2_P_R

AUD_DIFF

1TO1_DIFFPAIR

AUDIO

SSM2315_R_N

DIFFPAIR

AUDIO

SPK_OUT

SPKRAMP_R_N_OUT

DIFFPAIR

AUDIO

SPK_OUT

SPKRAMP_R_P_OUT

DIFFPAIR

AUDIO

SPK_OUT

SPKRAMP_SUB_P_OUT

DIFFPAIR

AUDIO

SPK_OUT

SPKRAMP_SUB_N_OUT

DIFFPAIR

AUDIO

SPK_OUT

SPKRAMP_L_N_OUT

CLK_PCIE_90D CLK_PCIE

PCIE_CLK100M_AP

PCIE_CLK100M_AP_CONN_P

USB_85D

USB

USB2_EXTA_MUXED_N

USB_85D

USB

USB2_LT1_P

USB_85D

USB

USB2_LT1_N

USB_85D

USB

USB_LT2_P

USB_85D

USB

CONN_USB2_BT_N

USB_85D

USB

USB2_EXTA_MUXED_P

1TO1_DIFFPAIR

CHGR_CSO_R_N

USB_85D

USB

CONN_USB2_BT_P

USB_85D

USB

USB_LT2_N

DP_85D

DISPLAYPORT

DP_IG_AUX_CH_C_P

DP_85D

DISPLAYPORT

DP_IG_AUX_CH_C_N

DIFFPAIR

AUDIO

SPK_OUT

SPKRAMP_L_P_OUT

USB_85D

USB

USB_EXTA_MUXED_N

1TO1_DIFFPAIR

AUDIO

SPKRAMP_INL_N

AUD_DIFF

AUDIO

1TO1_DIFFPAIR

AUD_LO2_N_L

USB_85D

USB

USB_TPAD_R_N

PP3V3_S0

SB_POWER

AUD_DIFF

1TO1_DIFFPAIR

AUDIO

AUD_LO1_P_R

DIFFPAIR

MAX98300_R

MAX98300_R_P

AUDIO

ISNS_HS_COMPUTING_P

SENSE

SENSE_1TO1_55S

SATA_90D SATA

SATA_ODD_D2R_UF_N

SATA_90D SATA

SATA_HDD_D2R_RDRVR_OUT_N

SATA_90D SATA

SATA_HDD_D2R_RDRVR_IN_N

SATA_90D SATA

SATA_HDD_D2R_RDRVR_IN_P

SATA_90D SATA

SATA_HDD_R2D_RDRVR_OUT_P

THERM

SENSE_DIFFPAIR

CPUTHMSNS_D2_P

THERM_1TO1_55S

CPUTHMSNS_D2_N

THERM

THERM_1TO1_55S

THERM

T29_THERMD_N

THERM_1TO1_55S

SENSE_DIFFPAIR

T29_THERMD_P

THERM_1TO1_55S

THERM

GND

108 OF 109

2.5.0

051-8871

73 OF 74

6 7

6

39 50 73

6

39 50 73

50

6

39 50 73

6

39 50 73

44 57

44

53

56 57

45 55

44

56 57

53

37 45

45 55

44

44 57

44 58

45

9

46

9

46

8

45

37 45

44 56 57

36 45

44 58

6

48

6

48

8

45

52

45 52

6

50 51

6

50 51

38

45 52

6 7

50

45

46

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_BOARD_INFO

VERSION

ALLEGRO

(MIL or MM)

BOARD UNITS

BOARD LAYERS

BOARD AREAS

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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REVISION

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SIZE

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PAGE TITLE

C

A

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21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

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345678

D

B

8 7 5 4 2 1

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

K90i Board-Specific Spacing & Physical Constraints

NOTE: 110_DIFF is 110-ohms differential impedance on outer layers and 105-ohms on inner layers.

NOTE: These are Intel recommended impedances for PEG, unused on K90i.

NOTE: 85_DIFF_BGA is 85-ohms differential impedance on outer layers and 80-ohms on inner layers.

NOTE: 100_DIFF_BGA is 100-ohms differential impedance on outer layers and 95-ohms on inner layers.

NOTE: 90_DIFF_BGA is 90-ohms differential impedance on outer layers and 85-ohms on inner layers.

?

0.25 MM

*

2.5:1_SPACING

?

0.3 MM

*

3:1_SPACING

?

0.4 MM

*

4:1_SPACING

?

0.2 MM

*

2:1_SPACING

?

0.15 MM

*

1.5:1_SPACING

?

=DEFAULT

*

STANDARD

?

=DEFAULT

*

BGA_P1MM

?

=DEFAULT

*

BGA_P2MM

?

0.1 MM

*

DEFAULT

?

0.350 MM

*

5X_DIELECTRIC

?

0.280 MM

*

4X_DIELECTRIC

?

0.490 MM

*

7X_DIELECTRIC

?

0.210 MM

*

3X_DIELECTRIC

?

0.140 MM

*

2X_DIELECTRIC

BGA_P2MM

BGA

*

MEM_CLK

BGA_P2MM

BGA

*

CLK_PCIE

BGA_P2MM

BGA

*

CLK_SLOW

BGA_P1MM

BGA

**

=STANDARD=STANDARD=STANDARD0.1 MM0.160 MM

Y

37_OHM_SE

ISL3,ISL4,ISL9,ISL10

=STANDARD=STANDARD=STANDARD=STANDARD=STANDARD

Y

37_OHM_SE

*

0.1 MM0.195 MM

Y

37_OHM_SE TOP,BOTTOM

=STANDARD=STANDARD=STANDARD=STANDARD=STANDARD

Y*

40_OHM_SE

=STANDARD=STANDARD=STANDARD0.140 MM0.140 MM

Y

40_OHM_SE

ISL3,ISL4,ISL9,ISL10

0.170 MM0.170 MM

Y

TOP,BOTTOM40_OHM_SE

=STANDARD=STANDARD=STANDARD0.090 MM0.090 MM

Y*

50_OHM_SE

0.090 MM0.110 MM

Y

TOP,BOTTOM50_OHM_SE

=DEFAULT=DEFAULT10 MM=DEFAULT=DEFAULT

Y*

STANDARD

0 MM0 MM10 MM=50_OHM_SE=50_OHM_SE

Y*

DEFAULT

15.5.1MMNO_TYPE,BGA

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM

TOP,BOTTOM

Y

0.090 MM 0.090 MM55_OHM_SE

55_OHM_SE

* Y

0.076 MM 0.076 MM =STANDARD =STANDARD =STANDARD

PCB Rule Definitions

SYNC_DATE=04/06/2011

SYNC_MASTER=CONSTRAINTS

* Y

=STANDARD =STANDARD =STANDARD =STANDARD =STANDARD90_OHM_DIFF

*

85_OHM_DIFF

Y

=STANDARD =STANDARD =STANDARD =STANDARD =STANDARD

85_OHM_DIFF ISL4,ISL9

Y

0.115 MM 0.115 MM 0.170 MM 0.170 MM

85_OHM_DIFF TOP,BOTTOM

Y

0.130 MM 0.130 MM 0.195 MM 0.195 MM

85_OHM_DIFF ISL3,ISL10

Y

0.095 MM 0.1 MM 0.170 MM 0.170 MM

ISL3,ISL10

Y

0.089 MM 0.089 MM 0.210 MM 0.210 MM90_OHM_DIFF

90_OHM_DIFF ISL4,ISL9

Y

0.105 MM 0.105 MM 0.210 MM 0.210 MM

90_OHM_DIFF TOP,BOTTOM

Y

0.115 MM 0.115 MM 0.210 MM 0.210 MM

100_OHM_DIFF ISL3,ISL10

Y

0.074 MM 0.074 MM 0.250 MM 0.250 MM

*

100_OHM_DIFF

Y

=STANDARD =STANDARD =STANDARD =STANDARD =STANDARD

100_OHM_DIFF ISL4,ISL9

Y

0.085 MM 0.085 MM 0.250 MM 0.250 MM

110_OHM_DIFF ISL4,ISL9

Y

0.071 MM 0.071 MM 0.300 MM 0.300 MM

110_OHM_DIFF ISL3,ISL10

N

0.070 MM 0.070 MM 0.330 MM 0.330 MM

110_OHM_DIFF

* Y

=STANDARD =STANDARD =STANDARD =STANDARD =STANDARD

100_OHM_DIFF TOP,BOTTOM

Y

0.091 MM 0.091 MM 0.200 MM 0.200 MM

110_OHM_DIFF TOP,BOTTOM

Y

0.077 MM 0.077 MM 0.280 MM 0.280 MM

48_OHM_SE TOP,BOTTOM

Y

0.120 MM 0.165 MM

48_OHM_SE

* Y

0.097 MM 0.090 MM =STANDARD =STANDARD =STANDARD

*

80_OHM_DIFF

Y

=STANDARD =STANDARD =STANDARD =STANDARD =STANDARD

80_OHM_DIFF ISL3,ISL10

Y

0.110 MM 0.110 MM 0.170 MM 0.170 MM

80_OHM_DIFF TOP,BOTTOM

Y

0.145 MM 0.145 MM 0.180 MM 0.180 MM

80_OHM_DIFF ISL4,ISL9

Y

0.129 MM 0.129 MM 0.170 MM 0.170 MM

85_DIFF_BGA =85_OHM_DIFF*=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

85_DIFF_BGA ISL3,ISL4

Y

0.075 MM 0.075 MM 0.125 MM 0.125 MM

85_DIFF_BGA ISL9,ISL10

Y

0.075 MM 0.075 MM 0.125 MM 0.125 MM

90_DIFF_BGA ISL3,ISL4

Y

0.075 MM 0.075 MM 0.125 MM 0.125 MM

90_DIFF_BGA

*

=90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF

=90_OHM_DIFF

90_DIFF_BGA ISL9,ISL10

Y

0.075 MM 0.075 MM 0.125 MM 0.125 MM

100_DIFF_BGA ISL3,ISL4

Y

0.075 MM 0.075 MM 0.125 MM 0.125 MM

100_DIFF_BGA

*

=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF

100_DIFF_BGA ISL9,ISL10

Y

0.075 MM 0.075 MM 0.125 MM 0.125 MM

*

1:1_DIFFPAIR

Y

=STANDARD=STANDARD =STANDARD 0.1 MM0.1 MM

27P4_OHM_SE TOP,BOTTOM

Y

0.310 MM 0.2 MM

27P4_OHM_SE

* Y

0.250 MM 0.2 MM =STANDARD =STANDARD =STANDARD

72_OHM_DIFF

* Y

=STANDARD =STANDARD =STANDARD =STANDARD =STANDARD

72_OHM_DIFF ISL4,ISL9

Y

0.155MM 0.155 MM 0.130 MM 0.130 MM

72_OHM_DIFF TOP,BOTTOM

Y

0.165 MM 0.165 MM 0.130 MM 0.130 MM

72_OHM_DIFF ISL3,ISL10

Y

0.135 MM 0.135 MM 0.130 MM 0.130 MM

109 OF 109

2.5.0

051-8871

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