Apple 820-2610-A Schematic

87

www.vinafix.vn

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

6

5

4

SCHEMATIC,Folsten_MBP17

3

REV

21

ZONE

ECN

738810B

DESCRIPTION OF CHANGE

Production Release

CK
APPD

DATE

ENG
APPD

6/19/096/19/09

DATE

06/15/09

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45

(.csa)

1

Table of Contents

2
3
4
5
6
7
8
9

2

System Block Diagram

3

Power Block Diagram

4

Revision History

5

BOM Configuration

6

JTAG Scan Chain

7

Functional / ICT Test

8

Power Aliases

9

Signal Aliases

10

CPU FSB

11

CPU Power & Ground

12

CPU Decoupling & VID

13

eXtended Debug Port(MiniXDP)

14

MCP CPU Interface

15

MCP Memory Interface

16

MCP Memory Misc

17

MCP PCIe Interfaces

18

MCP Ethernet & Graphics

19

MCP PCI & LPC

20

MCP SATA & USB

21

MCP HDA & MISC

22

MCP Power & Ground

25

MCP Standard Decoupling

26

MCP Graphics Support

28

SB Misc

29

FSB/DDR3/FRAMEBUF Vref Margining

31

DDR3 SO-DIMM Connector A

32

DDR3 SO-DIMM Connector B

33

DDR3 Support

34

Right Clutch Connector

35

ExpressCard Connector

37

Ethernet PHY (RTL8211CL)

38

Ethernet & AirPort Support

39

Ethernet Connector

41

FireWire LLC/PHY (FW643)

42

FireWire Port Power

43

FireWire Ports

45

SATA Connectors

46

External USB Connectors

48

Front Flex Support

49

SMC

50

SMC Support

51

LPC+SPI Debug Connector

52

K20 SMBUS CONNECTIONS

53

Current & Voltage Sensing

Contents

K20_MLB

M98_MLB

RXU_K20

NA

K20A_MLB

BEN_K20

K20_MLB

RXU_K20

K20_MLB

M98_MLB

M98_MLB

M98_MLB

M98_MLB

T18_MLB

T18_MLB

T18_MLB

T18_MLB

T18_MLB

T18_MLB

T18_MLB

T18_MLB

T18_MLB

M98_MLB

M98_MLB

M98_MLB

BEN_K20

BEN_K20

BEN_K20

M98_MLB

M98_MLB

BEN_K20

SUMA_K20

SUMA_K20

SUMA_K20

M98_MLB

YWU_K20

M98_MLB

M98_MLB

M98_MLB

CHANG_K20

T18_MLB

M98_MLB

CHANG_K20

BEN_K20

YWU_K20

D

C

B

Page

TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_HEAD

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TABLE_TABLEOFCONTENTS_ITEM

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Sync

Date

04/01/2008

04/01/2008

07/24/2008

NA

04/01/2008

07/11/2008

09/24/2008

05/07/2008

09/24/2008

04/01/2008

04/01/2008

04/01/2008

04/01/2008

06/06/2008

06/06/2008

06/06/2008

06/06/2008

06/06/2008

06/06/2008

06/06/2008

06/06/2008

06/06/2008

04/01/2008

04/01/2008

05/01/2008

10/15/2008

06/10/2008

07/14/2008

04/01/2008

05/01/2008

10/15/2008

07/22/2008

07/15/2008

07/15/2008

04/01/2008

05/28/2008

07/14/2008

05/01/2008

07/14/2008

07/18/2008

06/06/2008

05/01/2008

05/28/2008

07/22/2008

08/20/2008

(.csa)

Page Sync

46

TABLE_TABLEOFCONTENTS_ITEM

47

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48

TABLE_TABLEOFCONTENTS_ITEM

49

TABLE_TABLEOFCONTENTS_ITEM

50

TABLE_TABLEOFCONTENTS_ITEM

51

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52

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53

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54

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55

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56

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57

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58

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59

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60

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61

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62

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63

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64

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65

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66

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67

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68

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69

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70

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71

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72

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73

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74

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75

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76

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77

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78

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79

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80

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81

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82

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83

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84

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85

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86

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87

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88

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89

TABLE_TABLEOFCONTENTS_ITEM

90

TABLE_TABLEOFCONTENTS_ITEM

54

Current Sensing

55

Thermal Sensors

56

Fan Connectors

57

WELLSPRING 1

58

WELLSPRING 2

59

Sudden Motion Sensor (SMS)

61

SPI ROM

62

AUDIO:CODEC

63

AUDIO: LINE IN

65

AUDIO: HEADPHONE AMP

66

AUDIO:SPEAKER AMP

67

AUDIO: JACKS

68

AUDIO: JACK TRANSLATORS

69

DC-In & Battery Connectors

70

PBus Supply & Battery Charger

71

IMVP6 CPU VCore Regulator

72

5V / 3.3V Power Supply

73

1.5V DDR3 Supply

75

5V_S0 / MCP CORE REGULATOR

76

CPU VTT Power Supply

77

Misc Power Supplies

78

Power Control

79

Power FETs

80

NV G96 PCI-E

81

NV G96 CORE/FB POWER

82

NV G96 FRAME BUFFER I/F

84

GDDR3 Frame Buffer A (Bottom)

85

GDDR3 Frame Buffer B (Bottom)

86

NV G96 GPIO/MIO/MISC

87

G96 GPIOs & Straps

88

NV G96 Video Interfaces

89

GPU (G96) CORE SUPPLY

90

LVDS Display Connector

91

GDDR3 Frame Buffer A (Top)

92

GDDR3 Frame Buffer B (Top)

93

Muxed Graphics Support

94

DisplayPort Connector

95

1.1V / 1V8 FB Power Supply

96

Graphics MUX (GMUX)

97

LCD BACKLIGHT DRIVER

98

LCD Backlight Support

99

Misc Power Supplies

100

CPU/FSB Constraints

101

Memory Constraints

102

MCP Constraints 1

Contents

YWU_K20

YWU_K20

M98_MLB

YMA_K20

K20_MLB

YWU_K20

M98_MLB

AUDIO_K20

AUDIO_K20

AUDIO_K20

AUDIO_K20

AUDIO_K20

AUDIO_K20

RXU_K20

RXU_K20

RXU_K20

RXU_K20

RXU_K20

RXU_K20

RXU_K20

RXU_K20

YMA_K20

YMA_K20

M98_MLB

M98_MLB

K20_MLB

M98_MLB

M98_MLB

K20_MLB

M98_MLB

K20_MLB

RXU_K20

M98_MLB

M99_MLB

M88_MLB

M98_MLB

K20_MLB

RXU_K20

T18_MXMGMUX

KIRAN_K20

YLEE_K20

RXU_K20

M98_MLB

M98_MLB

M98_MLB

Date

08/12/2008

05/28/2008

04/01/2008

05/19/2008

09/24/2008

06/17/2008

05/01/2008

09/29/2008

09/29/2008

09/29/2008

09/29/2008

09/29/2008

09/29/2008

05/21/2008

05/21/2008

05/21/2008

05/21/2008

05/21/2008

05/21/2008

05/21/2008

05/21/2008

09/09/2008

05/19/2008

04/01/2008

04/01/2008

09/24/2008

04/01/2008

04/01/2008

09/24/2008

05/12/2008

09/24/2008

05/21/2008

07/14/2008

04/04/2008

11/01/2007

05/01/2008

09/24/2008

05/21/2008

02/13/2008

03/19/2009

07/18/2008

05/07/2008

04/01/2008

04/01/2008

04/01/2008

Page

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEMTABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

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TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

911
92
93
94
95
96
97
98

(.csa)

103

MCP Constraints 2

104

Ethernet Constraints

105

FireWire Constraints

106

SMC Constraints

107

GPU (G96) Constraints

108

Project Specific Constraints

109

PCB Rule Definitions

123

PROJECT SPECIFIC CONNS

Contents

Sync

M98_MLB

M98_MLB

M98_MLB

M98_MLB

M98_MLB

M98_MLB

M98_MLB

N/A

Date

04/01/2008

04/01/2008

04/01/2008

04/01/2008

05/01/2008

04/01/2008

04/01/2008

N/A

D

C

B

A

8

76

DIMENSIONS ARE IN MILLIMETERS

XX

X.XX

X.XXX

ANGLES

DO NOT SCALE DRAWING

THIRD ANGLE PROJECTION

5

4

3

DRAFTER

ENG APPD

QA APPD

RELEASE

METRIC

MATERIAL/FINISH

NOTED AS

APPLICABLE

DESIGN CK

MFG APPD

DESIGNER

SCALE

NONE

SIZE

2

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

TITLE

DRAWING NUMBER

D

APPLE INC.

SCHEM,Folsten,MBP17

051-8071

REV.

SHT

1

1

A

B

OF

98

87

www.vinafix.vn

6

U1000

INTEL CPU

2.X OR 3.X GHZ

PENRYN

PG 9

5

U1300

XDP CONN

PG 12

4

3

21

FSB

D

PG 13

GPIOs

FSB INTERFACE

64-Bit

800/1067/1333 MHz

MAIN

MEMORY

PG 14

2 UDIMMs

DDR2-800MHZ
DDR3-1067/1333MHZ

J2900

DIMM

PG 25,26

J6950

DC/BATT

PG 60

U4900

POWER SUPPLY

D

TEMP SENSOR

USB

PG 39

PG 41

PG 45

PG 48,49

J5100

Port80,serial

LPC Conn

PG 43

C

B

CLK

SYNTH

J4510

SATA

Conn

PG 38

HD

J4520

SATA

Conn

PG 38

C

ODD

1.05V/3GHZ.

1.05V/3GHZ.

SATA

PG 19

NVIDIA

MCP79

U1400

J9000

LVDS

CONN

J9400

DISPLAY PORT

CONN

PG 71

PG 71

LVDS OUT

RGB OUT

DP OUT

HDMI OUT

DVI OUT

TMDS OUT

PG 17

UP TO 20 LANES3

PG 16

PCI-E

B

RGMII

PG 17

PCI

(UP TO FOUR PORTS)

PG 18

Misc

PG 24

SPI

PG 20

LPC

PG 18

PWR

CTRL

USB

PG 19

(UP TO 12 DEVICES)

SMB

PG 20

HDA

PG 20

J4720

Bluetooth

4

389

2

10567

U6100

SPI

Boot ROM

PG 52

J4900

B,0

BSB

FanADC

SMC

PG 41

J4700

TRACKPAD/

PG 40

KEYBOARD

PG 40

J4710

IR

PG 40

J4710

CAMERA

PG 40

POWER SENSE

J5650,5600,5610,5611,5660,5720,5730,5750

FAN CONN AND CONTROL

Ser

Prt

J3900,4635,4655

EXTERNAL

Connectors

SMB

CONN

DIMM’s

PG 44

A

J3400 U3900

Mini PCI-E

AirPort

PG 28

8

76

U3700

GB

E-NET

88E1116

PG 31

E-NET

Conn

PG 33

U6200

U6301 U6500U6400

Line In

Amp

PG 54

HEADPHONE

Amp Amp

J6800,6801,6802,6803

5

Audio

Codec

PG 53

U6600,6605,6610,6620

Line Out

PG 56PG 55

Audio

Conns

PG 59

4

Speaker

Amps

PG 57

3

SYNC_MASTER=M98_MLB

APPLE INC.

2

System Block Diagram

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

SHT

051-8071

2

1

SYNC_DATE=04/01/2008

REV.

B

OF

98

A

87

www.vinafix.vn

6

5

4

3

21

"Folsten" POWER SYSTEM ARCHITECTURE

PPDCIN_G3H

J6900

D

AC

ADAPTER

IN

DCIN(16.5V)

F6905
6A FUSE

R7020

SMC_DCIN_ISENSE

A

U7000

VIN

ISL6258A

PBUS SUPPLY/

BATTERY CHARGER

(PAGE 60)

J6950

PPVBATT_G3H_CONN

2S4P

(6 TO 8.4V)

C

GMUX

U9600

XP28

(PAGE 84)

PB16B

PB17A

PB17B

PB18A

PL32A

EG_RAIL1_EN

EG_RAIL2_EN

EG_RAIL3_EN

EG_RAIL4_EN

PM_ALL_GPU_PGOOD

SMC

RC

DELAY

Q7056

BATT_POS_GATE

P1V1GPU_EN

P3V3GPU_EN

GPUVCORE_EN

P1V8_S0GPU_EN

P3V3S5_EN

Q7055

CHGR_BGATE

U4900

PM_G2_P1V05S5_EN

RC

DELAY

(PAGE 42)

P60

SMC_PM_G2_EN

MCP79

SLP_RMGT#(J17)

B

PCI_RESET0#(R10)

U1400

SLP_S5#(H17)

SLP_S3#(G17)

PM_SLP_RMGT_L

R2870

RC

DELAY

PM_SLP_S4_L

PM_SLP_S3_L

MEM_VTT_EN

DDRREG_EN

P5VS3_EN

R6905

VOUT

PPVBAT_G3H_CHGR_R

P1V1_GPU_EN

P1V8_S0GPU_EN

BKLT_PLT_RST_L

LCD_BKLT_EN

PPVBAT_G3H_CHGR_REG

R7050
U5303

SMC_BATT_ISENSE

MCPCORES0_EN

PM_SLP_S3_L_R

Q4260

VIN

EN1

1.103V(L/H)

EN2

1.8V(R/H)

ISL6236

U9500

(PAGE 83)

ENA&&

(PAGE 85~86)

A

VOUT2

P5VS3_EN

P3V3S5_EN

VIN

APP001

U9701

VIN

(PAGE 14~22)

FW_PORTPWR_EN&&(SMC_ADAPTER_EN||PM_SLP_S3_L)

R7878

PM_SLP_S3_L_R

A

DELAY

DELAY

DELAY

DELAY

RC

RC

RC

RC

P1V8S0_EN

MCPDDR_EN

CPUVTTS0_EN

MCPCORES0_EN

DELAY

DELAY

DELAY

P1V05S0_EN

RC

P1V2_S0_EN

RC

P2V5S0_EN

RC

PM_G2_P1V05S5_EN

EN

VIN

1.05V AUX

ISL6269

U7750

(PAGE 66)

VOUT1

POK1

POK2

(PAGE 66)

D6905

D6905

F7040

F7041

8A FUSE

MCP_CORE

EN2

EN1

VIN

(PAGE 64)

PP1V1_S0GPU

R5413

A

P1V1GPU_PGOOD

PM_ALL_GPU_PGOOD

VOUT

LTC1872

U7790

VOUT

PGOOD

VOUT2

5V

VOUT1

ISL6236

POK1

U7500

POK2

PP1V8_S0GPU_ISNS

SMC_GPU_1V8_ISENSE

VIN

EN1

5V

(L/H)

3.3V

EN2

(R/H)

TPS51220

U7201

(PAGE 62)

PGOOD1,2

P5V3V3_PGOOD

PPVOUT_S0_LCDBKLT

PP10V_FW

VOUT

PP1V2R1V05_S5

P1V05_S5_PGOOD

PPVIN_G3H_P3V42G3H

PPBUS_G3H

R7505

A

SMC_MCP_CORE_ISENSE

PP5V_S0

P5V_RTS0_PGOOD

MCPCORES0_PGOOD

DDRREG_EN

MEM_VTT_EN

PP5V_S3

VOUT1

PP3V3_S5

VOUT2

PPBUS_G3H_VSENSE

GPUVCORE_EN

SMC_CPU_HI_ISENSE

V

PPVCORE_S0_MCP

Q7953

P1V05S0_EN

V

SMC_MCP_VSENSE

Q7910

Q7930

Q7970

PP1V05_S0

Q3840

PM_SLP_RMGT_L

Q3810

Q5315

VIN

S5

S3

TPS51116

(PAGE 63)

PM_SLP_S4_L

PM_SLP_S3_L

P3V3GPU_EN

PM_SLP_RMGT_L

VIN

GPU VCORE

ISL6263C

U8900

(PAGE 77)

R5388

A

IMVP_VR_ON

1.5V

0.75V

U7300

PP3V3_S5

PP3V3_S3

PP3V3_S0

PP3V3_S0GPU

P3V3_ENET_PHY

PP1V2R1V05_ENET

PGOODVR_ON

VLDOIN

VOUT1

VOUT2

ENABLE

3.425V G3HOT

(PAGE 59)

VOUT

P1V8_S0GPU_EN

LT3470A

U6990

A

U5410

SMC_GPU_ISENSE

GPUVCORE_PGOOD

CPU VCORE

VIN

ISL9504B

U7100

VR_ON

(PAGE 61)

PP1V8R1V5_S3

PP0V9R0V75_S0_DDRVTT

P1V2_S0_EN

P2V5S0_EN

R0940

P1V0FW_EN

P1V8S0_EN

EN

PP3V42_G3H

VOUT

PGOOD

VI

TPS62202

U7760

(PAGE 66)

PP3V3_S5

P1V05_S5_PGOOD

SMC_GPU_VSENSE

V

PPVCORE_GPU

U7100

SMC_CPU_ISENSE

VR_PWRGOOD_DELAY

RUN1

LTC3547

U9900

RUN2

(PAGE 87)

RUN1

LTC3547

U7700

RUN2

(PAGE 66)

VOUT

PP3V42_G3H

A

Q7901

MCPDDR_EN

VIN

VOUT1

VOUT2

VIN

VOUT1

VOUT2

PP1V8_GPUIFPX

PP1V8R1V5_S0

PP1V05_S0

SENSE

(PAGE 67)

S5 PWRGD

NCP303LSN

(PAGE 42)

SMC_CPU_VSENSE

V

R5445

SMC_MCP_DDR_ISENSE

A

PP1V2_S0

PP2V5_S0

PM_ALL_GPU_PGOOD

PP1V0_FW

PP1V8_S0

VDD

U7840

TPS3808G

SMC PWRGD

U5000

CPUVTTS0_EN

PPVCORE_S0_CPU

PPMCPDDR_ISNS

PP1V8R1V5_S0

PP3V3_S5

S0PGOOD_PWROK

PP3V3_S0

ADJ1

ADJ2

RSMRST_PWRGD

RESET*

MR*

SMC_RESET_L

EN_PSV

R7894

P5V3V3_PGOOD

P5V_RTS0_PGOOD

MCPCORES0_PGOOD

CPUVTTS0_PGOOD

VCC

U7870

LTC2909

(PAGE 67)

TRST = 200mS

VIN

1.05V

SC417
U7600

(PAGE 65)

U7880

RST*

MIC5232-2.8YD5

U2801

VIN

(PAGE 25)

VOUT

PGOOD

ALL_SYS_PWRGD

RSMRST_PWRGD

VOUT

CPUVTTS0_PGOOD

MCP_PS_PWRGD

U2850

SMC_ONOFF_L

PM_SLP_S4_L

PM_SLP_S4_L

PM_SLP_S3_L

PP3V3_G3_RTC

R7650

PPCPUVTT_S0

A

SMC_CPU_FSB_ISENSE

PS_PWRGD

(PAGE 14~22)

CPU

U1000

(PAGE 10,11)

PWRGD(P12)

RSMRST_IN(P13)

PWR_BUTTON(P90)

SLP_S5_L(P95)

SLP_S4_L(P94)

SLP_S3_L(P93)

SYNC_MASTER=RXU_K20

APPLE INC.

SMC_TPAD_RST_L

SMC_ONOFF_L

U5001

MCP79

PWRBTN#

RSTBTN#

PWRGD_SB

CPU_RESET#

CPU_PWRGD

PM_SYSRST_DEBOUNCE_L

FSB_CPURST_L

CPU_PWRGD

U1400

PWRGOOD

RESET*

SMC

U4900

(PAGE 42)

RSMRST_OUT(P15)

99ms DLY

IMVP_VR_ON(P16)

P17(BTN_OUT)

SYSRST(PA2)

RES*

PM_RSMRST_L

IMVP_VR_ON

PM_SYSRST_L

PM_PWRBTN_L

SMC_RESET_L

Power Block Diagram

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

SHT

051-8071

3

SYNC_DATE=07/24/2008

REV.

B

OF

98

D

C

B

A

8

76

5

4

3

2

1

87

www.vinafix.vn

PVT:

03/24/09
csa.5: Project copied from K20 mlb_pvt.

Changed CPU APNs for 2.8 and 3.06GHz CPUs.

Changed BOM and EEE codes for K20A.
csa.45: Connected =PP1V5_EXP_S0 to J4501.13 for SATA redriver on flex.
03/25/09
csa.9: Added PBUS VS 5V voltage selection resistors for keyboard backlight driver.
03/27/09
csa.90: Added 1000pF cap to the backlight power pin for EMI baseline noise.
03/30/09

D

csa.5: Changed the bom option to KBDLED_5V per radar# 6723272.
03/31/09
csa.1: Changed rev to 1.0.0
04/09/09
csa.70: No stuff C7099 per radar# 6772695.
04/29/09
Production Release Fab to rev A
csa.5: Changed K20A EFI ROM APN 341S2507 ( BOM change only )
05/05/09
Added 128S0264 (SANYO) as alternate to 128S0257 (KEMET ELEC) per Radar# 6656624.
06/15/09
Added 107S0136 (DALE/VISHAY) as alternate to 107S0132 (CYNTEC) per Radar# 6971400.
For U7871 P/N 353S2718 is made primary. P/N 353S2310 is added back as alternate.
For U6100 Locked Bootrom P/N 341S2506 replaces existing Unlock Bootrom P/N 341S2507.

6

5

4

3

21

D

C

B

C

B

A

8

76

Revision History

OF

SYNC_DATE=NA

REV.

B

98

A

SYNC_MASTER=NA

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

5

4

3

2

SCALE

NONE

SHT

051-8071

4

1

87

www.vinafix.vn

BOM Variants

BOM NUMBER

639-0172

639-0173

639-0174

639-0175

D

Folsten BOM GROUPS

BOM GROUP

K20A_COMMON

K20A_COMMON1

K20A_COMMON2

K20A_DEBUG

K20A_PROGPARTS

BOM GROUP

FB_1024_SAMSUNG

FB_512_SAMSUNG

FB_512_HYNIX

6

BOM NAME

PCBA,BEST,2.8,512SAM_VRAM,K20A

PCBA,BEST,3.06,512SAM_VRAM,K20A

PCBA,BEST,2.8,512HYN_VRAM,K20A

PCBA,BEST,3.06,512HYN_VRAM,K20A

K20A_COMMON,EEE_9EH,CPU_2_80GHZ,FB_512_SAMSUNG

K20A_COMMON,EEE_9EK,CPU_3_06GHZ,FB_512_SAMSUNG

K20A_COMMON,EEE_9EL,CPU_2_80GHZ,FB_512_HYNIX

K20A_COMMON,EEE_9EM,CPU_3_06GHZ,FB_512_HYNIX

BOM OPTIONS

ALTERNATE,COMMON,K20A_COMMON1,K20A_COMMON2,K20A_DEBUG,K20A_PROGPARTS

ONEWIRE_PU,ISL6258,MEMRESET_HW,MEMRESET_MCP,MCP_B03,MCP_PROD,MCPSEQ_SMC,BMON_PROD,MCP_CS1_NO,FW_LVG_NEW,PROD_DIGSMS,TPDT_DEBOUNCE,KBDLED_5V

BOOT_MODE_USER,GPUVID_1P00V,MUXGFX,DPMUX_EN_S0,DP_ESD,EG_PWRSEQ_GMUX,DP_CA_DET_EG_PLD,BKLT_PLL_NOT,GMUX_1V8

SMC_DEBUG_YES,XDP,LPCPLUS_NOT,NO_VREFMRGN

GMUX_PROG,BOOTROM_PROG,SMC_PROG,TPAD_PROG

BOM OPTIONS

VRAM8,VRAM_1024_SAMSUNG

VRAM4,VRAM_512_SAMSUNG

VRAM4,VRAM_512_HYNIX

BOM OPTIONS

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

5

Alternate Parts

PART NUMBER

152S0476

353S1681

138S0603

152S0684 152S0368

104S0023 104S0018

104S0024 104S0017

341S2367 341S2366

152S0876

157S0058

152S0896

128S0264

107S0136

353S2310

ALTERNATE FOR
PART NUMBER

152S0276

353S1294

138S0602

152S0782

157S0055

514-0607514-0612

514-0608514-0613

152S0421152S0684

152S0518

152S0796152S0915

155S0329155S0457

128S0257

107S0132

353S2718

BOM OPTION

4

REF DES

COMMENTS:

ALL

Inductor alternate

ALL

TI alt to National

ALL

Murata alt to Samsung

ALL

Maglayers alt to Dale/Vishay

ALL

Cyntec alt to sense resistor

ALL

Panasonic alt to FW resistor

ALL

Macronix alt to SST

ALL

Maglayer alt to Delta

Delta alt to TDK Magnetics

ALL

FOXLINK ALT TO FOXCONN XCVRALL

FOXLINK ALT TO FOXCONN RCVRALL

ALL MAG LAYERS ALT TO VISHAY

MAG LAYERS ALT TO CYNTEC

ALL

ALL

MAG LAYERS ALT TO CYNTEC

MAG LAYERS ALT TO MURATA

ALL

ALL

SANYO ALT TO KEMET ELEC.

DALE/VISHAY ALT TO CYNTEC.

ALL

ALL

INTERSIL.COMMON TO K24/K19

3

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

21

D

C

Bar Code Labels / EEE #’s

PART NUMBER

826-4393

826-4393

826-4393

826-4393

Module Parts

B

PART NUMBER

338S0710

335S0610

341S2506

341S2384

341S2383

337S3744

333S0481

333S0506

QTY

1

1

1

1

QTY

1

1

1

1

1

1

1

1

1

1

1

1

4

8

4

DESCRIPTION

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

IC,ASSP,GPU,NV G96-GS,VLOWLKG,BGA969,LF

IC,RTL8251CA-VB-GR,GIGE TRANSCEIVER,48P LQFP

IC,FW643-E,1394B PHY/OHCI LINK/PCI-E,12

IC,MCP79XT-B3,35X35MM,BGA1437

IC,SMC,HS8/2117,9MMX9MM,TLP

IC,SMC,DEVELOPMENT,K20

IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP

IC,LOCKED EFI ROM,K20A

IR,ENCORE II, CY7C63833-LFXC

IC,PSOC +W/USB,56PIN,MLF,M98

IC,PDC,SLGKH,PRQ,3.06,35W,1066,E0,6M,BGA

IC,PDC,SLGEM.PRQ,2.80,35W,1066,E0,6M,BGA

IC,SGRAM,GDDR3,32MX32,800MHZ,136 FBGA

IC,SGRAM,GDDR3,32MX32,800MHZ,136 FBGA

IC,SDRAM,GDDR3,32MX32,900MHZ,TIVA,HF

A

DESCRIPTION

REFERENCE DES

[EEE:9EH]

[EEE:9EK]

[EEE:9EL]

[EEE:9EM]

REFERENCE DES

U8000

U3700

U4100

U1400

U4900

U4900

U6100

U6100

U4800

U5701

U1000

U1000

U8400,U8450,U8500,U8550

U8400,U8450,U8500,U8550,U9100,U9150,U9200,U9250

U8400,U8450,U8500,U8550

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL338S0737

CRITICAL338S0694

CRITICAL338S0654

CRITICAL

CRITICAL338S0563

CRITICAL341S2355

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL337S3682

CRITICAL333S0481

CRITICAL

CRITICAL

BOM OPTION

EEE_9EH

EEE_9EK

EEE_9EL

EEE_9EM

BOM OPTION

MCP_B03

SMC_BLANK

SMC_PROG

BOOTROM_BLANK

BOOTROM_PROG

TPAD_PROG

CPU_3_06GHZ

CPU_2_80GHZ

VRAM_512_SAMSUNG

VRAM_1024_SAMSUNG

VRAM_512_HYNIX

BOM Configuration

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

D

NONE

DRAWING NUMBER

SHT

051-8071

C

B

SYNC_DATE=04/01/2008SYNC_MASTER=K20A_MLB

REV.

OF

5

98

A

B

8

76

5

4

3

2

1

87

www.vinafix.vn

6

5

4

3

21

1.05V TO 3.3V LEVEL TRANSLATOR (M98: ON ICT FIXTURE)

=PP3V3_S0_XDP

6 8

13

D

C

8

10 11 12 13 61

=PP1V05_S0_CPU

JTAG_ALLDEV

R0601

1/16W
MF-LF

NOSTUFF

R0602

1/16W
MF-LF

10K

13 21

13 21

13 21

13 21

U1000

CPU

U1400

MCP

MAKE_BASE=TRUE

From XDP connector

JTAG_ALLDEV

1

C0601

0.1UF

20%
10V

2

CERM
402

1

5%

402

2

XDP_TCK

6

10 13 88

1

0

5%

402

2

XDP_TMS

6

10 13 88

XDP_TRST_L

6

10 13 88

JTAG_LVL_TRANS_EN_L

1

2

JTAG_ALLDEV

C0602

0.1UF

20%
10V
CERM
402

JTAG_ALLDEV

2

3

4

5

12

VCCA

NLSV4T244

A1
A2
A3
A4

OE*

1

U0600

UQFN

GND

6

11

VCCB

6

10 13 88

10 13 88

6

10 13 88

6

10 13 88

XDP_TCK

IN

XDP_TDI

IN

XDP_TMS

IN

XDP_TRST_L

IN

From XDP connector

or via level translator

10

B1

9

B2

8

B3

7

B4

1

R0606

10K

5%
1/16W
MF-LF
402

2

MAKE_BASE=TRUE

MAKE_BASE=TRUE

JTAG_MCP_TCK
JTAG_MCP_TDI
JTAG_MCP_TMS
JTAG_MCP_TRST_L

To XDP connector
and/or level translator

XDP_TDO

10 88

JTAG_MCP_TDO

21

XDP

PLACEMENT_NOTE=Place near pin U1000.AB3

R0603

0

21

5%
1/16W
MF-LF

402

XDP

PLACEMENT_NOTE=Place near pin U1400.F19

R0604

0

21

5%
1/16W
MF-LF

402

XDP_TDO_CONN

JTAG_MCP_TDO_CONN

13

OUT

XDP connector

13

OUT

XDP connector

D

C

NOSTUFF

PLACEMENT_NOTE=Place close to U8000

R0605

10K

1/16W
MF-LF

21

5%

402

GPU_JTAG_TMS

6

74

B

74

74

6

74

74

84

9

84

9

84

U8000

GPU

U9600

GMUX

74

84

9

GPU_JTAG_TDO

JTAG_GMUX_TDO

6

VCC

U0601

74LVC1G07

2

1

GMUX CPLD Programming Port

CRITICAL

J0600

1909782

M-RT-SM

GMUX_JTAG_CONN

B

7

=PP3V3_S0_XDP

1

TDO

2

3

TDI
TMS

4

5

TCK

6

8

6 8

NC NC

13

YA

4

5

NCNC

SOT886

GND

3

PLACEMENT_NOTE=Place close to U0600

GPU_JTAG_TCK

GPU_JTAG_TDI
GPU_JTAG_TMS
GPU_JTAG_TRST_L

JTAG_GMUX_TCK

JTAG_GMUX_TDI
JTAG_GMUX_TMS

=PP3V3_GPU_VDD33

8

74 75

TP_GPU_JTAG_TDO

MAKE_BASE=TRUE

A

8

76

JTAG Scan Chain

6

1

SYNC_DATE=07/11/2008

REV.

OF

98

A

B

SYNC_MASTER=BEN_K20

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

5

4

3

2

SCALE

NONE

051-8071

SHT

87

www.vinafix.vn

Functional Test Points

J5650 (LEFT FAN CONN)

FUNC_TEST

TRUE

TRUE

TRUE

=PP5V_S0_FAN_LT

FAN_LT_PWM
FAN_LT_TACH

8

48

48

48

J5660 (RIGHT FAN CONN)

TRUE

D

TRUE

TRUE

FAN_RT_PWM
FAN_RT_TACH
GND

48

48

J6780 (MIC CONN)

BI_MIC_LO

TRUE

I557

I558

I559

TRUE

TRUE

BI_MIC_SHIELD
BI_MIC_HI

57 58

57 58

57 58

J6781 (LEFT SPEAKER)

I985

I987

I986

I988

TRUE

TRUE

TRUE

TRUE

SPKRAMP_L1_OUT_N
SPKRAMP_L2_OUT_P
SPKRAMP_L2_OUT_N

56 57 96

56 57 96

56 57 96

56 57 96

SPKRAMP_L1_OUT_P

J6782 (RIGHT & SUB SPEAKER)

SPKRAMP_LFE_OUT_P

TRUE

I989

I990

I992

I991

I994

I993

C

TRUE

I1296

TRUE

I995

TRUE

I996

TRUE

I997

TRUE

I998

TRUE

I1000

TRUE

I1001

TRUE

I1002

TRUE

I1004

TRUE

I1003

TRUE

I1005

TRUE

I1007

TRUE

I1006

TRUE

I1009

TRUE

I1008

TRUE

I1010

TRUE

I1011

TRUE

I1012

TRUE

I1014

TRUE

I1013

TRUE

I1015

TRUE

I1016

TRUE

I1017

TRUE

I1018

TRUE

B

I1019

I1020

I1022

I1021

TRUE

TRUE

TRUE

TRUE

SPKRAMP_LFE_OUT_N

TRUE

SPKRAMP_R1_OUT_P

TRUE

SPKRAMP_R1_OUT_N

TRUE

SPKRAMP_R2_OUT_P

TRUE

SPKRAMP_R2_OUT_N

TRUE

J9000 (LVDS CONN)

BKL_SYNC
PP3V3_SW_LCD
=PP3V3_S0_DDC_LCD
PPVOUT_S0_LCDBKLT
LVDS_DDC_CLK
LVDS_DDC_DATA
LVDS_CONN_A_DATA_P<0>
LVDS_CONN_A_DATA_N<0>
LVDS_CONN_A_DATA_P<1>
LVDS_CONN_A_DATA_N<1>
LVDS_CONN_A_DATA_P<2>
LVDS_CONN_A_DATA_N<2>
LVDS_CONN_A_CLK_F_P
LVDS_CONN_A_CLK_F_N
LVDS_CONN_B_DATA_P<0>
LVDS_CONN_B_DATA_N<0>
LVDS_CONN_B_DATA_P<1>
LVDS_CONN_B_DATA_N<1>
LVDS_CONN_B_DATA_P<2>
LVDS_CONN_B_DATA_N<2>
LVDS_CONN_B_CLK_F_P
LVDS_CONN_B_CLK_F_N
LED_RETURN_1
LED_RETURN_2
LED_RETURN_3
LED_RETURN_4
LED_RETURN_5
LED_RETURN_6

GND

78 85

78

8

75 78

78 85

78 81

78 81

78 81 95

78 81 95

78 81 95

78 81 95

78 81 95

78 81 95

78 95

78 95

78 81 95

78 81 95

78 81 95

78 81 95

78 81 95

78 81 95

78 95

78 95

78 85

78 85

78 85

78 85

78 85

78 85

56 57 96

56 57 96

56 57 96

56 57 96

56 57 96

56 57 96

J4500 (SATA ODD CONN)

I1024

I1026

I1025

I1028

I1027

I1029

TRUE

SMC_ODD_DETECT

TRUE

SATA_ODD_D2R_C_P

TRUE

SATA_ODD_D2R_C_N

TRUE

SATA_ODD_R2D_P

TRUE

SATA_ODD_R2D_N

TRUE

TRUE

GND

38

38 41

38 90

38 90

38 90

38 90

PP5V_SW_ODD

J4501 (SATA HDD CONN)

PP5V_S0_HDD_FLT

TRUE

I1032

I1031

I1033

I1035

I1034

A

I1145

I1146

SATA_HDD_R2D_P

TRUE

SATA_HDD_R2D_N

TRUE

SATA_HDD_D2R_C_N

TRUE

SATA_HDD_D2R_C_P

TRUE

TRUE

J5815 (KBD BACKLIGHT CONN)

TRUE

TRUE

TRUE

FUNC_TEST

TRUE

GND

KBDLED_ANODE
SMC_KDBLED_PRESENT_L

GND

GND

6 TPs

TRUE

GND

38

38 90

38 90

38 90

38 90

50

50

3 TPs
per Fan

5 TPs
per Fan

2 TP needed

4 TPs

3 TPs

5 TPs

TRUE

I1038

TRUE

I1039

TRUE

I1040

TRUE

TRUE

I1042

TRUE

I1043

TRUE

I1044

TRUE

TRUE

I1046

TRUE

I1047

TRUE

I1048

TRUE

J3401 (AIRPORT/BT/CAMERA CONN)

TRUE

I1051

TRUE

I1050

TRUE

I1053

TRUE

I1052

TRUE

I1054

TRUE

I1056

TRUE

I1055

TRUE

I1058

TRUE

I1057

TRUE

I1059

TRUE

I1061

TRUE

I1060

TRUE

I1063

TRUE

I1062

TRUE

I1064

TRUE

I1066

TRUE

I1065

J3500 (EXPRESS CARD CONN)

TRUE

I1067

TRUE

I1068

TRUE

I1069

TRUE

I1071

TRUE

I1070

TRUE

I1072

TRUE

I1074

TRUE

I1073

TRUE

I1075

TRUE

I1076

TRUE

I1077

TRUE

I1079

TRUE

I1078

TRUE

I1081

TRUE

I1080

TRUE

I1082

TRUE

I1083

TRUE

I1084

J5800 (IPD FLEX CONN)

TRUE

I1085

TRUE

I1086

TRUE

I1087

TRUE

I1273

TRUE

I1089

TRUE

I1088

TRUE

I1090

TRUE

I1091

TRUE

I1098

TRUE

I1097

TRUE

I1095

TRUE

I1096

TRUE

I1092

TRUE

I1093

TRUE

I1094

TRUE

I1099

TRUE

I1100

TRUE

I1101

J6900 (DC POWER CONN)

TRUE

I1131

TRUE

I1132

TRUE

J6950 (MAIN BATT CONN)

TRUE

I1134

TRUE

I1136

TRUE

I1135

TRUE

I1137

TRUE

J6995 (BAT LED CONN)

TRUE

I1140

TRUE

I1142

TRUE

I1141

TRUE

I1143

TRUE

USB PORTS

PP5V_S3_RTUSB_A_F
USB2_LT1_N
USB2_LT1_P

GND

PP5V_S3_RTUSB_B_F
USB_LT2_N
USB_LT2_P

GND

PP5V_S3_RTUSB_C_F
USB_LT3_N
USB_LT3_P

GND

PCIE_MINI_D2R_P
PCIE_MINI_D2R_N
PCIE_MINI_R2D_P
PCIE_MINI_R2D_N
PCIE_CLK100M_MINI_CONN_P
PCIE_CLK100M_MINI_CONN_N
MINI_CLKREQ_Q_L
PCIE_WAKE_L
MINI_RESET_CONN_L
PP5V_WLAN
PP5V_S3_BTCAMERA_F
SMBUS_SMC_A_S3_SDA
SMBUS_SMC_A_S3_SCL
USB_CAMERA_CONN_P
USB_CAMERA_CONN_N
CONN_USB2_BT_P
CONN_USB2_BT_N

PP1V5_S0_EXCARD_SWITCH
PCIE_WAKE_L
SMBUS_MCP_0_CLK
SMBUS_MCP_0_DATA
PP3V3_S0_EXCARD_SWITCH
PP3V3_S3_EXCARD_SWITCH
USB2_EXCARD_CONN_N
USB2_EXCARD_CONN_P
EXCARD_CPUSB_L
EXCARD_CLKREQ_CONN_L
EXCARD_CPPE_L
PLT_RESET_SWITCH_L
PCIE_EXCARD_D2R_P
PCIE_EXCARD_D2R_N
PCIE_EXCARD_R2D_P
PCIE_EXCARD_R2D_N
PCIE_CLK100M_EXCARD_CONN_P
PCIE_CLK100M_EXCARD_CONN_N

PP3V3_S3_LDO
PP18V5_S3
TPAD_GND_F
Z2_CS_L
Z2_DEBUG3
Z2_MISO
Z2_BOOST_EN
Z2_BOOT_CFG1
Z2_CLKIN
Z2_KEY_ACT_L
Z2_RESET
PSOC_F_CS_L
PICKB_L
PSOC_MISO
PSOC_MOSI
PSOC_SCLK
SMBUS_SMC_A_S3_SCL
SMBUS_SMC_A_S3_SDA

ADAPTER_SENSE
PP18V5_DCIN_FUSE

GND

PPVBAT_G3H_CONN_F
SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SDA
SMC_BS_ALRT_L

GND

PP3V42_G3H
SMBUS_SMC_BSA_SDA
SMBUS_SMC_BSA_SCL
SMC_BIL_BUTTON_DB_L

GND

6

39

39 96

39 96

39

39 96

39 96

98

96 98

96 98

17 30 90

17 30 90

30 90

30 96

30 96

30

7

17 30 31

30

30

30

7

44 94

7

44 94

30 96

30 96

30 96

30 96

31

7

17 30 31

13 21 44 91

13 21 44 91

31

31

31 96

31 96

31

31

31

31

17 31 90

17 31 90

31 90

31 90

31 96

31 96

50

7

50

50

49 50

49 50

49 50

50

49 50

49 50

49 50

49 50

49 50

49 50

49 50

49 50

49 50

7

44 94

7

44 94

59

59

59

7

44 94

7

44 94

41 42 59

7 8

42

7

44 94

7

44 94

42 59

J5713 (KEY BOARD CONN)

PP3V3_S3

TRUE

I1103

I1102

I1104

I1105

I1107

I1106

I1108

I1109

I1110

I1111

I1112

I1113

I1114

I1115

I1117

I1116

I1118

I1119

I1120

I1122

I1121

I1123

I1124

I1125

I1127

I1126

I1128

I1129

I1130

PP3V42_G3H

TRUE

WS_KBD1

TRUE

WS_KBD2

TRUE

WS_KBD3

TRUE

WS_KBD4

TRUE

WS_KBD5

TRUE

WS_KBD6

TRUE

WS_KBD7

TRUE

WS_KBD8

TRUE

WS_KBD9

TRUE

WS_KBD10

TRUE

WS_KBD11

TRUE

WS_KBD12

TRUE

WS_KBD13

TRUE

WS_KBD14

TRUE

WS_KBD15_CAP

TRUE

WS_KBD16_NUM

TRUE

WS_KBD17

TRUE

WS_KBD18

TRUE

WS_KBD19

TRUE

WS_KBD20

TRUE

WS_KBD21

TRUE

WS_KBD22

TRUE

WS_KBD23

TRUE

WS_KBD_ONOFF_L

TRUE

WS_LEFT_SHIFT_KBD

TRUE

WS_LEFT_OPTION_KBD

TRUE

WS_CONTROL_KBD

TRUE

J4800 (FRONT CABLE CONN)

I1148

I1150

I1149

I1151

I1152

TRUE

TRUE

TRUE

TRUE

TRUE

PP5V_S3_IR_R
SMC_LID_R
IR_RX_OUT
SYS_LED_ANODE

PP3V42_G3H_LIDSWITCH_R

TRUE

J5502 (SENSOR CONN)

MCPTHMSNS_D_P

TRUE

I1154

I1155

I640

I602

I603

I604

I605

I607

I606

I608

I610

I612

I611

I613

I600

I625

I624

I623

I622

I620

I621

I618

I617

I615

I616

I614

I627

I626

I639

I638

I637

I636

I709

I714

I1156

I1157

I1159

I1160

I1161

TRUE

FUNC_TEST

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

MCPTHMSNS_D_N

POWER RAILS

PM_SLP_S3_L

PPBUS_G3H
PPBUS_CPU_IMVP_ISNS
PP3V42_G3H
PP5V_S3
PP5V_S0
PPVCORE_S0_CPU

PPVCORE_S0_MCP

PP3V3_S5
PP3V3_S3
PP3V3_S0

PP2V5_S0
PP1V2_S0

PP1V8_S0

PP1V8R1V5_S3

PP1V8R1V5_S0

PPMCPDDR_ISNS

PP1V05_S0

PP1V2R1V05_S5

PPCPUVTT_S0

PP0V9R0V75_S0_DDRVTT

PP1V2R1V05_ENET
PP3V3_ENET_PHY

PPVP_FW
PP1V0_FW
PP3V3_S0GPU

PP1V1_S0GPU

PP1V8_S0GPU_ISNS
PPVCORE_GPU
PP1V8_S0GPU_ISNS_R

PP3V3_S5_AVREF_SMC

PP18V5_S3

PPDCIN_G3H
PPVCORE_S0_MCP
PPMCPDDR_ISNS

PPVTTDDR_S3
PP1V8_GPUIFPX

GND

8

8

7 8

8

8

8

7 8

8

7 8

8 9

8

8

8

8

8

7 8

8

8

8

8

8

8

8

8

8

8

8

8

8

41 42

7

8

7 8

7 8

8

8

5

FUNC_TEST

SYS_LED_ANODE_R

I720

I722

I724

I723

I725

I726

I727

I729

I728

I730

I732

I731

I734

I733

I735

I736

I737

I739

I738

I740

I741

I742

I743

I744

I751

I752

I756

I1286

I1290

I1291

I1292

I1293

I1294

I1288

TRUE

LPC_CLK33M_LPCPLUS

TRUE

LPC_AD<0..3>

TRUE

SPI_ALT_MOSI

TRUE

SPI_ALT_MISO

TRUE

LPC_FRAME_L

TRUE

PM_CLKRUN_L

TRUE

SMC_TMS

TRUE

DEBUG_RESET_L

TRUE

SMC_TDO

TRUE

SMC_TRST_L

TRUE

SMC_MD1

TRUE

SMC_TX_L

TRUE

SPIROM_USE_MLB

TRUE

SPI_ALT_CLK

TRUE

SPI_ALT_CS_L

TRUE

LPC_SERIRQ

TRUE

LPC_PWRDWN_L

TRUE

SMC_TDI

TRUE

SMC_TCK

TRUE

SMC_RESET_L

TRUE

SMC_NMI

TRUE

SMC_RX_L

TRUE

LPCPLUS_GPIO

TRUE

ISSP_SCLK_P1_1

TRUE

ISSP_SDATA_P1_0

TRUE

SMC_ONOFF_L

TRUE

PM_SYSRST_L

TRUE

BKL_FB

TRUE

BKL_GD

TRUE

BKL_SW

TRUE

BKLT_EN

TRUE

BKL_SCL

TRUE

BKL_SDA

TRUE

LCD_BKLT_PWM

TRUE

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

17

17

17

17

17

17

17

17

69

49

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

21

42

20

20

20

9

9

9

9

13

13

7 8

7 8

42

49

49

49

49

49

49

49

49

49

49

49

49

49

49

49

49

49

49

49

49

49 30 90

49

49

49

49

49

49

40

40

40

40

40 42

47 96

47 96

67 82 84 21 33 36 41

45

42

96

96

50

4

40

25 43 91

19 41 43 84 91

43

43

19 41 43 84 91

19 41 43

41 42 43

25 43

41 42 43

41 43

41 43

39 41 42 43

43

43

43

19 41 43

19 41 43

41 42 43

41 42 43

41 42 43

41 43

39 41 42 43

18 43

49

49

41 42 49

25 41

85

84 85

TP_PCI_AD<31..8>
TP_PCI_C_BE_L<3..0>
TP_PCI_CLK0
TP_PCI_CLK1
TP_PCI_DEVSEL_L
TP_PCI_FRAME_L
TP_PCI_GNT0_L
TP_PCI_GNT1_L
TP_PCI_INTW_L
TP_PCI_INTX_L
TP_PCI_INTY_L
TP_PCI_INTZ_L
TP_PCI_IRDY_L
TP_PCI_PAR
TP_PCI_PERR_L
TP_PCI_RESET1_L
TP_PCI_SERR_L
TP_PCI_STOP_L
TP_PCI_TRDY_L
TP_PCIE_CLK100M_PE4P
TP_PCIE_CLK100M_PE5N
TP_PCIE_CLK100M_PE5P
TP_PCIE_CLK100M_PE6N
TP_PCIE_CLK100M_PE6P
TP_PCIE_PE4_D2RN
TP_PCIE_PE4_D2RP
TP_PE4_CLKREQ_L
TP_PEX_CLKREQ_L
TP_PSOC_P1_3
TP_SATA_C_D2RN
TP_SATA_C_D2RP
TP_SATA_C_R2D_CN
TP_SATA_C_R2D_CP
TP_SATA_D_D2RN
TP_SATA_D_D2RP
TP_SATA_D_R2D_CN
TP_SATA_D_R2D_CP
TP_SATA_E_D2RN
TP_SATA_E_D2RP
TP_SATA_E_R2D_CN
TP_SATA_E_R2D_CP
TP_SATA_F_D2RN
TP_SATA_F_D2RP
TP_SATA_F_R2D_CN
TP_SATA_F_R2D_CP
TP_SB_A20GATE
TP_SMC_P41
TP_USB_10P
TP_USB_11N
TP_USB_11P
TP_USB_EXTDN
TP_USB_EXTDP
TP_USB_MININ

TP_USB_MINIP
TP_XDP_OBSDATA_B2
TP_XDP_OBSDATA_B3

ICT Test Points

CPU FSB NO_TESTs

I1281

I1280

I1282

I1283

I1284

I1285

I982

I981

I1274

I1275

I1276

I1277

NO_TEST

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

FB NO_TESTs

NO_TEST

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

LVDS NO_TESTs

NO_TEST

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

NC NO_TESTs

NO_TEST

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

FSB_A_L<31..3>
FSB_ADS_L
FSB_ADSTB_L<1..0>
FSB_D_L<63..0>
FSB_DBSY_L
FSB_DINV_L<3..0>
FSB_DRDY_L
FSB_DSTB_L_N<3..0>
FSB_DSTB_L_P<3..0>
FSB_HIT_L
FSB_HITM_L
FSB_LOCK_L
FSB_REQ_L<4..0>

FB_A_DQ<63..0>
FB_B_DQ<63..0>
FB_B_BA<1>
FB_B_CAS_L
FB_B_CS0_L
FB_B_MA<11>

LVDS_A_DATA_N<0>
LVDS_A_DATA_P<0>
LVDS_B_CLK_P
LVDS_B_DATA_N<0>
LVDS_B_DATA_P<0>
LVDS_EG_A_DATA_N<2>

NC_PCI_AD<31..8>
NC_PCI_C_BE_L<3..0>
NC_PCI_CLK0
NC_PCI_CLK1
NC_PCI_DEVSEL_L
NC_PCI_FRAME_L
NC_PCI_GNT0_L
NC_PCI_GNT1_L
NC_PCI_INTW_L
NC_PCI_INTX_L
NC_PCI_INTY_L
NC_PCI_INTZ_L
NC_PCI_IRDY_L
NC_PCI_PAR
NC_PCI_PERR_L
NC_PCI_RESET1_L
NC_PCI_SERR_L
NC_PCI_STOP_L
NC_PCI_TRDY_L
NC_PCIE_CLK100M_PE4P
NC_PCIE_CLK100M_PE5N
NC_PCIE_CLK100M_PE5P
NC_PCIE_CLK100M_PE6N
NC_PCIE_CLK100M_PE6P
NC_PCIE_PE4_D2RN
NC_PCIE_PE4_D2RP
NC_PE4_CLKREQ_L
NC_PEX_CLKREQ_L
NC_PSOC_P1_3
NC_SATA_C_D2RN
NC_SATA_C_D2RP
NC_SATA_C_R2D_CN
NC_SATA_C_R2D_CP
NC_SATA_D_D2RN
NC_SATA_D_D2RP
NC_SATA_D_R2D_CN
NC_SATA_D_R2D_CP
NC_SATA_E_D2RN
NC_SATA_E_D2RP
NC_SATA_E_R2D_CN
NC_SATA_E_R2D_CP
NC_SATA_F_D2RN
NC_SATA_F_D2RP
NC_SATA_F_R2D_CN
NC_SATA_F_R2D_CP
NC_SB_A20GATE
NC_SMC_P41
NC_USB_10P
NC_USB_11N
NC_USB_11P
NC_USB_EXTDN
NC_USB_EXTDP
NC_USB_MININ

NC_USB_MINIP
NC_XDP_OBSDATA_B2
NC_XDP_OBSDATA_B3

3

10 14 88

10 14 88

10 14 88

10 14 88

10 14 88

10 14 88

10 14 88

10 14 88

10 14 88

10 14 88

10 14 88

10 14 88

10 14 88

71 72 79 95

71 73 80 95

71 73 80 95

71 73 80 95

71 73 95

71 73 80 95

81 84 95

81 84 95

81 84 95

81 84 95

81 84 95

76 84 95

NC NO_TESTs

I1297

I761

I762

I763

I764

I765

I767

I766

I769

I768

I770

I772

I771

I774

NO_TEST

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

NC_SMC_FAN_3_TACH
NC_SMC_FAN_3_CTL
NC_SMC_FAN_2_TACH
NC_SMC_FAN_2_CTL
NC_FW2_TPBP
NC_FW2_TPBN
NC_FW2_TPBIAS
NC_FW2_TPAP
NC_FW2_TPAN
NC_FW0_TPBP
NC_FW0_TPBN
NC_FW0_TPAP
NC_ESTARLDO_EN
NC_ALS_GAIN

NC NO_TESTs

TP_CPU_PECI_MCP

9

TP_CPU_TEST3

10

TP_ENET_INTR_L

18

TP_ENET_PWRDWN_L

18

TP_FW643_AVREG

35

TP_FW643_TDI

35

TP_MEM_A_A<15>

9

TP_MEM_A_CKE<2>

16

TP_MEM_A_CKE<3>

16

TP_MEM_A_CLK2N

15

15

TP_MEM_A_CLK3N

16

TP_MEM_A_CLK3P

16

TP_MEM_A_CLK4N

16

TP_MEM_A_CLK4P

16

TP_MEM_A_CLK5N

16

TP_MEM_A_CLK5P

16

TP_MEM_A_CS_L<2>

16

TP_MEM_A_CS_L<3>

16

TP_MEM_A_ODT<2>

16

TP_MEM_A_ODT<3>

16

TP_MEM_B_A<15>

9

TP_MEM_B_CKE<2>

16

TP_MEM_B_CLK2P

15

TP_MEM_B_CLK3N

16

TP_MEM_B_CLK3P

16

TP_MEM_B_CLK4N

16

TP_MEM_B_CLK4P

16

TP_MEM_B_CLK5N

16

TP_MEM_B_CLK5P

16

TP_MEM_B_CS_L<2>

16

TP_MEM_B_CS_L<3>

16

TP_MEM_B_ODT<2>

16

TP_MEM_B_ODT<3>

16

TP_MLB_RAM_SIZE

21

TP_MLB_RAM_VENDOR

21

TP_GPU_BUFRST_L

74

TP_GPU_GSTATE<0>

75

TP_GPU_GSTATE<1>

75

TP_GPU_MIOA_D<9..0>

75

TP_GPU_MIOA_DE

75

TP_GPU_PGOOD_OUT_L NC_GPU_PGOOD_OUT_L

74

TP_GPU_VCORE_VID3

75

TP_LPC_DRQ0_L

19

TP_LVDS_EG_B_CLK_N

75

TP_LVDS_EG_B_CLK_P

75

TP_LVDS_EG_BKL_PWM

75

TP_LVDS_IG_B_CLKN

9

TP_LVDS_IG_B_CLKP

9

TP_LVDS_IG_BKL_PWM

9

TP_MCP_BUF_SIO_CLK

21

TP_MCP_GPIO_18

17

TP_MCP_KBDRSTIN_L

21

TP_MCP_SATALED_L NC_MCP_SATALED_L

20

21

D

42

42

42

42

37

37

37

37

37

37

37

37

42

42

NO_TEST

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

SYNC_MASTER=K20_MLB

APPLE INC.

NC_CPU_PECI_MCP
NC_CPU_TEST3
NC_ENET_INTR_L
NC_ENET_PWRDWN_L
NC_FW643_AVREG
NC_FW643_TDI
NC_MEM_A_A<15>
NC_MEM_A_CKE<2>
NC_MEM_A_CKE<3>
NC_MEM_A_CLK2N
NC_MEM_A_CLK2PTP_MEM_A_CLK2P
NC_MEM_A_CLK3N
NC_MEM_A_CLK3P
NC_MEM_A_CLK4N
NC_MEM_A_CLK4P
NC_MEM_A_CLK5N
NC_MEM_A_CLK5P
NC_MEM_A_CS_L<2>
NC_MEM_A_CS_L<3>
NC_MEM_A_ODT<2>
NC_MEM_A_ODT<3>
NC_MEM_B_A<15>
NC_MEM_B_CKE<2>
NC_MEM_B_CLK2P
NC_MEM_B_CLK3N
NC_MEM_B_CLK3P
NC_MEM_B_CLK4N
NC_MEM_B_CLK4P
NC_MEM_B_CLK5N
NC_MEM_B_CLK5P
NC_MEM_B_CS_L<2>
NC_MEM_B_CS_L<3>
NC_MEM_B_ODT<2>
NC_MEM_B_ODT<3>
NC_MLB_RAM_SIZE
NC_MLB_RAM_VENDOR
NC_GPU_BUFRST_L
NC_GPU_GSTATE<0>
NC_GPU_GSTATE<1>
NC_GPU_MIOA_D<9..0>
NC_GPU_MIOA_DE

NC_GPU_VCORE_VID3
NC_LPC_DRQ0_L
NC_LVDS_EG_B_CLK_N
NC_LVDS_EG_B_CLK_P
NC_LVDS_EG_BKL_PWM
NC_LVDS_IG_B_CLKN
NC_LVDS_IG_B_CLKP
NC_LVDS_IG_BKL_PWM
NC_MCP_BUF_SIO_CLK
NC_MCP_GPIO_18
NC_MCP_KBDRSTIN_L

Functional / ICT Test

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

SHT

051-8071

7

SYNC_DATE=09/24/2008

REV.

B

OF

98

C

B

A

8

76

5

4

3

2

1

87

www.vinafix.vn

=PPBUS_G3H

60

D

=PPVIN_S5_CPU_IMVP_ISNS

45

=PP18V5_DCIN_CONN

59

=PP3V42_G3H_REG

59

C

=PP5V_S3_REG

62

B

=PP5V_S0_REG

64

=PPVCORE_S0_CPU_REG

61

A

=PPMCPCORE_S0_REG

64 87

"G3Hot" (Always-Present) Rails

PPBUS_G3H

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=6V
MAKE_BASE=TRUE

=PPVIN_S5_P5VP3V3

=PPVIN_S0_CPUVTTS0

=PPBUS_S0_LCDBKLT

=PPVIN_GPU_GPUVCORE

=PPVIN_S5_CPU_IMVP_ISNS_R
=PPVIN_S0_P5VRTS0_MCPCORE

=PPVIN_S3_DDRREG

=PPVIN_S0GPU_P1V8P1V1

=PPVBAT_G3H_P3V42G3H
=PPVIN_S0_P1V05S5
=PPVIN_PBUS_KBDLED

=PPVIN_S5_FWPWRSW

=PPVIN_S5_BKL

PPBUS_CPU_IMVP_ISNS

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=6V
MAKE_BASE=TRUE

=PPVIN_S5_CPU_IMVP

PPDCIN_G3H

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=18.5V
MAKE_BASE=TRUE

=PPDCIN_S5_CHGR

PP3V42_G3H

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.42V
MAKE_BASE=TRUE

=PP3V42_G3H_SMCUSBMUX
=PP3V42_G3H_SMBUS_SMC_BSA
=PP3V42_G3H_LIDSWITCH
=PP3V3_S5_SMC
=PP3V3_S5_LPCPLUS
=PPVIN_S5_SMCVREF
=PP3V42_G3H_PWRCTL

=PP3V42_G3H_CHGR

=PP3V3_S5_RTC_D

=PP3V42_G3H_BATT

=PP3V42_G3H_TPAD
=PP3V42_G3H_BMON_ISNS

=PP3V42_G3H_CPUCOREISNS

5V Rails

PP5V_S3

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V
MAKE_BASE=TRUE

=PP5V_S3_SYSLED

=PP5V_S3_BTCAMERA

=PP5V_S3_WLAN
=PP5V_S3_IR

=PP5V_S3_DDRREG

=PP5V_S3_GPUVCORE
=PP5V_S3_RTUSB

=PP5V_S3_TPAD

=PP5V_S3_P1V05S0FET

=PP5V_S3_MCPDDRFET
=PP5V_S3_VTTCLAMP

=PP5V_S3_AUDIO_PWR

PP5V_S0

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=5V
MAKE_BASE=TRUE

=PP5V_S0_FAN_LT
=PP5V_S0_FAN_RT
=PP5V_S0_CPU_IMVP

=PP5V_S0_CPUVTTS0

=PP5V_S0GPU_P1V1P1V8_GPU
=PP5V_S0_LPCPLUS
=PP5V_S0_ODD

=PP5V_S0_HDD

=PPVIN_PP5V_KBDLED

Chipset "VCore" Rails

PPVCORE_S0_CPU

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=1.25V
MAKE_BASE=TRUE

=PPVCORE_S0_CPU

PPVCORE_S0_MCP

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE

=PPVCORE_S0_MCP

11 12 45

22 23 45

7

45

62

65

86

77

45

64

63

83

59

66

9

36

7

61

7

60

7

39

44

40

41 42 51

43

42

67

60

25

59

49

45

45

7

42

30

30

40

63

77

39 98

50

68

68

68

9

7

7

48

61

65

83

43

38

38

9

7

7

42

48

=PP3V3_S5_REG

62

=PP3V3_S3_FET

68

=PP3V3_S0_FET

68

=PP2V5_S0_REG

87

=PP1V2_S0_REG

6

3.3V-2.5V Rails

PP3V3_S5

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
MAKE_BASE=TRUE

=PP3V3_S5_ROM
=PP3V3_S5_MEMRESET
=PP3V3_S3_P3V3S3FET
=PP3V3_S0_LCD
=PP3V3_S0_P3V3S0FET
=PP3V3_GPU_P3V3GPUFET
=PP3V3_S5_PWRCTL

=PP3V3_S5_P1V05FET

=PP3V3_S5_MCP

=PP3V3_S5_MCP_GPIO

=PP3V3_FW_LATEVG_ACTIVE

=PP3V3_S5_MCPPWRGD

=PP3V3_FW_LATEVG
=PP3V3_S5_P1V05ENETFET
=PP3V3_S5_P3V3ENETFET
=PP3V3_S5_DP_PORT_PWR

PP3V3_S3

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V
MAKE_BASE=TRUE

=PP3V3_S3_GMUX
=PP3V3_S3_BT

=PP3V3_S3_P1V8S0
=PP3V3_S3_SMBUS_SMC_A_S3
=PP3V3_S3_SMS

=PP3V3_S3_TPAD

=PP3V3_S3_SMS

=PP3V3_S3_WLAN
=PP3V3_S3_MCP_GPIO

=PP3V3_S3_VREFMRGN

=PP3V3_S3_SMBUS_SMC_MGMT

=PP3V3_S3_EXCARD

=PP3V3_S3_P1V5EXPS0

PP3V3_S0

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V
MAKE_BASE=TRUE

=PP3V3_S0_LPCPLUS
=PP3V3_S0_SMC
=PP3V3_S0_SMBUS_SMC_B_S0

=PP3V3_S0_MCPDDRISNS

=PP3V3_S0_GPU1V8ISNS
=PP3V3_S0_CPUTHMSNS
=PP3V3_S0_GPUTHMSNS
=PP3V3_S0_FAN_LT
=PP3V3_S0_FAN_RT
=PP3V3_S0_IMVP
=PP3V3_S0_PWRCTL
=PP3V3_S0_DDC_LCD
=PP3V3_S0_XDP

=PP3V3_S0_MCPCOREISNS

=PP3V3_S0_XDP

=PPSPD_S0_MEM_A

=PPSPD_S0_MEM_B

=PP3V3_S0_SMBUS_MCP_0

=PP3V3_S0_GMUX

=PP3V3_S0_DPMUX

=PP3V3_S0_DPCONN

=PP3V3_S0_P1V2P2V5

=PP3V3_S0_MCP_GPIO

=PP3V3_S0_HDCPROM

=PP3V3R1V5_S0_MCP_HDA

=PP3V3_S0_MCP_PLL_UF

=PP3V3_S0_MCP_VPLL_UF

=PP3V3_S0_MCP_DAC_UF

=PP3V3_S0_MCP

=PP3V3_S0_AUDIO

=PP3V3_S0_ODD

=PP3V3_S0_VMON

=PP3V3_S0_SMBUS_MCP_1

=PP3V3_S0_REMTHMSNS
=PP3V3_S0_EXCARD
=PP3V3_S0_LVDSDDCMUX

=PP3V3_S0_BATTCHARGERTMPSNSR

=PP3V3_GPU_SMBUS_SMC_0_S0

=PP3V3_S0_TPAD
=PP3V3_S0_MCP_PLL_VLDO

=PP3V3_FW_FWPHY

=PP3V3_FW_P1V0FW

PP2V5_S0

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=2.5V
MAKE_BASE=TRUE

=PP2V5_S0_GMUX

PP1V2_S0

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.2V
MAKE_BASE=TRUE

=PP1V2_S0_GMUX

5

=PP1V8_S0_REG

66

7

96

500 mA max supply

43 52

29

68

=PPDDR_S3_REG

78

63

68

68

67

68

22 23

18 20

36

25

=PP1V8R1V5_S0_FET

68

37

33

33

82

7

84

30

66

44

8

51

49

8

51

30

21

26

44

31

66

7 9

96

43

42

44

46

46

47

47

48

48

61

67

7

75 78

6 8

13

46

6 8

13

27

28

44

84

81

82

87

18 19 21

24

21 23

23

24

24

21 22 23

53 57 58

38

67

44

47

31

81

47

44

50

66

35 37

66

7

84

7

84

=PP1V5_EXP_S0

38 66

=PP1V8R1V5_S0_MCP_MEM

16 23

=PP1V05_S0_FET

66 68

1034 mA

PP1V05_S0_MCP_PLL_UF

MAKE_BASE=TRUE

=PP1V05_S0_MCP_PEX_DVDD

8

23

PP1V05_S0_MCP_PEX_AVDD

23

=PP1V05_S0_MCP_SATA_DVDD

8

23

PP1V05_S0_MCP_SATA_AVDD

MAKE_BASE=TRUE

=PP1V05_S5_MCP

66

241 mA max load

=PPCPUVTT_S0_REG

65

5300 mA

=PPVTT_S3_DDR_BUF

26 63

=PPVTT_S0_DDR_LDO

63

=PP1V05_ENET_FET

33

=PP3V3_ENET_FET

33

MAKE_BASE=TRUE

4

1.8V/DDR 1.5V Rails

190 mA

4771 mA

130 mA

500 mA

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

105 mA/241 mA

139 mA/ 0 mA

4500 mA

1182 mA

ENET Rails

PP3V3_ENET_PHY

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
MAKE_BASE=TRUE

PP1V8_S0

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.8V
MAKE_BASE=TRUE

=PP3V3R1V8_S0_MCP_IFP_VDD

=PP1V8_S0_MCP_PLL_VLDO

PP1V8R1V5_S3

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.5V
MAKE_BASE=TRUE

=PP1V8R1V5_S0_MCP_FET

=PPVIN_S0_DDRREG_LDO

=PP1V5_S3_MEM_A

=PP1V5_S3_MEM_B

=PP1V5_S3_MEMRESET

PP1V8R1V5_S0

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.5V
MAKE_BASE=TRUE

=PPMCPDDR_ISNS_R

=PP1V5_S0_CPU

=PP1V5_S0_VMON

PP1V5_EXP_S0

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.5V
MAKE_BASE=TRUE

=PP1V5_S0_EXCARD

PPMCPDDR_ISNS

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.5V
MAKE_BASE=TRUE

=PP1V5_S0_MEM_A

=PP1V5_S0_MEM_B

=PPMCPDDR_ISNS

PP1V05_S0

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE

=PP1V05_S0_MCP_AVDD_UF

=PP1V05_S0_MCP_PEX_DVDD

=PP1V05_S0_MCP_SATA_DVDD

=PP1V05_S0_MCP_HDMI_VDD

=PP1V05_S0_VMON

=PP1V05_S0_MCP_PLL_PEX_UF

=PP1V05_S0_MCP_PLL_UF

=PP1V05_S0_MCP_PEX_DVDD0

=PP1V05_S0_MCP_PEX_DVDD1

=PP1V05_S0_MCP_PEX_AVDD0

=PP1V05_S0_MCP_PEX_AVDD1

=PP1V05_S0_MCP_SATA_DVDD0

=PP1V05_S0_MCP_SATA_AVDD0

PP1V2R1V05_S5

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE

=PP1V05_S5_MCP_VDD_AUXC

=PP1V05_ENET_P1V05ENETFET

=PP1V05_S5_P1V05S0FET

PPCPUVTT_S0

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE

=PP1V05_S0_CPU

=PP1V05_S0_SMC_LS

=PP1V05_S0_MCP_FSB

PPVTTDDR_S3

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0.75V
MAKE_BASE=TRUE

PP0V9R0V75_S0_DDRVTT

MIN_LINE_WIDTH=2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.9V
MAKE_BASE=TRUE

=PP0V75_S0_MEM_VTT_A

=PP0V75_S0_MEM_VTT_B

=PPVTT_S0_VTTCLAMP

PP1V2R1V05_ENET

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE

=PP1V05_ENET_MCP_PLL_MAC

=PP1V05_ENET_MCP_RMGT
=PP1V05_ENET_PHY

=PP3V3_ENET_MCP_RMGT

=PP3V3_ENET_PHY

OR 0.75V

(1.1V for A01)

3

7

18 24

66

7

7

18 23

32

7

27

28

68

23

18 23

32

7

68

63

27

28

29

7

46

11 12

67

7

31

7

27

28

46

7

23

8

23

8

23

18 24

67

23

23 66

17

17

17

17

20

20 23

7

22 23

33

68

7

6

10 11 12 13 61

42

9

14 22 23

=PPVOUT_FW_FWPWRSW

36

=PFWBOOST_REG

66

=PPBOOST_S5_FW_FET

36

=PP1V0_FW_REG

66

=PP3V3_S0GPU_FET

68

=PP1V1_S0GPU_REG

83

=PP1V8_GPUIFPX_REG

66

=PP1V8_S0GPU_ISNS

46

=PPVCORE_GPU_REG

45 77

=PP1V8_GPU_REG

83

21

"FW" (FireWire) Rails

PPBUS_FW_FWBOOST

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=6V
MAKE_BASE=TRUE

=PPVIN_PFWBOOST

PP10V_FW

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=10V
MAKE_BASE=TRUE

=PPBOOST_FW_FWPWRSW_F

PPVP_FW

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=10V
MAKE_BASE=TRUE

=PPVP_FW_PORT1
=PPVP_FW_PHY_CPS_FET

PP1V0_FW

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.0V
MAKE_BASE=TRUE

=PP1V0_FW_FWPHY

"GPU" Rails

PP3V3_S0GPU

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V
MAKE_BASE=TRUE

=PP3V3_GPU_VDD33
=PP3V3_GPU_MIO

=PP3V3_GPU_LVDS_DDC

=PP3V3_GPU_PWRCTL
=PP3V3_GPU_VCORELOGIC

=PP3V3_GPU_P1V8S0

PP1V1_S0GPU

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.1V
MAKE_BASE=TRUE

=PP1V1_GPU_PEX_IOVDDQ

=PP1V1_GPU_PEX_IOVDD

=PP1V1_GPU_PEX_PLLXVDD

=PP1V1_GPU_PLLVDD

=PP1V1_GPU_H_PLLVDD

=PP1V1_GPU_VID_PLLVDD

=PP1V1_GPU_FBPLLAVDD

=PP1V1_GPU_IFPCD_IOVDD

PP1V8_GPUIFPX

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.15 MM
VOLTAGE=1.8V
MAKE_BASE=TRUE

=PP1V8_GPU_IFPX

PP1V8_S0GPU_ISNS

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.8V
MAKE_BASE=TRUE

=PP1V8_GPU_FB_VDD
=PP1V8_GPU_FB_VDDQ
=PP1V8_GPU_FBVDDQ
=PP1V8_GPU_FBIO

PPVCORE_GPU

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.2V
MAKE_BASE=TRUE

=PPVCORE_GPU

PP1V8_S0GPU_ISNS_R

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.25V
MAKE_BASE=TRUE

=PP1V8_S0GPU_ISNS_R

Power Aliases

SYNC_MASTER=RXU_K20

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

D

NONE

DRAWING NUMBER

051-8071

SHT

66

36

7

37

37

7

35

7

6

74 75

74 75

81

67

77

66

7

69

69

69

74

74

74

71

76

7

76

7

72 73 79 80

9

72 73 79 80

70

71

7

70

7

46

SYNC_DATE=05/07/2008

OF

8

D

C

B

A

REV.

B

98

8

76

5

4

3

2

1

87

www.vinafix.vn

6

5

4

3

21

D

ZT0915

3R2P5

60 59

ZT0945

3R2P5

ZT0932

3R2P5

C

ZT0960

3R2P5

ZT0971

3R2P5

ZT0965

3R2P5

ZT0940

3R2P5

ZT0970

3R2P5

B

ZT0934

STDOFF-4.0OD3.0H-SM

STDOFF-4.5OD.98H-1.1-3.48-TH

STDOFF-4.5OD.98H-1.1-3.48-TH

A

STDOFF-4.5OD.98H-1.1-3.48-TH

STDOFF-4.5OD.98H-1.1-3.48-TH

Left CPU

TM Hole

Frame Holes

1

GND_BATT_CHGND

1

GND_CHASSIS_USB

1

GND_CHASSIS_RIGHTHS

1

GND_CHASSIS_SATA

1

GND_CHASSIS_TPAD

1

GND_CHASSIS_CLUTCH

1

GND_CHASSIS_LVDS

1

GND_CHASSIS_DIMM

STDOFF-4.0OD3.0H-SM

1

ZT0988

1

STDOFF-4.5OD.98H-1.1-3.48-TH

ZT0991

1

ZT0989

1

Thermal Module Holes

ZT0982

ZT0983

Right CPU

TM Hole

ZT0931

1

=PPVIN_PBUS_KBDLED

8

=PPVIN_PP5V_KBDLED

8

STDOFF-4.5OD.98H-1.1-3.48-TH

STDOFF-4.5OD.98H-1.1-3.48-TH

Bottom Left GPU

80 79 73 72

ZT0984

Top GPU Right

TM Hole

STDOFF-4.5OD.98H-1.1-3.48-TH

TM Hole

STDOFF-4.5OD.98H-1.1-3.48-TH

8

ZT0980

ZT0987

=PP1V8_GPU_FB_VDDQ

STDOFF-4.5OD.98H-1.1-3.48-TH

R0900

10

21

1%
1/16W
MF-LF

402

R0901

10

21

1%
1/16W
MF-LF

402

Extra FSB Pull-ups

Exist in MRB but not Intel designs. Here for CYA.

If found to be necessary, will move to page14.csa

=PP1V05_S0_MCP_FSB

23 22 14

8

NO STUFF

1

R0950

220

5%
1/16W
MF-LF
402

2

OUT

OUT

OUT

OUT

OUT

CPU_DPRSTP_L
FSB_BREQ0_L
FSB_CPURST_L
CPU_INTR
CPU_NMI

88 61 14 10

88 14 10

88 14 13 10

88 14 10

88 14 10

Bosses for Flex Protector Bracket

ZT0957

KBDLED_PBUS

R0998

0

5%
1/10W
MF-LF

603

KBDLED_5V

R0999

0

5%
1/10W
MF-LF

603

4.0OD1.65H-M1.6X0.35

4.0OD1.65H-M1.6X0.35

21

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=8.4V

MAKE_BASE=TRUE

21

1

ZT0958

1

PP5VR8V4_KBDLED

NO STUFF

NO STUFF

1

R0960

62

5%
1/16W
MF-LF
402

2

R0970

200

1/16W
MF-LF

=PPVIN_S0_KBDLED

ZT0981

STDOFF-4.5OD.98H-1.1-3.48-TH

ZT0985

ZT0986

STDOFF-4.5OD.98H-1.1-3.48-TH

ZT0930

GPU_FB_A_VREF_DIV

MAKE_BASE=TRUE

=PP1V8_GPU_FB_VREF_A

GPU_FB_B_VREF_DIV

MAKE_BASE=TRUE

=PP1V8_GPU_FB_VREF_B

1.4DIA-SHORT-EMI-MLB-M97-M98

1.4DIA-SHORT-EMI-MLB-M97-M98

NO STUFF

R0990

1/16W
MF-LF

150

1

1%

402

2

1

5%

402

2

NO STUFF

1

R0980

150

1%
1/16W
MF-LF
402

2

2.0DIA-TALL-EMI-MLB-M97-M98

2.0DIA-TALL-EMI-MLB-M97-M98

2.0DIA-TALL-EMI-MLB-M97-M98

2.0DIA-TALL-EMI-MLB-M97-M98

50

2.0DIA-TALL-EMI-MLB-M97-M98

2.0DIA-TALL-EMI-MLB-M97-M98

2.0DIA-TALL-EMI-MLB-M97-M98

1.4DIA-SHORT-EMI-MLB-M97-M98

26

1.4DIA-SHORT-EMI-MLB-M97-M98

72

26

73

SH0902

SM

SH0903

SM

SH0920

SH0910

1

1

SM

1

1.4DIA-SHORT-EMI-MLB-M97-M98

SM

1

SH0912

SM

1

SH0923

SM

1

2.0DIA-TALL-EMI-MLB-M97-M98

SH0916

SM

1

SH0918

SM

1

SH0930

SM

1

SH0931

SM

1

SH0932

SM

1

SH0933

SM

1

2.0DIA-TALL-EMI-MLB-M97-M98

SH0900

SM

1

2.0DIA-TALL-EMI-MLB-M97-M98

SH0901

SM

1

SH0911

SM

1

1.4DIA-SHORT-EMI-MLB-M97-M98

1.4DIA-SHORT-EMI-MLB-M97-M98

2.0DIA-TALL-EMI-MLB-M97-M98

2.0DIA-TALL-EMI-MLB-M97-M98

2.0DIA-TALL-EMI-MLB-M97-M98

2.0DIA-TALL-EMI-MLB-M97-M98

2.0DIA-TALL-EMI-MLB-M97-M98

2.0DIA-TALL-EMI-MLB-M97-M98

SH0913

SM

1

SH0914

SM

1

SH0924

SM

1

SH0917

SM

1

SH0919

SM

1

SH0921

SM

1

SH0922

SM

1

SH0934

SM

1

2.0DIA-TALL-EMI-MLB-M97-M98

SH0935

SM

1

CPU signals

GPU signals

VR_PWRGD_CLKEN_L

IMVP6_VID<0..6>

=MCP_BSEL<0..2>

=SPI_CS1_R_L_USE_MLB

=PEG_D2R_P<0..15>

=PEG_D2R_N<0..15>

=PEG_R2D_C_P<0..15>

=PEG_R2D_C_N<0..15>

LVDS_BKL_ON

=MCP_HDMI_TXC_P

=MCP_HDMI_TXC_N

=MCP_HDMI_TXD_P<0..2>

=MCP_HDMI_TXD_N<0..2>

=MCP_HDMI_DDC_CLK

=MCP_HDMI_DDC_DATA

=MCP_HDMI_HPD

ALL_EG_PGOOD

LVDS_MUX_SEL_EG

GPU_RESET_L

TP_IMVP6_CLKEN_L

MAKE_BASE=TRUE

CPU_VID<0..6>

88 11 88 61

MAKE_BASE=TRUE

CPU_BSEL<0..2>

88 10 14

MAKE_BASE=TRUE

MEM_VTT_EN =DDRVTT_EN

25 68 63

MAKE_BASE=TRUE

TP_SPI_CS1_R_L_USE_MLB

MAKE_BASE=TRUE

PEG_D2R_P<0..15>

MAKE_BASE=TRUE

PEG_D2R_N<0..15>

MAKE_BASE=TRUE

PEG_R2D_C_P<0..15>

90 69

MAKE_BASE=TRUE

PEG_R2D_C_N<0..15>

MAKE_BASE=TRUE

LCD_BKLT_EN

MAKE_BASE=TRUE

DP_IG_ML_P<3>

90 81

MAKE_BASE=TRUE

DP_IG_ML_N<3>

90 81

MAKE_BASE=TRUE

DP_IG_ML_P<2..0>

90 81

MAKE_BASE=TRUE

DP_IG_ML_N<2..0>

90 81

MAKE_BASE=TRUE

DP_IG_DDC_CLK

81 75

MAKE_BASE=TRUE

DP_IG_DDC_DATA

81 75

MAKE_BASE=TRUE

DP_IG_HPD

81

MAKE_BASE=TRUE

PM_ALL_GPU_PGOOD

67

MAKE_BASE=TRUE

TP_LVDS_MUX_SEL_EG

MAKE_BASE=TRUE

EG_RESET_L

84

MAKE_BASE=TRUE

JTAG_GMUX_TDI

84

6

MAKE_BASE=TRUE

84

6

MAKE_BASE=TRUE

JTAG_GMUX_TDO

84

6

MAKE_BASE=TRUE

GMUX_INT

84

MAKE_BASE=TRUE

LVDS_IG_BKL_ON

18

MAKE_BASE=TRUE

LVDS_IG_PANEL_PWR

18

MAKE_BASE=TRUE

GMUX ALIASES

=PP1V05_S0_MCP_SATA_DVDD1

=PP1V05_S0_MCP_SATA_AVDD1

=P1V5_EXP_S0_EN

66

MCP_MII_PD

MAKE_BASE=TRUE

1

R0930

47K

5%

Digital Ground

1/16W
MF-LF
402

2

GND

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V

PP3V3_S0

61

43 21

17 90 69

17 90 69

17

17 90 69

86 84

18

18

18

18

18

18

18

84

84

69

GMUX_JTAG_TDI

GMUX_JTAG_TMSJTAG_GMUX_TMS

GMUX_JTAG_TDO

=DVI_HPD_GMUX_INT

IG_BKLT_EN

IG_LCD_PWR_EN

20

20

8 7

=MCP_MII_RXER

=MCP_MII_CRS

=MCP_MII_COL

TP_USB_EXTDP

7

MAKE_BASE=TRUE

TP_USB_EXTDN

7

MAKE_BASE=TRUE

TP_USB_MINIP

7

MAKE_BASE=TRUE

TP_USB_MININ

7

MAKE_BASE=TRUE

TP_MEM_A_A<15>

7

MAKE_BASE=TRUE

TP_MEM_B_A<15>

7

MAKE_BASE=TRUE

TP_CPU_PECI_MCP

7

MAKE_BASE=TRUE

NC_LVDS_IG_A_DATAP<3>

MAKE_BASE=TRUE

NC_LVDS_IG_A_DATAN<3>

MAKE_BASE=TRUE

NC_LVDS_IG_B_DATAP<3>

MAKE_BASE=TRUE

NC_LVDS_IG_B_DATAN<3>

MAKE_BASE=TRUE

HDA_BITCLK

53

MAKE_BASE=TRUE

=PP5V_S3_AUDIO_PWR

8

19

19

17

18

84

84

MCP_SPKR

21

33

33

32

32

96

USB_EXTD_P

USB_EXTD_N

USB_MINI_P

USB_MINI_N

MEM_A_A<15>

MEM_B_A<15>

CPU_PECI_MCP

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

TP_LVDS_IG_B_CLKP

7

MAKE_BASE=TRUE

TP_LVDS_IG_B_CLKN

7

MAKE_BASE=TRUE

TP_LVDS_IG_BKL_PWM

7

MAKE_BASE=TRUE

LVDS_IG_A_DATA_P<3>

LVDS_IG_A_DATA_N<3>

LVDS_IG_B_DATA_P<3>

LVDS_IG_B_DATA_N<3>

LVDS_IG_B_CLK_P

LVDS_IG_B_CLK_N

LVDS_IG_BKL_PWM

AUDIO ALIASES

HDA_BIT_CLK

XW0900

SM

=P3V3ENET_EN

=P1V05ENET_EN

=PP3V3_ENET_PHY_VDDREG

=RTL8211_REGOUT

21

21

XW0901

R0902

R0903

1/16W
MF-LF

402

PP5V_S3_AUDIO

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V

SM

PP5V_S3_AUDIO_AMP

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V

10K

AUD_IPHS_SWITCH_EN

21

MAKE_BASE=TRUE

5%
1/16W
MF-LF

402

0

21

5%

SMC_MCP_SAFE_MODE

ETHERNET ALIASES

PM_SLP_RMGT_L

MAKE_BASE=TRUE

TP_PP3V3_ENET_PHY_VDDREG

MAKE_BASE=TRUE

NC_RTL8211_REGOUT

MAKE_BASE=TRUE

=RTL8211_ENSWREG

MCP79 PCIe PRSNT# Straps

R0925

0

21

18

18

18

5%
1/16W
MF-LF

402

R0927

0

5%
1/16W
MF-LF

402

PCIE_FW_PRSNT_L

MAKE_BASE=TRUE

NO STUFF

21

MAKE_BASE=TRUE

APPLE INC.

PEG_PRSNT_L

R0926

0

5%
1/16W
MF-LF

402

Signal Aliases

SYNC_MASTER=K20_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

21

SIZE

D

SCALE

17

OUT

17

OUT

EG_CLKREQ_OUT_L

DRAWING NUMBER

NONE

051-8071

SHT

27

28

18

56

84

IN

SYNC_DATE=09/24/2008

OF

9

91 20

91 20

91 20

91 20

D

14

90 18

90 18

90 18

90 18

90 18

90 18

91 21

55 53

58 19

41

21

C

32

B

A

REV.

B

98

8

76

5

4

3

2

1

87

www.vinafix.vn

6

5

4

3

21

OMIT

BPRI*

DEFER*

DRDY*
DBSY*

IERR*
INIT*

LOCK*

RESET*

TRDY*

HITM*

BPM0*
BPM1*
BPM2*
BPM3*
PRDY*
PREQ*

TRST*

THERMDA
THERMDC

BCLK0
BCLK1

54.9

1%
1/16W
MF-LF

402

54.9

1%
1/16W
MF-LF

402

54.9

1%
1/16W
MF-LF

402

ADS*
BNR*

BR0*

RS0*
RS1*
RS2*

HIT*

TCK
TDI
TDO
TMS

DBR*

21

21

21

H1

FSB_ADS_L

E2

FSB_BNR_L

G5

FSB_BPRI_L

H5

FSB_DEFER_L

F21

FSB_DRDY_L

E1

FSB_DBSY_L

F1

FSB_BREQ0_L

D20

CPU_IERR_L

88

B3

CPU_INIT_L

H4

FSB_LOCK_L

C1

FSB_CPURST_L

F3

FSB_RS_L<0>

F4

FSB_RS_L<1>

G3

FSB_RS_L<2>

G2

FSB_TRDY_L

G6

FSB_HIT_L

E4

FSB_HITM_L

AD4

XDP_BPM_L<0>

AD3

XDP_BPM_L<1>

AD1

XDP_BPM_L<2>

AC4

XDP_BPM_L<3>

AC2

XDP_BPM_L<4>

AC1

XDP_BPM_L<5>

AC5

XDP_TCK

AA6

XDP_TDI

AB3

XDP_TDO

AB5

XDP_TMS

AB6

XDP_TRST_L

C20

XDP_DBRESET_L

D21

CPU_PROCHOT_L

A24

CPU_THERMD_P

B25

CPU_THERMD_N

C7

PM_THRMTRIP_L

A22

FSB_CLK_CPU_P

A21

FSB_CLK_CPU_N

=PP1V05_S0_CPU

6 8

10 11 12 13 61

7

14 88

BI

14 88

BI

14 88

BI

14 88

BI

7

14 88

BI

7

14 88

BI

9

14 88

BI

14 88

IN

7

14 88

BI

9

13 14 88

IN

14 88

IN

14 88

IN

14 88

IN

14 88

IN

7

14 88

BI

7

14 88

BI

13 88

BI

13 88

BI

13 88

BI

13 88

BI

13 88

BI

6

10 13 88

IN

6

10 13 88

IN

6

10 88

OUT

6

10 13 88

IN

6

10 13 88

IN

13 25

OUT

47 96

OUT

47 96

OUT

14 42 88

OUT

14 88

IN

14 88

IN

PLACE C1000 CLOSE TO CPU_TEST4
PIN. MAKE SURE CPU_TEST4 IS
REFERENCED TO GND

1

R1002

54.9

1%
1/16W
MF-LF
402

2

R1003

PM_THRMTRIP#
SHOULD CONNECT TO ICH AND
GMCH WITHOUT T (NO STUB)

=PP1V05_S0_CPU

6 8

10 11 12 13 61

=PP1V05_S0_CPU

1

54.9

1%
1/16W
MF-LF

402

2

6 8

10 11 12 13 61

PLACE TESTPOINT ON
FSB_IERR_L WITH A GND

0.1" AWAY

=PP1V05_S0_CPU

13 88

BI

1

R1004

68

5%
1/16W
MF-LF
402

2

14 42 61 88

OUT

1

R1005

1K

1%
1/16W
MF-LF

402

2

0.5" MAX LENGTH FOR CPU_GTLREF

1

R1006

2.0K

1%
1/16W
MF-LF

402

NOSTUFF

2

1

C1000

0.1uF

10%
16V

2

X5R
402

6 8

10 11 12 13 61

D

OMIT

D32*
D33*
D34*
D35*
D36*
D37*
D38*
D39*
D40*
D41*
D42*
D43*
D44*
D45*
D46*

D47*
DSTBN2*
DSTBP2*

DINV2*

D48*

D49*

D50*

D51*

D52*

D53*

D54*

D55*

D56*

D57*

D58*

D59*

D60*

D61*

D62*

D63*
DSTBN3*
DSTBP3*

DINV3*

COMP0
COMP1
COMP2
COMP3

DPRSTP*

DPSLP*

DPWR*

PWRGOOD

SLP*

PSI*

Y22

AB24

V24

V26

V23

T22

U25

U23

Y25

W22

Y23

W24

W25

AA23

AA24

AB25

Y26

AA26

U22

AE24

AD24

AA21

AB22

AB21

AC26

AD20

AE22

AF23

AC25

AE21

AD21

AC22

AD23

AF22

AC23

AE25

AF24

AC20

R26

U26

AA1

Y1

E5

B5

D24

D6

D7

AE6

FSB_D_L<32>
FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>
FSB_D_L<36>
FSB_D_L<37>
FSB_D_L<38>
FSB_D_L<39>
FSB_D_L<40>
FSB_D_L<41>
FSB_D_L<42>
FSB_D_L<43>
FSB_D_L<44>
FSB_D_L<45>
FSB_D_L<46>
FSB_D_L<47>
FSB_DSTB_L_N<2>
FSB_DSTB_L_P<2>
FSB_DINV_L<2>

FSB_D_L<48>
FSB_D_L<49>
FSB_D_L<50>
FSB_D_L<51>
FSB_D_L<52>
FSB_D_L<53>
FSB_D_L<54>
FSB_D_L<55>
FSB_D_L<56>
FSB_D_L<57>
FSB_D_L<58>
FSB_D_L<59>
FSB_D_L<60>
FSB_D_L<61>
FSB_D_L<62>
FSB_D_L<63>
FSB_DSTB_L_N<3>
FSB_DSTB_L_P<3>
FSB_DINV_L<3>

CPU_COMP<0>

88

CPU_COMP<1>

88

CPU_COMP<2>

88

CPU_COMP<3>

88

CPU_DPRSTP_L
CPU_DPSLP_L
FSB_DPWR_L
CPU_PWRGD
FSB_CPUSLP_L
CPU_PSI_L

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

9

14 61 88

IN

14 88

IN

14 88

IN

13 14 88

IN

14 88

IN

61

OUT

APPLE INC.

LAYOUT NOTE:
COMP0,2 CONNECT WITH ZO=27.4OHM,
MAKE TRACE LENGTH SHORTER THAN 0.5".
COMP1,3 CONNECT WITH ZO=55OHM,
MAKE TRACE LENGTH SHORTER THAN 0.5".

R1017

54.9

21

1%
1/16W
MF-LF

402

R1019

54.9

21

1%
1/16W
MF-LF

402

CPU FSB

SYNC_MASTER=M98_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

R1016

27.4

1%
1/16W
MF-LF

402

R1018

27.4

1%
1/16W
MF-LF

402

051-8071

SHT

21

21

SYNC_DATE=04/01/2008

OF

10

C

B

A

REV.

B

98

AD26

AF26

E22

F24

E26

G22

F23

G25

E25

E23

K24

G24

J24

J23

H22

F26

K22

H23

J26

H26

H25

N22

K25

P26

R23

L23

M24

L22

M23

P25

P23

P22

T24

R24

L25

T25

N25

L26

M26

N24

C23

D25

C24

AF1

A26

B22

B23

C21

C3

D0*
D1*
D2*
D3*
D4*
D5*
D6*
D7*
D8*
D9*
D10*
D11*
D12*
D13*
D14*
D15*
DSTBN0*
DSTBP0*
DINV0*

D16*
D17*
D18*
D19*
D20*
D21*
D22*
D23*
D24*
D25*
D26*
D27*
D28*
D29*
D30*
D31*
DSTBN1*
DSTBP1*
DINV1*

GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
BSEL0
BSEL1
BSEL2

U1000

PENRYN

FCBGA

2 OF 4

DATA GRP 0DATA GRP 1

MISC

DATA GRP 3 DATA GRP 2

FSB_D_L<0>

7

14 88

BI

FSB_D_L<1>

7

14 88

BI

FSB_D_L<2>

7

14 88

BI

FSB_D_L<3>

7

14 88

BI

FSB_D_L<4>

7

14 88

BI

FSB_D_L<5>

7

14 88

BI

FSB_D_L<6>

7

14 88

BI

FSB_D_L<7>

7

14 88

BI

FSB_D_L<8>

7

14 88

BI

FSB_D_L<9>

7

14 88

BI

FSB_D_L<10>

7

14 88

BI

FSB_D_L<11>

7

14 88

BI

FSB_D_L<12>

7

14 88

BI

FSB_D_L<13>

7

14 88

BI

FSB_D_L<14>

7

14 88

BI

FSB_D_L<15>

7

14 88

BI

FSB_DSTB_L_N<0>

7

14 88

BI

FSB_DSTB_L_P<0>

7

14 88

BI

FSB_DINV_L<0>

7

14 88

BI

FSB_D_L<16>

7

14 88

BI

FSB_D_L<17>

7

14 88

BI

FSB_D_L<18>

7

14 88

BI

FSB_D_L<19>

7

14 88

BI

FSB_D_L<20>

7

14 88

BI

FSB_D_L<21>

7

14 88

BI

FSB_D_L<22>

7

14 88

BI

FSB_D_L<23>

7

14 88

BI

FSB_D_L<24>

7

14 88

BI

FSB_D_L<25>

7

14 88

BI

FSB_D_L<26>

7

14 88

BI

FSB_D_L<27>

7

14 88

BI

FSB_D_L<28>

7

14 88

BI

FSB_D_L<29>

7

14 88

BI

FSB_D_L<30>

7

14 88

BI

FSB_D_L<31>

7

14 88

BI

FSB_DSTB_L_N<1>

7

14 88

BI

FSB_DSTB_L_P<1>

7

14 88

BI

FSB_DINV_L<1>

7

14 88

BI

CPU_GTLREF

26 88

CPU_TEST1
CPU_TEST2

TP_CPU_TEST3

7

CPU_TEST4
TP_CPU_TEST5
TP_CPU_TEST6
TP_CPU_TEST7

CPU_BSEL<0>

9

88

OUT

CPU_BSEL<1>

9

88

OUT

CPU_BSEL<2>

9

88

OUT

NOSTUFF

R1030

0

21

NOSTUFF

R1012

1/16W
MF-LF

1K

402

5%

1/16W

1

MF-LF

5%

2

NOSTUFF

1

402

R1007

1K

5%
1/16W
MF-LF
402

2

AA4

AB2

AA3

D22

J4

L5

L4

K5

M3

N2

J1

N3

P5

P2

L2

P4

P1

R1

M1

K3

H2

K2

J3

L1

Y2

U5

R3

W6

U4

Y5

U1

R4

T5

T3

W2

W5

Y4

U2

V4

W3

V1

A6

A5

C4

D5

C6

B4

A3

M4

N5

T2

V3

B2

F6

D2

D3

A3*
A4*
A5*
A6*
A7*
A8*
A9*
A10*
A11*
A12*
A13*
A14*
A15*
A16*
ADSTB0*

REQ0*
REQ1*
REQ2*
REQ3*
REQ4*

A17*
A18*
A19*
A20*
A21*
A22*
A23*
A24*
A25*
A26*
A27*
A28*
A29*
A30*
A31*
A32*
A33*
A34*
A35*
ADSTB1*

A20M*
FERR*
IGNNE*

STPCLK*
LINT0
LINT1
SMI*

RSVD0
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8

U1000

PENRYN

FCBGA

1 OF 4

ADDR GROUP0

ADDR GROUP1

THERMAL

THERMTRIP*

ICH

RESERVED

CONTROL

XDP/ITP SIGNALS

PROCHOT*

H CLK

FSB_A_L<3>

7

14 88

BI

FSB_A_L<4>

7

14 88

BI

FSB_A_L<5>

7

14 88

BI

FSB_A_L<6>

7

14 88

BI

FSB_A_L<7>

7

14 88

BI

FSB_A_L<8>

7

14 88

BI

FSB_A_L<9>

7

14 88

BI

FSB_A_L<10>

7

14 88

BI

FSB_A_L<11>

7

14 88

BI

FSB_A_L<12>

7

14 88

D

C

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

14 88

14 88

14 88

14 88

7

14 88

14 88

14 88

14 88

14 88

9

14 88

9

14 88

14 88

BI

FSB_A_L<13>

BI

FSB_A_L<14>

BI

FSB_A_L<15>

BI

FSB_A_L<16>

BI

FSB_ADSTB_L<0>

BI

FSB_REQ_L<0>

BI

FSB_REQ_L<1>

BI

FSB_REQ_L<2>

BI

FSB_REQ_L<3>

BI

FSB_REQ_L<4>

BI

FSB_A_L<17>

BI

FSB_A_L<18>

BI

FSB_A_L<19>

BI

FSB_A_L<20>

BI

FSB_A_L<21>

BI

FSB_A_L<22>

BI

FSB_A_L<23>

BI

FSB_A_L<24>

BI

FSB_A_L<25>

BI

FSB_A_L<26>

BI

FSB_A_L<27>

BI

FSB_A_L<28>

BI

FSB_A_L<29>

BI

FSB_A_L<30>

BI

FSB_A_L<31>

BI

FSB_A_L<32>

BI

FSB_A_L<33>

BI

FSB_A_L<34>

BI

FSB_A_L<35>

BI

FSB_ADSTB_L<1>

BI

CPU_A20M_L

IN

CPU_FERR_L

OUT

CPU_IGNNE_L

IN

CPU_STPCLK_L

IN

CPU_INTR

IN

CPU_NMI

IN

CPU_SMI_L

IN

TP_CPU_RSVD0
TP_CPU_RSVD1
TP_CPU_RSVD2
TP_CPU_RSVD3
TP_CPU_RSVD4
TP_CPU_RSVD5
TP_CPU_RSVD6
TP_CPU_RSVD7
TP_CPU_RSVD8

B

XDP_TMS

6

10 13 88

R1021

XDP_TDI

6

10 13 88

XDP_TDO

6

PLACEMENT_NOTE=Place R1024 near ITP connector (if present)

10 88

10 13 88

10 13 88

XDP_TCK

6

XDP_TRST_L

6

54.9

1%
1/16W
MF-LF

402

R1023

649

1%
1/16W
MF-LF

402

R1020

21

R1024

R1022

21

A

8

76

5

4

3

2

1

87

www.vinafix.vn

6

5

4

3

21

(CPU CORE POWER)

=PPVCORE_S0_CPU

Standard Voltage:

44.0 A (Design Target)

41.0 A (HFM)

30.4 A (LFM)

25.5 A (SuperLFM)

27.4 A (Auto-Halt/Stop-Grant HFM)

17.0 A (Auto-Halt/Stop-Grant SuperLFM)

27.4 A (Sleep HFM)

16.8 A (Sleep SuperLFM)

25.0 A (Deep Sleep HFM)

16.0 A (Deep Sleep SuperLFM)

11.5 A (Deeper Sleep)

9.4 A (Enhanced Deeper Sleep)

(CPU IO POWER 1.05V)

=PP1V05_S0_CPU

(CPU INTERNAL PLL POWER 1.5V)

=PP1V5_S0_CPU

CPU_VID<0>
CPU_VID<1>
CPU_VID<2>
CPU_VID<3>
CPU_VID<4>
CPU_VID<5>
CPU_VID<6>

CPU_VCCSENSE_P

CPU_VCCSENSE_N

VCC

VCCP

VCCA

VID0
VID1
VID2
VID3
VID4
VID5
VID6

VCCSENSE

VSSSENSE

AB20

AB7

AC7

AC9

AC12

AC13

AC15

AC17

AC18

AD7

AD9

AD10

AD12

AD14

AD15

AD17

AD18

AE9

AE10

AE12

AE13

AE15

AE17

AE18

AE20

AF9

AF10

AF12

AF14

AF15

AF17

AF18

AF20

G21

V6

J6

K6

M6

J21

K21

M21

N21

N6

R21

R6

T21

T6

V21

W21

B26

C26

AD6

AF5

AE5

AF4

AE3

AF3

AE2

AF7

AE7

D

C

B

AA10

AA12

AA13

AA15

AA17

AA18

AA20

AC10

AB10

AB12

AB14

AB15

AB17

AB18

A7

A9

A10

A12

A13

A15

A17

A18

A20

B7

B9

B10

B12

B14

B15

B17

B18

B20

C9

C10

C12

C13

C15

C17

C18

D9

D10

D12

D14

D15

VCC

D17

D18

E7

E9

E10

E12

E13

E15

E17

E18

E20

F7

F9

F10

F12

F14

F15

F17

F18

F20

AA7

AA9

AB9

OMIT

U1000

PENRYN

FCBGA

3 OF 4

A

Current numbers from Merom for Santa Rosa EMTS, doc #22221.

8

76

8

11 12 45

6 8

10 12 13 61

4500 mA (before VCC stable)
2500 mA (after VCC stable)

8

12

130 mA

9

88

OUT

9

88

OUT

9

88

OUT

9

88

OUT

9

88

OUT

9

88

OUT

9

88

OUT

Low Voltage:

23.0 A (Design Target)

21.0 A (HFM)

18.7 A (LFM)
TBD A (SuperLFM)

TBD A (Auto-Halt/Stop-Grant HFM)
TBD A (Auto-Halt/Stop-Grant SuperLFM)

TBD A (Sleep HFM)
TBD A (Sleep SuperLFM)

TBD A (Deep Sleep HFM)
TBD A (Deep Sleep SuperLFM)

TBD A (Deeper Sleep)

TBD A (Enhanced Deeper Sleep)

=PPVCORE_S0_CPU

1

R1100

100

1%
1/16W
MF-LF
402

2

PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.

61 88

OUT

61 88

OUT

1

R1101

100

1%
1/16W
MF-LF
402

2

PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.

8

11 12 45

Ultra Low Voltage:

17.0 A (Design Target)

TBD A (HFM)
TBD A (LFM)

TBD A (Auto-Halt/Stop-Grant HFM)
TBD A (Auto-Halt/Stop-Grant LFM)

TBD A (Sleep HFM)
TBD A (Sleep LFM)

TBD A (Deep Sleep HFM)
TBD A (Deep Sleep LFM)

TBD A (Deeper Sleep)

TBD A (Enhanced Deeper Sleep)

A4

A8

A11

A14

A16

A19

A23

AF2

B6

B8

B11

B13

B16

B19

B21

B24

C5

C8

C11

C14

C16

C19

C2

C22

C25

D1

D4

D8

D11

D13

D16

D19

D23

D26

E3

E6

E8

E11

E14

VSS VSS

E16

E19

E21

E24

F5

F8

F11

F13

F16

F19

F2

F22

F25

G4

G1

G23

G26

H3

H6

H21

H24

J2

J5

J22

J25

K1

K4

K23

K26

L3

L6

L21

L24

M2

M5

M22

M25

N1

N4

N23

N26

P3

B1

OMIT

U1000

PENRYN

FCBGA

4 OF 4

P6

P21

P24

R2

R5

R22

R25

T1

T4

T23

T26

U3

U6

U21

U24

V2

V5

V22

V25

W1

W4

W23

W26

Y3

Y6

Y21

Y24

AA2

AA5

AA8

AA11

AA14

AA16

AA19

AA22

AA25

AB1

AB4

AB8

AB11

AB13

AB16

AB19

AB23

AB26

AC3

AC6

AC8

AC11

AC14

AC16

AC19

AC21

AC24

AD2

AD5

AD8

AD11

AD13

AD16

AD19

AD22

AD25

AE1

AE4

AE8

AE11

AE14

AE16

AE19

AE23

AE26

A2

AF6

AF8

AF11

AF13

AF16

AF19

AF21

A25

AF25

D

C

B

CPU Power & Ground

051-8071

SHT

SYNC_DATE=04/01/2008

OF

11 98

1

A

REV.

B

SYNC_MASTER=M98_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

5

4

3

2

SCALE

NONE

87

www.vinafix.vn

6

5

4

3

21

D

D

CPU VCORE HF AND BULK DECOUPLING

=PPVCORE_S0_CPU

8

11 45

CRITICAL

C1250

PLACEMENT_NOTE=Place in CPU center cavity.

C

PLACEMENT_NOTE=Place in CPU center cavity.

POLY-TANT

PLACEMENT_NOTE=Place in CPU center cavity.

CRITICAL

C1252

POLY-TANT

PLACEMENT_NOTE=Place in CPU center cavity.

4x 330uF, 20x 22uF 0805

CRITICAL

1

C1251

330UF

D2T-SM2

330UF

D2T-SM2

20%

2.0V

20%

2.0V

330UF

20%

2.0V

32

POLY-TANT

D2T-SM2

CRITICAL

1

C1253

330UF

20%

2.0V

32

POLY-TANT

D2T-SM2

1

32

1

32

CRITICAL

1

C1200

22UF

20%

6.3V

2

X5R-CERM
603

CRITICAL

1

C1210

22UF

20%

6.3V

2

X5R-CERM
603

CRITICAL

1

C1201

22UF

20%

6.3V

2

X5R-CERM
603

CRITICAL

1

C1211

22UF

20%

6.3V

2

X5R-CERM
603

CRITICAL

1

C1202

22UF

20%

6.3V

2

X5R-CERM
603

CRITICAL

1

C1212

22UF

20%

6.3V

2

X5R-CERM
603

CRITICAL

1

C1203

22UF

20%

6.3V

2

X5R-CERM
603

CRITICAL

1

C1213

22UF

20%

6.3V

2

X5R-CERM
603

CRITICAL

1

C1204

22UF

20%

6.3V

2

X5R-CERM
603

CRITICAL

1

C1214

22UF

20%

6.3V

2

X5R-CERM
603

CRITICAL

1

C1205

22UF

20%

6.3V

2

X5R-CERM
603

CRITICAL

1

C1215

22UF

20%

6.3V

2

X5R-CERM
603

CRITICAL

1

C1206

22UF

20%

6.3V

2

X5R-CERM
603

CRITICAL

1

C1216

22UF

20%

6.3V

2

X5R-CERM

603

CRITICAL

1

C1207

22UF

20%

6.3V

2

X5R-CERM
603

CRITICAL

1

C1217

22UF

20%

6.3V

2

X5R-CERM
603

CRITICAL

1

C1208

22UF

20%

6.3V

2

X5R-CERM
603

CRITICAL

1

C1218

22UF

20%

6.3V

2

X5R-CERM
603

CRITICAL

1

C1209

22UF

20%

6.3V

2

X5R-CERM
603

CRITICAL

1

C1219

22UF

20%

6.3V

2

X5R-CERM
603

C

VCCP (CPU I/O) DECOUPLING

=PP1V05_S0_CPU

6 8

10 11 13 61

1x 470uF, 6x 0.1uF 0402

CRITICAL

1

C1235

470UF

20%

2.5V
POLY

D2T

WF: Consider sharing bulk cap with NB Vtt?

1

C1236

0.1UF

20%
10V

2

32

CERM
402

1

C1237

0.1UF

20%
10V

2

CERM
402

1

C1238

2

0.1UF

20%
10V
CERM
402

1

2

C1239

0.1UF

20%
10V
CERM
402

1

C1240

0.1UF

20%
10V

2

CERM
402

1

C1241

2

0.1UF

20%
10V
CERM
402

B

=PP1V5_S0_CPU

8

11

C1280

10uF

6.3V

20%

X5R
603

A

8

76

VCCA (CPU AVdd) DECOUPLING

1x 10uF, 1x 0.01uF

1

1

C1281

0.01UF

10%
16V

2

2

CERM
402

PLACEMENT_NOTE=Place near CPU pin B26.

B

CPU Decoupling & VID

SYNC_MASTER=M98_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

5

4

3

2

SCALE

NONE

051-8071

SHT

SYNC_DATE=04/01/2008

OF

1

A

REV.

B

9812

87

www.vinafix.vn

6

5

4

3

21

Mini-XDP Connector

NOTE: This is not the standard XDP pinout.

D

Use with 920-0620 adapter board to support CPU, MCP debugging.

D

MCP79-specific pinout

=PP3V3_S0_XDP

6 8

=PP1V05_S0_CPU

6 8

10 11 12 61

XDP

1

R1315

54.9

1%
1/16W
MF-LF

402

2

XDP_BPM_L<5>

10 88

BI

XDP_BPM_L<4>

10 88

BI

XDP_BPM_L<3>

10 88

BI

XDP_BPM_L<2>

10 88

IN

XDP_BPM_L<1>

10 88

IN

XDP_BPM_L<0>

10 88

IN

C

XDP

R1399

1K

1/16W
MF-LF

21

5%

402

CPU_PWRGD

10 14 88

IN

19

IN

6

21

OUT

7

21 44 91

BI

7

21 44 91

BI

6

10 88

OUT

TP_XDP_OBSFN_B0
TP_XDP_OBSFN_B1

TP_XDP_OBSDATA_B0
TP_XDP_OBSDATA_B1

TP_XDP_OBSDATA_B2

7

TP_XDP_OBSDATA_B3

7

XDP_PWRGD

PM_LATRIGGER_L
JTAG_MCP_TCK

SMBUS_MCP_0_DATA
SMBUS_MCP_0_CLK

XDP_TCK

XDP_OBS20

OBSFN_A0
OBSFN_A1

OBSDATA_A0
OBSDATA_A1

OBSDATA_A2
OBSDATA_A3

OBSFN_B0
OBSFN_B1

OBSDATA_B0
OBSDATA_B1 OBSDATA_D1

OBSDATA_B2
OBSDATA_B3

PWRGD/HOOK0

HOOK1

VCC_OBS_AB

HOOK2
HOOK3

SDA

SCL
TCK1
TCK0

XDP

1

C1300

0.1uF

10%
16V

2

X5R
402

B

CRITICAL
XDP_CONN

J1300

LTH-030-01-G-D-NOPEGS

F-ST-SM

2

1

4

3

6

5

87

10

12 11

14 13

16 15

18 17

20

22 21

24 23

26 25

28 27

30

32 31

34 33

36 35

38 37

40

42 41

44 43

46 45

48 47

50

52 51

54 53

56 55

NC

58 57

60

9

19

29

39

49

59

998-1571

OBSFN_C0
OBSFN_C1

OBSDATA_C0
OBSDATA_C1

OBSDATA_C2
OBSDATA_C3

OBSFN_D0
OBSFN_D1

OBSDATA_D0

OBSDATA_D2
OBSDATA_D3

ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.
TDO
TRSTn
TDI
TMS
XDP_PRESENT#
XDP

1

C1301

0.1uF

10%

16V

2

X5R

402

JTAG_MCP_TDO_CONN
JTAG_MCP_TRST_L

MCP_DEBUG<0>
MCP_DEBUG<1>

MCP_DEBUG<2>
MCP_DEBUG<3>

JTAG_MCP_TDI
JTAG_MCP_TMS

MCP_DEBUG<4>
MCP_DEBUG<5>

MCP_DEBUG<6>
MCP_DEBUG<7>

FSB_CLK_ITP_P
FSB_CLK_ITP_N

XDP_CPURST_L

88

XDP_DBRESET_L

XDP_TDO_CONN
XDP_TRST_L
XDP_TDI
XDP_TMS

6

IN

6

21

OUT

19 91

BI

19 91

BI

19 91

BI

19 91

BI

6

21

OUT

6

21

OUT

19 91

BI

19 91

BI

19 91

BI

19 91

BI

14 88

IN

14 88

IN

10 25

OUT

6

IN

6

10 88

OUT

6

10 88

OUT

6

10 88

OUT

XDP

R1303

1K

21

FSB_CPURST_L

5%

PLACEMENT_NOTE=Place close to CPU to minimize stub.

1/16W
MF-LF

402

9

10 14 88

IN

C

B

A

8

76

Direction of XDP module

Please avoid any obstructions
on even-numbered side of J1300

5

eXtended Debug Port(MiniXDP)

051-8071

SHT

SYNC_DATE=04/01/2008

OF

13

1

A

REV.

B

98

SYNC_MASTER=M98_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

4

3

2

SCALE

NONE

87

www.vinafix.vn

D

C

=PP1V05_S0_MCP_FSB

8 9

14 22 23

R1410

54.9

1%
1/16W
MF-LF

402

B

10 42 88

10 88

PM_THRMTRIP_L

IN

CPU_FERR_L

IN

NO STUFF

R1420

1K

5%
1/16W
MF-LF

402

9

9

9

IN

IN

IN

=MCP_BSEL<2>
=MCP_BSEL<1>
=MCP_BSEL<0>

A

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

8

76

6

5

4

3

21

OMIT

U1400

MCP79-TOPO-B

BGA

FSB_DSTB_L_P<0>

7

10 88

BI

FSB_DSTB_L_N<0>

7

10 88

BI

FSB_DINV_L<0>

7

10 88

BI

FSB_DSTB_L_P<1>

7

10 88

BI

FSB_DSTB_L_N<1>

7

10 88

BI

FSB_DINV_L<1>

7

10 88

BI

FSB_DSTB_L_P<2>

7

10 88

BI

FSB_DSTB_L_N<2>

7

10 88

BI

FSB_DINV_L<2>

7

10 88

BI

FSB_DSTB_L_P<3>

7

10 88

BI

FSB_DSTB_L_N<3>

7

10 88

BI

FSB_DINV_L<3>

7

10 88

BI

FSB_A_L<3>

7

10 88

BI

FSB_A_L<4>

7

10 88

BI

FSB_A_L<5>

7

10 88

BI

FSB_A_L<6>

7

10 88

BI

FSB_A_L<7>

7

10 88

BI

FSB_A_L<8>

7

10 88

BI

FSB_A_L<9>

7

10 88

BI

FSB_A_L<10>

7

10 88

BI

FSB_A_L<11>

7

10 88

BI

FSB_A_L<12>

7

10 88

BI

FSB_A_L<13>

7

10 88

BI

FSB_A_L<14>

7

10 88

BI

FSB_A_L<15>

7

10 88

BI

FSB_A_L<16>

7

10 88

BI

FSB_A_L<17>

7

10 88

BI

FSB_A_L<18>

7

10 88

BI

FSB_A_L<19>

7

10 88

BI

FSB_A_L<20>

7

10 88

BI

FSB_A_L<21>

7

10 88

BI

FSB_A_L<22>

7

10 88

BI

FSB_A_L<23>

7

10 88

BI

FSB_A_L<24>

7

10 88

BI

FSB_A_L<25>

7

10 88

BI

FSB_A_L<26>

7

10 88

BI

FSB_A_L<27>

7

10 88

BI

FSB_A_L<28>

7

10 88

BI

FSB_A_L<29>

7

10 88

BI

FSB_A_L<30>

7

10 88

BI

FSB_A_L<31>

7

10 88

BI

FSB_A_L<32>

10 88

BI

FSB_A_L<33>

10 88

BI

FSB_A_L<34>

10 88

BI

FSB_A_L<35>

10 88

BI

FSB_ADSTB_L<0>

7

10 88

BI

FSB_ADSTB_L<1>

7

10 88

BI

FSB_REQ_L<0>

7

10 88

BI

FSB_REQ_L<1>

7

10 88

BI

FSB_REQ_L<2>

7

10 88

BI

FSB_REQ_L<3>

7

10 88

BI

FSB_REQ_L<4>

7

10 88

BI

7

10 88

BI

10 88

BI

9

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

IN

10 88

OUT

9

OUT

10 42 61 88

OUT

10 88

OUT

10 88

OUT

10 88

OUT

23

270 mA (A01)

88

88

88

88

88

FSB_ADS_L
FSB_BNR_L
FSB_BREQ0_L
FSB_BREQ1_L
FSB_DBSY_L
FSB_DRDY_L
FSB_HIT_L
FSB_HITM_L
FSB_LOCK_L
FSB_TRDY_L

CPU_PECI_MCP
CPU_PROCHOT_L

(MCP_BSEL<2>)
(MCP_BSEL<1>)
(MCP_BSEL<0>)

FSB_RS_L<0>
FSB_RS_L<1>
FSB_RS_L<2>

PP1V05_S0_MCP_PLL_FSB

MCP_BCLK_VML_COMP_VDD
MCP_BCLK_VML_COMP_GND

MCP_CPU_COMP_VCC
MCP_CPU_COMP_GND

206 mA

20 mA
29 mA
15 mA

1/16W
MF-LF

1/16W
MF-LF

1

1

R1416

62

62

5%

5%

1/16W
MF-LF
402

402

2

2

NO STUFF

1

1

R1422

1K

1K

5%

5%
1/16W
MF-LF

402

402

2

2

1

1

1/16W
MF-LF

1/16W
MF-LF

R1435

49.9

1%

1%

1/16W
MF-LF
402

402

2

2

1

1

R1436

49.9

1%

1%
1/16W
MF-LF

402

402

2

2

R1430

49.9

R1431

49.9

1

R1415

2

NO STUFF

1

R1421

2

T40

CPU_DSTBP0#

U40

CPU_DSTBN0#

V41

CPU_DBI0#

W39

CPU_DSTBP1#

W37

CPU_DSTBN1#

V35

CPU_DBI1#

N37

CPU_DSTBP2#

L36

CPU_DSTBN2#

N35

CPU_DBI2#

M39

CPU_DSTBP3#

M41

CPU_DSTBN3#

J41

CPU_DBI3#

AC34

CPU_A3#

AE38

CPU_A4#

AE34

CPU_A5#

AC37

CPU_A6#

AE37

CPU_A7#

AE35

CPU_A8#

AB35

CPU_A9#

AF35

CPU_A10#

AG35

CPU_A11#

AG39

CPU_A12#

AE33

CPU_A13#

AG37

CPU_A14#

AG38

CPU_A15#

AG34

CPU_A16#

AN38

CPU_A17#

AL39

CPU_A18#

AG33

CPU_A19#

AL33

CPU_A20#

AJ33

CPU_A21#

AN36

CPU_A22#

AJ35

CPU_A23#

AJ37

CPU_A24#

AJ36

CPU_A25#

AJ38

CPU_A26#

AL37

CPU_A27#

AL34

CPU_A28#

AN37

CPU_A29#

AJ34

CPU_A30#

AL38

CPU_A31#

AL35

CPU_A32#

AN34

CPU_A33#

AR39

CPU_A34#

AN35

CPU_A35#

AE36

CPU_ADSTB0#

AK35

CPU_ADSTB1#

AC38

CPU_REQ0#

AA33

CPU_REQ1#

AC39

CPU_REQ2#

AC33

CPU_REQ3#

AC35

CPU_REQ4#

AD42

CPU_ADS#

AD43

CPU_BNR#

AE40

CPU_BR0#

AL32

CPU_BR1#

AD39

CPU_DBSY#

AD41

CPU_DRDY#

AB42

CPU_HIT#

AD40

CPU_HITM#

AC43

CPU_LOCK#

AE41

CPU_TRDY#

E41

CPU_PECI

AJ41

CPU_PROCHOT#

AG43

CPU_THERMTRIP#

AH40

CPU_FERR#

F42

CPU_BSEL2

D42

CPU_BSEL1

F41

CPU_BSEL0

AC41

CPU_RS0#

AB41

CPU_RS1#

AC42

CPU_RS2#

AG27

+V_DLL_DLCELL_AVDD

AH27

+V_PLL_MCLK

AG28

+V_PLL_FSB

AH28

+V_PLL_CPU

AM39

BCLK_VML_COMP_VDD

AM40

BCLK_VML_COMP_GND

AM43

CPU_COMP_VCC

AM42

CPU_COMP_GND

(1 OF 11)

FSB

CPU_BPRI#

CPU_DEFER#

BCLK_OUT_CPU_P
BCLK_OUT_CPU_N

BCLK_OUT_ITP_P
BCLK_OUT_ITP_N

BCLK_OUT_NB_P
BCLK_OUT_NB_N

BCLK_IN_N
BCLK_IN_P

CPU_A20M#

CPU_IGNNE#

CPU_INIT#

CPU_PWRGD

CPU_RESET#

CPU_DPSLP#

CPU_DPWR#
CPU_STPCLK#
CPU_DPRSTP#

5

CPU_D0#
CPU_D1#
CPU_D2#
CPU_D3#
CPU_D4#
CPU_D5#
CPU_D6#
CPU_D7#
CPU_D8#

CPU_D9#
CPU_D10#
CPU_D11#
CPU_D12#
CPU_D13#
CPU_D14#
CPU_D15#
CPU_D16#
CPU_D17#
CPU_D18#
CPU_D19#
CPU_D20#
CPU_D21#
CPU_D22#
CPU_D23#
CPU_D24#
CPU_D25#
CPU_D26#
CPU_D27#
CPU_D28#
CPU_D29#
CPU_D30#
CPU_D31#
CPU_D32#
CPU_D33#
CPU_D34#
CPU_D35#
CPU_D36#
CPU_D37#
CPU_D38#
CPU_D39#
CPU_D40#
CPU_D41#
CPU_D42#
CPU_D43#
CPU_D44#
CPU_D45#
CPU_D46#
CPU_D47#
CPU_D48#
CPU_D49#
CPU_D50#
CPU_D51#
CPU_D52#
CPU_D53#
CPU_D54#
CPU_D55#
CPU_D56#
CPU_D57#
CPU_D58#
CPU_D59#
CPU_D60#
CPU_D61#
CPU_D62#
CPU_D63#

CPU_INTR

CPU_NMI
CPU_SMI#

CPU_SLP#

Y43

W42

Y40

W41

Y39

V42

Y41

Y42

P42

U41

R42

T39

T42

T41

R41

T43

W35

AA37

W33

W34

AA36

AA34

AA38

AA35

U38

U36

U35

U33

U34

W38

R33

U37

N34

N33

R34

R35

P35

R39

R37

R38

L37

L39

L38

N36

N38

J39

J38

J37

L42

M42

P41

N41

N40

M40

H40

K42

H41

L41

H43

H42

K41

J40

H39

M43

AA41

AA40

G42

G41

AL43

AL42

AL41

AK42

AK41

AJ40

AF41

AH39

AH42

AF42

AG41

AH41

AH43

H38

AM33

AN33

AM32

AG42

AN32

4

FSB_D_L<0>
FSB_D_L<1>
FSB_D_L<2>
FSB_D_L<3>
FSB_D_L<4>
FSB_D_L<5>
FSB_D_L<6>
FSB_D_L<7>
FSB_D_L<8>
FSB_D_L<9>
FSB_D_L<10>
FSB_D_L<11>
FSB_D_L<12>
FSB_D_L<13>
FSB_D_L<14>
FSB_D_L<15>
FSB_D_L<16>
FSB_D_L<17>
FSB_D_L<18>
FSB_D_L<19>
FSB_D_L<20>
FSB_D_L<21>
FSB_D_L<22>
FSB_D_L<23>
FSB_D_L<24>
FSB_D_L<25>
FSB_D_L<26>
FSB_D_L<27>
FSB_D_L<28>
FSB_D_L<29>
FSB_D_L<30>
FSB_D_L<31>
FSB_D_L<32>
FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>
FSB_D_L<36>
FSB_D_L<37>
FSB_D_L<38>
FSB_D_L<39>
FSB_D_L<40>
FSB_D_L<41>
FSB_D_L<42>
FSB_D_L<43>
FSB_D_L<44>
FSB_D_L<45>
FSB_D_L<46>
FSB_D_L<47>
FSB_D_L<48>
FSB_D_L<49>
FSB_D_L<50>
FSB_D_L<51>
FSB_D_L<52>
FSB_D_L<53>
FSB_D_L<54>
FSB_D_L<55>
FSB_D_L<56>
FSB_D_L<57>
FSB_D_L<58>
FSB_D_L<59>
FSB_D_L<60>
FSB_D_L<61>
FSB_D_L<62>
FSB_D_L<63>

FSB_BPRI_L
FSB_DEFER_L

FSB_CLK_CPU_P
FSB_CLK_CPU_N

FSB_CLK_ITP_P
FSB_CLK_ITP_N

FSB_CLK_MCP_P

88

FSB_CLK_MCP_N

88

CPU_A20M_L
CPU_IGNNE_L
CPU_INIT_L
CPU_INTR
CPU_NMI
CPU_SMI_L

CPU_PWRGD
FSB_CPURST_L

FSB_CPUSLP_L
CPU_DPSLP_L
FSB_DPWR_L
CPU_STPCLK_L
CPU_DPRSTP_L

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

10 88

OUT

10 88

OUT

10 88

OUT

10 88

OUT

13 88

OUT

13 88

OUT

Loop-back clock for delay matching.

10 88

OUT

10 88

OUT

10 88

OUT

9

10 88

OUT

9

10 88

OUT

10 88

OUT

9

10 13 88

OUT

10 88

OUT

10 88

OUT

10 88

OUT

10 88

OUT

10 61 88

9

OUT

3

=PP1V05_S0_MCP_FSB

NO STUFF

1

R1440

150

5%
1/16W
MF-LF
402

2

10 13 88

OUT

8 9

14 22 23

APPLE INC.

2

MCP CPU Interface

SYNC_MASTER=T18_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

051-8071

SHT

SYNC_DATE=06/06/2008

OF

1

D

C

B

A

REV.

B

9814

87

www.vinafix.vn

6

5

4

3

21

MCP79-TOPO-B

MDQ1_63
MDQ1_62
MDQ1_61
MDQ1_60
MDQ1_59
MDQ1_58
MDQ1_57
MDQ1_56
MDQ1_55
MDQ1_54
MDQ1_53
MDQ1_52
MDQ1_51
MDQ1_50
MDQ1_49
MDQ1_48
MDQ1_47
MDQ1_46
MDQ1_45
MDQ1_44
MDQ1_43
MDQ1_42
MDQ1_41
MDQ1_40
MDQ1_39
MDQ1_38
MDQ1_37
MDQ1_36
MDQ1_35
MDQ1_34
MDQ1_33
MDQ1_32
MDQ1_31
MDQ1_30
MDQ1_29
MDQ1_28
MDQ1_27
MDQ1_26
MDQ1_25
MDQ1_24
MDQ1_23
MDQ1_22
MDQ1_21
MDQ1_20
MDQ1_19
MDQ1_18
MDQ1_17
MDQ1_16
MDQ1_15
MDQ1_14
MDQ1_13
MDQ1_12
MDQ1_11
MDQ1_10
MDQ1_9
MDQ1_8
MDQ1_7
MDQ1_6
MDQ1_5
MDQ1_4
MDQ1_3
MDQ1_2
MDQ1_1
MDQ1_0

MDQM1_7
MDQM1_6
MDQM1_5
MDQM1_4
MDQM1_3
MDQM1_2
MDQM1_1
MDQM1_0

OMIT

U1400

BGA

(3 OF 11)

MDQS1_7_P
MDQS1_7_N
MDQS1_6_P
MDQS1_6_N
MDQS1_5_P
MDQS1_5_N
MDQS1_4_P
MDQS1_4_N
MDQS1_3_P
MDQS1_3_N
MDQS1_2_P
MDQS1_2_N
MDQS1_1_P
MDQS1_1_N
MDQS1_0_P
MDQS1_0_N

MEMORY PARTITION 1

MEMORY

CONTROL

MCLK1A_2_P
MCLK1A_2_N

MCLK1A_1_P
MCLK1A_1_N

MCLK1A_0_P
MCLK1A_0_N

MRAS1#
MCAS1#

MWE1#

MBA1_2
MBA1_1
MBA1_0

MA1_14
MA1_13
MA1_12
MA1_11
MA1_10

MA1_9
MA1_8
MA1_7
MA1_6
MA1_5
MA1_4
MA1_3
MA1_2
MA1_1
MA1_0

1A

MCS1A_1#
MCS1A_0#

MODT1A_1
MODT1A_0

MCKE1A_1
MCKE1A_0

AT2

AT1

AY2

AY1

BB6

BA6

BA10

AY11

BB33

BA33

BB37

BA37

BA43

AY42

AT42

AT43

AW16

BA15

BA16

BB29

BB18

BB17

BA29

BA14

AW28

BC28

BA17

BB28

AY28

BA28

AY27

BA27

BA26

BB26

BA25

BB25

BA18

BA42

BB42

BB22

BA22

BA19

AY19

BB14

BB16

BB13

AY15

AY31

BB30

MEM_B_DQS_P<7>
MEM_B_DQS_N<7>
MEM_B_DQS_P<6>
MEM_B_DQS_N<6>
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
MEM_B_DQS_P<4>
MEM_B_DQS_N<4>
MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
MEM_B_DQS_P<2>
MEM_B_DQS_N<2>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQS_P<0>
MEM_B_DQS_N<0>

MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L

MEM_B_BA<2>
MEM_B_BA<1>
MEM_B_BA<0>

MEM_B_A<14>
MEM_B_A<13>
MEM_B_A<12>
MEM_B_A<11>
MEM_B_A<10>
MEM_B_A<9>
MEM_B_A<8>
MEM_B_A<7>
MEM_B_A<6>
MEM_B_A<5>
MEM_B_A<4>
MEM_B_A<3>
MEM_B_A<2>
MEM_B_A<1>
MEM_B_A<0>

TP_MEM_B_CLK2P
TP_MEM_B_CLK2N

MEM_B_CLK_P<1>
MEM_B_CLK_N<1>

MEM_B_CLK_P<0>
MEM_B_CLK_N<0>

MEM_B_CS_L<1>
MEM_B_CS_L<0>

MEM_B_ODT<1>
MEM_B_ODT<0>

MEM_B_CKE<1>
MEM_B_CKE<0>

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

7

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

D

C

B

OMIT

U1400

MCP79-TOPO-B

BGA

MDQ0_63
MDQ0_62
MDQ0_61
MDQ0_60
MDQ0_59
MDQ0_58
MDQ0_57
MDQ0_56
MDQ0_55
MDQ0_54
MDQ0_53
MDQ0_52
MDQ0_51
MDQ0_50
MDQ0_49
MDQ0_48
MDQ0_47
MDQ0_46
MDQ0_45
MDQ0_44
MDQ0_43
MDQ0_42
MDQ0_41
MDQ0_40
MDQ0_39
MDQ0_38
MDQ0_37
MDQ0_36
MDQ0_35
MDQ0_34
MDQ0_33
MDQ0_32
MDQ0_31
MDQ0_30
MDQ0_29
MDQ0_28
MDQ0_27
MDQ0_26
MDQ0_25
MDQ0_24
MDQ0_23
MDQ0_22
MDQ0_21
MDQ0_20
MDQ0_19
MDQ0_18
MDQ0_17
MDQ0_16
MDQ0_15
MDQ0_14
MDQ0_13
MDQ0_12
MDQ0_11
MDQ0_10
MDQ0_9
MDQ0_8
MDQ0_7
MDQ0_6
MDQ0_5
MDQ0_4
MDQ0_3
MDQ0_2
MDQ0_1
MDQ0_0

MDQM0_7
MDQM0_6
MDQM0_5
MDQM0_4
MDQM0_3
MDQM0_2
MDQM0_1
MDQM0_0

(2 OF 11)

MDQS0_7_P
MDQS0_7_N
MDQS0_6_P
MDQS0_6_N
MDQS0_5_P
MDQS0_5_N
MDQS0_4_P
MDQS0_4_N
MDQS0_3_P
MDQS0_3_N
MDQS0_2_P
MDQS0_2_N
MDQS0_1_P
MDQS0_1_N
MDQS0_0_P
MDQS0_0_N

MEMORY PARTITION 0

MEMORY

CONTROL

MCLK0A_2_P
MCLK0A_2_N

MCLK0A_1_P
MCLK0A_1_N

MCLK0A_0_P
MCLK0A_0_N

MCS0A_1#
MCS0A_0#

MODT0A_1
MODT0A_0

MCKE0A_1
MCKE0A_0

MRAS0#
MCAS0#

MBA0_2
MBA0_1
MBA0_0

MA0_14
MA0_13
MA0_12
MA0_11
MA0_10

0A

MWE0#

MA0_9
MA0_8
MA0_7
MA0_6
MA0_5
MA0_4
MA0_3
MA0_2
MA0_1
MA0_0

AL10

AL11

AR8

AR9

AW7

AW8

AP13

AR13

AV25

AW25

AU30

AU29

AT35

AU35

AU39

AT39

AV17

AP17

AR17

AP23

AP19

AW17

AR23

AU15

AN23

AW21

AN19

AV21

AR22

AU21

AP21

AR21

AN21

AV19

AU19

AT19

AR19

AW33

AV33

BA24

AY24

BB20

BC20

AT15

AR18

AP15

AV15

AU23

AT23

MEM_A_DQS_P<7>
MEM_A_DQS_N<7>
MEM_A_DQS_P<6>
MEM_A_DQS_N<6>
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
MEM_A_DQS_P<4>
MEM_A_DQS_N<4>
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DQS_P<0>
MEM_A_DQS_N<0>

MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L

MEM_A_BA<2>
MEM_A_BA<1>
MEM_A_BA<0>

MEM_A_A<14>
MEM_A_A<13>
MEM_A_A<12>
MEM_A_A<11>
MEM_A_A<10>
MEM_A_A<9>
MEM_A_A<8>
MEM_A_A<7>
MEM_A_A<6>
MEM_A_A<5>
MEM_A_A<4>
MEM_A_A<3>
MEM_A_A<2>
MEM_A_A<1>
MEM_A_A<0>

TP_MEM_A_CLK2P
TP_MEM_A_CLK2N

MEM_A_CLK_P<1>
MEM_A_CLK_N<1>

MEM_A_CLK_P<0>
MEM_A_CLK_N<0>

MEM_A_CS_L<1>
MEM_A_CS_L<0>

MEM_A_ODT<1>
MEM_A_ODT<0>

MEM_A_CKE<1>
MEM_A_CKE<0>

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

7

7

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

MEM_B_DQ<63>
MEM_B_DQ<62>
MEM_B_DQ<61>
MEM_B_DQ<60>
MEM_B_DQ<59>
MEM_B_DQ<58>
MEM_B_DQ<57>
MEM_B_DQ<56>
MEM_B_DQ<55>
MEM_B_DQ<54>
MEM_B_DQ<53>
MEM_B_DQ<52>
MEM_B_DQ<51>
MEM_B_DQ<50>
MEM_B_DQ<49>
MEM_B_DQ<48>
MEM_B_DQ<47>
MEM_B_DQ<46>
MEM_B_DQ<45>
MEM_B_DQ<44>
MEM_B_DQ<43>
MEM_B_DQ<42>
MEM_B_DQ<41>
MEM_B_DQ<40>
MEM_B_DQ<39>
MEM_B_DQ<38>
MEM_B_DQ<37>
MEM_B_DQ<36>
MEM_B_DQ<35>
MEM_B_DQ<34>
MEM_B_DQ<33>
MEM_B_DQ<32>
MEM_B_DQ<31>
MEM_B_DQ<30>
MEM_B_DQ<29>
MEM_B_DQ<28>
MEM_B_DQ<27>
MEM_B_DQ<26>
MEM_B_DQ<25>
MEM_B_DQ<24>
MEM_B_DQ<23>
MEM_B_DQ<22>
MEM_B_DQ<21>
MEM_B_DQ<20>
MEM_B_DQ<19>
MEM_B_DQ<18>
MEM_B_DQ<17>
MEM_B_DQ<16>
MEM_B_DQ<15>
MEM_B_DQ<14>
MEM_B_DQ<13>
MEM_B_DQ<12>
MEM_B_DQ<11>
MEM_B_DQ<10>
MEM_B_DQ<9>
MEM_B_DQ<8>
MEM_B_DQ<7>
MEM_B_DQ<6>
MEM_B_DQ<5>
MEM_B_DQ<4>
MEM_B_DQ<3>
MEM_B_DQ<2>
MEM_B_DQ<1>
MEM_B_DQ<0>

MEM_B_DM<7>
MEM_B_DM<6>
MEM_B_DM<5>
MEM_B_DM<4>
MEM_B_DM<3>
MEM_B_DM<2>
MEM_B_DM<1>
MEM_B_DM<0>

AN10

AP11

AU11

AV11

AV13

AW13

AR11

AT11

AR14

AU13

AR26

AU25

AT27

AU27

AP25

AR25

AP27

AR27

AP29

AR29

AP31

AR31

AV27

AN29

AV29

AN31

AU31

AR33

AV37

AW37

AT31

AV31

AT37

AU37

AW39

AV39

AR37

AR38

AV38

AW38

AR35

AP35

AR10

AN13

AN27

AW29

AV35

AR34

AL8

AL9

AP9

AN9

AL6

AL7

AN6

AN7

AR6

AR7

AV6

AW5

AR5

AU6

AV5

AU7

AU8

AW9

AW6

AY5

AU9

AV9

AN5

AU5

MEM_A_DQ<63>

27 89

BI

MEM_A_DQ<62>

27 89

BI

MEM_A_DQ<61>

27 89

BI

MEM_A_DQ<60>

27 89

BI

MEM_A_DQ<59>

27 89

D

C

B

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

MEM_A_DQ<58>
MEM_A_DQ<57>
MEM_A_DQ<56>
MEM_A_DQ<55>
MEM_A_DQ<54>
MEM_A_DQ<53>
MEM_A_DQ<52>
MEM_A_DQ<51>
MEM_A_DQ<50>
MEM_A_DQ<49>
MEM_A_DQ<48>
MEM_A_DQ<47>
MEM_A_DQ<46>
MEM_A_DQ<45>
MEM_A_DQ<44>
MEM_A_DQ<43>
MEM_A_DQ<42>
MEM_A_DQ<41>
MEM_A_DQ<40>
MEM_A_DQ<39>
MEM_A_DQ<38>
MEM_A_DQ<37>
MEM_A_DQ<36>
MEM_A_DQ<35>
MEM_A_DQ<34>
MEM_A_DQ<33>
MEM_A_DQ<32>
MEM_A_DQ<31>
MEM_A_DQ<30>
MEM_A_DQ<29>
MEM_A_DQ<28>
MEM_A_DQ<27>
MEM_A_DQ<26>
MEM_A_DQ<25>
MEM_A_DQ<24>
MEM_A_DQ<23>
MEM_A_DQ<22>
MEM_A_DQ<21>
MEM_A_DQ<20>
MEM_A_DQ<19>
MEM_A_DQ<18>
MEM_A_DQ<17>
MEM_A_DQ<16>
MEM_A_DQ<15>
MEM_A_DQ<14>
MEM_A_DQ<13>
MEM_A_DQ<12>
MEM_A_DQ<11>
MEM_A_DQ<10>
MEM_A_DQ<9>
MEM_A_DQ<8>
MEM_A_DQ<7>
MEM_A_DQ<6>
MEM_A_DQ<5>
MEM_A_DQ<4>
MEM_A_DQ<3>
MEM_A_DQ<2>
MEM_A_DQ<1>
MEM_A_DQ<0>

MEM_A_DM<7>
MEM_A_DM<6>
MEM_A_DM<5>
MEM_A_DM<4>
MEM_A_DM<3>
MEM_A_DM<2>
MEM_A_DM<1>
MEM_A_DM<0>

BB10

BB12

AW12

AY12

BA12

BC32

AW32

BA35

AY36

BA32

BB32

BA34

AY35

BC36

AW36

BA39

AY40

BA36

BB36

BA38

AY39

BB40

AW40

AV42

AV41

BA40

BC40

AW42

AW41

AT40

AT41

AP41

AN40

AU40

AU41

AR41

AP42

BA11

BB34

BB38

AY43

AR42

AT4

AT3

AV2

AV3

AR4

AR3

AU2

AU3

AY4

AY3

BB3

BC3

AW4

AW3

BA3

BB2

BB5

BA5

BA8

BC8

BB4

BC4

BA7

AY8

BA9

BB8

BB9

AT5

BA2

AY7

A

8

76

MCP Memory Interface

SYNC_MASTER=T18_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

5

4

3

2

SCALE

NONE

051-8071

SHT

SYNC_DATE=06/06/2008

OF

15

1

A

REV.

B

98

87

www.vinafix.vn

D

8

16 23

C

B

A

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

8

76

=PP1V8R1V5_S0_MCP_MEM

R1610

R1611

40.2

1/16W
MF-LF

6

5

4

3

21

OMIT

U1400

MCP79-TOPO-B

BGA

TP_MEM_A_CLK5P

7

TP_MEM_A_CLK5N

7

TP_MEM_A_CLK4P

7

TP_MEM_A_CLK4N

7

TP_MEM_A_CLK3P

7

TP_MEM_A_CLK3N

7

TP_MEM_A_CS_L<2>

7

TP_MEM_A_CS_L<3>

7

TP_MEM_A_ODT<2>

7

TP_MEM_A_ODT<3>

7

TP_MEM_A_CKE<2>

7

TP_MEM_A_CKE<3>

7

PP1V05_S0_MCP_PLL_CORE

23

1

40.2

1%
1/16W
MF-LF

402

2

1

1%

402

2

87 mA (A01)

89

89

MCP_MEM_COMP_VDD
MCP_MEM_COMP_GND

17 mA
12 mA
19 mA
39 mA

AU33

MCLK0B_2_P

AU34

MCLK0B_2_N

BB24

MCLK0B_1_P

BC24

MCLK0B_1_N

BA21

MCLK0B_0_P

BB21

MCLK0B_0_N

AU17

MCS0B_0#

AR15

MCS0B_1#

AN17

MODT0B_0

AN15

MODT0B_1

AV23

MCKE0B_0

AN25

MCKE0B_1

T27

+V_PLL_XREF_XS

U28

+V_PLL_DP

U27

+V_PLL_CORE

T28

+V_VPLL

AN41

MEM_COMP_VDD

AM41

MEM_COMP_GND

AA22

GND1

AP12

GND2

G30

GND3

P10

GND4

T10

GND5

T6

GND6

V10

GND7

V34

GND8

W5

GND9

AA39

GND10

AB22

GND11

AB7

GND12

AD22

GND13

AE20

GND14

AF24

GND15

AG24

GND16

AH35

GND17

AK7

GND18

AM28

GND19

AT25

GND20

AP30

GND21

AR36

GND22

AU10

GND23

F28

GND24

BC21

GND25

AY9

GND26

BC9

GND27

D34

GND28

F24

GND29

G32

GND30

H31

GND31

K7

GND32

M38

GND33

M5

GND34

M6

GND35

M7

GND36

M9

GND37

N39

GND38

N8

GND39

P33

GND40

P34

GND41

P37

GND42

P4

GND43

P40

GND44

P7

GND45

R36

GND46

R40

GND47

R43

GND48

R5

GND49

T18

GND50

T20

GND51

AK11

GND52

T24

GND53

T26

GND54

5

(4 OF 11)

MCLK1B_2_P
MCLK1B_2_N

MCLK1B_1_P
MCLK1B_1_N

MCLK1B_0_P
MCLK1B_0_N

MEMORY CONTROL 0B

MEMORY CONTROL 1B

+VDD_MEM1
+VDD_MEM2
+VDD_MEM3
+VDD_MEM4
+VDD_MEM5
+VDD_MEM6
+VDD_MEM7
+VDD_MEM8

+VDD_MEM9
+VDD_MEM10
+VDD_MEM11
+VDD_MEM12
+VDD_MEM13
+VDD_MEM14
+VDD_MEM15
+VDD_MEM16
+VDD_MEM17
+VDD_MEM18
+VDD_MEM19
+VDD_MEM20
+VDD_MEM21
+VDD_MEM22
+VDD_MEM23
+VDD_MEM24
+VDD_MEM25
+VDD_MEM26
+VDD_MEM27
+VDD_MEM28
+VDD_MEM29
+VDD_MEM30
+VDD_MEM31
+VDD_MEM32
+VDD_MEM33
+VDD_MEM34
+VDD_MEM35
+VDD_MEM36
+VDD_MEM37
+VDD_MEM38
+VDD_MEM39
+VDD_MEM40
+VDD_MEM41
+VDD_MEM42
+VDD_MEM43
+VDD_MEM44
+VDD_MEM45

MCS1B_0#
MCS1B_1#

MODT1B_0
MODT1B_1

MCKE1B_0
MCKE1B_1

MRESET0#

GND55
GND56
GND57
GND58
GND59
GND60
GND61
GND62
GND63
GND64

BA41

BB41

AY23

BA23

BA20

AY20

BC16

BA13

AY16

BC13

BA30

BA31

AY32

AM17

AM19

AM21

AM23

AM25

AM27

AM29

AN16

BC29

AN20

AN24

AT17

AP16

AN22

AP20

AP24

AV16

AR16

AR20

AR24

AW15

AP22

AP18

AU16

AN18

AU24

AT21

AY29

AV24

AU20

AU22

AW27

BC17

AV20

AY17

AY18

AM15

AU18

AY25

AY26

AW19

AW24

BC25

AL30

AM31

T33

T34

T35

T37

T38

T7

T9

U18

U20

U22

4

TP_MEM_B_CLK5P
TP_MEM_B_CLK5N

TP_MEM_B_CLK4P
TP_MEM_B_CLK4N

TP_MEM_B_CLK3P
TP_MEM_B_CLK3N

TP_MEM_B_CS_L<2>
TP_MEM_B_CS_L<3>

TP_MEM_B_ODT<2>
TP_MEM_B_ODT<3>

TP_MEM_B_CKE<2>
TP_MEM_B_CKE<3>

MCP_MEM_RESET_L

TP or NC for DDR2.

=PP1V8R1V5_S0_MCP_MEM

4771 mA (A01, DDR3)

7

7

7

7

7

7

7

7

7

7

7

29

OUT

8

16 23

D

C

B

MCP Memory Misc

051-8071

SHT

SYNC_DATE=06/06/2008

OF

16 98

1

A

REV.

B

SYNC_MASTER=T18_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

3

2

SCALE

NONE

87

www.vinafix.vn

D

C

B

A

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

8

76

6

5

4

OMIT

U1400

MCP79-TOPO-B

BGA

=PEG_D2R_P<0>

9

IN

=PEG_D2R_N<0>

9

IN

=PEG_D2R_P<1>

9

IN

=PEG_D2R_N<1>

9

IN

=PEG_D2R_P<2>

9

IN

=PEG_D2R_N<2>

9

IN

=PEG_D2R_P<3>

9

IN

=PEG_D2R_N<3>

9

IN

=PEG_D2R_P<4>

9

IN

=PEG_D2R_N<4>

9

IN

=PEG_D2R_P<5>

9

IN

=PEG_D2R_N<5>

9

IN

=PEG_D2R_P<6>

9

IN

=PEG_D2R_N<6>

9

IN

=PEG_D2R_P<7>

9

IN

=PEG_D2R_N<7>

9

IN

=PEG_D2R_P<8>

9

IN

=PEG_D2R_N<8>

9

IN

=PEG_D2R_P<9>

9

IN

=PEG_D2R_N<9>

9

IN

=PEG_D2R_P<10>

9

IN

=PEG_D2R_N<10>

9

IN

=PEG_D2R_P<11>

9

IN

=PEG_D2R_N<11>

9

IN

=PEG_D2R_P<12>

9

IN

=PEG_D2R_N<12>

9

IN

=PEG_D2R_P<13>

9

IN

=PEG_D2R_N<13>

9

IN

=PEG_D2R_P<14>

9

IN

=PEG_D2R_N<14>

9

IN

=PEG_D2R_P<15>

9

IN

=PEG_D2R_N<15>

9

IN

PEG_PRSNT_L

9

IN

MINI_CLKREQ_L

30

IN

PCIE_MINI_PRSNT_L

30

IN

FW_CLKREQ_L

35

IN

PCIE_FW_PRSNT_L

9

IN

EXCARD_CLKREQ_L

31

IN

PCIE_EXCARD_PRSNT_L

31

IN

TP_PE4_CLKREQ_L

7

TP_PE4_PRSNT_L

AUD_IP_PERIPHERAL_DET

58

IN

GMUX_JTAG_TCK_L

84

OUT

TP_MCP_GPIO_18

7

GMUX_JTAG_TDO

9

IN

PCIE_WAKE_L

7

30 31

IN

PCIE_MINI_D2R_P

7

30 90

IN

PCIE_MINI_D2R_N

7

30 90

IN

PCIE_FW_D2R_P

35 90

IN

PCIE_FW_D2R_N

35 90

IN

PCIE_EXCARD_D2R_P

7

31 90

IN

PCIE_EXCARD_D2R_N

7

31 90

IN

TP_PCIE_PE4_D2RP

7

TP_PCIE_PE4_D2RN

7

=PP1V05_S0_MCP_PEX_DVDD0

8

57 mA (A01, DVDD0 & 1)

Minimum 1.025V for Gen2 support Minimum 1.025V for Gen2 support

=PP1V05_S0_MCP_PEX_DVDD1

8

PP1V05_S0_MCP_PLL_PEX

23

84 mA (A01)

MCP_PEX_CLK_COMP

90

NO STUFF

1

R1710

2.37K

1%
1/16W
MF-LF
402

2

PLACEMENT_NOTE=Place within 12.7mm of U1400

F7

PE0_RX0_P

E7

PE0_RX0_N

D7

PE0_RX1_P

C7

PE0_RX1_N

E6

PE0_RX2_P

F6

PE0_RX2_N

E5

PE0_RX3_P

F5

PE0_RX3_N

E4

PE0_RX4_P

E3

PE0_RX4_N

C3

PE0_RX5_P

D3

PE0_RX5_N

G5

PE0_RX6_P

H5

PE0_RX6_N

J7

PE0_RX7_P

J6

PE0_RX7_N

J5

PE0_RX8_P

J4

PE0_RX8_N

L11

PE0_RX9_P

L10

PE0_RX9_N

L9

PE0_RX10_P

L8

PE0_RX10_N

L7

PE0_RX11_P

L6

PE0_RX11_N

N11

PE0_RX12_P

N10

PE0_RX12_N

N9

PE0_RX13_P

P9

PE0_RX13_N

N7

PE0_RX14_P

N6

PE0_RX14_N

N5

PE0_RX15_P

N4

PE0_RX15_N

Int PU

C9

PE0_PRSNT_16#

Int PU

D5

PEB_CLKREQ#/GPIO_49

D9

PEB_PRSNT#

Int PU

E8

PEC_CLKREQ#/GPIO_50

C10

PEC_PRSNT#

Int PU

M15

PED_CLKREQ#/GPIO_51

B10

PED_PRSNT#

Int PU

L16

PEE_CLKREQ#/GPIO_16

L18

PEE_PRSNT#/GPIO_46

Int PU

M16

PEF_CLKREQ#/GPIO_17

M18

PEF_PRSNT#/GPIO_47

Int PU

M17

PEG_CLKREQ#/GPIO_18

M19

PEG_PRSNT#/GPIO_48

F17

PE_WAKE#

K9

PE1_RX0_P

J9

PE1_RX0_N

H9

PE1_RX1_P

G9

PE1_RX1_N

F9

PE1_RX2_P

E9

PE1_RX2_N

H7

PE1_RX3_P

G7

PE1_RX3_N

T17

+DVDD0_PEX1

W19

+DVDD0_PEX2

U17

+DVDD0_PEX3

V19

+DVDD0_PEX4

W16

+DVDD0_PEX5

W17

+DVDD0_PEX6

W18

+DVDD0_PEX7

U16

+DVDD0_PEX8

T19

+DVDD1_PEX1

U19

+DVDD1_PEX2

T16

+V_PLL_PEX

A11

PEX_CLK_COMP

If PE0 interface is not used, ground DVDD0_PEX and AVDD0_PEX.
If PE1 interface is not used, ground DVDD1_PEX and AVDD1_PEX.

5

(5 OF 11)

Int PU

Int PU

Int PU

Int PU

Int PU

Int PU

Int PU (S5)

PE0_TX0_P

PE0_TX0_N

PE0_TX1_P

PE0_TX1_N

PE0_TX2_P

PE0_TX2_N

PE0_TX3_P

PE0_TX3_N

PE0_TX4_P

PE0_TX4_N

PE0_TX5_P

PE0_TX5_N

PE0_TX6_P

PE0_TX6_N

PE0_TX7_P

PE0_TX7_N

PE0_TX8_P

PE0_TX8_N

PE0_TX9_P

PE0_TX9_N
PE0_TX10_P
PE0_TX10_N
PE0_TX11_P
PE0_TX11_N
PE0_TX12_P
PE0_TX12_N
PE0_TX13_P
PE0_TX13_N
PE0_TX14_P
PE0_TX14_N
PE0_TX15_P
PE0_TX15_N

PCI EXPRESS

PE0_REFCLK_P
PE0_REFCLK_N

PE1_REFCLK_P
PE1_REFCLK_N

PE2_REFCLK_P
PE2_REFCLK_N

PE3_REFCLK_P
PE3_REFCLK_N

PE4_REFCLK_P
PE4_REFCLK_N

PE5_REFCLK_P
PE5_REFCLK_N

PE6_REFCLK_P
PE6_REFCLK_N

PEX_RST0#

PE1_TX0_P

PE1_TX0_N

PE1_TX1_P

PE1_TX1_N

PE1_TX2_P

PE1_TX2_N

PE1_TX3_P

PE1_TX3_N

+AVDD0_PEX1
+AVDD0_PEX2
+AVDD0_PEX3
+AVDD0_PEX4
+AVDD0_PEX5
+AVDD0_PEX6
+AVDD0_PEX7
+AVDD0_PEX8

+AVDD0_PEX9
+AVDD0_PEX10
+AVDD0_PEX11
+AVDD0_PEX12
+AVDD0_PEX13

+AVDD1_PEX1

+AVDD1_PEX2

+AVDD1_PEX3

C5

D4

C4

B4

A4

A3

B3

B2

C1

D1

D2

E1

E2

F2

F3

F4

G3

H4

H3

H2

H1

J1

J2

J3

K2

K3

L4

L3

M4

M3

M2

M1

E11

D11

G11

F11

J11

J10

G13

F13

J13

H13

L14

K14

N14

M14

K11

D8

C8

B8

A8

A7

B7

B6

C6

Y12

AA12

AB12

M12

P12

R12

N12

T12

U12

AC12

AD12

V12

W12

M13

N13

P13

=PEG_R2D_C_P<0>
=PEG_R2D_C_N<0>
=PEG_R2D_C_P<1>
=PEG_R2D_C_N<1>
=PEG_R2D_C_P<2>
=PEG_R2D_C_N<2>
=PEG_R2D_C_P<3>
=PEG_R2D_C_N<3>
=PEG_R2D_C_P<4>
=PEG_R2D_C_N<4>
=PEG_R2D_C_P<5>
=PEG_R2D_C_N<5>
=PEG_R2D_C_P<6>
=PEG_R2D_C_N<6>
=PEG_R2D_C_P<7>
=PEG_R2D_C_N<7>
=PEG_R2D_C_P<8>
=PEG_R2D_C_N<8>
=PEG_R2D_C_P<9>
=PEG_R2D_C_N<9>
=PEG_R2D_C_P<10>
=PEG_R2D_C_N<10>
=PEG_R2D_C_P<11>
=PEG_R2D_C_N<11>
=PEG_R2D_C_P<12>
=PEG_R2D_C_N<12>
=PEG_R2D_C_P<13>
=PEG_R2D_C_N<13>
=PEG_R2D_C_P<14>
=PEG_R2D_C_N<14>
=PEG_R2D_C_P<15>
=PEG_R2D_C_N<15>

PEG_CLK100M_P
PEG_CLK100M_N

PCIE_CLK100M_MINI_P
PCIE_CLK100M_MINI_N

PCIE_CLK100M_FW_P
PCIE_CLK100M_FW_N

PCIE_CLK100M_EXCARD_P
PCIE_CLK100M_EXCARD_N

TP_PCIE_CLK100M_PE4P
TP_PCIE_CLK100M_PE4N

TP_PCIE_CLK100M_PE5P
TP_PCIE_CLK100M_PE5N

TP_PCIE_CLK100M_PE6P
TP_PCIE_CLK100M_PE6N

PCIE_RESET_L

PCIE_MINI_R2D_C_P
PCIE_MINI_R2D_C_N

PCIE_FW_R2D_C_P
PCIE_FW_R2D_C_N

PCIE_EXCARD_R2D_C_P
PCIE_EXCARD_R2D_C_N

TP_PCIE_PE4_R2D_CP
TP_PCIE_PE4_R2D_CN

=PP1V05_S0_MCP_PEX_AVDD0

=PP1V05_S0_MCP_PEX_AVDD1

4

206 mA (A01, AVDD0 & 1)

3

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

69 90

OUT

69 90

OUT

30 90

OUT

30 90

OUT

35 90

OUT

35 90

OUT

31 90

OUT

31 90

OUT

7

7

7

7

7

25

OUT

30 90

OUT

30 90

OUT

35 90

OUT

35 90

OUT

31 90

OUT

31 90

OUT

8

8

21

D

C

B

MCP PCIe Interfaces

SYNC_MASTER=T18_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

3

2

SCALE

NONE

051-8071

SHT

SYNC_DATE=06/06/2008

OF

17 98

1

A

REV.

B

87

www.vinafix.vn

D

=PP3V3_ENET_MCP_RMGT

8

18 23

C

=PP3V3_S5_MCP_GPIO

8

20

Interface Mode

MCP Signal

=MCP_HDMI_TXC_P/N
=MCP_HDMI_TXD_P/N<0>
=MCP_HDMI_TXD_P/N<1>
=MCP_HDMI_TXD_P/N<2>
=MCP_HDMI_DDC_CLK
=MCP_HDMI_DDC_DATA

B

=MCP_HDMI_HPD
DP_IG_AUX_CH_P/N

NOTE: 1M pull-down required on DP_IG_CA_DET if DP not used.
NOTE: 20K pull-down required on DP_HPD_DET.
NOTE: 1K pull-down required on DP_IG_AUX_CH_N if DP is used.

NOTE: HDMI port requires level-shifting. IFP interface can
be used to provide HDMI or dual-channel TMDS without
level-shifters.

TMDS/HDMI

TMDS_IG_TXC_P/N
TMDS_IG_TXD_P/N<0>
TMDS_IG_TXD_P/N<1>
TMDS_IG_TXD_P/N<2>
TMDS_IG_DDC_CLK
TMDS_IG_DDC_DATA
TMDS_IG_HPD
TP_DP_IG_AUX_CHP/N

LVDS: Power +VDD_IFPx at 1.8V
Dual-channel TMDS: Power +VDD_IFPx at 3.3V

DisplayPort

DP_IG_ML_P/N<3>
DP_IG_ML_P/N<2>
DP_IG_ML_P/N<1>
DP_IG_ML_P/N<0>
DP_IG_DDC_CLK
DP_IG_DDC_DATA
DP_IG_HPD
DP_IG_AUX_CH_P/N

A

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

8

76

43

R1810

49.9

1/16W
MF-LF

R1811

49.9

1/16W
MF-LF

R1820

47K

1/16W
MF-LF

7

BI

6

5

4

3

21

OMIT

U1400

MCP79-TOPO-B

BGA

(6 OF 11)

ENET_RXD<0>

32 92

IN

ENET_RXD<1>

32 92

IN

ENET_RXD<2>

32 92

IN

ENET_RXD<3>

32 92

IN

ENET_CLK125M_RXCLK

32 92

IN

ENET_RX_CTRL

32 92

IN

=MCP_MII_RXER

9

IN

=MCP_MII_COL

9

IN

=MCP_MII_CRS

9

1

1%

402

2

1

1%

402

2

IN

TP_ENET_INTR_L

7

PP1V05_ENET_MCP_PLL_MAC

23

5 mA (A01)

MCP_MII_COMP_VDD

92

MCP_MII_COMP_GND

92

TP_MCP_RGB_DAC_RSET

24

TP_MCP_RGB_DAC_VREF

24

C23

RGMII_RXD0

B23

RGMII_RXD1

E24

RGMII_RXD2

A24

RGMII_RXD3

A23

RGMII_RXC/MII_RXCLK

C22

RGMII_RXCTL/MII_RXDV

F23

MII_RXER/GPIO_36

B26

MII_COL/GPIO_20/MSMB_DATA

B22

MII_CRS/GPIO_21/MSMB_CLK

J22

RGMII_INTR/GPIO_35

T23

+V_DUAL_MACPLL

C27

MII_COMP_VDD

B27

MII_COMP_GND

C39

RGB_DAC_RSET

B38

RGB_DAC_VREF

+3.3V_DUAL_RMGT1
+3.3V_DUAL_RMGT2

+V_DUAL_RMGT1
+V_DUAL_RMGT2

LAN

RGMII_TXC/MII_TXCLK

RGMII_TXCTL/MII_TXEN

RGMII_PWRDWN/GPIO_37

RGMII_TXD0
RGMII_TXD1
RGMII_TXD2
RGMII_TXD3

RGMII_MDC

RGMII_MDIO

BUF_25MHZ

MII_RESET#

+V_RGB_DAC

+V_TV_DAC

DDC_DATA0

RGB_DAC_RED

MCP_TV_DAC_RSET

24 90

OUT

MCP_TV_DAC_VREF

24 90

OUT

MCP_CLK27M_XTALIN

24

1

5%

402

2

IN

MCP_CLK27M_XTALOUT

24

OUT

LPCPLUS_GPIO
DP_IG_CA_DET

81

IN

LVDS_IG_BKL_PWM

9

OUT

LVDS_IG_BKL_ON

9

OUT

LVDS_IG_PANEL_PWR

9

OUT

=MCP_HDMI_TXC_P

9

OUT

=MCP_HDMI_TXC_N

9

OUT

=MCP_HDMI_TXD_P<0>

9

OUT

=MCP_HDMI_TXD_N<0>

9

OUT

=MCP_HDMI_TXD_P<1>

9

OUT

=MCP_HDMI_TXD_N<1>

9

OUT

=MCP_HDMI_TXD_P<2>

9

OUT

=MCP_HDMI_TXD_N<2>

9

OUT

DP_IG_AUX_CH_P

81 90

OUT

DP_IG_AUX_CH_N

81 90

OUT

=DVI_HPD_GMUX_INT

9

IN

=MCP_HDMI_HPD

9

IN

=PP3V3R1V8_S0_MCP_IFP_VDD

8

24

190 mA (A01, 1.8V)

PP3V3_S0_MCP_VPLL

24

16 mA (A01)

=PP1V05_S0_MCP_HDMI_VDD

8

24

95 mA (A01)

MCP_HDMI_RSET

24 90

OUT

MCP_HDMI_VPROBE

24 90

OUT

(See below)

(See below)

8 mA
8 mA

E36

TV_DAC_RSET

A35

TV_DAC_VREF

C38

XTALIN_TV

D38

XTALOUT_TV

E16

GPIO_6/FERR*/IGPU_GPIO_6

B15

GPIO_7/NFERR*/IGPU_GPIO_7

G39

LCD_BKL_CTL/GPIO_57

E37

LCD_BKL_ON/GPIO_59

F40

LCD_PANEL_PWR/GPIO_58

D35

HDMI_TXC_P/ML0_LANE3_P

E35

HDMI_TXC_N/ML0_LANE3_N

G35

HDMI_TXD0_P/ML0_LANE2_P

F35

HDMI_TXD0_N/ML0_LANE2_N

F33

HDMI_TXD1_P/ML0_LANE1_P

G33

HDMI_TXD1_N/ML0_LANE1_N

J33

HDMI_TXD2_P/ML0_LANE0_P

H33

HDMI_TXD2_N/ML0_LANE0_N

D43

DP_AUX_CH0_P

C43

DP_AUX_CH0_N

C31

HPLUG_DET2/GPIO_22

F31

HPLUG_DET3

M27

+VDD_IFPA

M26

+VDD_IFPB

M28

+V_PLL_IFPAB

M29

+V_PLL_HDMI

T25

+VDD_HDMI

J31

HDMI_RSET

J30

HDMI_VPROBE

DACS

TV / Component
C / Pr
Y / Y
Comp / Pb

RGB_DAC_GREEN

RGB_DAC_BLUE

RGB_DAC_HSYNC
RGB_DAC_VSYNC

RGB ONLY

TV_DAC_RED

TV_DAC_GREEN

TV_DAC_BLUE

TV_DAC_HSYNC/GPIO_44
TV_DAC_VSYNC/GPIO_45

IFPA_TXC_P
IFPA_TXC_N

IFPA_TXD0_P
IFPA_TXD0_N
IFPA_TXD1_P
IFPA_TXD1_N
IFPA_TXD2_P
IFPA_TXD2_N
IFPA_TXD3_P
IFPA_TXD3_N

IFPB_TXC_P
IFPB_TXC_N

IFPB_TXD4_P
IFPB_TXD4_N
IFPB_TXD5_P
IFPB_TXD5_N
IFPB_TXD6_P
IFPB_TXD6_N
IFPB_TXD7_P

FLAT PANEL

IFPB_TXD7_N

DDC_CLK2/GPIO_23

DDC_DATA2/GPIO_24

DDC_DATA3

IFPAB_RSET

IFPAB_VPROBE

MII_VREF

DDC_CLK0

DDC_CLK3

J24

K24

U23

V23

E28

B24

C24

C25

D25

D24

C26

D21

C21

G23

E23

J23

J32

K32

B31

A31

B39

A39

B40

A40

A41

A36

B36

C36

D36

C37

B35

C35

B32

A32

D32

C32

D33

C33

B34

C34

L31

K31

J29

H29

L29

K29

L30

K30

N30

M30

C30

B30

D31

E31

E32

G31

GPIOs 57-59 (if LCD panel is used):

In MCP79 these pins have undocumented internal
pull-ups (~10K to 3.3V S0). To ensure pins are low
by default, pull-downs (1K or stronger) must be used.

=DVI_HPD_GMUX_INT:

Alias to DVI_HPD for systems using IFP for DVI.
Alias to GMUX_INT for systems with GMUX.
Alias to HPLUG_DET2 for other systems.
Pull-down (20k) required in all cases.

5

4

=PP3V3_ENET_MCP_RMGT

=PP1V05_ENET_MCP_RMGT

MCP_MII_VREF

ENET_TXD<0>
ENET_TXD<1>
ENET_TXD<2>
ENET_TXD<3>

ENET_CLK125M_TXCLK
ENET_TX_CTRL

ENET_MDC
ENET_MDIO

TP_ENET_PWRDWN_L

MCP_CLK25M_BUF0_R

ENET_RESET_L

PP3V3_S0_MCP_DAC

103 mA
103 mA

MCP_DDC_CLK0
MCP_DDC_DATA0

TP_MCP_RGB_RED
TP_MCP_RGB_GREEN
TP_MCP_RGB_BLUE

TP_MCP_RGB_HSYNC
TP_MCP_RGB_VSYNC

CRT_IG_R_C_PR
CRT_IG_G_Y_Y
CRT_IG_B_COMP_PB

CRT_IG_HSYNC
CRT_IG_VSYNC

LVDS_IG_A_CLK_P
LVDS_IG_A_CLK_N

LVDS_IG_A_DATA_P<0>
LVDS_IG_A_DATA_N<0>
LVDS_IG_A_DATA_P<1>
LVDS_IG_A_DATA_N<1>
LVDS_IG_A_DATA_P<2>
LVDS_IG_A_DATA_N<2>
LVDS_IG_A_DATA_P<3>
LVDS_IG_A_DATA_N<3>

LVDS_IG_B_CLK_P
LVDS_IG_B_CLK_N

LVDS_IG_B_DATA_P<0>
LVDS_IG_B_DATA_N<0>
LVDS_IG_B_DATA_P<1>
LVDS_IG_B_DATA_N<1>
LVDS_IG_B_DATA_P<2>
LVDS_IG_B_DATA_N<2>
LVDS_IG_B_DATA_P<3>
LVDS_IG_B_DATA_N<3>

LVDS_IG_DDC_CLK
LVDS_IG_DDC_DATA

=MCP_HDMI_DDC_CLK
=MCP_HDMI_DDC_DATA

MCP_IFPAB_RSET
MCP_IFPAB_VPROBE

1

R1850

10K

5%
1/16W
MF-LF
402

2

8

18 23

83 mA (A01)

8

23

131 mA (A01)

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

7

OUT

OUT

24

206 mA (A01)

24

24

24

24

24

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

OUT

BI

OUT

OUT

3

23

32 92

32 92

32 92

32 92

32 92

32 92

32 92

32 92

1

5%

402

2

=PP3V3_S0_MCP_GPIO

1

R1861

100K

5%
1/16W
MF-LF
402

2

33 92

32 92

24 90

24 90

24 90

24 90

24 90

84 90

84 90

84 90

84 90

84 90

84 90

84 90

84 90

9

90

9

90

WF: IFP is capable of LVDS (1.8V) or TMDS (3.3V), need aliases

9

90

9

90

84 90

84 90

84 90

84 90

84 90

84 90

9

90

9

90

81

81

9

9

24 90

24 90

R1860

100K

1/16W
MF-LF

APPLE INC.

2

Network Interface Select

Interface

RGMII

MII 0

NOTE: All Apple products set strap to
MII, RGMII products will enable
feature via software. This
avoids a leakage issue since
MCP79 requires a S5 pull-up.

8

19 21

RGB DAC Disable:

Okay to float all RGB_DAC signals.
DDC_CLK0/DDC_DATA0 pull-ups still required.

TV DAC Disable:

Okay to float all TV_DAC signals.
Okay to float XTALIN_TV and XTALOUT_TV.
DDC_CLK0/DDC_DATA0 pull-ups still required.

ENET_TXD<0>

MCP Ethernet & Graphics

SYNC_MASTER=T18_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

051-8071

SHT

1

SYNC_DATE=06/06/2008

OF

18 98

1

D

C

B

A

REV.

B

87

www.vinafix.vn

6

5

4

3

21

OMIT

8.2K

8.2K

8.2K

8.2K

8.2K

D

NONE

DRAWING NUMBER

=PP3V3_S0_MCP_GPIO

8

18 21

21

21

21

21

21

051-8071

SHT

5%

5%

5%

5%

1/16W MF-LF

5%

SYNC_DATE=06/06/2008

402

MF-LF1/16W

402

MF-LF1/16W

402

MF-LF1/16W

402

402

MF-LF1/16W

D

C

B

A

REV.

B

OF

9819

U1400

MCP79-TOPO-B

BGA

Int PU

(7 OF 11)

PCI_GNT2#/GPIO_41/RS232_DTR#
PCI_GNT3#/GPIO_39/RS232_RTS#

PCI_GNT4#/GPIO_53/RS232_SOUT#

PCI_GNT1#/FANCTL2

PCI_PERR#/GPIO_43/RS232_DCD#

PCI_PME#/GPIO_30

Int PU (S5)

LPC_PWRDWN#/GPIO_54/EXT_NMI#

LPC PCIGND

PCI_GNT0#

PCI_CBE0#
PCI_CBE1#
PCI_CBE2#
PCI_CBE3#

PCI_DEVSEL#

PCI_FRAME#

PCI_IRDY#

PCI_PAR

PCI_SERR#
PCI_STOP#

PCI_RESET0#
PCI_RESET1#

PCI_CLK0
PCI_CLK1
PCI_CLK2

PCI_CLKIN

LPC_FRAME#

LPC_RESET0#

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_CLK0

GND98

GND99
GND100
GND101
GND102
GND103
GND104
GND105
GND106
GND107
GND108
GND109
GND110
GND111
GND112
GND113
GND114
GND115
GND116
GND117
GND118
GND119
GND120
GND121
GND122
GND123
GND124
GND125
GND126
GND127
GND128
GND129
GND130

R3

U10

R4

U11

P3

AA3

AA6

AA11

W10

AA9

Y4

AA10

Y1

AB9

AA7

Y2

T1

R10

R11

R6

R7

R8

R9

AD4

AE12

AE5

AD3

AD2

AD1

AD5

AE9

Y26

Y27

AB18

H34

AB20

AB21

AB23

AB24

AB25

AB26

AB27

AB28

AB34

AB37

AB4

AB40

AC22

AC36

AC40

AB33

AC5

AD16

AD17

AD18

AD19

AD20

AD24

AD25

AD26

AD27

AD28

AD33

AD34

TP_PCI_GNT0_L
TP_PCI_GNT1_L
GMUX_JTAG_TMS
GMUX_JTAG_TDI
MCP_RS232_SOUT_L

TP_PCI_C_BE_L<0>
TP_PCI_C_BE_L<1>
TP_PCI_C_BE_L<2>
TP_PCI_C_BE_L<3>

TP_PCI_DEVSEL_L
TP_PCI_FRAME_L
TP_PCI_IRDY_L
TP_PCI_PAR
TP_PCI_PERR_L
TP_PCI_SERR_L
TP_PCI_STOP_L

PM_LATRIGGER_L

MEM_VTT_EN_R
TP_PCI_RESET1_L

TP_PCI_CLK0
TP_PCI_CLK1
PCI_CLK33M_MCP_R

91

PCI_CLK33M_MCP

91

LPC_FRAME_R_L

43

LPC_PWRDWN_L

7

7

9

OUT

9

OUT

19

OUT

7

7

7

7

7

7

7

7

7 7

7

7

13

OUT

25

OUT

7

7

7

1

R1910

22

5%
1/16W
MF-LF
402

2

PLACEMENT_NOTE=Place close to pin R8

R1960

LPC_RESET_L

LPC_AD_R<0>
LPC_AD_R<1>
LPC_AD_R<2>
LPC_AD_R<3>

R1950
R1951
R1952
R1953

LPC_CLK33M_SMC_R

1

R1961

10K

5%
1/16W
MF-LF
402

2

Strap for Boot ROM Selection (See HDA_SDOUT)

22

22
22

21

5%

21

5%

21

5%

21

5%

21

5%

1/16W MF-LF

1/16W MF-LF22402

1/16W MF-LF22402

1/16W MF-LF

MF-LF1/16W

402

402

402

LPC_FRAME_L

LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>

7

41 43 84 91

OUT

7

41 43

OUT

25 84 91

OUT

7

41 43 84 91

BI

7

41 43 84 91

BI

7

41 43 84 91

BI

7

41 43 84 91

BI

25 91

OUT

PCI_REQ0_L

19 91

PCI_REQ1_L

19 91

CRTMUX_SEL_TV_L

19

OUT

AUD_IPHS_SWITCH_EN

9

58

OUT

MCP_RS232_SIN_L

19

IN

D

C

41 43

41 43

13 91

13 91

13 91

13 91

13 91

13 91

13 91

13 91

7

35

7

BI

BI

BI

BI

BI

BI

BI

BI

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

IN

IN

7

BI

MCP_DEBUG<0>
MCP_DEBUG<1>
MCP_DEBUG<2>
MCP_DEBUG<3>
MCP_DEBUG<4>
MCP_DEBUG<5>
MCP_DEBUG<6>
MCP_DEBUG<7>
TP_PCI_AD<8>
TP_PCI_AD<9>
TP_PCI_AD<10>
TP_PCI_AD<11>
TP_PCI_AD<12>
TP_PCI_AD<13>
TP_PCI_AD<14>
TP_PCI_AD<15>
TP_PCI_AD<16>
TP_PCI_AD<17>
TP_PCI_AD<18>
TP_PCI_AD<19>
TP_PCI_AD<20>
TP_PCI_AD<21>
TP_PCI_AD<22>
TP_PCI_AD<23>
TP_PCI_AD<24>
TP_PCI_AD<25>
TP_PCI_AD<26>
TP_PCI_AD<27>
TP_PCI_AD<28>
TP_PCI_AD<29>
TP_PCI_AD<30>
TP_PCI_AD<31>

TP_PCI_INTW_L
TP_PCI_INTX_L
TP_PCI_INTY_L
TP_PCI_INTZ_L

TP_PCI_TRDY_L

PM_CLKRUN_L

FW_PME_L
TP_LPC_DRQ0_L
LPC_SERIRQ

B

A

T2

PCI_REQ0#

V9

PCI_REQ1#/FANRPM2

T3

PCI_REQ2#/GPIO_40/RS232_DSR#

U9

PCI_REQ3#/GPIO_38/RS232_CTS#

T4

PCI_REQ4#/GPIO_52/RS232_SIN#

AC3

PCI_AD0

AE10

PCI_AD1

AC4

PCI_AD2

AE11

PCI_AD3

AB3

PCI_AD4

AC6

PCI_AD5

AB2

PCI_AD6

AC7

PCI_AD7

AC8

PCI_AD8

AA2

PCI_AD9

AC9

PCI_AD10

AC10

PCI_AD11

AC11

PCI_AD12

AA1

PCI_AD13

AA5

PCI_AD14

Y5

PCI_AD15

W3

PCI_AD16

W6

PCI_AD17

W4

PCI_AD18

W7

PCI_AD19

V3

PCI_AD20

W8

PCI_AD21

V2

PCI_AD22

W9

PCI_AD23

U3

PCI_AD24

W11

PCI_AD25

U2

PCI_AD26

U5

PCI_AD27

U1

PCI_AD28

U6

PCI_AD29

T5

PCI_AD30

U7

PCI_AD31

P2

PCI_INTW#

N3

PCI_INTX#

N2

PCI_INTY#

N1

PCI_INTZ#

Y3

PCI_TRDY#

AD11

PCI_CLKRUN#/GPIO_42

AE2

LPC_DRQ1#/GPIO_19

AE1

AE6

U24

U26

U39

U4

U8

V16

V17

V18

V20

V22

V24

V26

V27

V28

V33

V37

V4

V40

V7

W20

W22

W24

W36

W40

W43

Y16

Y17

Y18

Y19

Y20

Y22

Y24

Y25

LPC_DRQ0#
LPC_SERIRQ

GND65
GND66
GND67
GND68
GND69
GND70
GND71
GND72
GND73
GND74
GND75
GND76
GND77
GND78
GND79
GND80
GND81
GND82
GND83
GND84
GND85
GND86
GND87
GND88
GND89
GND90
GND91
GND92
GND93
GND94
GND95
GND96
GND97

Int PU
Int PU

MCP_RS232_SOUT_L

19

PCI_REQ0_L

19 91

PCI_REQ1_L

19 91

CRTMUX_SEL_TV_L

19

MCP_RS232_SIN_L

19

SYNC_MASTER=T18_MLB

APPLE INC.

R1989

R1990
R1991
R1992
R1994

MCP PCI & LPC

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

SCALE

8

76

5

4

3

2

1

87

www.vinafix.vn

D

C

B

A

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

8

76

6

SATA_HDD_R2D_C_P

38 90

OUT

SATA_HDD_R2D_C_N

38 90

OUT

SATA_HDD_D2R_N

38 90

IN

SATA_HDD_D2R_P

38 90

IN

SATA_ODD_R2D_C_P

38 90

OUT

SATA_ODD_R2D_C_N

38 90

OUT

SATA_ODD_D2R_N

38 90

IN

SATA_ODD_D2R_P

38 90

IN

TP_SATA_C_R2D_CP

7

TP_SATA_C_R2D_CN

7

TP_SATA_C_D2RN

7

TP_SATA_C_D2RP

7

TP_SATA_D_R2D_CP

7

TP_SATA_D_R2D_CN

7

TP_SATA_D_D2RN

7

TP_SATA_D_D2RP

7

TP_SATA_E_R2D_CP

7

TP_SATA_E_R2D_CN

7

TP_SATA_E_D2RN

7

TP_SATA_E_D2RP

7

TP_SATA_F_R2D_CP

7

TP_SATA_F_R2D_CN

7

TP_SATA_F_D2RN

7

TP_SATA_F_D2RP

7

TP_MCP_SATALED_L

7

PP1V05_S0_MCP_PLL_SATA

23

84 mA (A01)

=PP1V05_S0_MCP_SATA_DVDD0

8

43 mA (A01, DVDD0 & 1)

Minimum 1.025V for Gen2 support

=PP1V05_S0_MCP_SATA_DVDD1

9

=PP1V05_S0_MCP_SATA_AVDD0

8

127 mA (A01, AVDD0 & 1)

Minimum 1.025V for Gen2 support

=PP1V05_S0_MCP_SATA_AVDD1

9

MCP_SATA_TERMP

90

1

R2010

2

2.49K

1%
1/16W
MF-LF
402

If all SATA_Ax & Bx pins are not used, ground DVDD0_SATA and AVDD0_SATA.
If all SATA_Cx pins are not used, ground DVDD1_SATA and AVDD1_SATA.

5

AJ7

SATA_A0_TX_P

AJ6

SATA_A0_TX_N

AJ5

SATA_A0_RX_N

AJ4

SATA_A0_RX_P

AJ11

SATA_A1_TX_P

AJ10

SATA_A1_TX_N

AJ9

SATA_A1_RX_N

AK9

SATA_A1_RX_P

AK2

SATA_B0_TX_P

AJ3

SATA_B0_TX_N

AJ2

SATA_B0_RX_N

AJ1

SATA_B0_RX_P

AM4

SATA_B1_TX_P

AL3

SATA_B1_TX_N

AL4

SATA_B1_RX_N

AK3

SATA_B1_RX_P

AN1

SATA_C0_TX_P

AM1

SATA_C0_TX_N

AM2

SATA_C0_RX_N

AM3

SATA_C0_RX_P

AP3

SATA_C1_TX_P

AP2

SATA_C1_TX_N

AN3

SATA_C1_RX_N

AN2

SATA_C1_RX_P

E12

SATA_LED#

AE16

+V_PLL_SATA

AF19

+DVDD0_SATA1

AG16

+DVDD0_SATA2

AG17

+DVDD0_SATA3

AG19

+DVDD0_SATA4

AH17

+DVDD1_SATA1

AH19

+DVDD1_SATA2

AJ12

+AVDD0_SATA1

AN11

+AVDD0_SATA2

AK12

+AVDD0_SATA3

AK13

+AVDD0_SATA4

AL12

+AVDD0_SATA5

AM11

+AVDD0_SATA6

AM12

+AVDD0_SATA7

AN12

+AVDD0_SATA8

AL13

+AVDD0_SATA9

AN14

+AVDD1_SATA1

AL14

+AVDD1_SATA2

AM13

+AVDD1_SATA3

AM14

+AVDD1_SATA4

AE3

SATA_TERMP

5

OMIT

U1400

MCP79-TOPO-B

BGA

(8 OF 11)

SATA

USB_OC2#/GPIO_27/MGPIO
USB_OC3#/GPIO_28/MGPIO

USB

USB_OC0#/GPIO_25
USB_OC1#/GPIO_26

USB_RBIAS_GND

4

USB0_P
USB0_N

USB1_P
USB1_N

USB2_P
USB2_N

USB3_P
USB3_N

USB4_P
USB4_N

USB5_P
USB5_N

USB6_P
USB6_N

USB7_P
USB7_N

USB8_P
USB8_N

USB9_P
USB9_N

USB10_P
USB10_N

USB11_P
USB11_N

+V_PLL_USB

GND131
GND132
GND133
GND134
GND135
GND136
GND137
GND138
GND139
GND140
GND141
GND142
GND143
GND144
GND145
GND146
GND147
GND148
GND149
GND150
GND151
GND152
GND153
GND154
GND155
GND156
GND157
GND158
GND159
GND160

4

External A

C29

D29

C28

D28

A28

B28

F29

G29

K27

L27

J26

J27

F27

G27

D27

E27

K25

L25

H25

J25

F25

G25

K23

L23

L21

K21

J21

H21

L28

A27

AD35

AD37

AD38

AE22

AE24

AE39

AE4

AD6

AF16

AF17

AF18

AF20

AF22

AF26

AF27

AF28

AF33

AF34

AF37

AF40

AG18

AG20

AG22

AG26

AG36

AG40

AH18

AH20

AH22

AH24

USB_EXTA_P
USB_EXTA_N

AirPort (PCIe Mini-Card)

USB_MINI_P
USB_MINI_N

External D

USB_EXTD_P
USB_EXTD_N

Camera

USB_CAMERA_P
USB_CAMERA_N

IR

USB_IR_P
USB_IR_N

Geyser Trackpad/Keyboard

USB_TPAD_P
USB_TPAD_N

Bluetooth

USB_BT_P
USB_BT_N

External B

USB_EXTB_P
USB_EXTB_N

ExpressCard

USB_EXCARD_P
USB_EXCARD_N

External C

USB_EXTC_P
USB_EXTC_N

TP_USB_10P
TP_USB_10N

TP_USB_11P
TP_USB_11N

PP3V3_S0_MCP_PLL_USB

MCP_USB_RBIAS_GND

91

19 mA (A01)

R2060

1/16W
MF-LF

806

3

39 91

BI

39 91

BI

9

91

BI

9

91

BI

9

91

BI

9

91

BI

30 91

BI

30 91

BI

40 91

BI

40 91

BI

49 91

BI

49 91

BI

30 91

BI

30 91

BI

39 91

BI

39 91

BI

31 91

BI

31 91

BI

8.2K

1/16W
MF-LF

1

R2051

8.2K

5%
1/16W
MF-LF
402

2

1

R2052

5%

402

2

8.2K

1/16W
MF-LF

5%

402

91 96 98

BI

91 96 98

BI

7

7

7

23

1

1%

402

2

R2050

21

=PP3V3_S5_MCP_GPIO

1

R2053

8.2K

5%
1/16W
MF-LF
402

2

1

2

USB_EXTA_OC_L
USB_EXTB_OC_L
USB_EXTC_OC_L
EXCARD_OC_L

8

18

39

IN

39

IN

98

IN

31 42

IN

D

C

B

MCP SATA & USB

SYNC_MASTER=T18_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

3

2

SCALE

NONE

051-8071

SHT

SYNC_DATE=06/06/2008

OF

1

A

REV.

B

9820

87

www.vinafix.vn

6

5

4

3

21

OMIT

U1400

MCP79-TOPO-B

BGA

(9 OF 11)

D

=PP3V3R1V5_S0_MCP_HDA

8

21 23

1

R2110

49.9

1%
1/16W
MF-LF
402

2

PP3V3_G3_RTC

22 25

1

1/16W
MF-LF

1

R2121

49.9K

1%

1%
1/16W
MF-LF

402

402

2

2

R2120

C

49.9K

HDA_SDIN0

53 91

IN

TP_MLB_RAM_SIZE

7

TP_MLB_RAM_VENDOR

7

(MXM_OK for MXM systems)

MCP_HDA_PULLDN_COMP

91

PP1V05_S0_MCP_PLL_NV

23

37 mA (A01)

=SPI_CS1_R_L_USE_MLB

9

43

OUT

SMC_ADAPTER_EN

33 36 41 42

IN

TP_SB_A20GATE

7

TP_MCP_KBDRSTIN_L

7

SMC_WAKE_SCI_L

41

IN

SMC_RUNTIME_SCI_L

41

IN

20 mA
17 mA

SM_INTRUDER_L

TP_MCP_LID_L
PM_BATLOW_L

41

IN

PM_DPRSLPVR

61 88

IN

PM_PWRBTN_L

41

IN

PM_SYSRST_DEBOUNCE_L

25

IN

RTC_RST_L

PM_RSMRST_L

41

IN

MCP_PS_PWRGD

25

IN

MCP_CPU_VLD

IN

JTAG_MCP_TDI

6

13

IN

JTAG_MCP_TDO

6

OUT

JTAG_MCP_TMS

6

13

IN

JTAG_MCP_TRST_L

6

13

IN

JTAG_MCP_TCK

6

13

B

IN

25

IN

25

OUT

25

IN

25

OUT

MCP_CLK25M_XTALIN
MCP_CLK25M_XTALOUT

RTC_CLK32K_XTALIN
RTC_CLK32K_XTALOUT

R2150

1/16W
MF-LF

10K

1

5%

402

2

1

R2151

100K

5%
1/16W
MF-LF
402

2

G15

HDA_SDATA_IN0

Int PD

J14

HDA_SDATA_IN1_GPIO_2/PS2_KB_CLK

Int PD

J15

HDA_SDATA_IN2_GPIO_3/PS2_KB_DATA

Int PD

A15

HDA_PULLDN_COMP

AE18

+V_PLL_NV_H

AE17

+V_PLL_SP_SPREF

L24

GPIO_1/PWRDN_OK/SPI_CS1

L26

GPIO_12_SUS_STAT_ACCLMTR_EXT_TRIG_L

K13

A20GATE

L13

KBRDRSTIN*

C19

SIO_PME*

C18

EXT_SMI/GPIO_32*

B20

INTRUDER*

M25

LID*

M24

LLB*

M22

CPU_DPRSLPVR

C16

PWRBTN*

D16

RSTBTN*

C20

RTC_RST*

D20

PWRGD_SB

E20

PS_PWRGD

Int PU
Int PU
Int PU (S5)

Int PU (S5)
Int PU (S5)

Int PU (S5)
Int PU

Int PU (S5)

CPU_VLD

E19

JTAG_TDI

F19

JTAG_TDO

J19

JTAG_TMS

J18

JTAG_TRST*

G19

JTAG_TCK

A16

XTALIN

B16

XTALOUT

A19

XTALIN_RTC

B19

XTALOUT_RTC

Int PU

Int PU

HDA

HDA_DOCK_EN*_GPIO_4/PS2_MS_CLK

HDA_DOCK_RST*_GPIO_5/PS2_MS_DATA

(MGPIO2)

MISC

(MGPIO3)

+V_DUAL_HDA1
+V_DUAL_HDA2

HDA_SDATA_OUT

HDA_BITCLK

HDA_RESET*

HDA_SYNC

SLP_RMGT*

THERM_DIODE_P
THERM_DIODE_N

MCP_VID0/GPIO_13
MCP_VID1/GPIO_14
MCP_VID2/GPIO_15

SMB_CLK0

SMB_DATA0

SMB_CLK1/MSMB_CLK

SMB_DATA1/MSMB_DATA

SMB_ALERT*/GPIO_64

FANRPM0/GPIO_60
FANCTL0/GPIO_61
FANRPM1/GPIO_63
FANCTL1/GPIO_62

CPUVDD_EN

SPI_CS0/GPIO_10
SPI_CLK/GPIO_11

SPI_DI/GPIO_8
SPI_DO/GPIO_9

SUS_CLK/GPIO_34

BUF_SIO_CLK

TEST_MODE_EN

PKG_TEST

SLP_S3*

SLP_S5*

SPKR

J16

K16

F15

E15

K15

L15

K17

L17

G17

J17

H17

B11

C11

L20

M20

M21

C13

L19

K19

G21

F21

M23

B12

A12

D12

C12

D17C17

C14

D13

C15

B14

B18

AE7

K22

L22

=PP3V3R1V5_S0_MCP_HDA

1

R2160

8.2K

5%
1/16W
MF-LF
402

2

HDA_SDOUT_R

21 91

HDA_BIT_CLK_R

21 91

HDA_RST_R_L

21 91

HDA_SYNC_R

21 91

MCP_GPIO_4
AUD_I2C_INT_L

PM_SLP_S3_L
PM_SLP_RMGT_L
PM_SLP_S4_L

MCP_THMDIODE_P
MCP_THMDIODE_N

MCP_VID<0>
MCP_VID<1>
MCP_VID<2>

MCP_SPKR

SMBUS_MCP_0_CLK
SMBUS_MCP_0_DATA
SMBUS_MCP_1_CLK
SMBUS_MCP_1_DATA
AP_PWR_EN

MEM_EVENT_L
ODD_PWR_EN_L
SMC_IG_THROTTLE_L
ARB_DETECT

MCP_CPUVDD_EN

SPI_CS0_R_L
SPI_CLK_R
SPI_MISO
SPI_MOSI_R

PM_CLK32K_SUSCLK_R
TP_MCP_BUF_SIO_CLK

MCP_TEST_MODE_EN

1

R2163

10K

5%
1/16W
MF-LF
402

2

8

21 23

7 mA (A01)

R2171

22

5%
1/16W
MF-LF

402

R2173

22

5%
1/16W
MF-LF

402

21

21

21

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

IN

21

OUT

OUT

OUT

IN

OUT

OUT

7

1

2

BI

BI

R2190

1K

1%
1/16W
MF-LF
402

R2170

22

21

5%
1/16W
MF-LF

402

R2172

22

21

5%
1/16W
MF-LF

402

21 58

7

33 36 41 67 82 84

9

39 41 42 67

47 96

47 96

21 64

21 64

21 64

7

13 44 91

7

13 44 91

44 91

44 91

21 30 33

21 27 28 41

38

21 42

25 25

43 91

43 91

43 91

43 91

25 91

HDA_SDOUT

HDA_BIT_CLK

HDA_RST_L

HDA_SYNC

OUT

OUT

OUT

OUT

=PP3V3_S0_MCP

BOOT_MODE_SAFE

1

R2180

10K

5%
1/16W
MF-LF
402

2

9

OUT

BOOT_MODE_USER

1

R2181

10K

USER mode: Normal

5%
1/16W

SAFE mode: For ROMSIP

MF-LF
402

2

recovery

Connects to SMC for
automatic recovery.

53 91

9

53 91

53 91

D

BIOS Boot Select

91

I/F

LPC

PCI

SPI0

SPI1

SPI0 = SPI_CS0_L, SPI1 = SPI_CS1_L

R1961 and R2160 selects SPI0 ROM by
default, LPC+ debug card pulls
LPC_FRAME# high for SPI1 ROM override.

NOTE: MCP79 does not support FWH, only
LPC ROMs. So Apple designs will
not use LPC for BootROM override.

NOTE: MCP79 rev A01 does not support

8

22 23

SPI1 option. Rev B01 will.

HDA_SDOUT

LPC_FRAME#

0

0

1

1

BUF_SIO_CLK Frequency

Frequency

24 MHz

14.31818 MHz

HDA_SYNC

0

1

0

1

C

1

0

SPI Frequency Select

Frequency

31 MHz

0

42 MHz 0

25 MHz

1 MHz

NOTE: Straps not provided on this page.

1

1

SPI_CLKSPI_DO

0

1

0

1

B

HDA Output Caps

For EMI Reduction on HDA interface

HDA_SDOUT_R
HDA_BIT_CLK_R

HDA_RST_R_L
HDA_SYNC_R

C2172

10PF

1

5%

50V

2

CERM

402

1

C2173

10PF

5%
50V

2

CERM
402

1

A

C2170

10PF

5%

50V

2

CERM

402

1

C2171

10PF

5%
50V

2

CERM
402

21 91

21 91

21 91

21 91

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

8

76

1

R2140

10K

5%
1/16W
MF-LF
402

2

1

R2141

10K

5%
1/16W
MF-LF
402

2

1

R2142

10K

5%
1/16W
MF-LF
402

2

=PP3V3_S0_MCP_GPIO

1

R2143

10K

5%
1/16W
MF-LF
402

2

MCP_GPIO_4
AUD_I2C_INT_L
MEM_EVENT_L
SMC_IG_THROTTLE_L

ARB_DETECT

1

R2147

100K

5%
1/16W
MF-LF
402

2

5

8

18 19

21

21 58

21 27 28 41

21 42

21

=PP3V3_S3_MCP_GPIO

2

R2154

100K

5%
1/16W
MF-LF
402

1

AP_PWR_EN

MCP_VID<0>
MCP_VID<1>
MCP_VID<2>

1

R2155

22K

5%
1/16W
MF-LF
402

2

1

R2156

22K

5%
1/16W
MF-LF
402

2

1

R2157

22K

5%
1/16W
MF-LF
402

2

4

21 30 33

21 64

21 64

21 64

3

8

MCP HDA & MISC

051-8071

SHT

SYNC_DATE=06/06/2008

OF

21 98

1

A

REV.

B

SYNC_MASTER=T18_MLB

APPLE INC.

2

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

87

www.vinafix.vn

6

5

4

3

21

OMIT

U1400

MCP79-TOPO-B

BGA

AH26

AH33

AH34

AH37

AH38

AJ39

D

C

B

A

AK10

AK33

AK34

AK37

AK40

AL36

AL40

AM10

AM16

AM18

AM20

AM22

AM24

AM26

AM30

AM34

AM35

AM37

AM38

AP26

AN28

AN30

AN39

AP10

AU26

AP14

AU14

AP28

AP32

AP34

AP36

AP37

AP40

AW23

AR28

AR32

AR40

AT10

AR12

AT13

AT29

AT33

AY21

AY22

AU12

AU28

AP33

AU32

AR30

AU36

AU38

AV28

AV32

AV36

AW11

AR43

AW43

AY10

AV12

AY30

AY33

AY34

AY37

AY38

AY41

(11 OF 11)

GND161
GND162
GND163
GND164
GND165
GND166

AJ8

GND167
GND168
GND169
GND170
GND171

AK4

GND172
GND173
GND174
GND175

AL5

GND176
GND177
GND178
GND179
GND180
GND181
GND182
GND183
GND184
GND185
GND186
GND187
GND188

AM5

GND189

AM6

GND190

AM7

GND191

AM9

GND192
GND193
GND194
GND195
GND196

AN4

GND197

Y7

GND198
GND199
GND200
GND201
GND202
GND203
GND204
GND205
GND206
GND207

AP4

GND208
GND209

AP7

GND210
GND211
GND212
GND213
GND214
GND215
GND216
GND217
GND218
GND219

AT6

GND220

AT7

GND221

AT9

GND222
GND223
GND224

L12

GND225
GND226
GND227
GND228
GND229
GND230
GND231
GND232

AU4

GND233

G28

GND234

F20

GND235
GND236
GND237
GND238

AV4

GND239

AV7

GND240
GND241

G20

GND242
GND243
GND244
GND245
GND246
GND247
GND248
GND249
GND250 GND342
GND251
GND252

GND253
GND254
GND255
GND256
GND257
GND258
GND259
GND260
GND261
GND262
GND263
GND264
GND265
GND266
GND267
GND268
GND269
GND270
GND271
GND272
GND273
GND274
GND275
GND276
GND277
GND278
GND279
GND280
GND281
GND282
GND283
GND284
GND285
GND286
GND287
GND288
GND289
GND290
GND291
GND292
GND293
GND294
GND295
GND296
GND297
GND298
GND299
GND300
GND301

GND

GND302
GND303
GND304
GND305
GND306
GND307
GND308
GND309
GND310
GND311
GND312
GND313
GND314
GND315
GND316
GND317
GND318
GND319
GND320
GND321
GND322
GND323
GND324
GND325
GND326
GND327
GND328
GND329
GND330
GND331
GND332
GND333
GND334
GND335
GND336
GND337
GND338
GND339
GND340
GND341

GND343

AV40

BA1

BA4

AW31

AY6

L35

BC33

BC37

BC41

AY14

BC5

C2

D10

D14

D15

D18

D19

D22

D23

D26

D30

D37

D6

E13

E17

E21

E25

E29

E33

F12

F16

F32

F8

G10

G12

G14

G16

BC12

G22

G24

AW20

G34

G4

G43

G6

G8

H11

H15

AW35

H23

AN8

G40

J12

J8

K10

K12

K18

K26

K37

K4

K40

K8

AU1

L40

L43

L5

M10

M34

M35

M37

Y28

Y33

Y34

Y35

Y37

Y38

AB17

AB16

AN26

AD7

M11

AA4

AB19

AY13

P11

Y6

T11

V11

Y11

AH16

T22

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

8

76

=PPVCORE_S0_MCP

8

23 45

23065 mA (A01, 1.2V)
16996 mA (A01, 1.0V)

PP3V3_G3_RTC

21 25

10 uA (G3)
80 uA (S0)

OMIT

U1400

MCP79-TOPO-B

BGA

AA25

AC23

AH12

AG10

AA16

AA26

AA27

AA28

AC16

AC17

AC18

AC19

AC20

AC21

AA17

AC24

AC25

AC26

AC27

AC28

AD21

AD23

AA18

AE19

AE21

AE23

AE25

AE26

AE27

AE28

AF10

AF11

AA19

AF21

AF23

AF25

AH23

AA20

AG11

AG12

AG21

AG23

AG25

AA21

AH10

AH11

AA23

AH25

AH21

AA24

AF12

U25

AG5

Y21

Y23

W27

V25

AF2

AF3

AF4

AF7

AF9

AG3

AG4

AG6

AG7

AG8

AG9

AH1

W26

AH2

W28

AH3

AH4

AH5

AH6

AH7

AH9

W21

W23

W25

A20

+VDD_CORE1
+VDD_CORE2
+VDD_CORE3
+VDD_CORE4
+VDD_CORE5
+VDD_CORE6
+VDD_CORE7
+VDD_CORE8
+VDD_CORE9
+VDD_CORE10
+VDD_CORE11
+VDD_CORE12
+VDD_CORE13
+VDD_CORE14
+VDD_CORE15
+VDD_CORE16
+VDD_CORE17
+VDD_CORE18
+VDD_CORE19
+VDD_CORE20
+VDD_CORE21
+VDD_CORE22
+VDD_CORE23
+VDD_CORE24
+VDD_CORE25
+VDD_CORE26
+VDD_CORE27
+VDD_CORE28
+VDD_CORE29
+VDD_CORE30
+VDD_CORE31
+VDD_CORE32
+VDD_CORE33
+VDD_CORE34
+VDD_CORE35
+VDD_CORE36
+VDD_CORE37
+VDD_CORE38
+VDD_CORE39
+VDD_CORE40
+VDD_CORE41
+VDD_CORE42
+VDD_CORE43
+VDD_CORE44
+VDD_CORE45
+VDD_CORE46
+VDD_CORE47
+VDD_CORE48
+VDD_CORE49
+VDD_CORE50
+VDD_CORE51
+VDD_CORE52
+VDD_CORE53
+VDD_CORE54
+VDD_CORE55
+VDD_CORE56
+VDD_CORE57
+VDD_CORE58
+VDD_CORE59
+VDD_CORE60
+VDD_CORE61
+VDD_CORE62
+VDD_CORE63
+VDD_CORE64
+VDD_CORE65
+VDD_CORE66
+VDD_CORE67
+VDD_CORE68
+VDD_CORE69
+VDD_CORE70
+VDD_CORE71
+VDD_CORE72
+VDD_CORE73
+VDD_CORE74
+VDD_CORE75
+VDD_CORE76
+VDD_CORE77
+VDD_CORE78
+VDD_CORE79
+VDD_CORE80
+VDD_CORE81

+VBAT

(10 OF 11)

+VTT_CPU10
+VTT_CPU11
+VTT_CPU12
+VTT_CPU13
+VTT_CPU14
+VTT_CPU15
+VTT_CPU16
+VTT_CPU17
+VTT_CPU18
+VTT_CPU19
+VTT_CPU20
+VTT_CPU21
+VTT_CPU22
+VTT_CPU23
+VTT_CPU24
+VTT_CPU25
+VTT_CPU26
+VTT_CPU27
+VTT_CPU28
+VTT_CPU29
+VTT_CPU30
+VTT_CPU31
+VTT_CPU32
+VTT_CPU33
+VTT_CPU34
+VTT_CPU35
+VTT_CPU36
+VTT_CPU37

POWER

+VTT_CPU38
+VTT_CPU39
+VTT_CPU40
+VTT_CPU41
+VTT_CPU42
+VTT_CPU43
+VTT_CPU44
+VTT_CPU45
+VTT_CPU46
+VTT_CPU47
+VTT_CPU48
+VTT_CPU49
+VTT_CPU50
+VTT_CPU51
+VTT_CPU52

+VTT_CPUCLK

+3.3V_DUAL1
+3.3V_DUAL2
+3.3V_DUAL3
+3.3V_DUAL4

+3.3V_DUAL_USB1
+3.3V_DUAL_USB2
+3.3V_DUAL_USB3
+3.3V_DUAL_USB4

+VDD_AUXC1
+VDD_AUXC2
+VDD_AUXC3

+VTT_CPU1
+VTT_CPU2
+VTT_CPU3
+VTT_CPU4
+VTT_CPU5
+VTT_CPU6
+VTT_CPU7
+VTT_CPU8
+VTT_CPU9

+3.3V_1
+3.3V_2
+3.3V_3
+3.3V_4
+3.3V_5
+3.3V_6
+3.3V_7
+3.3V_8

5

=PP1V05_S0_MCP_FSB

R32

1139 mA

AC32

E40

J36

N32

T32

U32

V32

W32

P31

AF32

AE32

AH32

AJ32

AK31

AK32

AD32

AL31

AB32

B41

B42

C40

C41

C42

D39

D40

D41

E38

E39

F37

F38

F39

G36

G37

G38

H35

H37

J34

J35

K33

K34

K35

L32

L33

L34

M31

M32

M33

N31

P32

Y32

AA32

AG32

43 mA

=PP3V3_S0_MCP

AD10

AE8

AB10

AD9

Y10

AB11

AA8

Y9

=PP3V3_S5_MCP

G18

16 mA

H19

J20

K20

G26

250 mA

H27

J28

K28

=PP1V05_S5_MCP_VDD_AUXC

T21

U21

V21

4

8 9

14 23

1182 mA (A01)

8

21 23

450 mA (A01)

8

23

266 mA (A01)

8

23

105 mA (A01)

D

C

B

MCP Power & Ground

051-8071

SHT

SYNC_DATE=06/06/2008

OF

1

A

REV.

B

9822

SYNC_MASTER=T18_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

3

2

SCALE

NONE

87

www.vinafix.vn

6

5

4

3

21

MCP Core Power

=PPVCORE_S0_MCP

8

22 45

23065 mA (A01, 1.2V)
16996 mA (A01, 1.0V)

(No IG vs. EG data)

D

MCP PCIE (DVDD) Power

=PP1V05_S0_MCP_PEX_DVDD

MCP 1.05V AUX Power

=PP1V05_S5_MCP_VDD_AUXC

8

22

105 mA (A01) 131 mA (A01)

MCP FSB (VTT) Power

=PP1V05_S0_MCP_FSB

8 9

14 22

1182 mA (A01)

C

NV: 1x 10uF 0805, 2x 4.7uF 0402, 3x 1uF 0402, 9x 0.1uF 0402 (23.3 uF)
Apple: 4x 4.7uF 0402, 4x 1uF 0402, 6x 0.1uF 0402 (23.4 uF)

C2501

4.7UF

1

C2516

1UF

10%
10V

2

X5R
402-1

1

20%

4V

2

X5R
402

1

C2526

0.1uF

20%
10V

2

CERM
402

1

C2531

2.2UF

20%

6.3V

2

CERM
402-LF

C2502

4.7UF

1

C2517

1UF

10%
10V

2

X5R
402-1

1

20%

4V

2

X5R
402

1

C2532

2.2UF

20%

6.3V

2

CERM
402-LF

1

C2500

4.7UF

20%

4V

2

X5R
402

1

C2515

4.7UF

20%

4V

2

X5R
402

1

C2525

0.1uF

20%
10V

2

CERM
402

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)
Apple: 7x 2.2uF 0402 (15.4 uF)

1

C2530

2.2UF

20%

6.3V

2

CERM
402-LF

C2503

4.7UF

1

C2518

0.1uF

20%
10V

2

CERM
402

1

20%

4V

2

X5R
402

1

2

1

2

1

2

C2533

2.2UF

20%

6.3V
CERM
402-LF

C2504

1UF

10%
10V
X5R
402-1

C2519

0.1uF

20%
10V
CERM
402

8 8

18

1

C2505

1UF

10%
10V

2

X5R
402-1

MCP SATA (DVDD) Power

=PP1V05_S0_MCP_SATA_DVDD

43 mA (A01)57 mA (A01)

MCP 1.05V RMGT Power

=PP1V05_ENET_MCP_RMGT

8

1

C2534

2

2.2UF

20%

6.3V
CERM
402-LF

1

2

C2535

2.2UF

20%

6.3V
CERM
402-LF

1

C2506

1UF

10%
10V

2

X5R
402-1

C2520

4.7UF

C2528

4.7uF

1

C2536

2.2UF

20%

6.3V

2

CERM
402-LF

1

C2507

1UF

10%
10V

2

X5R
402-1

20%

4V
X5R
402

20%

4V
X5R
402

1

C2508

0.1UF

20%
10V

2

CERM
402

1

1

C2521

0.1uF

20%
10V

2

2

CERM
402

1

1

C2529

0.1uF

20%
10V

2

2

CERM
402

1

2

C2509

0.1UF

20%
10V
CERM
402

1

C2510

0.1UF

2

20%
10V
CERM
402

1

C2511

2

0.1UF

20%
10V
CERM
402

1

C2512

0.1UF

20%
10V

2

CERM
402

=PP1V05_S0_MCP_AVDD_UF

8

333 mA (A01)

=PP1V05_S0_MCP_PLL_PEX_UF

8

1

C2513

2

0.1UF

20%
10V
CERM
402

L2570

30-OHM-5A

0603

L2575

30-OHM-5A

0603

L2582

30-OHM-1.7A

0402

C2582

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 1uF 0402, 2x 0.1uF 0402 (16.9 uF)
Apple: 5x 2.2uF 0402 (11 uF)

21

17

84 mA (A01)

1

C2573

2.2UF

20%

6.3V

2

CERM
402-LF

127 mA (A01)

4.7UF

1

C2570

2.2UF

20%

6.3V

2

CERM
402-LF

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)
Apple: 2x 2.2uF 0402 (4.4 uF)

21

1

C2575

2.2UF

20%

6.3V

2

CERM
402-LF

21

1

1

20%

4V

2

2

X5R
402

1

C2571

2.2UF

20%

6.3V

2

CERM
402-LF

PP1V05_S0_MCP_SATA_AVDD

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

1

C2576

2.2UF

20%

6.3V

2

CERM
402-LF

PP1V05_S0_MCP_PLL_PEX

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

C2583

2.2UF

20%

6.3V
CERM
402-LF

1

2

C2572

2.2UF

20%

6.3V
CERM
402-LF

8

PP1V05_S0_MCP_PEX_AVDD

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

1

C2574

2.2UF

20%

6.3V

2

CERM
402-LF

8

206 mA (A01)

D

C

MCP Memory Power

=PP1V8R1V5_S0_MCP_MEM

8

16

4771 mA (A01, DDR3)

C2540

4.7UF

=PP1V05_S0_MCP_PLL_UF

8

66

1

1

C2541

20%

4V
X5R
402

0.1UF

20%
10V

2

2

CERM
402

1

C2542

0.1UF

2

20%
10V
CERM
402

1

C2543

2

0.1UF

20%
10V
CERM
402

1

2

C2544

0.1UF

20%
10V
CERM
402

1

2

C2545

0.1UF

20%
10V
CERM
402

1

C2546

0.1UF

20%
10V

2

CERM
402

1

C2547

0.1UF

20%
10V

2

CERM
402

1

C2548

2

0.1UF

20%
10V
CERM
402

1

2

C2549

0.1UF

20%
10V
CERM
402

562 mA (A01)

R2580

0.2

1%

1/6W

MF

402-HF

21

C2580

4.7UF

PP1V05_S0_MCP_PLL_FSB

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

1

1

C2581

2.2UF

20%

4V
X5R
402

10%
16V

2

2

X5R
603

14

270 mA (A01)

MCP 3.3V Power

=PP3V3_S0_MCP

8

21 22

450 mA (A01)

NV: 1x 4.7uF 0603, 4x 0.1uF 0402 (5.1 uF)
Apple: 4x 2.2uF 0402 (8.8 uF)

1

C2550

2.2UF

2

20%

6.3V
CERM
402-LF

1

C2551

2.2UF

2

20%

6.3V
CERM
402-LF

B

MCP 3.3V AUX/USB Power

=PP3V3_S5_MCP

8

22

266 mA (A01)

MCP 3.3V/1.5V HDA Power

=PP3V3R1V5_S0_MCP_HDA

8

21

7 mA (A01)

A

=PP1V05_ENET_MCP_PLL_MAC

8

5 mA (A01)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

8

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
Apple: 1x 2.2uF 0402 (2.2 uF)

1

C2560

2.2UF

20%

6.3V

2

CERM
402-LF

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
Apple: 1x 2.2uF 0402 (2.2 uF)

1

C2562

2.2UF

20%

6.3V

2

CERM
402-LF

L2595

30-OHM-1.7A

0402

C2595

4.7UF

21

1

20%

4V

2

X5R
402

76

1

C2552

2.2UF

20%

6.3V

2

CERM
402-LF

PP1V05_ENET_MCP_PLL_MAC

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

1

C2596

2.2UF

20%

6.3V

2

CERM
402-LF

1

C2553

2

2.2UF

20%

6.3V
CERM
402-LF

=PP3V3_S0_MCP_PLL_UF

8

19 mA (A01)

18

5 mA (A01)

MCP 3.3V Ethernet Power

=PP3V3_ENET_MCP_RMGT

8

18 23

83 mA (A01)

=PP3V3_ENET_MCP_RMGT

8

18 23

L2555

30-OHM-1.7A

0402

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
Apple: 1x 2.2uF 0402 (2.2 uF)

PP3V3_S0_MCP_PLL_USB

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

21

MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

1

C2555

2.2UF

20%

6.3V

2

CERM
402-LF

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
Apple: 1x 2.2uF 0402 (2.2 uF)

1

C2564

2.2UF

20%

6.3V

2

CERM
402-LF

MCP79 Ethernet VRef

1

R2591

1.47K

1%
1/16W
MF-LF

402

2

MCP_MII_VREF

1

R2590

1.47K

1/16W
MF-LF

1

C2591

0.1UF

1%

20%
10V

2

402

CERM
402

2

5

L2584

20

19 mA (A01)

30-OHM-1.7A

0402

C2584

4.7UF

21

20%

4V
X5R
402

PP1V05_S0_MCP_PLL_SATA

MIN_LINE_WIDTH=0.4 MM

VOLTAGE=1.05V

1

1

C2585

2.2UF

20%

6.3V

2

2

CERM
402-LF

20

84 mA (A01)

B

L2586

30-OHM-1.7A

30-OHM-1.7A

18

OUT

4

3

0402

L2588

0402

C2586

4.7UF

C2588

4.7UF

21

20%

4V
X5R
402

21

20%

4V
X5R
402

PP1V05_S0_MCP_PLL_CORE

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

1

1

C2587

2.2UF

20%

6.3V

2

2

CERM
402-LF

1

1

C2589

2.2UF

20%

6.3V

2

2

CERM
402-LF

PP1V05_S0_MCP_PLL_NV

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

1

C2590

0.1UF

20%
10V

2

CERM
402

2

16

87 mA (A01)

21

37 mA (A01)

MCP Standard Decoupling

SYNC_MASTER=M98_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

D

NONE

DRAWING NUMBER

051-8071

SHT

SYNC_DATE=04/01/2008

OF

23

1

A

REV.

B

98

87

www.vinafix.vn

6

5

4

3

21

WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

=PP3V3R1V8_S0_MCP_IFP_VDD

8

18

190 mA (A01, 1.8V)

D

=PP1V05_S0_MCP_HDMI_VDD

8

18

95 mA (A01)

Apple: 1x 2.2uF 0402 (2.2 uF)

1

C2610

2.2UF

20%

6.3V

2

CERM
402-LF

1

1

C2615

4.7UF

20%

4V
X5R
402

C2616

2

2

2.2UF

20%

6.3V
CERM
402-LF

=PP3V3_S0_MCP_DAC_UF

8

206 mA (A01)

NO STUFF

L2650

30-OHM-1.7A

0402

NV: 1x 4.7uF 0603, 2x 0.1uF 0402 (4.9 uF)
Apple: 2x 2.2uF 0402 (4.4 uF)

21

NO STUFF

1

C2650

2.2UF

20%

6.3V

2

CERM
402-LF

PP3V3_S0_MCP_DAC

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

1

R2651

0

5%
1/16W
MF-LF
402

2

18

206 mA (A01)

D

18

18

18

18

MCP_HDMI_RSET

18 90

MCP_HDMI_VPROBE

18 90

C

NO STUFF

C2620

0.1UF

CERM

1

R2620

1

1K

1%

20%
10V

402

1/16W
MF-LF
402

2

2

WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

L2640

=PP3V3_S0_MCP_VPLL_UF

8

16 mA (A01)

30-OHM-1.7A

0402

C2640

4.7UF

6.3V
CERM

21

1

20%

2

603

MCP_IFPAB_RSET

18 90

MCP_IFPAB_VPROBE

18 90

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
Apple: ???

PP3V3_S0_MCP_VPLL

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

1

C2641

2.2UF

20%

6.3V

2

CERM
402-LF

NO STUFF

C2630

0.1UF

20%
10V

CERM

402

1

2

16 mA (A01)

NO STUFF

1

R2630

1K

1%
1/16W
MF-LF
402

2

18

18

18 90

18 90

18 90

18 90

18 90

TP_MCP_RGB_DAC_RSET

18

TP_MCP_RGB_DAC_VREF

18

MCP_TV_DAC_RSET

18 90

MCP_TV_DAC_VREF

18 90

MCP_CLK27M_XTALIN

18

MCP_CLK27M_XTALOUT

18

TP_MCP_RGB_RED

TP_MCP_RGB_GREEN

TP_MCP_RGB_BLUE

TP_MCP_RGB_HSYNC

TP_MCP_RGB_VSYNC

CRT_IG_R_C_PR

CRT_IG_G_Y_Y

CRT_IG_B_COMP_PB

CRT_IG_HSYNC

CRT_IG_VSYNC

B

NC_MCP_RGB_RED

MAKE_BASE=TRUE

NC_MCP_RGB_GREEN

MAKE_BASE=TRUE

NC_MCP_RGB_BLUE

MAKE_BASE=TRUE

NC_MCP_RGB_HSYNC

MAKE_BASE=TRUE

NC_MCP_RGB_VSYNC

MAKE_BASE=TRUE

NC_CRT_IG_R_C_PR

MAKE_BASE=TRUE

NC_CRT_IG_G_Y_Y

MAKE_BASE=TRUE

NC_CRT_IG_B_COMP_PB

MAKE_BASE=TRUE

NC_CRT_IG_HSYNC

MAKE_BASE=TRUE

NC_CRT_IG_VSYNC

MAKE_BASE=TRUE

NC_MCP_RGB_DAC_RSET

MAKE_BASE=TRUE

NC_MCP_RGB_DAC_VREF

MAKE_BASE=TRUE

NC_MCP_TV_DAC_RSET

MAKE_BASE=TRUE

NC_MCP_TV_DAC_VREF

MAKE_BASE=TRUE

NC_MCP_CLK27M_XTALIN

MAKE_BASE=TRUE

NC_MCP_CLK27M_XTALOUT

MAKE_BASE=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

C

B

HDCP ROM

WF: Open question on which packge option(s) nVidia can support.

=PP3V3_S0_HDCPROM

8

C2690

0.1UF

1

NO STUFF

20%
10V

2

CERM

402

NO STUFF

8

VCC

U2695

AT24C08

SOIC

GND

5

SDA

6

SCL

7

WP

4

1

A0

2

A1

3

A2

A

Current numbers from email Xiaowei Lin provided 11/12/2007 3:22pm (no official document number).

8

76

=I2C_HDCPROM_SDA
=I2C_HDCPROM_SCL

HDCPROM_WP

R2690

10K

1/16W
MF-LF

1

NO STUFF

5%

402

2

44

BI

44

IN

MCP Graphics Support

051-8071

SHT

SYNC_DATE=04/01/2008

OF

24 98

1

A

REV.

B

SYNC_MASTER=M98_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

5

4

3

2

SCALE

NONE

87

www.vinafix.vn

6

5

4

3

21

RTC Power Sources

=PP3V3_S5_RTC_D

8

1

RTC_PS_YES

VIN

U2801

MIC5232-2.8YD5

TSOT-23-5

3

D

NO STUFF

1

C2802

1UF

10%
10V

2

X5R
402

CRITICAL

GND

2

5

VOUTEN

4

NC

RTC_DISCHARGE_R

RTC_CLK32K_XTALOUT

21

IN

NO STUFF

1

R2811

10M

5%

1/16W

C

RTC_CLK32K_XTALIN

21

OUT

MF-LF

402

2

RTC Crystal

R2810

0

21

RTC_CLK32K_XTALOUT_R

5%
1/16W
MF-LF

402

Y2810

32.768K

7X1.5X1.4-SM

MCP 25MHz Crystal

MCP_CLK25M_XTALOUT

21

IN

R2815

0

21

MCP_CLK25M_XTALOUT_R

1/16W
MF-LF

5%

402

SM-3.2X2.5MM

21

OUT

MCP_CLK25M_XTALIN

NO STUFF

R2816

1/16W
MF-LF

1

1M

5%

402

2

MCP S0 PWRGD & CPU_VLD

=PP3V3_S5_MCPPWRGD

8

B

ALL_SYS_PWRGD

41 67 84

IN

VR_PWRGOOD_DELAY

61

IN

MCP_CPUVDD_EN

21

IN

A

MCPSEQ_SMC represents MCP79 ’MLB’ power sequencing connections,
but results in MCP79 ROMSIP sequence happening after CPU powers up.

MCPSEQ_MIX is cross between MLB and internal power sequencing, which
results in earlier ROMSIP and MCP FSB I/O interface initialization.

SMC 99ms delay from ALL_SYS_PWRGD to IMVP_VR_ON plus IMVP6 delay for
VR_PWRGOOD_DELAY should guarantee CPU_VLD does not go high before
CPUVDD_EN (which is 40-100ms after PS_PWRGD assertion).

NOTE: If CPU_VLD deasserts during S0 MCP79 will take system to S5 immediately.

2

1

A

U2850

B

1

2

TC7SZ08AFEAPE

5

SOT665

MCPSEQ_SMC

3

MCPSEQ_SMC

C2850

0.1UF

20%
10V
CERM
402

4

S0_AND_IMVP_PGOOD

PLACEMENT_NOTE=Place close to U1400

MCPSEQ_MIX

R2851

0

5%
1/16W
MF-LF

402

21

NO STUFF

R2801

1/16W
MF-LF

CRITICAL

CRITICAL

Y2815

25.0000M

MCPSEQ_SMC

R2853

MCPSEQ_MIX

R2852

MCPSEQ_SMC

R2850

10

402

1/16W
MF-LF

1/16W
MF-LF

1/16W
MF-LF

1

5%

2

0

5%

402

0

5%

402

0

5%

402

R2803

0

21

5%
1/16W
MF-LF

402

NO STUFF

R2802

1.0M

21

5%
1/10W
MF-LF

603

41

31

42

NC

NC

21

MCP_PS_PWRGD

21

MCP_CPU_VLD

21

C2801

1UF

10%

6.3V
CERM

402

C2810

C2811

C2815

C2816

12pF

50V

CERM

402

12pF

50V

CERM

402

12pF

50V

CERM

402

12pF

50V

CERM

402

1

2

5%

5%

5%

5%

1

R2800

100

5%
1/16W
MF-LF
402

2

PP3V3_G3_SUPERCAP

1

2

21

21

21

21

PP3V3_G3_RTC

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

SUPERCAP_YES

C2800

SUPERCAP_YES

0.08F

2%

CRITICAL

3.3V
XHHG
SM

OUTY

OUT

Platform Reset Connections

LPC Reset (Unbuffered)

R2881

PLACEMENT_NOTE=Place close to U1400

PLACEMENT_NOTE=Place close to U1400

21 22

19 84 91

IN

LPC_RESET_L

PCIE Reset (Unbuffered)

PCIE_RESET_L

17

IN

MEM_VTT_EN_R

19

IN

LPC_CLK33M_SMC_R

19 91

IN

PM_CLK32K_SUSCLK_R

21 91

IN

21

21

PM_SYSRST_L

7

41

IN

XDP_DBRESET_L

IN

Reset Button

XDP

R2896

0

21

5%
1/16W
MF-LF

402

SILK_PART=FP SYS RESET

OMIT

R2897

1/16W
MF-LF

R2899

33

5%

1/16W

1

MF-LF

0

5%

402

402

2

PLACEMENT_NOTE=Place close to U1400

PLACEMENT_NOTE=Place close to U1400

10K pull-up to 3.3V S0 inside MCP

21

PM_SYSRST_DEBOUNCE_L

NO STUFF

1

C2899

1UF

10%
10V

2

X5R
402

33

21

5%
1/16W
MF-LF

402

R2890

1/16W
MF-LF

R2893

1/16W
MF-LF

R2895

R2825

33

5%
1/16W
MF-LF

402

R2827

33

5%
1/16W
MF-LF

402

PLACEMENT_NOTE=Place close to U1400

R2829

22

5%
1/16W
MF-LF

402

21 10 13

OUT

5%

402

5%

402

1/16W
MF-LF

0

0

21

21

0

21

5%

402

21

21

21

R2883

33

5%
1/16W
MF-LF

402

R2892

0

5%
1/16W
MF-LF

402

GMUX_PCIE_RESET_L

MAKE_BASE=TRUE

R2891

0

5%
1/16W
MF-LF

402

BKLT_PLT_RST_L

R2894

0

5%
1/16W
MF-LF

402

EXCARD_RESET_L

R2870

33

21

5%
1/16W
MF-LF

402

R2826

33

5%
1/16W
MF-LF

402

SYNC_MASTER=M98_MLB

APPLE INC.

DEBUG_RESET_L

21

SMC_LRESET_L

21

FW_RESET_L

=GMUX_PCIE_RESET_L

21

PCA9557D_RESET_L

21

MINI_RESET_L

MEM_VTT_EN

LPC_CLK33M_SMC

21

LPC_CLK33M_LPCPLUS

PLACEMENT_NOTE=Place close to U1400

LPC_CLK33M_GMUX

PM_CLK32K_SUSCLK

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

SB Misc

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

SHT

051-8071

25

7

43

41

35

84

26

86

30

31

9

41 91

7

43 91

84

41 91

SYNC_DATE=05/01/2008

REV.

OF

98

D

C

B

A

B

8

76

5

4

3

2

1

Page Notes

www.vinafix.vn

Power aliases required by this page:

- =PP3V3_S3_VREFMRGN

- =PP3V3_S5_VREFMRGN

- =PPVTT_S3_DDR_BUF

Signal aliases required by this page:

- =I2C_VREFDACS_SCL

- =I2C_VREFDACS_SDA

- =I2C_PCA9557D_SCL

- =I2C_PCA9557D_SDA

BOM options provided by this page:

D

VREFMRGN

NO_VREFMRGN

C

B

87

MEM A VREF DQ MEM A VREF CA MEM B VREF DQ

DAC channel A B A B C D

Min DAC code 0x00 0x00 0x00 0x00 0x00 0x00

Max DAC code 0x87 0x87 0x87 0x87 0x55 0xFF

Max sink I -3.75 mA -3.75 mA -3.75 mA -3.75 mA -0.91 mA -59.04 mA

Max source I 5 mA 5 mA 5 mA 5 mA 0.52 mA 51.15 mA

Nominal Vref 0.75 V 0.75 V 0.75 V 0.75 V 0.70 V 1.248 V

Min Vref 0.375 V 0.375 V 0.375 V 0.375 V 0.091 V 1.042 V

Max Vref 1.250 V 1.250 V 1.250 V 1.250 V 1.044 V 1.426 V

Vref Stepping 6.5 mV 6.5 mV 6.5 mV 6.5 mV 11.2 mV 1.5 mV

(per DAC LSB)

OMIT

=PP3V3_S3_VREFMRGN

8

44

44

R2918

SHORT

21

NONE
NONE
NONE

402

44

44

ADDR=0x98(WR)/0x99(RD)

OMIT

R2919

SHORT

NONE
NONE
NONE

402

ADDR=0x30(WR)/0x31(RD)

=I2C_PCA9557D_SCL

IN

=I2C_PCA9557D_SDA

BI

IN

BI

21

VREFMRGN

1

C2900

2.2UF

20%

6.3V

2

CERM
402-LF

=I2C_VREFDACS_SCL

=I2C_VREFDACS_SDA

1

2

VREFMRGN

1

C2902

0.1UF

20%
10V

2

CERM
402

VREFMRGN

C2901

0.1UF

20%
10V
CERM
402

PP3V3_S3_VREFMRGN_DAC

6

SCL

7

SDA

9

A0

10

A1

PP3V3_S3_VREFMRGN_CTRL

3

A0

4

A1

5

A2

1

SCL

2

SDA

THRM

PAD

17

U2901

PCA9557

GND

VREFMRGN

U2900

8

VDD

VOUTA

MSOP

VOUTB

VOUTC

DAC5574

VOUTD

GND

3

CRITICAL

VREFMRGN

16

VCC

QFN

RESET*

8

P0
P1
P2
P3
P4
P5
P6
P7

6

1

2

4

5

6

7

9

10

11

12

13

14

15

VREFMRGN_DQ_SODIMM

VREFMRGN_CA_SODIMM

VREFMRGN_CPUFSB

VREFMRGN_FRAMEBUF

NC

NC

VREFMRGN_CPUFSB_EN

VREFMRGN_CA_SODIMMA_EN

VREFMRGN_DQ_SODIMMA_EN

VREFMRGN_CA_SODIMMB_EN

VREFMRGN_DQ_SODIMMB_EN

VREFMRGN_FRAMEBUF_EN

PCA9557D_RESET_L

5

MEM B VREF CA

CPU FSB VREF

4

FRAME BUFFER VREF

3

21

SO-DIMM A and SO-DIMM B Vref settings should be margined separately

(i.e. not simultaneously) due to current limitation of TPS51116 regulator.

=PPVTT_S3_DDR_BUF

8

63

10mA max load

VREFMRGN

R2903

200

21

1%
1/16W
MF-LF

B1

VREFMRGN

V-

VREFMRGN

V-

VREFMRGN

V-

VREFMRGN

V-

VREFMRGN

V-

VREFMRGN

V-

U2902

MAX4253

V+

UCSP

A1

C1

A1

C1

A1

C1

VREFMRGN_DQ_SODIMMA_BUF

VREFMRGN_DQ_SODIMMA_EN

26

VREFMRGN_DQ_SODIMMB_BUF

VREFMRGN_DQ_SODIMMB_EN

26

VREFMRGN_CA_SODIMMA_BUF

VREFMRGN_CA_SODIMMA_EN

26

VREFMRGN_CA_SODIMMB_BUF

VREFMRGN_CA_SODIMMB_EN

26

VREFMRGN_FRAMEBUF_BUF

VREFMRGN_FRAMEBUF_EN

26

VREFMRGN_CPUFSB_BUF

VREFMRGN_CPUFSB_EN

26

R2901

R2902

R2907

R2908

R2915

R2913

100K

100K

100K

100K

100K

100K

1/16W
MF-LF

1/16W
MF-LF

1/16W
MF-LF

1/16W
MF-LF

1/16W
MF-LF

1/16W
MF-LF

21

VREFMRGN

5%

402

21

VREFMRGN

5%

402

21

VREFMRGN

5%

402

21

VREFMRGN

5%

402

21

VREFMRGN

5%

402

21

VREFMRGN

5%

402

A4

B4

B1

U2902

MAX4253

V+

UCSP

C4

B4

B1

U2903

MAX4253

V+

UCSP

A4

B4

B1

U2903

MAX4253

V+

UCSP

C4

B4

B1

U2904

MAX4253

V+

UCSP

A4

B4

B1

U2904

MAX4253

V+

UCSP

C4

B4

VREFMRGN

1

C2903

0.1UF

20%
10V

2

CERM
402

VREFMRGN

1

C2904

0.1UF

20%
10V

2

CERM
402

VREFMRGN

1

C2905

0.1UF

20%
10V

2

CERM
402

26

26

26

26

26

26

25

IN

A2

A3

C2

C3

A2

A3

C2

C3

A2

A3

C2

C3

402

VREFMRGN

R2904

100

21

1%

Place close to J3100.1

1/16W
MF-LF

402

VREFMRGN

R2905

200

21

1%
1/16W
MF-LF

402

VREFMRGN

R2906

100

21

1%

Place close to J3200.1

1/16W
MF-LF

402

VREFMRGN

R2909

200

21

1%
1/16W
MF-LF

402

VREFMRGN

R2910

100

21

1%

Place close to J3100.126

1/16W
MF-LF

402

VREFMRGN

R2911

200

21

1%
1/16W
MF-LF

402

VREFMRGN

R2912

100

21

1%

Place close to J3200.126

1/16W
MF-LF

402

VREFMRGN

R2916

49.9

21

1%

Place close to U8400, U8450

1/16W
MF-LF

402

VREFMRGN

R2917

49.9

21

1%

Place close to U8500, U8550

1/16W
MF-LF

402

VREFMRGN

R2914

100

21

1%

Place close to U1000.AD26

1/16W
MF-LF

402

PP0V75_S3_MEM_VREFDQ_A

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

PP0V75_S3_MEM_VREFDQ_B

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

PP0V75_S3_MEM_VREFCA_A

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

PP0V75_S3_MEM_VREFCA_B

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

GPU_FB_A_VREF_DIV

GPU_FB_B_VREF_DIV

CPU_GTLREF

27

28

27

28

9

OUT

9

OUT

10 88

OUT

D

C

B

A

Required zero ohm resistors when no VREF margining circuit stuffed

PART NUMBER

116S0004

116S0004

116S0004

116S0004

QTY

1

1

1

1

DESCRIPTION

RES,MTL FILM,0,5%,0402,SM,LF

RES,MTL FILM,0,5%,0402,SM,LF

RES,MTL FILM,0,5%,0402,SM,LF

RES,MTL FILM,0,5%,0402,SM,LF

8

REFERENCE DES

76

R2903

R2905

R2909

R2911

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

BOM OPTION

NO_VREFMRGN

NO_VREFMRGN

NO_VREFMRGN

NO_VREFMRGN

FSB/DDR3/FRAMEBUF Vref Margining

SYNC_MASTER=BEN_K20

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

5

4

3

2

SCALE

NONE

051-8071

SHT

SYNC_DATE=10/15/2008

OF

1

A

REV.

B

9826

87

www.vinafix.vn

6

5

4

3

21

Power aliases required by this page:

- =PP1V5_S0_MEM_A

- =PP1V5_S3_MEM_A

- =PP0V75_S0_MEM_VTT_A

- =PPSPD_S0_MEM_A (2.5 - 3.3V)

Signal aliases required by this page:

- =I2C_SODIMMA_SCL

- =I2C_SODIMMA_SDA

BOM options provided by this page:

D

(NONE)

C

B

A

Page Notes

=PPSPD_S0_MEM_A

8

1

2

C3140

2.2UF

20%

6.3V

CERM

402-LF

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

1

2

R3140

10K

5%

1/16W

MF-LF

402

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI

MEM_A_CKE<0>

MEM_A_BA<2>

MEM_A_A<12>

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<5>

MEM_A_A<3>

MEM_A_A<1>

MEM_A_CLK_P<0>

MEM_A_CLK_N<0>

MEM_A_A<10>

MEM_A_BA<0>

MEM_A_WE_L

MEM_A_CAS_L

MEM_A_A<13>

MEM_A_CS_L<1>

MEM_A_DQ<33>

MEM_A_DQ<32>

MEM_A_DQS_N<4>

MEM_A_DQS_P<4>

MEM_A_DQ<34>

MEM_A_DQ<35>

MEM_A_DQ<44>

MEM_A_DQ<41>

MEM_A_DM<5>

MEM_A_DQ<45>

MEM_A_DQ<42>

MEM_A_DQ<52>

MEM_A_DQ<51>

MEM_A_DQS_N<6>

MEM_A_DQS_P<6>

MEM_A_DQ<55>

MEM_A_DQ<54>

MEM_A_DQ<61>

MEM_A_DQ<60>

MEM_A_DM<7>

MEM_A_DQ<58>

MEM_A_DQ<59>

MEM_A_SA<0>

MEM_A_SA<1>

1

R3141

10K

5%

1/16W

MF-LF

402

2

=PP1V5_S0_MEM_A

8

=PP1V5_S3_MEM_A

8

NC

NC

1

C3100

10UF

20%

6.3V

2

X5R
603

KEY

CKE0

VDD

77

NC

79

83 84
85

89
91 92

95 96
97 98

99
101
103

107
109

113
115

119
121

125

129
131

135
137
139
141
143
145
147
149
151
153

157
159

163
165

169
171
173
175
177
179
181
183
185
187

191
193

197
199

J3100

BA2

F-RT-THB

VDD
A12/BC*
A9

VDD
A8
A5

VDD
A3
A1

VDD
CK0
CK0*

VDD
A10/AP
BA0

VDD
WE*
CAS*

VDD
A13
S1*

VDD
TEST

VSS
DQ32
DQ33

VSS
DQS4*
DQS4

VSS
DQ34
DQ35

VSS
DQ40
DQ41

VSS
DM5

VSS
DQ42
DQ43

VSS
DQ48
DQ49

VSS
DQS6*
DQS6

VSS
DQ50
DQ51

VSS
DQ56
DQ57

VSS
DM7

VSS
DQ58
DQ59

VSS
SA0
VDDSPD
SA1

VTT

516-0201

SPD ADDR=0xA0(WR)/0xA1(RD)

1

C3101

10UF

20%

6.3V

2

X5R
603

CKE1

VDD

A15
A14

VDD

A11

A7

VDD

A6
A4

VDD

(SYMBOL 2 OF 2)

A2
A0

VDD

CK1

CK1*

VDD

DDR3-SODIMM-DUAL-M97-3

BA1

RAS*

VDD

S0*

ODT0

VDD

ODT1

NC

VDD

VREFCA

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5*

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7*

DQS7

VSS
DQ62
DQ63

VSS

EVENT*

SDA
SCL

VTT

7473
7675
78
80
8281

86
8887
90

9493

100
102
104
106105
108
110
112111
114
116
118117
120
122
124123
126
128127
130
132
134133
136
138
140
142
144
146
148
150
152
154
156155
158
160
162161
164
166
168167
170
172
174
176
178
180
182
184
186
188
190189
192
194
196195
198
200
202201
204203

NC

MEM_A_CKE<1>

MEM_A_A<15>

MEM_A_A<14>

MEM_A_A<11>

MEM_A_A<7>

MEM_A_A<6>

MEM_A_A<4>

MEM_A_A<2>

MEM_A_A<0>

MEM_A_CLK_P<1>

MEM_A_CLK_N<1>

MEM_A_BA<1>

MEM_A_RAS_L

MEM_A_CS_L<0>

MEM_A_ODT<0>

MEM_A_ODT<1>

MEM_A_DQ<36>

MEM_A_DQ<37>

MEM_A_DM<4>

MEM_A_DQ<38>

MEM_A_DQ<39>

MEM_A_DQ<47>

MEM_A_DQ<40>

MEM_A_DQS_N<5>

MEM_A_DQS_P<5>

MEM_A_DQ<46>

MEM_A_DQ<43>

MEM_A_DQ<48>

MEM_A_DQ<53>

MEM_A_DM<6>

MEM_A_DQ<50>

MEM_A_DQ<49>

MEM_A_DQ<57>

MEM_A_DQ<56>

MEM_A_DQS_N<7>

MEM_A_DQS_P<7>

MEM_A_DQ<62>

MEM_A_DQ<63>

MEM_EVENT_L

=I2C_SODIMMA_SDA

=I2C_SODIMMA_SCL

DDR3 PLANE STITCHING CAPS (SPACE EVENLY ACROSS PLANE SPLIT)

1

C3110

0.1UF

2

20%
10V
CERM
402

1

C3111

0.1UF

20%
10V

2

CERM
402

PP0V75_S3_MEM_VREFDQ_A

26

15 89

IN

9

IN

15 89

IN

15 89

IN

15 89

IN

15 89

IN

15 89

IN

15 89

IN

15 89

IN

15 89

IN

15 89

IN

15 89

IN

15 89

IN

15 89

IN

15 89

IN

15 89

IN

15 89

BI

15 89

BI

15 89

IN

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

IN

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

21 28 41

OUT

BI

44

IN

DQS0

VSS

VSS
DQ12
DQ13

VSS

VSS
DQ14
DQ15

VSS
DQ20
DQ21

VSS

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3

VSS
DQ30
DQ31

VSS

DQ4
DQ5

DQ6
DQ7

DM1

DM2

VSS

VSS

21
4
6
8
10
12
1413
16
18
2019
22
24
2625
28
30
3231
34
36
3837
40
42
4443
46
48
50
52
54
56
58
60
62
64
6665
68
70
7271

1

C3118

0.1UF

20%
10V

2

CERM
402

1

C3116

0.1UF

20%
10V

2

CERM
402

VREFDQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

VSS

15

DQ2

17

DQ3

VSS

21

DQ8

23

DQ9

VSS

27

DQS1*

29

DQS1

VSS

33

DQ10

35

DQ11

VSS

39

DQ16

41

DQ17

VSS

45

DQS2*

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

VSS

67

DQ26

69

DQ27

VSS

C3130

2.2UF

20%

6.3V

CERM

402-LF

1

2

MEM_A_DQ<0>

MEM_A_DQ<1>

MEM_A_DM<0>

MEM_A_DQ<3>

MEM_A_DQ<2>

MEM_A_DQ<9>

MEM_A_DQ<13>

MEM_A_DQS_N<1>

MEM_A_DQS_P<1>

MEM_A_DQ<11>

MEM_A_DQ<14>

MEM_A_DQ<16>

MEM_A_DQ<18>

MEM_A_DQS_N<2>

MEM_A_DQS_P<2>

MEM_A_DQ<23>

MEM_A_DQ<19>

MEM_A_DQ<24>

MEM_A_DQ<30>

MEM_A_DM<3>

MEM_A_DQ<27>

MEM_A_DQ<25>

1

C3136

0.1UF

20%
10V

2

CERM

402

C3114

0.1UF

20%
10V
CERM
402

1

2

PP0V75_S3_MEM_VREFCA_A

1

C3112

0.1UF

20%
10V

2

CERM
402

44

1

C3113

2

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

1

C3135

2.2UF

20%

6.3V

2

CERM

402-LF

=PP0V75_S0_MEM_VTT_A

0.1UF

20%
10V
CERM
402

1

2

BI

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI

C3131

0.1UF

20%
10V

CERM

402

1

C3115

2

0.1UF

20%
10V
CERM
402

8

1

C3117

0.1UF

20%
10V

2

CERM
402

CRITICAL

F-RT-THB

DQS0*

(SYMBOL 1 OF 2)

RESET*

J3100

DDR3-SODIMM-DUAL-M97-3

DQS3*

KEY

516-0201

26

1

C3119

0.1UF

20%

10V

2

CERM
402

MEM_A_DQ<4>

MEM_A_DQ<5>

MEM_A_DQS_N<0>

MEM_A_DQS_P<0>

MEM_A_DQ<6>

MEM_A_DQ<7>

MEM_A_DQ<8>

MEM_A_DQ<12>

MEM_A_DM<1>

MEM_RESET_L

MEM_A_DQ<15>

MEM_A_DQ<10>

MEM_A_DQ<21>

MEM_A_DQ<20>

MEM_A_DM<2>

MEM_A_DQ<17>

MEM_A_DQ<22>

MEM_A_DQ<29>

MEM_A_DQ<28>

MEM_A_DQS_N<3>

MEM_A_DQS_P<3>

MEM_A_DQ<26>

MEM_A_DQ<31>

1

2

C3120

0.1UF

20%
10V
CERM
402

1

C3121

0.1UF

20%
10V

2

CERM
402

1

2

C3122

0.1UF

20%
10V
CERM
402

1

2

C3123

0.1UF

20%
10V
CERM
402

D

15 89

BI

15 89

BIBI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

IN

28 29

IN

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

IN

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

C

B

"Factory" (top) slot

DDR3 SO-DIMM Connector A

SYNC_MASTER=BEN_K20

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

D

NONE

DRAWING NUMBER

051-8071

SHT

OF

SYNC_DATE=06/10/2008

REV.

B

9827

A

8

76

5

4

3

2

1

87

www.vinafix.vn

6

5

4

3

21

D

C

B

A

Page Notes

Power aliases required by this page:

- =PP1V5_S0_MEM_B

- =PP1V5_S3_MEM_B

- =PP0V75_S0_MEM_VTT_B

- =PPSPD_S0_MEM_B (2.5 - 3.3V)

Signal aliases required by this page:

- =I2C_SODIMMB_SCL

- =I2C_SODIMMB_SDA

BOM options provided by this page:

(NONE)

=PPSPD_S0_MEM_B

8

1

2

1

R3240

2

C3240

2.2UF

=PP1V5_S0_MEM_B

8

=PP1V5_S3_MEM_B

8

1

C3200

10UF

20%

6.3V

2

X5R
603

MEM_B_CKE<0>

15 89

IN

77

MEM_B_BA<2>

15 89

IN

MEM_B_A<12>

15 89

IN

MEM_B_A<9>

15 89

IN

MEM_B_A<8>

15 89

IN

MEM_B_A<5>

15 89

IN

MEM_B_A<3>

15 89

IN

MEM_B_A<1>

15 89

IN

MEM_B_CLK_P<0>

15 89

IN

MEM_B_CLK_N<0>

15 89

IN

MEM_B_A<10>

15 89

IN

MEM_B_BA<0>

15 89

IN

MEM_B_WE_L

15 89

IN

MEM_B_CAS_L

15 89

IN

MEM_B_A<13>

15 89

IN

MEM_B_CS_L<1>

15 89

IN

79

83 84
85

89
91 92

95 96
97 98

99
101
103

107
109

113
115

119
121

125

MEM_B_DQ<32>

15 89

BI

MEM_B_DQ<37>

15 89

BI

MEM_B_DQS_N<4>

15 89

BI

MEM_B_DQS_P<4>

15 89

BI

MEM_B_DQ<34>

15 89

BI

MEM_B_DQ<35>

15 89

BI

MEM_B_DQ<41>

15 89

BI

MEM_B_DQ<40>

15 89

BI

MEM_B_DM<5>

15 89

IN

MEM_B_DQ<43>

15 89

BI

MEM_B_DQ<42>

15 89

BI

MEM_B_DQ<55>

15 89

BI

MEM_B_DQ<49>

15 89

BI

MEM_B_DQS_N<6>

15 89

BI

MEM_B_DQS_P<6>

15 89

BI

MEM_B_DQ<52>

15 89

BI

MEM_B_DQ<51>

15 89

BI

MEM_B_DQ<56>

15 89

BI

MEM_B_DQ<57>

15 89

BI

MEM_B_DM<7>

15 89

10K

5%

1/16W

MF-LF

402

20%

6.3V

CERM

402-LF

IN

MEM_B_DQ<63>

15 89

BI

MEM_B_DQ<59>

15 89

BI

MEM_B_SA<0>

MEM_B_SA<1>

1

R3241

10K

5%

1/16W

MF-LF

402

2

129
131

135
137
139
141
143
145
147
149
151
153

157
159

163
165

169
171
173
175
177
179
181
183
185
187

191
193

197
199

SPD ADDR=0xA2(WR)/0xA3(RD)

KEY

CKE0

VDD
NC

BA2

J3200

F-RT-BGA3

VDD
A12/BC*
A9

VDD
A8
A5

VDD
A3
A1

VDD
CK0
CK0*

VDD
A10/AP
BA0

VDD
WE*
CAS*

VDD
A13
S1*

VDD
TEST

VSS
DQ32
DQ33

VSS
DQS4*
DQS4

VSS
DQ34
DQ35

VSS
DQ40
DQ41

VSS
DM5

VSS
DQ42
DQ43

VSS
DQ48
DQ49

VSS
DQS6*
DQS6

VSS
DQ50
DQ51

VSS
DQ56
DQ57

VSS
DM7

VSS
DQ58
DQ59

VSS
SA0
VDDSPD
SA1

VTT

MTG PINS

MTG PIN

MTG PIN

MTG PIN MTG PIN

MTG PIN

516s0706

1

2

CKE1

VDD

A15
A14

VDD

A11

A7

VDD

(2 OF 2)

A6
A4

VDD

DDR3-SODIMM

A2
A0

VDD

CK1

CK1*

VDD

BA1

RAS*

VDD

S0*

ODT0

VDD

ODT1

NC

VDD

VREFCA

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5*

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7*

DQS7

VSS
DQ62
DQ63

VSS

EVENT*

SDA
SCL

VTT

MTG PIN

MTG PIN

MTG PIN

C3201

10UF

20%

6.3V
X5R
603

7473
7675
78
80
8281

86
8887
90

9493

100
102
104
106105
108
110
112111
114
116
118117
120
122
124123
126
128127
130
132
134133
136
138
140
142
144
146
148
150
152
154
156155
158
160
162161
164
166
168167
170
172
174
176
178
180
182
184
186
188
190189
192
194
196195
198
200
202201
204203

206205
208207
210209
212211

NC

MEM_B_CKE<1>

MEM_B_A<15>

MEM_B_A<14>

MEM_B_A<11>

MEM_B_A<7>

MEM_B_A<6>

MEM_B_A<4>

MEM_B_A<2>

MEM_B_A<0>

MEM_B_CLK_P<1>

MEM_B_CLK_N<1>

MEM_B_BA<1>

MEM_B_RAS_L

MEM_B_CS_L<0>

MEM_B_ODT<0>

MEM_B_ODT<1>

MEM_B_DQ<33>

MEM_B_DQ<36>

MEM_B_DM<4>

MEM_B_DQ<38>

MEM_B_DQ<39>

MEM_B_DQ<44>

MEM_B_DQ<45>

MEM_B_DQS_N<5>

MEM_B_DQS_P<5>

MEM_B_DQ<47>

MEM_B_DQ<46>

MEM_B_DQ<48>

MEM_B_DQ<54>

MEM_B_DM<6>

MEM_B_DQ<53>

MEM_B_DQ<50>

MEM_B_DQ<60>

MEM_B_DQ<61>

MEM_B_DQS_N<7>

MEM_B_DQS_P<7>

MEM_B_DQ<58>

MEM_B_DQ<62>

MEM_EVENT_L

=I2C_SODIMMB_SDA

=I2C_SODIMMB_SCL

DDR3 PLANE STITCHING CAPS (SPACE EVENLY ACROSS PLANE SPLIT)

1

2

C3210

0.1UF

20%
10V
CERM
402

1

C3211

0.1UF

20%
10V

2

CERM
402

PP0V75_S3_MEM_VREFDQ_B

26

15 89

IN

9

IN

15 89

IN

15 89

IN

15 89

IN

15 89

IN

15 89

IN

15 89

IN

15 89

IN

15 89

IN

15 89

IN

15 89

IN

15 89

IN

15 89

IN

15 89

IN

15 89

IN

15 89

BI

15 89

BI

15 89

IN

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

IN

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

21 27 41

OUT

BI

44

IN

DQS0

VSS

VSS
DQ12
DQ13

VSS

VSS
DQ14
DQ15

VSS
DQ20
DQ21

VSS

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3

VSS
DQ30
DQ31

VSS

VSS
DQ4
DQ5
VSS

DQ6
DQ7

DM1

DM2

21
4
6
8
10
12
1413
16
18
2019
22
24
2625
28
30
3231
34
36
3837
40
42
4443
46
48
50
52
54
56
58
60
62
64
6665
68
70
7271

1

C3218

2

0.1UF

20%
10V
CERM
402

CRITICAL

J3200

F-RT-BGA3

DDR3-SODIMM

KEY

516s0706

26

1

C3217

0.1UF

20%
10V

2

CERM
402

DQS0*

(1 OF 2)

RESET*

DQS3*

1

C3216

0.1UF

20%
10V

2

CERM
402

VREFDQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0
VSS

15

DQ2

17

DQ3
VSS

21

DQ8

23

DQ9
VSS

27

DQS1*

29

DQS1
VSS

33

DQ10

35

DQ11
VSS

39

DQ16

41

DQ17
VSS

45

DQS2*

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3
VSS

67

DQ26

69

DQ27
VSS

C3230

2.2UF

20%

6.3V

CERM

402-LF

1

2

MEM_B_DQ<0>

MEM_B_DQ<1>

MEM_B_DM<0>

MEM_B_DQ<2>

MEM_B_DQ<3>

MEM_B_DQ<28>

MEM_B_DQ<24>

MEM_B_DQS_N<3>

MEM_B_DQS_P<3>

MEM_B_DQ<31>

MEM_B_DQ<30>

MEM_B_DQ<9>

MEM_B_DQ<8>

MEM_B_DQS_N<1>

MEM_B_DQS_P<1>

MEM_B_DQ<15>

MEM_B_DQ<10>

MEM_B_DQ<21>

MEM_B_DQ<17>

MEM_B_DM<2>

MEM_B_DQ<18>

MEM_B_DQ<22>

1

C3236

0.1UF

20%
10V

2

CERM

402

C3214

0.1UF

20%
10V
CERM
402

1

2

PP0V75_S3_MEM_VREFCA_B

1

C3212

0.1UF

20%
10V

2

CERM
402

44

1

2

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

1

C3235

2.2UF

20%

6.3V

2

CERM

402-LF

=PP0V75_S0_MEM_VTT_B

C3213

0.1UF

20%
10V
CERM
402

1

2

BI

BI

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI

C3231

0.1UF

20%
10V

CERM

402

1

2

C3215

0.1UF

20%
10V
CERM
402

8

1

C3219

0.1UF

20%
10V

2

CERM
402

MEM_B_DQ<4>

MEM_B_DQ<5>

MEM_B_DQS_N<0>

MEM_B_DQS_P<0>

MEM_B_DQ<6>

MEM_B_DQ<7>

MEM_B_DQ<29>

MEM_B_DQ<25>

MEM_B_DM<3>

MEM_RESET_L

MEM_B_DQ<26>

MEM_B_DQ<27>

MEM_B_DQ<13>

MEM_B_DQ<12>

MEM_B_DM<1>

MEM_B_DQ<14>

MEM_B_DQ<11>

MEM_B_DQ<20>

MEM_B_DQ<16>

MEM_B_DQS_N<2>

MEM_B_DQS_P<2>

MEM_B_DQ<19>

MEM_B_DQ<23>

1

2

C3220

0.1UF

20%
10V
CERM
402

1

2

C3221

0.1UF

20%
10V
CERM
402

1

C3222

0.1UF

20%
10V

2

CERM
402

1

C3223

0.1UF

2

20%
10V
CERM
402

D

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

IN

27 29

IN

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

IN

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

C

B

"Expansion" (bottom) slot

DDR3 SO-DIMM Connector B

SYNC_MASTER=BEN_K20

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

D

NONE

DRAWING NUMBER

051-8071

SHT

28 98

OF

SYNC_DATE=07/14/2008

REV.

B

A

8

76

5

4

3

2

1

87

www.vinafix.vn

6

5

4

3

21

D

D

DDR3 RESET Support

MCP79 cannot control this signal directly since it must be high in sleep and MCP MEM rails are not powered in sleep.

=PP1V5_S3_MEMRESET

8

3.3V input must be stable before
before 1.5V starts to rise to

=PP3V3_S5_MEMRESET

8

C

MEMRESET_HW

MEMRESET_HW

avoid glitch on MEM_RESET_L.

1

R3300

10K

5%
1/16W
MF-LF

402

2

MEM_RESET_RC_L

MEMRESET_HW

1

R3301

1/16W
MF-LF

20K

1

C3300

0.1UF

5%

20%
10V

2

CERM

402

402

2

5

MEMRESET_HW

1

R3305

20K

5%
1/16W
MF-LF
402

2

MEM_RESET

MEMRESET_HW

3

Q3305

MMDT3904-X-G

SOT-363-LF

4

2

1

R3310

1K

5%
1/16W
MF-LF
402

2

MEMRESET_HW

6

Q3305

MMDT3904-X-G

SOT-363-LF

1

MEM_RESET_L

MEMRESET_MCP

1

R3309

0

5%
1/16W
MF-LF
402

2

27 28

OUT

C

MCP_MEM_RESET_L

16

IN

B

B

DDR3 Support

051-8071

SHT

SYNC_DATE=04/01/2008

OF

29 98

A

REV.

B

A

SYNC_MASTER=M98_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

SCALE

NONE

8

76

5

4

3

2

1

87

www.vinafix.vn

PCIE_MINI_PRSNT_L

17

OUT

3

D

Q3401

SSM6N15FEAPE

SOT563

5

SG

4

D

17

OUT

MINI_CLKREQ_L

6

D

SG

1

Q3401

SSM6N15FEAPE

SOT563

2

6

AP_PWR_EN

5

21 33

IN

4

5V S3 WLAN FET

MOSFET

CHANNEL

RDS(ON)

LOADING 0.8 A (EDP)

3

FDC606P

P-TYPE

26 mOhm @4.5V

21

D

20347-325E-12

C

B

CRITICAL
518S0610

J3401

F-RT-SM

31

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

32

FDC606P_G

6521

C3450

0.1UF

10%
16V
X5R
402

Q3450

SOT-6

D

21

4

S

G

3

P5VWLAN_SS

C3451

0.033UF

=PP5V_S3_WLAN

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

1

1

10%
16V

2

X5R
402

R3450

100K

5%
1/16W
MF-LF

402

R3451

10K

5%
1/16W
MF-LF
402

2

21

VOLTAGE=5V

PM_WLAN_EN_L

8

33

IN

C

PCIE_MINI_D2R_P
PCIE_MINI_D2R_N

PCIE_MINI_R2D_P

7

90

PCIE_MINI_R2D_N

7

90

PCIE_CLK100M_MINI_CONN_P

7

96

PCIE_CLK100M_MINI_CONN_N

96

7

MINI_CLKREQ_Q_L

7

PCIE_WAKE_L

L3404

PLACEMENT_NOTE=Place close to J3401.

C3431

21

0.1uF

21

16V

C3430

7

17 90

OUT

7

17 90

OUT

7

17 31

OUT

10% 16V X5R

0.1uF

402X5R10%

PLACEMENT_NOTE=Place close to J3401.

L3401

90-OHM-100MA

DLP11S

SYM_VER-1

43

PLACEMENT_NOTE=Place close to J3401.

21

PCIE_MINI_R2D_C_P

402

PCIE_MINI_R2D_C_N

AIRPORT

PCIE_CLK100M_MINI_P

PCIE_CLK100M_MINI_N

1000 mA peak

750 mA nominal max

IN

IN

17 90

17 90

IN

IN

17 90

17 90

PP5V_WLAN

7

MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.5 mm
VOLTAGE=5V

FERR-120-OHM-1.5A

C3422

0.1uF

20%
10V

CERM

402

PLACEMENT_NOTE=Place close to J3401.

0402-LF

21

1

2

C3421

PP5V_WLAN_F PP5V_WLAN_R

30

MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.5 mm
VOLTAGE=5V

1

1

C3420

0.1uF

20%
10V

CERM

402

PLACEMENT_NOTE=Place close to Q3450.

10UF

20%
10V

2

2

X5R
805

PLACEMENT_NOTE=Place close to Q3450.

R3404

5%
1/10W
MF-LF

603

0

21

MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.5 mm
VOLTAGE=5V

L3406

PP3V3_S3_BT_F

NC

PP5V_S3_BTCAMERA_F

USB_CAMERA_CONN_P

7

96

USB_CAMERA_CONN_N

7

96

CONN_USB2_BT_P

7

96

CONN_USB2_BT_N

7

96

7

I2C_ALS_SDA
I2C_ALS_SCL

BI

IN

44

44

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V

L3402

90-OHM
DLP0NS

SYM_VER-1

43

PLACEMENT_NOTE=Place close to J3401.

21

ALS
CAMERA

USB_CAMERA_P

USB_CAMERA_N

275 mA peak

206 mA nominal max

C3452

0.1uF

20 91

OUT

20 91

OUT

CERM

1

20%
10V

2

402

L3405

21

FERR-120-OHM-1.5A

0402-LF

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V

=PP5V_S3_BTCAMERA

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V

8

C3462

0.1uF

CERM

20%
10V

402

21

FERR-120-OHM-1.5A

1

2

0402-LF

=PP3V3_S3_BT

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V

8

B

L3403

90-OHM
DLP0NS

SYM_VER-1

43

PLACEMENT_NOTE=Place close to J3401.

21

BLUETOOTH

USB_BT_P

USB_BT_N

20 91

BI

20 91

BI

MINI_RESET_CONN_L

7

A

8

76

TC7SZ08AFEAPE

SOT665

4

=PP3V3_S3_WLAN

5

A

Y

U3401

B

3

2

WLAN_SMIT_BUF

1

MINI_RESET_L

8

U3402

74LVC1G17DRL

SOT-553

25

IN

PP5V_WLAN_F

1

R3453

33K

5%
1/16W

1UF

6.3V
CERM

1

10%

2

402

MF-LF
402

2

WLAN_SMIT_RC

1

R3454

62K

5%
1/16W
MF-LF
402

2

5

4

2

NC

13

NC

C3453

5

30

R3455

1

5%
1/16W
MF-LF

402

21

WLAN_SMIT_RC_FET

3

D

2

Q3402

SSM3K15FV

SOD-VESM-HF

1

GS

4

Right Clutch Connector

SYNC_MASTER=M98_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

3

2

SCALE

NONE

051-8071

SHT

SYNC_DATE=05/01/2008

OF

30 98

1

A

REV.

B

87

www.vinafix.vn

6

5

4

3

21

D

D

EXPRESSCARD/34 FLEX CONNECTOR

L3502

90-OHM
DLP0NS

SYM_VER-1

USB_EXCARD_N

BI

USB_EXCARD_P

BI

PCIE_CLK100M_EXCARD_N

IN

PCIE_CLK100M_EXCARD_P

IN

PCIE_EXCARD_R2D_C_N

IN

PCIE_EXCARD_R2D_C_P

IN

INPUT DECOUPLING

=PP3V3_S3_EXCARD

8

31

=PP1V5_S0_EXCARD

8

31

1

C3530

2

1

C3534

2

0.1uF

20%
10V
CERM
402

0.1uF

20%
10V
CERM
402

1

2

1

2

C3531

10uF

20%

6.3V
X5R
603

C3535

10uF

20%

6.3V
X5R
603

20 91

20 91

17 90

17 90

17 90

17 90

C

OMIT

R3504

SHORT

=PP3V3_S3_EXCARD

8

31

=PP3V3_S0_EXCARD

8

31

=PP1V5_S0_EXCARD

8

31

SMC_EXCARD_PWR_EN

41

IN

TP_EXCARD_STBY_L

25

20 42

IN

IN

EXCARD_RESET_L

EXCARD_OC_L

B

NONE
NONE
NONE

402

OMIT

R3503

SHORT

NONE
NONE
NONE

402

OMIT

R3502

SHORT

NONE
NONE
NONE

402

R3500

MF-LF

21

21

21

CRITICAL

U3500

TPS2231

PP3V3_S3_EXCARD_R
PP3V3_S0_EXCARD_R
PP1V5_S0_EXCARD_R

21

0

402

1/16W

5%

EXCARD_SHDN_L_R

17

2

12

20

1

6

19

NC
NC

13

NC

14

NC

16

NC

AUXIN
VIN3P3
VIN1P5

SHDN*
STBY*
SYSRST*
OC*

4

NC0

5

NC1
NC2
NC3
NC4

QFN

AUXOUT
VOUT3P3
VOUT1P5

PERST*

CPUSB*

RCLKEN

THRML_PAD

GND

7

CPPE*

15

3

11

8

10

9

EXCARD_RCLKEN

18

21

43

PLACEMENT_NOTE=Place close to J3500

L3503

90-OHM-100MA

43

PLACEMENT_NOTE=Place close to J3500

21

DLP11S

SYM_VER-1

21

PLACEMENT_NOTE=Place close to J3500

C3571

21

10%

C3570

PLACEMENT_NOTE=Place close to J3500

31

0.1uF

X5R 40216V

VOLTAGE=3.3V

MIN_LINE_WIDTH=.3mm

MIN_NECK_WIDTH=0.2mm

VOLTAGE=3.3V

MIN_LINE_WIDTH=.6mm

MIN_NECK_WIDTH=0.2mm

VOLTAGE=1.5V

MIN_LINE_WIDTH=.6mm

MIN_NECK_WIDTH=0.2mm

10% 16V X5R 402

USB2_EXCARD_CONN_N

USB2_EXCARD_CONN_P

PCIE_CLK100M_EXCARD_CONN_N

PCIE_CLK100M_EXCARD_CONN_P

21

0.1uF

PCIE_EXCARD_R2D_N
PCIE_EXCARD_R2D_P

OUTPUT DECOUPLING

PP3V3_S3_EXCARD_SWITCH

1

2

PP3V3_S0_EXCARD_SWITCH

1

2

PP1V5_S0_EXCARD_SWITCH

1

2

1

C3500

0.1uF

20%
10V

2

CERM
402

1

C3501

0.1uF

10%
16V

2

X5R
402

1

C3502

0.1uF

10%
16V

2

X5R
402

PLT_RESET_SWITCH_L

C3503

10uF

20%

6.3V
X5R
603

C3504

10uF

20%

6.3V
X5R
603

C3505

10uF

20%

6.3V
X5R
603

EXCARD_CPUSB_L

EXCARD_CPPE_L

7

31 96

7

31 96

PCIE_EXCARD_R2D_N

7

31 90

PCIE_EXCARD_D2R_P

7

17 90

OUT

PCIE_CLK100M_EXCARD_CONN_N

7

7

31 96

7

31 96

7

31 90

7

31 90

7

31

7

31

7

31

7

31

7

31

7

31

31 96

EXCARD_CLKREQ_CONN_L

7

31

PP3V3_S0_EXCARD_SWITCH

7

31

PP3V3_S3_EXCARD_SWITCH

7

31

PP1V5_S0_EXCARD_SWITCH

7

31

=SMBUS_EXCARD_SDA

44

BI

EXCARD_CPUSB_L

7

31

USB2_EXCARD_CONN_N

7

31 96

EXCARD_CPPE_L

7

31 17

R3501

NC

MF-LF

CRITICAL

J3500

502250-8627

F-RT-SM

26

24

22

20

18

16

14

12

10

8

6

4

2

518S0647

0

402

29

27

25

23

21

19

17

15

13

11

9

7

5

NC

3

1

28

21

5%

1/16W

PCIE_CLK100M_EXCARD_CONN_P

PCIE_EXCARD_PRSNT_L

PCIE_EXCARD_R2D_P

PCIE_EXCARD_D2R_N

PP3V3_S0_EXCARD_SWITCH

PP1V5_S0_EXCARD_SWITCH

EXCARD_CPPE_L

PLT_RESET_SWITCH_L

PCIE_WAKE_L

=SMBUS_EXCARD_SCL

USB2_EXCARD_CONN_P

7

31 90

7

17 90

OUT

7

31 96

7

31

7

31

7

31

7

17 30

OUT

7

31

44

BI

7

31 96

C

B

=PP3V3_S3_EXCARD

8

31

5

74HC1G00GWDG

A

EXCARD_CPPE_L

7

31

C3550

0.1uF

CERM

20%
10V

402

EXCARD_CPUSB_L

7

31

8

1

2

1

2

U3551

SC70-5

4

3

76

SMC_EXCARD_CP

=PP3V3_S0_EXCARD

8

31

1

R3561

100K

41 42

OUT

EXCARD_CLKREQ_CONN_L

7

31

1/16W
MF-LF

1%

402

2

B1

EXCARD_RCLKEN

31

EXCARD_CLKREQ_CONN

A2

U3561

SN74LVC1G04YZPR

C2

BGA

C1

C3560

0.1uF

CERM

1

20%
10V

2

402

1

2

U3560

5

3

74HC1G00GWDG

SC70-5

4

EXCARD_CLKREQ_L

17

OUT

SYNC_MASTER=BEN_K20

APPLE INC.

5

4

3

2

ExpressCard Connector

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

SHT

051-8071

31

1

SYNC_DATE=10/15/2008

REV.

B

OF

98

A

87

www.vinafix.vn

6

5

4

3

21

=PP1V05_ENET_PHY

(221mA typ - 1000base-T)

D

=PP3V3_ENET_PHY

R3796

5%
1/16W

402

MF-LF

R3730

2.49K

1/16W
MF-LF

8

1

CRITICAL

L3705

FERR-120-OHM-1.5A

0402-LF

2

PP3V3_ENET_PHYAVDD

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

Alias to =PP3V3_ENET_PHY for internal switcher.

Alias to GND for external 1.05V supply.

22

21

ENET_CLK125M_TXCLK_R

RTL8211_PHYRST_L

RTL8211_RSET

1

1%

402

2

R3731

1/16W
MF-LF

1

22

5%

402

2

=RTL8211_ENSWREG

9

IN

ENET_TXD<0>

18 92

IN

ENET_TXD<1>

18 92

IN

ENET_TXD<2>

18 92

IN

ENET_TXD<3>

18 92

IN

ENET_TX_CTRL

18 92

IN

ENET_MDC

18 92

IN

ENET_MDIO

18 92

BI

RTL8211_CLK125

RTL8211_CLK25M_CKXTAL1

33 92

IN

TP_RTL8211_CKXTAL2

1

C3700

0.1UF

10%
16V

2

X5R
402

1

C3705

0.1UF

10%
16V

2

X5R
402

R3720

1/16W
MF-LF

10K

1

C3701

0.1UF

10%
16V

2

X5R
402

1

C3706

0.1UF

10%
16V

2

X5R
402

NO STUFF

1

R3725

4.7K

5%

402

5%
1/16W
MF-LF

402

2

1

C3702

0.1UF

10%
16V

2

X5R
402

41

39

22

23

24

25

26

27

30

31

29

46

32

42

43

6

ENSWREG

TXC

TXD[0]
TXD[1]
TXD[2]
TXD[3]

TXCTL

MDC
MDIO

PHYRSTB*

RSET

CLK125

CKXTAL1
CKXTAL2

AVDD33

1

2

372115

DVDD33

MANAGEMENT

REFERENCE

C3714

0.1UF

10%
16V
X5R
402

45

44

OMIT

VDDREG

CRITICAL

U3700

RTL8211CLGR

TQFP

RGMII/MII

RESET

CLOCK

1

2

3

28

FB12

MEDIA DEPENDENT

LED

36

40

10

DVDD12

AVDD12

REGOUT

RXD[0]

RXD[1]/TXDLY

RXD[2]/AN0
RXD[3]/AN1

RXCTL

MDI+[0]
MDI-[0]

MDI+[1]
MDI-[1]

MDI+[2]
MDI-[2]

MDI+[3]
MDI-[3]

LED0/PHYAD0
LED1/PHYAD1

LED2/RXDLY

RXC

GND

7

473320

C3790 reserved for EMI
per RealTek request.
C3790 should be placed close to U3700.19

(43mA typ - 1000base-T)

WF: Marvell numbers, update for Realtek

(19mA typ - Energy Detect)

C

ENET_CLK125M_TXCLK

18 92

IN

PLACE R3796 CLOSE TO U1400, PIN D24

R3724

0

402

5%
1/16W

MF-LF

21

NO STUFF

1

C3725

0.1UF

20%
10V

2

CERM
402

ENET_RESET_L

18 92

IN

B

C3710

0.1UF

C3715

0.1UF

R3750

48

19

14

16

17

18

13

1

2

4

5

8

9

11

12

34

35

38

10%
16V
X5R
402

10%
16V
X5R
402

4.7K

1/16W
MF-LF

1

2

1

2

1

5%

402

2

NO STUFF

C3790

10PF

1

C3711

0.1UF

10%
16V

2

X5R
402

1

C3716

0.1UF

10%
16V

2

X5R
402

1

R3751

4.7K

5%
1/16W
MF-LF
402

2

ENET_CLK125M_RXCLK_R

92

ENET_RXD_R<0>

92

ENET_RXD_R<1>

92

ENET_RXD_R<2>

92

ENET_RXD_R<3>

92

ENET_RXCTL_R

ENET_MDI_P<0>
ENET_MDI_N<0>

ENET_MDI_P<1>
ENET_MDI_N<1>

ENET_MDI_P<2>
ENET_MDI_N<2>

ENET_MDI_P<3>
ENET_MDI_N<3>

RTL8211_PHYAD0
RTL8211_PHYAD1
RTL8211_RXDLY

1

5%

50V

2

CERM

402

FERR-120-OHM-1.5A

PP1V05_ENET_PHYAVDD

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

R3755

4.7K

1/16W
MF-LF

402

5%

CRITICAL

BI

BI

BI

BI

BI

BI

BI

BI

1

2

L3715

( 7mA typ - Energy Detect)

1

WF: Marvell numbers, update for Realtek

0402-LF

2

=PP3V3_ENET_PHY_VDDREG

If internal switcher is used, must place 1x 22uF &
1x 0.1uF caps within 5mm of U3700 pins 44 & 45.

NOTE: VDDREG rise time must be >1ms to avoid damage to switcher.

1

R3752

4.7K

1/16W
MF-LF

=RTL8211_REGOUT

5%

If internal switcher is used, must place inductor within 5mm
of U3700, and 1x 22uF & 1x 0.1uF caps within 5mm of inductor.

402

2

If internal switcher is not used, VDDREG and REGOUT can float.

R3790

R3791
R3792
R3793
R3794

R3795

34 92

34 92

34 92

34 92

34 92

34 92

34 92

34 92

1

1

R3756

4.7K

1/16W
MF-LF

R3757

4.7K

5%

5%

1/16W
MF-LF
402

402

2

2

8

D

9

9

C

22

22
22

22

21

21

5%

21

5%

21

5%

21

5%

21

5%

1/16W5%MF-LF

1/16W MF-LF

1/16W MF-LF

1/16W MF-LF22402

1/16W MF-LF22402

MF-LF1/16W

ENET_CLK125M_RXCLK

402

ENET_RXD<0>

402

ENET_RXD<1>

402

ENET_RXD<2>
ENET_RXD<3>

ENET_RX_CTRL

402

18 92

OUT

18 92

OUT

18 92

OUT

18 92

OUT

18 92

OUT

18 92

OUT

B

A

Configuration Settings:

PHYAD = 01 (PHY Address 00001)
AN[1:0] = 11 (Full auto-negotiation)
RXDLY = 0 (RXCLK transitions with data)
TXDLY = 0 (No TXCLK Delay)

8

76

Ethernet PHY (RTL8211CL)

SYNC_MASTER=SUMA_K20

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

5

4

3

2

SCALE

NONE

051-8071

SHT

SYNC_DATE=07/22/2008

OF

1

A

REV.

B

9832

87

www.vinafix.vn

6

5

4

3

21

3.3V ENET FET

@ 2.5V Vgs:
Rds(on) = 90mOhm max
I(max) = 1.7A (85C)

=PP3V3_S5_P3V3ENETFET

8 8

D

Q3801

SSM6N15FEAPE

=P3V3ENET_EN

9

IN

MOBILE:

Recommend aliasing PM_SLP_RMGT_L and
=P3V3ENET_EN. Nets separated on
ARB for alternate power options.

R3800

SOT563

5

1/16W
MF-LF

10K

5%

402

1

2

P3V3ENET_EN_L

3

D

SG

4

R3810

100K

5%
1/16W
MF-LF

402

21

1

C3811

0.033UF

10%
16V

2

X5R
402

P3V3ENET_SS

CRITICAL

Q3810

NTR4101P

SOT-23-HF

2

1

G

DS

C3810

0.01UF

21

10%
16V

CERM

402

3

=PP3V3_ENET_FET

D

WLAN Enable Generation

"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))

NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.

PM_WLAN_EN_L

C

Q3805

SSM6N15FEAPE

SOT563

Q3805

SSM6N15FEAPE

SOT563

2

5

21 30

21 36 41 42

21 36 41 67 82 84

IN

IN

7

IN

AP_PWR_EN

SMC_ADAPTER_EN

PM_SLP_S3_L

Pull-up is with power FET.

6

D

SG

1

AC_OR_S0_L

3

D

SG

4

6

D

SG

1

30

OUT

Q3801

SSM6N15FEAPE

SOT563

2

=PP3V3_S5_P1V05ENETFET

8

Q3841

SSM6N15FEAPE

SOT563

R3842

69.8K

1/16W
MF-LF

1

1%

402

2

3

D

=PP1V05_ENET_P1V05ENETFET

8

P1V05ENET_EN_L

1.05V ENET FET

1

C3840

0.1UF

20%
10V

2

CERM

R3840

100K

5%
1/16W
MF-LF

402

21

P1V05ENET_SS

R3841

1/16W
MF-LF

SSM6N15FEAPE

10K

1%

402

21

402

Q3841

SOT563

2

P1V05ENET_EN_L_RC

C

1.8V Vgs

3

CRITICAL

D

Q3840

1

G

6

D

SG

1

SI2312BDS

SOT23

S

2

=PP1V05_ENET_FET

1

C3841

0.01UF

10%
16V

2

CERM
402

8

5

SG

=P1V05ENET_EN

9

B

IN

Non-ARB:

Recommend aliasing PM_SLP_RMGT_L and
=P1V05ENET_EN. Nets separated on
ARB for alternate power options.

RTL8211 25MHz Clock

NOTE: MCP79 can provide 25MHz clock, but clock runs whenever RMGT rails are powered.

A

Designs must ensure PHY is powered whenever RMGT rails are, or use separate crystal.

18 92

IN

MCP_CLK25M_BUF0_R

PLACEMENT_NOTE=Place close to U1400

R3895

1/16W
MF-LF

4

22

21

RTL8211_CLK25M_CKXTAL1

5%

402

B

Ethernet & AirPort Support

SYNC_DATE=07/15/2008SYNC_MASTER=SUMA_K20

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

32 92

OUT

APPLE INC.

AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

051-8071

SHT

OF

33 98

REV.

A

B

8

76

5

4

3

2

1

87

www.vinafix.vn

Page Notes

Power aliases required by this page:
(NONE)

Signal aliases required by this page:
(NONE)

BOM options provided by this page:
(NONE)

6

5

4

3

21

D

Place one of 0.1uf cap close to each centertap pin of transformer

D

ENETCONN_CTAP

1

C3900

0.1UF

10%
16V

2

X5R
402

1

C3902

0.1UF

10%
16V

2

X5R
402

1

C3904

0.1UF

10%
16V

2

X5R
402

1

C3906

0.1UF

10%
16V

2

X5R
402

CRITICAL

T3900

ENET_MDI_P<0>

32 92

BI

ENET_MDI_N<0>

32 92

BI

C

ENET_MDI_N<1> ENETCONN_N<1>

32 92

BI

ENET_MDI_P<1>

32 92

BI

1

2

3

4

5

SM

TX

TLA-6T213HF

RX

CRITICAL

T3901

ENET_MDI_N<2>

32 92

BI

ENET_MDI_P<2>

32 92

BI

ENET_MDI_N<3>

32 92

BI

ENET_MDI_P<3>

32 92

BI

Transformers should be
mirrored on opposite

B

C3931

10PF

5%
50V
CERM
402-1

1

2

1

C3910

10PF

5%
50V

2

CERM
402-1

1

C3911

10PF

5%
50V

2

CERM
402-1

1

C3920

10PF

5%
50V

2

CERM
402-1

1

C3921

10PF

5%
50V

2

CERM
402-1

1

C3930

10PF

5%
50V

2

CERM
402-1

1

2

sides of the board

C3940

10PF

5%
50V
CERM
402-1

1

C3941

10PF

5%
50V

2

CERM
402-1

1

2

3

4

5

SM

TX

TLA-6T213HF

RX

12

ENETCONN_P<0>

96

11

ENETCONN_N<0>

96

10

ENET_CTAP0

9

ENET_CTAP1

8

96

76

ENETCONN_P<1>

96

12

ENETCONN_N<2>

96

11

ENETCONN_P<2>

96

10

ENET_CTAP2

9

ENET_CTAP3

8

ENETCONN_N<3>

96

76

ENETCONN_P<3>

96

R3900

1/16W
MF-LF

402

CRITICAL

J3900

RJ45-M97-2

F-RT-TH

9

OMIT

10

1
2
3
4
5
6
7
8

11
12

R3901

1/16W
MF-LF

402

1

R3902

75

75

5%

5%

1/16W
MF-LF
402

2

2

1

75

5%

2

1

1

R3903

75

5%
1/16W
MF-LF
402

2

ENET_BOB_SMITH_CAP

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

CRITICAL

C3908

1000PF

10%

2KV
CERM
1206

21

C

B

PLACEMENT_NOTE=Place on MDI lines so there are no stubs all 8 caps.

PLACEMENT_NOTE=Place on MDI lines so there are no stubs all 8 caps.

PLACEMENT_NOTE=Place on MDI lines so there are no stubs all 8 caps.

PLACEMENT_NOTE=Place on MDI lines so there are no stubs all 8 caps.

PLACEMENT_NOTE=Place on MDI lines so there are no stubs all 8 caps.

PLACEMENT_NOTE=Place on MDI lines so there are no stubs all 8 caps.

PLACEMENT_NOTE=Place on MDI lines so there are no stubs all 8 caps.

PLACEMENT_NOTE=Place on MDI lines so there are no stubs all 8 caps.

A

8

76

PART NUMBER

514-0636

QTY

DESCRIPTION

1

CONN,RJ45,HB,10/100TX

REFERENCE DES

J3900

CRITICAL

CRITICAL

BOM OPTION

Ethernet Connector

SYNC_MASTER=SUMA_K20 SYNC_DATE=07/15/2008

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

5

4

3

2

SCALE

NONE

SHT

051-8071

34

1

REV.

OF

98

A

B

87

www.vinafix.vn

6

5

4

3

21

21

21

=PP3V3_FW_FWPHY

PLACEMENT_NOTE=Place C4170 close to U1400
PLACEMENT_NOTE=Place C4171 close to U1400

C4170

C4171

C4175

C4176

21

10%

0.1UF

21

10%

0.1UF

21

10%

0.1UF

21

10%

0.1UF

PLACEMENT_NOTE=Place C4175 close to U4000
PLACEMENT_NOTE=Place C4176 close to U4000

FW643_LDO

R4165

1

R4164

10K

5%
1/16W
MF-LF
402

2

SYNC_MASTER=M98_MLB

7 mA I/O

C4121

1UF

6.3V
CERM

C4130

1UF

6.3V
CERM

1

10%

2

402

114 mA FireWire PHY

1

10%

2

402

17 mA PCIe SerDes25 mA PCIe SerDes

1

C4120

1UF

10%

6.3V
2

CERM

402

D

L4110

=PP1V0_FW_FWPHY

8

135 mA

120-OHM-0.3A-EMI

0402-LF

21

PP1V0_FW_FWPHY_AVDD

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.0V

1

C4110

2

1UF

10%

6.3V
CERM
402

1

C4111

2

1UF

10%

6.3V
CERM
402

110 mA Digital Core

1

C4100

2

1UF

10%

6.3V
CERM
402

1

C4101

2

1UF

10%

6.3V
CERM
402

1

2

C4102

1UF

10%

6.3V
CERM
402

1

C4103

2

1UF

10%

6.3V
CERM
402

1

2

C4104

1UF

10%

6.3V
CERM
402

1

C4105

2

1UF

10%

6.3V
CERM
402

1

C4106

2

1UF

10%

6.3V
CERM
402

C4122

1UF

6.3V
CERM

C4131

1UF

6.3V
CERM

C4135

1UF

6.3V
CERM

1

10%

2

402

1

10%

2

402

1

10%

2

402

0 mA VReg PWR

C4141

0.1UF

C4123

C4132

C4136

20%
10V

CERM

402

6.3V
CERM

6.3V
CERM

6.3V
CERM

1

2

1UF

1UF

1UF

10%

402

10%

402

10%

402

1

2

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

1

2

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

1

2

1

2

PP3V3_FW_FWPHY_VDDA

PP3V3_FW_FWPHY_VP25

C4124

C4140

1UF

10%

6.3V
CERM
402

1UF

6.3V
CERM

1

10%

2

402

L4130

120-OHM-0.3A-EMI

0402-LF

L4135

120-OHM-0.3A-EMI

0402-LF

C

N11N3M12

MISCELLANEOUS

F8

F7

F10

C1

1394 PHY

G4

G12F1C12

VDD33

G8G7G6

OMIT

CRITICAL

U4100

FW643

BGA

VSS

H4

G10

L11

H7D7H6

L1

K2

B1

A1

B13

ATBUSB

NC

A13

ATBUSH

NC

A11

ATBUSN

NC

=FW_PHY_DS0

37

IN

=FW_PHY_DS1

37

IN

=FW_PHY_DS2

37

IN

FW_P0_TPA_N

37 93

BI

FW_P0_TPA_P

37 93

BI

FW_P1_TPA_N

37 93

BI

FW_P1_TPA_P

37 93

BI

FW_P2_TPA_N

37

BI

FW_P2_TPA_P

37

BI

FW_P0_TPB_N

37 93

BI

FW_P0_TPB_P

37 93

BI

FW_P1_TPB_N

37 93

BI

FW_P1_TPB_P

37 93

BI

FW_P2_TPB_N

37

=PPVP_FW_PHY_CPS

37

1

R4160

B

C4150

22PF

5%

50V

CERM

402

C4151

22PF

5%

50V

CERM

402

21

21

NC
NC

FW_CLK24P576M_XO

CRITICAL

Y4150

24.576MHZ

SM-3.2X2.5MM

42

31

R4150

412

1%
1/16W
MF-LF

402

200K

1%
1/16W
MF-LF

402

2

21

1

1/16W
MF-LF

470K

1/16W
MF-LF

1

R4170

191

1%

1%
1/16W
MF-LF

402

402

2

2

1

1

C4162

0.33UF

5%

10%

6.3V

2

402

CERM-X5R

402

2

R4161

2.94K

R4162

BI

37

BI

37

BI

37

BI

37

BI

7

FW_P2_TPB_P

FW_P0_TPBIAS
FW_P1_TPBIAS
FW_P2_TPBIAS

FW643_R0
FW643_TPCPS

TP_FW643_NAND_TREE
FW643_REXT
FW_CLK24P576M_XO_R
FW_CLK24P576M_XI

TP_FW643_SE
TP_FW643_SM
TP_FW643_MODE_A
TP_FW643_CE
TP_FW643_FW620_L
TP_FW643_JASI_EN
TP_FW643_AVREG
TP_FW643_VBUF
FW643_PU_RST_L

TP_FW643_OCR10_CTL

F12

DS0

(IPD) NT-19

E12

DS1

(IPD) NT-20

E13

DS2

(IPD) NT-21

B8

TPA0N

A8

TPA0P

B5

TPA1N

A5

TPA1P

B3

TPA2N

A3

TPA2P

B9

TPB0N

A9

TPB0P

B6

TPB1N

A6

TPB1P

B4

TPB2N

A4

TPB2P

B7

TPBIAS0

C3

TPBIAS1

A2

TPBIAS2

B11

R0

B10

TPCPS

K1

NAND_TREE

L8

REXT

F13

XO

G13

XI

NT-9

M13

SE

(IPD)

N13

SM

(IPD)

J2

MODE_A
CE

(IPD)

FW620*

(IPU)
JASI_EN
AVREG
VBUF
FW_RESET*

OCR_CTL_V10
OCR_CTL_V12

D4

B2

(IPD) NT-18

(IPD) NT-11

L13

D12

D1

A10

H13

K13

J12

J13

NC

H2

H12

E10E2C13

B12

VDD10

NT-OUT

NOTE: NT-xx notes show
NAND tree order.

(IPU) NT-8

(Reserved)

D10

F6F4E9E5E4

M2

L3

J1

D8D6D5

A12

VDDH

L10

VP25

VP

PCI EXPRESS PHY

TEST CONTROLLER

FIXME!!! - TYPO IN SYMBOL REGCTL

POWER MANAGEMENT

NT-12 (IPD)

NT-13

SCIF

SERIAL EEPROM
CONTROLLER

CHIP RESET

J9J5J4

H8

J10

H10

VREG_PWR

NT-10 (IPD)

NT-16 (IPD)
NT-14 (IPD)

NT-15 (IPD)

K8D9K7K5K4

PCIE_RXD0N
PCIE_RXD0P
PCIE_TXD0N
PCIE_TXD0P

NT-4 (IPU)
NT-3 (IPU)

NT-1 (IPU)

NT-2 (IPU)

VAUX_DETECT

VAUX_DISABLE

(OD)

NT-17

NT-5

VREG_VSS

K6L7K9

K10

REFCLKN
REFCLKP

(IPU)

TRST*

WAKE*

REGCLT

CLKREQN

SCIFCLK
SCIFDAIN
SCIFDOUT

SCIFMC

NT-7
NT-6

PERST*

L12

TCK
TDI
TDO
TMS

SCL
SDA

N8

90

N7

N5

N6

N9

N10

M4

N2

M1

M3

N1

C2

D13

E1

D2

L2

G2

G1

H1

F2

N12

M11

N4

PCIE_FW_R2D_N
PCIE_FW_R2D_P

90

PCIE_FW_D2R_C_N

90

PCIE_FW_D2R_C_P

90

PCIE_CLK100M_FW_N
PCIE_CLK100M_FW_P

TP_FW643_TCK
TP_FW643_TDI
TP_FW643_TDO
TP_FW643_TMS

FW643_TRST_L

FW_PME_L
FW643_REGCTL
FW643_VAUX_DETECT
TP_FW643_VAUX_ENABLE
FW_CLKREQ_L

TP_FW643_SCIFCLK
TP_FW643_SCIFDAIN
TP_FW643_SCIFDOUT
TP_FW643_SCIFMC

FW643_SCL
TP_FW643_SDA

FW_RESET_L

1

R4163

10K

5%
1/16W
MF-LF
402

2

17 90

IN

17 90

IN

7

19

OUT

17

OUT

25

IN

K12

L9

L6

L5

A

APPLE INC.

8

35 37

138 mA

16V

PCIE_FW_R2D_C_N

402X5R

16V

PCIE_FW_R2D_C_P

402X5R

16V

PCIE_FW_D2R_N

402X5R

16V

PCIE_FW_D2R_P

402X5R

17 90

IN

17 90

IN

17 90

OUT

17 90

OUT

=PP3V3_FW_FWPHY

1

1

R4166

10K

10K

5%

5%
1/16W
MF-LF

1/16W
MF-LF
402

402

2

2

FireWire LLC/PHY (FW643)

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

051-8071

SHT

8

35 37

SYNC_DATE=04/01/2008

OF

35 98

D

C

B

A

REV.

B

8

76

5

4

3

2

1

87

www.vinafix.vn

Page Notes

Power aliases required by this page:

- =PPBUS_S5_FWPWRSW (system supply for bus power)

- =PP3V3_FW_LATEVG_ACTIVE

- =PPVP_FW_SUMNODE (power passthru summation node)

Signal aliases required by this page:
(NONE)

BOM options provided by this page:

- FW_PORT_FAULT_PU

D

C

=PPVIN_S5_FWPWRSW

8

36

NO STUFF

C4263

2.2UF

20%
10V

X5R-CERM

402

6

5

4

3

21

FireWire Port Power Switch

CRITICAL

Q4260

NDS9407

=PPVIN_S5_FWPWRSW

8

36

1

2

SSM6N15FEAPE

R4260

470K

5%
1/16W
MF-LF
402

2

FWPWR_EN_L_DIV

1

R4261

330K

5%
1/16W
MF-LF
402

2

FWPWR_EN_L

6

D

SG

1

FW_PORTPWR_EN_FET

Q4263

SOT563

2

Q4261

SSM6N15FEAPE

SOT563

6

D

SG

1

4

Q4262

SOT-963

N-CHN

2

FW_LVG_NEW

Q4262

S

G

5

1

2

FW_PORTPWR_EN_R

6

D

G

S

1

D

3

P-CHN

FW_LVG_NEW

R4265

10K

5%
1/16W
MF-LF
402

PPVIN_S5_FWPWRSW_FET

NTUD3127CXXG

SOT-963

Enables port power when machine

Enables port power when machine
is running or on AC.

is running or on AC.

SMC_ADAPTER_EN

21 33 41 42

IN

PM_SLP_S3_L

7

21 33 41 67 82 84

IN

FW_PORTPWR_EN

36

FW_LVG_NEW

R4262

10

5%
1/16W
MF-LF

402

SSM6N15FEAPE

21

Q4261

SOT563

1

2

FW_LVG_NEW

1

R4263

10K

5%
1/16W
MF-LF
402

2

PPVIN_S5_FWPWRSW_R

FW_LVG_NEW

NTUD3127CXXG

C4260

0.01uF

5

CERM

20%
16V

402

D

SG

1

2

3

4

FW_LVG_NEW

1

R4264

0

5%
1/16W
MF-LF
402

2

SOI-HF

3

2

1

8

7

6

5

4

=PPVOUT_FW_FWPWRSW

8

D

C

FW_PORTPWR_EN_L

CRITICAL

F4260

=PPBOOST_FW_FWPWRSW_F

Late-VG Event Detection

=PP3V3_FW_LATEVG_ACTIVE

8

PP2V4_FW_LATEVG

37

1

B

R4211

1/16W
MF-LF

C4211

100pF

CERM

1

R4212

10K

10K

1%

5%

1/16W
MF-LF
402

402

2

2

P2V4_FWLATEVG_RC

FWLATEGV_3V_REF

1

R4213

1

80.6K

1%

5%

50V

402

1/16W
MF-LF

2

402

2

4

3

V+

V-

R4210

200K

1%
1/16W
MF-LF

402

2

5

U4210

LMC7211

SM-HF

1

21

1

C4210

0.1UF

20%
10V

2

CERM
402

D4219

SOD-123

LATEVG_EVENT_L

FWLATEVG_3V_REF Hysteresis:

2.95V when port power is on

2.81V on late Vg event and port power is off

21

MBR0540XXH

1

R4219

2.0M

5%
1/16W
MF-LF
402

2

1

2

C4219

0.33UF

10%
10V
CERM-X5R
603

FW_PORTPWR_EN

36

Q4263

SSM6N15FEAPE

SOT563

FW_LVG_NEW

1

R4266

10K

5%
1/16W
MF-LF
402

2

3

D

5

SG

4

1.5A-24V

1812L15024HF

21

PP10V_FW_D

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=10V

CRITICAL

D4260

2

1

PDS540XF

PWRDI5

3

=PPBOOST_S5_FW_FET

8 8

B

FireWire Port Power

A

SYNC_MASTER=YWU_K20

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

SCALE

NONE

051-8071

SHT

SYNC_DATE=05/28/2008

OF

36 98

A

REV.

B

8

76

5

4

3

2

1

87

www.vinafix.vn

Page Notes

Power aliases required by this page:

- =PPVP_FW_PORT1

- =PP3V3_FW_LATEVG

- =GND_CHASSIS_FW_PORT1

- =GND_CHASSIS_FW_EMI_R

Signal aliases required by this page:
(NONE)

D

NOTE: This page is expected to contain
the necessary aliases to map the
FireWire TPA/TPB pairs to their
appropriate connectors and/or to
properly terminate unused signals.

BOM options provided by this page:
(NONE)

NOTE: FireWire TPA/TPB pairs are NOT
constrained on this page. It is
assumed that FireWire PHY page will
provide the appropriate constraints
to apply to entire TPA/TPB XNets.

1394b implementation based on Apple
FireWire Design Guide (FWDG 0.6, 5/14/03)

FW_P1_TPBIAS

35

C

FW_P1_TPA_P

35 93

FW_P1_TPA_N

35 93

FW_P1_TPB_P

35 93

FW_P1_TPB_N

35 93

B

Termination

Place close to FireWire PHY

TI PHYs require 1uF even though
FW spec calls out 0.33uF

1

C4360

0.33UF

10%

6.3V

2

CERM-X5R
402

SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=EMPTY

1

R4360

56.2

1%
1/16W
MF-LF
402

2

SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=EMPTY

1

R4362

56.2

1%
1/16W
MF-LF
402

2

FW_PORT1_TPB_C

1

C4364

220pF

5%
25V

2

CERM
402

R4361

56.2

1/16W
MF-LF

R4363

56.2

1/16W
MF-LF

R4364

4.99K

1/16W
MF-LF

1

1%

402

2

1

1%

402

2

1

1%

402

2

FW_PORT1_TPA_P

MAKE_BASE=TRUE

FW_PORT1_TPA_N

MAKE_BASE=TRUE

FW_PORT1_TPB_P

MAKE_BASE=TRUE

FW_PORT1_TPB_N

MAKE_BASE=TRUE

6

FireWire PHY Config Straps

Configures PHY for:

- 1-port Portable Power Class (0)

- Port "1" Bilingual (1394B)

SOT-363

BSS8402DW

(SYM-VER2)

=PPVP_FW_PHY_CPS_FET

8

1

R4311

470K

5%
1/16W
MF-LF

402

2

CPS_EN_L_DIV

1

R4312

330K

5%
1/16W
MF-LF

402

2

CPS_EN_L

37

37

37

37

8

35 37

=PP3V3_FW_FWPHY

SGD

4

5

6

D

G

2

S

1

Q4300

Q4300

BSS8402DW

SOT-363

(SYM-VER1)

8

35 37

3

=PP3V3_FW_FWPHY

PPVP_FW_CPS

MIN_LINE_WIDTH=0.4 MM

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=10V

21

D

35

35

35

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

3

7

7

7

7

7

7

7

7

1

2

FWPHY_DS0

MAKE_BASE=TRUE

FWPHY_DS2

MAKE_BASE=TRUE

FWPHY_DS1

MAKE_BASE=TRUE

4

=FW_PHY_DS0

=FW_PHY_DS2

=FW_PHY_DS1

NC_FW0_TPBIAS
NC_FW2_TPBIAS
NC_FW0_TPAN
NC_FW0_TPAP
NC_FW2_TPAN
NC_FW2_TPAP

NC_FW0_TPBN
NC_FW0_TPBP
NC_FW2_TPBN
NC_FW2_TPBPFW_P2_TPB_P

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

5

1

10K

R4380

10K

1/16W
MF-LF

R4381

10K

1%
1/16W
MF-LF

402

FW_P0_TPBIAS

35

FW_P2_TPBIAS

35

FW_P0_TPA_N

35 93

FW_P0_TPA_P

35 93

FW_P2_TPA_N

35

FW_P2_TPA_P

35

FW_P0_TPB_N

35 93

FW_P0_TPB_P

35 93

FW_P2_TPB_N

35

35

1%

402

1

2

1%

402

2

R4382

1/16W
MF-LF

C

MAKE_BASE=TRUE

=PPVP_FW_PHY_CPS

"Snapback" & "Late VG" Protection

PP2V4_FW_LATEVG

36 37

1

C4310

0.01uF

10%
50V

2

X7R
402

FW_PORT1_TPB_N

37

FW_PORT1_TPB_P

37

FW_PORT1_TPA_N

37

FW_PORT1_TPA_P

37

1

C4312

0.01uF

10%
50V

2

X7R
402

DP4310

BAV99DW-X-G

SOT-363

2

1

DP4311

BAV99DW-X-G

SOT-363

2

1

35

C4311

0.01uF

6

6

C4313

0.01uF

DP4310

BAV99DW-X-G

1

10%
50V

2

X7R
402

1

10%
50V

2

X7R
402

SOT-363

5

4

DP4311

BAV99DW-X-G

SOT-363

5

4

PLACEMENT_NOTE=Place C4319 close to connector pin 5.

Cable Power

=PPVP_FW_PORT1

8

3

3

1

R4319

1M

5%
1/16W
MF-LF
402

2

C4319

0.1uF

603-1

CRITICAL

L4310

FERR-250-OHM

SM

1

C4314

0.01UF

10%
50V

2

X7R
402

1

10%
50V

2

X7R

AREF needs to be isolated from all
local grounds per 1394b spec

When a bilingual device is connected to a
beta-only device, there is no DC path
between them (to avoid ground offset issue)

BREF should be hard-connected to logic
ground for speed signaling and connection

Note: Trace PPVP_FW_PORT1 must handle up to 5A

21

PPVP_FW_PORT1_F

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=33V

(FW_PORT1_BREF)

(GND_FW_PORT1_VG)

FW_PORT1_AREF

PORT 1

BILINGUAL

1394B-M97

1

9

2

8

7

NC

6

3

5

4

10

11

12

13

CRITICAL

J4310

F-RT-TH

TPB(R)

TPB-

TPA-

TPA(R)

TPA+

CHASSIS

GND

TPB-

TPB<R>

VPTPB+

TPB+

VP

NC

SC/NC

VG

VG

TPA-

TPA<R>

TPA+

514S0605

OUTPUT

B

INPUT

Late-VG Protection Power

A

PP2V4_FWLATEVG needs to be biased
to at least 2.1V for FW signal integrity
and should be biased to 2.4V for margin
R4390 should be 390 Ohms max for a 3.3V rail

8

76

=PP3V3_FW_LATEVG

8

R4390

332

1%
1/16W
MF-LF

402

FireWire Ports

051-8071

SHT

SYNC_DATE=07/14/2008

OF

37 98

1

A

REV.

B

PP2V4_FW_LATEVG

21

MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=2.4V

3

CRITICAL

D4390

MMBZ5227BLT1H

SOT23

1

36 37

ESD and late-VG rail
for snap-back diodes
(Common to all ports)

SYNC_MASTER=M98_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

5

4

3

2

SCALE

NONE

87

www.vinafix.vn

6

5

4

3

21

ODD Power Control

CRITICAL

Q4590

=PP5V_S0_ODD

8

D

NOTE: 3.3V must be S0 if 5V is S3 or S5 to
ensure the drive is unpowered in S3/S5.

38

8

=PP3V3_S0_ODD

R4597

Q4596

SSM6N15FEAPE

SOT563

ODD_PWR_EN_L

21

IN

5

100K

1/16W
MF-LF

1

5%

402

2

ODD_PWR_EN

3

D

SG

4

Q4596

SSM6N15FEAPE

R4596

SOT563

2

100K

1/16W
MF-LF

1

5%

402

2

D

SG

ODD_PWR_EN_LS5V_L

6

1

R4595

100K

5%
1/16W
MF-LF

402

1

C4595

0.068UF

10%
10V

2

CERM
402

21

ODD_PWR_SS

FDC606P_G

4

SOT-6

SGD

3

C4596

0.01UF

6521

PP5V_SW_ODD

7

MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.4mm
VOLTAGE=5V

21

10%
16V

CERM

402

D

C

C

SATA ODD Port

FL4520

90-OHM-100MA

DLP11S

SYM_VER-1

=PP3V3_S0_ODD

38

8

SMC_ODD_DETECT

41

7

OUT

Indicates disc presence

R4590

1/16W
MF-LF

33K

CRITICAL

J4500

CRITICAL

1

5%

402

2

55560-0168

M-ST-SM-LF

2

1

43

65

87

9

10

12 11

14 13

16 15

SATA_ODD_R2D_P

90

7

SATA_ODD_R2D_N

90

7

SATA_ODD_D2R_C_N

90

7

SATA_ODD_D2R_C_P

90

7

PLACEMENT_NOTE=PLACE C4526 CLOSE TO J4500

PLACEMENT_NOTE=PLACE C4525 NEXT TO C4526

516S0617

21

PLACEMENT_NOTE=Place FL4520 close to J4500

C4526

0.01UF

C4525

0.01UF

21

21

10% 16V

43

SATA_ODD_R2D_UF_P

96

SATA_ODD_R2D_UF_N

96

SATA_ODD_D2R_UF_N

96

16V10%

CERM

SATA_ODD_D2R_UF_P

96

CERM

402

402

B

FL4501

90-OHM-100MA

DLP11S

SYM_VER-1

1

C4502

0.1UF

2

21

21

43

20%
10V
CERM
402

10% 16V

PLACEMENT_NOTE=PLACE C4501 CLOSE TO J4501

PLACEMENT_NOTE=PLACE C4502 CLOSE TO J4501

=PP5V_S0_HDD

SATA_HDD_D2R_UF_P

96

CERM

402

16V10%

SATA_HDD_D2R_UF_N

96

402

CERM

SATA_HDD_R2D_UF_N

96

SATA_HDD_R2D_UF_P

96

SATA HDD Port

8

FL4502

90-OHM-100MA

DLP11S

SYM_VER-1

43

PLACEMENT_NOTE=PLACE FL4502 CLOSE TO J4501

CRITICAL

21

PLACEMENT_NOTE=Place C4511 next to C4510

C4511

21

0.01UF

C4510

0.01UF

PLACEMENT_NOTE=Place C4510 close to MCP79

21

10% 16V

SATA_HDD_D2R_P

SATA_HDD_D2R_N

402

402

SATA_HDD_R2D_C_N

SATA_HDD_R2D_C_P

16V10%

CERM

CERM

1

C4501

0.1UF

20%
10V

2

CERM
402

PP5V_S0_HDD_FLT

7

CRITICAL

J4501

QT500166-L020

M-ST-SM

2

1

43

65

9

516S0350

87

10

1211

1413

1615

NC

NC

=PP1V5_EXP_S0

66

8

NC

A

PLACEMENT_NOTE=PLACE L4500 CLOSE TO J4501

SATA_HDD_D2R_C_P

90

7

SATA_HDD_D2R_C_N

90

7

SATA_HDD_R2D_N

90

7

SATA_HDD_R2D_P

90

7

CRITICAL

L4500

FERR-70-OHM-4A

21

0603

PLACEMENT_NOTE=Place C4516 close to J4501

C4516

0.01UF

C4515

0.01UF

PLACEMENT_NOTE=Place C4515 next to C4516

CRITICAL

21

PLACEMENT_NOTE=Place FL4501 close to J4501

PLACEMENT_NOTE=PLACE C4520 CLOSE TO MCP79

PLACEMENT_NOTE=PLACE C4521 NEXT TO C4520

0.01UF

0.01UF

OUT

OUT

IN

IN

21

C4521

10% 16V

21

C4520

16V10%

FL4525

90-OHM-100MA

DLP11S

SYM_VER-1

43

90 20

90 20

90 20

90 20

CERM

CERM

SATA_ODD_R2D_C_P

402

SATA_ODD_R2D_C_N

402

CRITICAL

SATA_ODD_D2R_N

21

SATA_ODD_D2R_P

PLACEMENT_NOTE=Place FL4525 close to J4500

90 20

IN

90 20

IN

90 20

OUT

90 20

OUT

B

SATA Connectors

SYNC_MASTER=M98_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

DRAWING NUMBER

D

NONE

051-8071

SHT

SYNC_DATE=05/01/2008

REV.

B

OF

9838

A

8

76

5

4

3

2

1

87

www.vinafix.vn

6

5

4

3

21

D

Port Power Switch

CRITICAL

Q4690

TPS2064DGN

=PP5V_S3_RTUSB

8

C4692

0.47UF

98

1

R4690

5.1K

5%
1/16W
MF-LF
402

2

1

10%
10V

2

X5R
402

USB_PWR_EN

20

20

OUT

OUT

USB_EXTA_OC_L

USB_EXTB_OC_L

C4690

10UF

6.3V

1

1

C4691

20%

X5R
603

0.1UF

20%
10V

2

2

CERM
402

C

21 41 42 67

PM_SLP_S4_L

2

IN

8

OC1*

3

EN1

5

OC2*

4

EN2

GND

1

MSOP

TPAD

9

OUT1

OUT2

7

6

C4695

10UF

6.3V

PP5V_S3_RTUSB_A_ILIM

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.375 mm
VOLTAGE=5V

PP5V_S3_RTUSB_B_ILIM

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.375 mm
VOLTAGE=5V

USB2_EXTA_MUXED_N

CRITICAL

1

1

C4696

20%

X5R
603

100UF

20%

6.3V

2

2

POLY-TANT
CASE-B2-SM

C4617

10UF

6.3V

20%

X5R
603

CRITICAL

1

1

C4616

100UF

20%

6.3V

2

2

POLY-TANT
CASE-B2-SM

96

96

USB2_EXTA_MUXED_P

C4605

0.01uF

CERM

1

20%
16V

2

402

Left USB Port A

CRITICAL

L4605

FERR-220-OHM-2.5A

CRITICAL

90-OHM-100MA

43

0603

L4600

DLP11S

SYM_VER-1

21

PP5V_S3_RTUSB_A_F

7

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.375 mm
VOLTAGE=5V

USB2_LT1_N

7

96

21

USB2_LT1_P

7

96

CRITICAL

J4600

USB

F-RT-TH-M97-3

5

6

OMIT

1

2

3

4

3245

IOIONC

NC

6

VBUS

1

GND

7

8

D

C

D4600

RCLAMP0502N

SLP1210N6

96

96

CRITICAL

USB_LT2_N

7

USB_LT2_P

7

6

1

VBUS

GND

D4610

RCLAMP0502N

SLP1210N6

CRITICAL

Place L4600 and L4605 at connector pin

CRITICAL

J4610

USB

F-RT-TH-M97-3

5

6

OMIT

1

2

3

4

7

3245

IOIONC

NC

8

External USB Connectors

SYNC_MASTER=M98_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

D

NONE

DRAWING NUMBER

051-8071

SHT

SYNC_DATE=07/14/2008

REV.

B

OF

9839

B

A

CRITICAL

L4615

FERR-220-OHM-2.5A

0.01uF

20%
16V
CERM
402

0603

1

B

C4615

2

We can add protection to 5V if we want, but leaving NC for now

21

PP5V_S3_RTUSB_B_F

7

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.375 mm
VOLTAGE=5V

USB/SMC Debug Mux

=PP3V42_G3H_SMCUSBMUX

8

SMC_DEBUG_YES

SMC_RX_L

7

41 42 43

IN

SMC_TX_L

7

41 42 43

OUT

USB_EXTA_P

20 91

BI

USB_EXTA_N

20 91

BI

A

C4650

0.1UF

CERM

1

20%
10V

2

402

SMC_DEBUG_NO

R4651

0

5%
1/16W
MF-LF

402

SIGNAL_MODEL=USB_MUX

5

M+

4

M-

PI3USB102ZLE

7

D+

6

D-

8

21

9

VCC

U4650

TQFN

CRITICAL

GND

3

SMC_DEBUG_NO

R4652

5%
1/16W
MF-LF

402

1

R4650

10K

5%
1/16W
MF-LF
402

1

Y+

2

Y-

10

SELOE*

2

USB_DEBUGPRT_EN_L

SEL=0 Choose SMC
SEL=1 Choose USB

41

IN

20 91

20 91

BI

BI

USB_EXTB_N

USB_EXTB_P

Left USB Port B

0

21

PART NUMBER

514-0638 CRITICAL

QTY

2

DESCRIPTION

CONN,RCPT,USB,HB,4P

REFERENCE DES

J4600, J4610

CRITICAL

SMC_DEBUG_YES

CRITICAL

L4610

90-OHM-100MA

DLP11S

SYM_VER-1

43

21

BOM OPTION

8

76

5

4

3

2

1

87

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6

5

4

3

21

D

=PP5V_S3_IR

8

40

20 91

BI

BI

DIFFERENTIAL_PAIR=USB2_IR

DIFFERENTIAL_PAIR=USB2_IR

20 91

C

OMIT

R4801

SHORT

NONE
NONE
NONE

402

21

USB_IR_P

USB_IR_N

1

C4803

2

1UF

10%
10V
X5R
402-1

PP5V_S3_IR_USB

IR_VREF_FILTER

1

2

C4801

0.1UF

10%
16V
X7R-CERM
402

NC
NC
NC
NC

NC
NC
NC
NC
NC
NC
NC
NC

U4800

CY7C63803-LQXC

12

P1.0/D+

13

P1.1/D-

15

P1.2/VREG

16

P1.3/SSEL

17

P1.4/SCLK

18

P1.5/SMOSI

19

P1.6/SMISO

8
9

10

P/N 338S0633

20

NC

21
22
23
24

THRML

CRITICAL

25

VCC

QFN

OMIT

14

INT0/P0.2
INT1/P0.3
INT2/P0.4
TIO0/P0.5
TIO1/P0.6

VSSPAD

7

P0.0

NC

6

P0.1

NC

5

NC

4

NC

3

NC

2

IR_RX_OUT_RC

1

NC

1

2

11

C4804

0.001UF

10%
50V
CERM
402

R4800

100

5%
1/16W
MF-LF

402

21

IR_RX_OUT

7

40

IN

D

C

B

J4800

FF18-6A-R11AD-B-3H

F-RT-SM

CRITICAL

518S0692

A

8

76

B

PLACE R4805 NEAR J4800
PLACE R4806 NEAR J4800

1

2

21

402

R4806

1/16W

C4807

0.001UF

10%
50V
CERM
402

MF-LF

10

5%

PLACE R4807 NEAR J4800
PLACE R4808 NEAR J4800

21

402

R4807

100

21

402

1/16W

5%

MF-LF

1

C4808

2

0.001UF

10%
50V
CERM
402

PLACE C4805 NEAR J4800
PLACE C4806 NEAR J4800
PLACE C4807 NEAR J4800
PLACE C4808 NEAR J4800

=PP3V42_G3H_LIDSWITCH

R4808

4.7

21

1/16W

402

5%

MF-LF

5

=PP5V_S3_IR

SMC_LID

SYS_LED_ANODE

IR_RX_OUT

8

8

40

41 42 49

7

42

7

40

Front Flex Support

051-8071

SHT

SYNC_DATE=07/18/2008

OF

1

A

REV.

B

9840

SYNC_MASTER=CHANG_K20

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

4

3

2

SCALE

NONE

R4805

10

1/16W

1

2

3

4

5

6

PP3V42_G3H_LIDSWITCH_R

7

PP5V_S3_IR_R

7

SMC_LID_R

7

SYS_LED_ANODE_R

7

1

C4805

0.1UF

10%
16V

2

X7R-CERM
402

1

C4806

2

0.1UF

10%
16V
X7R-CERM
402

MF-LF

5%

87

www.vinafix.vn

NOTE: Unused pins have "SMC_Pxx" names. Unused
pins designed as outputs can be left floating,
those designated as inputs require pull-ups.

D

SMC_EXCARD_PWR_EN

31

OUT

SMC_RSTGATE_L

42

OUT

ALL_SYS_PWRGD

25 67 84

IN

RSMRST_PWRGD

67

IN

PM_RSMRST_L

21

OUT

IMVP_VR_ON

61

OUT

PM_PWRBTN_L

21

OUT

ESTARLDO_EN

42

OUT

SMC_P24

42

SMC_P26

42

LPC_AD<0>

7

19 43 84 91

BI

LPC_AD<1>

7

19 43 84 91

BI

LPC_AD<2>

7

19 43 84 91

BI

LPC_AD<3>

7

19 43 84 91

C

BI

7

19 43 84 91

IN

25

IN

25 91

IN

7

19 43

BI

44

BI

51

OUT

75

OUT

50

OUT

7

39 41 42 43

OUT

7

39 41 42 43

IN

44

BI

LPC_FRAME_L
SMC_LRESET_L
LPC_CLK33M_SMC
LPC_SERIRQ

SMC_P41

42

SMB_MGMT_DATA
SMS_ONOFF_L

SMC_GFX_THROTTLE_L
SMC_SYS_KBDLED

SMC_TX_L
SMC_RX_L
SMB_0_S0_CLK

NC

NC
NC
NC

NC

NC

NC

(OC)

NC
NC

(OC)

B12

P10

A13

P11

A12

P12

B13

P13

D11

P14

C13

P15

C12

P16 P66

D10

P17

D13

P20

E11

P21

D12

P22

F11

P23

E13

P24

E12

P25

F13

P26

E10

P27

A9

P30

D9

P31

C8

P32

B7

P33

A8

P34

D8

P35

D7

P36

D6

P37

D4

P40

A5

P41

B4

P42

A1

P43

C2

P44

B2

P45

C1

P46

C3

P47

G2

P50

F3

P51

E4

P52

U4900

H8S2117

LGA-HF

(1 OF 3)

OMIT

6

P60
P61
P62
P63
P64
P65

P67

P70
P71
P72
P73
P74
P75
P76
P77

P80
P81
P82
P83
P84
P85
P86

P90
P91
P92
P93
P94
P95
P96
P97

L13
K12
K11
J12
K13
J10
J11
H12

N10
M11
L10
N11
N12
M13
N13
L12

A7
B6
C7
D5
A6
B5
C6

J4
G3
H2
G1
H4
G4
F4
F1

SMC_PM_G2_EN

NC
NC
NC

SMC_ADAPTER_EN

NC

SMC_PROCHOT_3_3_L
SMC_BIL_BUTTON_L

SMC_CPU_ISENSE
SMC_CPU_VSENSE
SMC_GPU_ISENSE
SMC_GPU_VSENSE
SMC_DCIN_ISENSE
SMC_PBUS_VSENSE
SMC_BATT_ISENSE
SMC_NB_MISC_ISENSE

SMC_WAKE_SCI_L

NC

PM_CLKRUN_L
LPC_PWRDWN_L
SMC_TX_L
SMC_RX_L
SMB_MGMT_CLK

(OC)

SMC_ONOFF_L
SMC_BC_ACOK
SMC_BS_ALRT_L
PM_SLP_S3_L
PM_SLP_S4_L
PM_SLP_S5_L
PM_CLK32K_SUSCLK
SMB_0_S0_DATA

(OC)

5

42

42 51

67

OUT

21 33 36 42

OUT

42

IN

42

IN

45

IN

45

IN

46

IN

45

IN

45

IN

45

IN

45

IN

42

IN

21

OUT

7

19 43

OUT

7

19 43

IN

7

39 41 42 43

OUT

7

39 41 42 43

IN

44

BI

7

42 49

IN

42 59

IN

7

42 59

IN

7

21 33 36 67 82 84

IN

21 39 42 67

IN

42

IN

25 91

IN

44

BI

NOTE: P94 and P95 are shorted, P95 could be spare.

4

PP3V3_S5_AVREF_SMC

7

=PP3V3_S5_SMC

8

1

1

C4902

22UF

20%

6.3V
2

CERM

805

PLACEMENT_NOTE=Place R4999 close to U4900 pins N14,N15
PLACEMENT_NOTE=Place C4920 close to U4900 pins N14,N15

C4903

0.1UF

20%
10V

2

CERM
402

R4999

4.7

5%
1/16W
MF-LF

402

21

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V

42 43

1

C4904

0.1UF

20%
10V

2

CERM
402

PP3V3_S5_SMC_AVCC

7

IN

42

42

SMC_RESET_L

SMC_XTAL
SMC_EXTAL

3

1

C4905

0.1UF

20%
10V

2

CERM
402

C4920

0.1UF

CERM

1

C4906

0.1UF

20%
10V

2

CERM
402

E1

1

20%
10V

2

402

M12

AVCC

M1

B1

U4900

H8S2117

(3 OF 3)

D3

RES*

A3

XTAL

A2

EXTAL

H10

LGA-HF

OMIT

L11

VCLVCC

AVREF

ETRST

VSS

XW4900

C5

L3

D2

B11

F10

SM

21

21

PLACEMENT_NOTE=Place C4907 close to U4900 pin F1

SMC_VCL

1

C4907

0.47UF

10%

6.3V
2

CERM-X5R

MD1
MD2

NMI

AVSS

402

E5

NC

NC

D1

SMC_KBC_MDE

H1

R4909

E3

H3

L9

1

R4902

10K

5%
1/16W
MF-LF
402

2

GND_SMC_AVSS

1

R4998

10K

5%
1/16W
MF-LF
402

2

42 45 46

1/16W
MF-LF

10K

1

1

R4901

10K

5%

5%

1/16W
MF-LF
402

402

2

2

SMC_MD1

SMC_NMI

SMC_TRST_L

NO STUFF

1

R4903

0

5%
1/16W
MF-LF
402

2

7

43

IN

7

43

IN

7

43

IN

D

C

B

A

(DEBUG_SW_1)
(DEBUG_SW_2)

SMC_PA0

42

SMC_PA1

42

PM_SYSRST_L

7

25

OUT

USB_DEBUGPRT_EN_L

39

OUT

MEM_EVENT_L

21 27 28

BI

SMC_PA5

42

SYS_ONEWIRE

42 59

BI

PM_BATLOW_L

21

OUT

SMC_RUNTIME_SCI_L

21

OUT

SMC_ODD_DETECT

7

38

IN

SMC_PB3

31 42

IN

42

IN

75

IN

48

OUT

48

OUT

42

OUT

42

OUT

48

IN

48

IN

42

IN

42

IN

51

IN

51

IN

51

IN

42

IN

42

IN

42

IN

42

IN

42

IN

42

SMC_EXCARD_CP

SMC_EXCARD_OC_L
SMC_GFX_OVERTEMP_L

SMC_FAN_0_CTL
SMC_FAN_1_CTL
SMC_FAN_2_CTL
SMC_FAN_3_CTL
SMC_FAN_0_TACH
SMC_FAN_1_TACH
SMC_FAN_2_TACH
SMC_FAN_3_TACH

SMS_X_AXIS
SMS_Y_AXIS
SMS_Z_AXIS
SMC_ANALOG_ID
SMC_NB_CORE_ISENSE
SMC_NB_DDR_ISENSE
ALS_LEFT
ALS_RIGHT

(See below)

SMC_PB3:

SMC_IG_THROTTLE_L for MG systems.
Otherwise, TP/NC okay (was ISENSE_CAL_EN)

(OC)
(OC)
(OC)
(OC)
(OC)
(OC)

NC

NC

A10
C10
B10
C11
A11

G11
G13
F12
H13
G10
G12
H11
J13

M10

K10

N3

PA0

N1

PA1

M3

PA2

M2

PA3

N2

PA4

L1

PA5

K3

PA6

L2

PA7

B8

PB0

C9

PB1

B9

PB2
PB3
PB4
PB5
PB6
PB7

PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7

PD0

N9

PD1
PD2

L8

PD3

M9

PD4

N8

PD5

K9

PD6

L7

PD7

U4900

H8S2117

LGA-HF

(2 OF 3)

OMIT

PE0
PE1
PE2
PE3
PE4
PF0

PF1
PF2
PF3
PF4
PF5
PF6
PF7

PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7

PH0
PH1
PH2
PH3
PH4
PH5

K1
J3
K2
J1
K4
K5

N5
M6
L5
M5
N4
L4
M4

M8
N7
K8
K7
K6
N6
M7
L6

E2
F2
J2
A4
B3
C4

SMC_CASE_OPEN
SMC_TCK
SMC_TDI
SMC_TDO
SMC_TMS

NC

SMC_SYS_LED
SMC_LID

NC
NC

SMC_MCP_SAFE_MODE

NC
NC

NC

=SMC_SMS_INT
SMB_BSA_DATA

(OC)

SMB_BSA_CLK

(OC)

SMB_A_S3_DATA

(OC)

SMB_A_S3_CLK

(OC)

SMB_B_S0_DATA

(OC)

SMB_B_S0_CLK

(OC)

SMC_PROCHOT
SMC_THRMTRIP
SMC_PH2
ALS_GAIN

NC
NC

42

IN

7

42 43

IN

7

42 43

IN

7

42 43

OUT

7

42 43

IN

42

OUT

40 42 49

IN

9

OUT

42

IN

44

BI

44

BI

44

BI

44

BI

44

BI

44

BI

42

OUT

42

OUT

42

42

OUT

NOTE: SMS Interrupt can be active high or low, rename net accordingly.
If SMS interrupt is not used, pull up to SMC rail.

B

SMC

051-8071

SHT

SYNC_DATE=06/06/2008

REV.

B

OF

9841

A

SYNC_MASTER=T18_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

DRAWING NUMBER

D

NONE

8

76

5

4

3

2

1

21

www.vinafix.vn

=PP3V3_S0_SMC

8

42

1

R5060

470

5%

1/16W

MF-LF

402

5

100K

100K

100K

100K

2.0K

100K

470K

10K

10K

10K

10K

10K

10K

10K

10K

2

SMC_PROCHOT_3_3_L

3

Q5060

BC847BV-X-F
SOT563-HF

4

ONEWIRE_PU

8

41 42 51

21

21

5%

21

5%

21

21

5%

21

5%

21

5%

21

5%

21

5%

21

5%

21

21

5%

21

5%

21

5%

21

5%

1

R5061

3.3K

5%

1/16W

MF-LF

402

2

CPU_PROCHOT_BUF

6

Q5060

2

BC847BV-X-F
SOT563-HF

1

R5091
R5092

R5070
R5071
R5072
R5073
R5074

R5075
R5076
R5077
R5078
R5079
R5080
R5081
R5087

=PP3V3_S5_SMC

1/16W5%MF-LF

1/16W

1/16W

1/16W5%MF-LF

1/16W MF-LF

1/16W

1/16W

1/16W

1/16W

1/16W5%MF-LF

1/16W MF-LF

1/16W MF-LF

1/16W

TO SMC

MF-LF

MF-LF

MF-LF

MF-LF1/16W

MF-LF

MF-LF

MF-LF

MF-LF1/16W

MF-LF

41

OUT

402

402

402

402

402

402

402

402

402

402

402

402

402

402

402

D

C

B

SOT563

5

41 45 46

6

41

41

41

41

7

41 43

OUT

3

D

SG

4

7

41

SMC_XTAL

41

SMC_EXTAL

41

41

41 42 59

41 45

41 45

41 46

41

41

41

41

41

41

41

41

SMC_EXCARD_OC_L

OUT

51

SMC Crystal Circuit

R5010

0

21

SMC_XTAL_R

5%
1/16W
MF-LF

402

CRITICAL

Y5010

20.00MHZ

5X3.2-SM

5

SMC_FAN_2_CTL

SMC_FAN_2_TACH

SMC_FAN_3_CTL

SMC_FAN_3_TACH

ESTARLDO_EN

SMC_BC_ACOK

MAKE_BASE=TRUE

ALS_LEFT

ALS_RIGHT

SMC_NB_CORE_ISENSE

SMC_NB_DDR_ISENSE

SMC_NB_MISC_ISENSE

SMC_ANALOG_ID

SMC_P24

SMC_P26

SMC_P41

ALS_GAIN

SMC_PB3

SMC_RSTGATE_L

SMS_INT_L

MAKE_BASE=TRUE

1

2

C5010

15pF

5%

50V

CERM

402

C5011

15pF

5%

50V

CERM

402

21

21

NC_SMC_FAN_2_CTL

MAKE_BASE=TRUE

NC_SMC_FAN_2_TACH

MAKE_BASE=TRUE

NC_SMC_FAN_3_CTL

MAKE_BASE=TRUE

NC_SMC_FAN_3_TACH

MAKE_BASE=TRUE

NC_ESTARLDO_EN

MAKE_BASE=TRUE

=CHGR_ACOK

SMC_MCP_VSENSE

MAKE_BASE=TRUE

SMC_CPU_HI_ISENSE

MAKE_BASE=TRUE

SMC_MCP_CORE_ISENSE

MAKE_BASE=TRUE

SMC_MCP_DDR_ISENSE

MAKE_BASE=TRUE

SMC_CPU_FSB_ISENSE

MAKE_BASE=TRUE

SMC_GPU_1V8_ISENSE

MAKE_BASE=TRUE

TP_SMC_P24

MAKE_BASE=TRUE

SMC_BMON_MUX_SEL

MAKE_BASE=TRUE

TP_SMC_P41

MAKE_BASE=TRUE

NC_ALS_GAIN

MAKE_BASE=TRUE

SMC_IG_THROTTLE_L

MAKE_BASE=TRUE

TP_SMC_RSTGATE_L

MAKE_BASE=TRUE

R5095

0

5%
1/16W
MF-LF

402

SILK_PART=PWR_BTN

21

EXCARD_OC_L

Debug Power "Button"

=SMC_SMS_INT

SMC_ONOFF_L

OMIT

1

R5015

0

5%
1/10W
MF-LF
603

2

4

7

7

7

7

7

60

46

46

46

45

7

7

21

20 31 41

IN

41

7

41 42 49

OUT

PLACE R5015,R5001 ON BOTTOM SIDE

10 14 61 88

10 14 88

TO CPU

BI

OUT

CPU_PROCHOT_L

PM_THRMTRIP_L

87

SMC Reset "Button" / Brownout Detect

=PP3V3_S5_SMC

8

41 42 51

1

2

IN

5

SN74LVC1G02

SOT553-5

3

U5001

4

1

R5000

1K

5%
1/16W
MF-LF
402

2

SMC_RESET_L

SMC_TPAD_RST

Q5032

SSM6N15FEAPE

1

C5000

0.1uF

20%
10V

2

CERM

402

D

SILK_PART=SMC_RST

SMC_MANUAL_RST_L

OMIT

1

R5001

0

5%
1/10W
MF-LF
603

2

NC

1

C5001

0.01UF

10%
16V

2

CERM

402

=PP3V3_S5_SMC

8

41 42 51

SMC_TPAD_RST_L

49

SMC_ONOFF_L

7

41 42 49 41

NCP303LSN

5

CD

4

NC

U5000

SOT23-5-HF

GND

3

CRITICAL

1

2

OUT

02

C

SMC AVREF Supply

CRITICAL

VR5020

PART NUMBER

353S1381

1

2

C5020

0.47UF

10%

6.3V
CERM-X5R
402

IN

COMMENTS:

REF3333

SOT23-3

GND

3

=PPVIN_S5_SMCVREF

8

ALTERNATE FOR
PART NUMBER

353S1912 Intersil ISL60002-33

BOM OPTION

REF DES

ALL

OUT

C5025

10uF

20%

6.3V
X5R
603

PP3V3_S5_AVREF_SMC

MIN_LINE_WIDTH=0.4 mm

21

MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

1

C5026

0.01UF

10%
16V

2

CERM
402

1

2

GND_SMC_AVSS

TABLE_ALT_HEAD

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V

TABLE_ALT_ITEM

B

3

6

1

3

4

R5062

3.3K

5%

1/16W

MF-LF

402

D

Q5059

SSM6N15FEAPE

SOT563

SG

D

Q5059

SSM6N15FEAPE

SOT563

SG

2

5

SMC FSB to 3.3V Level Shifting

=PP1V05_S0_SMC_LS

8

21

CPU_PROCHOT_L_R

SMC_PROCHOT

SMC_THRMTRIP

41

41

7

41 42 49

40 41 49

41

7

39 41 43

7

39 41 43

41 59

7

41 59

7

41 43

7

41 43

7

41 43

7

41 43

41 42

41 42 59

SMC_PA0

SMC_PA1

SMC_ONOFF_L

SMC_LID

SMC_PH2

SMC_TX_L

SMC_RX_L

SYS_ONEWIRE

SMC_BS_ALRT_L

SMC_TMS

SMC_TDO

SMC_TDI

SMC_TCK

SMC_BIL_BUTTON_L

SMC_BC_ACOK

41

IN

41

IN

System (Sleep) LED Circuit

=PP5V_S3_SYSLED

8

1

1/16W
MF-LF

1/16W
MF-LF

523

1%

402

1%

402

1

R5030

20

1%
1/16W
MF-LF
402

2

2

SYS_LED_ILIM

SYS_LED_L_VDIV

1

2

SYS_LED_L

Q5032

SSM6N15FEAPE

SOT563

2

CRITICAL

SOD

2SA2154MFV-YAE

1

Q5030

3

SYS_LED_ANODE

6

D

2

SG

1

7

40

OUT

SMC_BIL_BUTTON_L

41 42

R5031

R5032

1.47K

A

SMC_SYS_LED

41

IN

PP3V42_G3H

7 8

74LVC1G17DRL

U5050

SOT-553

4

10K

SMC_ADAPTER_EN

21 33 36 41

SMC_CASE_OPEN

R5051

1

C5050

0.1UF

10%
16V

2

X5R
402

5

21

10K

1/16W

402

MF-LF

5%

SMC_BIL_BUTTON_DB_L

7

59

41

31 41

41

21 39 41 67

SMC_EXCARD_CP

PM_SLP_S5_L

PM_SLP_S4_L

R5085
R5086

R5088

R5090

10K

10K

100K

2

NC

13

NC

1

C5051

0.01UF

10%
25V

2

X7R
402

41

SMC_PA5

R5089

SYNC_MASTER=M98_MLB

10K

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

D

APPLE INC.

SCALE

21

5%

21

5%

21

5%

21

5%

=PP3V3_S0_SMC

8

42

21

5%

SMC Support

DRAWING NUMBER

SHT

NONE

1/16W

1/16W MF-LF

051-8071

402

MF-LF1/16W

402

MF-LF1/16W

402

MF-LF

402

MF-LF1/16W

402

SYNC_DATE=05/01/2008

REV.

OF

9842

A

B

8

76

5

4

3

2

1

87

www.vinafix.vn

6

5

4

3

21

LPC+SPI Connector

CRITICAL

LPCPLUS

J5100

55909-0374

M-ST-SM

31

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

33

32

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

34

MCP_CS1_YES

R5147

0

5%
1/16W
MF-LF

402

LPC_CLK33M_LPCPLUS
LPC_AD<2>
LPC_AD<3>

SPIROM_USE_MLB
SPI_ALT_CLK

SPI_ALT_CS_L
LPC_SERIRQ
LPC_PWRDWN_L
SMC_TDI
SMC_TCK
SMC_RESET_L
SMC_NMI
SMC_RX_L
LPCPLUS_GPIO

From Frank Card

To Frank Card

21

PLACEMENT_NOTE=PLACE NEXT TO U5120

7

25 91

IN

7

19 41 84 91

BI

7

19 41 84 91

BI

7

43

OUT

7

43

IN

7

43

IN

7

19 41

BI

7

19 41

IN

7

41 42

OUT

7

41 42

OUT

7

41 42

OUT

7

41

OUT

7

39 41 42

OUT

7

18

OUT

MCP_CS1_NO

R5142

0

5%
1/16W
MF-LF

402

MCP79 Internal SPI MUX Support

=PP3V3_S0_LPCPLUS

8

=PP3V3_S5_LPCPLUS

8

43

21

PLACEMENT_NOTE=Place near J5100

NOT SUPPORTED IN REV A01 OR B01 MCP79 SILICON

MCP_CS1_YES

1

R5140

100K

1/16W
MF-LF

402

2

5%

2

GS

1

SPI_CS1_R_L_USE_MLB

3

LPC_FRAME_PU

D

Q5140

SSM3J16FV

SOD-VESM-HF

MAKE_BASE=TRUE

MCP_CS1_YES

1

R5141

470

5%
1/16W
MF-LF

402

2

LPC_FRAME_R_L

=SPI_CS1_R_L_USE_MLB

D

C

19

OUT

9

21

BI

B

=PP3V3_S5_LPCPLUS

8

D

Alternate SPI ROM Support

MUX SEL CONTROLLED BY FRANKCARD SWITCH ONCE CS1 IS SUPPORTED IN MCP

=PP3V3_S5_LPCPLUS

8

10K

1/16W
MF-LF

402

1

5%

2

43

=PP3V3_S5_LPCPLUS

8
43

LPCPLUS

1

Y+

2

Y-

U5110

PI3USB102ZLE

TQFN

CRITICAL

10

SEL OE*

LPCPLUS

1

Y+

2

Y-

U5120

PI3USB102ZLE

TQFN

CRITICAL

10

SEL OE*

GND

GND

VCC

VCC

9

3

9

3

=PP3V3_S5_ROM

8

43 52

R5190

SPI_CLK_R

21 43 91

C

IN

1

R5191

10K

5%
1/16W
MF-LF

402

2

SEL HIGH OUTPUTS TO D (ON BOARD ROM)
SEL LOW OUTPUTS TO M (FRANKCARD ROM)

SPI_MOSI_R

21 43 91

IN

SPIROM_USE_MLB

7

43

21 43 91

OUT

21 91

IN

SPI_MISO
SPI_CS0_R_L

B

MCP_CS1_YES&LPCPLUS_NOT

R5146

0

21

5%

PLACEMENT_NOTE=PLACE NEXT TO U1400
1/16W
MF-LF

402

5

M+

4

M-

7

D+

6

D-

8

5

M+

4

M-

7

D+

6

D-

8

LPCPLUS

1

C5114

0.1UF

20%
10V

2

CERM
402

SPI_ALT_CLK
SPI_ALT_MOSI

SPI_CLK_MUX
SPI_MOSI_MUX

LPCPLUS

1

C5124

0.1UF

20%
10V

2

CERM
402

SPI_ALT_CS_L_MUX

SPI_MLB_CS_L_MUX

MCP_CS1_NO

1/16W

MF-LF

1/16W

SPI_ALT_MISO

0

R5127

21

402

5%

MCP_CS1_NO

0

5%

MF-LF

43

19 41 84 91

19 41 84 91

43

43

19 41 84 91

19 41

41 42

41

41

39 41 42

OUT

OUT

OUT

OUT

SPI_ALT_CS_L

SPI_MISO_MUX

R5126

21

402

MCP_CS1_NO

=PP5V_S0_LPCPLUS

8

LPC_AD<0>

7

BI

LPC_AD<1>

7

BI

SPI_ALT_MOSI

7

IN

SPI_ALT_MISO

7

OUT

LPC_FRAME_L

7

IN

PM_CLKRUN_L

7

OUT

SMC_TMS

7

OUT

DEBUG_RESET_L

IN

SMC_TDO

OUT

SMC_TRST_L

7

IN

SMC_MD1

7

OUT

SMC_TX_L

7

IN

7

43

7

43

43 52

43 52

Pull-up on debug card

SPI_MLB_CS_L

1

R5144

20K

5%
1/16W
MF-LF

402

2

516S0573

MCP SPI Override Options

MCP79 REV A01 REQUIRES EXTERNAL MUX, REV B01 STILL DOES NOT SUPPORT INTERNAL MUX

SPIROM_USE_MLB

7

43

7

43

IN

7

43

OUT

43 52

IN

52

OUT

=PP3V3_S5_ROM

8

43 52

SPI MUX BYPASS

SPI_CLK_MUX

43 52

OUT

SPI_MOSI_MUX

43 52

OUT

SPI_MISO_MUX

43 52

IN

A

8

76

LPCPLUS_NOT

R5156

0

5%
1/16W
MF-LF

402

LPCPLUS_NOT

R5158

0

5%
1/16W
MF-LF

402

21

LPCPLUS_NOT

R5157

0

5%
1/16W
MF-LF

402

21

SPI_CLK_R

21

SPI_MOSI_R

SPI_MISO

21 43 91

IN

21 43 91

IN

21 43 91

OUT

APPLE INC.

5

4

3

2

LPC+SPI Debug Connector

SYNC_MASTER=CHANG_K20

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

051-8071

SHT

SYNC_DATE=05/28/2008

OF

1

A

REV.

B

9843

87

www.vinafix.vn

6

5

4

3

21

MCP79 SMBus "0" Connections

=PP3V3_S0_SMBUS_MCP_0

8

1

1

4.7K

1/16W
MF-LF

402

R5201

4.7K

5%

5%

1/16W
MF-LF
402

402

2

2

SO-DIMM "A"

J3100

(Write: 0xA0 Read: 0xA1)

=I2C_SODIMMA_SCL

=I2C_SODIMMA_SDA

SO-DIMM "B"

(Write: 0xA2 Read: 0xA3)

=I2C_SODIMMB_SCL

=I2C_SODIMMB_SDA

=SMBUS_EXCARD_SCL

=SMBUS_EXCARD_SDA

J3200

ExpressCard Slot

J3500

27

27

28 30

28

31

31

SMB_0_S0_CLK

41

SMB_0_S0_DATA

41

SMB_BSA_CLK

41

SMB_BSA_DATA

41

SMC

U4900

(MASTER)

SMC

U4900

(MASTER)

Battery

Battery Manager - (Write: 0x16 Read: 0x17)

Battery LED Driver - (Write: 0x36 Read: 0x37)

Battery Temp - (Write: 0x90 Read: 0x91)

1

1

R5231

1.5K

5%

5%

1/16W
MF-LF
402

2

2

HDCP ROM

U2690 or U2695

(Write: 0xA0-0xAE,

Read: 0xA1-0xAF)

=I2C_HDCPROM_SCL

=I2C_HDCPROM_SDA

Mikey

(WRITE: 0X72 READ: 0X73)

=I2C_MIKEY_SCL

=I2C_MIKEY_SDA

U6800

24

24

58

58

SMB_MGMT_CLK

41

SMB_MGMT_DATA

41

SMC

U4900

(MASTER)

MCP79

U1400

(MASTER)

SMBUS_MCP_0_CLK

7

13 21 91

D

MAKE_BASE=TRUE

SMBUS_MCP_0_DATA

7

13 21 91

MAKE_BASE=TRUE

R5200

C

MCP79 SMBus "1" Connections

=PP3V3_S0_SMBUS_MCP_1

8

R5230

1.5K

1/16W
MF-LF

SMBUS_MCP_1_CLK

21 91

MAKE_BASE=TRUE

SMBUS_MCP_1_DATA

21 91

MAKE_BASE=TRUE

MCP79

U1400

(MASTER?)

B

SMC "0" SMBus Connections

=PP3V3_GPU_SMBUS_SMC_0_S0

8

1

4.7K

1/16W
MF-LF

4.7K

1/16W
MF-LF

1

R5251

4.7K

5%

5%
1/16W
MF-LF

402

402

2

2

1

1

R5281

1K

1K

5%

5%

1/16W
MF-LF
402

402

2

2

1

1

R5291

4.7K

5%

5%
1/16W
MF-LF

402

402

2

2

R5250

94

SMBUS_SMC_0_S0_SCL

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SDA

94

MAKE_BASE=TRUE

SMC "Battery A" SMBus Connections

=PP3V42_G3H_SMBUS_SMC_BSA

8

R5280

1/16W
MF-LF

SMBUS_SMC_BSA_SCL

MAKE_BASE=TRUE

SMBUS_SMC_BSA_SDA

MAKE_BASE=TRUE

SMC "Management" SMBus Connections

=PP3V3_S3_SMBUS_SMC_MGMT

8

R5290

94

SMBUS_SMC_MGMT_SCL

MAKE_BASE=TRUE

94

SMBUS_SMC_MGMT_SDA

MAKE_BASE=TRUE

GPU Temp (Ext)

EMC1043-1: U5550

(Write: 0x98 Read: 0x99)

=SMBUS_GPUTHMSNS_SCL

=SMBUS_GPUTHMSNS_SDA

GPU Temp (Int)

G96: U8000

=GPU_I2CS_SCL

=GPU_I2CS_SDA

Battery

J6955

(See Table)

=SMBUS_BATT_SCL

=SMBUS_BATT_SDA

Battery Charger

ISL6258 - U7000

(Write: 0x12 Read: 0x13)

=SMBUS_CHGR_SCL

=SMBUS_CHGR_SDA

The bus formerly known as "Battery B"

Vref DACs

U2900

(Write: 0x98 Read: 0x99)

=I2C_VREFDACS_SCL

=I2C_VREFDACS_SDA

Margin Control

U2901

(Write: 0x30 Read: 0x31)

=I2C_PCA9557D_SCL

=I2C_PCA9557D_SDA

SMC

U4900

(MASTER)

47

47

76

76

59

59

60

60

26

26

26

26

SMB_A_S3_CLK

41

SMB_A_S3_DATA

41

SMB_B_S0_CLK

41

SMB_B_S0_DATA

41

SMC

U4900

(MASTER)

SMC "A" SMBus Connections

NOTE: SMC RMT bus remains powered and may be active in S3 state

=PP3V3_S3_SMBUS_SMC_A_S3

8

1

R5270

1K

5%
1/16W
MF-LF

402

SMBUS_SMC_A_S3_SCL

MAKE_BASE=TRUE

SMBUS_SMC_A_S3_SDA

MAKE_BASE=TRUE

2

SMC "B" SMBus Connections

=PP3V3_S0_SMBUS_SMC_B_S0

8

1

R5260

3.3K

5%
1/16W
MF-LF

402

94

MAKE_BASE=TRUE

SMBUS_SMC_B_S0_SDA

94

MAKE_BASE=TRUE

2

1

R5271

1K

5%
1/16W
MF-LF
402

2

1

R5261

3.3K

5%
1/16W
MF-LF
402

2

TRACKPAD

J5800

(Write: 0x90 Read: 0x91)

=I2C_TPAD_SCL

=I2C_TPAD_SDA

ALS

J3401

(Write: 0x72 Read: 0x73)(Write: 0x9E Read: 0x9F)

I2C_ALS_SCL

I2C_ALS_SDA

CPU Temp

EMC1043-1: U5570

(Write: 0x98 Read: 0x99)

=I2C_CPUTHMSNS_SCLSMBUS_SMC_B_S0_SCL

=I2C_CPUTHMSNS_SDA

MCP Temp

EMC1043-2: U5500

(WRITE: 0X9A READ: 0X9B)

=SMBUS_MCPTHMSNS_SCL

=SMBUS_MCPTHMSNS_SDA

Battery Charger Temp

TMP102: U5540

(Write: 0x92 Read: 0x93)

=SMBUS_TMPSNSR_SCL

=SMBUS_TMPSNSR_SDA

50

50

30

D

C

47

47

47

47

B

47

47

A

8

76

SMS

U5930

(Write: 0x70 Read: 0x71)

=I2C_SMS_SCL

=I2C_SMS_SDA

51

51

K20 SMBUS CONNECTIONS

1

SYNC_DATE=07/22/2008

REV.

OF

9844

A

B

SYNC_MASTER=BEN_K20

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

5

4

3

2

SCALE

NONE

051-8071

SHT

87

www.vinafix.vn

CPU Voltage Sense / Filter

=PPVCORE_S0_CPU

8

11 12

Place short near U1000 center

D

=PPVCORE_GPU_REG

8

77

Place short near U8000 center

XW5309

SM

21

CPUVSENSE_IN

GPU Voltage Sense / Filter

XW5359

SM

21

GPUVSENSE_IN

MCP Voltage Sense / Filter

=PPVCORE_S0_MCP

8

22 23

PLACEMENT_NOTE=Place near U1400 center

XW5399

SM

21

MCPVSENSE_IN

R5309

4.53K

21

21

21

SMC_CPU_VSENSE

1

C5309

0.22UF

20%

6.3V

2

X5R

402

GND_SMC_AVSS

SMC_GPU_VSENSE

1

C5359

0.22UF

20%

6.3V

2

X5R

402

GND_SMC_AVSS

SMC_MCP_VSENSE

1

C5399

0.22UF

20%

6.3V

2

X5R
402

GND_SMC_AVSS

1%

1/16W

MF-LF

402

Place RC close to SMC

R5359

4.53K

1%

1/16W

MF-LF

402

Place RC close to SMC

R5399

4.53K

1%
1/16W
MF-LF

402

Place RC close to SMC

6

41 42 45 46

41 42 45 46

41 42 45 46

5

4

PBUS Voltage Sense & Filter

1

5%

2

PBUSVSENS_EN_DIV

Q5315

FDG6332CG

SC70-6

P-CHN

S

4

G

5

PBUSVSENS_EN_L

D

3

PPBUS_G3H_VSENSE

MIN_LINE_WIDTH=0.20 mm
MIN_NECK_WIDTH=0.20 mm
VOLTAGE=18.5V

1

R5316

100K

5%

1/16W

MF-LF

402

2

6

D

G

2

S

1

N-CHN

Q5315

FDG6332CG

SC70-6

R5385

12.7K

R5386

6.98K

1%

1/16W

MF-LF

402

1%

1/16W

MF-LF

402

1

Rthevenin = 4504 ohms

2

SMC_PBUS_VSENSE

1

1

C5385

0.22UF

20%

6.3V

2

X5R

402

2

GND_SMC_AVSS

Place RC close to SMC

OUT

41 42 45 46

41

OUT

PPBUS_G3H

7 8

R5315

100K

1/16W

MF-LF

402

41

OUT

=PBUSVSENS_EN

Enables PBUS VSense divider when high.

42

OUT

67

3

41

21

D

C

C

BMON Current Sense - Entire circuit must be near SMC (U4900)

=PP3V42_G3H_BMON_ISNS

8

BMON_ENG

BMON_ENG

1

C5318

0.1uF

20%
10V

2

CERM
402

5

IN-

4

IN+ REF

60 96

OUT

60 96

IN

REGULATOR SIDE:

CHGR_CSO_R_P

CHGR_CSO_R_N

LOAD SIDE:

B

Monitors battery discharge

current from battery to PBUS

3
V+

U5303

INA214

SC70

GND

2

BMON_ENG

OUT

BMON_INA_OUT

6

1

CHGR_BMON

60

IN

BMON_PROD

R5330

0

21

5%
1/16W
MF-LF

402

U5313

NC7SB3157P6XG

SC70

B1

1

2

GND

34

B0

1

0

VER 1

SEL

6

5

VCC

A

SMC_BMON_MUX_SEL

BMON_ENG

1

R5371

100K

5%
1/16W
MF-LF
402

2

BMON_AMUX_OUT

42

IN

R5391

4.53K

1/16W
MF-LF

BMON_ENG

1

C5369

0.1uF

20%
10V

2

CERM
402

DCIN Current Sense Filter

21

1%

402

SMC_BATT_ISENSE

1

C5390

0.22UF

20%

6.3V

2

X5R
402

GND_SMC_AVSS

41 42 45 46

41

OUT

60

CHGR_AMON

IN

Place RC close to SMC

R5380

4.53K

21

1%

1/16W

MF-LF

402

SMC_DCIN_ISENSE

1

C5380

0.22UF

20%

6.3V

2

X5R

402

GND_SMC_AVSS

41 42 45 46

41

OUT

B

INA214 has gain of 100V/V

U5303 only senses current up to 6.6A

CPU VCore High Side Current Sensor

=PP3V42_G3H_CPUCOREISNS

8

1

C5388

0.1UF

20%
10V

2

CERM

402

6

CPUVCORE_HISIDE_IOUT

1

R5335

4.53K

21

1%

1/16W

MF-LF

402

Place RC close to SMC

SMC_CPU_HI_ISENSE

1

C5335

0.22UF

20%

6.3V

2

X5R

402

GND_SMC_AVSS

41 42 45 46

61

42

OUT

IN-

3

V+

U5388

INA210

SC70

GND

2

OUT

REFIN+

=PPVIN_S5_CPU_IMVP_ISNS

8

OUT

1

ISNS_CPU_N

R5388

0.001

A

=PPVIN_S5_CPU_IMVP_ISNS_R

8

IN

96

1%
1W
MF

1206

432

ISNS_CPU_P

96

5

4

Consider INA211 (GAIN 500 version) since I=4.93 Amps across R5388

CPU VCore Load Side Current Sense / Filter

R5331

IMVP6_IMON

IN

6.19K

1/16W

MF-LF

1%

402

21

R5332

17.4K

1/16W
MF-LF

Place RC close to SMC

SMC_CPU_ISENSE

1

1

C5330

1%

2

402

2

GND_SMC_AVSS

0.22UF

20%

6.3V

X5R

402

41 42 45 46

41

OUT

Current & Voltage Sensing

SYNC_MASTER=YWU_K20

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

D

NONE

DRAWING NUMBER

051-8071

SHT

SYNC_DATE=08/20/2008

OF

45 98

A

REV.

B

8

76

5

4

3

2

1

87

www.vinafix.vn

6

5

4

3

21

MCP VCore Current Sense

=PP3V3_S0_MCPCOREISNS

8

3

V+

U5420

INA213

D

64 96

64 96

MCPCOREISNS_N

IN

MCPCOREISNS_P

IN

5

SC70

IN-

4

GND

2

OUT

1

C5420

0.1UF

20%
10V

2

CERM

402

6

1

REFIN+

MCPCORE_IOUT

MCP VCore Current Sense Filter

Place RC close to SMC

R5470

4.53K

21

1%

1/16W

MF-LF

402

SMC_MCP_CORE_ISENSE

1

C5470

0.22UF

20%

6.3V

2

X5R

402

GND_SMC_AVSS

41 42 45 46

R5493

2.87K

GFXIMVP6_IMON

77

IN

42

OUT

21

1%

1/16W

MF-LF

402

R5491

10K

21

1%

1/16W

MF-LF

402

MCP MEM VDD Current Sense

=PP3V3_S0_MCPDDRISNS

8

=PPMCPDDR_ISNS_R

8

IN

CRITICAL

1

DDRISNS_P

0.002

96

1%

1/4W

MF

1206

432

DDRISNS_N

96

SIGNAL_MODEL=EMPTY

R5445

C

8

OUT

=PPMCPDDR_ISNS

R5444

3.65K

R5443

3.65K

1%

1/16W

MF-LF

402

C5442

470PF

21

DDRISNS_R_P

96

1%

1/16W

MF-LF

402

21

10%
50V

CERM

402

1

2

DDRISNS_R_N

96

SIGNAL_MODEL=EMPTY

1

R5442

1M

1%
1/16W
MF-LF
402

2

3

2

R5441

1M

1%

1/16W

MF-LF

402

8

V+

V-

THRM

4

9

SIGNAL_MODEL=EMPTY

21

C5441

470PF

10%
50V

CERM

402

U5440

OPA2333

DFN

1

21

SIGNAL_MODEL=EMPTY

OPA2333s for proto are placeholders for OPA2330

B

MCP MEM VDD Current Sense and CPU FSB 1.05V Current Sense share

1

C5440

0.1UF

20%
10V

2

CERM

402

Gain: 274x

MCP MEM VDD Current Sense Filter

Place RC close to SMC

R5440

4.53K

MCPDDR_IOUT

21

1%

1/16W

MF-LF

402

SMC_MCP_DDR_ISENSE

1

C5490

0.22UF

20%

6.3V

2

X5R

402

GND_SMC_AVSS

41 42 45 46

42

OUT

8

IN

8

OUT

=PP1V8_S0GPU_ISNS_R

=PP1V8_S0GPU_ISNS

=PP3V3_S0_GPU1V8ISNS

8

CRITICAL

1

R5413

0.002

96

1%

1/4W

MF

1206

432

P1V8GPU_P

P1V8GPU_N

96

SIGNAL_MODEL=EMPTY

GPU VCore Current Sense and GPU 1.8V Current Sense share

R5415

3.65K

1%

1/16W

MF-LF

402

R5414

3.65K

1%

1/16W

MF-LF

402

C5412

470PF

dual package opamp U5440

CPU FSB 1.05V Current Sense

GPU VCore Current Sense

GPUISENS_P

96

GPUISENS_N

96

Gain: 1.4x

3

2

dual package opamp U5410

GPU 1.8V Current Sense

21

P1V8GPUISNS_R_P

96

21

P1V8GPUISNS_R_N

96

SIGNAL_MODEL=EMPTY

1

R5412

1

1M

2

2

Gain: 274x

1%
1/16W
MF-LF
402

10%
50V

CERM

402

THRM

9

NC

R5498

C5498

V+

V-

4.02K

1%

1/16W

MF-LF

402

470PF

10%
50V
CERM
402

NC

8

4

NC

21

5

6

R5411

1M

1%

1/16W

MF-LF

402

U5410

OPA2333

DFN

1

21

THRM

GPUVCORE_IOUT

U5410

OPA2333

8

DFN

V+

V-

4

9

SIGNAL_MODEL=EMPTY

21

C5411

470PF

21

SIGNAL_MODEL=EMPTY

10%
50V

CERM

402

7

1

C5410

0.1UF

20%
10V

2

CERM

402

P1V8_S0GPU_IOUT

GPU VCore Current Sense Filter

Place RC close to SMC

R5475

4.53K

21

1%

1/16W

MF-LF

402

SMC_GPU_ISENSE

1

C5475

0.22UF

20%

6.3V

2

X5R

402

GND_SMC_AVSS

GPU 1.8V Current Sense Filter

Place RC close to SMC

R5465

4.53K

21

1%

1/16W

MF-LF

402

SMC_GPU_1V8_ISENSE

1

C5465

0.22UF

20%

6.3V

2

X5R

402

GND_SMC_AVSS

41 42 45 46

41 42 45 46

41

OUT

D

C

42

OUT

B

1V05CPU_P

65 96

IN

1V05CPU_N

65 96

IN

A

8

SIGNAL_MODEL=EMPTY

76

R5431

3.65K

1%

1/16W

MF-LF

402

R5436

3.65K

1%

1/16W

MF-LF

402

C5472

470PF

21

96

21

96

1

10%
50V

2

CERM

402

1V05CPUISNS_R_P

1V05CPUISNS_R_N

SIGNAL_MODEL=EMPTY

1

R5437

1M

1%
1/16W
MF-LF
402

2

Gain: 274x

NC

5

V+

6

V-

THRM

9

NC

SIGNAL_MODEL=EMPTY

R5432

1M

21

1%

SIGNAL_MODEL=EMPTY

1/16W

MF-LF

C5432

402

470PF

10%
50V

CERM

402

8

4

NC

21

U5440

OPA2333

DFN

7

CPU1V05_S0_IOUT

1.05V CPU Current Sense Filter

R5495

4.53K

21

1%

1/16W

MF-LF

402

Place RC close to SMC

SMC_CPU_FSB_ISENSE

1

C5435

0.22UF

20%

6.3V

2

X5R

402

GND_SMC_AVSS

5

41 42 45 46

42

OUT

Current Sensing

SYNC_MASTER=YWU_K20

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

4

3

2

SCALE

NONE

051-8071

SHT

SYNC_DATE=08/12/2008

OF

1

A

REV.

B

9846

87

www.vinafix.vn

6

5

4

3

21

CPU Proximity/CPU Die/Right Fin Stack

R5570

47

21

1/16W
MF-LF

402

5%

0.0022UF

PP3V3_S0_CPUTHMSNS_R

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V

1

C5580

10%
50V

2

CERM

402

1

C5590

0.0022uF

10%
50V

2

CERM

402

1

C5570

0.1uF

1

VDD

U5570

EMC1403-1

DP1

DN1

DP2/DN3

DN2/DP3

GND

6

DFN

CRITICAL

THRM_PAD

THERM*

ALERT*

SMDATA

SMCLK

11

2

38

4

5

20%
10V

2

CERM
402

7

CPUTHMSNS_THM_L

CPUTHMSNS_ALERT_L

9

=I2C_CPUTHMSNS_SDA

10

=I2C_CPUTHMSNS_SCL

Placement note:

Place U5570 under CPU
and close to left fin stack

R5571

1/16W
MF-LF

10K

1

1

R5572

10K

5%

5%
1/16W
MF-LF

402

402

2

2

44

BI

44

BI

Placement note:

Place U5540 near battery
charger circuit

=PP3V3_S0_CPUTHMSNS

8

CPU_THERMD_P

10 96

BI

10 96

BI

CPUTHMSNS_D2_P

96

1

SIGNAL_MODEL=EMPTY

CPU_THERMD_N

SIGNAL_MODEL=EMPTY

CPUTHMSNS_D2_N

96

D

Detect Right Fin Stack Temperature

Detect CPU Die Temperature

Placement note:

Place Q5501 on bottom side
close to right fin stack

Q5501

BC846BMXXH

SOT732-3

3

2

Battery Charger Proximity

=PP3V3_S0_BATTCHARGERTMPSNSR

8

TEMP SENSOR HAS ADDRESS WRITE:0X92, READ: 0X93

=SMBUS_TMPSNSR_SDA

44

=SMBUS_TMPSNSR_SCL

44

6

1

SDA

SCL

5

V+

U5540

HPA00330AI

SOT563

GND

2

ADD0

ALERT

4

3

D

1

C5540

0.1uF

20%

10V

2

CERM

402

MCP Proximity/MCP Die/Right Heat Pipe

R5500

C

Detect MCP Die Temperature

J5502

78171-0002

M-RT-SM

Detect Right Heat Pipe Temperature

518S0519

3

1

2

4

=PP3V3_S0_REMTHMSNS

8

21 96

BI

21 96

BI

MCPTHMSNS_D_P

7

96

MCPTHMSNS_D_N

7

96

Placement note:

Keep 2 caps as close
to IC pins as possible

MCP_THMDIODE_P

MCP_THMDIODE_N

47

21

5%
1/16W
MF-LF

402

SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=EMPTY

PP3V3_S0_REMTHMSNS_R

MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V

1

C5511

0.0022uF

10%
50V

2

CERM

402

1

C5521

0.0022uF

10%
50V

2

CERM

402

1

C5500

0.1uF

20%
10V

2

CERM

1

VDD

U5500

EMC1403-2

DP1

DN1

DP2/DN3

DN2/DP3

GND

6

DFN

CRITICAL

THRM_PAD

THERM*

ALERT*

SMDATA

SMCLK

11

2

38

4

5

402

7

REMTHMSNS_THM_L

REMTHMSNS_ALERT_L

9

=SMBUS_MCPTHMSNS_SDA

10

=SMBUS_MCPTHMSNS_SCL

Placement note:

Place U5500 near MCP

R5501

1/16W
MF-LF

10K

1

1

R5502

10K

5%

5%

1/16W
MF-LF
402

402

2

2

BI

BI

NOTE: U5500 Changed to EMC1403-2. Write Address: 0x9A

Note: EMC1403 can perform Beta

Compensation for External Diode 1 only

44

44

B

C

B

Detect Left Heat Pipe Temperature

A

Placement note:

Place on top side under left heat pipe near CPU

8

76

GPU Proximity/GPU Die/Left Heat Pipe

R5550

47

21

5%
1/16W
MF-LF

402

SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=EMPTY

PP3V3_S0_GPUTHMSNS_R

MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V

1

C5551

0.0022uF

10%
50V

2

CERM

402

1

C5552

0.0022uF

10%
50V

2

CERM

402

Detect GPU Die Temperature

3

Q5503

BC846BMXXH

SOT732-3

2

=PP3V3_S0_GPUTHMSNS

8

75 96

BI

75 96

BI

GPUTHMSNS_D_P

96

1

GPU_TDIODE_P

GPU_TDIODE_N

GPUTHMSNS_D_N

96

Placement note:

Keep 2 caps as close
to IC pins as possible

5

1

C5550

0.1uF

20%
10V

2

CERM

1

VDD

U5550

EMC1403-1

DP1

DN1

DP2/DN3

DN2/DP3

GND
6

DFN

CRITICAL

THRM_PAD

THERM*

ALERT*

SMDATA

SMCLK

11

2

38

4

5

402

7

GPUTHMSNS_THM_L

GPUTHMSNS_ALERT_L

9

=SMBUS_GPUTHMSNS_SDA

10

=SMBUS_GPUTHMSNS_SCL

Placement note:

Place U5550 near GPU

4

R5551

1/16W
MF-LF

10K

1

1

R5552

10K

5%

5%

1/16W
MF-LF
402

402

2

2

44

BI

44

BI

SYNC_MASTER=YWU_K20

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

APPLE INC.

3

2

Thermal Sensors

SYNC_DATE=05/28/2008

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

DRAWING NUMBER

SIZE

D

SCALE

NONE

051-8071

SHT

OF

47 98

1

A

REV.

B

87

www.vinafix.vn

6

5

4

3

21

D

C

=PP5V_S0_FAN_LT

7 8

=PP3V3_S0_FAN_LT

8

SMC_FAN_0_TACH

OUT OUT

R5651

100K

1/16W
MF-LF

402

41

IN

SMC_FAN_0_CTL

1

5%

2

4

Left Fan

R5655

47K

21

FAN_LT_TACH

7

5%
1/16W
MF-LF

402

5

Q5660

G

2N7002DW-X-G

SOT-363

SD

3

FAN_LT_PWM

R5650

1/16W
MF-LF

47K

=PP5V_S0_FAN_RT

8

=PP3V3_S0_FAN_RT

41 41

41

8

SMC_FAN_1_TACH

SMC_FAN_1_CTL

IN

R5661

100K

1/16W
MF-LF

5%

402

CRITICAL

1

5%

402

2

J5650

78171-0004

M-RT-SM
5

1

2

3

4

6

Right Fan

R5665

1

2

G

2

SD

1

47K

21

5%
1/16W
MF-LF

402

Q5660

2N7002DW-X-G

SOT-363

6

FAN_RT_TACH

7

FAN_RT_PWM

7 7

R5660

1/16W
MF-LF

47K

CRITICAL

1

5%

402

2

J5660

78171-0004

M-RT-SM

5

1

2

3

4

6

518S0521518S0521

D

C

B

A

8

76

B

Fan Connectors

SYNC_MASTER=M98_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

5

4

3

2

SCALE

NONE

051-8071

SHT

SYNC_DATE=04/01/2008

OF

1

A

REV.

B

9848

87

www.vinafix.vn

6

5

4

3

21

PIN NAME

PSOC USB CONTROLLER

USB INTERFACES TO MLB

SPI HOST TO Z2

D

PICKB_L

7

50

BUTTON_DISABLE

49

Z2_HOST_INTN

50

WS_LEFT_SHIFT_KEY

49

WS_LEFT_OPTION_KEY

49

WS_CONTROL_KEY

49

Z2_KEY_ACT_L

7

50

Z2_BOOT_CFG1

7

50

TP_P4_5
Z2_DEBUG3

7

50

Z2_RESET

7

50

PSOC_MISO

7

50

PSOC_F_CS_L

7

50

PSOC_MOSI

7

50

PSOC_SCLK

7

50

Z2_MISO

7

50

Z2_CS_L

7

50

Z2_MOSI

50

Z2_SCLK

50

C

7

49

DIFFERENTIAL_PAIR=USB2_TPAD

B

TO MLB CONNECTOR

DIFFERENTIAL_PAIR=USB2_TPAD

20 91

20 91

USB_TPAD_P

USB_TPAD_N

1

2

3

4

5

6

7

8

9

10 33

11 32

12 31

13 30

14 29

P2_3
P2_1
P4_7
P4_5
P4_3
P4_1
P3_7
P3_5
P3_3
P3_1
P5_7
P5_5
P5_3
P5_1

P2_5

P1_7

15281627172618

TP_PSOC_SCL

TP_PSOC_SDA

TP_PSOC_P1_3

7

ISSP_SCLK_P1_1

ISSP SCLK/I2C SCL

R5701

24

21

5%

1/16W
MF-LF

402

R5702

24

21

5%

1/16W
MF-LF

402

TRACKPAD PICK BUTTONS
KEYBOARD SCANNER

P0_1

P0_3

P0_5

51485247534654

P0_7

50194922

VSS

554456

P2_7

CRITICAL

U5701

CY8C24794

MLF

(SYM-VER2)

APN 337S2983

OMIT

P1_1

P1_3

P1_5

D+

D-

VSS

21

20

USB_TPAD_R_P

DIFFERENTIAL_PAIR=USB2_TPAD
NET_SPACING_TYPE=USB
NET_PHYSICAL_TYPE=USB_90D

USB_TPAD_R_N

DIFFERENTIAL_PAIR=USB2_TPAD
NET_SPACING_TYPE=USB
NET_PHYSICAL_TYPE=USB_90D

PP3V3_S3_PSOC

49

49 7 49

7

7

WS_KBD22

WS_KBD23

WS_KBD21

VDD

P0_4

P0_2

P0_6

P7_7

P7_0

P1_0

VDD

23

24

25

PP3V3_S3_PSOC

49

49

49

49

7

7

7

WS_KBD18

WS_KBD19

WS_KBD20

43

45

P2_4

P2_6

P0_0

P2_2
P2_0
P4_6
P4_4
P4_2
P4_0
P3_6
P3_4
P3_2
P3_0
P5_6
P5_4
P5_2
P5_0

THRML

P1_2

P1_4

P1_6

ISSP_SDATA_P1_0

ISSP SDATA/I2C SDA

PAD

42

41

40

39

38

37

36

35

34

57

WS_KBD4
WS_KBD5
WS_KBD6

Z2_CLKIN

TP_P7_7

49

WS_KBD17
WS_KBD16N
WS_KBD15_C
WS_KBD14
WS_KBD13
WS_KBD12
WS_KBD11
WS_KBD10
WS_KBD9
WS_KBD8
WS_KBD7
WS_KBD1
WS_KBD2
WS_KBD3

7

7

7

7

49

7

50

7

49

49

49

7

49

7

49

7

49

7

49

7

49

7

49

7

49

7

49

7

49

7

49

7

49

49

49

49

IC

TMP102

3V3 LDO

PSOC

18V BOOSTER

PSOC PROGRAMMING CONNECTOR

TEST POINTS ARE FOR ON BOARD PROGRAMMING

=PP3V3_S3_TPAD

8

49

ISSP_SCLK_P1_1

7

49

ISSP_SDATA_P1_0

7

49

=PP3V3_S3_TPAD

8

49

WS_LEFT_SHIFT_KBD

7

49

=PP3V3_S3_TPAD

8

49

WS_LEFT_OPTION_KBD

7

49

8

49

7

49

CURRENT

V+

10UA

80UA

VDD

60MA MAX

60MA MAX

VOUT

VDD

8MA (TYP)

14MA (MAX)

VIN

4MA (MAX)

ISOLATION CIRCUIT

=PP3V42_G3H_TPAD

8

49

=PP3V42_G3H_TPAD

8

49

=PP3V42_G3H_TPAD

8

49

=PP3V3_S3_TPAD

WS_CONTROL_KBD

U5701 CHIP DECOUPLING

PLACE C5701, C5702 & C5703

CLOSE TO U5701

PP3V3_S3_PSOC

49

1

C5701

4.7UF

20%

6.3V

2

X5R
603

VDD PIN 22

1

C5702

100PF

5%
50V

2

CERM
402

MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM

1

C5703

0.1UF

10%
16V

2

X7R-CERM
402

PLACE C5704, C5705 & C5706

CLOSE TO U5701

1

2

C5704

100PF

5%
50V
CERM
402

VDD PIN 49

1

C5705

0.1UF

10%
16V

2

X7R-CERM
402

1

C5706

4.7UF

20%

6.3V

2

X5R
603

R5704

1.5

5%
1/16W
MF-LF

402

=PP3V3_S3_TPAD

21

TPAD BUTTONS DISABLE

8

49

R_SNS

2.55 KOHM

10 OHM

0.2 OHM

1.5 OHM

4.7 OHM

2

A

1

B

2

1

2

1

BUTTON_DISABLE

49

Q5701

SSM3K15FV

SOD-VESM-HF

U5725

A

B

U5726

A

B

TC7SZ08AFEAPE

5

3

5

3

U5727

D

CRITICAL

SOT665

4

Y

CRITICAL

TC7SZ08AFEAPE

SOT665

Y

CRITICAL

TC7SZ08AFEAPE

5

SOT665

Y

3

3

V_SNS POWER

0.0255 V

0.204 V

0.6 V

0.012 V

0.012 V

0.021 V

0.0188 V

4

0.255E-6 W

16.32E-6 W

36E-3 W

0.72E-3 W

96E-6 W

294E-6 W

75.2E-6 W

TPAD_DEBUG

CRITICAL

APN 518S0430

J5702

FH19C-4S-0.5SH25

F-RT-SM1

5

NC

1

2

3

ISSP CLOCK

4

ISSP DATA

6

NC

C5725

0.1UF

21

20%
10V

CERM

402

WS_LEFT_SHIFT_KEY

C5726

0.1UF

21

20%
10V

CERM

402

WS_LEFT_OPTION_KEY

C5727

0.1UF

21

20%
10V

CERM

4

402

PLACE THESE COMPONENTS CLOSE TO J5800

THIS ASSUMES THERE’S A PP3V42_G3H PULL UP ON MLB

WS_CONTROL_KEY

49

49

R5714

470

1%
1/16W
MF-LF

402

R5715

10K

1%
1/16W
MF-LF

402

1

C5710

0.1UF

20%

10V

2

CERM

402

21

21

7

41 42

SMC_ONOFF_L

OUT

WS_KBD15_C

49

WS_KBD16N

49

PLACEMENT_NOTE=NEAR J5713

SMC_MANUAL_RESET LOGIC

WS_LEFT_SHIFT_KBD

7

49

WS_LEFT_OPTION_KBD

7

49

WS_CONTROL_KBD

7

49

1

R5769

33K

5%

1/16W
MF-LF
402

2

49

A

1

SMC_LID

40 41 42

IN

GS

THE TPAD BUTTONS WILL BE DISABLE

2

WHEN THE LID IS CLOSED
LID OPEN => SMC_LID_LC ~ 3.42V

LID CLOSE => SMC_LID_LC < 0.50V

KEYBOARD CONNECTOR

=PP3V3_S3_TPAD

8

49

WS_KBD1

7

49

WS_KBD2

7

49

WS_KBD3

7

49

WS_KBD4

7

49

WS_KBD5

7

49

WS_KBD6

7

49

WS_KBD7

7

49

WS_KBD8

7

49

WS_KBD9

7

49

WS_KBD10

7

49

WS_KBD11

7

49

WS_KBD12

7

49

WS_KBD13

7

49

WS_KBD14

7

49

WS_KBD15_CAP

7

WS_KBD16_NUM

7

WS_KBD17

7

49

WS_KBD18

7

49

WS_KBD19

7

49

WS_KBD20

7

49

WS_KBD21

7

49

WS_KBD22

7

R5710

1K

21

5%
1/16W
MF-LF

402

=PP3V42_G3H_TPAD

8

49

1

R5770

33K

5%

1/16W
MF-LF
402

2

49

WS_KBD23

7

49

WS_KBD_ONOFF_L

7

=PP3V42_G3H_TPAD

8

49

WS_LEFT_SHIFT_KBD

7

49

WS_LEFT_OPTION_KBD

7

49

WS_CONTROL_KBD

7

49

1

R5771

33K

5%
1/16W
MF-LF
402

2

1

A

3

B

6

C

APPLE INC.

CRITICAL

J5713

APN 518S0637

32

NC

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

NC

31

F-RT-SM

FF14-30A-R11B-B-3H

1

C5758

0.1UF

10%
16V

2

X7R-CERM
402

APN 311S0406

CRITICAL

5

SN74LVC1G10

SC70

4

Y

U5703

2

SMC_TPAD_RST_L

WELLSPRING 1

SYNC_MASTER=YMA_K20

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

42

SYNC_DATE=05/19/2008

051-8071

SHT

OF

D

C

B

A

REV.

B

9849

8

76

5

4

3

2

1

87

www.vinafix.vn

6

5

4

3

21

BOOSTER +18.5VDC FOR SENSORS

BOOSTER DESIGN CONSIDERATION:

- POWER CONSUMPTION

- DROOP LINE REGULATION

- RIPPLE TO MEET ERS

D

=PP5V_S3_TPAD

50

8

VOLTAGE=5V
MIN_LINE_WIDTH=0.50MM

MIN_NECK_WIDTH=0.20MM

1

C5800

0.1UF

20%

PLACEMENT_NOTE=NEAR J5800

C

10V

2

CERM
402

R5801

5%
1/10W
MF-LF

603

0

TPAD_GND_F

21

50

7

VOLTAGE=0V
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM

21

0

5%

R5805

MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM

1

C5816

0.1UF

2

1/16W

MF-LF

10%
16V
X7R-CERM
402

402

INPUT_SW

0.50MM

0.20MM

PP5V_S3_BOOSTER

1

C5817

2.2UF

10%
16V

2

X5R
603

APN 152S0504

CRITICAL

L5801

3.3UH-870MA

VLF3010AT-SM-HF

APN 353S1401

21

BOOST_SW

2

VIN

U5805

1

L

TPS61045

QFN

35

DO

CRITICAL

THRML

PAD

9

PGND
7

CTRL

GND
6

4

FB

8

SW

- 100-300 KHZ CLEAN SPECTRUM

- STARTUP TIME LESS THAN 2MS

- R5812,R5813,C5818 MODIFIED

MIN_LINE_WIDTH=0.50MM

MIN_NECK_WIDTH=0.20MM

SWITCH_NODE=TRUE

BOOST_FB

Z2_BOOST_EN

1

R5811

100K

1%
1/16W
MF-LF
402

2

50

7

D5802

SOD-323

B0520WSXG

APN 371S0313

21

MIN_LINE_WIDTH=0.50MM

MIN_NECK_WIDTH=0.20MM

1

C5818

39PF

5%
50V

2

CERM
402

PP18V5_S3_SW

VOLTAGE=18.5V

1

R5812

1M

1%
1/16W
MF-LF
402

2

1

R5813

71.5K

1%

1/16W

MF-LF

402

2

1

2

C5819

1UF

10%
25V
X5R
603-1

R5806

0

5%
1/16W
MF-LF

402

PP18V5_S3

21

MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM

VOLTAGE=18.5V

50

7

50

7

49

7

49

7

49

49

7

49

7

50

49

49

7

49

7

50

7

IPD FLEX CONNECTOR

TPAD_GND_F

Z2_CS_L
Z2_DEBUG3
Z2_MOSI
Z2_MISO
Z2_SCLK
Z2_BOOST_EN
Z2_HOST_INTN

Z2_BOOT_CFG1
Z2_CLKIN

PP3V3_S3_LDO

0.50MM

0.20MM

0.50MM

0.20MM

APN 516S0689

10

12 11

14 13

16 15

18 17

20

22 21

CRITICAL

J5800

55560-0228

M-ST-SM

2

1

43

65

87

9

19

0.50MM

0.20MM

Z2_KEY_ACT_L

Z2_RESET

PSOC_F_CS_L

PICKB_L

PSOC_MISO

PSOC_MOSI

PSOC_SCLK

=I2C_TPAD_SDA

=I2C_TPAD_SCL

PP18V5_S3

49

7

49

7

49

7

49

7

49

7

49

7

49

7

44

44

50

7

D

C

3V3 LDO FOR IPD

R5873

=PP5V_S3_TPAD

50

8

B

10

1%
1/16W
MF-LF

402

1

C5853

2.2UF

10%

16V

2

X5R
603

21

PP5V_S3_VR

1

CRITICAL

APN 353S1364

2

VDD

VR5802

MM3243DRRE

MLF

CE

GND

4

VOUT

PP3V3_S3_LDO_R

3

MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM

VOLTAGE=3.3V

0.2

R5836

50

2

1

7

MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM

1%

PP3V3_S3_LDO

VOLTAGE=3.3V

MF

1/6W

402-HF

1

C5838

0.1UF

10%

16V

2

X7R-CERM
402

1

C5854

4.7UF

20%

6.3V

2

X5R
603

B

Keyboard LED Driver

10UH-0.58A-0.35OHM

1

VIN

SW

LED

CRITICAL

U5850

LT3491

DFN

CAP

THRML

PAD

7

CRITICAL

L5850

1098AS-SM

3

5

4

HF APN 152s0898

21

KBDLED_SW

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.25 MM
SWITCH_NODE=TRUE

1

R5855

10

1%

1/16W

MF-LF

402

2

KBDLED_CAP

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.25 MM

1

2

C5855

1UF

10%
35V
X5R
603

KBDLED_ANODE

7

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.25 MM

CRITICAL

J5815

FF18-4A-R11AD-B-3H

SMC_KDBLED_PRESENT_L

50

7

1

2

3

4

APN 518S0691

KBD BACKLIGHT CONNECTOR

F-RT-SM

J5815 pin 1 is grounded

on keyboard backlight flex

WELLSPRING 2

SYNC_MASTER=K20_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

D

NONE

DRAWING NUMBER

SYNC_DATE=09/24/2008

051-8071

SHT

OF

A

REV.

B

9850

=PP3V3_S0_TPAD

8

1

To detect Keyboard backlight, SMC will

tristate SMC_SYS_KBDLED:

LOW = keyboard backlight present

HIGH= keyboard backlight not present

BOM OPTION: KBDLED_YES

A

R5853 ALWAYS PRESENT

41

SMC_SYS_KBDLED

IN

SMC_KDBLED_PRESENT_L

50

7

R5853

470K

1/16W
MF-LF

R5854

5%

402

2

1

4.7K

5%
1/16W
MF-LF

402

2

=PPVIN_S0_KBDLED

9

NO STUFF

R5852

10K

1/16W
MF-LF

402

1

C5850

1UF

10%
16V

2

X5R
603

6

CTRL

1

5%

2

GND

2

8

76

5

4

3

2

1

87

www.vinafix.vn

6

5

4

3

21

D

42 41

42

OUT

Pull-up required if SMS_INT_L not used.

8

=PP3V3_S5_SMC

SMS_INT_L

1

R5932

10K

5%
1/16W
MF-LF
402

2

1

R5931

10K

5%
1/16W
MF-LF
402

2

PROD_DIGSMS

ENG_DIGSMS

=I2C_SMS_SCL

44

=I2C_SMS_SDA

44

=PP3V3_S3_SMS

51

8

Digital SMS

6

SCK

7

SDO

8

SDI

4

INT

5

CSB

2

VDDIO

VDD

U5930

273141043

LGA

CRITICAL

RESERVED

GND

3

9

NC

ENG_DIGSMS

ENG_DIGSMS

1

C5931

0.022UF

10%

11

NC

12

NC

1

NC

10

NC

16V

2

CERM-X5R
402

ENG_DIGSMS

1

C5932

0.1UF

10%
16V

2

X5R
402

Circle indicates pin 1 location when placed
in correct orientation

Desired orientation when

placed on board top-side:

+Y

+Z (up)

+X

Front of system

D

Stuff R5931 AND NoStuff R5932 to use U5930

C

NoStuff R5931 AND Stuff R5932 if U5930 is not used

C

Analog SMS

R5921 PULLS UP SMS_PWRDN TO TURN OFF SMS WHEN PIN IS NOT BEING DRIVEN BY SMC

=PP3V3_S3_SMS

51

8

AP344ALH

1

FS

5

PD

2

ST

RES

4

RES

3

NC

6

NC

9

NC

14

VDD

U5920

LGA

CRITICAL

GND

7

VOUTX

VOUTY

VOUTZ

SMS_X_AXIS

12

10

SMS_Y_AXIS

8

SMS_Z_AXIS

11

NC

NC

13

NC

NC

16

NC

NC

B

41

IN

SMS_ONOFF_L

SMS_PWRDN

MAKE_BASE=TRUE

R5921

10K

1/16W
MF-LF

402

5%

1

2

SMS_SELFTEST

1

R5922

10K

5%
1/16W
MF-LF
402

2

15

NC

NC
NC
NC

1

2

1

C5923

0.01UF

10%
16V

2

CERM
402

C5922

0.1UF

10%
16V
X5R
402

1

C5924

0.01UF

10%
16V

2

CERM
402

1

C5926

2

10UF

20%
4V
X5R
603

1

C5925

0.01UF

10%
16V

2

CERM
402

41

OUT

41

OUT

41

OUT

A

Desired orientation when

placed on board top-side:

+Y

Front of system

+Z (up)

Circle indicates pin 1 location when placed
in correct orientation

+X

Sudden Motion Sensor (SMS)

SYNC_MASTER=YWU_K20

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

D

NONE

DRAWING NUMBER

051-8071

SHT

SYNC_DATE=06/17/2008

REV.

B

OF

9851

B

A

8

76

5

4

3

2

1

87

www.vinafix.vn

6

5

4

3

21

D

=PP3V3_S5_ROM

43

8

NO STUFF

1

1/16W
MF-LF

10K

R6100

5%

402

2

R6190

C

SPI_CLK_MUX

43 43

PLACEMENT_NOTE=PLACE CLOSE TO U6100

SPI_MLB_CS_L

43

IN

R6150

0

5%
1/16W
MF-LF

402

21

3.3K

1/16W
MF-LF

1

1

R6101

3.3K

5%

5%

1/16W
MF-LF
402

402

2

2

SPI_CLK

91

SPI_WP_L
SPI_HOLD_L

C6100

0.1UF

CERM

1

20%
10V

2

402

6

SCLK

1

CE*

3

WP*/ACC

7

HOLD*

CRITICAL

8

VCC

U6100

32MBIT

SOP

MX25L3205DM2I-12G

OMIT

GND

4

SI/SIO0

SO/SIO1

R6152

5

SPI_MOSI

91

R6105

1/16W
MF-LF

402

0

5%

2

SPI_MISO_R

91

NO STUFF

1

R6191

10K

5%
1/16W
MF-LF
402

2

0

21

SPI_MOSI_MUX

5%

PLACEMENT_NOTE=PLACE CLOSE TO U6100

1/16W
MF-LF

402

21

PLACEMENT_NOTE=PLACE CLOSE TO U6100

SPI_MISO_MUX

ININ

43

OUT

D

C

MCP79 SPI Frequency Select

Frequency

B

25MHz is selected with R5190 and R5191
Any of the 4 frequencies can be selected
with R6190, R6191, R5190 and R5191

31 MHz

42 MHz

25 MHz

1 MHz

SPI_MOSI

0

0

1

1

SPI_CLK

0

1

0

1

B

SPI ROM

051-8071

SHT

SYNC_DATE=05/01/2008

REV.

B

OF

9852

A

A

SYNC_MASTER=M98_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

SCALE

NONE

8

76

5

4

3

2

1

87

www.vinafix.vn

6

5

4

3

21

AUDIO CODEC

C6206

0.001UF

10%
50V
CERM
402

1

R6206

20.0K

1%
1/16W
MF-LF
402

2

L6202

FERR-220-OHM

0402

CRITICAL

C6205

CASE-AL1

CRITICAL

C6221

3.3UF

TANT

SMA-HF1

100UF

6.3V
TANT

10%
16V

21

PP4V6_AUDIO_ANALOG

1

1

C6207

0.001UF

2

R6203

33

5%
1/16W
MF-LF

402

20%
50V

2

CERM
402

21

GND_AUDIO_CODEC

20%

58 54 53

58 56 55 54 53

AUD_SPDIF_OUT

AUD_SPDIF_IN
AUD_SENSE_A
AUD_SENSE_B

AUD_BI_PORT_A_L
AUD_BI_PORT_A_R

AUD_BI_PORT_F_L
AUD_BI_PORT_F_R
AUD_VREF_PORT_F
AUD_VREF_PORT_A
AUD_BI_PORT_E_L
AUD_BI_PORT_E_R

AUD_VREF_PORT_B
AUD_BI_PORT_B_L
AUD_BI_PORT_B_R

D

57

OUT

57

IN

58

IN

58

IN

54

IN

54

IN

58

IN

58

IN

58

OUT

54

OUT

58

OUT

58

OUT

56

OUT

56

OUT

56

OUT

C

AUD_BI_PORT_H_R

1

R6207

100K

5%
1/16W
MF-LF
402

1

C6222

0.001UF

10%
50V

2

CERM
402

1

2

2

56

OUT

APPLE P/N 353S1527

L6201

=PP3V3_S0_AUDIO

58 57 53

8

D

HDA_BITCLK

9

IN

HDA_SYNC

91 21

IN

HDA_SDOUT

91 21

IN

HDA_SDIN0

91 21

OUT

AUD_GPIO_0

55

OUT

AUD_GPIO_1

IN

AUD_BI_PORT_C_L

56

OUT

AUD_BI_PORT_C_R

56

OUT

AUD_BI_PORT_D_L

55

OUT

AUD_BI_PORT_D_R

55

OUT

FERR-220-OHM

0402

R6204

22

5%
1/16W
MF-LF

402

21

NOSTUFF

R6251

21

1/16W
MF-LF

20K

1

5%

402

2

C

HDA_RST_L

91 21

IN

GND_AUDIO_CODEC

58 56 55 54 53

MIN_LINE_WIDTH=0.30 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=0V

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.20MM

C6200

4.7UF

CODEC_SDATA_IN

R6250

33

21

5%
1/16W
MF-LF

402

VOLTAGE=3.3V

1

20%

4V

2

X5R
402

AUD_GPIO_0_R

NC_BAL_IN_L
NC_BAL_IN_COM
NC_BAL_IN_R

1

R6205

100K

5%
1/16W
MF-LF
402

2

1

C6201

0.001UF

10%
50V

2

CERM
402

1

2

NO_TEST

NO_TEST

NO_TEST

BEEP

C6220

0.1UF

10%
16V
X5R
402

CODEC_DVDD

1

C6203

0.001UF

10%
50V

2

CERM
402

6

10

5

8

2

3

23

24

35

18

19

20

12

11

NOSTUFF

1

R6201

0

5%
1/16W
MF-LF
402

2

BCLK
SYNC
SDATA_OUT
SDATA_IN

GPIO0/DMIC-CLK
GPIO1/DMIC-L

PORT-C-L
PORT-C-R

PORT-D-L
PORT-D-R

CD-L
CD-GND
CD-R

BEEP

RESET*

38

25

9

1

DVDD

DVDD_IO

SPDIFI/EAPD/MIDI-I/DMIC-R

CRITICAL

ALC885-VB3-GR

U6200

LQFP

REV B3

AVDD1

AVDD2

PORT-A-VREFO/DCVOL

DVSS

7

4

AVSS1

26

AVSS2

42

AVDD_ADC_DAC

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.20MM

VOLTAGE=4.6V

SPDIFO

SENSE_A
SENSE_B

PORT-A-L
PORT-A-R

PORT-F-L
PORT-F-R

PORT-F-VREFO

PORT-E-L

PORT-E-R
PORT-E-VREFO
PORT-B-VREFO

PORT-B-L

PORT-B-R

PORT-C-VREFO

PORT-B-VREFO2

PORT-G-L

PORT-G-R

PORT-H-L

PORT-H-R

VREF

JDREF

NC

CRITICAL

C6204

CASE-AL1

48

47

13

34

39

41

16

17

30

33

1436

15

31

NO_TEST

28

21

22

29

NO_TEST

32

NO_TEST

43

NO_TEST

44

NO_TEST

45

NO_TEST

46

27

AUD_CODEC_JDREF

40

NC_VRP

37

NO_TEST

1

100UF

20%

6.3V
2

TANT

NC_AUD_VREF_PORT_B2

1

2

AUD_SPDIF_O

NC_AUD_VREF_PORT_E

NC_AUD_VREF_PORT_C

NC_AUD_BI_PORT_G_L
NC_AUD_BI_PORT_G_R

NC_AUD_BI_PORT_H_L

AUD_CODEC_VREF

B

L6200

PP5V_S3_AUDIO

55

9

R6220

1K

=PP3V3_S0_AUDIO

58 57 53

8

A

5%
1/16W
MF-LF

402

XW6200

SM

21

C6210

21

8

FERR-220-OHM

21

0402

1

0.1UF

10%
16V

2

X5R
402

76

MIN_LINE_WIDTH=0.30 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=5V

AUD_4V6_REG_IN

AUD_REG_SHDN_L

1

R6221

10K

5%
1/16W
MF-LF
402

2

CRITICAL

C6208

4.7UF

AUDIO 4.6 V REGULATOR MIKEY 3.3 V REGULATOR

C6211

0.015UF

3

1

7

21

10%
25V
X7R
402

U6201

MAX8902A

TDFN

IN

BP

GNDENPAD

2

SELA
SELB

OUTS

THRML

9

OUT

4

5

8

6

4V6_REG_SENSE

XW6203

SM

21

CRITICAL

C6213

10UF

X5R-CERM

0805

PP4V6_AUDIO_ANALOG

58 54 53

R6252

1K

1/16W
MF-LF

21

5%

402

C6250

0.1UF

MIKEY_REG_SHDN_L

1

10%
16V

2

X5R
402

C6251

0.1UF

1

10%
16V

2

X5R
402

=PP3V3_S0_AUDIO

58 57 53

8

PP4V6_AUDIO_ANALOG

MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=4.6V

1

1

C6212

10%
16V

2

2

0.1UF

10%
25V
X5R
402

58 54 53

58 56 55 54 53

GND_AUDIO_CODEC

4V6_REG_BP

CRITICAL

1

1

C6209

10%
10V
X5R
805

0.001UF

10%
50V

2

2

CERM
402

1

R6253

10K

5%
1/16W
MF-LF
402

2

APPLE P/N 353S1860APPLE P/N 353S1897

B

CRITICAL

U6202

TPS71733

6

IN

4

EN

GND

1

SON

OUT

3

NR/FB

2

3V3_REG_FB

5

NC

C6252

0.01UF

CERM

1

1

10%
16V

2

402

2

CRITICAL

C6253

1UF

10%
10V
X5R
402

PP3V3_MIKEY_ANALOG

MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.10MM
VOLTAGE=3.3V

58

AUDIO:CODEC

051-8071

SHT

SYNC_DATE=09/29/2008

OF

53 98

1

A

REV.

B

GND_AUDIO_CODEC

58 56 55 54 53

SYNC_MASTER=AUDIO_K20

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

5

4

3

2

SCALE

NONE

87

www.vinafix.vn

6

5

4

3

21

D

D

Pseudo-Diff Line-In Filter
GAIN = -5.4 DB AV = 0.52

FC = 1.89 HZ

L6300

FERR-220-OHM

0402

R6302

27.4K

57

IN

58 53

AUD_LI_INL

PP4V6_AUDIO_ANALOG

C

AUD_LI_GND

57

IN

VOLTAGE=0V

R6301

10

5%
1/16W
MF-LF

402

58 56 55 54 53

GND_AUDIO_CODEC

R6303

27.4K

B

AUD_LI_INR

57

IN

1/16W
MF-LF

1/16W
MF-LF

21

1

1%

402

2

21

1

1%

402

2

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.20MM

PP4V6_AUDIO_LINE_IN

CRITICAL

C6310

3.3UF

21

AUD_LI_INL_C

10%
16V

TANT

SMA-HF1

CRITICAL

C6311

3.3UF

21

AUD_LIFILT_LT_R

10%
16V

TANT

SMA-HF1

3.3UF

21

10%
16V

TANT

SMA-HF1

3.3UF

21

10%
16V

TANT

SMA-HF1

CRITICAL

AUD_LIFILT_RT_R

AUD_LI_INR_C

C6320

CRITICAL

C6321

R6310

25.5K

1%
1/16W
MF-LF

402

CRITICAL

R6311

25.5K

1%
1/16W
MF-LF

402

R6320

25.5K

1%
1/16W
MF-LF

402

R6321

25.5K

1%
1/16W
MF-LF

402

21

AUD_LI_INL_R

C6301

4.7UF

20%

6.3V

X5R-CERM

402

21

AUD_LIFILT_LT

21

AUD_LIFILT_RT

21

AUD_LI_INR_R

1

2

CRITICAL

C6300

0.001UF

CERM

R6312

13.3K

21

1%
1/16W
MF-LF

402

AUD_PORTA_L

CRITICAL

10

8

U6300

7

R6313

13.3K

1%
1/16W
MF-LF

402

R6322

13.3K

1%
1/16W
MF-LF

402

3

U6300

2

V+

V-

4

21

21

4

V-

V+

10

R6323

13.3K

1%
1/16W
MF-LF

402

MAX4253EUB

UMAX-HF

9

6

AUD_CODEC_INREF

5

1

UMAX-HF

MAX4253EUB

CRITICAL

21

AUD_LIFILT_SHUTDOWN_L

CRITICAL

1

C6303

0.001UF

10%
50V

2

CERM

402

AUD_PORTA_R

1

10%
50V

2

402

CRITICAL

1

C6302

100UF

20%

6.3V

2

TANT
CASE-AL1

C6312

2.2UF

10%
16V
X5R
603

CRITICAL

R6300

165

1%
1/16W
MF-LF

402

C6322

2.2UF

CRITICAL

21

AUD_BI_PORT_A_L

53

OUT

C

58

IN

21

21

10%
16V
X5R
603

AUD_VREF_PORT_A

GND_AUDIO_CODEC

AUD_BI_PORT_A_R

53

IN

58 56 55 54 53

53

OUT

B

A

8

76

AUDIO: LINE IN

SYNC_MASTER=AUDIO_K20

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

5

4

3

2

SCALE

NONE

SYNC_DATE=09/29/2008

051-8071

SHT

1

A

REV.

B

OF

9854

87

www.vinafix.vn

6

5

4

3

21

Headphone Amplifier (MAX9724A)

APN:353S1637

D

PP5V_S3_AUDIO

53

9

AUD_HPAMP_INL_M

55

IN

AUD_HPAMP_INR_M

55

IN

L6501

AUD_GPIO_0

53

IN

FERR-1000-OHM

0402

C

GND_AUDIO_CODEC

58 56 54 53

L6500

FERR-120-OHM-1.5A

0402

21

AUD_HPAMP_MUTE_L

XW6500

SM

21

PP5V_AUDIO_HPAMP_PVDD_F

VOLTAGE=5V
MIN_LINE_WIDTH=0.40 MM
MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.40 MM
MIN_NECK_WIDTH=0.20 MM

VOLTAGE=0V

21

GND_AUDIO_HPAMP_PGND

CRITICAL

C6500

10UF

X5R-CERM

0805

R6500

10%
16V

1/16W
MF-LF

10K

1

1

C6501

0.001UF

10%

2

1

5%

402

2

50V

2

CERM
402

12

VDD

CRITICAL

6

INL
INR

SHDN*

THRM

13

PAD

U6500

MAX9724A

TQFN

SGND

742

PGND

8

5

SVSS

9

1

2

OUTL
OUTR

C1P
C1N

PVSS

CRITICAL

C6503

1UF

10%
10V
X5R
402

11

10

1

3

MAX9724_C1P

MAX9724_C1N

MIN_LINE_WIDTH=0.20 mm
MIN_NECK_WIDTH=0.10 mm

MAX9724_PVSS

CRITICAL

C6502

10UF

10%
16V

X5R-CERM

0805

1

2

CRITICAL

C6504

1UF

AUD_HPAMP_OUTL

MIN_LINE_WIDTH=0.20 MM
MIN_NECK_WIDTH=0.15 MM

AUD_HPAMP_OUTR

MIN_LINE_WIDTH=0.20 MM

1

10%
10V

2

X5R
402

1

1

R6514

2.21K

1/16W
MF-LF

1%

402

R6524

2.21K

1%
1/16W
MF-LF
402

2

2

XW6501

SM

21

MIN_NECK_WIDTH=0.15 MM

AUD_LO_GND

VOLTAGE=0V

MIN_LINE_WIDTH=0.40 MM
MIN_NECK_WIDTH=0.20 MM

57 55

OUT

57 55

OUT

57

IN

D

C

1st Order DAC Filter

HP:3.52 HZ
VOLTAGE GAIN:1.53

B

CRITICAL

C6510

3.3UF

10%
16V

TANT

SMA-HF1

CRITICAL

C6520

3.3UF

10%
16V

TANT

SMA-HF1

21

21

AUD_CODEC_OUTL_C

AUD_CODEC_OUTR_C

AUD_BI_PORT_D_L

53

IN

AUD_HPAMP_INL_M

55

AUD_HPAMP_INR_M

55

AUD_BI_PORT_D_R

53

IN

A

R6510

13.7K

1%
1/16W
MF-LF

402

R6520

13.7K

1%

1/16W
MF-LF

402

LP:34 KHZ

21

21

R6511

21K

1%
1/16W
MF-LF

402

CRITICAL

C6511

220PF

21

CERM

CRITICAL

C6521

220PF

21

CERM

R6521

21K

1/16W

MF-LF

402

B

21

5%

25V

402

5%

25V

402

21

1%

AUD_HPAMP_OUTL

AUD_HPAMP_OUTR

57 55

57 55

SYNC_MASTER=AUDIO_K20

APPLE INC.

AUDIO: HEADPHONE AMP

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

051-8071

SHT

SYNC_DATE=09/29/2008

REV.

B

OF

9855

A

8

76

5

4

3

2

1

87

www.vinafix.vn

6

4X MONO SPEAKER AMPLIFIERS (MAX9705)

APN: 353S1595
GAIN = 12 DB

FC (SPEAKERS L1/R1) = ~796 HZ
FC (SPEAKERS L2/R2/LFE) = ~97 HZ

5

4

3

21

SPEAKER CHECKPOINTS

PP5V_S3_AUDIO_AMP

56

9

D

58 56 55 54 53

C

AUD_BI_PORT_C_L

53

IN

GND_AUDIO_CODEC

AUD_VREF_PORT_B

53

IN

PP5V_S3_AUDIO_AMP

56

9

AUD_BI_PORT_B_L

53

IN

58 56 55 54 53

AUD_SPKRAMP_SHUTDOWN_L

56

PP5V_S3_AUDIO_AMP

56

9

AUD_BI_PORT_C_R

53

IN

58 56 55 54 53

GND_AUDIO_CODEC

AUD_SPKRAMP_SHUTDOWN_L

56

GND_AUDIO_CODEC

L6610

FERR-1000-OHM

0402

L6601

FERR-1000-OHM

0402

AUD_SPKRAMP_SHUTDOWN_L

56

L6620

FERR-1000-OHM

0402

L6630

FERR-1000-OHM

0402

21

AUD_SPKRAMP_INL1_L

21

R6600

21

AUD_SPKRAMP_INL2_L

21

AUD_SPKRAMP_INR1_L

100K

1/16W
MF-LF

CRITICAL

C6613

0.01UF

21

10%
16V

CERM

402

CRITICAL

C6614

0.01UF

21

10%
16V

CERM

402

1

5%

402

2

CRITICAL

C6623

0.082UF

21

10%
16V

CERM-X7R

402

CRITICAL

C6624

0.082UF

21

10%
16V

CERM-X7R

402

CRITICAL

C6633

0.01UF

21

10%
16V

CERM

402

CRITICAL

C6634

0.01UF

21

10%
16V

CERM

402

MAX9705L1_NIN

B

PP5V_S3_AUDIO_AMP

56

9

L6640

53

58 56 55 54 53

56

53

AUD_BI_PORT_B_R

IN

GND_AUDIO_CODEC

AUD_SPKRAMP_SHUTDOWN_L

56

PP5V_S3_AUDIO_AMP

9

AUD_BI_PORT_H_R

IN

FERR-1000-OHM

FERR-1000-OHM

0402

L6650

0402

21

AUD_SPKRAMP_INR2_L

21

AUD_SPKRAMP_INC_R

A

58 56 55 54 53

GND_AUDIO_CODEC

AUD_SPKRAMP_SHUTDOWN_L

56

CRITICAL

C6643

0.082UF

10%
16V

CERM-X7R

402

CRITICAL

C6644

0.082UF

10%
16V

CERM-X7R

402

CRITICAL

C6653

0.082UF

10%
16V

CERM-X7R

402

CRITICAL

C6654

0.082UF

10%
16V

CERM-X7R

402

21

21

21

21

PLACE C6615 CLOSE TO VDD PIN

C6615

MAX9705L1_PIN

PLACE C6625 CLOSE TO VDD PIN

C6625

MAX9705L2_PIN
MAX9705L2_NIN

PLACE C6635 CLOSE TO VDD PIN

C6635

MAX9705R1_PIN
MAX9705R1_NIN

PLACE C6645 CLOSE TO VDD PIN

C6645

MAX9705R2_PIN
MAX9705R2_NIN

PLACE C6655 CLOSE TO VDD PIN

C6655

MAX9705C_PIN
MAX9705C_NIN

1UF

1UF

1UF

1UF

1UF

CRITICAL

1

1

10%
10V

2

X5R
402

2
3

5

1

10%
10V

2

X5R
402

2
3

5

1

10%
10V

2

X5R
402

2
3

5

1

10%
10V

2

X5R
402

2
3

5

1

10%
10V

2

X5R
402

2
3

5

VDD

U6610

MAX9705

IN+
IN-

SHDN*

GND

PGND

4

VDD

U6620

MAX9705

IN+
IN-

SHDN*

GND

4

VDD

U6630

MAX9705

IN+
IN-

SHDN*

GND

4

VDD

U6640

MAX9705

IN+
IN-

SHDN*

GND

4

VDD

U6650

MAX9705

IN+
IN-

SHDN*

GND

4

TDFN1

7

1

TDFN1

PGND

7

1

TDFN1

PGND

7

1

TDFN1

PGND

7

1

TDFN1

PGND

7

10

PVDD

THRML

11

PVDD

PVDD

PVDD

PVDD

OUT+
OUT­SYNC

PAD

10

OUT+
OUT­SYNC

THRML

PAD

11

10

OUT+
OUT­SYNC

THRML

PAD

11

10

OUT+
OUT­SYNC

THRML

PAD

11

10

OUT+
OUT­SYNC

THRML

PAD

11

CRITICAL

CRITICAL

CRITICAL

CRITICAL

PLACE C6611/C6612 CLOSE TO PVDD PIN

8
9
6

PLACE C6621/C6622 CLOSE TO PVDD PIN

1

R6603

0

5%
1/16W
MF-LF
402

2

8
9

SPKRAMP_SYNC1

6

PLACE C6631/C6632 CLOSE TO PVDD PIN

1

R6605

0

5%
1/16W
MF-LF
402

2

8
9

SPKRAMP_SYNC2

6

PLACE C6641/C6642 CLOSE TO PVDD PIN

1

R6607

0

5%
1/16W
MF-LF
402

2

8
9

SPKRAMP_SYNC3

6

PLACE C6651/C6652 CLOSE TO PVDD PIN

1

R6609

0

5%
1/16W
MF-LF
402

2

8
9

SPKRAMP_SYNC4

6

CRITICAL

C6612

100UF

6.3V
TANT

CASE-AL1

CRITICAL

C6622

100UF

6.3V
TANT

CASE-AL1

56

CRITICAL

C6632

100UF

6.3V
TANT

CASE-AL1

56

CRITICAL

C6642

100UF

6.3V
TANT

CASE-AL1

56

CRITICAL

C6652

100UF

6.3V
TANT

CASE-AL1

56

MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM

CRITICAL

1

1

C6611

0.001UF

20%

20%

20%

20%

20%

10%
50V

2

2

CERM
402

SPKRAMP_L1_OUT_P
SPKRAMP_L1_OUT_N

NOSTUFF

1

R6602

33

5%
1/16W

PLACE CLOSE TO U6610 PIN 9

MF-LF
402

2

CRITICAL

1

1

C6621

0.001UF

10%
50V

2

2

CERM
402

NOSTUFF

1

R6604

33

5%
1/16W
MF-LF
402

2

CRITICAL

1

1

C6631

0.001UF

10%
50V

2

2

CERM
402

NOSTUFF

1

R6606

33

5%
1/16W
MF-LF
402

2

CRITICAL

1

1

C6641

0.001UF

10%
50V

2

2

CERM
402

NOSTUFF

1

R6608

33

5%
1/16W
MF-LF
402

2

CRITICAL

1

1

C6651

0.001UF

10%
50V

2

2

CERM
402

SPKRAMP_SYNC1

SPKRAMP_L2_OUT_P
SPKRAMP_L2_OUT_N

PLACE CLOSE TO U6620 PIN 9

SPKRAMP_SYNC2

SPKRAMP_R1_OUT_P
SPKRAMP_R1_OUT_N

PLACE CLOSE TO U6630 PIN 9

SPKRAMP_SYNC3

SPKRAMP_R2_OUT_P
SPKRAMP_R2_OUT_N

PLACE CLOSE TO U6640 PIN 9

SPKRAMP_SYNC4

SPKRAMP_LFE_OUT_P
SPKRAMP_LFE_OUT_N

96 57 56

7

96 57 56

7

56

96 57 56

7

96 57 56

7

56

96 57 56

7

96 57 56

7

56

96 57 56

7

96 57 56

7

56

96 57 56

7

96 57 56

7

SPKRAMP_L1_OUT_P

MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM

SPKRAMP_L1_OUT_N

MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM

SPKRAMP_L2_OUT_P

MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM

SPKRAMP_L2_OUT_N

MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM

SPKRAMP_R1_OUT_P

MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM

SPKRAMP_R1_OUT_N

MIN_NECK_WIDTH=0.20 MM
MIN_LINE_WIDTH=0.30 MM

SPKRAMP_R2_OUT_P

MIN_NECK_WIDTH=0.20 MM
MIN_LINE_WIDTH=0.30 MM

SPKRAMP_R2_OUT_N

MIN_NECK_WIDTH=0.20 MM
MIN_LINE_WIDTH=0.30 MM

SPKRAMP_LFE_OUT_P

MIN_NECK_WIDTH=0.20 MM
MIN_LINE_WIDTH=0.30 MM

SPKRAMP_LFE_OUT_N

SIGNAL_MODEL=EMPTY

NOSTUFF

R6610

1/16W
MF-LF

402

SIGNAL_MODEL=EMPTY

NOSTUFF

R6620

1/16W
MF-LF

402

SIGNAL_MODEL=EMPTY

NOSTUFF

R6630

1/16W
MF-LF

402

SIGNAL_MODEL=EMPTY

NOSTUFF

R6640

1/16W
MF-LF

402

SIGNAL_MODEL=EMPTY

NOSTUFF

R6650

1/16W
MF-LF

402

1

0

5%

2

1

0

5%

2

1

0

5%

2

1

0

5%

2

1

0

5%

2

AUDIO:SPEAKER AMP

SYNC_MASTER=AUDIO_K20

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

D

NONE

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

DRAWING NUMBER

7

7

7

7

7

7

7

7

7

7

051-8071

SHT

96 57 56

96 57 56

96 57 56

96 57 56

96 57 56

96 57 56

96 57 56

96 57 56

96 57 56

96 57 56

SYNC_DATE=09/29/2008

OF

D

C

B

A

REV.

B

9856

8

76

5

4

3

2

1

87

www.vinafix.vn

6

5

4

3

21

AUDIO JACK 1 LO/HP JACK, SPDIF TX

L6703

R6713

0

402

5%
1/16W
MF-LF

402

R6714

0

5%
1/16W
MF-LF

402

R6716

0

5%
1/16W
MF-LF

402

2

1

21

R6711

1/10W
MF-LF

603

21

R6715

1/16W
MF-LF

402

21

R6710

1/16W
MF-LF

402

0

21

5%

0

21

5%

0

21

5%

NOSTUFF

1

C6710

100PF

5%
50V

2

CERM
402

NOSTUFF

C6711

100PF

CERM

5%

50V

402

NOSTUFF

1

C6712

100PF

5%
50V

2

CERM
402

1

C6713

100PF

5%

2

CERM

50V

402

AUD_CONNJ1_SLEEVE2

D

C

=PP3V3_S0_AUDIO

58 57 53

8

APN: 514-0632

OPERATING VOLTAGE 3.3

CRITICAL

J6700

SPDIF-TX-K20

F-RT-TH

MICROPHONE

DETECT FOR PT

SWITCH

LEFT

RIGHT

GROUND

AUDIO

A - VIN
B - VCC
C - GND

POF

SHELL

SHIELD

PINS

AUD_CONNJ1_SLEEVE

MIN_LINE_WIDTH=0.40 MM
MIN_NECK_WIDTH=0.20 MM

AUD_CONNJ1_RING

MIN_LINE_WIDTH=0.20 MM

1

C6700

2

0.1UF

10%
16V
X5R
402

MIN_NECK_WIDTH=0.15 MM

AUD_CONNJ1_TIPDET

AUD_CONNJ1_TIP

MIN_LINE_WIDTH=0.20 MM
MIN_NECK_WIDTH=0.15 MM

AUD_CONNJ1_SLEEVEDET

1

C6701

2.2UF

20%

6.3V

2

CERM
402-LF

CRITICAL

DZ6700

6.8V-100PF

CRITICAL

2

DZ6701

6.8V-100PF

402

1

CRITICAL

2

DZ6702

6.8V-100PF

402

1

402

2

1

2

1

CRITICAL

DZ6703

6.8V-100PF

402

CRITICAL

DZ6704

6.8V-100PF

6
5
2
1
3
4

7
8
9

10
11
12
13

AUD_CONNJ1_SLEEVE2_F

AUD_CONNJ1_SLEEVE_F

MIN_LINE_WIDTH=0.40 MM
MIN_NECK_WIDTH=0.20 MM

AUD_CONNJ1_RING_F

MIN_LINE_WIDTH=0.20 MM
MIN_NECK_WIDTH=0.15 MM

AUD_CONNJ1_TIPDET_F

AUD_CONNJ1_TIP_F

MIN_LINE_WIDTH=0.20 MM
MIN_NECK_WIDTH=0.15 MM

AUD_CONNJ1_SLEEVEDET_F

NOSTUFF

1

C6714

100PF

5%
50V

2

CERM
402

NOSTUFF

1

C6715

2

100PF

CERM

1

5%

50V

2

402

FERR-1000-OHM

FERR-1000-OHM

FERR-220-OHM-2.5A

FERR-220-OHM

FERR-1000-OHM

FERR-220-OHM

0402

L6702

0402

L6701

0603

L6704

0402

L6705

0402

L6706

0402

R6700

10K

5%
1/16W
MF-LF

402

21

21

CRITICAL

21

CRITICAL

21

21

CRITICAL

21

21

GND_CHASSIS_AUDIO_JACK

AUD_SPDIF_OUT

HS_MIC_HI

HS_MIC_LO

AUD_LO_GND

AUD_HPAMP_OUTR

AUD_J1_TIPDET_R

AUD_HPAMP_OUTL

AUD_J1_SLEEVEDET_R

57

AUDIO JACK 2 LINE IN JACK, SPDIF RX

=PP3V3_S0_AUDIO

58 57 53

8

APN: 514-0633

CRITICAL

J6750

SPDIF-RX-K20

F-RT-TH

B

DETECT FOR PT

SWITCH

LEFT

RIGHT

GROUND

5
2
1
3
4

AUD_J2_OPT_OUT

AUD_CONNJ2_SLEEVE

AUD_CONNJ2_TIPDET

AUD_CONNJ2_RING

AUDIO

PINS

6
7
8

9
10
11
12

AUD_CONNJ2_TIP

AUD_CONNJ2_SLEEVEDET

1

C6750

0.1UF

10%
16V

2

X5R
402

A - VDD
B - GND

C - VOUT

OPERATING VOLTAGE 3.3

POF

SHELL

SHIELD

A

R6749

10

5%
1/16W
MF-LF

402

CRITICAL

2

DZ6752

6.8V-100PF

402

CRITICAL

1

DZ6753

6.8V-100PF

GND_CHASSIS_AUDIO_JACK

57

21

L6751

R6761

0

21

5%
1/16W
MF-LF

402

R6762

0

21

5%
1/16W
MF-LF

402

R6764

0

21

5%
1/16W
MF-LF

402

R6766

0

21

5%
1/16W
MF-LF

402

R6768

0

21

5%

1/16W

CRITICAL

2

DZ6754

6.8V-100PF

402

CRITICAL

1

2

DZ6755

402

6.8V-100PF

1

MF-LF

402

2

402

1

NOSTUFF

1

C6761

100PF

5%
50V

2

CERM
402

C6762

100PF

CERM

5%

50V

402

NOSTUFF

1

C6763

100PF

5%
50V

2

CERM
402

NOSTUFF

1

C6764

2

100PF

CERM

1

5%

50V

2

402

AUD_CONNJ2_SLEEVE_F

AUD_CONNJ2_TIPDET_F

AUD_CONNJ2_RING_F

AUD_CONNJ2_TIP_F

AUD_CONNJ2_SLEEVEDET_F

NOSTUFF

1

C6765

100PF

5%
50V

2

CERM
402

FERR-220-OHM

0402

L6752

FERR-1000-OHM

0402

L6754

FERR-1000-OHM

0402

L6756

FERR-1000-OHM

0402

L6758

FERR-220-OHM

0402

GND_CHASSIS_AUDIO_JACK

21

21

21

21

21

AUD_SPDIF_IN

AUD_J2_TIPDET_R

AUD_LI_INR

AUD_LI_INL

XW6701

AUD_J2_COM

57

RETURN FOR HF NOISE

R6701

0

21

5%
1/16W
MF-LF

402

53

IN

58

OUT

58

OUT

55

OUT

55

BI

58

OUT

96 56

55

BI

58

OUT

53

OUT

58

OUT

54

BI

54

BI

SM

21

AUD_LI_GND

96 56

96 56

96 56

96 56

96 56

96 56

96 56

96 56

96 56

54

SPKRAMP_L2_OUT_P

7

IN

SPKRAMP_L2_OUT_N

7

IN

SPKRAMP_L1_OUT_P

7

IN

SPKRAMP_L1_OUT_N

7

IN

SPKRAMP_R2_OUT_P

7

IN

SPKRAMP_R2_OUT_N

7

IN

SPKRAMP_R1_OUT_P

7

IN

SPKRAMP_R1_OUT_N

7

IN

SPKRAMP_LFE_OUT_P

7

IN

SPKRAMP_LFE_OUT_N

7

IN

58

58

58

7

OUT

7

OUT

7

OUT

NOSTUFF

C6785

BI_MIC_LO
BI_MIC_SHIELD
BI_MIC_HI

100PF

50V

CERM

402

MIC CONNECTOR

APN: 518S0520

SPEAKER CONNECTORS

APN: 518S0521

NOSTUFF

1

1

C6782

100PF

5%
50V

2

2

CERM
402

APN: 518S0672

NOSTUFF

1

C6787

100PF

5%

50V

2

CERM

402

NOSTUFF

C6786

100PF

5%
50V
CERM
402

SYNC_MASTER=AUDIO_K20

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

APPLE INC.

5%

NOSTUFF

C6781

100PF

1

2

CERM

5%

50V

402

1

2

NOSTUFF

1

C6783

100PF

5%

50V

2

CERM

402

NOSTUFF

1

C6788

100PF

5%
50V

2

CERM
402

NOSTUFF

C6789

100PF

AUDIO: JACKS

SIZE

D

SCALE

NOSTUFF

1

C6784

100PF

5%
50V

2

CERM
402

1

5%

50V

2

CERM

402

DRAWING NUMBER

NONE

78171-0003

78171-0004

78171-6006

NOSTUFF

1

C6790

100PF

5%
50V

2

CERM
402

051-8071

SHT

57 98

CRITICAL

J6780

M-RT-SM

4

1

2

3

5

CRITICAL

J6781

M-RT-SM

5

1

2

3

4

6

CRITICAL

J6782

M-RT-SM

7

1

2

3

4

5

6

8

SYNC_DATE=09/29/2008

REV.

OF

D

C

B

A

B

8

76

5

4

3

2

1

87

www.vinafix.vn

CODEC OUTPUT SIGNAL PATHS

PIN COMPLEX
0X14 (20,D) 0X14 (20,D)
0X1A (26,C)
0X18 (24,B)
0X17 (23,H)
0x1E (SPDIF OUT)

VREF

VREF_A (50%)

VREF_F (100%)
MIKEY

PORT D DETECT (Line-out)

AUD_OUTJACK_INSERT_L

3

4

1

1

2

R6803

100K

5%
1/16W
MF-LF

402

C6801

0.1UF

20%
CERM

21

SSM6N15FEAPE

MIXER(OUTPUT)
0X0C (12)
0X0F (15)
0X0D (13)
0X0E (14)
N/A

PIN COMPLEX
0X15 (21,A)
0x1F (SPDIF IN)
0X19 (25,F)
0X1B (27,E)

Q6800

SSM6N15FEAPE

SOT563

5

10V
402

AUD_J1_SLEEVEDET_INV

Q6800

SOT563

2

D

SG

6

D

SG

FUNCTION
HP/LINE OUT
SPEAKERS L1/R1
SPEAKERS L2/R2
SPEAKER LFE
SPDIF OUT

D

C

CODEC INPUT SIGNAL PATHS

FUNCTION
LINE IN
SPDIF IN
MIC
HEADSET MIC

53

58 53

58 57

58 56 55 54 53

58 57

58 56 55 54 53

VOLUME
0X0C (12)
0X0F (15)
0X0D (13)
0X0E (14)
N/A

MIXER(INPUT)
0X23 (35)
N/A
0X24 (36)
0X24 (36)

AUD_SENSE_B

OUT

AUD_SENSE_A

OUT

PP3V3_S0_AUDIO_F

58

AUD_J1_TIPDET_R

IN

GND_AUDIO_CODEC

PP3V3_S0_AUDIO_F

58

AUD_J1_SLEEVEDET_R

IN

GND_AUDIO_CODEC

CONVERTER
0X02 (2)
0X05 (5)
0X03 (3)
0X04 (4)
0X06 (6)

CONVERTER
0X08 (8)
0X0A (10)
0X07 (7)
0X07 (7)

1

R6801

220K

5%
1/16W
MF-LF
402

2

R6802

47K

5%
1/16W
MF-LF

402

1

R6804

220K

5%
1/16W
MF-LF
402

2

21

AUD_J1_DET_RC

1

C6802

0.01UF

10%
16V

2

CERM
402

6

Q6801

SSM6N15FEAPE

SOT563

58 57

MUTE CONTROL

GPIO_0
VREF_B (100%)
VREF_B (100%)
VREF_B (100%)
N/A

DET ASSIGNMENT
0X15 (21,A)
N/AN/A
N/A
MIKEY

1

R6806

5.11K

1%
1/16W
MF-LF
402

2

AUD_PORTD_DET_L

3

D

5

SG

4

AUD_J1_SLEEVEDET_R

DET ASSIGNMENT

N/A
N/A
N/A
0X16 (22,G)

PORT G DETECT

(SPDIF DELEGATE)

NC

Q6801

SSM6N15FEAPE

SOT563

2

5

1

R6805

10K

1%
1/16W
MF-LF
402

2

AUD_PORTG_DET_L

6

D

SG

1

44

IN

44

BI

21

OUT

9

19

IN

NC

58 57 53

=I2C_MIKEY_SCL

=I2C_MIKEY_SDA

AUD_I2C_INT_L

AUD_IPHS_SWITCH_EN

58 56 55 54 53

53

53

58 56 55 54 53

4

PP3V3_MIKEY_ANALOG

53

=PP3V3_S0_AUDIO

8

R6890

0

21

5%
1/16W
MF-LF

402

R6892

0

21

5%
1/16W
MF-LF

402

GND_AUDIO_CODEC

AUD_BI_PORT_E_L

OUT

MAKE_BASE=TRUE

AUD_BI_PORT_E_R

OUT

GND_AUDIO_CODEC

R6891

0

5%
1/16W
MF-LF

402

R6893

0

5%
1/16W
MF-LF

402

L6882

FERR-1000-OHM

NOSTUFF

L6880

FERR-1000-OHM

21

21

1

R6880

100K

5%
1/16W
MF-LF
402

2

NOSTUFF

1

R6884

0

5%
1/16W
MF-LF
402

2

XW6800

0402

0402

CRITICAL

C6883

SM

53

21

21

CRITICAL

C6880

10UF

6.3V

0.1UF

21

10%
16V

X7R-CERM

402

21

AUD_VREF_PORT_F

IN

LINE_IN AMP SHUTDOWN CONTROL

PP4V6_AUDIO_ANALOG

54 53

PORT A DETECT (Line-in)

AUD_SENSE_A

58 53

OUT

1

1

C6811

0.1UF

20%

2

CERM

PP3V3_S0_AUDIO_F

1

C6800

0.1UF

10%
16V

2

X5R
402

R6813

39.2K

1/16W
MF-LF

Q6802

SSM3K15FV

SOD-VESM-HF

10V
402

1%

402

2

AUD_INJACK_INSERT_L

D

1

GS

NC

3

2

58

AUD_J1_TIPDET_R

58 57

IN

Q6803

SSM6N15FEAPE

SOT563

B

58 56 55 54 53

A

58 56 55 54 53

PP3V3_S0_AUDIO_F

58

AUD_J2_TIPDET_R

57

IN

GND_AUDIO_CODEC

PLACE L6800/C6800 CLOSE TO Q6800/01/02

=PP3V3_S0_AUDIO

58 57 53

8

GND_AUDIO_CODEC

1

R6811

270K

5%
1/16W
MF-LF
402

2

R6812

47K

21

5%
1/16W
MF-LF

402

L6800

FERR-1000-OHM

0402

AUD_J2_DET_RC

21

5

53
58 57

TPDT_DEBOUNCE

1

R6814

100K

5%
1/16W
MF-LF
402

2

3

D

SG

4

=PP3V3_S0_AUDIO

8

R6860

0

21

5%
1/16W
MF-LF

402

AUD_LIN_SHUTDOWN

NOSTUFF

1

C6860

0.1UF

10%
16V

2

X5R
402

SSM6N15FEAPE

NOSTUFF

1

R6861

100K

5%
1/16W
MF-LF
402

2

SOT563

2

TPDT_DEBOUNCE

1

C6861

0.1UF

10%
16V

2

X5R
402

D

SG

Q6803

AUD_IP_PERPH_DET_R

1

R6815

100K

5%
1/16W
MF-LF
402

2

AUD_LIFILT_SHUTDOWN_L

6

1

TIPDET DEBOUNCE CIRCUIT

TPDT_DEBOUNCE

4
VDD

U6860

MR*

SC-70-1

GND

RST*

21

CRITICAL

TPS3801E18DCK

35

AUD_IP_PERPH_DET_DB

58 56 55 54 53

54

OUT

GND_AUDIO_CODEC

AUD_BI_PORT_F_L

53

OUT

AUD_BI_PORT_F_R

53

OUT

58 56 55 54 53

MAKE_BASE=TRUE

TPDT_BYPASS

R6865

0

21

5%
1/16W
MF-LF

402

TPDT_DEBOUNCE

R6862

0

21

AUD_IP_PERIPHERAL_DET_R

5%
1/16W
MF-LF

402

3

MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.10MM
VOLTAGE=3.3V

PP3V3_S0_HS_RX

1

1

20%

2

X5R
603

GND_AUDIO_CODEC

GND_CHASSIS_AUDIO_MIC

1

R6851

0

5%
1/16W
MF-LF
402

2

HS_SCL

HS_SDA

HS_INT_L

HS_RST_L

1

R6863

100K

5%
1/16W
MF-LF
402

2

C6886

0.001UF

10%
50V

2

CERM
402

1

R6883

100K

5%
1/16W
MF-LF
402

2

R6864

0

5%
1/16W
MF-LF

402

CRITICAL

3

AVDD

U6800

CD3275

DRC

6

SCL

MICBIAS

5

7

8

SDA

INT*

ENABLE

GND THM

4

9

DETECT

BYPASS

11

HS_MIC_HI_R

1

C6884

15PF

5%
50V

2

CERM
402

PORT F (BUILT-IN MIC)

R6855

2.2K

21

BI_MIC_BIAS

5%
1/16W
MF-LF

402

CRITICAL

C6850

0.1UF

21

10%

25V

X5R

402

XW6850

SM

21

XW6851

SM

21

21

AUD_IP_PERIPHERAL_DET

1

2

10

CRITICAL

1

C6853

10UF

20%
16V

2

TANT-POLY
2012-LLP

BI_MIC_HI_F

1

R6852

100K

5%
1/16W
MF-LF
402

2

BI_MIC_LO_F

HS_MIC_BIAS

HS_SW_DET

HS_RX_BP

21

KEEP DET TRACE AS SHORT AS POSS

1

C6881

0.01UF

10%
25V

2

X7R
402

1

C6885

0.0082UF

10%
25V

2

X7R
402

C6852

50V
402

OUT

R6885

2.2K

1/16W
MF-LF

R6850

2.2K

5%
1/16W
MF-LF

402

1

15PF

5%

2

CERM

SYNC_MASTER=AUDIO_K20

17

APPLE INC.

CRITICAL

1

C6882

4.7UF

20%

6.3V

2

TANT
603-HF

5%

402

21

1

2

1

C6887

100PF

5%
50V

2

CERM
402

21

C6851

0.001UF

10%
CERM

50V
402

1

2

L6850

FERR-1000-OHM

0402

L6851

FERR-1000-OHM

0402

R6881

1K

5%
1/16W
MF-LF
402

21

21

BI_MIC_HI

BI_MIC_LO

1

2

BI_MIC_SHIELD

AUDIO: JACK TRANSLATORS

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

051-8071

SHT

58 98

R6882

2.2K

5%
1/16W
MF-LF
402

HS_MIC_HI

HS_MIC_LO

SYNC_DATE=09/29/2008

IN

IN

7

IN

7

IN

7

IN

REV.

OF

D

C

57

57

B

57

57

57

A

B

8

76

5

4

3

2

1

87

www.vinafix.vn

MagSafe DC Power Jack

6

5

4

3

21

CRITICAL

J6900

=PP18V5_DCIN_CONN

59

8

78048-0573

M-RT-SM

PWR

PWR

GND

GND

SIG

PP18V5_DCIN_FUSE

7

MIN_LINE_WIDTH=1mm

1

2

3

4

5

MIN_NECK_WIDTH=0.20mm
VOLTAGE=18.5V

1

ADAPTER_SENSE

7

R6905

47

21

1%

1/3W

MF

805

3

SC-75

RCLAMP2402B

D6900

2

CRITICAL

PPDCIN_S5_P3V42G3H

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.3 mm
VOLTAGE=18.5V

=PPVBAT_G3H_P3V42G3H

8

1

C6905

0.01UF

2

20%
50V
CERM
603

D

The chassis ground will otherwise float and can
send transients onto ADAPTER_SENSE when AC is

C

connected.

B

XW6953

SHORT-1206

21

XW6952

SHORT-1206

XW6951

SHORT-1206

XW6950

SHORT-1206

402
CERM
50V
10%

0.001UF

C6951

21

21

21

PPVBAT_G3H_CONN

GND_BATT_CHGND

60 59

9

CRITICAL

J6950

GS731301047E7H

M-RT-SM

14

1
2
3
4
5
6
7
8
9

A

10
11
12
13

15

Battery Connector

PPVBAT_G3H_CONN_F

7

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=8.6V

1

C6950

0.001UF

10%
50V

2

CERM
402

42 41

9

60 59

1

2

3

=SMBUS_BATT_SCL
=SMBUS_BATT_SDA
SMC_BS_ALRT_L

CRITICAL

D6950

RCLAMP2402B

SC-75

GND_BATT_CHGND

59 44

59 44

7

2

1

518S0694

CRITICAL

F6905

6AMP-24V

21

1206-1

PLACEMENT_NOTE=Place near L6900

<Ra>

1

R6913

100K

5%
1/16W
MF-LF

402

2

ONEWIRE_DCIN_DIV

<Vth>

<Rb>

1

R6914

100K

1/16W
MF-LF

ONEWIRE_ESD

5%

402

2

Vth = Vdcin * (Rb / (Ra + Rb))
Vth = Vdcin / 2

1

R6920

24.3K

1%
1/16W
MF-LF
402

2

CRITICAL

D6905

BAT30CWFILM

SOT-323

1

2

BIL Connector

CRITICAL

J6995

FF18-5A-R11AD-B-3H

F-RT-SM

1

2

3

4

5

518S0720

1-Wire OverVoltage Protection

C6915

0.1UF

10%
25V
X5R
402

3

PPVIN_G3H_P3V42G3H
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.3 mm
VOLTAGE=18.5V

=PP3V42_G3H_BATT
=SMBUS_BATT_SDA
=SMBUS_BATT_SCL

SMC_BIL_BUTTON_DB_L

1

C6954

0.001UF

10%
50V

2

CERM

402

MIN_LINE_WIDTH=0.25mm
MIN_NECK_WIDTH=0.20mm

R6915

270K

1/16W
MF-LF

270K

5%
1/16W
MF-LF

402

5%

402

1

2

VOLTAGE=18.5V

1

CRITICAL

2

1

2

1

3

If ADAPTER_SENSE > Vth
then turn off FET

CRITICAL

U6915

5

LM397

SOT23-5-HF

V+

4

ONEWIRE_OVERVOLT

V-

2

R6916

Voltage divider from DCIN ensures Q6901
Vgs is met when SYS_ONEWIRE is high or low.
Q6920 used as bilateral switch to ensure
SYS_ONEWIRE doesn’t drive unpowered U6990

3.425V "G3Hot" Supply

Supply needs to guarantee 3.31V delivered to SMC VRef generator

6

U6990

LT3470A

DFN

CRITICAL

GND

5

C6955

0.001UF

10%
50V
CERM
402

BOOST

THRM

8

BI

BI

OUT

3

BIAS

PAD

48

SW

2

1

FB

9

59 44

59 44

42

7

C6953

47PF

1

C6990

10UF

10%
25V

2

X5R
805

VIN

SHDN*

7

NC

NC

1

C6952

47PF

1

5%

50V

CERM

402

2

2

1

5%

50V

2

CERM

402

Q6910 restricts system load to 10K-70K window until
adapter detects system and enables 16.5V output.

PP18V5_DCIN_ONEWIRE

ONEWIRE_EN

3

D

Q6915

SSM6N15FEAPE

SOT563

5

SG

4

CRITICAL

Q6920

SSM6N15FEAPE

SOT563

D

3

P3V42G3H_BOOST

1

C6994

0.22UF

20%

6.3V

2

X5R

P3V42G3H_SW

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
SWITCH_NODE=TRUE

P3V42G3H_FB

402

Vout = 1.25V * (1 + Ra / Rb)

R6917

R6918

270K

5%
1/16W
MF-LF

402

1

C6917

0.001UF

10%
50V

2

CERM
402

5

SG

SYS_ONEWIRE_BILAT

4

CRITICAL

L6995

33UH

CDPH4D19FHF-SM

C6995

22pF

50V

CERM

402

6

1

270K

5%
1/16W
MF-LF

402

2

Vgs = 11.750V @ 20V DCIN

1

Vgs = 7.63V @ 13V DCIN

2

21

<Ra>

1

R6995

1

348K

1%

5%

1/16W
MF-LF

2

402

2

<Rb>

1

R6996

200K

1%
1/16W
MF-LF
402

2

CRITICAL

Q6910

BSS84V

SOT-563

Vgs(max) = 20V

DS

G

2

ONEWIRE_PWR_EN_L_DIV

ONEWIRE_PWR_EN_L

6

D

SG

1

2

SG

1

=PP3V42_G3H_REG

Vout = 3.425

200mA max output

(Switcher limit)

1

C6999

22UF

20%

6.3V

2

X5R-CERM
603

1

Q6915

SSM6N15FEAPE

SOT563

2

CRITICAL

Q6920

SSM6N15FEAPE

SOT563

SMC_BC_ACOK_RC

D

SYS_ONEWIRE

6

SYNC_MASTER=RXU_K20

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

APPLE INC.

R6911

470K

1/16W
MF-LF

R6912

330K

1/16W
MF-LF

C6910

0.001UF

8

CERM

1

5%

402

2

1

5%

402

2

1

10%
50V

2

402

=PP18V5_DCIN_CONN

R6910

1K

21

SMC_BC_ACOK

5%
1/16W
MF-LF

402

42 41

BI

8

DC-In & Battery Connectors

SYNC_DATE=05/21/2008

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

DRAWING NUMBER

SIZE

D

SCALE

NONE

051-8071

SHT

59 98

59

IN

D

42 41

C

B

A

REV.

B

OF

8

76

5

4

3

2

1

87

www.vinafix.vn

6

5

4

3

21

D

C

B

A

1

R7010

30.1K

1%
1/16W
MF-LF

402

2

1

R7011

9.31K

1%
1/16W
MF-LF

402

2

PART NUMBER

353S1938

353S1832

=PP3V42_G3H_CHGR

8

60

ACIN pin threshold
is 3.2V, +/- 50mV

Divider sets ACIN
threshold at 13.07V

Input impedance of ~40K meets
sparkitecture requirements

1

R7015

56.2K

1%
1/16W
MF-LF
402

2

CHGR_VCOMP_R

C7015

0.001UF

10%
50V

CERM

402

R7016

3.01K

1%
1/16W
MF-LF

402

CHGR_VNEG_R

1

C7016

470PF

10%
50V

2

CERM
402

1

C7042

0.033UF

10%
16V

2

X5R
402

QTY

1

1

DESCRIPTION

IC,ISL6258,BAT CHARGER,28P,4X4,QFN,L

IC,ISL6258A,BAT CHARGER,4X4MM,QFN28

FROM ADAPTER

=PPDCIN_S5_CHGR

8

=SMBUS_CHGR_SCL

44

IN

=SMBUS_CHGR_SDA

44

BI

VREF = 3.2V, < 300uA

1

2

1

2

C7002

CHGR_ACIN

CHGR_ICOMP
CHGR_VCOMP
CHGR_VNEG
CHGR_CSO_P

94

CHGR_CSO_N

94

SIGNAL_MODEL=EMPTY

1

C7050

0.1uF

10%
16V

2

X5R
402

1

1UF

10%
10V

2

X5R
402

C7000

1UF

10%
10V
X5R
402

REFERENCE DES

PP5V1_CHGR_VDD

60

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5.1V

30mA max load

1

1

C7011

0.01UF

10%
16V

2

2

CERM
402

U7000

U7000

Inrush Limiter

1

R7060

470K

1%
1/16W
MF-LF
402

2

CHGR_AGATE_DIV

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.3 mm

1

R7061

332K

1%
1/16W
MF-LF
402

2

CRITICAL

D7005

BAT30CWFILM

SOT-323

1

2

12

VHST

11

SCL

10

SDA

4

VREF

NC

3

ACIN

5

ICOMP

7

VCOMP

8

VNEG

18

CSOP

17

CSON

CRITICAL

CRITICAL

CRITICAL

3

19

VDD

29

C7060

0.1UF

R7001

4.7

5%
1/16W
MF-LF

402

CRITICAL

U7000

QFN

OMIT

20V/V
32V/V

THRM_PAD

26

XW7000

1

10%
25V

2

X5R
402

4

(CHGR_AGATE)

(CHGR_DCIN)

21

PP5V1_CHGR_VDDP

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5.1V

20

VDDP

AGATE

CSIP
CSIN

BGATE

DCIN

ISL6258A

BOOT
UGATE
PHASE

LGATE

TRKL*

(OD)

AMON

BMON

ACOK

(OD)

AGND

PGND

6

22

SM

21

C7005

0.1UF

BOM OPTION

ISL6258

ISL6258A

321

GATE

S1

S3

S2

D2

D1D3D4

5

1

CHGR_AGATE

28

CHGR_CSI_P

94

27

CHGR_CSI_N

94

CHGR_BGATE

16

2

CHGR_DCIN

25

CHGR_BOOT

24

CHGR_UGATE

23

CHGR_PHASE

21

CHGR_LGATE

13

TP_CHGR_TRKL

9

CHGR_AMON

15

CHGR_BMON

14

=CHGR_ACOK

(CHGR_CSO_P)
(CHGR_CSO_N)

(PPVBAT_G3H_CHGR_R)

1

10%
25V

2

X5R
402

GND_CHGR_AGND

60

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V

2S Battery Default

3S Battery Default

CRITICAL

Q7060

HAT1128R01

SOI

876

PPDCIN_S5_INRUSH

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=18.5V

C7001

1UF

10%
10V
X5R
402

1

2

CRITICAL

Q7065

HAT1128R01

45

OUT

60
45

OUT

42

OUT

Max Current = 8.5A
(L7030 limit)
f = 400 kHz

1

C7026

0.001UF

2

SOI

876

SIGNAL_MODEL=EMPTY

1

C7020

0.047UF

10%
10V

2

CERM
402

1

2

4

10%
50V
CERM
402

Reverse-Current Protection

PPDCIN_S5_CHGR_R

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm

321

S3

S2

D3

D4

C7022

0.1UF

C7035

0.22UF

10%
10V
CERM
402

4

S1

D2

10%
25V
X5R
402

VOLTAGE=18.5V

CHGR_SGATE_DIV

GATE

MIN_LINE_WIDTH=0.3 mm

4

MIN_NECK_WIDTH=0.3 mm

D1

5

1

1

C7021

0.1UF

10%
25V

2

2

X5R
402

GND_CHGR_AGND

60

5

321

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE

5

CRITICAL

Q7036

RJK0305DPB

LFPAK-HF

152S0542

321

R7051

R7021

R7022

CRITICAL

152S0542

1/16W
MF-LF

10

21

5%
1/16W
MF-LF

402

10

21

5%
1/16W
MF-LF

402

Q7031

RJK0305DPB

LFPAK-HF

4

10

21

5%

402

4

R7065

100K

1/16W
MF-LF

R7066

1/16W
MF-LF

5

R7052

62K

96

96

1

5%

402

2

1

5%

402

2

CHGR_SGATE

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.25 mm

CHGR_CSI_R_P

CHGR_CSI_R_N

PPDCIN_S5_FET_CHGR

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=18.5V

5

CRITICAL

Q7030

RJK0305DPB

LFPAK-HF

152S0542

321

2.2UH-20A-5.5M-OHM

CRITICAL

Q7035

RJK0305DPB

LFPAK-HF

152S0542

CHGR_PHASE_RC

321

10

96

21

CHGR_CSO_R_N

45

5%
1/16W
MF-LF

402

1

C7070

0.1uF

10%
16V

2

X5R

U7070

5

TL331

SOT23-5

VCC

4

GND

2

CRITICAL

1

R7020

0.02

0.5%
1W
MF
0612

432

1

2

CRITICAL

1%
1W
MF

1

2

C7033

1UF

10%
25V
X5R
603-1

L7031

SM

12

34

CRITICAL

C7031

22UF

20%
25V
POLY-TANT
CASE-D2-SM

21

PPVBAT_G3H_CHGR_R

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=12.6V

CRITICAL

L7030

SM

NO STUFF

R7099

10

5%
1/10W
MF-LF

603

NO STUFF

1

2

CHGR_CSO_R_P

45 96

1

2

C7099

0.001UF

10%
50V
X7R
402

CRITICAL

1

C7030

22UF

20%
25V

2

POLY-TANT
CASE-D2-SM

1

C7032

1UF

10%
25V

2

X5R
603-1

2.2UH-20A-5.5M-OHM

21

PPVBAT_G3H_CHGR_REG_L

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm

VOLTAGE=12.6V

CRITICAL

R7050

0.005

0612

C7055

M99 differences from last sync on 12/02/07 to T18 MLB:

1. L7030 changed from T18 MLB inductor to 152S0542.

2. Added Q7056, C7058,R7055,R7056..

3. U7000 Thermal Pad is now connected to GND, not through XW.

4. Q7060 and Q7065 changed to 376S0667.

5. Q7055 and Q7056 changed to 376S0666.

1

3

1

2

1

C7034

0.001UF

10%
50V

2

X7R
402

PPVBAT_G3H_CHGR_REG

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=12.6V

1

1UF

10%
25V

2

X5R

603-1

402

CRITICAL

C7036

22UF

20%
25V
POLY-TANT
CASE-D2-SM

1

2

SGATE_P0V1_VREF

CRITICAL

1

C7037

22UF

20%
25V

2

POLY-TANT
CASE-D2-SM

1

C7057

0.01uF

10%
16V

2

CERM

402

C7056

0.1UF

10%
16V
X5R
402

R7070

57.6K

1/16W
MF-LF

402

R7071

1.82K

1/16W
MF-LF

402

CRITICAL

C7043

33UF

POLY-TANT

CASED2E-SM

3

2

1

1%

1%

20%
16V

3

2

1

1

2

1

2

4

3

D

SG

4

CRITICAL

1

2

CRITICAL

HAT1127H

LFPAK-SM

Q7057

S

G

CRITICAL

HAT1127H

LFPAK-SM

Q7055

S

G

4

Q7074

SSM6N15FEAPE

SOT563

C7040

33UF

POLY-TANT

CASED2E-SM

D

D

5

AMON_CLAMP

1

20%
16V

2

5

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=12.6V

5

PPVBAT_G3H_FET

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=12.6V

=PP3V42_G3H_CHGR

1

R7074

1M

5%
1/16W
MF-LF
402

2

CHGR_AMON

R7075 clamps CHGR_AMON when charger is
not powered to counter TL331 bias current.

6

D

SG

1

45 60

Q7074

SSM6N15FEAPE

SOT563

2

PP5V1_CHGR_VDD

TO SYSTEM

1

CRITICAL

HAT1127H

LFPAK-SM

CRITICAL

F7041

8AMP-24V

1206

2

1

C7041

0.001UF

2

10%
50V
X7R
402

1

CRITICAL

F7040

8AMP-24V

1206

2

Q7058

D

5

S

G

4

CRITICAL

HAT1127H

LFPAK-SM

Q7056

5

D

S

G

4

PBus Supply & Battery Charger

SYNC_MASTER=RXU_K20

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

8

=PPBUS_G3H

321

321

1

2

GND_BATT_CHGND

9

59

DRAWING NUMBER

D

NONE

60

60

8

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=12.6V

C7058

1UF

10%
10V
X5R

PPVBAT_G3H_CONN

402-1

BATT_POS_GATE

051-8071

SHT

59

R7056

21

1M

5%
MF-LF

402

1/16W

R7057

21

20K

5%
MF-LF

402

1/16W

SYNC_DATE=05/21/2008

REV.

B

OF

9860

D

C

B

A

8

76

5

4

3

2

1

87

www.vinafix.vn

=PPVIN_S5_CPU_IMVP

8

R7120

10

21

PPVIN_S5_IMVP6_VIN

MIN_LINE_WIDTH=0.25 MM

1%

402

10

1%

402

10

1%

402

0

5%

402

1

2

MIN_NECK_WIDTH=0.2 MM
VOLTAGE=12.6V

21

PP5V_S0_IMVP6_VDD

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V

21

PP3V3_S0_IMVP6_3V3

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

1

R7199

68

5%
1/16W
MF-LF
402

2

21

88 14 10

88

88

88

88

88

88

88

9

9

9

9

9

9

9

9

10

45

IN

IN

IN

IN

IN

IN

IN

IN

88

IN

OUT

C7130

IMVP6_VID<6>
IMVP6_VID<5>
IMVP6_VID<4>
IMVP6_VID<3>
IMVP6_VID<2>
IMVP6_VID<1>
IMVP6_VID<0>

CPU_DPRSTP_L
IMVP_DPRSLPVR
CPU_PSI_L
IMVP6_IMON

C7126

0.1uF

10%
16V
X5R
402

1/16W
MF-LF

=PP5V_S0_CPU_IMVP

8

R7112

D

=PP3V3_S0_IMVP

8

13 12 11 10

C

=PP1V05_S0_CPU

8 6

88 21

IN

88 42 14 10

OUT

LAYOUT NOTE:

Place R7126 in hot

spot of reg circuit.

CRITICAL

PM_DPRSLPVR

CPU_PROCHOT_L

R7126

470K

402

(IMVP6_NTC)

1

2

R7119

499

1/16W
MF-LF

1%

402

21

C7110

0.01uF

R7121

1/16W
MF-LF

R7198

10%
16V

CERM

402

1/16W
MF-LF

1/16W
MF-LF

IMVP6_NTC_R

VR_PWRGD_CLKEN_L

9

OUT

61

IN

25

OUT

IMVP_VR_ON_R
VR_PWRGOOD_DELAY
IMVP6_VR_TT_L
IMVP6_NTC

(GND_IMVP6_SGND)
IMVP6_SOFT

61

IMVP6_RBIAS

61

(GND_IMVP6_SGND)
IMVP6_VDIFF

61

IMVP6_FB2

61

IMVP6_FB

61

IMVP6_COMP

61

IMVP6_VW

61

C7105

0.015UF

1

10%
16V

2

X7R
402

1

R7108

147K

1%
1/16W
MF-LF
402

2

1

C7106

0.001UF

10%
50V

2

CERM
402

IMVP6_VDIFF_RC

R7111

1/16W
MF-LF

255

1%

402

R7127

4.02K

1/16W
MF-LF

1

2

402

1%

1

2

1

2

R7113

R7109

1K

1%
1/16W
MF-LF
402

1/16W
MF-LF

1

1K

1%

402

2

(IMVP6_FB)

B

1

C7114

470PF

10%
50V

2

CERM
402

IMVP6_COMP_RC

C7113

R7114

97.6K

1/16W
MF-LF

390PF

1%

402

1

10%
50V

2

CERM

402

(IMVP6_VW)

1

2

C7107

0.001UF

1

10%
50V

2

CERM

402

(IMVP6_COMP)

R7160

0

IMVP_VR_ON

41 61

IMVP6_OCSET

A

61

IMVP6_VO

61

IMVP6_DROOP

61

IMVP6_DFB

61

IMVP6_SOFT

61

IMVP6_RBIAS

61

IMVP6_VDIFF

61

IMVP6_FB2

61

IMVP6_FB

61

IMVP6_COMP

61

IMVP6_VW

61

21

IMVP_VR_ON_R

5%
1/16W
MF-LF

402

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.25 MM

C7196

0.1UF

1UF

10%
10V
X5R
402

1

2

1

R7110

6.81K

1%
1/16W
MF-LF
402

2

10%
16V
X5R
402

1

2

88 61

1

2

61

61

61

61

61

61

61

6

1

R7197

10K

5%
1/16W
MF-LF
402

2

GND_IMVP6_SGND

MIN_LINE_WIDTH=0.50 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=0V

IMVP6_PHASE1
IMVP6_BOOT1
IMVP6_UGATE1
IMVP6_LGATE1
IMVP6_ISEN1
IMVP6_VSUM1
IMVP6_VO1
IMVP6_VSEN_P

DPRSLPVR

1

C7135

4.7UF

20%

6.3V

2

X5R-CERM
402

20

22

CRITICAL

U7100

QFN

GND

XW7100

SM

31

PVCC

BOOT1

BOOT2

UGATE1

PHASE1

LGATE1

ISL9504BCRZ

PGND1

ISEN1

UGATE2

PHASE2

LGATE2

PGND2

ISEN2

VSUM

OCSET

DROOP

VSEN

TPAD

21

21

36

IMVP6_BOOT1

61

26

IMVP6_BOOT2

61

35

IMVP6_UGATE1

61

34

IMVP6_PHASE1

61

32

IMVP6_LGATE1

61

33

(GND)

24

IMVP6_ISEN1

61

27

IMVP6_UGATE2

61

28

IMVP6_PHASE2

61

30

IMVP6_LGATE2

61

29

(GND)

23

IMVP6_ISEN2

61

19

IMVP6_VSUM

8

61

IMVP6_OCSET

18

IMVP6_VO

VO

16

IMVP6_DROOP

17

IMVP6_DFB

61

DFB

14

15

RTN

49

1

C7121

0.22UF

20%

6.3V
2

X5R
402

MIN_NECK_WIDTH=0.2 MM

MIN_NECK_WIDTH=0.2 MM

MIN_NECK_WIDTH=0.25 MMMIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.2 MM

VIN VDD

43

VID6

42

VID5

41

VID4

40

VID3

39

VID2

38

VID1

37

VID0

46

DPRSTP*

45

DPRSLPVR

2

PSI*

3

IMON

(PGD_IN)

(ISL9504A)

48

3V3

47

CLK_EN*

44

VR_ON

1

PGOOD

5

VR_TT*

6

NTC

7

SOFT

4

RBIAS

13

VDIFF

12

FB2

11

FB

10

COMP

9

VW

25

NC

MIN_LINE_WIDTH=1.5 MM MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.25 MM

5

C7108

0.001UF

DPRSTP*

0

0

1

1 1-Phase

C7131

0.001UF

SIGNAL_MODEL=EMPTY

C7143

0.001UF

1

1

0

0

R7189

0

21

5%
1/10W
MF-LF

603

R7117

3.92K

1%
1/16W
MF-LF

1

10%
50V

2

CERM

402

88 61

88 61

1

10%
50V

2

CERM

402

402

1

R7118

1K

1%
1/16W
MF-LF
402

2

1

C7134

0.068UF

10%
10V

2

CERM
402

Place R7131 Between L7100,L7101 and CPU

IMVP6_VSEN_P

IMVP6_VSEN_N

1

C7132

0.001UF

10%
50V

2

CERM
402

I849 I848

Operation

1

0

1

2-Phase

1-Phase

1-Phase

0 DCM

R7188

0

21

5%

1/10W

IMVP6_BOOT2_R

MF-LF

603

OUT

OUT

21

1

C7129

180pF

5%
50V

2

CERM
402

1

2

1

C7128

0.22UF

10%

6.3V

2

CERM-X5R

402

R7122

1/16W
MF-LF

402

IMVP6_PHASE2

61

IMVP6_BOOT2

61

IMVP6_UGATE2

61

IMVP6_LGATE2

61

IMVP6_ISEN2

61

IMVP6_VSUM2

61

IMVP6_VO2

61

IMVP6_VSEN_N

88 61

1

10%
50V

2

X7R
402

IMVP6_BOOT1_R

C7127

0.22UF

20%
25V
X5R
603

61

61

R7115

11K

1%
1/16W
MF-LF
402

0

21

5%

4

These caps are for Q7100

CRITICAL

C7117

68UF

16V

D3L

1

2

1

R7116

13.3K

1%
1/16W
MF-LF
402

2

(IMVP6_VO)

IMVP6_VO_R

1

CRITICAL

R7131

10KOHM-5%

0603-LF

2

R7123

1/16W
MF-LF

402

1

1

C7109

1UF

20%

POLY-TANT

10%
25V

2

2

X5R
603-1

ModePSI*

CCM

CCM

DCM

1

C7115

0.22UF

20%
25V

2

X5R
603

NO STUFF

1

C7116

0.001uF

10%
50V

2

CERM

402

1

R7130

2.61K

1%
1/16W
MF-LF

402

2

CPU_VCCSENSE_P

0

21

CPU_VCCSENSE_N

5%

MIN_LINE_WIDTH=1.5 MM

MIN_LINE_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.25 MM

1

C7118

1UF

10%
25V

2

X5R
603-1

4

4

4

88 11

IN

88 11

IN

MIN_NECK_WIDTH=0.2 MM

MIN_NECK_WIDTH=0.2 MM

MIN_NECK_WIDTH=0.2 MM

MIN_NECK_WIDTH=0.2 MM

3

CRITICAL

C7155

33UF

20%

16V

POLY-TANT

CASED2E-SM

5

CRITICAL

Q7100

RJK0305DPB

LFPAK-HF

321

5

CRITICAL

Q7101

RJK0328DPB

LFPAK-HF

321

5

4

321

5

CRITICAL

Q7103

RJK0328DPB

LFPAK-HF

321

1

2

(IMVP6_PHASE1)

(IMVP6_ISEN1)

CRITICAL

Q7102

RJK0305DPB

LFPAK-HF

(IMVP6_PHASE2)

(IMVP6_ISEN2)

(IMVP6_VSUM)

(IMVP6_VO)

CRITICAL

C7153

33UF

20%

16V

POLY-TANT

CASED2E-SM

1

2

21

These caps are for Q7102

C7152

0.001UF

0.36UH-30A-1.05MOHM

XW7103

IMVP6_VSUM1

61

R7100

10K

21

1%
1/16W
MF-LF

402

1

R7101

3.65K

1%
1/10W
MF-LF
603

2

0.36UH-30A-1.05MOHM

XW7101

IMVP6_VSUM2

61

R7105

10K

21

1%
1/16W
MF-LF

402

1

R7106

3.65K

1%
1/10W
MF-LF
603

2

APPLE INC.

CRITICAL

1

C7133

68UF

10%
50V

16V

2

X7R
402

D3L

CRITICAL

L7100

PCMC104T-SM

SM

21

C7103

0.22UF

10%
10V

CERM

402

CRITICAL

L7101

PCMC104T-SM

SM

21

C7104

0.22UF

10%
10V

CERM

402

IMVP6 CPU VCore Regulator

SYNC_MASTER=RXU_K20

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

1

1

20%

POLY-TANT

C7154

1UF

10%
25V

2

2

X5R
603-1

1

C7158

1UF

10%
25V

2

X5R
603-1

=PPVCORE_S0_CPU_REG

44A MAX CURRENT

21

XW7104

SM

21

IMVP6_VO1

61

1

R7104

1

5%
1/16W
MF-LF
402

2

21

21

XW7102

SM

21

IMVP6_VO2

61

1

R7107

1

5%
1/16W
MF-LF
402

2

21

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SIZE

D

SCALE

NONE

051-8071

SHT

8

1

C7156

0.001UF

10%
50V

2

X7R
402

1

C7157

0.001UF

10%
50V

2

X7R
402

SYNC_DATE=05/21/2008

REV.

B

OF

9861

D

C

B

A

8

76

5

4

3

2

1

87

www.vinafix.vn

6

5

4

3

21

D

C

B

F=400KHZ

Vout = 5.0V

7A MAX OUTPUT

(Q7220 limit)

CASE-D3L-SM1

=PPVIN_S5_P5VP3V3

8

=PP5V_S3_REG

62

8

23

2

VIN

V5SW

6

SKIPSEL1

19

SKIPSEL2

14

TRIP

31

VBST1 VBST2

1

DRVH1 DRVH2

32

SW1 SW2

30

DRVL1

7

CSP1 CSP2

8

402

2

P5VS3_FUNC

P5VS3_VFB1

P5VS3_COMP1

1

R7249

0

5%

1/16W

MF-LF

402

2

CSN1 CSN2

11

FUNC

9

VFB1 VFB2

10

COMP1 COMP2

4

EN1 EN2

5

PGOOD1 PGOOD2

GND

28

PLACEMENT_NOTE=Place XW7200 between pins U7200.28 and 33.

GND_P5VP3V3_SGND

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V

CRITICAL

L7220

1.0UH-22A-10M-OHM

SM-IHLP

2

XW7220

SM

1

CRITICAL

C7240

33UF

20%

16V

POLY-TANT

CASED2E-SM

P5VS3_LL_RC

21

R7299

1/10W
MF-LF

1

2

CRITICAL

Q7220

RJK0305DPB

LFPAK-HF

2

XW7221

SM

1

1

1

5%

603

2

SI7110DN

PWRPK-1212-8-HF

1

C7299

0.0033UF

10%
50V

2

CERM
402

1

C7241

1UF

10%
25V

2

X5R
603-1

Q7225

P5VS3_CSP1-R

321

5

CRITICAL

5

D

S

321

4

4

G

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

1

R7256

2.74K

2

1

C7200

1UF

10%
25V

2

X5R

603-1

1

C7224

0.1UF

10%
50V

2

X7R

603-1

16V

X5R

10%

0.1UF

C7218

2

1

402

1/16W1%MF-LF

1.54K

R7247

1

P5VS3_COMP1_R

1%

1/16W

MF-LF

402

P5VS3_VBST

P5VS3_DRVH

GATE_NODE=TRUE

P5VS3_LL

SWITCH_NODE=TRUE

P5VS3_DRVL

GATE_NODE=TRUE

P5VS3_CSP1

P5VS3_CSN1

402

P5VP3V3_VREG3

62

R7248

1

NO STUFF

5%

MF-LF

1/16W

0

2

1

R7236

1

R7237

10K

20.0K

1%

1%

1/16W

1/16W

MF-LF

MF-LF

402

2

402

2

C7236

62

470PF

1

10%
50V

2

CERM

402

P5VP3V3_VREF2

One master PGOOD for both 5V and 3V3

67

OUT

C7237

100PF

5%

50V

CERM

402

P5V3V3_PGOOD

1

2

1

C7270

0.001UF

10%
50V

2

X7R
402

=PP5V_S3_REG

62

8 8

CRITICAL

1

C7252

330UF

POLY-TANT

20%

6.3V
2

1

2

PLACEMENT_NOTE=PLACE XW7222 NEXT TO L7220.

C7250

C7271

0.001UF

10%
50V
X7R
402

P5VS3_VFB1-R

1

10UF

20%

PLACEMENT_NOTE=PLACE XW7220 AND XW7221 NEXT TO L7220.

10V

2

X5R

805

2

XW7222

SM

1

PATH=I623

1

R7220

40.2K

1%
1/16W
MF-LF
402

2

1

R7221

10K

1%
1/16W
MF-LF
402

2

29

VREG5

CRITICAL

U7201

LLP

TPS51220

THRM_PAD

XW7200

SM

P5VP3V3_VREG5

22

VREG3

33

21

13

DRVL2

62

VREF2

EN

RF

P5VP3V3_VREF2

C7201

0.22UF

12

26

24

25

27

18
17

P3V3S5_RF

3
16
15

21
20

CRITICAL

C7280

Q7260

1

8

9432

MLP

Q1

Q2

P3V3S5_CSP2_R

33UF

16V

CASED2E-SM

7

P5VP3V3_VREG3

62

1

1

C7203

1UF

10%

6.3V
CERM

R7206

249K

1%

1/16W

MF-LF

402

C7238

62

P3V3S5_VFB2

P3V3S5_COMP2

470PF

10%
50V

CERM

402

P5VP3V3_VREF2

402

1

R7238

2

P3V3S5_COMP2_R

1

2

1

10%
10V

2

CERM

402

P3V3S5_VBST

P3V3S5_DRVH

GATE_NODE=TRUE

P3V3S5_LL

SWITCH_NODE=TRUE

P3V3S5_DRVL

GATE_NODE=TRUE

P3V3S5_CSP2

P3V3S5_CSN2

1

2

C7205

10UF

20%

6.3V

2

2

X5R
603

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

0.1UF

C7288

1

1.18K

R7246

1

R7239

10K

20.0K

1%

1/16W

1%

MF-LF

1/16W

402

MF-LF

402

2

1

C7239

100PF

5%

50V

2

CERM

402

1

1

C7264

0.1UF

25V

10%

X5R

402

2

402

MF-LF1%1/16W

2

603-1

1

R7216

3.83K

2

CRITICAL

10%
50V

2

X7R

1%

1/16W

MF-LF

402

FDMS9600S

20%

POLY-TANT

SW

65

10

P3V3S5_LL_RC

1

2

NO STUFF

R7298

1/10W
MF-LF

1

2

603

10

5%

C7281

1UF

10%
25V
X5R
603-1

1

2

1

C7273

0.001UF

10%
50V

2

X7R
402

CRITICAL

L7260

2.2UH-14A

IHLP2525CZ-SM1

2

XW7260

SM

1

PLACEMENT_NOTE=PLACE XW7260 AND XW7261 NEXT TO L7260 .

NO STUFF

1

C7298

0.001UF

10%
50V

2

X7R
402

XW7261

XW7262

F=400KHZ

=PP3V3_S5_REG

Vout = 3.3V

6A MAX OUTPUT

21

2

SM

1

SM

(L7260 limit)

1

C7290

10UF

20%

6.3V

2

X5R

603

2

1

PLACEMENT_NOTE=PLACE XW7262 NEXT TO L7260.

P3V3S5_VFB2_R

PATH=I621

1

R7260

23.2K

1%
1/16W
MF-LF
402

2

1

R7261

10K

1%
1/16W
MF-LF
402

2

CRITICAL

C7292

330UF

POLY-TANT

CASE-D3L-SM1

1

20%

6.3V
2

1

C7272

0.001UF

10%
50V

2

X7R
402

D

C

B

A

8

76

=P5VS3_EN

IN IN

67 67

5

P3V3S5_EN

5V / 3.3V Power Supply

1

SYNC_DATE=05/21/2008

REV.

OF

9862

A

B

SYNC_MASTER=RXU_K20

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

APPLE INC.

4

3

2

SIZE

D

SCALE

.

DRAWING NUMBER

NONE

051-8071

SHT

87

www.vinafix.vn

6

5

4

3

21

D

=PPVIN_S0_DDRREG_LDO

8

=PPVIN_S3_DDRREG

1

C7355

10UF

20%

6.3V

2

X5R
603

6.3V
CERM

R7305

4.7

21

5%
1/16W
MF-LF

402

1

C7305

C7350

0.033UF

1UF

10%
10V
X5R
402

1

10%

16V

2

X5R

402

20%

2

603

PP5V_S3_DDRREG_V5FILT

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V

1

2

6

COMP

10

S3

11

S5

13

PGOOD

5

VTTREF

24

VTT

2

VTTSNS

7

NC0

NC

12

NC1

NC

15

V5IN

VTTGND

1

VTT Enable

VDDQ/VTTREF Enable

VDDQ PGOOD

THRM_PAD

25

14

CRITICAL

U7300

TPS51116

QFN

SYM (2 OF 2)

GND

3

XW7300

23

VLDOINV5FILT

VDDQSNS

MODE

VBST

DRVH

LL

DRVL

CS

VDDQSET

CS_GND

PGND

18

17

2

PLACEMENT_NOTE=Place next to U7300.3

SM

1

8

4

22

21

20

19

16

9

=PP5V_S3_DDRREG

8

C7300

4.7UF

C

=DDRVTT_EN

68

9

IN

=DDRREG_EN

67

IN

DDRREG_PGOOD

67

OUT

=PPVTT_S3_DDR_BUF

26

8

=PPVTT_S0_DDR_LDO

8

MIN_LINE_WIDTH=2 mm

MIN_NECK_WIDTH=0.2 mm

CRITICAL

C7360

X5R-CERM

22UF

6.3V

1

20%

2

603

XW7360

CRITICAL

1

C7361

22UF

20%

6.3V

2

X5R-CERM
603

10mA max load

Vout = VDDQSNS/2

Vout = VTTREF

SM

21

DDRREG_VTTSNS

PLACEMENT_NOTE=Place next to C7361

B

GND_DDRREG_SGND

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V

8

DDRREG_VDDQSNS

DDRREG_VBST

DDRREG_DRVH

GATE_NODE=TRUE

DDRREG_LL

SWITCH_NODE=TRUE

DDRREG_DRVL

GATE_NODE=TRUE

DDRREG_CS

DDRREG_FB

DDRREG_CSGND

R7310

8.06K

1/16W
MF-LF

1%

402

CRITICAL

C7330

68UF

16V

D3L

1

2

20%

POLY-TANT

(DDRREG_DRVH)

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

(DDRREG_VBST)

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

(DDRREG_LL)

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

(DDRREG_DRVL)

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

(DDRREG_CSGND)

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm

(DDRREG_VDDQSNS)

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm

(DDRREG_FB)

CRITICAL

1

C7331

68UF

16V

2

D3L

PLACEMENT_NOTE=Place next to Q7335

20%

POLY-TANT

1

1

2

2

C7332

1UF

10%
25V
X5R
603-1

C7325

0.1UF

10%
50V
X7R

603-1

1

C7333

0.001UF

10%
50V

2

X7R
402

5

CRITICAL

4

21

5

4

XW7335

SM

21

Q7330

RJK0305DPB

LFPAK-HF

CRITICAL

CRITICAL

Q7335

RJK0328DPB

LFPAK-HF

L7330

1.0UH-20A

IHLP4040DZ11-SM

21

CRITICAL

1

C7340

330UF

20%

2.5V

2

POLY-TANT
CASE-C2-SM

CRITICAL

CASE-C2-SM

321

321

Vout = 0.75V * (1 + Ra / Rb)

C7341

330UF

POLY-TANT

2.5V

=PPDDR_S3_REG

Vout = 1.50V or 1.80V
18A MAX OUTPUT
(Q7335 limit)
f = 400 kHz

1

1

C7345

10UF

2

20%

6.3V

2

X5R
603

NO STUFF

C7320

100PF

CERM

1

5%

50V

2

402

20%

1

C7346

0.001UF

10%
50V

2

X7R
402

1

R7320

15.0K

2

<Ra>

1

R7321

15.0K

2

<Rb>

1%
1/16W
MF-LF
402

1%
1/16W
MF-LF
402

8

2

XW7345

SM

PLACEMENT_NOTE=Place next to L7330

1

D

C

B

A

8

76

1.5V DDR3 Supply

051-8071

SHT

SYNC_DATE=05/21/2008

OF

1

A

REV.

B

9863

SYNC_MASTER=RXU_K20

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

5

4

3

2

SCALE

NONE

87

www.vinafix.vn

=PPVIN_S0_P5VRTS0_MCPCORE

8

CRITICAL

1

C7512

C7510

D

0.001UF

20%
50V

2

CERM
402

33UF

POLY-TANT

CASED2E-SM

NO STUFF

R7599

1.00

1%

1/6W

MF

402

PP5VRTS0_LL_RC
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

CRITICAL

1

2

C7516

10UF

20%
10V

X5R

805

L7510

2.2UH-14A

IHLP2525CZ-SM1

=PP5V_S0_REG

8 8

Vout = 5.03V

C

3.5A MAX OUTPUT

(Q7510 limit?)

f = 200 kHz F = 300 KHZ

CRITICAL

1

C7515

330UF

20%

6.3V
2

POLY-TANT

CASE-D3L-SM1

B

1

1

C7511

1UF

2

NO STUFF

1

C7599

0.001UF

10%
50V

2

X7R
402

21

2

10%
25V
X5R
603-1

PWRPK-1212-8-HF

CRITICAL

Q7510

SI7110DN

PWRPK-1212-8-HF

CRITICAL

Q7511

SI7108DN

20%
16V

1

2

(=PP5V_RTS0_REG)

2

XW7516

SM

1

PLACEMENT_NOTE=Place next to C7516

P5VRTS0_VSNS

NO STUFF

1

R7520

61.9K

1%
1/16W
MF-LF
402

2

<Ra>

1

R7521

0

5%
1/16W
MF-LF
402

2

<Rb>

Vout = 0.7V * (1 + Ra / Rb)

=P5V_RTS0_EN

67

IN

MCPCORES0_PGOOD

67

OUT

P5V_RTS0_PGOOD

67

OUT

=MCPCORES0_EN

67

IN

5

D

S

321

5

D

S

321

NO STUFF

C7520

100PF

CERM

G

G

1

5%

50V

2

402

4

(P5VRTS0_UGATE)

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
GATE_NODE=TRUE

(P5VRTS0_LGATE)

4

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
GATE_NODE=TRUE

(P5VRTS0_BOOT)

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

1

C7514

0.22UF

10%
16V

2

X7R
603

(P5VRTS0_PHASE)

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
SWITCH_NODE=TRUE

6

R7500

1/16W
MF-LF

PVIN_P5VRTS0_MCPCORE

C7500

10UF

10%
25V
X5R
805

P5VRTS0_BOOT
P5VRTS0_UGATE
P5VRTS0_PHASE

P5VRTS0_LGATE

(=P5V_RTS0_EN)

P5V_RTS0_FB
P5V_RTS0_ILIM

1

R7514

100K

1%
1/16W
MF-LF
402

2

4.7

5

1

32019

V5DRV

V5FILT

U7500

QFN

SN0802043

GND

21

PGND

(Internal 10-ohm path

from PVCC to VCC)

PP5V_S0_MCPREG_VCC

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V

PP3V3_S0_MCP_VREF

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

5

VREF3

LDOREFIN

REFIN2

PGOOD2

LDO

VBST2
DRVH2

LL2
DRVL2
VOUT2

EN2

TRIP2

VREF2

PGOOD1

7
8
24
26
25
23
30
27

32
31

1
13
28

C7504

402-1

1UF

10%
10V
X5R

22

XW7500

SM

21

1

2

Max load 100mA

PP5V_S0_MCPREG_LDO

(SGND)

MCPCORES0_BOOT
MCPCORES0_UGATE
MCPCORES0_PHASE
MCPCORES0_LGATE

(=PPMCPCORE_S0_REG)

MCPCORES0_REFIN
MCPCORES0_ILIM

PP2V_S0_MCPREG_REF

VOLTAGE=2V

Max load 50uA

1

C7530

0.1UF

20%
10V

2

CERM
402

GND_MCPREG_SGND

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0V

Vout = 2.0V * Req / (Ra + Req)

5%

402

2

1

2

6

VIN

17

VBST1

CRITICAL

15

DRVH1

16

LL1

18

DRVL1

10

VOUT1

14

EN1

9

VSW

11

VFB1

12

TRIP1

29

SKIPSEL

4

EN_LDO
V5DRV1

2

TONSEL

THRM_PAD

33

4

VOLTAGE=5V

C7503

R7564

100K

1/16W
MF-LF

1

C7501

1UF

10%
10V

2

X5R
402-1

1

1

1UF

10%
10V

2

X5R

402-1

1

1%

402

2

2

MCP_PROD

R7570

48.7K

0.1%

1/16W

<Ra>

MCP_PROD

R7571

54.9K

0.1%

1/16W

<Rb>

C7502

4.7UF

20%

6.3V
X5R-CERM
402

1

MF

402

2

1

MF

402

2

(MCPCORES0_UGATE)

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
GATE_NODE=TRUE

(MCPCORES0_PHASE)

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
SWITCH_NODE=TRUE

(MCPCORES0_LGATE)

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
GATE_NODE=TRUE

1

C7590

0.01UF

10%
16V

2

CERM
402

SSM6N15FEAPE

Req = Rb || Rc || Rd || Re

3

PMCPCORE_VSNS

MCP_PROD

1

R7580

475K

0.1%
1/16W
MF
402

2

<Rc>

Q7580

SOT563

5

D

SG

1

C7563

0.001UF

10%
50V

2

X7R
402

C7564

0.22UF

CERM-X7R

4

3

4

1

5%

10V

2

603

5

<Rd>

SSM6N15FEAPE

4

CRITICAL

321

MCP_PROD

1

R7581

237K

0.1%
1/16W
MF
402

2

Q7580

SOT563

2

CRITICAL

5

321

Q7565

RJK0328DPB

LFPAK-HF

PPMCPCORE_LL_RC

D

SG

C7560

68UF

POLY-TANT

CRITICAL

Q7560

RJK0305DPB

LFPAK-HF

NO STUFF

R7598

6

1

20%
16V

D3L

1.00

1/6W

21

1

1

C7561

1UF

10%
25V

2

2

X5R
603-1

MCPCORES0_PHASE_L

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
SWITCH_NODE=TRUE

CRITICAL

L7560

1.0UH-20A

IHLP4040DZ11-SM

96 46

1

96 46

1%

MF

402

2

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

NO STUFF

1

C7598

0.001UF

10%
50V

2

X7R
402

MCP_PROD

1

R7582

110K

0.1%
1/16W
MF
402

2

<Re>

MCP_VID2_LMCP_VID1_LMCP_VID0_L

SSM6N15FEAPE

Q7582

SOT563

21

21
43

MCPCOREISNS_P

IN

MCPCOREISNS_N

IN

XW7510

5

R7505

0.001

1%
1W
MF

0612

SM

3

D

SG

4

CRITICAL

21

1

2

C7566

10UF

C7567

10UF

20%
4V
X5R
603

=PPMCPCORE_S0_REG

Vout = See below

MAX CURRENT: 11A

1

4V

2

(Q7560 Limit)

CRITICAL

1

C7565

330UF

20%

2.5V

2

POLY-TANT
CASE-C2-SM

1

C7569

0.001UF

10%

50V

2

X7R
402

20%

X5R
603

CRITICAL

1

C7562

330UF

20%

2.5V

2

POLY-TANT
CASE-C2-SM

CRITICAL

1

C7568

330UF

20%

2.5V

2

POLY-TANT
CASE-C2-SM

D

C

B

MCP_VID<0>

21

IN

MCP_VID<1>

21

IN

MCP_VID<2>

21

IN

MCP79 Rev A01 requires higher core & analog voltage

PART NUMBER

114S0382

114S0400

114S0482

114S0453

114S0422

114S0373

114S0404

A

114S0458

114S0447

114S0411

8

76

QTY

RES,MTL FILM,1/16W,48.7K,1,0402,SMD,LF

1

1

RES,MTL FILM,1/16W,76.8K,1,0402,SMD,LF

1

RES,MTL FILM,1/16W,523K,1,0402,SMD,LF

1

RES,MTL FILM,1/16W,267K,1,0402,SMD,LF

1

RES,MTL FILM,1/16W,130K,1,0402,SMD,LF

1

RES,MTL FILM,1/16W,40.2K,1,0402,SMD,LF

1

RES,MTL FILM,1/16W,84.5K,1,0402,SMD,LF

1

RES,MTL FILM,1/16W,301K,1,0402,SMD,LF

1

RES,MTL FILM,1/16W,237K,1,0402,SMD,LF

1

RES,MTL FILM,1/16W,100K,1,0402,SMD,LF

DESCRIPTION

REFERENCE DES

R7570

R7571

R7580

R7581

R7582

R7570

R7571

R7580

R7581

R7582

CRITICAL

BOM OPTION

MCP_A01

MCP_A01

MCP_A01

MCP_A01

MCP_A01

MCP_A01Q

MCP_A01Q

MCP_A01Q

MCP_A01Q

MCP_A01Q

5

Rev A01 Production

VID<2:0> Voltage Voltage MCP Target

000 +1.224V +1.060V +1.05V

001 +1.159V +0.994V +1.00V

010 +1.101V +0.937V +0.95V

011 +1.049V +0.885V +0.90V

100 +0.995V +0.830V +0.85V

101 +0.952V +0.789V +0.80V

110 +0.913V +0.752V +0.75V

111 +0.876V +0.719V +0.70V

4

5V_S0 / MCP CORE REGULATOR

051-8071

SHT

SYNC_DATE=05/21/2008

OF

64 98

1

A

REV.

B

SYNC_MASTER=RXU_K20

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

3

2

SCALE

NONE

87

www.vinafix.vn

=PPVIN_S0_CPUVTTS0

8

R7699

=PP5V_S0_CPUVTTS0

8

D

CRITICAL

C7650

33UF

20%
16V

POLY-TANT

CASED2E-SM

1

2

C7651

1UF

10%
25V
X5R
603-1

1

2

12

10

5%
1/16W
MF-LF

402

PP5V_S0_CPUVTTS0_R

CPUVTTS0_TONE

R7651

130K

1/16W
MF-LF

1

1%

402

2

C

1

C7657

1UF

10%
10V

2

X5R
402

6

VOLTAGE=5V
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm

1

FB

31

TON

5

7

VLDO

NC

2

FBL

NC

29

EN/PSV

26

PGOOD

4

CRITICAL

U7600

SC417

MLPQ

30

34

15161718192021

5

3

V5V

6

VIN0

9

VIN1

10

VIN2

11

VIN3

35

VIN4VOUT

8

CPUVTTS0_VBST

BST

12

NC

DH

13

LX0

23

LX1

24

LX2

25

LX3

28

LX4

33

LX5

27

22

DL

ENL

CPUVTTS0_ILIM

14

NC

32

ILIM

PGNDAGND

C7653

0.22UF

10%
10V
CERM
402

12

CPUVTTS0_LL

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

R7654

7.15K

1%
1/16W
MF-LF

402

12

NO STUFF

R7631

SM

XW7661

4

R7698

1

5%
1/10W
MF-LF

603

12

CPUVTTS0_LL_XW

1

10K

1%
1/16W
MF-LF
402

2

PPCPUVTT_ISNS_R

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

1

2

CPUVTTS0_LL_RC

1

C7698

0.001UF

10%
50V

2

X7R
402

CRITICAL

L7650

2.2UH-14A

12

IHLP2525CZ-SM1

1V05CPU_P

46 96

IN

1V05CPU_N

46 96

IN

CRITICAL

3

R7650

0.002

1%

1/4W

MF

1206

12
34

XW7662

CRITICAL

1

C7654

150UF

20%

6.3V

2

POLY-TANT
CASE-B2-SM

SM

12

PPCPUVTT_S0_REG_XW

NO STUFF

1

C7630

0.01UF

10%
16V

2

CERM
402

1

C7655

0.01UF

10%
16V

2

CERM
402

21

1

C7658

0.001UF

20%
50V

2

CERM
402

=PPCPUVTT_S0_REG

MAX CURRENT = 6A

PWM FREQ = 400KHZ

8

D

C

XW7660

SM

12

CPUVTTS0_FB_C

NO STUFF

1

C7631

330PF

10%

B

50V

2

CERM
402

CRITICAL

1

R7655

12.1K

1%
1/16W
MF-LF

402

2

NO STUFF

1

C7656

180PF

5%
50V

2

CERM
402

B

CPUVTTS0_FB

GND_CPUVTTS0_SGND

67

IN

67

IN

=CPUVTTS0_EN

CPUVTTS0_PGOOD

VOLTAGE=0V
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm

R7630

12

56.2K

1%
1/16W
MF-LF

402

CRITICAL

R7656

1

11K

1%
1/16W
MF-LF

402

2

CPU VTT Power Supply

051-8071

SHT

SYNC_DATE=05/21/2008

REV.

B

OF

9865

A

A

SYNC_MASTER=RXU_K20

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

SCALE

NONE

8

76

5

4

3

2

1

87

www.vinafix.vn

6

5

4

3

21

D

C

B

A

1.8V S0 Switcher / 1.0VFW SWITCHER

S5 power required for output discharge feature

CRITICAL

L7780

=PP3V3_S3_P1V8S0

8

=P1V8S0_EN

67

IN

=PP3V3_FW_P1V0FW

8

INPUT RAIL IS 3.3V S0

=PP3V3_GPU_P1V8S0

8

=P1V8FB_EN

67 83 84

=PPVIN_S0_P1V05S5

8

66

1

C7753

0.01UF

10%
16V

2

CERM

402

C7700

2.2UF

402-LF

1

8

20%

6.3V
CERM

VFB1
VFB2

THRML

C7760

1

R7752

38.3K

1%
1/16W
MF-LF
402

2

1

2

3

VIN

U7700

DFN-HF

CRITICAL

LTC3547

PAD

9

1

10uF

20%

6.3V
2

X5R
603

P1V05_S5_COMP

1

R7753

100K

1%
1/16W
MF-LF
402

2

P1V05S5_COMP_R

GND

SW1

RUN1
RUN2

5

SW2

1

2

P1V0FW_SW

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
SWITCH_NODE=TRUE

4

P1V8S0_LX

6

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE

2

7

P1V8S0_VFB

Vout = 0.6V * (1 + Ra/Rb)

1

VI

U7760

TPS62202

SOT23-5

4

FB

CRITICAL

3

EN

GND

2

12

C7752

1UF

10%
25V
X5R
603-1

P1V05_S5_FSET

67

67

1

C7755

22PF

5%

50V

2

CERM

402

1

C7754

470PF

10%
50V

2

CERM

402

5

SW

R7751

4.7

5%
1/16W
MF-LF

402

IN

OUT

P1V05_S5_PGOOD

2.2UH-1.2A

12

PCAA031B-SM

C7782

10PF

5%

50V

CERM

402

P1V0FW_VFB

CRITICAL

L7700

2.2UH-1.2A

12

PCAA031B-SM

C7701

10PF

CERM

5%

50V

402

1.8V S0 Switcher

CRITICAL

L7760

10UH-0.55A-330MOHM

PCAA031B-SM

P1V8GPU_SW

P5V_P1V05S5

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V

=P1V05S5_EN

P1V05S5_VFB

12

P5V_P1V05S5_V5FILT

C7751

4.7UF

6.3V
CERM

<Ra>

1

R7782

1

187K

1%
1/16W
MF-LF

2

402

2

<Rb>

1

R7783

280K

1%
1/16W
MF-LF
402

2

1

2

=PP1V0_FW_REG

Vout = 1.001V

300mA max output

(Switcher limit)

f = 2.25 MHz

1

C7785

4.7UF

20%
4V

2

X5R
402

<Ra>

1

R7700

562K

1%
1/16W
MF-LF
402

2

<Rb>

1

R7701

280K

1%
1/16W
MF-LF
402

2

MAX CURRENT = 300MA

=PP1V8_GPUIFPX_REG

1

C7762

10uF

20%

6.3V

2

X5R
603

=PP1V8_S0_REG

VOUT = 1.804V

0.3A max output

(Switcher limit)

F = 2.25 MHZ

1

C7705

4.7UF

20%
4V

2

X5R
402

8

=PP3V3_S0_MCP_PLL_VLDO

8

8

8

8

8

66

MCP 1.05V AUXC Supply

12

1

20%

2

603

1

VIN

7

FSET

4

EN

3

FCCM

16

PGOOD

5

COMP

6

FB

8

VO

PVCC

U7750

ISL6269

CRITICAL

THRML

17

2

XW7750

SM

1

PAD

2

VCC

QFN

BOOT

PHASE

ISEN

PGND

14

UG

13

15

9

11

LG

10

1

C7750

2.2UF

10%
16V

2

X5R
603

P1V05S5_DRVH

GATE_NODE=TRUE

P1V05S5_VBST
P1V05S5_LL

SWITCH_NODE=TRUE

P1V05S5_DRVL

GATE_NODE=TRUE

GND_P1V05S5_SGND

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V

(P1V05S5_VFB)

(=PP1V05_S5_REG)

R7743

100

12

5%
1/16W
MF-LF

402

C7740

=PP1V8_S0_MCP_PLL_VLDO

C7741

=PPVIN_S0_P1V05S5

P1V05S5_ISEN

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

MCP79 PLL VLDO

PP3V3_S0_MCP_PLL_VLDO_BIAS

1

1UF

10%

6.3V

2

CERM

402

1UF

10%

6.3V
CERM

402

(GND)

1

2

1

C7775

2

C7770

0.22UF

U7740

LTC3025

DFN

1

BIAS

CRITICAL

34

IN

6

SHDN*

THRML

GND

2

1UF

10%
25V
X5R
603-1

1

R7779

2.0K

1%
1/16W
MF-LF

402

2

1

10%
10V

2

CERM

402

=PP1V05_S0_FET

8

68

1

2

PAD

OUT

ADJ

7

4

G

4

G

5

P1V05_S0_MCP_PLL_UF_ADJ

5

D

S

123

5

D

S

123

<Ra>

1

R7740

66.5K

1%
1/16W
MF-LF
402

2

<Rb>

1

R7741

40.2K

1%
1/16W
MF-LF
402

2

CRITICAL

Q7770

SI7110DN

PWRPK-1212-8-HF

CRITICAL

Q7771

SI7108DN

PWRPK-1212-8-HF

Vout = 0.6V * (1 + Ra / Rb)

=PPVIN_PFWBOOST

8

C7790

10UF

10%
16V
X5R

1206

NO STUFF

R7742

0

5%
1/16W
MF-LF
402

1

C7742

1UF

10%

6.3V
2

CERM

402

=PP3V3_S3_P1V5EXPS0

8

=P1V5_EXP_S0_EN

9

CRITICAL

L7770

2.2UH-8.0A

12

PCMB065T-SM

P1V05S5_VSNS

<Ra>

1

R7780

3.74K

1%
1/16W
MF-LF
402

2

<Rb>

1

R7781

4.42K

1%
1/16W
MF-LF
402

2

1

2

PFWBOOST_ITH_R

C7797

0.0012UF

10%
50V

CERM

402

MAX CURRENT = 300MA

=PP1V05_S0_MCP_PLL_UF

Vout = 1.052V

1

R7712

1

5%
1/16W
MF-LF
402

2

C7711

1

0.1UF

10%
16V

2

X5R
402

PLACEMENT_NOTE=Place XW7775 next to C7775

2

XW7775

SM

1

PFWBOOST_ITH

1

R7797

38.3K

1%
1/16W
MF-LF
402

2

1

2

8

1

2

23

C7776

4.7UF

20%
4V
X5R
402

FW BOOST POWER

R7790

0.02

0.5%
1W
MF

0612

CRITICAL

U7790

1

ITH/RUN SENSE-

LTC1872

SOT23-6

3

VFB

VIN

GND

5

2

12
34

4

6

NGATE

PFWBOOST_SENSE

PFWBOOST_NGATE

PFWBOOST_FB

PFWBOOST_SW

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
SWITCH_NODE=TRUE

4

VOUT = 0.8V * (1 + RA / RB)

EXPRESSCARD 1.5V_S0 SUPPLY

CRITICAL

1

C7710

22UF

20%

6.3V

2

CERM

P1V5EXPS0_AVIN

6

5

OVT FB

7

MODE

AGND PGND

9

PVINAVIN

CRITICAL

U7710

TPS62510

BQA

3

2

10

THRM_PAD

11

805

SWEN

PG

P1V5EXPS0_SW

1

P1V5EXPS0_FB

4

8

P1V5EXPS0_SGND

VOUT = 0.6V * (1 + Ra / Rb)

Vout = 1.052V
5A max output

(L7770 limit)

CRITICAL

C7771

330UF

2.0V

POLY-TANT

B2-SM

1

20%

2

f = 400 kHz

CRITICAL

L7710

2.2UH-1.2A

PCAA031B-SM

12

TP_P1V5_EXP_S0_PGOOD

=PP1V05_S5_MCP

7

D

G

S

12356

8

CRITICAL

4.7UH-10A

12

PCMC063T-SM

PFWBOOST_BOOST

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

CRITICAL

D7790

DO222-SM

12

STPS1L30MF

CRITICAL

SUPERSOT-6

FDC796NG

Q7790

C7712

22PF

5%
50V
CERM
402

1

2

1

2

1

2

SYNC_MASTER=RXU_K20

APPLE INC.

L7795

VOUT = 10V

?MA MAX OUTPUT

<Ra>

F=550KHZ?

1

R7795

1

C7795

1

C7794

1UF

10%
16V

2

X5R
402

<Ra>

R7710

150K

1%
1/16W
MF-LF
402

<Rb>

R7711

100K

1%
1/16W
MF-LF
402

12

XW7710

SM

33PF

5%

50V

CERM

402

1

2

1.00M

1%
1/4W
MF-LF

2

1206

2

<Rb>

1

R7796

86.6K

1%
1/16W
MF-LF
402

2

=PP1V5_EXP_S0

CRITICAL

C7713

22UF

20%

6.3V
CERM
805

1

C7799

33UF

20%
16V

2

POLY-TANT
CASED2E-SM

8

38

Vout = 1.5V

MAX Current = 1.2A

FREQ = 1Mhz

Misc Power Supplies

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

051-8071

SHT

66 98

=PFWBOOST_REG

1

C7798

33UF

20%
16V

2

POLY-TANT
CASED2E-SM

SYNC_DATE=05/21/2008

REV.

OF

8

D

C

B

A

B

8

76

5

4

3

2

1

87

www.vinafix.vn

6

5

4

3

21

D

C

41

IN

PLACEMENT_NOTE=near U4900

84 82 41 36 33 21

TP_DDRREG_PGOOD

MAKE_BASE=TRUE

SMC_PM_G2_EN

R7858

100K

PM_SLP_S3_L

7

IN

Unused PGOOD signal

6

VDD

U7840

SOT23-6

GND

PM_SLP_S3_L

RESET*

MR*

1

0

00

0

C7840

0.1uF

1

1

2

R7840

100K

5%

1/16W

MF-LF

402

2

RSMRST_PWRGD

P1V05_S5_PGOOD

20%

10V

CERM

402

3

TPS3808 MR* HAS INTERNAL PULLUP

42 41 39 21

41

66

PM_SLP_S4_L

IN

MAKE_BASE=TRUE

PLACEMENT_NOTE=near U1400

R7810

100K

1/16W
MF-LF

402

1

5%

2

3.3V,5V S3 ENABLE

2

5.1K

5%

1/16W
MF-LF

1

402

PLACEMENT_NOTE=near U7300

1

C7810

0.47UF

10%

6.3V

2

CERM-X5R

402

PLACEMENT_NOTE=near U7300

R7811

2

1

NO STUFF

1

2

R7812

0

5%

1/16W
MF-LF

402

PLACEMENT_NOTE=near U7201

C7812

0.47UF

10%

6.3V

CERM-X5R

402

PLACEMENT_NOTE=near U7201

(PM_S4_STATE_L)

P5VS3_EN

MAKE_BASE=TRUE

DDRREG_EN

MAKE_BASE=TRUE

=P3V3S3_EN

=P5VS3_EN

=DDRREG_EN

68

OUT

62

OUT

63

OUT

D

2

IG high

EG PM_ALL_GPU_PGOOD

TC7SZ08AFEAPE

5

A

U7880

B

3

PM_ALL_GFX_PGOOD

1

C7889

0.1UF

20%
10V

2

CERM
402

SOT665

4

Y

=PP3V3_S5_PWRCTL

ALL_SYS_PWRGD

67

8

84 41 25

OUT

C

=P5V_RTS0_EN

=P3V3S0_EN

=PBUSVSENS_EN

=P2V5S0_EN

=P1V2S0_EN

P1V05S0_EN

=P1V8S0_EN

=MCPDDR_EN

=CPUVTTS0_EN

=MCPCORES0_EN

Other S0 RAILS

=PP3V3_S0_PWRCTL

67

8

64

OUT

68

OUT

45

OUT

S0PGOOD_PWROK

67

64

65

64

62

9

67

IN

IN

IN

IN

IN

PM_ALL_GPU_PGOOD

MCPCORES0_PGOOD

CPUVTTS0_PGOOD

P1V8S0_PGOOD

P5V_RTS0_PGOOD

P5V3V3_PGOOD

87

OUT

87

OUT

68

OUT

66

OUT

68

OUT

65

OUT

64

OUT

R7892

1/16W
MF-LF

NO STUFF

R7891

0

5%
1/16W
MF-LF

402

PLACEMENT_NOTE=near U7880

10K

5%

402

1

2

21

PLACEMENT_NOTE=near U7880

S0_PWR_PGOOD

MAKE_BASE=TRUE

ALL_GFX_PGOOD_R

R7894

1

0

5%
1/16W
MF-LF

2

402

2

1

3.3V 1,05V S5 ENABLE

R7802

100

21

5%
1/16W
MF-LF

402

1

5%

1/16W

MF-LF

402

2

R7801

5.1K

21

5%
1/16W
MF-LF

402

PLACEMENT_NOTE=near U7750

P3V3S5_EN

NO STUFF

1

C7802

0.068UF

10%
10V

2

CERM

402

PLACEMENT_NOTE=near U7201

PM_G2_P1V05S5_EN

MAKE_BASE=TRUE

1

C7801

0.47UF

10%

6.3V

2

CERM-X5R

402

PLACEMENT_NOTE=near U7750

OUT

62

=P1V05S5_EN

66

OUT

State

Run (S0)

Sleep (S3)

Soft-Off (S5)

Battery Off (G3Hot)

SMC_PM_G2_ENABLE

1

1

1

0

=PP3V3_S5_PWRCTL

67

8

C7841

0.001UF

=PP3V42_G3H_PWRCTL

8

20%

50V

CERM

402

PM_SLP_S4_L

1

1

0

S5 rail PWRGD

51

SENSE

TPS3808G33DBVRG4

4

CT

CT

1

2

S0 ENABLE

R7878

100

5%
1/16W
MF-LF

402

PLACEMENT_NOTE=near U1400

DDRREG_PGOOD

21

R7879

100K

1/16W
MF-LF

402

(PM_SLP_S3_L)

2

1

5%

2

63

R7880

22K

5%
1/16W

1

MF-LF

402

PLACEMENT_NOTE=nearU7500

MCPCORES0_EN

MAKE_BASE=TRUE

1

C7880

0.47UF

10%

6.3V

2

CERM-X5R

402

PLACEMENT_NOTE=nearU7500

PM_SLP_S3_L_R

MAKE_BASE=TRUE

R7881

2

33K

5%
1/16W

1

MF-LF

402

PLACEMENT_NOTE=nearU7600

CPUVTTS0_EN

MAKE_BASE=TRUE

1

C7881

0.47UF

10%

6.3V

2

CERM-X5R

402

PLACEMENT_NOTE=nearQ7600

2

0

5%
1/16W

1

MF-LF

402

PLACEMENT_NOTE=nearQ7971

MCPDDR_EN

MAKE_BASE=TRUE

NO STUFF

1

C7882

0.47UF

10%

6.3V

2

CERM-X5R

402

PLACEMENT_NOTE=nearQ7971

R7882

2

10K

5%

1/16W

1

MF-LF

402

PLACEMENT_NOTE=nearU7700

P1V8S0_EN

MAKE_BASE=TRUE

1

C7883

0.47UF

10%

6.3V

2

CERM-X5R

402

PLACEMENT_NOTE=nearU7700

R7883

2

R7884

0

5%
1/16W

1

MF-LF

402

PLACEMENT_NOTE=nearU7951

NO STUFF

1

C7884

0.47UF

10%

6.3V

2

CERM-X5R

402

PLACEMENT_NOTE=nearU7951

2

R7885

10K

5%

1/16W

1

MF-LF

402

PLACEMENT_NOTE=nearU9900

P1V2_S0_EN

MAKE_BASE=TRUE

1

C7885

0.47UF

10%

6.3V

2

CERM-X5R

402

PLACEMENT_NOTE=nearU9900

2

R7886

5.1K

5%
1/16W

1

MF-LF

402

PLACEMENT_NOTE=nearU9900

P2V5S0_EN

MAKE_BASE=TRUE

1

C7886

0.47UF

10%

6.3V

2

CERM-X5R

402

PLACEMENT_NOTE=nearU9900

1.1V GPU ENABLE

EG_PWRSEQ_HW

R7851

=PP3V3_S0_PWRCTL

67

84

8

=PP3V3_S5_PWRCTL

67

8

EXTGPU_PWR_EN

IN

R7853

100K

1/16W
MF-LF

5%

402

1

2

EG_PWRSEQ_HW

R7850

1/16W

EG_PWRSEQ_HW

Q7850

SSM6N15FEAPE

100K

5%

SOT563

2

B

21

P1V1_GPU_EN_RC

402

1/16W

MF-LF

5%

10K

21

MF-LF

SSM6N15FEAPE

6

D

SG

1

EG_PWRSEQ_HW
Q7850

402

SOT563

5

GPU_S0_EN_L

MAKE_BASE=TRUE

3

D

SG

4

EG_PWRSEQ_HW
R7852

0

5%
1/16W
MF-LF
402

21

PLACEMENT_NOTE=near U9500

P1V1_GPU_EN

MAKE_BASE=TRUE

NO STUFF

1

C7850

0.022UF

20%
16V

2

CERM

402

PLACEMENT_NOTE=near U9500

GPUVCORE_EN_RC_L

67

=P1V1GPU_EN

=PP3V3_GPU_PWRCTL

67

8

OUT

R7868

P1V8_S0GPU_EN_RC

21

402

1/16W

5%

MF-LF

GPUVCORE_PGOOD

77

84 83

100K

EG_PWRSEQ_HW

SSM6N15FEAPE

Q7861

3

D

SOT563

5

SG

4

GPUVCORE ENABLE

EG_PWRSEQ_HW

=PP3V3_GPU_PWRCTL

8

67

A

GPUVCORE_EN_RC_L

67

R7863

1/16W

5%

100K

EG_PWRSEQ_HW

Q7861

SSM6N15FEAPE

MF-LF

SOT563

2

GPUVCORE_EN_RC

21

402

6

D

SG

1

EG_PWRSEQ_HW

R7864

MF-LF

5%

1/16W

0

PLACEMENT_NOTE=near U8900

GPUVCORE_EN

MAKE_BASE=TRUE

21

402

EG_PWRSEQ_HW

PLACEMENT_NOTE=near U8900

C7861

0.01UF

=GPUVCORE_EN

1

10%

16V

2

CERM

402

84 77

OUT

=PP3V3_S0_PWRCTL

67

8

1

R7889

100K

5%
1/16W
MF-LF

402

2

EG_PWRSEQ_HW

1/16W05%

R7888

MF-LF

P3V3GPU_EN

21

402

P1V1GPU_PGOOD

83

PLACEMENT_NOTE=near U7972

Graphic MEM ENABLE

EG_PWRSEQ_HW

R7869

P1V8_S0GPU_EN

MAKE_BASE=TRUE

21

5%

MF-LF

1/16W

0

PLACEMENT_NOTE=near U9500

OUT

PART#

QTY

353S2718

1

402

NO STUFF

1

C7869

0.022UF

20%

16V

2

CERM

402

PLACEMENT_NOTE=near U9500

=PP3V3_S0_PWRCTL

67

8

P1V8FB_PGOOD

83

84 68

DESCRIPTION

IC, QUAD VOLTAGE MONITOR

=P1V8FB_EN

OUT

G96 GPU requires rails to come

up in the following order:

1) 1.1V

2) GPU_3.3V

3) GPUVcore

4) GDDR3 1.8V

BOMOPTION: EG

EXT GPU PWRGD Pullup

1

R7890

100K

5%
1/16W
MF-LF

402

2

PM_ALL_GPU_PGOOD

MAKE_BASE=TRUE

REFERENCE DESIGNATOR(S)

U7871

=PP3V3_S0_VMON

67

84 83 66

67

67

67

OUT

8

67

8

67

8

=PP3V3_S0_VMON

67

8

=PP3V3_S0_VMON

8

=PP1V5_S0_VMON

8

=PP1V05_S0_VMON

8

V2MON THRESHOLD IS 2.866V
V3MON THRESHOLD IS 0.6V
V4MON THRESHOLD IS 0.6V

9

67

=PP1V5_S0_VMON

=PP1V05_S0_VMON

CRITICAL BOM OPTION

CRITICAL

3.3V 1.05V AND 1.5V S0 RAILS MONITOR CIRCUIT

place XW0402 if needed to save trace space for pin 7,8

1

8
7

6

NC

2

7

VDD

U7871

ISL88042IRTEZ

TDFN

3

V2MON
V3MON

TABLE_5_HEAD

TABLE_5_ITEM

GND

4

OMIT

THRM_PAD

5
6

U7871 IS TO REPLACE U7870

1

MR*

NC

S0PGOOD_PWROK

8

RST*V4MON

9

SEL

ADJ1
ADJ2

REF

VCC

U7870

LTC2909

NO STUFF

GND

5

CLOSE TO U7870 & U7871

3

DFN

TMR

RST*

THRM_PAD

9

LTC2909 THRESHOLD IS 3.136V

1.5V 1.05V COMPARED TO 0.5V

67

APPLE INC.

1

C7870

0.1uF

20%
10V

2

CERM

402

TIE TMR TO GND

2

TRST = 200MS

4

S0PGOOD_PWROK

Power Control

SYNC_MASTER=YMA_K20

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

67

SYNC_DATE=09/09/2008

051-8071

SHT

67 98

B

A

REV.

B

OF

8

76

5

4

3

2

1

87

www.vinafix.vn

6

5

4

3

21

D

C

=P3V3S3_EN

67

IN

=PP5V_S3_P1V05S0FET

8

=PP3V3_S5_P1V05FET

8

=PP3V3_S3_P3V3S3FET

8

Q7912

SSM6N15FEAPE

SSM6N15FEAPE

SOT563

2

Q7951

SOT563

6

D

SG

R7953

1/16W
MF-LF

1

10K

5%

402

1

2

3

D

R7912

10K

1/16W

MF-LF

402

P1V05_EN_L

3.3V S3 FET

1

5%

2

P3V3S3_EN_L

R7910

47K

5%

1/16W

MF-LF

402

C7911

0.033UF

1

10%
16V

2

X5R

402

21

P3V3S3_SS

CRITICAL

Q7910

FDC638P_G

SM

4

3

C7910

0.01UF

10%

16V

CERM

402

=PP3V3_S3_FET

6

5

2

1

MOSFET

CHANNEL

21

RDS(ON)

LOADING

8

3.3V S3 FET

FDC638P

P-TYPE

48 mOhm @4.5V

0.087 A (EDP)

=P3V3S0_EN

67

IN

=PP3V3_S0_P3V3S0FET

8

Q7912

SSM6N15FEAPE

1

R7932

3

D

SOT563

5

SG

4

100K

5%

1/16W

MF-LF

402

2

P3V3S0_EN_L

1.05V S0 FET

=PP3V3_GPU_P3V3GPUFET

8

1

R7972

51K

5%

1/16W

MF-LF

402

2

Q7972

SSM3K15FV

SOD-VESM-HF

P3V3GPU_EN

IN

1

D

GS

P3V3GPU_EN_L

3

2

R7952

220K

5%
1/16W
MF-LF

402

21

R7951

100K

5%
1/16W
MF-LF

402

P1V05S0_SS

Q7951

SSM6N15FEAPE

21

P1V05_EN_L_RC

SOT563

=PP1V05_S5_P1V05S0FET

8

CRITICAL

Q7953

SI7108DN

PWRPK-1212-8-HF

5

APN 376S0651

D

4

G

S

6

D

321

MOSFET

CHANNEL

RDS(ON)

LOADING

=PP1V05_S0_FET

2

SG

1

1

2

C7953

0.068UF

10%
10V
CERM
402

1.05V S0 FET

66

8

SI7108DN

N-TYPE

5 mOhm @4.5V

5.1 A (EDP)

84 67

3.3V S0 FET

C7931

0.033UF

R7930

47K

21

5%

1/16W

MF-LF

402

3.3V GPU FET

1

C7971

1UF

10%
10V

2

X5R

402

R7970

1K

21

5%

1/16W

MF-LF

402

10%
16V

X5R

402

P3V3GPU_SS

1

2

P3V3S0_SS

4

4

CRITICAL

Q7970

FDC606P_G

SOT-6

SGD

3

CRITICAL

Q7930

FDC606P_G

SOT-6

SGD

3

C7970

0.01UF

10%

16V

CERM

402

C7930

0.01UF

21

10%

16V

CERM

402

6521

6521

21

=PP3V3_S0_FET

3.3V S0 FET

MOSFET

CHANNEL

RDS(ON)

LOADING

=PP3V3_S0GPU_FET

3.3V GPU FET

MOSFET

CHANNEL

RDS(ON)

LOADING 1.1 A (EDP)

8

8

FDC606P

P-TYPE

26 mOhm @4.5V

2.9 A (EDP)

FDC606P

P-TYPE

26 mOhm @4.5V

D

C

5

SG

P1V05S0_EN

67

IN

B

4

MCP79 DDR FETs

MCP79 DDR pad leakage is high enough that nVidia recommends unpowering during sleep.
In order to support unpowering rail, hardware must guarantee MEM_CKE signals are low
before rail is turned off, and remains low until after rail turns back on or DIMMs
will exit self-refresh prematurely. MEM_VTT_EN output from MCP79 used to enable clamp
on VTT rail, which pulls all CKE signals low through VTT termination resistors.

B

1.5V S0 FET

=PPVTT_S0_VTTCLAMP

8

SSM6N15FEAPE

NO STUFF

C7976

0.001UF

CERM

20%
50V

402

Q7975

SOT563

1

R7975

10

90mA max load @ 0.9V

5%

81mW max power

1/16W
MF-LF

402

VTTCLAMP_L

6

D

2

SG

1

1

2

2

Power FETs

68

SYNC_DATE=05/19/2008

REV.

OF

98

A

B

SYNC_MASTER=YMA_K20

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

D

NONE

DRAWING NUMBER

051-8071

SHT

MOSFET

CHANNEL

RDS(ON)

LOADING

1.5V S0 FET

SI7108DN

N-TYPE

5 mOhm @4.5V

5.4 A (EDP)

8

8

63

9

IN

=PP5V_S3_VTTCLAMP

SSM6N15FEAPE

=DDRVTT_EN

Q7975

SOT563

5

R7976

1/16W
MF-LF

100K

5%

402

1

2

VTTCLAMP_EN

3

D

SG

4

=PP1V8R1V5_S0_MCP_FET

8

APN 376S0651

1

C7902

0.1UF

20%
10V

2

CERM

1/16W
MF-LF

100K

5%

402

1

2

MCPDDR_EN_L

3

D

SG

4

R7901

10K

5%
1/16W
MF-LF

402

21

MCPDDR_SS

R7971

47K

5%
1/16W
MF-LF

402

=PP5V_S3_MCPDDRFET

8

R7903

A

Q7971

SSM6N15FEAPE

SOT563

=MCPDDR_EN

67

IN

5

SSM6N15FEAPE

21

402

D

Q7971

SOT563

2

SG

MCPDDR_EN_L_RC

6

1

5

CRITICAL

D

Q7901

S

1

C7903

0.068UF

10%
10V

2

CERM
402

SI7108DN

PWRPK-1212-8-HF

321

=PP1V8R1V5_S0_FET

4

G

8

76

5

4

3

2

1

Power aliases required by this page:

www.vinafix.vn

- =PP1V2_GPU_PEX_PLLXVDD

- =PP1V2_GPU_PEX_IOVDDQ

- =PP1V2_GPU_PEX_IOVDD

Signal aliases required by this page:

(NONE)

BOM options provided by this page:

(NONE)

D

NC_GPU_DFM

NO_TEST=TRUE

C

H32

NC

M7

NC

P6

P7

NC

R7

NC

U7

NC

V6

NC

AB7

NC

AD6

NC

AF6

NC

AG6

NC

AJ5

NC

D35

NC

AK15

NC

AL7

NC

E7

NC

E35

NC

F7

NC

A2

NC

B

87

Page Notes

=PP1V1_GPU_PEX_PLLXVDD

8

=PP1V1_GPU_PEX_IOVDDQ

8

=PP1V1_GPU_PEX_IOVDD

8

PEX 1.1V Current = 2A

250mA

SYMBOL 2 OF 9

NC

OMIT

U8000

NB9P-GS

BGA

PEX_IOVDD1
PEX_IOVDD2
PEX_IOVDD3
PEX_IOVDD4
PEX_IOVDD5

PEX_IOVDDQ1
PEX_IOVDDQ2
PEX_IOVDDQ3
PEX_IOVDDQ4
PEX_IOVDDQ5
PEX_IOVDDQ6
PEX_IOVDDQ7
PEX_IOVDDQ8

PEX_IOVDDQ9
PEX_IOVDDQ10
PEX_IOVDDQ11
PEX_IOVDDQ12
PEX_IOVDDQ13
PEX_IOVDDQ14
PEX_IOVDDQ15
PEX_IOVDDQ16
PEX_IOVDDQ17
PEX_IOVDDQ18
PEX_IOVDDQ19
PEX_IOVDDQ20
PEX_IOVDDQ21
PEX_IOVDDQ22
PEX_IOVDDQ23
PEX_IOVDDQ24
PEX_IOVDDQ25

PEX_PLLVDD

VDD_SENSE

GND_SENSE

AK16

AK17

AK21

AK24

AK27

AG11

AG12

AG13

AG15

AG16

AG17

AG18

AG22

AG23

AG24

AG25

AG26

AJ14

AJ15

AJ19

AJ21

AJ22

AJ24

AJ25

AJ27

AK18

AK20

AK23

AK26

AL16

AG14

AD20

AD19

1500mA

180mA

PP1V1_GPU_PEX_PLLVDD_F

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=1.2V

GPU_VDD_SENSE

GPU_GND_SENSE

1

2

1

2

1

2

1

2

C8002

1UF

10%

6.3V
CERM
402

C8003

1UF

10%

6.3V
CERM
402

C8008

1UF

10%

6.3V
CERM
402

C8009

1UF

10%

6.3V
CERM
402

1

C8001

4.7UF

20%

6.3V

2

CERM
603

1

C8004

0.1UF

20%
10V

2

CERM
402

1

C8007

4.7UF

20%

6.3V

2

CERM
603

1

C8010

0.1UF

20%
10V

2

CERM
402

77

77

1

C8017

2

0.1UF

20%
10V
CERM
402

1

C8000

2

1

C8005

2

1

C8006

2

1

C8011

2

22UF

20%

6.3V
CERM-X5R
805

0.1UF

20%
10V
CERM
402

22UF

20%

6.3V
CERM-X5R
805

0.1UF

20%
10V
CERM
402

1

C8016

2

4.7UF

20%

6.3V
CERM
603

L8015

10NH-600MA

0603

21

C8015

4.7UF

6.3V
CERM

6

5

4

3

21

OMIT

U8000

NB9P-GS

BGA

0.1uF

PEG_R2D_C_P<0>

90

9

IN

PEG_R2D_C_N<0>

90

9

IN

PEG_R2D_C_P<1>

90

9

IN

PEG_R2D_C_N<1>

90

9

IN

PEG_R2D_C_P<2>

90

9

IN

PEG_R2D_C_N<2>

90

9

IN

PEG_R2D_C_P<3>

90

9

IN

PEG_R2D_C_N<3>

90

9

IN

PEG_R2D_C_P<4>

90

9

IN

PEG_R2D_C_N<4>

90

9

IN

PEG_R2D_C_P<5>

90

9

IN

PEG_R2D_C_N<5>

90

9

IN

PEG_R2D_C_P<6>

90

9

IN

PEG_R2D_C_N<6>

90

9

IN

PEG_R2D_C_P<7>

90

9

IN

PEG_R2D_C_N<7>

90

9

IN

PEG_R2D_C_P<8>

90

9

IN

PEG_R2D_C_N<8>

90

9

IN

PEG_R2D_C_P<9>

90

9

IN

PEG_R2D_C_N<9>

90

9

IN

PEG_R2D_C_P<10>

90

9

IN

PEG_R2D_C_N<10>

90

9

IN

PEG_R2D_C_P<11>

90

9

IN

PEG_R2D_C_N<11>

90

9

IN

PEG_R2D_C_P<12>

90

9

IN

PEG_R2D_C_N<12>

90

9

IN

PEG_R2D_C_P<13>

90

9

IN

PEG_R2D_C_N<13>

90

9

90

90

90

90

90 17

90 17

IN

9

IN

9

IN

9

IN

9

IN

IN

IN

9

IN

PEG_R2D_C_P<14>

PEG_R2D_C_N<14>

PEG_R2D_C_P<15>

PEG_R2D_C_N<15>

PEG_CLK100M_P
PEG_CLK100M_N

GPU_RESET_L

1

20%

2

603

C8020

C8021

C8022

C8023

C8024

C8025

C8026

C8027

C8028

C8029

C8030

C8031

C8032

C8033

C8034

C8035

C8036

C8037

C8038

C8039

C8040

C8041

C8042

C8043

C8044

C8045

C8046

C8047

C8048

C8049

C8050

C8051

R8020

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

1/16W
MF-LF

402

21

10% 16V X5R 402

21

10% 16V

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

10% 16V

21

21

21

21

21

21

21

10% X5R 40216V

21

16V 402X5R10%

21

21

21

21

21

21

10% X5R 40216V

0

21

5%

GPU_RESET_R_L

PEG_R2D_P<0>

90

90

PEG_R2D_N<0>

X5R 402

PEG_R2D_P<1>

90

402X5R10% 16V

90

PEG_R2D_N<1>

X5R 40210% 16V

90

PEG_R2D_P<2>

X5R 40210% 16V

90

PEG_R2D_N<2>

X5R 40210% 16V

PEG_R2D_P<3>

90

X5R 40210% 16V

90

PEG_R2D_N<3>

X5R 40210% 16V

90

PEG_R2D_P<4>

X5R 40210% 16V

PEG_R2D_N<4>

90

X5R 40210% 16V

PEG_R2D_P<5>

90

X5R 40210% 16V

PEG_R2D_N<5>

90

X5R 40210% 16V

PEG_R2D_P<6>

90

X5R 40210% 16V

90

PEG_R2D_N<6>

X5R 40210% 16V

PEG_R2D_P<7>

90

X5R 40210% 16V

90

PEG_R2D_N<7>

X5R 40210% 16V

PEG_R2D_P<8>

90

X5R 40210% 16V

90 90

PEG_R2D_N<8>

X5R 402

PEG_R2D_P<9>

90

X5R

40210% 16V

90

PEG_R2D_N<9>

40210% 16V X5R

90

PEG_R2D_P<10>

X5R 40216V10%

90

PEG_R2D_N<10>

X5R 40210% 16V

90

PEG_R2D_P<11>

X5R 40210% 16V

90

PEG_R2D_N<11>

X5R 40210% 16V

PEG_R2D_P<12>

90

PEG_R2D_N<12>

90

PEG_R2D_P<13>

90

X5R 40210% 16V

PEG_R2D_N<13>

90

X5R 40210% 16V

PEG_R2D_P<14>

90

X5R 40210% 16V

PEG_R2D_N<14>

90

X5R 40210% 16V

PEG_R2D_P<15>

90

X5R 40210% 16V

90

PEG_R2D_N<15>

TP_PEX_CLKREQ_L

7

AP17

AN17

AN19

AP19

AR19

AR20

AP20

AN20

AN22

AP22

AR22

AR23

AP23

AN23

AN25

AP25

AR25

AR26

AP26

AN26

AN28

AP28

AR28

AR29

AP29

AN29

AN31

AP31

AR31

AR32

AR34

AP34

AR16

AR17

AM16

AR13

PEX_RX0
PEX_RX0*

PEX_RX1
PEX_RX1*

PEX_RX2
PEX_RX2*

PEX_RX3
PEX_RX3*

PEX_RX4
PEX_RX4*

PEX_RX5
PEX_RX5*

PEX_RX6
PEX_RX6*

PEX_RX7
PEX_RX7*

PEX_RX8
PEX_RX8*

PEX_RX9
PEX_RX9*

PEX_RX10
PEX_RX10*

PEX_RX11
PEX_RX11*

PEX_RX12
PEX_RX12*

PEX_RX13
PEX_RX13*

PEX_RX14
PEX_RX14*

PEX_RX15
PEX_RX15*

PEX_REFCLK
PEX_REFCLK*

PEX_RST*

PEX_CLKREQ*

SYMBOL 1 OF 9

PEX_TSTCLK_OUT

PEX_TSTCLK_OUT*

PEX_TX0

PEX_TX0*

PEX_TX1

PEX_TX1*

PEX_TX2

PEX_TX2*

PEX_TX3

PEX_TX3*

PEX_TX4

PEX_TX4*

PEX_TX5

PEX_TX5*

PEX_TX6

PEX_TX6*

PEX_TX7

PEX_TX7*

PEX_TX8

PEX_TX8*

PEX_TX9

PEX_TX9*

PEX_TX10

PEX_TX10*

PEX_TX11

PEX_TX11*

PEX_TX12

PEX_TX12*

PEX_TX13

PEX_TX13*

PEX_TX14

PEX_TX14*

PEX_TX15

PEX_TX15*

PEX_TERMP

PEX_RFU1

PEX_RFU2

AL17

AM17

AM18

AM19

AL19

AK19

AL20

AM20

AM21

AM22

AL22

AK22

AL23

AM23

AM24

AM25

AL25

AK25

AL26

AM26

AM27

AM28

AL28

AK28

AK29

AL29

AM29

AM30

AM31

AM32

AN32

AP32

AJ17

AJ18

AG21

AG19

AG20

NC
NC

PEG_D2R_C_P<0>

90

90

PEG_D2R_C_N<0>

90

PEG_D2R_C_P<1>

90

PEG_D2R_C_N<1>

90

PEG_D2R_C_P<2>
PEG_D2R_C_N<2>

90

PEG_D2R_C_P<3>

90

PEG_D2R_C_N<3>

90

PEG_D2R_C_P<4>

90

PEG_D2R_C_N<4>

90

PEG_D2R_C_P<5>

90

90

PEG_D2R_C_N<5>

PEG_D2R_C_P<6>

90

90

PEG_D2R_C_N<6>

90

PEG_D2R_C_P<7>

90

PEG_D2R_C_N<7>

PEG_D2R_C_P<8>

90

PEG_D2R_C_N<8>

PEG_D2R_C_P<9>

90

90

PEG_D2R_C_N<9>

90

PEG_D2R_C_P<10>
PEG_D2R_C_N<10>

90

90

PEG_D2R_C_P<11>

90

PEG_D2R_C_N<11>

90

PEG_D2R_C_P<12>

90

PEG_D2R_C_N<12>

PEG_D2R_C_P<13>

90

PEG_D2R_C_N<13>

90

PEG_D2R_C_P<14>

90

PEG_D2R_C_N<14>

90

PEG_D2R_C_P<15>

90

PEG_D2R_C_N<15>

90

PEX_TSTCLK_P
PEX_TSTCLK_N

PEX_TERMP_PD

C8055

C8056

C8057

C8058

C8059

C8060

C8061

C8062

C8063

C8064

C8065

C8066

C8067

C8068

C8069

C8070

C8071

C8072

C8073

C8074

C8075

C8076

C8077

C8078

C8079

C8080

C8081

C8082

C8083

C8084

C8085

C8086

R8050

2.49K

1%
1/16W
MF-LF

402

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

21

21

10% 402X5R16V

21

10% 402X5R16V

21

10% X5R16V 402

21

10% X5R16V 402

21

10% X5R16V 402

21

10% X5R16V 402

21

10% 16V X5R 402

21

10%

16V X5R 402

21

10% 16V X5R 402

21

10% 16V X5R 402

21

10% 16V X5R 402

21

10% X5R16V 402

21

10% X5R16V 402

21

10% X5R16V 402

21

10% X5R16V 402

21

10% X5R16V 402

21

10% 16V X5R 402

21

10% 16V X5R 402

21

10% 16V X5R 402

21

10% 16V X5R 402

21

10% X5R16V 402

21

10% X5R16V 402

21

10% X5R16V 402

21

10% X5R16V 402

21

10% X5R16V 402

21

10% X5R16V 402

21

10% X5R16V 402

21

10% X5R16V 402

21

10% X5R16V 402

21

10% 16V X5R 402

21

10% 16V X5R 402

21

10% 16V X5R 402

PEG_D2R_P<0>

PEG_D2R_N<0>

PEG_D2R_P<1>

PEG_D2R_N<1>

PEG_D2R_P<2>

PEG_D2R_N<2>

PEG_D2R_P<3>

PEG_D2R_N<3>

PEG_D2R_P<4>

PEG_D2R_N<4>

PEG_D2R_P<5>

PEG_D2R_N<5>

PEG_D2R_P<6>

PEG_D2R_N<6>

PEG_D2R_P<7>

PEG_D2R_N<7>

PEG_D2R_P<8>

PEG_D2R_N<8>

PEG_D2R_P<9>

PEG_D2R_N<9>

PEG_D2R_P<10>

PEG_D2R_N<10>

PEG_D2R_P<11>

PEG_D2R_N<11>

PEG_D2R_P<12>

PEG_D2R_N<12>

PEG_D2R_P<13>

PEG_D2R_N<13>

PEG_D2R_P<14>

PEG_D2R_N<14>

PEG_D2R_P<15>

PEG_D2R_N<15>

R8060

200

1%
1/16W
MF-LF

402

90

9

OUT

90

9

OUT

90

9

OUT

90

9

OUT

90

9

OUT

90

9

OUT

90

9

OUT

90

9

OUT

90

9

OUT

90

9

OUT

90

9

OUT

90

9

OUT

90

9

OUT

90

9

OUT

90

9

OUT

90

9

OUT

90

9

OUT

90

9

OUT

90

9

OUT

90

9

OUT

90

9

OUT

90

9

OUT

90

9

OUT

90

9

OUT

90

9

OUT

90

9

OUT

90

9

OUT

90

9

OUT

90

9

OUT

90

9

OUT

90

9

OUT

90

9

OUT

21

D

C

B

A

8

76

NV G96 PCI-E

SYNC_MASTER=M98_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

5

4

3

2

SCALE

NONE

051-8071

SHT

1

SYNC_DATE=04/01/2008

REV.

OF

9869

A

B

Power aliases required by this page:

www.vinafix.vn

- =PPVCORE_GPU

- =PP1V8_GPU_FBVDDQ

Signal aliases required by this page:

(NONE)

BOM options provided by this page:

(NONE)

D

C

B

A

87

Page Notes

=PPVCORE_GPU

8

???A @ ???/???MHz Core/Mem Clk for VDD

1

C8100

4.7UF

20%

6.3V

2

X5R-CERM

402

1

C8103

0.47UF

10%

6.3V

2

CERM-X5R

402

1

C8108

0.47UF

10%

6.3V

2

CERM-X5R

402

1

C8113

0.1UF

20%
10V

2

CERM

402

1

C8118

0.1UF

20%
10V

2

CERM

402

=PP1V8_GPU_FBVDDQ

8

Nvidia PRD for GB-128 uses 4x4.7uF, 8x0.47uF, 16x0.1uF

C8156

0.1UF

C8162

0.1UF

C8168

0.47UF

CERM-X5R

1

20%
10V

2

CERM

402

1

20%
10V

2

CERM

402

1

10%

6.3V
2

402

C8157

0.1UF

C8163

0.1UF

C8169

0.47UF

CERM-X5R

1

C8158

20%
10V

CERM

402

20%
10V

CERM

402

10%

6.3V

402

0.1UF

2

1

C8164

0.1UF

2

1

C8170

0.47UF

2

CERM-X5R

6

C8159

0.1UF

C8165

0.1UF

C8171

0.47UF

CERM-X5R

1

C8102

4.7UF

20%

6.3V

2

X5R-CERM

402

1

C8105

0.47UF

10%

6.3V

2

CERM-X5R

402

1

C8110

0.47UF

10%

6.3V

2

CERM-X5R

402

1

C8115

0.1UF

20%
10V

2

CERM

402

1

C8120

0.1UF

20%
10V

2

CERM

402

1

20%
10V

2

CERM

402

1

20%
10V

2

CERM

402

1

10%

6.3V
2

402

1

C8106

0.47UF

10%

6.3V

2

CERM-X5R

402

1

C8111

0.47UF

10%

6.3V

2

CERM-X5R

402

1

C8116

0.1UF

20%
10V

2

CERM

402

1

C8121

0.1UF

20%
10V

2

CERM

402

???A @ ???MHz 1.8V GDDR3

1

C8150

4.7UF

20%

6.3V
2

CERM

603

1

C8160

0.47UF

10%

6.3V
2

CERM-X5R

402

1

C8166

0.47UF

10%

6.3V
2

CERM-X5R

402

C8151

4.7UF

C8161

0.47UF

CERM-X5R

C8167

0.47UF

CERM-X5R

1

C8107

0.47UF

10%

6.3V

2

CERM-X5R

402

1

C8112

0.47UF

10%

6.3V

2

CERM-X5R

402

1

C8117

0.1UF

20%
10V

2

CERM

402

1

C8122

0.1UF

20%
10V

2

CERM

402

1

20%

6.3V
2

CERM

603

1

10%

6.3V
2

402

1

10%

6.3V
2

402

1

C8101

4.7UF

20%

6.3V

2

X5R-CERM

402

1

C8104

0.47UF

10%

6.3V

2

CERM-X5R

402

1

C8109

0.47UF

10%

6.3V

2

CERM-X5R

402

1

C8114

0.1UF

20%
10V

2

CERM

402

1

C8119

0.1UF

20%
10V

2

CERM

402

1

20%
10V

2

CERM

402

1

20%
10V

2

CERM

402

1

10%

6.3V
2

402

5

L11

L12

L13

L14

L15

L16

L17

L18

L19

L20

L21

L22

L23

L24

L25

M12

M14

M16

M18

M20

M22

M24

P11

P13

P15

P17

P19

P21

P23

P25

R11

R12

R13

R14

R15

R16

R17

R18

R19

R20

R21

R22

R23

R24

R25

T12

T14

T16

T18

T20

T22

T24

V11

V13

V15

V17

SYMBOL 9 OF 9

VDD VDD

SYMBOL 7 OF 9

B18

J17

U27

AB27

AB29

AC27

AD27

AE27

AJ28

E21

FBVDDQ FBVDDQ

G8

G9

G17

G18

G22

H29

J14

J15

J16

OMIT

U8000

NB9P-GS

BGA

OMIT

U8000

NB9P-GS

BGA

J20

J21

J22

J23

J24

J29

N27

P27

R27

T27

U29

V27

V29

V34

W27

Y27

AA27

AA29

AA31

V19

V21

V23

V25

W11

W12

W13

W14

W15

W16

W17

W18

W19

AD24

W21

W22

W23

W24

W25

Y12

Y14

Y16

Y18

Y20

Y22

Y24

AB11

AB13

AB15

AB17

AB19

AB21

AB23

AB25

AC11

AC12

AC13

AC14

AC15

AC16

AC17

AC18

AC19

AC20

AC21

AC22

AC23

AC24

AC25

AD12

AD14

AD16

AD18

AD22

W20

4

U8000

NB9P-GS

B3

B6

B9

B12

B15

B21

B24

B27

B30

B33

C2

C34

E6

E9

E12

E15

E18

E24

E27

E30

F2

F5

F31

F34

J2

J5

J31

J34

L9

M2

M5

M11

M13

M15

M17

M19

M21

M23

M25

M31

M34

N11

N12

N13

N14

N15

N16

N17

N18

N19

N20

N21

N22

N23

N24

N25

P12

P14

P16

P18

P20

P22

P24

R2

R5

R31

R34

T11

T13

T15

T17

T19

T21

T23

T25

U11

U12

U13

U14

U15

U16

U17

U18

U19

U20

U21

U22

U23

U24

U25

V2

V5

V9

V12

V14

V16

BGA

SYMBOL 8 OF 9

3

V18

V20

V22

V24

V31

Y11

Y13

Y15

Y17

Y19

Y21

Y23

Y25

AA2

AA5

AA11

AA12

AA13

AA14

AA15

AA16

AA17

AA18

AA19

AA20

AA21

AA22

AA23

AA24

AA25

AA34

AB12
AB14

AB16

AB18

AB20

AB22

AB24

AC9

AD2

AD5

AD11

AD13

AD15

AD17

AD21

AD23

AD25

GNDGND

AD31

AD34

AE11

AE12

AE13

AE14

AE15

AE16

AE17

AE18

AE19

AE20

AE21

AE22

AE23

AE24

AE25

AG2

AG5

AG31

AG34

AK2

AK5

AP33

AK31

AK34

AL6

AL9

AL12

AL15

AL18

AL21

AL24

AL27

AL30

AN2

AN34

AP3

AP6

AP9

AP12

AP15

AP18

AP21

AP24

AP27

AP30

21

D

C

B

NV G96 CORE/FB POWER

SYNC_MASTER=M98_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

D

NONE

DRAWING NUMBER

051-8071

SHT

SYNC_DATE=04/01/2008

REV.

OF

9870

A

B

8

76

5

4

3

2

1

Power aliases required by this page:

www.vinafix.vn

- =PP1V2_GPU_FBPLLAVDD

- =PP1V8_GPU_FBIO

Signal aliases required by this page:

(NONE)

BOM options provided by this page:

(NONE)

D

C

B

A

87

Page Notes

OMIT

U8000

NB9P-GS

BGA

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

FB_A_DQ<0>

7

BI

FB_A_DQ<1>

7

BI

FB_A_DQ<2>

7

BI

FB_A_DQ<3>

7

BI

FB_A_DQ<4>

7

BI

FB_A_DQ<5>

7

BI

FB_A_DQ<6>

7

BI

FB_A_DQ<7>

7

BI

FB_A_DQ<8>

7

BI

FB_A_DQ<9>

7

BI

FB_A_DQ<10>

7

BI

FB_A_DQ<11>

7

BI

FB_A_DQ<12>

7

BI

FB_A_DQ<13>

7

BI

FB_A_DQ<14>

7

BI

FB_A_DQ<15>

7

BI

FB_A_DQ<16>

7

BI

FB_A_DQ<17>

7

BI

FB_A_DQ<18>

7

BI

FB_A_DQ<19>

7

BI

FB_A_DQ<20>

7

BI

FB_A_DQ<21>

7

BI

FB_A_DQ<22>

7

BI

FB_A_DQ<23>

7

BI

FB_A_DQ<24>

7

BI

FB_A_DQ<25>

7

BI

FB_A_DQ<26>

7

BI

FB_A_DQ<27>

7

BI

FB_A_DQ<28>

7

BI

FB_A_DQ<29>

7

BI

FB_A_DQ<30>

7

BI

FB_A_DQ<31>

7

BI

FB_A_DQ<32>

7

BI

FB_A_DQ<33>

7

BI

FB_A_DQ<34>

7

BI

FB_A_DQ<35>

7

BI

FB_A_DQ<36>

7

BI

FB_A_DQ<37>

7

BI

FB_A_DQ<38>

7

BI

FB_A_DQ<39>

7

BI

FB_A_DQ<40>

7

BI

FB_A_DQ<41>

7

BI

FB_A_DQ<42>

7

BI

FB_A_DQ<43>

7

BI

FB_A_DQ<44>

7

BI

FB_A_DQ<45>

7

BI

FB_A_DQ<46>

7

BI

FB_A_DQ<47>

7

BI

FB_A_DQ<48>

7

BI

FB_A_DQ<49>

7

BI

FB_A_DQ<50>

7

BI

FB_A_DQ<51>

7

BI

FB_A_DQ<52>

7

BI

FB_A_DQ<53>

7

BI

FB_A_DQ<54>

7

BI

FB_A_DQ<55>

7

BI

FB_A_DQ<56>

7

BI

FB_A_DQ<57>

7

BI

FB_A_DQ<58>

7

BI

FB_A_DQ<59>

7

BI

FB_A_DQ<60>

7

BI

FB_A_DQ<61>

7

BI

FB_A_DQ<62>

7

BI

FB_A_DQ<63>

7

BI

R30

R32

P31

N30

L31

M32

M30

L30

P33

P34

N35

P35

N34

L33

L32

N33

K31

K30

G30

K32

G32

H30

F30

G31

H33

K35

K33

G34

K34

E33

E34

G33

AG30

AH31

AG32

AF31

AF30

AD30

AC32

AE30

AE32

AF33

AF34

AE35

AE33

AE34

AC35

AB32

AN33

AK32

AL33

AM33

AL31

AK30

AJ30

AH30

AM35

AH33

AH35

AH32

AH34

AM34

AL35

AJ33

P29

NC

R29

NC

L29

NC

M29

NC

AD29

NC

AE29

NC

AG29

NC

AH29

NC

SYMBOL 3 OF 9
FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63

FBA_RFU0
FBA_RFU1*
FBA_RFU2
FBA_RFU3*
FBA_RFU4
FBA_RFU5*
FBA_RFU6
FBA_RFU7*

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8

FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30

FBA_CLK0
FBA_CLK0*

FBA_CLK1
FBA_CLK1*

FBA_DQM0

FBA_DQM1

FBA_DQM2

FBA_DQM3

FBA_DQM4

FBA_DQM5

FBA_DQM6

FBA_DQM7

FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7

FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7

FB_DLLAVDD0
FB_PLLAVDD0

FBA_DEBUG

FB_CAL_PD_VDDQ

FB_CAL_PU_GND

FB_CAL_TERM_GND

V32

W31

U31

Y32

AB35

AB34

W35

W33

W30

T34

T35

AB31

Y30

Y34

W32

AA30

AA32

Y33

U32

Y31

U34

Y35

W34

V30

U35

U30

U33

AB30

AB33

T33

W29

T32

T31

AC31

AC30

P30

P32

J30

H34

AF32

AF35

AL32

AL34

N32

L35

H31

G35

AD32

AC34

AJ31

AJ35

N31

L34

J32

H35

AE31

AC33

AJ32

AJ34

AG27

AF27

T30

K27

L27

M27

PLACEMENT_NOTE=Place close to U8000.

FB_A_LMA<4>

FB_A_RAS_L

FB_A_LMA<5>

FB_A_BA<1>

FB_A_UMA<2>

FB_A_UMA<4>

FB_A_UMA<3>

FB_A_CS1_L

FB_A_CS0_L

FB_A_MA<11>

FB_A_CAS_L

FB_A_WE_L

FB_A_BA<0>

FB_A_UMA<5>

FB_A_MA<12>

FB_A_DRAM_RST

FB_A_MA<7>

FB_A_MA<10>

FB_A_CKE

FB_A_MA<0>

FB_A_MA<9>

FB_A_MA<6>

FB_A_LMA<2>

FB_A_MA<8>

FB_A_LMA<3>

FB_A_MA<1>

FB_A_MA<13>

FB_A_BA<2>

TP_FBA_CMD28

TP_FBA_CMD29

TP_FBA_CMD30

FB_A_CLK_P<0>

FB_A_CLK_N<0>

FB_A_CLK_P<1>

FB_A_CLK_N<1>

FB_A_DQM_L<0>

FB_A_DQM_L<1>

FB_A_DQM_L<2>

FB_A_DQM_L<3>

FB_A_DQM_L<4>

FB_A_DQM_L<5>

FB_A_DQM_L<6>

FB_A_DQM_L<7>

FB_A_RDQS<0>

FB_A_RDQS<1>

FB_A_RDQS<2>

FB_A_RDQS<3>

FB_A_RDQS<4>

FB_A_RDQS<5>

FB_A_RDQS<6>

FB_A_RDQS<7>

FB_A_WDQS<0>

FB_A_WDQS<1>

FB_A_WDQS<2>

FB_A_WDQS<3>

FB_A_WDQS<4>

FB_A_WDQS<5>

FB_A_WDQS<6>

FB_A_WDQS<7>

FBA_DEBUG

FBCAL_PD_VDDQ

FBCAL_PU_GND

FBCAL_TERM_GND

6

95 79 72

OUT

95 79 72

OUT

95 79 72

OUT

95 79 72

OUT

95 79 72

OUT

95 79 72

OUT

95 79 72

OUT

95 79

OUT

95 72

OUT

95 79 72

OUT

95 79 72

OUT

95 79 72

OUT

95 79 72

OUT

95 79 72

OUT

95 79 72

OUT

95 79 72

OUT

95 79 72

OUT

95 79 72

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT OUT

75

75

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

75

R8292

40.2

1/16W

MF-LF

1

95 79 72

R8201

10K

95 79 72

5%

1/16W

95 79 72

MF-LF

402

95 79 72

2

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

PP1V1_GPU_FBPLLAVDD_F

MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM

95 79 72

VOLTAGE=1.1V

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

95 79 72

1

1%

402

2

95 79 72

OUT

71

1

C8202

0.1UF

20%
10V

2

CERM

402

1

R8291

33.2

1%

1/16W

MF-LF

402

2

5

OUT

1

R8200

10K

5%

1/16W

MF-LF

402

2

=PP1V1_GPU_FBPLLAVDD

8

C8201

0.1UF

20%
10V

CERM

402

1

2

C8200

1UF

10%

6.3V

CERM

402

1

2

PLACEMENT_NOTE=Place close to U8000.

95 79 72

CRITICAL

L8200

FERR-220-OHM

21

0402

=PP1V8_GPU_FBIO

71

8

1

R8293

60.4

1%
1/16W
MF-LF

402

2

PLACEMENT_NOTE=Place close to U8000.

R8290

48.7

1/16W
MF-LF

1

1%

402

2

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

4

FB_B_DQ<0>

7

BI

FB_B_DQ<1>

7

BI

FB_B_DQ<2>

7

BI

FB_B_DQ<3>

7

BI

FB_B_DQ<4>

7

BI

FB_B_DQ<5>

7

BI

FB_B_DQ<6>

7

BI

FB_B_DQ<7>

7

BI

FB_B_DQ<8>

7

BI

FB_B_DQ<9>

7

BI

FB_B_DQ<10>

7

BI

FB_B_DQ<11>

7

BI

FB_B_DQ<12>

7

BI

FB_B_DQ<13>

7

BI

FB_B_DQ<14>

7

BI

FB_B_DQ<15>

7

BI

FB_B_DQ<16>

7

BI

FB_B_DQ<17>

7

BI

FB_B_DQ<18>

7

BI

FB_B_DQ<19>

7

BI

FB_B_DQ<20>

7

BI

FB_B_DQ<21>

7

BI

FB_B_DQ<22>

7

BI

FB_B_DQ<23>

7

BI

FB_B_DQ<24>

7

BI

FB_B_DQ<25>

7

BI

FB_B_DQ<26>

7

BI

FB_B_DQ<27>

7

BI

FB_B_DQ<28>

7

BI

FB_B_DQ<29>

7

BI

FB_B_DQ<30>

7

BI

FB_B_DQ<31>

7

BI

FB_B_DQ<32>

7

BI

FB_B_DQ<33>

7

BI

FB_B_DQ<34>

7

BI

FB_B_DQ<35>

7

BI

FB_B_DQ<36>

7

BI

FB_B_DQ<37>

7

BI

FB_B_DQ<38>

7

BI

FB_B_DQ<39>

7

BI

FB_B_DQ<40>

7

BI

FB_B_DQ<41>

7

BI

FB_B_DQ<42>

7

BI

FB_B_DQ<43>

7

BI

FB_B_DQ<44>

7

BI

FB_B_DQ<45>

7

BI

FB_B_DQ<46>

7

BI

FB_B_DQ<47>

7

BI

FB_B_DQ<48>

7

BI

FB_B_DQ<49>

7

BI

FB_B_DQ<50>

7

BI

FB_B_DQ<51>

7

BI

FB_B_DQ<52>

7

BI

FB_B_DQ<53>

7

BI

FB_B_DQ<54>

7

BI

FB_B_DQ<55>

7

BI

FB_B_DQ<56>

7

BI

FB_B_DQ<57>

7

BI

FB_B_DQ<58>

7

BI

FB_B_DQ<59>

7

BI

FB_B_DQ<60>

7

BI

FB_B_DQ<61>

7

BI

FB_B_DQ<62>

7

BI

FB_B_DQ<63>

7

BI

D11

FBC_D0

E11

FBC_D1

F10

FBC_D2

D8

FBC_D3

F8

FBC_D4

F9

FBC_D5

E8

FBC_D6

F12

FBC_D7

B11

FBC_D8

C13

FBC_D9

A11

FBC_D10

B8

FBC_D11

A8

FBC_D12

C8

FBC_D13

C11

FBC_D14

C10

FBC_D15

D12

FBC_D16

E13

FBC_D17

F17

FBC_D18

F15

FBC_D19

F16

FBC_D20

E16

FBC_D21

F14

FBC_D22

F13

FBC_D23

D13

FBC_D24

A13

FBC_D25

B13

FBC_D26

A14

FBC_D27

C16

FBC_D28

A17

FBC_D29

B16

FBC_D30

D16

FBC_D31

D24

FBC_D32

D26

FBC_D33

E25

FBC_D34

F25

FBC_D35

F27

FBC_D36

E28

FBC_D37

F28

FBC_D38

D29

FBC_D39

A25

FBC_D40

B25

FBC_D41

D25

FBC_D42

C26

FBC_D43

C28

FBC_D44

B28

FBC_D45

A28

FBC_D46

A29

FBC_D47

E29

FBC_D48

F29

FBC_D49

D30

FBC_D50

E31

FBC_D51

C33

FBC_D52

D33

FBC_D53

F32

FBC_D54

E32

FBC_D55

B29

FBC_D56

C29

FBC_D57

B31

FBC_D58

C31

FBC_D59

B32

FBC_D60

C32

FBC_D61

B34

FBC_D62

B35

FBC_D63

G11

FBC_RFU0

NC

G12

FBC_RFU1*

NC

G14

FBC_RFU2

NC

G15

FBC_RFU3*

NC

G24

FBC_RFU4

NC

G25

FBC_RFU5*

NC

G27

FBC_RFU6

NC

G28

FBC_RFU7*

NC

75 73 72

3

OMIT

U8000

NB9P-GS

BGA

SYMBOL 4 OF 9

FB_VREF_UNTERM

IN

FBC_CMD0
FBC_CMD1
FBC_CMD2
FBC_CMD3
FBC_CMD4
FBC_CMD5
FBC_CMD6
FBC_CMD7
FBC_CMD8

FBC_CMD9
FBC_CMD10
FBC_CMD11
FBC_CMD12
FBC_CMD13
FBC_CMD14
FBC_CMD15
FBC_CMD16
FBC_CMD17
FBC_CMD18
FBC_CMD19
FBC_CMD20
FBC_CMD21
FBC_CMD22
FBC_CMD23
FBC_CMD24
FBC_CMD25
FBC_CMD26
FBC_CMD27
FBC_CMD28
FBC_CMD29
FBC_CMD30

FBC_CLK0
FBC_CLK0*

FBC_CLK1
FBC_CLK1*

FBC_DQM0

FBC_DQM1

FBC_DQM2

FBC_DQM3

FBC_DQM4

FBC_DQM5

FBC_DQM6

FBC_DQM7

FBC_DQS_RN0
FBC_DQS_RN1
FBC_DQS_RN2
FBC_DQS_RN3
FBC_DQS_RN4
FBC_DQS_RN5
FBC_DQS_RN6
FBC_DQS_RN7

FBC_DQS_WP0
FBC_DQS_WP1
FBC_DQS_WP2
FBC_DQS_WP3
FBC_DQS_WP4
FBC_DQS_WP5
FBC_DQS_WP6
FBC_DQS_WP7

FB_DLLAVDD1
FB_PLLAVDD1

FBC_DEBUG

FB_VREF

C17

B19

D18

F21

A23

D21

B23

E20

G21

F20

F19

F23

A22

C22

B17

F24

C25

E22

C20

B22

A19

D22

D20

E19

D19

F18

C19

F22

C23

B20

A20

E17

D17

D23

E23

F11

D10

D15

A16

D27

D28

D34

A34

D9

B10

E14

B14

F26

A26

D31

A31

E10

A10

D14

C14

E26

B26

D32

A32

J19

J18

G19

J27

Q8295

SSM6N15FEAPE

SOT563

2

NO STUFF

FB_B_LMA<4>

FB_B_RAS_L

FB_B_LMA<5>

FB_B_BA<1>

FB_B_UMA<2>

FB_B_UMA<4>

FB_B_UMA<3>

FB_B_CS1_L

FB_B_CS0_L

FB_B_MA<11>

FB_B_CAS_L

FB_B_WE_L

FB_B_BA<0>

FB_B_UMA<5>

FB_B_MA<12>

FB_B_DRAM_RST

FB_B_MA<7>

FB_B_MA<10>

FB_B_CKE

FB_B_MA<0>

FB_B_MA<9>

FB_B_MA<6>

FB_B_LMA<2>

FB_B_MA<8>

FB_B_LMA<3>

FB_B_MA<1>

FB_B_MA<13>

FB_B_BA<2>

TP_FBC_CMD28

TP_FBC_CMD29

TP_FBC_CMD30

FB_B_CLK_P<0>

FB_B_CLK_N<0>

FB_B_CLK_P<1>

FB_B_CLK_N<1>

FB_B_DQM_L<0>

FB_B_DQM_L<1>

FB_B_DQM_L<2>

FB_B_DQM_L<3>

FB_B_DQM_L<4>

FB_B_DQM_L<5>

FB_B_DQM_L<6>

FB_B_DQM_L<7>

FB_B_RDQS<0>

FB_B_RDQS<1>

FB_B_RDQS<2>

FB_B_RDQS<3>

FB_B_RDQS<4>

FB_B_RDQS<5>

FB_B_RDQS<6>

FB_B_RDQS<7>

FB_B_WDQS<0>

FB_B_WDQS<1>

FB_B_WDQS<2>

FB_B_WDQS<3>

FB_B_WDQS<4>

FB_B_WDQS<5>

FB_B_WDQS<6>

FB_B_WDQS<7>

FBC_DEBUG

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm

6

D

SG

1

GPU_FB_VREF_UNTERM_L

21

95 80 73

OUT

95 80 73

OUT

95 80 73

OUT

95 80 73

7

OUT

95 80 73

OUT

95 80 73

OUT

95 80 73

OUT

95 80

OUT

95 73

7

OUT

95 80 73

7

OUT

95 80 73

7

OUT

95 80 73

OUT

95 80 73

OUT

95 80 73

OUT

95 80 73

OUT

95 80 73

OUT

95 80 73

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

75

OUT

75 75

75

75

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

95 80 73

1

95 80 73

R8251

10K

95 80 73

5%

1/16W

95 80 73

MF-LF

402

95 80 73

2

95 80 73

95 80 73

95 80 73 95 79 72

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

95 80 73

GPU_FB_VREF

NV G96 FRAME BUFFER I/F

SYNC_MASTER=K20_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

95 80 73

=PP1V1_GPU_FBPLLAVDD

71

8

NO STUFF

C8296

0.1uF

DRAWING NUMBER

D

NONE

10%
16V

X5R

402

1

R8250

10K

2

71

8

1

2

OUT

5%

1/16W

MF-LF

402

1

2

=PP1V8_GPU_FBIO

051-8071

SHT

C8290

0.1UF

20%
10V

CERM

402

R8294

NO STUFF

R8297

1.02K

95 80 73

1

60.4

1%
1/16W
MF-LF

402

2

1

1%

1/16W

MF-LF

402

2

1

C8291

0.1UF

20%
10V

2

CERM

402

R8295

1.07K

R8296

2.49K

SYNC_DATE=09/24/2008

REV.

OF

9871

D

C

B

1

1%

1/16W

MF-LF

402

2

1

1%

1/16W

MF-LF

402

2

A

B

8

76

5

4

3

2

1

87

www.vinafix.vn

6

5

4

OMIT

=PP1V8_GPU_FB_VDD

80 79 73 72

8

1

C8400

10UF

1

C8401

20%

6.3V

X5R

603

0.1uF

10%
16V

2

2

X5R
402

1

2

C8402

0.1uF

10%
16V
X5R
402

1

2

C8403

0.1uF

10%
16V
X5R
402

1

2

C8404

0.1uF

10%
16V
X5R
402

D

1

C8410

0.1uF

10%
16V

2

X5R

Connect to designated pin, then GND

80 79 73 72

C

B

A

=PP1V8_GPU_FB_VDDQ

9 8

1

C8420

10UF

20%

6.3V

X5R

603

=PP1V8_GPU_FB_VREF_A

72

9

R8440

95 79 72 71

95 79 72 71

95 79 71

95 79 71

95 79 71

95 79 71

95 79 72 71

95 79 72 71

95 79 72 71

95 79 72 71

95 79 72 71

95 79 72 71

95 79 72 71

95 79 71

95 79 71

95 72 71

95 79 72 71

95 79 72 71

95 79 72 71

95 79 72 71

95 79 71

95 79 71

95 79 71

95 79 71

95 79 71

95 79 71

95 79 71

95 79 71

95 79 72 71

95 79 72 71

95 79 72 71

FB_A_MA<0>

IN

FB_A_MA<1>

IN

FB_A_LMA<2>

IN

FB_A_LMA<3>

IN

FB_A_LMA<4>

IN

FB_A_LMA<5>

IN

FB_A_MA<6>

IN

FB_A_MA<7>

IN

FB_A_MA<8>

IN

FB_A_MA<9>

IN

FB_A_MA<10>

IN

FB_A_MA<11>

IN

FB_A_CKE

IN

FB_A_MA<12>

IN IN

FB_A_CLK_P<0>

IN

FB_A_CLK_N<0>

IN

FB_A_CS0_L

IN

FB_A_WE_L

IN

FB_A_CAS_L

IN

FB_A_RAS_L

IN

FB_A_DRAM_RST

IN

FB_A_RDQS<3>

OUT

FB_A_RDQS<2>

OUT

FB_A_RDQS<0>

OUT

FB_A_RDQS<1>

OUT

FB_A_WDQS<3>

IN

FB_A_WDQS<2>

IN

FB_A_WDQS<0>

IN

FB_A_WDQS<1>

IN

FB_A_BA<0>

IN

FB_A_BA<1>

IN

FB_A_BA<2> FB_A_BA<2>

IN

1

C8421

0.1uF

10%

2

1/16W
MF-LF

16V

2

X5R
402

VRAM4

1

1K

5%

402

2

R8430

R8431

1.33K

R8442

1

C8422

0.1uF

10%
16V

2

X5R
402

1

549

1%
1/16W
MF-LF

402

2

1

1%
1/16W
MF-LF

402

2

1

121

1%
1/16W
MF-LF

402

2

1

R8443

121

1%
1/16W
MF-LF
402

2

R8432

1/16W
MF-LF

VRAM4

VRAM4

931

1%

402

R8444

R8448

1

C8423

0.1uF

10%
16V

2

X5R
402

1

1

2

2

1

121

1%
1/16W
MF-LF

402

2

1

243

1%
1/16W
MF-LF

402

2

FB_A0_VREF

C8431

0.01UF

10%
16V
CERM
402

VRAM4

1

R8445

121

1%
1/16W
MF-LF
402

2

FB_A0_ZQ

FB_A0_MF

FB_A0_SEN

1

R8449

100

5%
1/16W
MF-LF
402

2

R8446

1

C8424

0.1uF

10%
16V

2

X5R
402

1

243

1%
1/16W
MF-LF

402

2

402

1

2

1

R8433

549

1%
1/16W
MF-LF

402

2

79 79

1

R8434

1.33K

1%
1/16W
MF-LF

402

2

FB_A_CLK0_TERM

VOLTAGE=0.9V

1

R8447

243

1%
1/16W
MF-LF
402

2

1

C8415

0.1uF

10%
16V

2

X5R
402

U8400.J12

1

K9

M9

K4

H2

K3

L4

K2

M4

L9

H9

J3

F4

H4

F9

A4

A9

V4

V9

D3

P3

D2

P2

G9

G4

H3

J2

R8435

931

1/16W
MF-LF

402

1

73 72 71

2

A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11
CKE

A12/CS1*

CK

CK*
CS0*
WE*
CAS*
RAS*

ZQ
MF
SEN

RESET

RDQS0
RDQS1
RDQS2
RDQS3

WDQS0
WDQS1

WDQS2
WDQS3

BA0
BA1
BA2

RFU

C8426

0.1uF

10%
16V

2

X5R
402

1

1

C8432

0.01UF

10%

1%

16V

2

CERM
402

2

FB_A2_VREF_UNTERM_L

FB_A0_VREF_UNTERM_L

FB_VREF_UNTERM

IN IN

75

OMIT

CRITICAL

DM0

U8400

DM1

BGA

(1 OF 2)

MFHIGH

MFHIGH

MFHIGH

DM2
DM3

DQ0
DQ1
DQ2
DQ3
DQ4

K4J10324QD-HC11

32MX32-900MHZ-MFH

DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

C8425

0.1uF

10%
16V
X5R
402

FB_A2_VREF FB_A3_VREF

C8446

0.01UF

10%
16V

CERM

402

H11

K10

K11

J11

J10

H10

D10

P10

D11

P11

NC NC

CRITICAL

A2

VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7

VDDA0
VDDA1

VDDQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21

VREF0
VREF1

E3

E10

N10

N3

B2

B3

C2

C3

E2

F3

F2

G3

B11

B10

C11

C10

E11

F10

F11

G10

M11

L10

N11

M10

R11

R10

T11

T10

M2

L3

N2

M3

R2

R3

T2

T3

U8400

(2 OF 2)

Q8400

SSM6N15FEAPE

BGA

32MX32-900MHZ-MFH

SOT563

2

FB_A_DQM_L<3>

FB_A_DQM_L<2>

FB_A_DQM_L<0>

FB_A_DQM_L<1>

FB_A_DQ<24>

FB_A_DQ<30>

FB_A_DQ<29>

FB_A_DQ<31>

FB_A_DQ<28>

FB_A_DQ<27>

FB_A_DQ<25>

FB_A_DQ<26>

FB_A_DQ<20>

FB_A_DQ<22>

FB_A_DQ<21>

FB_A_DQ<23>

FB_A_DQ<19>

FB_A_DQ<18>

FB_A_DQ<16>

FB_A_DQ<17>

FB_A_DQ<5>

FB_A_DQ<4>

FB_A_DQ<6>

FB_A_DQ<7>

FB_A_DQ<2>

FB_A_DQ<3>

FB_A_DQ<1>

FB_A_DQ<0>

FB_A_DQ<13>

FB_A_DQ<15>

FB_A_DQ<14>

FB_A_DQ<12>

FB_A_DQ<10>

FB_A_DQ<9>

FB_A_DQ<8>

FB_A_DQ<11>

A11

F1

F12

M1

M12

V2

V11

K1

K12

A1

A12

C1

C4

C9

C12

E1

E4

E9

E12

J4

J9

N1

N4

N9

N12

R1

R4

R9

R12

V1

V12

H1

H12

A3

VSS0

A10

VSS1

G1

VSS2

G12

VSS3

L1

VSS4

L12

VSS5

V3

VSS6

V10

VSS7

J1

VSSA0

K4J10324QD-HC11

J12

VSSA1

B1

VSSQ0

B4

VSSQ1

B9

VSSQ2

B12

VSSQ3

D1

VSSQ4

D4

VSSQ5

D9

VSSQ6

D12

VSSQ7

G2

VSSQ8

G11

VSSQ9

L2

VSSQ10

L11

VSSQ11

P1

VSSQ12

P4

VSSQ13

P9

VSSQ14

P12

VSSQ15

T1

VSSQ16

T4

VSSQ17

T9

VSSQ18

T12

VSSQ19

6

D

SG

1

Q8400

SSM6N15FEAPE

IN

IN

IN

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

SOT563

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

5

80 79 73 72

95 79 71

95 79 71

95 79 71

95 79 71

95 79 71

95 79 71

95 79 71

95 79 71

95 79 71

95 79 71

95 79 71

95 79 71

95 79 71

95 79 71

95 79 71

95 79 71

95 79 71

95 79 71

95 79 71

95 79 71

95 79 71

95 79 71

95 79 71

95 79 71

95 79 71

95 79 71

95 79 71

95 79 71

95 79 71

95 79 71

95 79 71

95 79 71

95 79 71

95 79 71

95 79 71

95 79 71

80 79 73 72

3

D

SG

4

95 79 72 71

95 79 72 71

95 79 72 71

95 79 72 71

95 79 72 71

95 79 72 71

95 79 72 71

95 79 72 71

95 79 72 71

95 79 72 71 95 79 72 71

95 79 72 71

95 79 72 71

95 79 72 71

95 79 72 71

95 79 72 71

95 79 72 71

95 79 72 71

=PP1V8_GPU_FB_VDD

8

=PP1V8_GPU_FB_VDDQ

9 8

=PP1V8_GPU_FB_VREF_A

72

9

95 79 71

95 79 71

95 79 71

95 79 71

95 79 71

95 79 71

95 72 71

95 79 71

95 79 71

95 79 71

95 79 71

95 79 71

95 79 71

95 79 71

95 79 71

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

C8470

10UF

6.3V

FB_A_MA<0>

FB_A_MA<1>

FB_A_UMA<2>

FB_A_UMA<3>

FB_A_UMA<4>

FB_A_UMA<5>

FB_A_MA<6>

FB_A_MA<7>

FB_A_MA<8>

FB_A_MA<9>

FB_A_MA<10>

FB_A_MA<11>

FB_A_CKE

FB_A_MA<12>

FB_A_CLK_P<1>

FB_A_CLK_N<1>

FB_A_CS0_L

FB_A_WE_L

FB_A_CAS_L

FB_A_RAS_L

FB_A_DRAM_RST

FB_A_RDQS<7>

FB_A_RDQS<5>

FB_A_RDQS<6>

FB_A_RDQS<4>

FB_A_WDQS<7>

FB_A_WDQS<5>

FB_A_WDQS<6>

FB_A_WDQS<4>

FB_A_BA<0>

FB_A_BA<1>

Connect to designated pin, then GND

1

1

20%

X5R

603

R8490

2

2

1

1K

5%
1/16W
MF-LF

402

2

C8471

0.1uF

10%
16V
X5R
402

R8480

R8481

VRAM4

R8492

1/16W
MF-LF

1.33K

1/16W
MF-LF

1/16W
MF-LF

1

20%

X5R

603

C8472

1

2

0.1uF

10%
16V
X5R
402

R8482

VRAM4

R8493

121

1%
1/16W
MF-LF
402

2

VRAM4

931

1/16W
MF-LF

402

R8494

R8498

1

C8451

0.1uF

10%
16V

2

X5R
402

1

2

1

1%

2

1

121

1%
1/16W
MF-LF

402

2

1

243

1%
1/16W
MF-LF

402

2

C8450

10UF

6.3V

1

2

1

549

1%

402

2

1

1%

402

2

1

121

1%

402

2

79 79

1

2

C8473

0.1uF

10%
16V
X5R
402

FB_A1_VREF

C8481

0.01uF

10%
16V
CERM
402

VRAM4

1

R8495

121

1%
1/16W
MF-LF
402

2

FB_A1_ZQ

FB_A1_MF

FB_A1_SEN

1

R8499

100

5%
1/16W
MF-LF
402

2

1

2

R8496

1/16W
MF-LF

C8452

0.1uF

10%
16V
X5R
402

1

2

243

1%

402

C8474

0.1uF

10%
16V
X5R
402

1

2

R8483

549

1/16W
MF-LF

402

R8484

1.33K

1/16W
MF-LF

402

FB_A_CLK1_TERM

VOLTAGE=0.9V

1

R8497

243

2

1

C8453

0.1uF

10%
16V

2

X5R
402

1

C8460

0.1uF

10%
16V

2

X5R
402

U8400.J1U8400.J1

1

C8475

0.1uF

10%
16V

2

X5R
402

1

1%

2

1

1%

2

1

C8496

0.01UF

10%
16V

2

CERM

402

1%
1/16W
MF-LF
402

K9

A0

H11

A1

K10

A2

M9

A3

K4

A4

H2

A5

K3

A6

L4

A7

K2

A8/AP

M4

A9

K11

A10

L9

A11

H9

CKE

J3

A12/CS1*

J11

CK

J10

CK*

F4

CS0*

H4

WE*

F9

CAS*

H10

RAS*

A4

ZQ

A9

MF

V4

SEN

V9

RESET

D3

RDQS0

D10

RDQS1

P10

RDQS2

P3

RDQS3

D2

WDQS0

D11

WDQS1

P11

WDQS2

P2

WDQS3

G9

BA0

G4

BA1

H3

BA2

J2

RFU

1

C8454

0.1uF

2

1

C8465

0.1uF

2

U8400.J12

R8485

931

1/16W
MF-LF

402

73 72 71

CRITICAL

10%
16V
X5R
402

10%
16V
X5R
402

MFHIGH

3

1

C8476

0.1uF

10%
16V

2

X5R
402

1

1

1%

2

2

75

OMIT

U8450

BGA

(1 OF 2)

32MX32-900MHZ-MFH

MFHIGH

MFHIGH

A2

A11

F1

F12

M1

M12

V2

V11

K1

K12

A1

A12

C1

C4

C9

C12

E1

E4

E9

E12

J4

J9

N1

N4

N9

N12

R1

R4

R9

R12

V1

V12

H1

H12

C8482

0.01uF

10%
16V
CERM
402

FB_A3_VREF_UNTERM_L

FB_A1_VREF_UNTERM_L

FB_VREF_UNTERM

DM0
DM1
DM2
DM3

DQ0
DQ1
DQ2
DQ3
DQ4

K4J10324QD-HC11

DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7

VDDA0
VDDA1

VDDQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21

VREF0
VREF1

E3

E10

N10

N3

B2

B3

C2

C3

E2

F3

F2

G3

B11

B10

C11

C10

E11

F10

F11

G10

M11

L10

N11

M10

R11

R10

T11

T10

M2

L3

N2

M3

R2

R3

T2

T3

OMIT

CRITICAL

U8450

(2 OF 2)

Q8450

SSM6N15FEAPE

VSS0
VSS1

BGA

VSS2
VSS3
VSS4
VSS5
VSS6
VSS7

VSSA0

K4J10324QD-HC11

VSSA1

32MX32-900MHZ-MFH

VSSQ0
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8

VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ15
VSSQ16
VSSQ17
VSSQ18
VSSQ19

6

D

SOT563

2

SG

1

FB_A_DQM_L<7>

FB_A_DQM_L<5>

FB_A_DQM_L<6>

FB_A_DQM_L<4>

FB_A_DQ<59>

FB_A_DQ<58>

FB_A_DQ<63>

FB_A_DQ<60>

FB_A_DQ<57>

FB_A_DQ<56>

FB_A_DQ<61>

FB_A_DQ<62>

FB_A_DQ<40>

FB_A_DQ<47>

FB_A_DQ<46>

FB_A_DQ<45>

FB_A_DQ<42>

FB_A_DQ<44>

FB_A_DQ<43>

FB_A_DQ<41>

FB_A_DQ<54>

FB_A_DQ<55>

FB_A_DQ<53>

FB_A_DQ<52>

FB_A_DQ<49>

FB_A_DQ<51>

FB_A_DQ<50>

FB_A_DQ<48>

FB_A_DQ<36>

FB_A_DQ<37>

FB_A_DQ<32>

FB_A_DQ<38>

FB_A_DQ<39>

FB_A_DQ<34>

FB_A_DQ<33>

FB_A_DQ<35>

A3

A10

G1

G12

L1

L12

V3

V10

J1

J12

B1

B4

B9

B12

D1

D4

D9

D12

G2

G11

L2

L11

P1

P4

P9

P12

T1

T4

T9

T12

SSM6N15FEAPE

21

Page Notes

Power aliases required by this page:

- =PP1V8_S0_FB_VDD

- =PP1V8_S0_FB_VREFA

Signal aliases required by this page:

(NONE)

BOM options provided by this page:

VRAM4

3

D

Q8450

SOT563

5

SG

4

95 79 71

IN

95 79 71

IN

95 79 71

IN

95 79 71

IN

95 79 71

7

BI

95 79 71

7

BI

95 79 71

7

BI

95 79 71

7

BI

95 79 71

7

BI

95 79 71

7

BI

95 79 71

7

BI

95 79 71

7

BI

95 79 71

7

BI

95 79 71

7

BI

95 79 71

7

BI

95 79 71

7

BI

95 79 71

7

BI

95 79 71

7

BI

95 79 71

7

BI

95 79 71

7

BI

95 79 71

7

BI

95 79 71

7

BI

95 79 71

7

BI

95 79 71

7

BI

95 79 71

7

BI

95 79 71

7

BI

95 79 71

7

BI

95 79 71

7

BI

95 79 71

7

BI

95 79 71

7

BI

BI

BI

BI

BI

BI

BI

7

7

7

7

7

7

95 79 71

SYNC_MASTER=M98_MLB

95 79 71

95 79 71

95 79 71

95 79 71

95 79 71

APPLE INC.

GDDR3 Frame Buffer A (Bottom)

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

051-8071

SHT

72 98

SYNC_DATE=04/01/2008

REV.

B

OF

D

C

B

A

8

76

5

4

3

2

1

87

www.vinafix.vn

6

OMIT

=PP1V8_GPU_FB_VDD =PP1V8_GPU_FB_VDD

80 79 73 72

8

1

C8500

10UF

1

C8501

20%

6.3V

X5R

603

0.1uF

10%
16V

2

2

X5R
402

1

2

C8502

0.1uF

10%
16V
X5R
402

1

2

C8503

0.1uF

10%
16V
X5R
402

1

2

C8504

0.1uF

10%
16V
X5R
402

D

1

C8510

0.1uF

10%
16V

2

X5R
402

Connect to designated pin, then GND

80 79 73 72

C

B

A

=PP1V8_GPU_FB_VDDQ

9 8

1

C8520

10UF

20%

6.3V

X5R

603

73

9

R8540

95 80 73 71

95 80 73 71

95 80 71

95 80 71

95 80 71

95 80 71

95 80 73 71

95 80 73 71

95 80 73 71

95 80 73 71

95 80 73 71

95 80 73 71

95 80 73 71

95 80 73 71 95 80 73 71

95 80 71

95 80 71

95 73 71

95 80 73 71

95 80 73 71

95 80 73 71

95 80 73 71

95 80 71

95 80 71

95 80 71

95 80 71

95 80 71

95 80 71

95 80 71

95 80 71

95 80 73 71

95 80 73 71

95 80 73 71

FB_B_MA<0>

IN

FB_B_MA<1>

IN

FB_B_LMA<2>

IN

FB_B_LMA<3>

IN

FB_B_LMA<4>

IN

FB_B_LMA<5>

IN

FB_B_MA<6>

IN

FB_B_MA<7>

IN

FB_B_MA<8>

IN

FB_B_MA<9>

IN

FB_B_MA<10>

IN

FB_B_MA<11>

7

IN

FB_B_CKE

IN

FB_B_MA<12>

FB_B_CLK_P<0>

IN

FB_B_CLK_N<0>

IN

FB_B_CS0_L

7

IN

FB_B_WE_L

IN

FB_B_CAS_L

7

IN

FB_B_RAS_L

IN

FB_B_DRAM_RST

IN

FB_B_RDQS<1>

OUT

FB_B_RDQS<0>

OUT

FB_B_RDQS<2>

OUT

FB_B_RDQS<3>

OUT

FB_B_WDQS<1>

IN

FB_B_WDQS<0>

IN

FB_B_WDQS<2>

IN

FB_B_WDQS<3>

IN

FB_B_BA<0>

IN

FB_B_BA<1>

7

IN

FB_B_BA<2>

IN

1

C8521

0.1uF

10%

2

1/16W
MF-LF

16V

2

X5R
402

VRAM4

1

1K

5%

402

2

R8530

R8531

1.33K

R8542

1

C8522

0.1uF

10%
16V

2

X5R
402

1

549

1%
1/16W
MF-LF

402

2

1

1%
1/16W
MF-LF

402

2

1

121

1%
1/16W
MF-LF

402

2

1

R8543

121

1%
1/16W
MF-LF
402

2

R8532

1/16W
MF-LF

VRAM4

VRAM4

1

C8523

0.1uF

10%
16V

2

X5R
402

80 80

1

1

931

1%

2

402

2

1

R8544

121

1%
1/16W
MF-LF

402

2

1

R8548

243

1%
1/16W
MF-LF

402

2

FB_B0_VREF

C8531

0.01uF

10%
16V
CERM
402

VRAM4

1

R8545

121

1%
1/16W
MF-LF
402

2

FB_B0_ZQ

FB_B0_SEN

1

R8549

100

5%
1/16W
MF-LF
402

2

R8546

FB_B0_MF

1

2

243

1%
1/16W
MF-LF

402

U8500.J1

C8524

0.1uF

10%
16V
X5R
402

1

2

1

2

1

R8533

549

1%
1/16W
MF-LF

402

2

80 80

1

R8534

1.33K

1%
1/16W
MF-LF

402

2

FB_B_CLK0_TERM FB_B_CLK1_TERM

VOLTAGE=0.9V

C8546

0.01UF

1

R8547

243

1%
1/16W
MF-LF
402

2

1

C8515

0.1uF

10%
16V

2

X5R
402

U8500.J12

1

1

2

K9

H11

K10

M9

K4

H2

K3

L4

K2

M4

K11

L9

H9

J3

J11

J10

F4

H4

F9

H10

A4

A9

V4

V9

D3

D10

P10

P3

D2

D11

P11

P2

G9

G4

H3

J2

C8526

0.1uF

10%
16V

2

X5R
402

1

1

R8535

1/16W
MF-LF

73 72 71

A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11
CKE

A12/CS1*

CK

CK*
CS0*
WE*
CAS*
RAS*

ZQ
MF
SEN

RESET

RDQS0
RDQS1
RDQS2
RDQS3

WDQS0
WDQS1

WDQS2
WDQS3

BA0
BA1
BA2

C8532

0.01uF

931

10%

1%

16V

2

CERM
402

402

2

FB_B2_VREF_UNTERM_L

FB_B0_VREF_UNTERM_L FB_B1_VREF_UNTERM_L

FB_VREF_UNTERM

IN IN

75

OMIT

CRITICAL

DM0

U8500

DM1

BGA

(1 OF 2)

MFHIGH

MFHIGH

MFHIGH

DM2
DM3

DQ0
DQ1
DQ2
DQ3
DQ4

K4J10324QD-HC11

32MX32-900MHZ-MFH

DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

RFU

C8525

0.1uF

10%
16V
X5R
402

FB_B2_VREF FB_B3_VREF

10%
16V

CERM

402

NC NC

CRITICAL

A2

VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7

VDDA0
VDDA1

VDDQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21

VREF0
VREF1

E3

E10

N10

N3

B2

B3

C2

C3

E2

F3

F2

G3

B11

B10

C11

C10

E11

F10

F11

G10

M11

L10

N11

M10

R11

R10

T11

T10

M2

L3

N2

M3

R2

R3

T2

T3

U8500

(2 OF 2)

Q8500

SSM6N15FEAPE

BGA

32MX32-900MHZ-MFH

SOT563

2

FB_B_DQM_L<1>

FB_B_DQM_L<0>

FB_B_DQM_L<2>

FB_B_DQM_L<3>

FB_B_DQ<12>

FB_B_DQ<8>

FB_B_DQ<11>

FB_B_DQ<10>

FB_B_DQ<13>

FB_B_DQ<15>

FB_B_DQ<14>

FB_B_DQ<9>

FB_B_DQ<6>

FB_B_DQ<5>

FB_B_DQ<3>

FB_B_DQ<4>

FB_B_DQ<0>

FB_B_DQ<2>

FB_B_DQ<1>

FB_B_DQ<7>

FB_B_DQ<21>

FB_B_DQ<16>

FB_B_DQ<19>

FB_B_DQ<17>

FB_B_DQ<20>

FB_B_DQ<22>

FB_B_DQ<18>

FB_B_DQ<23>

FB_B_DQ<26>

FB_B_DQ<27>

FB_B_DQ<31>

FB_B_DQ<28>

FB_B_DQ<24>

FB_B_DQ<25>

FB_B_DQ<29>

FB_B_DQ<30>

A11

F1

F12

M1

M12

V2

V11

K1

K12

A1

A12

C1

C4

C9

C12

E1

E4

E9

E12

J4

J9

N1

N4

N9

N12

R1

R4

R9

R12

V1

V12

H1

H12

A3

VSS0

A10

VSS1

G1

VSS2

G12

VSS3

L1

VSS4

L12

VSS5

V3

VSS6

V10

VSS7

J1

VSSA0

K4J10324QD-HC11

J12

VSSA1

B1

VSSQ0

B4

VSSQ1

B9

VSSQ2

B12

VSSQ3

D1

VSSQ4

D4

VSSQ5

D9

VSSQ6

D12

VSSQ7

G2

VSSQ8

G11

VSSQ9

L2

VSSQ10

L11

VSSQ11

P1

VSSQ12

P4

VSSQ13

P9

VSSQ14

P12

VSSQ15

T1

VSSQ16

T4

VSSQ17

T9

VSSQ18

T12

VSSQ19

6

D

SG

1

Q8500

SSM6N15FEAPE

IN

IN

IN

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

SOT563

5

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7
95

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

80 79 73 72

80 79 73 72

3

D

SG

4

95 80 73 71

95 80 71

95 80 73 71

95 80 71

95 80 71

95 80 71

95 80 71

95 80 71

95 80 73 71

95 80 71

95 80 73 71

95 80 71

95 80 73 71

95 80 71

95 80 73 71

95 80 71

95 80 73 71

95 80 71

95 80 73 71

95 80 71

95 80 73 71

95 80 71

95 80 71

95 80 71

95 80 71

95 73 71

95 80 71

95 80 73 71

95 80 71

95 80 73 71

80 71

95 80 73 71

95 80 71

95 80 71

95 80 71

95 80 71

95 80 73 71

95 80 71

95 80 71

95 80 71

95 80 71

95 80 71

95 80 71

95 80 71

95 80 71

95 80 71

95 80 71

95 80 71

95 80 73 71

95 80 71

95 80 73 71

95 80 71

95 80 73 71

5

9 8

73

95 80 71

95 80 71

95 80 71

95 80 71

95 80 71

95 80 71

95 80 71

95 80 71

95 80 71

95 80 71

95 80 71

95 80 71

95 80 71

95 80 71

8

9

=PP1V8_GPU_FB_VDDQ

=PP1V8_GPU_FB_VREF_B=PP1V8_GPU_FB_VREF_B

FB_B_MA<0>

IN

FB_B_MA<1>

IN

FB_B_UMA<2>

IN

FB_B_UMA<3>

IN

FB_B_UMA<4>

IN

FB_B_UMA<5>

IN

FB_B_MA<6>

IN

FB_B_MA<7>

IN

FB_B_MA<8>

IN

FB_B_MA<9>

IN

FB_B_MA<10>

IN

FB_B_MA<11>

7

IN

FB_B_CKE

IN

FB_B_MA<12>

ININ

FB_B_CLK_P<1>

IN

FB_B_CLK_N<1>

IN

FB_B_CS0_L

7

IN

FB_B_WE_L

IN

FB_B_CAS_L

7

IN

FB_B_RAS_L

IN

FB_B_DRAM_RST

IN

FB_B_RDQS<6>

OUT

FB_B_RDQS<5>

OUT

FB_B_RDQS<4>

OUT

FB_B_RDQS<7>

OUT

FB_B_WDQS<6>

IN

FB_B_WDQS<5>

IN

FB_B_WDQS<4>

IN

FB_B_WDQS<7>

IN

FB_B_BA<0>

IN

FB_B_BA<1>

7

IN

FB_B_BA<2>

IN

C8570

10UF

Connect to designated pin, then GND

1

20%

6.3V
2

X5R

603

1

R8590

1K

5%
1/16W
MF-LF

402

2

1

2

C8571

0.1uF

10%
16V
X5R
402

R8580

R8581

VRAM4

R8592

1/16W
MF-LF

1.33K

1/16W
MF-LF

1/16W
MF-LF

4

3

OMIT

CRITICAL

A2

VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7

VDDA0
VDDA1

VDDQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21

VREF0
VREF1

E3

E10

N10

N3

B2

B3

C2

C3

E2

F3

F2

G3

B11

B10

C11

C10

E11

F10

F11

G10

M11

L10

N11

M10

R11

R10

T11

T10

M2

L3

N2

M3

R2

R3

T2

T3

U8550

(2 OF 2)

Q8550

SSM6N15FEAPE

BGA

32MX32-900MHZ-MFH

SOT563

2

FB_B_DQM_L<6>

FB_B_DQM_L<5>

FB_B_DQM_L<4>

FB_B_DQM_L<7>

FB_B_DQ<49>

FB_B_DQ<50>

FB_B_DQ<48>

FB_B_DQ<51>

FB_B_DQ<53>

FB_B_DQ<55>

FB_B_DQ<54>

FB_B_DQ<52>

FB_B_DQ<41>

FB_B_DQ<42>

FB_B_DQ<40>

FB_B_DQ<47>

FB_B_DQ<44>

FB_B_DQ<45>

FB_B_DQ<43>

FB_B_DQ<46>

FB_B_DQ<34>

FB_B_DQ<35>

FB_B_DQ<33>

FB_B_DQ<32>

FB_B_DQ<37>

FB_B_DQ<38>

FB_B_DQ<39>

FB_B_DQ<36>

FB_B_DQ<56>

FB_B_DQ<57>

FB_B_DQ<63>

FB_B_DQ<59>

FB_B_DQ<58>

FB_B_DQ<62>

FB_B_DQ<61>

FB_B_DQ<60>

1

20%

X5R

603

C8572

1

2

0.1uF

10%
16V
X5R
402

R8582

VRAM4

R8593

121

1%
1/16W
MF-LF
402

2

VRAM4

931

1/16W
MF-LF

402

R8594

R8598

1

C8551

0.1uF

10%
16V

2

X5R
402

1

2

1

1%

2

1

121

1%
1/16W
MF-LF

402

2

1

243

1%
1/16W
MF-LF

402

2

C8550

10UF

6.3V

1

2

1

549

1%

402

2

1

1%

402

2

1

121

1%

402

2

C8573

0.1uF

10%
16V
X5R
402

FB_B1_VREF

1

C8581

0.01uF

10%
16V

2

CERM
402

1

2

VRAM4

R8595

121

1%
1/16W
MF-LF
402

1

R8599

100

5%
1/16W
MF-LF
402

2

R8596

FB_B1_ZQ

FB_B1_MF

FB_B1_SEN

1

2

1/16W
MF-LF

C8552

0.1uF

10%
16V
X5R
402

1

2

243

1%

402

C8574

0.1uF

10%
16V
X5R
402

1

2

R8583

1/16W
MF-LF

R8584

1.33K

1/16W
MF-LF

1

2

1

2

1

549

1%

402

2

1

1%

402

2

VOLTAGE=0.9V

1

R8597

243

1%
1/16W
MF-LF
402

2

C8553

0.1uF

10%
16V
X5R
402

C8560

0.1uF

10%
16V
X5R
402

U8500.J1

1

2

C8596

0.01UF

C8575

0.1uF

10%
16V
X5R
402

10%
16V

CERM

402

K9

H11

K10

M9

K4

H2

K3

L4

K2

M4

K11

L9

H9

J3

J11

J10

F4

H4

F9

H10

A4

A9

V4

V9

D3

D10

P10

P3

D2

D11

P11

P2

G9

G4

H3

J2

R8585

1

73 72 71

2

A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11
CKE

A12/CS1*

CK

CK*
CS0*
WE*
CAS*
RAS*

ZQ
MF
SEN

RESET

RDQS0
RDQS1
RDQS2
RDQS3

WDQS0
WDQS1

WDQS2
WDQS3

BA0
BA1
BA2

RFU

1

C8554

0.1uF

10%
16V

2

X5R
402

1

C8565

0.1uF

10%
16V

2

X5R
402

U8500.J12

1

2

931

1%
1/16W
MF-LF

402

75

CRITICAL

MFHIGH

MFHIGH

C8576

0.1uF

10%
16V
X5R
402

1

2

OMIT

(1 OF 2)

MFHIGH

U8550

BGA

32MX32-900MHZ-MFH

A11

F1

F12

M1

M12

V2

V11

K1

K12

A1

A12

C1

C4

C9

C12

E1

E4

E9

E12

J4

J9

N1

N4

N9

N12

R1

R4

R9

R12

V1

V12

H1

H12

1

C8582

0.01uF

10%
16V

2

CERM
402

FB_B3_VREF_UNTERM_L

FB_VREF_UNTERM

DM0
DM1
DM2
DM3

DQ0
DQ1
DQ2
DQ3
DQ4

K4J10324QD-HC11

DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

A3

VSS0

A10

VSS1

G1

VSS2

G12

VSS3

L1

VSS4

L12

VSS5

V3

VSS6

V10

VSS7

J1

VSSA0

K4J10324QD-HC11

J12

VSSA1

B1

VSSQ0

B4

VSSQ1

B9

VSSQ2

B12

VSSQ3

D1

VSSQ4

D4

VSSQ5

D9

VSSQ6

D12

VSSQ7

G2

VSSQ8

G11

VSSQ9

L2

VSSQ10

L11

VSSQ11

P1

VSSQ12

P4

VSSQ13

P9

VSSQ14

P12

VSSQ15

T1

VSSQ16

T4

VSSQ17

T9

VSSQ18

T12

VSSQ19

6

D

SG

1

SSM6N15FEAPE

21

Page Notes

Power aliases required by this page:

- =PP1V8_S0_FB_VDD

- =PP1V8_S0_FB_VREF_B

Signal aliases required by this page:

(NONE)

BOM options provided by this page:

VRAM4

3

D

Q8550

SOT563

5

SG

4

95 80 71

IN

95 80 71

IN

95 80 71

IN

95 80 71

IN

95 80 71

7

BI

95 80 71

7

BI

95 80 71

7

BI

95 80 71

7

BI

95 80 71

7

BI

95 80 71

7

BI

95 80 71

7

BI

95 80 71

7

BI

95 80 71

7

BI

95 80 71

7

BI

95 80 71

7

BI

95 80 71

7

BI

95 80 71

7

BI

95 80 71

7

BI

95 80 71

7

BI

95 80 71

7

BI

95 80 71

7

BI

95 80 71

7

BI

95 80 71

7

BI

95 80 71

7

BI

95 80 71

7

BI

95 80 71

7

BI

95 80 71

7

BI

95 80 71

7

BI

95 80 71

7

BI

95 80 71

7

BI

95 80 71

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

95 80 71

95 80 71

95 80 71

95 80 71

95 80 71

SYNC_MASTER=M98_MLB

APPLE INC.

GDDR3 Frame Buffer B (Bottom)

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

051-8071

SHT

73 98

SYNC_DATE=04/01/2008

REV.

OF

D

C

B

A

B

8

76

5

4

3

2

1

Power aliases required by this page:

www.vinafix.vn

- =PP3V3_GPU_VDD33

- =PP3V3_GPI_MIO

- =PP1V2_GPU_PLLVDD

- =PP1V2_GPU_H_PLLVDD

- =PP1V2_GPU_VID_PLLVDD

Signal aliases required by this page:

(NONE)

BOM options provided by this page:

(NONE)

D

75 74

8 6

C

B

A

87

Page Notes

=PP3V3_GPU_VDD33

=PP3V3_GPU_MIO

75 74

8

=PP1V1_GPU_PLLVDD

8

=PP1V1_GPU_H_PLLVDD

8

=PP1V1_GPU_VID_PLLVDD

8

Typically <??mA

1

2

R8620

49.9

1/16W

MF-LF

402

R8622

49.9

1/16W

MF-LF

402

C8600

0.47UF

10%

6.3V

CERM-X5R

402

1

1%

2

1

1%

2

C8633

C8637

C8643

4.7UF

4.7UF

4.7UF

20%

6.3V

CERM

603

20%

6.3V

CERM

603

20%

6.3V

CERM

603

1

R8621

49.9

1%

1/16W

MF-LF

402

2

GPU_MIOA_PD_VDDQ

GPU_MIOB_PD_VDDQ

GPU_MIOA_PU_GND

GPU_MIOB_PU_GND

1

R8623

49.9

1%

1/16W

MF-LF

402

2

1

2

1

2

1

2

1

C8601

0.47UF

10%

6.3V

2

CERM-X5R

402

CRITICAL

L8630

FERR-220-OHM

0402

CRITICAL

L8635

FERR-220-OHM

0402

CRITICAL

L8640

FERR-220-OHM

0402

75 74

1

2

=PP3V3_GPU_MIO

8

21

PP1V1_GPU_PLLVDD_F

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.2V

21

PP1V1_GPU_H_PLLVDD_F

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.2V

21

PP1V1_GPU_VID_PLLVDD_F

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.2V

C8602

0.47UF

10%

6.3V

CERM-X5R

402

74

74

74

74

1

2

1

2

C8690

0.022UF

10%
16V
CERM-X5R
402

C8691

0.022UF

10%
16V
CERM-X5R
402

R8616

R8617

10K

1/16W

MF-LF

402

10K

1/16W

MF-LF

402

C8630

C8635

C8640

5%

5%

4.7UF

4.7UF

4.7UF

75 74

1

2

1

2

20%

6.3V

CERM

603

20%

6.3V

CERM

603

20%

6.3V

CERM

603

8 6

1

2

1

2

1

2

6

110mA

=PP3V3_GPU_VDD33

1

C8692

0.022UF

10%
16V

2

CERM-X5R
402

1

C8693

0.022UF

10%
16V

2

CERM-X5R
402

1

C8617

0.1uF

10%
16V

2

X5R

402

65mA

1

C8631

0.1uF

10%
16V

2

X5R

402

25mA

1

C8636

0.1uF

10%
16V

2

X5R

402

50mA

1

C8641

0.1uF

10%
16V

2

X5R

402

1

2

1

2

1

R8618

10K

2

1

R8619

10K

2

C8694

0.1UF

20%
10V
CERM
402

C8695

0.1UF

20%
10V
CERM
402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

1

R8696

40.2K

1%
1/16W
MF-LF
402

2

1

2

1

2

1

2

C8619

0.1uF

10%
16V

X5R

402

C8696

0.47UF

10%

6.3V
CERM-X5R
402

C8697

0.47UF

10%

6.3V
CERM-X5R
402

1

R8697

40.2K

1%
1/16W
MF-LF
402

2

1

R8660

10K

5%
1/16W
MF-LF
402

2

1

2

C8698

1UF

10%

6.3V

CERM
402

75

75

75

75

GPU_ROM_CS_L

75

GPU_ROM_SCLK

75

GPU_ROM_SI

75

GPU_ROM_SO

75

C8610

GPU_TESTMODE_PD

GPU_MIOA_VREF

GPU_MIOB_VREF

GPU_MIOA_PD_VDDQ

74

GPU_MIOA_PU_GND

74

GPU_MIOB_PD_VDDQ

74

GPU_MIOB_PU_GND

74

IN

OUT

OUT

IN

5

GPU_STRAP_REF_3V3_PD

GPU_STRAP_REF_MIOB_PD

1

1UF

10%

6.3V
2

CERM

402

GPU_XTALIN

GPU_XTALOUT

GPU_XTALOUTBUFF

GPU_XTALSSIN

C8611

4

OMIT

U8000

NB9P-GS

BGA

ROM_CS*

SYMBOL 6 OF 9

(IPD)

MIOA_CLKOUT*

MIOB_CLKOUT

MIOB_CLKOUT*

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23

HDA_SDI

HDA_SDO
HDA_SYNC
HDA_BCLK
HDA_RST*

SPDIF

BUFRST*

JTAG_TCK

JTAG_TDI
JTAG_TDO
JTAG_TMS

JTAG_TRST*

MIOA_CLKIN

MIOA_CLKOUT

MIOA_CTL3

MIOA_DE
MIOA_D0
MIOA_D1
MIOA_D2
MIOA_D3
MIOA_D4
MIOA_D5
MIOA_D6
MIOA_D7
MIOA_D8

MIOA_D9
MIOA_D10
MIOA_D11
MIOA_D12
MIOA_D13
MIOA_D14

MIOA_HSYNC
MIOA_VSYNC

MIOB_CLKIN

MIOB_CTL3

MIOB_DE

MIOB_D0

MIOB_D1

MIOB_D2

MIOB_D3

MIOB_D4

MIOB_D5

MIOB_D6

MIOB_D7

MIOB_D8

MIOB_D9
MIOB_D10
MIOB_D11
MIOB_D12
MIOB_D13
MIOB_D14
MIOB_D15
MIOB_D16
MIOB_D17

MIOB_HSYNC
MIOB_VSYNC

THERMDP

THERMDN

PGOOD_OUT*

K1

K2

K3

H3

H2

H1

H4

H5

H6

J7

K4

K5

H7

J4

J6

L1

L2

L4

M4

L7

L5

K6

L6

M6

C7

B7

A7

D7

D6

A5

A4

AP14

AN14

AN16

AR14

AP16

N4

R4

T4

P5

N2

N1

P4

P1

P2

P3

T3

T2

T1

U4

U1

U2

U3

R6

T6

N6

N3

L3

AE1

V4

W4

W3

Y5

Y1

Y2

Y3

AB3

AB2

AB1

AC4

AC1

AC2

AC3

AE3

AE2

U6

W6

Y6

W5

W7

V7

W1

W2

B5

B4

C5

GPU_GPIO_0

GPU_GPIO_1

GPU_GPIO_2

GPU_GPIO_3

GPU_GPIO_4

GPU_GPIO_5

GPU_GPIO_6

GPU_GPIO_7

GPU_GPIO_8

GPU_GPIO_9

GPU_GPIO_10

GPU_GPIO_11

GPU_GPIO_12

GPU_GPIO_13

GPU_GPIO_14

GPU_GPIO_15

GPU_GPIO_16

GPU_GPIO_17

GPU_GPIO_18

GPU_GPIO_19

GPU_GPIO_20

GPU_GPIO_21

GPU_GPIO_22

GPU_GPIO_23

GPU_HDA_SDI

GPU_HDA_SDO

GPU_HDA_SYNC

GPU_HDA_BCLK

GPU_HDA_RST_L

GPU_SPDIF

TP_GPU_BUFRST_L

GPU_JTAG_TCK

GPU_JTAG_TDI

GPU_JTAG_TDO

GPU_JTAG_TMS

GPU_JTAG_TRST_L

GPU_MIOA_CLKIN

GPU_MIOA_CLKOUT_P

GPU_MIOA_CLKOUT_N

GPU_MIOA_CTL3

GPU_MIOA_DE

GPU_MIOA_D<0>

GPU_MIOA_D<1>

GPU_MIOA_D<2>

GPU_MIOA_D<3>

GPU_MIOA_D<4>

GPU_MIOA_D<5>

GPU_MIOA_D<6>

GPU_MIOA_D<7>

GPU_MIOA_D<8>

GPU_MIOA_D<9>

GPU_MIOA_D<10>

GPU_MIOA_D<11>

GPU_MIOA_D<12>

GPU_MIOA_D<13>

GPU_MIOA_D<14>

GPU_MIOA_HSYNC

GPU_MIOA_VSYNC

GPU_MIOB_CLKIN

GPU_MIOB_CLKOUT_P

GPU_MIOB_CLKOUT_N

GPU_MIOB_CTL3

GPU_MIOB_DE

GPU_MIOB_D<0>

GPU_MIOB_D<1>

GPU_MIOB_D<2>

GPU_MIOB_D<3>

GPU_MIOB_D<4>

GPU_MIOB_D<5>

GPU_MIOB_D<6>

GPU_MIOB_D<7>

GPU_MIOB_D<8>

GPU_MIOB_D<9>

GPU_MIOB_D<10>

GPU_MIOB_D<11>

GPU_MIOB_D<12>

GPU_MIOB_D<13>

GPU_MIOB_D<14>

GPU_STRAP<0>

GPU_STRAP<1>

GPU_STRAP<2>

GPU_MIOB_HSYNC

GPU_MIOB_VSYNC

GPU_THERMD_P

GPU_THERMD_N

TP_GPU_PGOOD_OUT_L

J9

VDD33_1

J10

VDD33_2

J11

VDD33_3

J12

VDD33_4

J13

VDD33_5

J25

RFU0

NC

J26

RFU1

NC

AK14

RFU0_GND

K9

RFU1_GND

C3

D4

ROM_SCLK

D3

ROM_SI

C4

ROM_SO

N9

STRAP_REF_3V3

M9

STRAP_REF_MIOB

P9

MIOA_VDDQ_1

R9

MIOA_VDDQ_2

1

1UF

10%

6.3V
2

CERM

402

T9

MIOA_VDDQ_3

U9

MIOA_VDDQ_4

AA9

MIOB_VDDQ_1

AB9

MIOB_VDDQ_2

W9

MIOB_VDDQ_3

Y9

MIOB_VDDQ_4

AP35

TESTMODE

N5

MIOA_VREF

AF1

MIOB_VREF

U5

MIOA_CAL_PD_VDDQ

T5

MIOA_CAL_PU_GND

AA7

MIOB_CAL_PD_VDDQ

AA6

MIOB_CAL_PU_GND

AF9

SP_PLLVDD

AE9

PLLVDD

AD9

VID_PLLVDD

B1

XTAL_IN

B2

XTAL_OUT

D1

XTAL_OUTBUFF

D2

XTAL_SSIN

3

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

OUT

75

OUT

75

OUT

75

OUT

75

OUT

75

IN

7

OUT

6

IN

6

IN

6

OUT

6

IN

6

IN

75

IN

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

IN

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

IN

75

OUT

7

OUT

21

D

C

B

NV G96 GPIO/MIO/MISC

SYNC_MASTER=K20_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

D

NONE

DRAWING NUMBER

051-8071

SHT

74

SYNC_DATE=09/24/2008

REV.

OF

98

A

B

8

76

5

4

3

2

1

87

www.vinafix.vn

6

5

4

3

Renamed signals

Native Func

GPU_GPIO_0

74

GPU_GPIO_1

74

GPU_GPIO_2

74

GPU_GPIO_3

74

GPU_GPIO_4

74

GPU_GPIO_5

74

D

GPU_GPIO_6

74

GPU_GPIO_7

74

GPU_GPIO_8

74

GPU_GPIO_9

74

GPU_GPIO_10

74

GPU_GPIO_11

74

GPU_GPIO_12

74

GPU_GPIO_13

74

GPU_GPIO_14

74

GP

HPDC

LCD0_BL_PWM

LCD0_VDD

LCD0_BL_EN

VID0

VID1

VID2/MEM_VID

THERM

FAN_PWM

MEM_VREF

SLI_SYNC

AC_DET

PWR_CTL0

PWR_CTL1

Config Straps

=PP3V3_GPU_MIO

8

75 74

OMIT

R8707

C

GPU_ROM_SI

74

OUT

GPU_ROM_SO

74

IN

GPU_ROM_SCLK

74

IN

OMIT

R8708

75 74

8

=PP3V3_GPU_MIO

R8701

GPU_STRAP<0>

74

BI

GPU_STRAP<1>

74

BI

GPU_STRAP<2>

74

B

BI

NO STUFF

R8702

=PP3V3_GPU_VDD33

75 74

8 6

DP_CA_DET_EG_FET

EG_DP_CA_DET

75

A

2.0K

1/16W
MF-LF

45.3K

1/16W
MF-LF

45.3K

1/16W
MF-LF

2.0K

1/16W
MF-LF

GPIOs

9

9

75 74

IN

BI

IN

BI

84

GPU_GPIO_15

74

GPU_GPIO_16

74

GPU_GPIO_17

74

GPU_GPIO_18

74

GPU_GPIO_19

74

GPU_GPIO_20

74

GPU_GPIO_21

74

GPU_GPIO_22

74

GPU_GPIO_23

74

78

8 7

8 6

DP_EG_DDC_CLK

DP_EG_DDC_DATA

DP_IG_DDC_CLK

DP_IG_DDC_DATA

84 82 81

DESCRIPTION

RES,MTL FILM,1/16W,45.3K,1,0402,SMD,LF

RES,MTL FILM,1/16W,45.3K,1,0402,SMD,LF

RES,MTL FILM,1/16W,35.7K,1,0402,SMD,LF

=PP3V3_S0_DDC_LCD

=PP3V3_GPU_VDD33

NC_GPU_GPIO_0

MAKE_BASE=TRUE

DP_EG_HPD

MAKE_BASE=TRUE

TP_LVDS_EG_BKL_PWM

MAKE_BASE=TRUE

EG_LCD_PWR_EN

MAKE_BASE=TRUE

EG_BKLT_EN

MAKE_BASE=TRUE

TP_GPU_GSTATE<0>

MAKE_BASE=TRUE

TP_GPU_GSTATE<1>

MAKE_BASE=TRUE

GPIO7_FBVDD_ALTVO

MAKE_BASE=TRUE

SMC_GFX_OVERTEMP_R_L

MAKE_BASE=TRUE

SMC_GFX_THROTTLE_R_L

MAKE_BASE=TRUE

FB_VREF_UNTERM

MAKE_BASE=TRUE

GPU_VCORE_VID0

MAKE_BASE=TRUE

GPU_VCORE_VID1

MAKE_BASE=TRUE

GPU_VCORE_VID2

MAKE_BASE=TRUE

TP_GPU_VCORE_VID3

MAKE_BASE=TRUE

NO STUFF

R8709

NO STUFF

R8710

NO STUFF

R8703

R8704

R8742

4.99K

100K

1/16W
MF-LF

1/16W
MF-LF

2.0K

1/16W
MF-LF

1/16W
MF-LF

1/16W
MF-LF

1

1%

402

2

1

5%

402

2

1

10K

1%

402

2

1

10K

1%

402

2

1

1%

402

2

1

5%

402

2

1

1%

402

2

1

1%

402

2

1

5%

402

2

R8711

R8712

NO STUFF

R8705

R8706

1

4.99K

1%
1/16W
MF-LF

402

2

1

15.0K

1%
1/16W
MF-LF

402

2

1

10K

1%
1/16W
MF-LF

402

2

1

45.3K

1%
1/16W
MF-LF

402

2

DP_CA_DET_EG_FET

Q8742

SOD-VESM-HF

SSM3K15FV

1

GS

2

R8743

0

5%

1/16W
MF-LF

402

DP_CA_DET_EG_PLD

NO_TEST=TRUE

Physical
Strapping Pin

ROM_SO

ROM_SCLK

ROM_SI

STRAP 2

STRAP 1

STRAP 0

Strap S1/S2 Bit[3:0] PU/PD Rval
0 0000 PD 5k
1 0001 PD 10k
2 0010 PD 15k
3 0011 PD 20k
4 0100 PD 25k
5 0101 PD 30k
6 0110 PD 35k
7 0111 PD 45k

PART NUMBER

114S0378

114S0378

114S0368

D

DP_CA_DET

3

21

DP_CA_DET_EG

81

IN

7

84 75

84 75

7

7

83 75

75

75

77

OUT

77

OUT

77

OUT

7

QTY

75 73 72 71

Strapping Bit 3

XCLK_277

PCI_DEVID[4]

RAMCFG[3]

PCI_DEVID[3]

3GIO_PADCFG[3]

USER[3]

1

1

1

81 75

81 75

81

81

IN

IN

Native Func

HPDE

DVI_MODE0

HDMI_DETECT0

DVI_MODE1

HDMI_DETECT1

HPDD

HPDF

SWAPRDY_A

GP

Strapping Bit 2

TVMODE[2]

SUB_VENDOR

RAMCFG[2]

PCI_DEVID[2]

3GIO_PADCFG[2]

USER[2]

Strap S1/S2 Bit[3:0] PU/PD Rval
8 1000 PU 5k
9 1001 PU 10k
A 1010 PU 15k
B 1011 PU 20k
C 1100 PU 25k
D 1101 PU 30k
E 1110 PU 35k
F 1111 PU 45k

R8750

4.7K

1/16W
MF-LF

1

5%

402

2

R8751

4.7K

1/16W
MF-LF

1

5%

402

2

GPIOs

Strapping Bit 1

TVMODE[1]

SLOT_CLK_CFG

RAMCFG[1]

PCI_DEVID[1]

3GIO_PADCFG[1]

USER[1]

REFERENCE DES

R8708

R8707

R8708

1

4.7K

1/16W
MF-LF

R8753

4.7K

5%

1/16W
MF-LF

402

2

R8752

5%

402

NC_GPU_GPIO_15

MAKE_BASE=TRUE

EG_DP_CA_DET

NC_GPU_GPIO_17

MAKE_BASE=TRUE

NC_GPU_GPIO_18

MAKE_BASE=TRUE

NC_GPU_GPIO_19

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NC_GPU_GPIO_22

MAKE_BASE=TRUE

MAKE_BASE=TRUE

1

2

NC_GPU_GPIO_20

NC_GPU_GPIO_21

NC_GPU_GPIO_23

CRITICAL

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

Strapping Bit 0

TVMODE[0]

PEX_PLLEN_TERM100

RAMCFG[0]

PCI_DEVID[0]

3GIO_PADCFG[0]

USER[0]

BOM OPTION

75 74

8 6

75

VRAM_512_SAMSUNG

VRAM_1024_SAMSUNG

VRAM_512_HYNIX

95 75

IN

75 74

OUT

=PP3V3_GPU_VDD33

SMC_GFX_OVERTEMP_R_L

75

SMC_GFX_THROTTLE_R_L

75

R8792

10K

5%
1/16W
MF-LF

402

MAKE_BASE=TRUE

GPU_CLK27M

95 75

MAKE_BASE=TRUE

GPU_CLK27M_SS

95

MAKE_BASE=TRUE

GPU_TDIODE_P

96 47

MAKE_BASE=TRUE

GPU_TDIODE_N

96 47

MAKE_BASE=TRUE

LVDS_EG_DDC_CLK

81

MAKE_BASE=TRUE

LVDS_EG_DDC_DATA

81

MAKE_BASE=TRUE

DP_EG_DDC_CLK

81 75 76

MAKE_BASE=TRUE

DP_EG_DDC_DATA

81 75

MAKE_BASE=TRUE

GPU_XTALOUTGPU_XTALOUT

GPU_XTALIN

GPU_XTALSSIN

GPU_THERMD_P

GPU_THERMD_N

GPU_I2CA_SCL

GPU_I2CA_SDA

GPU_I2CB_SCL

GPU_I2CB_SDA

Unused I2C Buses

NC_GPU_I2CC_SCL

MAKE_BASE=TRUE

NC_GPU_I2CC_SDA

MAKE_BASE=TRUE

NC_GPU_I2CD_SCL

MAKE_BASE=TRUE

NC_GPU_I2CD_SDA

MAKE_BASE=TRUE

NC_GPU_I2CE_SCL

MAKE_BASE=TRUE

NC_GPU_I2CE_SDA

MAKE_BASE=TRUE

NC_GPU_I2CH_SCL

MAKE_BASE=TRUE

NC_GPU_I2CH_SDA

MAKE_BASE=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

I2CS ties into SMBus connection page

(I2CS requires pullups even if not used)

GPU_I2CC_SCL

GPU_I2CC_SDA

GPU_I2CD_SCL

GPU_I2CD_SDA

GPU_I2CE_SCL

GPU_I2CE_SDA

GPU_I2CH_SCL

GPU_I2CH_SDA

GPU 27MHz Crystal

R8783

GPU_CLK27M

NO STUFF

R8782

10M

1/16W
MF-LF

2.2K

1/16W
MF-LF

1/16W
MF-LF

402

1

R8797

5%

402

2

NO STUFF

1

R8795

10K

5%

402

2

GPU_XTALOUT

R8796

1

2

R8793

1/16W
MF-LF

1

R8794

10K

5%

402

2

0

21

GPU_CLK27M_XTALOUT_R

5%

1/16W

1

MF-LF

402

5%

2

1

2.2K

5%
1/16W
MF-LF

402

2

R8798

R8799

1

10K

5%
1/16W
MF-LF

402

2

0

0

21

21

CRITICAL

Y8780

5%

5%

27MHZ

1/16W

1/16W

SM-2

31

42

NC
NC

402

MF-LF

402

MF-LF

EG_LCD_PWR_EN

EG_BKLT_EN

GPIO7_FBVDD_ALTVO

FB_VREF_UNTERM

C8780

12pF

21

5%

50V

CERM

402

C8781

12pF

21

5%

50V

CERM

402

SMC_GFX_OVERTEMP_L

SMC_GFX_THROTTLE_L

75 74 75 74

74

75 74

74

74

76

76

76

76

76

76

76

76

76

76

76

7

7

NC_GPU_MIOA_CLKOUT_P

NC_GPU_MIOA_CLKOUT_N

NC_GPU_MIOA_CTL3

TP_GPU_MIOA_DE

7

TP_GPU_MIOA_D<9..0>

7

NC_GPU_MIOA_CLKIN

NC_GPU_MIOA_D<14..10>

NC_GPU_MIOA_HSYNC

NC_GPU_MIOA_VSYNC

NC_GPU_MIOB_CLKIN

NC_GPU_MIOB_CLKOUT_P

NC_GPU_MIOB_CLKOUT_N

NC_GPU_MIOB_CTL3

NC_GPU_MIOB_DE

NC_GPU_MIOB_D<14..0>

NC_GPU_MIOB_VSYNC

NC_GPU_MIOB_HSYNC

NC_GPU_SPDIF

MAKE_BASE=TRUE

NC_CPU_HDA_SDI

MAKE_BASE=TRUE

NC_CPU_HDA_SD0

MAKE_BASE=TRUE

NC_CPU_HDA_SYNC

MAKE_BASE=TRUE

NC_CPU_HDA_BCLK

MAKE_BASE=TRUE

NC_CPU_HDA_RST_L

MAKE_BASE=TRUE

NC_FBA_MA<13>

MAKE_BASE=TRUE

NC_FBB_MA<13>

MAKE_BASE=TRUE

NC_FBA_CMD28

MAKE_BASE=TRUE

NC_FBC_CMD28

MAKE_BASE=TRUE

NC_FBA_CMD29

MAKE_BASE=TRUE

NC_FBC_CMD29

MAKE_BASE=TRUE

NC_FBA_CMD30

MAKE_BASE=TRUE

NC_FBC_CMD30

MAKE_BASE=TRUE

NC_GPU_ROM_CS_L

MAKE_BASE=TRUE

TP_LVDS_EG_B_CLK_P

MAKE_BASE=TRUE

TP_LVDS_EG_B_CLK_N

MAKE_BASE=TRUE

NC_LVDS_EG_A_DATA_P<3>

MAKE_BASE=TRUE

NC_LVDS_EG_A_DATA_N<3>

MAKE_BASE=TRUE

NC_LVDS_EG_B_DATA_P<3>

MAKE_BASE=TRUE

NC_LVDS_EG_B_DATA_N<3>

MAKE_BASE=TRUE

G96 MIOA_DE and MIOA_D<9..0> are used as Debug Port.

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

OUT

OUT

OUT

OUT

OUT

OUT

Isolation FETs for DP MUX inputs

21

Unused signals

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

Unused Clocks

GPU_XTALSSIN

75 74

GPU_XTALOUTBUFF

74

R8780

41

41

84 75

84 75

83 75

75 73 72 71

SYNC_MASTER=M98_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

APPLE INC.

GPU_SPDIF

GPU_HDA_SDI

GPU_HDA_SDO

GPU_HDA_SYNC

GPU_HDA_BCLK

GPU_HDA_RST_L

FB_A_MA<13>

FB_B_MA<13>

TP_FBA_CMD28

TP_FBC_CMD28

TP_FBA_CMD29

TP_FBC_CMD29

TP_FBA_CMD30

TP_FBC_CMD30

GPU_ROM_CS_L

LVDS_EG_B_CLK_P

LVDS_EG_B_CLK_N

LVDS_EG_A_DATA_P<3>

LVDS_EG_A_DATA_N<3>

LVDS_EG_B_DATA_P<3>

LVDS_EG_B_DATA_N<3>

GPU_MIOA_CLKOUT_P

GPU_MIOA_CLKOUT_N

GPU_MIOA_CTL3

GPU_MIOA_DE

GPU_MIOA_D<9..0>

GPU_MIOA_CLKIN

GPU_MIOA_D<14..10>

GPU_MIOA_HSYNC

GPU_MIOA_VSYNC

GPU_MIOB_CLKIN

GPU_MIOB_CLKOUT_P

GPU_MIOB_CLKOUT_N

GPU_MIOB_CTL3

GPU_MIOB_DE

GPU_MIOB_D<14..0>

GPU_MIOB_VSYNC

GPU_MIOB_HSYNC

GPU_SS_INT

1

10K

5%
1/16W
MF-LF

402

2

R8781

1

10K

5%
1/16W
MF-LF

402

2

G96 GPIOs & Straps

DRAWING NUMBER

SIZE

D

SCALE

NONE

051-8071

SHT

SYNC_DATE=05/12/2008

OF

75 98

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

REV.

74

74

74

74

74

74

71

D

71

71

71

71

71

71

71

74

76

76

76

76

76

76

C

B

A

B

8

76

5

4

3

2

1

87

www.vinafix.vn

6

5

4

3

21

Power aliases required by this page:

- =PP1V8_GPU_IFPX

- =PP3V3_GPU_IFPCD_IOVDD

Signal aliases required by this page:

(NONE)

BOM options provided by this page:

(NONE)

D

C

B

A

Page Notes

1

R8855

1K

1%
1/16W
MF-LF
402

2

1

R8856

10K

5%
1/16W
MF-LF
402

2

1

R8850

2

1K

1%
1/16W
MF-LF
402

1

2

R8857

10K

5%
1/16W
MF-LF
402

1

R8851

1K

1%
1/16W
MF-LF
402

2

PP1V1_GPU_IFPEF_IOVDD_F

PP1V8_GPU_IFPEF_PLLVDD_F

Power inputs must be pulled down if not used

76

76

Sum of peak currents: 240mA

=PP1V8_GPU_IFPX

8

GPU_IFPEF_RSET

GPU_IFPCD_RSET

GPU_IFPAB_RSET

=PP1V1_GPU_IFPCD_IOVDD

8

CRITICAL

L8800

FERR-220-OHM

0402

CRITICAL

76

76

76

L8805

FERR-220-OHM

0402

CRITICAL

L8810

FERR-220-OHM

0402

CRITICAL

L8815

FERR-220-OHM

0402

21

21

21

21

C8800

4.7UF

C8805

4.7UF

C8810

4.7UF

C8815

4.7UF

?mA peak per diff pair

?mA peak for all pairs

1

20%

6.3V
2

CERM

603

80mA peak

1

20%

6.3V
2

CERM

603

?mA peak per diff pair

?mA peak for all pairs

1

20%

6.3V
2

CERM

603

160mA peak

1

20%

6.3V
2

CERM

603

C8801

0.1UF

20%
10V

CERM

402

Place at AG9

C8806

0.1UF

20%
10V

CERM

402

C8811

0.1UF

20%
10V

CERM

402

Place at AJ8

I2CS must be pulled up if not used

I2CS addr fixed at 0x9E,0x9F

C8816

0.1UF

20%
10V

CERM

402

1

2

Place at AG10

PP1V8_GPU_IFPAB_PLLVDD_F

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.8V

1

2

1

2

Place at AK8

PP1V8_GPU_IFPCD_PLLVDD_F

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.8V

1

2

1

1

R8852

10K

5%
1/16W
MF-LF
402

2

2

PP1V8_GPU_IFPAB_IOVDD_F

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm

1

C8803

0.1UF

20%
10V

2

CERM

402

PP1V1_GPU_IFPCD_IOVDD_F

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.1 mm
VOLTAGE=1.1V

1

C8813

0.1UF

20%
10V

2

CERM

402

I2CS must be pulled up if not used.
I2CS addr fixed at 0x9E,0x9F

GPU_DACB_VDD

GPU_DACC_VDD

1

R8854

R8853

10K

10K

5%

5%

1/16W

1/16W

MF-LF

MF-LF

402

402

2

VOLTAGE=1.8V

PP1V1_GPU_IFPCD_IOVDD_F

76

PP1V1_GPU_IFPEF_IOVDD_F

76

76

76

76

76

76

75

BI

75

BI

75

BI

75

BI

76

44

BI

44

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

75

BI

GPU_DACA_VDD

GPU_IFPAB_RSET

PP1V8_GPU_IFPCD_PLLVDD_F

GPU_IFPCD_RSET

PP1V8_GPU_IFPEF_PLLVDD_F

GPU_IFPEF_RSET

76

GPU_I2CA_SCL

GPU_I2CA_SDA

GPU_I2CC_SCL

GPU_I2CC_SDA

=GPU_I2CS_SCL

=GPU_I2CS_SDA

GPU_I2CH_SCL

GPU_I2CH_SDA

GPU_I2CB_SCL

GPU_I2CB_SDA

GPU_I2CD_SCL

GPU_I2CD_SDA

GPU_I2CE_SCL

GPU_I2CE_SDA

NC
NC

NC
NC

NC

AG10

AJ11

AJ12

AK12

AK13

AG9

AJ8

AK8

AE7

AD7

AK9

AJ9

AK7

AJ6

AL1

G1

G4

E3

E4

E2

E1

F6

G6

G3

G2

F4

G5

D5

E5

AC6

AC5

AB6

AG7

AK6

AH7

NB9P-GS

SYMBOL 5 OF 9

IFPA_IOVDD
IFPB_IOVDD
IFPC_IOVDD
IFPD_IOVDD
IFPE_IOVDD
IFPF_IOVDD

IFPAB_PLLVDD
IFPAB_RSET

IFPCD_PLLVDD
IFPCD_RSET

IFPEF_PLLVDD
IFPEF_RSET

I2CA_SCL
I2CA_SDA

I2CC_SCL
I2CC_SDA

I2CS_SCL
I2CS_SDA

I2CH_SCL
I2CH_SDA

I2CB_SCL
I2CB_SDA

I2CD_SCL
I2CD_SDA

I2CE_SCL
I2CE_SDA

DACA_VDD

DACA_VREF
DACA_RSET

DACB_VDD

DACB_VREF
DACB_RSET

DACC_VDD

DACC_VREF
DACC_RSET

OMIT

U8000

BGA

IFPA_TXC

IFPA_TXC*

IFPA_TXD0

IFPA_TXD0*

IFPA_TXD1

IFPA_TXD1*

IFPA_TXD2

IFPA_TXD2*

IFPA_TXD3

IFPA_TXD3*

IFPB_TXC

IFPB_TXC*

IFPB_TXD4

IFPB_TXD4*

IFPB_TXD5

IFPB_TXD5*

IFPB_TXD6

IFPB_TXD6*

IFPB_TXD7

IFPB_TXD7*

IFPC_AUX

IFPC_AUX*

IFPC_L0

IFPC_L0*

IFPC_L1

IFPC_L1*

IFPC_L2

IFPC_L2*

IFPC_L3

IFPC_L3*

IFPD_AUX

IFPD_AUX*

IFPD_L0

IFPD_L0*

IFPD_L1

IFPD_L1*

IFPD_L2

IFPD_L2*

IFPD_L3

IFPD_L3*

IFPE_AUX

IFPE_AUX*

IFPE_L0

IFPE_L0*

IFPE_L1

IFPE_L1*

IFPE_L2

IFPE_L2*

IFPE_L3

IFPE_L3*

IFPF_AUX

IFPF_AUX*

IFPF_L0

IFPF_L0*

IFPF_L1

IFPF_L1*

IFPF_L2

IFPF_L2*

IFPF_L3

IFPF_L3*

DACA_RED

DACA_GREEN

DACA_BLUE

DACA_HSYNC
DACA_VSYNC

DACB_RED

DACB_GREEN

DACB_BLUE

DACB_CSYNC

DACC_RED

DACC_GREEN

DACC_BLUE

DACC_HSYNC
DACC_VSYNC

AM11

AM12

AM8

AL8

AM10

AM9

AK10

AL10

AK11

AL11

AP13

AN13

AN8

AP8

AP10

AN10

AR11

AR10

AN11

AP11

AP2

AN3

AM7

AM6

AL5

AM5

AM3

AM4

AP1

AR2

AP4

AN4

AR8

AR7

AP7

AN7

AN5

AP5

AR5

AR4

AE4

AD4

AH6

AH5

AH4

AG4

AF4

AF5

AE6

AE5

AF3

AF2

AL2

AL3

AJ3

AJ2

AJ1

AH1

AH2

AH3

AM15

AM14

AL14

AM13

AL13

AA4

AB4

Y4

AB5

AK4

AL4

AJ4

AM1

AM2

NC
NC

NC
NC
NC
NC
NC
NC
NC
NC

NC
NC

NC
NC
NC
NC
NC
NC
NC
NC

NC
NC

NC
NC
NC
NC
NC
NC
NC
NC

NC
NC
NC

NC
NC

NC
NC
NC

NC

NC
NC
NC

NC
NCNC

LVDS_EG_A_CLK_P

LVDS_EG_A_CLK_N

LVDS_EG_A_DATA_P<0>

LVDS_EG_A_DATA_N<0>

LVDS_EG_A_DATA_P<1>

LVDS_EG_A_DATA_N<1>

LVDS_EG_A_DATA_P<2>

LVDS_EG_A_DATA_N<2>

LVDS_EG_A_DATA_P<3>

LVDS_EG_A_DATA_N<3>

LVDS_EG_B_CLK_P

LVDS_EG_B_CLK_N

LVDS_EG_B_DATA_P<0>

LVDS_EG_B_DATA_N<0>

LVDS_EG_B_DATA_P<1>

LVDS_EG_B_DATA_N<1>

LVDS_EG_B_DATA_P<2>

LVDS_EG_B_DATA_N<2>

LVDS_EG_B_DATA_P<3>

LVDS_EG_B_DATA_N<3>

DP_EG_AUX_CH_P

DP_EG_AUX_CH_N

DP_EG_ML_P<0>

DP_EG_ML_N<0>

DP_EG_ML_P<1>

DP_EG_ML_N<1>

DP_EG_ML_P<2>

DP_EG_ML_N<2>

DP_EG_ML_P<3>

DP_EG_ML_N<3>

95 84

OUT

95 84

OUT

95 84

OUT

95 84

OUT

95 84

OUT

95 84

OUT

95 84

OUT

95 84

7

OUT

75

OUT

75

OUT

75

OUT

75

OUT

95 84

OUT

95 84

OUT

95 84

OUT

95 84

OUT

95 84

OUT

95 84

OUT

75

OUT

75

OUT

95 81

OUT

95 81

OUT

95 81

OUT

95 81

OUT

95 81

OUT

95 81

OUT

95 81

OUT

95 81

OUT

1

R8861

1K

5%
1/16W
MF-LF
402

2

NO STUFF

1

R8860

1K

5%
1/16W
MF-LF
402

2

95 81

OUT

95 81

OUT

D

C

B

NV G96 Video Interfaces

SYNC_MASTER=K20_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

D

NONE

DRAWING NUMBER

051-8071

SHT

SYNC_DATE=09/24/2008

REV.

OF

9876

A

B

8

76

5

4

3

2

1

D

www.vinafix.vn

77

C

B

A

=PP5V_S3_GPUVCORE

8

=PP3V3_GPU_VCORELOGIC

8

GPU_VDD_SENSE

69

MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.25 mm
VOLTAGE=1.25V

GPU_GND_SENSE

69

MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.25 mm
VOLTAGE=0V

GPU_VCORE_VID0

75

IN

GPU_VCORE_VID1

75

IN

GPU_VCORE_VID2

75

IN

87

R8911

1

21

PP5V_S5_GFXIMVP6_PVCC

MIN_LINE_WIDTH=0.3MM

5%

402

10

1%

402

21

21

21

1

2

C8920

0.001UF

10%
50V
CERM
402

MIN_NECK_WIDTH=0.2MM
VOLTAGE=5V

1

C8901

1uF

10%
10V

2

X5R
402

C8950

180PF

21

CERM

GPUVID0_1

PP5V_S5_GFXIMVP6_VDD

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=5V

R8905

150K

1%
1/16W
MF-LF

402

46

84 67

R8909

4.99K

1%
1/16W
MF-LF

402

5%

50V

402

R8987

C8951

560PF

10%
50V

CERM

402

2.2K

5%
1/16W
MF-LF

402

21

GPUVID1_1

1

2

1

2

1

2

GPUVID1_0

12

C8904

0.033UF

21

10%
16V
X5R
402

GPUVCORE_PGOOD

67

OUT

GFXIMVP6_VID0

77

GFXIMVP6_VID1

77

GFXIMVP6_VID2

77

GFXIMVP6_VID3

77

GFXIMVP6_VID4

77

=GPUVCORE_EN

IN

GFXIMVP6_AF_EN
GFXIMVP6_FDE

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

GFXIMVP6_VSEN_P

GFXIMVP6_VSEN_N

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

1

C8923

0.001UF

10%
50V

2

CERM
402

(GFXIMVP6_AGND)

GFXIMVP6_VW

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

1

1

C8922

0.001UF

10%
50V

2

X7R
402

2

GFXIMVP6_COMP

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

C8952

68PF

5%
50V
CERM
402-1

GFXIMVP6_FB

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

R8953

2.21K

1%
1/16W
MF-LF
402

GFXIMVP6_VDIFF

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

1

R8984

2.2K

5%
1/16W
MF-LF

402

2

GPUVID2_0

1

R8985

2.2K

5%

1/16W
MF-LF

402

2

GFXIMVP6_RBIAS

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

GFXIMVP6_SOFT

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

GFXIMVP6_IMON

GPUVID2_1

R8982

R8983

2.2K

1/16W
MF-LF

0.001UF

2.2K

1/16W
MF-LF

402

1

5%

402

2

C8921

CERM

1

5%

2

1/16W
MF-LF

R8904

1/16W
MF-LF

1

1

5%

402

2

R8920

20

5%
1/16W
MF-LF

402

R8908

20

5%
1/16W
MF-LF

402

GFXIMVP6_COMP_RC

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.3MM

1

R8950

374K

1%
1/16W
MF-LF
402

2

1

R8951

4.99K

1%
1/16W
MF-LF
402

2

GFXIMVP6_VDIFF_RC

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.3MM

77

8

R8986

0

21

5%
1/16W
MF-LF

402

R8990

0

5%
1/16W
MF-LF

402

R8994

0

5%
1/16W
MF-LF

402

R8910

10K

5%
1/16W
MF-LF
402

2

21

21

=PP3V3_GPU_VCORELOGIC

R8907

10K

1/16W
MF-LF

PLACEMENT_NOTE=Place R8920 at U8900
PLACEMENT_NOTE=Place R8908 at U8900

6

GPU VCore Regulator

1

1

C8902

4.7UF

X5R-CERM

10%
50V

402

20%

6.3V

402

1

2

R8980

C8903

0.01uF

10%
16V

2

2

CERM
402

16

VDD

1

RBIAS

U8900

2

SOFT

28

IMON

31

PGOOD

23

VID0

24

VID1

25

VID2

26

VID3

27

VID4

29

VR_ON

30

AF_EN

32

FDE

8

VSEN

9

RTN

4

VW

5

COMP

CRITICAL

QFN

ISL6263C

CRITICAL

CASED2E-SM

22

PVCC

UGATE

PHASE

LGATE

OCSET

6

FB

VSS

15

XW8900

SM

GFXIMVP6_VID0
GFXIMVP6_VID1
GFXIMVP6_VID2
GFXIMVP6_VID3
GFXIMVP6_VID4

1

R8988

0

5%
1/16W
MF-LF
402

2

ICOMP

THRM_PAD

33

21

7

VDIFF

PGND

20

1

0

5%
1/16W
MF-LF

402

2

C8931

33UF

POLY-TANT

VIN

BOOT

VO

ISP
ISN

CRITICAL

1

20%
16V

2

14

18

17

19

21

1

2

12

3

13
11

10

C8930

POLY-TANT

CASED2E-SM

GFXIMVP6_VIN

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

GFXIMVP6_UGATE

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

GFXIMVP6_BOOT

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

GFXIMVP6_PHASE

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
SWITCH_NODE=TRUE

GFXIMVP6_LGATE

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

C8953

680pF

10%
50V
CERM
402

GFXIMVP6_VO

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

GFXIMVP6_OCSET

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

GFXIMVP6_DROOP

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

GND_GFXIMVP6_AGND

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V

5

=PPVIN_GPU_GPUVCORE

1

33UF

20%
16V

2

2

9.76K

1%
1/16W
MF-LF

402

1

BOM GROUP

GPUVID_0P90V

GPUVID_1P00V

8

1

2

R8900

7.87K

1%
1/16W
MF-LF

402

C8971

68PF

5%

50V

CERM

402-1

C8932

1UF

10%
25V
X5R
603-1

C8956

0.22UF

4

21

21

C8972

C8933

603-1

10%
16V
X7R
603

1

R8901

5.11K

1%
1/16W
MF-LF
402

2

0.1uF

10%
16V
X5R
402

1

1UF

10%
25V

2

X5R

1

2

5

1

2

VID3

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

1

1

1

CRITICAL

1

C8935

33UF

20%
16V

2

POLY-TANT

CASED2E-SM

GFXIMVP6_DFB

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

77

77

77

77

77

R8902

Default Vcore Setpoints

1

C8934

0.001UF

10%
50V

2

X7R
402

R8930

1K

5%
1/16W
MF-LF

402

CRITICAL

Q8951

RJK0328DPB

LFPAK-HF

321

GFXIMVP6_VSUM

C8906

VID2

1

1

4

1

5

2

4

4

1

R8903

1K

1%
1/16W
MF-LF

402

2

1

330PF

5%

50V

2

COG
402

VID1

1

1

110

Other VID states may not be valid

CRITICAL

Q8950

RJK0305DPB

LFPAK-HF

321

CRITICAL

L8920

0.6UH-30A-1.5MOHM

MPL104-SM

5

CRITICAL

Q8952

RJK0328DPB

LFPAK-HF

321

GFXIMVP6_PHASE_VSUM

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.3MM

(PPVCORE_GPU_REG)

GPU VCore Setpoints

VID0

Voltage

1

0.90125V

0

0.92700V

1.00425V

21

PPVCORE_GPU_REG_R

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

Max Batt Balanced

X

-

-

X

-

BOM OPTIONS

GPUVID2_1,GPUVID1_1,GPUVID0_1

GPUVID2_0,GPUVID1_1,GPUVID0_1

3

R8940

0.001

1%
1W
MF

0612

Max perf

21

43

-

-

X

21

Vout = 1.05V - 0.96V

=PPVCORE_GPU_REG

1

C8966

C8969

0.001UF

1

10%
50V

2

X7R
402

1

C8967

10UF

20%

6.3V

2

X5R
603

10UF

6.3V

20%

2

X5R
603

1

C8968

1

C8965

2

10UF

20%

6.3V
X5R
603

10UF

6.3V

20%

2

X5R
603

PLACE C8965,C8966,C8967 AND C8968 ON THE BACK SIDE OF GPU

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

APPLE INC.

CRITICAL

C8942

330UF

20%

2.0V

POLY-TANT

D2T-SM2

CRITICAL

1

C8943

330UF

20%

2.0V

32

POLY-TANT
D2T-SM2

GPU (G96) CORE SUPPLY

SYNC_MASTER=RXU_K20

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

45

8

24.6A max output

1

(OCP limit)

32

DRAWING NUMBER

SIZE

D

SCALE

NONE

051-8071

SHT

SYNC_DATE=05/21/2008

REV.

B

OF

9877

D

C

B

A

8

76

5

4

3

2

1

87

www.vinafix.vn

6

5

4

3

21

D

D

LCD (LVDS) INTERFACE

=PP3V3_S0_LCD

8

C9000

LCD_PWREN_L_RC

3

D

2

81 95

81 95

81 95

81 95

0.0022uF

21

10%
50V

CERM

402

LVDS_CONN_A_CLK_N

LVDS_CONN_A_CLK_P

LVDS_CONN_B_CLK_N

LVDS_CONN_B_CLK_P

4

3

1

75

100K pull-ups are for

no-panel case (development).

Panel has 2K pull-ups

81

81

Place close to the connector

Place close to the connector

CRITICAL

Q9000

FDC638P_G

SM

652

=PP3V3_S0_DDC_LCD

7 8

LVDS_DDC_CLK

7

LVDS_DDC_DATA

7

CRITICAL

L9010

90-OHM-100MA

DLP11S

SYM_VER-1

43

21

CRITICAL

L9011

90-OHM-100MA

DLP11S

SYM_VER-1

43

21

PP3V3_SW_LCD_UF

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V

1

R9010

100K

5%
1/16W
MF-LF

402

2

1

R9011

100K

5%
1/16W
MF-LF
402

2

C9010

0.001UF

C9001

0.1UF

10%
50V
X7R
402

CRITICAL

L9000

FERR-250-OHM

1

10%
16V

2

X5R
402

1

2

LED_RETURN_1

7

85

LED_RETURN_2

7

85

LED_RETURN_3

7

85

LED_RETURN_4

7

85

LED_RETURN_5

7

85

LED_RETURN_6

7

85

7

85

21

SM

1

C9002

0.001UF

10%
50V

2

X7R
402

BKL_SYNC

7

85

LVDS_CONN_A_DATA_N<0>

7

81 95

LVDS_CONN_A_DATA_P<0>

7

81 95

LVDS_CONN_A_DATA_N<1>

7

81 95

LVDS_CONN_A_DATA_P<1>

7

81 95

LVDS_CONN_A_DATA_N<2>

7

81 95

LVDS_CONN_A_DATA_P<2>

7

81 95

LVDS_CONN_A_CLK_F_N

7

95

LVDS_CONN_A_CLK_F_P

7

95

LVDS_CONN_B_DATA_N<0>

7

81 95

LVDS_CONN_B_DATA_P<0>

7

81 95

LVDS_CONN_B_DATA_N<1>

7

81 95

LVDS_CONN_B_DATA_P<1>

7

81 95

LVDS_CONN_B_DATA_N<2>

7

81 95

LVDS_CONN_B_DATA_P<2>

7

81 95

LVDS_CONN_B_CLK_F_N

7

95

LVDS_CONN_B_CLK_F_P

7

95

PPVOUT_S0_LCDBKLT

PP3V3_SW_LCD

7

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V

NC

1

C9008

2

1000PF

10%
100V
X7R
603

CRITICAL

J9000

20474-040E-11

F-RT-SM

41

42

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

43

44

C

B

518S0651

1

R9000

100K

5%
1/16W
MF-LF

402

2

R9001

100K

21

5%
1/16W
MF-LF

402

LCD_PWREN_L

Q9001

SSM3K15FV

SOD-VESM-HF

1

C

LCD_PWR_EN

84

IN

GS

B

A

8

76

LVDS Display Connector

SYNC_MASTER=M98_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

5

4

3

2

SCALE

NONE

051-8071

SHT

1

SYNC_DATE=07/14/2008

REV.

OF

9878

A

B

21

www.vinafix.vn

Page Notes

Power aliases required by this page:

- =PP1V8_S0_FB_VDD

- =PP1V8_S0_FB_VDDQ

Signal aliases required by this page:

(NONE)

BOM options provided by this page:

VRAM8

D

C

VRAM8

6

CRITICAL

OMIT

A2

VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7

VDDA0
VDDA1

VDDQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21

VREF0
VREF1

U9100

BGA

(2 OF 2)

32MX32-900MHZ-MFL

A11

F1

F12

M1

M12

V2

V11

K1

K12

A1

A12

C1

C4

C9

C12

E1

E4

E9

E12

J4

J9

N1

N4

N9

N12

R1

R4

R9

R12

V1

V12

H1

H12

A3

VSS0

A10

VSS1

G1

VSS2

G12

VSS3

L1

VSS4

L12

VSS5

V3

VSS6

V10

VSS7

J1

VSSA0

K4J10324QD-HC11

J12

VSSA1

B1

VSSQ0

B4

VSSQ1

B9

VSSQ2

B12

VSSQ3

D1

VSSQ4

D4

VSSQ5

D9

VSSQ6

D12

VSSQ7

G2

VSSQ8

G11

VSSQ9

L2

VSSQ10

L11

VSSQ11

P1

VSSQ12

P4

VSSQ13

P9

VSSQ14

P12

VSSQ15

T1

VSSQ16

T4

VSSQ17

T9

VSSQ18

T12

VSSQ19

80 79 73 72

80 79 73 72

5

=PP1V8_GPU_FB_VDD

8

=PP1V8_GPU_FB_VDDQ

9 8

VRAM8

C9170

10UF

VRAM8

C9150

Connect to designated pin, then GNDConnect to designated pin, then GND

1

2

C9171

0.1uF

10%
16V
X5R
402

VRAM8

1

20%

6.3V
2

X5R

603

10UF

1

2

20%

6.3V

X5R

603

C9172

0.1uF

10%
16V
X5R
402

1

2

VRAM8

4

VRAM8

VRAM8

1

C9153

0.1uF

10%
16V

2

X5R
402

VRAM8

1

C9160

0.1uF

10%
16V

2

X5R
402

U8400.J1

VRAM8

1

C9175

0.1uF

10%
16V

2

X5R
402

FB_A3_VREF

72

IN

FB_A1_VREF

72 72

1

2

C9151

0.1uF

10%
16V
X5R
402

1

2

VRAM8

C9173

0.1uF

10%
16V
X5R
402

VRAM8

1

2

C9152

0.1uF

10%
16V
X5R
402

1

2

VRAM8

C9174

0.1uF

10%
16V
X5R
402

87

=PP1V8_GPU_FB_VDD

80 79 73 72

8

VRAM8

1

C9100

10UF

20%

6.3V
2

X5R

603

D

80 79 73 72

=PP1V8_GPU_FB_VDDQ

9 8

VRAM8

C9120

10UF

1

2

C9121

0.1uF

10%
16V
X5R
402

VRAM8

1

20%

6.3V
2

X5R

603

1

2

C9122

0.1uF

10%
16V
X5R
402

VRAM8

C

1

2

C9101

0.1uF

10%
16V
X5R
402

1

2

VRAM8

C9123

0.1uF

10%
16V
X5R
402

VRAM8

1

2

C9102

0.1uF

10%
16V
X5R
402

1

2

FB_A2_VREF

FB_A0_VREF

1

2

1

2

U8400.J12

C9104

0.1uF

10%
16V
X5R
402

C9115

0.1uF

10%
16V
X5R
402

1

2

VRAM8

VRAM8

C9126

0.1uF

10%
16V
X5R
402

VRAM8

C9124

0.1uF

10%
16V
X5R
402

VRAM8

VRAM8

1

C9103

0.1uF

10%
16V

2

X5R
402

VRAM8

1

C9110

0.1uF

10%
16V

2

X5R
402

U8400.J1

VRAM8

1

C9125

0.1uF

10%
16V

2

X5R
402

72

IN

IN IN

1

2

1

2

U8400.J12

C9154

0.1uF

10%
16V
X5R
402

C9165

0.1uF

10%
16V
X5R
402

1

2

VRAM8

VRAM8

VRAM8

C9176

0.1uF

10%
16V
X5R
402

3

CRITICAL

A2

OMIT

VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7

VDDA0
VDDA1

VDDQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21

VREF0
VREF1

U9150

BGA

(2 OF 2)

32MX32-900MHZ-MFL

A11

F1

F12

M1

M12

V2

V11

K1

K12

A1

A12

C1

C4

C9

C12

E1

E4

E9

E12

J4

J9

N1

N4

N9

N12

R1

R4

R9

R12

V1

V12

H1

H12

A3

VSS0

A10

VSS1

G1

VSS2

G12

VSS3

L1

VSS4

L12

VSS5

V3

VSS6

V10

VSS7

J1

VSSA0

K4J10324QD-HC11

J12

VSSA1

B1

VSSQ0

B4

VSSQ1

B9

VSSQ2

B12

VSSQ3

D1

VSSQ4

D4

VSSQ5

D9

VSSQ6

D12

VSSQ7

G2

VSSQ8

G11

VSSQ9

L2

VSSQ10

L11

VSSQ11

P1

VSSQ12

P4

VSSQ13

P9

VSSQ14

P12

VSSQ15

T1

VSSQ16

T4

VSSQ17

T9

VSSQ18

T12

VSSQ19

K4

H2

K3

M4

K9

H11

K10

L9

K11

M9

K2

L4

H4

J3

J11

J10

F9

H9

F4

H3

A4

A9

V4

V9

D3

D10

P10

P3

D2

D11

P11

P2

G4

G9

H10

J2

CRITICAL

A0
A1
A2
A3
A4
A5

MFLOW

A6
A7
A8/AP
A9
A10
A11
CKE

A12/CS1*

CK

CK*
CS0*
WE*
CAS*
RAS*

ZQ
MF
SEN

RESET

RDQS0
RDQS1
RDQS2
RDQS3

WDQS0
WDQS1

WDQS2
WDQS3

BA0
BA1
BA2

RFU

OMIT

U9150

BGA

(1 OF 2)

32MX32-900MHZ-MFL

MFLOW

MFLOW

E3

DM0

E10

DM1

N10

DM2

N3

DM3

B2

DQ0

B3

DQ1

C2

DQ2

C3

DQ3

E2

DQ4

K4J10324QD-HC11

F3

DQ5

F2

DQ6

G3

DQ7

B11

DQ8

B10

DQ9

C11

DQ10

C10

DQ11

E11

DQ12

F10

DQ13

F11

DQ14

G10

DQ15

M11

DQ16

L10

DQ17

N11

DQ18

M10

DQ19

R11

DQ20

R10

DQ21

T11

DQ22

T10

DQ23

M2

DQ24

L3

DQ25

N2

DQ26

M3

DQ27

R2

DQ28

R3

DQ29

T2

DQ30

T3

DQ31

FB_A_DQM_L<5>

FB_A_DQM_L<7>

FB_A_DQM_L<4>

FB_A_DQM_L<6>

FB_A_DQ<40>

FB_A_DQ<47>

FB_A_DQ<46>

FB_A_DQ<45>

FB_A_DQ<42>

FB_A_DQ<44>

FB_A_DQ<43>

FB_A_DQ<41>

FB_A_DQ<59>

FB_A_DQ<58>

FB_A_DQ<63>

FB_A_DQ<60>

FB_A_DQ<57>

FB_A_DQ<56>

FB_A_DQ<61>

FB_A_DQ<62>

FB_A_DQ<36>

FB_A_DQ<37>

FB_A_DQ<32>

FB_A_DQ<38>

FB_A_DQ<39>

FB_A_DQ<34>

FB_A_DQ<33>

FB_A_DQ<35>

FB_A_DQ<54>

FB_A_DQ<55>

FB_A_DQ<53>

FB_A_DQ<52>

FB_A_DQ<49>

FB_A_DQ<51>

FB_A_DQ<50>

FB_A_DQ<48>

IN

IN

IN

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

95 72 71

95 72 71

95 72 71

95 72 71

95 72 71

7

95 72 71

7

95 72 71

7

95 72 71

7

95 72 71

7

95 72 71

7

95 72 71

7

95 72 71

7

95 72 71

7

95 72 71

7

95 72 71

7

95 72 71

7

95 72 71

7

95 72 71

7

95 72 71

7

95 72 71

7

95 72 71

7

95 72 71

7

95 72 71

7

95 72 71

7

95 72 71

7

95 72 71

7

95 72 71

7

95 72 71

7

72 71

7
95

72 71

7
95

72 71

7
95

72 71

7
95

72 71

7
95

72 71

7
95

72 71

7
95

7

72 71

95

APPLE INC.

GDDR3 Frame Buffer A (Top)

SYNC_MASTER=M99_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

SHT

051-8071

79

SYNC_DATE=04/04/2008

REV.

OF

98

B

A

B

CRITICAL

95 79 72 71

95 79 72 71

95 72 71

95 72 71

95 72 71

95 72 71

B

A

95 79 72 71

95 79 72 71

95 79 72 71

95 79 72 71

95 79 72 71

95 79 72 71

95 79 72 71

95 72 71

95 72 71

95 79 71

95 79 72 71

95 79 72 71

95 79 72 71

95 79 72 71

95 72 71

95 72 71

95 72 71

95 72 71

95 72 71

95 72 71

95 72 71

95 72 71

95 79 72 71

95 79 72 71

95 79 72 71

FB_A_MA<0>

IN

FB_A_MA<1>

IN

FB_A_LMA<2>

IN

FB_A_LMA<3>

IN

FB_A_LMA<4>

IN

FB_A_LMA<5>

IN

FB_A_MA<6>

IN

FB_A_MA<7>

IN

FB_A_MA<8>

IN

FB_A_MA<9>

IN

FB_A_MA<10>

IN

FB_A_MA<11>

IN

FB_A_CKE

IN

FB_A_MA<12>

IN IN

FB_A_CLK_P<0>

IN

FB_A_CLK_N<0>

IN

FB_A_CS1_L

IN

FB_A_WE_L

IN

FB_A_CAS_L

IN

FB_A_RAS_L

IN

IN

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

FB_A_DRAM_RST

FB_A_RDQS<2>

FB_A_RDQS<3>

FB_A_RDQS<1>

FB_A_RDQS<0>

FB_A_WDQS<2>

FB_A_WDQS<3>

FB_A_WDQS<1>

FB_A_WDQS<0>

FB_A_BA<0>

FB_A_BA<1>

FB_A_BA<2>

VRAM8

R9140

VRAM8

1

R9148

1K

5%
1/16W
MF-LF

402

1/16W
MF-LF

2

FB_A2_ZQ

FB_A2_MF

FB_A2_SEN

VRAM8

1

1

R9149

243

100

1%

5%
1/16W
MF-LF

402

402

2

2

K4

H2

K3

M4

K9

H11

K10

L9

K11

M9

K2

L4

H4

J3

J11

J10

F9

H9

F4

H3

A4

A9

V4

V9

D3

D10

P10

P3

D2

D11

P11

P2

G4

G9

H10

J2

A0
A1
A2
A3
A4
A5

MFLOW

A6
A7
A8/AP
A9
A10
A11
CKE

A12/CS1*

CK

CK*
CS0*
WE*
CAS*
RAS*

ZQ
MF
SEN

RESET

RDQS0
RDQS1
RDQS2
RDQS3

WDQS0
WDQS1

WDQS2
WDQS3

BA0
BA1
BA2

RFU

U9100

BGA

(1 OF 2)

32MX32-900MHZ-MFL

MFLOW

MFLOW

K4J10324QD-HC11

OMIT

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DM0
DM1
DM2
DM3

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9

E3

E10

N10

N3

B2

B3

C2

C3

E2

F3

F2

G3

B11

B10

C11

C10

E11

F10

F11

G10

M11

L10

N11

M10

R11

R10

T11

T10

M2

L3

N2

M3

R2

R3

T2

T3

FB_A_DQM_L<2>

FB_A_DQM_L<3>

FB_A_DQM_L<1>

FB_A_DQM_L<0>

FB_A_DQ<20>

FB_A_DQ<22>

FB_A_DQ<21>

FB_A_DQ<23>

FB_A_DQ<19>

FB_A_DQ<18>

FB_A_DQ<16>

FB_A_DQ<17>

FB_A_DQ<24>

FB_A_DQ<30>

FB_A_DQ<29>

FB_A_DQ<31>

FB_A_DQ<28>

FB_A_DQ<27>

FB_A_DQ<25>

FB_A_DQ<26>

FB_A_DQ<13>

FB_A_DQ<15>

FB_A_DQ<14>

FB_A_DQ<12>

FB_A_DQ<10>

FB_A_DQ<9>

FB_A_DQ<8>

FB_A_DQ<11>

FB_A_DQ<5>

FB_A_DQ<4>

FB_A_DQ<6>

FB_A_DQ<7>

FB_A_DQ<2>

FB_A_DQ<3>

FB_A_DQ<1>

FB_A_DQ<0>

IN

IN

IN

IN

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

95 79 72 71

95 72 71

95 72 71

95 72 71

95 72 71

95 72 71

95 72 71

95 72 71

95 72 71

95 72 71

95 79 72 71

95 72 71

95 79 72 71

95 72 71

95 79 72 71

95 72 71

95 79 72 71

95 72 71

95 79 72 71

95 72 71

95 79 72 71

95 72 71

95 79 72 71

95 72 71

95 79 72 71 95 79 72 71

95 72 71

95 72 71

95 72 71

95 72 71

95 72 71

95 79 71

95 72 71

95 79 72 71

95 72 71

95 79 72 71

95 72 71

95 79 72 71

95 72 71

95 72 71

95 72 71

95 72 71

95 79 72 71

95 72 71

95 72 71

95 72 71

95 72 71

95 72 71

95 72 71

95 72 71

95 72 71

95 72 71

95 72 71

95 72 71

95 72 71

95 72 71

95 72 71

95 72 71

95 72 71

95 72 71

95 72 71

95 72 71

95 79 72 71

95 72 71

95 79 72 71

95 72 71

95 79 72 71

95 79 72 71

95 72 71

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

FB_A_MA<0>

FB_A_MA<1>

FB_A_UMA<2>

FB_A_UMA<3>

FB_A_UMA<4>

FB_A_UMA<5>

FB_A_MA<6>

FB_A_MA<7>

FB_A_MA<8>

FB_A_MA<9>

FB_A_MA<10>

FB_A_MA<11>

FB_A_CKE

FB_A_MA<12>

FB_A_CLK_P<1>

FB_A_CLK_N<1>

FB_A_CS1_L

FB_A_WE_L

FB_A_CAS_L

FB_A_RAS_L

FB_A_DRAM_RST

FB_A_RDQS<5>

FB_A_RDQS<7>

FB_A_RDQS<4>

FB_A_RDQS<6>

FB_A_WDQS<5>

FB_A_WDQS<7>

FB_A_WDQS<4>

FB_A_WDQS<6>

FB_A_BA<0>

FB_A_BA<1>

FB_A_BA<2>

VRAM8

R9190

1/16W
MF-LF

FB_A3_ZQ

FB_A3_MF

FB_A3_SEN

VRAM8

1

R9198

1K

5%

402

243

1%
1/16W
MF-LF

402

2

VRAM8

1

1

R9199

100

5%
1/16W
MF-LF
402

2

2

NCNC

8

76

5

4

3

2

1

21

www.vinafix.vn

Page Notes

Power aliases required by this page:

- =PP1V8_S0_FB_VDD

- =PP1V8_S0_FB_VDDQ

Signal aliases required by this page:

(NONE)

BOM options provided by this page:

VRAM8

D

C

VRAM8

6

CRITICAL

OMIT

A2

VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7

VDDA0
VDDA1

VDDQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21

VREF0
VREF1

U9200

BGA

(2 OF 2)

32MX32-900MHZ-MFL

A11

F1

F12

M1

M12

V2

V11

K1

K12

A1

A12

C1

C4

C9

C12

E1

E4

E9

E12

J4

J9

N1

N4

N9

N12

R1

R4

R9

R12

V1

V12

H1

H12

A3

VSS0

A10

VSS1

G1

VSS2

G12

VSS3

L1

VSS4

L12

VSS5

V3

VSS6

V10

VSS7

J1

VSSA0

K4J10324QD-HC11

J12

VSSA1

B1

VSSQ0

B4

VSSQ1

B9

VSSQ2

B12

VSSQ3

D1

VSSQ4

D4

VSSQ5

D9

VSSQ6

D12

VSSQ7

G2

VSSQ8

G11

VSSQ9

L2

VSSQ10

L11

VSSQ11

P1

VSSQ12

P4

VSSQ13

P9

VSSQ14

P12

VSSQ15

T1

VSSQ16

T4

VSSQ17

T9

VSSQ18

T12

VSSQ19

80 79 73 72

80 79 73 72

5

=PP1V8_GPU_FB_VDD

8

=PP1V8_GPU_FB_VDDQ

9 8

VRAM8

C9270

10UF

Connect to designated pin, then GND

1

20%

6.3V
2

X5R

603

1

2

C9271

0.1uF

10%
16V
X5R
402

VRAM8

VRAM8

C9250

10UF

1

2

20%

6.3V

X5R

603

C9272

0.1uF

10%
16V
X5R
402

1

2

VRAM8

4

1

2

C9251

0.1uF

10%
16V
X5R
402

1

2

VRAM8

VRAM8

C9273

0.1uF

10%
16V
X5R
402

1

2

C9252

0.1uF

10%
16V
X5R
402

1

2

VRAM8

VRAM8

C9274

0.1uF

10%
16V
X5R
402

VRAM8

1

C9253

0.1uF

10%
16V

2

X5R
402

VRAM8

1

C9260

0.1uF

10%
16V

2

X5R
402

U8500.J1

VRAM8

1

C9275

0.1uF

10%
16V

2

X5R
402

FB_B3_VREF

73

IN

FB_B1_VREF

73 73

87

=PP1V8_GPU_FB_VDD

80 79 73 72

8

VRAM8

1

C9200

10UF

20%

6.3V
2

X5R

603

D

Connect to designated pin, then GND

80 79 73 72

=PP1V8_GPU_FB_VDDQ

9 8

VRAM8

C9220

10UF

1

2

C9221

0.1uF

10%
16V
X5R
402

VRAM8

1

20%

6.3V
2

X5R

603

1

2

C9222

0.1uF

10%
16V
X5R
402

VRAM8

C

1

2

C9201

0.1uF

10%
16V
X5R
402

1

2

VRAM8

C9223

0.1uF

10%
16V
X5R
402

VRAM8

1

2

C9202

0.1uF

10%
16V
X5R
402

1

2

FB_B2_VREF

FB_B0_VREF

1

2

1

2

U8500.J12

C9204

0.1uF

10%
16V
X5R
402

C9215

0.1uF

10%
16V
X5R
402

1

2

VRAM8

VRAM8

C9226

0.1uF

10%
16V
X5R
402

VRAM8

C9224

0.1uF

10%
16V
X5R
402

VRAM8

VRAM8

1

C9203

0.1uF

10%
16V

2

X5R
402

VRAM8

1

C9210

0.1uF

10%
16V

2

X5R
402

U8500.J1

VRAM8

1

C9225

0.1uF

10%
16V

2

X5R
402

73

IN

IN IN

1

2

1

2

U8500.J12

C9254

0.1uF

10%
16V
X5R
402

C9265

0.1uF

10%
16V
X5R
402

1

2

VRAM8

VRAM8

VRAM8

C9276

0.1uF

10%
16V
X5R
402

3

CRITICAL

OMIT

A2

VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7

VDDA0
VDDA1

VDDQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21

VREF0
VREF1

U9250

BGA

(2 OF 2)

32MX32-900MHZ-MFL

A11

F1

F12

M1

M12

V2

V11

K1

K12

A1

A12

C1

C4

C9

C12

E1

E4

E9

E12

J4

J9

N1

N4

N9

N12

R1

R4

R9

R12

V1

V12

H1

H12

A3

VSS0

A10

VSS1

G1

VSS2

G12

VSS3

L1

VSS4

L12

VSS5

V3

VSS6

V10

VSS7

J1

VSSA0

K4J10324QD-HC11

J12

VSSA1

B1

VSSQ0

B4

VSSQ1

B9

VSSQ2

B12

VSSQ3

D1

VSSQ4

D4

VSSQ5

D9

VSSQ6

D12

VSSQ7

G2

VSSQ8

G11

VSSQ9

L2

VSSQ10

L11

VSSQ11

P1

VSSQ12

P4

VSSQ13

P9

VSSQ14

P12

VSSQ15

T1

VSSQ16

T4

VSSQ17

T9

VSSQ18

T12

VSSQ19

K4

H2

K3

M4

K9

H11

K10

L9

K11

M9

K2

L4

H4

J3

J11

J10

F9

H9

F4

H3

A4

A9

V4

V9

D3

D10

P10

P3

D2

D11

P11

P2

G4

G9

H10

J2

CRITICAL

A0
A1
A2
A3
A4
A5

MFLOW

A6
A7
A8/AP
A9
A10
A11
CKE

A12/CS1*

CK

CK*
CS0*
WE*
CAS*
RAS*

ZQ
MF
SEN

RESET

RDQS0
RDQS1
RDQS2
RDQS3

WDQS0
WDQS1

WDQS2
WDQS3

BA0
BA1
BA2

RFU

OMIT

U9250

BGA

(1 OF 2)

32MX32-900MHZ-MFL

MFLOW

MFLOW

E3

DM0

E10

DM1

N10

DM2

N3

DM3

B2

DQ0

B3

DQ1

C2

DQ2

C3

DQ3

E2

DQ4

K4J10324QD-HC11

F3

DQ5

F2

DQ6

G3

DQ7

B11

DQ8

B10

DQ9

C11

DQ10

C10

DQ11

E11

DQ12

F10

DQ13

F11

DQ14

G10

DQ15

M11

DQ16

L10

DQ17

N11

DQ18

M10

DQ19

R11

DQ20

R10

DQ21

T11

DQ22

T10

DQ23

M2

DQ24

L3

DQ25

N2

DQ26

M3

DQ27

R2

DQ28

R3

DQ29

T2

DQ30

T3

DQ31

FB_B_DQM_L<5>

FB_B_DQM_L<6>

FB_B_DQM_L<7>

FB_B_DQM_L<4>

FB_B_DQ<41>

FB_B_DQ<42>

FB_B_DQ<40>

FB_B_DQ<47>

FB_B_DQ<44>

FB_B_DQ<45>

FB_B_DQ<43>

FB_B_DQ<46>

FB_B_DQ<49>

FB_B_DQ<50>

FB_B_DQ<48>

FB_B_DQ<51>

FB_B_DQ<53>

FB_B_DQ<55>

FB_B_DQ<54>

FB_B_DQ<52>

FB_B_DQ<56>

FB_B_DQ<57>

FB_B_DQ<63>

FB_B_DQ<59>

FB_B_DQ<58>

FB_B_DQ<62>

FB_B_DQ<61>

FB_B_DQ<60>

FB_B_DQ<34>

FB_B_DQ<35>

FB_B_DQ<33>

FB_B_DQ<32>

FB_B_DQ<37>

FB_B_DQ<38>

FB_B_DQ<39>

FB_B_DQ<36>

IN

IN

IN

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

95 73 71

95 73 71

95 73 71

95 73 71

95 73 71

7

95 73 71

7

95 73 71

7

95 73 71

7

95 73 71

7

95 73 71

7

95 73 71

7

95 73 71

7

95 73 71

7

95 73 71

7

95 73 71

7

95 73 71

7

95 73 71

7

95 73 71

7

95 73 71

7

95 73 71

7

95 73 71

7

95 73 71

7

95 73 71

7

95 73 71

7

95 73 71

7

95 73 71

7

95 73 71

7

95 73 71

7

73 71

7
95

73 71

7
95

73 71

7
95

73 71

7
95

73 71

7
95

73 71

7
95

73 71

7
95

7

73 71

95

APPLE INC.

GDDR3 Frame Buffer B (Top)

SYNC_MASTER=M88_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

SHT

051-8071

SYNC_DATE=11/01/2007

REV.

OF

9880

B

A

B

CRITICAL

95 80 73 71

95 80 73 71

95 73 71

95 73 71

95 73 71

95 73 71

B

A

95 80 73 71

95 80 73 71

95 80 73 71

95 80 73 71

95 80 73 71

95 80 73 71

95 80 73 71

95 73 71

95 80 71

95 80 73 71

95 80 73 71

95 80 73 71

95 80 73 71

95 73 71

95 73 71

95 73 71

95 73 71

95 73 71

95 73 71

95 73 71

95 73 71

95 80 73 71

95 80 73 71

95 80 73 71

FB_B_MA<0>

IN

FB_B_MA<1>

IN

FB_B_LMA<2>

IN

FB_B_LMA<3>

IN

FB_B_LMA<4>

IN

FB_B_LMA<5>

IN

FB_B_MA<6>

IN

FB_B_MA<7>

IN

FB_B_MA<8>

IN

FB_B_MA<9>

IN

FB_B_MA<10>

IN

FB_B_MA<11>

7

IN

FB_B_CKE

IN

FB_B_MA<12>

IN IN

FB_B_CLK_P<0>

IN IN

FB_B_CLK_N<0>

IN

FB_B_CS1_L

IN

FB_B_WE_L

IN

FB_B_CAS_L

7

IN

FB_B_RAS_L

IN

FB_B_DRAM_RST

IN

FB_B_RDQS<0>

OUT

FB_B_RDQS<1>

OUT

FB_B_RDQS<3>

OUT

FB_B_RDQS<2>

OUT

FB_B_WDQS<0>

IN

FB_B_WDQS<1>

IN

FB_B_WDQS<3>

IN

FB_B_WDQS<2>

IN

FB_B_BA<0>

IN

FB_B_BA<1>

7

IN

FB_B_BA<2>

IN

VRAM8

R9240

VRAM8

1

R9248

1K

5%
1/16W
MF-LF

402

1/16W
MF-LF

2

FB_B2_ZQ

FB_B2_MF

FB_B2_SEN

VRAM8

1

1

R9249

243

100

1%

5%
1/16W
MF-LF

402

402

2

2

K4

A0
A1
A2
A3
A4
A5

MFLOW

A6
A7
A8/AP
A9
A10
A11
CKE

A12/CS1*

CK

CK*
CS0*
WE*
CAS*
RAS*

ZQ
MF
SEN

RESET

RDQS0
RDQS1
RDQS2
RDQS3

WDQS0
WDQS1

WDQS2
WDQS3

BA0
BA1
BA2

RFU

U9200

BGA

(1 OF 2)

32MX32-900MHZ-MFL

MFLOW

MFLOW

K4J10324QD-HC11

H2

K3

M4

K9

H11

K10

L9

K11

M9

K2

L4

H4

J3

J11

J10

F9

H9

F4

H3

A4

A9

V4

V9

D3

D10

P10

P3

D2

D11

P11

P2

G4

G9

H10

J2

NC NC

OMIT

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DM0
DM1
DM2
DM3

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9

E3

E10

N10

N3

B2

B3

C2

C3

E2

F3

F2

G3

B11

B10

C11

C10

E11

F10

F11

G10

M11

L10

N11

M10

R11

R10

T11

T10

M2

L3

N2

M3

R2

R3

T2

T3

FB_B_DQM_L<0>

FB_B_DQM_L<1>

FB_B_DQM_L<3>

FB_B_DQM_L<2>

FB_B_DQ<6>

FB_B_DQ<5>

FB_B_DQ<3>

FB_B_DQ<4>

FB_B_DQ<0>

FB_B_DQ<2>

FB_B_DQ<1>

FB_B_DQ<7>

FB_B_DQ<12>

FB_B_DQ<8>

FB_B_DQ<11>

FB_B_DQ<10>

FB_B_DQ<13>

FB_B_DQ<15>

FB_B_DQ<14>

FB_B_DQ<9>

FB_B_DQ<26>

FB_B_DQ<27>

FB_B_DQ<31>

FB_B_DQ<28>

FB_B_DQ<24>

FB_B_DQ<25>

FB_B_DQ<29>

FB_B_DQ<30>

FB_B_DQ<21>

FB_B_DQ<16>

FB_B_DQ<19>

FB_B_DQ<17>

FB_B_DQ<20>

FB_B_DQ<22>

FB_B_DQ<18>

FB_B_DQ<23>

95 73 71

IN

95 73 71

IN

95 73 71

IN

95 73 71

IN

95 73 71

7

BI

95 73 71

7

BI

95 73 71

7

BI

95 73 71

7

BI

95 73 71

7

BI

95 73 71

7

BI

95 73 71

7

BI

95 73 71

7

BI

95 73 71

7

BI

95 73 71

7

BI

95 73 71

7

BI

95 73 71

7

BI

95 73 71

7

BI

95 73 71

7

BI

95 73 71

7

BI

95 73 71

7

BI

95 73 71

7

BI

95 73 71

7

BI

95 73 71

7

BI

95 73 71

7

BI

95 73 71

7

BI

95 73 71

7

BI

95 73 71

7

BI

95 73 71

7

BI

95 73 71

7

BI

95 73 71

7

BI

95 73 71

7

BI

95 73 71

7

BI

95 73 71

7

BI

95 73 71

7

BI

95 73 71

7

BI

95 73 71

7

BI

95 80 73 71

95 80 73 71

95 73 71

95 73 71

95 73 71

95 73 71

95 80 73 71

95 80 73 71

95 80 73 71

95 80 73 71

95 80 73 71

95 80 73 71

95 80 73 71

95 80 73 71 95 80 73 71

95 73 71 95 73 71

95 73 71

95 80 71

95 80 73 71

95 80 73 71

95 80 73 71

95 80 73 71

95 73 71

95 73 71

95 73 71

95 73 71

95 73 71

95 73 71

95 73 71

95 73 71

95 80 73 71

95 80 73 71

95 80 73 71

FB_B_MA<0>

IN

FB_B_MA<1>

IN

FB_B_UMA<2>

IN

FB_B_UMA<3>

IN

FB_B_UMA<4>

IN

FB_B_UMA<5>

IN

FB_B_MA<6>

IN

FB_B_MA<7>

IN

FB_B_MA<8>

IN

FB_B_MA<9>

IN

FB_B_MA<10>

IN

FB_B_MA<11>

7

IN

FB_B_CKE

IN

FB_B_MA<12>

FB_B_CLK_P<1>

FB_B_CLK_N<1>

IN

FB_B_CS1_L

IN

FB_B_WE_L

IN

FB_B_CAS_L

7

IN

FB_B_RAS_L

IN

FB_B_DRAM_RST

IN

FB_B_RDQS<5>

OUT

FB_B_RDQS<6>

OUT

FB_B_RDQS<7>

OUT

FB_B_RDQS<4>

OUT

FB_B_WDQS<5>

IN

FB_B_WDQS<6>

IN

FB_B_WDQS<7>

IN

FB_B_WDQS<4>

IN

FB_B_BA<0>

IN

FB_B_BA<1>

7

IN

FB_B_BA<2>

IN

VRAM8

R9290

VRAM8

1

R9298

1K

5%
1/16W
MF-LF

402

1/16W
MF-LF

2

FB_B3_ZQ

FB_B3_MF

FB_B3_SEN

VRAM8

1

1

R9299

100

243

5%

1%

1/16W
MF-LF
402

402

2

2

8

76

5

4

3

2

1

87

www.vinafix.vn

6

5

4

3

21

DisplayPort Mux

=PP3V3_S0_DPMUX

81

8

MUXGFX

1

J4

SIGNAL_MODEL=DPMUX

LO=PORT1
HI=PORT2

A2

VDD

MUXGFX

U9320

CBTL06141EE

BGA

CRITICAL

DOUT_0+
DOUT_0-

DOUT_1+
DOUT_1-

DOUT_2+
DOUT_2-

DOUT_3+
DOUT_3-

LO=AUX_CH
HI=DDC

DDC_AUX_SEL

GND

H7H4G8C8B3

AUX+
AUX-

HPDIN

TST0

LVDS Transmitter Termination

All emulated LVDS outputs require this termination

PLACEMENT_NOTE=Place at U9600

PLACEMENT_NOTE=Place at U9600

PLACEMENT_NOTE=Place at U9600

PLACEMENT_NOTE=Place at U9600

PLACEMENT_NOTE=Place at U9600

PLACEMENT_NOTE=Place at U9600

PLACEMENT_NOTE=Place at U9600

PLACEMENT_NOTE=Place at U9600

PLACEMENT_NOTE=Place at U9600

PLACEMENT_NOTE=Place at U9600

PLACEMENT_NOTE=Place at U9600

PLACEMENT_NOTE=Place at U9600

PLACEMENT_NOTE=Place at U9600

PLACEMENT_NOTE=Place at U9600

PLACEMENT_NOTE=Place at U9600

PLACEMENT_NOTE=Place at U9600

PLACEMENT_NOTE=Place at U9600

PLACEMENT_NOTE=Place at U9600

PLACEMENT_NOTE=Place at U9600

PLACEMENT_NOTE=Place at U9600

PLACEMENT_NOTE=Place at U9600

PLACEMENT_NOTE=Place at U9600

PLACEMENT_NOTE=Place at U9600

PLACEMENT_NOTE=Place at U9600

D

LVDS_A_CLK_P

95 84

IN

LVDS_A_CLK_N

95 84

IN

7

7

95 84

LVDS_A_DATA_P<0>

IN

LVDS_A_DATA_N<0>

IN

LVDS_A_DATA_P<1>

IN

95 84

95 84

C

LVDS_A_DATA_N<1>

95 84

IN

LVDS_A_DATA_P<2>

95 84

IN

LVDS_A_DATA_N<2>

95 84

IN

95 84

B

95 84

95 84

A

LVDS_B_CLK_P

7

IN

LVDS_B_CLK_N

95 84

IN

LVDS_B_DATA_P<0>

7

IN

LVDS_B_DATA_N<0>

7

IN

LVDS_B_DATA_P<1>

95 84

IN

LVDS_B_DATA_N<1>

95 84

IN

LVDS_B_DATA_P<2>

95 84

IN

LVDS_B_DATA_N<2>

95 84

IN

PART#

114S0517

114S0174 GMUX_1V8

DESCRIPTION

QTY

RES,MTL FILM,270 OHM,1%,1/16W,0402,SMD,L

16

RES,MTL FILM,1/16W,357 OHM,1,0402,SMD,LF

16

OMIT

R9320

270

1%
1/16W
MF-LF

402

OMIT

R9322

270

1%
1/16W
MF-LF

402

OMIT

R9330

270

1%
1/16W
MF-LF

402

OMIT

R9332

270

1%
1/16W
MF-LF

402

OMIT

R9340

270

1%
1/16W
MF-LF

402

OMIT

R9342

270

1%
1/16W
MF-LF

402

OMIT

R9350

270

1%
1/16W
MF-LF

402

OMIT

R9352

270

1%
1/16W
MF-LF

402

21

21

21

21

21

21

21

21

GMUX_2V5

1

R9321

133

SIGNAL_MODEL=EMPTY

1%
1/16W
MF-LF
402

2

OMIT

R9325

270

21

1%
1/16W
MF-LF

402

OMIT

R9327

270

21

1%
1/16W
MF-LF

402

GMUX_2V5

1

R9331

133

SIGNAL_MODEL=EMPTY

1%
1/16W
MF-LF
402

2

OMIT

R9335

270

21

1%
1/16W
MF-LF

402

OMIT

R9337

270

21

1%
1/16W
MF-LF

402

GMUX_2V5

1

R9341

133

SIGNAL_MODEL=EMPTY

1%
1/16W
MF-LF
402

2

OMIT

R9345

270

21

1%
1/16W
MF-LF

402

OMIT

R9347

270

21

1%
1/16W
MF-LF

402

GMUX_2V5

1

R9351

133

SIGNAL_MODEL=EMPTY

1%
1/16W
MF-LF
402

2

OMIT

R9355

270

21

1%
1/16W
MF-LF

402

OMIT

R9357

270

21

1%
1/16W
MF-LF

402

REFERENCE DESIGNATOR(S)

R9320,R9322,R9325,R9327,R9330,R9332,R9335,R9337,R9340,R9342,R9345,R9347,R9350,R9352,R9355,R9357

R9320,R9322,R9325,R9327,R9330,R9332,R9335,R9337,R9340,R9342,R9345,R9347,R9350,R9352,R9355,R9357

LVDS_CONN_A_CLK_P

LVDS_CONN_A_CLK_N

LVDS_CONN_A_DATA_P<0>

GMUX_2V5

1

R9326

133

1%
1/16W
MF-LF
402

2

LVDS_CONN_A_DATA_N<0>

LVDS_CONN_A_DATA_P<1>

LVDS_CONN_A_DATA_N<1>

LVDS_CONN_A_DATA_P<2>

GMUX_2V5

1

R9336

133

1%
1/16W
MF-LF
402

2

LVDS_CONN_A_DATA_N<2>

LVDS_CONN_B_CLK_P

LVDS_CONN_B_CLK_N

LVDS_CONN_B_DATA_P<0>

GMUX_2V5

1

R9346

133

1%
1/16W
MF-LF
402

2

LVDS_CONN_B_DATA_N<0>

LVDS_CONN_B_DATA_P<1>

LVDS_CONN_B_DATA_N<1>

LVDS_CONN_B_DATA_P<2>

GMUX_2V5

1

R9356

133

1%
1/16W
MF-LF
402

2

LVDS_CONN_B_DATA_N<2>

(All 24 resistors)

SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=EMPTY

CRITICAL BOM OPTION

GMUX_2V5

95 78

OUT

1/16W
MF-LF

10K

90 18

95 76

95 76

95 76

95 76

95 76

95 76

95 76

95 76

95 76

95 76

1

1%

402

2

90 18

BI

9

OUT

75

OUT

DP_IG_AUX_CH_N

DP_IG_HPD

R9304

100K

1/16W
MF-LF

402

DP_EG_HPD

R9305

100K

1/16W
MF-LF

402

1

5%

2

1

R9306

1K

5%
1/16W
MF-LF

402

2

1

5%

2

=PP3V3_S0_DPMUX

8

81

DPMUX_EN_S0&DPMUX_EN_PLD

R9302

95 78

OUT

95 78

7

OUT

95 78

7

OUT

95 78

7

OUT

95 78

7

OUT

95 78

7

OUT

95 78

7

OUT

DPMUX_EN_PLD

R9303

1/16W
MF-LF

0

21

5%

402

95 78

OUT

95 78

OUT

95 78

7

OUT

DP_MUX_EN

84

IN

LVDS DDC MUX

95 78

7

OUT

=PP3V3_S0_LVDSDDCMUX

84

IN

84

IN

8

LVDS_DDC_SEL_EG

LVDS_DDC_SEL_IG

C9370

0.1UF

20%
10V

CERM

402

95 78

7

OUT

95 78

7

OUT

95 78

7

OUT

95 78

7

OUT

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

90

90

90

90

90

90

90

90

75

75

75

75

84

84

18

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

BI

9

IN

9

BI

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

IN

BI

IN

OUT

OUT

1

2

DP_IG_ML_P<0>
DP_IG_ML_N<0>

DP_IG_ML_P<1>
DP_IG_ML_N<1>

DP_IG_ML_P<2>
DP_IG_ML_N<2>

DP_IG_ML_P<3>
DP_IG_ML_N<3>

DP_IG_AUX_CH_P

DP_IG_DDC_CLK
DP_IG_DDC_DATA

DP_EG_ML_P<0>
DP_EG_ML_N<0>

DP_EG_ML_P<1>
DP_EG_ML_N<1>

DP_EG_ML_P<2>
DP_EG_ML_N<2>

DP_EG_ML_P<3>
DP_EG_ML_N<3>

DP_EG_AUX_CH_P
DP_EG_AUX_CH_N

DP_EG_DDC_CLK
DP_EG_DDC_DATA

DP_MUX_SEL_EG

DP_HOTPLUG_DET

MAKE_BASE=TRUE

DP_IG_CA_DET

=PP3V3_GPU_LVDS_DDC

8

14

VCC

U9370

QFN1

13

C1

5

C2

6

SN74LV4066A

C3

12

C4

GND

THRM

7

R9372

1

A1

2

B1

4

A2

3

B2

8

A3

9

B3

11

A4

10

B4

15

DP_MUX_XSD_L

1

20K

5%
1/16W
MF-LF

402

2

C9330

0.1uF

C9331

0.1uF

C9335

0.1uF

C9336

0.1uF

DPMUX_EN_HPD

R9370

1

R9373

20K

5%
1/16W
MF-LF
402

2

R9301

20K

5%
1/16W
MF-LF

402

21

96

21

96

21

95

21

95

1

10K

1%
1/16W
MF-LF

402

2

1

1

R9371

20K

2

2

DP_IG_AUX_CH_C_P

16V10% 402X5R

DP_IG_AUX_CH_C_N

16V10% 402X5R

DP_EG_AUX_CH_C_P

16V10% 402X5R

DP_EG_AUX_CH_C_N

16V

40210% X5R

1

C9301

1UF

10%

6.3V

2

CERM-X5R
402

5%
1/16W
MF-LF
402

LVDS_EG_DDC_CLK

LVDS_IG_DDC_CLK
LVDS_DDC_CLK

LVDS_EG_DDC_DATA

LVDS_IG_DDC_DATA
LVDS_DDC_DATA

DPMUX_EN_HPD

B4

DIN1_0+

A4

DIN1_0-

B5

DIN1_1+

A5

DIN1_1-

B6

DIN1_2+

A6

DIN1_2-

A8

DIN1_3+

A9

DIN1_3-

H9

DAUX1+

J9

DAUX1-

H8

DDC_CLK1

J8

DDC_DAT1

J2

HPD_1

B8

DIN2_0+

B9

DIN2_0-

D8

DIN2_1+

D9

DIN2_1-

E8

DIN2_2+

E9

DIN2_2-

F8

DIN2_3+

F9

DIN2_3-

H6

DAUX2+

J6

DAUX2-

H5

DDC_CLK2

J5

DDC_DAT2

H3

HPD_2

A1

GPU_SEL

B7

XSD*

75

IN

18

IN

78

7

OUT

75

BI

18

BI

78

7

BI

C9320

0.1UF

20%
10V

2

CERM
402

B2

B1

D2

D1

E2

E1

F2

F1

H2

H1

PLACEMENT_NOTE=Place at U9320

J1

DP_HPD_R

C2

G2

MAKE_BASE=TRUE

SYNC_MASTER=M98_MLB

APPLE INC.

MUXGFX

1

C9321

0.1UF

20%
10V

2

CERM
402

DP_ML_P<0>
DP_ML_N<0>

DP_ML_P<1>
DP_ML_N<1>

DP_ML_P<2>
DP_ML_N<2>

DP_ML_P<3>
DP_ML_N<3>

DP_AUX_CH_C_P
DP_AUX_CH_C_N

95 82

OUT

95 82

OUT

95 82

OUT

95 82

OUT

95 82

OUT

95 82

OUT

95 82

OUT

95 82

OUT

95 82

BI

95 82

BI

MUXGFX

R9307

1K

DP_CA_DET

1/16W
MF-LF

21

5%

402

IN

DP_HPD

84 82 75

Muxed Graphics Support

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

SHT

82

IN

051-8071

81 98

SYNC_DATE=05/01/2008

REV.

B

OF

D

C

B

A

8

76

5

4

3

2

1

87

www.vinafix.vn

Port Power Switch

D

=PP3V3_S5_DP_PORT_PWR

8

84 67 41 36 33 21

HDMI_CEC

C

84 81 75

1

R9425

1M

5%
1/16W
MF-LF
402

2

95 81

95 81

95 81

95 81

=PP3V3_S0_DPCONN

82

8

DP_CA_DET

OUT

IN

IN

BI

BI

DP_ML_P<3>

DP_ML_N<3>

DP_AUX_CH_C_P

DP_AUX_CH_C_N

B

Q9440 must have Drain to Gate leakage of <500nA and Gate to Source resistance of >5MOhm

7

IN

PM_SLP_S3_L

C9414

C9415

2N7002DW-X-G

C9480

0.1uF

0.1uF

R9443

Q9440

10UF

100K

SOT-363

1/16W
MF-LF

6.3V

20%

X5R
603

5%

402

1

2

21

DP_ML_C_P<3>

95

10% X5R

16V 402

21

DP_ML_C_N<3>

95

10% X5R

16V 402

1

2

6

D

G

S

1

1

C9481

0.1UF

20%
10V

2

CERM
402

2

2N7002DW-X-G

5

4

R9442

100K

5%
1/16W
MF-LF

402

DP_CA_DET_L_Q

Q9440

SOT-363

IN

EN

R9403

R9413

1

2

3

4

CRITICAL

U9480

TPS2051B

SOT23

GND
2

D

G

S

1

OUT

3

OC*

1

C9485

0.1UF

20%
10V

2

CERM

402

NO STUFF

0

0

4

32

5

NO STUFF

CRITICAL

FL9403

12-OHM-100MA

TCM1210-4SM

SYM_VER-2

21

21

6

TP_DPPWR_OC_L

CRITICAL

1

C9486

22UF

20%

6.3V

2

X5R-CERM
603

5%

1/16W

5%

1/16W

1

R9420

MF-LF

MF-LF

R9421

100K

5%
1/16W
MF-LF

402

DP_CA_DET_Q

100K

5%
1/16W
MF-LF

402

402

402

1

2

R9422

1

2

1/16W
MF-LF

1M

402

PP3V3_S0_DPILIM

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V

DP_ML_CONN_P<3>

95

DP_ML_CONN_N<3>

95

DP to DVI/HDMI

1

Cable Adapter
(CA) has 100k

5%

pull-up to DP_PWR.

2

DP_ESD

CRITICAL

D9411

RCLAMP0524P

SLP2510P8

IO

9

NC NC

GND

3

21

45

76

MF-LF

MF-LF

DP_ML_C_P<0>

95

DP_ML_C_N<0>

95

DP_ML_C_P<1>

DP_ML_C_N<1>

DP_ML_C_P<2>

DP_ML_C_N<2>

402

402

21

C9410

C9411

C9412

C9413

C9416

C9417

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

DP_ML_P<0>

16V10% 402X5R

21

DP_ML_N<0>

10% 16V 402X5R

21

DP_ML_P<1>

16V10% 402X5R

21

DP_ML_N<1>

16V10% 402X5R

21

DP_ML_P<2>

16V10% 402X5R

21

DP_ML_N<2>

16V10% 402X5R

IN

IN

IN

IN

IN

IN

1/16W

1/16W

4

32

95

95

95

95

402

402

D

C

95 81

95 81

95 81

95 81

95 81

95 81

B

12

IO

10

NO STUFF

NO STUFF

FL9401

12-OHM-100MA

TCM1210-4SM

SYM_VER-2

CRITICAL

R9402

R9432

45

IO

76

3

DP_ESD

CRITICAL

D9410

RCLAMP0524P

SLP2510P8

IO

IO

NC NC

GND

3

NO STUFF

SYM_VER-2

0

0

402

402

4

32

R9400

21

5%

21

5%

R9430

1/16W

MF-LF

1/16W

MF-LF

4

32

FL9402

12-OHM-100MA

TCM1210-4SM

1

CRITICAL

NO STUFF

0

0

NO STUFF

21

5%

21

5%

CRITICAL

FL9400

12-OHM-100MA

TCM1210-4SM

1

1/16W

1/16W

NO STUFF

SYM_VER-2

MF-LF

MF-LF

21

5%

21

5%

ML_LANE0P
ML_LANE0N

ML_LANE1P
ML_LANE1N

ML_LANE2P
ML_LANE2N

RETURN

GND

GND

GND

4

DP_ESD

CRITICAL

D9410

RCLAMP0524P

SLP2510P8

IO

9

NC NC

GND

3

R9401

R9431

95

1

3

5

95

9

11

95

15

17

19

95

DP_ML_CONN_P<1>

DP_ML_CONN_N<1>

95

95

0

0

DP_ML_CONN_P<0>
DP_ML_CONN_N<0>

1

DP_ML_CONN_P<2>

DP_ML_CONN_N<2>

5

FERR-120-OHM-3A

1

C9400

0.01UF

20%
50V

2

CERM
603

L9400

0603

21

PP3V3_S0_DPPWR

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V

CRITICAL

J9400

DSPLYPRT-M97

F-RT-THSM

BOT ROW TOP ROW

TH PINS SM PINS

2

4

6

8 7

10

12

14 13

16

18

20

OMIT

HOT_PLUG_DETECT
CONFIG1
CONFIG2
GND
ML_LANE3P
ML_LANE3N
GND
AUX_CHP
AUX_CHN
DP_PWR

SHIELD PINS

22 21

12

IO

10

DP_ESD

CRITICAL

D9400

RCLAMP0504F

SC70-6-1

1

3

6

52

4

DP_ESD

CRITICAL

D9411

RCLAMP0524P

SLP2510P8

IO
NC NC

GND

3

=PP3V3_S0_DPCONN

82

8

DP_HPD

81

OUT

2N7002DW-X-G

R9445

Q9441

SOT-363

1

10K

5%

1/16W

MF-LF

402

2

6

D

2

G

S

1

A

8

76

DP_HPD_L_Q

2N7002DW-X-G

R9444

Q9441

SOT-363

1

10K

5%

1/16W

MF-LF

402

2

PART NUMBER

514-0637 CRITICAL

3

D

5

G

S

4

DP_HPD_Q

R9423

100K

1

5%

1/16W

MF-LF

402

2

DP Source must pull

down HPD input with

greater than or equal

to 100K (DPv1.1a).

5

4

QTY

1

3

DESCRIPTION

CONN,RCP,MDP,HB,20P,P=0.6

REFERENCE DES

J9400

SYNC_MASTER=K20_MLB

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

APPLE INC.

2

CRITICAL

BOM OPTION

DisplayPort Connector

SYNC_DATE=09/24/2008

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SIZE

D

SCALE

NONE

051-8071

SHT

1

A

REV.

B

OF

9882

87

www.vinafix.vn

6

5

4

3

21

D

C

B

=PP1V1_S0GPU_REG

8

Vout = 1.103V

3.5A MAX OUTPUT

(Q9510 limit?)

f = 400 kHz

XW9515

SM

C9515

P1V1S0_VSNS

<Ra>

1

R9520

5.76K

1%
1/16W
MF-LF
402

2

<Rb>

1

R9521

10K

1%
1/16W
MF-LF
402

2

10UF

6.3V

D

=PPVIN_S0GPU_P1V8P1V1

8

CRITICAL

1

C9510

330UF

20%

2.0V

2

21

20%

X5R
603

1

2

NO STUFF

POLY-TANT
B2-SM

1

C9520

100PF

5%

50V

2

CERM

402

Vout = 0.7V * (1 + Ra / Rb)
(Rb should be between 10K and 100K)

CRITICAL

1

C9540

33UF

20%
16V

2

POLY-TANT

CASED2E-SM

CRITICAL

L9510

2.2UH-8.0A

PCMB065T-SM

21

PLACEMENT_NOTE=Place XW9515 next to C7615

1

C9545

1UF

10%
25V

2

X5R
603-1

CRITICAL

Q9510

SI7110DN

PWRPK-1212-8-HF

PWRPK-1212-8-HF

CRITICAL

Q9515

SI7108DN

5

D

S

321

321

CRITICAL

1

1

D

2

C9595

1UF

2

4

G

Q9565

SSM3K15FV

SOD-VESM-HF

1

GS

GPIO7_FBVDD_ALTVO

10%
25V
X5R
603-1

5

CRITICAL

D

Q9560

4

G

5

D

S

321

SI7110DN

PWRPK-1212-8-HF

S

321

1.0UH-13A-5.6MOHM

CRITICAL

Q9561

SI7108DN

PWRPK-1212-8-HF

PLACEMENT_NOTE=Place next to C7665

GPIO7

FBVDDQ

1

1.553V

0

1.8V

CRITICAL

L9560

PCMB065T-SM

XW9565

SM

21

=PP1V8_GPU_REG

Vout = 1.8V

1

20%

2

8A MAX OUTPUT

(Q9560 limit?)

F = 500 KHZ

1

C9565

10UF

20%

6.3V

2

X5R
603

21

CRITICAL

C9560

220UF

2.5V

POLY-TANT

CASE-B2-SM2

C

8

B

75

IN

C9590

R9500

4.7

21

PVIN_S0GPU_P1V1

5%
1/16W
MF-LF

=P1V1GPU_EN

IN

P1V1GPU_PGOOD

OUT

P1V8FB_PGOOD

OUT

=P1V8FB_EN

IN

402

P1V1GPU_VFB
P1V1GPU_TRIP

1

R9535

75K

1%
1/16W
MF-LF
402

2

C9500

10UF

1

10%
25V

2

X5R
805

1

C9501

1UF

10%
10V

2

X5R

402-1

VIN
BOOT1
UGATE1
PHASE1
LGATE1
OUT1
EN1

9

BYP

11

FB1
ILIM1

29

SKIP*

4

EN_LDO

20

SECFB

2

TON

THRM_PAD

GND_P1V1P1V8_SGND

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V

=PP5V_S0GPU_P1V1P1V8_GPU

(Internal 10-ohm path
from PVCC to VCC)

PP5V_S0GPU_P1V1P1V8_VCC

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V

PP5V_S0GPU_VREF

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

VCC

OMIT

U9500

ISL6236

QFN

GND

VREF3

21

VOLTAGE=5V

563

LDOREFIN

BOOT2
UGATE2
PHASE2
LGATE2

OUT2

REFIN2

ILIM2

POK1
POK2

PGND

22

XW9500

SM

LDO

EN2

REF

21

19

PVCC

CRITICAL

33

C9504

7

8

2417

2615

2516

2318

3010

2714

32

3112

1

13

28

1

1UF

10%
10V

2

X5R

402-1

NC

(=PP1V8FB_S0_REG)

GPU_P1V8_REFIN
P1V8FB_TRIP

PP2V_S0GPU_P1V8_REF

VOLTAGE=2V

1

C9585

0.1UF

20%
10V

2

CERM
402

8

(SGND)

R9585

130K

1/16W
MF-LF

C9503

1

1%

402

2

402-1

1UF

10%
10V
X5R

1

2

P1V8FB_VBST

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

<Ra>

R9563

R9564

14.0K

1/16W
MF-LF

<Rb>

127K

1/16W
MF-LF

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
GATE_NODE=TRUE

1

C9580

0.1UF

10%
50V

2

X7R
603-1

1

1%

402

2

1

1%

402

2

1

C9561

2

0.01UF

10%
16V
CERM
402

P1V8_GPU_VSNS

1

R9562

78.7K

1%
1/16W
MF-LF
402

2

GPUFB_VID_L

4

G

P1V1GPU_DRVH

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
GATE_NODE=TRUE

5

D

4

G

P1V1GPU_DRVL

MIN_LINE_WIDTH=0.6MM

C9530

0.1UF

603-1

MIN_NECK_WIDTH=0.2MM
GATE_NODE=TRUE

1

10%
50V

2

X7R

P1V1GPU_VBST

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

P1V1GPU_LL

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
SWITCH_NODE=TRUE

84 67

67

67

84 67 66

S

33UF

20%
16V

POLY-TANT

CASED2E-SM

P1V8FB_DRVH

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
GATE_NODE=TRUE

P1V8FB_DRVL

P1V8FB_LL

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
SWITCH_NODE=TRUE

Vout = 2(Req/(Ra+Req))

3

2

A

8

76

PART NUMBER

353S2312

QTY

1

DESCRIPTION

IC,ISL6236,DUAL PWM CNTRL,QFN32

REFERENCE DES

U9500

CRITICAL

CRITICAL

BOM OPTION

1.1V / 1V8 FB Power Supply

SYNC_MASTER=RXU_K20

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

5

4

3

2

SCALE

NONE

051-8071

SHT

SYNC_DATE=05/21/2008

OF

83 98

1

A

REV.

B

87

www.vinafix.vn

6

5

4

3

21

=PP3V3_S0_GMUX

84

8

C9600

R9645

10K

1%
1/16W
MF-LF
402

4.7UF

1

C9622

0.1UF

20%
10V

2

CERM
402

1

C9611

0.1UF

20%
10V

2

CERM
402

1

20%

4V

2

X5R
402

1

C9621

2

0.1UF

20%
10V
CERM
402

=PP2V5_S0_GMUX

8

1

C9610

0.1UF

2

20%
10V
CERM
402

D

=PP1V2_S0_GMUX

8

=PP3V3_S0_GMUX

84

8

1

1

R9640

10K

1%
1/16W
MF-LF

402

2

2

1

C9604

0.1UF

20%
10V

2

CERM
402

1

C9623

2

1

C9612

2

0.1UF

20%
10V
CERM
402

0.1UF

20%
10V
CERM
402

1

C9605

2

0.1UF

20%
10V
CERM
402

1

2

1

2

C9624

0.1UF

20%
10V
CERM
402

C9613

0.1UF

20%
10V
CERM
402

9 6

9 6

9 6

C

85 84

84 81

91 43 41 19

91 43 41 19

91 43 41 19

91 43 41 19

91 43 41 19

91 25 19

90 84 18

90 84 18

90 84 18

90 84 18

90 84 18

90 84 18

90 84 18

90 84 18

90 84 18

90 84 18

90 84 18

90 84 18

90 84 18

90 84 18

84 81

84 81

84

84

84 78

84

1/16W
MF-LF

10K

NO STUFF

1

1

R9646

10K

1%

1%

1/16W
MF-LF
402

402

2

2

NO STUFF

R9641

B

NO STUFF

1

R9647

10K

1%
1/16W
MF-LF
402

2

(Tie/strap low if EGPU doesn’t provide CLKREQ_L output, provide pullup to GPU rail if using CLKREQ_L output from EGPU)

1

C9606

0.1UF

20%
10V

2

CERM
402

84

6

IN

OUT

IN

9

OUT

7

OUT

OUT

OUT

81

OUT

OUT

9

OUT

84

OUT

84

OUT

84

OUT

84

OUT

9

OUT

75

OUT

OUT

7

BI

7

BI

7

BI

7

BI

7

BI

IN

25

IN

9

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

9

OUT

25

IN

84

IN

9

IN

84

IN

1

C9625

0.1UF

20%
10V

2

CERM
402

1

C9614

0.1UF

20%
10V

2

CERM
402

JTAG_GMUX_TCK
JTAG_GMUX_TDI
JTAG_GMUX_TDO
JTAG_GMUX_TMS
GMUX_TOE

GMUX_CFG0

LCD_BKLT_EN
LCD_BKLT_PWM
LVDS_DDC_SEL_EG
LVDS_DDC_SEL_IG
DP_MUX_EN
DP_MUX_SEL_EG
EG_RESET_L
EG_RAIL1_EN
EG_RAIL2_EN
EG_RAIL3_EN
EG_RAIL4_EN
EG_CLKREQ_OUT_L
DP_CA_DET_EG
LCD_PWR_EN
LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
LPC_FRAME_L
LPC_RESET_L
LPC_CLK33M_GMUX
GMUX_INT

LVDS_IG_B_DATA_P<2>
LVDS_IG_B_DATA_N<2>
TP_GMUX_PL10A
TP_GMUX_PL10B
LVDS_IG_A_DATA_P<0>
LVDS_IG_A_DATA_N<0>
LVDS_IG_A_DATA_P<1>
LVDS_IG_A_DATA_N<1>
LVDS_IG_A_DATA_P<2>
LVDS_IG_A_DATA_N<2>
LVDS_IG_B_DATA_P<0>
LVDS_IG_B_DATA_N<0>
LVDS_IG_B_DATA_P<1>
LVDS_IG_B_DATA_N<1>
LVDS_IG_A_CLK_P
LVDS_IG_A_CLK_N
LVDS_MUX_SEL_EG
TP_GMUX_PL18B_VSYNC
=GMUX_PCIE_RESET_L
GMUX_PM_SLP_S3_L
ALL_EG_PGOOD
EG_CLKREQ_IN_L

1

C9607

2

0.1UF

20%
10V
CERM
402

1

C9626

0.1UF

20%
10V

2

CERM
402

1

C9615

0.1UF

20%
10V

2

CERM
402

1

2

C9608

0.1UF

20%
10V
CERM
402

1

2

1

2

K14

L13

K13

L12

P10

M10

P12

P13

N12

P14

C9627

0.1UF

20%
10V
CERM
402

C9616

0.1UF

20%
10V
CERM
402

TCK
TDI
TDO
TMS

K2

TOE

K1

CFG0

P2

PB2A

N2

PB2B

P4

PB14A

N4

PB14B

N3

PB15A

M4

PB15B

P5

PB16A

M5

PB16B

P6

PB17A

M6

PB17B

P7

PB18A

M7

PB18B

N7

PB19A

N8

PB19B

P9

PB20A

N9

PB20B
PB30A
PB30B
PB31A
PB31B
PB32A
PB32B

B1

PL2A

B2

PL2B

C2

PL10A

D3

PL10B

D1

PL11A

E1

PL11B

D2

PL12A

E3

PL12B

F1

PL13A

G1

PL13B

F3

PL14A

G2

PL14B

H2

PL15A

G3

PL15B

H1

PL16A

H3

PL16B

L1

PL18A

L3

PL18B

K3

PL19A

L2

PL19B

N1

PL32A

P1

PL32B

1

2

B11

PM_SLP_S3_L Isolation

=PP3V3_S0_GMUX

84

8

A

7

IN

PM_SLP_S3_L

41 36 33 21

82 67

Q9670

SSM6N15FEAPE

SOT563

D

6

PART#

336S0027

341S2501

1

R9670

10K

2

1%
1/16W
MF-LF
402

2

SG

GMUX_PM_SLP_S3_L

1

MAKE_BASE=TRUE

DESCRIPTION

QTY

IC,XP2-8,HF,CPLD,BLANK

IC,CPLD,LATTICE,132CSBGA,REV,K20

1

EG_PWRSEQ_EN

84

REFERENCE DESIGNATOR(S)

U9600

U9600

84

CRITICAL BOM OPTION

CRITICAL1GMUX_8K_BLANK

CRITICAL

GMUX CPLD

1

C9628

0.1UF

20%
10V

2

CERM
402

1

C9617

0.1UF

20%
10V

2

CERM
402

C9609

0.1UF

20%
10V
CERM
402

N11

J13J3C4

VCC

(OD)

BANK5

(OD)

BANK7 BANK6BANK4

GMUX_PROG

GND

LVDS_IG_A_CLK_P

1

C9629

0.1UF

20%
10V

2

CERM
402

PP3V3_S0_GMUX_ULC_VCCPLL

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

PP3V3_S0_GMUX_LRC_VCCPLL

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

GMUX_JTAG_TCK Inversion

K12

VCCIO5

GNDIO7

E2C1M2P3N6

F2C3M1N5M3M9M12

VCCIO6

VCCIO7

LRC_GNDPLL

ULC_GNDPLL

B4

M11

VCCJ

BANK0

BANK1

BANK2

BANK3

A4

P11

LRC_VCCPLL

ULC_VCCPLL

PT2A
PT2B
PT3A
PT3B
PT4A

PT4B
PT14A
PT14B
PT15A
PT15B
PT16A
PT16B
PT17A
PT17B
PT18A
PT18B
PT19A
PT19B
PT20A
PT20B
PT32A
PT32B

PR2A

PR2B
PR10A
PR10B
PR11A
PR11B
PR12A
PR12B
PR13A
PR13B
PR14A
PR14B
PR15A
PR15B
PR16A
PR16B
PR18A
PR18B
PR30A
PR30B

F13

C14

A12B7B5

M8

J14J2C11

P8

VCCAUX

VCCIO0

VCCIO1

VCCIO2

VCCIO3

VCCIO4

OMIT

CRITICAL

U9600

XP28

CSBGA-HF

GNDIO0

GNDIO1

GNDIO2

GNDIO3

GNDIO4

GNDIO5

GNDIO6

C6

B8

J1

N10

M14

E13

C13

C12

84

LVDS_B_DATA_P<0>

A2

LVDS_B_DATA_N<0>

A3

LVDS_B_DATA_P<1>

A1

LVDS_B_DATA_N<1>

B3

LVDS_B_DATA_P<2>

C5

LVDS_B_DATA_N<2>

A5

EG_PWRSEQ_EN

B6

GMUX_DEBUG_RESET_L

C7

LVDS_A_CLK_P

A6

LVDS_A_CLK_N

A7

LVDS_B_CLK_P

C8

LVDS_B_CLK_N

C9

LVDS_A_DATA_P<0>

A8

LVDS_A_DATA_N<0>

B9

LVDS_A_DATA_P<1>

A9

LVDS_A_DATA_N<1>

C10

LVDS_A_DATA_P<2>

B10

LVDS_A_DATA_N<2>

A10

TP_GMUX_PT20A

A11

TP_GMUX_PT20B

B12

TP_GMUX_PT32A

B13

TP_GMUX_PT32B

A13

DP_CA_DET

A14

DP_HOTPLUG_DET

B14

LVDS_EG_A_DATA_P<0>

D12

LVDS_EG_A_DATA_N<0>

D13

LVDS_EG_A_DATA_P<1>

D14

LVDS_EG_A_DATA_N<1>

E14

LVDS_EG_A_DATA_P<2>

E12

LVDS_EG_A_DATA_N<2>

F12

LVDS_EG_B_DATA_P<0>

F14

LVDS_EG_B_DATA_N<0>

G14

LVDS_EG_B_DATA_P<1>

G12

LVDS_EG_B_DATA_N<1>

G13

LVDS_EG_B_DATA_P<2>

H13

LVDS_EG_B_DATA_N<2>

H12

LVDS_EG_A_CLK_P

H14

LVDS_EG_A_CLK_N

J12

IG_LCD_PWR_EN

L14

EG_LCD_PWR_EN

M13

IG_BKLT_EN

N14

EG_BKLT_EN

N13

=PP3V3_S3_GMUX

8

6

1

C9631

0.1UF

20%
10V

2

CERM
402

FERR-220-OHM

1

C9630

0.1UF

20%
10V

2

CERM
402

JTAG_GMUX_TCK

NO STUFF

R9677

10K

1/16W
MF-LF

1%

402

21

R9684

GMUX_S0_PD_DIS_RC

0

21

5%
1/16W
MF-LF

402

NO STUFF

1

C9695

1UF

10%

6.3V

2

CERM
402

=PP3V3_S0_GMUX

84

8

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

67 41 25

IN

ALL_SYS_PWRGD

L9620

0402

1

R9676

100K

5%
1/16W
MF-LF
402

2

L9621

FERR-220-OHM

0402

21

3

D

SG

4

7

OUT

7

OUT

OUT

OUT

OUT

OUT

84

IN

84

IN

OUT

OUT

7

OUT

OUT

7

OUT

7

OUT

OUT

OUT

OUT

OUT

IN

81

IN

IN

IN

IN

IN

IN

7

IN

IN

IN

IN

IN

IN

IN

IN

IN

9

IN

75

IN

9

IN

75

IN

GMUX_S3_PD_EN

Q9607

SSM6N15FEAPE

SOT563

95 81

95 81

95 81

95 81

95 81

95 81

95 81

95 81

95 81

95 81

95 81

90 84 18

LVDS_IG_A_DATA_P<0>

90 84 18

LVDS_IG_A_DATA_P<1>

90 84 18

LVDS_IG_A_DATA_P<2> LVDS_IG_A_DATA_N<2>

90 84 18 90 84 18

LVDS_IG_B_DATA_P<0> LVDS_IG_B_DATA_N<0>

90 84 18 90 84 18

LVDS_IG_B_DATA_P<1>

90 84 18

21

LVDS_IG_B_DATA_P<2>

90 84 18

LVDS_EG_A_CLK_P LVDS_EG_A_CLK_N

95 84 76 95 84 76

LVDS_EG_A_DATA_P<0>

95 84 76

LVDS_EG_A_DATA_P<1>

95 84 76

LVDS_EG_A_DATA_P<2>

95 84 76

LVDS_EG_B_DATA_P<0> LVDS_EG_B_DATA_N<0>

95 84 76 95 84 76

LVDS_EG_B_DATA_P<1> LVDS_EG_B_DATA_N<1>

95 84 76 95 84 76

LVDS_EG_B_DATA_P<2>

95 84 76

GMUX_DEBUG_RESET_L

84

JTAG_GMUX_TCK

EG_CLKREQ_OUT_L

84

9

Q9670

SSM6N15FEAPE

SOT563

5

SILK_PART=GMUX_RST

GMUX_JTAG_TCK_L

4.7K

1/16W
MF-LF

84

84

84

84

5%

402

DP_MUX_SEL_EG

84 81

LVDS_DDC_SEL_IG

84 81

LVDS_DDC_SEL_EG

84 81

84

9

84

9

85 84

7

84

EG_RAIL1_EN

EG_RAIL2_EN

EG_RAIL3_EN

EG_RAIL4_EN

1

2

3

D

SG

4

EG_RESET_L
GMUX_INT
LCD_BKLT_PWM
EG_CLKREQ_IN_L

EG_PWRSEQ_GMUX

95 81

95 81

(Use open-drain PGOOD output to hold off the start of the GPU PWRSEQ until the first GPU rail’s source is valid)

95 81

95 81

95 81

82 81 75

95 84 76

95 84 76

95 84 76

95 84 76

95 84 76

95 84 76

LCD_PWR_EN

84 78

95 84 76

95 84 76

95 84 76

95 84 76

95 84 76

95 84 76

R9678

95 84 76

95 84 76

Q9607

SSM6N15FEAPE

SOT563

5

6

D

2

SG

1

LVDS Receiver Termination

PLACEMENT_NOTE=Place at U9600

PLACEMENT_NOTE=Place at U9600

PLACEMENT_NOTE=Place at U9600

PLACEMENT_NOTE=Place at U9600

PLACEMENT_NOTE=Place at U9600

PLACEMENT_NOTE=Place at U9600

PLACEMENT_NOTE=Place at U9600

PLACEMENT_NOTE=Place at U9600

PLACEMENT_NOTE=Place at U9600

PLACEMENT_NOTE=Place at U9600

PLACEMENT_NOTE=Place at U9600

PLACEMENT_NOTE=Place at U9600

PLACEMENT_NOTE=Place at U9600

PLACEMENT_NOTE=Place at U9600

R9650
R9651
R9652
R9653

R9654
R9655
R9656

R9660
R9661
R9662
R9663

R9664
R9665
R9666

100
100
100
100

100
100
100

100
100
100
100

100
100
100

SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=EMPTY

21

1%

21

1%

21

1/16W

1%

21

1%

21

1%

21

1%

21

1%

21

1%

1/16W MF-LF

21

1%

21

1%

21

1/16W MF-LF

1%

21

1%

21

1%

21

1%

Required Pullups

IN

NO STUFF

R9679

1/16W
MF-LF

17

10K

R9680

R9690

R9695

1

1%

402

2

1K

4.7K

10K

PLACEMENT_NOTE=Place on top side at U9600

21

21

21

5%

5%

5%

1/16W MF-LF

1/16W

Required Pulldowns

1

R9671

4.7K

5%
1/16W
MF-LF
402

2

R9630

R9631

R9632

R9633

R9634

EG_PWRSEQ_GMUX

1

R9672

4.7K

5%
1/16W
MF-LF
402

2

1

R9673

4.7K

2

R9681

R9682

R9683

R9691
R9692
R9693
R9694

5%
1/16W
MF-LF
402

EG_PWRSEQ_GMUX

1

R9675

2

10K

10K

10K

100K

20K
100K
100K

EG_PWRSEQ_HW

EG_PWRSEQ_GMUX
0

EG_PWRSEQ_GMUX
0

EG_PWRSEQ_GMUX
0

EG_PWRSEQ_GMUX
0

The MAKE BASE properties for these signals are on the POWER CONTROL page.

EG_PWRSEQ_GMUX

1

R9674

4.7K

5%
1/16W
MF-LF
402

2

GMUX_S3_PD_GND

NO STUFF

0

5%
1/16W
MF-LF
402

21

21

21

NO STUFF

21

21

21

21

21

1/16W MF-LF0402

5%

21

1/16W MF-LF

5%

21

5%

1/16W

21

5%

1/16W

21

5%

1/16W

SYNC_MASTER=T18_MXMGMUX

APPLE INC.

5%

5%

5%

5%

5%

5%

5%

(All 14 resistors)

MF-LF1/16W

MF-LF1/16W

MF-LF

MF-LF1/16W

MF-LF1/16W

MF-LF1/16W

MF-LF1/16W

MF-LF1/16W

MF-LF1/16W

MF-LF1/16W

MF-LF1/16W

MF-LF1/16W

MF-LF1/16W

MF-LF

1/16W

1/16W MF-LF

1/16W

1/16W

1/16W

1/16W MF-LF

MF-LF

MF-LF

MF-LF

402

402

402

402

402

402

402

402

402

402

402

402

402

402

402

402

402

402

402

402

NO STUFF

1

C9691

0.1UF

20%
10V

2

CERM
402

MF-LF1/16W

MF-LF

MF-LF

MF-LF

MF-LF

LVDS_IG_A_DATA_N<0>
LVDS_IG_A_DATA_N<1>

LVDS_IG_B_DATA_N<1>
LVDS_IG_B_DATA_N<2>

LVDS_EG_A_DATA_N<0>
LVDS_EG_A_DATA_N<1>
LVDS_EG_A_DATA_N<2>

LVDS_EG_B_DATA_N<2>

=PP3V3_S0_GMUX

84

8

402

402

402

402

402

402

402

EXTGPU_PWR_EN

=P1V1GPU_EN

P3V3GPU_EN

=GPUVCORE_EN

=P1V8FB_EN

NO STUFF

1

C9693

0.1UF

20%
10V

2

CERM

NO STUFF

1

C9692

0.1UF

20%
10V

2

CERM
402

402

NO STUFF

1

C9694

0.1UF

20%
10V

2

CERM
402

LVDS_IG_A_CLK_N

402

Graphics MUX (GMUX)

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

051-8071

SHT

84 98

90 84 18

90 84 18

90 84 18

90 84 18

90 84 18

95 84 76

95 84 76

95 84 76

7

95 84 76

67

OUT

83 67

OUT

68 67

OUT

77 67

OUT

83 67 66

OUT

SYNC_DATE=02/13/2008

REV.

B

OF

D

C

B

A

8

76

5

4

3

2

1

87

www.vinafix.vn

6

5

*Q9701, D9701, C9709, C9710, L9701, R9702, AND R9715 SHOULD ALL BE PLACED NEAR EACHOTHER.

4

*BOOST_FET_CNTL AND PPVOUT_S0_LCDBKLT_SW SHOULD BE KEPT AS SHORT AS POSSIBLE.

3

21

CRITICAL

L9701

R9701

49.9

1%
1/16W
MF-LF

402

BKL_VIN

1

C9702

0.1UF

10%
25V

2

X5R
402

22UH-2.5A

IHLP2525CZ-SM

PPBUS_S0_LCDBKLT_PWR

86 85

IN

D

GND_BKL_PWRGND GND_BKL_PWRGND

PLACEMENT_NOTE=XW9701 PLACE NEAR C9701

VOLTAGE=6V
MIN_NECK_WIDTH=0.375 MM
MIN_LINE_WIDTH=0.5 MM

XW9701

SM

21

85

21

R9730

MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.5 mm

MF-LF

PPVIN_S0_LCDBKLT_BUF

VOLTAGE=6V
MIN_NECK_WIDTH=0.375MM

0

5%

1/10W

603

CRITICAL

1

C9701

10UF

10%
25V

2

X5R
805

PLACEMENT_NOTE=C9701 PLACE NEAR L9701

MIN_LINE_WIDTH=0.5MM

21

21

PPVOUT_S0_LCDBKLT_SW

VOLTAGE=50V
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm

PLACEMENT_NOTE=L9701 PLACE NEAR Q9701

SWITCH_NODE=TRUE

BOOST_FET_CNTL

MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.6MM

4

BOOST_SINK

R9704

21

100

BKL_VREF_4V9

85

PPBUS_S0_LCDBKLT_PWR

86 85

1

R9707

C

21

2.67K

1%
1/16W
MF-LF

402

PLACEMENT_NOTE=R9707 AWAY FROM Q9701

PLACEMENT_NOTE=R9708 AWAY FROM Q9701

R9708

21

100K

1%
1/16W
MF-LF

402

C9703

1UF

10%
10V

2

X5R
402

PLACEMENT_NOTE=R9709 AWAY FROM Q9701

R9709

21

10K

1%
1/16W
MF-LF

402

21

R9703

5.1M

5%
1/16W
MF-LF

402

BKL_SSTCMP_RC

1

C9705

0.0022UF

10%
50V

2

CERM
402

R9731

187K

1%
1/16W
MF-LF

402

21

1

C9713

0.1UF

10%
25V

2

X5R
402

BKLT_PWM_RC

85

78

R9705

21

100K

1%
1/16W
MF-LF

402

1

C9706

0.0022UF

10%
50V

2

CERM
402

BKL_VREF_4V9

7

21

B

PLACEMENT_NOTE=R9713 AWAY FROM Q9701

CRITICAL

Q9702

NTUD3127CXXG

SOT-963

S

BKL_VREF_4V9

85

R9700

21

10K

1%
1/16W
MF-LF

402

BKL_PWR_EN_L

CRITICAL

Q9702

NTUD3127CXXG

SOT-963

2

84

7

IN

LCD_BKLT_PWM

A

N-CHN

4

6

D

G

S

1

D

G

5

BKL_VREF_IN_4V9

3

P-CHN

21

21

R9710

4.02K

1%
1/16W
MF-LF

402

R9711

8.06K

1%
1/16W
MF-LF

402

IN

R9733

4.7K

5%
1/16W

MF-LF

402

BKLT_PLL_NOT

BKLT_EN

7

BKL_SYNC

21

1

C9714

1UF

10%
10V

2

X5R
402

R9713

0

5%
1/16W
MF-LF
402

BKLT_PLL

21

R9734

MF-LF

5%

402

0

1/16W

BKL_VSYNC

R9706

21

10K

5%
1/16W
MF-LF

402

BKL_ISET

BKL_RT

BKL_SSTCMP

BKL_DIM

BKL_LPF

PLACEMENT_NOTE=R9714 AWAY FROM Q9701

BKLT_PLL

R9714

21

10K

5%
1/16W
MF-LF

BKLT_PLL

1

C9707

2.2UF

20%

6.3V

2

CERM
402-LF

402

BKLT_PLL

BKL_LRT_RC

1

2

C9708

0.1UF

10%
25V
X5R
402

OMIT

CRITICAL

4

5

17

8

6

7

20

19

BKL_LRT

18

85

R9727

21

75K

1%
1/16W
MF-LF

402

PLACEMENT_NOTE=R9727 AWAY FROM Q9701

3

VIN

U9700

QFN

VREF

ENA

VSYNC

ISET

RT

SSTCMP

DIM

LPF

LRT

GNDA

13

GND_BKL_PWRGND

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

1

DRV

2

10

11

12

14

15

16

9

BOOST_SINK_R

BKL_ISEN1

BKL_ISEN2

BKL_ISEN3

BKL_ISEN4

BKL_ISEN5

BKL_ISEN6

ISWSEN

APP001

ISEN1

ISEN2

ISEN3

ISEN4

ISEN5

ISEN6

VSEN

THRM_PAD

21

50.4*R9724/(R9723+R9724)=2.4V

THRESHOLD=2.5V

BKL_VSEN

1%
1/16W
MF-LF

402

*R9702 AND R9715 PIN 1 SHOULD BE PLACED NEAR C9709 PIN 2

1

C9712

47PF

5%
50V

2

CERM
402

NO STUFF

R9723

21

1.2M

1%
1/10W
MF-LF

603

R9724

21

60.4K

1%
1/16W
MF-LF

402

*R9707, R9708, R9709, R9713, R9714, R9727, AND R9729 SHOULD AWAY FROM BOOST CIRCUIT

PLACEMENT_NOTE=D9701 PLACE NEAR Q9701

D9701

SOD-123

5

321

MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.5MM

PLACEMENT_NOTE=R9715 PLACE NEAR C9709 AND Q9701

R9702

21

0.4

1%

1/6W

MF

402

MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.5MM

PLACEMENT_NOTE=R9702 PLACE NEAR C9709 AND Q9701

CRITICAL

Q9701

SI7308DN

PWRPK-1212-8

R9715

21

0.4

1%

1/6W

402

GND_BKL_PWRGND_X

RB160M-60G

CRITICAL

85

MF

PLACEMENT_NOTE=C9709 PLACE NEAR C9710

21

PLACEMENT_NOTE=C9710 PLACE NEAR J9000

1

2

GND_BKL_PWRGND

XW9702

SM

CRITICAL
NO STUFF

C9709

2.2UF

10%
100V
X7R
1210

21

CRITICAL

1

C9710

1.0UF

10%
100V

2

X7R
1210

PPVOUT_S0_LCDBKLT

R9717

10.2

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

PPVOUT_S0_LCDBKLT

PART NUMBER

353S2413 CRITICAL

QTY

1

85 78

7

DESCRIPTION

IC,APP001A,WHT LED BKLGHT CTR,SCRN,QFN20

1/16W

TF

402

R9718

10.2

1/16W

TF

402

R9719

10.2

1/16W

TF

402

R9720

10.2

1/16W

TF

402

R9721

10.2

1/16W

TF

402

R9722

10.2

1/16W

TF

402

21

0.1%

21

0.1%

21

0.1%

21

0.1%

21

0.1%

21

0.1%

LED_RETURN_6

LED_RETURN_5

LED_RETURN_4

LED_RETURN_3

LED_RETURN_2

LED_RETURN_1

REFERENCE DES

U9700

LCD BACKLIGHT DRIVER

SYNC_MASTER=KIRAN_K20

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

D

APPLE INC.

SCALE

VOLTAGE=50V
MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.5 mm

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

CRITICAL

DRAWING NUMBER

NONE

051-8071

SHT

OUT

OUT

OUT

OUT

OUT

OUT

BOM OPTION

SYNC_DATE=03/19/2009

OF

85

D

C

85 78

7

OUT

78

7

78

7

78

7

78

7

78

7

78

7

B

A

REV.

B

98

8

76

5

4

3

2

1

21

www.vinafix.vn

D

C

Q9807

SOT563

6

5

1

R9808

301K

1%

1/16W

MF-LF

402

2

PPBUS_S0_LCDBKLT_EN_L

3

D

SG

4

BKLT_EN_L

1

C9802

0.1UF

10%
16V

2

X5R
402

PPBUS_S0_LCDBKLT_EN_DIV

1

R9809

147K

1%

1/16W

MF-LF

402

2

5

CRITICAL

Q9806

FDC638APZ_SBMS001

SSOT6-HF

4

3

4

PPBUS S0 LCDBkLT FET

6521

MOSFET

CHANNEL

RDS(ON)

LOADING

PPBUS_S0_LCDBKLT_PWR

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.375 MM
VOLTAGE=6V

FDC638APZ

P-TYPE

43 mOhm @4.5V

0.4 A (EDP)

85

87

F9800

D

9

8

IN

=PPBUS_S0_LCDBKLT

LVDS_BKL_ON

C

3AMP-32V-467

603-HF

21

PPBUS_S0_LCDBKLT_FUSED

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.375 MM
VOLTAGE=6V

SSM6N15FEAPE

1

R9840

4.7K

5%

1/16W

MF-LF

402

2

3

6

SOT563

D

2

SG

1

B

Q9807

SSM6N15FEAPE

BKLT_PLT_RST_L

25

IN

B

A

8

76

LCD Backlight Support

SYNC_DATE=07/18/2008SYNC_MASTER=YLEE_K20

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

5

4

3

2

SCALE

NONE

.

051-8071

SHT

86 98

1

REV.

OF

A

B

87

www.vinafix.vn

6

5

4

3

21

GMUX 1.8V/1.2V S0 Switcher

D

=PP3V3_S0_P1V2P2V5

8

CRITICAL

L9900

2.2UH-1.2A

PCAA031B-SM

CRITICAL

L9980

2.2UH-1.2A

PCAA031B-SM

C9982

21

C9901

10PF

10PF

CERM

<Ra>

1

R9900

475K

1%
1/16W
MF-LF
402

2

<Rb>

OMIT

1

R9901

150K

1%
1/16W
MF-LF
402

2

=PP1V2_S0_REG

Vout = 1.2V

300mA max output

(Switcher limit)

f = 2.25 MHz

1

C9985

4.7UF

20%
4V

2

X5R
402

=PP2V5_S0_REG

Vout = 2.5V

0.3A max output

(Switcher limit)

f = 2.25 MHz

1

C9905

4.7UF

20%
4V

2

X5R
402

21

<Ra>

1

R9982

1

280K

1%

5%

1/16W

50V

MF-LF

2

CERM

5%

50V

402

402

402

2

<Rb>

1

R9983

280K

1%
1/16W
MF-LF
402

2

1

2

8

8

PART#

114S0428 GMUX_2V5

114S0447 GMUX_1V8

DESCRIPTION

QTY

RES,MTL FILM,1/16W,150K,1,0402,SMD,LF

1

RES,MTL FILM,1/16W,237K,1,0402,SMD,LF

1

REFERENCE DESIGNATOR(S)

R9901

R9901

CRITICAL BOM OPTION

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

1

C9900

2.2UF

20%

6.3V
2

CERM

402-LF

C

=P2V5S0_EN

67

IN

=P1V2S0_EN

67

3

VIN

U9900

DFN-HF

SW1

CRITICAL

1

VFB1

8

VFB2

THRML

PAD

9

LTC3547

GND

RUN1
RUN2

5

SW2

4

6

2

7

P1V2S0_SW

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
SWITCH_NODE=TRUE

P2V5S0_SW

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE

P2V5S0_VFB

P1V2S0_VFB

D

C

Vout = 0.6V * (1 + Ra/Rb)

B

B

A

8

76

Misc Power Supplies

SYNC_MASTER=RXU_K20

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

5

4

3

2

SCALE

NONE

051-8071

SHT

SYNC_DATE=05/07/2008

OF

87 98

1

A

REV.

B

87

www.vinafix.vn

FSB (Front-Side Bus) Constraints CPU / FSB Net Properties

LAYER

FSB_50S

FSB_DSTB_50S

LAYER

D

SPACING_RULE_SET

FSB_DATA

FSB_DSTB

FSB_ADDR

FSB_ADSTB

FSB_1X =STANDARD

All 4x/2x/1x FSB signals with impedance requirements are 50-ohm single-ended.

FSB 4X signals / groups shown in signal table on right.
Signals within each 4x group should be matched within 5 ps of strobe.
DSTB# complementary pairs should be matched within 1 ps of each other, all DSTB#s matched to +/- 300 ps.
Spacing is 2x dielectric between DATA#, DINV# signals, with 3x dielectric spacing to the DSTB#s.
DSTB# complementary pairs are spaced normally and are NOT routed as differential pairs.

FSB 2X signals / groups shown in signal table on right.
Signals within each 2x group should be matched within 20 ps. ADTSB#s should be matched +/- 300 ps.
Spacing is 1x dielectric between ADDR#, REQ# signals, with 2x dielectric spacing to ADSTB#.

FSB 1X signals shown in signal table on right.
Signals within each 1x group should be matched to CPU clock, +0/-1000 mils.

Design Guide recommends each strobe/signal group is routed on the same layer.
Intel Design Guide recommends FSB signals be routed only on internal layers.

NOTE: Intel Design Guide allows closer spacing if signal lengths can be shortened.

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2
SOURCE: Santa Rosa Platform DG, Rev 1.5 (#22294), Sections 4.2 & 4.3

CPU Signal Constraints

C

CPU_50S

CPU_27P4S

NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.

SPACING_RULE_SET

CPU_AGTL

CPU_8MIL

CPU_COMP

CPU_GTLREF

CPU_ITP

CPU_VCCSENSE

Most CPU signals with impedance requirements are 55-ohm single-ended.
Some signals require 27.4-ohm single-ended impedance.

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2
SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4

LAYER

LAYER

MCP FSB COMP Signal Constraints

LAYER

MCP_50S

B

SPACING_RULE_SET

MCP_FSB_COMP

LAYER

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.4

FSB Clock Constraints

LAYER

CLK_FSB_100D

SPACING_RULE_SET

CLK_FSB

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.5

LAYER

ALLOW ROUTE
ON LAYER?

=50_OHM_SE

*

*

=50_OHM_SE

MINIMUM LINE WIDTH

=50_OHM_SE

=50_OHM_SE =50_OHM_SE =50_OHM_SE

LINE-TO-LINE SPACING

=2x_DIELECTRIC

*

*

* ?

* ?

*

*

=3x_DIELECTRIC

=STANDARD

=2x_DIELECTRIC

ALLOW ROUTE
ON LAYER?

=27P4_OHM_SE

MINIMUM LINE WIDTH

=50_OHM_SE=50_OHM_SE =50_OHM_SE=50_OHM_SE

=27P4_OHM_SE

LINE-TO-LINE SPACING

* ?

* ?

*

*

*

=STANDARD

=2:1_SPACING

ALLOW ROUTE
ON LAYER?

8 MIL

25 MIL

25 MIL

25 MIL

MINIMUM LINE WIDTH

=50_OHM_SE =50_OHM_SE=50_OHM_SE

LINE-TO-LINE SPACING

8 MIL

ALLOW ROUTE
ON LAYER?

*

=100_OHM_DIFF

MINIMUM LINE WIDTH

LINE-TO-LINE SPACING

*

=3x_DIELECTRIC

MINIMUM NECK WIDTH

TABLE_SPACING_RULE_HEAD

WEIGHT

?*

?

?

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

SPACING_RULE_SET

FSB_DATA

FSB_DSTB

FSB_ADDR

FSB_ADSTB

FSB_1X

MINIMUM NECK WIDTH

TABLE_SPACING_RULE_HEAD

WEIGHT

SPACING_RULE_SET

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?*

TABLE_SPACING_RULE_ITEM

?*

TABLE_SPACING_RULE_ITEM

?

CPU_AGTL

SR DG recommends at least 25 mils, >50 mils preferred

MINIMUM NECK WIDTH

=50_OHM_SE

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?*

MINIMUM NECK WIDTH

=100_OHM_DIFF=100_OHM_DIFF =100_OHM_DIFF

TABLE_SPACING_RULE_HEAD

WEIGHT

?

TABLE_SPACING_RULE_ITEM

SPACING_RULE_SET

CLK_FSB =4x_DIELECTRIC

MAXIMUM NECK LENGTH

=50_OHM_SE=50_OHM_SE

LAYER

TOP,BOTTOM

TOP,BOTTOM

TOP,BOTTOM

TOP,BOTTOM

TOP,BOTTOM

MAXIMUM NECK LENGTH

=27P4_OHM_SE=27P4_OHM_SE

LAYER

TOP,BOTTOM

MAXIMUM NECK LENGTH

MAXIMUM NECK LENGTH

LAYER

TOP,BOTTOM

DIFFPAIR PRIMARY GAP

LINE-TO-LINE SPACING

=4x_DIELECTRIC

=5x_DIELECTRIC

=3x_DIELECTRIC

=4x_DIELECTRIC

=3x_DIELECTRIC

DIFFPAIR PRIMARY GAP

LINE-TO-LINE SPACING

=2x_DIELECTRIC

DIFFPAIR PRIMARY GAP

DIFFPAIR PRIMARY GAP

LINE-TO-LINE SPACING

A

6

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

WEIGHT

WEIGHT

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

=STANDARD

=STANDARD=STANDARD

=STANDARD=STANDARD

=100_OHM_DIFF

=STANDARD

=1:1_DIFFPAIR =1:1_DIFFPAIR

7 MIL 7 MIL

=100_OHM_DIFF

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

5

ELECTRICAL_CONSTRAINT_SET

FSB_DATA_GROUP0

FSB_DATA_GROUP0

FSB_DSTB0

FSB_DSTB0

FSB_DATA_GROUP1

FSB_DATA_GROUP1

FSB_DSTB1

FSB_DSTB1

FSB_DATA_GROUP2

FSB_DATA_GROUP2

FSB_DSTB2

FSB 4X Signal Groups

FSB 2X

Signals

FSB 1X Signals

FSB_DSTB2

FSB_DATA_GROUP3

FSB_DATA_GROUP3

FSB_DSTB3

FSB_DSTB3

FSB_ADDR_GROUP0

FSB_ADDR_GROUP0

FSB_ADSTB0

FSB_ADDR_GROUP1

FSB_ADSTB1

FSB_1X FSB_1X

FSB_BREQ0_L

FSB_BREQ1_L

FSB_1X FSB_1X

FSB_1X FSB_1X

FSB_1X

FSB_1X

FSB_1X

FSB_1X

FSB_1X FSB_1X

FSB_1X FSB_1X

FSB_CPURST_L

FSB_1X

FSB_1X

CPU_ASYNC

CPU_BSEL

CPU_FERR_L

CPU_ASYNC

CPU_INIT_L

CPU_ASYNC_R

CPU_ASYNC_R

CPU_PROCHOT_L

CPU_PWRGD

CPU_ASYNC

CPU_ASYNC

PM_THRMTRIP_L

FSB_CPUSLP_L

CPU_FROM_SB

CPU_DPRSTP_L

CPU_ASYNC

FSB_CLK_CPU

FSB_CLK_CPU

FSB_CLK_ITP

FSB_CLK_ITP

FSB_CLK_MCP

FSB_CLK_MCP

CPU_IERR_L

PM_DPRSLPVR

(See above)

CPU_GTLREF

CPU_COMP

CPU_COMP

CPU_COMP

CPU_COMP CPU_COMP

XDP_TDI CPU_50S CPU_ITP

XDP_TDO CPU_50S CPU_ITP

XDP_TMS CPU_50S CPU_ITP

XDP_TCK CPU_50S CPU_ITP

XDP_TRST_L

XDP_BPM_L

XDP_BPM_L5

(FSB_CPURST_L)

CPU_VCCSENSE

CPU_VCCSENSE

(CPU_VCCSENSE)
(CPU_VCCSENSE)

4

NET_TYPE

PHYSICAL

FSB_50S

FSB_50S

FSB_DSTB_50S

FSB_DSTB_50S

FSB_50S

FSB_50S

FSB_DSTB_50S

FSB_DSTB_50S

FSB_50S

FSB_50S

FSB_DSTB_50S

FSB_DSTB_50S

FSB_50S

FSB_50S

FSB_DSTB_50S

FSB_DSTB_50S

FSB_50S

FSB_50S

FSB_50S

FSB_50S

FSB_50S

FSB_50S

FSB_50S

FSB_50S

FSB_50S

FSB_50S

FSB_50S

FSB_50S

FSB_50S

FSB_50S

FSB_50S

FSB_50S

FSB_50S

FSB_50S

FSB_50S

CPU_50S

CPU_50S

CPU_50S

CPU_50S

CPU_50S

CPU_50S

CPU_50S

CPU_50S

CPU_50S

CPU_50S

CPU_50S

CPU_50S

CPU_50S

CPU_50S

CPU_50S

CPU_50S

MCP_50S

MCP_50S

MCP_50S

MCP_50S

CLK_FSB_100D

CLK_FSB_100D

CLK_FSB_100D

CLK_FSB_100D

CLK_FSB_100D

CLK_FSB_100D

CPU_50S

CPU_50S

CPU_50S

CPU_50S

CPU_50S

CPU_27P4S

CPU_50S

CPU_27P4S

CPU_50S CPU_ITP

CPU_50S

CPU_50S CPU_ITP

CPU_50S

CPU_50S

CPU_27P4S

CPU_27P4S

CPU_27P4S

CPU_27P4S

FSB_DATA

FSB_DATA

FSB_DSTB

FSB_DSTB

FSB_DATA

FSB_DATA

FSB_DSTB

FSB_DSTB

FSB_DATA

FSB_DATA

FSB_DSTB

FSB_DSTB

FSB_DATA

FSB_DATA

FSB_DSTB

FSB_DSTB

FSB_ADDR

FSB_ADDR

FSB_ADSTB

FSB_ADDR

FSB_ADSTB

FSB_1X

FSB_1X

FSB_1X

FSB_1X

FSB_1X

FSB_1X

FSB_1X

FSB_1X

FSB_1X

CPU_AGTL

CPU_AGTL

CPU_8MIL

CPU_AGTL

CPU_AGTL

CPU_AGTL

CPU_AGTL

CPU_AGTL

CPU_AGTL

CPU_AGTL

CPU_AGTL

CPU_8MIL

CPU_AGTL

CPU_AGTL

CPU_AGTL

CPU_AGTL

MCP_FSB_COMPMCP_CPU_COMP

MCP_FSB_COMPMCP_CPU_COMP

MCP_FSB_COMPMCP_CPU_COMP

MCP_FSB_COMPMCP_CPU_COMP

CLK_FSB

CLK_FSB

CLK_FSB

CLK_FSB

CLK_FSB

CLK_FSB

CPU_AGTL

CPU_AGTL

CPU_GTLREF

CPU_COMP

CPU_COMP

CPU_COMP

CPU_ITP

CPU_ITPCPU_50S

CPU_8MIL

CPU_8MIL

CPU_VCCSENSE

CPU_VCCSENSE

CPU_VCCSENSE

CPU_VCCSENSE

SPACING

3

FSB_D_L<15..0>
FSB_DINV_L<0>
FSB_DSTB_L_P<0>
FSB_DSTB_L_N<0>

FSB_D_L<31..16>
FSB_DINV_L<1>
FSB_DSTB_L_P<1>
FSB_DSTB_L_N<1>

FSB_D_L<47..32>
FSB_DINV_L<2>
FSB_DSTB_L_P<2>
FSB_DSTB_L_N<2>

FSB_D_L<63..48>
FSB_DINV_L<3>
FSB_DSTB_L_P<3>
FSB_DSTB_L_N<3>

FSB_A_L<16..3>
FSB_REQ_L<4..0>
FSB_ADSTB_L<0>

FSB_A_L<35..17>
FSB_ADSTB_L<1>

FSB_ADS_L
FSB_BREQ0_L
FSB_BREQ1_L
FSB_BNR_L
FSB_BPRI_L
FSB_DBSY_L
FSB_DEFER_L
FSB_DRDY_L
FSB_HIT_L
FSB_HITM_L
FSB_LOCK_L
FSB_CPURST_L
FSB_RS_L<2..0>
FSB_TRDY_L

CPU_A20M_L
CPU_BSEL<2..0>
CPU_FERR_L
CPU_IGNNE_L
CPU_INIT_L
CPU_INTR
CPU_NMI
CPU_PROCHOT_L
CPU_PWRGD
CPU_SMI_L
CPU_STPCLK_L
PM_THRMTRIP_L
FSB_CPUSLP_L
CPU_DPSLP_L
CPU_DPRSTP_L

FSB_DPWR_L
MCP_BCLK_VML_COMP_VDD
MCP_BCLK_VML_COMP_GND
MCP_CPU_COMP_VCC
MCP_CPU_COMP_GND

FSB_CLK_CPU_P

FSB_CLK_CPU_N

FSB_CLK_ITP_P

FSB_CLK_ITP_N

FSB_CLK_MCP_P

FSB_CLK_MCP_N

CPU_IERR_L

PM_DPRSLPVR

IMVP_DPRSLPVR

CPU_GTLREF

CPU_COMP<3>

CPU_COMP<2>

CPU_COMP<1>

CPU_COMP<0>

XDP_TDI

XDP_TDO

XDP_TMS

XDP_TCK

XDP_TRST_L

XDP_BPM_L<4..0>

XDP_BPM_L<5>

XDP_CPURST_L

CPU_VID<6..0>

IMVP6_VID<6..0>

CPU_VCCSENSE_P

CPU_VCCSENSE_N

IMVP6_VSEN_P

IMVP6_VSEN_N

21

14 10

7

14 10

7

14 10

7

14 10

7

14 10

7

14 10

7

14 10

7

14 10

7

14 10

7

14 10

7

14 10

7

14 10

7

14 10

7

14 10

7

14 10

7

14 10

7

14 10

7

14 10

7

14 10

7

14 10

7

14 10

7

14 10

7

14 10

9

14

14 10

14 10

14 10

7

14 10

14 10

7

14 10

7

14 10

7

14 10

7

14 13 10

9

14 10

14 10

14 10

10

9

14 10

14 10

14 10

14 10

9

14 10

9

61 42 14 10

14 13 10

14 10

14 10

42 14 10

14 10

14 10

61 14 10

9

14 10

14

14

14

14

14 10

14 10

14 13

14 13

14

14

10

61 21

61

26 10

10

10

10

10

6

13 10

10

6

13 10

6

13 10

6

13 10

6

13 10

13 10

13

11

9

61

9

61 11

61 11

61

61

SYNC_MASTER=M98_MLB

APPLE INC.

CPU/FSB Constraints

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

051-8071

SHT

SYNC_DATE=04/01/2008

REV.

OF

9888

D

C

B

A

B

8

76

5

4

3

2

1

87

www.vinafix.vn

Memory Bus Constraints

LAYER

MEM_40S

MEM_40S_VDD

MEM_70D

MEM_70D_VDD

SPACING_RULE_SET

MEM_CLK2MEM

D

MEM_CTRL2CTRL

MEM_CTRL2MEM

MEM_CMD2CMD

MEM_CMD2MEM

MEM_DATA2DATA

MEM_DATA2MEM =3:1_SPACING

MEM_DQS2MEM

MEM_2OTHER

LAYER

Memory Bus Spacing Group Assignments

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_CLK MEM_CLK

MEM_CLK

MEM_CLK

MEM_CLK

MEM_CLK

NET_SPACING_TYPE1 NET_SPACING_TYPE2

C

MEM_CTRL

MEM_CTRL

MEM_CTRL

MEM_CTRL

MEM_CTRL

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_DQS

MEM_DQS

MEM_DQS

DDR2:

DQ signals should be matched within 20 ps of associated DQS pair.
DQS intra-pair matching should be within 1 ps, no inter-pair matching requirement.
All DQS pairs should be matched within 100 ps of clocks.
CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 140 ps.
A/BA/cmd signals should be matched within 75 ps, no CLK matching requirement.
All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate).

B

DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric.

DDR3:

DQ signals should be matched within 5 ps of associated DQS pair.
DQS intra-pair matching should be within 1 ps, inter-pair matching shoulw be within 180 ps
No DQS to clock matching requirement.
CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 2 ps.
A/BA/cmd signals should be matched within 5 ps of CLK pairs.
All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate).
DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric.

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2

MCP MEM COMP Signal Constraints

LAYER

MCP_MEM_COMP

SPACING_RULE_SET

MCP_MEM_COMP

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3.4

LAYER

ALLOW ROUTE
ON LAYER?

*

=40_OHM_SE =40_OHM_SE =40_OHM_SE =40_OHM_SE

*

=40_OHM_SE

=70_OHM_DIFF

*

*

=70_OHM_DIFF

LINE-TO-LINE SPACING

* ?

* ?

* ?

* ?

* ?

* ?

* ?

*

* ?

MEM_CTRL

MEM_CMD

MEM_DATA

MEM_DQS

MEM_CLK

MEM_CTRL

MEM_CMD

MEM_DATA

MEM_DQS

MEM_CLK

MEM_CTRL

MEM_CMDMEM_DQS

MEM_DATA

MEM_DQSMEM_DQS

=4:1_SPACING

=2:1_SPACING

=2.5:1_SPACING

=1.5:1_SPACING

=3:1_SPACING

=1.5:1_SPACING

=3:1_SPACING

25 MIL

AREA_TYPE

*

*

*

*

*

AREA_TYPE

*

*

*

*

*

AREA_TYPE

*

*

*

*

*

MINIMUM LINE WIDTH

=70_OHM_DIFF

=70_OHM_DIFF

WEIGHT

?

SPACING_RULE_SET

MEM_CLK2MEM

MEM_CLK2MEM

MEM_CLK2MEM

MEM_CLK2MEM

MEM_CLK2MEM

SPACING_RULE_SET

MEM_CTRL2MEM

MEM_CTRL2CTRL

MEM_CTRL2MEM

MEM_CTRL2MEM

MEM_CTRL2MEM

SPACING_RULE_SET

MEM_DQS2MEM

MEM_DQS2MEM

MEM_DQS2MEM

MEM_DQS2MEM

MEM_DQS2MEM

MINIMUM NECK WIDTH

=70_OHM_DIFF =70_OHM_DIFF

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CMD

MEM_CMD

MEM_CMD MEM_CMD

MEM_CMD

MEM_CMD

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_CLK

MEM_CTRL

MEM_CMD

MEM_DATA

MEM_DQS

Need to support MEM_*-style wildcards!

ALLOW ROUTE
ON LAYER?

*

LINE-TO-LINE SPACING

* ?

Y

8 MIL

MINIMUM LINE WIDTH

WEIGHT

MINIMUM NECK WIDTH

7 MIL7 MIL

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MAXIMUM NECK LENGTH

MAXIMUM NECK LENGTH

A

DIFFPAIR PRIMARY GAP

=40_OHM_SE=40_OHM_SE=40_OHM_SE

=70_OHM_DIFF=70_OHM_DIFF

MEM_CLK

MEM_CTRL

MEM_DATA

MEM_DQS

MEM_CLK

MEM_CTRL

MEM_CMD

MEM_DATA

MEM_DQS

**

**

DIFFPAIR PRIMARY GAP

=STANDARD

6

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD

=STANDARD

=70_OHM_DIFF =70_OHM_DIFF

AREA_TYPE

AREA_TYPE

AREA_TYPE

SPACING_RULE_SET

*

*

*

*

*

SPACING_RULE_SET

*

*

*

*

*

SPACING_RULE_SET

**

**

**

=STANDARD =STANDARD

MEM_CMD2MEM

MEM_CMD2MEM

MEM_CMD2CMD

MEM_CMD2MEM

MEM_CMD2MEM

MEM_DATA2MEM

MEM_DATA2MEM

MEM_DATA2MEM

MEM_DATA2DATA

MEM_DATA2MEM

MEM_2OTHER

MEM_2OTHER

MEM_2OTHER

MEM_2OTHER

MEM_2OTHER

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD

=STANDARD

=70_OHM_DIFF=70_OHM_DIFF

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

5

Memory Net Properties

ELECTRICAL_CONSTRAINT_SET

MEM_A_CLK

MEM_A_CLK

MEM_A_CNTL

MEM_A_CNTL

MEM_A_CNTL

MEM_A_CMD

MEM_A_CMD

MEM_A_CMD

MEM_A_CMD

MEM_A_CMD

MEM_A_DQ_BYTE0

MEM_A_DQ_BYTE1

MEM_A_DQ_BYTE2

MEM_A_DQ_BYTE6

MEM_A_DQ_BYTE7

MEM_A_DQS0

MEM_A_DQS0

MEM_A_DQS1

MEM_A_DQS1

MEM_A_DQS2

MEM_A_DQS2

MEM_A_DQS3

MEM_A_DQS3

MEM_A_DQS4

MEM_A_DQS4

MEM_A_DQS5

MEM_A_DQS5

MEM_A_DQS6

MEM_A_DQS6

MEM_A_DQS7

MEM_A_DQS7

MEM_B_CLK

MEM_B_CLK

MEM_B_CNTL

MEM_B_CNTL

MEM_B_CNTL

MEM_B_CMD

MEM_B_CMD

MEM_B_CMD

MEM_B_CMD

MEM_B_CMD

MEM_B_DQ_BYTE0

MEM_B_DQ_BYTE1

MEM_B_DQ_BYTE2

MEM_B_DQ_BYTE3

MEM_B_DQ_BYTE5

MEM_B_DQ_BYTE6

MEM_B_DQ_BYTE7

MEM_B_DQ_BYTE0

MEM_B_DQ_BYTE1

MEM_B_DQ_BYTE2

MEM_B_DQ_BYTE3

MEM_B_DQ_BYTE4

MEM_B_DQ_BYTE5

MEM_B_DQ_BYTE6

MEM_B_DQ_BYTE7

MEM_B_DQS0

MEM_B_DQS0

MEM_B_DQS1

MEM_B_DQS1

MEM_B_DQS2

MEM_B_DQS2

MEM_B_DQS3

MEM_B_DQS3

MEM_B_DQS4

MEM_B_DQS4

MEM_B_DQS5

MEM_B_DQS5

MEM_B_DQS6

MEM_B_DQS6

MEM_B_DQS7

MEM_B_DQS7

4

MEM_70D_VDD

MEM_70D_VDD

MEM_40S_VDD

MEM_40S_VDD

MEM_40S_VDD

MEM_40S_VDD

MEM_40S_VDD

MEM_40S_VDD

MEM_40S_VDD

MEM_40S_VDD

MEM_40S

MEM_40S

MEM_40S

MEM_40SMEM_A_DQ_BYTE3

MEM_40SMEM_A_DQ_BYTE4

MEM_40SMEM_A_DQ_BYTE5

MEM_40S

MEM_40S

MEM_40SMEM_A_DQ_BYTE0

MEM_40SMEM_A_DQ_BYTE1

MEM_40SMEM_A_DQ_BYTE2

MEM_40SMEM_A_DQ_BYTE3

MEM_40SMEM_A_DQ_BYTE4

MEM_40SMEM_A_DQ_BYTE5

MEM_40SMEM_A_DQ_BYTE6

MEM_40SMEM_A_DQ_BYTE7

MEM_70D MEM_DQS

MEM_70D MEM_DQS

MEM_70D

MEM_70D MEM_DQS

MEM_70D MEM_DQS

MEM_70D

MEM_70D MEM_DQS

MEM_70D MEM_DQS

MEM_70D MEM_DQS

MEM_70D

MEM_70D MEM_DQS

MEM_70D MEM_DQS

MEM_70D

MEM_70D

MEM_70D MEM_DQS

MEM_70D

MEM_70D_VDD

MEM_70D_VDD

MEM_40S_VDD

MEM_40S_VDD

MEM_40S_VDD

MEM_40S_VDD

MEM_40S_VDD

MEM_40S_VDD

MEM_40S_VDD

MEM_40S_VDD

MEM_40S

MEM_40S

MEM_40S

MEM_40S

MEM_40SMEM_B_DQ_BYTE4

MEM_40S

MEM_40S

MEM_40S

MEM_40S

MEM_40S

MEM_40S

MEM_40S

MEM_40S

MEM_40S

MEM_40S

MEM_40S

MEM_70D

PHYSICAL

NET_TYPE

SPACING

MEM_CLK

MEM_CLK

MEM_CTRL

MEM_CTRL

MEM_CTRL

MEM_CMD

MEM_CMD

MEM_CMD

MEM_CMD

MEM_CMD

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DQS

MEM_DQS

MEM_DQS

MEM_DQS

MEM_DQS

MEM_DQS

MEM_CLK

MEM_CLK

MEM_CTRL

MEM_CTRL

MEM_CTRL

MEM_CMD

MEM_CMD

MEM_CMD

MEM_CMD

MEM_CMD

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DATA

MEM_DQSMEM_70D

MEM_DQSMEM_70D

MEM_DQSMEM_70D

MEM_DQSMEM_70D

MEM_DQSMEM_70D

MEM_DQSMEM_70D

MEM_DQSMEM_70D

MEM_DQSMEM_70D

MEM_DQSMEM_70D

MEM_DQS

MEM_DQSMEM_70D

MEM_DQSMEM_70D

MEM_DQSMEM_70D

MEM_DQSMEM_70D

MEM_DQSMEM_70D

MEM_DQSMEM_70D

MCP_MEM_COMPMCP_MEM_COMPMCP_MEM_COMP

MCP_MEM_COMPMCP_MEM_COMPMCP_MEM_COMP

MEM_A_CLK_P<5..0>

MEM_A_CLK_N<5..0>

MEM_A_CKE<3..0>

MEM_A_CS_L<3..0>

MEM_A_ODT<3..0>

MEM_A_A<14..0>

MEM_A_BA<2..0>

MEM_A_RAS_L

MEM_A_CAS_L

MEM_A_WE_L

MEM_A_DQ<7..0>

MEM_A_DQ<15..8>

MEM_A_DQ<23..16>

MEM_A_DQ<31..24>

MEM_A_DQ<39..32>

MEM_A_DQ<47..40>

MEM_A_DQ<55..48>

MEM_A_DQ<63..56>

MEM_A_DM<0>

MEM_A_DM<1>

MEM_A_DM<2>

MEM_A_DM<3>

MEM_A_DM<4>

MEM_A_DM<5>

MEM_A_DM<6>

MEM_A_DM<7>

MEM_A_DQS_P<0>

MEM_A_DQS_N<0>

MEM_A_DQS_P<1>

MEM_A_DQS_N<1>

MEM_A_DQS_P<2>

MEM_A_DQS_N<2>

MEM_A_DQS_P<3>

MEM_A_DQS_N<3>

MEM_A_DQS_P<4>

MEM_A_DQS_N<4>

MEM_A_DQS_P<5>

MEM_A_DQS_N<5>

MEM_A_DQS_P<6>

MEM_A_DQS_N<6>

MEM_A_DQS_P<7>

MEM_A_DQS_N<7>

MEM_B_CLK_P<5..0>

MEM_B_CLK_N<5..0>

MEM_B_CKE<3..0>

MEM_B_CS_L<3..0>

MEM_B_ODT<3..0>

MEM_B_A<14..0>

MEM_B_BA<2..0>

MEM_B_RAS_L

MEM_B_CAS_L

MEM_B_WE_L

MEM_B_DQ<7..0>

MEM_B_DQ<15..8>

MEM_B_DQ<23..16>

MEM_B_DQ<31..24>

MEM_B_DQ<39..32>

MEM_B_DQ<47..40>

MEM_B_DQ<55..48>

MEM_B_DQ<63..56>

MEM_B_DM<0>

MEM_B_DM<1>

MEM_B_DM<2>

MEM_B_DM<3>

MEM_B_DM<4>

MEM_B_DM<5>

MEM_B_DM<6>

MEM_B_DM<7>

MEM_B_DQS_P<0>

MEM_B_DQS_N<0>

MEM_B_DQS_P<1>

MEM_B_DQS_N<1>

MEM_B_DQS_P<2>

MEM_B_DQS_N<2>

MEM_B_DQS_P<3>

MEM_B_DQS_N<3>

MEM_B_DQS_P<4>

MEM_B_DQS_N<4>

MEM_B_DQS_P<5>

MEM_B_DQS_N<5>

MEM_B_DQS_P<6>

MEM_B_DQS_N<6>

MEM_B_DQS_P<7>

MEM_B_DQS_N<7>

MCP_MEM_COMP_VDD

MCP_MEM_COMP_GND

3

27 15

27 15

27 15

27 15

27 15

27 15

27 15

27 15

27 15

27 15

27 15

27 15

27 15

27 15

27 15

27 15

27 15

27 15

27 15

27 15

27 15

27 15

27 15

27 15

27 15

27 15

27 15

27 15

27 15

27 15

27 15

27 15

27 15

27 15

27 15

27 15

27 15

27 15

27 15

27 15

27 15

27 15

28 15

28 15

28 15

28 15

28 15

28 15

28 15

28 15

28 15

28 15

28 15

28 15

28 15

28 15

28 15

28 15

28 15

28 15

28 15

28 15

28 15

28 15

28 15

28 15

28 15

28 15

28 15

28 15

28 15

28 15

28 15

28 15

28 15

28 15

28 15

28 15

28 15

28 15

28 15

28 15

28 15

28 15

16

16

21

D

C

B

Memory Constraints

051-8071

SHT

SYNC_DATE=04/01/2008

OF

89 98

A

REV.

B

SYNC_MASTER=M98_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

DRAWING NUMBER

D

NONE

8

76

5

4

3

2

1

87

www.vinafix.vn

PCI-Express

LAYER

PCIE_90D

CLK_PCIE_100D =100_OHM_DIFF

SPACING_RULE_SET

PCIE

CLK_PCIE

MCP_PEX_COMP

D

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.4

LAYER

Analog Video Signal Constraints

LAYER

CRT_50S

SPACING_RULE_SET

CRT

CRT_2CRT

CRT_2CLK

CRT_2SWITCHER

CRT_SYNC

MCP_DAC_COMP

CRT signal single-ended impedence varies by location:

- 37.5-ohm from MCP to first termination resistor.

- 50-ohm from first to second termination resistor.

- 75-ohm from output of three-pole filter to connector (if possible).
R/G/B signals should be matched as close as possible and < 10 inches.
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.1 & 2.5.2.

Digital Video Signal Constraints

C

LAYER

LAYER

DP_100D

LVDS_100D

MCP_DV_COMP

SPACING_RULE_SET

DISPLAYPORT

LVDS

LVDS intra-pair matching should be 5 mils. Pairs should be within 100 mils of clock length.
DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps.
DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals.
Max length of LVDS/DisplayPort/TMDS traces: 12 inches.
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4.

LAYER

SATA Interface Constraints

LAYER

SATA_100D

SPACING_RULE_SET

B

SATA

SATA_TERMP

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.7.1.

LAYER

ALLOW ROUTE
ON LAYER?

*

=90_OHM_DIFF

=100_OHM_DIFF

*

MINIMUM LINE WIDTH

=90_OHM_DIFF

=100_OHM_DIFF

LINE-TO-LINE SPACING

=3X_DIELECTRIC

20 MIL

8 MIL

ALLOW ROUTE
ON LAYER?

*

MINIMUM LINE WIDTH

=50_OHM_SE

LINE-TO-LINE SPACING

=4:1_SPACING

* ?

* ?

* ?

*

*

*

=STANDARD

250 MIL

=2:1_SPACING

ALLOW ROUTE
ON LAYER?

=100_OHM_DIFF

=100_OHM_DIFF

50 MIL

16 MIL

MINIMUM LINE WIDTH

=100_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFF

LINE-TO-LINE SPACING

=3x_DIELECTRIC

* ?

*

=3x_DIELECTRIC

ALLOW ROUTE
ON LAYER?

=100_OHM_DIFF

MINIMUM LINE WIDTH

=100_OHM_DIFF

LINE-TO-LINE SPACING

*

=4x_DIELECTRIC

8 MIL

WEIGHT

?*

?*

?*

WEIGHT

?*

?*

?*

WEIGHT

?*

WEIGHT

?

?*

MINIMUM NECK WIDTH

=90_OHM_DIFF =90_OHM_DIFF

=100_OHM_DIFF

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

PCIE

MINIMUM NECK WIDTH

=50_OHM_SE=50_OHM_SE =50_OHM_SE

TABLE_SPACING_RULE_HEAD

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

CRT CRT

MINIMUM NECK WIDTH

=100_OHM_DIFF =100_OHM_DIFF

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

DISPLAYPORT

LVDS

MINIMUM NECK WIDTH

=100_OHM_DIFF

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

SATA

A

MAXIMUM NECK LENGTH

LAYER

TOP,BOTTOM

MAXIMUM NECK LENGTH

MAXIMUM NECK LENGTH

=100_OHM_DIFF

=STANDARD20 MIL20 MILY

LAYER

TOP,BOTTOM

TOP,BOTTOM

MAXIMUM NECK LENGTH

=100_OHM_DIFF

LAYER

TOP,BOTTOM

6

DIFFPAIR PRIMARY GAP

=90_OHM_DIFF =90_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFF

LINE-TO-LINE SPACING

=4X_DIELECTRIC

DIFFPAIR PRIMARY GAP

=STANDARD

AREA_TYPE

DIFFPAIR PRIMARY GAP

LINE-TO-LINE SPACING

=4x_DIELECTRIC

=4x_DIELECTRIC

DIFFPAIR PRIMARY GAP

LINE-TO-LINE SPACING

=3x_DIELECTRIC

SPACING_RULE_SET

*

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

WEIGHT

CRT_2CRT

WEIGHT

WEIGHT

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

=STANDARD

=100_OHM_DIFF

=100_OHM_DIFF

=STANDARD=STANDARD

=100_OHM_DIFF

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

5

ELECTRICAL_CONSTRAINT_SET

PEG_R2D

PEG_D2R

PCIE_MINI_R2D

PCIE_MINI_D2R

PCIE_FW_R2D

PCIE_FW_D2R

PCIE_EXCARD_R2D

PCIE_EXCARD_D2R

MCP_PE0_REFCLK

MCP_PE1_REFCLK

MCP_PE2_REFCLK

MCP_PE3_REFCLK

MCP_PEX_CLK_COMP

CRT_RED

CRT_GREEN

CRT_BLUE

CRT_SYNC

CRT_SYNC

TMDS_IG_TXC

TMDS_IG_TXD

TMDS_IG_TXD

DP_ML

DP_ML

DP_AUX_CH

DP_AUX_CH

MCP_HDMI_RSET

MCP_HDMI_VPROBE

LVDS_IG_A_CLK

LVDS_IG_A_CLK

LVDS_IG_A_DATA

LVDS_IG_A_DATA

LVDS_IG_A_DATA3

LVDS_IG_A_DATA3

LVDS_IG_B_CLK

LVDS_IG_B_CLK

LVDS_IG_B_DATA

LVDS_IG_B_DATA

LVDS_IG_B_DATA3

LVDS_IG_B_DATA3

MCP_IFPAB_RSET

MCP_IFPAB_VPROBE

SATA_HDD_R2D

SATA_HDD_D2R

SATA_ODD_R2D

SATA_ODD_D2R

MCP_SATA_TERMP

4

NET_TYPE

PHYSICAL

PCIE_90D

PCIE_90D

PCIE_90D

PCIE_90D

PCIE_90D

PCIE_90D

PCIE_90D

PCIE_90D

PCIE_90D

PCIE_90D

PCIE_90D

PCIE_90D

PCIE_90D

PCIE_90D

PCIE_90D

PCIE_90D

PCIE_90D

PCIE_90D

PCIE_90D

PCIE_90D

PCIE_90D

PCIE_90D

PCIE_90D

PCIE_90D

PCIE_90D

PCIE_90D

PCIE_90D

PCIE_90D

CLK_PCIE_100D

CLK_PCIE_100D

CLK_PCIE_100D

CLK_PCIE_100D

CLK_PCIE_100D

CLK_PCIE_100D

CLK_PCIE_100D

CLK_PCIE_100D

CRT_50S

CRT_50S

CRT_50S

CRT_50S

CRT_50S

DP_100D

DP_100D

DP_100D

DP_100D

DP_100D

DP_100D

DP_100D

DP_100D

MCP_DV_COMP

MCP_DV_COMP

LVDS_100D

LVDS_100D

LVDS_100D

LVDS_100D

LVDS_100D

LVDS_100D

LVDS_100D

LVDS_100D

LVDS_100D

LVDS_100D

LVDS_100D

LVDS_100D

MCP_DV_COMP

SATA_100D

SATA_100D

SATA_100D

SATA_100D

SATA_100D

SATA_100D

SATA_100D

SATA_100D

SATA_100D

SATA_100D

SATA_100D

SATA_100D

SATA_100D

SATA_100D

SATA_100D

SATA_100D

SPACING

PCIE

PCIE

PCIE

PCIE

PCIE

PCIE

PCIE

PCIE

PCIE

PCIE

PCIE

PCIE

PCIE

PCIE

PCIE

PCIE

PCIE

PCIE

PCIE

PCIE

PCIE

PCIE

PCIE

PCIE

PCIE

PCIE

PCIE

PCIE

CLK_PCIE

CLK_PCIE

CLK_PCIE

CLK_PCIE

CLK_PCIE

CLK_PCIE

CLK_PCIE

CLK_PCIE

MCP_PEX_COMP

CRT

CRT

CRT

CRT_SYNC

CRT_SYNC

MCP_DAC_COMPMCP_DAC_RSET

MCP_DAC_COMPMCP_DAC_VREF

DISPLAYPORT

DISPLAYPORTTMDS_IG_TXC

DISPLAYPORT

DISPLAYPORT

DISPLAYPORT

DISPLAYPORT

DISPLAYPORT

DISPLAYPORT

LVDS

LVDS

LVDS

LVDS

LVDS

LVDS

LVDS

LVDS

LVDS

LVDS

LVDS

LVDS

SATA

SATA

SATA

SATA

SATA

SATA

SATA

SATA

SATA

SATA

SATA

SATA

SATA

SATA

SATA

SATA

SATA_TERMP

PEG_R2D_P<15..0>

PEG_R2D_N<15..0>

PEG_R2D_C_P<15..0>

PEG_R2D_C_N<15..0>

PEG_D2R_P<15..0>

PEG_D2R_N<15..0>

PEG_D2R_C_P<15..0>

PEG_D2R_C_N<15..0>

PCIE_MINI_R2D_P

PCIE_MINI_R2D_N

PCIE_MINI_R2D_C_P

PCIE_MINI_R2D_C_N

PCIE_MINI_D2R_P

PCIE_MINI_D2R_N

PCIE_FW_R2D_P

PCIE_FW_R2D_N

PCIE_FW_R2D_C_P

PCIE_FW_R2D_C_N

PCIE_FW_D2R_P

PCIE_FW_D2R_N

PCIE_FW_D2R_C_P

PCIE_FW_D2R_C_N

PCIE_EXCARD_R2D_P

PCIE_EXCARD_R2D_N

PCIE_EXCARD_R2D_C_P

PCIE_EXCARD_R2D_C_N

PCIE_EXCARD_D2R_P

PCIE_EXCARD_D2R_N

PEG_CLK100M_P

PEG_CLK100M_N

PCIE_CLK100M_MINI_P

PCIE_CLK100M_MINI_N

PCIE_CLK100M_FW_P

PCIE_CLK100M_FW_N

PCIE_CLK100M_EXCARD_P

PCIE_CLK100M_EXCARD_N

MCP_PEX_CLK_COMP

CRT_IG_R_C_PR

CRT_IG_G_Y_Y

CRT_IG_B_COMP_PB

CRT_IG_HSYNC

CRT_IG_VSYNC

MCP_TV_DAC_RSET

MCP_TV_DAC_VREF

TMDS_IG_TXC_P

TMDS_IG_TXC_N

TMDS_IG_TXD_P<2..0>

TMDS_IG_TXD_N<2..0>

DP_IG_ML_P<3..0>

DP_IG_ML_N<3..0>

DP_IG_AUX_CH_P

DP_IG_AUX_CH_N

MCP_HDMI_RSET

MCP_HDMI_VPROBE

LVDS_IG_A_CLK_P

LVDS_IG_A_CLK_N

LVDS_IG_A_DATA_P<2..0>

LVDS_IG_A_DATA_N<2..0>

LVDS_IG_A_DATA_P<3>

LVDS_IG_A_DATA_N<3>

LVDS_IG_B_CLK_P

LVDS_IG_B_CLK_N

LVDS_IG_B_DATA_P<2..0>

LVDS_IG_B_DATA_N<2..0>

LVDS_IG_B_DATA_P<3>

LVDS_IG_B_DATA_N<3>

MCP_IFPAB_RSET

MCP_IFPAB_VPROBE

SATA_HDD_R2D_C_P

SATA_HDD_R2D_C_N

SATA_HDD_R2D_P

SATA_HDD_R2D_N

SATA_HDD_D2R_P

SATA_HDD_D2R_N

SATA_HDD_D2R_C_P

SATA_HDD_D2R_C_N

SATA_ODD_R2D_C_P

SATA_ODD_R2D_C_N

SATA_ODD_R2D_P

SATA_ODD_R2D_N

SATA_ODD_D2R_P

SATA_ODD_D2R_N

SATA_ODD_D2R_C_P

SATA_ODD_D2R_C_N

MCP_SATA_TERMP

3

69

69

69

9

69

9

69

9

69

9

69

69

30

7

30

7

30 17

30 17

30 17

7

30 17

7

35

35

35 17

35 17

35 17

35 17

35

35

31

7

31

7

31 17

31 17

31 17

7

31 17

7

69 17

69 17

30 17

30 17

35 17

35 17

31 17

31 17

17

24 18

24 18

24 18

24 18

24 18

24 18

24 18

81

9

81

9

81 18

81 18

24 18

24 18

84 18

84 18

84 18

84 18

18

9

18

9

18

9

18

9

84 18

84 18

18

9

18

9

24 18

24 18

38 20

38 20

38

7

38

7

38 20

38 20

38

7

38

7

38 20

38 20

38

7

38

7

38 20

38 20

38

7

38

7

20

21

D

C

B

MCP Constraints 1

SYNC_MASTER=M98_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

DRAWING NUMBER

D

NONE

051-8071

SHT

SYNC_DATE=04/01/2008

OF

90 98

A

REV.

B

8

76

5

4

3

2

1

87

www.vinafix.vn

PCI Bus Constraints

LAYER

PCI_55S

CLK_PCI_55S

SPACING_RULE_SET

PCI =STANDARD

CLK_PCI

D

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.8.

LAYER

LPC Bus Constraints

LAYER

LPC_55S

CLK_LPC_55S

SPACING_RULE_SET

LPC

CLK_LPC

LAYER

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.9.1.

USB 2.0 Interface Constraints

LAYER

MCP_USB_RBIAS

USB_90D

SPACING_RULE_SET

USB

C

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.10.1.

LAYER

SMBus Interface Constraints

LAYER

SMB_55S

SPACING_RULE_SET

SMB

LAYER

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.11.1.

HD Audio Interface Constraints

LAYER

HDA_55S

SPACING_RULE_SET

HDA

MCP_HDA_COMP

LAYER

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.12.1.

SIO Signal Constraints

B

CLK_SLOW_55S

SPACING_RULE_SET

CLK_SLOW

LAYER

LAYER

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.13.

SPI Interface Constraints

LAYER

SPI_55S

SPACING_RULE_SET

SPI

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.14.

LAYER

ALLOW ROUTE
ON LAYER?

*

=55_OHM_SE =55_OHM_SE =55_OHM_SE

*

MINIMUM LINE WIDTH

LINE-TO-LINE SPACING

* ?

* ?

*

*

8 MIL

ALLOW ROUTE
ON LAYER?

=55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE

=55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE

MINIMUM LINE WIDTH

LINE-TO-LINE SPACING

* ?

*

*

ALLOW ROUTE
ON LAYER?

=90_OHM_DIFF

6 MIL

8 MIL

MINIMUM LINE WIDTH

LINE-TO-LINE SPACING

* ?

*

=2x_DIELECTRIC

ALLOW ROUTE
ON LAYER?

=55_OHM_SE

MINIMUM LINE WIDTH

LINE-TO-LINE SPACING

=2x_DIELECTRIC

ALLOW ROUTE
ON LAYER?

*

=55_OHM_SE =55_OHM_SE =55_OHM_SE=55_OHM_SE

MINIMUM LINE WIDTH

LINE-TO-LINE SPACING

* ?

*

=2x_DIELECTRIC

8 MIL

ALLOW ROUTE
ON LAYER?

=55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE

MINIMUM LINE WIDTH

LINE-TO-LINE SPACING

*

*

8 MIL

ALLOW ROUTE
ON LAYER?

=55_OHM_SE =55_OHM_SE =55_OHM_SE

MINIMUM LINE WIDTH

LINE-TO-LINE SPACING

*

8 MIL

MINIMUM NECK WIDTH

=55_OHM_SE

=55_OHM_SE

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM NECK WIDTH

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

?*

MINIMUM NECK WIDTH

8 MIL 8 MIL

=90_OHM_DIFF =90_OHM_DIFF

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

=90_OHM_DIFF

SPACING_RULE_SET

USB

MINIMUM NECK WIDTH

=55_OHM_SE =55_OHM_SE =55_OHM_SE

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?*

MINIMUM NECK WIDTH

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

?*

MINIMUM NECK WIDTH

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

MINIMUM NECK WIDTH

=55_OHM_SE

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

MAXIMUM NECK LENGTH

=55_OHM_SE=55_OHM_SE=55_OHM_SE

MAXIMUM NECK LENGTH

MAXIMUM NECK LENGTH

=STANDARD=STANDARD

LAYER

TOP,BOTTOM

MAXIMUM NECK LENGTH

MAXIMUM NECK LENGTH

MAXIMUM NECK LENGTH

MAXIMUM NECK LENGTH

6

DIFFPAIR PRIMARY GAP

=STANDARD

=STANDARD

DIFFPAIR PRIMARY GAP

=STANDARD

=STANDARD =STANDARD

DIFFPAIR PRIMARY GAP

=STANDARD =STANDARD

=90_OHM_DIFF =90_OHM_DIFF

LINE-TO-LINE SPACING

=4x_DIELECTRIC

DIFFPAIR PRIMARY GAP

=STANDARD =STANDARD

DIFFPAIR PRIMARY GAP

DIFFPAIR PRIMARY GAP

=STANDARD =STANDARD

DIFFPAIR PRIMARY GAP

WEIGHT

5

=STANDARD

=STANDARD

=STANDARD

=STANDARD=STANDARD

=STANDARD=STANDARD

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

ELECTRICAL_CONSTRAINT_SET

MCP_DEBUG

PCI_AD

PCI_AD24

PCI_AD

PCI_AD

PCI_C_BE_L

PCI_CNTL

PCI_CNTL

PCI_CNTL

PCI_CNTL

PCI_CNTL

PCI_CNTL

PCI_CNTL

PCI_REQ0_L

PCI_GNT0_L

PCI_REQ1_L

PCI_GNT1_L

PCI_INTW_L

PCI_INTX_L

PCI_INTY_L

PCI_INTZ_L

MCP_PCI_CLK2

LPC_AD

LPC_FRAME_L

LPC_RESET_L

MCP_LPC_CLK0

USB_EXTA

USB_MINI

USB_EXTD

USB_CAMERA

USB_BT

USB_TPAD

USB_IR

USB_EXTB

USB_EXCARD

USB_EXTC

SMBUS_MCP_0_CLK

SMBUS_MCP_0_DATA

SMBUS_MCP_1_CLK

SMBUS_MCP_1_DATA

HDA_BIT_CLK

HDA_SYNC

HDA_RST_L

HDA_SDIN0

HDA_SDOUT

MCP_HDA_PULLDN_COMP

MCP_SUS_CLK

SPI_CLK SPI_55S

SPI_MOSI

SPI_MISO

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

4

NET_TYPE

PHYSICAL

PCI_55S

PCI_55S

PCI_55S

PCI_55S

PCI_55S

PCI_55S

PCI_55S

PCI_55S

PCI_55S

PCI_55S

PCI_55S

PCI_55S

PCI_55S

PCI_55S

PCI_55S

PCI_55S

PCI_55S

PCI_55S

PCI_55S

PCI_55S

PCI_55S

CLK_PCI_55S

CLK_PCI_55S

LPC_55S

LPC_55S

LPC_55S

CLK_LPC_55S

CLK_LPC_55S

CLK_LPC_55S

USB_90D

USB_90D

USB_90D

USB_90D

USB_90D

USB_90D

USB_90D

USB_90D

USB_90D

USB_90D

USB_90D

USB_90D

USB_90D

USB_90D

USB_90D

USB_90D

USB_90D

USB_90D

USB_90D

USB_90D

USB_90D

USB_90D

MCP_USB_RBIASMCP_USB_RBIAS

SMB_55S

SMB_55S

SMB_55S

SMB_55S

HDA_55S

HDA_55S

HDA_55S

HDA_55S

HDA_55S

HDA_55S

HDA_55S

HDA_55S

HDA_55S

HDA_55S

CLK_SLOW_55S

CLK_SLOW_55S

SPI_55S

SPI_55S

SPI_55S

SPI_55S

SPI_55S

SPI_55SSPI_CS0

SPI_55S

SPACING

PCI

PCI

PCI

PCI

PCI

PCI

PCI

PCI

PCI

PCI

PCI

PCI

PCI

PCI

PCI

PCI

PCI

PCI

PCI

PCI

PCI

CLK_PCI

CLK_PCI

LPC

LPC

LPC

CLK_LPC

CLK_LPC

CLK_LPC

USB

USB

USB

USB

USB

USB

USB

USB

USB

USB

USB

USB

USB

USB

USB

USB

USB

USB

USB

USB

USB

USB

SMB

SMB

SMB

SMB

HDA

HDA

HDA

HDA

HDA

HDA

HDA

HDA

HDA

HDA

MCP_HDA_COMP

CLK_SLOW

CLK_SLOW

SPI

SPI

SPI

SPI

SPI

SPI

SPI

SPI

MCP_DEBUG<7..0>

PCI_AD<23..8>

PCI_AD<24>

PCI_AD<31..25>

PCI_PAR

PCI_C_BE_L<3..0>

PCI_IRDY_L

PCI_DEVSEL_L

PCI_PERR_L

PCI_SERR_L

PCI_STOP_L

PCI_TRDY_L

PCI_FRAME_L

PCI_REQ0_L

PCI_GNT0_L

PCI_REQ1_L

PCI_GNT1_L

PCI_INTW_L

PCI_INTX_L

PCI_INTY_L

PCI_INTZ_L

PCI_CLK33M_MCP_R

PCI_CLK33M_MCP

LPC_AD<3..0>

LPC_FRAME_L

LPC_RESET_L

LPC_CLK33M_SMC_R

LPC_CLK33M_SMC

LPC_CLK33M_LPCPLUS

USB_EXTA_P

USB_EXTA_N

USB_EXTA_MUXED_P

USB_EXTA_MUXED_N

USB_MINI_P

USB_MINI_N

USB_EXTD_P

USB_EXTD_N

USB_CAMERA_P

USB_CAMERA_N

USB_BT_P

USB_BT_N

USB_TPAD_P

USB_TPAD_N

USB_IR_P

USB_IR_N

USB_EXTB_P

USB_EXTB_N

USB_EXCARD_P

USB_EXCARD_N

USB_EXTC_P

USB_EXTC_N

MCP_USB_RBIAS_GND

SMBUS_MCP_0_CLK

SMBUS_MCP_0_DATA

SMBUS_MCP_1_CLK

SMBUS_MCP_1_DATA

HDA_BIT_CLK

HDA_BIT_CLK_R

HDA_SYNC

HDA_SYNC_R

HDA_RST_R_L

HDA_RST_L

HDA_SDIN0

HDA_SDIN_CODEC

HDA_SDOUT

HDA_SDOUT_R

MCP_HDA_PULLDN_COMP

PM_CLK32K_SUSCLK_R

PM_CLK32K_SUSCLK

SPI_CLK_R

SPI_CLK

SPI_MOSI_R

SPI_MOSI

SPI_MISO

SPI_MISO_R

SPI_CS0_R_L

SPI_CS0_L

3

19 13

19

19

19

19

84 43 41 19

7

84 43 41 19

7

84 25 19

25 19

41 25

43 25

7

39 20

39 20

20

9

20

9

20

9

20

9

30 20

30 20

30 20

30 20

49 20

49 20

40 20

40 20

39 20

39 20

31 20

31 20

98 96 20

98 96 20

20

44 21 13

7

44 21 13

7

44 21

44 21

21

9

21

53 21

21

21

53 21

53 21

53 21

21

21

25 21

41 25

43 21

52

43 21

52

43 21

52

43 21

21

D

C

B

A

8

76

MCP Constraints 2

SYNC_MASTER=M98_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

5

4

3

2

SCALE

NONE

051-8071

SHT

SYNC_DATE=04/01/2008

OF

1

A

REV.

B

9891

87

www.vinafix.vn

MCP RGMII (Ethernet) Constraints

LAYER

MCP_MII_COMP

ENET_MII_55S

SPACING_RULE_SET

MCP_BUF0_CLK

ENET_MII

D

SOURCE: MCP73 Interface DG (DG-02974-001_v01), Sections 2.7.2 & 2.7.4

LAYER

88E1116R (Ethernet PHY) Constraints

LAYER

ENET_MDI_100D

SPACING_RULE_SET

ENET_MDI

SOURCE: MCP73 Interface DG (DG-02974-001_v01), Section 2.7.4

LAYER

ALLOW ROUTE
ON LAYER?

*

=STANDARD

*

=55_OHM_SE

LINE-TO-LINE SPACING

* ?

ALLOW ROUTE
ON LAYER?

*

=100_OHM_DIFF

LINE-TO-LINE SPACING

* ?

MINIMUM LINE WIDTH

7.5 MIL

=55_OHM_SE =55_OHM_SE =55_OHM_SE

=3:1_SPACING

12 MIL

MINIMUM LINE WIDTH

25 MIL

WEIGHT

?*

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM NECK WIDTH

7.5 MIL

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF

6

DIFFPAIR PRIMARY GAP

DIFFPAIR PRIMARY GAP

=100_OHM_DIFF =100_OHM_DIFF

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

5

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

=STANDARD=STANDARD

TABLE_PHYSICAL_RULE_ITEM

=STANDARD=STANDARD

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

ELECTRICAL_CONSTRAINT_SET

MCP_MII_COMP

MCP_MII_COMP

MCP_CLK25M_BUF0

ENET_INTR_L

ENET_MDIO

ENET_PWRDWN_L

ENET_RXCLK

ENET_RXD

ENET_RXD_STRAP

ENET_RXD

ENET_TXCLK

ENET_TXD0

ENET_TXD

ENET_TXD

ENET_MDI

4

PHYSICAL

MCP_MII_COMP

MCP_MII_COMP

ENET_MII_55S MCP_BUF0_CLK

ENET_MII_55S MCP_BUF0_CLK

ENET_MII_55S

ENET_MII_55S

ENET_MII_55S

ENET_MII_55S

ENET_MII_55S

ENET_MII_55S

ENET_MII_55S

ENET_MII_55S

ENET_MII_55S

ENET_MII_55S

ENET_MII_55S

ENET_MII_55S

ENET_MII_55S

ENET_MII_55S

ENET_MII_55S

ENET_MDI_100D

ENET_MDI_100D

NET_TYPE

SPACING

ENET_MII

ENET_MII

ENET_MIIENET_MDC

ENET_MII

ENET_MII

ENET_MII

ENET_MII

ENET_MII

ENET_MII

ENET_MII

ENET_MII

ENET_MII

ENET_MII

ENET_MII

ENET_MII

ENET_MDI

ENET_MDI

MCP_MII_COMP_VDD

MCP_MII_COMP_GND

MCP_CLK25M_BUF0_R

RTL8211_CLK25M_CKXTAL1

ENET_INTR_L

ENET_MDIO

ENET_MDC

ENET_PWRDWN_L

ENET_CLK125M_RXCLK_R

ENET_CLK125M_RXCLK

ENET_RXD_R<3..0>

ENET_RXD<0>

ENET_RXD<3..1>

ENET_RX_CTRL

ENET_CLK125M_TXCLK

ENET_TXD<0>

ENET_TXD<3..1>

ENET_TX_CTRL

ENET_RESET_L

ENET_MDI_P<3..0>

ENET_MDI_N<3..0>

3

18

18

33 18

33 32

32 18

32 18

32

32 18

32

32 18

32 18

32 18

32 18

32 18

32 18

32 18

32 18

34 32

34 32

21

D

C

B

C

B

A

8

76

Ethernet Constraints

SYNC_MASTER=M98_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

5

4

3

2

SCALE

NONE

051-8071

SHT

SYNC_DATE=04/01/2008

OF

1

A

REV.

B

9892

87

www.vinafix.vn

FireWire Interface Constraints

LAYER

FW_110D

SPACING_RULE_SET

FW_TP

LAYER

*

*

ALLOW ROUTE
ON LAYER?

=110_OHM_DIFF

LINE-TO-LINE SPACING

=3:1_SPACING

D

MINIMUM LINE WIDTH

=110_OHM_DIFF =110_OHM_DIFF

WEIGHT

?

MINIMUM NECK WIDTH

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MAXIMUM NECK LENGTH

=110_OHM_DIFF

6

DIFFPAIR PRIMARY GAP

=110_OHM_DIFF =110_OHM_DIFF

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

5

FireWire Net Properties

ELECTRICAL_CONSTRAINT_SET

FW_P0_TPA

FW_P0_TPA

FW_P0_TPB

FW_P0_TPB

FW_P1_TPA

FW_P1_TPA

FW_P1_TPB

FW_P1_TPB

Port 2 Not Used

4

NET_TYPE

FW_110D

FW_110D

FW_110D

FW_110D

FW_110D

FW_110D

FW_110D

FW_110D

PHYSICAL

FW_TP

FW_TP

FW_TP

FW_TP

FW_TP

FW_TP

FW_TP

FW_TP

SPACING

FW_P0_TPA_P

FW_P0_TPA_N

FW_P0_TPB_P

FW_P0_TPB_N

FW_P1_TPA_P

FW_P1_TPA_N

FW_P1_TPB_P

FW_P1_TPB_N

3

37 35

37 35

37 35

37 35

37 35

37 35

37 35

37 35

21

D

C

B

C

B

A

8

76

FireWire Constraints

051-8071

SHT

SYNC_DATE=04/01/2008

OF

93 98

1

A

REV.

B

SYNC_MASTER=M98_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

5

4

3

2

SCALE

NONE

87

www.vinafix.vn

1TO1_DIFFPAIR

LAYER

ALLOW ROUTE
ON LAYER?

=STANDARD =STANDARD

*

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=STANDARD=STANDARD

DIFFPAIR PRIMARY GAP

D

6

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

0.1 MM0.1 MM

5

SMC SMBus Net Properties

ELECTRICAL_CONSTRAINT_SET

SMBUS_SMC_A_S3_SCL

SMBUS_SMC_A_S3_SDA

SMBUS_SMC_B_S0_SCL

SMBUS_SMC_B_S0_SDA

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_0_S0_SDA

SMBUS_SMC_BSA_SCL

SMBUS_SMC_BSA_SDA

SMBUS_SMC_MGMT_SCL

SMBUS_SMC_MGMT_SDA

4

NET_TYPE

SMB_55S

SMB_55S

SMB_55S

SMB_55S

SMB_55S

SMB_55S

SMB_55S

SMB_55S

SMB_55S

SMB_55S

PHYSICAL

SMB

SMB

SMB

SMB

SMB

SMB

SMB

SMB

SMB

SMB

SPACING

SMBUS_SMC_A_S3_SCL

SMBUS_SMC_A_S3_SDA

SMBUS_SMC_B_S0_SCL

SMBUS_SMC_B_S0_SDA

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_0_S0_SDA

SMBUS_SMC_BSA_SCL

SMBUS_SMC_BSA_SDA

SMBUS_SMC_MGMT_SCL

SMBUS_SMC_MGMT_SDA

3

44

7

44

7

44

44

44

44

7

44

44

7

44

44

21

D

SMBus Charger Net Properties

ELECTRICAL_CONSTRAINT_SET

CHGR_CSI

CHGR_CSO

1TO1_DIFFPAIR

1TO1_DIFFPAIR

1TO1_DIFFPAIR

1TO1_DIFFPAIR

C

PHYSICAL

NET_TYPE

SPACING

CHGR_CSI_P

CHGR_CSI_N

CHGR_CSO_P

CHGR_CSO_N

60

60

60

60

C

B

A

8

76

B

SMC Constraints

051-8071

SHT

SYNC_DATE=04/01/2008

OF

94 98

1

A

REV.

B

SYNC_MASTER=M98_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

5

4

3

2

SCALE

NONE

87

www.vinafix.vn

GDDR3 Frame Buffer Signal Constraints

LAYER

GDDR3_40R55SE

GDDR3_80D

LAYER

D

SPACING_RULE_SET

GDDR3_CLK

GDDR3_CMD

GDDR3_DATA

GDDR3_DQS

From T18 MXM:

Digital Video Signal Constraints

LAYER

DP_100D

C

LVDS_100D

SPACING_RULE_SET

LAYER

DISPLAYPORT

LVDS

LVDS intra-pair matching should be 5 mils. Pairs should be within 100 mils of clock length.
DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps.
DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals.
Max length of LVDS/DisplayPort/TMDS traces: 12 inches.
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4.

B

ALLOW ROUTE
ON LAYER?

*

*

*

=55_OHM_SE

=40_OHM_SE

=80_OHM_DIFF

MINIMUM LINE WIDTH

=40_OHM_SE

=40_OHM_SE

=80_OHM_DIFF

LINE-TO-LINE SPACING

*

*

*

*

*

*

=2.5:1_SPACING

=2.5:1_SPACING

=2.5:1_SPACING

=2.5:1_SPACING

ALLOW ROUTE
ON LAYER?

=100_OHM_DIFF

=100_OHM_DIFF

MINIMUM LINE WIDTH

=100_OHM_DIFF

=100_OHM_DIFF

LINE-TO-LINE SPACING

* ?

=3x_DIELECTRIC

=3x_DIELECTRIC

MUXGFX Net Properties

ELECTRICAL_CONSTRAINT_SET

LVDS_A_CLK

I148

LVDS_A_CLK

I149

LVDS_A_DATA LVDS

I199

LVDS_A_DATA

I198

WEIGHT

WEIGHT

?*

LVDS_100D

LVDS_100D

LVDS_100D

LVDS_100D

?

?

?

?

PHYSICAL

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM NECK WIDTH

0.095 MM

0.095 MM

0.095 MM

MINIMUM NECK WIDTH

=100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFF

SPACING_RULE_SET

DISPLAYPORT

LVDS

NET_TYPE

SPACING

LVDS

LVDS

LVDS

MAXIMUM NECK LENGTH

12.7 MM

=40_OHM_SEGDDR3_40SE

=80_OHM_DIFF

MAXIMUM NECK LENGTH

LAYER

TOP,BOTTOM

TOP,BOTTOM

LVDS_A_CLK_P

LVDS_A_CLK_N

LVDS_A_DATA_P<2..0>

LVDS_A_DATA_N<2..0>

DIFFPAIR PRIMARY GAP

=STANDARD =STANDARD

=80_OHM_DIFF =80_OHM_DIFF

DIFFPAIR PRIMARY GAP

=100_OHM_DIFF

=100_OHM_DIFF

LINE-TO-LINE SPACING

=4x_DIELECTRIC

=4x_DIELECTRIC

6

GDDR3 FB A/B Net Properties

ELECTRICAL_CONSTRAINT_SET

G96 Net Properties

ELECTRICAL_CONSTRAINT_SET

7

7

WEIGHT

84 81

84 81

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

84 81

84 81

=STANDARD=STANDARD

=100_OHM_DIFF

=100_OHM_DIFF

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

5

NET_TYPE

NET_TYPE

SPACING

GDDR3_CLKGDDR3_80D

GDDR3_CLK

GDDR3_CLK

GDDR3_CMD

GDDR3_CMD

GDDR3_CMD

GDDR3_CMD

GDDR3_CMD

GDDR3_CMDFB_AB_CMD_PD

GDDR3_CMD

GDDR3_CMD

GDDR3_CMD

GDDR3_CMD

GDDR3_DQS

GDDR3_DQS

GDDR3_DQS

GDDR3_DQS

GDDR3_DQS

GDDR3_DQS

GDDR3_DQS

GDDR3_DQS

GDDR3_DATA

GDDR3_DATA

GDDR3_DATA

GDDR3_DATA

GDDR3_DATA

GDDR3_DATA

GDDR3_DQS

GDDR3_DQS

GDDR3_DQS

GDDR3_DQS

GDDR3_DQS

GDDR3_DQS

GDDR3_DQS

GDDR3_DQS

GDDR3_DATA

GDDR3_DATAGDDR3_40SE

GDDR3_DATAGDDR3_40SE

GDDR3_DATA

GDDR3_DATAGDDR3_40SE

GDDR3_DATA

GDDR3_CMD

SPACING

CLK_SLOW

CLK_SLOW

LVDS

LVDS

LVDS

LVDS

PHYSICAL

FB_A_CLK_P

FB_B_CLK_P

FB_AB_CMD

FB_AB_CMD

FB_AB_CMD GDDR3_CMD

FB_AB_CMD

FB_AB_CMD

FB_AB_CMD

FB_AB_CS0

FB_AB_CMD_PD

FB_A_CMD

FB_B_CMD

FB_A_WDQS2

FB_A_RDQS0

FB_A_RDQS1

FB_A_RDQS2

FB_A_RDQS3

FB_A_DQ_BYTE0

FB_A_DQ_BYTE1

FB_A_DQ_BYTE2

FB_A_DQ_BYTE3

FB_A_DQM0

FB_A_DQM1

FB_A_DQM2

FB_A_DQM3

FB_B_WDQS0

FB_B_WDQS1

FB_B_WDQS2

FB_B_WDQS3

FB_B_RDQS1

FB_B_RDQS2

FB_B_RDQS3 GDDR3_40SE

FB_B_DQ_BYTE0

FB_B_DQ_BYTE1

FB_B_DQ_BYTE2

FB_B_DQ_BYTE3

FB_B_DQM0

FB_B_DQM1

FB_B_DQM2

FB_B_DQM3

FB_AB_CS1

(CK505_DOT96)

CK505_CLK27MSS

LVDS_EG_A_CLK

LVDS_EG_A_CLK

LVDS_EG_A_DATA

LVDS_EG_A_DATA

GDDR3_80D GDDR3_CLK

GDDR3_80D

GDDR3_80D

GDDR3_40R55SE

GDDR3_40R55SE

GDDR3_40R55SE

GDDR3_40R55SE

GDDR3_40R55SE

GDDR3_40R55SE

GDDR3_40R55SE

GDDR3_40R55SE

GDDR3_40R55SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SEFB_A_WDQS0

GDDR3_40SEFB_A_WDQS1

GDDR3_40SE

GDDR3_40SEFB_A_WDQS3

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE GDDR3_DATA

GDDR3_40SE GDDR3_DATA

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SEFB_B_RDQS0

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE GDDR3_DATA

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE GDDR3_DATA

GDDR3_40R55SE

PHYSICAL

CLK_SLOW_55S

CLK_SLOW_55S

LVDS_100D

LVDS_100D

LVDS_100D

LVDS_100D

4

FB_A_CLK_P<0>

FB_A_CLK_N<0>

FB_A_CLK_P<1>

FB_A_CLK_N<1>

FB_A_MA<1..0>

FB_A_MA<12..6>

FB_A_BA<2..0>

FB_A_RAS_L

FB_A_CAS_L

FB_A_WE_L

FB_A_CKE

FB_A_CS0_L

FB_A_DRAM_RST

FB_A_LMA<5..2>

FB_A_UMA<5..2>

FB_A_WDQS<0>

FB_A_WDQS<1>

FB_A_WDQS<2>

FB_A_WDQS<3>

FB_A_RDQS<0>

FB_A_RDQS<1>

FB_A_RDQS<2>

FB_A_RDQS<3>

FB_A_DQ<7..0>

FB_A_DQ<15..8>

FB_A_DQ<23..16>

FB_A_DQ<31..24>

FB_A_DQM_L<0>

FB_A_DQM_L<1>

FB_A_DQM_L<2>

FB_A_DQM_L<3>

FB_A_WDQS<4>

FB_A_WDQS<5>

FB_A_WDQS<6>

FB_A_WDQS<7>

FB_A_RDQS<4>

FB_A_RDQS<5>

FB_A_RDQS<6>

FB_A_RDQS<7>

FB_A_DQ<39..32>

FB_A_DQ<47..40>

FB_A_DQ<55..48>

FB_A_DQ<63..56>

FB_A_DQM_L<4>

FB_A_DQM_L<5>

FB_A_DQM_L<6>

FB_A_DQM_L<7>

FB_A_CS1_L

GPU_CLK27M

GPU_CLK27M_SS

LVDS_EG_A_CLK_P

LVDS_EG_A_CLK_N

LVDS_EG_A_DATA_P<2..0>

LVDS_EG_A_DATA_N<2..0>

79 72 71

79 72 71

79 72 71

79 72 71

79 72 71

79 72 71

79 72 71

79 72 71

79 72 71

79 72 71

79 72 71

72 71

79 72 71

79 72 71

79 72 71

79 72 71

79 72 71

79 72 71

79 72 71

79 72 71

79 72 71

79 72 71

79 72 71

79 72 71

7

79 72 71

7

79 72 71

7

79 72 71

7

79 72 71

79 72 71

79 72 71

79 72 71

79 72 71

79 72 71

79 72 71

79 72 71

79 72 71

79 72 71

79 72 71

79 72 71

79 72 71

7

79 72 71

7

79 72 71

7

79 72 71

7

79 72 71

79 72 71

79 72 71

79 72 71

79 71

75

75

84 76

84 76

84 76

84 76

7

3

GDDR3 FB C/D Net Properties

ELECTRICAL_CONSTRAINT_SET

FB_C_CLK_P

FB_D_CLK_P

FB_CD_CMD

FB_CD_CMD

FB_CD_CMD

FB_CD_CMD

FB_CD_CMD

FB_CD_CMD_PD

FB_CD_CMD_PD GDDR3_CMD

FB_C_CMD

FB_D_CMD

FB_C_RDQS1

FB_C_RDQS2

FB_C_RDQS3

FB_C_DQ_BYTE0

FB_C_DQ_BYTE1

FB_C_DQ_BYTE2

FB_C_DQ_BYTE3

FB_C_DQM0

FB_C_DQM1

FB_C_DQM2

FB_C_DQM3

FB_D_RDQS3

FB_D_DQ_BYTE0

FB_D_DQ_BYTE1

FB_D_DQ_BYTE2

FB_D_DQ_BYTE3

FB_D_DQM0

FB_D_DQM1

FB_D_DQM2

FB_D_DQM3

I205I204

GDDR3_80D

GDDR3_80D

GDDR3_80D

GDDR3_80D

GDDR3_40R55SE

GDDR3_40R55SE

GDDR3_40R55SE

GDDR3_40R55SE

GDDR3_40R55SE

GDDR3_40R55SE

GDDR3_40R55SE

GDDR3_40R55SE

GDDR3_40R55SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SEFB_C_WDQS0

GDDR3_40SEFB_C_WDQS1

GDDR3_40SEFB_C_WDQS2

GDDR3_40SEFB_C_WDQS3

GDDR3_40SEFB_C_RDQS0

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE GDDR3_DATA

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SEFB_D_WDQS0

GDDR3_40SEFB_D_WDQS1

GDDR3_40SEFB_D_WDQS2

GDDR3_40SEFB_D_WDQS3

GDDR3_40SEFB_D_RDQS0

GDDR3_40SEFB_D_RDQS1

GDDR3_40SEFB_D_RDQS2

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE GDDR3_DATA

GDDR3_40SE

GDDR3_40R55SE

PHYSICAL

21

NET_TYPE

SPACING

GDDR3_CLK

GDDR3_CLK

GDDR3_CLK

GDDR3_CLK

GDDR3_CMD

GDDR3_CMDFB_CD_CMD

GDDR3_CMD

GDDR3_CMD

GDDR3_CMD

GDDR3_CMD

GDDR3_CMD

GDDR3_CMDFB_CD_CS0

GDDR3_CMD

GDDR3_CMD

GDDR3_DQS

GDDR3_DQS

GDDR3_DQS

GDDR3_DQS

GDDR3_DQS

GDDR3_DQS

GDDR3_DQS

GDDR3_DQS

GDDR3_DATA

GDDR3_DATA

GDDR3_DATA

GDDR3_DATA

GDDR3_DATA

GDDR3_DATA

GDDR3_DATA

GDDR3_DQS

GDDR3_DQS

GDDR3_DQS

GDDR3_DQS

GDDR3_DQS

GDDR3_DQS

GDDR3_DQS

GDDR3_DQS

GDDR3_DATA

GDDR3_DATA

GDDR3_DATAGDDR3_40SE

GDDR3_DATAGDDR3_40SE

GDDR3_DATAGDDR3_40SE

GDDR3_DATA

GDDR3_DATA

GDDR3_CMDFB_CD_CS1

FB_B_CLK_P<0>

FB_B_CLK_N<0>

FB_B_CLK_P<1>

FB_B_CLK_N<1>

FB_B_MA<1..0>

FB_B_MA<12..6>

FB_B_BA<2..0>

FB_B_RAS_L

FB_B_CAS_L

FB_B_WE_L

FB_B_CKE

FB_B_CS0_L

FB_B_DRAM_RST

FB_B_LMA<5..2>

FB_B_UMA<5..2>

FB_B_WDQS<0>

FB_B_WDQS<1>

FB_B_WDQS<2>

FB_B_WDQS<3>

FB_B_RDQS<0>

FB_B_RDQS<1>

FB_B_RDQS<2>

FB_B_RDQS<3>

FB_B_DQ<7..0>

FB_B_DQ<15..8>

FB_B_DQ<23..16>

FB_B_DQ<31..24>

FB_B_DQM_L<0>

FB_B_DQM_L<1>

FB_B_DQM_L<2>

FB_B_DQM_L<3>

FB_B_WDQS<4>

FB_B_WDQS<5>

FB_B_WDQS<6>

FB_B_WDQS<7>

FB_B_RDQS<4>

FB_B_RDQS<5>

FB_B_RDQS<6>

FB_B_RDQS<7>

FB_B_DQ<39..32>

FB_B_DQ<47..40>

FB_B_DQ<55..48>

FB_B_DQ<63..56>

FB_B_DQM_L<4>

FB_B_DQM_L<5>

FB_B_DQM_L<6>

FB_B_DQM_L<7>

FB_B_CS1_L

80 73 71

80 73 71

80 73 71

80 73 71

80 73 71

80 73 71

7

80 73 71

7

80 73 71

80 73 71

7

80 73 71

80 73 71

7

73 71

80 73 71

80 73 71

80 73 71

80 73 71

80 73 71

80 73 71

80 73 71

80 73 71

80 73 71

80 73 71

80 73 71

80 73 71

7

80 73 71

7

80 73 71

7

80 73 71

7

80 73 71

80 73 71

80 73 71

80 73 71

80 73 71

80 73 71

80 73 71

80 73 71

80 73 71

80 73 71

80 73 71

80 73 71

80 73 71

7

80 73 71

7

80 73 71

7

80 73 71

7

80 73 71

80 73 71

80 73 71

80 73 71

80 71

D

C

B

LVDS_B_CLK

I152

LVDS_B_CLK

I153

LVDS_B_DATA

I201

LVDS_B_DATA

I200

I183

I182

I184

I185

I190

I191

I192

I193

I194

I195

I196

I197

DP_ML

A

I161

I160

DP_ML

I155

I157

DP_ML

I202

I203

DP_AUX_CH

I159

DP_AUX_CH

I158

8

LVDS_100D

LVDS_100D

LVDS_100D

LVDS_100D

LVDS_100D

LVDS_100D

LVDS_100D

LVDS_100D

LVDS_100D

LVDS_100D

LVDS_100D

LVDS_100D

LVDS_100D

LVDS_100D

LVDS_100D

LVDS_100D

DP_100D

DP_100D

DP_100D

DP_100D

DP_100D

DP_100D

DP_100D

DP_100D

76

LVDS

LVDS

LVDS

LVDS

LVDS

LVDS

LVDS

LVDS

LVDS

LVDS

LVDS

LVDS

LVDS

LVDS

LVDS

LVDS

DISPLAYPORT

DISPLAYPORT

DISPLAYPORT

DISPLAYPORT

DISPLAYPORT

DISPLAYPORT

DISPLAYPORT

DISPLAYPORT

LVDS_B_CLK_P

LVDS_B_CLK_N

LVDS_B_DATA_P<2..0>

LVDS_B_DATA_N<2..0>

LVDS_CONN_A_CLK_F_P

LVDS_CONN_A_CLK_F_N

LVDS_CONN_B_CLK_F_P

LVDS_CONN_B_CLK_F_N

LVDS_CONN_A_CLK_P

LVDS_CONN_A_CLK_N

LVDS_CONN_A_DATA_P<2..0>

LVDS_CONN_A_DATA_N<2..0>

LVDS_CONN_B_CLK_P

LVDS_CONN_B_CLK_N

LVDS_CONN_B_DATA_P<2..0>

LVDS_CONN_B_DATA_N<2..0>

DP_ML_C_P<3..0>
DP_ML_C_N<3..0>
DP_ML_P<3..0>DP_ML_P<3..0>
DP_ML_N<3..0>

DP_ML_N<3..0>
DP_ML_CONN_P<3..0>
DP_ML_CONN_N<3..0>

DP_AUX_CH_C_P
DP_AUX_CH_C_N

84 81

7

84 81

84 81

7

84 81

7

78

7

78

7

78

7

78

7

81 78

81 78

81 78

7

81 78

7

81 78

81 78

81 78

7

81 78

7

LVDS_EG_B_DATA

LVDS_EG_B_DATA

DP_ML

I142

DP_ML

I144

DP_AUX_CH

I145

DP_AUX_CH

I143

I139

I138

LVDS_100D

LVDS_100D

DP_100D

DP_100D

DP_100D

DP_100D

DP_100D

DP_100D

LVDS

LVDS

DISPLAYPORT

DISPLAYPORT

DISPLAYPORT

DISPLAYPORT

DISPLAYPORT

DISPLAYPORT

LVDS_EG_B_DATA_P<2..0>

LVDS_EG_B_DATA_N<2..0>

DP_EG_ML_P<3..0>DP_EG_ML_P<3..0>
DP_EG_ML_N<3..0>

DP_EG_ML_N<3..0>
DP_EG_AUX_CH_P

DP_EG_AUX_CH_N
DP_EG_AUX_CH_C_P
DP_EG_AUX_CH_C_N

84 76

84 76

81 76

81 76

81 76

81 76

81

81

GPU (G96) Constraints

82

82

82 81

82 81

82

82

82 81

82 81

5

4

3

SYNC_MASTER=M98_MLB

APPLE INC.

2

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

051-8071

SHT

SYNC_DATE=05/01/2008

OF

95 98

1

A

REV.

B

87

www.vinafix.vn

6

5

4

3

21

ALLOW ROUTE
ON LAYER?

*

*

*

=1:1_DIFFPAIR

=1:1_DIFFPAIR

=1:1_DIFFPAIR =1:1_DIFFPAIR

LINE-TO-LINE SPACING

*

*

*

LINE-TO-LINE SPACING

*

LINE-TO-LINE SPACING

*

*

LINE-TO-LINE SPACING

*

*

D

SENSE_1TO1_55S

THERM_1TO1_55S

DIFFPAIR

SPACING_RULE_SET

SENSE

THERM

AUDIO

SPACING_RULE_SET

ENETCONN

SPACING_RULE_SET

GND

PP1V8_MEM

SPACING_RULE_SET

GND_P2MM

PWR_P2MM

LAYER

LAYER

LAYER

LAYER

LAYER

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_CLK

MEM_CMD

C

B

MEM_CTRL GND_P2MM

MEM_DATA GND_P2MM

MEM_DQS

MEM_40S

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

MEM_40S_VDD

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

MEM_70D 0.09 MM 100 MIL

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

MEM_70D_VDD

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

PCIE_90D

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

USB_90D 500 MIL

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

MCP_DV_COMP

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

MCP_MEM_COMP

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

MCP_MII_COMP

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

MCP_USB_RBIAS

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

MCP_DV_COMP

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

CPU_27P4S

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

MEM_40S

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

MEM_40S_VDD

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

MEM_70D

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

MEM_70D_VDD

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

Ground-referenced memory signals (DQ,DQM,DQS) MAY route on ISL9 (VDD-referenced plane)but not next to VDD island.
Forces power-referenced memory signals (CLK,ADDR,CTRL) to not route on ISL3, ISL4 & ISL10(GND-referenced planes).

LAYER

*

*

*

*

*

TOP

*

BOTTOM

LAYER

ISL4,ISL9

ISL3,ISL10

ISL4,ISL9

ISL3,ISL10

GND

GND

GND

GND

GND

ALLOW ROUTE
ON LAYER?

ALLOW ROUTE
ON LAYER?

=2:1_SPACING

=2:1_SPACING

=2:1_SPACING

25 MILS

=STANDARD

=STANDARD

0.20 MM

0.20 MM

AREA_TYPE

N

N

MINIMUM LINE WIDTH

=55_OHM_SE

SPACING_RULE_SET

*

*

*

*

*

MINIMUM LINE WIDTH

MINIMUM LINE WIDTH

WEIGHT

WEIGHT

WEIGHT

WEIGHT

1000

1000

GND_P2MM

GND_P2MM

GND_P2MM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MINIMUM NECK WIDTH

=55_OHM_SE

=55_OHM_SE=55_OHM_SE

MAXIMUM NECK LENGTH

NET_SPACING_TYPE1 NET_SPACING_TYPE2

CLK_FSB

CPU_COMP GND_P2MM

CPU_GTLREF

CPU_VCCSENSE

FSB_DSTB

NET_SPACING_TYPE1 NET_SPACING_TYPE2

ENET_MDI

NET_SPACING_TYPE1 NET_SPACING_TYPE2

CLK_PCIE GND_P2MM

PCIE

SATA

USB

CLK_PCIE PWR_P2MM

SATA

USB

NET_SPACING_TYPE1 NET_SPACING_TYPE2

LVDS

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

0.09 MM 100 MIL

0.09 MM

0.1 MMTOP

0.1 MMTOP

0.1 MMTOP

0.1 MMTOP

0.1 MM

0.25 MM 250 MIL

0.23 MM

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=55_OHM_SE

=55_OHM_SE

100 MIL0.09 MM

100 MIL0.09 MM

100 MIL

500 MIL

500 MIL

500 MIL

500 MIL

100 MIL

Graphics ,SATA Constraint Relaxations

Alternate diffpair width/gap through BGA fanout areas (95-ohm diff)

PHYSICAL_RULE_SET

BGA

BGA

BGA

A

NET_PHYSICAL_TYPE

LVDS_100D

DP_100D

SATA_100D

AREA_TYPE

100_DIFF_BGA

100_DIFF_BGA

100_DIFF_BGA

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

FLASH MEMORY BUS CONSTRAINTS

LAYER

FLSH_55S

ALLOW ROUTE
ON LAYER?

=55_OHM_SE

*

Memory Constraint Relaxations

Allow 0.127 mm necks for >0.127 mm lines for GMCH fanout.

LAYER

MEM_70D 6.35 MM

BOTTOM

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

0.127 MM

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

GND

GND

GND

GND

GND

GND

GND

GND

GND

SB_POWER

SB_POWER

GND

DIFFPAIR PRIMARY GAP

DIFFPAIR PRIMARY GAP

MINIMUM LINE WIDTH

=55_OHM_SE

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=1:1_DIFFPAIR

=1:1_DIFFPAIR =1:1_DIFFPAIR

=1:1_DIFFPAIR =1:1_DIFFPAIR

AREA_TYPE

*

*

*

*

*

AREA_TYPE

*

AREA_TYPE

*

*

*

*

*

*

*

AREA_TYPE

*

=1:1_DIFFPAIR

GND_P2MM

GND_P2MM

GND_P2MM

GND_P2MMFSB_DSTB

GND_P2MM

GND_P2MM

GND_P2MM

GND_P2MM

PWR_P2MMSB_POWER

PWR_P2MM

GND_P2MM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

SPACING_RULE_SET

SPACING_RULE_SET

SPACING_RULE_SET

SPACING_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

MINIMUM NECK WIDTH

=55_OHM_SE =55_OHM_SE

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MAXIMUM NECK LENGTH

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

M99 Specific Net Properties

ELECTRICAL_CONSTRAINT_SET

I146

I145

I144

I142

I143

I140

I141

I139

SENSE_DIFFPAIR

CPUTHMSNS_D2_DP

I124

I125

CPU_THERMD_DP

I127

I126

GPUTHMSNS_D_DP

I128

I130

GPU_THERMD_DP

I129

MCPTHMSNS_D_DP

I138

I137

MCP_THERMD_DP

I135

I136

SENSE_DIFFPAIR

I156

I157

SENSE_DIFFPAIR

I155

I154

SENSE_DIFFPAIR

I153

I152

SENSE_DIFFPAIR

I151

I150

I149

I148

SENSE_DIFFPAIR

I158

I147

I186

I185

SENSE_DIFFPAIR

I131

I132

SENSE_DIFFPAIR

I134

I133

ASIC_CNTRLMEM1

I245

ASIC_CNTRLMEM1

I246

ASIC_CNTRLMEM1

I244

ASIC_CNTRLMEM1

I243

ASIC_CNTRLMEM1

I242

ASIC_CNTRLMEM1

I241

ASIC_CNTRLMEM2

I239

ASIC_CNTRLMEM2

I240

ASIC_CNTRLMEM2

I238

ASIC_CNTRLMEM2

I237

ASIC_CNTRLMEM2

I236

ASIC_CNTRLMEM2

I235

ASIC_CNTRLMEM3

I234

ASIC_CNTRLMEM3

I233

ASIC_CNTRLMEM3

I232

ASIC_CNTRLMEM3

I231

ASIC_CNTRLMEM3

I230

ASIC_CNTRLMEM3

I229

ASIC_CNTRLMEM2

I228

ASIC_CNTRLMEM2

I227

ASIC_CNTRLMEM2

I226

ASIC_CNTRLMEM2

I225

ASIC_CNTRLMEM2

I224

ASIC_CNTRLMEM2

I223

DIFFPAIR PRIMARY GAP

=STANDARD

PHYSICAL

ENET_MDI_100D

ENET_MDI_100D

SATA_100D

SATA_100D

SATA_100D

SATA_100D

SATA_100D

SATA_100D

SATA_100D

SATA_100D

SENSE_1TO1_55S

SENSE_1TO1_55S

THERM_1TO1_55S

THERM_1TO1_55S

THERM_1TO1_55S

THERM_1TO1_55S

THERM_1TO1_55S

THERM_1TO1_55S

THERM_1TO1_55S

THERM_1TO1_55S

THERM_1TO1_55S

THERM_1TO1_55S

THERM_1TO1_55S

THERM_1TO1_55S

SENSE_1TO1_55S

SENSE_1TO1_55S

SENSE_1TO1_55S

SENSE_1TO1_55S

SENSE_1TO1_55S

SENSE_1TO1_55S

SENSE_1TO1_55S

SENSE_1TO1_55S

SENSE_1TO1_55SSENSE_DIFFPAIR

SENSE_1TO1_55S

SENSE_1TO1_55S

SENSE_1TO1_55S

SENSE_1TO1_55SSENSE_DIFFPAIR

SENSE_1TO1_55S

SENSE_1TO1_55S

SENSE_1TO1_55S

SENSE_1TO1_55S

SENSE_1TO1_55S

FLSH_55S

FLSH_55S

FLSH_55S

FLSH_55S

FLSH_55S

FLSH_55S

FLSH_55S

FLSH_55S

FLSH_55S

FLSH_55S

FLSH_55S

FLSH_55S

FLSH_55S

FLSH_55S

FLSH_55S

FLSH_55S

FLSH_55S

FLSH_55S

FLSH_55S

FLSH_55S

FLSH_55S

FLSH_55S

FLSH_55S

FLSH_55S

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

NET_TYPE

SPACING SPACING

ENETCONN

ENETCONN

SATA

SATA

SATA

SATA

SATA

SATA

SATA

SATA

SENSE

SENSE

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

THERM

SENSE

SENSE

SENSE

SENSE

SENSE

SENSE

SENSE

SENSE

SENSE

SENSE

SENSE

SENSE

SENSE

SENSE

GND

SB_POWER

SB_POWER

SB_POWER

SENSE

SENSE

SENSE

SENSE

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

=STANDARD

ENETCONN_P<3..0>

ENETCONN_N<3..0>

SATA_ODD_R2D_UF_P

SATA_ODD_R2D_UF_N

SATA_ODD_D2R_UF_P

SATA_ODD_D2R_UF_N

SATA_HDD_D2R_UF_P

SATA_HDD_D2R_UF_N

SATA_HDD_R2D_UF_P

SATA_HDD_R2D_UF_N

MCPCOREISNS_P

MCPCOREISNS_N

CPUTHMSNS_D2_P

CPUTHMSNS_D2_N

CPU_THERMD_P

CPU_THERMD_N

GPUTHMSNS_D_P

GPUTHMSNS_D_N

GPU_TDIODE_P

GPU_TDIODE_N

MCPTHMSNS_D_P

MCPTHMSNS_D_N

MCP_THMDIODE_P

MCP_THMDIODE_N

1V05CPUISNS_R_P
1V05CPUISNS_R_N
DDRISNS_R_P
DDRISNS_R_N
GPUISENS_P
GPUISENS_N
1V05CPU_P
1V05CPU_N
DDRISNS_P
DDRISNS_N
P1V8GPU_P
P1V8GPU_N
ISNS_CPU_P
ISNS_CPU_N

GND

PP3V3_S5

PP3V3_S0

PP1V5_S0

P1V8GPUISNS_P

P1V8GPUISNS_N

P1V8GPUISNS_R_P

P1V8GPUISNS_R_N

NF_CLE_R

NF_ALE_R

NF_CE0_L_R

NF_CE1_L_R

NF_RE0_L_R

NF_WE0_L_R

NF_CLE_R

NF_ALE_R

NF_CE0_L_R

NF_CE1_L_R

NF_RE0_L_R

NF_WE0_L_R

NF_CLE

NF_ALE

NF_CE0_L

NF_CE1_L

NF_RE0_L

NF_WE0_L

NF_CLE

NF_ALE

NF_CE0_L

NF_CE1_L

NF_RE0_L

NF_WE0_L

34

34

38

38

38

38

38

38

38

38

64 46

64 46

47

47

47 10

47 10

47

47

75 47

75 47

47

7

7

47

47 21

47 21

46

46

46

46

46

46

65 46

65 46

46

46

46

46

45

45

8 7

9 8 7

46

46

96

96

96

96

96

96

96

96

96

96

96

96

96

96

96

96

96

96

96

96

96

96

96

96

M99 Specific Net Properties

ELECTRICAL_CONSTRAINT_SET

I160

I159

I168

I166

I167

I165

(USB_EXTA)

I182

(USB_EXTA)

I181

(USB_EXTA)

I179

(USB_EXTA)

I180

(USB_EXTD)

I177

(USB_EXTD)

I178

(USB_CAMERA)

I176

(USB_CAMERA)

I175

I174

I172

I173

I171

I169

I170

I183

I184

MCP_PE4_REFCLK

I187

I188

PCIE_FC_R2D

I189

I190

PCIE_FC_D2R

I191

I192

I193

I194

I195

I196

SPK_OUT

I198

I197

SPK_OUT

I201

I200

SPK_OUT

I199

I202

SPK_OUT

I206

I207

SPK_OUT

I247

I248

I210

I209

I212

I211

NET_TYPE

PHYSICAL

CLK_PCIE_100D

CLK_PCIE_100D

1TO1_DIFFPAIR

1TO1_DIFFPAIR

1TO1_DIFFPAIR

1TO1_DIFFPAIR

USB_90D

USB_90D

USB_90D

USB_90D

USB_90D

USB_90D

USB_90D

USB_90D

USB_90D

USB_90D

USB_90D

USB_90D

USB_90D

USB_90D

DP_100D

DP_100D

CLK_PCIE_100D

CLK_PCIE_100D

PCIE_90D PCIE

PCIE_90D PCIE

PCIE_90D

PCIE_90D PCIE

CLK_PCIE_100D

CLK_PCIE_100D

DIFFPAIR

DIFFPAIR

DIFFPAIR

DIFFPAIR

DIFFPAIR

DIFFPAIR

DIFFPAIR

DIFFPAIR

DIFFPAIR

DIFFPAIR

USB_90D

USB_90D

USB_90D

USB_90D

CLK_PCIE

CLK_PCIE

USB

USB

USB

USB

USB

USB

USB

USB

USB

USB

USB

USB

USB

USB

DISPLAYPORT

DISPLAYPORT

CLK_PCIE

CLK_PCIE

PCIEPCIE_90D

PCIEPCIE_90D

PCIE

CLK_PCIE

CLK_PCIE

AUDIO

AUDIO

AUDIO

AUDIO

AUDIO

AUDIO

AUDIO

AUDIO

AUDIO

AUDIO

USB

USB

USB

USB

APPLE INC.

PCIE_CLK100M_MINI_CONN_P

PCIE_CLK100M_MINI_CONN_N

CHGR_CSI_R_P
CHGR_CSI_R_N
CHGR_CSO_R_P
CHGR_CSO_R_N

USB2_EXTA_MUXED_P

USB2_EXTA_MUXED_N

USB2_LT1_P
USB2_LT1_N

CONN_TPAD_USB_P

CONN_TPAD_USB_N

USB_CAMERA_CONN_P

USB_CAMERA_CONN_N

CONN_USB2_BT_P

CONN_USB2_BT_N

USB_LT2_P
USB_LT2_N

USB2_EXCARD_CONN_P

USB2_EXCARD_CONN_N

DP_IG_AUX_CH_C_P
DP_IG_AUX_CH_C_N
PCIE_CLK100M_FC_P
PCIE_CLK100M_FC_N
PCIE_FC_R2D_C_P
PCIE_FC_R2D_C_N
PCIE_FC_D2R_P
PCIE_FC_D2R_N
PCIE_FC_R2D_P

PCIE_FC_R2D_N
PCIE_CLK100M_EXCARD_CONN_N
PCIE_CLK100M_EXCARD_CONN_P

SPKRAMP_L1_OUT_P
SPKRAMP_L1_OUT_N
SPKRAMP_L2_OUT_P
SPKRAMP_L2_OUT_N
SPKRAMP_R1_OUT_P
SPKRAMP_R1_OUT_N
SPKRAMP_R2_OUT_P

SPKRAMP_R2_OUT_N
SPKRAMP_LFE_OUT_P
SPKRAMP_LFE_OUT_N

USB_EXTC_P

USB_EXTC_N

USB_LT3_P
USB_LT3_N

Project Specific Constraints

SYNC_MASTER=M98_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

SHT

051-8071

60

60

30

7

30

7

60 45

60 45

39

39

39

7

39

7

30

7

30

7

30

7

30

7

39

7

39

7

31

7

31

7

81

81

31

7

7

31

57 56

7

57 56

7

57 56

7

57 56

7

57 56

7

57 56

7

57 56

7

57 56

7

57 56

7

57 56

7

98 91 20

98 91 20

98

7

98

7

SYNC_DATE=04/01/2008

OF

96 98

D

C

B

A

REV.

B

8

76

5

4

3

2

1

87

www.vinafix.vn

M99 Board-Specific Spacing & Physical Constraints

BOARD LAYERS

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM

LAYER

DEFAULT

STANDARD

D

55_OHM_SE

55_OHM_SE

LAYER

TOP,BOTTOM

LAYER

50_OHM_SE

50_OHM_SE =STANDARD

TOP,BOTTOM

ALLOW ROUTE
ON LAYER?

*

ALLOW ROUTE
ON LAYER?

*

ALLOW ROUTE
ON LAYER?

*Y

Y*

Y

Y

Y

Y

MINIMUM LINE WIDTH

=50_OHM_SE

MINIMUM LINE WIDTH

MINIMUM LINE WIDTH

0.090 MM

0.090 MM

MINIMUM NECK WIDTH

=50_OHM_SE

=DEFAULT=DEFAULT

MINIMUM NECK WIDTH

0.090 MM

0.076 MM0.076 MM

MINIMUM NECK WIDTH

0.095 MM0.110 MM

0.090 MM

BOARD AREAS

NO_TYPE,BGA

MAXIMUM NECK LENGTH

10 MM

10 MM

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

6

DIFFPAIR PRIMARY GAP

0 MM

=DEFAULT =DEFAULT

DIFFPAIR PRIMARY GAP

=STANDARD

DIFFPAIR PRIMARY GAP

BOARD UNITS
(MIL or MM)

MM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

0 MM

=STANDARD

=STANDARD=STANDARD

ALLEGRO
VERSION

15.5.1

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_BOARD_INFO

SPACING_RULE_SET

SPACING_RULE_SET

DEFAULT

STANDARD

BGA_P1MM

BGA_P3MM

1.5:1_SPACING

1.8:1_SPACING

2:1_SPACING

2.5:1_SPACING

3:1_SPACING

4:1_SPACING

21

D

BGA

BGA

BGA

BGA

BGA

BGA

3

TABLE_SPACING_ASSIGNMENT_HEAD

SPACING_RULE_SET

TABLE_SPACING_ASSIGNMENT_ITEM

BGA_P1MM

TABLE_SPACING_ASSIGNMENT_ITEM

BGA_P2MM

TABLE_SPACING_ASSIGNMENT_ITEM

BGA_P2MM

TABLE_SPACING_ASSIGNMENT_ITEM

BGA_P2MM

TABLE_SPACING_ASSIGNMENT_ITEM

BGA_P2MM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?*

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

5

*

*

*

*

*

*

*

*

*

*

*

LINE-TO-LINE SPACING

0.1 MM

=DEFAULT

=DEFAULT

=DEFAULTBGA_P2MM

=DEFAULT

LINE-TO-LINE SPACING

0.15 MM

0.18 MM

0.2 MM

0.25 MM

0.3 MM

0.4 MM

WEIGHT

WEIGHT

LAYER

LAYER

4

TABLE_SPACING_RULE_HEAD

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

* *

MEM_CLK

CLK_FSB

CLK_PCIE

CLK_SLOW

FSB_DSTB BGA_P3MMFSB_DSTB

NOTE:From T18 MLB, changed to reflect M99 stackup.

SPACING_RULE_SET

LAYER

2X_DIELECTRIC

3X_DIELECTRIC

4X_DIELECTRIC

5X_DIELECTRIC

AREA_TYPE

*

*

*

*

LINE-TO-LINE SPACING

0.140 MM

* ?

*

* ?

0.210 MM

0.280 MM

0.350 MM

=STANDARD

=STANDARD

=STANDARD

0.175 MM0.175 MM

0.150 MM0.150 MM

=STANDARD

0.180 MM0.180 MM

0.190 MM0.190 MM

=STANDARD

0.220 MM

0.230 MM0.230 MM

=STANDARD=STANDARD

0.200 MM0.200 MM

0.200 MM

0.220 MM0.220 MM

=STANDARD

0.330 MM

0.330 MM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

1:1_DIFFPAIR

100_DIFF_BGA

100_DIFF_BGA

100_DIFF_BGA

NOTE: 100_DIFF_BGA is 100-ohms differential impedance on outer layers and 95-ohms on inner layers.

LAYER

LAYER

ISL3,ISL4

ISL9,ISL10

ALLOW ROUTE
ON LAYER?

ALLOW ROUTE
ON LAYER?

*

=100_OHM_DIFF

MINIMUM LINE WIDTH

Y*

MINIMUM LINE WIDTH

=100_OHM_DIFF =100_OHM_DIFF

Y

Y

MINIMUM NECK WIDTH

=STANDARD =STANDARD

=STANDARD

MINIMUM NECK WIDTH

=100_OHM_DIFF

0.075 MM

0.075 MM

0.075 MM

0.075 MM

MAXIMUM NECK LENGTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

0.1 MM 0.1 MM

DIFFPAIR PRIMARY GAP

=100_OHM_DIFF =100_OHM_DIFF

0.125 MM 0.125 MM

0.125 MM 0.125 MM

C

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

B

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

PCB Rule Definitions

SYNC_MASTER=M98_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

D

NONE

DRAWING NUMBER

051-8071

SHT

SYNC_DATE=04/01/2008

OF

97 98

A

REV.

B

LAYER

40_OHM_SE

40_OHM_SE

C

27P4_OHM_SE

27P4_OHM_SE

TOP,BOTTOM

LAYER

TOP,BOTTOM

LAYER

70_OHM_DIFF

70_OHM_DIFF

70_OHM_DIFF

70_OHM_DIFF

70_OHM_DIFF

ISL3,ISL4

ISL9,ISL10

ISL2,ISL11

TOP,BOTTOM

LAYER

80_OHM_DIFF

80_OHM_DIFF

80_OHM_DIFF

80_OHM_DIFF

80_OHM_DIFF

ISL3,ISL4

ISL9,ISL10

ISL2,ISL11

TOP,BOTTOM

ALLOW ROUTE
ON LAYER?

*

ALLOW ROUTE
ON LAYER?

ALLOW ROUTE
ON LAYER?

*

ALLOW ROUTE
ON LAYER?

*

Y

Y

Y

Y*

N

Y

Y

Y

Y

N

Y

Y

Y

Y

MINIMUM LINE WIDTH

0.165 MM

0.135 MM

MINIMUM LINE WIDTH

MINIMUM LINE WIDTH

=STANDARD

0.170 MM

0.170 MM

MINIMUM LINE WIDTH

=STANDARD

0.140 MM

0.140 MM

MINIMUM NECK WIDTH

0.095 MM

0.135 MM

MINIMUM NECK WIDTH

0.095 MM0.310 MM

0.250 MM0.250 MM

MINIMUM NECK WIDTH

=STANDARD

0.160 MM0.160 MM

0.160 MM0.160 MM

0.170 MM

0.095 MM

MINIMUM NECK WIDTH

=STANDARD

0.125 MM0.125 MM

0.125 MM0.125 MM

0.140 MM

0.095 MM

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

=STANDARD

DIFFPAIR PRIMARY GAP

=STANDARD

DIFFPAIR PRIMARY GAP

=STANDARD

DIFFPAIR PRIMARY GAP

=STANDARD

0.175 MM 0.175 MM

0.150 MM 0.150 MM

DIFFPAIR PRIMARY GAP

=STANDARD

0.180 MM 0.180 MM

0.190 MM 0.190 MM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

B

LAYER

90_OHM_DIFF

90_OHM_DIFF

90_OHM_DIFF

90_OHM_DIFF

90_OHM_DIFF

ISL3,ISL4

ISL9,ISL10

ISL2,ISL11

TOP,BOTTOM

LAYER

100_OHM_DIFF

100_OHM_DIFF

100_OHM_DIFF

A

100_OHM_DIFF

100_OHM_DIFF

ISL3,ISL4

ISL9,ISL10

ISL2,ISL11

TOP,BOTTOM

LAYER

110_OHM_DIFF

110_OHM_DIFF

110_OHM_DIFF

110_OHM_DIFF

110_OHM_DIFF

ISL3,ISL4

ISL9,ISL10

ISL2,ISL11

TOP,BOTTOM

ALLOW ROUTE
ON LAYER?

ALLOW ROUTE
ON LAYER?

*N

ALLOW ROUTE
ON LAYER?

*

N*

Y

Y

Y

Y

Y

Y

Y

Y

N

Y

Y

Y

Y

MINIMUM LINE WIDTH

0.102 MM

0.102 MM 0.102 MM

0.115 MM

0.115 MM

MINIMUM LINE WIDTH

=STANDARD =STANDARD

0.080 MM

0.080 MM

0.089 MM

0.089 MM 0.089 MM

MINIMUM LINE WIDTH

=STANDARD =STANDARD

0.077 MM

0.077 MM

0.077 MM

0.077 MM 0.077 MM

MINIMUM NECK WIDTH

0.102 MM

0.115 MM

0.095 MM

MINIMUM NECK WIDTH

=STANDARD

0.080 MM

0.080 MM

0.089 MM

MINIMUM NECK WIDTH

0.077 MM

0.077 MM

0.077 MM

MAXIMUM NECK LENGTH

=STANDARD=STANDARD=STANDARD

MAXIMUM NECK LENGTH

MAXIMUM NECK LENGTH

=STANDARD

DIFFPAIR PRIMARY GAP

=STANDARD

0.220 MM 0.220 MM

0.220 MM

0.230 MM 0.230 MM

DIFFPAIR PRIMARY GAP

0.200 MM

0.220 MM 0.220 MM

DIFFPAIR PRIMARY GAP

=STANDARD

0.330 MM

0.330 MM

0.330 MM 0.330 MM

0.330 MM 0.330 MM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

8

76

5

4

3

2

1

87

www.vinafix.vn

6

5

4

3

21

Port Power Switch

ENABLE TIED LOW SO INPUT POWER SOURCE MUST BE S3!!!

=PP5V_S3_RTUSB

8

39

D

20

USB_EXTC_OC_L

OUT

20 91 96

20 91 96

BI

BI

CC380

USB_EXTC_N
USB_EXTC_P

10UF

6.3V

1

1

CC381

0.1UF

20%

X5R
603

20%
10V

2

2

CERM
402

2

3

5

4

CRITICAL

UC380

TPS2068

IN1

MSOP

IN2

OC*

EN*

GND

1

TPAD

9

OUT1

OUT2

OUT3

6

7

8

CC385

10UF

6.3V

PP5V_S3_RTUSB_C_ILIM

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.375 mm
VOLTAGE=5V

CRITICAL

1

1

CC386

20%

X5R
603

100UF

20%

6.3V

2

2

POLY-TANT
CASE-B2-SM

CC325

0.01uF

CERM

1

20%
16V

2

402

C

PART NUMBER

514-0638 CRITICAL

QTY

1

LEFT USB PORT C

CRITICAL

LC325

FERR-220-OHM-2.5A

CRITICAL

90-OHM-100MA

43

DESCRIPTION

CONN,RCPT,USB,HB,4P

0603

LC320

DLP11S

SYM_VER-1

21

PP5V_S3_RTUSB_C_F

7

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.375 mm
VOLTAGE=5V

USB_LT3_N

7

96

21

USB_LT3_P

7

96

PLACE LC320 AND LC325 AT CONNECTOR PIN

REFERENCE DES

6

VBUS

1

GND

RCLAMP0502N

JC320

NC

DC320

SLP1210N6

CRITICAL

IOIONC

CRITICAL

JC320

USB

F-RT-TH-M97-3

5

6

OMIT

1

2

3

4

3245

7

8

D

C

CRITICAL

BOM OPTION

B

A

8

76

B

PROJECT SPECIFIC CONNS

SYNC_MASTER=N/A

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

5

4

3

2

SCALE

NONE

051-8071

SHT

SYNC_DATE=N/A

OF

98 98

1

A

REV.

B