Apple 820-2610-A Schematic

87

www.vinafix.vn

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

6

5

4

SCHEMATIC,Folsten_MBP17

3

REV

21

ZONE

ECN

738810B

DESCRIPTION OF CHANGE

Production Release

CK
APPD

DATE

ENG
APPD

6/19/096/19/09

DATE

06/15/09

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45

(.csa)

1

Table of Contents

2
3
4
5
6
7
8
9

2

System Block Diagram

3

Power Block Diagram

4

Revision History

5

BOM Configuration

6

JTAG Scan Chain

7

Functional / ICT Test

8

Power Aliases

9

Signal Aliases

10

CPU FSB

11

CPU Power & Ground

12

CPU Decoupling & VID

13

eXtended Debug Port(MiniXDP)

14

MCP CPU Interface

15

MCP Memory Interface

16

MCP Memory Misc

17

MCP PCIe Interfaces

18

MCP Ethernet & Graphics

19

MCP PCI & LPC

20

MCP SATA & USB

21

MCP HDA & MISC

22

MCP Power & Ground

25

MCP Standard Decoupling

26

MCP Graphics Support

28

SB Misc

29

FSB/DDR3/FRAMEBUF Vref Margining

31

DDR3 SO-DIMM Connector A

32

DDR3 SO-DIMM Connector B

33

DDR3 Support

34

Right Clutch Connector

35

ExpressCard Connector

37

Ethernet PHY (RTL8211CL)

38

Ethernet & AirPort Support

39

Ethernet Connector

41

FireWire LLC/PHY (FW643)

42

FireWire Port Power

43

FireWire Ports

45

SATA Connectors

46

External USB Connectors

48

Front Flex Support

49

SMC

50

SMC Support

51

LPC+SPI Debug Connector

52

K20 SMBUS CONNECTIONS

53

Current & Voltage Sensing

Contents

K20_MLB

M98_MLB

RXU_K20

NA

K20A_MLB

BEN_K20

K20_MLB

RXU_K20

K20_MLB

M98_MLB

M98_MLB

M98_MLB

M98_MLB

T18_MLB

T18_MLB

T18_MLB

T18_MLB

T18_MLB

T18_MLB

T18_MLB

T18_MLB

T18_MLB

M98_MLB

M98_MLB

M98_MLB

BEN_K20

BEN_K20

BEN_K20

M98_MLB

M98_MLB

BEN_K20

SUMA_K20

SUMA_K20

SUMA_K20

M98_MLB

YWU_K20

M98_MLB

M98_MLB

M98_MLB

CHANG_K20

T18_MLB

M98_MLB

CHANG_K20

BEN_K20

YWU_K20

D

C

B

Page

TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_HEAD

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TABLE_TABLEOFCONTENTS_ITEM

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Sync

Date

04/01/2008

04/01/2008

07/24/2008

NA

04/01/2008

07/11/2008

09/24/2008

05/07/2008

09/24/2008

04/01/2008

04/01/2008

04/01/2008

04/01/2008

06/06/2008

06/06/2008

06/06/2008

06/06/2008

06/06/2008

06/06/2008

06/06/2008

06/06/2008

06/06/2008

04/01/2008

04/01/2008

05/01/2008

10/15/2008

06/10/2008

07/14/2008

04/01/2008

05/01/2008

10/15/2008

07/22/2008

07/15/2008

07/15/2008

04/01/2008

05/28/2008

07/14/2008

05/01/2008

07/14/2008

07/18/2008

06/06/2008

05/01/2008

05/28/2008

07/22/2008

08/20/2008

(.csa)

Page Sync

46

TABLE_TABLEOFCONTENTS_ITEM

47

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48

TABLE_TABLEOFCONTENTS_ITEM

49

TABLE_TABLEOFCONTENTS_ITEM

50

TABLE_TABLEOFCONTENTS_ITEM

51

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52

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53

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54

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55

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56

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57

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58

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59

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60

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61

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62

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63

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64

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65

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66

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67

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68

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69

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70

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71

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72

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73

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74

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75

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76

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77

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78

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79

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80

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81

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82

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83

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84

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85

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86

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87

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88

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89

TABLE_TABLEOFCONTENTS_ITEM

90

TABLE_TABLEOFCONTENTS_ITEM

54

Current Sensing

55

Thermal Sensors

56

Fan Connectors

57

WELLSPRING 1

58

WELLSPRING 2

59

Sudden Motion Sensor (SMS)

61

SPI ROM

62

AUDIO:CODEC

63

AUDIO: LINE IN

65

AUDIO: HEADPHONE AMP

66

AUDIO:SPEAKER AMP

67

AUDIO: JACKS

68

AUDIO: JACK TRANSLATORS

69

DC-In & Battery Connectors

70

PBus Supply & Battery Charger

71

IMVP6 CPU VCore Regulator

72

5V / 3.3V Power Supply

73

1.5V DDR3 Supply

75

5V_S0 / MCP CORE REGULATOR

76

CPU VTT Power Supply

77

Misc Power Supplies

78

Power Control

79

Power FETs

80

NV G96 PCI-E

81

NV G96 CORE/FB POWER

82

NV G96 FRAME BUFFER I/F

84

GDDR3 Frame Buffer A (Bottom)

85

GDDR3 Frame Buffer B (Bottom)

86

NV G96 GPIO/MIO/MISC

87

G96 GPIOs & Straps

88

NV G96 Video Interfaces

89

GPU (G96) CORE SUPPLY

90

LVDS Display Connector

91

GDDR3 Frame Buffer A (Top)

92

GDDR3 Frame Buffer B (Top)

93

Muxed Graphics Support

94

DisplayPort Connector

95

1.1V / 1V8 FB Power Supply

96

Graphics MUX (GMUX)

97

LCD BACKLIGHT DRIVER

98

LCD Backlight Support

99

Misc Power Supplies

100

CPU/FSB Constraints

101

Memory Constraints

102

MCP Constraints 1

Contents

YWU_K20

YWU_K20

M98_MLB

YMA_K20

K20_MLB

YWU_K20

M98_MLB

AUDIO_K20

AUDIO_K20

AUDIO_K20

AUDIO_K20

AUDIO_K20

AUDIO_K20

RXU_K20

RXU_K20

RXU_K20

RXU_K20

RXU_K20

RXU_K20

RXU_K20

RXU_K20

YMA_K20

YMA_K20

M98_MLB

M98_MLB

K20_MLB

M98_MLB

M98_MLB

K20_MLB

M98_MLB

K20_MLB

RXU_K20

M98_MLB

M99_MLB

M88_MLB

M98_MLB

K20_MLB

RXU_K20

T18_MXMGMUX

KIRAN_K20

YLEE_K20

RXU_K20

M98_MLB

M98_MLB

M98_MLB

Date

08/12/2008

05/28/2008

04/01/2008

05/19/2008

09/24/2008

06/17/2008

05/01/2008

09/29/2008

09/29/2008

09/29/2008

09/29/2008

09/29/2008

09/29/2008

05/21/2008

05/21/2008

05/21/2008

05/21/2008

05/21/2008

05/21/2008

05/21/2008

05/21/2008

09/09/2008

05/19/2008

04/01/2008

04/01/2008

09/24/2008

04/01/2008

04/01/2008

09/24/2008

05/12/2008

09/24/2008

05/21/2008

07/14/2008

04/04/2008

11/01/2007

05/01/2008

09/24/2008

05/21/2008

02/13/2008

03/19/2009

07/18/2008

05/07/2008

04/01/2008

04/01/2008

04/01/2008

Page

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEMTABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

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TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

911
92
93
94
95
96
97
98

(.csa)

103

MCP Constraints 2

104

Ethernet Constraints

105

FireWire Constraints

106

SMC Constraints

107

GPU (G96) Constraints

108

Project Specific Constraints

109

PCB Rule Definitions

123

PROJECT SPECIFIC CONNS

Contents

Sync

M98_MLB

M98_MLB

M98_MLB

M98_MLB

M98_MLB

M98_MLB

M98_MLB

N/A

Date

04/01/2008

04/01/2008

04/01/2008

04/01/2008

05/01/2008

04/01/2008

04/01/2008

N/A

D

C

B

A

8

76

DIMENSIONS ARE IN MILLIMETERS

XX

X.XX

X.XXX

ANGLES

DO NOT SCALE DRAWING

THIRD ANGLE PROJECTION

5

4

3

DRAFTER

ENG APPD

QA APPD

RELEASE

METRIC

MATERIAL/FINISH

NOTED AS

APPLICABLE

DESIGN CK

MFG APPD

DESIGNER

SCALE

NONE

SIZE

2

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

TITLE

DRAWING NUMBER

D

APPLE INC.

SCHEM,Folsten,MBP17

051-8071

REV.

SHT

1

1

A

B

OF

98

87

www.vinafix.vn

6

U1000

INTEL CPU

2.X OR 3.X GHZ

PENRYN

PG 9

5

U1300

XDP CONN

PG 12

4

3

21

FSB

D

PG 13

GPIOs

FSB INTERFACE

64-Bit

800/1067/1333 MHz

MAIN

MEMORY

PG 14

2 UDIMMs

DDR2-800MHZ
DDR3-1067/1333MHZ

J2900

DIMM

PG 25,26

J6950

DC/BATT

PG 60

U4900

POWER SUPPLY

D

TEMP SENSOR

USB

PG 39

PG 41

PG 45

PG 48,49

J5100

Port80,serial

LPC Conn

PG 43

C

B

CLK

SYNTH

J4510

SATA

Conn

PG 38

HD

J4520

SATA

Conn

PG 38

C

ODD

1.05V/3GHZ.

1.05V/3GHZ.

SATA

PG 19

NVIDIA

MCP79

U1400

J9000

LVDS

CONN

J9400

DISPLAY PORT

CONN

PG 71

PG 71

LVDS OUT

RGB OUT

DP OUT

HDMI OUT

DVI OUT

TMDS OUT

PG 17

UP TO 20 LANES3

PG 16

PCI-E

B

RGMII

PG 17

PCI

(UP TO FOUR PORTS)

PG 18

Misc

PG 24

SPI

PG 20

LPC

PG 18

PWR

CTRL

USB

PG 19

(UP TO 12 DEVICES)

SMB

PG 20

HDA

PG 20

J4720

Bluetooth

4

389

2

10567

U6100

SPI

Boot ROM

PG 52

J4900

B,0

BSB

FanADC

SMC

PG 41

J4700

TRACKPAD/

PG 40

KEYBOARD

PG 40

J4710

IR

PG 40

J4710

CAMERA

PG 40

POWER SENSE

J5650,5600,5610,5611,5660,5720,5730,5750

FAN CONN AND CONTROL

Ser

Prt

J3900,4635,4655

EXTERNAL

Connectors

SMB

CONN

DIMM’s

PG 44

A

J3400 U3900

Mini PCI-E

AirPort

PG 28

8

76

U3700

GB

E-NET

88E1116

PG 31

E-NET

Conn

PG 33

U6200

U6301 U6500U6400

Line In

Amp

PG 54

HEADPHONE

Amp Amp

J6800,6801,6802,6803

5

Audio

Codec

PG 53

U6600,6605,6610,6620

Line Out

PG 56PG 55

Audio

Conns

PG 59

4

Speaker

Amps

PG 57

3

SYNC_MASTER=M98_MLB

APPLE INC.

2

System Block Diagram

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

SHT

051-8071

2

1

SYNC_DATE=04/01/2008

REV.

B

OF

98

A

87

www.vinafix.vn

6

5

4

3

21

"Folsten" POWER SYSTEM ARCHITECTURE

PPDCIN_G3H

J6900

D

AC

ADAPTER

IN

DCIN(16.5V)

F6905
6A FUSE

R7020

SMC_DCIN_ISENSE

A

U7000

VIN

ISL6258A

PBUS SUPPLY/

BATTERY CHARGER

(PAGE 60)

J6950

PPVBATT_G3H_CONN

2S4P

(6 TO 8.4V)

C

GMUX

U9600

XP28

(PAGE 84)

PB16B

PB17A

PB17B

PB18A

PL32A

EG_RAIL1_EN

EG_RAIL2_EN

EG_RAIL3_EN

EG_RAIL4_EN

PM_ALL_GPU_PGOOD

SMC

RC

DELAY

Q7056

BATT_POS_GATE

P1V1GPU_EN

P3V3GPU_EN

GPUVCORE_EN

P1V8_S0GPU_EN

P3V3S5_EN

Q7055

CHGR_BGATE

U4900

PM_G2_P1V05S5_EN

RC

DELAY

(PAGE 42)

P60

SMC_PM_G2_EN

MCP79

SLP_RMGT#(J17)

B

PCI_RESET0#(R10)

U1400

SLP_S5#(H17)

SLP_S3#(G17)

PM_SLP_RMGT_L

R2870

RC

DELAY

PM_SLP_S4_L

PM_SLP_S3_L

MEM_VTT_EN

DDRREG_EN

P5VS3_EN

R6905

VOUT

PPVBAT_G3H_CHGR_R

P1V1_GPU_EN

P1V8_S0GPU_EN

BKLT_PLT_RST_L

LCD_BKLT_EN

PPVBAT_G3H_CHGR_REG

R7050
U5303

SMC_BATT_ISENSE

MCPCORES0_EN

PM_SLP_S3_L_R

Q4260

VIN

EN1

1.103V(L/H)

EN2

1.8V(R/H)

ISL6236

U9500

(PAGE 83)

ENA&&

(PAGE 85~86)

A

VOUT2

P5VS3_EN

P3V3S5_EN

VIN

APP001

U9701

VIN

(PAGE 14~22)

FW_PORTPWR_EN&&(SMC_ADAPTER_EN||PM_SLP_S3_L)

R7878

PM_SLP_S3_L_R

A

DELAY

DELAY

DELAY

DELAY

RC

RC

RC

RC

P1V8S0_EN

MCPDDR_EN

CPUVTTS0_EN

MCPCORES0_EN

DELAY

DELAY

DELAY

P1V05S0_EN

RC

P1V2_S0_EN

RC

P2V5S0_EN

RC

PM_G2_P1V05S5_EN

EN

VIN

1.05V AUX

ISL6269

U7750

(PAGE 66)

VOUT1

POK1

POK2

(PAGE 66)

D6905

D6905

F7040

F7041

8A FUSE

MCP_CORE

EN2

EN1

VIN

(PAGE 64)

PP1V1_S0GPU

R5413

A

P1V1GPU_PGOOD

PM_ALL_GPU_PGOOD

VOUT

LTC1872

U7790

VOUT

PGOOD

VOUT2

5V

VOUT1

ISL6236

POK1

U7500

POK2

PP1V8_S0GPU_ISNS

SMC_GPU_1V8_ISENSE

VIN

EN1

5V

(L/H)

3.3V

EN2

(R/H)

TPS51220

U7201

(PAGE 62)

PGOOD1,2

P5V3V3_PGOOD

PPVOUT_S0_LCDBKLT

PP10V_FW

VOUT

PP1V2R1V05_S5

P1V05_S5_PGOOD

PPVIN_G3H_P3V42G3H

PPBUS_G3H

R7505

A

SMC_MCP_CORE_ISENSE

PP5V_S0

P5V_RTS0_PGOOD

MCPCORES0_PGOOD

DDRREG_EN

MEM_VTT_EN

PP5V_S3

VOUT1

PP3V3_S5

VOUT2

PPBUS_G3H_VSENSE

GPUVCORE_EN

SMC_CPU_HI_ISENSE

V

PPVCORE_S0_MCP

Q7953

P1V05S0_EN

V

SMC_MCP_VSENSE

Q7910

Q7930

Q7970

PP1V05_S0

Q3840

PM_SLP_RMGT_L

Q3810

Q5315

VIN

S5

S3

TPS51116

(PAGE 63)

PM_SLP_S4_L

PM_SLP_S3_L

P3V3GPU_EN

PM_SLP_RMGT_L

VIN

GPU VCORE

ISL6263C

U8900

(PAGE 77)

R5388

A

IMVP_VR_ON

1.5V

0.75V

U7300

PP3V3_S5

PP3V3_S3

PP3V3_S0

PP3V3_S0GPU

P3V3_ENET_PHY

PP1V2R1V05_ENET

PGOODVR_ON

VLDOIN

VOUT1

VOUT2

ENABLE

3.425V G3HOT

(PAGE 59)

VOUT

P1V8_S0GPU_EN

LT3470A

U6990

A

U5410

SMC_GPU_ISENSE

GPUVCORE_PGOOD

CPU VCORE

VIN

ISL9504B

U7100

VR_ON

(PAGE 61)

PP1V8R1V5_S3

PP0V9R0V75_S0_DDRVTT

P1V2_S0_EN

P2V5S0_EN

R0940

P1V0FW_EN

P1V8S0_EN

EN

PP3V42_G3H

VOUT

PGOOD

VI

TPS62202

U7760

(PAGE 66)

PP3V3_S5

P1V05_S5_PGOOD

SMC_GPU_VSENSE

V

PPVCORE_GPU

U7100

SMC_CPU_ISENSE

VR_PWRGOOD_DELAY

RUN1

LTC3547

U9900

RUN2

(PAGE 87)

RUN1

LTC3547

U7700

RUN2

(PAGE 66)

VOUT

PP3V42_G3H

A

Q7901

MCPDDR_EN

VIN

VOUT1

VOUT2

VIN

VOUT1

VOUT2

PP1V8_GPUIFPX

PP1V8R1V5_S0

PP1V05_S0

SENSE

(PAGE 67)

S5 PWRGD

NCP303LSN

(PAGE 42)

SMC_CPU_VSENSE

V

R5445

SMC_MCP_DDR_ISENSE

A

PP1V2_S0

PP2V5_S0

PM_ALL_GPU_PGOOD

PP1V0_FW

PP1V8_S0

VDD

U7840

TPS3808G

SMC PWRGD

U5000

CPUVTTS0_EN

PPVCORE_S0_CPU

PPMCPDDR_ISNS

PP1V8R1V5_S0

PP3V3_S5

S0PGOOD_PWROK

PP3V3_S0

ADJ1

ADJ2

RSMRST_PWRGD

RESET*

MR*

SMC_RESET_L

EN_PSV

R7894

P5V3V3_PGOOD

P5V_RTS0_PGOOD

MCPCORES0_PGOOD

CPUVTTS0_PGOOD

VCC

U7870

LTC2909

(PAGE 67)

TRST = 200mS

VIN

1.05V

SC417
U7600

(PAGE 65)

U7880

RST*

MIC5232-2.8YD5

U2801

VIN

(PAGE 25)

VOUT

PGOOD

ALL_SYS_PWRGD

RSMRST_PWRGD

VOUT

CPUVTTS0_PGOOD

MCP_PS_PWRGD

U2850

SMC_ONOFF_L

PM_SLP_S4_L

PM_SLP_S4_L

PM_SLP_S3_L

PP3V3_G3_RTC

R7650

PPCPUVTT_S0

A

SMC_CPU_FSB_ISENSE

PS_PWRGD

(PAGE 14~22)

CPU

U1000

(PAGE 10,11)

PWRGD(P12)

RSMRST_IN(P13)

PWR_BUTTON(P90)

SLP_S5_L(P95)

SLP_S4_L(P94)

SLP_S3_L(P93)

SYNC_MASTER=RXU_K20

APPLE INC.

SMC_TPAD_RST_L

SMC_ONOFF_L

U5001

MCP79

PWRBTN#

RSTBTN#

PWRGD_SB

CPU_RESET#

CPU_PWRGD

PM_SYSRST_DEBOUNCE_L

FSB_CPURST_L

CPU_PWRGD

U1400

PWRGOOD

RESET*

SMC

U4900

(PAGE 42)

RSMRST_OUT(P15)

99ms DLY

IMVP_VR_ON(P16)

P17(BTN_OUT)

SYSRST(PA2)

RES*

PM_RSMRST_L

IMVP_VR_ON

PM_SYSRST_L

PM_PWRBTN_L

SMC_RESET_L

Power Block Diagram

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

SHT

051-8071

3

SYNC_DATE=07/24/2008

REV.

B

OF

98

D

C

B

A

8

76

5

4

3

2

1

87

www.vinafix.vn

PVT:

03/24/09
csa.5: Project copied from K20 mlb_pvt.

Changed CPU APNs for 2.8 and 3.06GHz CPUs.

Changed BOM and EEE codes for K20A.
csa.45: Connected =PP1V5_EXP_S0 to J4501.13 for SATA redriver on flex.
03/25/09
csa.9: Added PBUS VS 5V voltage selection resistors for keyboard backlight driver.
03/27/09
csa.90: Added 1000pF cap to the backlight power pin for EMI baseline noise.
03/30/09

D

csa.5: Changed the bom option to KBDLED_5V per radar# 6723272.
03/31/09
csa.1: Changed rev to 1.0.0
04/09/09
csa.70: No stuff C7099 per radar# 6772695.
04/29/09
Production Release Fab to rev A
csa.5: Changed K20A EFI ROM APN 341S2507 ( BOM change only )
05/05/09
Added 128S0264 (SANYO) as alternate to 128S0257 (KEMET ELEC) per Radar# 6656624.
06/15/09
Added 107S0136 (DALE/VISHAY) as alternate to 107S0132 (CYNTEC) per Radar# 6971400.
For U7871 P/N 353S2718 is made primary. P/N 353S2310 is added back as alternate.
For U6100 Locked Bootrom P/N 341S2506 replaces existing Unlock Bootrom P/N 341S2507.

6

5

4

3

21

D

C

B

C

B

A

8

76

Revision History

OF

SYNC_DATE=NA

REV.

B

98

A

SYNC_MASTER=NA

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

5

4

3

2

SCALE

NONE

SHT

051-8071

4

1

87

www.vinafix.vn

BOM Variants

BOM NUMBER

639-0172

639-0173

639-0174

639-0175

D

Folsten BOM GROUPS

BOM GROUP

K20A_COMMON

K20A_COMMON1

K20A_COMMON2

K20A_DEBUG

K20A_PROGPARTS

BOM GROUP

FB_1024_SAMSUNG

FB_512_SAMSUNG

FB_512_HYNIX

6

BOM NAME

PCBA,BEST,2.8,512SAM_VRAM,K20A

PCBA,BEST,3.06,512SAM_VRAM,K20A

PCBA,BEST,2.8,512HYN_VRAM,K20A

PCBA,BEST,3.06,512HYN_VRAM,K20A

K20A_COMMON,EEE_9EH,CPU_2_80GHZ,FB_512_SAMSUNG

K20A_COMMON,EEE_9EK,CPU_3_06GHZ,FB_512_SAMSUNG

K20A_COMMON,EEE_9EL,CPU_2_80GHZ,FB_512_HYNIX

K20A_COMMON,EEE_9EM,CPU_3_06GHZ,FB_512_HYNIX

BOM OPTIONS

ALTERNATE,COMMON,K20A_COMMON1,K20A_COMMON2,K20A_DEBUG,K20A_PROGPARTS

ONEWIRE_PU,ISL6258,MEMRESET_HW,MEMRESET_MCP,MCP_B03,MCP_PROD,MCPSEQ_SMC,BMON_PROD,MCP_CS1_NO,FW_LVG_NEW,PROD_DIGSMS,TPDT_DEBOUNCE,KBDLED_5V

BOOT_MODE_USER,GPUVID_1P00V,MUXGFX,DPMUX_EN_S0,DP_ESD,EG_PWRSEQ_GMUX,DP_CA_DET_EG_PLD,BKLT_PLL_NOT,GMUX_1V8

SMC_DEBUG_YES,XDP,LPCPLUS_NOT,NO_VREFMRGN

GMUX_PROG,BOOTROM_PROG,SMC_PROG,TPAD_PROG

BOM OPTIONS

VRAM8,VRAM_1024_SAMSUNG

VRAM4,VRAM_512_SAMSUNG

VRAM4,VRAM_512_HYNIX

BOM OPTIONS

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

5

Alternate Parts

PART NUMBER

152S0476

353S1681

138S0603

152S0684 152S0368

104S0023 104S0018

104S0024 104S0017

341S2367 341S2366

152S0876

157S0058

152S0896

128S0264

107S0136

353S2310

ALTERNATE FOR
PART NUMBER

152S0276

353S1294

138S0602

152S0782

157S0055

514-0607514-0612

514-0608514-0613

152S0421152S0684

152S0518

152S0796152S0915

155S0329155S0457

128S0257

107S0132

353S2718

BOM OPTION

4

REF DES

COMMENTS:

ALL

Inductor alternate

ALL

TI alt to National

ALL

Murata alt to Samsung

ALL

Maglayers alt to Dale/Vishay

ALL

Cyntec alt to sense resistor

ALL

Panasonic alt to FW resistor

ALL

Macronix alt to SST

ALL

Maglayer alt to Delta

Delta alt to TDK Magnetics

ALL

FOXLINK ALT TO FOXCONN XCVRALL

FOXLINK ALT TO FOXCONN RCVRALL

ALL MAG LAYERS ALT TO VISHAY

MAG LAYERS ALT TO CYNTEC

ALL

ALL

MAG LAYERS ALT TO CYNTEC

MAG LAYERS ALT TO MURATA

ALL

ALL

SANYO ALT TO KEMET ELEC.

DALE/VISHAY ALT TO CYNTEC.

ALL

ALL

INTERSIL.COMMON TO K24/K19

3

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

21

D

C

Bar Code Labels / EEE #’s

PART NUMBER

826-4393

826-4393

826-4393

826-4393

Module Parts

B

PART NUMBER

338S0710

335S0610

341S2506

341S2384

341S2383

337S3744

333S0481

333S0506

QTY

1

1

1

1

QTY

1

1

1

1

1

1

1

1

1

1

1

1

4

8

4

DESCRIPTION

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

IC,ASSP,GPU,NV G96-GS,VLOWLKG,BGA969,LF

IC,RTL8251CA-VB-GR,GIGE TRANSCEIVER,48P LQFP

IC,FW643-E,1394B PHY/OHCI LINK/PCI-E,12

IC,MCP79XT-B3,35X35MM,BGA1437

IC,SMC,HS8/2117,9MMX9MM,TLP

IC,SMC,DEVELOPMENT,K20

IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP

IC,LOCKED EFI ROM,K20A

IR,ENCORE II, CY7C63833-LFXC

IC,PSOC +W/USB,56PIN,MLF,M98

IC,PDC,SLGKH,PRQ,3.06,35W,1066,E0,6M,BGA

IC,PDC,SLGEM.PRQ,2.80,35W,1066,E0,6M,BGA

IC,SGRAM,GDDR3,32MX32,800MHZ,136 FBGA

IC,SGRAM,GDDR3,32MX32,800MHZ,136 FBGA

IC,SDRAM,GDDR3,32MX32,900MHZ,TIVA,HF

A

DESCRIPTION

REFERENCE DES

[EEE:9EH]

[EEE:9EK]

[EEE:9EL]

[EEE:9EM]

REFERENCE DES

U8000

U3700

U4100

U1400

U4900

U4900

U6100

U6100

U4800

U5701

U1000

U1000

U8400,U8450,U8500,U8550

U8400,U8450,U8500,U8550,U9100,U9150,U9200,U9250

U8400,U8450,U8500,U8550

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL338S0737

CRITICAL338S0694

CRITICAL338S0654

CRITICAL

CRITICAL338S0563

CRITICAL341S2355

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL337S3682

CRITICAL333S0481

CRITICAL

CRITICAL

BOM OPTION

EEE_9EH

EEE_9EK

EEE_9EL

EEE_9EM

BOM OPTION

MCP_B03

SMC_BLANK

SMC_PROG

BOOTROM_BLANK

BOOTROM_PROG

TPAD_PROG

CPU_3_06GHZ

CPU_2_80GHZ

VRAM_512_SAMSUNG

VRAM_1024_SAMSUNG

VRAM_512_HYNIX

BOM Configuration

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

D

NONE

DRAWING NUMBER

SHT

051-8071

C

B

SYNC_DATE=04/01/2008SYNC_MASTER=K20A_MLB

REV.

OF

5

98

A

B

8

76

5

4

3

2

1

87

www.vinafix.vn

6

5

4

3

21

1.05V TO 3.3V LEVEL TRANSLATOR (M98: ON ICT FIXTURE)

=PP3V3_S0_XDP

6 8

13

D

C

8

10 11 12 13 61

=PP1V05_S0_CPU

JTAG_ALLDEV

R0601

1/16W
MF-LF

NOSTUFF

R0602

1/16W
MF-LF

10K

13 21

13 21

13 21

13 21

U1000

CPU

U1400

MCP

MAKE_BASE=TRUE

From XDP connector

JTAG_ALLDEV

1

C0601

0.1UF

20%
10V

2

CERM
402

1

5%

402

2

XDP_TCK

6

10 13 88

1

0

5%

402

2

XDP_TMS

6

10 13 88

XDP_TRST_L

6

10 13 88

JTAG_LVL_TRANS_EN_L

1

2

JTAG_ALLDEV

C0602

0.1UF

20%
10V
CERM
402

JTAG_ALLDEV

2

3

4

5

12

VCCA

NLSV4T244

A1
A2
A3
A4

OE*

1

U0600

UQFN

GND

6

11

VCCB

6

10 13 88

10 13 88

6

10 13 88

6

10 13 88

XDP_TCK

IN

XDP_TDI

IN

XDP_TMS

IN

XDP_TRST_L

IN

From XDP connector

or via level translator

10

B1

9

B2

8

B3

7

B4

1

R0606

10K

5%
1/16W
MF-LF
402

2

MAKE_BASE=TRUE

MAKE_BASE=TRUE

JTAG_MCP_TCK
JTAG_MCP_TDI
JTAG_MCP_TMS
JTAG_MCP_TRST_L

To XDP connector
and/or level translator

XDP_TDO

10 88

JTAG_MCP_TDO

21

XDP

PLACEMENT_NOTE=Place near pin U1000.AB3

R0603

0

21

5%
1/16W
MF-LF

402

XDP

PLACEMENT_NOTE=Place near pin U1400.F19

R0604

0

21

5%
1/16W
MF-LF

402

XDP_TDO_CONN

JTAG_MCP_TDO_CONN

13

OUT

XDP connector

13

OUT

XDP connector

D

C

NOSTUFF

PLACEMENT_NOTE=Place close to U8000

R0605

10K

1/16W
MF-LF

21

5%

402

GPU_JTAG_TMS

6

74

B

74

74

6

74

74

84

9

84

9

84

U8000

GPU

U9600

GMUX

74

84

9

GPU_JTAG_TDO

JTAG_GMUX_TDO

6

VCC

U0601

74LVC1G07

2

1

GMUX CPLD Programming Port

CRITICAL

J0600

1909782

M-RT-SM

GMUX_JTAG_CONN

B

7

=PP3V3_S0_XDP

1

TDO

2

3

TDI
TMS

4

5

TCK

6

8

6 8

NC NC

13

YA

4

5

NCNC

SOT886

GND

3

PLACEMENT_NOTE=Place close to U0600

GPU_JTAG_TCK

GPU_JTAG_TDI
GPU_JTAG_TMS
GPU_JTAG_TRST_L

JTAG_GMUX_TCK

JTAG_GMUX_TDI
JTAG_GMUX_TMS

=PP3V3_GPU_VDD33

8

74 75

TP_GPU_JTAG_TDO

MAKE_BASE=TRUE

A

8

76

JTAG Scan Chain

6

1

SYNC_DATE=07/11/2008

REV.

OF

98

A

B

SYNC_MASTER=BEN_K20

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

5

4

3

2

SCALE

NONE

051-8071

SHT

87

www.vinafix.vn

Functional Test Points

J5650 (LEFT FAN CONN)

FUNC_TEST

TRUE

TRUE

TRUE

=PP5V_S0_FAN_LT

FAN_LT_PWM
FAN_LT_TACH

8

48

48

48

J5660 (RIGHT FAN CONN)

TRUE

D

TRUE

TRUE

FAN_RT_PWM
FAN_RT_TACH
GND

48

48

J6780 (MIC CONN)

BI_MIC_LO

TRUE

I557

I558

I559

TRUE

TRUE

BI_MIC_SHIELD
BI_MIC_HI

57 58

57 58

57 58

J6781 (LEFT SPEAKER)

I985

I987

I986

I988

TRUE

TRUE

TRUE

TRUE

SPKRAMP_L1_OUT_N
SPKRAMP_L2_OUT_P
SPKRAMP_L2_OUT_N

56 57 96

56 57 96

56 57 96

56 57 96

SPKRAMP_L1_OUT_P

J6782 (RIGHT & SUB SPEAKER)

SPKRAMP_LFE_OUT_P

TRUE

I989

I990

I992

I991

I994

I993

C

TRUE

I1296

TRUE

I995

TRUE

I996

TRUE

I997

TRUE

I998

TRUE

I1000

TRUE

I1001

TRUE

I1002

TRUE

I1004

TRUE

I1003

TRUE

I1005

TRUE

I1007

TRUE

I1006

TRUE

I1009

TRUE

I1008

TRUE

I1010

TRUE

I1011

TRUE

I1012

TRUE

I1014

TRUE

I1013

TRUE

I1015

TRUE

I1016

TRUE

I1017

TRUE

I1018

TRUE

B

I1019

I1020

I1022

I1021

TRUE

TRUE

TRUE

TRUE

SPKRAMP_LFE_OUT_N

TRUE

SPKRAMP_R1_OUT_P

TRUE

SPKRAMP_R1_OUT_N

TRUE

SPKRAMP_R2_OUT_P

TRUE

SPKRAMP_R2_OUT_N

TRUE

J9000 (LVDS CONN)

BKL_SYNC
PP3V3_SW_LCD
=PP3V3_S0_DDC_LCD
PPVOUT_S0_LCDBKLT
LVDS_DDC_CLK
LVDS_DDC_DATA
LVDS_CONN_A_DATA_P<0>
LVDS_CONN_A_DATA_N<0>
LVDS_CONN_A_DATA_P<1>
LVDS_CONN_A_DATA_N<1>
LVDS_CONN_A_DATA_P<2>
LVDS_CONN_A_DATA_N<2>
LVDS_CONN_A_CLK_F_P
LVDS_CONN_A_CLK_F_N
LVDS_CONN_B_DATA_P<0>
LVDS_CONN_B_DATA_N<0>
LVDS_CONN_B_DATA_P<1>
LVDS_CONN_B_DATA_N<1>
LVDS_CONN_B_DATA_P<2>
LVDS_CONN_B_DATA_N<2>
LVDS_CONN_B_CLK_F_P
LVDS_CONN_B_CLK_F_N
LED_RETURN_1
LED_RETURN_2
LED_RETURN_3
LED_RETURN_4
LED_RETURN_5
LED_RETURN_6

GND

78 85

78

8

75 78

78 85

78 81

78 81

78 81 95

78 81 95

78 81 95

78 81 95

78 81 95

78 81 95

78 95

78 95

78 81 95

78 81 95

78 81 95

78 81 95

78 81 95

78 81 95

78 95

78 95

78 85

78 85

78 85

78 85

78 85

78 85

56 57 96

56 57 96

56 57 96

56 57 96

56 57 96

56 57 96

J4500 (SATA ODD CONN)

I1024

I1026

I1025

I1028

I1027

I1029

TRUE

SMC_ODD_DETECT

TRUE

SATA_ODD_D2R_C_P

TRUE

SATA_ODD_D2R_C_N

TRUE

SATA_ODD_R2D_P

TRUE

SATA_ODD_R2D_N

TRUE

TRUE

GND

38

38 41

38 90

38 90

38 90

38 90

PP5V_SW_ODD

J4501 (SATA HDD CONN)

PP5V_S0_HDD_FLT

TRUE

I1032

I1031

I1033

I1035

I1034

A

I1145

I1146

SATA_HDD_R2D_P

TRUE

SATA_HDD_R2D_N

TRUE

SATA_HDD_D2R_C_N

TRUE

SATA_HDD_D2R_C_P

TRUE

TRUE

J5815 (KBD BACKLIGHT CONN)

TRUE

TRUE

TRUE

FUNC_TEST

TRUE

GND

KBDLED_ANODE
SMC_KDBLED_PRESENT_L

GND

GND

6 TPs

TRUE

GND

38

38 90

38 90

38 90

38 90

50

50

3 TPs
per Fan

5 TPs
per Fan

2 TP needed

4 TPs

3 TPs

5 TPs

TRUE

I1038

TRUE

I1039

TRUE

I1040

TRUE

TRUE

I1042

TRUE

I1043

TRUE

I1044

TRUE

TRUE

I1046

TRUE

I1047

TRUE

I1048

TRUE

J3401 (AIRPORT/BT/CAMERA CONN)

TRUE

I1051

TRUE

I1050

TRUE

I1053

TRUE

I1052

TRUE

I1054

TRUE

I1056

TRUE

I1055

TRUE

I1058

TRUE

I1057

TRUE

I1059

TRUE

I1061

TRUE

I1060

TRUE

I1063

TRUE

I1062

TRUE

I1064

TRUE

I1066

TRUE

I1065

J3500 (EXPRESS CARD CONN)

TRUE

I1067

TRUE

I1068

TRUE

I1069

TRUE

I1071

TRUE

I1070

TRUE

I1072

TRUE

I1074

TRUE

I1073

TRUE

I1075

TRUE

I1076

TRUE

I1077

TRUE

I1079

TRUE

I1078

TRUE

I1081

TRUE

I1080

TRUE

I1082

TRUE

I1083

TRUE

I1084

J5800 (IPD FLEX CONN)

TRUE

I1085

TRUE

I1086

TRUE

I1087

TRUE

I1273

TRUE

I1089

TRUE

I1088

TRUE

I1090

TRUE

I1091

TRUE

I1098

TRUE

I1097

TRUE

I1095

TRUE

I1096

TRUE

I1092

TRUE

I1093

TRUE

I1094

TRUE

I1099

TRUE

I1100

TRUE

I1101

J6900 (DC POWER CONN)

TRUE

I1131

TRUE

I1132

TRUE

J6950 (MAIN BATT CONN)

TRUE

I1134

TRUE

I1136

TRUE

I1135

TRUE

I1137

TRUE

J6995 (BAT LED CONN)

TRUE

I1140

TRUE

I1142

TRUE

I1141

TRUE

I1143

TRUE

USB PORTS

PP5V_S3_RTUSB_A_F
USB2_LT1_N
USB2_LT1_P

GND

PP5V_S3_RTUSB_B_F
USB_LT2_N
USB_LT2_P

GND

PP5V_S3_RTUSB_C_F
USB_LT3_N
USB_LT3_P

GND

PCIE_MINI_D2R_P
PCIE_MINI_D2R_N
PCIE_MINI_R2D_P
PCIE_MINI_R2D_N
PCIE_CLK100M_MINI_CONN_P
PCIE_CLK100M_MINI_CONN_N
MINI_CLKREQ_Q_L
PCIE_WAKE_L
MINI_RESET_CONN_L
PP5V_WLAN
PP5V_S3_BTCAMERA_F
SMBUS_SMC_A_S3_SDA
SMBUS_SMC_A_S3_SCL
USB_CAMERA_CONN_P
USB_CAMERA_CONN_N
CONN_USB2_BT_P
CONN_USB2_BT_N

PP1V5_S0_EXCARD_SWITCH
PCIE_WAKE_L
SMBUS_MCP_0_CLK
SMBUS_MCP_0_DATA
PP3V3_S0_EXCARD_SWITCH
PP3V3_S3_EXCARD_SWITCH
USB2_EXCARD_CONN_N
USB2_EXCARD_CONN_P
EXCARD_CPUSB_L
EXCARD_CLKREQ_CONN_L
EXCARD_CPPE_L
PLT_RESET_SWITCH_L
PCIE_EXCARD_D2R_P
PCIE_EXCARD_D2R_N
PCIE_EXCARD_R2D_P
PCIE_EXCARD_R2D_N
PCIE_CLK100M_EXCARD_CONN_P
PCIE_CLK100M_EXCARD_CONN_N

PP3V3_S3_LDO
PP18V5_S3
TPAD_GND_F
Z2_CS_L
Z2_DEBUG3
Z2_MISO
Z2_BOOST_EN
Z2_BOOT_CFG1
Z2_CLKIN
Z2_KEY_ACT_L
Z2_RESET
PSOC_F_CS_L
PICKB_L
PSOC_MISO
PSOC_MOSI
PSOC_SCLK
SMBUS_SMC_A_S3_SCL
SMBUS_SMC_A_S3_SDA

ADAPTER_SENSE
PP18V5_DCIN_FUSE

GND

PPVBAT_G3H_CONN_F
SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SDA
SMC_BS_ALRT_L

GND

PP3V42_G3H
SMBUS_SMC_BSA_SDA
SMBUS_SMC_BSA_SCL
SMC_BIL_BUTTON_DB_L

GND

6

39

39 96

39 96

39

39 96

39 96

98

96 98

96 98

17 30 90

17 30 90

30 90

30 96

30 96

30

7

17 30 31

30

30

30

7

44 94

7

44 94

30 96

30 96

30 96

30 96

31

7

17 30 31

13 21 44 91

13 21 44 91

31

31

31 96

31 96

31

31

31

31

17 31 90

17 31 90

31 90

31 90

31 96

31 96

50

7

50

50

49 50

49 50

49 50

50

49 50

49 50

49 50

49 50

49 50

49 50

49 50

49 50

49 50

7

44 94

7

44 94

59

59

59

7

44 94

7

44 94

41 42 59

7 8

42

7

44 94

7

44 94

42 59

J5713 (KEY BOARD CONN)

PP3V3_S3

TRUE

I1103

I1102

I1104

I1105

I1107

I1106

I1108

I1109

I1110

I1111

I1112

I1113

I1114

I1115

I1117

I1116

I1118

I1119

I1120

I1122

I1121

I1123

I1124

I1125

I1127

I1126

I1128

I1129

I1130

PP3V42_G3H

TRUE

WS_KBD1

TRUE

WS_KBD2

TRUE

WS_KBD3

TRUE

WS_KBD4

TRUE

WS_KBD5

TRUE

WS_KBD6

TRUE

WS_KBD7

TRUE

WS_KBD8

TRUE

WS_KBD9

TRUE

WS_KBD10

TRUE

WS_KBD11

TRUE

WS_KBD12

TRUE

WS_KBD13

TRUE

WS_KBD14

TRUE

WS_KBD15_CAP

TRUE

WS_KBD16_NUM

TRUE

WS_KBD17

TRUE

WS_KBD18

TRUE

WS_KBD19

TRUE

WS_KBD20

TRUE

WS_KBD21

TRUE

WS_KBD22

TRUE

WS_KBD23

TRUE

WS_KBD_ONOFF_L

TRUE

WS_LEFT_SHIFT_KBD

TRUE

WS_LEFT_OPTION_KBD

TRUE

WS_CONTROL_KBD

TRUE

J4800 (FRONT CABLE CONN)

I1148

I1150

I1149

I1151

I1152

TRUE

TRUE

TRUE

TRUE

TRUE

PP5V_S3_IR_R
SMC_LID_R
IR_RX_OUT
SYS_LED_ANODE

PP3V42_G3H_LIDSWITCH_R

TRUE

J5502 (SENSOR CONN)

MCPTHMSNS_D_P

TRUE

I1154

I1155

I640

I602

I603

I604

I605

I607

I606

I608

I610

I612

I611

I613

I600

I625

I624

I623

I622

I620

I621

I618

I617

I615

I616

I614

I627

I626

I639

I638

I637

I636

I709

I714

I1156

I1157

I1159

I1160

I1161

TRUE

FUNC_TEST

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

MCPTHMSNS_D_N

POWER RAILS

PM_SLP_S3_L

PPBUS_G3H
PPBUS_CPU_IMVP_ISNS
PP3V42_G3H
PP5V_S3
PP5V_S0
PPVCORE_S0_CPU

PPVCORE_S0_MCP

PP3V3_S5
PP3V3_S3
PP3V3_S0

PP2V5_S0
PP1V2_S0

PP1V8_S0

PP1V8R1V5_S3

PP1V8R1V5_S0

PPMCPDDR_ISNS

PP1V05_S0

PP1V2R1V05_S5

PPCPUVTT_S0

PP0V9R0V75_S0_DDRVTT

PP1V2R1V05_ENET
PP3V3_ENET_PHY

PPVP_FW
PP1V0_FW
PP3V3_S0GPU

PP1V1_S0GPU

PP1V8_S0GPU_ISNS
PPVCORE_GPU
PP1V8_S0GPU_ISNS_R

PP3V3_S5_AVREF_SMC

PP18V5_S3

PPDCIN_G3H
PPVCORE_S0_MCP
PPMCPDDR_ISNS

PPVTTDDR_S3
PP1V8_GPUIFPX

GND

8

8

7 8

8

8

8

7 8

8

7 8

8 9

8

8

8

8

8

7 8

8

8

8

8

8

8

8

8

8

8

8

8

8

41 42

7

8

7 8

7 8

8

8

5

FUNC_TEST

SYS_LED_ANODE_R

I720

I722

I724

I723

I725

I726

I727

I729

I728

I730

I732

I731

I734

I733

I735

I736

I737

I739

I738

I740

I741

I742

I743

I744

I751

I752

I756

I1286

I1290

I1291

I1292

I1293

I1294

I1288

TRUE

LPC_CLK33M_LPCPLUS

TRUE

LPC_AD<0..3>

TRUE

SPI_ALT_MOSI

TRUE

SPI_ALT_MISO

TRUE

LPC_FRAME_L

TRUE

PM_CLKRUN_L

TRUE

SMC_TMS

TRUE

DEBUG_RESET_L

TRUE

SMC_TDO

TRUE

SMC_TRST_L

TRUE

SMC_MD1

TRUE

SMC_TX_L

TRUE

SPIROM_USE_MLB

TRUE

SPI_ALT_CLK

TRUE

SPI_ALT_CS_L

TRUE

LPC_SERIRQ

TRUE

LPC_PWRDWN_L

TRUE

SMC_TDI

TRUE

SMC_TCK

TRUE

SMC_RESET_L

TRUE

SMC_NMI

TRUE

SMC_RX_L

TRUE

LPCPLUS_GPIO

TRUE

ISSP_SCLK_P1_1

TRUE

ISSP_SDATA_P1_0

TRUE

SMC_ONOFF_L

TRUE

PM_SYSRST_L

TRUE

BKL_FB

TRUE

BKL_GD

TRUE

BKL_SW

TRUE

BKLT_EN

TRUE

BKL_SCL

TRUE

BKL_SDA

TRUE

LCD_BKLT_PWM

TRUE

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

17

17

17

17

17

17

17

17

69

49

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

21

42

20

20

20

9

9

9

9

13

13

7 8

7 8

42

49

49

49

49

49

49

49

49

49

49

49

49

49

49

49

49

49

49

49

49

49 30 90

49

49

49

49

49

49

40

40

40

40

40 42

47 96

47 96

67 82 84 21 33 36 41

45

42

96

96

50

4

40

25 43 91

19 41 43 84 91

43

43

19 41 43 84 91

19 41 43

41 42 43

25 43

41 42 43

41 43

41 43

39 41 42 43

43

43

43

19 41 43

19 41 43

41 42 43

41 42 43

41 42 43

41 43

39 41 42 43

18 43

49

49

41 42 49

25 41

85

84 85

TP_PCI_AD<31..8>
TP_PCI_C_BE_L<3..0>
TP_PCI_CLK0
TP_PCI_CLK1
TP_PCI_DEVSEL_L
TP_PCI_FRAME_L
TP_PCI_GNT0_L
TP_PCI_GNT1_L
TP_PCI_INTW_L
TP_PCI_INTX_L
TP_PCI_INTY_L
TP_PCI_INTZ_L
TP_PCI_IRDY_L
TP_PCI_PAR
TP_PCI_PERR_L
TP_PCI_RESET1_L
TP_PCI_SERR_L
TP_PCI_STOP_L
TP_PCI_TRDY_L
TP_PCIE_CLK100M_PE4P
TP_PCIE_CLK100M_PE5N
TP_PCIE_CLK100M_PE5P
TP_PCIE_CLK100M_PE6N
TP_PCIE_CLK100M_PE6P
TP_PCIE_PE4_D2RN
TP_PCIE_PE4_D2RP
TP_PE4_CLKREQ_L
TP_PEX_CLKREQ_L
TP_PSOC_P1_3
TP_SATA_C_D2RN
TP_SATA_C_D2RP
TP_SATA_C_R2D_CN
TP_SATA_C_R2D_CP
TP_SATA_D_D2RN
TP_SATA_D_D2RP
TP_SATA_D_R2D_CN
TP_SATA_D_R2D_CP
TP_SATA_E_D2RN
TP_SATA_E_D2RP
TP_SATA_E_R2D_CN
TP_SATA_E_R2D_CP
TP_SATA_F_D2RN
TP_SATA_F_D2RP
TP_SATA_F_R2D_CN
TP_SATA_F_R2D_CP
TP_SB_A20GATE
TP_SMC_P41
TP_USB_10P
TP_USB_11N
TP_USB_11P
TP_USB_EXTDN
TP_USB_EXTDP
TP_USB_MININ

TP_USB_MINIP
TP_XDP_OBSDATA_B2
TP_XDP_OBSDATA_B3

ICT Test Points

CPU FSB NO_TESTs

I1281

I1280

I1282

I1283

I1284

I1285

I982

I981

I1274

I1275

I1276

I1277

NO_TEST

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

FB NO_TESTs

NO_TEST

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

LVDS NO_TESTs

NO_TEST

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

NC NO_TESTs

NO_TEST

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

FSB_A_L<31..3>
FSB_ADS_L
FSB_ADSTB_L<1..0>
FSB_D_L<63..0>
FSB_DBSY_L
FSB_DINV_L<3..0>
FSB_DRDY_L
FSB_DSTB_L_N<3..0>
FSB_DSTB_L_P<3..0>
FSB_HIT_L
FSB_HITM_L
FSB_LOCK_L
FSB_REQ_L<4..0>

FB_A_DQ<63..0>
FB_B_DQ<63..0>
FB_B_BA<1>
FB_B_CAS_L
FB_B_CS0_L
FB_B_MA<11>

LVDS_A_DATA_N<0>
LVDS_A_DATA_P<0>
LVDS_B_CLK_P
LVDS_B_DATA_N<0>
LVDS_B_DATA_P<0>
LVDS_EG_A_DATA_N<2>

NC_PCI_AD<31..8>
NC_PCI_C_BE_L<3..0>
NC_PCI_CLK0
NC_PCI_CLK1
NC_PCI_DEVSEL_L
NC_PCI_FRAME_L
NC_PCI_GNT0_L
NC_PCI_GNT1_L
NC_PCI_INTW_L
NC_PCI_INTX_L
NC_PCI_INTY_L
NC_PCI_INTZ_L
NC_PCI_IRDY_L
NC_PCI_PAR
NC_PCI_PERR_L
NC_PCI_RESET1_L
NC_PCI_SERR_L
NC_PCI_STOP_L
NC_PCI_TRDY_L
NC_PCIE_CLK100M_PE4P
NC_PCIE_CLK100M_PE5N
NC_PCIE_CLK100M_PE5P
NC_PCIE_CLK100M_PE6N
NC_PCIE_CLK100M_PE6P
NC_PCIE_PE4_D2RN
NC_PCIE_PE4_D2RP
NC_PE4_CLKREQ_L
NC_PEX_CLKREQ_L
NC_PSOC_P1_3
NC_SATA_C_D2RN
NC_SATA_C_D2RP
NC_SATA_C_R2D_CN
NC_SATA_C_R2D_CP
NC_SATA_D_D2RN
NC_SATA_D_D2RP
NC_SATA_D_R2D_CN
NC_SATA_D_R2D_CP
NC_SATA_E_D2RN
NC_SATA_E_D2RP
NC_SATA_E_R2D_CN
NC_SATA_E_R2D_CP
NC_SATA_F_D2RN
NC_SATA_F_D2RP
NC_SATA_F_R2D_CN
NC_SATA_F_R2D_CP
NC_SB_A20GATE
NC_SMC_P41
NC_USB_10P
NC_USB_11N
NC_USB_11P
NC_USB_EXTDN
NC_USB_EXTDP
NC_USB_MININ

NC_USB_MINIP
NC_XDP_OBSDATA_B2
NC_XDP_OBSDATA_B3

3

10 14 88

10 14 88

10 14 88

10 14 88

10 14 88

10 14 88

10 14 88

10 14 88

10 14 88

10 14 88

10 14 88

10 14 88

10 14 88

71 72 79 95

71 73 80 95

71 73 80 95

71 73 80 95

71 73 95

71 73 80 95

81 84 95

81 84 95

81 84 95

81 84 95

81 84 95

76 84 95

NC NO_TESTs

I1297

I761

I762

I763

I764

I765

I767

I766

I769

I768

I770

I772

I771

I774

NO_TEST

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

NC_SMC_FAN_3_TACH
NC_SMC_FAN_3_CTL
NC_SMC_FAN_2_TACH
NC_SMC_FAN_2_CTL
NC_FW2_TPBP
NC_FW2_TPBN
NC_FW2_TPBIAS
NC_FW2_TPAP
NC_FW2_TPAN
NC_FW0_TPBP
NC_FW0_TPBN
NC_FW0_TPAP
NC_ESTARLDO_EN
NC_ALS_GAIN

NC NO_TESTs

TP_CPU_PECI_MCP

9

TP_CPU_TEST3

10

TP_ENET_INTR_L

18

TP_ENET_PWRDWN_L

18

TP_FW643_AVREG

35

TP_FW643_TDI

35

TP_MEM_A_A<15>

9

TP_MEM_A_CKE<2>

16

TP_MEM_A_CKE<3>

16

TP_MEM_A_CLK2N

15

15

TP_MEM_A_CLK3N

16

TP_MEM_A_CLK3P

16

TP_MEM_A_CLK4N

16

TP_MEM_A_CLK4P

16

TP_MEM_A_CLK5N

16

TP_MEM_A_CLK5P

16

TP_MEM_A_CS_L<2>

16

TP_MEM_A_CS_L<3>

16

TP_MEM_A_ODT<2>

16

TP_MEM_A_ODT<3>

16

TP_MEM_B_A<15>

9

TP_MEM_B_CKE<2>

16

TP_MEM_B_CLK2P

15

TP_MEM_B_CLK3N

16

TP_MEM_B_CLK3P

16

TP_MEM_B_CLK4N

16

TP_MEM_B_CLK4P

16

TP_MEM_B_CLK5N

16

TP_MEM_B_CLK5P

16

TP_MEM_B_CS_L<2>

16

TP_MEM_B_CS_L<3>

16

TP_MEM_B_ODT<2>

16

TP_MEM_B_ODT<3>

16

TP_MLB_RAM_SIZE

21

TP_MLB_RAM_VENDOR

21

TP_GPU_BUFRST_L

74

TP_GPU_GSTATE<0>

75

TP_GPU_GSTATE<1>

75

TP_GPU_MIOA_D<9..0>

75

TP_GPU_MIOA_DE

75

TP_GPU_PGOOD_OUT_L NC_GPU_PGOOD_OUT_L

74

TP_GPU_VCORE_VID3

75

TP_LPC_DRQ0_L

19

TP_LVDS_EG_B_CLK_N

75

TP_LVDS_EG_B_CLK_P

75

TP_LVDS_EG_BKL_PWM

75

TP_LVDS_IG_B_CLKN

9

TP_LVDS_IG_B_CLKP

9

TP_LVDS_IG_BKL_PWM

9

TP_MCP_BUF_SIO_CLK

21

TP_MCP_GPIO_18

17

TP_MCP_KBDRSTIN_L

21

TP_MCP_SATALED_L NC_MCP_SATALED_L

20

21

D

42

42

42

42

37

37

37

37

37

37

37

37

42

42

NO_TEST

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

SYNC_MASTER=K20_MLB

APPLE INC.

NC_CPU_PECI_MCP
NC_CPU_TEST3
NC_ENET_INTR_L
NC_ENET_PWRDWN_L
NC_FW643_AVREG
NC_FW643_TDI
NC_MEM_A_A<15>
NC_MEM_A_CKE<2>
NC_MEM_A_CKE<3>
NC_MEM_A_CLK2N
NC_MEM_A_CLK2PTP_MEM_A_CLK2P
NC_MEM_A_CLK3N
NC_MEM_A_CLK3P
NC_MEM_A_CLK4N
NC_MEM_A_CLK4P
NC_MEM_A_CLK5N
NC_MEM_A_CLK5P
NC_MEM_A_CS_L<2>
NC_MEM_A_CS_L<3>
NC_MEM_A_ODT<2>
NC_MEM_A_ODT<3>
NC_MEM_B_A<15>
NC_MEM_B_CKE<2>
NC_MEM_B_CLK2P
NC_MEM_B_CLK3N
NC_MEM_B_CLK3P
NC_MEM_B_CLK4N
NC_MEM_B_CLK4P
NC_MEM_B_CLK5N
NC_MEM_B_CLK5P
NC_MEM_B_CS_L<2>
NC_MEM_B_CS_L<3>
NC_MEM_B_ODT<2>
NC_MEM_B_ODT<3>
NC_MLB_RAM_SIZE
NC_MLB_RAM_VENDOR
NC_GPU_BUFRST_L
NC_GPU_GSTATE<0>
NC_GPU_GSTATE<1>
NC_GPU_MIOA_D<9..0>
NC_GPU_MIOA_DE

NC_GPU_VCORE_VID3
NC_LPC_DRQ0_L
NC_LVDS_EG_B_CLK_N
NC_LVDS_EG_B_CLK_P
NC_LVDS_EG_BKL_PWM
NC_LVDS_IG_B_CLKN
NC_LVDS_IG_B_CLKP
NC_LVDS_IG_BKL_PWM
NC_MCP_BUF_SIO_CLK
NC_MCP_GPIO_18
NC_MCP_KBDRSTIN_L

Functional / ICT Test

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

SHT

051-8071

7

SYNC_DATE=09/24/2008

REV.

B

OF

98

C

B

A

8

76

5

4

3

2

1

87

www.vinafix.vn

=PPBUS_G3H

60

D

=PPVIN_S5_CPU_IMVP_ISNS

45

=PP18V5_DCIN_CONN

59

=PP3V42_G3H_REG

59

C

=PP5V_S3_REG

62

B

=PP5V_S0_REG

64

=PPVCORE_S0_CPU_REG

61

A

=PPMCPCORE_S0_REG

64 87

"G3Hot" (Always-Present) Rails

PPBUS_G3H

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=6V
MAKE_BASE=TRUE

=PPVIN_S5_P5VP3V3

=PPVIN_S0_CPUVTTS0

=PPBUS_S0_LCDBKLT

=PPVIN_GPU_GPUVCORE

=PPVIN_S5_CPU_IMVP_ISNS_R
=PPVIN_S0_P5VRTS0_MCPCORE

=PPVIN_S3_DDRREG

=PPVIN_S0GPU_P1V8P1V1

=PPVBAT_G3H_P3V42G3H
=PPVIN_S0_P1V05S5
=PPVIN_PBUS_KBDLED

=PPVIN_S5_FWPWRSW

=PPVIN_S5_BKL

PPBUS_CPU_IMVP_ISNS

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=6V
MAKE_BASE=TRUE

=PPVIN_S5_CPU_IMVP

PPDCIN_G3H

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=18.5V
MAKE_BASE=TRUE

=PPDCIN_S5_CHGR

PP3V42_G3H

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.42V
MAKE_BASE=TRUE

=PP3V42_G3H_SMCUSBMUX
=PP3V42_G3H_SMBUS_SMC_BSA
=PP3V42_G3H_LIDSWITCH
=PP3V3_S5_SMC
=PP3V3_S5_LPCPLUS
=PPVIN_S5_SMCVREF
=PP3V42_G3H_PWRCTL

=PP3V42_G3H_CHGR

=PP3V3_S5_RTC_D

=PP3V42_G3H_BATT

=PP3V42_G3H_TPAD
=PP3V42_G3H_BMON_ISNS

=PP3V42_G3H_CPUCOREISNS

5V Rails

PP5V_S3

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V
MAKE_BASE=TRUE

=PP5V_S3_SYSLED

=PP5V_S3_BTCAMERA

=PP5V_S3_WLAN
=PP5V_S3_IR

=PP5V_S3_DDRREG

=PP5V_S3_GPUVCORE
=PP5V_S3_RTUSB

=PP5V_S3_TPAD

=PP5V_S3_P1V05S0FET

=PP5V_S3_MCPDDRFET
=PP5V_S3_VTTCLAMP

=PP5V_S3_AUDIO_PWR

PP5V_S0

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=5V
MAKE_BASE=TRUE

=PP5V_S0_FAN_LT
=PP5V_S0_FAN_RT
=PP5V_S0_CPU_IMVP

=PP5V_S0_CPUVTTS0

=PP5V_S0GPU_P1V1P1V8_GPU
=PP5V_S0_LPCPLUS
=PP5V_S0_ODD

=PP5V_S0_HDD

=PPVIN_PP5V_KBDLED

Chipset "VCore" Rails

PPVCORE_S0_CPU

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=1.25V
MAKE_BASE=TRUE

=PPVCORE_S0_CPU

PPVCORE_S0_MCP

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE

=PPVCORE_S0_MCP

11 12 45

22 23 45

7

45

62

65

86

77

45

64

63

83

59

66

9

36

7

61

7

60

7

39

44

40

41 42 51

43

42

67

60

25

59

49

45

45

7

42

30

30

40

63

77

39 98

50

68

68

68

9

7

7

48

61

65

83

43

38

38

9

7

7

42

48

=PP3V3_S5_REG

62

=PP3V3_S3_FET

68

=PP3V3_S0_FET

68

=PP2V5_S0_REG

87

=PP1V2_S0_REG

6

3.3V-2.5V Rails

PP3V3_S5

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
MAKE_BASE=TRUE

=PP3V3_S5_ROM
=PP3V3_S5_MEMRESET
=PP3V3_S3_P3V3S3FET
=PP3V3_S0_LCD
=PP3V3_S0_P3V3S0FET
=PP3V3_GPU_P3V3GPUFET
=PP3V3_S5_PWRCTL

=PP3V3_S5_P1V05FET

=PP3V3_S5_MCP

=PP3V3_S5_MCP_GPIO

=PP3V3_FW_LATEVG_ACTIVE

=PP3V3_S5_MCPPWRGD

=PP3V3_FW_LATEVG
=PP3V3_S5_P1V05ENETFET
=PP3V3_S5_P3V3ENETFET
=PP3V3_S5_DP_PORT_PWR

PP3V3_S3

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V
MAKE_BASE=TRUE

=PP3V3_S3_GMUX
=PP3V3_S3_BT

=PP3V3_S3_P1V8S0
=PP3V3_S3_SMBUS_SMC_A_S3
=PP3V3_S3_SMS

=PP3V3_S3_TPAD

=PP3V3_S3_SMS

=PP3V3_S3_WLAN
=PP3V3_S3_MCP_GPIO

=PP3V3_S3_VREFMRGN

=PP3V3_S3_SMBUS_SMC_MGMT

=PP3V3_S3_EXCARD

=PP3V3_S3_P1V5EXPS0

PP3V3_S0

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V
MAKE_BASE=TRUE

=PP3V3_S0_LPCPLUS
=PP3V3_S0_SMC
=PP3V3_S0_SMBUS_SMC_B_S0

=PP3V3_S0_MCPDDRISNS

=PP3V3_S0_GPU1V8ISNS
=PP3V3_S0_CPUTHMSNS
=PP3V3_S0_GPUTHMSNS
=PP3V3_S0_FAN_LT
=PP3V3_S0_FAN_RT
=PP3V3_S0_IMVP
=PP3V3_S0_PWRCTL
=PP3V3_S0_DDC_LCD
=PP3V3_S0_XDP

=PP3V3_S0_MCPCOREISNS

=PP3V3_S0_XDP

=PPSPD_S0_MEM_A

=PPSPD_S0_MEM_B

=PP3V3_S0_SMBUS_MCP_0

=PP3V3_S0_GMUX

=PP3V3_S0_DPMUX

=PP3V3_S0_DPCONN

=PP3V3_S0_P1V2P2V5

=PP3V3_S0_MCP_GPIO

=PP3V3_S0_HDCPROM

=PP3V3R1V5_S0_MCP_HDA

=PP3V3_S0_MCP_PLL_UF

=PP3V3_S0_MCP_VPLL_UF

=PP3V3_S0_MCP_DAC_UF

=PP3V3_S0_MCP

=PP3V3_S0_AUDIO

=PP3V3_S0_ODD

=PP3V3_S0_VMON

=PP3V3_S0_SMBUS_MCP_1

=PP3V3_S0_REMTHMSNS
=PP3V3_S0_EXCARD
=PP3V3_S0_LVDSDDCMUX

=PP3V3_S0_BATTCHARGERTMPSNSR

=PP3V3_GPU_SMBUS_SMC_0_S0

=PP3V3_S0_TPAD
=PP3V3_S0_MCP_PLL_VLDO

=PP3V3_FW_FWPHY

=PP3V3_FW_P1V0FW

PP2V5_S0

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=2.5V
MAKE_BASE=TRUE

=PP2V5_S0_GMUX

PP1V2_S0

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.2V
MAKE_BASE=TRUE

=PP1V2_S0_GMUX

5

=PP1V8_S0_REG

66

7

96

500 mA max supply

43 52

29

68

=PPDDR_S3_REG

78

63

68

68

67

68

22 23

18 20

36

25

=PP1V8R1V5_S0_FET

68

37

33

33

82

7

84

30

66

44

8

51

49

8

51

30

21

26

44

31

66

7 9

96

43

42

44

46

46

47

47

48

48

61

67

7

75 78

6 8

13

46

6 8

13

27

28

44

84

81

82

87

18 19 21

24

21 23

23

24

24

21 22 23

53 57 58

38

67

44

47

31

81

47

44

50

66

35 37

66

7

84

7

84

=PP1V5_EXP_S0

38 66

=PP1V8R1V5_S0_MCP_MEM

16 23

=PP1V05_S0_FET

66 68

1034 mA

PP1V05_S0_MCP_PLL_UF

MAKE_BASE=TRUE

=PP1V05_S0_MCP_PEX_DVDD

8

23

PP1V05_S0_MCP_PEX_AVDD

23

=PP1V05_S0_MCP_SATA_DVDD

8

23

PP1V05_S0_MCP_SATA_AVDD

MAKE_BASE=TRUE

=PP1V05_S5_MCP

66

241 mA max load

=PPCPUVTT_S0_REG

65

5300 mA

=PPVTT_S3_DDR_BUF

26 63

=PPVTT_S0_DDR_LDO

63

=PP1V05_ENET_FET

33

=PP3V3_ENET_FET

33

MAKE_BASE=TRUE

4

1.8V/DDR 1.5V Rails

190 mA

4771 mA

130 mA

500 mA

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

105 mA/241 mA

139 mA/ 0 mA

4500 mA

1182 mA

ENET Rails

PP3V3_ENET_PHY

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
MAKE_BASE=TRUE

PP1V8_S0

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.8V
MAKE_BASE=TRUE

=PP3V3R1V8_S0_MCP_IFP_VDD

=PP1V8_S0_MCP_PLL_VLDO

PP1V8R1V5_S3

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.5V
MAKE_BASE=TRUE

=PP1V8R1V5_S0_MCP_FET

=PPVIN_S0_DDRREG_LDO

=PP1V5_S3_MEM_A

=PP1V5_S3_MEM_B

=PP1V5_S3_MEMRESET

PP1V8R1V5_S0

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.5V
MAKE_BASE=TRUE

=PPMCPDDR_ISNS_R

=PP1V5_S0_CPU

=PP1V5_S0_VMON

PP1V5_EXP_S0

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.5V
MAKE_BASE=TRUE

=PP1V5_S0_EXCARD

PPMCPDDR_ISNS

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.5V
MAKE_BASE=TRUE

=PP1V5_S0_MEM_A

=PP1V5_S0_MEM_B

=PPMCPDDR_ISNS

PP1V05_S0

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE

=PP1V05_S0_MCP_AVDD_UF

=PP1V05_S0_MCP_PEX_DVDD

=PP1V05_S0_MCP_SATA_DVDD

=PP1V05_S0_MCP_HDMI_VDD

=PP1V05_S0_VMON

=PP1V05_S0_MCP_PLL_PEX_UF

=PP1V05_S0_MCP_PLL_UF

=PP1V05_S0_MCP_PEX_DVDD0

=PP1V05_S0_MCP_PEX_DVDD1

=PP1V05_S0_MCP_PEX_AVDD0

=PP1V05_S0_MCP_PEX_AVDD1

=PP1V05_S0_MCP_SATA_DVDD0

=PP1V05_S0_MCP_SATA_AVDD0

PP1V2R1V05_S5

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE

=PP1V05_S5_MCP_VDD_AUXC

=PP1V05_ENET_P1V05ENETFET

=PP1V05_S5_P1V05S0FET

PPCPUVTT_S0

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE

=PP1V05_S0_CPU

=PP1V05_S0_SMC_LS

=PP1V05_S0_MCP_FSB

PPVTTDDR_S3

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0.75V
MAKE_BASE=TRUE

PP0V9R0V75_S0_DDRVTT

MIN_LINE_WIDTH=2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.9V
MAKE_BASE=TRUE

=PP0V75_S0_MEM_VTT_A

=PP0V75_S0_MEM_VTT_B

=PPVTT_S0_VTTCLAMP

PP1V2R1V05_ENET

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE

=PP1V05_ENET_MCP_PLL_MAC

=PP1V05_ENET_MCP_RMGT
=PP1V05_ENET_PHY

=PP3V3_ENET_MCP_RMGT

=PP3V3_ENET_PHY

OR 0.75V

(1.1V for A01)

3

7

18 24

66

7

7

18 23

32

7

27

28

68

23

18 23

32

7

68

63

27

28

29

7

46

11 12

67

7

31

7

27

28

46

7

23

8

23

8

23

18 24

67

23

23 66

17

17

17

17

20

20 23

7

22 23

33

68

7

6

10 11 12 13 61

42

9

14 22 23

=PPVOUT_FW_FWPWRSW

36

=PFWBOOST_REG

66

=PPBOOST_S5_FW_FET

36

=PP1V0_FW_REG

66

=PP3V3_S0GPU_FET

68

=PP1V1_S0GPU_REG

83

=PP1V8_GPUIFPX_REG

66

=PP1V8_S0GPU_ISNS

46

=PPVCORE_GPU_REG

45 77

=PP1V8_GPU_REG

83

21

"FW" (FireWire) Rails

PPBUS_FW_FWBOOST

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=6V
MAKE_BASE=TRUE

=PPVIN_PFWBOOST

PP10V_FW

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=10V
MAKE_BASE=TRUE

=PPBOOST_FW_FWPWRSW_F

PPVP_FW

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=10V
MAKE_BASE=TRUE

=PPVP_FW_PORT1
=PPVP_FW_PHY_CPS_FET

PP1V0_FW

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.0V
MAKE_BASE=TRUE

=PP1V0_FW_FWPHY

"GPU" Rails

PP3V3_S0GPU

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V
MAKE_BASE=TRUE

=PP3V3_GPU_VDD33
=PP3V3_GPU_MIO

=PP3V3_GPU_LVDS_DDC

=PP3V3_GPU_PWRCTL
=PP3V3_GPU_VCORELOGIC

=PP3V3_GPU_P1V8S0

PP1V1_S0GPU

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.1V
MAKE_BASE=TRUE

=PP1V1_GPU_PEX_IOVDDQ

=PP1V1_GPU_PEX_IOVDD

=PP1V1_GPU_PEX_PLLXVDD

=PP1V1_GPU_PLLVDD

=PP1V1_GPU_H_PLLVDD

=PP1V1_GPU_VID_PLLVDD

=PP1V1_GPU_FBPLLAVDD

=PP1V1_GPU_IFPCD_IOVDD

PP1V8_GPUIFPX

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.15 MM
VOLTAGE=1.8V
MAKE_BASE=TRUE

=PP1V8_GPU_IFPX

PP1V8_S0GPU_ISNS

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.8V
MAKE_BASE=TRUE

=PP1V8_GPU_FB_VDD
=PP1V8_GPU_FB_VDDQ
=PP1V8_GPU_FBVDDQ
=PP1V8_GPU_FBIO

PPVCORE_GPU

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.2V
MAKE_BASE=TRUE

=PPVCORE_GPU

PP1V8_S0GPU_ISNS_R

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.25V
MAKE_BASE=TRUE

=PP1V8_S0GPU_ISNS_R

Power Aliases

SYNC_MASTER=RXU_K20

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

D

NONE

DRAWING NUMBER

051-8071

SHT

66

36

7

37

37

7

35

7

6

74 75

74 75

81

67

77

66

7

69

69

69

74

74

74

71

76

7

76

7

72 73 79 80

9

72 73 79 80

70

71

7

70

7

46

SYNC_DATE=05/07/2008

OF

8

D

C

B

A

REV.

B

98

8

76

5

4

3

2

1

87

www.vinafix.vn

6

5

4

3

21

D

ZT0915

3R2P5

60 59

ZT0945

3R2P5

ZT0932

3R2P5

C

ZT0960

3R2P5

ZT0971

3R2P5

ZT0965

3R2P5

ZT0940

3R2P5

ZT0970

3R2P5

B

ZT0934

STDOFF-4.0OD3.0H-SM

STDOFF-4.5OD.98H-1.1-3.48-TH

STDOFF-4.5OD.98H-1.1-3.48-TH

A

STDOFF-4.5OD.98H-1.1-3.48-TH

STDOFF-4.5OD.98H-1.1-3.48-TH

Left CPU

TM Hole

Frame Holes

1

GND_BATT_CHGND

1

GND_CHASSIS_USB

1

GND_CHASSIS_RIGHTHS

1

GND_CHASSIS_SATA

1

GND_CHASSIS_TPAD

1

GND_CHASSIS_CLUTCH

1

GND_CHASSIS_LVDS

1

GND_CHASSIS_DIMM

STDOFF-4.0OD3.0H-SM

1

ZT0988

1

STDOFF-4.5OD.98H-1.1-3.48-TH

ZT0991

1

ZT0989

1

Thermal Module Holes

ZT0982

ZT0983

Right CPU

TM Hole

ZT0931

1

=PPVIN_PBUS_KBDLED

8

=PPVIN_PP5V_KBDLED

8

STDOFF-4.5OD.98H-1.1-3.48-TH

STDOFF-4.5OD.98H-1.1-3.48-TH

Bottom Left GPU

80 79 73 72

ZT0984

Top GPU Right

TM Hole

STDOFF-4.5OD.98H-1.1-3.48-TH

TM Hole

STDOFF-4.5OD.98H-1.1-3.48-TH

8

ZT0980

ZT0987

=PP1V8_GPU_FB_VDDQ

STDOFF-4.5OD.98H-1.1-3.48-TH

R0900

10

21

1%
1/16W
MF-LF

402

R0901

10

21

1%
1/16W
MF-LF

402

Extra FSB Pull-ups

Exist in MRB but not Intel designs. Here for CYA.

If found to be necessary, will move to page14.csa

=PP1V05_S0_MCP_FSB

23 22 14

8

NO STUFF

1

R0950

220

5%
1/16W
MF-LF
402

2

OUT

OUT

OUT

OUT

OUT

CPU_DPRSTP_L
FSB_BREQ0_L
FSB_CPURST_L
CPU_INTR
CPU_NMI

88 61 14 10

88 14 10

88 14 13 10

88 14 10

88 14 10

Bosses for Flex Protector Bracket

ZT0957

KBDLED_PBUS

R0998

0

5%
1/10W
MF-LF

603

KBDLED_5V

R0999

0

5%
1/10W
MF-LF

603

4.0OD1.65H-M1.6X0.35

4.0OD1.65H-M1.6X0.35

21

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=8.4V

MAKE_BASE=TRUE

21

1

ZT0958

1

PP5VR8V4_KBDLED

NO STUFF

NO STUFF

1

R0960

62

5%
1/16W
MF-LF
402

2

R0970

200

1/16W
MF-LF

=PPVIN_S0_KBDLED

ZT0981

STDOFF-4.5OD.98H-1.1-3.48-TH

ZT0985

ZT0986

STDOFF-4.5OD.98H-1.1-3.48-TH

ZT0930

GPU_FB_A_VREF_DIV

MAKE_BASE=TRUE

=PP1V8_GPU_FB_VREF_A

GPU_FB_B_VREF_DIV

MAKE_BASE=TRUE

=PP1V8_GPU_FB_VREF_B

1.4DIA-SHORT-EMI-MLB-M97-M98

1.4DIA-SHORT-EMI-MLB-M97-M98

NO STUFF

R0990

1/16W
MF-LF

150

1

1%

402

2

1

5%

402

2

NO STUFF

1

R0980

150

1%
1/16W
MF-LF
402

2

2.0DIA-TALL-EMI-MLB-M97-M98

2.0DIA-TALL-EMI-MLB-M97-M98

2.0DIA-TALL-EMI-MLB-M97-M98

2.0DIA-TALL-EMI-MLB-M97-M98

50

2.0DIA-TALL-EMI-MLB-M97-M98

2.0DIA-TALL-EMI-MLB-M97-M98

2.0DIA-TALL-EMI-MLB-M97-M98

1.4DIA-SHORT-EMI-MLB-M97-M98

26

1.4DIA-SHORT-EMI-MLB-M97-M98

72

26

73

SH0902

SM

SH0903

SM

SH0920

SH0910

1

1

SM

1

1.4DIA-SHORT-EMI-MLB-M97-M98

SM

1

SH0912

SM

1

SH0923

SM

1

2.0DIA-TALL-EMI-MLB-M97-M98

SH0916

SM

1

SH0918

SM

1

SH0930

SM

1

SH0931

SM

1

SH0932

SM

1

SH0933

SM

1

2.0DIA-TALL-EMI-MLB-M97-M98

SH0900

SM

1

2.0DIA-TALL-EMI-MLB-M97-M98

SH0901

SM

1

SH0911

SM

1

1.4DIA-SHORT-EMI-MLB-M97-M98

1.4DIA-SHORT-EMI-MLB-M97-M98

2.0DIA-TALL-EMI-MLB-M97-M98

2.0DIA-TALL-EMI-MLB-M97-M98

2.0DIA-TALL-EMI-MLB-M97-M98

2.0DIA-TALL-EMI-MLB-M97-M98

2.0DIA-TALL-EMI-MLB-M97-M98

2.0DIA-TALL-EMI-MLB-M97-M98

SH0913

SM

1

SH0914

SM

1

SH0924

SM

1

SH0917

SM

1

SH0919

SM

1

SH0921

SM

1

SH0922

SM

1

SH0934

SM

1

2.0DIA-TALL-EMI-MLB-M97-M98

SH0935

SM

1

CPU signals

GPU signals

VR_PWRGD_CLKEN_L

IMVP6_VID<0..6>

=MCP_BSEL<0..2>

=SPI_CS1_R_L_USE_MLB

=PEG_D2R_P<0..15>

=PEG_D2R_N<0..15>

=PEG_R2D_C_P<0..15>

=PEG_R2D_C_N<0..15>

LVDS_BKL_ON

=MCP_HDMI_TXC_P

=MCP_HDMI_TXC_N

=MCP_HDMI_TXD_P<0..2>

=MCP_HDMI_TXD_N<0..2>

=MCP_HDMI_DDC_CLK

=MCP_HDMI_DDC_DATA

=MCP_HDMI_HPD

ALL_EG_PGOOD

LVDS_MUX_SEL_EG

GPU_RESET_L

TP_IMVP6_CLKEN_L

MAKE_BASE=TRUE

CPU_VID<0..6>

88 11 88 61

MAKE_BASE=TRUE

CPU_BSEL<0..2>

88 10 14

MAKE_BASE=TRUE

MEM_VTT_EN =DDRVTT_EN

25 68 63

MAKE_BASE=TRUE

TP_SPI_CS1_R_L_USE_MLB

MAKE_BASE=TRUE

PEG_D2R_P<0..15>

MAKE_BASE=TRUE

PEG_D2R_N<0..15>

MAKE_BASE=TRUE

PEG_R2D_C_P<0..15>

90 69

MAKE_BASE=TRUE

PEG_R2D_C_N<0..15>

MAKE_BASE=TRUE

LCD_BKLT_EN

MAKE_BASE=TRUE

DP_IG_ML_P<3>

90 81

MAKE_BASE=TRUE

DP_IG_ML_N<3>

90 81

MAKE_BASE=TRUE

DP_IG_ML_P<2..0>

90 81

MAKE_BASE=TRUE

DP_IG_ML_N<2..0>

90 81

MAKE_BASE=TRUE

DP_IG_DDC_CLK

81 75

MAKE_BASE=TRUE

DP_IG_DDC_DATA

81 75

MAKE_BASE=TRUE

DP_IG_HPD

81

MAKE_BASE=TRUE

PM_ALL_GPU_PGOOD

67

MAKE_BASE=TRUE

TP_LVDS_MUX_SEL_EG

MAKE_BASE=TRUE

EG_RESET_L

84

MAKE_BASE=TRUE

JTAG_GMUX_TDI

84

6

MAKE_BASE=TRUE

84

6

MAKE_BASE=TRUE

JTAG_GMUX_TDO

84

6

MAKE_BASE=TRUE

GMUX_INT

84

MAKE_BASE=TRUE

LVDS_IG_BKL_ON

18

MAKE_BASE=TRUE

LVDS_IG_PANEL_PWR

18

MAKE_BASE=TRUE

GMUX ALIASES

=PP1V05_S0_MCP_SATA_DVDD1

=PP1V05_S0_MCP_SATA_AVDD1

=P1V5_EXP_S0_EN

66

MCP_MII_PD

MAKE_BASE=TRUE

1

R0930

47K

5%

Digital Ground

1/16W
MF-LF
402

2

GND

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V

PP3V3_S0

61

43 21

17 90 69

17 90 69

17

17 90 69

86 84

18

18

18

18

18

18

18

84

84

69

GMUX_JTAG_TDI

GMUX_JTAG_TMSJTAG_GMUX_TMS

GMUX_JTAG_TDO

=DVI_HPD_GMUX_INT

IG_BKLT_EN

IG_LCD_PWR_EN

20

20

8 7

=MCP_MII_RXER

=MCP_MII_CRS

=MCP_MII_COL

TP_USB_EXTDP

7

MAKE_BASE=TRUE

TP_USB_EXTDN

7

MAKE_BASE=TRUE

TP_USB_MINIP

7

MAKE_BASE=TRUE

TP_USB_MININ

7

MAKE_BASE=TRUE

TP_MEM_A_A<15>

7

MAKE_BASE=TRUE

TP_MEM_B_A<15>

7

MAKE_BASE=TRUE

TP_CPU_PECI_MCP

7

MAKE_BASE=TRUE

NC_LVDS_IG_A_DATAP<3>

MAKE_BASE=TRUE

NC_LVDS_IG_A_DATAN<3>

MAKE_BASE=TRUE

NC_LVDS_IG_B_DATAP<3>

MAKE_BASE=TRUE

NC_LVDS_IG_B_DATAN<3>

MAKE_BASE=TRUE

HDA_BITCLK

53

MAKE_BASE=TRUE

=PP5V_S3_AUDIO_PWR

8

19

19

17

18

84

84

MCP_SPKR

21

33

33

32

32

96

USB_EXTD_P

USB_EXTD_N

USB_MINI_P

USB_MINI_N

MEM_A_A<15>

MEM_B_A<15>

CPU_PECI_MCP

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

TP_LVDS_IG_B_CLKP

7

MAKE_BASE=TRUE

TP_LVDS_IG_B_CLKN

7

MAKE_BASE=TRUE

TP_LVDS_IG_BKL_PWM

7

MAKE_BASE=TRUE

LVDS_IG_A_DATA_P<3>

LVDS_IG_A_DATA_N<3>

LVDS_IG_B_DATA_P<3>

LVDS_IG_B_DATA_N<3>

LVDS_IG_B_CLK_P

LVDS_IG_B_CLK_N

LVDS_IG_BKL_PWM

AUDIO ALIASES

HDA_BIT_CLK

XW0900

SM

=P3V3ENET_EN

=P1V05ENET_EN

=PP3V3_ENET_PHY_VDDREG

=RTL8211_REGOUT

21

21

XW0901

R0902

R0903

1/16W
MF-LF

402

PP5V_S3_AUDIO

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V

SM

PP5V_S3_AUDIO_AMP

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V

10K

AUD_IPHS_SWITCH_EN

21

MAKE_BASE=TRUE

5%
1/16W
MF-LF

402

0

21

5%

SMC_MCP_SAFE_MODE

ETHERNET ALIASES

PM_SLP_RMGT_L

MAKE_BASE=TRUE

TP_PP3V3_ENET_PHY_VDDREG

MAKE_BASE=TRUE

NC_RTL8211_REGOUT

MAKE_BASE=TRUE

=RTL8211_ENSWREG

MCP79 PCIe PRSNT# Straps

R0925

0

21

18

18

18

5%
1/16W
MF-LF

402

R0927

0

5%
1/16W
MF-LF

402

PCIE_FW_PRSNT_L

MAKE_BASE=TRUE

NO STUFF

21

MAKE_BASE=TRUE

APPLE INC.

PEG_PRSNT_L

R0926

0

5%
1/16W
MF-LF

402

Signal Aliases

SYNC_MASTER=K20_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

21

SIZE

D

SCALE

17

OUT

17

OUT

EG_CLKREQ_OUT_L

DRAWING NUMBER

NONE

051-8071

SHT

27

28

18

56

84

IN

SYNC_DATE=09/24/2008

OF

9

91 20

91 20

91 20

91 20

D

14

90 18

90 18

90 18

90 18

90 18

90 18

91 21

55 53

58 19

41

21

C

32

B

A

REV.

B

98

8

76

5

4

3

2

1

87

www.vinafix.vn

6

5

4

3

21

OMIT

BPRI*

DEFER*

DRDY*
DBSY*

IERR*
INIT*

LOCK*

RESET*

TRDY*

HITM*

BPM0*
BPM1*
BPM2*
BPM3*
PRDY*
PREQ*

TRST*

THERMDA
THERMDC

BCLK0
BCLK1

54.9

1%
1/16W
MF-LF

402

54.9

1%
1/16W
MF-LF

402

54.9

1%
1/16W
MF-LF

402

ADS*
BNR*

BR0*

RS0*
RS1*
RS2*

HIT*

TCK
TDI
TDO
TMS

DBR*

21

21

21

H1

FSB_ADS_L

E2

FSB_BNR_L

G5

FSB_BPRI_L

H5

FSB_DEFER_L

F21

FSB_DRDY_L

E1

FSB_DBSY_L

F1

FSB_BREQ0_L

D20

CPU_IERR_L

88

B3

CPU_INIT_L

H4

FSB_LOCK_L

C1

FSB_CPURST_L

F3

FSB_RS_L<0>

F4

FSB_RS_L<1>

G3

FSB_RS_L<2>

G2

FSB_TRDY_L

G6

FSB_HIT_L

E4

FSB_HITM_L

AD4

XDP_BPM_L<0>

AD3

XDP_BPM_L<1>

AD1

XDP_BPM_L<2>

AC4

XDP_BPM_L<3>

AC2

XDP_BPM_L<4>

AC1

XDP_BPM_L<5>

AC5

XDP_TCK

AA6

XDP_TDI

AB3

XDP_TDO

AB5

XDP_TMS

AB6

XDP_TRST_L

C20

XDP_DBRESET_L

D21

CPU_PROCHOT_L

A24

CPU_THERMD_P

B25

CPU_THERMD_N

C7

PM_THRMTRIP_L

A22

FSB_CLK_CPU_P

A21

FSB_CLK_CPU_N

=PP1V05_S0_CPU

6 8

10 11 12 13 61

7

14 88

BI

14 88

BI

14 88

BI

14 88

BI

7

14 88

BI

7

14 88

BI

9

14 88

BI

14 88

IN

7

14 88

BI

9

13 14 88

IN

14 88

IN

14 88

IN

14 88

IN

14 88

IN

7

14 88

BI

7

14 88

BI

13 88

BI

13 88

BI

13 88

BI

13 88

BI

13 88

BI

6

10 13 88

IN

6

10 13 88

IN

6

10 88

OUT

6

10 13 88

IN

6

10 13 88

IN

13 25

OUT

47 96

OUT

47 96

OUT

14 42 88

OUT

14 88

IN

14 88

IN

PLACE C1000 CLOSE TO CPU_TEST4
PIN. MAKE SURE CPU_TEST4 IS
REFERENCED TO GND

1

R1002

54.9

1%
1/16W
MF-LF
402

2

R1003

PM_THRMTRIP#
SHOULD CONNECT TO ICH AND
GMCH WITHOUT T (NO STUB)

=PP1V05_S0_CPU

6 8

10 11 12 13 61

=PP1V05_S0_CPU

1

54.9

1%
1/16W
MF-LF

402

2

6 8

10 11 12 13 61

PLACE TESTPOINT ON
FSB_IERR_L WITH A GND

0.1" AWAY

=PP1V05_S0_CPU

13 88

BI

1

R1004

68

5%
1/16W
MF-LF
402

2

14 42 61 88

OUT

1

R1005

1K

1%
1/16W
MF-LF

402

2

0.5" MAX LENGTH FOR CPU_GTLREF

1

R1006

2.0K

1%
1/16W
MF-LF

402

NOSTUFF

2

1

C1000

0.1uF

10%
16V

2

X5R
402

6 8

10 11 12 13 61

D

OMIT

D32*
D33*
D34*
D35*
D36*
D37*
D38*
D39*
D40*
D41*
D42*
D43*
D44*
D45*
D46*

D47*
DSTBN2*
DSTBP2*

DINV2*

D48*

D49*

D50*

D51*

D52*

D53*

D54*

D55*

D56*

D57*

D58*

D59*

D60*

D61*

D62*

D63*
DSTBN3*
DSTBP3*

DINV3*

COMP0
COMP1
COMP2
COMP3

DPRSTP*

DPSLP*

DPWR*

PWRGOOD

SLP*

PSI*

Y22

AB24

V24

V26

V23

T22

U25

U23

Y25

W22

Y23

W24

W25

AA23

AA24

AB25

Y26

AA26

U22

AE24

AD24

AA21

AB22

AB21

AC26

AD20

AE22

AF23

AC25

AE21

AD21

AC22

AD23

AF22

AC23

AE25

AF24

AC20

R26

U26

AA1

Y1

E5

B5

D24

D6

D7

AE6

FSB_D_L<32>
FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>
FSB_D_L<36>
FSB_D_L<37>
FSB_D_L<38>
FSB_D_L<39>
FSB_D_L<40>
FSB_D_L<41>
FSB_D_L<42>
FSB_D_L<43>
FSB_D_L<44>
FSB_D_L<45>
FSB_D_L<46>
FSB_D_L<47>
FSB_DSTB_L_N<2>
FSB_DSTB_L_P<2>
FSB_DINV_L<2>

FSB_D_L<48>
FSB_D_L<49>
FSB_D_L<50>
FSB_D_L<51>
FSB_D_L<52>
FSB_D_L<53>
FSB_D_L<54>
FSB_D_L<55>
FSB_D_L<56>
FSB_D_L<57>
FSB_D_L<58>
FSB_D_L<59>
FSB_D_L<60>
FSB_D_L<61>
FSB_D_L<62>
FSB_D_L<63>
FSB_DSTB_L_N<3>
FSB_DSTB_L_P<3>
FSB_DINV_L<3>

CPU_COMP<0>

88

CPU_COMP<1>

88

CPU_COMP<2>

88

CPU_COMP<3>

88

CPU_DPRSTP_L
CPU_DPSLP_L
FSB_DPWR_L
CPU_PWRGD
FSB_CPUSLP_L
CPU_PSI_L

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

7

14 88

BI

9

14 61 88

IN

14 88

IN

14 88

IN

13 14 88

IN

14 88

IN

61

OUT

APPLE INC.

LAYOUT NOTE:
COMP0,2 CONNECT WITH ZO=27.4OHM,
MAKE TRACE LENGTH SHORTER THAN 0.5".
COMP1,3 CONNECT WITH ZO=55OHM,
MAKE TRACE LENGTH SHORTER THAN 0.5".

R1017

54.9

21

1%
1/16W
MF-LF

402

R1019

54.9

21

1%
1/16W
MF-LF

402

CPU FSB

SYNC_MASTER=M98_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

R1016

27.4

1%
1/16W
MF-LF

402

R1018

27.4

1%
1/16W
MF-LF

402

051-8071

SHT

21

21

SYNC_DATE=04/01/2008

OF

10

C

B

A

REV.

B

98

AD26

AF26

E22

F24

E26

G22

F23

G25

E25

E23

K24

G24

J24

J23

H22

F26

K22

H23

J26

H26

H25

N22

K25

P26

R23

L23

M24

L22

M23

P25

P23

P22

T24

R24

L25

T25

N25

L26

M26

N24

C23

D25

C24

AF1

A26

B22

B23

C21

C3

D0*
D1*
D2*
D3*
D4*
D5*
D6*
D7*
D8*
D9*
D10*
D11*
D12*
D13*
D14*
D15*
DSTBN0*
DSTBP0*
DINV0*

D16*
D17*
D18*
D19*
D20*
D21*
D22*
D23*
D24*
D25*
D26*
D27*
D28*
D29*
D30*
D31*
DSTBN1*
DSTBP1*
DINV1*

GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
BSEL0
BSEL1
BSEL2

U1000

PENRYN

FCBGA

2 OF 4

DATA GRP 0DATA GRP 1

MISC

DATA GRP 3 DATA GRP 2

FSB_D_L<0>

7

14 88

BI

FSB_D_L<1>

7

14 88

BI

FSB_D_L<2>

7

14 88

BI

FSB_D_L<3>

7

14 88

BI

FSB_D_L<4>

7

14 88

BI

FSB_D_L<5>

7

14 88

BI

FSB_D_L<6>

7

14 88

BI

FSB_D_L<7>

7

14 88

BI

FSB_D_L<8>

7

14 88

BI

FSB_D_L<9>

7

14 88

BI

FSB_D_L<10>

7

14 88

BI

FSB_D_L<11>

7

14 88

BI

FSB_D_L<12>

7

14 88

BI

FSB_D_L<13>

7

14 88

BI

FSB_D_L<14>

7

14 88

BI

FSB_D_L<15>

7

14 88

BI

FSB_DSTB_L_N<0>

7

14 88

BI

FSB_DSTB_L_P<0>

7

14 88

BI

FSB_DINV_L<0>

7

14 88

BI

FSB_D_L<16>

7

14 88

BI

FSB_D_L<17>

7

14 88

BI

FSB_D_L<18>

7

14 88

BI

FSB_D_L<19>

7

14 88

BI

FSB_D_L<20>

7

14 88

BI

FSB_D_L<21>

7

14 88

BI

FSB_D_L<22>

7

14 88

BI

FSB_D_L<23>

7

14 88

BI

FSB_D_L<24>

7

14 88

BI

FSB_D_L<25>

7

14 88

BI

FSB_D_L<26>

7

14 88

BI

FSB_D_L<27>

7

14 88

BI

FSB_D_L<28>

7

14 88

BI

FSB_D_L<29>

7

14 88

BI

FSB_D_L<30>

7

14 88

BI

FSB_D_L<31>

7

14 88

BI

FSB_DSTB_L_N<1>

7

14 88

BI

FSB_DSTB_L_P<1>

7

14 88

BI

FSB_DINV_L<1>

7

14 88

BI

CPU_GTLREF

26 88

CPU_TEST1
CPU_TEST2

TP_CPU_TEST3

7

CPU_TEST4
TP_CPU_TEST5
TP_CPU_TEST6
TP_CPU_TEST7

CPU_BSEL<0>

9

88

OUT

CPU_BSEL<1>

9

88

OUT

CPU_BSEL<2>

9

88

OUT

NOSTUFF

R1030

0

21

NOSTUFF

R1012

1/16W
MF-LF

1K

402

5%

1/16W

1

MF-LF

5%

2

NOSTUFF

1

402

R1007

1K

5%
1/16W
MF-LF
402

2

AA4

AB2

AA3

D22

J4

L5

L4

K5

M3

N2

J1

N3

P5

P2

L2

P4

P1

R1

M1

K3

H2

K2

J3

L1

Y2

U5

R3

W6

U4

Y5

U1

R4

T5

T3

W2

W5

Y4

U2

V4

W3

V1

A6

A5

C4

D5

C6

B4

A3

M4

N5

T2

V3

B2

F6

D2

D3

A3*
A4*
A5*
A6*
A7*
A8*
A9*
A10*
A11*
A12*
A13*
A14*
A15*
A16*
ADSTB0*

REQ0*
REQ1*
REQ2*
REQ3*
REQ4*

A17*
A18*
A19*
A20*
A21*
A22*
A23*
A24*
A25*
A26*
A27*
A28*
A29*
A30*
A31*
A32*
A33*
A34*
A35*
ADSTB1*

A20M*
FERR*
IGNNE*

STPCLK*
LINT0
LINT1
SMI*

RSVD0
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8

U1000

PENRYN

FCBGA

1 OF 4

ADDR GROUP0

ADDR GROUP1

THERMAL

THERMTRIP*

ICH

RESERVED

CONTROL

XDP/ITP SIGNALS

PROCHOT*

H CLK

FSB_A_L<3>

7

14 88

BI

FSB_A_L<4>

7

14 88

BI

FSB_A_L<5>

7

14 88

BI

FSB_A_L<6>

7

14 88

BI

FSB_A_L<7>

7

14 88

BI

FSB_A_L<8>

7

14 88

BI

FSB_A_L<9>

7

14 88

BI

FSB_A_L<10>

7

14 88

BI

FSB_A_L<11>

7

14 88

BI

FSB_A_L<12>

7

14 88

D

C

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

14 88

14 88

14 88

14 88

7

14 88

14 88

14 88

14 88

14 88

9

14 88

9

14 88

14 88

BI

FSB_A_L<13>

BI

FSB_A_L<14>

BI

FSB_A_L<15>

BI

FSB_A_L<16>

BI

FSB_ADSTB_L<0>

BI

FSB_REQ_L<0>

BI

FSB_REQ_L<1>

BI

FSB_REQ_L<2>

BI

FSB_REQ_L<3>

BI

FSB_REQ_L<4>

BI

FSB_A_L<17>

BI

FSB_A_L<18>

BI

FSB_A_L<19>

BI

FSB_A_L<20>

BI

FSB_A_L<21>

BI

FSB_A_L<22>

BI

FSB_A_L<23>

BI

FSB_A_L<24>

BI

FSB_A_L<25>

BI

FSB_A_L<26>

BI

FSB_A_L<27>

BI

FSB_A_L<28>

BI

FSB_A_L<29>

BI

FSB_A_L<30>

BI

FSB_A_L<31>

BI

FSB_A_L<32>

BI

FSB_A_L<33>

BI

FSB_A_L<34>

BI

FSB_A_L<35>

BI

FSB_ADSTB_L<1>

BI

CPU_A20M_L

IN

CPU_FERR_L

OUT

CPU_IGNNE_L

IN

CPU_STPCLK_L

IN

CPU_INTR

IN

CPU_NMI

IN

CPU_SMI_L

IN

TP_CPU_RSVD0
TP_CPU_RSVD1
TP_CPU_RSVD2
TP_CPU_RSVD3
TP_CPU_RSVD4
TP_CPU_RSVD5
TP_CPU_RSVD6
TP_CPU_RSVD7
TP_CPU_RSVD8

B

XDP_TMS

6

10 13 88

R1021

XDP_TDI

6

10 13 88

XDP_TDO

6

PLACEMENT_NOTE=Place R1024 near ITP connector (if present)

10 88

10 13 88

10 13 88

XDP_TCK

6

XDP_TRST_L

6

54.9

1%
1/16W
MF-LF

402

R1023

649

1%
1/16W
MF-LF

402

R1020

21

R1024

R1022

21

A

8

76

5

4

3

2

1

87

www.vinafix.vn

6

5

4

3

21

(CPU CORE POWER)

=PPVCORE_S0_CPU

Standard Voltage:

44.0 A (Design Target)

41.0 A (HFM)

30.4 A (LFM)

25.5 A (SuperLFM)

27.4 A (Auto-Halt/Stop-Grant HFM)

17.0 A (Auto-Halt/Stop-Grant SuperLFM)

27.4 A (Sleep HFM)

16.8 A (Sleep SuperLFM)

25.0 A (Deep Sleep HFM)

16.0 A (Deep Sleep SuperLFM)

11.5 A (Deeper Sleep)

9.4 A (Enhanced Deeper Sleep)

(CPU IO POWER 1.05V)

=PP1V05_S0_CPU

(CPU INTERNAL PLL POWER 1.5V)

=PP1V5_S0_CPU

CPU_VID<0>
CPU_VID<1>
CPU_VID<2>
CPU_VID<3>
CPU_VID<4>
CPU_VID<5>
CPU_VID<6>

CPU_VCCSENSE_P

CPU_VCCSENSE_N

VCC

VCCP

VCCA

VID0
VID1
VID2
VID3
VID4
VID5
VID6

VCCSENSE

VSSSENSE

AB20

AB7

AC7

AC9

AC12

AC13

AC15

AC17

AC18

AD7

AD9

AD10

AD12

AD14

AD15

AD17

AD18

AE9

AE10

AE12

AE13

AE15

AE17

AE18

AE20

AF9

AF10

AF12

AF14

AF15

AF17

AF18

AF20

G21

V6

J6

K6

M6

J21

K21

M21

N21

N6

R21

R6

T21

T6

V21

W21

B26

C26

AD6

AF5

AE5

AF4

AE3

AF3

AE2

AF7

AE7

D

C

B

AA10

AA12

AA13

AA15

AA17

AA18

AA20

AC10

AB10

AB12

AB14

AB15

AB17

AB18

A7

A9

A10

A12

A13

A15

A17

A18

A20

B7

B9

B10

B12

B14

B15

B17

B18

B20

C9

C10

C12

C13

C15

C17

C18

D9

D10

D12

D14

D15

VCC

D17

D18

E7

E9

E10

E12

E13

E15

E17

E18

E20

F7

F9

F10

F12

F14

F15

F17

F18

F20

AA7

AA9

AB9

OMIT

U1000

PENRYN

FCBGA

3 OF 4

A

Current numbers from Merom for Santa Rosa EMTS, doc #22221.

8

76

8

11 12 45

6 8

10 12 13 61

4500 mA (before VCC stable)
2500 mA (after VCC stable)

8

12

130 mA

9

88

OUT

9

88

OUT

9

88

OUT

9

88

OUT

9

88

OUT

9

88

OUT

9

88

OUT

Low Voltage:

23.0 A (Design Target)

21.0 A (HFM)

18.7 A (LFM)
TBD A (SuperLFM)

TBD A (Auto-Halt/Stop-Grant HFM)
TBD A (Auto-Halt/Stop-Grant SuperLFM)

TBD A (Sleep HFM)
TBD A (Sleep SuperLFM)

TBD A (Deep Sleep HFM)
TBD A (Deep Sleep SuperLFM)

TBD A (Deeper Sleep)

TBD A (Enhanced Deeper Sleep)

=PPVCORE_S0_CPU

1

R1100

100

1%
1/16W
MF-LF
402

2

PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.

61 88

OUT

61 88

OUT

1

R1101

100

1%
1/16W
MF-LF
402

2

PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.

8

11 12 45

Ultra Low Voltage:

17.0 A (Design Target)

TBD A (HFM)
TBD A (LFM)

TBD A (Auto-Halt/Stop-Grant HFM)
TBD A (Auto-Halt/Stop-Grant LFM)

TBD A (Sleep HFM)
TBD A (Sleep LFM)

TBD A (Deep Sleep HFM)
TBD A (Deep Sleep LFM)

TBD A (Deeper Sleep)

TBD A (Enhanced Deeper Sleep)

A4

A8

A11

A14

A16

A19

A23

AF2

B6

B8

B11

B13

B16

B19

B21

B24

C5

C8

C11

C14

C16

C19

C2

C22

C25

D1

D4

D8

D11

D13

D16

D19

D23

D26

E3

E6

E8

E11

E14

VSS VSS

E16

E19

E21

E24

F5

F8

F11

F13

F16

F19

F2

F22

F25

G4

G1

G23

G26

H3

H6

H21

H24

J2

J5

J22

J25

K1

K4

K23

K26

L3

L6

L21

L24

M2

M5

M22

M25

N1

N4

N23

N26

P3

B1

OMIT

U1000

PENRYN

FCBGA

4 OF 4

P6

P21

P24

R2

R5

R22

R25

T1

T4

T23

T26

U3

U6

U21

U24

V2

V5

V22

V25

W1

W4

W23

W26

Y3

Y6

Y21

Y24

AA2

AA5

AA8

AA11

AA14

AA16

AA19

AA22

AA25

AB1

AB4

AB8

AB11

AB13

AB16

AB19

AB23

AB26

AC3

AC6

AC8

AC11

AC14

AC16

AC19

AC21

AC24

AD2

AD5

AD8

AD11

AD13

AD16

AD19

AD22

AD25

AE1

AE4

AE8

AE11

AE14

AE16

AE19

AE23

AE26

A2

AF6

AF8

AF11

AF13

AF16

AF19

AF21

A25

AF25

D

C

B

CPU Power & Ground

051-8071

SHT

SYNC_DATE=04/01/2008

OF

11 98

1

A

REV.

B

SYNC_MASTER=M98_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

5

4

3

2

SCALE

NONE

87

www.vinafix.vn

6

5

4

3

21

D

D

CPU VCORE HF AND BULK DECOUPLING

=PPVCORE_S0_CPU

8

11 45

CRITICAL

C1250

PLACEMENT_NOTE=Place in CPU center cavity.

C

PLACEMENT_NOTE=Place in CPU center cavity.

POLY-TANT

PLACEMENT_NOTE=Place in CPU center cavity.

CRITICAL

C1252

POLY-TANT

PLACEMENT_NOTE=Place in CPU center cavity.

4x 330uF, 20x 22uF 0805

CRITICAL

1

C1251

330UF

D2T-SM2

330UF

D2T-SM2

20%

2.0V

20%

2.0V

330UF

20%

2.0V

32

POLY-TANT

D2T-SM2

CRITICAL

1

C1253

330UF

20%

2.0V

32

POLY-TANT

D2T-SM2

1

32

1

32

CRITICAL

1

C1200

22UF

20%

6.3V

2

X5R-CERM
603

CRITICAL

1

C1210

22UF

20%

6.3V

2

X5R-CERM
603

CRITICAL

1

C1201

22UF

20%

6.3V

2

X5R-CERM
603

CRITICAL

1

C1211

22UF

20%

6.3V

2

X5R-CERM
603

CRITICAL

1

C1202

22UF

20%

6.3V

2

X5R-CERM
603

CRITICAL

1

C1212

22UF

20%

6.3V

2

X5R-CERM
603

CRITICAL

1

C1203

22UF

20%

6.3V

2

X5R-CERM
603

CRITICAL

1

C1213

22UF

20%

6.3V

2

X5R-CERM
603

CRITICAL

1

C1204

22UF

20%

6.3V

2

X5R-CERM
603

CRITICAL

1

C1214

22UF

20%

6.3V

2

X5R-CERM
603

CRITICAL

1

C1205

22UF

20%

6.3V

2

X5R-CERM
603

CRITICAL

1

C1215

22UF

20%

6.3V

2

X5R-CERM
603

CRITICAL

1

C1206

22UF

20%

6.3V

2

X5R-CERM
603

CRITICAL

1

C1216

22UF

20%

6.3V

2

X5R-CERM

603

CRITICAL

1

C1207

22UF

20%

6.3V

2

X5R-CERM
603

CRITICAL

1

C1217

22UF

20%

6.3V

2

X5R-CERM
603

CRITICAL

1

C1208

22UF

20%

6.3V

2

X5R-CERM
603

CRITICAL

1

C1218

22UF

20%

6.3V

2

X5R-CERM
603

CRITICAL

1

C1209

22UF

20%

6.3V

2

X5R-CERM
603

CRITICAL

1

C1219

22UF

20%

6.3V

2

X5R-CERM
603

C

VCCP (CPU I/O) DECOUPLING

=PP1V05_S0_CPU

6 8

10 11 13 61

1x 470uF, 6x 0.1uF 0402

CRITICAL

1

C1235

470UF

20%

2.5V
POLY

D2T

WF: Consider sharing bulk cap with NB Vtt?

1

C1236

0.1UF

20%
10V

2

32

CERM
402

1

C1237

0.1UF

20%
10V

2

CERM
402

1

C1238

2

0.1UF

20%
10V
CERM
402

1

2

C1239

0.1UF

20%
10V
CERM
402

1

C1240

0.1UF

20%
10V

2

CERM
402

1

C1241

2

0.1UF

20%
10V
CERM
402

B

=PP1V5_S0_CPU

8

11

C1280

10uF

6.3V

20%

X5R
603

A

8

76

VCCA (CPU AVdd) DECOUPLING

1x 10uF, 1x 0.01uF

1

1

C1281

0.01UF

10%
16V

2

2

CERM
402

PLACEMENT_NOTE=Place near CPU pin B26.

B

CPU Decoupling & VID

SYNC_MASTER=M98_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

5

4

3

2

SCALE

NONE

051-8071

SHT

SYNC_DATE=04/01/2008

OF

1

A

REV.

B

9812

87

www.vinafix.vn

6

5

4

3

21

Mini-XDP Connector

NOTE: This is not the standard XDP pinout.

D

Use with 920-0620 adapter board to support CPU, MCP debugging.

D

MCP79-specific pinout

=PP3V3_S0_XDP

6 8

=PP1V05_S0_CPU

6 8

10 11 12 61

XDP

1

R1315

54.9

1%
1/16W
MF-LF

402

2

XDP_BPM_L<5>

10 88

BI

XDP_BPM_L<4>

10 88

BI

XDP_BPM_L<3>

10 88

BI

XDP_BPM_L<2>

10 88

IN

XDP_BPM_L<1>

10 88

IN

XDP_BPM_L<0>

10 88

IN

C

XDP

R1399

1K

1/16W
MF-LF

21

5%

402

CPU_PWRGD

10 14 88

IN

19

IN

6

21

OUT

7

21 44 91

BI

7

21 44 91

BI

6

10 88

OUT

TP_XDP_OBSFN_B0
TP_XDP_OBSFN_B1

TP_XDP_OBSDATA_B0
TP_XDP_OBSDATA_B1

TP_XDP_OBSDATA_B2

7

TP_XDP_OBSDATA_B3

7

XDP_PWRGD

PM_LATRIGGER_L
JTAG_MCP_TCK

SMBUS_MCP_0_DATA
SMBUS_MCP_0_CLK

XDP_TCK

XDP_OBS20

OBSFN_A0
OBSFN_A1

OBSDATA_A0
OBSDATA_A1

OBSDATA_A2
OBSDATA_A3

OBSFN_B0
OBSFN_B1

OBSDATA_B0
OBSDATA_B1 OBSDATA_D1

OBSDATA_B2
OBSDATA_B3

PWRGD/HOOK0

HOOK1

VCC_OBS_AB

HOOK2
HOOK3

SDA

SCL
TCK1
TCK0

XDP

1

C1300

0.1uF

10%
16V

2

X5R
402

B

CRITICAL
XDP_CONN

J1300

LTH-030-01-G-D-NOPEGS

F-ST-SM

2

1

4

3

6

5

87

10

12 11

14 13

16 15

18 17

20

22 21

24 23

26 25

28 27

30

32 31

34 33

36 35

38 37

40

42 41

44 43

46 45

48 47

50

52 51

54 53

56 55

NC

58 57

60

9

19

29

39

49

59

998-1571

OBSFN_C0
OBSFN_C1

OBSDATA_C0
OBSDATA_C1

OBSDATA_C2
OBSDATA_C3

OBSFN_D0
OBSFN_D1

OBSDATA_D0

OBSDATA_D2
OBSDATA_D3

ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.
TDO
TRSTn
TDI
TMS
XDP_PRESENT#
XDP

1

C1301

0.1uF

10%

16V

2

X5R

402

JTAG_MCP_TDO_CONN
JTAG_MCP_TRST_L

MCP_DEBUG<0>
MCP_DEBUG<1>

MCP_DEBUG<2>
MCP_DEBUG<3>

JTAG_MCP_TDI
JTAG_MCP_TMS

MCP_DEBUG<4>
MCP_DEBUG<5>

MCP_DEBUG<6>
MCP_DEBUG<7>

FSB_CLK_ITP_P
FSB_CLK_ITP_N

XDP_CPURST_L

88

XDP_DBRESET_L

XDP_TDO_CONN
XDP_TRST_L
XDP_TDI
XDP_TMS

6

IN

6

21

OUT

19 91

BI

19 91

BI

19 91

BI

19 91

BI

6

21

OUT

6

21

OUT

19 91

BI

19 91

BI

19 91

BI

19 91

BI

14 88

IN

14 88

IN

10 25

OUT

6

IN

6

10 88

OUT

6

10 88

OUT

6

10 88

OUT

XDP

R1303

1K

21

FSB_CPURST_L

5%

PLACEMENT_NOTE=Place close to CPU to minimize stub.

1/16W
MF-LF

402

9

10 14 88

IN

C

B

A

8

76

Direction of XDP module

Please avoid any obstructions
on even-numbered side of J1300

5

eXtended Debug Port(MiniXDP)

051-8071

SHT

SYNC_DATE=04/01/2008

OF

13

1

A

REV.

B

98

SYNC_MASTER=M98_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

4

3

2

SCALE

NONE

87

www.vinafix.vn

D

C

=PP1V05_S0_MCP_FSB

8 9

14 22 23

R1410

54.9

1%
1/16W
MF-LF

402

B

10 42 88

10 88

PM_THRMTRIP_L

IN

CPU_FERR_L

IN

NO STUFF

R1420

1K

5%
1/16W
MF-LF

402

9

9

9

IN

IN

IN

=MCP_BSEL<2>
=MCP_BSEL<1>
=MCP_BSEL<0>

A

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

8

76

6

5

4

3

21

OMIT

U1400

MCP79-TOPO-B

BGA

FSB_DSTB_L_P<0>

7

10 88

BI

FSB_DSTB_L_N<0>

7

10 88

BI

FSB_DINV_L<0>

7

10 88

BI

FSB_DSTB_L_P<1>

7

10 88

BI

FSB_DSTB_L_N<1>

7

10 88

BI

FSB_DINV_L<1>

7

10 88

BI

FSB_DSTB_L_P<2>

7

10 88

BI

FSB_DSTB_L_N<2>

7

10 88

BI

FSB_DINV_L<2>

7

10 88

BI

FSB_DSTB_L_P<3>

7

10 88

BI

FSB_DSTB_L_N<3>

7

10 88

BI

FSB_DINV_L<3>

7

10 88

BI

FSB_A_L<3>

7

10 88

BI

FSB_A_L<4>

7

10 88

BI

FSB_A_L<5>

7

10 88

BI

FSB_A_L<6>

7

10 88

BI

FSB_A_L<7>

7

10 88

BI

FSB_A_L<8>

7

10 88

BI

FSB_A_L<9>

7

10 88

BI

FSB_A_L<10>

7

10 88

BI

FSB_A_L<11>

7

10 88

BI

FSB_A_L<12>

7

10 88

BI

FSB_A_L<13>

7

10 88

BI

FSB_A_L<14>

7

10 88

BI

FSB_A_L<15>

7

10 88

BI

FSB_A_L<16>

7

10 88

BI

FSB_A_L<17>

7

10 88

BI

FSB_A_L<18>

7

10 88

BI

FSB_A_L<19>

7

10 88

BI

FSB_A_L<20>

7

10 88

BI

FSB_A_L<21>

7

10 88

BI

FSB_A_L<22>

7

10 88

BI

FSB_A_L<23>

7

10 88

BI

FSB_A_L<24>

7

10 88

BI

FSB_A_L<25>

7

10 88

BI

FSB_A_L<26>

7

10 88

BI

FSB_A_L<27>

7

10 88

BI

FSB_A_L<28>

7

10 88

BI

FSB_A_L<29>

7

10 88

BI

FSB_A_L<30>

7

10 88

BI

FSB_A_L<31>

7

10 88

BI

FSB_A_L<32>

10 88

BI

FSB_A_L<33>

10 88

BI

FSB_A_L<34>

10 88

BI

FSB_A_L<35>

10 88

BI

FSB_ADSTB_L<0>

7

10 88

BI

FSB_ADSTB_L<1>

7

10 88

BI

FSB_REQ_L<0>

7

10 88

BI

FSB_REQ_L<1>

7

10 88

BI

FSB_REQ_L<2>

7

10 88

BI

FSB_REQ_L<3>

7

10 88

BI

FSB_REQ_L<4>

7

10 88

BI

7

10 88

BI

10 88

BI

9

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

IN

10 88

OUT

9

OUT

10 42 61 88

OUT

10 88

OUT

10 88

OUT

10 88

OUT

23

270 mA (A01)

88

88

88

88

88

FSB_ADS_L
FSB_BNR_L
FSB_BREQ0_L
FSB_BREQ1_L
FSB_DBSY_L
FSB_DRDY_L
FSB_HIT_L
FSB_HITM_L
FSB_LOCK_L
FSB_TRDY_L

CPU_PECI_MCP
CPU_PROCHOT_L

(MCP_BSEL<2>)
(MCP_BSEL<1>)
(MCP_BSEL<0>)

FSB_RS_L<0>
FSB_RS_L<1>
FSB_RS_L<2>

PP1V05_S0_MCP_PLL_FSB

MCP_BCLK_VML_COMP_VDD
MCP_BCLK_VML_COMP_GND

MCP_CPU_COMP_VCC
MCP_CPU_COMP_GND

206 mA

20 mA
29 mA
15 mA

1/16W
MF-LF

1/16W
MF-LF

1

1

R1416

62

62

5%

5%

1/16W
MF-LF
402

402

2

2

NO STUFF

1

1

R1422

1K

1K

5%

5%
1/16W
MF-LF

402

402

2

2

1

1

1/16W
MF-LF

1/16W
MF-LF

R1435

49.9

1%

1%

1/16W
MF-LF
402

402

2

2

1

1

R1436

49.9

1%

1%
1/16W
MF-LF

402

402

2

2

R1430

49.9

R1431

49.9

1

R1415

2

NO STUFF

1

R1421

2

T40

CPU_DSTBP0#

U40

CPU_DSTBN0#

V41

CPU_DBI0#

W39

CPU_DSTBP1#

W37

CPU_DSTBN1#

V35

CPU_DBI1#

N37

CPU_DSTBP2#

L36

CPU_DSTBN2#

N35

CPU_DBI2#

M39

CPU_DSTBP3#

M41

CPU_DSTBN3#

J41

CPU_DBI3#

AC34

CPU_A3#

AE38

CPU_A4#

AE34

CPU_A5#

AC37

CPU_A6#

AE37

CPU_A7#

AE35

CPU_A8#

AB35

CPU_A9#

AF35

CPU_A10#

AG35

CPU_A11#

AG39

CPU_A12#

AE33

CPU_A13#

AG37

CPU_A14#

AG38

CPU_A15#

AG34

CPU_A16#

AN38

CPU_A17#

AL39

CPU_A18#

AG33

CPU_A19#

AL33

CPU_A20#

AJ33

CPU_A21#

AN36

CPU_A22#

AJ35

CPU_A23#

AJ37

CPU_A24#

AJ36

CPU_A25#

AJ38

CPU_A26#

AL37

CPU_A27#

AL34

CPU_A28#

AN37

CPU_A29#

AJ34

CPU_A30#

AL38

CPU_A31#

AL35

CPU_A32#

AN34

CPU_A33#

AR39

CPU_A34#

AN35

CPU_A35#

AE36

CPU_ADSTB0#

AK35

CPU_ADSTB1#

AC38

CPU_REQ0#

AA33

CPU_REQ1#

AC39

CPU_REQ2#

AC33

CPU_REQ3#

AC35

CPU_REQ4#

AD42

CPU_ADS#

AD43

CPU_BNR#

AE40

CPU_BR0#

AL32

CPU_BR1#

AD39

CPU_DBSY#

AD41

CPU_DRDY#

AB42

CPU_HIT#

AD40

CPU_HITM#

AC43

CPU_LOCK#

AE41

CPU_TRDY#

E41

CPU_PECI

AJ41

CPU_PROCHOT#

AG43

CPU_THERMTRIP#

AH40

CPU_FERR#

F42

CPU_BSEL2

D42

CPU_BSEL1

F41

CPU_BSEL0

AC41

CPU_RS0#

AB41

CPU_RS1#

AC42

CPU_RS2#

AG27

+V_DLL_DLCELL_AVDD

AH27

+V_PLL_MCLK

AG28

+V_PLL_FSB

AH28

+V_PLL_CPU

AM39

BCLK_VML_COMP_VDD

AM40

BCLK_VML_COMP_GND

AM43

CPU_COMP_VCC

AM42

CPU_COMP_GND

(1 OF 11)

FSB

CPU_BPRI#

CPU_DEFER#

BCLK_OUT_CPU_P
BCLK_OUT_CPU_N

BCLK_OUT_ITP_P
BCLK_OUT_ITP_N

BCLK_OUT_NB_P
BCLK_OUT_NB_N

BCLK_IN_N
BCLK_IN_P

CPU_A20M#

CPU_IGNNE#

CPU_INIT#

CPU_PWRGD

CPU_RESET#

CPU_DPSLP#

CPU_DPWR#
CPU_STPCLK#
CPU_DPRSTP#

5

CPU_D0#
CPU_D1#
CPU_D2#
CPU_D3#
CPU_D4#
CPU_D5#
CPU_D6#
CPU_D7#
CPU_D8#

CPU_D9#
CPU_D10#
CPU_D11#
CPU_D12#
CPU_D13#
CPU_D14#
CPU_D15#
CPU_D16#
CPU_D17#
CPU_D18#
CPU_D19#
CPU_D20#
CPU_D21#
CPU_D22#
CPU_D23#
CPU_D24#
CPU_D25#
CPU_D26#
CPU_D27#
CPU_D28#
CPU_D29#
CPU_D30#
CPU_D31#
CPU_D32#
CPU_D33#
CPU_D34#
CPU_D35#
CPU_D36#
CPU_D37#
CPU_D38#
CPU_D39#
CPU_D40#
CPU_D41#
CPU_D42#
CPU_D43#
CPU_D44#
CPU_D45#
CPU_D46#
CPU_D47#
CPU_D48#
CPU_D49#
CPU_D50#
CPU_D51#
CPU_D52#
CPU_D53#
CPU_D54#
CPU_D55#
CPU_D56#
CPU_D57#
CPU_D58#
CPU_D59#
CPU_D60#
CPU_D61#
CPU_D62#
CPU_D63#

CPU_INTR

CPU_NMI
CPU_SMI#

CPU_SLP#

Y43

W42

Y40

W41

Y39

V42

Y41

Y42

P42

U41

R42

T39

T42

T41

R41

T43

W35

AA37

W33

W34

AA36

AA34

AA38

AA35

U38

U36

U35

U33

U34

W38

R33

U37

N34

N33

R34

R35

P35

R39

R37

R38

L37

L39

L38

N36

N38

J39

J38

J37

L42

M42

P41

N41

N40

M40

H40

K42

H41

L41

H43

H42

K41

J40

H39

M43

AA41

AA40

G42

G41

AL43

AL42

AL41

AK42

AK41

AJ40

AF41

AH39

AH42

AF42

AG41

AH41

AH43

H38

AM33

AN33

AM32

AG42

AN32

4

FSB_D_L<0>
FSB_D_L<1>
FSB_D_L<2>
FSB_D_L<3>
FSB_D_L<4>
FSB_D_L<5>
FSB_D_L<6>
FSB_D_L<7>
FSB_D_L<8>
FSB_D_L<9>
FSB_D_L<10>
FSB_D_L<11>
FSB_D_L<12>
FSB_D_L<13>
FSB_D_L<14>
FSB_D_L<15>
FSB_D_L<16>
FSB_D_L<17>
FSB_D_L<18>
FSB_D_L<19>
FSB_D_L<20>
FSB_D_L<21>
FSB_D_L<22>
FSB_D_L<23>
FSB_D_L<24>
FSB_D_L<25>
FSB_D_L<26>
FSB_D_L<27>
FSB_D_L<28>
FSB_D_L<29>
FSB_D_L<30>
FSB_D_L<31>
FSB_D_L<32>
FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>
FSB_D_L<36>
FSB_D_L<37>
FSB_D_L<38>
FSB_D_L<39>
FSB_D_L<40>
FSB_D_L<41>
FSB_D_L<42>
FSB_D_L<43>
FSB_D_L<44>
FSB_D_L<45>
FSB_D_L<46>
FSB_D_L<47>
FSB_D_L<48>
FSB_D_L<49>
FSB_D_L<50>
FSB_D_L<51>
FSB_D_L<52>
FSB_D_L<53>
FSB_D_L<54>
FSB_D_L<55>
FSB_D_L<56>
FSB_D_L<57>
FSB_D_L<58>
FSB_D_L<59>
FSB_D_L<60>
FSB_D_L<61>
FSB_D_L<62>
FSB_D_L<63>

FSB_BPRI_L
FSB_DEFER_L

FSB_CLK_CPU_P
FSB_CLK_CPU_N

FSB_CLK_ITP_P
FSB_CLK_ITP_N

FSB_CLK_MCP_P

88

FSB_CLK_MCP_N

88

CPU_A20M_L
CPU_IGNNE_L
CPU_INIT_L
CPU_INTR
CPU_NMI
CPU_SMI_L

CPU_PWRGD
FSB_CPURST_L

FSB_CPUSLP_L
CPU_DPSLP_L
FSB_DPWR_L
CPU_STPCLK_L
CPU_DPRSTP_L

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

7

10 88

BI

10 88

OUT

10 88

OUT

10 88

OUT

10 88

OUT

13 88

OUT

13 88

OUT

Loop-back clock for delay matching.

10 88

OUT

10 88

OUT

10 88

OUT

9

10 88

OUT

9

10 88

OUT

10 88

OUT

9

10 13 88

OUT

10 88

OUT

10 88

OUT

10 88

OUT

10 88

OUT

10 61 88

9

OUT

3

=PP1V05_S0_MCP_FSB

NO STUFF

1

R1440

150

5%
1/16W
MF-LF
402

2

10 13 88

OUT

8 9

14 22 23

APPLE INC.

2

MCP CPU Interface

SYNC_MASTER=T18_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

051-8071

SHT

SYNC_DATE=06/06/2008

OF

1

D

C

B

A

REV.

B

9814

87

www.vinafix.vn

6

5

4

3

21

MCP79-TOPO-B

MDQ1_63
MDQ1_62
MDQ1_61
MDQ1_60
MDQ1_59
MDQ1_58
MDQ1_57
MDQ1_56
MDQ1_55
MDQ1_54
MDQ1_53
MDQ1_52
MDQ1_51
MDQ1_50
MDQ1_49
MDQ1_48
MDQ1_47
MDQ1_46
MDQ1_45
MDQ1_44
MDQ1_43
MDQ1_42
MDQ1_41
MDQ1_40
MDQ1_39
MDQ1_38
MDQ1_37
MDQ1_36
MDQ1_35
MDQ1_34
MDQ1_33
MDQ1_32
MDQ1_31
MDQ1_30
MDQ1_29
MDQ1_28
MDQ1_27
MDQ1_26
MDQ1_25
MDQ1_24
MDQ1_23
MDQ1_22
MDQ1_21
MDQ1_20
MDQ1_19
MDQ1_18
MDQ1_17
MDQ1_16
MDQ1_15
MDQ1_14
MDQ1_13
MDQ1_12
MDQ1_11
MDQ1_10
MDQ1_9
MDQ1_8
MDQ1_7
MDQ1_6
MDQ1_5
MDQ1_4
MDQ1_3
MDQ1_2
MDQ1_1
MDQ1_0

MDQM1_7
MDQM1_6
MDQM1_5
MDQM1_4
MDQM1_3
MDQM1_2
MDQM1_1
MDQM1_0

OMIT

U1400

BGA

(3 OF 11)

MDQS1_7_P
MDQS1_7_N
MDQS1_6_P
MDQS1_6_N
MDQS1_5_P
MDQS1_5_N
MDQS1_4_P
MDQS1_4_N
MDQS1_3_P
MDQS1_3_N
MDQS1_2_P
MDQS1_2_N
MDQS1_1_P
MDQS1_1_N
MDQS1_0_P
MDQS1_0_N

MEMORY PARTITION 1

MEMORY

CONTROL

MCLK1A_2_P
MCLK1A_2_N

MCLK1A_1_P
MCLK1A_1_N

MCLK1A_0_P
MCLK1A_0_N

MRAS1#
MCAS1#

MWE1#

MBA1_2
MBA1_1
MBA1_0

MA1_14
MA1_13
MA1_12
MA1_11
MA1_10

MA1_9
MA1_8
MA1_7
MA1_6
MA1_5
MA1_4
MA1_3
MA1_2
MA1_1
MA1_0

1A

MCS1A_1#
MCS1A_0#

MODT1A_1
MODT1A_0

MCKE1A_1
MCKE1A_0

AT2

AT1

AY2

AY1

BB6

BA6

BA10

AY11

BB33

BA33

BB37

BA37

BA43

AY42

AT42

AT43

AW16

BA15

BA16

BB29

BB18

BB17

BA29

BA14

AW28

BC28

BA17

BB28

AY28

BA28

AY27

BA27

BA26

BB26

BA25

BB25

BA18

BA42

BB42

BB22

BA22

BA19

AY19

BB14

BB16

BB13

AY15

AY31

BB30

MEM_B_DQS_P<7>
MEM_B_DQS_N<7>
MEM_B_DQS_P<6>
MEM_B_DQS_N<6>
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
MEM_B_DQS_P<4>
MEM_B_DQS_N<4>
MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
MEM_B_DQS_P<2>
MEM_B_DQS_N<2>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQS_P<0>
MEM_B_DQS_N<0>

MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L

MEM_B_BA<2>
MEM_B_BA<1>
MEM_B_BA<0>

MEM_B_A<14>
MEM_B_A<13>
MEM_B_A<12>
MEM_B_A<11>
MEM_B_A<10>
MEM_B_A<9>
MEM_B_A<8>
MEM_B_A<7>
MEM_B_A<6>
MEM_B_A<5>
MEM_B_A<4>
MEM_B_A<3>
MEM_B_A<2>
MEM_B_A<1>
MEM_B_A<0>

TP_MEM_B_CLK2P
TP_MEM_B_CLK2N

MEM_B_CLK_P<1>
MEM_B_CLK_N<1>

MEM_B_CLK_P<0>
MEM_B_CLK_N<0>

MEM_B_CS_L<1>
MEM_B_CS_L<0>

MEM_B_ODT<1>
MEM_B_ODT<0>

MEM_B_CKE<1>
MEM_B_CKE<0>

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

7

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

D

C

B

OMIT

U1400

MCP79-TOPO-B

BGA

MDQ0_63
MDQ0_62
MDQ0_61
MDQ0_60
MDQ0_59
MDQ0_58
MDQ0_57
MDQ0_56
MDQ0_55
MDQ0_54
MDQ0_53
MDQ0_52
MDQ0_51
MDQ0_50
MDQ0_49
MDQ0_48
MDQ0_47
MDQ0_46
MDQ0_45
MDQ0_44
MDQ0_43
MDQ0_42
MDQ0_41
MDQ0_40
MDQ0_39
MDQ0_38
MDQ0_37
MDQ0_36
MDQ0_35
MDQ0_34
MDQ0_33
MDQ0_32
MDQ0_31
MDQ0_30
MDQ0_29
MDQ0_28
MDQ0_27
MDQ0_26
MDQ0_25
MDQ0_24
MDQ0_23
MDQ0_22
MDQ0_21
MDQ0_20
MDQ0_19
MDQ0_18
MDQ0_17
MDQ0_16
MDQ0_15
MDQ0_14
MDQ0_13
MDQ0_12
MDQ0_11
MDQ0_10
MDQ0_9
MDQ0_8
MDQ0_7
MDQ0_6
MDQ0_5
MDQ0_4
MDQ0_3
MDQ0_2
MDQ0_1
MDQ0_0

MDQM0_7
MDQM0_6
MDQM0_5
MDQM0_4
MDQM0_3
MDQM0_2
MDQM0_1
MDQM0_0

(2 OF 11)

MDQS0_7_P
MDQS0_7_N
MDQS0_6_P
MDQS0_6_N
MDQS0_5_P
MDQS0_5_N
MDQS0_4_P
MDQS0_4_N
MDQS0_3_P
MDQS0_3_N
MDQS0_2_P
MDQS0_2_N
MDQS0_1_P
MDQS0_1_N
MDQS0_0_P
MDQS0_0_N

MEMORY PARTITION 0

MEMORY

CONTROL

MCLK0A_2_P
MCLK0A_2_N

MCLK0A_1_P
MCLK0A_1_N

MCLK0A_0_P
MCLK0A_0_N

MCS0A_1#
MCS0A_0#

MODT0A_1
MODT0A_0

MCKE0A_1
MCKE0A_0

MRAS0#
MCAS0#

MBA0_2
MBA0_1
MBA0_0

MA0_14
MA0_13
MA0_12
MA0_11
MA0_10

0A

MWE0#

MA0_9
MA0_8
MA0_7
MA0_6
MA0_5
MA0_4
MA0_3
MA0_2
MA0_1
MA0_0

AL10

AL11

AR8

AR9

AW7

AW8

AP13

AR13

AV25

AW25

AU30

AU29

AT35

AU35

AU39

AT39

AV17

AP17

AR17

AP23

AP19

AW17

AR23

AU15

AN23

AW21

AN19

AV21

AR22

AU21

AP21

AR21

AN21

AV19

AU19

AT19

AR19

AW33

AV33

BA24

AY24

BB20

BC20

AT15

AR18

AP15

AV15

AU23

AT23

MEM_A_DQS_P<7>
MEM_A_DQS_N<7>
MEM_A_DQS_P<6>
MEM_A_DQS_N<6>
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
MEM_A_DQS_P<4>
MEM_A_DQS_N<4>
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DQS_P<0>
MEM_A_DQS_N<0>

MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L

MEM_A_BA<2>
MEM_A_BA<1>
MEM_A_BA<0>

MEM_A_A<14>
MEM_A_A<13>
MEM_A_A<12>
MEM_A_A<11>
MEM_A_A<10>
MEM_A_A<9>
MEM_A_A<8>
MEM_A_A<7>
MEM_A_A<6>
MEM_A_A<5>
MEM_A_A<4>
MEM_A_A<3>
MEM_A_A<2>
MEM_A_A<1>
MEM_A_A<0>

TP_MEM_A_CLK2P
TP_MEM_A_CLK2N

MEM_A_CLK_P<1>
MEM_A_CLK_N<1>

MEM_A_CLK_P<0>
MEM_A_CLK_N<0>

MEM_A_CS_L<1>
MEM_A_CS_L<0>

MEM_A_ODT<1>
MEM_A_ODT<0>

MEM_A_CKE<1>
MEM_A_CKE<0>

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

7

7

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

MEM_B_DQ<63>
MEM_B_DQ<62>
MEM_B_DQ<61>
MEM_B_DQ<60>
MEM_B_DQ<59>
MEM_B_DQ<58>
MEM_B_DQ<57>
MEM_B_DQ<56>
MEM_B_DQ<55>
MEM_B_DQ<54>
MEM_B_DQ<53>
MEM_B_DQ<52>
MEM_B_DQ<51>
MEM_B_DQ<50>
MEM_B_DQ<49>
MEM_B_DQ<48>
MEM_B_DQ<47>
MEM_B_DQ<46>
MEM_B_DQ<45>
MEM_B_DQ<44>
MEM_B_DQ<43>
MEM_B_DQ<42>
MEM_B_DQ<41>
MEM_B_DQ<40>
MEM_B_DQ<39>
MEM_B_DQ<38>
MEM_B_DQ<37>
MEM_B_DQ<36>
MEM_B_DQ<35>
MEM_B_DQ<34>
MEM_B_DQ<33>
MEM_B_DQ<32>
MEM_B_DQ<31>
MEM_B_DQ<30>
MEM_B_DQ<29>
MEM_B_DQ<28>
MEM_B_DQ<27>
MEM_B_DQ<26>
MEM_B_DQ<25>
MEM_B_DQ<24>
MEM_B_DQ<23>
MEM_B_DQ<22>
MEM_B_DQ<21>
MEM_B_DQ<20>
MEM_B_DQ<19>
MEM_B_DQ<18>
MEM_B_DQ<17>
MEM_B_DQ<16>
MEM_B_DQ<15>
MEM_B_DQ<14>
MEM_B_DQ<13>
MEM_B_DQ<12>
MEM_B_DQ<11>
MEM_B_DQ<10>
MEM_B_DQ<9>
MEM_B_DQ<8>
MEM_B_DQ<7>
MEM_B_DQ<6>
MEM_B_DQ<5>
MEM_B_DQ<4>
MEM_B_DQ<3>
MEM_B_DQ<2>
MEM_B_DQ<1>
MEM_B_DQ<0>

MEM_B_DM<7>
MEM_B_DM<6>
MEM_B_DM<5>
MEM_B_DM<4>
MEM_B_DM<3>
MEM_B_DM<2>
MEM_B_DM<1>
MEM_B_DM<0>

AN10

AP11

AU11

AV11

AV13

AW13

AR11

AT11

AR14

AU13

AR26

AU25

AT27

AU27

AP25

AR25

AP27

AR27

AP29

AR29

AP31

AR31

AV27

AN29

AV29

AN31

AU31

AR33

AV37

AW37

AT31

AV31

AT37

AU37

AW39

AV39

AR37

AR38

AV38

AW38

AR35

AP35

AR10

AN13

AN27

AW29

AV35

AR34

AL8

AL9

AP9

AN9

AL6

AL7

AN6

AN7

AR6

AR7

AV6

AW5

AR5

AU6

AV5

AU7

AU8

AW9

AW6

AY5

AU9

AV9

AN5

AU5

MEM_A_DQ<63>

27 89

BI

MEM_A_DQ<62>

27 89

BI

MEM_A_DQ<61>

27 89

BI

MEM_A_DQ<60>

27 89

BI

MEM_A_DQ<59>

27 89

D

C

B

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

MEM_A_DQ<58>
MEM_A_DQ<57>
MEM_A_DQ<56>
MEM_A_DQ<55>
MEM_A_DQ<54>
MEM_A_DQ<53>
MEM_A_DQ<52>
MEM_A_DQ<51>
MEM_A_DQ<50>
MEM_A_DQ<49>
MEM_A_DQ<48>
MEM_A_DQ<47>
MEM_A_DQ<46>
MEM_A_DQ<45>
MEM_A_DQ<44>
MEM_A_DQ<43>
MEM_A_DQ<42>
MEM_A_DQ<41>
MEM_A_DQ<40>
MEM_A_DQ<39>
MEM_A_DQ<38>
MEM_A_DQ<37>
MEM_A_DQ<36>
MEM_A_DQ<35>
MEM_A_DQ<34>
MEM_A_DQ<33>
MEM_A_DQ<32>
MEM_A_DQ<31>
MEM_A_DQ<30>
MEM_A_DQ<29>
MEM_A_DQ<28>
MEM_A_DQ<27>
MEM_A_DQ<26>
MEM_A_DQ<25>
MEM_A_DQ<24>
MEM_A_DQ<23>
MEM_A_DQ<22>
MEM_A_DQ<21>
MEM_A_DQ<20>
MEM_A_DQ<19>
MEM_A_DQ<18>
MEM_A_DQ<17>
MEM_A_DQ<16>
MEM_A_DQ<15>
MEM_A_DQ<14>
MEM_A_DQ<13>
MEM_A_DQ<12>
MEM_A_DQ<11>
MEM_A_DQ<10>
MEM_A_DQ<9>
MEM_A_DQ<8>
MEM_A_DQ<7>
MEM_A_DQ<6>
MEM_A_DQ<5>
MEM_A_DQ<4>
MEM_A_DQ<3>
MEM_A_DQ<2>
MEM_A_DQ<1>
MEM_A_DQ<0>

MEM_A_DM<7>
MEM_A_DM<6>
MEM_A_DM<5>
MEM_A_DM<4>
MEM_A_DM<3>
MEM_A_DM<2>
MEM_A_DM<1>
MEM_A_DM<0>

BB10

BB12

AW12

AY12

BA12

BC32

AW32

BA35

AY36

BA32

BB32

BA34

AY35

BC36

AW36

BA39

AY40

BA36

BB36

BA38

AY39

BB40

AW40

AV42

AV41

BA40

BC40

AW42

AW41

AT40

AT41

AP41

AN40

AU40

AU41

AR41

AP42

BA11

BB34

BB38

AY43

AR42

AT4

AT3

AV2

AV3

AR4

AR3

AU2

AU3

AY4

AY3

BB3

BC3

AW4

AW3

BA3

BB2

BB5

BA5

BA8

BC8

BB4

BC4

BA7

AY8

BA9

BB8

BB9

AT5

BA2

AY7

A

8

76

MCP Memory Interface

SYNC_MASTER=T18_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

5

4

3

2

SCALE

NONE

051-8071

SHT

SYNC_DATE=06/06/2008

OF

15

1

A

REV.

B

98

87

www.vinafix.vn

D

8

16 23

C

B

A

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

8

76

=PP1V8R1V5_S0_MCP_MEM

R1610

R1611

40.2

1/16W
MF-LF

6

5

4

3

21

OMIT

U1400

MCP79-TOPO-B

BGA

TP_MEM_A_CLK5P

7

TP_MEM_A_CLK5N

7

TP_MEM_A_CLK4P

7

TP_MEM_A_CLK4N

7

TP_MEM_A_CLK3P

7

TP_MEM_A_CLK3N

7

TP_MEM_A_CS_L<2>

7

TP_MEM_A_CS_L<3>

7

TP_MEM_A_ODT<2>

7

TP_MEM_A_ODT<3>

7

TP_MEM_A_CKE<2>

7

TP_MEM_A_CKE<3>

7

PP1V05_S0_MCP_PLL_CORE

23

1

40.2

1%
1/16W
MF-LF

402

2

1

1%

402

2

87 mA (A01)

89

89

MCP_MEM_COMP_VDD
MCP_MEM_COMP_GND

17 mA
12 mA
19 mA
39 mA

AU33

MCLK0B_2_P

AU34

MCLK0B_2_N

BB24

MCLK0B_1_P

BC24

MCLK0B_1_N

BA21

MCLK0B_0_P

BB21

MCLK0B_0_N

AU17

MCS0B_0#

AR15

MCS0B_1#

AN17

MODT0B_0

AN15

MODT0B_1

AV23

MCKE0B_0

AN25

MCKE0B_1

T27

+V_PLL_XREF_XS

U28

+V_PLL_DP

U27

+V_PLL_CORE

T28

+V_VPLL

AN41

MEM_COMP_VDD

AM41

MEM_COMP_GND

AA22

GND1

AP12

GND2

G30

GND3

P10

GND4

T10

GND5

T6

GND6

V10

GND7

V34

GND8

W5

GND9

AA39

GND10

AB22

GND11

AB7

GND12

AD22

GND13

AE20

GND14

AF24

GND15

AG24

GND16

AH35

GND17

AK7

GND18

AM28

GND19

AT25

GND20

AP30

GND21

AR36

GND22

AU10

GND23

F28

GND24

BC21

GND25

AY9

GND26

BC9

GND27

D34

GND28

F24

GND29

G32

GND30

H31

GND31

K7

GND32

M38

GND33

M5

GND34

M6

GND35

M7

GND36

M9

GND37

N39

GND38

N8

GND39

P33

GND40

P34

GND41

P37

GND42

P4

GND43

P40

GND44

P7

GND45

R36

GND46

R40

GND47

R43

GND48

R5

GND49

T18

GND50

T20

GND51

AK11

GND52

T24

GND53

T26

GND54

5

(4 OF 11)

MCLK1B_2_P
MCLK1B_2_N

MCLK1B_1_P
MCLK1B_1_N

MCLK1B_0_P
MCLK1B_0_N

MEMORY CONTROL 0B

MEMORY CONTROL 1B

+VDD_MEM1
+VDD_MEM2
+VDD_MEM3
+VDD_MEM4
+VDD_MEM5
+VDD_MEM6
+VDD_MEM7
+VDD_MEM8

+VDD_MEM9
+VDD_MEM10
+VDD_MEM11
+VDD_MEM12
+VDD_MEM13
+VDD_MEM14
+VDD_MEM15
+VDD_MEM16
+VDD_MEM17
+VDD_MEM18
+VDD_MEM19
+VDD_MEM20
+VDD_MEM21
+VDD_MEM22
+VDD_MEM23
+VDD_MEM24
+VDD_MEM25
+VDD_MEM26
+VDD_MEM27
+VDD_MEM28
+VDD_MEM29
+VDD_MEM30
+VDD_MEM31
+VDD_MEM32
+VDD_MEM33
+VDD_MEM34
+VDD_MEM35
+VDD_MEM36
+VDD_MEM37
+VDD_MEM38
+VDD_MEM39
+VDD_MEM40
+VDD_MEM41
+VDD_MEM42
+VDD_MEM43
+VDD_MEM44
+VDD_MEM45

MCS1B_0#
MCS1B_1#

MODT1B_0
MODT1B_1

MCKE1B_0
MCKE1B_1

MRESET0#

GND55
GND56
GND57
GND58
GND59
GND60
GND61
GND62
GND63
GND64

BA41

BB41

AY23

BA23

BA20

AY20

BC16

BA13

AY16

BC13

BA30

BA31

AY32

AM17

AM19

AM21

AM23

AM25

AM27

AM29

AN16

BC29

AN20

AN24

AT17

AP16

AN22

AP20

AP24

AV16

AR16

AR20

AR24

AW15

AP22

AP18

AU16

AN18

AU24

AT21

AY29

AV24

AU20

AU22

AW27

BC17

AV20

AY17

AY18

AM15

AU18

AY25

AY26

AW19

AW24

BC25

AL30

AM31

T33

T34

T35

T37

T38

T7

T9

U18

U20

U22

4

TP_MEM_B_CLK5P
TP_MEM_B_CLK5N

TP_MEM_B_CLK4P
TP_MEM_B_CLK4N

TP_MEM_B_CLK3P
TP_MEM_B_CLK3N

TP_MEM_B_CS_L<2>
TP_MEM_B_CS_L<3>

TP_MEM_B_ODT<2>
TP_MEM_B_ODT<3>

TP_MEM_B_CKE<2>
TP_MEM_B_CKE<3>

MCP_MEM_RESET_L

TP or NC for DDR2.

=PP1V8R1V5_S0_MCP_MEM

4771 mA (A01, DDR3)

7

7

7

7

7

7

7

7

7

7

7

29

OUT

8

16 23

D

C

B

MCP Memory Misc

051-8071

SHT

SYNC_DATE=06/06/2008

OF

16 98

1

A

REV.

B

SYNC_MASTER=T18_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

3

2

SCALE

NONE

87

www.vinafix.vn

D

C

B

A

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

8

76

6

5

4

OMIT

U1400

MCP79-TOPO-B

BGA

=PEG_D2R_P<0>

9

IN

=PEG_D2R_N<0>

9

IN

=PEG_D2R_P<1>

9

IN

=PEG_D2R_N<1>

9

IN

=PEG_D2R_P<2>

9

IN

=PEG_D2R_N<2>

9

IN

=PEG_D2R_P<3>

9

IN

=PEG_D2R_N<3>

9

IN

=PEG_D2R_P<4>

9

IN

=PEG_D2R_N<4>

9

IN

=PEG_D2R_P<5>

9

IN

=PEG_D2R_N<5>

9

IN

=PEG_D2R_P<6>

9

IN

=PEG_D2R_N<6>

9

IN

=PEG_D2R_P<7>

9

IN

=PEG_D2R_N<7>

9

IN

=PEG_D2R_P<8>

9

IN

=PEG_D2R_N<8>

9

IN

=PEG_D2R_P<9>

9

IN

=PEG_D2R_N<9>

9

IN

=PEG_D2R_P<10>

9

IN

=PEG_D2R_N<10>

9

IN

=PEG_D2R_P<11>

9

IN

=PEG_D2R_N<11>

9

IN

=PEG_D2R_P<12>

9

IN

=PEG_D2R_N<12>

9

IN

=PEG_D2R_P<13>

9

IN

=PEG_D2R_N<13>

9

IN

=PEG_D2R_P<14>

9

IN

=PEG_D2R_N<14>

9

IN

=PEG_D2R_P<15>

9

IN

=PEG_D2R_N<15>

9

IN

PEG_PRSNT_L

9

IN

MINI_CLKREQ_L

30

IN

PCIE_MINI_PRSNT_L

30

IN

FW_CLKREQ_L

35

IN

PCIE_FW_PRSNT_L

9

IN

EXCARD_CLKREQ_L

31

IN

PCIE_EXCARD_PRSNT_L

31

IN

TP_PE4_CLKREQ_L

7

TP_PE4_PRSNT_L

AUD_IP_PERIPHERAL_DET

58

IN

GMUX_JTAG_TCK_L

84

OUT

TP_MCP_GPIO_18

7

GMUX_JTAG_TDO

9

IN

PCIE_WAKE_L

7

30 31

IN

PCIE_MINI_D2R_P

7

30 90

IN

PCIE_MINI_D2R_N

7

30 90

IN

PCIE_FW_D2R_P

35 90

IN

PCIE_FW_D2R_N

35 90

IN

PCIE_EXCARD_D2R_P

7

31 90

IN

PCIE_EXCARD_D2R_N

7

31 90

IN

TP_PCIE_PE4_D2RP

7

TP_PCIE_PE4_D2RN

7

=PP1V05_S0_MCP_PEX_DVDD0

8

57 mA (A01, DVDD0 & 1)

Minimum 1.025V for Gen2 support Minimum 1.025V for Gen2 support

=PP1V05_S0_MCP_PEX_DVDD1

8

PP1V05_S0_MCP_PLL_PEX

23

84 mA (A01)

MCP_PEX_CLK_COMP

90

NO STUFF

1

R1710

2.37K

1%
1/16W
MF-LF
402

2

PLACEMENT_NOTE=Place within 12.7mm of U1400

F7

PE0_RX0_P

E7

PE0_RX0_N

D7

PE0_RX1_P

C7

PE0_RX1_N

E6

PE0_RX2_P

F6

PE0_RX2_N

E5

PE0_RX3_P

F5

PE0_RX3_N

E4

PE0_RX4_P

E3

PE0_RX4_N

C3

PE0_RX5_P

D3

PE0_RX5_N

G5

PE0_RX6_P

H5

PE0_RX6_N

J7

PE0_RX7_P

J6

PE0_RX7_N

J5

PE0_RX8_P

J4

PE0_RX8_N

L11

PE0_RX9_P

L10

PE0_RX9_N

L9

PE0_RX10_P

L8

PE0_RX10_N

L7

PE0_RX11_P

L6

PE0_RX11_N

N11

PE0_RX12_P

N10

PE0_RX12_N

N9

PE0_RX13_P

P9

PE0_RX13_N

N7

PE0_RX14_P

N6

PE0_RX14_N

N5

PE0_RX15_P

N4

PE0_RX15_N

Int PU

C9

PE0_PRSNT_16#

Int PU

D5

PEB_CLKREQ#/GPIO_49

D9

PEB_PRSNT#

Int PU

E8

PEC_CLKREQ#/GPIO_50

C10

PEC_PRSNT#

Int PU

M15

PED_CLKREQ#/GPIO_51

B10

PED_PRSNT#

Int PU

L16

PEE_CLKREQ#/GPIO_16

L18

PEE_PRSNT#/GPIO_46

Int PU

M16

PEF_CLKREQ#/GPIO_17

M18

PEF_PRSNT#/GPIO_47

Int PU

M17

PEG_CLKREQ#/GPIO_18

M19

PEG_PRSNT#/GPIO_48

F17

PE_WAKE#

K9

PE1_RX0_P

J9

PE1_RX0_N

H9

PE1_RX1_P

G9

PE1_RX1_N

F9

PE1_RX2_P

E9

PE1_RX2_N

H7

PE1_RX3_P

G7

PE1_RX3_N

T17

+DVDD0_PEX1

W19

+DVDD0_PEX2

U17

+DVDD0_PEX3

V19

+DVDD0_PEX4

W16

+DVDD0_PEX5

W17

+DVDD0_PEX6

W18

+DVDD0_PEX7

U16

+DVDD0_PEX8

T19

+DVDD1_PEX1

U19

+DVDD1_PEX2

T16

+V_PLL_PEX

A11

PEX_CLK_COMP

If PE0 interface is not used, ground DVDD0_PEX and AVDD0_PEX.
If PE1 interface is not used, ground DVDD1_PEX and AVDD1_PEX.

5

(5 OF 11)

Int PU

Int PU

Int PU

Int PU

Int PU

Int PU

Int PU (S5)

PE0_TX0_P

PE0_TX0_N

PE0_TX1_P

PE0_TX1_N

PE0_TX2_P

PE0_TX2_N

PE0_TX3_P

PE0_TX3_N

PE0_TX4_P

PE0_TX4_N

PE0_TX5_P

PE0_TX5_N

PE0_TX6_P

PE0_TX6_N

PE0_TX7_P

PE0_TX7_N

PE0_TX8_P

PE0_TX8_N

PE0_TX9_P

PE0_TX9_N
PE0_TX10_P
PE0_TX10_N
PE0_TX11_P
PE0_TX11_N
PE0_TX12_P
PE0_TX12_N
PE0_TX13_P
PE0_TX13_N
PE0_TX14_P
PE0_TX14_N
PE0_TX15_P
PE0_TX15_N

PCI EXPRESS

PE0_REFCLK_P
PE0_REFCLK_N

PE1_REFCLK_P
PE1_REFCLK_N

PE2_REFCLK_P
PE2_REFCLK_N

PE3_REFCLK_P
PE3_REFCLK_N

PE4_REFCLK_P
PE4_REFCLK_N

PE5_REFCLK_P
PE5_REFCLK_N

PE6_REFCLK_P
PE6_REFCLK_N

PEX_RST0#

PE1_TX0_P

PE1_TX0_N

PE1_TX1_P

PE1_TX1_N

PE1_TX2_P

PE1_TX2_N

PE1_TX3_P

PE1_TX3_N

+AVDD0_PEX1
+AVDD0_PEX2
+AVDD0_PEX3
+AVDD0_PEX4
+AVDD0_PEX5
+AVDD0_PEX6
+AVDD0_PEX7
+AVDD0_PEX8

+AVDD0_PEX9
+AVDD0_PEX10
+AVDD0_PEX11
+AVDD0_PEX12
+AVDD0_PEX13

+AVDD1_PEX1

+AVDD1_PEX2

+AVDD1_PEX3

C5

D4

C4

B4

A4

A3

B3

B2

C1

D1

D2

E1

E2

F2

F3

F4

G3

H4

H3

H2

H1

J1

J2

J3

K2

K3

L4

L3

M4

M3

M2

M1

E11

D11

G11

F11

J11

J10

G13

F13

J13

H13

L14

K14

N14

M14

K11

D8

C8

B8

A8

A7

B7

B6

C6

Y12

AA12

AB12

M12

P12

R12

N12

T12

U12

AC12

AD12

V12

W12

M13

N13

P13

=PEG_R2D_C_P<0>
=PEG_R2D_C_N<0>
=PEG_R2D_C_P<1>
=PEG_R2D_C_N<1>
=PEG_R2D_C_P<2>
=PEG_R2D_C_N<2>
=PEG_R2D_C_P<3>
=PEG_R2D_C_N<3>
=PEG_R2D_C_P<4>
=PEG_R2D_C_N<4>
=PEG_R2D_C_P<5>
=PEG_R2D_C_N<5>
=PEG_R2D_C_P<6>
=PEG_R2D_C_N<6>
=PEG_R2D_C_P<7>
=PEG_R2D_C_N<7>
=PEG_R2D_C_P<8>
=PEG_R2D_C_N<8>
=PEG_R2D_C_P<9>
=PEG_R2D_C_N<9>
=PEG_R2D_C_P<10>
=PEG_R2D_C_N<10>
=PEG_R2D_C_P<11>
=PEG_R2D_C_N<11>
=PEG_R2D_C_P<12>
=PEG_R2D_C_N<12>
=PEG_R2D_C_P<13>
=PEG_R2D_C_N<13>
=PEG_R2D_C_P<14>
=PEG_R2D_C_N<14>
=PEG_R2D_C_P<15>
=PEG_R2D_C_N<15>

PEG_CLK100M_P
PEG_CLK100M_N

PCIE_CLK100M_MINI_P
PCIE_CLK100M_MINI_N

PCIE_CLK100M_FW_P
PCIE_CLK100M_FW_N

PCIE_CLK100M_EXCARD_P
PCIE_CLK100M_EXCARD_N

TP_PCIE_CLK100M_PE4P
TP_PCIE_CLK100M_PE4N

TP_PCIE_CLK100M_PE5P
TP_PCIE_CLK100M_PE5N

TP_PCIE_CLK100M_PE6P
TP_PCIE_CLK100M_PE6N

PCIE_RESET_L

PCIE_MINI_R2D_C_P
PCIE_MINI_R2D_C_N

PCIE_FW_R2D_C_P
PCIE_FW_R2D_C_N

PCIE_EXCARD_R2D_C_P
PCIE_EXCARD_R2D_C_N

TP_PCIE_PE4_R2D_CP
TP_PCIE_PE4_R2D_CN

=PP1V05_S0_MCP_PEX_AVDD0

=PP1V05_S0_MCP_PEX_AVDD1

4

206 mA (A01, AVDD0 & 1)

3

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

69 90

OUT

69 90

OUT

30 90

OUT

30 90

OUT

35 90

OUT

35 90

OUT

31 90

OUT

31 90

OUT

7

7

7

7

7

25

OUT

30 90

OUT

30 90

OUT

35 90

OUT

35 90

OUT

31 90

OUT

31 90

OUT

8

8

21

D

C

B

MCP PCIe Interfaces

SYNC_MASTER=T18_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

3

2

SCALE

NONE

051-8071

SHT

SYNC_DATE=06/06/2008

OF

17 98

1

A

REV.

B

87

www.vinafix.vn

D

=PP3V3_ENET_MCP_RMGT

8

18 23

C

=PP3V3_S5_MCP_GPIO

8

20

Interface Mode

MCP Signal

=MCP_HDMI_TXC_P/N
=MCP_HDMI_TXD_P/N<0>
=MCP_HDMI_TXD_P/N<1>
=MCP_HDMI_TXD_P/N<2>
=MCP_HDMI_DDC_CLK
=MCP_HDMI_DDC_DATA

B

=MCP_HDMI_HPD
DP_IG_AUX_CH_P/N

NOTE: 1M pull-down required on DP_IG_CA_DET if DP not used.
NOTE: 20K pull-down required on DP_HPD_DET.
NOTE: 1K pull-down required on DP_IG_AUX_CH_N if DP is used.

NOTE: HDMI port requires level-shifting. IFP interface can
be used to provide HDMI or dual-channel TMDS without
level-shifters.

TMDS/HDMI

TMDS_IG_TXC_P/N
TMDS_IG_TXD_P/N<0>
TMDS_IG_TXD_P/N<1>
TMDS_IG_TXD_P/N<2>
TMDS_IG_DDC_CLK
TMDS_IG_DDC_DATA
TMDS_IG_HPD
TP_DP_IG_AUX_CHP/N

LVDS: Power +VDD_IFPx at 1.8V
Dual-channel TMDS: Power +VDD_IFPx at 3.3V

DisplayPort

DP_IG_ML_P/N<3>
DP_IG_ML_P/N<2>
DP_IG_ML_P/N<1>
DP_IG_ML_P/N<0>
DP_IG_DDC_CLK
DP_IG_DDC_DATA
DP_IG_HPD
DP_IG_AUX_CH_P/N

A

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

8

76

43

R1810

49.9

1/16W
MF-LF

R1811

49.9

1/16W
MF-LF

R1820

47K

1/16W
MF-LF

7

BI

6

5

4

3

21

OMIT

U1400

MCP79-TOPO-B

BGA

(6 OF 11)

ENET_RXD<0>

32 92

IN

ENET_RXD<1>

32 92

IN

ENET_RXD<2>

32 92

IN

ENET_RXD<3>

32 92

IN

ENET_CLK125M_RXCLK

32 92

IN

ENET_RX_CTRL

32 92

IN

=MCP_MII_RXER

9

IN

=MCP_MII_COL

9

IN

=MCP_MII_CRS

9

1

1%

402

2

1

1%

402

2

IN

TP_ENET_INTR_L

7

PP1V05_ENET_MCP_PLL_MAC

23

5 mA (A01)

MCP_MII_COMP_VDD

92

MCP_MII_COMP_GND

92

TP_MCP_RGB_DAC_RSET

24

TP_MCP_RGB_DAC_VREF

24

C23

RGMII_RXD0

B23

RGMII_RXD1

E24

RGMII_RXD2

A24

RGMII_RXD3

A23

RGMII_RXC/MII_RXCLK

C22

RGMII_RXCTL/MII_RXDV

F23

MII_RXER/GPIO_36

B26

MII_COL/GPIO_20/MSMB_DATA

B22

MII_CRS/GPIO_21/MSMB_CLK

J22

RGMII_INTR/GPIO_35

T23

+V_DUAL_MACPLL

C27

MII_COMP_VDD

B27

MII_COMP_GND

C39

RGB_DAC_RSET

B38

RGB_DAC_VREF

+3.3V_DUAL_RMGT1
+3.3V_DUAL_RMGT2

+V_DUAL_RMGT1
+V_DUAL_RMGT2

LAN

RGMII_TXC/MII_TXCLK

RGMII_TXCTL/MII_TXEN

RGMII_PWRDWN/GPIO_37

RGMII_TXD0
RGMII_TXD1
RGMII_TXD2
RGMII_TXD3

RGMII_MDC

RGMII_MDIO

BUF_25MHZ

MII_RESET#

+V_RGB_DAC

+V_TV_DAC

DDC_DATA0

RGB_DAC_RED

MCP_TV_DAC_RSET

24 90

OUT

MCP_TV_DAC_VREF

24 90

OUT

MCP_CLK27M_XTALIN

24

1

5%

402

2

IN

MCP_CLK27M_XTALOUT

24

OUT

LPCPLUS_GPIO
DP_IG_CA_DET

81

IN

LVDS_IG_BKL_PWM

9

OUT

LVDS_IG_BKL_ON

9

OUT

LVDS_IG_PANEL_PWR

9

OUT

=MCP_HDMI_TXC_P

9

OUT

=MCP_HDMI_TXC_N

9

OUT

=MCP_HDMI_TXD_P<0>

9

OUT

=MCP_HDMI_TXD_N<0>

9

OUT

=MCP_HDMI_TXD_P<1>

9

OUT

=MCP_HDMI_TXD_N<1>

9

OUT

=MCP_HDMI_TXD_P<2>

9

OUT

=MCP_HDMI_TXD_N<2>

9

OUT

DP_IG_AUX_CH_P

81 90

OUT

DP_IG_AUX_CH_N

81 90

OUT

=DVI_HPD_GMUX_INT

9

IN

=MCP_HDMI_HPD

9

IN

=PP3V3R1V8_S0_MCP_IFP_VDD

8

24

190 mA (A01, 1.8V)

PP3V3_S0_MCP_VPLL

24

16 mA (A01)

=PP1V05_S0_MCP_HDMI_VDD

8

24

95 mA (A01)

MCP_HDMI_RSET

24 90

OUT

MCP_HDMI_VPROBE

24 90

OUT

(See below)

(See below)

8 mA
8 mA

E36

TV_DAC_RSET

A35

TV_DAC_VREF

C38

XTALIN_TV

D38

XTALOUT_TV

E16

GPIO_6/FERR*/IGPU_GPIO_6

B15

GPIO_7/NFERR*/IGPU_GPIO_7

G39

LCD_BKL_CTL/GPIO_57

E37

LCD_BKL_ON/GPIO_59

F40

LCD_PANEL_PWR/GPIO_58

D35

HDMI_TXC_P/ML0_LANE3_P

E35

HDMI_TXC_N/ML0_LANE3_N

G35

HDMI_TXD0_P/ML0_LANE2_P

F35

HDMI_TXD0_N/ML0_LANE2_N

F33

HDMI_TXD1_P/ML0_LANE1_P

G33

HDMI_TXD1_N/ML0_LANE1_N

J33

HDMI_TXD2_P/ML0_LANE0_P

H33

HDMI_TXD2_N/ML0_LANE0_N

D43

DP_AUX_CH0_P

C43

DP_AUX_CH0_N

C31

HPLUG_DET2/GPIO_22

F31

HPLUG_DET3

M27

+VDD_IFPA

M26

+VDD_IFPB

M28

+V_PLL_IFPAB

M29

+V_PLL_HDMI

T25

+VDD_HDMI

J31

HDMI_RSET

J30

HDMI_VPROBE

DACS

TV / Component
C / Pr
Y / Y
Comp / Pb

RGB_DAC_GREEN

RGB_DAC_BLUE

RGB_DAC_HSYNC
RGB_DAC_VSYNC

RGB ONLY

TV_DAC_RED

TV_DAC_GREEN

TV_DAC_BLUE

TV_DAC_HSYNC/GPIO_44
TV_DAC_VSYNC/GPIO_45

IFPA_TXC_P
IFPA_TXC_N

IFPA_TXD0_P
IFPA_TXD0_N
IFPA_TXD1_P
IFPA_TXD1_N
IFPA_TXD2_P
IFPA_TXD2_N
IFPA_TXD3_P
IFPA_TXD3_N

IFPB_TXC_P
IFPB_TXC_N

IFPB_TXD4_P
IFPB_TXD4_N
IFPB_TXD5_P
IFPB_TXD5_N
IFPB_TXD6_P
IFPB_TXD6_N
IFPB_TXD7_P

FLAT PANEL

IFPB_TXD7_N

DDC_CLK2/GPIO_23

DDC_DATA2/GPIO_24

DDC_DATA3

IFPAB_RSET

IFPAB_VPROBE

MII_VREF

DDC_CLK0

DDC_CLK3

J24

K24

U23

V23

E28

B24

C24

C25

D25

D24

C26

D21

C21

G23

E23

J23

J32

K32

B31

A31

B39

A39

B40

A40

A41

A36

B36

C36

D36

C37

B35

C35

B32

A32

D32

C32

D33

C33

B34

C34

L31

K31

J29

H29

L29

K29

L30

K30

N30

M30

C30

B30

D31

E31

E32

G31

GPIOs 57-59 (if LCD panel is used):

In MCP79 these pins have undocumented internal
pull-ups (~10K to 3.3V S0). To ensure pins are low
by default, pull-downs (1K or stronger) must be used.

=DVI_HPD_GMUX_INT:

Alias to DVI_HPD for systems using IFP for DVI.
Alias to GMUX_INT for systems with GMUX.
Alias to HPLUG_DET2 for other systems.
Pull-down (20k) required in all cases.

5

4

=PP3V3_ENET_MCP_RMGT

=PP1V05_ENET_MCP_RMGT

MCP_MII_VREF

ENET_TXD<0>
ENET_TXD<1>
ENET_TXD<2>
ENET_TXD<3>

ENET_CLK125M_TXCLK
ENET_TX_CTRL

ENET_MDC
ENET_MDIO

TP_ENET_PWRDWN_L

MCP_CLK25M_BUF0_R

ENET_RESET_L

PP3V3_S0_MCP_DAC

103 mA
103 mA

MCP_DDC_CLK0
MCP_DDC_DATA0

TP_MCP_RGB_RED
TP_MCP_RGB_GREEN
TP_MCP_RGB_BLUE

TP_MCP_RGB_HSYNC
TP_MCP_RGB_VSYNC

CRT_IG_R_C_PR
CRT_IG_G_Y_Y
CRT_IG_B_COMP_PB

CRT_IG_HSYNC
CRT_IG_VSYNC

LVDS_IG_A_CLK_P
LVDS_IG_A_CLK_N

LVDS_IG_A_DATA_P<0>
LVDS_IG_A_DATA_N<0>
LVDS_IG_A_DATA_P<1>
LVDS_IG_A_DATA_N<1>
LVDS_IG_A_DATA_P<2>
LVDS_IG_A_DATA_N<2>
LVDS_IG_A_DATA_P<3>
LVDS_IG_A_DATA_N<3>

LVDS_IG_B_CLK_P
LVDS_IG_B_CLK_N

LVDS_IG_B_DATA_P<0>
LVDS_IG_B_DATA_N<0>
LVDS_IG_B_DATA_P<1>
LVDS_IG_B_DATA_N<1>
LVDS_IG_B_DATA_P<2>
LVDS_IG_B_DATA_N<2>
LVDS_IG_B_DATA_P<3>
LVDS_IG_B_DATA_N<3>

LVDS_IG_DDC_CLK
LVDS_IG_DDC_DATA

=MCP_HDMI_DDC_CLK
=MCP_HDMI_DDC_DATA

MCP_IFPAB_RSET
MCP_IFPAB_VPROBE

1

R1850

10K

5%
1/16W
MF-LF
402

2

8

18 23

83 mA (A01)

8

23

131 mA (A01)

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

7

OUT

OUT

24

206 mA (A01)

24

24

24

24

24

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

OUT

BI

OUT

OUT

3

23

32 92

32 92

32 92

32 92

32 92

32 92

32 92

32 92

1

5%

402

2

=PP3V3_S0_MCP_GPIO

1

R1861

100K

5%
1/16W
MF-LF
402

2

33 92

32 92

24 90

24 90

24 90

24 90

24 90

84 90

84 90

84 90

84 90

84 90

84 90

84 90

84 90

9

90

9

90

WF: IFP is capable of LVDS (1.8V) or TMDS (3.3V), need aliases

9

90

9

90

84 90

84 90

84 90

84 90

84 90

84 90

9

90

9

90

81

81

9

9

24 90

24 90

R1860

100K

1/16W
MF-LF

APPLE INC.

2

Network Interface Select

Interface

RGMII

MII 0

NOTE: All Apple products set strap to
MII, RGMII products will enable
feature via software. This
avoids a leakage issue since
MCP79 requires a S5 pull-up.

8

19 21

RGB DAC Disable:

Okay to float all RGB_DAC signals.
DDC_CLK0/DDC_DATA0 pull-ups still required.

TV DAC Disable:

Okay to float all TV_DAC signals.
Okay to float XTALIN_TV and XTALOUT_TV.
DDC_CLK0/DDC_DATA0 pull-ups still required.

ENET_TXD<0>

MCP Ethernet & Graphics

SYNC_MASTER=T18_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

051-8071

SHT

1

SYNC_DATE=06/06/2008

OF

18 98

1

D

C

B

A

REV.

B

87

www.vinafix.vn

6

5

4

3

21

OMIT

8.2K

8.2K

8.2K

8.2K

8.2K

D

NONE

DRAWING NUMBER

=PP3V3_S0_MCP_GPIO

8

18 21

21

21

21

21

21

051-8071

SHT

5%

5%

5%

5%

1/16W MF-LF

5%

SYNC_DATE=06/06/2008

402

MF-LF1/16W

402

MF-LF1/16W

402

MF-LF1/16W

402

402

MF-LF1/16W

D

C

B

A

REV.

B

OF

9819

U1400

MCP79-TOPO-B

BGA

Int PU

(7 OF 11)

PCI_GNT2#/GPIO_41/RS232_DTR#
PCI_GNT3#/GPIO_39/RS232_RTS#

PCI_GNT4#/GPIO_53/RS232_SOUT#

PCI_GNT1#/FANCTL2

PCI_PERR#/GPIO_43/RS232_DCD#

PCI_PME#/GPIO_30

Int PU (S5)

LPC_PWRDWN#/GPIO_54/EXT_NMI#

LPC PCIGND

PCI_GNT0#

PCI_CBE0#
PCI_CBE1#
PCI_CBE2#
PCI_CBE3#

PCI_DEVSEL#

PCI_FRAME#

PCI_IRDY#

PCI_PAR

PCI_SERR#
PCI_STOP#

PCI_RESET0#
PCI_RESET1#

PCI_CLK0
PCI_CLK1
PCI_CLK2

PCI_CLKIN

LPC_FRAME#

LPC_RESET0#

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_CLK0

GND98

GND99
GND100
GND101
GND102
GND103
GND104
GND105
GND106
GND107
GND108
GND109
GND110
GND111
GND112
GND113
GND114
GND115
GND116
GND117
GND118
GND119
GND120
GND121
GND122
GND123
GND124
GND125
GND126
GND127
GND128
GND129
GND130

R3

U10

R4

U11

P3

AA3

AA6

AA11

W10

AA9

Y4

AA10

Y1

AB9

AA7

Y2

T1

R10

R11

R6

R7

R8

R9

AD4

AE12

AE5

AD3

AD2

AD1

AD5

AE9

Y26

Y27

AB18

H34

AB20

AB21

AB23

AB24

AB25

AB26

AB27

AB28

AB34

AB37

AB4

AB40

AC22

AC36

AC40

AB33

AC5

AD16

AD17

AD18

AD19

AD20

AD24

AD25

AD26

AD27

AD28

AD33

AD34

TP_PCI_GNT0_L
TP_PCI_GNT1_L
GMUX_JTAG_TMS
GMUX_JTAG_TDI
MCP_RS232_SOUT_L

TP_PCI_C_BE_L<0>
TP_PCI_C_BE_L<1>
TP_PCI_C_BE_L<2>
TP_PCI_C_BE_L<3>

TP_PCI_DEVSEL_L
TP_PCI_FRAME_L
TP_PCI_IRDY_L
TP_PCI_PAR
TP_PCI_PERR_L
TP_PCI_SERR_L
TP_PCI_STOP_L

PM_LATRIGGER_L

MEM_VTT_EN_R
TP_PCI_RESET1_L

TP_PCI_CLK0
TP_PCI_CLK1
PCI_CLK33M_MCP_R

91

PCI_CLK33M_MCP

91

LPC_FRAME_R_L

43

LPC_PWRDWN_L

7

7

9

OUT

9

OUT

19

OUT

7

7

7

7

7

7

7

7

7 7

7

7

13

OUT

25

OUT

7

7

7

1

R1910

22

5%
1/16W
MF-LF
402

2

PLACEMENT_NOTE=Place close to pin R8

R1960

LPC_RESET_L

LPC_AD_R<0>
LPC_AD_R<1>
LPC_AD_R<2>
LPC_AD_R<3>

R1950
R1951
R1952
R1953

LPC_CLK33M_SMC_R

1

R1961

10K

5%
1/16W
MF-LF
402

2

Strap for Boot ROM Selection (See HDA_SDOUT)

22

22
22

21

5%

21

5%

21

5%

21

5%

21

5%

1/16W MF-LF

1/16W MF-LF22402

1/16W MF-LF22402

1/16W MF-LF

MF-LF1/16W

402

402

402

LPC_FRAME_L

LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>

7

41 43 84 91

OUT

7

41 43

OUT

25 84 91

OUT

7

41 43 84 91

BI

7

41 43 84 91

BI

7

41 43 84 91

BI

7

41 43 84 91

BI

25 91

OUT

PCI_REQ0_L

19 91

PCI_REQ1_L

19 91

CRTMUX_SEL_TV_L

19

OUT

AUD_IPHS_SWITCH_EN

9

58

OUT

MCP_RS232_SIN_L

19

IN

D

C

41 43

41 43

13 91

13 91

13 91

13 91

13 91

13 91

13 91

13 91

7

35

7

BI

BI

BI

BI

BI

BI

BI

BI

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

IN

IN

7

BI

MCP_DEBUG<0>
MCP_DEBUG<1>
MCP_DEBUG<2>
MCP_DEBUG<3>
MCP_DEBUG<4>
MCP_DEBUG<5>
MCP_DEBUG<6>
MCP_DEBUG<7>
TP_PCI_AD<8>
TP_PCI_AD<9>
TP_PCI_AD<10>
TP_PCI_AD<11>
TP_PCI_AD<12>
TP_PCI_AD<13>
TP_PCI_AD<14>
TP_PCI_AD<15>
TP_PCI_AD<16>
TP_PCI_AD<17>
TP_PCI_AD<18>
TP_PCI_AD<19>
TP_PCI_AD<20>
TP_PCI_AD<21>
TP_PCI_AD<22>
TP_PCI_AD<23>
TP_PCI_AD<24>
TP_PCI_AD<25>
TP_PCI_AD<26>
TP_PCI_AD<27>
TP_PCI_AD<28>
TP_PCI_AD<29>
TP_PCI_AD<30>
TP_PCI_AD<31>

TP_PCI_INTW_L
TP_PCI_INTX_L
TP_PCI_INTY_L
TP_PCI_INTZ_L

TP_PCI_TRDY_L

PM_CLKRUN_L

FW_PME_L
TP_LPC_DRQ0_L
LPC_SERIRQ

B

A

T2

PCI_REQ0#

V9

PCI_REQ1#/FANRPM2

T3

PCI_REQ2#/GPIO_40/RS232_DSR#

U9

PCI_REQ3#/GPIO_38/RS232_CTS#

T4

PCI_REQ4#/GPIO_52/RS232_SIN#

AC3

PCI_AD0

AE10

PCI_AD1

AC4

PCI_AD2

AE11

PCI_AD3

AB3

PCI_AD4

AC6

PCI_AD5

AB2

PCI_AD6

AC7

PCI_AD7

AC8

PCI_AD8

AA2

PCI_AD9

AC9

PCI_AD10

AC10

PCI_AD11

AC11

PCI_AD12

AA1

PCI_AD13

AA5

PCI_AD14

Y5

PCI_AD15

W3

PCI_AD16

W6

PCI_AD17

W4

PCI_AD18

W7

PCI_AD19

V3

PCI_AD20

W8

PCI_AD21

V2

PCI_AD22

W9

PCI_AD23

U3

PCI_AD24

W11

PCI_AD25

U2

PCI_AD26

U5

PCI_AD27

U1

PCI_AD28

U6

PCI_AD29

T5

PCI_AD30

U7

PCI_AD31

P2

PCI_INTW#

N3

PCI_INTX#

N2

PCI_INTY#

N1

PCI_INTZ#

Y3

PCI_TRDY#

AD11

PCI_CLKRUN#/GPIO_42

AE2

LPC_DRQ1#/GPIO_19

AE1

AE6

U24

U26

U39

U4

U8

V16

V17

V18

V20

V22

V24

V26

V27

V28

V33

V37

V4

V40

V7

W20

W22

W24

W36

W40

W43

Y16

Y17

Y18

Y19

Y20

Y22

Y24

Y25

LPC_DRQ0#
LPC_SERIRQ

GND65
GND66
GND67
GND68
GND69
GND70
GND71
GND72
GND73
GND74
GND75
GND76
GND77
GND78
GND79
GND80
GND81
GND82
GND83
GND84
GND85
GND86
GND87
GND88
GND89
GND90
GND91
GND92
GND93
GND94
GND95
GND96
GND97

Int PU
Int PU

MCP_RS232_SOUT_L

19

PCI_REQ0_L

19 91

PCI_REQ1_L

19 91

CRTMUX_SEL_TV_L

19

MCP_RS232_SIN_L

19

SYNC_MASTER=T18_MLB

APPLE INC.

R1989

R1990
R1991
R1992
R1994

MCP PCI & LPC

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

SCALE

8

76

5

4

3

2

1

87

www.vinafix.vn

D

C

B

A

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

8

76

6

SATA_HDD_R2D_C_P

38 90

OUT

SATA_HDD_R2D_C_N

38 90

OUT

SATA_HDD_D2R_N

38 90

IN

SATA_HDD_D2R_P

38 90

IN

SATA_ODD_R2D_C_P

38 90

OUT

SATA_ODD_R2D_C_N

38 90

OUT

SATA_ODD_D2R_N

38 90

IN

SATA_ODD_D2R_P

38 90

IN

TP_SATA_C_R2D_CP

7

TP_SATA_C_R2D_CN

7

TP_SATA_C_D2RN

7

TP_SATA_C_D2RP

7

TP_SATA_D_R2D_CP

7

TP_SATA_D_R2D_CN

7

TP_SATA_D_D2RN

7

TP_SATA_D_D2RP

7

TP_SATA_E_R2D_CP

7

TP_SATA_E_R2D_CN

7

TP_SATA_E_D2RN

7

TP_SATA_E_D2RP

7

TP_SATA_F_R2D_CP

7

TP_SATA_F_R2D_CN

7

TP_SATA_F_D2RN

7

TP_SATA_F_D2RP

7

TP_MCP_SATALED_L

7

PP1V05_S0_MCP_PLL_SATA

23

84 mA (A01)

=PP1V05_S0_MCP_SATA_DVDD0

8

43 mA (A01, DVDD0 & 1)

Minimum 1.025V for Gen2 support

=PP1V05_S0_MCP_SATA_DVDD1

9

=PP1V05_S0_MCP_SATA_AVDD0

8

127 mA (A01, AVDD0 & 1)

Minimum 1.025V for Gen2 support

=PP1V05_S0_MCP_SATA_AVDD1

9

MCP_SATA_TERMP

90

1

R2010

2

2.49K

1%
1/16W
MF-LF
402

If all SATA_Ax & Bx pins are not used, ground DVDD0_SATA and AVDD0_SATA.
If all SATA_Cx pins are not used, ground DVDD1_SATA and AVDD1_SATA.

5

AJ7

SATA_A0_TX_P

AJ6

SATA_A0_TX_N

AJ5

SATA_A0_RX_N

AJ4

SATA_A0_RX_P

AJ11

SATA_A1_TX_P

AJ10

SATA_A1_TX_N

AJ9

SATA_A1_RX_N

AK9

SATA_A1_RX_P

AK2

SATA_B0_TX_P

AJ3

SATA_B0_TX_N

AJ2

SATA_B0_RX_N

AJ1

SATA_B0_RX_P

AM4

SATA_B1_TX_P

AL3

SATA_B1_TX_N

AL4

SATA_B1_RX_N

AK3

SATA_B1_RX_P

AN1

SATA_C0_TX_P

AM1

SATA_C0_TX_N

AM2

SATA_C0_RX_N

AM3

SATA_C0_RX_P

AP3

SATA_C1_TX_P

AP2

SATA_C1_TX_N

AN3

SATA_C1_RX_N

AN2

SATA_C1_RX_P

E12

SATA_LED#

AE16

+V_PLL_SATA

AF19

+DVDD0_SATA1

AG16

+DVDD0_SATA2

AG17

+DVDD0_SATA3

AG19

+DVDD0_SATA4

AH17

+DVDD1_SATA1

AH19

+DVDD1_SATA2

AJ12

+AVDD0_SATA1

AN11

+AVDD0_SATA2

AK12

+AVDD0_SATA3

AK13

+AVDD0_SATA4

AL12

+AVDD0_SATA5

AM11

+AVDD0_SATA6

AM12

+AVDD0_SATA7

AN12

+AVDD0_SATA8

AL13

+AVDD0_SATA9

AN14

+AVDD1_SATA1

AL14

+AVDD1_SATA2

AM13

+AVDD1_SATA3

AM14

+AVDD1_SATA4

AE3

SATA_TERMP

5

OMIT

U1400

MCP79-TOPO-B

BGA

(8 OF 11)

SATA

USB_OC2#/GPIO_27/MGPIO
USB_OC3#/GPIO_28/MGPIO

USB

USB_OC0#/GPIO_25
USB_OC1#/GPIO_26

USB_RBIAS_GND

4

USB0_P
USB0_N

USB1_P
USB1_N

USB2_P
USB2_N

USB3_P
USB3_N

USB4_P
USB4_N

USB5_P
USB5_N

USB6_P
USB6_N

USB7_P
USB7_N

USB8_P
USB8_N

USB9_P
USB9_N

USB10_P
USB10_N

USB11_P
USB11_N

+V_PLL_USB

GND131
GND132
GND133
GND134
GND135
GND136
GND137
GND138
GND139
GND140
GND141
GND142
GND143
GND144
GND145
GND146
GND147
GND148
GND149
GND150
GND151
GND152
GND153
GND154
GND155
GND156
GND157
GND158
GND159
GND160

4

External A

C29

D29

C28

D28

A28

B28

F29

G29

K27

L27

J26

J27

F27

G27

D27

E27

K25

L25

H25

J25

F25

G25

K23

L23

L21

K21

J21

H21

L28

A27

AD35

AD37

AD38

AE22

AE24

AE39

AE4

AD6

AF16

AF17

AF18

AF20

AF22

AF26

AF27

AF28

AF33

AF34

AF37

AF40

AG18

AG20

AG22

AG26

AG36

AG40

AH18

AH20

AH22

AH24

USB_EXTA_P
USB_EXTA_N

AirPort (PCIe Mini-Card)

USB_MINI_P
USB_MINI_N

External D

USB_EXTD_P
USB_EXTD_N

Camera

USB_CAMERA_P
USB_CAMERA_N

IR

USB_IR_P
USB_IR_N

Geyser Trackpad/Keyboard

USB_TPAD_P
USB_TPAD_N

Bluetooth

USB_BT_P
USB_BT_N

External B

USB_EXTB_P
USB_EXTB_N

ExpressCard

USB_EXCARD_P
USB_EXCARD_N

External C

USB_EXTC_P
USB_EXTC_N

TP_USB_10P
TP_USB_10N

TP_USB_11P
TP_USB_11N

PP3V3_S0_MCP_PLL_USB

MCP_USB_RBIAS_GND

91

19 mA (A01)

R2060

1/16W
MF-LF

806

3

39 91

BI

39 91

BI

9

91

BI

9

91

BI

9

91

BI

9

91

BI

30 91

BI

30 91

BI

40 91

BI

40 91

BI

49 91

BI

49 91

BI

30 91

BI

30 91

BI

39 91

BI

39 91

BI

31 91

BI

31 91

BI

8.2K

1/16W
MF-LF

1

R2051

8.2K

5%
1/16W
MF-LF
402

2

1

R2052

5%

402

2

8.2K

1/16W
MF-LF

5%

402

91 96 98

BI

91 96 98

BI

7

7

7

23

1

1%

402

2

R2050

21

=PP3V3_S5_MCP_GPIO

1

R2053

8.2K

5%
1/16W
MF-LF
402

2

1

2

USB_EXTA_OC_L
USB_EXTB_OC_L
USB_EXTC_OC_L
EXCARD_OC_L

8

18

39

IN

39

IN

98

IN

31 42

IN

D

C

B

MCP SATA & USB

SYNC_MASTER=T18_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

3

2

SCALE

NONE

051-8071

SHT

SYNC_DATE=06/06/2008

OF

1

A

REV.

B

9820

87

www.vinafix.vn

6

5

4

3

21

OMIT

U1400

MCP79-TOPO-B

BGA

(9 OF 11)

D

=PP3V3R1V5_S0_MCP_HDA

8

21 23

1

R2110

49.9

1%
1/16W
MF-LF
402

2

PP3V3_G3_RTC

22 25

1

1/16W
MF-LF

1

R2121

49.9K

1%

1%
1/16W
MF-LF

402

402

2

2

R2120

C

49.9K

HDA_SDIN0

53 91

IN

TP_MLB_RAM_SIZE

7

TP_MLB_RAM_VENDOR

7

(MXM_OK for MXM systems)

MCP_HDA_PULLDN_COMP

91

PP1V05_S0_MCP_PLL_NV

23

37 mA (A01)

=SPI_CS1_R_L_USE_MLB

9

43

OUT

SMC_ADAPTER_EN

33 36 41 42

IN

TP_SB_A20GATE

7

TP_MCP_KBDRSTIN_L

7

SMC_WAKE_SCI_L

41

IN

SMC_RUNTIME_SCI_L

41

IN

20 mA
17 mA

SM_INTRUDER_L

TP_MCP_LID_L
PM_BATLOW_L

41

IN

PM_DPRSLPVR

61 88

IN

PM_PWRBTN_L

41

IN

PM_SYSRST_DEBOUNCE_L

25

IN

RTC_RST_L

PM_RSMRST_L

41

IN

MCP_PS_PWRGD

25

IN

MCP_CPU_VLD

IN

JTAG_MCP_TDI

6

13

IN

JTAG_MCP_TDO

6

OUT

JTAG_MCP_TMS

6

13

IN

JTAG_MCP_TRST_L

6

13

IN

JTAG_MCP_TCK

6

13

B

IN

25

IN

25

OUT

25

IN

25

OUT

MCP_CLK25M_XTALIN
MCP_CLK25M_XTALOUT

RTC_CLK32K_XTALIN
RTC_CLK32K_XTALOUT

R2150

1/16W
MF-LF

10K

1

5%

402

2

1

R2151

100K

5%
1/16W
MF-LF
402

2

G15

HDA_SDATA_IN0

Int PD

J14

HDA_SDATA_IN1_GPIO_2/PS2_KB_CLK

Int PD

J15

HDA_SDATA_IN2_GPIO_3/PS2_KB_DATA

Int PD

A15

HDA_PULLDN_COMP

AE18

+V_PLL_NV_H

AE17

+V_PLL_SP_SPREF

L24

GPIO_1/PWRDN_OK/SPI_CS1

L26

GPIO_12_SUS_STAT_ACCLMTR_EXT_TRIG_L

K13

A20GATE

L13

KBRDRSTIN*

C19

SIO_PME*

C18

EXT_SMI/GPIO_32*

B20

INTRUDER*

M25

LID*

M24

LLB*

M22

CPU_DPRSLPVR

C16

PWRBTN*

D16

RSTBTN*

C20

RTC_RST*

D20

PWRGD_SB

E20

PS_PWRGD

Int PU
Int PU
Int PU (S5)

Int PU (S5)
Int PU (S5)

Int PU (S5)
Int PU

Int PU (S5)

CPU_VLD

E19

JTAG_TDI

F19

JTAG_TDO

J19

JTAG_TMS

J18

JTAG_TRST*

G19

JTAG_TCK

A16

XTALIN

B16

XTALOUT

A19

XTALIN_RTC

B19

XTALOUT_RTC

Int PU

Int PU

HDA

HDA_DOCK_EN*_GPIO_4/PS2_MS_CLK

HDA_DOCK_RST*_GPIO_5/PS2_MS_DATA

(MGPIO2)

MISC

(MGPIO3)

+V_DUAL_HDA1
+V_DUAL_HDA2

HDA_SDATA_OUT

HDA_BITCLK

HDA_RESET*

HDA_SYNC

SLP_RMGT*

THERM_DIODE_P
THERM_DIODE_N

MCP_VID0/GPIO_13
MCP_VID1/GPIO_14
MCP_VID2/GPIO_15

SMB_CLK0

SMB_DATA0

SMB_CLK1/MSMB_CLK

SMB_DATA1/MSMB_DATA

SMB_ALERT*/GPIO_64

FANRPM0/GPIO_60
FANCTL0/GPIO_61
FANRPM1/GPIO_63
FANCTL1/GPIO_62

CPUVDD_EN

SPI_CS0/GPIO_10
SPI_CLK/GPIO_11

SPI_DI/GPIO_8
SPI_DO/GPIO_9

SUS_CLK/GPIO_34

BUF_SIO_CLK

TEST_MODE_EN

PKG_TEST

SLP_S3*

SLP_S5*

SPKR

J16

K16

F15

E15

K15

L15

K17

L17

G17

J17

H17

B11

C11

L20

M20

M21

C13

L19

K19

G21

F21

M23

B12

A12

D12

C12

D17C17

C14

D13

C15

B14

B18

AE7

K22

L22

=PP3V3R1V5_S0_MCP_HDA

1

R2160

8.2K

5%
1/16W
MF-LF
402

2

HDA_SDOUT_R

21 91

HDA_BIT_CLK_R

21 91

HDA_RST_R_L

21 91

HDA_SYNC_R

21 91

MCP_GPIO_4
AUD_I2C_INT_L

PM_SLP_S3_L
PM_SLP_RMGT_L
PM_SLP_S4_L

MCP_THMDIODE_P
MCP_THMDIODE_N

MCP_VID<0>
MCP_VID<1>
MCP_VID<2>

MCP_SPKR

SMBUS_MCP_0_CLK
SMBUS_MCP_0_DATA
SMBUS_MCP_1_CLK
SMBUS_MCP_1_DATA
AP_PWR_EN

MEM_EVENT_L
ODD_PWR_EN_L
SMC_IG_THROTTLE_L
ARB_DETECT

MCP_CPUVDD_EN

SPI_CS0_R_L
SPI_CLK_R
SPI_MISO
SPI_MOSI_R

PM_CLK32K_SUSCLK_R
TP_MCP_BUF_SIO_CLK

MCP_TEST_MODE_EN

1

R2163

10K

5%
1/16W
MF-LF
402

2

8

21 23

7 mA (A01)

R2171

22

5%
1/16W
MF-LF

402

R2173

22

5%
1/16W
MF-LF

402

21

21

21

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

IN

21

OUT

OUT

OUT

IN

OUT

OUT

7

1

2

BI

BI

R2190

1K

1%
1/16W
MF-LF
402

R2170

22

21

5%
1/16W
MF-LF

402

R2172

22

21

5%
1/16W
MF-LF

402

21 58

7

33 36 41 67 82 84

9

39 41 42 67

47 96

47 96

21 64

21 64

21 64

7

13 44 91

7

13 44 91

44 91

44 91

21 30 33

21 27 28 41

38

21 42

25 25

43 91

43 91

43 91

43 91

25 91

HDA_SDOUT

HDA_BIT_CLK

HDA_RST_L

HDA_SYNC

OUT

OUT

OUT

OUT

=PP3V3_S0_MCP

BOOT_MODE_SAFE

1

R2180

10K

5%
1/16W
MF-LF
402

2

9

OUT

BOOT_MODE_USER

1

R2181

10K

USER mode: Normal

5%
1/16W

SAFE mode: For ROMSIP

MF-LF
402

2

recovery

Connects to SMC for
automatic recovery.

53 91

9

53 91

53 91

D

BIOS Boot Select

91

I/F

LPC

PCI

SPI0

SPI1

SPI0 = SPI_CS0_L, SPI1 = SPI_CS1_L

R1961 and R2160 selects SPI0 ROM by
default, LPC+ debug card pulls
LPC_FRAME# high for SPI1 ROM override.

NOTE: MCP79 does not support FWH, only
LPC ROMs. So Apple designs will
not use LPC for BootROM override.

NOTE: MCP79 rev A01 does not support

8

22 23

SPI1 option. Rev B01 will.

HDA_SDOUT

LPC_FRAME#

0

0

1

1

BUF_SIO_CLK Frequency

Frequency

24 MHz

14.31818 MHz

HDA_SYNC

0

1

0

1

C

1

0

SPI Frequency Select

Frequency

31 MHz

0

42 MHz 0

25 MHz

1 MHz

NOTE: Straps not provided on this page.

1

1

SPI_CLKSPI_DO

0

1

0

1

B

HDA Output Caps

For EMI Reduction on HDA interface

HDA_SDOUT_R
HDA_BIT_CLK_R

HDA_RST_R_L
HDA_SYNC_R

C2172

10PF

1

5%

50V

2

CERM

402

1

C2173

10PF

5%
50V

2

CERM
402

1

A

C2170

10PF

5%

50V

2

CERM

402

1

C2171

10PF

5%
50V

2

CERM
402

21 91

21 91

21 91

21 91

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

8

76

1

R2140

10K

5%
1/16W
MF-LF
402

2

1

R2141

10K

5%
1/16W
MF-LF
402

2

1

R2142

10K

5%
1/16W
MF-LF
402

2

=PP3V3_S0_MCP_GPIO

1

R2143

10K

5%
1/16W
MF-LF
402

2

MCP_GPIO_4
AUD_I2C_INT_L
MEM_EVENT_L
SMC_IG_THROTTLE_L

ARB_DETECT

1

R2147

100K

5%
1/16W
MF-LF
402

2

5

8

18 19

21

21 58

21 27 28 41

21 42

21

=PP3V3_S3_MCP_GPIO

2

R2154

100K

5%
1/16W
MF-LF
402

1

AP_PWR_EN

MCP_VID<0>
MCP_VID<1>
MCP_VID<2>

1

R2155

22K

5%
1/16W
MF-LF
402

2

1

R2156

22K

5%
1/16W
MF-LF
402

2

1

R2157

22K

5%
1/16W
MF-LF
402

2

4

21 30 33

21 64

21 64

21 64

3

8

MCP HDA & MISC

051-8071

SHT

SYNC_DATE=06/06/2008

OF

21 98

1

A

REV.

B

SYNC_MASTER=T18_MLB

APPLE INC.

2

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

87

www.vinafix.vn

6

5

4

3

21

OMIT

U1400

MCP79-TOPO-B

BGA

AH26

AH33

AH34

AH37

AH38

AJ39

D

C

B

A

AK10

AK33

AK34

AK37

AK40

AL36

AL40

AM10

AM16

AM18

AM20

AM22

AM24

AM26

AM30

AM34

AM35

AM37

AM38

AP26

AN28

AN30

AN39

AP10

AU26

AP14

AU14

AP28

AP32

AP34

AP36

AP37

AP40

AW23

AR28

AR32

AR40

AT10

AR12

AT13

AT29

AT33

AY21

AY22

AU12

AU28

AP33

AU32

AR30

AU36

AU38

AV28

AV32

AV36

AW11

AR43

AW43

AY10

AV12

AY30

AY33

AY34

AY37

AY38

AY41

(11 OF 11)

GND161
GND162
GND163
GND164
GND165
GND166

AJ8

GND167
GND168
GND169
GND170
GND171

AK4

GND172
GND173
GND174
GND175

AL5

GND176
GND177
GND178
GND179
GND180
GND181
GND182
GND183
GND184
GND185
GND186
GND187
GND188

AM5

GND189

AM6

GND190

AM7

GND191

AM9

GND192
GND193
GND194
GND195
GND196

AN4

GND197

Y7

GND198
GND199
GND200
GND201
GND202
GND203
GND204
GND205
GND206
GND207

AP4

GND208
GND209

AP7

GND210
GND211
GND212
GND213
GND214
GND215
GND216
GND217
GND218
GND219

AT6

GND220

AT7

GND221

AT9

GND222
GND223
GND224

L12

GND225
GND226
GND227
GND228
GND229
GND230
GND231
GND232

AU4

GND233

G28

GND234

F20

GND235
GND236
GND237
GND238

AV4

GND239

AV7

GND240
GND241

G20

GND242
GND243
GND244
GND245
GND246
GND247
GND248
GND249
GND250 GND342
GND251
GND252

GND253
GND254
GND255
GND256
GND257
GND258
GND259
GND260
GND261
GND262
GND263
GND264
GND265
GND266
GND267
GND268
GND269
GND270
GND271
GND272
GND273
GND274
GND275
GND276
GND277
GND278
GND279
GND280
GND281
GND282
GND283
GND284
GND285
GND286
GND287
GND288
GND289
GND290
GND291
GND292
GND293
GND294
GND295
GND296
GND297
GND298
GND299
GND300
GND301

GND

GND302
GND303
GND304
GND305
GND306
GND307
GND308
GND309
GND310
GND311
GND312
GND313
GND314
GND315
GND316
GND317
GND318
GND319
GND320
GND321
GND322
GND323
GND324
GND325
GND326
GND327
GND328
GND329
GND330
GND331
GND332
GND333
GND334
GND335
GND336
GND337
GND338
GND339
GND340
GND341

GND343

AV40

BA1

BA4

AW31

AY6

L35

BC33

BC37

BC41

AY14

BC5

C2

D10

D14

D15

D18

D19

D22

D23

D26

D30

D37

D6

E13

E17

E21

E25

E29

E33

F12

F16

F32

F8

G10

G12

G14

G16

BC12

G22

G24

AW20

G34

G4

G43

G6

G8

H11

H15

AW35

H23

AN8

G40

J12

J8

K10

K12

K18

K26

K37

K4

K40

K8

AU1

L40

L43

L5

M10

M34

M35

M37

Y28

Y33

Y34

Y35

Y37

Y38

AB17

AB16

AN26

AD7

M11

AA4

AB19

AY13

P11

Y6

T11

V11

Y11

AH16

T22

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

8

76

=PPVCORE_S0_MCP

8

23 45

23065 mA (A01, 1.2V)
16996 mA (A01, 1.0V)

PP3V3_G3_RTC

21 25

10 uA (G3)
80 uA (S0)

OMIT

U1400

MCP79-TOPO-B

BGA

AA25

AC23

AH12

AG10

AA16

AA26

AA27

AA28

AC16

AC17

AC18

AC19

AC20

AC21

AA17

AC24

AC25

AC26

AC27

AC28

AD21

AD23

AA18

AE19

AE21

AE23

AE25

AE26

AE27

AE28

AF10

AF11

AA19

AF21

AF23

AF25

AH23

AA20

AG11

AG12

AG21

AG23

AG25

AA21

AH10

AH11

AA23

AH25

AH21

AA24

AF12

U25

AG5

Y21

Y23

W27

V25

AF2

AF3

AF4

AF7

AF9

AG3

AG4

AG6

AG7

AG8

AG9

AH1

W26

AH2

W28

AH3

AH4

AH5

AH6

AH7

AH9

W21

W23

W25

A20

+VDD_CORE1
+VDD_CORE2
+VDD_CORE3
+VDD_CORE4
+VDD_CORE5
+VDD_CORE6
+VDD_CORE7
+VDD_CORE8
+VDD_CORE9
+VDD_CORE10
+VDD_CORE11
+VDD_CORE12
+VDD_CORE13
+VDD_CORE14
+VDD_CORE15
+VDD_CORE16
+VDD_CORE17
+VDD_CORE18
+VDD_CORE19
+VDD_CORE20
+VDD_CORE21
+VDD_CORE22
+VDD_CORE23
+VDD_CORE24
+VDD_CORE25
+VDD_CORE26
+VDD_CORE27
+VDD_CORE28
+VDD_CORE29
+VDD_CORE30
+VDD_CORE31
+VDD_CORE32
+VDD_CORE33
+VDD_CORE34
+VDD_CORE35
+VDD_CORE36
+VDD_CORE37
+VDD_CORE38
+VDD_CORE39
+VDD_CORE40
+VDD_CORE41
+VDD_CORE42
+VDD_CORE43
+VDD_CORE44
+VDD_CORE45
+VDD_CORE46
+VDD_CORE47
+VDD_CORE48
+VDD_CORE49
+VDD_CORE50
+VDD_CORE51
+VDD_CORE52
+VDD_CORE53
+VDD_CORE54
+VDD_CORE55
+VDD_CORE56
+VDD_CORE57
+VDD_CORE58
+VDD_CORE59
+VDD_CORE60
+VDD_CORE61
+VDD_CORE62
+VDD_CORE63
+VDD_CORE64
+VDD_CORE65
+VDD_CORE66
+VDD_CORE67
+VDD_CORE68
+VDD_CORE69
+VDD_CORE70
+VDD_CORE71
+VDD_CORE72
+VDD_CORE73
+VDD_CORE74
+VDD_CORE75
+VDD_CORE76
+VDD_CORE77
+VDD_CORE78
+VDD_CORE79
+VDD_CORE80
+VDD_CORE81

+VBAT

(10 OF 11)

+VTT_CPU10
+VTT_CPU11
+VTT_CPU12
+VTT_CPU13
+VTT_CPU14
+VTT_CPU15
+VTT_CPU16
+VTT_CPU17
+VTT_CPU18
+VTT_CPU19
+VTT_CPU20
+VTT_CPU21
+VTT_CPU22
+VTT_CPU23
+VTT_CPU24
+VTT_CPU25
+VTT_CPU26
+VTT_CPU27
+VTT_CPU28
+VTT_CPU29
+VTT_CPU30
+VTT_CPU31
+VTT_CPU32
+VTT_CPU33
+VTT_CPU34
+VTT_CPU35
+VTT_CPU36
+VTT_CPU37

POWER

+VTT_CPU38
+VTT_CPU39
+VTT_CPU40
+VTT_CPU41
+VTT_CPU42
+VTT_CPU43
+VTT_CPU44
+VTT_CPU45
+VTT_CPU46
+VTT_CPU47
+VTT_CPU48
+VTT_CPU49
+VTT_CPU50
+VTT_CPU51
+VTT_CPU52

+VTT_CPUCLK

+3.3V_DUAL1
+3.3V_DUAL2
+3.3V_DUAL3
+3.3V_DUAL4

+3.3V_DUAL_USB1
+3.3V_DUAL_USB2
+3.3V_DUAL_USB3
+3.3V_DUAL_USB4

+VDD_AUXC1
+VDD_AUXC2
+VDD_AUXC3

+VTT_CPU1
+VTT_CPU2
+VTT_CPU3
+VTT_CPU4
+VTT_CPU5
+VTT_CPU6
+VTT_CPU7
+VTT_CPU8
+VTT_CPU9

+3.3V_1
+3.3V_2
+3.3V_3
+3.3V_4
+3.3V_5
+3.3V_6
+3.3V_7
+3.3V_8

5

=PP1V05_S0_MCP_FSB

R32

1139 mA

AC32

E40

J36

N32

T32

U32

V32

W32

P31

AF32

AE32

AH32

AJ32

AK31

AK32

AD32

AL31

AB32

B41

B42

C40

C41

C42

D39

D40

D41

E38

E39

F37

F38

F39

G36

G37

G38

H35

H37

J34

J35

K33

K34

K35

L32

L33

L34

M31

M32

M33

N31

P32

Y32

AA32

AG32

43 mA

=PP3V3_S0_MCP

AD10

AE8

AB10

AD9

Y10

AB11

AA8

Y9

=PP3V3_S5_MCP

G18

16 mA

H19

J20

K20

G26

250 mA

H27

J28

K28

=PP1V05_S5_MCP_VDD_AUXC

T21

U21

V21

4

8 9

14 23

1182 mA (A01)

8

21 23

450 mA (A01)

8

23

266 mA (A01)

8

23

105 mA (A01)

D

C

B

MCP Power & Ground

051-8071

SHT

SYNC_DATE=06/06/2008

OF

1

A

REV.

B

9822

SYNC_MASTER=T18_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

3

2

SCALE

NONE

87

www.vinafix.vn

6

5

4

3

21

MCP Core Power

=PPVCORE_S0_MCP

8

22 45

23065 mA (A01, 1.2V)
16996 mA (A01, 1.0V)

(No IG vs. EG data)

D

MCP PCIE (DVDD) Power

=PP1V05_S0_MCP_PEX_DVDD

MCP 1.05V AUX Power

=PP1V05_S5_MCP_VDD_AUXC

8

22

105 mA (A01) 131 mA (A01)

MCP FSB (VTT) Power

=PP1V05_S0_MCP_FSB

8 9

14 22

1182 mA (A01)

C

NV: 1x 10uF 0805, 2x 4.7uF 0402, 3x 1uF 0402, 9x 0.1uF 0402 (23.3 uF)
Apple: 4x 4.7uF 0402, 4x 1uF 0402, 6x 0.1uF 0402 (23.4 uF)

C2501

4.7UF

1

C2516

1UF

10%
10V

2

X5R
402-1

1

20%

4V

2

X5R
402

1

C2526

0.1uF

20%
10V

2

CERM
402

1

C2531

2.2UF

20%

6.3V

2

CERM
402-LF

C2502

4.7UF

1

C2517

1UF

10%
10V

2

X5R
402-1

1

20%

4V

2

X5R
402

1

C2532

2.2UF

20%

6.3V

2

CERM
402-LF

1

C2500

4.7UF

20%

4V

2

X5R
402

1

C2515

4.7UF

20%

4V

2

X5R
402

1

C2525

0.1uF

20%
10V

2

CERM
402

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)
Apple: 7x 2.2uF 0402 (15.4 uF)

1

C2530

2.2UF

20%

6.3V

2

CERM
402-LF

C2503

4.7UF

1

C2518

0.1uF

20%
10V

2

CERM
402

1

20%

4V

2

X5R
402

1

2

1

2

1

2

C2533

2.2UF

20%

6.3V
CERM
402-LF

C2504

1UF

10%
10V
X5R
402-1

C2519

0.1uF

20%
10V
CERM
402

8 8

18

1

C2505

1UF

10%
10V

2

X5R
402-1

MCP SATA (DVDD) Power

=PP1V05_S0_MCP_SATA_DVDD

43 mA (A01)57 mA (A01)

MCP 1.05V RMGT Power

=PP1V05_ENET_MCP_RMGT

8

1

C2534

2

2.2UF

20%

6.3V
CERM
402-LF

1

2

C2535

2.2UF

20%

6.3V
CERM
402-LF

1

C2506

1UF

10%
10V

2

X5R
402-1

C2520

4.7UF

C2528

4.7uF

1

C2536

2.2UF

20%

6.3V

2

CERM
402-LF

1

C2507

1UF

10%
10V

2

X5R
402-1

20%

4V
X5R
402

20%

4V
X5R
402

1

C2508

0.1UF

20%
10V

2

CERM
402

1

1

C2521

0.1uF

20%
10V

2

2

CERM
402

1

1

C2529

0.1uF

20%
10V

2

2

CERM
402

1

2

C2509

0.1UF

20%
10V
CERM
402

1

C2510

0.1UF

2

20%
10V
CERM
402

1

C2511

2

0.1UF

20%
10V
CERM
402

1

C2512

0.1UF

20%
10V

2

CERM
402

=PP1V05_S0_MCP_AVDD_UF

8

333 mA (A01)

=PP1V05_S0_MCP_PLL_PEX_UF

8

1

C2513

2

0.1UF

20%
10V
CERM
402

L2570

30-OHM-5A

0603

L2575

30-OHM-5A

0603

L2582

30-OHM-1.7A

0402

C2582

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 1uF 0402, 2x 0.1uF 0402 (16.9 uF)
Apple: 5x 2.2uF 0402 (11 uF)

21

17

84 mA (A01)

1

C2573

2.2UF

20%

6.3V

2

CERM
402-LF

127 mA (A01)

4.7UF

1

C2570

2.2UF

20%

6.3V

2

CERM
402-LF

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)
Apple: 2x 2.2uF 0402 (4.4 uF)

21

1

C2575

2.2UF

20%

6.3V

2

CERM
402-LF

21

1

1

20%

4V

2

2

X5R
402

1

C2571

2.2UF

20%

6.3V

2

CERM
402-LF

PP1V05_S0_MCP_SATA_AVDD

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

1

C2576

2.2UF

20%

6.3V

2

CERM
402-LF

PP1V05_S0_MCP_PLL_PEX

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

C2583

2.2UF

20%

6.3V
CERM
402-LF

1

2

C2572

2.2UF

20%

6.3V
CERM
402-LF

8

PP1V05_S0_MCP_PEX_AVDD

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

1

C2574

2.2UF

20%

6.3V

2

CERM
402-LF

8

206 mA (A01)

D

C

MCP Memory Power

=PP1V8R1V5_S0_MCP_MEM

8

16

4771 mA (A01, DDR3)

C2540

4.7UF

=PP1V05_S0_MCP_PLL_UF

8

66

1

1

C2541

20%

4V
X5R
402

0.1UF

20%
10V

2

2

CERM
402

1

C2542

0.1UF

2

20%
10V
CERM
402

1

C2543

2

0.1UF

20%
10V
CERM
402

1

2

C2544

0.1UF

20%
10V
CERM
402

1

2

C2545

0.1UF

20%
10V
CERM
402

1

C2546

0.1UF

20%
10V

2

CERM
402

1

C2547

0.1UF

20%
10V

2

CERM
402

1

C2548

2

0.1UF

20%
10V
CERM
402

1

2

C2549

0.1UF

20%
10V
CERM
402

562 mA (A01)

R2580

0.2

1%

1/6W

MF

402-HF

21

C2580

4.7UF

PP1V05_S0_MCP_PLL_FSB

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

1

1

C2581

2.2UF

20%

4V
X5R
402

10%
16V

2

2

X5R
603

14

270 mA (A01)

MCP 3.3V Power

=PP3V3_S0_MCP

8

21 22

450 mA (A01)

NV: 1x 4.7uF 0603, 4x 0.1uF 0402 (5.1 uF)
Apple: 4x 2.2uF 0402 (8.8 uF)

1

C2550

2.2UF

2

20%

6.3V
CERM
402-LF

1

C2551

2.2UF

2

20%

6.3V
CERM
402-LF

B

MCP 3.3V AUX/USB Power

=PP3V3_S5_MCP

8

22

266 mA (A01)

MCP 3.3V/1.5V HDA Power

=PP3V3R1V5_S0_MCP_HDA

8

21

7 mA (A01)

A

=PP1V05_ENET_MCP_PLL_MAC

8

5 mA (A01)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

8

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
Apple: 1x 2.2uF 0402 (2.2 uF)

1

C2560

2.2UF

20%

6.3V

2

CERM
402-LF

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
Apple: 1x 2.2uF 0402 (2.2 uF)

1

C2562

2.2UF

20%

6.3V

2

CERM
402-LF

L2595

30-OHM-1.7A

0402

C2595

4.7UF

21

1

20%

4V

2

X5R
402

76

1

C2552

2.2UF

20%

6.3V

2

CERM
402-LF

PP1V05_ENET_MCP_PLL_MAC

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

1

C2596

2.2UF

20%

6.3V

2

CERM
402-LF

1

C2553

2

2.2UF

20%

6.3V
CERM
402-LF

=PP3V3_S0_MCP_PLL_UF

8

19 mA (A01)

18

5 mA (A01)

MCP 3.3V Ethernet Power

=PP3V3_ENET_MCP_RMGT

8

18 23

83 mA (A01)

=PP3V3_ENET_MCP_RMGT

8

18 23

L2555

30-OHM-1.7A

0402

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
Apple: 1x 2.2uF 0402 (2.2 uF)

PP3V3_S0_MCP_PLL_USB

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

21

MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

1

C2555

2.2UF

20%

6.3V

2

CERM
402-LF

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
Apple: 1x 2.2uF 0402 (2.2 uF)

1

C2564

2.2UF

20%

6.3V

2

CERM
402-LF

MCP79 Ethernet VRef

1

R2591

1.47K

1%
1/16W
MF-LF

402

2

MCP_MII_VREF

1

R2590

1.47K

1/16W
MF-LF

1

C2591

0.1UF

1%

20%
10V

2

402

CERM
402

2

5

L2584

20

19 mA (A01)

30-OHM-1.7A

0402

C2584

4.7UF

21

20%

4V
X5R
402

PP1V05_S0_MCP_PLL_SATA

MIN_LINE_WIDTH=0.4 MM

VOLTAGE=1.05V

1

1

C2585

2.2UF

20%

6.3V

2

2

CERM
402-LF

20

84 mA (A01)

B

L2586

30-OHM-1.7A

30-OHM-1.7A

18

OUT

4

3

0402

L2588

0402

C2586

4.7UF

C2588

4.7UF

21

20%

4V
X5R
402

21

20%

4V
X5R
402

PP1V05_S0_MCP_PLL_CORE

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

1

1

C2587

2.2UF

20%

6.3V

2

2

CERM
402-LF

1

1

C2589

2.2UF

20%

6.3V

2

2

CERM
402-LF

PP1V05_S0_MCP_PLL_NV

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

1

C2590

0.1UF

20%
10V

2

CERM
402

2

16

87 mA (A01)

21

37 mA (A01)

MCP Standard Decoupling

SYNC_MASTER=M98_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

D

NONE

DRAWING NUMBER

051-8071

SHT

SYNC_DATE=04/01/2008

OF

23

1

A

REV.

B

98

87

www.vinafix.vn

6

5

4

3

21

WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

=PP3V3R1V8_S0_MCP_IFP_VDD

8

18

190 mA (A01, 1.8V)

D

=PP1V05_S0_MCP_HDMI_VDD

8

18

95 mA (A01)

Apple: 1x 2.2uF 0402 (2.2 uF)

1

C2610

2.2UF

20%

6.3V

2

CERM
402-LF

1

1

C2615

4.7UF

20%

4V
X5R
402

C2616

2

2

2.2UF

20%

6.3V
CERM
402-LF

=PP3V3_S0_MCP_DAC_UF

8

206 mA (A01)

NO STUFF

L2650

30-OHM-1.7A

0402

NV: 1x 4.7uF 0603, 2x 0.1uF 0402 (4.9 uF)
Apple: 2x 2.2uF 0402 (4.4 uF)

21

NO STUFF

1

C2650

2.2UF

20%

6.3V

2

CERM
402-LF

PP3V3_S0_MCP_DAC

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

1

R2651

0

5%
1/16W
MF-LF
402

2

18

206 mA (A01)

D

18

18

18

18

MCP_HDMI_RSET

18 90

MCP_HDMI_VPROBE

18 90

C

NO STUFF

C2620

0.1UF

CERM

1

R2620

1

1K

1%

20%
10V

402

1/16W
MF-LF
402

2

2

WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

L2640

=PP3V3_S0_MCP_VPLL_UF

8

16 mA (A01)

30-OHM-1.7A

0402

C2640

4.7UF

6.3V
CERM

21

1

20%

2

603

MCP_IFPAB_RSET

18 90

MCP_IFPAB_VPROBE

18 90

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
Apple: ???

PP3V3_S0_MCP_VPLL

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

1

C2641

2.2UF

20%

6.3V

2

CERM
402-LF

NO STUFF

C2630

0.1UF

20%
10V

CERM

402

1

2

16 mA (A01)

NO STUFF

1

R2630

1K

1%
1/16W
MF-LF
402

2

18

18

18 90

18 90

18 90

18 90

18 90

TP_MCP_RGB_DAC_RSET

18

TP_MCP_RGB_DAC_VREF

18

MCP_TV_DAC_RSET

18 90

MCP_TV_DAC_VREF

18 90

MCP_CLK27M_XTALIN

18

MCP_CLK27M_XTALOUT

18

TP_MCP_RGB_RED

TP_MCP_RGB_GREEN

TP_MCP_RGB_BLUE

TP_MCP_RGB_HSYNC

TP_MCP_RGB_VSYNC

CRT_IG_R_C_PR

CRT_IG_G_Y_Y

CRT_IG_B_COMP_PB

CRT_IG_HSYNC

CRT_IG_VSYNC

B

NC_MCP_RGB_RED

MAKE_BASE=TRUE

NC_MCP_RGB_GREEN

MAKE_BASE=TRUE

NC_MCP_RGB_BLUE

MAKE_BASE=TRUE

NC_MCP_RGB_HSYNC

MAKE_BASE=TRUE

NC_MCP_RGB_VSYNC

MAKE_BASE=TRUE

NC_CRT_IG_R_C_PR

MAKE_BASE=TRUE

NC_CRT_IG_G_Y_Y

MAKE_BASE=TRUE

NC_CRT_IG_B_COMP_PB

MAKE_BASE=TRUE

NC_CRT_IG_HSYNC

MAKE_BASE=TRUE

NC_CRT_IG_VSYNC

MAKE_BASE=TRUE

NC_MCP_RGB_DAC_RSET

MAKE_BASE=TRUE

NC_MCP_RGB_DAC_VREF

MAKE_BASE=TRUE

NC_MCP_TV_DAC_RSET

MAKE_BASE=TRUE

NC_MCP_TV_DAC_VREF

MAKE_BASE=TRUE

NC_MCP_CLK27M_XTALIN

MAKE_BASE=TRUE

NC_MCP_CLK27M_XTALOUT

MAKE_BASE=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

C

B

HDCP ROM

WF: Open question on which packge option(s) nVidia can support.

=PP3V3_S0_HDCPROM

8

C2690

0.1UF

1

NO STUFF

20%
10V

2

CERM

402

NO STUFF

8

VCC

U2695

AT24C08

SOIC

GND

5

SDA

6

SCL

7

WP

4

1

A0

2

A1

3

A2

A

Current numbers from email Xiaowei Lin provided 11/12/2007 3:22pm (no official document number).

8

76

=I2C_HDCPROM_SDA
=I2C_HDCPROM_SCL

HDCPROM_WP

R2690

10K

1/16W
MF-LF

1

NO STUFF

5%

402

2

44

BI

44

IN

MCP Graphics Support

051-8071

SHT

SYNC_DATE=04/01/2008

OF

24 98

1

A

REV.

B

SYNC_MASTER=M98_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

5

4

3

2

SCALE

NONE

87

www.vinafix.vn

6

5

4

3

21

RTC Power Sources

=PP3V3_S5_RTC_D

8

1

RTC_PS_YES

VIN

U2801

MIC5232-2.8YD5

TSOT-23-5

3

D

NO STUFF

1

C2802

1UF

10%
10V

2

X5R
402

CRITICAL

GND

2

5

VOUTEN

4

NC

RTC_DISCHARGE_R

RTC_CLK32K_XTALOUT

21

IN

NO STUFF

1

R2811

10M

5%

1/16W

C

RTC_CLK32K_XTALIN

21

OUT

MF-LF

402

2

RTC Crystal

R2810

0

21

RTC_CLK32K_XTALOUT_R

5%
1/16W
MF-LF

402

Y2810

32.768K

7X1.5X1.4-SM

MCP 25MHz Crystal

MCP_CLK25M_XTALOUT

21

IN

R2815

0

21

MCP_CLK25M_XTALOUT_R

1/16W
MF-LF

5%

402

SM-3.2X2.5MM

21

OUT

MCP_CLK25M_XTALIN

NO STUFF

R2816

1/16W
MF-LF

1

1M

5%

402

2

MCP S0 PWRGD & CPU_VLD

=PP3V3_S5_MCPPWRGD

8

B

ALL_SYS_PWRGD

41 67 84

IN

VR_PWRGOOD_DELAY

61

IN

MCP_CPUVDD_EN

21

IN

A

MCPSEQ_SMC represents MCP79 ’MLB’ power sequencing connections,
but results in MCP79 ROMSIP sequence happening after CPU powers up.

MCPSEQ_MIX is cross between MLB and internal power sequencing, which
results in earlier ROMSIP and MCP FSB I/O interface initialization.

SMC 99ms delay from ALL_SYS_PWRGD to IMVP_VR_ON plus IMVP6 delay for
VR_PWRGOOD_DELAY should guarantee CPU_VLD does not go high before
CPUVDD_EN (which is 40-100ms after PS_PWRGD assertion).

NOTE: If CPU_VLD deasserts during S0 MCP79 will take system to S5 immediately.

2

1

A

U2850

B

1

2

TC7SZ08AFEAPE

5

SOT665

MCPSEQ_SMC

3

MCPSEQ_SMC

C2850

0.1UF

20%
10V
CERM
402

4

S0_AND_IMVP_PGOOD

PLACEMENT_NOTE=Place close to U1400

MCPSEQ_MIX

R2851

0

5%
1/16W
MF-LF

402

21

NO STUFF

R2801

1/16W
MF-LF

CRITICAL

CRITICAL

Y2815

25.0000M

MCPSEQ_SMC

R2853

MCPSEQ_MIX

R2852

MCPSEQ_SMC

R2850

10

402

1/16W
MF-LF

1/16W
MF-LF

1/16W
MF-LF

1

5%

2

0

5%

402

0

5%

402

0

5%

402

R2803

0

21

5%
1/16W
MF-LF

402

NO STUFF

R2802

1.0M

21

5%
1/10W
MF-LF

603

41

31

42

NC

NC

21

MCP_PS_PWRGD

21

MCP_CPU_VLD

21

C2801

1UF

10%

6.3V
CERM

402

C2810

C2811

C2815

C2816

12pF

50V

CERM

402

12pF

50V

CERM

402

12pF

50V

CERM

402

12pF

50V

CERM

402

1

2

5%

5%

5%

5%

1

R2800

100

5%
1/16W
MF-LF
402

2

PP3V3_G3_SUPERCAP

1

2

21

21

21

21

PP3V3_G3_RTC

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

SUPERCAP_YES

C2800

SUPERCAP_YES

0.08F

2%

CRITICAL

3.3V
XHHG
SM

OUTY

OUT

Platform Reset Connections

LPC Reset (Unbuffered)

R2881

PLACEMENT_NOTE=Place close to U1400

PLACEMENT_NOTE=Place close to U1400

21 22

19 84 91

IN

LPC_RESET_L

PCIE Reset (Unbuffered)

PCIE_RESET_L

17

IN

MEM_VTT_EN_R

19

IN

LPC_CLK33M_SMC_R

19 91

IN

PM_CLK32K_SUSCLK_R

21 91

IN

21

21

PM_SYSRST_L

7

41

IN

XDP_DBRESET_L

IN

Reset Button

XDP

R2896

0

21

5%
1/16W
MF-LF

402

SILK_PART=FP SYS RESET

OMIT

R2897

1/16W
MF-LF

R2899

33

5%

1/16W

1

MF-LF

0

5%

402

402

2

PLACEMENT_NOTE=Place close to U1400

PLACEMENT_NOTE=Place close to U1400

10K pull-up to 3.3V S0 inside MCP

21

PM_SYSRST_DEBOUNCE_L

NO STUFF

1

C2899

1UF

10%
10V

2

X5R
402

33

21

5%
1/16W
MF-LF

402

R2890

1/16W
MF-LF

R2893

1/16W
MF-LF

R2895

R2825

33

5%
1/16W
MF-LF

402

R2827

33

5%
1/16W
MF-LF

402

PLACEMENT_NOTE=Place close to U1400

R2829

22

5%
1/16W
MF-LF

402

21 10 13

OUT

5%

402

5%

402

1/16W
MF-LF

0

0

21

21

0

21

5%

402

21

21

21

R2883

33

5%
1/16W
MF-LF

402

R2892

0

5%
1/16W
MF-LF

402

GMUX_PCIE_RESET_L

MAKE_BASE=TRUE

R2891

0

5%
1/16W
MF-LF

402

BKLT_PLT_RST_L

R2894

0

5%
1/16W
MF-LF

402

EXCARD_RESET_L

R2870

33

21

5%
1/16W
MF-LF

402

R2826

33

5%
1/16W
MF-LF

402

SYNC_MASTER=M98_MLB

APPLE INC.

DEBUG_RESET_L

21

SMC_LRESET_L

21

FW_RESET_L

=GMUX_PCIE_RESET_L

21

PCA9557D_RESET_L

21

MINI_RESET_L

MEM_VTT_EN

LPC_CLK33M_SMC

21

LPC_CLK33M_LPCPLUS

PLACEMENT_NOTE=Place close to U1400

LPC_CLK33M_GMUX

PM_CLK32K_SUSCLK

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

SB Misc

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

SHT

051-8071

25

7

43

41

35

84

26

86

30

31

9

41 91

7

43 91

84

41 91

SYNC_DATE=05/01/2008

REV.

OF

98

D

C

B

A

B

8

76

5

4

3

2

1

Page Notes

www.vinafix.vn

Power aliases required by this page:

- =PP3V3_S3_VREFMRGN

- =PP3V3_S5_VREFMRGN

- =PPVTT_S3_DDR_BUF

Signal aliases required by this page:

- =I2C_VREFDACS_SCL

- =I2C_VREFDACS_SDA

- =I2C_PCA9557D_SCL

- =I2C_PCA9557D_SDA

BOM options provided by this page:

D

VREFMRGN

NO_VREFMRGN

C

B

87

MEM A VREF DQ MEM A VREF CA MEM B VREF DQ

DAC channel A B A B C D

Min DAC code 0x00 0x00 0x00 0x00 0x00 0x00

Max DAC code 0x87 0x87 0x87 0x87 0x55 0xFF

Max sink I -3.75 mA -3.75 mA -3.75 mA -3.75 mA -0.91 mA -59.04 mA

Max source I 5 mA 5 mA 5 mA 5 mA 0.52 mA 51.15 mA

Nominal Vref 0.75 V 0.75 V 0.75 V 0.75 V 0.70 V 1.248 V

Min Vref 0.375 V 0.375 V 0.375 V 0.375 V 0.091 V 1.042 V

Max Vref 1.250 V 1.250 V 1.250 V 1.250 V 1.044 V 1.426 V

Vref Stepping 6.5 mV 6.5 mV 6.5 mV 6.5 mV 11.2 mV 1.5 mV

(per DAC LSB)

OMIT

=PP3V3_S3_VREFMRGN

8

44

44

R2918

SHORT

21

NONE
NONE
NONE

402

44

44

ADDR=0x98(WR)/0x99(RD)

OMIT

R2919

SHORT

NONE
NONE
NONE

402

ADDR=0x30(WR)/0x31(RD)

=I2C_PCA9557D_SCL

IN

=I2C_PCA9557D_SDA

BI

IN

BI

21

VREFMRGN

1

C2900

2.2UF

20%

6.3V

2

CERM
402-LF

=I2C_VREFDACS_SCL

=I2C_VREFDACS_SDA

1

2

VREFMRGN

1

C2902

0.1UF

20%
10V

2

CERM
402

VREFMRGN

C2901

0.1UF

20%
10V
CERM
402

PP3V3_S3_VREFMRGN_DAC

6

SCL

7

SDA

9

A0

10

A1

PP3V3_S3_VREFMRGN_CTRL

3

A0

4

A1

5

A2

1

SCL

2

SDA

THRM

PAD

17

U2901

PCA9557

GND

VREFMRGN

U2900

8

VDD

VOUTA

MSOP

VOUTB

VOUTC

DAC5574

VOUTD

GND

3

CRITICAL

VREFMRGN

16

VCC

QFN

RESET*

8

P0
P1
P2
P3
P4
P5
P6
P7

6

1

2

4

5

6

7

9

10

11

12

13

14

15

VREFMRGN_DQ_SODIMM

VREFMRGN_CA_SODIMM

VREFMRGN_CPUFSB

VREFMRGN_FRAMEBUF

NC

NC

VREFMRGN_CPUFSB_EN

VREFMRGN_CA_SODIMMA_EN

VREFMRGN_DQ_SODIMMA_EN

VREFMRGN_CA_SODIMMB_EN

VREFMRGN_DQ_SODIMMB_EN

VREFMRGN_FRAMEBUF_EN

PCA9557D_RESET_L

5

MEM B VREF CA

CPU FSB VREF

4

FRAME BUFFER VREF

3

21

SO-DIMM A and SO-DIMM B Vref settings should be margined separately

(i.e. not simultaneously) due to current limitation of TPS51116 regulator.

=PPVTT_S3_DDR_BUF

8

63

10mA max load

VREFMRGN

R2903

200

21

1%
1/16W
MF-LF

B1

VREFMRGN

V-

VREFMRGN

V-

VREFMRGN

V-

VREFMRGN

V-

VREFMRGN

V-

VREFMRGN

V-

U2902

MAX4253

V+

UCSP

A1

C1

A1

C1

A1

C1

VREFMRGN_DQ_SODIMMA_BUF

VREFMRGN_DQ_SODIMMA_EN

26

VREFMRGN_DQ_SODIMMB_BUF

VREFMRGN_DQ_SODIMMB_EN

26

VREFMRGN_CA_SODIMMA_BUF

VREFMRGN_CA_SODIMMA_EN

26

VREFMRGN_CA_SODIMMB_BUF

VREFMRGN_CA_SODIMMB_EN

26

VREFMRGN_FRAMEBUF_BUF

VREFMRGN_FRAMEBUF_EN

26

VREFMRGN_CPUFSB_BUF

VREFMRGN_CPUFSB_EN

26

R2901

R2902

R2907

R2908

R2915

R2913

100K

100K

100K

100K

100K

100K

1/16W
MF-LF

1/16W
MF-LF

1/16W
MF-LF

1/16W
MF-LF

1/16W
MF-LF

1/16W
MF-LF

21

VREFMRGN

5%

402

21

VREFMRGN

5%

402

21

VREFMRGN

5%

402

21

VREFMRGN

5%

402

21

VREFMRGN

5%

402

21

VREFMRGN

5%

402

A4

B4

B1

U2902

MAX4253

V+

UCSP

C4

B4

B1

U2903

MAX4253

V+

UCSP

A4

B4

B1

U2903

MAX4253

V+

UCSP

C4

B4

B1

U2904

MAX4253

V+

UCSP

A4

B4

B1

U2904

MAX4253

V+

UCSP

C4

B4

VREFMRGN

1

C2903

0.1UF

20%
10V

2

CERM
402

VREFMRGN

1

C2904

0.1UF

20%
10V

2

CERM
402

VREFMRGN

1

C2905

0.1UF

20%
10V

2

CERM
402

26

26

26

26

26

26

25

IN

A2

A3

C2

C3

A2

A3

C2

C3

A2

A3

C2

C3

402

VREFMRGN

R2904

100

21

1%

Place close to J3100.1

1/16W
MF-LF

402

VREFMRGN

R2905

200

21

1%
1/16W
MF-LF

402

VREFMRGN

R2906

100

21

1%

Place close to J3200.1

1/16W
MF-LF

402

VREFMRGN

R2909

200

21

1%
1/16W
MF-LF

402

VREFMRGN

R2910

100

21

1%

Place close to J3100.126

1/16W
MF-LF

402

VREFMRGN

R2911

200

21

1%
1/16W
MF-LF

402

VREFMRGN

R2912

100

21

1%

Place close to J3200.126

1/16W
MF-LF

402

VREFMRGN

R2916

49.9

21

1%

Place close to U8400, U8450

1/16W
MF-LF

402

VREFMRGN

R2917

49.9

21

1%

Place close to U8500, U8550

1/16W
MF-LF

402

VREFMRGN

R2914

100

21

1%

Place close to U1000.AD26

1/16W
MF-LF

402

PP0V75_S3_MEM_VREFDQ_A

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

PP0V75_S3_MEM_VREFDQ_B

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

PP0V75_S3_MEM_VREFCA_A

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

PP0V75_S3_MEM_VREFCA_B

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

GPU_FB_A_VREF_DIV

GPU_FB_B_VREF_DIV

CPU_GTLREF

27

28

27

28

9

OUT

9

OUT

10 88

OUT

D

C

B

A

Required zero ohm resistors when no VREF margining circuit stuffed

PART NUMBER

116S0004

116S0004

116S0004

116S0004

QTY

1

1

1

1

DESCRIPTION

RES,MTL FILM,0,5%,0402,SM,LF

RES,MTL FILM,0,5%,0402,SM,LF

RES,MTL FILM,0,5%,0402,SM,LF

RES,MTL FILM,0,5%,0402,SM,LF

8

REFERENCE DES

76

R2903

R2905

R2909

R2911

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

BOM OPTION

NO_VREFMRGN

NO_VREFMRGN

NO_VREFMRGN

NO_VREFMRGN

FSB/DDR3/FRAMEBUF Vref Margining

SYNC_MASTER=BEN_K20

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

5

4

3

2

SCALE

NONE

051-8071

SHT

SYNC_DATE=10/15/2008

OF

1

A

REV.

B

9826

87

www.vinafix.vn

6

5

4

3

21

Power aliases required by this page:

- =PP1V5_S0_MEM_A

- =PP1V5_S3_MEM_A

- =PP0V75_S0_MEM_VTT_A

- =PPSPD_S0_MEM_A (2.5 - 3.3V)

Signal aliases required by this page:

- =I2C_SODIMMA_SCL

- =I2C_SODIMMA_SDA

BOM options provided by this page:

D

(NONE)

C

B

A

Page Notes

=PPSPD_S0_MEM_A

8

1

2

C3140

2.2UF

20%

6.3V

CERM

402-LF

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

1

2

R3140

10K

5%

1/16W

MF-LF

402

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI

MEM_A_CKE<0>

MEM_A_BA<2>

MEM_A_A<12>

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<5>

MEM_A_A<3>

MEM_A_A<1>

MEM_A_CLK_P<0>

MEM_A_CLK_N<0>

MEM_A_A<10>

MEM_A_BA<0>

MEM_A_WE_L

MEM_A_CAS_L

MEM_A_A<13>

MEM_A_CS_L<1>

MEM_A_DQ<33>

MEM_A_DQ<32>

MEM_A_DQS_N<4>

MEM_A_DQS_P<4>

MEM_A_DQ<34>

MEM_A_DQ<35>

MEM_A_DQ<44>

MEM_A_DQ<41>

MEM_A_DM<5>

MEM_A_DQ<45>

MEM_A_DQ<42>

MEM_A_DQ<52>

MEM_A_DQ<51>

MEM_A_DQS_N<6>

MEM_A_DQS_P<6>

MEM_A_DQ<55>

MEM_A_DQ<54>

MEM_A_DQ<61>

MEM_A_DQ<60>

MEM_A_DM<7>

MEM_A_DQ<58>

MEM_A_DQ<59>

MEM_A_SA<0>

MEM_A_SA<1>

1

R3141

10K

5%

1/16W

MF-LF

402

2

=PP1V5_S0_MEM_A

8

=PP1V5_S3_MEM_A

8

NC

NC

1

C3100

10UF

20%

6.3V

2

X5R
603

KEY

CKE0

VDD

77

NC

79

83 84
85

89
91 92

95 96
97 98

99
101
103

107
109

113
115

119
121

125

129
131

135
137
139
141
143
145
147
149
151
153

157
159

163
165

169
171
173
175
177
179
181
183
185
187

191
193

197
199

J3100

BA2

F-RT-THB

VDD
A12/BC*
A9

VDD
A8
A5

VDD
A3
A1

VDD
CK0
CK0*

VDD
A10/AP
BA0

VDD
WE*
CAS*

VDD
A13
S1*

VDD
TEST

VSS
DQ32
DQ33

VSS
DQS4*
DQS4

VSS
DQ34
DQ35

VSS
DQ40
DQ41

VSS
DM5

VSS
DQ42
DQ43

VSS
DQ48
DQ49

VSS
DQS6*
DQS6

VSS
DQ50
DQ51

VSS
DQ56
DQ57

VSS
DM7

VSS
DQ58
DQ59

VSS
SA0
VDDSPD
SA1

VTT

516-0201

SPD ADDR=0xA0(WR)/0xA1(RD)

1

C3101

10UF

20%

6.3V

2

X5R
603

CKE1

VDD

A15
A14

VDD

A11

A7

VDD

A6
A4

VDD

(SYMBOL 2 OF 2)

A2
A0

VDD

CK1

CK1*

VDD

DDR3-SODIMM-DUAL-M97-3

BA1

RAS*

VDD

S0*

ODT0

VDD

ODT1

NC

VDD

VREFCA

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5*

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7*

DQS7

VSS
DQ62
DQ63

VSS

EVENT*

SDA
SCL

VTT

7473
7675
78
80
8281

86
8887
90

9493

100
102
104
106105
108
110
112111
114
116
118117
120
122
124123
126
128127
130
132
134133
136
138
140
142
144
146
148
150
152
154
156155
158
160
162161
164
166
168167
170
172
174
176
178
180
182
184
186
188
190189
192
194
196195
198
200
202201
204203

NC

MEM_A_CKE<1>

MEM_A_A<15>

MEM_A_A<14>

MEM_A_A<11>

MEM_A_A<7>

MEM_A_A<6>

MEM_A_A<4>

MEM_A_A<2>

MEM_A_A<0>

MEM_A_CLK_P<1>

MEM_A_CLK_N<1>

MEM_A_BA<1>

MEM_A_RAS_L

MEM_A_CS_L<0>

MEM_A_ODT<0>

MEM_A_ODT<1>

MEM_A_DQ<36>

MEM_A_DQ<37>

MEM_A_DM<4>

MEM_A_DQ<38>

MEM_A_DQ<39>

MEM_A_DQ<47>

MEM_A_DQ<40>

MEM_A_DQS_N<5>

MEM_A_DQS_P<5>

MEM_A_DQ<46>

MEM_A_DQ<43>

MEM_A_DQ<48>

MEM_A_DQ<53>

MEM_A_DM<6>

MEM_A_DQ<50>

MEM_A_DQ<49>

MEM_A_DQ<57>

MEM_A_DQ<56>

MEM_A_DQS_N<7>

MEM_A_DQS_P<7>

MEM_A_DQ<62>

MEM_A_DQ<63>

MEM_EVENT_L

=I2C_SODIMMA_SDA

=I2C_SODIMMA_SCL

DDR3 PLANE STITCHING CAPS (SPACE EVENLY ACROSS PLANE SPLIT)

1

C3110

0.1UF

2

20%
10V
CERM
402

1

C3111

0.1UF

20%
10V

2

CERM
402

PP0V75_S3_MEM_VREFDQ_A

26

15 89

IN

9

IN

15 89

IN

15 89

IN

15 89

IN

15 89

IN

15 89

IN

15 89

IN

15 89

IN

15 89

IN

15 89

IN

15 89

IN

15 89

IN

15 89

IN

15 89

IN

15 89

IN

15 89

BI

15 89

BI

15 89

IN

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

IN

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

21 28 41

OUT

BI

44

IN

DQS0

VSS

VSS
DQ12
DQ13

VSS

VSS
DQ14
DQ15

VSS
DQ20
DQ21

VSS

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3

VSS
DQ30
DQ31

VSS

DQ4
DQ5

DQ6
DQ7

DM1

DM2

VSS

VSS

21
4
6
8
10
12
1413
16
18
2019
22
24
2625
28
30
3231
34
36
3837
40
42
4443
46
48
50
52
54
56
58
60
62
64
6665
68
70
7271

1

C3118

0.1UF

20%
10V

2

CERM
402

1

C3116

0.1UF

20%
10V

2

CERM
402

VREFDQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

VSS

15

DQ2

17

DQ3

VSS

21

DQ8

23

DQ9

VSS

27

DQS1*

29

DQS1

VSS

33

DQ10

35

DQ11

VSS

39

DQ16

41

DQ17

VSS

45

DQS2*

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

VSS

67

DQ26

69

DQ27

VSS

C3130

2.2UF

20%

6.3V

CERM

402-LF

1

2

MEM_A_DQ<0>

MEM_A_DQ<1>

MEM_A_DM<0>

MEM_A_DQ<3>

MEM_A_DQ<2>

MEM_A_DQ<9>

MEM_A_DQ<13>

MEM_A_DQS_N<1>

MEM_A_DQS_P<1>

MEM_A_DQ<11>

MEM_A_DQ<14>

MEM_A_DQ<16>

MEM_A_DQ<18>

MEM_A_DQS_N<2>

MEM_A_DQS_P<2>

MEM_A_DQ<23>

MEM_A_DQ<19>

MEM_A_DQ<24>

MEM_A_DQ<30>

MEM_A_DM<3>

MEM_A_DQ<27>

MEM_A_DQ<25>

1

C3136

0.1UF

20%
10V

2

CERM

402

C3114

0.1UF

20%
10V
CERM
402

1

2

PP0V75_S3_MEM_VREFCA_A

1

C3112

0.1UF

20%
10V

2

CERM
402

44

1

C3113

2

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

1

C3135

2.2UF

20%

6.3V

2

CERM

402-LF

=PP0V75_S0_MEM_VTT_A

0.1UF

20%
10V
CERM
402

1

2

BI

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI

C3131

0.1UF

20%
10V

CERM

402

1

C3115

2

0.1UF

20%
10V
CERM
402

8

1

C3117

0.1UF

20%
10V

2

CERM
402

CRITICAL

F-RT-THB

DQS0*

(SYMBOL 1 OF 2)

RESET*

J3100

DDR3-SODIMM-DUAL-M97-3

DQS3*

KEY

516-0201

26

1

C3119

0.1UF

20%

10V

2

CERM
402

MEM_A_DQ<4>

MEM_A_DQ<5>

MEM_A_DQS_N<0>

MEM_A_DQS_P<0>

MEM_A_DQ<6>

MEM_A_DQ<7>

MEM_A_DQ<8>

MEM_A_DQ<12>

MEM_A_DM<1>

MEM_RESET_L

MEM_A_DQ<15>

MEM_A_DQ<10>

MEM_A_DQ<21>

MEM_A_DQ<20>

MEM_A_DM<2>

MEM_A_DQ<17>

MEM_A_DQ<22>

MEM_A_DQ<29>

MEM_A_DQ<28>

MEM_A_DQS_N<3>

MEM_A_DQS_P<3>

MEM_A_DQ<26>

MEM_A_DQ<31>

1

2

C3120

0.1UF

20%
10V
CERM
402

1

C3121

0.1UF

20%
10V

2

CERM
402

1

2

C3122

0.1UF

20%
10V
CERM
402

1

2

C3123

0.1UF

20%
10V
CERM
402

D

15 89

BI

15 89

BIBI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

IN

28 29

IN

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

IN

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

C

B

"Factory" (top) slot

DDR3 SO-DIMM Connector A

SYNC_MASTER=BEN_K20

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

D

NONE

DRAWING NUMBER

051-8071

SHT

OF

SYNC_DATE=06/10/2008

REV.

B

9827

A

8

76

5

4

3

2

1

87

www.vinafix.vn

6

5

4

3

21

D

C

B

A

Page Notes

Power aliases required by this page:

- =PP1V5_S0_MEM_B

- =PP1V5_S3_MEM_B

- =PP0V75_S0_MEM_VTT_B

- =PPSPD_S0_MEM_B (2.5 - 3.3V)

Signal aliases required by this page:

- =I2C_SODIMMB_SCL

- =I2C_SODIMMB_SDA

BOM options provided by this page:

(NONE)

=PPSPD_S0_MEM_B

8

1

2

1

R3240

2

C3240

2.2UF

=PP1V5_S0_MEM_B

8

=PP1V5_S3_MEM_B

8

1

C3200

10UF

20%

6.3V

2

X5R
603

MEM_B_CKE<0>

15 89

IN

77

MEM_B_BA<2>

15 89

IN

MEM_B_A<12>

15 89

IN

MEM_B_A<9>

15 89

IN

MEM_B_A<8>

15 89

IN

MEM_B_A<5>

15 89

IN

MEM_B_A<3>

15 89

IN

MEM_B_A<1>

15 89

IN

MEM_B_CLK_P<0>

15 89

IN

MEM_B_CLK_N<0>

15 89

IN

MEM_B_A<10>

15 89

IN

MEM_B_BA<0>

15 89

IN

MEM_B_WE_L

15 89

IN

MEM_B_CAS_L

15 89

IN

MEM_B_A<13>

15 89

IN

MEM_B_CS_L<1>

15 89

IN

79

83 84
85

89
91 92

95 96
97 98

99
101
103

107
109

113
115

119
121

125

MEM_B_DQ<32>

15 89

BI

MEM_B_DQ<37>

15 89

BI

MEM_B_DQS_N<4>

15 89

BI

MEM_B_DQS_P<4>

15 89

BI

MEM_B_DQ<34>

15 89

BI

MEM_B_DQ<35>

15 89

BI

MEM_B_DQ<41>

15 89

BI

MEM_B_DQ<40>

15 89

BI

MEM_B_DM<5>

15 89

IN

MEM_B_DQ<43>

15 89

BI

MEM_B_DQ<42>

15 89

BI

MEM_B_DQ<55>

15 89

BI

MEM_B_DQ<49>

15 89

BI

MEM_B_DQS_N<6>

15 89

BI

MEM_B_DQS_P<6>

15 89

BI

MEM_B_DQ<52>

15 89

BI

MEM_B_DQ<51>

15 89

BI

MEM_B_DQ<56>

15 89

BI

MEM_B_DQ<57>

15 89

BI

MEM_B_DM<7>

15 89

10K

5%

1/16W

MF-LF

402

20%

6.3V

CERM

402-LF

IN

MEM_B_DQ<63>

15 89

BI

MEM_B_DQ<59>

15 89

BI

MEM_B_SA<0>

MEM_B_SA<1>

1

R3241

10K

5%

1/16W

MF-LF

402

2

129
131

135
137
139
141
143
145
147
149
151
153

157
159

163
165

169
171
173
175
177
179
181
183
185
187

191
193

197
199

SPD ADDR=0xA2(WR)/0xA3(RD)

KEY

CKE0

VDD
NC

BA2

J3200

F-RT-BGA3

VDD
A12/BC*
A9

VDD
A8
A5

VDD
A3
A1

VDD
CK0
CK0*

VDD
A10/AP
BA0

VDD
WE*
CAS*

VDD
A13
S1*

VDD
TEST

VSS
DQ32
DQ33

VSS
DQS4*
DQS4

VSS
DQ34
DQ35

VSS
DQ40
DQ41

VSS
DM5

VSS
DQ42
DQ43

VSS
DQ48
DQ49

VSS
DQS6*
DQS6

VSS
DQ50
DQ51

VSS
DQ56
DQ57

VSS
DM7

VSS
DQ58
DQ59

VSS
SA0
VDDSPD
SA1

VTT

MTG PINS

MTG PIN

MTG PIN

MTG PIN MTG PIN

MTG PIN

516s0706

1

2

CKE1

VDD

A15
A14

VDD

A11

A7

VDD

(2 OF 2)

A6
A4

VDD

DDR3-SODIMM

A2
A0

VDD

CK1

CK1*

VDD

BA1

RAS*

VDD

S0*

ODT0

VDD

ODT1

NC

VDD

VREFCA

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5*

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7*

DQS7

VSS
DQ62
DQ63

VSS

EVENT*

SDA
SCL

VTT

MTG PIN

MTG PIN

MTG PIN

C3201

10UF

20%

6.3V
X5R
603

7473
7675
78
80
8281

86
8887
90

9493

100
102
104
106105
108
110
112111
114
116
118117
120
122
124123
126
128127
130
132
134133
136
138
140
142
144
146
148
150
152
154
156155
158
160
162161
164
166
168167
170
172
174
176
178
180
182
184
186
188
190189
192
194
196195
198
200
202201
204203

206205
208207
210209
212211

NC

MEM_B_CKE<1>

MEM_B_A<15>

MEM_B_A<14>

MEM_B_A<11>

MEM_B_A<7>

MEM_B_A<6>

MEM_B_A<4>

MEM_B_A<2>

MEM_B_A<0>

MEM_B_CLK_P<1>

MEM_B_CLK_N<1>

MEM_B_BA<1>

MEM_B_RAS_L

MEM_B_CS_L<0>

MEM_B_ODT<0>

MEM_B_ODT<1>

MEM_B_DQ<33>

MEM_B_DQ<36>

MEM_B_DM<4>

MEM_B_DQ<38>

MEM_B_DQ<39>

MEM_B_DQ<44>

MEM_B_DQ<45>

MEM_B_DQS_N<5>

MEM_B_DQS_P<5>

MEM_B_DQ<47>

MEM_B_DQ<46>

MEM_B_DQ<48>

MEM_B_DQ<54>

MEM_B_DM<6>

MEM_B_DQ<53>

MEM_B_DQ<50>

MEM_B_DQ<60>

MEM_B_DQ<61>

MEM_B_DQS_N<7>

MEM_B_DQS_P<7>

MEM_B_DQ<58>

MEM_B_DQ<62>

MEM_EVENT_L

=I2C_SODIMMB_SDA

=I2C_SODIMMB_SCL

DDR3 PLANE STITCHING CAPS (SPACE EVENLY ACROSS PLANE SPLIT)

1

2

C3210

0.1UF

20%
10V
CERM
402

1

C3211

0.1UF

20%
10V

2

CERM
402

PP0V75_S3_MEM_VREFDQ_B

26

15 89

IN

9

IN

15 89

IN

15 89

IN

15 89

IN

15 89

IN

15 89

IN

15 89

IN

15 89

IN

15 89

IN

15 89

IN

15 89

IN

15 89

IN

15 89

IN

15 89

IN

15 89

IN

15 89

BI

15 89

BI

15 89

IN

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

IN

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

21 27 41

OUT

BI

44

IN

DQS0

VSS

VSS
DQ12
DQ13

VSS

VSS
DQ14
DQ15

VSS
DQ20
DQ21

VSS

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3

VSS
DQ30
DQ31

VSS

VSS
DQ4
DQ5
VSS

DQ6
DQ7

DM1

DM2

21
4
6
8
10
12
1413
16
18
2019
22
24
2625
28
30
3231
34
36
3837
40
42
4443
46
48
50
52
54
56
58
60
62
64
6665
68
70
7271

1

C3218

2

0.1UF

20%
10V
CERM
402

CRITICAL

J3200

F-RT-BGA3

DDR3-SODIMM

KEY

516s0706

26

1

C3217

0.1UF

20%
10V

2

CERM
402

DQS0*

(1 OF 2)

RESET*

DQS3*

1

C3216

0.1UF

20%
10V

2

CERM
402

VREFDQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0
VSS

15

DQ2

17

DQ3
VSS

21

DQ8

23

DQ9
VSS

27

DQS1*

29

DQS1
VSS

33

DQ10

35

DQ11
VSS

39

DQ16

41

DQ17
VSS

45

DQS2*

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3
VSS

67

DQ26

69

DQ27
VSS

C3230

2.2UF

20%

6.3V

CERM

402-LF

1

2

MEM_B_DQ<0>

MEM_B_DQ<1>

MEM_B_DM<0>

MEM_B_DQ<2>

MEM_B_DQ<3>

MEM_B_DQ<28>

MEM_B_DQ<24>

MEM_B_DQS_N<3>

MEM_B_DQS_P<3>

MEM_B_DQ<31>

MEM_B_DQ<30>

MEM_B_DQ<9>

MEM_B_DQ<8>

MEM_B_DQS_N<1>

MEM_B_DQS_P<1>

MEM_B_DQ<15>

MEM_B_DQ<10>

MEM_B_DQ<21>

MEM_B_DQ<17>

MEM_B_DM<2>

MEM_B_DQ<18>

MEM_B_DQ<22>

1

C3236

0.1UF

20%
10V

2

CERM

402

C3214

0.1UF

20%
10V
CERM
402

1

2

PP0V75_S3_MEM_VREFCA_B

1

C3212

0.1UF

20%
10V

2

CERM
402

44

1

2

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

1

C3235

2.2UF

20%

6.3V

2

CERM

402-LF

=PP0V75_S0_MEM_VTT_B

C3213

0.1UF

20%
10V
CERM
402

1

2

BI

BI

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI

C3231

0.1UF

20%
10V

CERM

402

1

2

C3215

0.1UF

20%
10V
CERM
402

8

1

C3219

0.1UF

20%
10V

2

CERM
402

MEM_B_DQ<4>

MEM_B_DQ<5>

MEM_B_DQS_N<0>

MEM_B_DQS_P<0>

MEM_B_DQ<6>

MEM_B_DQ<7>

MEM_B_DQ<29>

MEM_B_DQ<25>

MEM_B_DM<3>

MEM_RESET_L

MEM_B_DQ<26>

MEM_B_DQ<27>

MEM_B_DQ<13>

MEM_B_DQ<12>

MEM_B_DM<1>

MEM_B_DQ<14>

MEM_B_DQ<11>

MEM_B_DQ<20>

MEM_B_DQ<16>

MEM_B_DQS_N<2>

MEM_B_DQS_P<2>

MEM_B_DQ<19>

MEM_B_DQ<23>

1

2

C3220

0.1UF

20%
10V
CERM
402

1

2

C3221

0.1UF

20%
10V
CERM
402

1

C3222

0.1UF

20%
10V

2

CERM
402

1

C3223

0.1UF

2

20%
10V
CERM
402

D

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

IN

27 29

IN

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

IN

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

15 89

BI

C

B

"Expansion" (bottom) slot

DDR3 SO-DIMM Connector B

SYNC_MASTER=BEN_K20

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

D

NONE

DRAWING NUMBER

051-8071

SHT

28 98

OF

SYNC_DATE=07/14/2008

REV.

B

A

8

76

5

4

3

2

1

87

www.vinafix.vn

6

5

4

3

21

D

D

DDR3 RESET Support

MCP79 cannot control this signal directly since it must be high in sleep and MCP MEM rails are not powered in sleep.

=PP1V5_S3_MEMRESET

8

3.3V input must be stable before
before 1.5V starts to rise to

=PP3V3_S5_MEMRESET

8

C

MEMRESET_HW

MEMRESET_HW

avoid glitch on MEM_RESET_L.

1

R3300

10K

5%
1/16W
MF-LF

402

2

MEM_RESET_RC_L

MEMRESET_HW

1

R3301

1/16W
MF-LF

20K

1

C3300

0.1UF

5%

20%
10V

2

CERM

402

402

2

5

MEMRESET_HW

1

R3305

20K

5%
1/16W
MF-LF
402

2

MEM_RESET

MEMRESET_HW

3

Q3305

MMDT3904-X-G

SOT-363-LF

4

2

1

R3310

1K

5%
1/16W
MF-LF
402

2

MEMRESET_HW

6

Q3305

MMDT3904-X-G

SOT-363-LF

1

MEM_RESET_L

MEMRESET_MCP

1

R3309

0

5%
1/16W
MF-LF
402

2

27 28

OUT

C

MCP_MEM_RESET_L

16

IN

B

B

DDR3 Support

051-8071

SHT

SYNC_DATE=04/01/2008

OF

29 98

A

REV.

B

A

SYNC_MASTER=M98_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

SCALE

NONE

8

76

5

4

3

2

1

87

www.vinafix.vn

PCIE_MINI_PRSNT_L

17

OUT

3

D

Q3401

SSM6N15FEAPE

SOT563

5

SG

4

D

17

OUT

MINI_CLKREQ_L

6

D

SG

1

Q3401

SSM6N15FEAPE

SOT563

2

6

AP_PWR_EN

5

21 33

IN

4

5V S3 WLAN FET

MOSFET

CHANNEL

RDS(ON)

LOADING 0.8 A (EDP)

3

FDC606P

P-TYPE

26 mOhm @4.5V

21

D

20347-325E-12

C

B

CRITICAL
518S0610

J3401

F-RT-SM

31

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

32

FDC606P_G

6521

C3450

0.1UF

10%
16V
X5R
402

Q3450

SOT-6

D

21

4

S

G

3

P5VWLAN_SS

C3451

0.033UF

=PP5V_S3_WLAN

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

1

1

10%
16V

2

X5R
402

R3450

100K

5%
1/16W
MF-LF

402

R3451

10K

5%
1/16W
MF-LF
402

2

21

VOLTAGE=5V

PM_WLAN_EN_L

8

33

IN

C

PCIE_MINI_D2R_P
PCIE_MINI_D2R_N

PCIE_MINI_R2D_P

7

90

PCIE_MINI_R2D_N

7

90

PCIE_CLK100M_MINI_CONN_P

7

96

PCIE_CLK100M_MINI_CONN_N

96

7

MINI_CLKREQ_Q_L

7

PCIE_WAKE_L

L3404

PLACEMENT_NOTE=Place close to J3401.

C3431

21

0.1uF

21

16V

C3430

7

17 90

OUT

7

17 90

OUT

7

17 31

OUT

10% 16V X5R

0.1uF

402X5R10%

PLACEMENT_NOTE=Place close to J3401.

L3401

90-OHM-100MA

DLP11S

SYM_VER-1

43

PLACEMENT_NOTE=Place close to J3401.

21

PCIE_MINI_R2D_C_P

402

PCIE_MINI_R2D_C_N

AIRPORT

PCIE_CLK100M_MINI_P

PCIE_CLK100M_MINI_N

1000 mA peak

750 mA nominal max

IN

IN

17 90

17 90

IN

IN

17 90

17 90

PP5V_WLAN

7

MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.5 mm
VOLTAGE=5V

FERR-120-OHM-1.5A

C3422

0.1uF

20%
10V

CERM

402

PLACEMENT_NOTE=Place close to J3401.

0402-LF

21

1

2

C3421

PP5V_WLAN_F PP5V_WLAN_R

30

MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.5 mm
VOLTAGE=5V

1

1

C3420

0.1uF

20%
10V

CERM

402

PLACEMENT_NOTE=Place close to Q3450.

10UF

20%
10V

2

2

X5R
805

PLACEMENT_NOTE=Place close to Q3450.

R3404

5%
1/10W
MF-LF

603

0

21

MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.5 mm
VOLTAGE=5V

L3406

PP3V3_S3_BT_F

NC

PP5V_S3_BTCAMERA_F

USB_CAMERA_CONN_P

7

96

USB_CAMERA_CONN_N

7

96

CONN_USB2_BT_P

7

96

CONN_USB2_BT_N

7

96

7

I2C_ALS_SDA
I2C_ALS_SCL

BI

IN

44

44

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V

L3402

90-OHM
DLP0NS

SYM_VER-1

43

PLACEMENT_NOTE=Place close to J3401.

21

ALS
CAMERA

USB_CAMERA_P

USB_CAMERA_N

275 mA peak

206 mA nominal max

C3452

0.1uF

20 91

OUT

20 91

OUT

CERM

1

20%
10V

2

402

L3405

21

FERR-120-OHM-1.5A

0402-LF

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V

=PP5V_S3_BTCAMERA

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V

8

C3462

0.1uF

CERM

20%
10V

402

21

FERR-120-OHM-1.5A

1

2

0402-LF

=PP3V3_S3_BT

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V

8

B

L3403

90-OHM
DLP0NS

SYM_VER-1

43

PLACEMENT_NOTE=Place close to J3401.

21

BLUETOOTH

USB_BT_P

USB_BT_N

20 91

BI

20 91

BI

MINI_RESET_CONN_L

7

A

8

76

TC7SZ08AFEAPE

SOT665

4

=PP3V3_S3_WLAN

5

A

Y

U3401

B

3

2

WLAN_SMIT_BUF

1

MINI_RESET_L

8

U3402

74LVC1G17DRL

SOT-553

25

IN

PP5V_WLAN_F

1

R3453

33K

5%
1/16W

1UF

6.3V
CERM

1

10%

2

402

MF-LF
402

2

WLAN_SMIT_RC

1

R3454

62K

5%
1/16W
MF-LF
402

2

5

4

2

NC

13

NC

C3453

5

30

R3455

1

5%
1/16W
MF-LF

402

21

WLAN_SMIT_RC_FET

3

D

2

Q3402

SSM3K15FV

SOD-VESM-HF

1

GS

4

Right Clutch Connector

SYNC_MASTER=M98_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

3

2

SCALE

NONE

051-8071

SHT

SYNC_DATE=05/01/2008

OF

30 98

1

A

REV.

B