ANALOG DEVICES AD679 Service Manual

14-Bit 128 kSPS

a

FEATURES
AC and DC Characterized and Specified

(K, B, T Grades)
128k Conversions per Second
1 MHz Full Power Bandwidth
500 kHz Full Linear Bandwidth
78 dB S/N+D (K, B, T Grades)
Twos Complement Data Format (Bipolar Mode)
Straight Binary Data Format (Unipolar Mode)
10 M Input Impedance
8-Bit Bus Interface
On-Board Reference and Clock
10 V Unipolar or Bipolar Input Range
Pin Compatible with AD678 12-Bit, 200 kSPS ADC
MIL-STD-883 Compliant Versions Available

GENERAL DESCRIPTION

The AD679 is a complete, multipurpose 14-bit monolithic
analog-to-digital converter, consisting of a sample-and-hold am­plifier (SHA), a microprocessor-compatible bus interface, a volt­age reference, and clock generation circuitry.

The AD679 is specified for ac (or dynamic) parameters such as
S/N+D ratio, THD, and IMD, which are important in signal
processing applications. In addition, the AD679K, B, and T
grades are fully specified for dc parameters that are important in
measurement applications.

The 14 data bits are accessed in two read operations (8 + 6),
with left justification. Data format is straight binary for unipolar
mode and twos complement binary for bipolar mode. The input
has a full-scale range of 10 V with a full power bandwidth of
1 MHz and a full linear bandwidth of 500 kHz. High input
impedance (10 MΩ) allows direct connection to unbuffered
sources without signal degradation. Conversions can be initiated
either under microprocessor control or by an external clock
asynchronous to the system clock.

This product is fabricated on Analog Devices’ BiMOS process,
combining low power CMOS logic with high precision, low
noise bipolar circuits; laser-trimmed thin-film resistors provide
high accuracy. The converter utilizes a recursive subranging
algorithm that includes error correction and flash converter
circuitry to achieve high speed and resolution.

The AD679 operates from +5 V and ±12 V supplies and dissipates
560 mW (typ). The part is available in 28-lead plastic DIP,
ceramic DIP, and 44 J-leaded ceramic surface-mount packages.

*Protected by U.S. Patent Nos. 4,804,960; 4,814,767; 4,833,345; 4,250,445;

4,808,908; RE 30,586

REV. D

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

Complete Sampling ADC

AD679

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

1. COMPLETE INTEGRATION: The AD679 minimizes
external component requirements by combining a high
speed sample-and-hold amplifier (SHA), ADC, 5 V refer­ence, clock, and digital interface on a single chip. This
provides a fully specified sampling A/D function unattain­able with discrete designs.

2. SPECIFICATIONS: The AD679K, B, and T grades provide
fully specified and tested ac and dc parameters. The AD679J,
A, and S grades are specified and tested for ac parameters; dc
accuracy specifications are shown as typicals. DC specifica­tions (such as INL, gain, and offset) are important in control
and measurement applications. AC specifications (such as
S/N+D ratio, THD, and IMD) are of value in signal process­ing applications.

3. EASE OF USE: The pinout is designed for easy board layout,
and the two-read output provides compatibility with 8-bit
buses. Factory trimming eliminates the need for calibration
modes or external trimming to achieve rated performance.

4. RELIABILITY: The AD679 utilizes Analog Devices’ mono­lithic BiMOS technology. This ensures long-term reliability
compared to multichip and hybrid designs.

5. UPGRADE PATH: The AD679 provides the same pinout as
the 12-bit, 200 kSPS AD678 ADC.

6. The AD679 is available in versions compliant with MIL­STD-883. Refer to the Analog Devices Military Products
Databook or current AD679/883B data sheet for detailed
specifications.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

*

AD679–SPECIFICATIONS

(T

to T

, VCC = +12 V  5%, VEE = –12 V  5%, VDD = +5 V  10%, f

MAX

1

AC SPECIFICATIONS

MIN

unless otherwise noted)

AD679J/A/S AD679K/B/T

Parameter Min Typ Max Min Typ Max Unit

SIGNAL-TO-NOISE AND DISTORTION (S/N+D) RATIO

2

–0.5 dB Input (Referred to –0 dB Input) 76 79 78 81 dB
–20 dB Input (Referred to –20 dB Input) 58 59 60 61 dB
–60 dB Input (Referred to –60 dB Input) 18 19 20 21 dB

TOTAL HARMONIC DISTORTION (THD)

3

@ 25°C –90 –82 –90 –82 dB

0.003 0.006 0.003 0.006 %

to T

T

MIN

MAX

–88 –82 –88 –82 dB

0.004 0.008 0.004 0.008 %

PEAK SPURIOUS OR PEAK HARMONIC COMPONENT –90 –82 –90 –82 dB

FULL POWER BANDWIDTH 1 1 MHz

FULL LINEAR BANDWIDTH 500 500 kHz

INTERMODULATION DISTORTION (IMD)

4

2nd Order Products –90 –82 –90 –82 dB
3rd Order Products –90 –82 –90 –82 dB

NOTES

1

flN amplitude = –0.5 dB (9.44 V p-p) bipolar mode full scale unless otherwise indicated. All measurements referred to a –0 dB (9.997 V p-p) input signal
unless otherwise noted.

2

See TPC 3 for higher frequencies and other input amplitudes.

3

See TPCs 1 and 2 for higher frequencies and other input amplitudes.

4

fA = 9.08 kHz, fB = 9.58 kHz, with f

Specifications subject to change without notice.

100 kSPS. See Definition of Specifications section.

SAMPLE

= 128 kSPS, fIN = 10.009 kHz,

SAMPLE

DIGITAL SPECIFICATIONS

(All device types T

MIN

to T

, VCC = +12 V  5%, VEE = –12 V  5%, VDD = +5 V  10%)

MAX

Parameter Test Conditions Min Max Unit

LOGIC INPUTS

V

IH

V

IL

I

IH

I

IL

C

IN

High Level Input Voltage 2.0 V

DD

Low Level Input Voltage 0 0.8 V
High Level Input Current VIN = 5 V –10 +10 µA
Low Level Input Current VIN = 0 V –10 +10 µA
Input Capacitance 10 pF

V

LOGIC OUTPUTS

V

OH

V

OL

I

OZ

C

OZ

NOTES

1

flN amplitude = –0.5 dB (9.44 V p-p) bipolar mode full scale unless otherwise indicated. All measurements referred to a –0 dB (9.997 V p-p) input signal
unless otherwise noted.

2

See TPC 3 for higher frequencies and other input amplitudes.

3

See TPCs 1 and 2 for higher frequencies and other input amplitudes.

4

fA = 9.08 kHz, fB = 9.58 kHz, with f

Specifications subject to change without notice.

High Level Output Voltage IOH = 0.1 mA 4.0 V

= 0.5 mA 2.4 V

I

OH

Low Level Output Voltage IOL = 1.6 mA 0.4 V
High Z Leakage Current VIN = 0 or 5 V –10 +10 µA
High Z Output Capacitance 10 pF

100 kSPS. See Definition of Specifications section.

SAMPLE

–2–

REV. D

(T

to T

DC SPECIFICATIONS

MIN

, VCC = +12 V  5%, VEE = –12 V  5%, VDD = +5 V  10%, unless otherwise noted)

MAX

AD679J/A/S AD679K/B/T

Parameter Min Typ Max Min Typ Max Unit

TEMPERATURE RANGE

J, K Grades 0 70 0 70 °C
A, B Grades –40 +85 –40 +85 °C
S, T Grades –55 +125 –55 +125 °C

ACCURACY

Resolution 14 14 Bits
Integral Nonlinearity (INL) 2 1 2.5 LSB
Differential Nonlinearity (DNL) 14 14 Bits
Unipolar Zero Error
Bipolar Zero Error1 (@ 25°C) 0.08 0.05 0.07 % FSR
Gain Error

1, 3

Temperature Drift

Unipolar Zero

1

(@ 25°C) 0.08 0.05 0.07 % FSR

(@ 25°C) 0.12 0.09 0.11 % FSR

4

J, K Grades 0.04 0.04 0.05 % FSR
A, B Grades 0.05 0.05 0.07 % FSR
S, T Grades 0.09 0.09 0.10 % FSR

Bipolar Zero

4

J, K Grades 0.02 0.02 0.04 % FSR
A, B Grades 0.04 0.04 0.05 % FSR
S, T Grades 0.08 0.08 0.09 % FSR

4

Gain

J, K Grades 0.09 0.09 0.11 % FSR
A, B Grades 0.10 0.10 0.16 % FSR
S, T Grades 0.20 0.20 0.25 % FSR

5

Gain

J, K Grades 0.04 0.04 0.05 % FSR
A, B Grades 0.05 0.05 0.07 % FSR
S, T Grades 0.09 0.09 0.10 % FSR

ANALOG INPUT

Input Ranges

Unipolar Mode 0 +10 0 +10 V

Bipolar Mode –5 +5 –5 +5 V
Input Resistance 10 10 MΩ
Input Capacitance 10 10 pF
Input Settling Time 1.5 1.5 µs
Aperture Delay 10 10 ns
Aperture Jitter 150 150 ps

INTERNAL VOLTAGE REFERENCE

Output Voltage

6

4.98 5.02 4.98 5.02 V

External Load

Unipolar Mode 1.5 1.5 mA

Bipolar Mode 0.5 0.5 mA

POWER SUPPLIES

Power Supply Rejection

= +12 V ± 5% 6 6 LSB

V

CC

V

= –12 V ± 5% 6 6 LSB

EE

V

= +5 V ± 10% 6 6 LSB

DD

Operating Current

I

CC

I

EE

I

DD

Power Consumption 560 745 560 745 m

NOTES

1

Adjustable to zero. See Figures 5 and 6.

2

% FSR = percent of full-scale range.

3

Includes internal voltage reference error.

4

Includes internal voltage reference drift.

5

Excludes internal voltage reference drift.

6

With maximum external load applied.
Specifications shown in boldface are tested on all devices at final electrical test with worst case supply voltages at T
calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested.

Specifications subject to change without notice.

18 20 18 20 mA
25 34 25 34 mA
8 12 8 12 mA

, 25°C and T

MIN

. Results from those tests are used to

MAX

W

AD679

2

REV. D

–3–

AD679

TIMING SPECIFICATIONS

(All device types T
 5%, VDD = +5 V  10%)

MIN

to T

, VCC = +12 V  5%, VEE = –12 V

MAX

Parameter Symbol Min Max Unit

SC Delay t
Conversion Time t
Conversion Rate

1

Convert Pulse Width t
Aperture Delay t
Status Delay t
Access Time

Float Delay

2, 3

5

Output Delay t
Format Setup t
OE Delay t
Read Pulse Width t
Conversion Delay t
EOCEN Delay t

NOTES

1

Includes acquisition time.

2

Measured from the falling edge of OE/EOCEN (0.8 V) to the time at which the
data lines/EOC cross 2.0 V or 0.8 V. See Figure 4.

3

C

= 100 pF.

OUT

4

C

= 50 pF.

OUT

5

Measured from the rising edge of OE/EOCEN (2.0 V) to the time at which the output voltage changes by 0.5. See Figure 4; C
= 10 pF.

Specifications subject to change without notice.

SC

C

t

CR

CP

AD

SD

t

BA

t

FD

OD

FS

OE

RP

CD

EO

50 ns

6.3 µs

7.8 µs

0.097 3.0 µs
520ns
0 400 ns
10 100 ns
10 57

4

ns

10 80 ns

0ns
100 ns
20 ns
195 ns
400 ns
50 ns

OUT

NOTES

1

IN ASYNCHRONOUS MODE, STATE OF CS DOES NOT AFFECT OPERATION.

SEE THE START CONVERSION TRUTH TABLE FOR DETAILS.

2

EOCEN = LOW (SEE FIGURE 3). IN SYNCHRONOUS MODE, EOC IS A THREE-

STATE OUTPUT. IN ASYNCHRONOUS MODE, EOC IS AN OPEN DRAIN OUTPUT.

3

DATA SHOULD NOT BE ENABLED DURING A CONVERSION.

Figure 1. Conversion Timing

Figure 2. Output Timing

–4–

NOTE

1

EOC IS A THREE-STATE OUTPUT IN SYNCHRONOUS MODE
AND AN OPEN DRAIN OUTPUT IN ASYNCHRONOUS. ACCESS (t
AND FLOAT (t
ASYNCHRONOUS MODE WHERE THEY ARE A FUNCTION OF THE
TIME CONSTANT FORMED BY THE 10pF OUTPUT CAPACITANCE
AND THE PULL-UP RESISTOR.

) TIMING SPECIFICATIONS DO NOT APPLY IN

FD

)

BA

Figure 3. EOC Timing

TEST VCP C

ACCESS TIME HIGH Z TO LOGIC LOW 5V 100pF
FLOAT TIME LOGIC HIGH TO HIGH Z 0V 10pF
ACCESS TIME HIGH Z TO LOGIC HIGH 0V 100pF
FLOAT TIME LOGIC LOW TO HIGH Z 5V 10pF

I

OL

D

OUT

C

OUT

I

OH

V

CP

OUT

Figure 4. Load Circuit for Bus Timing Specifications

REV. D

AD679

ABSOLUTE MAXIMUM RATINGS

1

With
Respect

Specification To Min Max Unit

V

CC

V

EE

2

V

CC

V

DD

AGND –0.3 +18 V
AGND –18 +0.3 V
V

EE

–0.3 +26.4 V

DGND 0 +7 V
AGND DGND –1 +1 V
AIN, REF

IN

AGND V

EE

V

CC

V
Digital Inputs DGND –0.5 +7 V
Digital Outputs DGND –0.5 V

+ 0.3 V

DD

Max Junction

Temperature 175 °C

ORDERING GUIDE

Model Package Range Specified Option

With
Respect

Specification To Min Max Unit

Operating
Temperature

J and K Grades 0 70 °C
A and B Grades –40 +85 °C

S and T Grades –55 +125 °C
Storage Temperature –65 +150 °C
Lead Temperature

(10 sec max) 300 °C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

The AD679 is not designed to operate from ⫾15 V supplies.

1

Temperature Tested and Package

2

AD679JN 28-Pin Plastic DIP 0°C to +70°CAC N-28
AD679KN 28-Pin Plastic DIP 0°C to +70°C AC + DC N-28
AD679JD 28-Pin Ceramic DIP 0°C to +70°CAC D-28
AD679KD 28-Pin Ceramic DIP 0°C to +70°C AC + DC D-28
AD679AD 28-Pin Ceramic DIP –40°C to +85°CAC D-28
AD679BD 28-Pin Ceramic DIP –40°C to +85°C AC + DC D-28
AD679SD 28-Pin Ceramic DIP –55°C to +125°CAC D-28
AD679TD 28-Pin Ceramic DIP –55°C to +125°C AC + DC D-28
AD679AJ 44-Lead Ceramic JLCC –40°C to +85°CAC J-44
AD679BJ 44-Lead Ceramic JLCC –40°C to +85°C AC + DC J-44
AD679SD/883B

NOTES

1

For parallel read (14-bits) interface to 16-bit buses, see AD779.

2

N = Plastic DIP; D = Ceramic DIP; J = J-Leaded Ceramic Chip Carrier.

3

For details, grade, and package offerings screened in accordance with MIL-STD-883, refer to the
Analog Devices Military Products Databook or the current AD679/883B data sheet.

3

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD679 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

REV. D

–5–