Analog Devices AD677KR, AD677KN, AD677KD, AD677JR, AD677JN Datasheet

16-Bit 100 kSPS

a

FEATURES
Autocalibrating
On-Chip Sample-Hold Function
Serial Output
16 Bits No Missing Codes
61 LSB INL
–99 dB THD
92 dB S/(N+D)
1 MHz Full Power Bandwidth

PRODUCT DESCRIPTION

The AD677 is a multipurpose 16-bit serial output analog-to­digital converter which utilizes a switched-capacitor/charge
redistribution architecture to achieve a 100 kSPS conversion
rate (10 µs total conversion time). Overall performance is opti-
mized by digitally correcting internal nonlinearities through
on-chip autocalibration.

The AD677 circuitry is segmented onto two monolithic chips—
a digital control chip fabricated on Analog Devices DSP CMOS
process and an analog ADC chip fabricated on our BiMOS II
process. Both chips are contained in a single package.

The AD677 is specified for ac (or “dynamic”) parameters such
as S/(N+D) Ratio, THD and IMD which are important in sig­nal processing applications. In addition, dc parameters are
specified which are important in measurement applications.

The AD677 operates from +5 V and ± 12 V supplies and typi­cally consumes 450 mW using a 10 V reference (360 mW with
5 V reference) during conversion. The digital supply (V
separated from the analog supplies (V

, VEE) for reduced digi-

CC

tal crosstalk. An analog ground sense is provided to remotely
sense the ground potential of the signal source. This can be use­ful if the signal has to be carried some distance to the A/D con­verter. Separate analog and digital grounds are also provided.

The AD677 is available in a 16-pin narrow plastic DIP, 16-pin
narrow side-brazed ceramic package, or 28-lead SOIC. A paral­lel output version, the AD676, is available in a 28-pin ceramic
or plastic DIP. All models operate over a commercial tempera­ture range of 0°C to +70°C or an industrial range of –40°C to
+85°C.

DD

) is

Sampling ADC

AD677

FUNCTIONAL BLOCK DIAGRAM

SAR
ALU
RAM

).

A CHIP

COMP

D CHIP

AD677

15

14

3

BUSY

SCLK

SDATA

V

10

AGND SENSE

V

REF

AGND

CAL
CLK

SAMPLE

IN

9

INPUT

BUFFERS

11

8

16

MICROCODED
CONTROLLER

2

1

16-BIT

DAC

CAL
DAC

LOGIC TIMING

LEVEL TRANSLATORS

PRODUCT HIGHLIGHTS

1. Autocalibration provides excellent dc performance while
eliminating the need for user adjustments or additional exter­nal circuitry.

2. ± 5 V to ±10 V input range (±V

REF

3. Available in 16-pin 0.3" skinny DIP or 28-lead SOIC.

4. Easy serial interface to standard ADI DSPs.

5. TTL compatible inputs/outputs.

6. Excellent ac performance: –99 dB THD, 92 dB S/(N+D)
peak spurious –101 dB.

7. Industry leading dc performance: 1.0 LSB INL, ± 1 LSB full
scale and offset.

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] Fax: [phone]

AD677–SPECIFICATIONS

AC SPECIFICATIONS

(T

MIN

to T

= +12 V 6 5%, V

MAX, VCC

= –12 V 6 5%, VDD = +5 V 6 10%)

EE

1

AD677J/A AD677K/B

Parameter Min Typ Max Min Typ Max Units

Total Harmonic Distortion (THD)

@ 83 kSPS, T

MIN

to T

MAX

2

–97 –92 –99 –95 dB

@ 100 kSPS, +25°C –97 –92 –99 –95 dB
@ 100 kSPS, T

Signal-to-Noise and Distortion Ratio (S/(N+D))

@ 83 kSPS, T

MIN

MIN

to T

to T

MAX

MAX

2, 3

–93 –95 dB

89 91 90 92 dB

@ 100 kSPS, +25°C89919092dB

@ 100 kSPS, T
Peak Spurious or Peak Harmonic Component –101 –101 dB
Intermodulation Distortion (IMD)

MIN

to T

MAX

89 90 dB

4

2nd Order Products –102 –102 dB

3rd Order Products –98 –98 dB
Full Power Bandwidth 1 1 MHz
Noise 160 160 µV rms

DIGITAL SPECIFICATIONS

(for all grades T

MIN

to T

, VCC = +12 V 6 5%, VEE = –12 V 6 5%, VDD = +5 V 6 10%)

MAX

Parameter Test Conditions Min Typ Max Units

LOGIC INPUTS
V

IH

V

IL

I

IH

I

IL

C

IN

High Level Input Voltage 2.0 VDD + 0.3 V
Low Level Input Voltage –0.3 0.8 V
High Level Input Current VIH = V
Low Level Input Current V

= 0 V –10 +10 µA

IL

DD

–10 +10 µA

Input Capacitance 10 pF

LOGIC OUTPUTS
V

OH

V

OL

NOTES

1

V

= 10.0 V, Conversion Rate = 100 kSPS, flN = 1.0 kHz, VIN = –0.05 dB, Bandwidth = 50 kHz unless otherwise indicated. All measurements referred to a 0 dB

REF

(20 V p-p) input signal. Values are post-calibration.

2

For other input amplitudes, refer to Figure 12.

3

For dynamic performance with different reference values see Figure 11.

4

fa = 1008 Hz, fb = 1055 Hz. See Definition of Specifications section and Figure 16.

Specifications subject to change without notice.

High Level Output Voltage IOH = 0.1 mA VDD – 1 V V

I

= 0.5 mA 2.4 V

OH

Low Level Output Voltage IOL = 1.6 mA 0.4 V

–2–

REV. A

AD677

DC SPECIFICATIONS

(T

to T

MIN

, VCC = +12 V 6 5%, VEE = –12 V 6 5%, VDD = +5 V 6 1O%)

MAX

AD677J/A AD677K/B

Parameter Min Typ Max Min Typ Max Units

TEMPERATURE RANGE

J, K Grades 0 +70 0 +70 °C
A, B Grades –40 +85 –40 +85 °C

ACCURACY

Resolution 16 16 Bits
Integral Nonlinearity (INL)

@ 83 kSPS, T

MIN

to T

MAX

±1 ±1 ±1.5 LSB

@ 100 kSPS, +25°C ±1+1±1.5 LSB

@ 100 kSPS, T
Differential Nonlinearity (DNL)–No Missing Codes 16 16 Bits
Bipolar Zero Error
Positive, Negative FS Errors

MIN

2

to T

MAX

2

±2 ±2 LSB
±2 ±4 ±1 ±3 LSB

@ 83 kSPS ±2 ±4 ±1 ±3 LSB

@ 100 kSPS, +25°C ±2 ±4 ±1 ±3 LSB

@ 100 kSPS ±4 ±4 LSB

TEMPERATURE DRIFT

3

Bipolar Zero ±0.5 ±0.5 LSB
Postive Full Scale ±0.5 ±0.5 LSB
Negative Full Scale ±0.5 ±0.5 LSB

1

VOLTAGE REFERENCE INPUT RANGE4 (V

ANALOG INPUT

Input Range (V

5

) ±V

IN

)5 10 5 10V

REF

REF

±V

REF

V

Input Impedance * *
Input Settling Time 2 2 µs
Input Capacitance During Sample 50* 50* pF
Aperture Delay 6 6 ns
Aperture Jitter 100 100 ps

POWER SUPPLIES

Power Supply Rejection

V

= +12 V ± 5% ±0.5 ±0.5 LSB

CC

V

= –12 V ± 5% ±0.5 ±0.5 LSB

EE

V

= +5 V ± 10% ±0.5 ±0.5 LSB

DD

6

Operating Current

V

= +5 V

REF

I

I

I

CC
EE
DD

14.5 18 14.5 18 mA

14.5 18 14.5 18 –mA
35 35mA

Power Consumption 360 480 360 480 mW

V

= +10 V

REF

I

I

I

CC
EE
DD

18 24 18 24 mA
18 24 18 24 –mA
35 35mA

Power Consumption 450 630 450 630 mW

NOTES

1

V

= 10.0 V, Conversion Rate = 100 kSPS unless otherwise noted. Values are post-calibration.

REF

2

Values shown apply to any temperature from T

3

Values shown are based upon calibration at +25°C with no additional calibration at temperature. Values shown are the typical variation from the value at +25 °C.

4

See “APPLICATIONS” section for recommended voltage reference circuit, and Figure 11 for dynamic performance with other reference voltage values.

5

See “APPLICATIONS” section for recommended input buffer circuit.

6

Typical deviation of bipolar zero, –full scale or +full scale from min to max rating.

*For explanation of input characteristics, see “ANALOG INPUT” section.
Specifications subject to change without notice.

MIN

to T

after calibration at that temperature at nominal supplies.

MAX

REV. A

–3–

AD677

TIMING SPECIFICATIONS

(T

to T

MIN

, VCC = +12 V 6 5%, VEE = –12 V 6 5%, VDD = +5 V 6 10%)

MAX

1

Parameter Symbol Min Typ Max Units

Conversion Period
CLK Period
Calibration Time t
Sampling Time t
Last CLK to SAMPLE Delay
SAMPLE Low t
SAMPLE to Busy Delay t
1st CLK Delay t
CLK Low
CLK High

6

6

CLK to BUSY Delay t
CLK to SDATA Valid t
CLK to SCLK High t
SCLK Low t
SDATA to SCLK High t
CAL High Time t
CAL to BUSY Delay t

NOTES

1

See the “CONVERSION CONTROL” and “AUTOCALIBRATION” sections for detailed explanations of the above timing.

2

Depends upon external clock frequency; includes acquisition time and conversion time. The maximum conversion period is specified to account for the droop of the

internal sample/hold function. Operation at slower rates may degrade performance.

3

tC = t

+ 16 × t

FCD

4

580 ns is recommended for optimal accuracy over temperature (not necessary during calibration cycle).

5

If SAMPLE goes high before the 17th CLK pulse, the device will start sampling approximately 100 ns after the rising edge of the 17th CLK pulse.

6

tCH + tCL = t

CLK

2, 3

4

5

+ t

LCS

.

CLK

and must be greater than 480 ns.

t

C

t

CLK
CT
S

t

LCS
SL
SS
FCD

t

CL

t

CH
CB
CD
CSH
SCL
DSH
CALH
CALB

10 1000 µs
480 ns

85532 t

2 µs

2.1 µs
100 ns

30 75 ns
50 ns
50 ns
50 ns

180 300 ns
50 100 175 ns
100 180 300 ns
50 80 ns
50 80 ns
50 ns

15 50 ns

CLK

CAL

(INPUT)

BUSY

(OUTPUT)

CLK

(INPUT)

SAMPLE*

(INPUT)

BUSY

(OUTPUT)

CLK

(INPUT)

SCLK

(OUTPUT)

SDATA

(OUTPUT)

t

CALH

t

CALB

t

FCD

*

*

SHADED PORTIONS OF INPUT SIGNALS ARE OPTIONAL. FOR BEST PERFORMANCE, WE

RECOMMEND THAT THESE SIGNALS BE HELD LOW EXCEPT WHEN EXPLICITY SHOWN HIGH.

1

t

CH

23

t

CLK

t

CT

t

CL

85530

t

CB

85531 85532

Figure 1. Calibration Timing

t

S

t

SL

t

SB

t

FCD

*

t

CLK

OLD BIT 16

t

CH

1

t

t

CD

t

23

CL

CSH

t

SCL

BIT

MSB

2

t

C

15 16 17

t

DSH

BIT13BIT

t

S

t

CB

t

LCS

BIT

BIT

15

14

16

*

SHADED PORTIONS OF INPUT SIGNALS ARE OPTIONAL. FOR BEST PERFORMANCE, WE

RECOMMEND THAT THESE SIGNALS BE HELD LOW EXCEPT WHEN EXPLICITY SHOWN HIGH.

Figure 2. General Conversion Timing

–4–

REV. A

AD677

WARNING!

ESD SENSITIVE DEVICE

ORDERING GUIDE

Temperature Package

Model Range S/(N+D) Max INL Package Description Option*

AD677JN 0°C to +70°C 89 dB Typ Only Plastic 16-Pin DIP N-16
AD677KN 0°C to +70°C 90 dB ±1.5 LSB Plastic 16-Pin DIP N-16
AD677JD 0°C to +70°C 89 dB Typ Only Ceramic 16-Pin DIP D-16
AD677KD 0°C to +70°C 90 dB ±1.5 LSB Ceramic 16-Pin DIP D-16
AD677JR 0°C to +70°C 89 dB Typ Only Plastic 28-Lead SOIC R-28
AD677KR 0°C to +70°C 90 dB ±1.5 LSB Plastic 28-Lead SOIC R-28
AD677AD –40°C to +85°C 89 dB Typ Only Ceramic 16-Pin DIP D-16
AD677BD –40°C to +85°C 90 dB ±1.5 LSB Ceramic 16-Pin DIP D-16

*D = Ceramic DIP; N = Plastic DIP; R = Small Outline IC (SOIC).

ABSOLUTE MAXIMUM RATINGS*

VCC to VEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +26.4 V

V

to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DD

Vcc to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +18 V

VEE to AGND . . . . . . . . . . . . . . . . . . . . . . . . . .–18 V to +0.3 V

AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V

Digiul Inputs to DGND . . . . . . . . . . . . . . . . . . . . . . 0 to +5.5 V

Analog Inputs, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . (V

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C, 10 sec

Storage Temperature . . . . . . . . . . . . . . . . . . . . .–65°C to +150°C

*Stresses greater than those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

to AGND

REF

+0.3 V) to (VEE –0.3 V)

CC

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD677 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

REV. A

–5–