ANALOG DEVICES AD6649 Service Manual
AD6649
DC
CORRECTION
ADC
THRESHOL D DE TECT
AVDD FDA DRVDD
AD6649
VIN+A
VIN–A
FDB
DC
CORRECTION
REFERENCE
ADC
I
Q
Q
I
VIN–B
VIN+B
D13+/D13–
D0+/D0–
CLK+
CLK–
DCO+
DCO–
DIVIDE 1
TO 8
DUTY
CYCLE
STABILIZER
AGND SDIO SCLK CSB
SPI
PROGRAMMING DATA
THRESHOL D DE TECT
SELECTABLE
FIR
FILTER
SELECTABLE
FIR
FILTER
DIGITAL
INTERLEAVING
f
S
/4
NCO
OR+
OR–
OEBPDWN
DCO
GENERATION
SYNC
MULTICHIP
SYNC
09635-001
DDR LVDS
OUTPUT BUFFER
SELECTABLE
FIR
FILTER
SELECTABLE
FIR
FILTER
32-BIT
TUNING NCO
Data Sheet
FEATURES
SNR = 73.4 dBFS in a 95 MHz bandwidth at
185 MHz A
SFDR = 85 dBc at 185 MHz A
Noise density = −151.2 dBFS/Hz input at 185 MHz, −1 dBFS
A
and 250 MSPS
IN
Total power consumption: 1 W with fixed-frequency NCO,
95 MHz FIR filter
1.8 V supply voltages
LVDS (ANSI-644 levels) outputs
Integer 1-to-8 input clock divider (625 MHz maximum input)
Integrated dual-channel ADC
Sample rates of up to 250 MSPS
IF sampling frequencies to 400 MHz
Internal ADC voltage reference
Flexible input range
1.4 V p-p to 2.1 V p-p (1.75 V p-p nominal)
ADC clock duty cycle stabilizer
95 dB channel isolation/crosstalk
Integrated wideband digital processor
32-bit complex numerically controlled oscillator (NCO)
FIR filter with 2 modes
Real output from an f
Amplitude detect bits for efficient AGC implementation
Energy saving power-down modes
Decimated, interleaved real LVDS data outputs
and 245.76 MSPS
IN
/4 output NCO
S
and 250 MSPS
IN
IF Diversity Receiver
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers (3G)
TD-SCDMA, WiMax, WCDMA,
CDMA2000, GSM, EDGE, LTE
General-purpose software radios
Broadband data applications
GENERAL DESCRIPTION
The AD6649 is a mixed-signal intermediate frequency (IF) receiver
consisting of dual 14-bit, 250 MSPS ADCs and a wideband digital
downconverter (DDC). The AD6649 is designed to support
communications applications, where low cost, small size, wide
bandwidth, and versatility are desired.
The dual ADC cores feature a multistage, differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth inputs supporting a variety of
user-selectable input ranges. An integrated voltage reference
eases design considerations. A duty cycle stabilizer is provided to
compensate for variations in the ADC clock duty cycle, allowing
the converters to maintain excellent performance.
FUNCTIONAL BLOCK DIAGRAM
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Figure 1.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved.
www.analog.com
AD6649 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Product Highlights ........................................................................... 3
Specifications ..................................................................................... 4
ADC DC Specifications ................................................................. 4
ADC AC Specifications ................................................................. 5
Digital Specifications ..................................................................... 6
Switching Specifications ................................................................ 8
Timing Specifications .................................................................. 9
Absolute Maximum Ratings .......................................................... 10
Thermal Characteristics ............................................................ 10
ESD Caution ................................................................................ 10
Pin Configuration and Function Descriptions ........................... 11
Typical Performance Characteristics ........................................... 13
Equivalent Circuits ......................................................................... 16
Theory of Operation ...................................................................... 17
ADC Architecture ...................................................................... 17
Analog Input Considerations .................................................... 17
Voltage Reference ....................................................................... 19
Clock Input Considerations ...................................................... 19
Power Dissipation and Standby Mode ..................................... 20
Digital Outputs ........................................................................... 21
Overrange (OR) .......................................................................... 21
Digital Processing ........................................................................... 22
Numerically Controlled Oscillator (NCO) ............................. 22
NCO and FIR Filter Modes ....................................................... 22
fS/4 Fixed-Frequency NCO ....................................................... 22
Numerically Controlled Oscillator (NCO) ................................. 23
Frequency Translation ............................................................... 23
NCO Synchronization ............................................................... 23
NCO Amplitude and Phase Dither .......................................... 23
FIR Filters ........................................................................................ 24
FIR Synchronization .................................................................. 24
Filter Performance ...................................................................... 24
Output NCO ............................................................................... 25
ADC Overrange and Gain Control .............................................. 26
ADC Overrange (OR) ................................................................ 26
Gain Switching ............................................................................ 26
DC Correction ................................................................................ 27
Channel/Chip Synchronization .................................................... 28
Serial Port Interface (SPI) .............................................................. 29
Configuration Using the SPI ..................................................... 29
Hardware Interface ..................................................................... 29
SPI Accessible Features .............................................................. 30
Memory Map .................................................................................. 31
Reading the Memory Map Register Table ............................... 31
Memory Map Register Table ..................................................... 32
Memory Map Register Description ......................................... 36
Applications Information .............................................................. 39
Design Guidelines ...................................................................... 39
Outline Dimensions ....................................................................... 40
Ordering Guide .......................................................................... 40
REVISION HISTORY
9/11—Rev. 0 to Rev. A
Changes to Table 1 ............................................................................ 4
Changes to Table 3 ............................................................................ 6
Changes to Table 4 ............................................................................ 8
Changes to Table 8 .......................................................................... 11
Added Overrange (OR) Section ................................................... 21
Changes to Channel/Chip Synchronization Section ................. 28
Change to the NCO/FIR SYNC Pin Control (Register 0x59) .. 38
4/11—Revision 0: Initial Ve r si o n
Rev. A | Page 2 of 40
Data Sheet AD6649
ADC data outputs are internally connected directly to the digital
downconverter (DDC) of the receiver. The digital receiver has
two channels and provides processing flexibility. Each receive
channel has four cascaded signal processing stages: a 32-bit
frequency translator (numerically controlled oscillator (NCO)),
an optional sample rate converter, a fixed FIR filter, and an f
/4
S
fixed-frequency NCO.
In addition to the receiver DDC, the AD6649 has several
functions that simplify the automatic gain control (AGC)
function in the system receiver. The programmable threshold
detector allows monitoring of the incoming signal power using
the fast detect output bits of the ADC. If the input signal level
exceeds the programmable threshold, the fast detect indicator goes
high. Because this threshold indicator has low latency, the user
can quickly turn down the system gain to avoid an overrange
condition at the ADC input.
After digital processing, data is routed directly to the 14-bit
output port. These outputs operate at ANSI or reduced swing
LVDS signal levels.
The AD6649 receiver digitizes a wide spectrum of IF frequencies.
Each receiver is designed for simultaneous reception of the main
channel and the diversity channel. This IF sampling architecture
greatly reduces component cost and complexity compared with
traditional analog techniques or less integrated digital methods.
In diversity applications, the output data format is real due to
the final NCO, which shifts the output center frequency to f
S
/4.
Flexible power-down options allow significant power savings,
when desired.
Programming for setup and control is accomplished using a 3-pin
SPI-compatible serial interface.
The AD6649 is available in a 64-lead LFCSP and is specified over
the industrial temperature range of −40°C to +85°C. This
product is protected by a U.S. patent.
PRODUCT HIGHLIGHTS
1. Integrated dual, 14-bit, 250 MSPS ADCs.
2. Integrated wideband filter and 32-bit complex NCO.
3. Fast overrange and threshold detect.
4. Proprietary differential input maintains excellent SNR
performance for input frequencies of up to 400 MHz.
5. SYNC input allows synchronization of multiple devices.
6. 3-pin, 1.8 V SPI port for register programming and register
readback.
Rev. A | Page 3 of 40
AD6649 Data Sheet
AVDD
SPECIFICATIONS
ADC DC SPECIFICATIONS
AVDD = 1. 8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input,1 1.75 V p-p full-scale input range,
duty cycle stabilizer (DCS) enabled, NCO enabled, FIR filter enabled, unless otherwise noted.
Table 1.
Parameter Temperature Min Typ Max Unit
RESOLUTION Full 14 Bits
ACCURACY
No Missing Codes Full Guaranteed
Offset Error Full ±10 mV
Gain Error Full −5.5 +2.5 %FSR
MATCHING CHARACTERISTIC
Offset Error Full ±13 mV
Gain Error Full ±2.5 %FSR
TEMPERATURE DRIFT
Offset Error Full
Gain Error Full
INPUT REFERRED NOISE
VREF = 1.0 V 25°C 1.32 LSB rms
ANALOG INPUT
Input Span Full 1.75 V p-p
Input Capacitance2 Full 2.5 pF
Input Resistance3 Full 20 kΩ
Input Common-Mode Voltage Full 0.9 V
POWER SUPPLIES
Supply Voltage
AVDD Full 1.7 1.8 1.9 V
DRVDD Full 1.7 1.8 1.9 V
Supply Current
4
I
Full 271 275 mA
4
I
(Fixed-Frequency NCO, 95 MHz FIR Filter) Full 283 300 mA
DRVDD
4
I
(Tunable-Frequency NCO, 100 MHz FIR Filter) Full 375 mA
DRVDD
POWER CONSUMPTION
Sine Wave Input (Fixed-Frequency NCO, 95 MHz FIR Filter) Full 997 1035 mW
Sine Wave Input (Tunable-Frequency NCO, 100 MHz FIR Filter) Full 1163 mW
Standby Power5 Full 104 mW
Power-Down Power Full 10 mW
1
A −1.0 dBFS input level at the analog inputs corresponds to an output level of −2.5 dBFS when using the fixed-frequency NCO and 95 MHz FIR filter. When using the
tunable-frequency NCO and 100 MHz FIR filter, the output level is −1.3 dBFS. These respective output level reductions are due to FIR filter losses. See the FIR Filters
section for more details.
2
Input capacitance refers to the effective capacitance between one differential input pin and AGND.
3
Input resistance refers to the effective resistance between one differential input pin and its complement.
4
Measured with a 185 MHz, full-scale sine wave input on both channels and an NCO frequency of 62.5 MHz (fS/4).
5
Standby power is measured with a dc input and the CLK pin inactive (set to AVDD or AGND).
±5
±100
ppm/°C
ppm/°C
Rev. A | Page 4 of 40
Data Sheet AD6649
ADC AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input,1 1.75 V p-p full-scale input range,
DCS enabled, NCO enabled, FIR filter enabled, unless otherwise noted.
Table 2.
Parameter2 Temperature Min Typ Max Unit
SIGNAL-TO-NOISE RATIO (SNR)3
fIN = 30 MHz 25°C 74.5 dBFS
fIN = 90 MHz 25°C 74.2 dBFS
fIN = 140 MHz 25°C 73.9 dBFS
fIN = 185 MHz 25°C 73.4 dBFS
Full 70.9 dBFS
fIN = 220 MHz 25°C 72.9 dBFS
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
fIN = 30 MHz 25°C 73.4 dBFS
fIN = 90 MHz 25°C 73.0 dBFS
fIN = 140 MHz 25°C 72.3 dBFS
fIN = 185 MHz 25°C 71.7 dBFS
Full 68.7 dBFS
fIN = 220 MHz 25°C 71.0 dBFS
WORST SECOND OR THIRD HARMONIC
fIN = 30 MHz 25°C
fIN = 90 MHz 25°C
fIN = 140 MHz 25°C
fIN = 185 MHz 25°C
Full
−92
−88 dBc
−85
−85
−80 dBc
fIN = 220 MHz 25°C −89 dBc
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 30 MHz 25°C
92
fIN = 90 MHz 25°C 88
fIN = 140 MHz 25°C
fIN = 185 MHz 25°C
Full
fIN = 220 MHz 25°C
WORST OTHER HARMONIC OR SPUR
fIN = 30 MHz 25°C
fIN = 90 MHz 25°C
fIN = 140 MHz 25°C
fIN = 185 MHz 25°C
Full
fIN = 220 MHz 25°C
80
85
85
84
−95
−94 dBc
−93
−93
−80 dBc
−84
TWO-TONE SFDR
fIN = 184.12 MHz, 187.12 MHz (−7 dBFS) 25°C
CROSSTALK4 Full
ANALOG INPUT BANDWIDTH 25°C
1
A −1.0 dBFS input level at the analog inputs corresponds to an output level of −2.5 dBFS when using the fixed-frequency NCO and 95 MHz FIR filter. When using the
tunable-frequency NCO and 100 MHz FIR filter, the output level is −1.3 dBFS. These respective output level reductions are due to FIR filter losses. See the FIR Filters
section for more details.
2
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluat ion, for a complete set of definitions.
3
SNR specifications are for filtered 95 MHz bandwidth.
4
Crosstalk is measured at 100 MHz with −1 dBFS on one channel and with no input on the alternate channel.
88
95
1000
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dB
MHz
Rev. A | Page 5 of 40
AD6649 Data Sheet
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input,1 1.0 V internal reference,
DCS enabled, unless otherwise noted.
Table 3.
Parameter Temperature Min Typ Max Unit
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance CMOS/LVDS/LVPECL
Internal Common-Mode Bias Full 0.9 V
Differential Input Voltage Full 0.3 3.6 V p-p
Input Voltage Range Full AGND AVDD V
Input Common-Mode Range Full 0.9 1.4 V
High Level Input Current Full +10 +22 µA
Low Level Input Current Full −22 −10 µA
Input Capacitance Full
Input Resistance Full 8 10 12 kΩ
SYNC INPUT
Logic Compliance CMOS/LVD S
Internal Bias Full 0.9 V
Input Voltage Range Full AGND AVDD V
High Level Input Voltage Full 1.2 AVDD V
Low Level Input Voltage Full AGND 0.6 V
High Level Input Current Full −5 +5 µA
Low Level Input Current Full −5 +5 µA
Input Capacitance Full 1 pF
Input Resistance Full 12 16 20 kΩ
LOGIC INPUT (CSB)2
High Level Input Voltage Full 1.22 2.1 V
Low Level Input Voltage Full 0 0.6 V
High Level Input Current Full −5 +5 µA
Low Level Input Current Full −80 −45 µA
Input Resistance Full 26 kΩ
Input Capacitance Full 2 pF
LOGIC INPUT (SCLK)3
High Level Input Voltage Full 1.22 2.1 V
Low Level Input Voltage Full 0 0.6 V
High Level Input Current Full 45 70 µA
Low Level Input Current Full −5 +5 µA
Input Resistance Full 26 kΩ
Input Capacitance Full 2 pF
LOGIC INPUT/OUTPUT (SDIO)2
High Level Input Voltage Full 1.22 2.1 V
Low Level Input Voltage Full 0 0.6 V
High Level Input Current Full 45 70 µA
Low Level Input Current Full −5 +5 µA
Input Resistance Full 26 kΩ
Input Capacitance Full 5 pF
LOGIC INPUTS (OEB, PDWN)3
High Level Input Voltage Full 1.22 2.1 V
Low Level Input Voltage Full 0 0.6 V
High Level Input Current Full 45 70 µA
Low Level Input Current Full −5 +5 µA
4
pF
Rev. A | Page 6 of 40
Data Sheet AD6649
Parameter Temperature Min Typ Max Unit
Input Resistance Full 26 kΩ
Input Capacitance Full 5 pF
DIGITAL OUTPUTS
FDA and FDB
High Level Output Voltage
IOH = 50 µA Full 1.79 V
IOH = 0.5 mA Full 1.75 V
Low Level Output Voltage
IOL = 1.6 mA Full 0.2 V
IOL = 50 µA Full 0.05 V
LVDS Data and OR Outputs
Differential Output Voltage (VOD), ANSI Mode Full 250 350 450 mV
Output Offset Voltage (VOS),
ANSI Mode
Differential Output Voltage (VOD), Reduced Swing Mode Full 150 200 280 mV
Output Offset Voltage (VOS),
Reduced Swing Mode
1
A −1.0 dBFS input level at the analog inputs corresponds to an output level of −2.5 dBFS when using the fixed-frequency NCO and 95 MHz FIR filter. When using the
tunable-frequency NCO and 100 MHz FIR filter, the output level is −1.3 dBFS. These respective output level reductions are due to FIR filter losse s. See the FIR Filters
section for more details.
2
Pull-up.
3
Pull-down.
Full 1.15 1.22 1.35 V
Full 1.15 1.22 1.35 V
Rev. A | Page 7 of 40
AD6649 Data Sheet
SWITCHING SPECIFICATIONS
Table 4.
Parameter Temperature Min Ty p Max Unit
CLOCK INPUT PARAMETERS
Input Clock Rate Full 625 MHz
Conversion Rate1 Full 40 250 MSPS
CLK Period—Divide-by-1 Mode (t
CLK Pulse Width High (tCH)
Divide-by-1 Mode, DCS Enabled Full 1.8 2.0 2.2 ns
Divide-by-1 Mode, DCS Disabled Full 1.9 2.0 2.1 ns
Divide-by-3 Through Divide-by-8 Modes, DCS Enabled Full 0.8 ns
DATA OUTPUT PARAMETERS (DATA, OR)
Data Propagation Delay (tPD) Full 4.8 ns
DCO Propagation Delay (t
DCO-to-Data Skew (t
DCO
) Full 0.3 0.7 1.1 ns
SKEW
Pipeline Delay—Fixed-Frequency NCO, 95 MHz FIR Filter (Latency) Full 23 Cycles
Pipeline Delay—Tunable-Frequency NCO, 100 MHz FIR Filter (Latency) Full 43 Cycles
Aperture Delay (tA) Full 1.0 ns
Aperture Uncertainty (Jitter, tJ) Full 0.1 ps rms
Wake-Up Time (from Standby) Full 10 µs
Wake-Up Time (from Power-Down) Full 250 µs
OUT-OF-RANGE RECOVERY TIME Full 3 Cycles
1
Conversion rate is the clock rate after the divider.
) Full 4.0 ns
CLK
) Full 5.5 ns
Rev. A | Page 8 of 40
Data Sheet AD6649
me required for the SDIO pin to switch from an input to an output
Time required for the SDIO pin to switch from an output to an input
CLK+
CLK–
DCO+
DCO–
CHA3 CHB3
CHA4
CHB4 CHA5
D0+ TO D13+
D0– TO D13–
t
CH
t
CLK
t
DCO
t
PD
t
SKEW
CHA1 CHB1CHA0 CHB0
CHA2 CHB2
CHB5
CHA6
CHB6
09635-002
t
SSYNC
t
HSYNC
SYNC
CLK+
09635-016
TIMING SPECIFICATIONS
Table 5.
Parameter Conditions Min Typ Max Unit
SYNC TIMING REQUIREMENTS
t
SYNC to the rising edge of CLK setup time 0.3 ns
SSYNC
t
SYNC to the rising edge of CLK hold time 0.4 ns
HSYNC
SPI TIMING REQUIREMENTS
tDS Setup time between the data and the rising edge of SCLK 2 ns
tDH Hold time between the data and the rising edge of SCLK 2 ns
t
Period of the SCLK 40 ns
CLK
tS Setup time between CSB and SCLK 2 ns
tH Hold time between CSB and SCLK 2 ns
t
Minimum period that SCLK should be in a logic high state 10 ns
HIGH
t
Minimum period that SCLK should be in a logic low state 10 ns
LOW
t
Ti
EN_SDIO
t
DIS_SD IO
Timing Diagrams
relative to the SCLK falling edge
relative to the SCLK rising edge
10 ns
10 ns
Figure 2. Interleaved LVDS Mode Data Output Timing
Figure 3. SYNC Timing Inputs
Rev. A | Page 9 of 40
AD6649 Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter Rating
Electrical
AVDD to AGND −0.3 V to +2.0 V
DRVDD to AGND −0.3 V to +2.0 V
VIN+A/VIN+B, VIN−A/VIN−B to AGND −0.3 V to AVDD + 0.2 V
CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V
SYNC to AGND −0.3 V to AVDD + 0.2 V
VCM to AGND −0.3 V to AVDD + 0.2 V
CSB to AGND −0.3 V to DRVDD + 0.3 V
SCLK to AGND −0.3 V to DRVDD + 0.3 V
SDIO to AGND −0.3 V to DRVDD + 0.3 V
OEB to AGND −0.3 V to DRVDD + 0.3 V
PDWN to AGND −0.3 V to DRVDD + 0.3 V
D0−/D0+ through D13−/D13+
−0.3 V to DRVDD + 0.3 V
to AGND
FDA/FDB to AGND −0.3 V to DRVDD + 0.3 V
OR+/OR− to AGND −0.3 V to DRVDD + 0.3 V
DCO+/DCO− to AGND −0.3 V to DRVDD + 0.3 V
Environmental
Operating Temperature Range
−40°C to +85°C
(Ambient)
Maximum Junction Temperature
150°C
Under Bias
Storage Temperature Range
−65°C to +125°C
(Ambient)
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS
The exposed paddle must be soldered to the ground plane for
the LFCSP package. Soldering the exposed paddle to the
customer board increases the reliability of the solder joints,
maximizing the thermal capability of the package.
Table 7. Thermal Resistance
Airflow
Package
Type
64-Lead LFCSP
9 mm × 9 mm
(CP-64-4)
1
Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board.
2
Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
3
Per MIL-Std 883, Method 1012.1.
4
Per JEDEC JESD51-8 (still air).
Velocity
(m/sec) θ
1, 2
JA
1, 3
θ
JC
1, 4
θ
Unit
JB
0 26.8 1.14 10.4 °C/W
1.0 21.6 °C/W
2.0 20.2 °C/W
Typ i c a l θJA is specified for a 4-layer PCB with solid ground
plane. As shown in Table 7, airflow increases heat dissipation,
which reduces θ
. In addition, metal in direct contact with the
JA
package leads from metal traces, through holes, ground, and
power planes, reduces the θ
.
JA
ESD CAUTION
Rev. A | Page 10 of 40
Data Sheet AD6649
171819202122232425262728293031
32
D4–
D4+
DRVDD
D5–
D5+
D6–
D6+
DCO–
DCO+
D7–
D7+
DRVDD
D8–
D8+
D9–
D9+
646362616059585756555453525150
49
AVDD
AVDD
VIN+B
VIN–B
AVDD
AVDD
DNC
VCM
DNC
DNC
AVDD
AVDD
VIN–A
VIN+A
AVDD
AVDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK+
CLK–
SYNC
FDA
FDB
DNC
DNC
D0– (LSB)
D0+ (LSB)
DRVDD
D1–
D1+
D2–
D2+
D3–
D3+
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THEPACKAGE PROVI DE S THE ANALOG
GROUND FO R THE PART. THIS EXPOSED PADDLE MUST BE CONNECTED TO GRO UND FOR PROPE R OPERATION.
PDWN
OEB
CSB
SCLK
SDIO
OR+
OR–
D13+ (MSB)
D13– (MSB)
D12+
D21–
DRVDD
D11+
D11–
D10+
D10–
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AD6649
TOP VIEW
(Not to S cale)
09635-004
PIN 1
INDICATOR
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 4. LFCSP Interleaved Parallel LVDS Pin Configuration (Top View)
Table 8. Pin Function Descriptions (Interleaved Parallel LVDS Mode)
Pin No. Mnemonic Type Description
ADC Power Supplies
10, 19, 28, 37 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal).
49, 50, 53, 54, 59, 60, 63, 64 AVDD Supply Analog Power Supply (1.8 V Nominal).
6, 7, 55, 56, 58 DNC Do Not Connect. Do not connect to this pin.
0 AGND,
Exposed Paddle
Ground Analog Ground. The exposed thermal paddle on the bottom of the
package provides the analog ground for the part. This exposed
paddle must be connected to ground for proper operation.
ADC Analog
51 VIN+A Input Differential Analog Input Pin (+) for Channel A.
52 VIN−A Input Differential Analog Input Pin (−) for Channel A.
62 VIN+B Input Differential Analog Input Pin (+) for Channel B.
61 VIN−B Input Differential Analog Input Pin (−) for Channel B.
57 VCM Output Common-Mode Level Bias Output for Analog Inputs. This pin
1 CLK+ Input ADC Clock Input—True.
2 CLK− Input ADC Clock Input—Complement.
ADC Fast Detect Outputs
4 FDA Output Channel A Fast Detect Indicator (CMOS Levels).
5 FDB Output Channel B Fast Detect Indicator (CMOS Levels).
Digital Input
3 SYNC Input Digital Synchronization Pin. Slave mode only.
Digital Outputs
9 D0+ (LSB) Output Channel A/Channel B LVDS Output Data 0—True.
8 D0− (LSB) Output Channel A/Channel B LVDS Output Data 0—Complement.
12 D1+ Output Channel A/Channel B LVDS Output Data 1—True.
11 D1− Output Channel A/Channel B LVDS Output Data 1—Complement.
should be decoupled to ground using a 0.1 μF capacitor.
14 D2+ Output Channel A/Channel B LVDS Output Data 2—True.
13 D2− Output Channel A/Channel B LVDS Output Data 2—Complement.
16 D3+ Output Channel A/Channel B LVDS Output Data 3—True.
Rev. A | Page 11 of 40
AD6649 Data Sheet
Pin No. Mnemonic Type Description
15 D3− Output Channel A/Channel B LVDS Output Data 3—Complement.
18 D4+ Output Channel A/Channel B LVDS Output Data 4—True.
17 D4− Output Channel A/Channel B LVDS Output Data 4—Complement.
21 D5+ Output Channel A/Channel B LVDS Output Data 5—True.
20 D5− Output Channel A/Channel B LVDS Output Data 5—Complement.
23 D6+ Output Channel A/Channel B LVDS Output Data 6—True.
22 D6− Output Channel A/Channel B LVDS Output Data 6—Complement.
27 D7+ Output Channel A/Channel B LVDS Output Data 7—True.
26 D7− Output Channel A/Channel B LVDS Output Data 7—Complement.
30 D8+ Output Channel A/Channel B LVDS Output Data 8—True.
29 D8− Output Channel A/Channel B LVDS Output Data 8—Complement.
32 D9+ Output Channel A/Channel B LVDS Output Data 9—True.
31 D9− Output Channel A/Channel B LVDS Output Data 9—Complement.
34 D10+ Output Channel A/Channel B LVDS Output Data 10—True.
33 D10− Output Channel A/Channel B LVDS Output Data 10—Complement.
36 D11+ Output Channel A/Channel B LVDS Output Data 11—True.
35 D11− Output Channel A/Channel B LVDS Output Data 11—Complement.
39 D12+ Output Channel A/Channel B LVDS Output Data 12—True.
38 D12− Output Channel A/Channel B LVDS Output Data 12—Complement.
41 D13+ (MSB) Output Channel A/Channel B LVDS Output Data 13—True.
40 D13− (MSB) Output Channel A/Channel B LVDS Output Data 13—Complement.
43 OR+ Output Channel A/Channel B LVDS Overrange—True.
42 OR− Output Channel A/Channel B LVDS Overrange—Complement.
25 DCO+ Output Channel A/Channel B LVDS Data Clock Output—True.
24 DCO− Output Channel A/Channel B LVDS Data Clock Output—Complement.
SPI Control
45 SCLK Input SPI Serial Clock.
44 SDIO Input/Output SPI Serial Data Input/Output.
46 CSB Input SPI Chip Select (Active Low).
Output Enable Bar and Power-
Down
47 OEB Input/Output Output Enable Bar Input (Active Low).
48 PDWN
Input/Output Power-Down Input (Active High). The operation of this pin
depends on the SPI mode and can be configured as power-down
or standby (see Tab le 14).
Rev. A | Page 12 of 40
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