Analog Devices AD6645 b Datasheet

14-Bit, 80/105 MSPS

A/D Converter

AD6645

FEATURES
SNR = 75 dB, fIN 15 MHz up to 105 MSPS
SNR = 72 dB, f

200 MHz up to 105 MSPS

IN

SFDR = 89 dBc, fIN 70 MHz up to 105 MSPS
100 dB Multitone SFDR
IF Sampling to 200 MHz
Sampling Jitter 0.1 ps

1.5 W Power Dissipation
Differential Analog Inputs
Pin Compatible to AD6644
Twos Complement Digital Output Format

3.3 V CMOS Compatible
DataReady for Output Latching

APPLICATIONS
Multichannel, Multimode Receivers
Base Station Infrastructure
AMPS, IS-136, CDMA, GSM, WCDMA
Single Channel Digital Receivers
Antenna Array Processing
Communications Instrumentation
Radar, Infrared Imaging
Instrumentation

PRODUCT DESCRIPTION

The AD6645 is a high speed, high performance, monolithic 14-bit
analog-to-digital converter. All necessary functions, including
track-and-hold (T/H) and reference, are included on the chip to
provide a complete conversion solution. The AD6645 provides
CMOS compatible digital outputs. It is the fourth generation in a
wideband ADC family, preceded by the AD9042 (12-bit, 41 MSPS),

the AD6640 (12-bit, 65 MSPS, IF sampling), and the AD6644
(14-bit, 40 MSPS/65 MSPS).

Designed for multichannel, multimode receivers, the AD6645
is part of Analog Devices’ SoftCell

®

transceiver chipset. The
AD6645 maintains 100 dB multitone, spurious-free dynamic
range (SFDR) through the second Nyquist band. This break­through performance eases the burden placed on multimode
digital receivers (software radios) that are typically limited by the
ADC. Noise performance is exceptional; typical signal-to-noise
ratio is 74.5 dB through the first Nyquist band.

The AD6645 is built on Analog Devices’ high speed complemen­tary bipolar process (XFCB) and uses an innovative, multipass
circuit architecture. Units are available in a thermally enhanced
52-lead PowerQuad 4® (LQFP_PQ4) specified from –40°C to
+85°C at 80 MSPS and –10°C to +85°C at 105 MSPS.

PRODUCT HIGHLIGHTS

1. IF Sampling

The AD6645 maintains outstanding ac performance up to
input frequencies of 200 MHz, suitable for multicarrier 3G
wideband cellular IF sampling receivers.

2. Pin Compatibility

The ADC has the same footprint and pin layout as the
AD6644, 14-Bit 40 MSPS/65 MSPS ADC.

3. SFDR Performance and Oversampling

Multitone SFDR performance of –100 dBc can reduce the
requirements of high end RF components and allows the
use of receive signal processors such as the AD6620 or
AD6624/AD6624A.

FUNCTIONAL BLOCK DIAGRAM

DV

AV

CC

CC

AIN

AIN

VREF

ENCODE

ENCODE

A1 TH2 A2 TH4 ADC3TH5TH3TH1

2.4V

INTERNAL

TIMING

GND DMID OVR DRY D13

ADC1

DAC1 ADC2 DAC2

5

D12 D11 D10 D9D8D7D6D5D4D3D2D1D0

MSB

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

AD6645

6

5

DIGITAL ERROR CORRECTION LOGIC

LSB

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

AD6645–SPECIFICATIONS

DC SPECIFICATIONS

(AVCC = 5 V, DVCC = 3.3 V; T

MIN

and T

at rated speed grade, unless otherwise noted.)

MAX

Test AD6645ASQ-80 AD6645ASQ-105

Parameter Temp Level Min Typ Max Min Typ Max Unit

RESOLUTION 14 Bits

ACCURACY

No Missing Codes Full II Guaranteed Guaranteed
Offset Error Full II –10 +1.2 +10 –10 +1.2 +10 mV
Gain Error Full II –10 0 +10 –10 0 +10 % FS
Differential Nonlinearity (DNL) Full II –1.0 ± 0.25 +1.5 –1.0 ±0.5 +1.5 LSB
Integral Nonlinearity (INL) Full V ±0.5 ±1.5 LSB

TEMPERATURE DRIFT

Offset Error Full V 1.5 1.5 ppm/°C
Gain Error Full V 48 48 ppm/°C

POWER SUPPLY REJECTION (PSRR) 25°CV ±1.0 ±1.0 mV/V

REFERENCE OUT (VREF)

1

Full V 2.4 2.4 V

ANALOG INPUTS (AIN, AIN)

Differential Input Voltage Range Full V 2.2 2.2 V p-p
Differential Input Resistance Full V 1 1 kΩ
Differential Input Capacitance 25°CV 1.5 1.5 pF

POWER SUPPLY

Supply Voltages

AV
DV

CC

CC

Full II 4.75 5.0 5.25 4.75 5.0 5.25 V
Full II 3.0 3.3 3.6 3.0 3.3 3.6 V

Supply Current

(AVCC = 5.0 V) Full II 275 320 275 320 mA

I AV

CC

(DVCC = 3.3 V) Full II 32 45 32 45 mA

I DV

CC

CC

2

Full IV 250 250 ms

Rise Time

AV

POWER CONSUMPTION Full II 1.5 1.75 1.5 1.75 W

NOTES

1

VREF is provided for setting the common-mode offset of a differential amplifier such as the AD8138 when a dc-coupled analog input is required. VREF should be
buffered if used to drive additional circuit functions.

2

Specified for dc supplies with linear rise time characteristics.

Specifications subject to change without notice

DIGITAL SPECIFICATIONS

(AVCC = 5 V, DVCC = 3.3 V; T

MIN

and T

at rated speed grade, unless otherwise noted.)

MAX

Test AD6645ASQ-80 AD6645ASQ-105

Parameter (Conditions) Temp Level Min Typ Max Min Typ Max Unit

ENCODE INPUTS (ENC, ENC)

Differential Input Voltage

1

Full IV 0.4 0.4 V p-p

Differential Input Resistance 25°CV 10 10 kΩ
Differential Input Capacitance 25°CV 2.5 2.5 pF

2

LOGIC OUTPUTS (D13–D0, DRY, OVR

Logic Compatibility CMOS CMOS
Logic 1 Voltage (DV
Logic 0 Voltage (DV

= 3.3 V)

CC

= 3.3 V)

CC

3

3

)

Full II 2.85 DVCC–2 2.85 DVCC–2 V

Full II 0.2 0.5 0.2 0.5 V
Output Coding Twos Complement Twos Complement
DMID Full V DVCC/2 DVCC/2 V

NOTES

1

All ac specifications tested by driving ENCODE and ENCODE differentially.

2

The functionality of the Overrange bit is specified for a temperature range of 25°C to 85°C only.

3

Digital output logic levels: DVCC = 3.3 V, C

Specifications subject to change without notice.

= 10 pF. Capacitive loads >10 pF will degrade performance.

LOAD

–2–

REV. B

AD6645

AC SPECIFICATIONS

1

(AVCC = 5 V, DVCC = 3.3 V; ENCODE, ENCODE, T

MIN

and T

at rated speed grade, unless otherwise noted.)

MAX

Test AD6645ASQ-80 AD6645ASQ-105

Parameter (Conditions) Temp Level Min Typ Max Min Typ Max Unit

SNR

Analog Input 15.5 MHz 25°CV 75.0 75.0 dB
@ –1 dBFS 30.5 MHz Full II 72.5 74.5 dB

37.7 MHz 25°CI 72.5 74.5 dB

70.0 MHz Full II 72.0 73.5 72.0 73.5 dB

150.0 MHz 25°CV 73.0 73.0 dB

200.0 MHz 25°CV 72.0 72.0 dB

SINAD

Analog Input 15.5 MHz 25°CV 75.0 75.0 dB
@ –1 dBFS 30.5 MHz Full II 72.5 74.5 dB

37.7 MHz 25°CI 72.5 74.5 dB

70.0 MHz Full V 73.0 73.0 dB

150.0 MHz 25°CV 68.5 67.5 dB

200.0 MHz 25°CV 62.5 62.5 dB

WORST HARMONIC (Second or Third)

Analog Input 15.5 MHz 25°CV 93.0 93.1 dBc
@ –1 dBFS 30.5 MHz Full II 85.0 93.0 dBc

37.7 MHz 25°CI 85.0 93.0 dBc

70.0 MHz Full V 89.0 87.0 dBc

150.0 MHz 25°CV 70.0 70.0 dBc

200.0 MHz 25°CV 63.5 63.5 dBc

WORST HARMONIC (Fourth or Higher)

Analog Input 15.5 MHz 25°CV 96.0 96.0 dBc
@ –1 dBFS 30.5 MHz Full II 85.0 95.0 dBc

37.7 MHz 25°CI 86.0 95.0 dBc

70.0 MHz Full V 90.0 90.0 dBc

150.0 MHz 25°CV 90.0 90.0 dBc

200.0 MHz 25°CV 88.0 88.0 dBc

TWO TONE SFDR @30.5 MHz

55.0 MHz

70.0 MHz

TWO TONE IMD REJECTION

2, 3

2, 4

2, 5

3, 4

25°CV 100 98.0 dBFS
25°CV 100 98.0 dBFS
25°CV 98.0 dBFS

F1, F2 @ –7 dBFS 25°CV 90 90 dBc

ANALOG INPUT BANDWIDTH 25°CV 270 270 MHz

NOTES

1

All ac specifications tested by driving ENCODE and ENCODE differentially.

2

Analog input signal power swept from –10 dBFS to –100 dBFS.

3

F1 = 30.5 MHz, F2 = 31.5 MHz.

4

F1 = 55.25 MHz, F2 = 56.25 MHz.

5

F1 = 69.1 MHz, F2 = 71.1 MHz.

Specifications subject to change without notice.

SWITCHING SPECIFICATIONS

(AVCC = 5 V, DVCC = 3.3 V; ENCODE, ENCODE, T
otherwise noted.)

MIN

and T

at rated speed grade, unless

MAX

Test AD6645ASQ-80 AD6645ASQ-105

Parameter (Conditions) Temp Level Min Typ Max Min Typ Max Unit

Maximum Conversion Rate Full II 80 105 MSPS
Minimum Conversion Rate Full IV 30 MSPS
ENCODE Pulsewidth High (t
ENCODE Pulsewidth Low (t

*Several timing parameters are a function of t

Specifications subject to change without notice.

REV. B

)* Full IV 5.625 4.286 30 ns

ENCH

)* Full IV 5.625 4.286 ns

ENCL

ENCL

and t

ENCH

.

–3–

AD6645

SWITCHING SPECIFICATIONS

(continued)

(AVCC = 5 V, DVCC = 3.3 V; ENCODE, ENCODE, T
C

= 10 pF, unless otherwise noted.)

LOAD

MIN

and T

at rated speed grade,

MAX

Test AD6645ASQ-80 AD6645ASQ-105

Parameter (Conditions) Name Temp Level Min Typ Max Min Typ Max Unit

ENCODE Input Parameters

Encode Period

1

Encode Pulsewidth High
Encode Pulsewidth Low t

1

t

Full V 12.5 9.5 ns

2

ENC

t

Full V 6.25 4.75 ns

ENCH

Full V 6.25 4.75 ns

ENCL

ENCODE/DataReady

Encode Rising to DataReady Falling t
Encode Rising to DataReady Rising t

Full V 1.0 2.0 3.1 1.0 2.0 3.1 ns

DR

Full V t

E_DR

ENCH

+ t

DR

t

ENCH

+ t

DR

ns

(50% Duty Cycle) Full V 7.3 8.3 9.4 5.7 6.75 7.9 ns

ENCODE/DATA (D13:0), OVR

ENC to DATA Falling Low t
ENC to DATA Rising Low t
ENCODE to DATA Delay (Hold Time) t
ENCODE to DATA Delay (Setup Time) t

Full V 2.4 4.7 7.0 2.4 4.7 7.0 ns

E_FL

Full V 1.4 3.0 4.7 1.4 3.0 4.7 ns

E_RL

Full V 1.4 3.0 4.7 1.4 3.0 4.7 ns

H_E

Full V t

S_E

ENC

– t

E_FL(max)

t

ENC

– t

E_FL(typ)

t

ENC

– t

E_FL(min)

t

ENC

– t

E_FL(max)

t

ENC

– t

E_FL(typ)

t

ENC

– t

E_FL(min)

ns
ns
ns

(50% Duty Cycle) Full V 5.3 7.6 10.0 2.3 4.8 7.0 ns

DataReady (DRY3)/DATA, OVR

DataReady to DATA Delay (Hold Time) t

Full V Note 4 Note 4

H_DR

(50% Duty Cycle) 6.6 7.2 7.9 5.1 5.7 6.4 ns

DataReady to DATA Delay (Setup Time) t

Full V Note 4 Note 4

S_DR

(50% Duty Cycle) 2.1 3.6 5.1 0.6 2.1 3.5 ns

APERTURE DELAY t

APERTURE UNCERTAINTY (Jitter) t

NOTES

1

Several timing parameters are a function of t

2

ENCODE TO DATA Delay (Hold Time) is the absolute minimum propagation delay through the analog-to-digital converter, t

3

DRY is an inverted and delayed version of the encode clock. Any change in the duty cycle of the clock will correspondingly change the duty cycle of DRY.

4

DataReady to DATA Delay (t

H_DR

and t

ENC

) is calculated relative to rated speed grade and is dependent on t

S_DR

25°CV –500 –500 ps

A

25°CV 0.1 0.1 ps rms

J

and t

ENCH

.

= t

H_E

.

and duty cycle.

ENC

E_RL

Specifications subject to change without notice.

AIN

ENC, ENC

t

D[13:0], OVR

DRY

t

A

N

N+1

N+2

t

t

ENC

NN+1N+2N+3 N+4

E_RL

t

t

E_FL

ENCH

ENCL

t

E_DR

t

S_DR

t

DR

t

H_DR

t

N+3

S_E

Figure 1. Timing Diagram

N+4

t

H_E

NN–1N–2N–3

–4–

REV. B

ABSOLUTE MAXIMUM RATINGS*

Parameter Min Max Unit

ELECTRICAL

AVCC Voltage 0 7 V

Voltage 0 7 V

DV

CC

Analog Input Voltage 0 AV

CC

V
Analog Input Current 25 mA
Digital Input Voltage 0 AV

CC

V
Digital Output Current 4 mA

ENVIRONMENTAL

-80 Operating Temperature Range (Ambient) –40 +85 °C

-105 Operating Temperature Range (Ambient) –10 +85 °C
Maximum Junction Temperature 150 °C
Lead Temperature (Soldering, 10 sec) 300 °C
Storage Temperature Range (Ambient) –65 +150 °C

* Absolute maximum ratings are limiting values to be applied individually and beyond which the serviceability

of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute
maximum rating conditions for an extended period of time may affect device reliability.

AD6645

THERMAL CHARACTERISTICS

52-Lead Power Quad 4 LQFP_PQ4

= 23°C/W Soldered Slug, No Airflow

␪

JA

= 17°C/W Soldered Slug, 200 LFPM Airflow

␪

JA

␪

= 30°C/W Unsoldered Slug, No Airflow

JA

= 24°C/W Unsoldered Slug, 200 LFPM Airflow

␪

JA

= 2°C/W Bottom of Package (Heatslug)

␪

JC

Typical 4-Layer JEDEC Board Horizontal Orientation

ORDERING GUIDE

EXPLANATION OF TEST LEVELS
Test Level

I. 100% production tested.
II. 100% production tested at 25°C and guaranteed by design

and characterization at temperature extremes.
III. Sample tested only.
IV. Parameter is guaranteed by design and characterization

testing.
V. Parameter is a typical value only.

Model Temperature Range Package Description Package Option

AD6645ASQ-80 –40°C to +85°C (Ambient) 52-Lead PowerQuad 4 (LQFP_PQ4) SQ-52
AD6645ASQ-105 –10°C to +85°C (Ambient) 52-Lead PowerQuad 4 (LQFP_PQ4) SQ-52
AD6645-80/PCB Evaluation Board
AD6645-105/PCB Evaluation Board

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although the AD6645
features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to
high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid
performance degradation or loss of functionality.

REV. B

–5–

AD6645

PIN CONFIGURATION

GND

C1

D7

GND

D6

AV

DVCCGNDD5D4

CC

GNDC2GND

AV

CC

39

D3

38

D2

37

D1

36

D0 (LSB)

35

DMID

34

GND

33

DV

32

OVR

31

DNC

30

AV

29

GND

28

AV

27

GND

CC

CC

CC

DV

GND

VREF

GND

ENC

ENC

GND

AV

AV

GND

AIN

AIN

GND

DRY

D13 (MSB)

D12

D11

52 51 50 49 48 43 42 41 4047 4 6 45 44

1

CC

CC

CC

PIN 1
IDENTIFIER

2

3

4

5

6

7

8

9

10

11

12

13

14 15 16 17 18 19 20 21 22 23 24 25 26

CC

AV

D10D9D8

AD6645

TOP VIEW

(Not to Scale)

CC

CC

GND

GND

AV

AV

DNC = DO NOT CONNECT

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function

1, 33, 43 DV

CC

3.3 V Power Supply (Digital) Output Stage Only.

2, 4, 7, 10, 13, GND Ground.
15, 17, 19, 21,
23, 25, 27, 29,
34, 42

3 VREF 2.4 V Reference. Bypass to ground with a 0.1 µF microwave chip capacitor.

5 ENC Encode Input. Conversion initiated on rising edge.
6 ENC Complement of ENC, Differential Input.

8, 9, 14, 16, 18, AV

CC

5 V Analog Power Supply.

22, 26, 28, 30

11 AIN Analog Input.
12 AIN Complement of AIN, Differential Analog Input.
20 C1 Internal Voltage Reference. Bypass to ground with a 0.1 µF chip capacitor.
24 C2 Internal Voltage Reference. Bypass to ground with a 0.1 µF chip capacitor.

31 DNC Do not connect this pin.
32 OVR* Overrange Bit. A logic level high indicates analog input exceeds ±FS.

35 DMID Output Data Voltage Midpoint. Approximately equal to (DV

CC

)/2.

36 D0 (LSB) Digital Output Bit (Least Significant Bit); Twos Complement.

37–41, 44–50 D1–D5, D6–D12 Digital Output Bits in Twos Complement.

51 D13 (MSB) Digital Output Bit (Most Significant Bit); Twos Complement.

52 DRY DataReady Output.

*The functionality of the overrange bit is specified for a temperature range of 25°C to 85°C only.

–6–

REV. B