Analog Devices AD6645ASQ-80, AD6645-PCB Datasheet

14-Bit, 80 MSPS

FEATURES 80 MSPS Guaranteed Sample Rate SNR = 75 dB, f SNR = 72 dB, f SFDR = 89 dBc, f

15 MHz @ 80 MSPS

200 MHz @ 80 MSPS

70 MHz @ 80 MSPS

100 dB Multitone SFDR IF Sampling to 200 MHz Sampling Jitter 0.1 ps

1.5 W Power Dissipation Differential Analog Inputs Pin-Compatible to AD6644 Two’s Complement Digital Output Format

3.3 V CMOS-Compatible DataReady for Output Latching

APPLICATIONS Multichannel, Multimode Receivers Base Station Infrastructure AMPS, IS-136, CDMA, GSM, WCDMA Single Channel Digital Receivers Antenna Array Processing Communications Instrumentation Radar, Infrared Imaging Instrumentation

PRODUCT DESCRIPTION

The AD6645 is a high-speed, high-performance, monolithic 14-bit analog-to-digital converter. All necessary functions, including track-and-hold (T/H) and reference, are included on the chip to provide a complete conversion solution. The AD6645 provides CMOS-compatible digital outputs. It is the fourth

generation in a wideband ADC family, preceded by the AD9042 (12-bit, 41 MSPS), the AD6640 (12-bit, 65 MSPS, IF sampling), and the AD6644 (14-bit, 40 MSPS/65 MSPS).

Designed for multichannel, multimode receivers, the AD6645 is part of Analog Device’s SoftCell™ transceiver chipset. The AD6645 maintains 100 dB multitone, spurious-free dynamic range (SFDR) through the second Nyquist band. This breakthrough performance eases the burden placed on multimode digital receivers (software radios) that are typically limited by the ADC. Noise performance is exceptional; typical signal-tonoise ratio is 74.5 dB through the first Nyquist band.

The AD6645 is built on Analog Devices’ high-speed complementary bipolar process (XFCB) and uses an innovative, multipass circuit architecture. Units are available in a thermally enhanced 52lead PowerQuad 4

PRODUCT HIGHLIGHTS

1. IF Sampling

2. Pin Compatibility

3. SFDR Performance and Oversampling

A/D Converter

AD6645

(LQFP_ED) specified from –40∞C to +85∞C.

The AD6645 maintains outstanding ac performance up to input frequencies of 200 MHz. Suitable for multicarrier 3G wideband cellular IF sampling receivers.

The ADC has the same footprint and pin layout as the AD6644, 14-Bit 40 MSPS/65 MSPS ADC.

Multitone SFDR performance of –100 dBc can reduce the requirements of high-end RF components and allows the use of receive signal processors such as the AD6620 or AD6624/ AD6624A.

FUNCTIONAL BLOCK DIAGRAM

AIN

VREF

ENCODE

SoftCell is a trademark of Analog Devices, Inc. PowerQuad 4 is a registered trademark of Amkor Technology, Inc.

A1 TH2 A2 TH4 ADC3TH5TH3TH1

2.4V

INTERNAL

TIMING

GND DMID OVR DRY D13

ADC1

DAC1 ADC2 DAC2

D12 D11 D10 D9D8D7D6D5D4D3D2D1D0

MSB

REV. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

AD6645

DIGITAL ERROR CORRECTION LOGIC

LSB

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002

AD6645

–SPECIFICATIONS

DC SPECIFICATIONS

(AVCC = 5 V, DVCC = 3.3 V; T

= –40ⴗC, T

MIN

= +85ⴗC, unless otherwise noted.)

MAX

AD6645ASQ-80

Parameter Temp Test Level Min Typ Max Unit

RESOLUTION 14 Bits

ACCURACY

No Missing Codes Full II Guaranteed Offset Error Full II –10 +1.2 +10 mV Gain Error Full II –10 0 +10 % FS Differential Nonlinearity (DNL) Full II –1.0 ± 0.25 +1.5 LSB Integral Nonlinearity (INL) Full V ± 0.5 LSB

TEMPERATURE DRIFT

Offset Error Full V 1.5 ppm/∞C Gain Error Full V 48 ppm/∞C

POWER SUPPLY REJECTION (PSRR) 25∞CV ± 1.0 mV/V

REFERENCE OUT (VREF)

Full V 2.4 V

ANALOG INPUTS (AIN, AIN)

Differential Input Voltage Range Full V 2.2 V p-p Differential Input Resistance Full V 1 kW Differential Input Capacitance 25∞CV 1.5 pF

POWER SUPPLY

Supply Voltages

AV DV

Full II 4.75 5.0 5.25 V Full II 3.0 3.3 3.6 V

Supply Current

(AVCC = 5.0 V) Full II 275 320 mA

I AV

I DV

(DVCC = 3.3 V) Full II 32 45 mA

Full IV TBD ms

Rise Time

POWER CONSUMPTION Full II 1.5 1.75 W

NOTES

VREF is provided for setting the common-mode offset of a differential amplifier such as the AD8138 when a dc-coupled analog input is required. VREF should be

buffered if used to drive additional circuit functions.

Specified for dc supplies with linear rise-time characteristics. The use of dc supplies with linear rise-times of <45 ms is highly recommended.

Specifications subject to change without notice

DIGITAL SPECIFICATIONS

(AVCC = 5 V, DVCC = 3.3 V; T

= –40ⴗC, T

MIN

= +85ⴗC, unless otherwise noted.)

MAX

AD6645ASQ-80

Parameter (Conditions) Temp Test Level Min Typ Max Unit

ENCODE INPUTS (ENC, ENC)

Differential Input Voltage

Full IV 0.4 V p-p

Differential Input Resistance 25∞CV 10 kW Differential Input Capacitance 25∞CV 2.5 pF

LOGIC OUTPUTS (D13–D0, DRY, OVR

Logic Compatibility CMOS Logic “1” Voltage (DV Logic “0” Voltage (DV

= 3.3 V)

)

Full II 2.85 DV

– 0.2 V

Full II 0.2 0.5 V Output Coding Two’s Complement DMID Full V DVCC/2 V

NOTES

All ac specifications tested by driving ENCODE and ENCODE differentially.

The functionality of the Over-Range bit is specified for a temperature range of 25∞C to 85∞C only.

Digital output logic levels: DVCC = 3.3 V, C

Specifications subject to change without notice.

= 10 pF. Capacitive loads >10 pF will degrade performance.

LOAD

–2–

REV. 0

AD6645

AC SPECIFICATIONS

(AVCC = 5 V, DVCC = 3.3 V; ENCODE and ENCODE = 80 MSPS; T

otherwise noted.)

= –40ⴗC, T

MIN

= +85ⴗC, unless

MAX

AD6645ASQ-80

Parameter (Conditions) Temp Test Level Min Typ Max Unit

SNR

Analog Input 15.5 MHz 25∞CV 75.0 dB @ –1 dBFS 30.5 MHz 25∞CII 72.5 74.5 dB

70.0 MHz 25∞CII 72.0 73.5 dB

150.0 MHz 25∞CV 73.0 dB

200.0 MHz 25∞CV 72.0 dB

SINAD

Analog Input 15.5 MHz 25∞CV 75.0 dB @ –1 dBFS 30.5 MHz 25∞CII 72.5 74.5 dB

70.0 MHz 25∞CV 73.0 dB

150.0 MHz 25∞CV 68.5 dB

200.0 MHz 25∞CV 62.5 dB

WORST HARMONIC (2

or 3rd) Analog Input 15.5 MHz 25∞CV 93.0 dBc @ –1 dBFS 30.5 MHz 25∞CII 85.0 93.0 dBc

70.0 MHz 25∞CV 89.0 dBc

150.0 MHz 25∞CV 70.0 dBc

200.0 MHz 25∞CV 63.5 dBc

or H

IGHER

WORST HARMONIC (4

) Analog Input 15.5 MHz 25∞CV 96.0 dBc @ –1 dBFS 30.5 MHz 25∞CII 85.0 95.0 dBc

70.0 MHz 25∞CV 90.0 dBc

150.0 MHz 25∞CV 90.0 dBc

200.0 MHz 25∞CV 88.0 dBc

TWO TONE SFDR @ 30.5 MHz

55.0 MHz

TWO TONE IMD REJECTION

3, 4

2, 3

2, 4

25∞CV 100 dBFS 25∞CV 100 dBFS

F1, F2 @ –7 dBFS 25∞CV 90 dBc

ANALOG INPUT BANDWIDTH 25∞CV 270 MHz

NOTES

All ac specifications tested by driving ENCODE and ENCODE differentially.

Analog input signal power swept from –10 dBFS to –100 dBFS.

F1 = 30.5 MHz, F2 = 31.5 MHz.

F1 = 55.25 MHz, F2 = 56.25 MHz.

Specifications subject to change without notice.

SWITCHING SPECIFICATIONS

(AVCC = 5 V, DVCC = 3.3 V; ENCODE and ENCODE = 80 MSPS; T otherwise noted.)

= –40ⴗC, T

MIN

= +85ⴗC, unless

MAX

AD6645ASQ-80

Parameter (Conditions) Temp Test Level Min Typ Max Unit

Maximum Conversion Rate Full II 80 MSPS Minimum Conversion Rate Full IV 30 MSPS ENCODE Pulsewidth High (t ENCODE Pulsewidth Low (t

*Several timing parameters are a function of t

Specifications subject to change without notice.

REV. 0

)* Full IV 5.625 ns

ENCH

)* Full IV 5.625 ns

ENCL

and t

ENCH

–3–

AD6645

SWITCHING SPECIFICATIONS

(continued)

(AVCC = 5 V, DVCC = 3.3 V; ENCODE and ENCODE = 80 MSPS; T T

= +85ⴗC, C

MAX

= 10 pF, unless otherwise noted.)

LOAD

= –40ⴗC,

MIN

AD6645ASQ-80

Parameter (Conditions) Name Temp Test Level Min Typ Max Unit

ENCODE Input Parameters

Encode Period1 @ 80 MSPS t Encode Pulsewidth High Encode Pulsewidth Low @ 80 MSPS t

@ 80 MSPS t

ENC

ENCH

ENCL

Full V 12.5 ns Full V 6.25 ns Full V 6.25 ns

ENCODE/DataReady

Encode Rising to DataReady Falling t Encode Rising to DataReady Rising t

E_DR

Full V 1.0 2.0 3.1 ns Full V t

ENCH

+ t

@ 80 MSPS (50% Duty Cycle) Full V 7.3 8.3 9.4 ns

ENCODE/DATA (D13:0), OVR

ENC to DATA Falling Low t ENC to DATA Rising Low t ENCODE to DATA Delay (Hold Time) ENCODE to DATA Delay (Setup Time)

E_FL

E_RL

H_E

S_E

Full V 2.4 4.7 7.0 ns Full V 1.4 3.0 4.7 ns Full V 1.4 3.0 4.7 ns Full V t

ENC

– t

E_FL

Encode = 80 MSPS (50% Duty Cycle) Full V 5.3 7.6 10.0 ns

DataReady (DRY

DataReady to DATA Delay (Hold Time)

Encode = 80 MSPS (50% Duty Cycle) 6.6 7.2 7.9

DataReady to DATA Delay (Setup Time)

)/DATA, OVR

H_DR

S_DR

Full V Note 6 ns

Encode = 80 MSPS (50% Duty Cycle) 2.1 3.6 5.1

APERTURE DELAY t

APERTURE UNCERTAINTY (Jitter) t

NOTES

Several timing parameters are a function of t

To compensate for a change in duty cycle for t

Newt Newt

ENCODE TO DATA Delay (Hold Time) is the absolute minimum propagation delay through the Analog-to-Digital Converter, t

ENCODE TO DATA Delay (Setup Time) is calculated relative to 80 MSPS (50% duty cycle). To calculate t

Newt

DRY is an inverted and delayed version of the encode clock. Any change in the duty cycle of the clock will correspondingly change the duty cycle of DRY.

DataReady to DATA Delay (t t

Newt

= (t

S_DR

ENC(NEW)

= t

ENC(NEW)

H_DR

– % Change(t

– t

+ t

ENC

/2 – t

ENCH

/2 – t

ENCH

H_DR

S_DR

= t

S_E

for a given encode, use the following equations:

S_DR

H_DR

= t

S_DR

))

ENCH

))

ENCH

(i.e., for 40 MSPS: Newt

S_E

and t

H_DR

+ t

H_DR

+ t

S_DR

and t

ENC

and t

H_DR

) is calculated relative to 80 MSPS (50% duty cycle) and is dependent on t

S_DR

(i.e., for 40 MSPS: Newt

ENCH

use the following equation:

S_DR

S_E(TYP)

H_DR(TYP)

S_DR(TYP)

Specifications subject to change without notice.

25∞CV –500 ps

25∞CV 0.1 ps rms

= t

for a given encode, use the following equation:

= 25 ¥ 10–9 – 15.38 ¥ 10–9 + 9.8 ¥ 10–9 = 19.4 ¥ 10 –9).

S_E

= 12.5 ¥ 10–9 – 6.25 ¥ 10–9 + 7.2 ¥ 10–9 = 13.45 ¥ 10

= 12.5 ¥ 10–9 – 6.25 ¥ 10–9 + 3.6 ¥ 10–9 = 9.85 ¥ 10

E_RL

and duty cycle. To calculate t

ENC

–9

H_E

H_DR

and

AIN

ENC, ENC

D[13:0], OVR

DRY

N+1

N+2

ENC

NN+1N+2N+3 N+4

E_RL

E_FL

ENCH

ENCL

E_DR

S_DR

H_DR

N+3

S_E

Figure 1. Timing Diagram

–4–

N+4

H_E

NN–1N–2N–3

REV. 0

ABSOLUTE MAXIMUM RATINGS*

WARNING!

ESD SENSITIVE DEVICE

Parameter Min Max Unit

ELECTRICAL

Voltage 0 7 V

Analog Input Voltage 0 AV

V Analog Input Current 25 mA Digital Input Voltage 0 AV

V Digital Output Current 4 mA

ENVIRONMENTAL

Operating Temperature Range (Ambient) –40 +85 ∞C Maximum Junction Temperature 150 ∞C Lead Temperature (Soldering, 10 sec) 300 ∞C Storage Temperature Range (Ambient) –65 +150 ∞C

*Absolute maximum ratings are limiting values to be applied individually and beyond which the serviceability

of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability.

AD6645

THERMAL CHARACTERISTICS

52-Lead PowerQuad 4 . . . . . . . . . . . . . . . . . . . . . . LQFP_ED



= 23∞C/W . . . . . . . . . . . . . . . Soldered Slug, No Airflow



= 17∞C/W . . . . . . . . Soldered Slug, 200 LFPM Airflow

= 30∞C/W . . . . . . . . . . . . . Unsoldered Slug, No Airflow



= 24∞C/W . . . . . . Unsoldered Slug, 200 LFPM Airflow



= 2∞C/W . . . . . . . . . . . . . Bottom of Package (Heatslug)

Typical Four-Layer JEDEC Board Horizontal Orientation

ORDERING GUIDE

EXPLANATION OF TEST LEVELS Test Level

I. 100% production tested. II. 100% production tested at 25∞C and guaranteed by design

and characterization at temperature extremes. III. Sample tested only. IV. Parameter is guaranteed by design and characterization

testing. V. Parameter is a typical value only.

Model Temperature Range Package Description Package Option

AD6645ASQ-80 –40∞C to +85∞C (Ambient) 52-Lead PowerQuad 4 (LQFP_ED) SQ-52 AD6645/PCB 25∞C Evaluation Board

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD6645 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

REV. 0

–5–

AD6645

PIN CONFIGURATION

GND

D0 (LSB)

DMID

GND

OVR

DNC

GND

GNDC2GND

GND

VREF

GND

ENC

GND

AIN

GND

DRY

D13 (MSB)

D12

D11

52 51 50 49 48 43 42 41 4047 4 6 4 5 44

PIN 1 IDENTIFIER

14 15 16 17 18 19 20 21 22 23 24 25 26

D10D9D8D7DVCCGNDD5D4

AD6645

TOP VIEW

(Not to Scale)

GND

DNC = DO NOT CONNECT

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function

1, 33, 43 DV

3.3 V Power Supply (Digital) Output Stage Only

2, 4, 7, 10, 13, GND Ground 15, 17, 19, 21, 23, 25, 27, 29, 34, 42

3 VREF 2.4 V Reference. Bypass to ground with a 0.1 mF microwave chip capacitor.

5 ENC Encode Input. Conversion initiated on rising edge. 6 ENC Complement of ENC, Differential Input

8, 9, 14, 16, 18, AV

5 V Analog Power Supply

22, 26, 28, 30

11 AIN Analog Input 12 AIN Complement of AIN, Differential Analog Input 20 C1 Internal Voltage Reference. Bypass to ground with a 0.1 mF chip capacitor. 24 C2 Internal Voltage Reference. Bypass to ground with a 0.1 mF chip capacitor.

31 DNC Do not connect this pin. 32 OVR* Over-Range Bit. A logic-level high indicates analog input exceeds ± FS.

35 DMID Output Data Voltage Midpoint. Approximately equal to (DV

)/2.

36 D0 (LSB) Digital Output Bit (Least Significant Bit); Two’s Complement

37–41, 44–50 D1–D5, D6–D12 Digital Output Bits in Two’s Complement

51 D13 (MSB) Digital Output Bit (Most Significant Bit); Two’s Complement

52 DRY DataReady Output

*The functionality of the Over-Range bit is specified for a temperature range of 25∞C to 85∞C only.

–6–

REV. 0

+ 14 hidden pages

Analog Devices AD6645ASQ-80, AD6645-PCB Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

PRODUCT DESCRIPTION

PRODUCT HIGHLIGHTS

FUNCTIONAL BLOCK DIAGRAM

ABSOLUTE MAXIMUM RATINGS*

ORDERING GUIDE

CAUTION