ANALOG DEVICES AD6643 Service Manual

Dual IF Receiver

AD6643

Rev. B

Trademarks and registered trademarks are the prop erty of their respective owner s.

VIN+A

D0±

D10±

V

IN–A

PIPELINE

ADC

NOISE SHAP ING

REQUANTIZER

VIN+B VIN–B

NOTES

1. THE D0± TO D10± PINS REPRE S E NT BOTH THE CHANNE L A AND CHANNEL B LVDS OUTPUT DATA.

PIPELINE

ADC

SERIAL PORT

REFERENCE

14 11

NOISE SHAP ING

REQUANTIZER

AD6643

DATA MULTIPLEXER

AND LVDS DRIVE RS

14

11

CLOCK

DIVIDER

VCM

DCO±

OEB

SCLK SDIO CSB CLK+

AVDD

AGND

DRVDD

CLK–

SYNC

PDWN

09638-001

Data Sheet

FEATURES

11-bit, 250 MSPS output data rate per channel Performance with NSR enabled

SNR: 74.5 dBFS in a 55 MHz band to 90 MHz at 250 MSPS SNR: 72.0 dBFS in a 82 MHz band to 90 MHz at 250 MSPS

Performance with NSR disabled

SNR: 66.2 dBFS up to 90 MHz at 250 MSPS SFDR: 85 dBc up to 185 MHz at 250 MSPS

Total power consumption: 706 mW at 200 MSPS

1.8 V supply voltages LVDS (ANSI-644 levels) outputs Integer 1-to-8 input clock divider (625 MHz maximum input) Internal ADC voltage reference Flexible analog input range

1.4 V p-p to 2.0 V p-p (1.75 V p -p nominal) Differential analog inputs with 400 MHz bandwidth 95 dB channel isolation/crosstalk Serial port control Energy saving power-down modes User-configurable, built-in self test (BIST) capability

APPLICATIONS

Communications Diversity radio and smart antenna (MIMO) systems Multimode digital receivers (3G)

WCDMA, LTE, CDMA2000

WiMAX, TD-SCDMA I/Q demodulation systems General-purpose software radios

GENERAL DESCRIPTION

The AD6643 is an 11-bit, 200 MSPS/250 MSPS, dual-channel intermediate frequency (IF) receiver specifically designed to support multi-antenna systems in telecommunication applications where high dynamic range performance, low power, and small size are desired.

The device consists of two high performance analog-to-digital converters (ADCs) and noise shaping requantizer (NSR) digital blocks. Each ADC consists of a multistage, differential pipelined architecture with integrated output error correction logic, and each ADC features a wide bandwidth switched capacitor sampling network within the first stage of the differential pipeline. An integrated voltage reference eases design considerations. A duty cycle stabilizer (DCS) compensates for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

Each ADC output is connected internally to an NSR block. The integrated NSR circuitry allows for improved SNR performance in a smaller frequency band within the Nyquist bandwidth. The device supports two different output modes selectable via the SPI. With the NSR feature enabled, the outputs of the ADCs are processed such that the AD6643 supports enhanced SNR performance within a limited portion of the Nyquist bandwidth while maintaining an 11-bit output resolution.

The NSR block can be programmed to provide a bandwidth of either 22% or 33% of the sample clock. For example, with a sample clock rate of 185 MSPS, the AD6643 can achieve up to

75.5 dBFS SNR for a 40 MHz bandwidth in the 22% mode and up to 73.7 dBFS SNR for a 60 MHz bandwidth in the 33% mode.

(continued on Page 3)

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com

AD6643 Data Sheet

REVISION HISTORY

6/12—Rev. A to Rev. B

Changes to Features .......................................................................... 1

Changes to Full Power Bandwidth Parameter, Deleted Noise

Bandwidth Parameter, Changes to Endnote 3; Tabl e 2 ............... 6

Added Figure 20 to Figure 33; Renumbered Sequentially ........ 17

Changes to Figure 52 ...................................................................... 24

Updated Outline Dimensions ....................................................... 35

9/11—Rev. 0 to Rev. A

Added 250 MSPS Speed Grade Throughout................................. 1

Changes to Table 1 ............................................................................ 4

Changes to Table 2 ............................................................................ 5

Changes to Table 4 ............................................................................ 8

Changes to Figure 2 .......................................................................... 9

Change to OEB Pin Description, Table 8 .................................... 12

Changes Figure 5 and Table 9 ....................................................... 13

Changes to Typical Performance Characteristics Conditions

Summary .......................................................................................... 15

Rev. B | Page 2 of 40

Added AD6643-200 Throughout ................................................. 15

Changes to Figure 24 and Figure 25 ............................................ 18

Changes to Theory of Operation Section.................................... 19

Changes to Timing Section ........................................................... 23

Added ADC Overrange (OR) Section ......................................... 23

Changed Frequency (Hz) to Frequency (MHz) in Figure 39,

Figure 40, and Figure 41 ................................................................ 24

Changed Frequency (Hz) to Frequency (MHz) in Figure 42,

Figure 43, and Figure 44 ................................................................ 25

Changes to Channel/Chip Synchronization Section ................. 26

Changed 0x59 to 0x3E Throughout ............................................. 29

Changes to 0x02, Bits[5:4] and 0x16, Bit 5 in Table 14 ............. 30

Deleted 0x59, Table 14 ................................................................... 32

Deleted SYNC Pin Control (Register 0x59) Section .................. 33

Changes to Ordering Guide .......................................................... 35

4/11—R

evision 0: Initial Version

Data Sheet AD6643

When the NSR block is disabled, the ADC data is provided directly to the output at a resolution of 11 bits. The AD6643 can achieve up to 66.5 dBFS SNR for the entire Nyquist bandwidth when operated in this mode. This allows the AD6643 to be used in telecommunication applications such as a digital predistortion observation path where wider bandwidths are required.

After digital signal processing, multiplexed output data is routed into two 11-bit output ports such that the maximum data rate is 400 Mbps (DDR). These outputs are LVDS and support ANSI-644 levels.

The AD6643 receiver digitizes a wide spectrum of IF frequencies. Each receiver is designed for simultaneous reception of a separate antenna. This IF sampling architecture greatly reduces component cost and complexity compared with traditional analog techniques or less integrated digital methods.

Flexible power-down options allow significant power savings. Programming for device setup and control is accomplished using a 3-wire SPI-compatible serial interface with numerous modes to support board level system testing.

The AD6643 is available in a Pb-free, RoHS-compliant, 64-lead, 9 mm × 9 mm lead frame chip scale package (LFCSP_VQ) and is specified over the industrial temperature range of −40°C to +85°C. This product is protected by a U.S. patent.

PRODUCT HIGHLIGHTS

1. Two ADCs are contained in a small, space-saving,

9 mm × 9 mm × 0.85 mm, 64-lead LFCSP package.

2. Pin selectable noise shaping requantizer (NSR) function

that allows for improved SNR within a reduced bandwidth of up to 60 MHz at 185 MSPS.

3. LVDS digital output interface configured for low cost

FPGA families.

4. Operation from a single 1.8 V supply.

5. Standard serial port interface (SPI) that supports various

product features and functions, such as data formatting (offset binary or twos complement), NSR, power-down, test modes, and voltage reference mode.

6. On-chip integer 1-to-8 input clock divider and multichip

sync function to support a wide range of clocking schemes and multichannel subsystems.

Rev. B | Page 3 of 40

AD6643 Data Sheet

RESOLUTION

Full

11

Bits

I

(NSR Enabled—33% Mode)

Full 186

218 mA

SPECIFICATIONS

ADC DC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, default SPI, unless otherwise noted.

Table 1.

AD6643-200 AD6643-250 Parameter Temperature Min Typ Max Min Typ Max Unit

ACCURACY

No Missing Codes Full Guaranteed Guaranteed Offset Error Full ±10 ±10 mV Gain Error Full +2/−6 −5/+3 % FSR Differential Nonlinearity (DNL)1 Full ±0.1 ±0.25 ±0.1 ±0.4 LSB Integral Nonlinearity (INL)1 Full ±0.2 ±0.25 ±0.2 ±0.4 LSB

MATCHING CHARACTERISTIC

Offset Error 25°C ±13 ±13 mV Gain Error 25°C −2/+3.5 −2.5/+3.5 % FSR

TEMPERATURE DRIFT

Offset Error Full ±15 ±15 ppm/°C Gain Error Full ±87 ±87 ppm/°C

INPUT REFERRED NOISE

VREF = 1.0 V 25°C 0.614 0.614 LSB rms

ANALOG INPUT

Input Span Full 1.75 1.75 V p-p Input Capacitance2 Full 2.5 2.5 pF Input Resistance3 Full 20 20 kΩ Input Common-Mode Voltage Full 0.9 0.9 V

POWER SUPPLIES

Supply Voltage

AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V

Supply Current

1

I

Full 238 260 256 275 mA

AVDD

1

I

(NSR Disabled) Full 154 215 180 215 mA

DRVDD

1

I

(NSR Enabled—22% Mode) Full 172 206 mA

DRVDD

1

DRVDD

POWER CONSUMPTION

Sine Wave Input1 (DRVDD = 1.8 V,

NSR Disabled)

Sine Wave Input1 (DRVDD = 1.8 V,

NSR Enabled—22% Mode)

Sine Wave Input1 (DRVDD = 1.8 V,

NSR Enabled—33% Mode) Standby Power4 Full 90 90 mW Power-Down Power Full 10 10 mW

1

Measured using a 10 MHz, 0 dBFS sine wave, and 100 Ω termination on each LVDS output pair.

2

Input capacitance refers to the effective capacitance between one differential input pin and its complement.

3

Input resistance refers to the effective resistance between one differential input pin and its complement.

4

Standby power is measured using a dc input and the CLK± pins inactive (set to AVDD or AGND).

Full 706 855 785 873 mW

Full 738 832 mW

Full 765 853 mW

Rev. B | Page 4 of 40

Data Sheet AD6643

fIN = 220 MHz

25°C 66.0

65.6 dBFS

fIN = 220 MHz

25°C 72.1

70.9 dBFS

fIN = 90 MHz

25°C −91

−88 dBc

fIN = 220 MHz

25°C −84

−85 dBc

ADC AC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, default SPI,

unless otherwise noted.

Table 2.

AD6643-200 AD6643-250

Parameter1 Temperature Min Typ Max Min Typ Max Unit

SIGNAL-TO-NOISE-RATIO (SNR)

NSR Disabled

fIN = 30 MHz 25°C 66.6 66.4 dBFS fIN = 90 MHz 25°C 66.5 66.2 dBFS Full 66.2 dBFS fIN = 140 MHz 25°C 66.4 66.1 dBFS fIN = 185 MHz 25°C 66.2 65.9 dBFS Full 65.3 dBFS

NSR Enabled

22% BW Mode

fIN = 30 MHz 25°C 76.1 74.8 dBFS fIN = 90 MHz 25°C 76.1 74.5 dBFS Full 74.5 dBFS fIN = 140 MHz 25°C 75.5 74.2 dBFS fIN = 185 MHz 25°C 74.7 73.7 dBFS Full 72.6 dBFS fIN = 220 MHz 25°C 74.2 73.4 dBFS

33% BW Mode

fIN = 30 MHz 25°C 76.1 72.3 dBFS fIN = 90 MHz 25°C 73.6 72.0 dBFS Full 72.0 dBFS fIN = 140 MHz 25°C 73.1 71.7 dBFS fIN = 185 MHz 25°C 72.6 71.2 dBFS Full 70.1 dBFS

SIGNAL-TO-NOISE-AND-DISTORTION (SINAD)

fIN = 30 MHz 25°C fIN = 90 MHz 25°C Full 65.1 fIN = 140 MHz 25°C fIN = 185 MHz 25°C Full fIN = 220 MHz 25°C

WORST SECOND OR THIRD HARMONIC

fIN = 30 MHz 25°C

Full fIN = 140 MHz 25°C fIN = 185 MHz 25°C Full

Rev. B | Page 5 of 40

65.6

65.5

65.3

65.1

64.9

−92

−88

65.4

65.2

65.1

64.9

64.3

64.6

−90

−80

−86

−85

−80 dBc

dBFS dBFS dBFS dBFS dBFS dBFS dBFS

dBc

dBc dBc dBc

AD6643 Data Sheet

Full

−80

dBc

FULL POWER BANDWIDTH3

25°C 1000

1000

MHz

Logic Compliance

Internal Common-Mode Bias

Differential Input Voltage

Full

0.9 1.4

V

Input Current Level

4

AD6643-200 AD6643-250 Parameter1 Temperature Min Typ Max Min Ty p Max Unit

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

fIN = 30 MHz 25°C fIN = 90 MHz 25°C Full 80 fIN = 140 MHz 25°C fIN = 185 MHz 25°C Full fIN = 220 MHz 25°C

WORST OTHER HARMONIC OR SPUR

fIN = 30 MHz 25°C fIN = 90 MHz 25°C

92 91

88 88

84

−94

79

90 88

86 85

85

−94

−93

dBc dBc dBc dBc dBc dBc dBc

dBc dBc

fIN = 140 MHz 25°C fIN = 185 MHz 25°C Full fIN = 220 MHz 25°C

−95

−94

−93

−92

−80 dBc

−88

TWO TONE SFDR

fIN = 184.12 MHz, 187.12 MHz (−7 dBFS) 25°C

CROSSTALK2 Full

1

For a complete set of definitions, see the AN-835 Application Note, Understanding High Spee d ADC Testing and Evaluation.

2

Crosstalk is measured at 100 MHz with −1 dBFS on one channel and with no input on the alternate channel.

3

Full power bandwidth is the bandwidth for the ADC inputs at which the spectral power of the fundamental frequency is reduced by 3 dB.

88 95

DIGITAL SPECIFICATIONS—AD6643-200/AD6643-250

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, DCS enabled, default SPI, unless otherwise noted.

Table 3.

Parameter Temperature Min Typ Max Unit

DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)

CMOS/LVDS/LVPECL Full 0.9 V

Full 0.3 3.6 V p-p Input Voltage Range Input Common-Mode Range

Full AGND AVDD V

dBc dBc

dBc

dBc dB

High Full 10 22 µA

Low Full −22 −10 µA Input Capacitance Full Input Resistance Full 8 10 12 kΩ

SYNC INPUT

Logic Compliance CMOS/LVDS Internal Bias Full 0.9 V Input Voltage Range Full AGND AVD D V Input Voltage Level

High Full 1.2 AVDD V

Low Full AGND 0.6 V

pF

Rev. B | Page 6 of 40

Data Sheet AD6643

Input Resistance

Full

12

16

20

kΩ

Input Capacitance

Full 2 pF

Input Voltage Level

Low

Full 0

0.6

V

Parameter Temperature Min Typ Max Unit

Input Current Level

High Full −5 +5 µA Low Full −100 +100 µA

Input Capacitance Full 1 pF

LOGIC INPUT (CSB)1

Input Voltage Level

High Full 1.22 2.1 V Low Full 0 0.6 V

Input Current Level

High Full −5 +5 µA Low Full −80 −45 µA

Input Resistance Full 26 kΩ

LOGIC INPUT (SCLK)2

High Full 1.22 2.1 V Low Full 0 0.6 V

Input Current Level

High Full 45 70 µA

Low Full −5 +5 µA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF

LOGIC INPUTS (SDIO)1

Input Voltage Level

High Full 1.22 2.1 V

Low Full 0 0.6 V Input Current Level

High Full 45 70 µA

Low Full −5 +5 µA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF

LOGIC INPUTS (OEB, PDWN)2

Input Voltage Level

High Full 1.22 2.1 V

DIGITAL OUTPUTS

1

Pull up.

2

Pull down.

Input Current Level

High Full 45 70 µA

Low Full −5 +5 µA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF

LVDS Data and OR Outputs

Differential Output Voltage (VOD)

ANSI Mode Full 250 350 450 mV Reduced Swing Mode Full 150 200 280 mV

Output Offset Voltage (VOS)

ANSI Mode Full 1.15 1.25 1.35 V Reduced Swing Mode Full 1.15 1.25 1.35 V

Rev. B | Page 7 of 40

AD6643 Data Sheet

CLK Pulse Width High2

tCH

DCO Propagation Delay2

t

Full 5.5

5.5 ns

SYNC TIMING REQUIREMENTS

See Figure 3 for timing details

SWITCHING SPECIFICATIONS

Table 4.

AD6643-200 AD6643-250 Parameter Symbol Te mperature Min Typ Max Min Typ Max Unit

CLOCK INPUT PARAMETERS

Input Clock Rate Full 625 625 MHz Conversion Rate1 Full 40 200 40 250 MSPS CLK Period—Divide-by-1 Mode2 t

Divide-by-1 Mode, DCS Enabled Full 2.25 2.5 2.75 1.8 2.0 2.2 ns Divide-by-1 Mode, DCS Disabled Full 2.375 2.5 2.625 1.9 2.0 2.1 ns Divide-by-2 Through Divide-by-8 Modes, DCS

Enabled

DATA OUTPUT PARAMETERS (DATA, OR) 1.0

LVDS Mode 0.1

Data Propagation Delay2 tPD Full 4.8 4.8 ns

DCO to Data Skew2 t

Pipeline Delay (Latency) Full 10 10 Cycles3

NSR Enabled Full 13 13 Cycles3 Aperture Delay4 tA Full 1.0 1.0 ns Aperture Uncertainty (Jitter)4 tJ Full 0.1 0.1 ps rms Wake-Up Time (from Standby) Full 10 10 μs Wake-Up Time (from Power-Down) Full 250 250 μs

OUT-OF-RANGE RECOVERY TIME Full 3 3 Cycles

1

Conversion rate is the clock rate after the divider.

2

See Figure 2 for timing diagram.

3

Cycles refers to ADC input sample rate cycles.

4

Not shown in timing diagrams.

Full 4.0 4 ns

CLK

Full 0.8 0.8

DCO

Full 0.3 0.7 1.1 0.3 0.7 1.1 ns

SKEW

ns

TIMING SPECIFICATIONS—AD6643-200/AD6643-250

Table 5.

Parameter Conditions Min Typ Max Unit

t

SYNC to the rising edge of CLK setup time 0.3 ns

SSYNC

t

SYNC to the rising edge of CLK hold time 0.4 ns

HSYNC

SPI TIMING REQUIREMENTS See Figure 59 for SPI timing diagram

tDS Setup time between the data and the rising edge of SCLK 2 ns tDH Hold time between the data and the rising edge of SCLK 2 ns t

Period of the SCLK 40 ns

CLK

tS Setup time between CSB and SCLK 2 ns tH Hold time between CSB and SCLK 2 ns t

Minimum period that SCLK should be in a logic high state 10 ns

HIGH

t

Minimum period that SCLK should be in a logic low state 10 ns

LOW

t

Time required for the SDIO pin to switch from an input to an output

EN_SDIO

relative to the SCLK falling edge (not shown in Figure 59)

t

Time required for the SDIO pin to switch from an output to an input

DIS_SD IO

relative to the SCLK rising edge (not shown in Figure 59)

10 ns

Rev. B | Page 8 of 40

Data Sheet AD6643

VIN

CLK+

CLK–

DCO–

DCO+

D0

(LSB)

PARALLEL INTERLEAVED

CHANNEL MULTIPLEXED

(ODD/EVEN) MODE

CHANNEL MULTIPLEXED

(ODD/EVEN) MODE

D11

(MSB)

0/D0±

(LSB)

CH A

N – 10

CH B

N – 10

CH A N – 9

CH B N – 9

CH A N – 8

CH B N – 8

CH A N – 7

CH B N – 7

CH A N – 6

CH A

N – 10

CH B

N – 10

CH A N – 9

CH B N – 9

CH A N – 8

CH B N – 8

CH A N – 7

CH B N – 7

CH A N – 6

0

N – 10

CH A0 N – 100N – 9

CH A0

N – 90N – 8

CH A0

N – 80N – 7

CH A0

N – 70N – 6

CH A9 N – 10

CH A10

N – 10

CH A9

N – 9

CH A10

N – 9

CH A9

N – 8

CH A10

N – 8

CH A9

N – 7

CH A10

N – 7

CH A9

N – 6

0

N – 10

CH B0 N – 100N – 9

CH B0

N – 90N – 8

CH B0

N – 80N – 7

CH B0

N – 70N – 6

CH B9 N – 10

CH B10

N – 10

CH B9

N – 9

CH B10

N – 9

CH B9

N – 8

CH B10

N – 8

CH B9

N – 7

CH B10

N – 7

CH B9

N – 6

CHANNEL A

D9/D10±

(MSB)

0/D0±

(LSB)

CHANNEL B

D9/D10±

(MSB)

N – 1

N

N + 1

N + 2

N + 3

N + 4

N + 5

t

A

t

CH

t

PD

t

SKEW

t

DCO

t

CLK

09638-002

. . .

CHANNEL A AND

CHANNEL B

t

SSYNC

t

HSYNC

SYNC

CLK+

09638-003

Timing Diagrams

Figure 2. LVDS Modes for Data Output Timing Latency. NSR Disabled (Enabling NSR Adds an Additional Three Clock Cycles of Latency)

Figure 3. SYNC Timing Inputs

Rev. B | Page 9 of 40

AD6643 Data Sheet

AVDD to AGND

−0.3 V to +2.0 V

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter Rating

Electrical

DRVDD to AGND −0.3 V to +2.0 V VIN+A/VIN+B, VIN−A/VIN−B to AGND −0.3 V to AVDD + 0.2 V CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V SYNC to AGND −0.3 V to AVDD + 0.2 V VCM to AGND −0.3 V to AVDD + 0.2 V CSB to AGND −0.3 V to DRVDD + 0.3 V SCLK to AGND −0.3 V to DRVDD + 0.3 V SDIO to AGND −0.3 V to DRVDD + 0.3 V OEB to AGND −0.3 V to DRVDD + 0.3 V PDWN to AGND −0.3 V to DRVDD + 0.3 V OR+/OR− to AGND −0.3 V to DRVDD + 0.3 V D0−/D0+ Through D10−/D10+

−0.3 V to DRVDD + 0.3 V

to AGND

DCO+/DCO− to AGND −0.3 V to DRVDD + 0.3 V

Environmental

Operating Temperature Range

−40°C to +85°C

(Ambient) Maximum Junction Temperature

150°C

Under Bias Storage Temperature Range

−65°C to +125°C

(Ambient)

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL CHARACTERISTICS

The exposed paddle must be soldered to the ground plane for the LFCSP package. Soldering the exposed paddle to the printed circuit board (PCB) increases the reliability of the solder joints, maximizing the thermal capability of the package.

Typ i c a l θ

is specified for a 4-layer PCB that uses a solid ground

JA

plane. As listed in Table 7, airflow increases heat dissipation, which reduces θ

. In addition, metal in direct contact with the

JA

package leads from metal traces, through holes, ground, and power planes, reduces the θ

.

JA

Table 7. Thermal Resistance

Airflow Velocity

Package Type

64-Lead LFCSP

9 mm × 9 mm (CP-64-4)

1

Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board.

2

Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).

3

Per MIL-Std 883, Method 1012.1.

4

Per JEDEC JESD51-8 (still air).

(m/sec) θ

0 26.8 1.14 10.4 °C/W

1.0 21.6 °C/W

2.0 20.2 °C/W

1, 2

JA

1, 3

θ

JC

1, 4

θ

Unit

JB

ESD CAUTION

Rev. B | Page 10 of 40

Data Sheet AD6643

09638-004

171819202122232425262728293031

32

D1–

D1+

DRVDD

D2–

D2+

D3–

D3+

DCO–

DCO+

D4–

D4+

DRVDD

D5–

D5+

D6–

D6+

646362616059585756555453525150

49

AVDD

VIN+B

VIN–B

AVDD

DNC

VCM

DNC

AVDD

VIN–A

VIN+A

AVDD

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

CLK+ CLK–

SYNC

DNC DNC DNC DNC DNC DNC

DRVDD

DNC DNC DNC

DNC D0– (LSB) D0+ (LSB)

NOTES

1. DNC = DO NOT CONNECT. DO NOT CONNE CT TO THIS PIN.

2. THE EXP OSED THERMAL P ADDLE ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PADDLE MUST BE CONNE CTED TO GROUND FOR PRO P E R OPERATION.

PDWN OEB CSB SCLK SDIO OR+ OR– D10+ (MSB) D10– (MSB) D9+ D9– DRVDD D8+ D8– D7+ D7–

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

AD6643

INTERLEAVED

PARALLEL

LVDS

TOP VIEW

(Not to S cale)

PIN 1

INDICATOR

2

CLK−

Input

ADC Clock Input—Complement.

22

D3−

Output

Channel A/Channel B LVDS Output Data 3—Complement.

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 4. Pin Configuration (Top View), LFCSP Interleaved Parallel LVDS

Table 8. Pin Function Descriptions for the Interleaved Parallel LVDS Mode

Pin No. Mnemonic Type Description

ADC Power Supplies

10, 19, 28, 37 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal). 49, 50, 53, 54, 59, 60, 63, 64 AVDD Supply Analog Power Supply (1.8 V Nominal). 4 to 9, 11 to 14, 55, 56, 58 DNC Do Not Connect. Do not connect to these pins. 0 AGND,

Exposed Paddle

Ground Analog Ground. The exposed thermal paddle on the bottom of the

package provides the analog ground for the device. This exposed paddle must be connected to ground for proper operation.

ADC Analog

51 VIN+A Input Differential Analog Input Pin (+) for Channel A. 52 VIN−A Input Differential Analog Input Pin (−) for Channel A. 62 VIN+B Input Differential Analog Input Pin (+) for Channel B. 61 VIN−B Input Differential Analog Input Pin (−) for Channel B. 57 VCM Output Common-Mode Level Bias Output for Analog Inputs. This pin should be

decoupled to ground using a 0.1 μF capacitor.

1 CLK+ Input ADC Clock Input—True.

Digital Input

3 SYNC Input Digital Synchronization Pin. Slave mode only.

Digital Outputs

15 D0− (LSB) Output Channel A/Channel B LVDS Output Data 0—True. 16 D0+ (LSB) Output Channel A/Channel B LVDS Output Data 0—Complement. 18 D1+ Output Channel A/Channel B LVDS Output Data 1—True. 17 D1− Output Channel A/Channel B LVDS Output Data 1—Complement. 21 D2+ Output Channel A/Channel B LVDS Output Data 2—True. 20 D2− Output Channel A/Channel B LVDS Output Data 2—Complement. 23 D3+ Output Channel A/Channel B LVDS Output Data 3—True.

27 D4+ Output Channel A/Channel B LVDS Output Data 4—True.

Rev. B | Page 11 of 40

AD6643 Data Sheet

31

D6−

Output

Channel A/Channel B LVDS Output Data 6—Complement.

45

SCLK

Input

SPI Serial Clock. The serial shift clock input, which is used to synchronize

Pin No. Mnemonic Type Description

26 D4− Output Channel A/Channel B LVDS Output Data 4—Complement. 30 D5+ Output Channel A/Channel B LVDS Output Data 5—True. 29 D5− Output Channel A/Channel B LVDS Output Data 5—Complement. 32 D6+ Output Channel A/Channel B LVDS Output Data 6—True.

34 D7+ Output Channel A/Channel B LVDS Output Data 7—True. 33 D7− Output Channel A/Channel B LVDS Output Data 7—Complement. 36 D8+ Output Channel A/Channel B LVDS Output Data 8—True. 35 D8− Output Channel A/Channel B LVDS Output Data 8—Complement. 39 D9+ Output Channel A/Channel B LVDS Output Data 9—True. 38 D9− Output Channel A/Channel B LVDS Output Data 9—Complement. 41 D10+ (MSB) Output Channel A/Channel B LVDS Output Data 10—True. 40 D10− (MSB) Output Channel A/Channel B LVDS Output Data 10—Complement. 43 OR+ Output Channel A/Channel B LVDS Overrange—True. 42 OR− Output Channel A/Channel B LVDS Overrange—Complement. 25 DCO+ Output Channel A/Channel B LVDS Data Clock Output—True. 24 DCO− Output Channel A/Channel B LVDS Data Clock Output—Complement.

SPI Control

serial interface reads and writes.

44 SDIO Input/Output SPI Serial Data I/O. A dual purpose pin that typically serves as an input or

an output, depending on the instruction being sent and the relative position in the timing frame.

46 CSB Input Chip Select Bar (Active Low). CSB gates the read and write cycles.

Output Enable Bar

and Power-Down 47 OEB Input/Output Output Enable Bar Input (Active Low). 48 PDWN

Input/Output Power-Down Input (Active High). The operation of this pin depends on

the SPI mode and can be configured as power-down or standby (see Table 14).

Rev. B | Page 12 of 40

ANALOG DEVICES AD6643 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

PRODUCT HIGHLIGHTS

SPECIFICATIONS

ADC DC SPECIFICATIONS

ADC AC SPECIFICATIONS

DIGITAL SPECIFICATIONS—AD6643-200/AD6643-250

SWITCHING SPECIFICATIONS

TIMING SPECIFICATIONS—AD6643-200/AD6643-250

Timing Diagrams

ABSOLUTE MAXIMUM RATINGS

THERMAL CHARACTERISTICS

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS