Analog Devices AD6634 Datasheet
80 MSPS, Dual-Channel WCDMA
a
FEATURES
80 MSPS Wideband Inputs (14 Linear Bits Plus Three
RSSI)
Processes Two WCDMA Channels (UMTS or CDMA2000
1ⴛ) or Four GSM/EDGE, IS136 Channels
Four Independent Digital Receivers in a Single Package
Dual 16-Bit Parallel Output Ports
Dual 8-Bit Link Ports
Programmable Digital AGC Loops with 96 dB Range
Digital Resampling for Noninteger Decimation Rates
Programmable Decimating FIR Filters
Interpolating Half-Band Filters
Programmable Attenuator Control for Clip Prevention
and External Gain Ranging via Level Indicator
Flexible Control for Multicarrier and Phased Array
3.3 V I/O, 2.5 V CMOS Core
User Configurable Built-In Self-Test (BIST) Capability
JTAG Boundary Scan
Receive Signal Processor (RSP)
AD6634
APPLICATIONS
Multicarrier, Multimode Digital Receivers
GSM, IS136, EDGE, PHS, IS95, UMTS, CDMA2000
Micro and Pico Cell Systems, Software Radios
Wireless Local Loop
Smart Antenna Systems
In Building Wireless Telephony
INA[13:0]
EXPA[2:0]
IENA
LIA-A
LIA-B
INB[13:0]
EXPB[2:0]
IENB
LIB-A
LIB-B
SYNCA
SYNCB
SYNCC
SYNCD
I
N
P
U
T
M
A
T
R
I
X
EXTERNAL
SYNC.
CIRCUIT
NCO
NCO
NCO
NCO
rCIC2
RESAMPLER
rCIC2
RESAMPLER
rCIC2
RESAMPLER
rCIC2
RESAMPLER
FUNCTIONAL BLOCK DIAGRAM
CIC5
CIC5
CIC5
CIC5
JTAG
RAM
COEFFICIENT
FILTER
CHANNEL 0
RAM
COEFFICIENT
FILTER
CHANNEL 1
RAM
COEFFICIENT
FILTER
CHANNEL 2
RAM
COEFFICIENT
FILTER
CHANNEL 3
BUILT-IN (BIST)
SELF-TEST CIRCUITRY
MICROPORT OR SERIAL
PORT CONTROL
RCF OUTPUTS
CHANNELS 0, 1, 2, 3
INTERPOLATING
HALF-BAND FILTER
PLUS
DIGITAL AGC
INTERPOLATING
HALF-BAND FILTER
PLUS
DIGITAL AGC
RCF OUTPUTS
CHANNELS 0, 1, 2, 3
PORT A
LINK PORT
OR
PARALLEL
PORT
OUTPUT
MUX
CIRCUITRY
PORT B
LINK PORT
OR
PARALLEL
PORT
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2002
AD6634
TABLE OF CONTENTS
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 4
ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 6
THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . 6
EXPLANATION OF TEST LEVELS . . . . . . . . . . . . . . . . . 6
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
RECOMMENDED OPERATING CONDITIONS . . . . . . . 7
ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . 7
GENERAL TIMING CHARACTERISTICS . . . . . . . . . . . . 8
MICROPROCESSOR PORT TIMING CHARACTERISTICS 9
TIMING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . 17
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . 18
EXAMPLE FILTER RESPONSE . . . . . . . . . . . . . . . . . . . 19
INPUT DATA PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Input Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Input Enable Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Gain Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Input Data Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Scaling with Fixed-Point ADCs . . . . . . . . . . . . . . . . . . . . 21
Scaling with Floating-Point or Gain-Ranging ADCs . . . . 22
NUMERICALLY CONTROLLED OSCILLATOR . . . . . 22
Frequency Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
NCO Frequency Hold-Off Register . . . . . . . . . . . . . . . . . 23
Phase Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
NCO Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Phase Dither . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Amplitude Dither . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Clear Phase Accumulator on HOP . . . . . . . . . . . . . . . . . . 23
Input Enable Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Mode 00: Blank on IEN Low . . . . . . . . . . . . . . . . . . . . . . 23
Mode 01: Clock on IEN High . . . . . . . . . . . . . . . . . . . . . 23
Mode 10: Clock on IEN Transition to High . . . . . . . . . . 24
Mode 11: Clock on IEN Transition to Low . . . . . . . . . . . 24
WB Input Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Sync Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
SECOND ORDER rCIC FILTER . . . . . . . . . . . . . . . . . . . 24
rCIC2 Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Example Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Decimation and Interpolation Registers . . . . . . . . . . . . . . 25
rCIC2 Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
FIFTH ORDER CIC FILTER . . . . . . . . . . . . . . . . . . . . . . 25
CIC5 Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
RAM COEFFICIENT FILTER . . . . . . . . . . . . . . . . . . . . . 27
RCF Decimation Register . . . . . . . . . . . . . . . . . . . . . . . . 27
RCF Decimation Phase . . . . . . . . . . . . . . . . . . . . . . . . . . 27
RCF Filter Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
RCF Output Scale Factor and Control Register . . . . . . . . 27
INTERPOLATING HALF-BAND FILTERS . . . . . . . . . . 28
AUTOMATIC GAIN CONTROL . . . . . . . . . . . . . . . . . . . 28
The AGC Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Desired Signal Level Mode . . . . . . . . . . . . . . . . . . . . . . . 29
Desired Clipping Level Mode . . . . . . . . . . . . . . . . . . . . . 31
Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
USER CONFIGURABLE BUILT-IN SELF TEST (BIST) 31
RAM BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Channel BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
CHIP SYNCHRONIZATION . . . . . . . . . . . . . . . . . . . . . . 32
Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Start with No Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Start with Soft Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Start with Pin Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Hop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Set Freq No Hop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Hop with Soft Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Hop with Pin Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
PARALLEL OUTPUT PORTS . . . . . . . . . . . . . . . . . . . . . 33
Channel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
AGC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Master/Slave PCLK Modes . . . . . . . . . . . . . . . . . . . . . . . 35
Parallel Port Pin Functionality . . . . . . . . . . . . . . . . . . . . . 35
LINK PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Link Port Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Link Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
TigerSHARC Configuration . . . . . . . . . . . . . . . . . . . . . . 36
MEMORY MAPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
0x00–0x7F: Coefficient Memory (CMEM) . . . . . . . . . . . 36
0x80: Channel Sleep Register . . . . . . . . . . . . . . . . . . . . . . 37
0x81: Soft_SYNC Register . . . . . . . . . . . . . . . . . . . . . . . . 37
0x82: Pin_SYNC Register . . . . . . . . . . . . . . . . . . . . . . . . 37
0x83: Start Hold-Off Counter . . . . . . . . . . . . . . . . . . . . . 37
0x84: NCO Frequency Hold-Off Counter . . . . . . . . . . . . 37
0x85: NCO Frequency Register 0 . . . . . . . . . . . . . . . . . . 37
0x86: NCO Frequency Register 1 . . . . . . . . . . . . . . . . . . 38
0x87: NCO Phase Offset Register . . . . . . . . . . . . . . . . . . 38
0x88: NCO Control Register . . . . . . . . . . . . . . . . . . . . . . 38
0x90: rCIC2 Decimation–1 (M
0x91: rCIC2 Interpolation–1 (L
–1) . . . . . . . . . . . . . . 39
rCIC2
–1) . . . . . . . . . . . . . . 39
rCIC2
0x92: rCIC2 Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
0x93: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
0x94: CIC5 Decimation–1 (M
–1) . . . . . . . . . . . . . . . 40
CIC5
0x95: CIC5 Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
0x96: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
0xA0: RCF Decimation–1 (M
0xA1: RCF Decimation Phase (P
0xA2: RCF Number of Taps Minus One (N
0xA3: RCF Coefficient Offset (CO
–1) . . . . . . . . . . . . . . . . 40
RCF
) . . . . . . . . . . . . . . . 40
RCF
) . . . . . . . . . . . . . . 40
RCF
–1) . . . . . 40
RCF
0xA4: RCF Control Register . . . . . . . . . . . . . . . . . . . . . . 40
0xA5: BIST Register for I . . . . . . . . . . . . . . . . . . . . . . . . 40
0xA6: BIST Register for Q . . . . . . . . . . . . . . . . . . . . . . . . 40
0xA7: BIST Control Register . . . . . . . . . . . . . . . . . . . . . . 41
0xA8: RAM BIST Control Register . . . . . . . . . . . . . . . . . 41
0xA9: Output Control Register . . . . . . . . . . . . . . . . . . . . 41
Memory Map for Input Port Control Registers . . . . . . . . . . 41
Input Port Control Registers . . . . . . . . . . . . . . . . . . . . . . 41
0x00 Lower Threshold A . . . . . . . . . . . . . . . . . . . . . . . . . 41
0x01 Upper Threshold A . . . . . . . . . . . . . . . . . . . . . . . . . 41
0x02 Dwell Time A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
0x03 Gain Range A Control Register . . . . . . . . . . . . . . . . 41
0x04 Lower Threshold B . . . . . . . . . . . . . . . . . . . . . . . . . 42
0x05 Upper Threshold B . . . . . . . . . . . . . . . . . . . . . . . . . 42
0x06 Dwell Time B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
0x07 Gain Range B Control Register . . . . . . . . . . . . . . . . 42
REV. 0–2–
TABLE OF CONTENTS (continued)
Memory Map for Output Port Control Registers . . . . . . . . . 45
0x08 Port A Control Register . . . . . . . . . . . . . . . . . . . . . . 45
0x09 Port B Control Register . . . . . . . . . . . . . . . . . . . . . . 45
0x0A AGC A Control Register . . . . . . . . . . . . . . . . . . . . . 45
0x0B AGC A Hold-Off Counter . . . . . . . . . . . . . . . . . . . 45
0x0C AGC A Desired Level . . . . . . . . . . . . . . . . . . . . . . . 45
0x0D AGC A Signal Gain . . . . . . . . . . . . . . . . . . . . . . . . 45
0x0E AGC A Loop Gain . . . . . . . . . . . . . . . . . . . . . . . . . 45
0x0F AGC A Pole Location . . . . . . . . . . . . . . . . . . . . . . . 45
0x10 AGC A Average Samples . . . . . . . . . . . . . . . . . . . . . 45
0x11 AGC A Update Decimation . . . . . . . . . . . . . . . . . . 46
0x12 AGC B Control Register . . . . . . . . . . . . . . . . . . . . . 46
0x13 AGC B Hold-Off Counter . . . . . . . . . . . . . . . . . . . . 46
0x14 AGC B Desired Level . . . . . . . . . . . . . . . . . . . . . . . 46
0x15 AGC B Signal Gain . . . . . . . . . . . . . . . . . . . . . . . . . 46
0x16 AGC B Loop Gain . . . . . . . . . . . . . . . . . . . . . . . . . 46
0x17 AGC B Pole Location . . . . . . . . . . . . . . . . . . . . . . . 46
0x18 AGC B Average Samples . . . . . . . . . . . . . . . . . . . . . 46
0x19 AGC B Update Decimation . . . . . . . . . . . . . . . . . . 46
0x1A Parallel Port Control A . . . . . . . . . . . . . . . . . . . . . . 46
0x1B Link Port Control A . . . . . . . . . . . . . . . . . . . . . . . . 47
0x1C Parallel Port Control B . . . . . . . . . . . . . . . . . . . . . . 47
0x1D Link Port Control B . . . . . . . . . . . . . . . . . . . . . . . . 47
0x1E Port Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . 47
AD6634
MICROPORT CONTROL . . . . . . . . . . . . . . . . . . . . . . . . 48
External Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Access Control Register (ACR) . . . . . . . . . . . . . . . . . . . . 48
Microport Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Channel Address Register (CAR) . . . . . . . . . . . . . . . . . . . 49
SOFT_SYNC Control Register . . . . . . . . . . . . . . . . . . . . 49
PIN_SYNC Control Register . . . . . . . . . . . . . . . . . . . . . . 49
SLEEP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . 49
Data Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Write Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Read Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Read/Write Chaining . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Intel Nonmultiplexed Mode (INM) . . . . . . . . . . . . . . . . . 50
Motorola Nonmultiplexed Mode (MNM) . . . . . . . . . . . . 50
SERIAL PORT CONTROL . . . . . . . . . . . . . . . . . . . . . . . . 50
Serial Port Timing Specifications . . . . . . . . . . . . . . . . . . . 50
SDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
SCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
JTAG BOUNDARY SCAN . . . . . . . . . . . . . . . . . . . . . . . . 51
INTERNAL WRITE ACCESS . . . . . . . . . . . . . . . . . . . . . . 51
Write Pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
INTERNAL READ ACCESS . . . . . . . . . . . . . . . . . . . . . . . 52
Read Pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 52
REV. 0
–3–
AD6634
GENERAL DESCRIPTION
The AD6634 is a multimode 4-channel digital receive signal processor (RSP) capable of processing up to two WCDMA channels.
Each channel consists of four cascaded signal processing elements:
a frequency translator, two fixed coefficient decimating filters,
and a programmable coefficient decimating filter. Each input port
has input level threshold detection circuitry and an AGC controller for accommodating large dynamic ranges or situations
where gain ranging converters are used. Dual 16-bit parallel output
ports accommodate high data rate WBCDMA applications. On-chip
interpolating half-band can also be used to further increase the
output rate. In addition, each parallel output port has a digital
AGC for output data scaling. Link port outputs are provided to
enable glueless interfaces to ADI’s TigerSHARC
The AD6634 is part of Analog Devices’ SoftCell
®
DSP core.
®
Multicarrier
transceiver chipset designed for compatibility with Analog Devices’
family of high sample rate IF sampling ADCs (AD9238/AD6645
12- and 14-bit). The SoftCell receiver comprises a digital receiver
capable of digitizing an entire spectrum of carriers and digitally
selecting the carrier of interest for tuning and channel selection.
This architecture eliminates redundant radios in wireless base
station applications.
High dynamic range decimation filters offer a wide range of
decimation rates. The RAM-based architecture allows easy
reconfiguration for multimode applications.
The decimating filters remove unwanted signals and noise from
the channel of interest. When the channel of interest occupies less
bandwidth than the input signal, this rejection of out-of-band
noise is called processing gain. By using large decimation factors,
this processing gain can improve the SNR of the ADC by 30 dB
or more. In addition, the programmable RAM coefficient filter
allows antialiasing, matched filtering, and static equalization functions to be combined in a single, cost-effective filter. Half-band
interpolating filters at the output are used in WCDMA applications
to increase the output rate from 2× to 4× of the chip rate. The
AD6634 is also equipped with two independent automatic gain
control (AGC) loops for direct interface to a RAKE receiver.
The AD6634 is compatible with standard ADC converters such
as the AD664x, AD923x, AD943x, and the AD922x families of
data converters. The AD6634 is also compatible with the AD6600
diversity ADC, providing a cost and size reduction path.
ARCHITECTURE
The AD6634 has four signal processing stages: a frequency
translator, second order resampling cascaded integrator comb
FIR filters (rCIC2), a fifth order cascaded integrator comb FIR
filter (CIC5), and a RAM coefficient FIR filter (RCF). Multiple
modes are supported for clocking data into and out of the chip
and provide flexibility for interfacing to a wide variety of digitizers.
Programming and control are accomplished via serial and/or
microprocessor interfaces.
Frequency translation is accomplished with a 32-bit, complex,
numerically controlled oscillator (NCO). Real data entering this
stage is separated into inphase (I) and quadrature (Q) components.
This stage translates the input signal from a digital intermediate
frequency (IF) to digital baseband. Phase and amplitude dither
may be enabled on-chip to improve spurious performance of the
NCO. A phase-offset word is available to create a known phase
relationship among multiple AD6634s or between channels.
Following frequency translation is a resampling, fixed coefficient,
high speed, second order, resampling cascade integrator comb
(rCIC2) filter that reduces the sample rate based on the ratio
between the decimation and interpolation registers.
The next stage is a fifth order cascaded integrator comb (CIC5)
filter whose response is defined by the decimation rate. The purpose
of this filter is to reduce the data rate to the final filter stage so
that it can calculate more taps per output.
The final stage is a sum-of-products FIR filter with programmable 20-bit coefficients, and decimation rates programmable
from 1 to 256 (1–32 in practice). The RAM coefficient FIR filter
(RCF in the Functional Block Diagram) can handle a maximum
of 160 taps.
The next stage is a fixed coefficient half-band interpolation filter
where data from different channels is combined together and
interpolated by a factor of 2. Next, an AGC section with a gain
range of 96.3 dB is available. This AGC section is completely
programmable in terms of its response. Two each of half-band
filters and AGCs are present in the AD6634, as shown in the
Functional Block Diagram. These half-band filters and AGC
sections can be bypassed independent of each other.
The overall filter response for the AD6634 is the composite of all
decimating and interpolating stages. Each successive filter stage is
capable of narrower transition bandwidths but requires a greater
number of CLK cycles to calculate the output. More decimation
in the first filter stage will minimize overall power consumption.
Data from the chip is interfaced to the DSP via either a high
speed parallel port or a TigerSHARC compatible link port.
Figure 1a illustrates the basic function of the AD6634: to select and
filter a single channel from a wide input spectrum. The frequency
translator tunes the desired carrier to baseband. Figure 1b shows
the combined filter response of the rCIC2, CIC5, and RCF.
*TigerSHARC and SoftCell are registered trademarks of Analog Devices, Inc.
REV. 0–4–
AD6634
WIDEBAND INPUT SPECTRUM
SIGNAL OF INTEREST “IMAGE” SIGNAL OF INTEREST
–fS/2 –3fS/8 –5fS/16 –fS/4 –3fS/16 –fS/8 –fS/16
WIDEBAND INPUT SPECTRUM (e.g., 30MHz FROM HIGH SPEED ADC)
AFTER FREQUENCY TRANSLATION NCO “TUNES” SIGNAL TO BASEBAND
–fS/2 –3fS/8 –5fS/16 –fS/4 –3fS/16 –fS/8 –fS/16
FREQUENCY TRANSLATION (e.g., SINGLE 1MHz CHANNEL TUNED TO BASEBAND)
Figure 1a. Frequency Translation of Wideband Input Spectrum
20
/2 TO f
(f
SAMPLE
dc
dc
f
/16 fS/8 3fS/16 fS/4 5fS/16 3fS/8 fS/2
S
f
/16 fS/8 3fS/16 fS/4 5fS/16 3fS/8 fS/2
S
SAMPLE
/2)
dBc
–20
–40
–60
–80
–100
–120
0
–1.510
4
–1.010
4
–5000 0 5000
kHz
Figure 1b. Composite Filter Response of rCIC2, CIC5, and RCF
1.010
4
1.510
4
REV. 0
–5–
AD6634
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 V
Input Voltage . . . . . . . . . . . . –0.3 V to +5.3 V (5 V Tolerant)
Output Voltage Swing . . . . . . . . . . –0.3 V to VDDIO +0.3 V
Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF
Junction Temperature Under Bias . . . . . . . . . . . . . . . . . 125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
THERMAL CHARACTERISTICS
196-Lead BGA:
= 41°C/W, No Airflow
JA
= 39°C/W, 200-lfpm Airflow
JA
= 37°C/W, 400-lfpm Airflow
JA
Thermal measurements made in the horizontal position on a
4-layer board.
Lead Temperature (5 sec) . . . . . . . . . . . . . . . . . . . . . . 280°C
*Stresses greater than those listed under Absolute Maximum Ratings may cause
permanent damage to the device. These are stress ratings only; functional
operation of the devices at these or any other conditions greater than those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect device
reliability.
EXPLANATION OF TEST LEVELS
I. 100% Production Tested.
II. 100% Production Tested at 25°C, and Sampled Tested at
Specified Temperatures.
III. Sample Tested Only
IV. Parameter Guaranteed by Design and Analysis
V. Parameter is Typical Value Only
VI. 100% Production Tested at 25°C, and Sampled Tested at
Temperature Extremes
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD6634BBC –40°C to +85°C (Ambient) 196-Lead CSPBGA (Ball Grid Array) BC-196
AD6634BC/PCB Evaluation Board with AD6634 and Software
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD6634 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0–6–
AD6634
SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
Test AD6634BBC
Parameter Temp Level Min Typ Max Unit
VDD IV 2.25 2.5 2.75 V
VDDIO IV 3.0 3.3 3.6 V
T
AMBIENT
ELECTRICAL CHARACTERISTICS
Parameter (Conditions) Temp Level Min Typ Max Unit
LOGIC INPUTS (5 V Tolerant)
Logic Compatibility Full IV 3.3 CMOS V
Logic “1” Voltage Full IV 2.0 5.0 V
Logic “0” Voltage Full IV –0.3 +0.8 V
Logic “1” Current Full IV 1 10 µA
Logic “0” Current Full IV 1 10 µA
Logic “1” Current (Inputs with Pull-Down) Full IV
Logic “0” Current (Inputs with Pull-Up) Full IV
Input Capacitance 25°CV 4 pF
LOGIC OUTPUTS
Logic Compatibility Full IV 3.3 CMOS/TTL V
Logic “1” Voltage (I
Logic “0” Voltage (I
IDD SUPPLY CURRENT
CLK = 80 MHz, (VDD = 2.75 V, VDDIO = 3.6 V) Full IV
I
VDD
I
VDDIO
CLK = GSM Example (65 MSPS, VDD = 2.5 V,
VDDIO = 3.3 V, Dec = 2/10/6 120 Taps
Four Channels) 25°CV
I
VDD
I
VDDIO
CLK = WBCDMA Example (76.8 MSPS,
VDD = 2.5 V, VDDIO = 3.3 V, Dec = 2/10/6
120 Taps Four Channels) 25°CV
I
VDD
I
VDDIO
POWER DISSIPATION
CLK = 80 MHz Full IV 1.05 1.45 W
CLK = 65 MHz GSM/EDGE Example V 840 mW
CLK = 76.8 MHz WBCDMA Example V 1.2 W
Sleep Mode Full IV 287 µW
Specifications subject to change without notice.
= 0.25 mA) Full IV 2.4 VDD–0.2 V
OH
= 0.25 mA) Full IV 0.2 0.4 V
OL
IV –40 +25 +85 °C
Test AD6634BBC
397 443 mA
50 58 mA
TBD mA
TBD mA
TBD mA
TBD mA
REV. 0
–7–
AD6634
GENERAL TIMING CHARACTERISTICS
1, 2
Test AD6634BBC
Parameter (Conditions) Temp Level Min Typ Max Unit
CLK TIMING REQUIREMENTS
t
CLK
t
CLKL
t
CLKH
CLK Period Full I 12.5 ns
CLK Width Low Full IV 5.6 0.5 × t
CLK Width High Full IV 5.6 0.5 × t
CLK
CLK
ns
ns
RESET TIMING REQUIREMENTS
t
RESL
RESET Width Low Full I 30.0 ns
INPUT WIDEBAND DATA TIMING REQUIREMENTS
t
SI
t
HI
Input to ↑CLK Setup Time Full IV 2.0 ns
Input to ↑CLK Hold Time Full IV 1.0 ns
LEVEL INDICATOR OUTPUT SWITCHING CHARACTERISTICS
t
DLI
↑CLK to LI (A–A, B; B–A, B) Output Delay Time Full IV 3.3 10.0 ns
SYNC TIMING REQUIREMENTS
t
SS
t
HS
SERIAL PORT CONTROL TIMING REQUIREMENTS
SWITCHING CHARACTERISTICS
t
SCLK
t
SCLKL
t
SCLKH
SYNC (A, B, C, D) to ↑CLK Setup Time Full IV 2.0 ns
SYNC (A, B, C, D) to ↑CLK Hold Time Full IV 1.0 ns
2
SCLK Period Full IV 16 ns
SCLK Low Time Full IV 3.0 ns
SCLK High Time Full IV 3.0 ns
INPUT CHARACTERISTICS
t
SSI
t
HSI
PARALLEL PORT TIMING REQUIREMENTS (MASTER MODE)
SWITCHING CHARACTERISTICS
t
DPOCLKL
t
DPOCLKLL
t
DPREQ
t
DPP
SDI to ↓SCLK Setup Time Full IV 1.0 ns
SDI to ↓SCLK Hold Time Full IV 1.0 ns
3
↓CLK to ↑PCLK Delay (Divide by 1) Full IV 6.5 10.5 ns
↓CLK to ↑PCLK Delay (Divide by 2, 4, or 8) Full IV 8.3 14.6 ns
↑CLK to ↑PxREQ Delay 1.0 ns
↑CLK to Px[15:0] Delay 0.0 ns
INPUT CHARACTERISTICS
t
SPA
t
HPA
PARALLEL PORT TIMING REQUIREMENTS (SLAVE MODE)
SWITCHING CHARACTERISTICS
t
POCLK
t
POCLKL
t
POCLKH
t
DPREQ
t
DPP
PxACK to ↓PCLK Setup Time +7.0 ns
PxACK to ↓PCLK Hold Time –3.0 ns
3
PCLK Period Full I 12.5 ns
PCLK Low Period (when PCLK Divisor = 1) Full IV 2.0 0.5 × t
PCLK High Period (when PCLK Divisor = 1) Full IV 2.0 0.5 × t
POCLK
POCLK
ns
ns
↑CLK to ↑PxREQ Delay 10.0 ns
↑CLK to Px[15:0] Delay 11.0 ns
INPUT CHARACTERISTICS
t
SPA
t
HPA
LINK PORT TIMING REQUIREMENTS
SWITCHING CHARACTERISTICS
t
RDLCLK
t
FDLCLK
t
RLCLKDAT
t
FLCLKDAT
NOTES
1
All Timing Specifications valid over VDD range of 2.25 V to 2.75 V and VDDIO range of 3.0 V to 3.6 V.
2
C
= 40 pF on all outputs unless otherwise specified
LOAD
3
The timing parameters for Px[15:0], PxREQ, PxACK, LxCLKOUT, Lx[7:0] apply for port A and B (x stands for A or B).
Specifications subject to change without notice.
PxACK to ↓PCLK Setup Time 1.0 ns
PxACK to ↓PCLK Hold Time 1.0 ns
3
↑PCLK to ↑LxCLKOUT Delay Full IV 2.5 ns
↓PCLK to ↓LxCLKOUT Delay Full IV 0 ns
↑LCLKOUT to Lx[7:0] Delay Full IV 0 2.9 ns
↓LCLKOUT to Lx[7:0] Delay Full IV 0 2.2 ns
REV. 0–8–
AD6634
MICROPROCESSOR PORT TIMING CHARACTERISTICS
1, 2
Test AD6634BBC
Parameter (Conditions) Temp Level Min Typ Max Unit
MICROPROCESSOR PORT, MODE INM (MODE = 0)
MODE INM WRITE TIMING
t
SC
t
HC
t
HWR
t
SAM
t
HAM
t
DRDY
t
ACC
Control3 to ↑CLK Setup Time Full IV 2.0 ns
Control3 to ↑CLK Hold Time Full IV 2.5 ns
WR(RW) to RDY(DTACK) Hold Time Full IV 7.0 ns
Address/Data to WR(RW) Setup Time Full IV 3.0 ns
Address/Data to RDY(DTACK) Hold Time Full IV 5.0 ns
WR(RW) to RDY(DTACK) Delay Full IV 8.0 ns
WR(RW) to RDY(DTACK) High Delay Full IV 4 × t
CLK
5 × t
CLK
9 × t
CLK
ns
MODE INM READ TIMING
t
SC
t
HC
t
SAM
t
HAM
t
DRDY
t
ACC
Control3 to ↑CLK Setup Time Full IV 5.0 ns
Control3 to ↑CLK Hold Time Full IV 2.0 ns
Address to RD(DS) Setup Time Full IV 0.0 ns
Address to Data Hold Time Full IV 5.0 ns
RD(DS) to RDY(DTACK) Delay Full IV 8.0 ns
RD(DS) to RDY(DTACK) High Delay Full IV 8 × t
CLK
10 × t
CLK
13 × t
CLK
ns
MICROPROCESSOR PORT, MODE MNM (MODE = 1)
MODE MNM WRITE TIMING
t
SC
t
HC
t
HDS
t
HRW
t
SAM
t
HAM
t
DDTACK
t
ACC
Control3 to ↑CLK Setup Time Full IV 2.0 ns
Control3 to ↑CLK Hold Time Full IV 2.5 ns
DS(RD) to DTACK(RDY) Hold Time Full IV 8.0 ns
RW(WR) to DTACK(RDY) Hold Time Full IV 7.0 ns
Address/Data to RW(WR) Setup Time Full IV 3.0 ns
Address/Data to RW(WR) Hold Time Full IV 5.0 ns
DS(RD) to DTACK(RDY) Delay Full IV 8.0 ns
RW(WR) to DTACK(RDY) Low Delay Full IV 4 × t
CLK
5 × t
CLK
9 × t
CLK
ns
MODE MNM READ TIMING
t
SC
t
HC
t
HDS
t
SAM
t
HAM
t
DDTACK
t
ACC
NOTES
1
All Timing Specifications valid over VDD range of 2.25 V to 2.75 V and VDDIO range of 3.0 V to 3.6 V.
2
C
LOAD
3
Specification pertains to control signals: R/W, (WR), DS (RD), CS.
Specifications subject to change without notice.
Control3 to ↑CLK Setup Time Full IV 5.0 ns
Control3 to ↑CLK Hold Time Full IV 2.0 ns
DS(RD) to DTACK(RDY) Hold Time Full IV 8.0 ns
Address to DS(RD) Setup Time Full IV 0.0 ns
Address to Data Hold Time Full IV 5.0 ns
DS(RD) to DTACK(RDY) Delay Full IV 8.0 ns
DS(RD) to DTACK(RDY) Low Delay Full IV 8 × t
= 40 pF on all outputs, unless otherwise specified.
CLK
10 × t
CLK
13 × t
CLK
ns
REV. 0
–9–
AD6634
TIMING DIAGRAMS
t
CLK
t
CLK
LIA–A
LIA–B
LIB–A
LIB–B
t
CLKH
t
DLI
CLKL
Figure 2. Level Indicator Output Switching Characteristics
RESET
t
RESL
SCLK
SDI
SCLK
t
SCLKL
Figure 3.
t
SCLKH
RESET
Timing Requirements
Figure 4. SCLK Switching Characteristics
t
SSI
t
HSI
DATAn
Figure 5. Serial Port Input Timing Characteristics
CLK
t
HI
INx[13:0]
EXPx[2:0]
IENx
t
SI
Figure 6. Input Timing for A and B Channels
REV. 0–10–
CLK
AD6634
CLK
PCLK
CLK
t
HS
SYNCA
SYNCB
SYNCC
CYNCD
t
SS
Figure 7. SYNC Timing Inputs
t
DPOCLKL
Figure 8. PCLK to CLK Switching Characteristics Divide by 1
t
DPOCLKLL
PCLK
t
POCLKH
t
POCLKL
Figure 9. PCLK to CLK Switching Characteristics Divide by 2, 4, or 8
PCLK
t
HPA
PxACK
t
SPA
Figure 10. Master Mode PxACK to PCLK Setup and Hold Characteristics
REV. 0
–11–
AD6634
PxREQ
PxACK
PCLK
t
SPA
t
SPA
Px[15:0]
PCLK
PxACK
PxREQ
Px[15:0]
t
DPP
DATA 1 DATA 2 DATA N–1 DATA N
t
DPP
Figure 11. Master Mode PxACK to PCLK Switching Characteristics
t
DPREQ
t
DPP
DATA 1 DATA N
Figure 12. Master Mode PxREQ to PCLK Switching Characteristics
t
DPP
t
PCLK
PxACK
t
POCLKH
t
SPA
POCLKL
t
HPA
Figure 13. Slave Mode PxACK to PCLK Setup and Hold Characteristics
REV. 0–12–
PCLK
PxREQ
PxACK
AD6634
t
SPA
t
SPA
Px[15:0]
PCLK
PxACK
PxREQ
Px[15:0]
t
DPP
DATA 1 DATA 2 DATA N–1 DATA N
t
DPP
Figure 14. Slave Mode PxACK to PCLK Switching Characteristics
t
DPREQ
t
DPP
DATA 1 DATA N
Figure 15. Slave Mode PxREQ to PCLK Switching Characteristics
t
DPP
REV. 0
PCLK
LxCLKOUT
t
RDLCLK
t
FDLCL
Figure 16. LxCLKOUT to PCLK Switching Characteristics
–13–
AD6634
LxCLKOUT
LxCLKIN
WAIT > = 6 CYCLES
ONE TIME CONNECTIVITY CHECK
8 LxCLKOUT CYCLES
NEXT TRANSFER
ACKNOWLEDGE
NEXT TRANSFER
BEGINS
Lx[7:0]
LxCLKOUT
Lx[7:0]
D1 D2 D3 D4 D15 D0 D1 D2 D3
D0
Figure 17. LxCLKIN to LxCLKOUT Data Switching Characteristics
t
FDLCLKDAT
t
RDLCLKDAT
Figure 18. LxCLKOUT to Lx[7:0] Data Switching Characteristics
REV. 0–14–
TIMING DIAGRAMS—INM MICROPORT MODE
CLK
RD (DS
)
t
SC
WR
(RW)
CS
t
HWR
AD6634
t
HC
A[2:0]
D[7:0]
RDY
DTACK
(
CLK
RD (DS)
WR (RW)
t
SAM
t
SAM
t
DRDY
)
NOTES
1.
t
ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS MEASURED
ACC
FROM FE OF WR TO RE OF RDY.
t
REQUIRES A MAXIMUM OF 9 CLK PERIODS.
2.
ACC
VA LID ADDRESS
VA LID DATA
t
ACC
t
t
HAM
HAM
Figure 19. INM Microport Write Timing Requirements
t
SC
t
HC
REV. 0
CS
A[2:0]
D[7:0]
RDY
(DTACK)
t
SAM
VA LID ADDRESS
VA LID DATA
t
DRDY
t
NOTES
1.
t
ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS MEASURED
ACC
FROM FE OF WR TO RE OF RDY.
t
REQUIRES A MAXIMUM OF 13 CLK PERIODS.
2.
ACC
ACC
Figure 20. INM Microport Read Timing Requirements
–15–
t
HAM
AD6634
TIMING DIAGRAMS—MNM MICROPORT MODE
CLK
t
SC
DS (RD)
RW (WR)
CS
t
HDS
t
HRW
t
HC
A[2:0]
D[7:0]
DTACK
(RDY)
CLK
DS (RD)
RW (WR)
t
ACC
t
t
HAM
HAM
t
DDTACK
t
SAM
VA LID ADDRESS
t
SAM
VA LID DATA
NOTES
t
ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS MEASURED
1.
ACC
FROM FE OF DS TO TH E FE OF DTACK.
t
REQUIRES A MAXIMUM OF 9 CLK PERIODS.
2.
ACC
Figure 21. MNM Microport Write Timing Requirements
t
t
SC
t
HDS
HC
CS
A[2:0]
D[7:0]
DTACK
(RDY)
t
SAM
VA LID ADDRESS
t
HAM
VA LID DATA
t
DDTACK
t
ACC
NOTES
t
ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS MEASURED
1.
ACC
FROM THE FE OF DS TO TH E FE OF DTACK.
t
REQUIRES A MAXIMUM OF 13 CLK PERIODS.
2.
ACC
Figure 22. MNM Microport Read Timing Requirements
REV. 0–16–
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