Analog Devices AD5334 5 6 44 Datasheet
2.5 V to 5.5 V, 500 A, Parallel Interface
a
Quad Voltage-Output 8-/10-/12-Bit DACs
FEATURES
AD5334: Quad 8-Bit DAC in 24-Lead TSSOP
AD5335: Quad 10-Bit DAC in 24-Lead TSSOP
AD5336: Quad 10-Bit DAC in 28-Lead TSSOP
AD5344: Quad 12-Bit DAC in 28-Lead TSSOP
Low Power Operation: 500 A @ 3 V, 600 A @ 5 V
Power-Down to 80 nA @ 3 V, 200 nA @ 5 V via PD Pin
2.5 V to 5.5 V Power Supply
Double-Buffered Input Logic
Guaranteed Monotonic by Design Over All Codes
Output Range: 0–V
or 0–2 V
REF
REF
Power-On Reset to Zero Volts
Simultaneous Update of DAC Outputs via LDAC Pin
Asynchronous CLR Facility
Low Power Parallel Data Interface
On-Chip Rail-to-Rail Output Buffer Amplifiers
Temperature Range: –40ⴗC to +105ⴗC
APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
Industrial Process Control
AD5334/AD5335/AD5336/AD5344*
GENERAL DESCRIPTION
The AD5334/AD5335/AD5336/AD5344 are quad 8-, 10-, and
12-bit DACs. They operate from a 2.5 V to 5.5 V supply consuming just 500 µA at 3 V, and feature a power-down mode that
further reduces the current to 80 nA. These devices incorporate
an on-chip output buffer that can drive the output to both supply rails.
The AD5334/AD5335/AD5336/AD5344 have a parallel interface.
CS selects the device and data is loaded into the input registers
on the rising edge of WR.
The GAIN pin on the AD5334 and AD5336 allows the output
range to be set at 0 V to V
Input data to the DACs is double-buffered, allowing simultaneous
update of multiple DACs in a system using the LDAC pin.
On the AD5334, AD5335 and AD5336 an asynchronous CLR
input is also provided. This resets the contents of the Input
Register and the DAC Register to all zeros. These devices also
incorporate a power-on-reset circuit that ensures that the DAC
output powers on to 0 V and remains there until valid data is
written to the device.
The AD5334/AD5335/AD5336/AD5344 are available in Thin
Shrink Small Outline Packages (TSSOP).
or 0 V to 2 × V
REF
REF
.
AD5334 FUNCTIONAL BLOCK DIAGRAM
(Other Diagrams Inside)
POWER-ON
RESET
GAIN
DB
7
.
.
.
DB
0
CS
WR
A0
A1
CLR
LDAC
*Protected by U.S. Patent Number 5,969,657; other patents pending.
INTER-
FACE
LOGIC
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
V
A/B
REF
V
DD
AD5334
8-BIT
DAC
8-BIT
DAC
8-BIT
8-BIT
DAC
DAC
8-BIT
DAC
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2000
BUFFER
BUFFER
BUFFER
BUFFER
TO ALL DACS
AND BUFFERS
POWER-DOWN
LOGIC
V
REF
C/D
PD
GND
V
A
OUT
V
B
OUT
C
V
OUT
D
V
OUT
AD5334/AD5335/AD5336/AD5344–SPECIFICATIONS
(VDD = 2.5 V to 5.5 V, V
Parameter
DC PERFORMANCE
DAC REFERENCE INPUT
OUTPUT CHARACTERISTICS
LOGIC INPUTS
POWER REQUIREMENTS
NOTES
1
See Terminology section.
2
Temperature range: B Version: –40°C to +105°C; typical specifications are at 25°C.
3
Linearity is tested using a reduced code range: AD5334 (Code 8 to 255); AD5335/AD5336 (Code 28 to 1023); AD5344 (Code 115 to 4095).
4
DC specifications tested with outputs unloaded.
5
This corresponds to x codes. x = Deadband voltage/LSB size.
6
Guaranteed by design and characterization, not production tested.
7
In order for the amplifier output to reach its minimum voltage, Offset Error must be negative. In order for the amplifier output to reach its maximum voltage, V
“Offset plus Gain” Error must be positive.
Specifications subject to change without notice.
1
AD5334
Resolution 8 Bits
Relative Accuracy ± 0.15 ± 1 LSB
Differential Nonlinearity ± 0.02 ± 0.25 LSB Guaranteed Monotonic By Design Over All Codes
AD5335/AD5336
Resolution 10 Bits
Relative Accuracy ± 0.5 ± 4 LSB
Differential Nonlinearity ± 0.05 ± 0.5 LSB Guaranteed Monotonic By Design Over All Codes
AD5344
Resolution 12 Bits
Relative Accuracy ± 2 ± 16 LSB
Differential Nonlinearity ± 0.2 ± 1 LSB Guaranteed Monotonic By Design Over All Codes
Offset Error ± 0.4 ± 3 % of FSR
Gain Error ± 0.1 ± 1 % of FSR
Lower Deadband
Upper Deadband 10 60 mV VDD = 5 V. Upper Deadband Exists Only if V
Offset Error Drift
Gain Error Drift
DC Power Supply Rejection Ratio
DC Crosstalk
V
Input Range 0.25 V
REF
V
Input Impedance 180 kΩ Gain = 1. Input Impedance = R
REF
6
6
Reference Feedthrough –90 dB Frequency = 10 kHz
Channel-to-Channel Isolation –90 dB Frequency = 10 kHz
Minimum Output Voltage
Maximum Output Voltage
DC Output Impedance 0.5 Ω
Short Circuit Current 50 mA VDD = 5 V
Power-Up Time 2.5 µs Coming Out of Power-Down Mode. VDD = 5 V
6
Input Current ± 1 µA
VIL, Input Low Voltage 0.8 V V
VIH, Input High Voltage 2.4 V VDD = 5 V ± 10%
Pin Capacitance 3.5 pF
V
DD
IDD (Normal Mode) All DACs active and excluding load currents.
VDD = 4.5 V to 5.5 V 600 900 µAV
VDD = 2.5 V to 3.6 V 500 700 µAI
IDD (Power-Down Mode)
VDD = 4.5 V to 5.5 V 0.2 1 µA
VDD = 2.5 V to 3.6 V 0.08 1 µA
= 2 V. RL = 2 k⍀ to GND; CL =200 pF to GND; all specifications T
REF
B Version
2
Min Typ Max Unit Conditions/Comments
3, 4
5
6
6
10 60 mV Lower Deadband Exists Only if Offset Error Is Negative
–12 ppm of FSR/°C
–5 ppm of FSR/°C
–60 dB ∆VDD = ±10%
200 µVR
6
DD
V
90 kΩ Gain = 2. Input Impedance = R
90 kΩ Gain = 1. Input Impedance = R
45 kΩ Gain = 2. Input Impedance = R
6
4, 7
4, 7
0.001 V min Rail-to-Rail Operation
VDD – 0.001 V max
20 mA VDD = 3 V
5 µs Coming Out of Power-Down Mode. VDD = 3 V
0.6 V VDD = 3 V ± 10%
0.5 V VDD = 2.5 V
2.1 V VDD = 3 V ± 10%
2.0 V VDD = 2.5 V
2.5 5.5 V
to T
MIN
= 2 kΩ to GND, 2 kΩ to VDD; CL = 200 pF to GND;
L
unless otherwise noted.)
MAX
Gain = 0
(AD5336/AD5344)
DAC
(AD5336)
DAC
(AD5334/AD5335)
DAC
(AD5334)
DAC
= 5 V ± 10%
DD
= VDD, V
IH
increases by 50 µA at V
DD
= GND.
IL
> VDD – 100 mV.
REF
REF = VDD
= VDD and
REF
–2–
REV. 0
AD5334/AD5335/AD5336/AD5344
(VDD = 2.5 V to 5.5 V. RL = 2 k⍀ to GND; CL = 200 pF to GND. All specifications T
AC CHARACTERISTICS
Parameter
2
1
wise noted.)
B Version
3
Min Typ Max Unit Conditions/Comments
Output Voltage Settling Time V
= 2 V. See Figure 20
REF
MIN
to T
MAX
unless other-
AD5334 6 8 µs 1/4 Scale to 3/4 Scale Change (40 H to C0 H)
AD5335 7 9 µs 1/4 Scale to 3/4 Scale Change (100 H to 300 H)
AD5336 7 9 µs 1/4 Scale to 3/4 Scale Change (100 H to 300 H)
AD5344 8 10 µs 1/4 Scale to 3/4 Scale Change (400 H to C00 H)
Slew Rate 0.7 V/µs
Major Code Transition Glitch Energy 8 nV-s 1 LSB Change Around Major Carry
Digital Feedthrough 0.5 nV-s
Digital Crosstalk 3 nV-s
Analog Crosstalk 0.5 nV-s
DAC-to-DAC Crosstalk 3.5 nV-s
Multiplying Bandwidth 200 kHz V
Total Harmonic Distortion –70 dB V
NOTES
1
Guaranteed by design and characterization, not production tested.
2
See Terminology section.
3
Temperature range: B Version: –40°C to +105°C; typical specifications are at 25°C.
Specifications subject to change without notice.
1, 2, 3
TIMING CHARACTERISTICS
Parameter Limit at T
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
t
14
t
15
NOTES
1
Guaranteed by design and characterization, not production tested.
2
All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD)
and timed from a voltage level of (VIL + VIH)/2.
3
See Figure 1.
Specifications subject to change without notice.
0 ns min CS to WR Setup Time
0 ns min CS to WR Hold Time
20 ns min WR Pulsewidth
5 ns min Data, GAIN, HBEN Setup Time
4.5 ns min Data, GAIN, HBEN Hold Time
5 ns min Synchronous Mode. WR Falling to LDAC Falling.
5 ns min Synchronous Mode. LDAC Falling to WR Rising.
4.5 ns min Synchronous Mode. WR Rising to LDAC Rising.
5 ns min Asynchronous Mode. LDAC Rising to WR Rising.
4.5 ns min Asynchronous Mode. WR Rising to LDAC Falling.
20 ns min LDAC Pulsewidth
20 ns min CLR Pulsewidth
50 ns min Time Between WR Cycles
20 ns min A0, A1 Setup Time
0 ns min A0, A1 Hold Time
MIN
, T
(VDD = 2.5 V to 5.5 V, All specifications T
MAX
Unit Condition/Comments
DATA,
GAIN,
HBEN
LDAC
LDAC
CS
WR
1
2
CLR
A0,
A1
NOTES:
1
SYNCHRONOUS LDAC UPDATE MODE
2
ASYNCHRONOUS LDAC UPDATE MODE
= 2 V ± 0.1 V p-p. Unbuffered Mode
REF
= 2.5 V ± 0.1 V p-p. Frequency = 10 kHz
REF
to T
MIN
t
unless otherwise noted.)
MAX
1
t
3
t
4
t
6
t
7
t
9
t
14
t
2
t
13
t
5
t
8
t
10
t
15
t
11
t
12
Figure 1. Parallel Interface Timing Diagram
REV. 0
–3–
AD5334/AD5335/AD5336/AD5344
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS*
(TA = 25°C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Digital Input Voltage to GND . . . . . . . .–0.3 V to V
Digital Output Voltage to GND . . . . . .–0.3 V to V
Reference Input Voltage to GND . . . . –0.3 V to V
V
to GND . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
OUT
+ 0.3 V
DD
+ 0.3 V
DD
+ 0.3 V
DD
Operating Temperature Range
Reflow Soldering
Peak Temperature . . . . . . . . . . . . . . . . . . . . . . 220 +5/–0°C
Time at Peak Temperature . . . . . . . . . . . . .10 sec to 40 sec
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +105°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
TSSOP Package
Power Dissipation . . . . . . . . . . . . . . . (T
θ
Thermal Impedance (24-Lead TSSOP) . . . . . 128°C/W
JA
Thermal Impedance (28-Lead TSSOP) . . . . . 97.9°C/W
θ
JA
θ
Thermal Impedance (24-Lead TSSOP) . . . . . . 42°C/W
JC
θ
Thermal Impedance (28-Lead TSSOP) . . . . . . 14°C/W
JC
max – TA)/θJA mW
J
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD5334BRU –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-24
AD5335BRU –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-24
AD5336BRU –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-28
AD5344BRU –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-28
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5334/AD5335/AD5336/AD5344 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
–4–
REV. 0
AD5334/AD5335/AD5336/AD5344
GAIN
DB
DB
CS
WR
A0
A1
CLR
LDAC
AD5334 FUNCTIONAL BLOCK DIAGRAM
V
A/B
REF
POWER-ON
RESET
7
.
.
.
0
INTER-
FACE
LOGIC
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
8-BIT
DAC
8-BIT
DAC
8-BIT
DAC
8-BIT
DAC
8-BIT
DAC
BUFFER
BUFFER
BUFFER
BUFFER
V
C/D
REF
V
DD
AD5334
TO ALL DACS
AND BUFFERS
POWER-DOWN
LOGIC
PD
GND
V
A
OUT
V
B
OUT
C
V
OUT
D
V
OUT
AD5334 PIN CONFIGURATION
8-BIT
24
CLR
23
GAIN
22
DB
7
21
DB
6
20
DB
5
19
DB
4
18
DB
3
17
DB
2
16
DB
1
15
DB
0
14
V
DD
13
PD
V
V
REF
REF
V
OUT
V
OUT
V
OUT
V
OUT
LDAC
C/D
A/B
GND
CS
WR
A
B
C
D
A0
A1
1
2
3
4
5
AD5334
6
TOP VIEW
(Not to Scale)
7
8
9
10
11
12
AD5334 PIN FUNCTION DESCRIPTIONS
Pin
No. Mnemonic Function
1V
2V
3V
4V
5V
6V
C/D Unbuffered Reference Input for DACs C and D.
REF
A/B Unbuffered Reference Input for DACs A and B.
REF
A Output of DAC A. Buffered Output with Rail-to-Rail Operation.
OUT
B Output of DAC B. Buffered Output with Rail-to-Rail Operation.
OUT
C Output of DAC C. Buffered Output with Rail-to-Rail Operation.
OUT
D Output of DAC D. Buffered Output with Rail-to-Rail Operation.
OUT
7 GND Ground Reference Point for All Circuitry on the Part.
8 CS Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
9 WR Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.
10 A0 LSB Address Pin for Selecting which DAC Is to Be Written to.
11 A1 MSB Address Pin for Selecting which DAC Is to Be Written to.
12 LDAC Active Low Control Input that Updates the DAC Registers with the Contents of the Input Registers.
This allows all DAC outputs to be simultaneously updated.
13 PD Power-Down Pin. This active low control pin puts all DACs into power-down mode.
14 V
DD
Power Supply Pin. This part can operate from 2.5 V to 5.5 V and the supply should be decoupled with a
10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
15–22 DB
23 GAIN Gain Control Pin. This controls whether the output range from the DAC is 0–V
–DB
0
7
Eight Parallel Data Inputs. DB7 is the MSB of these eight bits.
or 0–2 V
REF
REF
24 CLR Asynchronous Active Low Control Input that Clears All Input Registers and DAC Registers to Zeros.
REV. 0
–5–
AD5334/AD5335/AD5336/AD5344
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
AD5335
LDAC
A1
A0
WR
CS
V
REF
C/D
V
REF
A/B
V
OUT
A
V
OUT
B
GND
V
OUT
D
V
OUT
C
PD
V
DD
DB
0
DB
1
DB
2
CLR
HBEN
DB
7
DB
6
DB
3
DB
4
DB
5
10-BIT
DB
DB
CS
WR
A0
A1
HBEN
CLR
LDAC
AD5335 FUNCTIONAL BLOCK DIAGRAM
V
A/B
REF
POWER-ON
RESET
HIGH BYTE
REGISTER
7
.
.
.
.
.
.
0
INTER-
FACE
LOGIC
RESET
LOW BYTE
REGISTER
HIGH BYTE
REGISTER
LOW BYTE
REGISTER
HIGH BYTE
REGISTER
LOW BYTE
REGISTER
HIGH BYTE
REGISTER
LOW BYTE
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
10-BIT
DAC
10-BIT
DAC
10-BIT
DAC
10-BIT
DAC
BUFFER
BUFFER
BUFFER
BUFFER
AND BUFFERS
V
AD5335
TO ALL DACS
POWER-DOWN
DD
LOGIC
V
OUT
V
OUT
V
OUT
V
OUT
AD5335 PIN CONFIGURATION
A
B
C
D
V
REF
C/D
PD
GND
AD5335 PIN FUNCTION DESCRIPTIONS
Pin
No. Mnemonic Function
1V
2V
3V
4V
5V
6V
C/D Unbuffered Reference Input for DACs C and D.
REF
A/B Unbuffered Reference Input for DACs A and B.
REF
A Output of DAC A. Buffered output with rail-to-rail operation.
OUT
B Output of DAC B. Buffered output with rail-to-rail operation.
OUT
C Output of DAC C. Buffered output with rail-to-rail operation.
OUT
D Output of DAC D. Buffered output with rail-to-rail operation.
OUT
7 GND Ground Reference Point for All Circuitry on the Part.
8 CS Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
9 WR Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.
10 A0 LSB Address Pin for Selecting which DAC Is to Be Written to.
11 A1 MSB Address Pin for Selecting which DAC Is to Be Written to.
12 LDAC Active Low Control Input that Updates the DAC Registers with the Contents of the Input Registers.
13 PD Power-Down Pin. This active low control pin puts all DACs into power-down mode.
14 V
15–22 DB
23 HBEN This pin is used when writing to the device to determine if data is written to the high byte register or the
24 CLR Asynchronous Active Low Control Input that Clears All Input Registers and DAC Registers to Zeros.
DD
–DB
0
7
This allows all DAC outputs to be simultaneously updated.
Power Supply Pin. This part can operate from 2.5 V to 5.5 V and the supply should be decoupled with a
10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
Eight Parallel Data Inputs. DB7 is the MSB of these eight bits.
low byte register.
–6–
REV. 0
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