Analog Devices AD5325, AD5315, AD5305 Datasheet
2.5 V to 5.5 V, 500 A, 2-Wire Interface
a
Quad Voltage Output, 8-/10-/12-Bit DACs
FEATURES
AD5305
Four Buffered 8-Bit DACs in 10-Lead microSOIC
AD5315
Four Buffered 10-Bit DACs in 10-Lead microSOIC
AD5325
Four Buffered 12-Bit DACs in 10-Lead microSOIC
Low Power Operation: 500 A @ 3 V, 600 A @ 5 V
2-Wire (I
2C®
-Compatible) Serial Interface
2.5 V to 5.5 V Power Supply
Guaranteed Monotonic By Design Over All Codes
Power-Down to 80 nA @ 3 V, 200 nA @ 5 V
Double-Buffered Input Logic
Output Range: 0–V
REF
Power-On-Reset to Zero Volts
Simultaneous Update of Outputs (LDAC Function)
Software Clear Facility
Data Readback Facility
On-Chip Rail-to-Rail Output Buffer Amplifiers
ⴗ
Temperature Range –40
C to +105ⴗC
APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
Industrial Process Control
AD5305/AD5315/AD5325*
GENERAL DESCRIPTION
The AD5305/AD5315/AD5325 are quad 8-, 10- and 12-bit
buffered voltage output DACs in a 10-lead microSOIC package
that operate from a single 2.5 V to 5.5 V supply consuming
500 µA at 3 V. Their on-chip output amplifiers allow rail-to-rail
output swing with a slew rate of 0.7 V/µs. A 2-wire serial interface is used which operates at clock rates up to 400 kHz. This
interface is SMBus-compatible at V
can be placed on the same bus.
The references for the four DACs are derived from one reference
pin. The outputs of all DACs may be updated simultaneously
using the software LDAC function. The parts incorporate a
power-on-reset circuit that ensures that the DAC outputs power
up to zero volts and remain there until a valid write takes place
to the device. There is also a software clear function which resets
all input and DAC registers to 0 V. The parts contain a powerdown feature that reduces the current consumption of the devices
to 200 nA @ 5 V (80 nA @ 3 V).
The low power consumption of these parts in normal operation
makes them ideally suited to portable battery-operated equipment. The power consumption is 3 mW at 5 V, 1.5 mW at 3 V,
reducing to 1 µW in power-down mode.
FUNCTIONAL BLOCK DIAGRAM
V
DD
REF IN
< 3.6 V. Multiple devices
DD
LDAC
INPUT
REGISTER
SCL
SDA
A0
*Protected by U.S. Patent No. 5,969,657; other patents pending.
I2C is a registered trademark of Philips Corporation.
INTERFACE
LOGIC
POWER-ON
RESET
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
AD5305/AD5315/AD5325
GND
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2000
STRING
DAC A
STRING
DAC B
STRING
DAC C
STRING
DAC D
BUFFER
POWER-DOWN
LOGIC
A
V
OUT
BBUFFER
V
OUT
V
CBUFFER
OUT
V
DBUFFER
OUT
AD5305/AD5315/AD5325–SPECIFICATIONS
GND; CL = 200 pF to GND; All specifications T
Parameter
1
DC PERFORMANCE
3, 4
B Version
Min Typ Max Unit Conditions/Comments
MIN
to T
unless otherwise noted.)
MAX
2
(VDD = 2.5 V to 5.5 V; V
= 2 V; RL = 2 k⍀ to
REF
AD5305
Resolution 8 Bits
Relative Accuracy ± 0.15 ± 1 LSB
Differential Nonlinearity ± 0.02 ± 0.25 LSB Guaranteed Monotonic by Design Over All Codes
AD5315
Resolution 10 Bits
Relative Accuracy ± 0.5 ± 4 LSB
Differential Nonlinearity ± 0.05 ± 0.5 LSB Guaranteed Monotonic by Design Over All Codes
AD5325
Resolution 12 Bits
Relative Accuracy ± 2 ± 16 LSB
Differential Nonlinearity ± 0.2 ± 1 LSB Guaranteed Monotonic by Design Over All Codes
Offset Error ± 0.4 ± 3 % of FSR
Gain Error ± 0.15 ± 1 % of FSR
Lower Deadband 20 60 mV Lower Deadband Exists Only If Offset Error Is Negative
Offset Error Drift
Gain Error Drift
Power Supply Rejection Ratio
DC Crosstalk
DAC REFERENCE INPUTS
V
Input Range 0.25 V
REF
V
Input Impedance 37 45 kΩ Normal Operation
REF
5
5
5
5
5
–12 ppm of FSR/°C
–5 ppm of FSR/°C
–60 dB ∆VDD = ±10%
200 µVR
DD
V
= 2 k⍀ to GND or V
L
DD
>10 MΩ Power-Down Mode
Reference Feedthrough –90 dB Frequency = 10 kHz
OUTPUT CHARACTERISTICS
Minimum Output Voltage
Maximum Output Voltage
5
6
6
0.001 V This is a measure of the minimum and maximum drive
VDD – 0.001 V capability of the output amplifier.
DC Output Impedance 0.5 Ω
Short Circuit Current 25 mA VDD = 5 V
16 mA VDD = 3 V
Power-Up Time 2.5 µs Coming Out of Power-Down Mode. VDD = 5 V
5 µs Coming Out of Power-Down Mode. VDD = 3 V
LOGIC INPUTS (A0)
5
Input Current ± 1 µA
VIL, Input Low Voltage 0.8 V VDD = 5 V ± 10%
0.6 V VDD = 3 V ± 10%
0.5 V VDD = 2.5 V
VIH, Input High Voltage 2.4 V VDD = 5 V ± 10%
2.1 V VDD = 3 V ± 10%
2.0 V VDD = 2.5 V
Pin Capacitance 3 pF
LOGIC INPUTS (SCL, SDA)
VIH, Input High Voltage 0.7 V
VIL, Input Low Voltage –0.3 0.3 V
5
DD
VDD+ 0.3 V SMBus-Compatible at VDD < 3.6 V
V SMBus-Compatible at VDD < 3.6 V
DD
IIN, Input Leakage Current ± 1 µA
V
, Input Hysteresis 0.05 V
HYST
DD
V
CIN, Input Capacitance 8 pF
Glitch Rejection 50 ns Input filtering suppresses noise spikes of less than 50 ns.
LOGIC OUTPUT (SDA)
VOL, Output Low Voltage 0.4 V I
5
= 3 mA
0.6 V I
SINK
SINK
= 6 mA
Three-State Leakage Current ± 1 µA
Three-State Output Capacitance 8 pF
POWER REQUIREMENTS
V
DD
IDD (Normal Mode)
7
2.5 5.5 V
VIH = VDD and VIL = GND
VDD = 4.5 V to 5.5 V 600 900 µA
VDD = 2.5 V to 3.6 V 500 700 µA
IDD (Power-Down Mode) VIH = VDD and VIL = GND,
VDD = 4.5 V to 5.5 V 0.2 1 µAI
VDD = 2.5 V to 3.6 V 0.08 1 µAI
= 4 µA (Max) During “0” Readback on SDA
DD
= 1.5 µA (Max) During “0” Readback on SDA
DD
–2–
REV. B
AD5305/AD5315/AD5325
NOTES
1
See Terminology.
2
Temperature range: B Version: –40°C to +105°C; typical at 25°C.
3
DC specifications tested with the outputs unloaded.
4
Linearity is tested using a reduced code range: AD5305 (Code 8 to 248); AD5315 (Code 28 to 995); AD5325 (Code 115 to 3981).
5
Guaranteed by design and characterization, not production tested.
6
For the amplifier output to reach its minimum voltage, Offset Error must be negative; to reach its maximum voltage, V
7
IDD specification is valid for all DAC codes. Interface inactive. All DACs active and excluding load currents.
Specifications subject to change without notice.
= VDD and “Offset plus Gain” Error must be positive.
REF
(VDD = 2.5 V to 5.5 V; RL = 2 k⍀ to GND; CL = 200 pF to GND; all specifications T
AC CHARACTERISTICS
Parameter
Output Voltage Settling Time V
2
1
otherwise noted.)
B Version
Min Typ Max Unit Conditions/Comments
3
= VDD = 5 V
REF
AD5305 6 8 µs 1/4 Scale to 3/4 Scale
AD5315 7 9 µs 1/4 Scale to 3/4 Scale
AD5325 8 10 µs 1/4 Scale to 3/4 Scale
Change
Change
Change
to T
MIN
(40 Hex to C0 Hex)
(100 Hex to 300 Hex)
(400 Hex to C00 Hex)
Slew Rate 0.7 V/µs
Major-Code Transition Glitch Energy 12 nV-s 1 LSB Change Around Major Carry
Digital Feedthrough 1 nV-s
Digital Crosstalk 1 nV-s
DAC-to-DAC Crosstalk 3 nV-s
Multiplying Bandwidth 200 kHz V
Total Harmonic Distortion –70 dB V
NOTES
1
Guaranteed by design and characterization, not production tested.
2
See Terminology.
3
Temperature range: B Version: –40°C to +105°C
Specifications subject to change without notice.
TIMING CHARACTERISTICS
Limit at T
MIN
, T
MAX
; typical at 25°C.
1, 2
(VDD = 2.5 V to 5.5 V. All specifications T
= 2 V ± 0.1 V p-p
REF
= 2.5 V ± 0.1 V p-p. Frequency = 10 kHz
REF
to T
MIN
unless otherwise noted)
MAX
Parameter (B Version) Unit Conditions/Comments
F
SCL
t
1
t
2
t
3
t
4
t
5
3
t
6
t
7
t
8
t
9
t
10
t
11
C
B
NOTES
1
See Figure 1.
2
Guaranteed by design and characterization, not production tested.
3
CB is the total capacitance of one bus line in pF. tR and tF measured between 0.3 VDD and 0.7 VDD.
Specifications subject to change without notice.
400 kHz max SCL Clock Frequency
2.5 µs min SCL Cycle Time
0.6 µs min t
1.3 µs min t
0.6 µs min t
100 ns min t
0.9 µs max t
0 µs min t
0.6 µs min t
0.6 µs min t
1.3 µs min t
, SCL High Time
HIGH
, SCL Low Time
LOW
, Start/Repeated Start Condition Hold Time
HD,STA
, Data Setup Time
SU,DAT
, Data Hold Time
HD,DAT
, Data Hold Time
HD,DAT
, Setup Time for Repeated Start
SU,STA
, Stop Condition Setup Time
SU,STO
, Bus Free Time Between a STOP and a START Condition
BUF
300 ns max tR, Rise Time of SCL and SDA when Receiving
0 ns min t
, Rise Time of SCL and SDA when Receiving (CMOS-Compatible)
R
250 ns max tF, Fall Time of SDA when Transmitting
0 ns min t
300 ns max t
20 + 0.1C
3
B
ns min tF, Fall Time of SCL and SDA when Transmitting
, Fall Time of SDA when Receiving (CMOS-Compatible)
F
, Fall Time of SCL and SDA when Receiving
F
400 pF max Capacitive Load for Each Bus Line
MAX
unless
REV. B
–3–
AD5305/AD5315/AD5325
WARNING!
ESD SENSITIVE DEVICE
SDA
SCL
t
9
START
CONDITION
t
3
t
4
t
10
t
6
t
2
Figure 1. Two-Wire Serial Interface Timing Diagram
ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)
1, 2
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
SCL, SDA to GND . . . . . . . . . . . . . . . .–0.3 V to V
A0 to GND . . . . . . . . . . . . . . . . . . . . . .–0.3 V to V
Reference Input Voltage to GND . . . . –0.3 V to V
A–D to GND . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
V
OUT
+ 0.3 V
DD
+ 0.3 V
DD
+ 0.3 V
DD
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +105°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (T
max) . . . . . . . . . . . . . . . . . . . 150°C
J
t
11
t
5
t
7
REPEATED
START
CONDITION
t
4
t
1
t
8
STOP
CONDITION
microSOIC Package
Power Dissipation . . . . . . . . . . . . . . . . . . (T
max – TA)/θ
J
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 206°C/W
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 44°C/W
θ
JC
Reflow Soldering
Peak Temperature . . . . . . . . . . . . . . . . . . . . . . 220 +5/–0°C
Time at Peak Temperature . . . . . . . . . . . . 10 sec to 40 sec
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; and functional operation
of the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Transient currents of up to 100 mA will not cause SCR latch-up.
JA
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5305/AD5315/AD5325 features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
Temperature Package Package Branding
Model Range Description Option Information
AD5305BRM –40°C to +105°C 10-Lead microSOIC RM-10 DEB
AD5315BRM –40°C to +105°C 10-Lead microSOIC RM-10 DFB
AD5325BRM –40°C to +105°C 10-Lead microSOIC RM-10 DGB
–4–
REV. B
AD5305/AD5315/AD5325
PIN CONFIGURATION
V
1
DD
A
2
B
3
C
4
5
AD5305/
AD5315/
AD5325
TOP VIEW
(Not to Scale)
V
OUT
V
OUT
V
OUT
REFIN
PIN FUNCTION DESCRIPTIONS
Pin
No. Mnemonic Function
1V
DD
Power Supply Input. These parts can be operated from 2.5 V to 5.5 V and the supply should be
decoupled to GND.
2V
3V
4V
A Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
OUT
B Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
OUT
C Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
OUT
5 REFIN Reference Input Pin for All Four DACs. It has an input range from 0.25 V to V
6V
D Buffered analog output voltage from DAC D. The output amplifier has rail-to-rail operation.
OUT
7 GND Ground Reference Point for All Circuitry on the Part.
8 SDA Serial Data Line. This is used in conjunction with the SCL line to clock data into or out of the 16-bit
input shift register. It is a bidirectional open-drain data line that should be pulled to the supply with
an external pull-up resistor.
9 SCL Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 16-bit
input shift register. Clock rates of up to 400 kbit/s can be accommodated in the 2-wire interface.
10 A0 Address Input. Sets the least significant bit of the 7-bit slave address.
A0
10
SCL
9
SDA
8
GND
7
6
V
D
OUT
.
DD
TERMINOLOGY
RELATIVE ACCURACY
For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer function.
Typical INL versus Code plots can be seen in Figures 4, 5, and 6.
DIFFERENTIAL NONLINEARITY
Differential Nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of ±1 LSB
maximum ensures monotonicity. This DAC is guaranteed monotonic by design. Typical DNL versus Code plots can be seen in
Figures 7, 8, and 9.
OFFSET ERROR
This is a measure of the offset error of the DAC and the output
amplifier. It is expressed as a percentage of the full-scale range.
GAIN ERROR
This is a measure of the span error of the DAC. It is the deviation in slope of the actual DAC transfer characteristic from the
ideal expressed as a percentage of the full-scale range.
OFFSET ERROR DRIFT
This is a measure of the change in offset error with changes
in temperature. It is expressed in (ppm of full-scale range)/°C.
GAIN ERROR DRIFT
This is a measure of the change in gain error with changes
in temperature. It is expressed in (ppm of full-scale range)/°C.
POWER-SUPPLY REJECTION RATIO (PSRR)
This indicates how the output of the DAC is affected by
changes in the supply voltage. PSRR is the ratio of the change
in V
to a change in VDD for full-scale output of the DAC. It is
OUT
measured in dBs. V
is held at 2 V and VDD is varied ± 10%.
REF
DC CROSSTALK
This is the dc change in the output level of one DAC at midscale in response to a full-scale code change (all 0s to all 1s
and vice versa) and output change of another DAC. It is
expressed in µV.
REFERENCE FEEDTHROUGH
This is the ratio of the amplitude of the signal at the DAC
output to the reference input when the DAC output is not
being updated. It is expressed in dBs.
REV. B
–5–
AD5305/AD5315/AD5325
MAJOR-CODE TRANSITION GLITCH ENERGY
Major-code transition glitch energy is the energy of the impulse
injected into the analog output when the code in the DAC
register changes state. It is normally specified as the area of the
glitch in nV-secs and is measured when the digital code is changed
by 1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00
or 100 . . . 00 to 011 . . . 11).
DIGITAL FEEDTHROUGH
Digital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital input pins of the
device when the DAC output is not being updated. It is specified
in nV-secs and is measured with a worst-case change on the
digital input pins, e.g., from all 0s to all 1s or vice versa.
DIGITAL CROSSTALK
This is the glitch impulse transferred to the output of one DAC
at midscale in response to a full-scale code change (all 0s to all
1s and vice versa) in the input register of another DAC. It is
expressed in nV-secs.
DAC-TO-DAC CROSSTALK
This is the glitch impulse transferred to the output of one DAC
due to a digital code change and subsequent output change of
another DAC. This includes both digital and analog crosstalk. It
is measured by loading one of the DACs with a full-scale code
change (all 0s to all 1s and vice versa) with the LDAC bit set low
and monitoring the output of another DAC. The energy of the
glitch is expressed in nV-secs.
GAIN ERROR
PLUS
OFFSET ERROR
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
ERROR
AMPLIFIER
FOOTROOM
(1mV)
NEGATIVE
OFFSET
ERROR
IDEAL
ACTUAL
DAC CODE
DEADBAND CODES
Figure 2. Transfer Function with Negative Offset
MULTIPLYING BANDWIDTH
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at which
the output amplitude falls to 3 dB below the input.
TOTAL HARMONIC DISTORTION
This is the difference between an ideal sine wave and its attenuated
version using the DAC. The sine wave is used as the reference
for the DAC and the THD is a measure of the harmonics present
on the DAC output. It is measured in dBs.
GAIN ERROR
PLUS
OFFSET ERROR
OUTPUT
VOLTAGE
POSITIVE
OFFSET
ACTUAL
IDEAL
DAC CODE
Figure 3. Transfer Function with Positive Offset
–6–
REV. B
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