ANALOG DEVICES AD5320 Service Manual

2.7 V to 5.5 V, 140 μA, Rail-to-Rail Output

T

FEATURES

Single 12-bit DAC
6-lead SOT-23 and 8-lead MSOP packages
Micropower operation: 140 μA @ 5 V
Power-down to 200 nA @ 5 V, 50 nA @ 3 V

2.7 V to 5.5 V power supply
Guaranteed monotonic by design
Reference derived from power supply
Power-on reset to zero volts
Three power-down functions
Low power serial interface with Schmitt-triggered inputs
On-chip output buffer amplifier, rail-to-rail operation

interrupt facility

SYNC

APPLICATIONS

Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators

GENERAL DESCRIPTION

The AD53201 is a single, 12-bit buffered voltage out digital-to­analog converter (DAC) that operates from a single 2.7 V to

5.5 V supply consuming 115 μA at 3 V. Its on-chip precision
output amplifier allows rail-to-rail output swing to be achieved.
The AD5320 utilizes a versatile 3-wire serial interface that
operates at clock rates up to 30 MHz and is compatible with
standard SPI®, QSPI™, MICROWIRE™ and digital signal
processing (DSP) interface standards.

The reference for AD5320 is derived from the power supply
inputs and thus gives the widest dynamic output range. The
part incorporates a power-on reset circuit that ensures that the
DAC output powers up to zero volts and remains there until a
valid write takes place to the device. The part contains a power­down feature that reduces the current consumption of the
device to 200 nA at 5 V and provides software selectable output
loads while in power-down mode. The part is put into power­down mode over the serial interface.

The low power consumption of this part in normal operation
makes it ideally suited to portable, battery-operated equipment.
The power consumption is 0.7 mW at 5 V reducing to 1 μW in
power-down mode.

1

Patent pending; protected by U.S. Patent No. 5684481.

12-Bit DAC in an SOT-23

AD5320

FUNCTIONAL BLOCK DIAGRAM

V

DD

GND

OUTPUT
BUFFER

AD5320

REGISTER
NETWORK

V

00934-001

POWER-ON

RESET

REF (+) REF (–)

12-BIT

DAC

POWER-DOWN

CONTROL LOG IC

Figure 1.

SYNC

DAC

REGISTER

INPUT

CONTRO L

LOGIC

SCLK DIN

The AD5320 is one of a family of pin-compatible DACs. The
AD5300 is the 8-bit version and the AD5310 is the 10-bit
version. The AD5300/AD5310/AD5320 are available in 6-lead
SOT-23 packages and 8-lead MSOP packages.

PRODUCT HIGHLIGHTS

1. Available in 6-lead SOT-23 and 8-lead MSOP packages.

2. Low power, single-supply operation. This part operates

from a single 2.7 V to 5.5 V supply and typically consumes

0.35 mW at 3 V and 0.7 mW at 5 V, making it ideal for
battery-powered applications.

3. The on-chip output buffer amplifier allows the output of

the DAC to swing rail-to-rail with a slew rate of 1 V/μs.

4. Reference derived from the power supply.

5. High speed serial interface with clock speeds up to

30 MHz. Designed for very low power consumption. The
interface only powers up during a write cycle.

6. Power-down capability. When powered down, the DAC

typically consumes 50 nA at 3 V and 200 nA at 5 V.

OU

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

AD5320

TABLE OF CONTENTS

Features.............................................................................................. 1

Serial Interface ................................................................................ 12

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Characteristics ................................................................ 4

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configurations and Function Descriptions ........................... 6

Terminology ...................................................................................... 7

Typical Performance Characteristics ............................................. 8

Theory of Operation ...................................................................... 11

D/A Section................................................................................. 11

Resistor String............................................................................. 11

Input Shift Register .................................................................... 12

SYNC

Interrupt .......................................................................... 12

Power-On Reset.......................................................................... 12

Power-Down Modes .................................................................. 13

Microprocessor Interfacing........................................................... 14

AD5320 to ADSP-2101/ADSP-2103 Interface ....................... 14

AD5320 to 68HC11/68L11 Interface....................................... 14

AD5320 to 80C51/80L51 Interface.......................................... 14

AD5320 to MICROWIRE Interface......................................... 14

Applications..................................................................................... 15

Using REF19x as a Power Supply for AD5320 ....................... 15

Bipolar Operation Using the AD5320..................................... 15

Using AD5320 with an Opto-Isolated Interface .................... 15

Power Supply Bypassing and Grounding................................ 16

Outline Dimensions....................................................................... 17

Output Amplifier........................................................................ 11

REVISION HISTORY

11/05—Rev. B to Rev. C

Updated Format..................................................................Universal

Changes to Table 4............................................................................ 6

Updated Outline Dimensions....................................................... 17

Changes to Ordering Guide.......................................................... 17

Ordering Guide .......................................................................... 17

Rev. C | Page 2 of 20

AD5320

SPECIFICATIONS

VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications T

Table 1.

B Version

1

Parameter Min Typ Max Unit Test Conditions/Comments

STATIC PERFORMANCE

2

Resolution 12 Bits
Relative Accuracy ±16 LSB See Figure 5
Differential Nonlinearity ±1 LSB Guaranteed monotonic by design (see Figure 6)
Zero-Code Error 5 40 mV All zeroes loaded to DAC register (see Figure 9)
Full-Scale Error −0.15 −1.25 % of FSR All ones loaded to DAC register (see Figure 9)
Gain Error ±1.25 % of FSR
Zero-Code Error Drift −20 μV/°C
Gain Temperature Coefficient −5 ppm of FSR/°C

OUTPUT CHARACTERISTICS

3

Output Voltage Range 0 VDD V
Output Voltage Settling Time 8 10 μs

12 μs RL = 2 kΩ, CL = 500 pF
Slew Rate 1 V/μs
Capacitive Load Stability 470 pF RL = ∞
1000 pF RL = 2 kΩ
Digital-to-Analog Glitch Impulse 20 nV-s 1 LSB change around major carry (see Figure 22)
Digital Feedthrough 0.5 nV-s
DC Output Impedance 1 Ω
Short Circuit Current 50 mA VDD = 5 V
20 mA VDD = 3 V
Power-Up Time 2.5 μs Coming out of power-down mode, VDD = 5 V
5 μs Coming out of power-down mode, VDD = 3 V

LOGIC INPUTS

3

Input Current ±1 μA
V

, Input Low Voltage 0.8 V VDD = 5 V

INL

V

, Input Low Voltage 0.6 V VDD = 3 V

INL

V

, Input High Voltage 2.4 V VDD = 5 V

INH

V

, Input High Voltage 2.1 V VDD = 3 V

INH

Pin Capacitance 3 pF

POWER REQUIREMENTS

VDD 2.7 5.5 V
IDD (Normal Mode) DAC active and excluding load current

VDD = 4.5 V to 5.5 V 140 250 μA VIH = VDD and VIL = GND
VDD = 2.7 V to 3.6 V 115 200 μA VIH = VDD and VIL = GND

IDD (All Power-Down Modes)

VDD = 4.5 V to 5.5 V 0.2 1 μA VIH = VDD and VIL = GND
VDD = 2.7 V to 3.6 V 0.05 1 μA VIH = VDD and VIL = GND

POWER EFFICIENCY

I

93 % I

OUT/IDD

1

Temperature range is as follows: B Version: −40°C to +105°C.

2

Linearity calculated using a reduced code range of 48 to 4047; output unloaded.

3

Guaranteed by design and characterization, not production tested.

MIN

to T

, unless otherwise noted.

MAX

1/4 scale to 3/4 scale change (400 hex to C00 hex)

= 2 kΩ, 0 pF < CL < 200 pF (see Figure 19)

R

L

= 2 mA, VDD = 5 V

LOAD

Rev. C | Page 3 of 20

AD5320

TIMING CHARACTERISTICS

VDD = 2.7 V to 5.5 V, all specifications T

Table 2.

Limit at T
Parameter

3

t

1

1, 2

VDD = 2.7 V to 3.6 V VDD = 3.6 V to 5.5 V Unit Description

50 33 ns min SCLK cycle time
t2 13 13 ns min SCLK high time
t3 22.5 13 ns min SCLK low time
t4 0 0 ns min

t5 5 5 ns min Data setup time
t6 4.5 4.5 ns min Data hold time
t7 0 0 ns min
t8 50 33 ns min

1

All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

2

See Figure 2.

3

Maximum SCLK frequency is 30 MHz at VDD = 3.6 V to 5.5 V and 20 MHz at VDD = 2.7 V to 3.6 V.

SCLK

t

8

SYNC

DIN

MIN

t

4

DB15

to T

t

, unless otherwise noted.

MAX

, T

MIN

5

MAX

t

1

t

t

3

t

6

2

DB0

SYNC to SCLK rising edge setup time

SCLK falling edge to
Minimum

t

7

SYNC high time

SYNC rising edge

00934-002

Figure 2. Serial Write Operation

Rev. C | Page 4 of 20

AD5320

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Ratings

VDD to GND −0.3 V to +7 V
Digital Input Voltage to GND −0.3 V to VDD + 0.3 V
V

to GND −0.3 V to VDD + 0.3 V

OUT

Operating Temperature Range

Industrial (B Version) −40°C to +105°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ Max) 150°C
SOT-23 Package

Power Dissipation (TJ Max − TA)/θJA

θJA Thermal Impedance 240°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C

MSOP Package 450 mW

Power Dissipation (TJ Max − TA)/θJA

θJA Thermal Impedance 206°C/W

θJC Thermal Impedance 44°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. C | Page 5 of 20

AD5320

V

V

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

SYNC

OUT

GND

V

DD

1

AD5320

2

TOP VIEW

3

(Not to Scale)

6

5

4

SCLK

DIN

00934-003

Figure 3. SOT-23 Pin Configuration

Table 4. Pin Function Descriptions

SOT-23
Pin No.

1 4 V

MSOP
Pin No. Mnemonic Description

Analog Output Voltage from DAC. The output amplifier has rail-to-rail operation.

OUT

2 8 GND Ground Reference Point for All Circuitry on the Part.
3 1 VDD

Power Supply Input. These parts can be operated from 2.5 V to 5.5 V and V
to GND.

4 7 DIN

Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling
edge of the serial clock input.

5 6 SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock
input. Data can be transferred at rates up to 30 MHz.

6 5

SYNC Level Triggered Control Input (Active Low). This is the frame synchronization signal for the input data.

When

SYNC goes low, it enables the input shift register and data is transferred in on the falling edges
of the following clocks. The DAC is updated following the 16th clock cycle unless
before this edge, in which case the rising edge of SYNC acts as an interrupt and the write sequence is
ignored by the DAC.

2, 3 NC No Connect.

1

V

DD

NC

NC

OUT

AD5320

2

TOP VIEW

3

(Not to Scale)

4

NC = NO CONNECT

8

7

6

5

Figure 4. MSOP Pin Configuration

DD

GND

DIN

SCLK

SYNC

00934-004

should be decoupled

SYNC is taken high

Rev. C | Page 6 of 20