Akai PDP-5006M Service Manual

SERVICE MANUAL

Model:

PDP-5006M

Safety Precaution

Technical Specifications

Block Diagram Circuit Diagram Basic Operations & Circuit Description Main IC Specifications

Trouble Shooting Manual of PDP Module

Spare Part list Exploded View

If You Forget Your V-CHIP Password

Software Upgrade

This manual is th e la test at th e time of printing, and do e s not include th e modification which may b e made after th e printing, by the co n st an t improvement of product.

Safety Precaution

CAUTION

RISK OF ELE CTRIC S HOCK

DO NOT OPEN

A

CAUTION: TO REDUCE THE RISK OF ELECTRIC SHOCK, DO NOT REMOVE COVER (OR BACK). NO USER-SERVICEABLE PARTS INSIDE. REFER SERVICING TO QUALIFIED SERVICE PERSONNEL ONLY.

A

The lightning flash with arrowhead symbol, within an equilateral triangle, is intended to alert the user to the presence of uninsulated “dangerous voltage” within the product’s enclo sure that m ay be of sufficient magnitude to constitute a risk of electric shock to persons.

The exclamation point within an equilateral triangle is intended to alert the user to the presence of important operating and maintenance (servicing) instructions in the literature accompanying the appliance.

P R E C A U T IO N S D U R IN G

S E R V IC IN G

1. In addition to safety, other parts and assemblies are specified for conformance with such regulations as those applying to spurious radiation. These must also be replaced only with specified replacements. Examples: RF converters, tuner units, antenna selection switches, RF cables, noise-blocking capacitors, noise-blocking filters, etc.

2. Use specified internal Wiring. Note especially:

1) Wires covered with PVC tubing

2) Double insulated wires

3) High voltage leads

3. Use specified insulating materials for hazardous live parts. Note especially:

1) Insulating Tape

2) PVC tubing

3) Spacers (insulating barriers)

4) Insulating sheets for transistors

5) Plastic screws for fixing micro switches

4. When replacing AC primary side components (transformers, power cords, noise blocking capacitors, etc.), wrap ends of wires securely about the terminals before soldering.

5. Make sure that wires do not contact heat generating parts (heat sinks, oxide metal film resistors, fusible resistors, etc.)

6. Check if replaced wires do not contact sharply edged or pointed parts.

7. Make sure that foreign objects (screws, solder droplets, etc.) do not rem ain inside the set.

M A K E Y O U R C O N T R IB U T IO N

T O P R O T E C T TH E

E N V IR O N M E N T

Used batteries with the ISO symbol

\5<9

for recycling as well as small accumulators (rechargeable batteries), mini-batteries (cells) and starter batteries should not be thrown into the garbage can.

Please leave them at an appropriate depot.

W A R N IN G :

Before servicing this TV receiver, read the SAFETY INSTRUCTION and PRODUCT SAFETY NOTICE.

S A F E T Y IN S T R U C T IO N

The service should not be attempted by anyone

unfamiliar with the necessary instructions on this

apparatus. The following are the necessary

instructions to be observed before servicing.

1. An isolation transformer should be connected in the power line between the receiver and the AC line when a service is performed on the

primary of the converter transformer of the set.

2. Comply with all caution and safety related provided on the back of the cabinet, inside the

cabinet, on the chassis or picture tube.

3. To avoid a shock hazard, always discharge the picture tube's anode to the chassis ground before removing the anode cap.

4. Completely discharge the high potential voltage

of the picture tube before handling. The picture tube is a vacuum and if broken, the glass will explode.

5. When replacing a MAIN PCB in the cabinet, always be certain that all protective are installed properly such as control knobs, adjustment covers or shields, barriers, isolation resistor networks etc.

6. When servicing is required, observe the original lead dressing. Extra precaution should be given to assure correct lead dressing in the high voltage area.

7. Keep w ires away from high voltage or high tempera ture components.

8. Before returning the set to the customer, always perform an AC leakage current check on the exposed m etallic parts of the cabinet, such as antennas, terminals, screwheads, metal overlay, control shafts, etc., to be sure the set is safe to operate without danger of electrical shock. Plug the AC line cord directly to the AC outlet (do not use a line isolation transformer during this check). Use an AC voltmeter having 5K ohms volt sensitivity or more in the following manner. Connect a 1.5K ohm 10 watt resistor paralleled by a 0.15pF AC type capacitor, between a good earth ground (water pipe, conductor etc.,) and the exposed metallic parts, one at a time. Measure the AC voltage across the combination of the 1.5K ohm resistor and 0.15 uF capacitor. Reverse the AC plug at the AC outlet and repeat the AC voltage measurements for each exposed metallic part. The measured voltage must not exceed 0.3V RMS. This corresponds to 0.5mA AC. Any value exceeding this limit constitutes a potential shock hazard and must be corrected immediately. The resistance measurement should be done between accessible exposed metal parts and power cord plug prongs with the power switch "ON". The resistance should be more than 6M ohms.

AC VOLTMETER

P R O D U C T S A F E T Y N O T IC E

Many electrical and mechanical parts in this apparatus have special safety-related characteristics.

These characteristics are offer passed unnoticed by visual spection and the protection afforded by them cannot necessarily be obtained by using replacement components rates for a higher voltage, wattage, etc.

The replacement parts which have these special safety characteristics are identified by A marks on the schem atic diagram and on the parts list.

Before replacing any of these components, read the parts list in this manual carefully. The use of substitute replacement parts w hich do not have the same safety characteristics as specified in the parts list may create shock, fire, or other hazards.

9. Must be sure that the ground w ire of the AC inlet is connected with the ground of the apparatus properly.

Good earth ground

such as the w ater

- p ip e, cond u ctor,

etc.

AC Leakage Current Check

1500 ohmi, lOwatt

Place this probe on each exposed metallic part

Technical Specifications

M O D E L : PDP-5006M

5 0 ” P la s m a D is p la y

DATE FIRST ISSUED ISSUE

1

REVISIONS

ISSUED DATE DESCRIPTION RAISED BY :

RAISED BY CHECKED BY NUMBER OF PAGES

9

SPECIFICATION AGREED : SIGNATURE DATE

R & D DEPARTMENT

COMMERCIAL DEPARTMENT

PRODUCTION DEPARTMENT

Q/A DEPARTMENT

CUSTOMER

SPECIFICATION APPROVED : SIGNATURE : DATE

NOTE : On l y d o c um e n t s s t amp ed “Co n t ro l le d Do c u m en t ” t o b e us e d fo r m an u f a c t u r e o f p ro d u ct io n pa rt s.

CONTINUATION PAGE

Technical Specifications

1. S ta n d a rd T e s t C o n d itio n s

PDP-5006M

NUMBER 2 OF 9 PAGES

All tests shall be performed under the following conditions, unless otherwise specified.

1.1 Ambient light

1.2 Viewing distance

1.3 Warm up time

1.4 PDP Panel facing

1.5 Measuring Equipment

1.6 Magnetic field

1.7 Control settings

1.8 Power input

1.9 Ambient temperature

1.10 Display mode

150ux (When measuring IB, the ambient luminance

= 0.1Cd/m2)

50cm in front of PDP

30 minutes

no restricted

PC, Chroma 2225 signal generator (with Chroma digital additional card) or equivalent, Minolta CA100 photometer

no restricted

Brightness, Contrast, Tint, Color set at Center(50)

100~240Vac

20°C ± 5°C (68°F ± 9°F)

31.5KHz/60Hz (Resolution 1366 x 768)

1.11 Other conditions

1.11.1 With image sticking protection of PDP module, the luminance will descend by time on a same still screen and rapidly go down in 5 minutes. When measuring the color tracking and luminance of a same still screen, be sure t o accomplish the measurement in one minute to ensure its accuracy.

1.11.2 Due to the structure of PDP, the extra-high-bright same screen should not hold over 5 minutes for fear of branding on the panel.

Technical Specifications

E L E C T R IC A L C H A R A C T E R IS T IC S

2. P o w e r In p u t

PDP-5006M

CONTINUATION PAGE

NUMBER 3 OF 9 PAGES

2.1 Voltage

2.2 Input Current

2.3 Maximum Inrush Current Test condition

2.4 Frequency

2.5 Power Consumption Test condition

2.6 Power Factor

2.7 Withstanding voltage

3. D is p la y

3.1 Screen Size

3.2 Aspect Ratio

3.3 Pixel Resolution

3.4 Peak Brightness

3.5 Contrast Ratio (Dark room)

3.6 Viewing Angle

3.7 OSD language

100 ~ 240VAC

5.0 /2.5A

<30 A (FOR AC110V ONLY) Measured when switched off for at least 20 mins

50Hz to 60Hz(±3Hz)

< 480W full white display with maximum brightness and contrast

Meets I EC 1000-3-2

1.5kVac or 2.2kVdc for 1 sec

50” Plasma display 16:9

1366x768 1000 cd/m2 (Panel module without filter) 5000:1 (Panel module without filter)

Over 160° English

4. Sig n a l

4.1 AV & Graphic input

4.1.1 Composite signal

4.1.2 Y,C Signal

4.1.3 Component signal

4.1.4 Graphic I/P

4.1.5EDID compatibility

4.1.6 I/P frequency

CVBS S-Video Y, Pb/Cb, Pr/Cr, HDTV compatible

Analog: D-sub 15pin detachable cable

Digital: DVI

DDC 1.3

fH 31.5kHz to 60kHz/fV: 56.25Hz to 75Hz (1024X768

recommended)

Technical Specifications

4.2 Audio input Audio I/P(L/Rx5)

4.3 AV output Audio&Video O/P(RCAx3)

PDP-5006M

1 for DVI / D-Sub 1 for Y/ Pb/Pr 1 for Y/ Cb/Cr 1 for CVBS 1 for S-Video

: Monitor out(Video & Audio L/R)

CONTINUATION PAGE

NUMBER 4 OF 9 PAGES

4.4 Other function :

5. E n v iro n m e n t

5.1 Operating environment

5.1.1 Temperature :

5.1.2 Relative humidity:

5.2 Storage and Transport

5.2.1 Temperature :

5.2.2 Relative humidity:

6. P a n e l C h a r a c te r is t ic s

6.1 Type

6.2 Size

6.3 Aspect ratio

6.4 Viewing angle

6.5 Resolution

6.6 Weight

6.7 Color

6.8 Contrast

6.9 Peak brightness :

PIP/POP/PBP, Picture size, Picture Still, Sound mode,Last

memory, Timer, MTS

5° to 33°C 20% to 85%(non-condensing)

-20°C to 60°C(-4° to 140°F) 5% to 95%

S50HW-XD03 50”, 1190mm(width)x7005mm(height)x59mm(depth)±1

mm)

16:9

Over 160°

1366X768

22.0kg ±0.5 kg (Net) 1024(R)X1024(G)X1024(B) COLORS

Average 60:1 (In a bright room with 150Lux at center) Typical 5000:1 (In a dark room 1/100 White Window pattern at center).

Typical 1000cd/m2 (1/25 White Window)

6.10 Color Coordinate Uniformity :

Test Pattern :

Contrast; Brightness and Color control at norma setting Full white pattern

Average of point A,B,C,D and E +/- 0.01

Technical Specifications

PDP-5006M

NUMBER 5 OF 9 PAGES

6.11 Color temperature Contrast at center (50); Brightness center (50); Color temperature set at Natural x=0.285±0.02 y=0.290±0.02

6.12 Cell Defect Specifications

Subject to Panel supplier specification as appends.

7. F ro n t P a n e l C o n tro l B u tto n

CONTINUATION PAGE

7.1 SET Up / Down Button

Push the key to select Item up or down.

When selecting the item on OSD menu.

Volume Up/ Down Button

Push the key to increase the volume up or down.

When selecting the adjusting item on OSD menu

increase or decrease the data-bar.

Menu Button

Source Select Button

7.2 Stand by Button

Enter to the OSD menu.

Push the key to select the input signals source.

Switch on main power, or switch off to enter power Saving modes.

7.3 Main Power Switch

8. O S D F u n c tio n

Turn on or off the unit.

8.1 Picture : State (Normal,Dark,Bright,User); Display (Bright,contrast,Color,Hue)

Temp (warm,Cool,Normal,User);

Position (H-posit,V-posit,Phase,H-size,Auto Adjust)

8.2 Sound : Setup (Mode,AVC,Volume,Balance);

Equalizer (120HZ,500HZ,1.5KHZ,5KHZ,10KHZ) BBE Setup (Gain,Treble,Bass)

8.3 OSD : Size (Panorama,16:9,Normal,Anamorphic,Letter Box,TV Mode)

OSD Set (Language,OSD Position,Time Out) Option (Burn Protect, Version)

V-Chip , C/C

8.4 Layout : Layout (Full Screen,PIP,Split Screen,Grid,POP 3,POP 12) PIP Set (Sub Win Source,Sub Win Size,PIP Size.PIP Position)

8.5 Time : Sleep (30Min,60Min,90Min,120Min,180Min)

Wake Up (Time Edit,Volume,TV Mode,Channel) Time Set

Technical Specifications

9. A g e n c y A p p r o v a ls

Safety UL60950

Emissions FCC class B

10. R e liab ility

PDP-5006M

CONTINUATION PAGE

NUMBER 6 OF 9 PAGES

11.1 MTBF

11. A c c e s s o rie s

20,000 hours(Use moving picture signal at 25°C ambient)

User manual x1, Remote control x1, Stand x1, Power cord x1, Battery x 2, Accessories box x 1 ,Speaker x 2,Speaker wire x2

Technical Specifications

12. Support the Signal Mode

A. D-Sub Mode (VGA or DVI)

PDP-5006M

CONTINUATION PAGE

NUMBER 7 OF 9 PAGES

NO.

1 640 x 400 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

Resolution

640 x 480 640 x 480 640 x 480 640 x 480 720 x 400 800 x 600 800 x 600 800 x 600 800 x 600 832 x 624

1024x 768 1024x 768 1024x 768 1152x 864 1152x 864 1152x 864 1280x 960 1280x 1024

Horizontal

Frequency

(KHz)

31.47 70.08

31.50 60.00

35.00 67.00

37.50 75.00

37.86 72.81

31.47 70.08

35.16 56.25

37.90 60.32

46.90 75.00

48.08 72.19

49.00 74.00

48.40 60.00

56.50 70.00

60.00 75.00

54.53 61.13

63.86 70.02

67.52 75.02

60.02 60.02 108.04

64.00 60.01 108.00

Vertical

Frequency

(Hz)

Dot Clock

Frequency

(MHz)

25.17

25.18

30.24

31.50

28.32

36.00

40.00

49.50

50.00

57.27

65.00

75.00

78.75

80.37

94.51

108.03

B. DTV Mode

Horizontal

NO. Resolution

1 480 i 2 3 4 5 6 7 8

- When the signal received by the Display exceeds the allowed range, a warning message "Out Of Range” shall appear on the screen.

- You can confirm the input signal format from the "OSD Menu”.

1080i(1920x1080) 1080i(1920x1080)

576 i 480p(720x480) 576p(720x576)

720p(1280x720) 720p(1280x720)

Frequency

(KHz)

15.734 59.94

15.625 50.00

31.468 59.94

31.25 50.00

45.00 60.00

37.50 50.00

28.125 50.00

33.75 60.00

Vertical

Frequency

(Hz)

Dot Clock

Frequency

(MHz)

13.50

27.00

74.25

CONTINUATION PAGE

Technical Specifications

4 . 4 R e m o te C o n tro l

0 Power ( 6 ): Press to turn on and off. 2 Mute ( ^

): Press to mute the sound. Press

again or press ◄ or ► to restore the sound.

3 P.STILL: Press to freeze the picture. Press

again to restore the picture.

4 P.SIZE: Press to cycles through the picture

size: Normal, Fill Screen, Anamorphic, Letter Box, TV Mode or Panorama.

5 P. MODE: Press to cycles through the picture

mode: NORMAL, BRIGHT, DARK, USER.

select: Main window sound or Sub window sound.

0 PIP: Press to turns on PIP (picture-in-

picture) feature. Such as Full Screen, PIP or Split Screen.

8 SWAP: Press to switches the Main window

or Sub window pictures.

9 C/C: Press to select the Closed Caption

mode.

10 V-Chip: Press to select the child protect

mode. 11 TIME: Press to display the current time. 12 SLEEP: Press repeatedly until it displays

the time in minutes (30 Min, 60 Min, 90 Min,

120 Min, 180 Min or Off ) that you want the PDP to remain on before shutting off. To cancel Sleep Time, press SLEEP repeatedly until Sleep Off appears. And you can press

◄ or ► to select sleep time shut down.

13 Number buttons: Use these buttons to

enter password.

(Note: The 100 button is inactive in this model.)

14 PIP Source: Press to select the signal for Sub Window.(Only for PIP.) 15 F.WHITE: Press to show a full white picture. 16 INFO: Press to display on-screen information. 17 SOUND: Press to select different sound system, such as Normal, Flat, News, Cinema,

User or BBE Digital.

18 PICTURE: Press to select “BRIGHT”, “COLOR”, “CONTRAST”, ”HUE” or “SHARP”, and

you can use^ or ► to adjust.

19 EXIT: Press to return or exit OSD menu.

PDP-5006M

1 3 4 7

NUMBER 8 OF 9 PAGES

-GD P.STILL P.SIZE P.MODE/S. SEI E

t f j f c l d T C D r

PIP SWAP C/C V-CHIP r

□ C D

TIME SLEEP

©

PIP Source F.WHITE INFO 1 100

-ED ED CD CD

SOUND PICTURE EXIT SOURCE

-ED ED ED ED-

C l>

2 5

12

(Continued on next page)

CONTINUATION PAGE

Technical Specifications

21 SOUND: Press to select different sound system, such as Normal, Flat, News, Cinema,

PDP-5006M

NUMBER 9 OF 9 PAGES

User or BBE Digital.

22 PICTURE: Press to select “BRIGHTNESS”, “COLOR”, “CONTRAST”, ”HUE” or

“SHARPNESS”, and you can use A or ► to adjust.

23 EXIT: Press to return or exit OSD menu. 24 SOURCE: Press to select the signal sources directly. Such as TV, AV1, S-VIDEO,

YCbCr, YPbPr, Analog RGB or Digital RGB.

23 MENU: Press to display the OSD Menu. 23 OK: Press to enter or confirm. 21 ▲ / ▼ : They are used as ▲ / ▼ buttons in the OSD Menu screen and they can be

used for the selection of the program when the OSD Menu is not shown on the screen.

2 3 -4 / ► : They are used as -4 / ► buttons in the OSD Menu screen and they can be

used for the adjustment of volume when the OSD Menu is not shown on the screen.

P H Y S IC A L C H A R A C T E R IS T IC S

14. P o w e r C o rd

Length : 1.8m nominal

Type :

15. C a b in e t

optional

15.1 Color : silver colour as defined by colour plaque reference number

15.2 Weight

Net weight :

Gross weight :

51.8kg 74kg

15.3 Dimensions (with stand&speak)

Width : Height :

Depth :

1227.8mm

739.8mm

120.6mm

Block Diagram

Product Specification of PDP Module

LVDS Input

Control Signal —

(Serial Interface)

APL Data

Memory

Input Interface Controller

Display data, Driver timing

>

•c Q

G

cd

O

GO

Controller

Driver

Timing Controller

Color Plasma Display Panel

1366 X 768 pixels

<u

>

•G

T3

cö 3 c

O

Vs(180V~190V)

Va(55V~65V)

Vcc(+5V)

o

Address Driver

Applied Voltage level is specified at the time when Full-White pattern is displayed on the panel.

Block Diagram MAIN/AUDIO BOARD

Circuit Diagram

- Power supply board of Audio Amplifier,

- Main (Video) board

- Audio/Tuner board

- Keypad board

- Remote control receiver board

- Remote control board

MPT012A

1

DbhM4812V12 Vtek BOM.sch-3 - Wed Oct 06 23:58:10 2004

I--X SB_SCL [3]

1--< SB_SDA [3]

CE20Q

D201

W -

D200

W -

H h

[3] MAX_TX[?--[.

[3] MAX_RX[)--|_

TTTyTTTTTT

j_um

vcc ADO.PD.D EA.VP AD2.P0.2 RESET AD4.P0.4 P1.0.T2

P1.1.T2EX

P1.2

P1.3.PWM0

P1.4.PWM1

P1.5.PWM2

P1.6.PWM3

P1.7.PWM4 P3.0.RXD A13.P2.5

P3.1.TXD

P3.2.INT0 (B)A15,P2.7

P3.3.INT1

P3.4.T0 ALE.P

P3.5.T1 XI X2 P4.0

GND (B)INT2,P4,3

AD1.P0.1 AD3.P0.3 AD5.P0.5

AD6.PÛ.6

AD7.P0.7

AB.P2.0

A9.P2.1

A10.P2.2

A11.P2.3

A12.P2.4

(B)A14,P2.B

PSEN

WR.P3.6

RD.P3.7

P4.1

INT3.P4.2

I— Öl-

X1 VCC X? sni

SI)A

INI A

SOW GND

1 SB_SCL [3]

SB_SDA [3]

Project:

Dubhe Main

Title:

Micom Block

Date: Sheet:

Rev:

1.2

SEP.10 '2004 03 of 13

DbhM4812V12 Vtek BOM.sch-4 - Wed Oct 06 23:58:11 2004

DDF[00:23]

~m

------ DDF07/

11

noma.

10

DDFOL

9

psbi

. DF04 1 » DF05 ? 7 R DFilfi „ DFOfi 3 » DF07 4 5 D n m z

„ DFOB 1 » UFOS 7 „ DF10 3 » DF11 4

„ DF17 1 » DF1.1 7

. DF14 3

» DF15 4

„ DF1fi 1

. DF17 2

v DF18 3

„ nnq 4 5 DDF19, „ DF70 1

„ DF71 7

v DF22 3

, DF23 4

■'S/VS/

I

A252

/w v 'S/VS/

A253

/yv v /w v

FA 254

/yv v

I

FA255

— :

1

b DnF04, b o nrnfi,

B DDFOfl. 7 DnFns, 6 DDF10,

5 RDF11 ,

B DDF17/ 7 RDFI.T. 6 DDF14/ 5 DHF15,

R DDF16.

7 DDF17,

R DDF18.

fi DDF20.

7 DDF21,

R DDF2Z

5 DDF23,

DDF07,

-| 17

IÎDF0.1

11

in DDF04,

RDF05, DDF14/

I17

RDF15,

in DDFOR.

R0F09, DDF10/

I17

IÎDF11 ,

in I50F17/

DDF13, DDF22,

i1?

DDF23,

11

DDF16,

10

DDF17, DDF18,

l1?

DDF19,

11

DDF20,

10

DDF21,

9

nnsn7.

11 10 n ns oa

nn sm.

DDS07,

I 17

nn sn.\

10 ODSfH,

IÎDS05.

9

[4TD1+

nnsu,

I 17

DDS15/

10 nnsna,

nnsns,

D0S10/

I 17

IÎDR11 ,

10 D0S17/

IÎDR1.T,

DDS2Z

I 17

DDS23. DDS16,

10

DDS17,

DDS18.

-|1? DDS19,

11

DDS20.

10

DDS21,

9

[4 A2-

[4fA2+

[4ÎB2-

[4TB2+

FOR DUAL THINE FORMAT

. DDF01 52

. DDF02 54

. DDF03 55

. DDF04 56

. DDF05 3

. DDF08 50

. DDF07 2 . DDF08 4

. DDF09 6

. DDF10 7

. DDF11

. DDF12 12

. DDF13 14

. DDF14 B

. DDF15 10 . DDF16 15

. DDF17 19

. DDF1B 20

. DDF19 22

. DDF20 23

. DDF21 24

. DDF22 16

. DDF23 1B

11

>CL KIN PVCC TA0(R2,RD)

TA1(R3,R1)

TA2(R4,R2)

TA3lR5,R3)

TA4(R6,R4) VCC1

TA5(R7,R5) VCC2

TD0(R0,R6) RS(VCC)

TD1(R1,R7) TA6ÎG2.G0) TXOUTG—

TB0(G3,G1) TXOUTO+

TB1(G4,G2)

TB2(G5,G3) TXOUT1-

TB3 G6.G4) TXOUT14

TB4 G7.G5)

TD2 G0,G6) TXOUT2-

TD3(G1,B7) TB5(B2,B0)

TB6(B3,B1)

TC0(B4,B2) TXOUT3-

TC1(B5,B3) TXOUT3+

TC2(B6,B4)

TC3 B7.B5) GND1

TD4 B0.B6) GND2

TD5(B1,B7) TC4(HS)

TC5 VS) 0GND1

TC61EN) OGND2

TD6(RES) OGND3

R FB (THINE,NS) PgnD1

PWRDN# PGND2

LVDSVCC

TXOUT2+

TXCLK-

TXCLK+

GND3

GND4

GND5

-R

TA1+

[4]

TB1- [4]

TB1+

[4]

TC1-

[4]

TC1+[4] TCLK1—[4]

TCLK1-K4] TD1-

[4]

TD1+

[4]

. DDSOB1 4

. DDS091 6

. DDS101 /

. DDS11 1

. DDS121 17

. DDS131 14

. DDS141 K

. DDS151 1U . DDS161 15

. DDS171 19

. DDS181 70

. DDS191 22

11

1

>CLKIN PVCC TA0(R2,R0)

TA1(R3,R1) LVDSVCC

TA2(R4,R2)

TA3(R5,R3)

TA4 R6,R4) VCC1

TA5 R7.R5) VCC2

TD0(R0,R6) RS(VCC)

TD1(R1,R7) TA6(G2,G0) TXOUTO—

TB0(G3,G1) TXOUTO+

TB1(G4,G2)

TB2(G5,G3) TX0UT1-

TB3(G6,G4) TX0UT1+

TB4(G7,G5)

TD2(GD,G6) TX0UT2-

TD3(G1,G7) TX0UT2+ TB5(B2,B0) TXCLK+

TB6fB3,Bl)

TCD(B4,B2)

TC1(B5,B3) TX0UT3+

TC2(B6,B4)

TC3(B7,B5) GND1

TD4(BD,B6) GND2

TD5(B1,B7) GND3 TC4(HS)

TC5 VS) 0GND1

TC6ÎEN) 0GND2

TD6(RES) 0GND3 R FB (THINE,NS) pGND1

PWRDNjf PGND2

TXCLK-

TX0UT3-

GND4

GND5

TA2-

[4]

TA2+

[4]

TB2- [4]

TB2+

[4]

TC2-

[4]

TC2+[4]

- [4]

TCLK2

-R

TCLK2+ [4] TD2-

St

-R

TD2+

[4]

Project:

Dubhe Main

Title:

TTL & LVDS Output

Date: Sheet:

SEP.10 '2004 04 of 13

Rev:

1.2

3bhM4812V12 Vtek BOM.sch-5 - Wed Oct 06 23:58:15 2004

DbhM4812V12 Vtek BOM.sch-6 - Wed Oct 06 23:58:16 2004

O j

C411 jc^412_jc413_jc414Jc 415 Jc416 Jc 417 +

TTTTTT“M

PV

03

c

p

Ç41BjÇ419 +iï

CE400

:E401

?

2

1

■— 1—

JÇ420JÇ421_|Ç422

io ^ T T T 1

[5] GHSYNC

Jc42

I

[5] GVSYNC

HDPRIN I

HDYIN I

HDPBIN I

GRAIN I--y_ GGAIN I--v_

[5] ' [5] ' [5] '

[5] '--^

ru i 1

-----

Jc42

I

H \~

VCC5

A

S1A VCC SIR

DA

SIC

DB

sin

DC

S2A DD

'

S2B IN S2C ËN S2D GND

«FB40Q,

1FrM019

[8.11.12] SDA3G I

[8.11.12] 5CL3G [11]

[11]

R40B w K4P9 WV

R41P w

----

-PV&3

C4B2^ | C403| | C404 | |

C405 | |

jc408_Jc4l

-----

Q

R40CT"

------

;

C4Q0

o

o it cm ro m to r- oo oi orrcMr'wm oz;

SDA REDO

SCL RED1

AO RED2 CLAMP

COAST RED5

HSYNC RED6

VSYNC RED7

54.

RAIN

4L

GAIN

43.

BAIN

«

50GIN

AVD3

VCC3

▲

ld in in to ^

U400 GREEN0

DATACLK S0G0UT HSOUT

VSOUT BLUE6 REFBYPASS

M!DSCV0

ÛQÛQÛQQÛQÛQÛÛQQÛQQQÛ

zzzzzzzzzzzzzzzzzzzz

CJUUUUUUUUUUUUUCDUUUUU

PVD3

Q

RED3

RED4

GREEN1

GREEN2

GREEN3

GREEN4

GREEN5

GREEN6

GREEN7

BLUEO

BLUE1

BLUE2

BLUE3

BLUE4

BLUE5

BLUE7

VCC5

A

7fi RA40©

/h 3

74

73 1 -

RA4019

r?

71 3

/0 9 1 r

RA40Z>

K

/

6

5 1 -

4 RA403>

A

?

19 1 r

1H RA404?

17

IK

15 1 h

14 RA40®

13 3

12

4 4 3

4 3

4 4

B

fi

8 6 GRGROR

5

1R

7 GRGROft

fi

5

8 GRBR19,

7 GRGB13/

fi

5

18

6

18

6 GRGR7Z

fi

RGB[00:07] - Red RGB[08:15] - Green RGB[16:23] - Blue

GRGBGL

GRGRGT.

GRGB0.1

GRGR04

RRRROR GRGR07, GRGB0& GRGR10/

GRGR11, GRGR14/

GRGR15/ GRGR16/

GRGR17/

GRGR1R/

BRBR19,

GRGR7C1

GRBR71/ GRGB23

GRGBrOD:231

^402-A

3

-----

7

U4D2-B

6

---

R4Q5 VA_

T

JC4

[7.8.11|3—> GVS [7.11] |--> GFBK

[7.6.1^ GHS

Project:

Dubhe Main

Title:

PC Analog Input

Date: Sheet:

Rev:

1.2

SEP.10 '2004 06 of 13

DbhM4812V12 Vtek BOM.sch-7 - Wed Oct 06 23:58:18 2004

JL

RX2+ I--y_

RX2- |—p

[5]

RX1 + I—v_

[5]

RX1- h^C

RX0+

RX0- RXC+

R-

RXC-

DVLSCL I—> DVLSDA I—s R460 »n

GDFEOE I--\

[3,B,9,10,12,13J '--7 vv^

---

[5.11] '—7 vvv^ [5.11] '—7 vvv^

[11] '--^

RST# i-^

R459 VW-

______

---

VCC3

▲

R458 R457 IR456 R454 R453

rrcNio u

rr cN K5 m

> > > Q-

D O O o o

EXT_RES QE7 RX2P

RX2M Q E12 RX1P QE14

RX1M QE15 RXOP QE17

RXOM QE18 RXCP QE20

RXCM QE21

OCKJNV/SCL Q07 ST/SDA 009 PDO 0011 PD 0013 STAG_0UT Q015 SCAN Q017 DFO/RST# 0019 PIXS Q021 CTL1/KSCL Q023 CTL2/KSDA ODCK <

QÛQOQ

U450

CM ro C3

<<<

u QEO

ÿ QE1

< QE2

QE3

QE4

QE5

QE6 QE8

QE9

0 E10

QE11

QE13 QE16 QE19

QE22

QE23

QOO

001

Q02

003

Q04

005

Q06

008 Q010 Q012 Q014

0016

Q018

0020

Q022

DE

VSYNC

HSYNC

_cMir«-irj C7L3

OQOQQ “IL“

C4SsJç*SS_£45’j:+SeJçJS9jç460_Ë+SlJç'

TTTTTTT

10 1 r

11 RA4503

12 3

13

14 1

15 RA4519

16 3

17

20 1

21 RA457?

22 3

23

24 1

25 RA453?

26

27

30 1

31

32 3

33

34 1

35

36 3

37 49

50

51

RA4549 RA45S

7

4

7

4

7

4

8

7

3

4

R

P

7 R

7 5

RRRRH1 RRRRH5

RRRR07

4 4

RGB[00:07] RGB[08:15] RGB[16:23]

Red Green Blue

Project:

Dubhe Main

Title:

PC Digital Input

Date: Sheet:

Rev:

1.2

SEP.10 '2004 07 of 13

DbhM4812V12 Vtek BOM.sch-8 - Wed Oct 06 23:58:29 2004

DbhM4812V12 Vtek BOM.sch-9 - Wed Oct 06 23:58:20 2004

DbhM4812V12 Vtek BOM.sch-10 - Wed Oct 06 23:58:22 2004

„ D31A01 RA? ?

„ D31A0? 3

, D31A03 4

< D31A04 1

, D31A05 RA3 ?

„ 031AÍJ6

< D31A07 4

. D31A0B 1

„ 031A09

RA4 2

„ 031A10

, D31A11 4

. D31A12 1

V D31A13 RA5 2

0 C75B|

Should be Daizy-Chain

3 3

'

C735

r

VSSO VDDO

_

71

VSS1 VDD1

104

VSS2 VDD2

134

VSS3 VDD3 PVSSO PVDDO

PVSS1 PVDD1

PVSS2 PVDD2

PVSS3 PVDD3

PVSS4 PVDD4

122

PVSS5 PVDD5

147

PVSS6 PVDD6

7B

DPAVSS DPAVDD

76

DPDVSS DPDVDD

123

MPAVSS MPAVDD ADDVSS ADDVDD

ADAVSS ADAVDD

ADGVSS ADGVDD AVS33B AVD33B

AVS55G AVD35G

AVSS33R AVD33R AVSS33SVM AVD53SVM

£_40

MAO MD15

3B

7

MA1 MD14

3H

fi

MA2 MD13

5A4

MA3 MD12

33

R

MA4 MD11

35

7

MA5 MD10

3/

fi

MAß MD9

34

ñ

MA7 MDB

41

R

MAB MD7

43

7

MA9 MD6

4^

fi

MA10 MD5

4b

5

M A11 MD4

4h

R

MA12 MD3

44

7

MA15 MD2 MCLKFB MRÄS"

>MCLK UWE

osuno 25

24

22

35

20

21

15

39 37

13n 40

36

RAS VDD1

VDD2

CAS VDD3

VDD4

WE VDD5

VDD6

>CLK VDD7 AO DO

AI DI

A2 D2

A3 D3

A4 D4

A5 D5

A6 D6

A7 D7

AB DB

A9 D9

A10 D10

D11

All

D12

BAO D13

BA1 D14

D15

DQML

DQMH VSS1

VSS2

CKE VSS5

CS VSS4

VSS5

NC1 VSS6

NC2 VSS7

90

121

146

160

68 D51D15

66

H4

ßV

Bl>

5B

hh 031009

S4 D31D0B

55

b/

h»

61

h3

Rh 03100?

67

MD1

t>y

MDO

MCAS

V DINT 3

2 osioon

4

!)

/

H

11)

11

13

47

44

4 h

4/

4H

.40

M

b3

031015

--V0tNT18-- Á

D31D14

031013

031017

031011

D31D10 031007

D31DD6

031005

D31D04

031003 D31D01

D51D00

,

, ,

,

■W“

Jc704_]c705

_Jc 71

I

Je 7 0 oje 7 01_Jc 7 02_Jc 71 T T T

lFB70a,

jç706_jç707jç708jç709_jç710_lç711 Jç712_[c7' T T T T T T T

JÇ717_|Ç716_|Ç715

T T

C721_[c720_|c719_|c71B -J?E7°5

T T T T 1

VPCCLK

[TOM

11

10

9

11

10

9

11

10

9

10

9

W S A —i V W 1

--

VPCVS

VPCHS

VPCPEN

VPC[0D:15]

’ L9.1ÜJ . vpnnR 1?

„ VPC09

, VPC10

. VPR11

„ VPC15

. VPC14

„ VPC15

, VPC01

. VPC02

, VPC03

. VPCOB 11

. vpnoR

„ VPC07

VDINT1B

▲

:e700

VDA3

VCC3

A

îfl

CE704

s

SMD 2

[5,7,8,9,12,13] RST# |

R720

R721

R722

R725

' [10]

RA7D1

.VYCOB B

. VYC09 7

. VYC10 R 5 VRGB18 .

. VYC11 B 4 VRGB19 .

RA702

. VYC12 R

. VYC13 7 ? VRGB21 .

✓W'

. VYC14 fi

. VYC15 B 4 VRGB25.

RA703

. VYCOO R

. VYC01 7 ? VRGB09.

./W"

. VYC02 fi

. VYC03 B 4. VRGB11 .

VYC04 B 1 VRGB12 VYC06 6

VYC07 B

I

1 VRGB16 .

? VRGB17 .

1 VRGB20.

3 VRGB22.

1 VRGBOB. 3 VRGB10 .

[9.11.12]

L

VPCC00:15]

mn

----

[9.10] VPCCLK

[9.10] VPCPEN

[9.10] VPCVS

[9.10] VPCHS

SCL3V

SDA3V

-->_

— DB0

R*RDB3

bSt»DB4

— DB7 — DG0

V DG3

Y DG4

. DR3

' DR4

- DR7 DCLK

ADSVM

COMP

VREFIN

VREFOUT

TRST

XTALI

V VPCOO

. VPH01

» vpno?

. VPR03

V VPC04

. vpnoñ

V VPC06

„ VPC07 V VPCOB

. VPR09

V VPC10

„ VPC11

» VPG1?

» VPH13

, VPC14

, VPC15

92

93

94 95

96

97

98

99

100

101

102

109

110

111

112

113

114

115

116

72

135

VBO

VB1

VB2

VB3

VB4

VB5

VB6

VB7 SVHS

SWS

SVCLK —1 VGO

VG1

VG2

VG3

VG4

VG5

VG6

VG7 VRO

VR1

VR2

VR3

VR4

VR5

VR6

VR7 PVCLK

CREF

PWS

PVHS • I2CA1

I2CA2 SCL

SDA DEN

TESTCLK

TEST

CGMS

MACRO

VRGB[00:07] - Red VRGB[08:15] - Green VRGB[16:23] - Blue

Jç72B Jç729 jc730 jç731 jç732 jç735 C;

T T T T T T

1B7

VYROB ,

15B

VYC09/

DB1

IS»

VYC10 ,

DB2

V

VYC11 /

3

VYC1? ,

4

VYR13 .

DB5

b

VYC14 ,

DB6

H

VYC1B ,

149

VYCOO/

l.sr»

VYnm ,

DG1

1B1

VYGO?,

DG2

1b2

VYR03 ,

1b3

VYC04/

1b4

VYC05/

DG5

1f>b

VYC06/

DG6

IbB

VYC07/

DG7

140 RA705P

141

DR2

142

143 1 -

144 RA708?

DR5

145

DR6

14B

DVS

DHS

12 VDA3

21

ADR

18

ADG

fj ^723 ff

ADB

27 J C725

TDO

TCK

129 RA70R?

TDI

130 3

TMS

131

L

I smd|2

R70B a

4

“AVr

-O-

_£gg£_

VDINT3

o

VYCrOQ:151

VRßROO ,

B

VRRB01 .

3

VRßBO? ,

B

4

VRGB03 /

VRGR04 ,

fi

VRRBOB .

7

3

VRßBOfi ,

4

VRGB07 ,

5

\ h

Y700

I.

Project:

Dubhe Main

Title:

Deinterlacer PW1231

Date: Sheet:

SEP.10 '2004 10 Of 13

VRGB[00:23]

LID,TU

--------

> VCLK [10,11]

> WS [10,11]

V VHS [10,11]

OUT

mTAB

VDINT1

A

Rev:

1.2

DbhM4812V12 Vtek BOM.sch-11 - Wed Oct 06 23:58:32 2004

GFBK i

[6,7] 1

GCLK i

[6,7,8] 1

[7,8] GPEN I

[6.7.8] GVS

[6.7.8] GHS

GRGB[00:23]

[6,7,B]

. GRGB01

. GRGR07 M

. GRGB03 h 4

. GRGBÛ4 U2

. GRGB05 U

. GRGB06 DA

. GRGB07 \)V . GRGB08 C11

. GRGBÛ9bi2

. GRGB10 Hl 1

. GRGB11 AH

. GRGB12 HK

. GRGB13 V. H

. GRGB14 A/

. GRGB15 H/ . GRGB16R1R

. GRGB17A/’t)

. GRGB18 Hl/

. GRGB19A19

. GRGB20Hl K

. GRGB21A1 /

. GRGB22

. GRGB23A1 b

GRGB[00:07]

: Red,

GRGB[08:15]

: Green, Y

GRGB[16:23]

: Blue, UV

VCLK

VPBH

VW3

vm

VFIBCD

_tai

VRGB[00:23]

[10]

GRGBQO E4

CA

A1h

C15

B15

A14

B14

A13

C12

B13

A12

VRGBOO E2

. VRGB01

. VRGB02

. VRGB03

. VRGB04

. VRGB05 HA

. VRGB06 HV

. VRGB07 . VRGB08

. VRGB09

. VRGB10 JA

. VRGB11

. VRGB12

. VRGB13 KA

. VRGB14 KV

. VRGB15 K1 . VRGB6 1 ?

. VRGBI 1 1

. VRGBH I A

. VRGB9 L4

. VRGB2DMA

. VRGB21 M1

. VRGB22 N1

. VRGB23 M2

GFBKGBLKSPL

GREFGCOAST

GCLKGHSFOUT GPEN DCLK

(WS

DVS

GHS DHS

CSOG DEN

U800-A

GREO DREO

GRM DREI

GRE2 DRE2

GRE3 DRE3

GRE4 DRE4

GRE5 DRE5

GRE6 DRE6

GRE7 DRE7 GGEO DGEO

GGE1 DGE1

GGE2 DGE2

GGE3 DGE3

GGE4 DGE4

GGE5 DGE5

GGE6 DGE6

GGE7 DGE7 GBEO DBEO

GBE1 DBE1

GBE2 DBE2

GBE3 DBE3

GBE4 DBE4

GBE5 DBE5

GBE6 DBE6

GBE7 DBE7 GROO DROO

GR01 DR01

GR02 DR02

GROA

DR03

GR04 DR04

GR05 DR05

GR06 DR06

GR07 DR07 GGOO DGOO

GG01 DG01

GG02 DG02

GG03 DG03

GG04 DG04

GG05 DG05

GG06 DG06

GG07 DG07 GBOO DBOO

GB01 DB01

GB02 DB02

GB03 DB03

GH04 DB04

GB05 DB05

GB06 DB06

GB07 DB07

VCLK

VPEN

WS

VHS

VFIELD VRO

H

VR1

\'i

VR2

UA

VR3

W

VR4

VR5

VR6

1,1

VR7

,14

VGO

HI

VG1

VG2

J>>

VG3

J1

VG4

VG5

VG6

VG7 VBO

VB1

VB2

VB3

VB4

VB5

VB6

VB7

A1B I—< GCOAST [6]

Y20 DFD1

R16 DF02

U19 DFD3

RIB

W20 DFD5

V20 DFD6

U20 DFD7 T19 DF08

T2Q DFD9

R19 DF1D

R20 DF11

M18 DF12

P18 DF13

P19 DF14

P20 DF15 M17 DF16

N20 DF17

M20 DF18

L17 DF19

M19 DF20

K17 DF21

L19 DF22

L20 DF23 K19 DSOO

K20 DS01

K1B DS02

J20 DS03

J18 DS04

J19 DS05

H20 DS06

H19 DS07 H18 DSOB

H17 DS09

G20 DS10

G19 DS11

G18 DS12

F20 DS13

F19 DS14

F18 DS15 E20 DS16

E19 DS17

E18 DS18

F17 DS19

D20 DS2D

D19 DS21

D16 DS22

D17 DS23

GBLKSPL [6]

[3,4]

[4]

DF[00:23]

[4] [6,8,12]

,

DF04

,

DF[00:07]

,

DF[08:15]

,

DF[16:23]

,

, ,

,

[5] DVI_DET

,

, ,

,

, ,

,

, ,

,

[3] TWCLK

[3] TWDAT

[3] TWDFB

DS[00:23]

[4]

DS[00:07] DS[08:15] DS[16:23]

[6,8,12]

Red

Sreen

Blue

Red Green Blue

VRGB[00:07] - Red VRGB[08:15] - Green VRGB[16:23] - Blue

V15

Á

io io ifs in io

9999q9o2S2d2Sd2c

¿ Ü Ü Û D Q Ü Q Û

-CNKWWtOr-OOO

ÛÛÛÛÛÛQÛÛÛQÛÛÛQÛÛÛÛÛÛÛÛÛÛÛÛÛÛÛÛÛÛÛÛÛQÛ

zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz

>>>>>>>>>'

MCMtMCNCMCNCMC'JC'

RESET

[12] SC2_SWL0W

[12] SC2_SWHIGH

Q Q Q Q

QÛÛQ

>>>>

a œ i i

SMD|2 SMD 2

TTTTTTT

CBO7_[cB0bJcBO9_[cB1O_1cB11 _jcß12_]c B13_jcß14_}c B15_]c816_lcS17_]cB1ß_lcS19 Jcj

TTTTTTTTTTTTT

CB2ijçB22 jçB23 jç825jçB26_jç827_lçB2B _jç829_jç83ojç831 jçj

TT T TTTT TTT

C B3^jcB3 ^jc B35_jc B36 jc837_lc B38_[c839_[c B4 q_lc841_[c842_lcB43_[c844jcj

TTTT TTTTTTTT

VCC3

A

OUT

,.|TAB

R.81C

JçBl

1

)EB03 CE804

VCC3

A

L.

Project:

Dubhe Main

Title:

PW181 Scaler

Date: Sheet:

SEP.10 '2004 11 of 13

WB™

jçB53_jçB52 CI

1 1

VCC2

À

V15P

Á

Rev:

1.2

DbhM4812V12 Vtek BOM.sch-12 - Wed Oct 06 23:58:25 2004

RST# I-->

[3,7,8,9,10,12,13] 1—

RSTj

[3,7,8,9,10,12,13]

[6,8,11,12] SDA3G |

[2] REG5A I

[9,10,11,12BDA3V

[9,10,11,12]SCL3V

[13] SC1_B0X

[13] SC1_GRN

[12] SC1_SW

[9] MA_VIN

[9] MA_CIN

SC2_BLU I

SC2_RED

[5] S D_AIR I

[5] SD_AIL I

VCC5 VAMP

A A

SDA3G

[6,8,11,12]

SCL3G I--V

re b 11 ion 1--/

VCC3

A

sn

49

4/ 4H

4 b46

4 A44

41 47

AW41)

AK

A/

AH

Ah

AAA4

A1A 7

79At)

7/

7H

7h76

VA

74

77

71

70

1«

1/

1H

1h 16

1A 14

17

11

9

10

/ H

b 6

A

4

1 2

VCC3 VCC3

VCC3

A

_<--1 REGBV

SCL3G

PWR33V

«

l SC1_BLU

I SC1_RED ] MA_YIN

SC2_B0X

SC2_GRN

SC2_SW

SB_V IN

SB_CIN

HD_AIR

HD_AIL

1 P C_AIL

SBi-pWLOW

SEi-pWHIGl

1 SCL3G [6,8,11,12]

SDA3G [6,8,11,12]

R904 a « * I--x IRRCVh [

6

Dm .

9

DO? .

11)

D03 .

13

D04 .

14

DOS .

15

D06 ,

IK DH7 .

79

D08 ,

Al>

D09 .

31

D10 ,

A 7

D11 .

Ah

D1? .

AH

D13 .

3/ 014 .

AK

D15 >

39

40 h

1?

A4

1

-----

1

- 1

ptS:

Ï

ta

p

Project:

Dubhe Main

Title:

Memory & Etc. Block

Date: Sheet:

Rev:

1.2

SEP.10 '2004 12 of 13

3bhM4812V12 Vtek BOM.sch-13 - Wed Oct 06 23:58:27 2004

Dbh1S4909V12.sch-2 - Thu Oct 07 00:30:42 2004

Dbh1S4909V12.sch-3 - Thu Oct 07 00:30:43 2004

Dbh1S4909V12.sch-4 - Thu Oct 07 00:30:45 2004

Dbh1S4909V12.sch-5 - Thu Oct 07 00:30:47 2004

Dbh1S4909V12.sch-6 - Thu Oct 07 00:30:49 2004

Dbh1S4909V12.sch-7 - Thu Oct 07 00:30:50 2004

Dbh2S4909V12.sch-2 - Thu Oct 07 00:32:34 2004

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0025.sch-1 - Mon May 16 09:25:50 2005

FOR NTSC

Basic Operations & Circuit Description

MODULE

There are 1 pc. panel and 12 pc.s PCB including 2 pc.s Y/Z Sustainer board, 2 pc.s Y Drive

board, 6 pc.s X Extension boards, 1 pc. Control (Signal Input) and 1 pc. Power board in the Module.

SET

There are 6 pc.s PCBs including 1 pc. AUX. PSU Board, 1 pc. Keypad board, 1 pc.

Remote Control Receiver board, 1 pc. L/R Speakers and 1 pc. Main (Video) board in the SET.

Y-D river Top

X-extension Top L/C/R

Control board Assy.

Power Supply

AUX PSU Board

Y-Sustainer

Y-Driver Bottom

Local Key

Stand Main (Video)

Tuner/Audio

Z-Sustainer

External Speaker Terminals

EMI Filter & AC Inlet

X-extension Bottom L/C/R

PCB function

1. Power: (1). Input voltage: AC 110V~240V, 47Hz~63Hz.

Input range: AC 90V(Min)~265V(Max) auto regulation.

(2). To provide power for PCBs.

2. Main (Video InterFace) board: To converter TV signals, S signals, AV signals, Y Pb/ Cb Pr/Cr signals, DVI signals and D-SUB signals to digital ones and to transmit to Control board.

3. Control board: Dealing with the digital signal for output to panel.

4. Y-Sustainer / Z-Sustainer board: (1). Receiving the signals from Control and high voltage supply. (2). Output scanning waveform for Module.

5. Y-Drive board: Receive signal from Y sustainer, output horizontal scanning wave

form to the panel.

6. X extension board (6pcs): Output addressing signals.

7. Tuner/Audio Board: Process and Amplifying the audio signal to speakers and convert TV RF signal to video/audio signal and send to Main board.

PCB failure analysis

1. CONTROL

2. MAIN (video) :

3. POWER

4. Z - Sustainer

5. Y - Sustainer

6. X - Extension : Abormal vertical noise on screen.

7. Audio Board or AUX PSU: a. No voice. (Make sure Mute/OFF)

: a. Abnormal noise on screen. b. No picture.

a. Lacking color, Bad color scale.

b. No voice. c. No picture but with signals output, OSD and back light. d. Abnormal noise on screen.

: No picture, no power output.

:a. No picture.

b. Color not enough.

c. Flash on screen.

: Darker picture with signals.

b. Noise.

Basic operation of Plasma Display

1. A fter turning on pow er switch, power board sends 5Vst-by Volt to Micro Processor

2. The m icro Processor m em orize the last state of Power, W hen the last state of pow er is on or receive power on signal from local Key or Rem ote control, Micro Processor will send on control signal to power. Then Power sends (5Vsc, 9Vsc, 24V and RLYON, Vs ON) to PCBs w orking. This time VIF will send signals to display Image, O SD on the panel and start to search available signal sources. If the audio signals input, them will be amplified by Audio AMP and transm itted to Speakers.

3. If som e abnorm al signals are detected (for example: over volts, over current, over

tem perature and under volts), the system will be shut down by Power off.

Main IC Specifications

- PW181 Image Processor, Scaler

- PW1231 Digital Video Signal Processor

- uPD64083 Three -Dimensional Y/C Separation LSI

With On-Chip Memory

- AD9883A 110MSPS/140MSPS Analog Interface

- VPC 323XD Comb-filter Video Processor

- Si161B Panel Link Receiver

- Z86229 NTSC Line 21 CCD decorder

- MSP34x0G Multistandard Sound Processor

PW181

Product Specification

General Description

The PW181 ImageProcessor is a highly integrated “system-on-a-chip” that interfaces computer graphics and video inputs in virtually any format to a fixed-frequency flat panel display.

Computer and video images from NTSC/PAL to WUXGA at virtually any refresh rate can be resized to fit on a fixed- frequency target display device with any resolution up to WUXGA. Video data from 4:3 aspect ratio NTSC or PAL and 16:9 aspect ratio HDTV or SDTV is supported. Multi region, nonlinear scaling allows these inputs to be resized optimally for the native resolution of the display.

Advanced scaling techniques are supported, such as format conversion using multiple programmable regions. Three independent image scalers coupled with frame locking circuitry and dual programmable color lookup tables create sharp images in multiple windows, without user intervention.

Embedded SDRAM frame buffers and memory controllers perform frame rate conversion and enhanced video processing completely on-chip. A separate memory is dedicated to storage of on-screen display images and CPU general purpose use.

Advanced video processing techniques are supported using the internal frame buffer, including motion adaptive, temporal deinterlacing with film mode detection. When used in combination with the new third-generation scaler, this advanced video processing technology delivers the highest quality video for advanced displays.

Both input ports support integrated DVI 1.0 content protection using standard DVI receivers.

A new advanced OSD Generator with more colors and larger sizes supports more demanding OSD applications, such as on-screen programming guides. When coupled with the new, faster, integrated microprocessor, this OSD Generator supports advanced OSD animation techniques.

Video

TV

Signal

TV

Signal

Input

TV Tuner

Com puter

j TV Tuner j

Video

Input

Video

Decoder

ADC/

TMDS

ADC/

TMDS

r 1

Video

Decoder

PW181 System Block Diagram

Crystal

~ r

PW181

ROM

Features

• Third-generation, two-dimensional filtering techniques

• Third-generation, advanced scaling techniques

• Second-generation Automatic Image Optim ization

• Fram e rate conversion

• Video processing

• On-Screen Display (OSD)

• On-chip microprocessor

• JTAG debugger and boundary scan

• Picture-in-picture (PIP)

• M ulti-region, non-linear scaling

• Hardware 2-wire serial bus support

Applications

• M ultimedia Displays

• Plasma Displays

• Digital Television

Device Application Package

PW181-10V Up to XGA Displays PW181-20V Up to UXGA Displays

352 PBGA

Dis p lay

Programmable features include the user interface, custom start-up screen, all automatic imaging features, and special screen effects.

p ix e lw o r k s

8100 SW Nyberg Road

Tualatin, OR 97062 USA

Telephone: 503.454.1750

FAX: 503.612.0848

www.pixelworks.com PRELIMINARY I CONFIDENTIAL

AN A LOG 110 MSPS/140 MSPS Analog Interface

►

FEATURES 140 MSPS Maximum Conversion Rate

300 MHz Analog Bandwidth

0.5 V to 1.0 V Analog Input Range 500 ps p-p PLL Clock Jitter at 110 MSPS

3.3 V Power Supply Full Sync Processing Sync Detect for “Hot Plugging” Midscale Clamping Power-Down Mode Low Power: 500 mW Typical 4:2:2 Output Format Mode

APPLICATIONS

RGB Graphics Processing LCD Monitors and Projectors Plasma Display Panels Scan Converters Microdisplays Digital TV

DEVICES for Flat Panel Displays

AD9883A

FUNCTIO N A L BLOCK DIAG R A M

GENERAL DESCRIPTION

The AD9883A is a complete 8-bit, 140 MSPS monolithic analog interface optimized for capturing RG B graphics signals from personal computers and workstations. Its 140 M SPS encode rate capability and full power analog bandwidth of 300 MHz supports resolutions up to SXGA (1280 x 1024 at 75 Hz).

The AD 9883A includes a 140 MHz triple ADC with internal

1.25 V reference, a PLL, and programmable gain, offset, and clamp control. The user provides only a 3.3 V power supply, analog input, and Hsync and CO A ST signals. Three-state CMOS outputs may be powered from 2.5 V to 3.3 V.

The AD9883A’s on-chip PL L generates a pixel clock from the Hsync input. Pixel clock output frequencies range from 12 MHz to

140 MHz. PLL clock jitter is 500 ps p-p typical at 140 MSPS. When the CO AST signal is presented, the PLL maintains its output frequency in the absence of Hsync. A sampling phase adjustment is provided. Data, Hsync, and clock output phase relationships are maintained. The AD9883A also offers full sync processing for composite sync and sync-on-green applications.

A clamp signal is generated internally or may be provided by the user through the CLAMP input pin. This interface is fully programmable via a 2-wire serial interface.

Fabricated in an advanced CM OS process, the AD9883A is provided in a space-saving 80-lead LQFP surface-mount plastic package and is specified over the 0°C to 70°C temperature range.

REV. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: Fax:

PW1231A

Product Specification

General

The PW1231A is a high-quality, digital video signal processor that incorporates Pixelworks' patented deinterlacing, scaling, and video enhancement algorithms. The PW1231A accepts industry-standard

video formats and resolutions, and converts the input into

many desired output formats.The highly efficient video algorithms result in excellent quality video.

The PW1231A combines many functions into a single device, including a memory controller, auto-configuration, and others. This high level of integration enables simple, flexible, cost-effective solutions that require fewer components.

Crystal

Video

PW1231A

System Block Diagram

Video

Decoder

PW1231A

PW1231AL

SD RAM

Digital

Output

Features

• Built-In Memory Controller

• Motion-Adaptive Deinterlace Processor

• Intelligent Edge Deinterlacing

• Digital Color/Luminance Transient Improvement (DCTI/DLTI)

• Interlaced Video Input Options, including NTSC and PAL

• Independent horizontal and vertical scaling

• Copy Protection

• Two-Wire Serial Interface

Applications:

For use with Digital Displays

• Flat-Panel (LCD, DLP) TVs

• Rear Projection TVs

• Plasma Displays

• LCD Multimedia Monitors

• Multimedia Projectors

Device Applic ation Package

PW1231A

PW1231AL

NOTE: “ L” denotes lead (Pb) free

Up to XGA 160-pin PQF

p ix e lw o r k s

8100 SW Nyberg Road

Tualatin, OR 97062 USA P/N 001-0097-00 Rev B

Telephone: 503.612.6700 J uly 2003

www^xelwoi^s.com PRELIMINARY CONFIDENTIAL

DATA SHEET

MOS INTEGRATED CIRCUIT

THREE-DIMENSIONAL Y/C SEPARATION LSI WITH ON-CHIP MEMORY

DESCRIPTION

The ^PD 64083 realizes a high precision Y/C separation and a noise reduction by the three-dimension signal

processing for NTSC signal.

This product has the On-chip 4-Mbit mem ory for flame delay, 2ch of high precision internal 10-bit A/D converter, and

adapting 10-bit signal processing (only for lum inance signal) and high picture quality. The ^PD64083 is completely single-chip system of 3D Y/C separation.

This LSI includes the Wide Clear Vision ID signal (Japanese local format) decoder and ID-1 signal decoder.

FEATURES

• On-chip 4-Mbit fram e delay memory.

• 4 Operation mode (Compatible to the ^PD64082) Motion adaptive 3D Y/C separation (for Com posite video input) Frame recursive Y/C NR (for Y/C separated video input) Frame com b type YNR + 1H delayed C signal (for Y/C separated video input)

2D Y/C separation + Frame recursive Y/C NR (for Composite video input)

• Embedded A/D converter (2ch), D/A converter (2ch), clock generator.

• Embedded Y coring, Vertical enhancer, Peaking filter, and Noise detector.

• Embedded W CV-ID decoder and ID-1 decoder.

• I2C bus control.

• Dual power supply of 2.5 V and 3.3 V. For digital : DVdd = 2.5 V For analog : AVdd = 2.5 V For DRAM : DVddram = 2.5 V For I/O : DVddio = 3.3 V

ORDERING INFORMATION

Part number

^PD64083GF-3B A

100-pin plastic QFP (14 x 20)

Package

Document No. S15849EJ1V0DS00 (1st edition) Date Published January 2002 NS CP (K) Printed in Japan

PRELIMINARY DATA SHEET VPC 323xD

Comb Filter Video Processor

1. In troduction

The VPC 323xD is a high-quality, single-chip video front-end, which is targeted for 4:3 and 16:9, 50/60-Hz and 100/120 Hz TV sets. It can be combined with other members of the DIGIT3000 IC family (such as DDP 331x) and/or it can be used with 3rd-party prod ucts.

The main features of the VPC 323xD are

- high-performance adaptive 4H comb filter Y/C sepa rator with adjustable vertical peaking

- multi-standard color decoder PAL/NTSC/SECAM

including all substandards

- four CVBS, one S-VHS input, one CVBS output

- two RGB/YCrCb component inputs, one Fast Blank (FB) input

- integrated high-quality A/D converters and associ

ated clamp and AGC circuits

- multi-standard sync processing

- linear horizontal scaling (0.25 ... 4), as well as non-linear horizontal scaling ‘Panoramavision'

- PAL+ preprocessing

- peaking, contrast, brightness, color saturation and tint for RGB/YCrCb and CVBS/S-VHS

- high-quality soft mixer controlled by Fast Blank

- PIP processing for four picture sizes (1-, 1-,

36 of normal size) with 8 -bit resolution

1 6 , or

- 15 predefined PIP display configurations and expert

mode (fully programmable)

- control interface for external field memory

- I2 C-bus interface

- one 20.25-MHz crystal, few external components

- 80-pin PQFP package

1.1. System A rchitectu re

Fig.1-1 shows the block diagram of the video proces

sor

- line-locked clock, data and sync, or 656-output interface

c i n o

VIN1 O VIN20

VIN30 VIN40-

VOUTO

RGB/

YCrCb

FBO

RGB/q -

YCrCb

Y OUT

LL Cock H Sync V Sync AVO

Fig. 1 -1 : Block diagram of the VPC 323xD

Micronas

HDH

20.25 MHz I2C Bus

Sil 161B PanelLink® Receiver Data Sheet

August 2002

General D escription

The SiI 161B receiver uses PanelLink Digital technology to support high-resolution displays up to

UXGA (25-165MHz). This receiver supports up to true color panels (24 bits per pixel, 16M colors) with both one and two pixels per clock.

All PanelLink products are designed on a scaleable

CMOS architecture, ensuring support for future performance enhancements while maintaining the

same logical interface. System designers can be

assured that the interface will be stable through a number of technology and performance generations.

PanelLink Digital technology simplifies PC and display interface design by resolving many of the system level issues associated with high-speed mixed signal design, providing the system designer with a digital interface

solution that is quicker to market and lower in cost.

Features

Low Power Operation: 280mA max. current consumption at 3.3V core operation

Time staggered data output for reduced ground

bounce and lower EMI Sync Detect feature for Plug & Display Cable Distance Support: over 5m with twisted pair, fiber-optics ready ESD tolerant to 5kV (HBM on all pins) Compliant with DVI 1.0 (DVI is backwards compatible with VESA® P&DTM, FPDI-2™ and DFP) HSYNC de-jitter circuitry enables stable operation even when HSYNC contains jitter

Low power standby mode Automatic entry into standby mode with clock detect circuitry

Standard and Pb-free packages (see page 25).

O

Pr e l im in a r y Pr o d u c t S p e c if ic a t io n

o

Z86229

N

T o t a ll y L o g ic a l

FEATURES

Speed Pin C o u n t/ Standard On-Screen Display Program

Devices (M Hz) Package Types Tem p. Range & Closed Captioning Rating Time of Day

Z86229 V 2 18-Pin DIP, SOIC 0°C to +70°C Yes Yes Yes

N T SC Line 2 1 CC D Decod er

Automatic Data Extraction

Complete Stand-Alone Line 21 Decoder for Closed- Captioned and Extended Data Services (XDS)

Preprogrammed to Provide Full Compliance with EIA-608 Specifications for Extended Data Services

Automatic Extraction and Serial Output of Special XDS Packets (Time of Day, Local Time Zone, and Program Blocking)

Programmable XDS Filter for a Specific XDS Packet Cost-Effective Solution for NTSC Violence Blocking

inside Picture-in-Picture (PiP) Windows

GENERAL DESCRIPTION

Capable of processing Vertical Blanking Interval (VBI) data from both fields of the video frame in data, the Z86229 Line 21 Decoder offers a feature-rich solution for any tele vision or set-top application. The robust nature of the Z86229 helps the device conform to the transmission format defined in the Television Decoder Circuits Act of 1990, and in accordance with the Electronics Industry Association

specification 608 (EIA-608).

The Line 21 data stream can consist of data from several data channels multiplexed together. Field 1 consists of four data channels: two Captions and two Texts. Field 2 consists of five additional data channels: two Captions, two Texts, and Extended Data Services (XDS). The XDS data structure is

Minimal Communications and Control Overhead Pro vide Simple Implementation of Violence Blocking, Closed Captioning, and Auto Clock Set Features

Programmable, On-Screen Display (OSD) for Creat ing Full Screen OSD or Captions inside a Picture-in- Picture (PiP) Window

User-Programmable Horizontal Display Position for easy OSD Centering and Adjustment

I2C Serial Data and Control Communication

Supports 2 Selectable I C Addresses

defined in EIA-608. The Z86229 can recover and display data transmitted on any of these nine data channels.

The Z86229 can recover and output to a host processor via the I2C serial bus. The recovered XDS data packet is further defined in the EIA-608 specification. The on-chip XDS fil ters in the Z86229 are fully programmable, enabling recov ery of only those XDS datapackets selected by the user. This functionality allows the device to extract the required XDS information with proper XDS filter setup for compatibility in a variety of TVs, VCRs, and Set-Top boxes.

In addition, the Z86229 is ideally suited to monitor Line 21 video displayed in a PiP window for violence blocking, CCD, and other XDS data services. A block diagram of the Z86229 is illustrated in Figure 1.

DS005103-0601

1

PRELIMINARY DATA SHEET

MSP 34xOG

Multistandard Sound P rocessor Family

Release Note: Revision bars indicate significant chan ges to the previous edition. The hardware and software description in this docum ent is valid for the MSP 34xOG version B8 and following versions.

1. Introduction

The MSP 34xOG family of single-chip Multistandard

Sound Processors covers the sound processing of all

analog TV-Standards worldwide, as well as the NICAM digital sound standards. The full TV sound processing, starting with analog sound IF signal-in, down to pro

cessed analog AF-out, is performed on a single chip.

Figure 1-1 shows a simplified functional block diagram

of the MSP 34xOG. This new generation of TV sound processing ICs now

includes versions for processing the multichannel tele vision sound (MTS) signal conforming to the standard

recommended by the Broadcast Television Systems

Committee (BTSC). The DBX noise reduction, or alter

natively, Micronas Noise Reduction (MNR) is per formed alignment free.

Other processed standards are the Japanese FM-FM

multiplex standard (EIA-J) and the FM Stereo Radio standard.

Current ICs have to perform adjustment procedures in order to achieve good stereo separation for BTSC and EIA-J. The MSP 34xOG has optimum stereo perfor mance without any adjustments.

All MSP 34xxG versions are pin compatible to the

MSP 34xxD. Only minor modifications are necessary

to adapt a MSP 34xxD controlling software to the

MSP 34xxG. The MSP 34xOG further simplifies con

trolling software. Standard selection requires a single

l2C transmission only.

The MSP 34xOG has built-in automatic functions: The

IC is able to detect the actual sound standard automat ically (Automatic Standard Detection). Furthermore, pilot levels and identification signals can be evaluated internally with subsequent switching between mono/

stereo/bilingual; no l2C interaction is necessary (Auto

matic Sound Selection).

The MSP 34xOG can handle very high FM deviations

even in conjunction with NICAM processing. This is especially important for the introduction of NICAM in China.

The ICs are produced in submicron CMOS technology. The MSP 34xOG is available in the following packages:

PLCC68 (not intended for new design), PSDIP64, PSDIP52, PQFP80, and PLQFP64.

Sound IF1 o-

Sound IF2 &

SCART3

SCART4

MONO »

Fig. 1 - 1: Simplified functional block diagram of the MSP 34xOG

Loud

speaker

Sound

Processing

Headphone

Sound

Processing

DAC

SCAR T

Output

Select

Lou d

C

speaker

«0 Subwoofer

Headphone

SCART1

c

SCART2

c

Micronas

MODEL : SG" HD D3.1 PDP

1,269cm (50 Inch) Wide Plasma Display Module

Quality innovation Team

CONTENTS

1.O ve rview

1-1 Model Name of plasma Display 1-2 External View 1-3 Specifications

2. Pre c a u tion

2-1 Handling Precaution for Plasna Display, 2-2 Safety Precautions for Service (Handling, prevention of a electrical shock, measure against

power outage, etc)

3. N a m e & Fu nction

3-1 Layout of Assemblies 3-2 Block Diagram:

3-3 Main function of Each Assembly 3-4 Product/Serial Label Location

4. O peration c h ec k in g a fter rectification

4-1 Flow chart 4-2 Defects , Symptoms and Detective Parts

5. D isa sse m b lin g / A s sem bling

5-1 Tools and m easurem ent equipment 5-2 Exploded View 5-3 Disassembling & Re-assembling

6. O peration C h e ck a fter R ep air Se rv ic e

6-1 Check Item 6-2 Check Procedure

__

Formation and Specification of Module

^ 1'k * /vi»» am ^ \ • /

1

. O ver vi ew

1-1 Model Name of Plasm a Display

MODEL : 50HD” D3.1 PD P (S50HW-X D03)

1-2 External View

[ M3 = X Board + Y Board + Logic Board + PSU + SUB PSU ]

1-3 Points of Screw Mount

Trouble Shooting

Blue Dot : SC R EW 4X12 Red Dot : S C R EW 3X 10

1-4 Specifications

No Item S p e cification

1 Pixel

2 Number of Cells

3 Pixel Pitch

4

Cell Pitch

5 Display size

Horizontal 1366 X Vertical 768 pixels

(1 pixel = 1 R,G,B cells)

Horizontal 4,098 X Vertical 768 cells

Horizontal 810m X Vertical 810m

R G

B

Horizontal 270m X Vertical 810m Horizontal 270m X Vertical 810m Horizontal 270m X Vertical 810m

Horizontal 1106.46m X Vertical 622.08m

6 Screen size Diagonal 50" Color Plasma Display Module

7 Screen aspect 16 : 9 8 Display color 16.77 million colors

Over 160°

9 Viewing angle

(Angle with 50% and greater brightness perpendicular to PDP

module)

10 Dimensions

1184(W) x 700 (H) x 60.1 (D) m 11 Weight Module 1 About 18.0 kg 12 Packing weight Module 1 13 Packing size

L 760 * W 1465 * H 1106(mm) / 10pcs/BOX

140kg ± 5kg (including modules) /

5pcs/BOX

60Hz/ 50Hz, LVDS

Broadcasting reception

14

Vertical frequency

and

Video/Logic Interface

Samsung SDI Co. Ltd

2 . P re c a u t io n

A/S Manual Plasna Dispáty Mot

** To p rev en t th e r isks o f unit d am a ge , electrical s h o c k a n d radiation , tak e th e follo w in g sa fe ty, se rv ice , and ESD p reca u tion s.

2-1 Handling Precautions for P lasm a Display

PDP module use high voltage that is dangerous to human. Before operating PDP, always check the dust to prevent circuit short. Be careful touching the circuit device when power is on.

PDP module is sensitive to dust and humidity. Therefore, assembling and disassembling must be done in no dust place.

PDP module has a lot of electric devices. Service engineer must wear equipment(for example , earth ring) to prevent electric shock and working clothes to prevent electrostatic.

■ PDP module use a fine pitch connector which is only working by exactly connecting with flat cable. Operator must pay attention to a complete connection when connector is reconnected after repairing.

■ The capacitor's remaining voltage in the PDP module's circuit board temporarily remains after power is off. Operator must wait for discharging of remaining voltage during at least 1 minute.

2-2 Safety Precautions for Service (Handling, prevention of a electrical shock, m easu re

against power outage, etc)

( Safety P recautions )

■ Before replacing a board, discharge forcibly The remaining electricity from board.

■ When connecting FFC and TCPs to the module, recheck that they are perfectly connected.

■ To prevent electrical shock, be careful not to touch leads during circuit operations.

■ To prevent the Logic circuit from being damaged due to wrong working, do not connect/disconnect signal cables during circuit operations.

le

■ Do thoroughly adjustment of a voltage label and voltage-insulation.

■ Before reinstalling the chassis and the chassis assembly, be sure to use all protective stuffs including a nonmetal controlling handle and the covering of partitioning type.

■ Caution for design change : Do not install any additional devices to the module, and do not change the electrical circuit design.

■ For example: Do not insert a subsidiary audio or video connector. If you insert It, It cause danger on safety. And, If you change the design or insert, Manufactor guarantee

■ Examine carefully the cable status if it is twisted or damaged or displaced. Do not change the space between parts and circuit

board. Check the cord of AC power preparing damage.

■ Product Safety Mark : Some of electric or

implement material have special characteristics invisible that was related on safety. In case of the parts are changed with new one, even though the Voltage and Watt is higher than before, the Safety and

Protection function will be lost.

■ The AC power always should be turned off, before next repair..

will be not effect. .

■ If any parts of wire is overheats of damaged, replace it with a new specified one immediately, and identify the cause of the problem and remove the possible dangerous factors.

( Precaution when repairing ESD )

■ There is ESD which is easily damaged by electrostatics.(for example Integrated circuit, FET ) Electrostatic damage rate of product will be reduced by the following technics

■ Check assembly condition of screw, parts and wire arrangement after repairing. Check whether the material around the

parts get damaged.

electric by ground connection, or must wear the antistatic wrist-belt and ring. ( It must be operated after removing dust on it - It comes under precaution of electric shock.)

■ Before handling semiconductor parts/assembly, must remove positive

Samsung SDI Co. Ltd. A/S Manual Plasma Display Mo

After removing ESD assembly, put on it with aluminum stuff on the conductive surface to prevent charging.

Do not use chemical stuff using Freon. It generates positive electric that can damage ESD.

Must use a soldering device for ground-tip when soldering or de-soldering ESD.

Must use anti-static solder removal device. Most removal device do not have antistatic which can charge a enough positive electric enough damaging ESD.

Before removeing the protective material

protective material into contact with the

chassis or assembly that the ESD is to be

installed on.

■ When handing an unpacked ESD for replacement, do not move around too much Moving (legs on the carpet, for example)

generates enough electrostatic to damage the ESD.

■ Do not take a new ESD from the protective

case until the ESD is ready to be installed.

Most ESD have a lead, which is easily

short-circuited by conductive materials (such as conductive foam and aluminum)

from the lead of a new ESD, bring the

No. Code No. Location Name

1 LJ44-00065A Main PUS ASSY PCB PSU 2 LJ44-00099A SUB-PSU ASSY PCB SUB-PSU 3 LJ92-00949C LOGIC-MAIN Board ASSY PCB LOGIC MAIN 4 LJ92-00852A X-MAIN Driving Board ASSY PCB X MAIN 5 LJ92-00853A Y-MAIN Driving Board ASSY PCBY MAIN 6 LJ92-00917A LOGIC E BUFFER Board ASSY PCB BUFFER 7 LJ92-00918A LOGIC F BUFFER Board ASSY PCB BUFFER 8 LJ92-00919A LOGIC G BUFFER Board ASSY PCB BUFFER 9 LJ92-00920A LOGIC H BUFFER Board ASSY PCB BUFFER

10 LJ92-00921A LOGIC I BUFFER Board ASSY PCB BUFFER 11 LJ92-00922A LOGIC J BUFFER Board ASSY PCB BUFFER 12 LJ92-00880A Y-BUFFER (UPPER) Board ASSY PCB BUFFER 13 LJ92-00881A Y-BUFFER (DOWN) Board ASSY PCB BUFFER 14 LJ92-00959A SUB-R ASSY PCB BUFFER 15 LJ92-00923A SUB-L ASSY PCB BUFFER 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

3809-001526 3809-001516 3809-001414 3809-001414 3809-001414 3809-001415 3809-001415 3809-001415

LJ39-00121A

LJ39-00122A

LJ39-00113A LJ39-00118A

LOGIC + Y-MAIN FFC CABLE-FLAT

LOGIC + X-MAIN FFC CABLE-FLAT

SUB R + LOGIC FFC CABLE-FLAT

SUB L + LOGIC FFC CABLE-FLAT

LOGIC BUF(I) + LOGIC BUF(J) (UP) FFC CABLE-FLAT

LOGIC + LOGIC BUF(E)(Down) FFC CABLE-FLAT LOGIC + LOGIC BUF(F)(Down) FFC CABLE-FLAT

LOGIC + LOGIC BUF(G)(Down) FFC CABLE-FLAT LOGIC BUF(E) + LOGIC BUF(F) LEAD CONNECTOR LOGIC BUF(F) + LOGIC BUF(G) LEAD CONNECTOR

LOGIC BUF(H) + LOGIC BUF(I) LEAD CONNECTOR LOGIC BUF(I) + LOGIC BUF(J) LEAD CONNECTOR

Y-MAIN + LOGIC BUF(H) LEAD CONNECTOR Y-MAIN + LOGIC BUF(E) LEAD CONNECTOR

PSU + LOGIC MAIN LEAD CONNECTOR

PSU + LOGIC BUF(E) LEAD CONNECTOR 32 33 34 35

LJ39-00177A LJ39-00175A LJ39-00173A LJ39-00178A

PSU + LOGIC BUF(H) LEAD CONNECTOR

PSU + Y-MAIN LEAD CONNECTOR PSU + X-MAIN LEAD CONNECTOR

PSU + SUB PSU LEAD CONNECTOR

1. L-Main 2.X-Main

9. J-Buffer 10. Y-Buffer (lower)

3-2 BLOCK DIAGRAM

3-2-1 BLOCK DIAGRAM FOR DRIVE CIRCUIT OPERATION

To be Updated

3-2-2 Block Diagram for Logic circuit Block Diagram

DATA_R

a(9)Bits

DATA_G

a(9)Bits

DATA B

X Pulse

Vb

Reference

-Vcc V o lta g e fo r Lo g ic C o n trol

-V dd

-Va V o lta g e f o r ad d ress p u lse

-Vsc _ l

-V scan V o ltag e f o r scan h ig h

-Vb V o lta g e f o r X b ia s

-Vs e t

V o ltag e f o r FET d riv e r

V o ltag e f o r s u s ta in low

V o ltag e f o r Y ramp p u lse

3-3 Main function o f Each Assem bly

■ X-main board : The X-main board generate a drive signal by switching the FET in synchronization with logic

main board timing and supplies the X electrode of the panel with the drive signal through the connector.

1) Maintain voltage waveforms (including ERC)

2) Generate X rising ramp signal

3) Maintain Ve bias between Scan intervals

■.Y -main board : The Y-main board generate a drive signal by switching the FET in synchronization with the logic

Main Board timing and sequentially supplies the Y electrode of the panel with the drive signal

through the scan driver IC on the Y-buffer board. This board connected to the panel's

Y terminal has the following main functions.

1) Maintain voltage waveforms (including ERC)

2) Generate Y-rising Falling Ramp

3) Maintain V scan bias

■ Logic main board : The logic main board generates and outputs the address drive output signal and the X ,Y

drive signal by processing the video signals. This Board buffers the address dirve output signal and feeds it to the address drive IC (COF module)

(video signal- X Y drive signal generation , frame memory circuit / address data rearrangement)

■.Logic buffer(E,F) : The logic buffer transmits data signal and control signal.

■.Y-buffer board (Upper, Lower) : The Y-buffer board consisting of the upper and lower boards supplies the

Y-terminal with scan waveforms. The board comprises 8 scan driver IC's (ST microelectronics STV 7617 : 64 or 65 output pins) , but 4 ICs for the SD class

■.AC Noise Filter : The AC Noise filter has function for removing noise(low Frequency) and blocking surge.

It effects Safety standards(EMC,EMI)

■.TCP( Tape Carrier Package ) : The TCP applies Va pulse to the address electrode and constitutes address

discharge by the potential difference between the Va pulse and the pulse applied to the Y electrode. The TCP comprise 4 data driver Ics(STV7610A

:96 pins output pins) 7 TCPs are required for signal scan

3-4 PRODUCT/ SERIAL LABEL LOCATION

Serial No.

Voltage label

3-4-1 Serial No.

2 6 1 4 0 8 07 0 8 6 5

Serial No : 0001~9999 Date : Month

1i1

T

01

CM

Year : 00(2000)

~99(2099)

Line No : 1 ~ 9

(0:Pilot Line)

Type : 02~48 (e x . 5 0 H D v 3 :2 6 )

(Step of even)

4 . O P E R A T IO N C H E C K IN G A F T E R R E C T IF IC A T IO N

4-1 Flow chart

* A/S Check Point *

1 .Checking the voltage for each assembly

L

j :

2. Judging the Logic board working or not [Vsync, 3.3 V, 5 V]

j d

3. Adjusting the output signal through test points

4. Checking the panel’s crack

4-1-1 No voltage output

OK

NG

Reconnect it

PSU Voltage ch eck

D5V; 5V Check Vs ; 170V Check Va ; 72V Check Vset; 18QV Check Vscan;-9Q V C heck Vb; 155 V Check Vcc; 1 5V Check Vcan_h; 2 5V Check D3V3; 3.3V Check 9Vstandby;9V Check Fuse 8QQ1/8QQ2/8QQ3

—

On/OFF Relay (RLY 8001, 8002 Acts?

PSU

LED (Green) Replace

w

8001, 8002 off

w

PSU

OK

r

1

Go to 4-1-2 No Display

4-1-2 NO display (operating Voltage but an image doesn’t exist on Screen)

=» No Display is related with Y-MAIN, X-MAIN, Logic Main and so on.

This page shows you how to check the boards, and the following pages show you how to find the defective board.

N o D i s p l a y

L o g ic M a in

[Vsync Blinks]

LED 1

Y - M a i n

X - M a in B r o k e n p a n e l

Replace Logic B’d

Check

Q5007/Q502

©

Q5011 /Q50112/Q5027

©

Q5009/Q5008/Q5030

©

Q5013/Q5014/Q5029

©

Q5018/Q5019/Q5028

©

Replace Y-B’d

X-Main

Fuse

OK

OPEN

►

SHORT

Replace X -B’d

Check

Q4004 /Q4005/Q4021

©

Q4013/Q4019

©

Q4006/Q4020

©

Q4009/Q4010/Q4022

©

Q4014/Q4015

©

Q4016/Q4017/Q4023

©

4-1-3 Abnormal D isplay (Abnormal Image is on Screen. (except abnormality in Sustain or Address)

FET

Replace X -B’d

Replace PDP

=» Abnormal Display is related with Y-MAIN, X-MAIN, Logic Main and so on.

This page shows you how to check the boards, and the following pages show you how to find the defective board.

Y-Main

OK

Fuse

X-Main

OPEN

Replace Y-B’d

Replace

OK

Check © Q4004 /Q4005/Q 4021 © Q 4 013/Q4019 © Q 4 006/Q4020 © Q 4 0 09/Q4010/Q4022 © Q 4 014/Q4015 © Q 4 0 16/Q4017/Q4023

Fuse

OPEN

Replace X -B’d

[Logic Main]

Vsync Blinks

LED 1

(Motion of Vsync)

[Y-FPC]

Sustain Open

OK

Done

(Defect is from buffer)

Replace PDP

4-1-5 Sustain Short ( some horizontal lines appear to be linked on Video )

OK

4-1-6 A ddress Open ( some vertical lines don’t exist on screen )

=» Address Open is related with Logic Main, Logic Buffer, FFC, TCP and so on.

This page shows you how to check the boards, and the following pages show you how to find

the defective board.

Address Open

=» Line Open =» Data Block Open =» TCP Block Open

[ Logic Main/FFC ]

Chanaina some Darts

[ Logic Buffer ]

Changing necessary

Parts (E /F/G)

NG

Replace

NG

4-1-7 A ddress Short (som e vertical lines appear to be linked on screen

=» Address Short is related with Logic Main, Logic Buffer, FFC, TCP and so on.

This page shows you how to check the boards, and the following pages show you how to find

the defective board.

Logic Main/

Address Buffer

(E /F/G/H/I/J)

Done

OK

What is the status of oDen?

NG

4-2 DEFECTS, SYM PTONS AND DETECTIVE PARTS

Condition Name Description Related Board

■ No Voltage Output Operating Voltages don't exist. PSU

■ No Display

■ Abnormal Display

■ Sustain Open

■ Sustain Short

■ Address Open some vertical lines don't exist on screen Logic Main, Logic Buffer, FFC,TCP

■ Address Short

Operating Voltages exist, but an Image

doesn't exist on screen

Abnormal Image(not open or short) is on

screen.

some horizontal lines don't exist on

screen

some horizontal lines appear to be

linked on screen

some vertical lines appear to be linked

on screen

Y-MAIN , X -M AIN, Logic Main, Cables

Y-MAIN , X -M AIN, Logic Main

Scan Buffer, FPC of X / Y

Logic Main, Logic Buffer ,FFC,TCP

♦ Defect: Address(vertical stripe) Open ♦ Defect: Address(vertical stripe) Short

■ Symptom : A line or block does not light up in address

electrode direction.(1 line ,block open)

foreign material./electrostatic/ TCP defect

■ Symptom: Another color simultaneously appears because adjacent

data recognizes the single pattern signal

■ Cause

0 manufacturing : Panel electrode short / Foreign material

conductive foreign object i nside TCP

defect

♦ Defect: Address output error ♦ Defect: Sustain(horizontal stripe) Open

■ Symptom.: A defect other than address open

and short Data printout signal error occurring at certain Gradation or pattern

■ Symptom : One or more line do not light up in Sustain direction

FPC pressure defect

♦ Defect: Sustain(horizontal stripe) Short ♦ Defect: Dielectric material layer damage

■ Symptom : Combined or adjacent lines are short in sustain direction. The l ine appear brighter

than other at Ramp gradation pattern or l ow

gradation patter

■ Symptom: Burn caused by the damage of address bus dielectric layer appears in the panel discharge/non discharge area. sustain also open/short occurs by the damage of address sustain printout

■ Cause

material.

■ Cause : layer uneven / abnormal voltage / foreign material

repair failed

♦ Defext: F/White low discharge ♦ Defect: Weak discharge

■Symptom : Low discharge caused by unstable cells occurring at full white pattern if high

(60 degree) or normal temparature.

■Symptom : Normal discharge but cells appear darker due to weak light emission occurring mainly at low (5 degree) Full white/Red/Green/Blue pattern or gradation pattern

■ Cause

cell pitch/phosphor

■ Cause

aging condition

♦ Defect : panel damage ♦ Defect: Exhaust pipe damage

■ Symptom : Panel crack or break. No image appears in some cause depending on the damaged parts and damage level.

■ Symptom. : Crack in break if exhaust pipe

an image i s partially l acking or the panel noise occurs depending on the damaged parts and with the passage of time

■ Cause

■ Cause : Careless panel handling

5. Disassembling / Assembling

5-1 Tools and measurement equipment

5-1-1. Tools

1) (+) type Screw Drivers : to screw the screws

2) Air Blower

3) Earth Ring

4) Small Driver : to adjust potentiometer

5) Dummy Discharge Resistor : 2.4kOhm/10W

5-1-2. M easuring Equipm ent

1) Oscilloscope : 500MHz sampling

2) Probe : 10:1

3) Digital Multi-meter

4) Signal Generator

5-3 D isassembling & Re-assem bling

5-3-1 D isassem bling & Re-assembling of FPC (Flexible Printed Circuit)

and Y-Buffer(U pper and Lower)

1. Removal procedures

1) Full out the FPC from Connector by holding the lead of the FPC with hands.

2. Assembling Procedures

5-3-2 Assembling & D isassembling of Flat Cable Connector of X-Main Board

1. Disassembling Procedure

1) Pull out the clamp of

connector.

2. Assembling Procedure

1) Put the Flat cable into the connector press down lightly until locking sound (“Dack”) comes out.

2) Pull Flat cable out

press down lightly.

3) Turn the Flat

cable reversely.

5-3-3 Assembling & Disassembling the FFC and TCP from Connector

1. Disassembling of TCP

1) Open the clamp carefully. 2) Pull the TCP out from Connector.

2. Assembling o f TCP

1) Put the TCP into the Connector carefully 2) Close the clamp completely.

( The sound (“ Dack”) comes out. )

* Notice : TCP and Connector was connected surely.

* Notice :

1) Checking whether the foreign material is on the Connector inside before assembling of TCP.

2) Be careful do not get a damage on the board by ESD during handling of TCP.

3. Misassembling of TCP

1) The misassembling of TCP is the cause of defect.

4. Checking m ethod of misassembling of TCP

S. A ssem bling & Disassembling of FFC

( This i s the photo of the assembling of FFC )

The procedure of assembling and disassembling of FFC is the same as TCP.

5-3-4 Exchange of LBE, LBF, LBG board

( Photo 1 )

( Photo 2 )

1) Remove the screws in order of Center - Left Side - Right Side from heat sink and then get rid of heat sink. ( Photo 1 )

2) Remove the TPC, FFC and power cable from the connectors.

3) Remove all of the screws from defected board.

4) Remove the defected board.

5) Replace the new board and then screw tightly.

6) Get rid of the foreign material from the connector.

7) Connect the TCP,FFC and power cable to the connector.

8) Reassemble the TCP heat sink.

9) Screw in order of Right Side - Left Side - Center ( Photo 2 ) If you screw too tightly, it is possible to get damage on the Driver IC of TCP.

5-3-5 E xchange YBU, YBL and YM board

1) Separate all of the FPC connector of YBU (Y-Buffer upper) and YBL (Lower). ( Photo 1 )

2) Separate all of the connector of CN5001 and CN5008 from Y-Main.

3) Loosen all of the screws of YBU, YBL and YM.

4) Remove the board from chassis.

5) Remove the connector of CN5006 and CN5007 among YBU, YBL and YM.

6) Remove the YBL and YBU from Y-main.

7) Replace the defected board.

8) Reassemble the YBU and YBL to the Y-Main.

9) Connect the connector of CN5006 and CN5007 among YBU, YBL and YM.

10) Arrange the board on the chassis and then screw to fix.

11) Connect the FPC and YM of panel to the connector.

12) Supply the electric power to the module and then check the waveform of board.

13) Turn off the power after the waveform is adjusted.

6. Operation Check after Repair Service

6-1 Check Item

Check Item

Speci f ication Remarks

TCP Assembling

cond ition

Module

assemble

check

Drive board Y BUFFER Logic & Logic

Securely connected or

tightened

Buf fer Harness Securely connected Material Mixing No material mixing

6-2 C heck Procedure

1) Visual check as following a. Assembling condition of module.

b. No problem on the connection of module.

c. The grounding and easily short-circuited parts are not damaged.

2) Check the Dip Switch is setting [SW2000 ]

3) Turn on the power to PDP module, and then check that LED lights up and the SET is working well.

4) Check the power voltage after turn on the power, and then check the Display condition by tapping slightly the Y-FPC 2 or 3 times.

5) Check whether something wrong during Full White Pattern period.

6) If something wrong, each voltage should be set to the standard voltage by using Multi-Tester and adjusting tools.

7) Adjust the waveform, using Oscilloscope for the waveform adjusting point.

8) Check the discharge of front panel by changing the image for each pattern.

9) Check the Low-discharge, Over-discharge and panel condition by adjusting the Pattern Generator Level.

10) Discharge still remain send back to SDI

PDP50HAA-C01 AKAI PDP 50" SDI-XGA AC100-240V USA PDP5006H

Item Component Description/Country Origin Unit

—. E L E C T PA R T

1 E2301-559001 IC TDA8946J AUDIO AMPLIFIER PCS 2 E3213-011001 SOCKET ANT F/RCA PCS 3 E3403-004001 TUBE SUMITUBE D5.0 BLK 600V M 4 E3413-003001 CABLE COAXIAL RCA/F FOR USA L=45 PCS 5 E3421-926031 WIRE ASSY 2 .5 11P/11P FOR (SDI 50" L PCS 6 E3421-926032 WIRE ASSY 2.5 10P/7P+3P FOR (SDI 50" PCS 7 E3421-926033 WIRE ASSY L=220MM 31P(SDI 50") (LVDS PCS 8 E6205-002003 DISPLAY PDP SDI-WXGA 50" (127CM) S5 PCS 9 E7801-056007 PCB ASSY MAIN 1VPC DVI CCD SDI (EROO PCS

10 E7801-056201 PCB ASSY TUNER NTSC PCS 11 E7801-057001 PCB ASSY SMPS 24/18V MPTO12A MEGMEET PCS 12 771-50SB03-01 IR RECEIVE PCB ASSY SB/EROOM PCS 13 771-42AF01-01 SPK JACK PCB ASSY E-ROOM PCS 14 774P50AA02-01 POWER ASSY 50AA/SDI STYLE B PCS 15 786-SW0402-02 AKAI WOOD SPEAKER ASSY W/POLYFOAM BL PCS 16 771-42D105-01

—. M EC H PA R T

1 244-34B811-01 GIFT BOX HANDLE 34B8 PCS 2 248-46D201-01 HANDLE FOR PLASMA PCS 3 263-42D101-01S POWER LENS 42D1 PCS 4 269-42D101-01L REMOTE LENS 42D1 PCS 5 322-42P101-01 REMOTE LENS RUBBER SPACER PDP-42TP1 PCS 6 322-42P102-01 POWER LENS RUBBER SPACER PDP-42TP1 PCS 7 322-42P103-01 SEPARATE RUBBER SPACER FOR REMOTE AN PCS 8 326-064510-50 SPONGE CUSHION 645X10X5.0MM W/ADHESI PCS 9 326-115010-50 SPONGE CUSHION 1150X10X5.0MM W/ADHES PCS

10 361-101261-01 CABLE TIE PCS 11 367-42D101-01 EDGE SADDLE 14MM 42D1 PCS 12 379-42P101-01 FILTER RUBBER BAG A PDP-42TP1 PCS 13 379-42P103-01 FILTER RUBBER BAR C 5.5X50X3.0MM W/ PCS 14 384-42D103-04H PVC SHEET FOR E-ROOM PCB USA PCS 15 387-50AA01-01H MODEL PLATE AKAI ENG PDP5006H PCS 16 388-42D103-01H CAUTION PLATE ENG 42D1 H PCS 17 388-42P101-01 PC SHEET FOR REMOTE PCB 42P1 94V0 PCS 18 388-42SB04-01H POWER PLATE SANSUI 42SB PCS

19 388-50AD01-01H SPEAKER PLATE FOR PDP50HAD PCS 20 400-50AA03-01 FRONT CABINET FOR SAMSUNG PANEL STYL PCS 21 402-50SB02-01S BACK COVER FOR 50" LG PCS 22 420-50SB02-01S MAIN BRACKET LEFT FOR 50" SAMSUNG T PCS 23 420-50SB03-01S MAIN BRACKET RIGHT FOR 50" SAMSUNG T PCS 24 423-50SB03-01S FILTER SUPPORT FOR SIDE PCS 25 423-50SB06-01S FILTER SUPPORT FOR TOP PCS

KEY PCB A SSY FOR TD1/EROOM

PCS

Quantity

Summary

1 1

0.5 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2

1 1 1 1 1

2 2

20

5 6 6

1 1 1 1 1 1 1 1 1 1

2

1

2e

42S-50SB07-01S FILTER SUPPORT FOR BOTTOM PCS

2?

424-50SB01-01S POWER PCB BRACKER (A) PCS

28

424-50SB02-01S POWER PCB BRACKET (B) PCS

29

42e-50S B 0l-0lS AV2 BRACKET PCS

S0

42e-50SB0A -0lS POWER BRACKET STYLE B PCS

S1

429-50AD07-01 REMOTE PCB BRACKET PCS

S2

429-50AD08-01S SUPPORT BRACKET PCS

SS

429-50SB0e-0lS SHIELD BOX BRACKET PCS

S4

429-50SB0A-01S CONNECT BRACKET STYLE B PCS

S5

4S0-42D102-01 HEAT SINK FOR E-ROOM 42D1 PCS

Se

436-42D113-01S TERMINAL SHEET FOR E-ROOM PCB USA PCS

S?

45?-42D101-01 CLAMP ID=4.SMM L=46M PCS

S8

45?-42D101-01 CLAMP ID=4.SMM L=46M PCS

S9

481-42D105-01 SHIELD BOX FOR USA RF 42D1 PCS

40

481-50SB01-01S SHIELD BOX FOR E-ROOM PCB PCS

41

48S-42D10S-01 SHIELD COVER FOR E-ROOM PCB 42D1 PCS

42

48S-42D104-01 SHIELD COVER TOP FOR 42D1 PCS

4S

48S-50SB11-01 SHIELD SHEET PCS

44

48e-50AD0l-0l NAME PLATE AKAI SIL/BLACK 50AD PCS

45

55S-002509-40A EMI SHIELD GASKET 25X9X4.0MM W/CONDU PCS

4e

55S-005009-25A SHIELD GASKET 50X9X2.5MM W/CONDUCTIV PCS

4?

553-006509-40A SHIELD GASKET 65X9X4.0MM W/CONDUCTIV PCS

48

55S-015009-40A EMI SHIELD GASKET 150X9X4.0MM W/COND PCS

49

55S-020009-40A SHIELD GASKET 200X9X4.0MM W/CONDUCTI PCS

50

55S-024509-40A SHIELD GASKET 245X9X4.0MM W/CONDUCTI PCS

51

55S-026009-40A EMI SHIELD GASKET 260X9X4.0MM W/COND PCS

52

55S-028009-40A EMI SHIELD GASKET 280X9X4.0MM W/COND PCS

5S

553-039509-10A SHIELD GASKET S95X9X1.0MM W/CONDUCTI PCS

54

55S-067009-40A EMI SHIELD GASKET 670X9X4.0MM W/COND PCS

55

55S-114009-40A EMI SHIELD GASKET 1140X9X4.0MM W/CON PCS

5e

554-0900S0-01 SHIELD CLOTH 90XS0MM W/CONDUCTIVE AD PCS

5?

568-119-

58

5e8-P4eT02-02 WARNING LB ENG 42SF NIL PCS

59

5?9-42D10S-02 ON/OFF LB ENG 42D1 NIL PCS

e0

5?9-42D105-01 PROTECTIVE EARTH LABEL FOR ESA 42TD1 PCS

e 1

579-50AA01-01 BAR CODE LABEL AKAI W/SERIAL NO PDP5 PCS

e2

579-50AA02-01 DANGER CAUTION LABEL PCS 579-50AA0S-01 PHOTO CARD FOR PDP5006 AKAI PCS

eS

579-50AD02-01 SERIAL NO/BAR CODE LABEL 50HA (USA) PCS

e4 e5

590-50AA01-01 WARRANTY CARD ENG AKAI PDP5006H PCS

ee

e01-S05008-00 MACH.SCREW CTS SX8 BZN + PCS

e?

e02-S0500e-00 MACH. SCREW PAN-WASHER SX6 B ZNP +H PCS

e8

e02-S0500e-10 MACH.SCREW WHR SX6 NIP + PCS

e9

e02-S0500e-10 MACH.SCREW WHR SX6 NIP + PCS

?0

e02-40?008-00 MECH. SCREW PAN-WASHER 4X8 B ZNP +H PCS

?1

e04-S05005-S0 MACH.SCREW BID SX5 BNI + PCS

?2

e04-S05008-10 MACH.SCREW BID SX8 NIP + PCS

SERIAL NO. LABEL PCS

73 604-407022-10 MECH. SCREW BINDING M4X22 W NIP +H PCS 74 604-601020-00 MACHINE SCREW BINDING M6X1.0PX20MM B PCS 75 60D-407010-40 MACH. SCREW W/SPRING WASHER M4.0X0.7 PCS 76 60D-508012-40 MACH. SCREW W/SPRING WASHER M5.0X0.8 PCS 77 610-300210-00 S-TAP.SCREW RND 3X10 A BZN + PCS 78 614-300210-10 S-TAP.SCREW BID 3X10 A NIP + PCS 79 623-401812-00 TAPING SCREW B-TYPE TRUSS 4X12 B ZNP PCS 80 624-302406-10 TAP SCREW B-TYPE BINDING 3.0X6 WNC + PCS 81 734-BM0304-01 SECC STAND BASE 50" W/PACKING BIG BO SET 82 844-50AD01-01 WOODEN PALLET 1545X1115X116 PCS 83 844-50AD02-01 WOOD PALLET 1545X745X116 PCS 84 900-50AA01-01 DISPLAY FILTER 50" OPTIMAX FOR SAMSU PCS

H . PACKING

1 300-50P101-02C POLYFOAM TOP 50TP1 PCS 2 300-50P102-02C POLYFOAM BOTTOM 50TP1 PCS 3 310-111404-07V POLYBAG 11"X14"X0.04 PCS 4 310-633810-02T POLYBAG 63"X38"X1.0MM W/WARNING &REC PCS 5 510-50AA01-04K GIFT BOX AKAI WHITE PDP5006H K PCS 6 511-42D102-01A ACCESSORY BOX PCS 7 512-50AD01-01 SHEET PCS 8 512-50AD02-01 SHEET 1545X945 PCS

9 518-50AD01-01K BOTTOM BOX PCS 10 580-50AA01-03 INSTRUCTION BOOKLET E FOR AKAI PDP50 PCS 11 E3404-157001 AC CORD UL 1.88M MET-4D7+SJT 16AWG/ PCS 12 E7301-011002 BATTERY AA R6P1.5V <2> PCS 13 790-002514-A3 AKAI REMOTE ASSY 42KEY 0025 USA BLACK PCS

8 6

27

4

2

7 24 22

1

0.3182

0.0227 1

1 1 1 1 1 1

0.6364

0.0454 1 1 1

2

1

If you forget y our V-Chip Password

- Omnipotence V-Chip Password: 1234.

- Press MENU button.

- Press Up, Down and CH+, CH-buttons to highlight "V-Chip" Control.

- Press OK button to pop up "INPUT PASSWORD".

- Use the Number buttons (0~9) to enter the omnipotence Password 1234.

- Press Down to highlight "Password change" Control.

- Press OK button to confirm and will pop up "Password Change" item.

- Change to your familiar Password again.

So f t w a r e u pg r ad e

- Connect the RS-232C input jack to an external control device (such as a computer) and software upgrade.

Type of connector; D-Sub 9-pin male

No. Pin name

1 No connection 2 RXD (Receive data) 3 TXD (Transmit data) 4 DTR (DTE side ready) 5 GND 6 DSR (DCE side ready) 7 RTS (Ready to send) 8 CTS (Clear to send) 9 No Connection

RS-232C configurations

7-wire configuration

(Standard RS-232C cable)

PC PDP

RXD TXD GND

DTR

DSR

RTS CTS

2 3 2 5 5 4 6 6 4

7 8

8 7

TXD RXD

3

RXD TXD GND GND DSR DTR DTR DSR CTS RTS

RTS CTS

3-wire configuration

(Not standard)

PC PDP

2 3 5 4 6 7 8

3 2 5 4 6 7 8

1

5

TXD RXD

GND

DTR DSR RTS CTS

D-Sub 9

Software upgrade Process

- Power Switch OFF.

- Connect the serial port of the control device to the RS-232 jack on the PDP back panel. RS-232C connection cables are not supplied with the PDP.

- Power Switch ON. The power indicator on the front of the panel should now display red, means

that the PDP is in standby mode.

- Copy the software (Flash Upgrader) to the computer.

- Open the software (Flash Upgrader.exe)

- Point "Flash" on the interface of the Flash Upgrader.exe.

- Press STANDBY button on the front panel or POWER button of Remote control, Power indicator

green, the PDP is in power ON mode, software start upgrader immediately.

- Waiting for the upgrader programing, when it is finished, the PDP will auto power on.

- After the upgrader is finished, shut down the power switch, take out the RS-232C connection

after the power indicator is extinguished.

Note: The computer and PDP must be keep Power ON in the software upgrade processing.