Xilinx Virtex-6 FPGA GTH Transceivers User Manual

Virtex-6 FPGA GTH Transceivers

User Guide

UG371 (v2.0) February 16, 2010

Xilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to you solely for use in the development of designs to oper ate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of an y corrections or updates . Xi linx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information.

THE DOCUMENTA TI ON IS DISCLOSED TO YOU “AS-IS” WITH NO WARRANTY OF ANY KIND. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DOCUMENTATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PAR T ICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OF THE DOCUMENTATION.

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Virtex-6 FPGA GTH Transceivers User Guide www.xilinx.com UG371 (v2.0) February 16, 2010

Revision History

The following table shows the revision history for this document.

Date Version Revision

09/16/09 1.0 Initial Xilinx release.

02/16/10 2.0

Changed the clock domain for the RXPOWERDOWNx[1:0] ports in Ta b l e 1-3, p a g e 15, Ta bl e 2 -1 0,

page 56, and Table 2-12, page 66. Chapter 1: Updated OTU-3 values in Ta bl e 1 -1. In Ta bl e 1- 3, renamed DO port to DRPDO and

relocated ports I, IB, and O to new Ta bl e 1 - 4.

Chapter 2: In the GTHRESET description in Ta b le 2- 7 and Tab le 2 -1 0, indicated that GTHINIT must

be pulsed only after GTHRESET is deasserted. In Ta bl e 2- 1 0 and Ta b le 2- 1 2, changed RXPOWERDOWN and TXPOWERDOWN descriptions for the x4 link case. Added Reference

Clock Input Structure, page 43. Removed reference to LVDS clocks as being able to drive the

reference clock pins, page 44. Added sentence about MMCM and BUFR to TSTREFCLKOUT port description in Ta bl e 2 -4 . Added PLL, page 48. Revised Figure 2-12, Figure 2-13, and Figure 2-14. In

Ta bl e 2 -11 , changed the meaning of bit code 110 for bits [13:11] and [10:8] of the

PCS_MODE_LANE attribute to Reserved; changed the 8B/10B reset value for the PCS_RESET_LANE attribute; added reference to the Virtex-6 FPGA GTH Transceiver Wizard to attribute PCS_RESET_1_LANE, bits [15:2]. In Ta bl e 2 -1 4, added the encoding to the PMA_LPBK_CTRL_LANE attribute description; changed the Reserved bits for [13:11] and [10:8] in the PCS_MODE_LANE attribute; added reference to the Virtex-6 FPGA GTH Transceiver Wizard to attribute PMA_LPBK_CTRL_LANE, bits [15:2]. In Ta bl e 2 -1 5 , changed the name of port DO[15:0] to DRPDO[15:0]. Added note about DISABLEDRP to Using the DRP Interface, page 70 and Using the Management Interface, page 72.

Chapter 3: Added 32 and 64 bits to 8B/10B mode in Ta bl e 3 -1 . Added two rows to 8B/10B Mode

for 32-bit and 64-bit fabric interface data width in Tab l e 3 -2 . Revised manual adjustment mode settings for the BUFFER_CONFIG_LANE attribute in Ta bl e 3 -4 , and changed the meaning of bit code 110 for bits [13:11] and [10:8] of the PCS_MODE_LANE attribute to Reserved in Tab l e 3 -4 ,

Ta bl e 3 -6 , Ta bl e 3 -8 , and Ta bl e 3 -1 0. Added reference to the Virtex-6 FPGA GTH Transceiver Wizard

to attribute PCS_RESET_1_LANE, bits [15:2] in Tab le 3- 6 . Changed the 8B/10B reset value for the PCS_RESET_LANE attribute in Ta bl e 3 -6 , Tab le 3 -8 the Virtex-6 FPGA GTH Transceiver Wizard to attribute PCS_RESET_1_LANE, bits [15:2] in

Ta bl e 3 -1 0. Changed the PCS_RESET_LANE value in step 2 of Enabling 8B/10B Mode, page 85. In Ta bl e 3 -1 2, and added reference to the Virtex-6 FPGA GTH Transceiver Wizard to attribute

PRBS_CFG_LANE, bits [15:4] and PCS_RESET_1_LANE, bits [15:2]; changed the Reserved bits for [13:11] and [10:8] in the PCS_MODE_LANE attribute. In Tab le 3 -1 3 , added reference to the Virtex-6 FPGA GTH Transceiver Wizard to attribute PCS_MISC_CFG_0_LANE, bits [15:12] and [5:0]. Added TX Configurable Driver.

Chapter 4: Added RX Analog Front End, RX Equalization, and RX CDR. Added reference to the

Virtex-6 FPGA GTH Transceiver Wizard to attribute PCS_MISC_CFG_0_LANE, bits [15:12] and [5:0] in Ta bl e 4 -8 , and to attributes PCS_MISC_CFG_0_LANE, bits [15:12] and [5:0], PCS_RESET_1_LANE bits [15:2], and PRBS_CFG_LANE bits [15:4] in Ta bl e 4 -1 0. In the Functional Description section of RX Pattern Checker, added paragraph about when the checker is forced into PRBS31 mode, and added two sentences at the end of the section. Added Tab l e 4 -9 . Changed the 8B/10B reset value for the PCS_RESET_LANE attribute in Ta bl e 4 -1 0, Ta bl e 4 -1 3, Ta bl e 4 -1 6 , and

Ta bl e 4 -1 8. Deleted PRBS checker reference in Description of RXCODEERR in Ta bl e 4 -1 2, Ta bl e 4 -1 5, Ta bl e 4 -1 7, and Ta bl e 4 - 21 . In Tab le 4- 13 , Ta bl e 4- 1 6, Ta bl e 4 - 18 , and Tab l e 4- 2 2, changed

transmitter to receiver in the description of RX_FABRIC_WIDTH, and changed the meaning of bit code 110 for bits [13:11] and [10:8] of the PCS_MODE_LANE attribute to Reserved. In Ta bl e 4 - 13 ,

Ta bl e 4 -1 6, and Ta bl e 4 -1 8 , added reference to the Virtex-6 FPGA GTH Transceiver Wizard to

attribute PCS_RESET_1_LANE, bits [15:2]. Changed the PCS_RESET_LANE value in step 2 of

Enabling 8B/10B Mode, page 130. Added 32 and 64 bits to 8B/10B mode in Ta bl e 4 -1 9. Added two

rows to 8B/10B Mode for 32-bit and 64-bit fabric interface data width in Tab le 4 -2 0 manual adjustment mode

Added Chapter 5, Board Design Guidelines.

settings for the BUFFER_CONFIG_LANE attribute in Ta bl e 4 -2 2 .

, Ta

b le 3 - 10 , and Tab le 3 -1 2. Added reference to

. Revised

UG371 (v2.0) February 16, 2010 www.xilinx.com Virtex-6 FPGA GTH Transceivers User Guide

Virtex-6 FPGA GTH Transceivers User Guide www.xilinx.com UG371 (v2.0) February 16, 2010

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Chapter 1: Transceiver and Tool Overview

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Port and Attribute Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Virtex-6 FPGA GTH Transceiver Wizard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

FF1155 Package Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

FF1923 and FF1924 Package Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Chapter 2: Shared Transceiver Features

Reference Clock Input Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Using the Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Reference Clock Distribution and Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Clocking from an External Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Clocking from a Neighboring GTH Quad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

PLL Settings for the Common Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Reset and Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

GTH Quad Initialization in Response to Completion of Configuration . . . . . . . . . . . 60

GTH Quad Reset in Response to GTHRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Resetting the Transmit Datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Resetting the Receive Datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Using Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

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Far-end Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Near-end PCS Loopback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Near-end PMA Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Dynamic Reconfiguration Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Using the DRP Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Using the Management Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Chapter 3: Transmitter

FPGA TX Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Transmit Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Configuring the Transmitter for Multi-lane Applications . . . . . . . . . . . . . . . . . . . . . . . 82

TX 8B/10B Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Enabling 8B/10B Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

TX 64B/66B Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Enabling 64B/66B Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

TX Raw Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Enabling Raw Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

TX Pattern Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

TX Polarity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Using TX Polarity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

TX Configurable Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Setting the TX Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Amplitude (Swing) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Post-Cursor Emphasis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Pre-Cursor Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Chapter 4: Receiver

RX Analog Front End. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Interfacing to the RX AFE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

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RX Equalization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Setting the RX Equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

DFE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

CTLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

RX CDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

RX Polarity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Using RX Polarity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

RX Pattern Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Using RX Pattern Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

RX Raw Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Enabling Raw Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Using the Barrel Shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

RX 64B/66B Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Enabling 64B/66B Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

RX 8B/10B Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Enabling 8B/10B Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Using Comma Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

FPGA RX Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Receive Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Configuring the Receiver for Multi-lane Applications . . . . . . . . . . . . . . . . . . . . . . . . . 137

Chapter 5: Board Design Guidelines

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Pin Description and Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

GTH Quad Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Termination Resistor Calibration Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Reference Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

GTH Transceiver Reference Clock Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Reference Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

LVPECL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

AC Coupled Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Unused Reference Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Reference Clock Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

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Power Supplies and Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Power Supply Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Linear vs. Switching Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

SelectIO Interface Usage Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

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About This Guide

This document describes how to use the GTH transceivers in Virtex®-6 FPGAs. In this document:

• Virtex-6 FPGA GTH transceiver is abbreviated as GTH transceiver.

• GTHE1_QUAD is the name of the instantiation primitive that instantiates one

Virtex-6 FPGA GTH transceiver.

•A Quad is a cluster or set of four GTH transceivers that share two differential reference

clock pin pairs and analog supply pins.

• GTH lane [n] refers to a specific lane within the GTH Quad, where n = 0, 1, 2, or 3.

•The terms FPGA logic and fabric refer to internal FPGA circuitry not including the

GTH transceiver.

Guide Contents

Preface

This manual contains the following chapters:

• Chapter 1, Transceiver and Tool Overview

• Chapter 2, Shared Transceiver Features

• Chapter 3, Transmitter

• Chapter 4, Receiver

• Chapter 5, Board Design Guidelines

Additional Documentation

The following documents are also available for download at

http://www.xilinx.com/support/documentation/virtex-6.htm

• Virtex-6 Family Overview

The features and product selection of the Virtex-6 family are outlined in this overview.

• Virtex-6 FPGA Data Sheet: DC and Switching Characteristics

This data sheet contains the DC and Switching Characteristic specifications for the Virtex-6 family.

• Virtex-6 FPGA Packaging and Pinout Specifications

This specification includes the tables for device/package combinations and maximum I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and thermal specifications.

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UG371 (v2.0) February 16, 2010

Preface: About This Guide

• Virtex-6 FPGA Configuration User Guide

• Virtex-6 FPGA SelectIO Resources User Guide

• Virtex-6 FPGA Clocking Resources User Guide

• Virtex-6 FPGA Memory Resources User Guide

• Virtex-6 FPGA Configurable Logic Block User Guide

• Virtex-6 FPGA DSP48E1 Slice User Guide

This all-encompassing configuration guide includes chapters on configuration interfaces (serial and SelectMAP), bitstream encryption, boundary-scan and JTAG configuration, reconfiguration techniques, and readback through the SelectMAP and JTAG interfaces.

This guide describes the SelectIO™ resources available in all Virtex-6 devices.

This guide describes the clocking resources available in all Virtex-6 devices, including the MMCM and PLLs.

The functionality of the block RAM and FIFO are described in this user guide.

This guide describes the capabilities of the configurable logic blocks (CLBs) available in all Virtex-6 devices.

This guide describes the architecture of the DSP48E1 slice in Virtex-6 FPGAs and provides configuration examples.

• Virtex-6 FPGA GTX Transceivers User Guide

This guide describes the GTX transceivers available in all Virtex-6 FPGAs except the XC6VLX760.

• Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC User Guide

This guide describes the dedicated Tri-Mode Ethernet Media Access Controller available in all Virtex-6 FPGAs except the XC6VLX760.

• Virtex-6 FPGA System Monitor User Guide

The System Monitor functionality available in all Virtex-6 devices is outlined in this guide.

• Virtex-6 FPGA PCB Designer Guide

This guide provides information on PCB design for Virtex-6 FPGA GTX transceivers, with a focus on strategies for making design decisions at the PCB and interface level.

Additional Resources

To find additional documentation, see the Xilinx website at:

http://www.xilinx.com/support/documentation/index.htm

To search the Answer Database of silicon, software, and IP questions and answers, or to create a technical support WebCase, see the Xilinx website at:

http://www.xilinx.com/support

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Transceiver and Tool Overview

Overview

The Virtex®-6 FPGA GTH transceiver is highly configurable and tightly integrated with the programmable logic resources of the FPGA. It provides these features to support a wide variety of applications:

• Current Mode Logic (CML) serial drivers/buffers with configurable termination and voltage swing

• Support for multiple industry standards with the following line rates:

• 2.488 Gb/s to 2.795 Gb/s

• 9.953 Gb/s to 11.18 Gb/s

•One PLL per GTH Quad

GTH lanes within a Quad can be configured with different line rates that are integer multiples of each other (i.e., full line rate and line rate/4)

Chapter 1

• Linear equalizer with adaptive gain control and programmable boost

• Selectable DFE with three TAPs that can either be controlled manually or by an automatic adaptive engine

• Three-tap FIR filter for the TX driver

Support for pre-cursor and post-cursor pre-emphasis

• Optional built-in PCS features

• 8B/10B encoder/decoder with comma alignment

• 64B/66B block based on the IEEE 802.3-2008 Clause 49 implementation

• Raw mode (non-encoded datapath)

• PRBS generator and checker

• Configurable fabric interface width

• DRP and management interface to access the configuration registers

The Xilinx® CORE Generator™ tool includes a Wizard to automatically configure GTH transceivers to support configurations for different protocols or perform custom configuration (see Virtex-6 FPGA GTH Transceiver Wizard, page 30).

Figure 1-1 shows the GTH transceiver placement in an example Virtex-6 FPGA device

(XC6VHX255T).

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Chapter 1: Transceiver and Tool Overview

MMCM

GTHE1_QUAD

Column

GTXE1 Column

GTXE1_

X1Y10

GTXE1_

X1Y9

GTXE1_

X1Y8

GTXE1_

X1Y7

GTXE1_

X1Y6

GTXE1_

X1Y5

GTXE1_

X1Y4

GTXE1_

X1Y3

GTXE1_

X1Y2

GTXE1_

X1Y1

GTXE1_

X1Y0

GTXE1_

X1Y11

GTHE1_

QUAD_

X1Y2

GTHE1_

QUAD_

X1Y1

GTHE1_

QUAD_

X1Y0

GTHE1_QUAD

Column

GTXE1 Column

GTXE1_

X0Y10

GTXE1_

X0Y9

GTXE1_

X0Y8

GTXE1_

X0Y7

GTXE1_

X0Y6

GTXE1_

X0Y5

GTXE1_

X0Y4

GTXE1_

X0Y3

GTXE1_

X0Y2

GTXE1_

X0Y1

GTXE1_

X0Y0

GTXE1_

X0Y11

GTHE1_

QUAD_

X0Y2

GTHE1_

QUAD_

X0Y1

GTHE1_

QUAD_

X0Y0

MMCM

I/O

Collumn

Configuration

I/O

Collumn

PCI

Express

PCI

Express

Ether

net

MAC

Ethernet

MAC

MMCM

UG371_c1_01_082109

X-Ref Target - Figure 1-1

Figure 1-1: GTH Transceiver Inside the Virtex-6 XC6VHX255T FPGA

Notes relevant to Figure 1-1:

1. This figure does not illustrate exact size, location, or scale of the functional blocks to each other. It does show the correct number of available resources.

2. To improve clarity, this figure does not show the CLB, DSP, and block RAM columns.

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X-Ref Target - Figure 1-2

UG371_c1_02_120809

GTH3

Fabric Data, Control, and Clock for GTH3

PCS

PCS to Fabric

Interface

TX3

RX3

GTH2

Fabric Data, Control, and Clock for GTH2

PCS

PCS to Fabric

Interface

TX2

RX2

GTH1

Fabric Data, Control, and Clock for GTH1

PCS

PCS to Fabric

Interface

TX1

RX1

GTH0

GTH QUAD

Fabric Data, Control, and Clock for GTH0

PCS

PCS to Fabric

Interface

TX0

RX0

PMA

PLL

Reset and

Power-Down

Controls

DRP Interface

Management Interface Unit

REFCLK

Overview

Figure 1-2 shows a diagram of the GTH Quad, containing four GTH transceivers, a PLL,

and shared resources for controlling and initializing the Quad.

Figure 1-2: GTH Quad Block Diagram

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Chapter 1: Transceiver and Tool Overview

Tab le 1 -1 shows example PLL settings of GTH transceivers that are compatible with the

protocol line rate.

Table 1-1: PLL Settings for Protocol Sta ndards

Standard Line Rate [Gb/s]

10GBASE-R 10.3125 156.25 33 5.16 1

CEI11 11.1 173.37 32 5.55 1

OC-192

9.953

OC-48 2.488

OTU-1 2.667

OTU-2 10.71

OTU-3 10.75

OTU-4 11.18

XFP 9.953 155.52 32 4.98 1

Reference Clock

Frequency [MHz]

155.52 32 4.98 1

622.08 8 4.98 1

155.52 32 4.98 4

622.08 8 4.98 4

167.33 32 5.35 4

669.38 8 5.35 4

167.33 32 5.35 1

669.38 8 5.35 1

168.05 32 5.38 1

672.19 8 5.38 1

174.69 32 5.59 1

698.75 8 5.59 1

PLL Clock

Multiplier, N

PLL Frequency

[GHz]

PLL Output

Divider, D

XLAUI 10.3125 156.25 33 5.16 1

CAUI 10.3125 156.25 33 5.16 1

Port and Attribute Summary

This section contains alphabetical tables of power pins, ports, and attributes for the GTH transceiver.

For all ports mentioned in this guide:

• Names that end with 0 are for the GTH0 transceiver on the Quad

• Names that end with 1 are for the GTH1 transceiver on the Quad

• Names that end with 2 are for the GTH2 transceiver on the Quad

• Names that end with 3 are for the GTH3 transceiver on the Quad

• Port names that do not end with 0, 1, 2 or 3 are shared.

For all attributes mentioned in this guide:

• Names that end with LANE0 are for the GTH0 transceiver on the Quad

• Names that end with LANE1 are for the GTH1 transceiver on the Quad

• Names that end with LANE2 are for the GTH2 transceiver on the Quad

• Names that end with LANE3 are for the GTH3 transceiver on the Quad

• Attribute names that do not end with LANE0, LANE1, LANE2 or LANE3 are shared.

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Port and Attribute Summary

Tab le 1 -2 lists alphabetically the signal names and directions of the GTH transceiver analog

pins.

Table 1-2: GTH Analog Pin Summary

Pin Dir

(1)

MGTHAGND_[L,R]

MGTHAVCC_[L,R]

MGTHAVCCPLL_[L,R]

MGTHAVCCRX_[L,R]

MGTHAVTT_[L,R]

MGTRBIAS In

MGTREFCLKP/MGTREFCLKN In

MGTTXP0/MGTTXN0

MGTTXP1/MGTTXN1

Out

MGTTXP2/MGTTXN2

MGTTXP3/MGTTXN3

MGTRXP0/MGTRXN0

MGTRXP1/MGTRXN1

MGTRXP2/MGTRXN2

MGTRXP3/MGTRXN3

Notes:

1. These are power supply pins.

Tab le 1 -3 lists alphabetically the signal names, directions, and clock domain of the GTH

Quad ports.

Table 1-3: GTH Quad Port Summary

Port Dir Clock Domain

DADDR[15:0] In DCLK

DCLK In N/A

DEN In DCLK

DFETRAINCTRL0

DFETRAINCTRL1

In DCLK

DFETRAINCTRL2

DFETRAINCTRL3

DI[15:0] In DCLK

DISABLEDRP In DCLK

DRPDO[15:0] Out DCLK

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Chapter 1: Transceiver and Tool Overview

Table 1-3: GTH Quad Port Summary (Cont’d)

Port Dir Clock Domain

DRDY Out DCLK

DWE In DCLK

GTHINIT In DCLK

GTHINITDONE Out DCLK

GTHRESET In Async

GTHX2LANE01 In Async

GTHX2LANE23 In Async

GTHX4LANE In Async

MGMTPCSLANESEL[3:0] In DCLK

MGMTPCSMMDADDR[4:0] In DCLK

MGMTPCSRDACK Out DCLK

MGMTPCSRDDATA[15:0] Out DCLK

MGMTPCSREGADDR[15:0] In DCLK

MGMTPCSREGRD In DCLK

MGMTPCSREGWR In DCLK

MGMTPCSWRDATA[15:0] In DCLK

PLLPCSCLKDIV[5:0] In DCLK

PLLREFCLKSEL[2:0] In DCLK

POWERDOWN0

POWERDOWN1 TXUSERCLKIN1

POWERDOWN2 TXUSERCLKIN2

POWERDOWN3 TXUSERCLKIN3

REFCLK In N/A

RXBUFRESET0

RXBUFRESET1 RXUSERCLKIN1

RXBUFRESET2 RXUSERCLKIN2

RXBUFRESET3 RXUSERCLKIN3

RXCODEERR0[7:0]

TXUSERCLKIN0

RXUSERCLKIN0

RXCODEERR1[7:0] RXUSERCLKIN1

RXCODEERR2[7:0] RXUSERCLKIN2

RXCODEERR3[7:0] RXUSERCLKIN3

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Out

UG371 (v2.0) February 16, 2010

Table 1-3: GTH Quad Port Summary (Cont’d)

Port Dir Clock Domain

Port and Attribute Summary

RXCTRL0[7:0]

RXCTRL1[7:0] RXUSERCLKIN1

Out

RXCTRL2[7:0] RXUSERCLKIN2

RXCTRL3[7:0] RXUSERCLKIN3

RXCTRLACK0

RXCTRLACK1 TXUSERCLKIN1

Out

RXCTRLACK2 TXUSERCLKIN2

RXCTRLACK3 TXUSERCLKIN3

RXDATA0[63:0]

RXDATA1[63:0] RXUSERCLKIN1

Out

RXDATA2[63:0] RXUSERCLKIN2

RXDATA3[63:0] RXUSERCLKIN3

RXDISPERR0[7:0]

RXDISPERR1[7:0] RXUSERCLKIN1

Out

RXDISPERR2[7:0] RXUSERCLKIN2

RXDISPERR3[7:0] RXUSERCLKIN3

RXUSERCLKIN0

TXUSERCLKIN0

RXUSERCLKIN0

RXENCOMMADET0

RXENCOMMADET1 RXUSERCLKIN1

RXENCOMMADET2 RXUSERCLKIN2

RXENCOMMADET3 RXUSERCLKIN3

RXN0

RXN1

RXN2

RXN3

In (Pad) RX Serial Clock

RXP0

RXP1

RXP2

RXP3

RXPOLARITY0

RXPOLARITY1 RXUSERCLKIN1

RXPOLARITY2 RXUSERCLKIN2

RXPOLARITY3 RXUSERCLKIN3

RXUSERCLKIN0

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Table 1-3: GTH Quad Port Summary (Cont’d)

Port Dir Clock Domain

RXPOWERDOWN0[1:0]

RXPOWERDOWN1[1:0] TXUSERCLKIN1

RXPOWERDOWN2[1:0] TXUSERCLKIN2

RXPOWERDOWN3[1:0] TXUSERCLKIN3

RXRATE0[1:0]

RXRATE1[1:0] TXUSERCLKIN1

RXRATE2[1:0] TXUSERCLKIN2

RXRATE3[1:0] TXUSERCLKIN3

RXSLIP0

RXSLIP1 RXUSERCLKIN1

RXSLIP2 RXUSERCLKIN2

RXSLIP3 RXUSERCLKIN3

RXUSERCLKIN0

RXUSERCLKIN1

In N/A

RXUSERCLKIN2

RXUSERCLKIN3

TXUSERCLKIN0

RXUSERCLKIN0

RXUSERCLKOUT0

RXUSERCLKOUT1

RXUSERCLKOUT2

RXUSERCLKOUT3

RXVALID0[7:0]

RXVALID1[7:0] RXUSERCLKIN1

RXVALID2[7:0] RXUSERCLKIN2

RXVALID3[7:0] RXUSERCLKIN3

SAMPLERATE0[2:0]

SAMPLERATE1[2:0] TXUSERCLKIN1

SAMPLERATE2[2:0] TXUSERCLKIN2

SAMPLERATE3[2:0] TXUSERCLKIN3

TSTPATH Out Async

TSTREFCLKFAB Out N/A

TSTREFCLKOUT Out N/A

Out N/A

RXUSERCLKIN0

Out

TXUSERCLKIN0

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Table 1-3: GTH Quad Port Summary (Cont’d)

Port Dir Clock Domain

Port and Attribute Summary

TXBUFRESET0

TXBUFRESET1 TXUSERCLKIN1

TXBUFRESET2 TXUSERCLKIN2

TXBUFRESET3 TXUSERCLKIN3

TXCTRL0[7:0]

TXCTRL1[7:0] TXUSERCLKIN1

TXCTRL2[7:0] TXUSERCLKIN2

TXCTRL3[7:0] TXUSERCLKIN3

TXCTRLACK0

TXCTRLACK1 TXUSERCLKIN1

Out

TXCTRLACK2 TXUSERCLKIN2

TXCTRLACK3 TXUSERCLKIN3

TXDATA0[63:0]

TXDATA1[63:0] TXUSERCLKIN1

TXDATA2[63:0] TXUSERCLKIN2

TXDATA3[63:0] TXUSERCLKIN3

TXUSERCLKIN0

TXDATAMSB0[7:0]

TXDATAMSB1[7:0] TXUSERCLKIN1

TXDATAMSB2[7:0] TXUSERCLKIN2

TXDATAMSB3[7:0] TXUSERCLKIN3

TXDEEMPH0

TXDEEMPH1 TXUSERCLKIN1

TXDEEMPH2 TXUSERCLKIN2

TXDEEMPH3 TXUSERCLKIN3

TXMARGIN0[2:0]

TXMARGIN1[2:0] TXUSERCLKIN1

TXMARGIN2[2:0] TXUSERCLKIN2

TXMARGIN3[2:0] TXUSERCLKIN3

TXUSERCLKIN0

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Chapter 1: Transceiver and Tool Overview

Table 1-3: GTH Quad Port Summary (Cont’d)

Port Dir Clock Domain

TXN0

TXN1

TXN2

TXN3

TXP0

TXP1

TXP2

TXP3

TXPOWERDOWN0[1:0]

TXPOWERDOWN1[1:0] TXUSERCLKIN1

TXPOWERDOWN2[1:0] TXUSERCLKIN2

TXPOWERDOWN3[1:0] TXUSERCLKIN3

TXRATE0[1:0]

TXRATE1[1:0] TXUSERCLKIN1

TXRATE2[1:0] TXUSERCLKIN2

TXRATE3[1:0] TXUSERCLKIN3

TXUSERCLKIN0

TXUSERCLKIN1

TXUSERCLKIN2

Out

(Pad)

In N/A

TX Serial Clock

TXUSERCLKIN0

TXUSERCLKIN3

TXUSERCLKOUT0

TXUSERCLKOUT1

TXUSERCLKOUT2

TXUSERCLKOUT3

Out N/A

The ports in Ta bl e 1 -4 are part of the GTH IBUFDS primitive.

Table 1-4: GTH Reference Clock (IBUFDS_GTHE1) Port Summary

Port Dir Clock Domain

IInAsync

IB In Async

OOutAsync

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UG371 (v2.0) February 16, 2010

Port and Attribute Summary

Tab le 1 -5 lists alphabetically the attribute names and type of the GTH Quad attributes.

Table 1-5: GTH Quad Attribute Summary

Attribute Type

BER_CONST_PTRN0 16-bit Hex

BER_CONST_PTRN1 16-bit Hex

BUFFER_CONFIG_LANE0

BUFFER_CONFIG_LANE1

16-bit Hex

BUFFER_CONFIG_LANE2

BUFFER_CONFIG_LANE3

DFE_TRAIN_CTRL_LANE0

DFE_TRAIN_CTRL_LANE1

16-bit Hex

DFE_TRAIN_CTRL_LANE2

DFE_TRAIN_CTRL_LANE3

DLL_CFG0 16-bit Hex

DLL_CFG1 16-bit Hex

E10GBASEKR_LD_COEFF_UPD_LANE0

E10GBASEKR_LD_COEFF_UPD_LANE1

16-bit Hex

E10GBASEKR_LD_COEFF_UPD_LANE2

E10GBASEKR_LD_COEFF_UPD_LANE3

E10GBASEKR_LP_COEFF_UPD_LANE0

E10GBASEKR_LP_COEFF_UPD_LANE1

16-bit Hex

E10GBASEKR_LP_COEFF_UPD_LANE2

E10GBASEKR_LP_COEFF_UPD_LANE3

E10GBASEKR_PMA_CTRL_LANE0

E10GBASEKR_PMA_CTRL_LANE1

16-bit Hex

E10GBASEKR_PMA_CTRL_LANE2

E10GBASEKR_PMA_CTRL_LANE3

E10GBASEKX_CTRL_LANE0

E10GBASEKX_CTRL_LANE1

16-bit Hex

E10GBASEKX_CTRL_LANE2

E10GBASEKX_CTRL_LANE3

E10GBASER_PCS_CFG_LANE0

E10GBASER_PCS_CFG_LANE1

16-bit Hex

E10GBASER_PCS_CFG_LANE2

E10GBASER_PCS_CFG_LANE3

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UG371 (v2.0) February 16, 2010

Chapter 1: Transceiver and Tool Overview

Table 1-5: GTH Quad Attribute Summary (Cont’d)

E10GBASER_PCS_SEEDA0_LANE0

Attribute Type

E10GBASER_PCS_SEEDA0_LANE1

E10GBASER_PCS_SEEDA0_LANE2

E10GBASER_PCS_SEEDA0_LANE3

E10GBASER_PCS_SEEDA1_LANE0

E10GBASER_PCS_SEEDA1_LANE1

E10GBASER_PCS_SEEDA1_LANE2

E10GBASER_PCS_SEEDA1_LANE3

E10GBASER_PCS_SEEDA2_LANE0

E10GBASER_PCS_SEEDA2_LANE1

E10GBASER_PCS_SEEDA2_LANE2

E10GBASER_PCS_SEEDA2_LANE3

E10GBASER_PCS_SEEDA3_LANE0

E10GBASER_PCS_SEEDA3_LANE1

E10GBASER_PCS_SEEDA3_LANE2

E10GBASER_PCS_SEEDA3_LANE3

E10GBASER_PCS_SEEDB0_LANE0

E10GBASER_PCS_SEEDB0_LANE1

E10GBASER_PCS_SEEDB0_LANE2

16-bit Hex

E10GBASER_PCS_SEEDB0_LANE3

E10GBASER_PCS_SEEDB1_LANE0

E10GBASER_PCS_SEEDB1_LANE1

E10GBASER_PCS_SEEDB1_LANE2

E10GBASER_PCS_SEEDB1_LANE3

E10GBASER_PCS_SEEDB2_LANE0

E10GBASER_PCS_SEEDB2_LANE1

E10GBASER_PCS_SEEDB2_LANE2

E10GBASER_PCS_SEEDB2_LANE3

E10GBASER_PCS_SEEDB3_LANE0

E10GBASER_PCS_SEEDB3_LANE1

E10GBASER_PCS_SEEDB3_LANE2

E10GBASER_PCS_SEEDB3_LANE3

16-bit Hex

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UG371 (v2.0) February 16, 2010

Table 1-5: GTH Quad Attribute Summary (Cont’d)

Attribute Type

E10GBASER_PCS_TEST_CTRL_LANE0

Port and Attribute Summary

E10GBASER_PCS_TEST_CTRL_LANE1

E10GBASER_PCS_TEST_CTRL_LANE2

E10GBASER_PCS_TEST_CTRL_LANE3

E10GBASEX_PCS_TSTCTRL_LANE0

E10GBASEX_PCS_TSTCTRL_LANE1

E10GBASEX_PCS_TSTCTRL_LANE2

E10GBASEX_PCS_TSTCTRL_LANE3

GLBL0_NOISE_CTRL 16-bit Hex

GLBL_AMON_SEL 16-bit Hex

GLBL_DMON_SEL 16-bit Hex

GLBL_PWR_CTRL 16-bit Hex

GTH_CFG_PWRUP_LANE0

GTH_CFG_PWRUP_LANE1

GTH_CFG_PWRUP_LANE2

GTH_CFG_PWRUP_LANE3

LANE_AMON_SEL 16-bit Hex

LANE_DMON_SEL 16-bit Hex

16-bit Hex

1-bit Binary

LANE_LNK_CFGOVRD 16-bit Hex

LANE_PWR_CTRL_LANE0

LANE_PWR_CTRL_LANE1

LANE_PWR_CTRL_LANE2

LANE_PWR_CTRL_LANE3

LNK_TRN_CFG_LANE0

LNK_TRN_CFG_LANE1

LNK_TRN_CFG_LANE2

LNK_TRN_CFG_LANE3

LNK_TRN_COEFF_REQ_LANE0

LNK_TRN_COEFF_REQ_LANE1

LNK_TRN_COEFF_REQ_LANE2

LNK_TRN_COEFF_REQ_LANE3

MISC_CFG 16-bit Hex

MODE_CFG1 16-bit Hex

MODE_CFG2 16-bit Hex

MODE_CFG3 16-bit Hex

16-bit Hex

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UG371 (v2.0) February 16, 2010

Chapter 1: Transceiver and Tool Overview

Table 1-5: GTH Quad Attribute Summary (Cont’d)

MODE_CFG4 16-bit Hex

MODE_CFG5 16-bit Hex

MODE_CFG6 16-bit Hex

MODE_CFG7 16-bit Hex

PCS_ABILITY_LANE0

Attribute Type

PCS_ABILITY_LANE1

PCS_ABILITY_LANE2

PCS_ABILITY_LANE3

PCS_CTRL1_LANE0

PCS_CTRL1_LANE1

PCS_CTRL1_LANE2

PCS_CTRL1_LANE3

PCS_CTRL2_LANE0

PCS_CTRL2_LANE1

PCS_CTRL2_LANE2

PCS_CTRL2_LANE3

PCS_MISC_CFG_0_LANE0

PCS_MISC_CFG_0_LANE1

PCS_MISC_CFG_0_LANE2

PCS_MISC_CFG_0_LANE3

PCS_MISC_CFG_1_LANE0

PCS_MISC_CFG_1_LANE1

PCS_MISC_CFG_1_LANE2

16-bit Hex

PCS_MISC_CFG_1_LANE3

PCS_MODE_LANE0

PCS_MODE_LANE1

PCS_MODE_LANE2

PCS_MODE_LANE3

PCS_RESET_LANE0

PCS_RESET_LANE1

PCS_RESET_LANE2

PCS_RESET_LANE3

24 www.xilinx.com Vir tex-6 FPGA GTH Transceivers User Guide

16-bit Hex

UG371 (v2.0) February 16, 2010

Table 1-5: GTH Quad Attribute Summary (Cont’d)

Attribute Type

PCS_RESET_1_LANE0

Port and Attribute Summary

PCS_RESET_1_LANE1

PCS_RESET_1_LANE2

PCS_RESET_1_LANE3

PCS_TYPE_LANE0

PCS_TYPE_LANE1

PCS_TYPE_LANE2

PCS_TYPE_LANE3

PLL_CFG0 16-bit Hex

PLL_CFG1 16-bit Hex

PLL_CFG2 16-bit Hex

PMA_CTRL1_LANE0

PMA_CTRL1_LANE1

PMA_CTRL1_LANE2

PMA_CTRL1_LANE3

PMA_CTRL2_LANE0

PMA_CTRL2_LANE1

PMA_CTRL2_LANE2

16-bit Hex

PMA_CTRL2_LANE3

PMA_LPBK_CTRL_LANE0

PMA_LPBK_CTRL_LANE1

PMA_LPBK_CTRL_LANE2

PMA_LPBK_CTRL_LANE3

PRBS_BER_CFG0_LANE0

PRBS_BER_CFG0_LANE1

PRBS_BER_CFG0_LANE2

PRBS_BER_CFG0_LANE3

PRBS_BER_CFG1_LANE0

PRBS_BER_CFG1_LANE1

PRBS_BER_CFG1_LANE2

PRBS_BER_CFG1_LANE3

PRBS_CFG_LANE0

PRBS_CFG_LANE1

PRBS_CFG_LANE2

PRBS_CFG_LANE3

16-bit Hex

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UG371 (v2.0) February 16, 2010

Chapter 1: Transceiver and Tool Overview

Table 1-5: GTH Quad Attribute Summary (Cont’d)

PTRN_CFG0_LSB 16-bit Hex

PTRN_CFG0_MSB 16-bit Hex

PTRN_LEN_CFG 16-bit Hex

PWRUP_DLY 16-bit Hex

RX_AEQ_VAL0_LANE0

Attribute Type

RX_AEQ_VAL0_LANE1

RX_AEQ_VAL0_LANE2

RX_AEQ_VAL0_LANE3

RX_AEQ_VAL1_LANE0

RX_AEQ_VAL1_LANE1

RX_AEQ_VAL1_LANE2

RX_AEQ_VAL1_LANE3

RX_AGC_CTRL_LANE0

RX_AGC_CTRL_LANE1

RX_AGC_CTRL_LANE2

RX_AGC_CTRL_LANE3

RX_CDR_CTRL0_LANE0

RX_CDR_CTRL0_LANE1

RX_CDR_CTRL0_LANE2

RX_CDR_CTRL0_LANE3

RX_CDR_CTRL1_LANE0

RX_CDR_CTRL1_LANE1

RX_CDR_CTRL1_LANE2

16-bit Hex

RX_CDR_CTRL1_LANE3

RX_CDR_CTRL2_LANE0

RX_CDR_CTRL2_LANE1

RX_CDR_CTRL2_LANE2

RX_CDR_CTRL2_LANE3

RX_CFG0_LANE0

RX_CFG0_LANE1

RX_CFG0_LANE2

RX_CFG0_LANE3

26 www.xilinx.com Vir tex-6 FPGA GTH Transceivers User Guide

16-bit Hex

UG371 (v2.0) February 16, 2010

Table 1-5: GTH Quad Attribute Summary (Cont’d)

Attribute Type

RX_CFG1_LANE0

Port and Attribute Summary

RX_CFG1_LANE1

RX_CFG1_LANE2

RX_CFG1_LANE3

RX_CFG2_LANE0

RX_CFG2_LANE1

RX_CFG2_LANE2

RX_CFG2_LANE3

RX_CTLE_CTRL_LANE0

RX_CTLE_CTRL_LANE1

RX_CTLE_CTRL_LANE2

RX_CTLE_CTRL_LANE3

RX_CTRL_OVRD_LANE0

RX_CTRL_OVRD_LANE1

RX_CTRL_OVRD_LANE2

RX_CTRL_OVRD_LANE3

RX_FABRIC_WIDTH0

RX_FABRIC_WIDTH1

RX_FABRIC_WIDTH2

16-bit Hex

Integer

RX_FABRIC_WIDTH3

RX_LOOP_CTRL_LANE0

RX_LOOP_CTRL_LANE1

RX_LOOP_CTRL_LANE2

RX_LOOP_CTRL_LANE3

RX_MVAL0_LANE0

RX_MVAL0_LANE1

RX_MVAL0_LANE2

RX_MVAL0_LANE3

RX_MVAL1_LANE0

RX_MVAL1_LANE1

RX_MVAL1_LANE2

RX_MVAL1_LANE3

RX_P0_CTRL 16-bit Hex

RX_P0S_CTRL 16-bit Hex

RX_P1_CTRL 16-bit Hex

16-bit Hex

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UG371 (v2.0) February 16, 2010

Chapter 1: Transceiver and Tool Overview

Table 1-5: GTH Quad Attribute Summary (Cont’d)

RX_P2_CTRL 16-bit Hex

RX_PI_CTRL0 16-bit Hex

RX_PI_CTRL1 16-bit Hex

SIM_GTHRESET_SPEEDUP Integer

SIM_VERSION String

SLICE_CFG 16-bit Hex

Attribute Type

SLICE_NOISE_CTRL_0_LANE01

SLICE_NOISE_CTRL_0_LANE23

SLICE_NOISE_CTRL_1_LANE01

SLICE_NOISE_CTRL_1_LANE23

SLICE_NOISE_CTRL_2_LANE01

SLICE_NOISE_CTRL_2_LANE23

SLICE_TX_RESET_LANE01

SLICE_TX_RESET_LANE23

TERM_CTRL_LANE0

TERM_CTRL_LANE1

TERM_CTRL_LANE2

TERM_CTRL_LANE3

TX_CFG0_LANE0

TX_CFG0_LANE1

TX_CFG0_LANE2

TX_CFG0_LANE3

TX_CFG1_LANE0

16-bit Hex

TX_CFG1_LANE1

TX_CFG1_LANE2

TX_CFG1_LANE3

TX_CFG2_LANE0

TX_CFG2_LANE1

TX_CFG2_LANE2

TX_CFG2_LANE3

TX_CLK_SEL0_LANE0

TX_CLK_SEL0_LANE1

TX_CLK_SEL0_LANE2

TX_CLK_SEL0_LANE3

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16-bit Hex

UG371 (v2.0) February 16, 2010

Table 1-5: GTH Quad Attribute Summary (Cont’d)

Attribute Type

TX_CLK_SEL1_LANE0

Port and Attribute Summary

TX_CLK_SEL1_LANE1

TX_CLK_SEL1_LANE2

TX_CLK_SEL1_LANE3

TX_DISABLE_LANE0

TX_DISABLE_LANE1

TX_DISABLE_LANE2

TX_DISABLE_LANE3

TX_FABRIC_WIDTH0

TX_FABRIC_WIDTH1

TX_FABRIC_WIDTH2

TX_FABRIC_WIDTH3

TX_P0P0S_CTRL 16-bit Hex

TX_P1P2_CTRL 16-bit Hex

TX_PREEMPH_LANE0

TX_PREEMPH_LANE1

TX_PREEMPH_LANE2

TX_PREEMPH_LANE3

16-bit Hex

Integer

16-bit Hex

TX_PWR_RATE_OVRD_LANE0

TX_PWR_RATE_OVRD_LANE1

TX_PWR_RATE_OVRD_LANE2

TX_PWR_RATE_OVRD_LANE3

16-bit Hex

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UG371 (v2.0) February 16, 2010

Chapter 1: Transceiver and Tool Overview

Virtex-6 FPGA GTH Transceiver Wizard

The Virtex-6 FPGA GTH Transceiver Wizard is the preferred tool to generate a wrapper to instantiate a GTH transceiver primitive called GTHE1_QUAD. The Wizard can be found in the CORE Generator tool. The user is recommended to download the most up-to-date IP update before using the Wizard. Details on how to use this Wizard can be found in UG691, Virtex-6 FPGA GTH Transceiver Wizard Getting Started Guide.

1. Start the CORE Generator tool.

2. Locate the Virtex-6 FPGA GTH Transceiver Wizard in the taxonomy tree under: /FPGA Features & Design/IO Interfaces (see Figure 1-1, page 12).

X-Ref Target - Figure 1-3

UG371_c1_03_080609

Figure 1-3: Virtex-6 FPGA GTH Transceiver Wizard

3. Double-click Virtex-6 FPGA GTH Transceiver Wizard to launch the Wizard.

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UG371 (v2.0) February 16, 2010

+ 118 hidden pages

Xilinx Virtex-6 FPGA GTH Transceivers User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Revision History

Table of Contents

About This Guide

Guide Contents

Additional Documentation

Additional Resources

Transceiver and Tool Overview

Overview

Port and Attribute Summary

Virtex-6 FPGA GTH Transceiver Wizard