Xilinx Virtex-6 FPGA GTH Transceivers User Manual

Virtex-6 FPGA GTH Transceivers

User Guide

UG371 (v2.0) February 16, 2010

Xilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to you solely for use in the development of designs to oper ate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of an y corrections or updates . Xi linx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information.

THE DOCUMENTA TI ON IS DISCLOSED TO YOU “AS-IS” WITH NO WARRANTY OF ANY KIND. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DOCUMENTATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PAR T ICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OF THE DOCUMENTATION.

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Virtex-6 FPGA GTH Transceivers User Guide www.xilinx.com UG371 (v2.0) February 16, 2010

Revision History

The following table shows the revision history for this document.

Date Version Revision

09/16/09 1.0 Initial Xilinx release.

02/16/10 2.0

Changed the clock domain for the RXPOWERDOWNx[1:0] ports in Ta b l e 1-3, p a g e 15, Ta bl e 2 -1 0,

page 56, and Table 2-12, page 66. Chapter 1: Updated OTU-3 values in Ta bl e 1 -1. In Ta bl e 1- 3, renamed DO port to DRPDO and

relocated ports I, IB, and O to new Ta bl e 1 - 4.

Chapter 2: In the GTHRESET description in Ta b le 2- 7 and Tab le 2 -1 0, indicated that GTHINIT must

be pulsed only after GTHRESET is deasserted. In Ta bl e 2- 1 0 and Ta b le 2- 1 2, changed RXPOWERDOWN and TXPOWERDOWN descriptions for the x4 link case. Added Reference

Clock Input Structure, page 43. Removed reference to LVDS clocks as being able to drive the

reference clock pins, page 44. Added sentence about MMCM and BUFR to TSTREFCLKOUT port description in Ta bl e 2 -4 . Added PLL, page 48. Revised Figure 2-12, Figure 2-13, and Figure 2-14. In

Ta bl e 2 -11 , changed the meaning of bit code 110 for bits [13:11] and [10:8] of the

PCS_MODE_LANE attribute to Reserved; changed the 8B/10B reset value for the PCS_RESET_LANE attribute; added reference to the Virtex-6 FPGA GTH Transceiver Wizard to attribute PCS_RESET_1_LANE, bits [15:2]. In Ta bl e 2 -1 4, added the encoding to the PMA_LPBK_CTRL_LANE attribute description; changed the Reserved bits for [13:11] and [10:8] in the PCS_MODE_LANE attribute; added reference to the Virtex-6 FPGA GTH Transceiver Wizard to attribute PMA_LPBK_CTRL_LANE, bits [15:2]. In Ta bl e 2 -1 5 , changed the name of port DO[15:0] to DRPDO[15:0]. Added note about DISABLEDRP to Using the DRP Interface, page 70 and Using the Management Interface, page 72.

Chapter 3: Added 32 and 64 bits to 8B/10B mode in Ta bl e 3 -1 . Added two rows to 8B/10B Mode

for 32-bit and 64-bit fabric interface data width in Tab l e 3 -2 . Revised manual adjustment mode settings for the BUFFER_CONFIG_LANE attribute in Ta bl e 3 -4 , and changed the meaning of bit code 110 for bits [13:11] and [10:8] of the PCS_MODE_LANE attribute to Reserved in Tab l e 3 -4 ,

Ta bl e 3 -6 , Ta bl e 3 -8 , and Ta bl e 3 -1 0. Added reference to the Virtex-6 FPGA GTH Transceiver Wizard

to attribute PCS_RESET_1_LANE, bits [15:2] in Tab le 3- 6 . Changed the 8B/10B reset value for the PCS_RESET_LANE attribute in Ta bl e 3 -6 , Tab le 3 -8 the Virtex-6 FPGA GTH Transceiver Wizard to attribute PCS_RESET_1_LANE, bits [15:2] in

Ta bl e 3 -1 0. Changed the PCS_RESET_LANE value in step 2 of Enabling 8B/10B Mode, page 85. In Ta bl e 3 -1 2, and added reference to the Virtex-6 FPGA GTH Transceiver Wizard to attribute

PRBS_CFG_LANE, bits [15:4] and PCS_RESET_1_LANE, bits [15:2]; changed the Reserved bits for [13:11] and [10:8] in the PCS_MODE_LANE attribute. In Tab le 3 -1 3 , added reference to the Virtex-6 FPGA GTH Transceiver Wizard to attribute PCS_MISC_CFG_0_LANE, bits [15:12] and [5:0]. Added TX Configurable Driver.

Chapter 4: Added RX Analog Front End, RX Equalization, and RX CDR. Added reference to the

Virtex-6 FPGA GTH Transceiver Wizard to attribute PCS_MISC_CFG_0_LANE, bits [15:12] and [5:0] in Ta bl e 4 -8 , and to attributes PCS_MISC_CFG_0_LANE, bits [15:12] and [5:0], PCS_RESET_1_LANE bits [15:2], and PRBS_CFG_LANE bits [15:4] in Ta bl e 4 -1 0. In the Functional Description section of RX Pattern Checker, added paragraph about when the checker is forced into PRBS31 mode, and added two sentences at the end of the section. Added Tab l e 4 -9 . Changed the 8B/10B reset value for the PCS_RESET_LANE attribute in Ta bl e 4 -1 0, Ta bl e 4 -1 3, Ta bl e 4 -1 6 , and

Ta bl e 4 -1 8. Deleted PRBS checker reference in Description of RXCODEERR in Ta bl e 4 -1 2, Ta bl e 4 -1 5, Ta bl e 4 -1 7, and Ta bl e 4 - 21 . In Tab le 4- 13 , Ta bl e 4- 1 6, Ta bl e 4 - 18 , and Tab l e 4- 2 2, changed

transmitter to receiver in the description of RX_FABRIC_WIDTH, and changed the meaning of bit code 110 for bits [13:11] and [10:8] of the PCS_MODE_LANE attribute to Reserved. In Ta bl e 4 - 13 ,

Ta bl e 4 -1 6, and Ta bl e 4 -1 8 , added reference to the Virtex-6 FPGA GTH Transceiver Wizard to

attribute PCS_RESET_1_LANE, bits [15:2]. Changed the PCS_RESET_LANE value in step 2 of

Enabling 8B/10B Mode, page 130. Added 32 and 64 bits to 8B/10B mode in Ta bl e 4 -1 9. Added two

rows to 8B/10B Mode for 32-bit and 64-bit fabric interface data width in Tab le 4 -2 0 manual adjustment mode

Added Chapter 5, Board Design Guidelines.

settings for the BUFFER_CONFIG_LANE attribute in Ta bl e 4 -2 2 .

, Ta

b le 3 - 10 , and Tab le 3 -1 2. Added reference to

. Revised

UG371 (v2.0) February 16, 2010 www.xilinx.com Virtex-6 FPGA GTH Transceivers User Guide

Virtex-6 FPGA GTH Transceivers User Guide www.xilinx.com UG371 (v2.0) February 16, 2010

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Chapter 1: Transceiver and Tool Overview

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Port and Attribute Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Virtex-6 FPGA GTH Transceiver Wizard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

FF1155 Package Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

FF1923 and FF1924 Package Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Chapter 2: Shared Transceiver Features

Reference Clock Input Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Using the Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Reference Clock Distribution and Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Clocking from an External Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Clocking from a Neighboring GTH Quad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

PLL Settings for the Common Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Reset and Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

GTH Quad Initialization in Response to Completion of Configuration . . . . . . . . . . . 60

GTH Quad Reset in Response to GTHRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Resetting the Transmit Datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Resetting the Receive Datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Using Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

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Far-end Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Near-end PCS Loopback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Near-end PMA Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Dynamic Reconfiguration Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Using the DRP Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Using the Management Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Chapter 3: Transmitter

FPGA TX Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Transmit Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Configuring the Transmitter for Multi-lane Applications . . . . . . . . . . . . . . . . . . . . . . . 82

TX 8B/10B Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Enabling 8B/10B Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

TX 64B/66B Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Enabling 64B/66B Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

TX Raw Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Enabling Raw Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

TX Pattern Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

TX Polarity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Using TX Polarity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

TX Configurable Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Setting the TX Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Amplitude (Swing) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Post-Cursor Emphasis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Pre-Cursor Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Chapter 4: Receiver

RX Analog Front End. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Interfacing to the RX AFE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

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RX Equalization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Setting the RX Equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

DFE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

CTLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

RX CDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

RX Polarity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Using RX Polarity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

RX Pattern Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Using RX Pattern Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

RX Raw Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Enabling Raw Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Using the Barrel Shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

RX 64B/66B Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Enabling 64B/66B Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

RX 8B/10B Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Enabling 8B/10B Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Using Comma Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

FPGA RX Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Receive Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Configuring the Receiver for Multi-lane Applications . . . . . . . . . . . . . . . . . . . . . . . . . 137

Chapter 5: Board Design Guidelines

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Pin Description and Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

GTH Quad Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Termination Resistor Calibration Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Reference Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

GTH Transceiver Reference Clock Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Reference Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

LVPECL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

AC Coupled Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Unused Reference Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Reference Clock Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

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Power Supplies and Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Power Supply Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Linear vs. Switching Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

SelectIO Interface Usage Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

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About This Guide

This document describes how to use the GTH transceivers in Virtex®-6 FPGAs. In this document:

• Virtex-6 FPGA GTH transceiver is abbreviated as GTH transceiver.

• GTHE1_QUAD is the name of the instantiation primitive that instantiates one

Virtex-6 FPGA GTH transceiver.

•A Quad is a cluster or set of four GTH transceivers that share two differential reference

clock pin pairs and analog supply pins.

• GTH lane [n] refers to a specific lane within the GTH Quad, where n = 0, 1, 2, or 3.

•The terms FPGA logic and fabric refer to internal FPGA circuitry not including the

GTH transceiver.

Guide Contents

Preface

This manual contains the following chapters:

• Chapter 1, Transceiver and Tool Overview

• Chapter 2, Shared Transceiver Features

• Chapter 3, Transmitter

• Chapter 4, Receiver

• Chapter 5, Board Design Guidelines

Additional Documentation

The following documents are also available for download at

http://www.xilinx.com/support/documentation/virtex-6.htm

• Virtex-6 Family Overview

The features and product selection of the Virtex-6 family are outlined in this overview.

• Virtex-6 FPGA Data Sheet: DC and Switching Characteristics

This data sheet contains the DC and Switching Characteristic specifications for the Virtex-6 family.

• Virtex-6 FPGA Packaging and Pinout Specifications

This specification includes the tables for device/package combinations and maximum I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and thermal specifications.

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UG371 (v2.0) February 16, 2010

Preface: About This Guide

• Virtex-6 FPGA Configuration User Guide

• Virtex-6 FPGA SelectIO Resources User Guide

• Virtex-6 FPGA Clocking Resources User Guide

• Virtex-6 FPGA Memory Resources User Guide

• Virtex-6 FPGA Configurable Logic Block User Guide

• Virtex-6 FPGA DSP48E1 Slice User Guide

This all-encompassing configuration guide includes chapters on configuration interfaces (serial and SelectMAP), bitstream encryption, boundary-scan and JTAG configuration, reconfiguration techniques, and readback through the SelectMAP and JTAG interfaces.

This guide describes the SelectIO™ resources available in all Virtex-6 devices.

This guide describes the clocking resources available in all Virtex-6 devices, including the MMCM and PLLs.

The functionality of the block RAM and FIFO are described in this user guide.

This guide describes the capabilities of the configurable logic blocks (CLBs) available in all Virtex-6 devices.

This guide describes the architecture of the DSP48E1 slice in Virtex-6 FPGAs and provides configuration examples.

• Virtex-6 FPGA GTX Transceivers User Guide

This guide describes the GTX transceivers available in all Virtex-6 FPGAs except the XC6VLX760.

• Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC User Guide

This guide describes the dedicated Tri-Mode Ethernet Media Access Controller available in all Virtex-6 FPGAs except the XC6VLX760.

• Virtex-6 FPGA System Monitor User Guide

The System Monitor functionality available in all Virtex-6 devices is outlined in this guide.

• Virtex-6 FPGA PCB Designer Guide

This guide provides information on PCB design for Virtex-6 FPGA GTX transceivers, with a focus on strategies for making design decisions at the PCB and interface level.

Additional Resources

To find additional documentation, see the Xilinx website at:

http://www.xilinx.com/support/documentation/index.htm

To search the Answer Database of silicon, software, and IP questions and answers, or to create a technical support WebCase, see the Xilinx website at:

http://www.xilinx.com/support

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Transceiver and Tool Overview

Overview

The Virtex®-6 FPGA GTH transceiver is highly configurable and tightly integrated with the programmable logic resources of the FPGA. It provides these features to support a wide variety of applications:

• Current Mode Logic (CML) serial drivers/buffers with configurable termination and voltage swing

• Support for multiple industry standards with the following line rates:

• 2.488 Gb/s to 2.795 Gb/s

• 9.953 Gb/s to 11.18 Gb/s

•One PLL per GTH Quad

GTH lanes within a Quad can be configured with different line rates that are integer multiples of each other (i.e., full line rate and line rate/4)

Chapter 1

• Linear equalizer with adaptive gain control and programmable boost

• Selectable DFE with three TAPs that can either be controlled manually or by an automatic adaptive engine

• Three-tap FIR filter for the TX driver

Support for pre-cursor and post-cursor pre-emphasis

• Optional built-in PCS features

• 8B/10B encoder/decoder with comma alignment

• 64B/66B block based on the IEEE 802.3-2008 Clause 49 implementation

• Raw mode (non-encoded datapath)

• PRBS generator and checker

• Configurable fabric interface width

• DRP and management interface to access the configuration registers

The Xilinx® CORE Generator™ tool includes a Wizard to automatically configure GTH transceivers to support configurations for different protocols or perform custom configuration (see Virtex-6 FPGA GTH Transceiver Wizard, page 30).

Figure 1-1 shows the GTH transceiver placement in an example Virtex-6 FPGA device

(XC6VHX255T).

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Chapter 1: Transceiver and Tool Overview

MMCM

GTHE1_QUAD

Column

GTXE1 Column

GTXE1_

X1Y10

GTXE1_

X1Y9

GTXE1_

X1Y8

GTXE1_

X1Y7

GTXE1_

X1Y6

GTXE1_

X1Y5

GTXE1_

X1Y4

GTXE1_

X1Y3

GTXE1_

X1Y2

GTXE1_

X1Y1

GTXE1_

X1Y0

GTXE1_

X1Y11

GTHE1_

QUAD_

X1Y2

GTHE1_

QUAD_

X1Y1

GTHE1_

QUAD_

X1Y0

GTHE1_QUAD

Column

GTXE1 Column

GTXE1_

X0Y10

GTXE1_

X0Y9

GTXE1_

X0Y8

GTXE1_

X0Y7

GTXE1_

X0Y6

GTXE1_

X0Y5

GTXE1_

X0Y4

GTXE1_

X0Y3

GTXE1_

X0Y2

GTXE1_

X0Y1

GTXE1_

X0Y0

GTXE1_

X0Y11

GTHE1_

QUAD_

X0Y2

GTHE1_

QUAD_

X0Y1

GTHE1_

QUAD_

X0Y0

MMCM

I/O

Collumn

Configuration

I/O

Collumn

PCI

Express

PCI

Express

Ether

net

MAC

Ethernet

MAC

MMCM

UG371_c1_01_082109

X-Ref Target - Figure 1-1

Figure 1-1: GTH Transceiver Inside the Virtex-6 XC6VHX255T FPGA

Notes relevant to Figure 1-1:

1. This figure does not illustrate exact size, location, or scale of the functional blocks to each other. It does show the correct number of available resources.

2. To improve clarity, this figure does not show the CLB, DSP, and block RAM columns.

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X-Ref Target - Figure 1-2

UG371_c1_02_120809

GTH3

Fabric Data, Control, and Clock for GTH3

PCS

PCS to Fabric

Interface

TX3

RX3

GTH2

Fabric Data, Control, and Clock for GTH2

PCS

PCS to Fabric

Interface

TX2

RX2

GTH1

Fabric Data, Control, and Clock for GTH1

PCS

PCS to Fabric

Interface

TX1

RX1

GTH0

GTH QUAD

Fabric Data, Control, and Clock for GTH0

PCS

PCS to Fabric

Interface

TX0

RX0

PMA

PLL

Reset and

Power-Down

Controls

DRP Interface

Management Interface Unit

REFCLK

Overview

Figure 1-2 shows a diagram of the GTH Quad, containing four GTH transceivers, a PLL,

and shared resources for controlling and initializing the Quad.

Figure 1-2: GTH Quad Block Diagram

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Chapter 1: Transceiver and Tool Overview

Tab le 1 -1 shows example PLL settings of GTH transceivers that are compatible with the

protocol line rate.

Table 1-1: PLL Settings for Protocol Sta ndards

Standard Line Rate [Gb/s]

10GBASE-R 10.3125 156.25 33 5.16 1

CEI11 11.1 173.37 32 5.55 1

OC-192

9.953

OC-48 2.488

OTU-1 2.667

OTU-2 10.71

OTU-3 10.75

OTU-4 11.18

XFP 9.953 155.52 32 4.98 1

Reference Clock

Frequency [MHz]

155.52 32 4.98 1

622.08 8 4.98 1

155.52 32 4.98 4

622.08 8 4.98 4

167.33 32 5.35 4

669.38 8 5.35 4

167.33 32 5.35 1

669.38 8 5.35 1

168.05 32 5.38 1

672.19 8 5.38 1

174.69 32 5.59 1

698.75 8 5.59 1

PLL Clock

Multiplier, N

PLL Frequency

[GHz]

PLL Output

Divider, D

XLAUI 10.3125 156.25 33 5.16 1

CAUI 10.3125 156.25 33 5.16 1

Port and Attribute Summary

This section contains alphabetical tables of power pins, ports, and attributes for the GTH transceiver.

For all ports mentioned in this guide:

• Names that end with 0 are for the GTH0 transceiver on the Quad

• Names that end with 1 are for the GTH1 transceiver on the Quad

• Names that end with 2 are for the GTH2 transceiver on the Quad

• Names that end with 3 are for the GTH3 transceiver on the Quad

• Port names that do not end with 0, 1, 2 or 3 are shared.

For all attributes mentioned in this guide:

• Names that end with LANE0 are for the GTH0 transceiver on the Quad

• Names that end with LANE1 are for the GTH1 transceiver on the Quad

• Names that end with LANE2 are for the GTH2 transceiver on the Quad

• Names that end with LANE3 are for the GTH3 transceiver on the Quad

• Attribute names that do not end with LANE0, LANE1, LANE2 or LANE3 are shared.

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Port and Attribute Summary

Tab le 1 -2 lists alphabetically the signal names and directions of the GTH transceiver analog

pins.

Table 1-2: GTH Analog Pin Summary

Pin Dir

(1)

MGTHAGND_[L,R]

MGTHAVCC_[L,R]

MGTHAVCCPLL_[L,R]

MGTHAVCCRX_[L,R]

MGTHAVTT_[L,R]

MGTRBIAS In

MGTREFCLKP/MGTREFCLKN In

MGTTXP0/MGTTXN0

MGTTXP1/MGTTXN1

Out

MGTTXP2/MGTTXN2

MGTTXP3/MGTTXN3

MGTRXP0/MGTRXN0

MGTRXP1/MGTRXN1

MGTRXP2/MGTRXN2

MGTRXP3/MGTRXN3

Notes:

1. These are power supply pins.

Tab le 1 -3 lists alphabetically the signal names, directions, and clock domain of the GTH

Quad ports.

Table 1-3: GTH Quad Port Summary

Port Dir Clock Domain

DADDR[15:0] In DCLK

DCLK In N/A

DEN In DCLK

DFETRAINCTRL0

DFETRAINCTRL1

In DCLK

DFETRAINCTRL2

DFETRAINCTRL3

DI[15:0] In DCLK

DISABLEDRP In DCLK

DRPDO[15:0] Out DCLK

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Chapter 1: Transceiver and Tool Overview

Table 1-3: GTH Quad Port Summary (Cont’d)

Port Dir Clock Domain

DRDY Out DCLK

DWE In DCLK

GTHINIT In DCLK

GTHINITDONE Out DCLK

GTHRESET In Async

GTHX2LANE01 In Async

GTHX2LANE23 In Async

GTHX4LANE In Async

MGMTPCSLANESEL[3:0] In DCLK

MGMTPCSMMDADDR[4:0] In DCLK

MGMTPCSRDACK Out DCLK

MGMTPCSRDDATA[15:0] Out DCLK

MGMTPCSREGADDR[15:0] In DCLK

MGMTPCSREGRD In DCLK

MGMTPCSREGWR In DCLK

MGMTPCSWRDATA[15:0] In DCLK

PLLPCSCLKDIV[5:0] In DCLK

PLLREFCLKSEL[2:0] In DCLK

POWERDOWN0

POWERDOWN1 TXUSERCLKIN1

POWERDOWN2 TXUSERCLKIN2

POWERDOWN3 TXUSERCLKIN3

REFCLK In N/A

RXBUFRESET0

RXBUFRESET1 RXUSERCLKIN1

RXBUFRESET2 RXUSERCLKIN2

RXBUFRESET3 RXUSERCLKIN3

RXCODEERR0[7:0]

TXUSERCLKIN0

RXUSERCLKIN0

RXCODEERR1[7:0] RXUSERCLKIN1

RXCODEERR2[7:0] RXUSERCLKIN2

RXCODEERR3[7:0] RXUSERCLKIN3

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Out

UG371 (v2.0) February 16, 2010

Table 1-3: GTH Quad Port Summary (Cont’d)

Port Dir Clock Domain

Port and Attribute Summary

RXCTRL0[7:0]

RXCTRL1[7:0] RXUSERCLKIN1

Out

RXCTRL2[7:0] RXUSERCLKIN2

RXCTRL3[7:0] RXUSERCLKIN3

RXCTRLACK0

RXCTRLACK1 TXUSERCLKIN1

Out

RXCTRLACK2 TXUSERCLKIN2

RXCTRLACK3 TXUSERCLKIN3

RXDATA0[63:0]

RXDATA1[63:0] RXUSERCLKIN1

Out

RXDATA2[63:0] RXUSERCLKIN2

RXDATA3[63:0] RXUSERCLKIN3

RXDISPERR0[7:0]

RXDISPERR1[7:0] RXUSERCLKIN1

Out

RXDISPERR2[7:0] RXUSERCLKIN2

RXDISPERR3[7:0] RXUSERCLKIN3

RXUSERCLKIN0

TXUSERCLKIN0

RXUSERCLKIN0

RXENCOMMADET0

RXENCOMMADET1 RXUSERCLKIN1

RXENCOMMADET2 RXUSERCLKIN2

RXENCOMMADET3 RXUSERCLKIN3

RXN0

RXN1

RXN2

RXN3

In (Pad) RX Serial Clock

RXP0

RXP1

RXP2

RXP3

RXPOLARITY0

RXPOLARITY1 RXUSERCLKIN1

RXPOLARITY2 RXUSERCLKIN2

RXPOLARITY3 RXUSERCLKIN3

RXUSERCLKIN0

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Table 1-3: GTH Quad Port Summary (Cont’d)

Port Dir Clock Domain

RXPOWERDOWN0[1:0]

RXPOWERDOWN1[1:0] TXUSERCLKIN1

RXPOWERDOWN2[1:0] TXUSERCLKIN2

RXPOWERDOWN3[1:0] TXUSERCLKIN3

RXRATE0[1:0]

RXRATE1[1:0] TXUSERCLKIN1

RXRATE2[1:0] TXUSERCLKIN2

RXRATE3[1:0] TXUSERCLKIN3

RXSLIP0

RXSLIP1 RXUSERCLKIN1

RXSLIP2 RXUSERCLKIN2

RXSLIP3 RXUSERCLKIN3

RXUSERCLKIN0

RXUSERCLKIN1

In N/A

RXUSERCLKIN2

RXUSERCLKIN3

TXUSERCLKIN0

RXUSERCLKIN0

RXUSERCLKOUT0

RXUSERCLKOUT1

RXUSERCLKOUT2

RXUSERCLKOUT3

RXVALID0[7:0]

RXVALID1[7:0] RXUSERCLKIN1

RXVALID2[7:0] RXUSERCLKIN2

RXVALID3[7:0] RXUSERCLKIN3

SAMPLERATE0[2:0]

SAMPLERATE1[2:0] TXUSERCLKIN1

SAMPLERATE2[2:0] TXUSERCLKIN2

SAMPLERATE3[2:0] TXUSERCLKIN3

TSTPATH Out Async

TSTREFCLKFAB Out N/A

TSTREFCLKOUT Out N/A

Out N/A

RXUSERCLKIN0

Out

TXUSERCLKIN0

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Table 1-3: GTH Quad Port Summary (Cont’d)

Port Dir Clock Domain

Port and Attribute Summary

TXBUFRESET0

TXBUFRESET1 TXUSERCLKIN1

TXBUFRESET2 TXUSERCLKIN2

TXBUFRESET3 TXUSERCLKIN3

TXCTRL0[7:0]

TXCTRL1[7:0] TXUSERCLKIN1

TXCTRL2[7:0] TXUSERCLKIN2

TXCTRL3[7:0] TXUSERCLKIN3

TXCTRLACK0

TXCTRLACK1 TXUSERCLKIN1

Out

TXCTRLACK2 TXUSERCLKIN2

TXCTRLACK3 TXUSERCLKIN3

TXDATA0[63:0]

TXDATA1[63:0] TXUSERCLKIN1

TXDATA2[63:0] TXUSERCLKIN2

TXDATA3[63:0] TXUSERCLKIN3

TXUSERCLKIN0

TXDATAMSB0[7:0]

TXDATAMSB1[7:0] TXUSERCLKIN1

TXDATAMSB2[7:0] TXUSERCLKIN2

TXDATAMSB3[7:0] TXUSERCLKIN3

TXDEEMPH0

TXDEEMPH1 TXUSERCLKIN1

TXDEEMPH2 TXUSERCLKIN2

TXDEEMPH3 TXUSERCLKIN3

TXMARGIN0[2:0]

TXMARGIN1[2:0] TXUSERCLKIN1

TXMARGIN2[2:0] TXUSERCLKIN2

TXMARGIN3[2:0] TXUSERCLKIN3

TXUSERCLKIN0

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Chapter 1: Transceiver and Tool Overview

Table 1-3: GTH Quad Port Summary (Cont’d)

Port Dir Clock Domain

TXN0

TXN1

TXN2

TXN3

TXP0

TXP1

TXP2

TXP3

TXPOWERDOWN0[1:0]

TXPOWERDOWN1[1:0] TXUSERCLKIN1

TXPOWERDOWN2[1:0] TXUSERCLKIN2

TXPOWERDOWN3[1:0] TXUSERCLKIN3

TXRATE0[1:0]

TXRATE1[1:0] TXUSERCLKIN1

TXRATE2[1:0] TXUSERCLKIN2

TXRATE3[1:0] TXUSERCLKIN3

TXUSERCLKIN0

TXUSERCLKIN1

TXUSERCLKIN2

Out

(Pad)

In N/A

TX Serial Clock

TXUSERCLKIN0

TXUSERCLKIN3

TXUSERCLKOUT0

TXUSERCLKOUT1

TXUSERCLKOUT2

TXUSERCLKOUT3

Out N/A

The ports in Ta bl e 1 -4 are part of the GTH IBUFDS primitive.

Table 1-4: GTH Reference Clock (IBUFDS_GTHE1) Port Summary

Port Dir Clock Domain

IInAsync

IB In Async

OOutAsync

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UG371 (v2.0) February 16, 2010

Port and Attribute Summary

Tab le 1 -5 lists alphabetically the attribute names and type of the GTH Quad attributes.

Table 1-5: GTH Quad Attribute Summary

Attribute Type

BER_CONST_PTRN0 16-bit Hex

BER_CONST_PTRN1 16-bit Hex

BUFFER_CONFIG_LANE0

BUFFER_CONFIG_LANE1

16-bit Hex

BUFFER_CONFIG_LANE2

BUFFER_CONFIG_LANE3

DFE_TRAIN_CTRL_LANE0

DFE_TRAIN_CTRL_LANE1

16-bit Hex

DFE_TRAIN_CTRL_LANE2

DFE_TRAIN_CTRL_LANE3

DLL_CFG0 16-bit Hex

DLL_CFG1 16-bit Hex

E10GBASEKR_LD_COEFF_UPD_LANE0

E10GBASEKR_LD_COEFF_UPD_LANE1

16-bit Hex

E10GBASEKR_LD_COEFF_UPD_LANE2

E10GBASEKR_LD_COEFF_UPD_LANE3

E10GBASEKR_LP_COEFF_UPD_LANE0

E10GBASEKR_LP_COEFF_UPD_LANE1

16-bit Hex

E10GBASEKR_LP_COEFF_UPD_LANE2

E10GBASEKR_LP_COEFF_UPD_LANE3

E10GBASEKR_PMA_CTRL_LANE0

E10GBASEKR_PMA_CTRL_LANE1

16-bit Hex

E10GBASEKR_PMA_CTRL_LANE2

E10GBASEKR_PMA_CTRL_LANE3

E10GBASEKX_CTRL_LANE0

E10GBASEKX_CTRL_LANE1

16-bit Hex

E10GBASEKX_CTRL_LANE2

E10GBASEKX_CTRL_LANE3

E10GBASER_PCS_CFG_LANE0

E10GBASER_PCS_CFG_LANE1

16-bit Hex

E10GBASER_PCS_CFG_LANE2

E10GBASER_PCS_CFG_LANE3

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Chapter 1: Transceiver and Tool Overview

Table 1-5: GTH Quad Attribute Summary (Cont’d)

E10GBASER_PCS_SEEDA0_LANE0

Attribute Type

E10GBASER_PCS_SEEDA0_LANE1

E10GBASER_PCS_SEEDA0_LANE2

E10GBASER_PCS_SEEDA0_LANE3

E10GBASER_PCS_SEEDA1_LANE0

E10GBASER_PCS_SEEDA1_LANE1

E10GBASER_PCS_SEEDA1_LANE2

E10GBASER_PCS_SEEDA1_LANE3

E10GBASER_PCS_SEEDA2_LANE0

E10GBASER_PCS_SEEDA2_LANE1

E10GBASER_PCS_SEEDA2_LANE2

E10GBASER_PCS_SEEDA2_LANE3

E10GBASER_PCS_SEEDA3_LANE0

E10GBASER_PCS_SEEDA3_LANE1

E10GBASER_PCS_SEEDA3_LANE2

E10GBASER_PCS_SEEDA3_LANE3

E10GBASER_PCS_SEEDB0_LANE0

E10GBASER_PCS_SEEDB0_LANE1

E10GBASER_PCS_SEEDB0_LANE2

16-bit Hex

E10GBASER_PCS_SEEDB0_LANE3

E10GBASER_PCS_SEEDB1_LANE0

E10GBASER_PCS_SEEDB1_LANE1

E10GBASER_PCS_SEEDB1_LANE2

E10GBASER_PCS_SEEDB1_LANE3

E10GBASER_PCS_SEEDB2_LANE0

E10GBASER_PCS_SEEDB2_LANE1

E10GBASER_PCS_SEEDB2_LANE2

E10GBASER_PCS_SEEDB2_LANE3

E10GBASER_PCS_SEEDB3_LANE0

E10GBASER_PCS_SEEDB3_LANE1

E10GBASER_PCS_SEEDB3_LANE2

E10GBASER_PCS_SEEDB3_LANE3

16-bit Hex

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UG371 (v2.0) February 16, 2010

Table 1-5: GTH Quad Attribute Summary (Cont’d)

Attribute Type

E10GBASER_PCS_TEST_CTRL_LANE0

Port and Attribute Summary

E10GBASER_PCS_TEST_CTRL_LANE1

E10GBASER_PCS_TEST_CTRL_LANE2

E10GBASER_PCS_TEST_CTRL_LANE3

E10GBASEX_PCS_TSTCTRL_LANE0

E10GBASEX_PCS_TSTCTRL_LANE1

E10GBASEX_PCS_TSTCTRL_LANE2

E10GBASEX_PCS_TSTCTRL_LANE3

GLBL0_NOISE_CTRL 16-bit Hex

GLBL_AMON_SEL 16-bit Hex

GLBL_DMON_SEL 16-bit Hex

GLBL_PWR_CTRL 16-bit Hex

GTH_CFG_PWRUP_LANE0

GTH_CFG_PWRUP_LANE1

GTH_CFG_PWRUP_LANE2

GTH_CFG_PWRUP_LANE3

LANE_AMON_SEL 16-bit Hex

LANE_DMON_SEL 16-bit Hex

16-bit Hex

1-bit Binary

LANE_LNK_CFGOVRD 16-bit Hex

LANE_PWR_CTRL_LANE0

LANE_PWR_CTRL_LANE1

LANE_PWR_CTRL_LANE2

LANE_PWR_CTRL_LANE3

LNK_TRN_CFG_LANE0

LNK_TRN_CFG_LANE1

LNK_TRN_CFG_LANE2

LNK_TRN_CFG_LANE3

LNK_TRN_COEFF_REQ_LANE0

LNK_TRN_COEFF_REQ_LANE1

LNK_TRN_COEFF_REQ_LANE2

LNK_TRN_COEFF_REQ_LANE3

MISC_CFG 16-bit Hex

MODE_CFG1 16-bit Hex

MODE_CFG2 16-bit Hex

MODE_CFG3 16-bit Hex

16-bit Hex

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UG371 (v2.0) February 16, 2010

Chapter 1: Transceiver and Tool Overview

Table 1-5: GTH Quad Attribute Summary (Cont’d)

MODE_CFG4 16-bit Hex

MODE_CFG5 16-bit Hex

MODE_CFG6 16-bit Hex

MODE_CFG7 16-bit Hex

PCS_ABILITY_LANE0

Attribute Type

PCS_ABILITY_LANE1

PCS_ABILITY_LANE2

PCS_ABILITY_LANE3

PCS_CTRL1_LANE0

PCS_CTRL1_LANE1

PCS_CTRL1_LANE2

PCS_CTRL1_LANE3

PCS_CTRL2_LANE0

PCS_CTRL2_LANE1

PCS_CTRL2_LANE2

PCS_CTRL2_LANE3

PCS_MISC_CFG_0_LANE0

PCS_MISC_CFG_0_LANE1

PCS_MISC_CFG_0_LANE2

PCS_MISC_CFG_0_LANE3

PCS_MISC_CFG_1_LANE0

PCS_MISC_CFG_1_LANE1

PCS_MISC_CFG_1_LANE2

16-bit Hex

PCS_MISC_CFG_1_LANE3

PCS_MODE_LANE0

PCS_MODE_LANE1

PCS_MODE_LANE2

PCS_MODE_LANE3

PCS_RESET_LANE0

PCS_RESET_LANE1

PCS_RESET_LANE2

PCS_RESET_LANE3

24 www.xilinx.com Vir tex-6 FPGA GTH Transceivers User Guide

16-bit Hex

UG371 (v2.0) February 16, 2010

Table 1-5: GTH Quad Attribute Summary (Cont’d)

Attribute Type

PCS_RESET_1_LANE0

Port and Attribute Summary

PCS_RESET_1_LANE1

PCS_RESET_1_LANE2

PCS_RESET_1_LANE3

PCS_TYPE_LANE0

PCS_TYPE_LANE1

PCS_TYPE_LANE2

PCS_TYPE_LANE3

PLL_CFG0 16-bit Hex

PLL_CFG1 16-bit Hex

PLL_CFG2 16-bit Hex

PMA_CTRL1_LANE0

PMA_CTRL1_LANE1

PMA_CTRL1_LANE2

PMA_CTRL1_LANE3

PMA_CTRL2_LANE0

PMA_CTRL2_LANE1

PMA_CTRL2_LANE2

16-bit Hex

PMA_CTRL2_LANE3

PMA_LPBK_CTRL_LANE0

PMA_LPBK_CTRL_LANE1

PMA_LPBK_CTRL_LANE2

PMA_LPBK_CTRL_LANE3

PRBS_BER_CFG0_LANE0

PRBS_BER_CFG0_LANE1

PRBS_BER_CFG0_LANE2

PRBS_BER_CFG0_LANE3

PRBS_BER_CFG1_LANE0

PRBS_BER_CFG1_LANE1

PRBS_BER_CFG1_LANE2

PRBS_BER_CFG1_LANE3

PRBS_CFG_LANE0

PRBS_CFG_LANE1

PRBS_CFG_LANE2

PRBS_CFG_LANE3

16-bit Hex

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UG371 (v2.0) February 16, 2010

Chapter 1: Transceiver and Tool Overview

Table 1-5: GTH Quad Attribute Summary (Cont’d)

PTRN_CFG0_LSB 16-bit Hex

PTRN_CFG0_MSB 16-bit Hex

PTRN_LEN_CFG 16-bit Hex

PWRUP_DLY 16-bit Hex

RX_AEQ_VAL0_LANE0

Attribute Type

RX_AEQ_VAL0_LANE1

RX_AEQ_VAL0_LANE2

RX_AEQ_VAL0_LANE3

RX_AEQ_VAL1_LANE0

RX_AEQ_VAL1_LANE1

RX_AEQ_VAL1_LANE2

RX_AEQ_VAL1_LANE3

RX_AGC_CTRL_LANE0

RX_AGC_CTRL_LANE1

RX_AGC_CTRL_LANE2

RX_AGC_CTRL_LANE3

RX_CDR_CTRL0_LANE0

RX_CDR_CTRL0_LANE1

RX_CDR_CTRL0_LANE2

RX_CDR_CTRL0_LANE3

RX_CDR_CTRL1_LANE0

RX_CDR_CTRL1_LANE1

RX_CDR_CTRL1_LANE2

16-bit Hex

RX_CDR_CTRL1_LANE3

RX_CDR_CTRL2_LANE0

RX_CDR_CTRL2_LANE1

RX_CDR_CTRL2_LANE2

RX_CDR_CTRL2_LANE3

RX_CFG0_LANE0

RX_CFG0_LANE1

RX_CFG0_LANE2

RX_CFG0_LANE3

26 www.xilinx.com Vir tex-6 FPGA GTH Transceivers User Guide

16-bit Hex

UG371 (v2.0) February 16, 2010

Table 1-5: GTH Quad Attribute Summary (Cont’d)

Attribute Type

RX_CFG1_LANE0

Port and Attribute Summary

RX_CFG1_LANE1

RX_CFG1_LANE2

RX_CFG1_LANE3

RX_CFG2_LANE0

RX_CFG2_LANE1

RX_CFG2_LANE2

RX_CFG2_LANE3

RX_CTLE_CTRL_LANE0

RX_CTLE_CTRL_LANE1

RX_CTLE_CTRL_LANE2

RX_CTLE_CTRL_LANE3

RX_CTRL_OVRD_LANE0

RX_CTRL_OVRD_LANE1

RX_CTRL_OVRD_LANE2

RX_CTRL_OVRD_LANE3

RX_FABRIC_WIDTH0

RX_FABRIC_WIDTH1

RX_FABRIC_WIDTH2

16-bit Hex

Integer

RX_FABRIC_WIDTH3

RX_LOOP_CTRL_LANE0

RX_LOOP_CTRL_LANE1

RX_LOOP_CTRL_LANE2

RX_LOOP_CTRL_LANE3

RX_MVAL0_LANE0

RX_MVAL0_LANE1

RX_MVAL0_LANE2

RX_MVAL0_LANE3

RX_MVAL1_LANE0

RX_MVAL1_LANE1

RX_MVAL1_LANE2

RX_MVAL1_LANE3

RX_P0_CTRL 16-bit Hex

RX_P0S_CTRL 16-bit Hex

RX_P1_CTRL 16-bit Hex

16-bit Hex

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UG371 (v2.0) February 16, 2010

Chapter 1: Transceiver and Tool Overview

Table 1-5: GTH Quad Attribute Summary (Cont’d)

RX_P2_CTRL 16-bit Hex

RX_PI_CTRL0 16-bit Hex

RX_PI_CTRL1 16-bit Hex

SIM_GTHRESET_SPEEDUP Integer

SIM_VERSION String

SLICE_CFG 16-bit Hex

Attribute Type

SLICE_NOISE_CTRL_0_LANE01

SLICE_NOISE_CTRL_0_LANE23

SLICE_NOISE_CTRL_1_LANE01

SLICE_NOISE_CTRL_1_LANE23

SLICE_NOISE_CTRL_2_LANE01

SLICE_NOISE_CTRL_2_LANE23

SLICE_TX_RESET_LANE01

SLICE_TX_RESET_LANE23

TERM_CTRL_LANE0

TERM_CTRL_LANE1

TERM_CTRL_LANE2

TERM_CTRL_LANE3

TX_CFG0_LANE0

TX_CFG0_LANE1

TX_CFG0_LANE2

TX_CFG0_LANE3

TX_CFG1_LANE0

16-bit Hex

TX_CFG1_LANE1

TX_CFG1_LANE2

TX_CFG1_LANE3

TX_CFG2_LANE0

TX_CFG2_LANE1

TX_CFG2_LANE2

TX_CFG2_LANE3

TX_CLK_SEL0_LANE0

TX_CLK_SEL0_LANE1

TX_CLK_SEL0_LANE2

TX_CLK_SEL0_LANE3

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16-bit Hex

UG371 (v2.0) February 16, 2010

Table 1-5: GTH Quad Attribute Summary (Cont’d)

Attribute Type

TX_CLK_SEL1_LANE0

Port and Attribute Summary

TX_CLK_SEL1_LANE1

TX_CLK_SEL1_LANE2

TX_CLK_SEL1_LANE3

TX_DISABLE_LANE0

TX_DISABLE_LANE1

TX_DISABLE_LANE2

TX_DISABLE_LANE3

TX_FABRIC_WIDTH0

TX_FABRIC_WIDTH1

TX_FABRIC_WIDTH2

TX_FABRIC_WIDTH3

TX_P0P0S_CTRL 16-bit Hex

TX_P1P2_CTRL 16-bit Hex

TX_PREEMPH_LANE0

TX_PREEMPH_LANE1

TX_PREEMPH_LANE2

TX_PREEMPH_LANE3

16-bit Hex

Integer

16-bit Hex

TX_PWR_RATE_OVRD_LANE0

TX_PWR_RATE_OVRD_LANE1

TX_PWR_RATE_OVRD_LANE2

TX_PWR_RATE_OVRD_LANE3

16-bit Hex

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UG371 (v2.0) February 16, 2010

Chapter 1: Transceiver and Tool Overview

Virtex-6 FPGA GTH Transceiver Wizard

The Virtex-6 FPGA GTH Transceiver Wizard is the preferred tool to generate a wrapper to instantiate a GTH transceiver primitive called GTHE1_QUAD. The Wizard can be found in the CORE Generator tool. The user is recommended to download the most up-to-date IP update before using the Wizard. Details on how to use this Wizard can be found in UG691, Virtex-6 FPGA GTH Transceiver Wizard Getting Started Guide.

1. Start the CORE Generator tool.

2. Locate the Virtex-6 FPGA GTH Transceiver Wizard in the taxonomy tree under: /FPGA Features & Design/IO Interfaces (see Figure 1-1, page 12).

X-Ref Target - Figure 1-3

UG371_c1_03_080609

Figure 1-3: Virtex-6 FPGA GTH Transceiver Wizard

3. Double-click Virtex-6 FPGA GTH Transceiver Wizard to launch the Wizard.

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UG371 (v2.0) February 16, 2010

Simulation

Functional Description

For simulating a design with GTH transceivers, SecureIP libraries must be compiled using the COMPXLIB tool. For more details on SecureIP, COMPXLIB, and setting up the simulation environment, refer to UG626

Ports and Attributes

There are no simulation-only ports. The GTHE1_QUAD primitive has attributes intended only for simulation. Ta bl e 1- 6 lists the

simulation-only attributes of the GTHE1_QUAD primitive. The names of these attributes start with SIM_.

Table 1-6: Simulation Attributes

Attribute Type Description

SIM_GTHRESET_SPEEDUP Integer This attribute shortens the number of DCLK cycles required to finish the

GTHRESET sequence during simulation (deassertion of GTHRESET to the assertion of GTHINITDONE).

0: The GTHRESET sequence is simulated with its original duration (standard initialization is approximately 360 μs for a 50

1: The GTHRESET cycle time is shortened (fast initialization is approximately 50 μs for a 50

, Synthesis and Simulation Design Guide.

MHz DCLK).

SIM_VERSION Real This attribute selects the simulation version to match different steppings

of silicon. The default for this attribute is 1.0.

Implementation

Functional Description

This section provides the information needed to map Virtex-6 FPGA GTH transceivers instantiated in a design to device resources, including:

• The location of the GTH transceiver on the available device and package combinations.

• The pad numbers of external signals associated with each GTH transceiver.

• How the GTH Quad and clocking resources instantiated in a design are mapped to available locations with a user constraints file (UCF).

It is a common practice to define the location of the GTH Quad early in the design process to ensure correct usage of clock resources and to facilitate signal integrity analysis during board design. The implementation flow facilitates this practice through the use of location constraints in the UCF.

While this section describes how to instantiate GTH clocking components, the details of the different GTH transceiver clocking options are discussed in Reference Clock

Distribution and Selection, page 45.

The position of the GTH Quad is specified by an XY coordinate system that describes the column number and its relative position within that column. In the Virtex-6 HXT device,

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UG371 (v2.0) February 16, 2010

Chapter 1: Transceiver and Tool Overview

there are packages with all the GTH Quads located in a single column along one side of the die, and other packages with all GTH Quads located on both the left column (X0) and right column (X1) of the die.

There are two ways to create a UCF for designs that use the GTH transceiver. The preferred method is to use the Virtex-6 FPGA GTH Transceiver Wizard (see Virtex-6 FPGA GTH

Transceiver Wizard, page 30). The Wizard automatically generates a UCF file from the

example design. The UCF file generated by the Wizard can then be edited to customize operating parameters and placement information for the application.

The second approach is to create the UCF by hand. When using this approach, the designer must enter the location constraint for the GTH transceiver used in the application.

Figure 1-4 through Figure 1-12, page 41 provide the GTH Quad position information for all

available device and package combinations along with the pad numbers for the external signals associated with each GTH lane of the Quad. The list of device and package include:

• XC6VHX255T-FF1155

• XC6VHX255T-FF1923

• XC6VHX380T-FF1155

• XC6VHX380T-FF1923

• XC6VHX380T-FF1924

• XC6VHX565T-FF1923

• XC6VHX565T-FF1924

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UG371 (v2.0) February 16, 2010

FF1155 Package Diagrams

HX255T: GTHE1_QUAD_X1Y2 HX380T: GTHE1_QUAD_X1Y2

B6 B5

Right edge of the die

MGTRXP3_118 MGTRXN3_118

B2 B1

MGTTXP3_118 MGTTXN3_118

A8 A7

MGTRXP2_118 MGTRXN2_118

UG371_C1_04_080609

A4 A3

MGTTXP2_118 MGTTXN2_118

C4 C3

MGTREFCLKP_118 MGTREFCLKN_118

C8 C7

MGTRXP1_118 MGTRXN1_118

D2 D1

MGTTXP1_118 MGTTXN1_118

E8 E7

MGTRXP0_118 MGTRXN0_118

E4 E3

MGTTXP0_118 MGTTXN0_118

Figure 1-4 through Figure 1-6, page 35 show the placement diagrams for the FF1155

package.

X-Ref Target - Figure 1-4

Implementation

Figure 1-4: Placement Diagram for the FF1155 Package (1 of 3)

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UG371 (v2.0) February 16, 2010

Chapter 1: Transceiver and Tool Overview

HX255T: GTHE1_QUAD_X1Y1 HX380T: GTHE1_QUAD_X1Y1

F6 F5

Right edge of the die

MGTRXP3_117 MGTRXN3_117

G4 G3

MGTTXP3_117 MGTTXN3_117

D6 D5

MGTRXP2_117 MGTRXN2_117

UG371_C1_05_080609

F2 F1

MGTTXP2_117 MGTTXN2_117

H2 H1

MGTREFCLKP_117 MGTREFCLKN_117

H6 H5

MGTRXP1_117 MGTRXN1_117

J4 J3

MGTTXP1_117 MGTTXN1_117

K6 K5

MGTRXP0_117 MGTRXN0_117

K2 K1

MGTTXP0_117 MGTTXN0_117

X-Ref Target - Figure 1-5

Figure 1-5: Placement Diagram for the FF1155 Package (2 of 3)

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UG371 (v2.0) February 16, 2010

X-Ref Target - Figure 1-6

HX255T: GTHE1_QUAD_X1Y0 HX380T: GTHE1_QUAD_X1Y0

M6 M5

Right edge of the die

MGTRXP3_116 MGTRXN3_116

M2 M1

MGTTXP3_116 MGTTXN3_116

N4 N3

MGTRXP2_116 MGTRXN2_116

UG371_C1_06_080609

L4 L3

MGTTXP2_116 MGTTXN2_116

P6 P5

MGTREFCLKP_116 MGTREFCLKN_116

R4 R3

MGTRXP1_116 MGTRXN1_116

P2 P1

MGTTXP1_116 MGTTXN1_116

U4 U3

MGTRXP0_116 MGTRXN0_116

T2 T1

MGTTXP0_116 MGTTXN0_116

Implementation

Figure 1-6: Placement Diagram for the FF1155 Package (3 of 3)

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Chapter 1: Transceiver and Tool Overview

HX255T: GTHE1_QUAD_X1Y2 HX380T: GTHE1_QUAD_X1Y2 HX565T: GTHE1_QUAD_X1Y2

D6 D5

Right edge of the die

MGTRXP3_118 MGTRXN3_118

C4 C3

MGTTXP3_118 MGTTXN3_118

B6 B5

MGTRXP2_118 MGTRXN2_118

UG371_C1_07_080609

A4 A3

MGTTXP2_118 MGTTXN2_118

E4 E3

MGTREFCLKP_118 MGTREFCLKN_118

F6 F5

MGTRXP1_118 MGTRXN1_118

D2 D1

MGTTXP1_118 MGTTXN1_118

G8 G7

MGTRXP0_118 MGTRXN0_118

F2 F1

MGTTXP0_118 MGTTXN0_118

FF1923 and FF1924 Package Diagrams

Figure 1-7 through Figure 1-12, page 41 show the placement diagrams for the FF1923 and

FF1924 packages. The XC6VHX255T device is available only in the FF1923 package.

X-Ref Target - Figure 1-7

Figure 1-7: Placement Diagram for the FF1923 and FF1924 Packages (1 of 6)

Note:

36 www.xilinx.com Vir tex-6 FPGA GTH Transceivers User Guide

The XC6VHX255T device is available only in the FF1923 package.

UG371 (v2.0) February 16, 2010

X-Ref Target - Figure 1-8

HX255T: GTHE1_QUAD_X1Y1 HX380T: GTHE1_QUAD_X1Y1 HX565T: GTHE1_QUAD_X1Y1

J8 J7

Right edge of the die

MGTRXP3_117 MGTRXN3_117

H2 H1

MGTTXP3_117 MGTTXN3_117

H6 H5

MGTRXP2_117 MGTRXN2_117

UG371_C1_08_080609

G4 G3

MGTTXP2_117 MGTTXN2_117

J4 J3

MGTREFCLKP_117 MGTREFCLKN_117

L8 L7

MGTRXP1_117 MGTRXN1_117

K2 K1

MGTTXP1_117 MGTTXN1_117

K6 K5

MGTRXP0_117 MGTRXN0_117

L4 L3

MGTTXP0_117 MGTTXN0_117

Implementation

Figure 1-8: Placement Diagram for the FF1923 and FF1924 Packages (2 of 6)

Note: The XC6VHX255T device is available only in the FF1923 package.

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Chapter 1: Transceiver and Tool Overview

HX255T: GTHE1_QUAD_X1Y0 HX380T: GTHE1_QUAD_X1Y0 HX565T: GTHE1_QUAD_X1Y0

M6 M5

Right edge of the die

MGTRXP3_116 MGTRXN3_116

N4 N3

MGTTXP3_116 MGTTXN3_116

N8 N7

MGTRXP2_116 MGTRXN2_116

UG371_C1_09_080609

M2 M1

MGTTXP2_116 MGTTXN2_116

R4 R3

MGTREFCLKP_116 MGTREFCLKN_116

T6 T5

MGTRXP1_116 MGTRXN1_116

P2 P1

MGTTXP1_116 MGTTXN1_116

U4 U3

MGTRXP0_116 MGTRXN0_116

T2 T1

MGTTXP0_116 MGTTXN0_116

X-Ref Target - Figure 1-9

Figure 1-9: Placement Diagram for the FF1923 and FF1924 Packages (3 of 6)

Note: The XC6VHX255T device is available only in the FF1923 package.

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X-Ref Target - Figure 1-10

HX255T: GTHE1_QUAD_X0Y2 HX380T: GTHE1_QUAD_X0Y2 HX565T: GTHE1_QUAD_X0Y2

D39 D40

Left edge of the die

MGTRXP3_108 MGTRXN3_108

C41 C42

MGTTXP3_108 MGTTXN3_108

B39 B40

MGTRXP2_108 MGTRXN2_108

UG371_C1_10_080609

A41 A42

MGTTXP2_108 MGTTXN2_108

E41 E42

MGTREFCLKP_108 MGTREFCLKN_108

F39 F40

MGTRXP1_108 MGTRXN1_108

D43 D44

MGTTXP1_108 MGTTXN1_108

G37 G38

MGTRXP0_108 MGTRXN0_108

F43 F44

MGTTXP0_108 MGTTXN0_108

Implementation

Figure 1-10: Placement Diagram for the FF1923 and FF1924 Packages (4 of 6)

Note: The XC6VHX255T device is available only in the FF1923 package.

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UG371 (v2.0) February 16, 2010

Chapter 1: Transceiver and Tool Overview

HX255T: GTHE1_QUAD_X0Y1 HX380T: GTHE1_QUAD_X0Y1 HX565T: GTHE1_QUAD_X0Y1

J37 J38

Left edge of the die

MGTRXP3_107 MGTRXN3_107

H43 H44

MGTTXP3_107 MGTTXN3_107

H39 H40

MGTRXP2_107 MGTRXN2_107

UG371_C1_11_080609

G41 G42

MGTTXP2_107 MGTTXN2_107

J41 J42

MGTREFCLKP_107 MGTREFCLKN_107

L37 L38

MGTRXP1_107 MGTRXN1_107

K43 K44

MGTTXP1_107 MGTTXN1_107

K39 K40

MGTRXP0_107 MGTRXN0_107

L41 L42

MGTTXP0_107 MGTTXN0_107

X-Ref Target - Figure 1-11

Figure 1-11: Placement Diagram for the FF1923 and FF1924 Packages (5 of 6)

Note: The XC6VHX255T device is available only in the FF1923 package.

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X-Ref Target - Figure 1-12

HX255T: GTHE1_QUAD_X0Y0 HX380T: GTHE1_QUAD_X0Y0 HX565T: GTHE1_QUAD_X0Y0

M39 M40

Left edge of the die

MGTRXP3_106 MGTRXN3_106

N41 N42

MGTTXP3_106 MGTTXN3_106

N37 N38

MGTRXP2_106 MGTRXN2_106

UG371_C1_12_080609

M43 M44

MGTTXP2_106 MGTTXN2_106

R41 R42

MGTREFCLKP_106 MGTREFCLKN_106

T39 T40

MGTRXP1_106 MGTRXN1_106

P43 P44

MGTTXP1_106 MGTTXN1_106

U41 U42

MGTRXP0_106 MGTRXN0_106

T43 T44

MGTTXP0_106 MGTTXN0_106

Implementation

Figure 1-12: Placement Diagram for the FF1923 and FF1924 Packages (6 of 6)

Note: The XC6VHX255T device is available only in the FF1923 package.

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Chapter 1: Transceiver and Tool Overview

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Shared Transceiver Features

UG371_c2_14_120809

MGTREFCLKP

MGTREFCLKN

MGTHAVCCPLL_[L,R]

2/3 MGTHAVCCPLL_[L,R]

pll_refclk_term_b

MGTHAVCCRX_[L,R]

Nominal 50Ω

Reference Clock Input Structure

Functional Description

The reference clock input structure is illustrated in Figure 2-1. The input is terminated internally with 50Ω on each leg to 2/3 MGTHAVCCPLL. The reference clock input is instantiated in software with an IBUFDS_GTHE1 primitive. Its location is fixed via LOC constraints in the UCF. Refer to Implementation, page 31 for details.

The output of the IBUFDS_GTHE1 primitive drives the REFCLK input of the GTHE1_QUAD primitive. The ports and attributes controlling each of the IBUFDS_GTHE1 primitives are mapped to the respective GTHE1_QUAD primitive.

X-Ref Target - Figure 2-1

Chapter 2

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UG371 (v2.0) February 16, 2010

Figure 2-1: Reference Clock Input Structure

Chapter 2: Shared Transceiver Features

Ports and Attributes

Tab le 2 -1 defines the reference clock input structure ports for the GTHE1_QUAD

primitive.

Table 2-1: Reference Clock Input Structure Ports for the GTHE1_QUAD Primitive

Port Dir Clock Domain Description

REFCLK In N/A REFCLK is an external clock driven by the

Tab le 2 -2 defines the reference clock input structure ports for the IBUFDS_GTHE1 software

primitive.

Table 2-2: Reference Clock Input Structure Ports for the IBUFDS_GTHE1 Primitive

Port Dir Clock Domain Description

I In Async This port is the positive input of the reference

IB In Async This port is the negative input of the reference

O port of the IBUFDS_GTHE1 software primitive as the reference clock to the GTHE1_QUAD primitive.

clock differential pair.

O Out Async This port is the output of the reference clock

Tab le 2 -3 defines the reference clock input structure attribute for the GTHE1_QUAD

software primitive.

Table 2-3: Reference Clock Input Structure Attribute

Attribute Type Description

PLL_CFG1 16-bit Binary This attribute defaults to 16'h8440.

Using the Reference Clock

The reference clock is always used in an AC-coupled mode. The recommended value for the AC-coupling capacitors is 100 nF. The LVPECL clock must be used to drive the reference clock pins. Refer to DS152 Characteristics for electrical and switching specifications.

buffer connected to the REFCLK port of the GTHE1_QUAD primitive.

[15]: REFCLK termination control (pll_refclk_term_b)

AC-coupled mode: 1'b1 Reserved: 1'b0

[14:0]: Reserved

Reserved: 15'h0440

, Virtex-6 FPGA Data Sheet: DC and Switching

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Reference Clock Distribution and Selection

Reference Clock Distribu tion and Selection

Functional Description

For proper high-speed operation, the GTH transceiver requires a high-quality, low-jitter reference clock. Because of the shared PMA PLL architecture inside the GTH Quad, each reference clock sources all four lanes. The reference clock is used to produce the PLL clock, which is divided by one or four to make individual TX and RX serial clocks and parallel clocks for each GTH transceiver.

The GTH Quad reference clock is provided through the REFCLK port. There are two ways to drive the REFCLK port:

• Using an external oscillator to drive GTH dedicated clock routing

• Using a clock from a neighboring GTH Quad through GTH dedicated clock routing (not recommended for GTH transceivers operating a line rates 2.8 Gb/s and above)

Using the dedicated clock routing provides the best possible clock to the GTH Quad. Each GTH Quad has a dedicated clock pin, represented by the IBUFDS_GTHE1 primitive, that can be used to drive the dedicated clock routing.

This clocking section shows how to select the dedicated clocks for use by one or more GTH Quads.

Ports and Attributes

Tab le 2 -4 defines the reference clock selection ports.

Table 2-4: Reference Clock Selection Ports

Port Dir Clock Domain Description

PLLREFCLKSEL[2:0] In DCLK Reserved. Tie these inputs to 000.

REFCLK In N/A This input is the external jitter stable

TSTREFCLKFAB Out N/A This port provides direct access to

TSTREFCLKOUT Out N/A This port provides direct access to

clock driven by the IBUFDS_GTHE1 primitive as the reference clock to the GTHE1_QUAD primitive.

the reference clock provided to the shared PLL in the GTHE1_QUAD primitive. The clock is routed through interconnect and can be used to clock FPGA logic.

the reference clock provided to the shared PLL in the GTHE1_QUAD primitive. The clock is routed through the global clock tree (must be connected through a BUFG) and can be used to clock FPGA logic. This port can also connect directly to an MMCM or BUFR.

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Chapter 2: Shared Transceiver Features

Tab le 2 -5 defines the reference clock selection attributes.

Table 2-5: Reference Clock Selection Attributes

Attribute Type Description

PLL_CFG2 16-bit Hex Reserved. Use the recommended values from the

Clocking from an External Source

Each GTH Quad has a dedicated pin that can be connected to an external clock source. To use these pins, an IBUFDS_GTHE1 primitive is instantiated. In the user constraints file (UCF), the IBUFDS_GTHE1 input pins are constrained to the locations of the dedicated clock pins for the GTH Quad. In the design, the output of the IBUFDS_GTHE1 primitive is connected to the REFCLK input port. The locations of the dedicated pins for all GTH Quads are documented in Implementation, page 31.

Figure 2-2 shows a differential GTH clock pin pair sourced by an external oscillator on the

board.

X-Ref Target - Figure 2-2

Virtex®-6 FPGA GTH Transceiver Wizard.

GTHE1_QUAD

MGTREFCLKP

MGTREFCLKN

Figure 2-2: Single GTHE1_QUAD Clocked Externally

Clocking from a Neighboring GTH Quad

The external reference clock from one GTH Quad can be used to drive the REFCLK input port of the neighboring GTH Quad. The example in Figure 2-3 uses the clock from one GTH Quad to clock one neighbor above and one neighbor below. A GTH Quad shares its clock with its neighbors using the dedicated clock routing resources.

REFCLK

UG371_c2_01_082609

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X-Ref Target - Figure 2-3

Reference Clock Distribution and Selection

Tied Off Float

GTHE1_QUAD

OFF

MGTREFCLKP

MGTREFCLKN

REFCLK

PLL

GTHE1_QUAD

OFF

REFCLK

PLL

GTHE1_QUAD

OFF

REFCLK

PLL

Tied Off Float

UG371_c2_02_082609

Figure 2-3: Multiple GTHE1_QUADs with Shared Reference Clock

These rules must be observed when sharing a reference clock to ensure that jitter margins for high-speed designs are met:

1. The sharing of a reference clock is allowed only for 2.8 Gb/s and below.

2. The external reference clock that drives the REFCLK input port of a given quad (the sourcing GTH Quad) needs to be used by the PLL in the same Quad due to the position of the REFCLK multiplexer.

3. The number of GTH Quads above the sourcing GTH Quad must not exceed one.

4. The number of GTH Quads below the sourcing GTH Quad must not exceed one.

5. The reference clock cannot be routed across the FPGA to the other GTH Quad column.

6. The reference clock cannot be shared with a neighboring GTX transceiver.

The maximum number of GTH transceivers that can be sourced by a single clock pin pair is 12.

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Chapter 2: Shared Transceiver Features

PLL

Functional Description

Each GTHE1_QUAD primitive has one PLL block that is shared between the four lanes within the Quad. Each lane in the GTH Quad has separate dividers for the transmitter and the receiver, which allow each transmitter and receiver to operate in different divided-down line rates based on the VCO frequency. The PLL in one GTHE1_QUAD primitive cannot be shared with another GTH Quad.

The PLL has an operating range from 4.96 GHz to 5.591 GHz with the lane divider, which can divide the output of the PLL by one or four. Ta bl e 2- 6 shows the supported line rate and PLL settings in the GTH transceiver.

Table 2-6: Supported Line Rates per TX and RX Lane Divider Settings

TX and RX PLL Lane Divider Line Rate Range (Gb/s)

Figure 2-4 illustrates the PLL architecture. A low phase noise PLL input clock is

recommended for optimal jitter performance. The feedback divider determines the VCO multiplication and the PLL output frequency.

1 9.920 – 11.182

4 2.48 – 2.58

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X-Ref Target - Figure 2-4

UG371_c2_15_120809

TX PMA

Lane 0

TX Div:

RX CDR

RX Div:

TX PMA

Lane 1

TX Div:

RX CDR

PLL CLKIN

PLL Block

RX Div:

PFD VCO

Charge

Pump

Loop Filter

Feedback

Divider: M

Interface

Block

TX PMA

Lane 2

TX Div:

RX CDR

RX Div:

TX PMA

Lane 3

TX Div:

RX CDR

RX Div:

TX_LineRatefPLLClkin

-------

×=

RX_LineRatefPLLClkin

------- -

×=

PLL

The feedback divider value (M), part of the PLL_CFG0 attribute, is set by the Virtex-6 FPGA GTH Transceiver Wizard. The TX output lane divider (D TXRATE port, and the RX output lane divider (D

Equation 2-1 shows how to determine the TX line rate (Gb/s).

Equation 2-2 shows how to determine the RX line rate (Gb/s).

Figure 2-4: PLL Block Diagram

) is set by the RXRATE ports.

) is set by the

Equation 2-1

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UG371 (v2.0) February 16, 2010

Equation 2-2

Chapter 2: Shared Transceiver Features

The PLL output clock is used to generate the PCS clocks. There are three dividers to generate different PCS clocks (see Figure 2-5):

• PLLPCSCLKDIV

• SAMPLERATE (must have the same setting as TXRATE)

• TX_FABRIC_WIDTH/RX_FABRIC_WIDTH

Figure 2-5 shows the relationship between the dividers in the PCS block. The

PLLPCSCLKDIV ports determines the PCS clock frequency common across all the lanes in the Quad. The SAMPLERATE port divides the Quad PCS clock and determine the internal lane PCS clock for the each lane. The FABRIC_WIDTH attributes need to have correct values to get the correct TXUSERCLKOUT and RXUSERCLKOUT values, depending on the ratio between the FPGA logic data bus width and internal data bus width.

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UG371_c2_16_020210

RX_FABRIC_WIDTH0

TX_FABRIC_WIDTH0

SAMPLERATE0[2:0]

RX PCS Clock for Lane 0

TXUSERCLK0

TX PCS

Clock for

Lane 0

Quad

PCS

Clock

RXUSERCLK0

RECCLK0

Lane 0

TX Lane PCS

Clock Divider

QUAD

PLL

PMA Block

Common TX

PCS Clock

Divider for

GTH Quad

RX PCS Clock

Divider 0

TX Fabric

Clock Divider

PLLPCSCLKDIV[5:0]

SIPO_Data_Width0

RX Fabric

Clock Divider

RX_FABRIC_WIDTH1

TX_FABRIC_WIDTH1

SAMPLERATE1[2:0]

RX PCS Clock for Lane 1

TXUSERCLK1

TX PCS

Clock for

Lane 1

RXUSERCLK1

Lane 1

TX Lane PCS

Clock Divider

TX Fabric

Clock Divider

RX Fabric

Clock Divider

RX_FABRIC_WIDTH2

TX_FABRIC_WIDTH2

SAMPLERATE2[2:0]

RX PCS Clock for Lane 2

TXUSERCLK2

TX PCS

Clock for

Lane 2

RXUSERCLK2

Lane 2

TX Lane PCS

Clock Divider

TX Fabric

Clock Divider

RX Fabric

Clock Divider

RX_FABRIC_WIDTH3

TX_FABRIC_WIDTH3

SAMPLERATE3[2:0]

RX PCS Clock for Lane 3

TXUSERCLK3

TX PCS

Clock for

Lane 3

RXUSERCLK3

Lane 3

TX Lane PCS

Clock Divider

TX Fabric

Clock Divider

RX Fabric

Clock Divider

CDR0

RECCLK1

RX PCS Clock

Divider 1

SIPO_Data_Width1

CDR1

RECCLK2

RX PCS Clock

Divider 2

SIPO_Data_Width2

CDR2

RECCLK3

RX PCS Clock

Divider 3

SIPO_Data_Width3

CDR3

X-Ref Target - Figure 2-5

PLL

Figure 2-5: TX and RX Parallel Clock Dividers in the PCS Block

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Chapter 2: Shared Transceiver Features

Ports and Attributes

Tab le 2 -7 defines the PLL ports.

Table 2-7: PLL Ports

Port Dir Clock Domain Description

GTHINIT In DCLK This input triggers the programming of

GTHINITDONE Out DCLK This port goes High when the process of

the attributes setting from configuration memory to the registers in the GTHE1_QUAD primitive.

This port must be asserted for 1 DCLK clock cycle.

programming the bits from the configuration memory to the registers in the GTHE1_QUAD primitive is completed.

This output is driven Low when GTHRESET or GTHINIT is asserted. It remains Low until after the assertion of GTHINIT.

GTHRESET In DCLK This port resets the GTHE1_QUAD

primitive. When this port is asserted, the configuration of all GTH transceivers within the GTHE1_QUAD primitive reverts to the default setting of 10GBASE-R. To maintain the same user configuration, GTHINIT must be pulsed after GTHRESET is deasserted.

This port must be asserted for 1 DCLK clock cycle.

PLLPCSCLKDIV[5:0] In DCLK PLL output divider for the GTH Quad

PCS clock. This port specifies the divider for the PCS clock frequency. It must be set to N – 1 to achieve an N division of the PLL clock frequency.

RXCTRLACK0

RXCTRLACK1

RXCTRLACK2

RXCTRLACK3

Out TXUSERCLKIN0

TXUSERCLKIN1

TXUSERCLKIN2

TXUSERCLKIN3

Assertion of this acknowledgment signal indicates completion of a change event on RXRATE<n> and RXPOWERDOWN<n>.

The state of this port is valid only after GTHINITDONE is driven High and TXUSERCLKIN<n> is stable.

This port is not asserted until all internal clocks for the RX datapath, including the PLL output clock, are stable.

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Table 2-7: PLL Ports (Cont’d)

Port Dir Clock Domain Description

PLL

RXRATE0[1:0]

RXRATE1[1:0]

RXRATE2[1:0]

RXRATE3[1:0]

SAMPLERATE0[2:0]

SAMPLERATE1[2:0]

SAMPLERATE2[2:0]

SAMPLERATE3[2:0]

TXCTRLACK0

TXCTRLACK1

TXCTRLACK2

TXCTRLACK3

In TXUSERCLKIN0

TXUSERCLKIN1

TXUSERCLKIN2

TXUSERCLKIN3

In TXUSERCLKIN0

TXUSERCLKIN1

TXUSERCLKIN2

TXUSERCLKIN3

Out TXUSERCLKIN0

TXUSERCLKIN1

TXUSERCLKIN2

TXUSERCLKIN3

This control signal specifies the receiver lane divider values:

00: Full data rate 10: 1/4 data rate

All other encodings are reserved.

This port is active after the TX side becomes active. TXUSERCLKIN<n> must be stable to use this port.

This port must always be set to 2'b00 during initialization and when GTHRESET is asserted.

This control signal specifies the frequency of the strobe signal relative to the internal transmitter PCS clock after the transmitter lane dividers:

000: Full rate 010: 1/4 rate

All other encodings are reserved. This port must always be set to 3'b000

during initialization and when GTHRESET is asserted.

Assertion of this acknowledgment signal indicates completion of a change event on TXRATE<n>, SAMPLERATE<n>, and TXPOWERDOWN<n>.

The state of this port is valid only after GTHINITDONE is driven High and TXUSERCLKIN<n> is stable.

This port is not asserted until all internal clocks for the TX datapath, including the PLL output clock, are stable.

TXRATE0[1:0]

TXRATE1[1:0]

TXRATE2[1:0]

TXRATE3[1:0]

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In TXUSERCLKIN0

TXUSERCLKIN1

TXUSERCLKIN2

TXUSERCLKIN3

This control signal specifies the transmitter lane divider values:

00: Full data rate 10: 1/4 data rate

All other encodings are reserved. This port must always be set to 2'b00

during initialization and when GTHRESET is asserted.

Chapter 2: Shared Transceiver Features

Tab le 2 -8 defines the PLL attributes.

Table 2-8: PLL Attributes

Attribute Type Description

DLL_CFG0 16-bit Hex Reserved. Use the recommended values from the

DLL_CFG1 16-bit Hex Reserved. Use the recommended values from the

PLL_CFG0 16-bit Hex Reserved. Use the recommended values from the

PLL_CFG1 16-bit Hex Reserved. Use the recommended values from the

PLL_CFG2 16-bit Hex Reserved. Use the recommended values from the

Virtex-6 FPGA GTH Transceiver Wizard.

[15:6]: Reserved

[5:0]: PLL feedback divider

Virtex-6 FPGA GTH Transceiver Wizard.

RX_FABRIC_WIDTH0

RX_FABRIC_WIDTH1

RX_FABRIC_WIDTH2

RX_FABRIC_WIDTH3

TX_FABRIC_WIDTH0

TX_FABRIC_WIDTH1

TX_FABRIC_WIDTH2

TX_FABRIC_WIDTH3

Integer This attribute sets the mapping of the internal data

width (PCS) to the external data width (fabric) for the receiver. Valid settings are:

“16” (DRP value 3'b000): PCS to Fabric 1:1 “20” (DRP value 3'b000): PCS to Fabric 1:1 “32” (DRP value 3'b011): PCS to Fabric 1:2 32 bit “40” (DRP value 3'b101): PCS to Fabric 1:2 40 bit “64” (DRP value 3'b010): PCS to Fabric 1:4 64 bit “80” (DRP value 3'b110): PCS to Fabric 1:4 80 bit “6466” (DRP value 3'b111): 64B/66B mode

Integer This attribute sets the mapping of the internal data

width (PCS) to the external data width (fabric) for the transmitter. Valid settings are:

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Reset and Initialization

PLL Settings for the Common Protocol

Tab le 2 -9 shows example PLL divider settings for several standard protocols that the GTH

transceiver supports.

Table 2-9: PLL Divider Settings for Common Protocols

Protocol

10GBASE-KR 10.3125 156.25 32 5.15625 2'b00 32 156.25 3'b000 156.25 3'b111 156.25

CEI11 11.096 173.37 31 5.54784 2'b00 7 693.75 3'b000 693.75 3'b010 173.44

OC-192

OC-48

OTU1

OTU3

OTU4

XFP 9.953 155.52 31 4.9765 2'b00 7 622.07 3'b000 622.07 3'b010 155.52

Line Rate

10.7546 168.05 31 5.3773 2'b00 7 672.16 3'b000 672.16 3'b010 168.04

10.7546 672.19 7 5.3773 2'b00 7 672.16 3'b000 672.16 3'b010 168.04

REFCLK

[Gb/s]

9.953 155.52 31 4.9765 2'b00 7 622.06 3'b000 622.06 3'b010 155.52

9.953 311.03 15 4.9765 2'b00 7 622.06 3'b000 622.06 3'b010 155.52

9.953 622.06 7 4.9765 2'b00 7 622.06 3'b000 622.06 3'b010 155.52

2.488 155.52 31 4.976 2'b10 7 622.06 3'b010 155.5 3'b000 155.5

2.488 311.03 15 4.976 2'b10 7 622.06 3'b010 155.5 3'b000 155.5

2.488 622.06 7 4.976 2'b10 7 622.06 3'b010 155.5 3'b000 155.5

2.677 166.69 31 5.334 2'b10 7 666.75 3'b010 166.69 3'b000 166.69

2.677 666.75 7 5.334 2'b10 7 666.75 3'b010 166.69 3'b000 166.69

10.709 167.33 31 5.35456 2'b00 7 669.31 3'b000 669.31 3'b010 167.33

10.709 669.31 7 5.35504 2'b00 7 669.31 3'b000 669.31 3'b010 167.33

11.18 174.69 31 5.590 2'b00 7 698.75 3'b000 698.75 3'b010 174.69

11.18 698.75 7 5.590 2'b00 7 698.75 3'b000 698.75 3'b010 174.69

[MHz]

PLL Feedback

Divider

PLL_CFG0[5:0]

(N – 1)

PLL Freq

[GHz]

TXRATE

RXRATE

PLLPCSCLKDIV

(N – 1)

Quad

PCS Clock [MHz]

SAMPLE

RATE

Lane

TX_FABRIC_WIDTH

PCS

RX_FABRIC_WIDTH

Clock

(Note 1)

TXUSERCLK RXUSERCLK

Notes:

1. The settings for the TX_FABRIC_WIDTH and RX_FABRIC_WIDTH listed in this table are examples. The settings depend on the external data width that the user selects for the fabric logic.

Reset and Initialization

Functional Description

The different ways to reset the GTH Quad are:

1. Power-up and configure the FPGA.

2. Apply a reset sequence to the GTHRESET and GTHINIT ports.

3. Reset the PCS logic using the power-down ports.

All these methods are described in this section.

These items must be considered to initialize the GTH Quad properly:

• DCLK must always be provided to the GTHE1_QUAD primitive even if the DRP or management interface is not used.

Note:

DCLK must be sourced from a free-running clock. It cannot be sourced from

TSTREFCLKOUT or TSTREFCLKFAB of the GTH Quad.

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Chapter 2: Shared Transceiver Features

• Asserting GTHRESET not only resets the GTH Quad but also changes its configuration back to its default of 10GBASE-R. For example, if the design is configured for OC-192, asserting GTHRESET changes the configuration to 10GBASE-R.

• To keep the user configuration after GTHRESET is deasserted, GTHINIT must be pulsed.

• Both TXUSERCLKIN<n> and RXUSERCLKIN<n> clocks must be stable when TXPOWERDOWN<n> and RXPOWERDOWN<n> are set in normal operation mode.

• The PCS_MODE_LANE<n>, PCS_RESET_LANE<n>, and PCS_RESET_1_LANE<n> attributes must be set to the datapath mode configuration used in the application.

Ports and Attributes

Tab le 2 -1 0 defines the reset ports.

Table 2-10: Reset Ports

Port Dir Clock Domain Description

DCLK In N/A This input is the DRP interface clock. It is also used as the

management interface clock when the management interface is enabled. This clock must be connected and available all the time for the GTHE1_QUAD primitive to initialize properly, even if the DRP or the management interface is not used in the design.

GTHINIT In DCLK This input triggers the programming of the attributes

setting from configuration memory to the registers in the GTHE1_QUAD primitive.

This port must be asserted for 1 DCLK clock cycle.

GTHINITDONE Out DCLK This port is driven High upon completion of programming

the bits from the configuration memory to the registers in the GTHE1_QUAD primitive.

This output is driven Low when GTHRESET or GTHINIT is asserted. It remains Low until after the assertion of GTHINIT.

GTHRESET In DCLK This port resets the GTHE1_QUAD primitive. When this

port is asserted, the configuration of all GTH transceivers within the GTHE1_QUAD primitive reverts to the default setting of 10GBASE-R. To maintain the same user configuration, GTHINIT must be pulsed after GTHRESET is deasserted.

This port must be asserted for 1 DCLK clock cycle.

RXBUFRESET0

RXBUFRESET1

RXBUFRESET2

RXBUFRESET3

In RXUSERCLKIN0

RXUSERCLKIN1

RXUSERCLKIN2

RXUSERCLKIN3

This input resets the buffer inside the RX data converter (see

Figure 4-5, page 136). Both the internal RX clock and

RXUSERCLKIN<n> applied to the buffer.

(1)

must be stable before a reset can be

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Table 2-10: Reset Ports (Cont’d)

Port Dir Clock Domain Description

Reset and Initialization

RXCTRLACK0

RXCTRLACK1

RXCTRLACK2

RXCTRLACK3

RXPOWERDOWN0[1:0]

RXPOWERDOWN1[1:0]

RXPOWERDOWN2[1:0]

RXPOWERDOWN3[1:0]

RXRATE0[1:0]

RXRATE1[1:0]

RXRATE2[1:0]

RXRATE3[1:0]

Out TXUSERCLKIN0

TXUSERCLKIN1

TXUSERCLKIN2

TXUSERCLKIN3

In TXUSERCLKIN0

TXUSERCLKIN1

TXUSERCLKIN2

TXUSERCLKIN3

In TXUSERCLKIN0

TXUSERCLKIN1

TXUSERCLKIN2

TXUSERCLKIN3

Assertion of this acknowledgment signal indicates completion of a change event on RXRATE<n> and RXPOWERDOWN<n>.

The state of this port is valid only after GTHINITDONE is driven High and TXUSERCLKIN<n> is stable.

This control signal requests the receiver power state:

00: Normal operation. 10: Power off receiver logic. The PLL continues to

operate in this state.

This port must always be set to 2'b10 during initialization and when GTHRESET is asserted.

If the Quad is configured as a x4 link, only the port from Lane 0 is valid.

This control signal specifies the receiver lane divider values:

00: Full data rate 10: 1/4 data rate

All other encodings are reserved.

This port is active after the TX side becomes active. TXUSERCLKIN<n> must be stable to use this port.

This port must always be set to 2'b00 during initialization and when GTHRESET is asserted.

RXUSERCLKIN0

RXUSERCLKIN1

RXUSERCLKIN2

RXUSERCLKIN3

SAMPLERATE0[2:0]

SAMPLERATE1[2:0]

SAMPLERATE2[2:0]

SAMPLERATE3[2:0]

TXBUFRESET0

TXBUFRESET1

TXBUFRESET2

TXBUFRESET3

TXCTRLACK0

TXCTRLACK1

TXCTRLACK2

TXCTRLACK3

In N/A This port provides a clock for the internal receiver PCS

datapath. It is a buffered version of RXUSERCLKOUT<n>.

In TXUSERCLKIN0

TXUSERCLKIN1

TXUSERCLKIN2

TXUSERCLKIN3

In TXUSERCLKIN0

TXUSERCLKIN1

TXUSERCLKIN2

TXUSERCLKIN3

Out TXUSERCLKIN0

TXUSERCLKIN1

TXUSERCLKIN2

TXUSERCLKIN3

This control signal specifies the frequency of the strobe signal relative to the internal transmitter PCS clock after the transmitter lane dividers:

000: Full rate 010: 1/4 rate

All other encodings are reserved. This port must always be set to 3'b000 during

initialization and when GTHRESET is asserted.

This input resets the buffer inside the TX data converter (see

Figure 3-2, page 81). Both the internal TX clock and

TXUSERCLKIN<n> must be stable before a reset can be applied to the buffer.

This acknowledgment signal indicates completion of a change event on TXRATE<n>, SAMPLERATE<n>, and TXPOWERDOWN<n>.

The state of this port is valid only after the GTHINITDONE is driven High and TXUSERCLKIN<n> is stable.

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Table 2-10: Reset Ports (Cont’d)

Port Dir Clock Domain Description

TXPOWERDOWN0[1:0]

TXPOWERDOWN1[1:0]

TXPOWERDOWN2[1:0]

TXPOWERDOWN3[1:0]

TXRATE0[1:0]

TXRATE1[1:0]

TXRATE2[1:0]

TXRATE3[1:0]

TXUSERCLKIN0

TXUSERCLKIN1

TXUSERCLKIN2

TXUSERCLKIN3

Notes:

1. <n> denotes lane 0, 1, 2, or 3.

In TXUSERCLKIN0

TXUSERCLKIN1

TXUSERCLKIN2

TXUSERCLKIN3

This control signal requests the transmitter power state:

00: Normal operation 10: Power off transmitter logic. The PLL continues to

operate in this state.

This port must always be set to 2'b10 during initialization and when GTHRESET is asserted.

If the Quad is configured as a x4 link, only the port from Lane 0 is valid.

In TXUSERCLKIN0

TXUSERCLKIN1

TXUSERCLKIN2

TXUSERCLKIN3

This control signal specifies the transmitter lane divider values:

00: Full data rate 10: 1/4 data rate

All other encodings are reserved. This port must always be set to 2'b00 during initialization

and when GTHRESET is asserted.

In N/A This port provides a clock for the internal transmitter PCS

datapath. It is a buffered version of the TXUSERCLKOUT<n>.

This clock must be stable for RXCTRLACK<n> and RXRATE<n> ports to be active.

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Tab le 2 -11 defines the reset attributes.

Table 2-11: Reset Attributes

Attribute Type Description

Reset and Initialization

PCS_MODE_LANE0

PCS_MODE_LANE1

PCS_MODE_LANE2

PCS_MODE_LANE3

16-bit Hex This attribute sets the PCS mode.

[15]: Loopback serializer/deserializer RX to serializer/deserializer TX

[14]: Loopback PCS TX to PCS RX

[13:11]: PRBS generator mode

000: None 001: PRBS7 010: PRBS9 011: PRBS11 100: PRBS23 101: PRBS31

Others: Reserved

[10:8]: PRBS checker mode

000: None 001: PRBS7 010: PRBS9 011: PRBS11 100: PRBS23 101: PRBS31

Others: Reserved

[7:4]: PCS RX mode

0000: Zero 0001: 64B/66B 0111: 8B/10B 1010: 16-bit raw data 1011: 20-bit raw data 1100: PRBS

Others: Reserved

[3:0]: PCS TX mode

0000: Zero 0001: 64B/66B 0111: 8B/10B 1010: 16-bit raw data 1011: 20-bit raw data 1100: PRBS

Others: Reserved

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Chapter 2: Shared Transceiver Features

Table 2-11: Reset Attributes (Cont’d)

Attribute Type Description

PCS_RESET_LANE0

PCS_RESET_LANE1

PCS_RESET_LANE2

PCS_RESET_LANE3

PCS_RESET_1_LANE0

PCS_RESET_1_LANE1

PCS_RESET_1_LANE2

PCS_RESET_1_LANE3

16-bit Hex This attribute controls the datapath resets. These bits vary by mode:

64B/66B: 0xF3FE 8B/10B: 0xFC5B Raw: 0xFF3B PRBS: 0xFFCE Default: 0xFFFF

[15:12]: Reserved

[11]: Reset 64B/66B receive

[10]: Reset 64B/66B transmit

[9]: Reset 8B/10B receive

[8]: Reset 8B/10B transmit

[7]: Reset RX FIFO

[6]: Reset RX Raw FIFO

[5]: Reset PRBS checker

[4]: Reset PRBS generator

[3]: Reserved

[2]: Reset 8B/10B TX FIFO

[1]: Reset RX loopback FIFO

[0]: Reset 64B/66B and PRBS TX FIFO

16-bit Hex [15:2]: Reserved. Use the recommended values from the Virtex-6 FPGA

GTH Transceiver Wizard.

[1:0]: These bits control the datapath resets. They vary by mode:

64B/66B: 2'b10 8B/10B: 2'b00 Raw: 2'b00 PRBS: 2'b10 Default: 2'b11

GTH Quad Initialization in Response to Completion of Configuration

Figure 2-6 shows the initialization sequence of the GTH Quad following completion of

configuration when the GTH transceiver is configured in full line rate mode (i.e., TXRATE<n>[1:0], SAMPLERATE<n>[2:0], and RXRATE<n>[1:0] ports are set to all zeros).

Follow these steps to initialize the GTH transceiver, when configured in full line rate mode:

1. Set PCS_MODE_LANE<n>[7:4] and PCS_MODE_LANE<n>[3:0] to the datapath mode used in the application for RX and TX, respectively.

2. Set PCS_RESET_LANE<n> to the datapath mode used in the application.

3. Set PCS_RESET_1_LANE<n> to the datapath mode used in the application.

4. Set TXPOWERDOWN<n>[1:0] and RXPOWERDOWN<n>[1:0] to 2'b10.

5. After completion of configuration (GSR going High), wait for GTHINITDONE to go High. The PLL is locked after GTHINITDONE is asserted.

6. Pulse TXBUFRESET for one TXUSERCLKIN clock cycle.

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X-Ref Target - Figure 2-6

GTHINITDONE

GSR

TXPOWERDOWN<n>[1:0]

TXBUFRESET<n>

TXCTRLACK<n>

RXPOWERDOWN<n>[1:0]

RXCTRLACK<n>

RXBUFRESET<n>

UG371_c2_03_080709

2Õb10 2Õb00

Reset and Initialization

7. Change TXPOWERDOWN<n>[1:0] to 2'b00 to power up the transmitter logic.

8. Wait for TXCTRLACK<n> to go High. The transmitter is ready for normal operation.

9. Change RXPOWERDOWN<n>[1:0] to 2'b00.

10. Wait for RXCTRLACK<n> to go High.

11. Pulse RXBUFRESET for one RXUSERCLKIN clock cycle. The receiver is ready for normal operation.

Figure 2-6: GTH Transceiver Initialization when in Full Line Rate Mode

Note relevant to Figure 2-6:

1. The TXCTRLACK<n> and RXCTRLACK<n> signals can be High for more than 1 DCLK clock cycle.

Figure 2-7 shows the initialization sequence of the GTH Quad following completion of

configuration when the GTH transceiver is configured in divided line rate mode (i.e., TXRATE<n>[1:0], SAMPLERATE<n>[2:0], and RXRATE<n>[1:0] ports are set to non-zero values).

Follow these steps to initialize the GTH transceiver, when configured in divided line rate mode:

1. Set PCS_MODE_LANE<n>[7:4] and PCS_MODE_LANE<n>[3:0] to the datapath mode used in the application for RX and TX, respectively.

2. Set PCS_RESET_LANE<n> to the datapath mode used in the application.

3. Set PCS_RESET_1_LANE<n> to the datapath mode used in the application.

4. Set TXPOWERDOWN<n>[1:0] and RXPOWERDOWN<n>[1:0] to 2'b10.

5. Set TXRATE<n>[1:0] and RXRATE<n>[1:0] to 2'b00, and set SAMPLERATE<n>[2:0] to 3'b000.

6. After completion of configuration (GSR going High), wait for GTHINITDONE to go High. The PLL is locked after GTHINITDONE is asserted.

7. Change TXRATE<n>[1:0] to the value used for the application and wait for TXCTRLACK to go High.

8. Change SAMPLERATE<n>[2:0] to the value used for the application and wait for TXCTRLACK to go High.

9. Pulse TXBUFRESET for one TXUSERCLKIN clock cycle.

10. Change TXPOWERDOWN<n>[1:0] to 2'b00 to power up the transmitter logic.

11. Wait for TXCTRLACK<n> to go High. The transmitter is ready for normal operation.

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Chapter 2: Shared Transceiver Features

GTHINITDONE

GSR

TXRATE <n>[1:0]

SAMPLERATE<n>[2:0]

TXPOWERDOWN<n>[1:0]

TXBUFRESET<n>

TXCTRLACK<n>

RXCTRLACK<n>

RXRATE<n>[1:0]

RXPOWERDOWN<n>[1:0]

RXBUFRESET<n>

UG371_c2_04_082609

2’b00 USER_TXRATE

3’b000 USER_SAMPLERATE

2’b10 2’b00

2’b00 USER_RXRATE

2’b10 2’b00

12. Change RXRATE<n>[1:0] to the value used for the application and wait for RXCTRLACK to go High.

13. Change RXPOWERDOWN<n>[1:0] to 2'b00.

14. Wait for RXCTRLACK<n> to go High.

15. Pulse RXBUFRESET for one RXUSERCLKIN clock cycle. The receiver is ready for normal operation.

X-Ref Target - Figure 2-7

Figure 2-7: GTH Transceiver Initialization when in Divided Line Rate Mode

Note relevant to Figure 2-7:

1. The TXCTRLACK<n> and RXCTRLACK<n> signals can be High for more than 1 DCLK clock cycle.

GTH Quad Reset in Response to GTHRESET

GTHRESET is used as a reset to all four GTH lanes within the Quad, including the PLL. Besides resetting the GTH Quad, GTHRESET also changes the Quad to its default configuration of 10GBASE-R. If the GTH Quad has a different configuration from the default of 10GBASE-R, the design must also assert GTHINIT after GTHRESET is deasserted.

Figure 2-8 shows the reset sequence of the GTH Quad following the assertion of

GTHRESET when the GTH transceiver is configured in full line rate mode (i.e., the TXRATE<n>[1:0], SAMPLERATE<n>[2:0], and RXRATE<n>[1:0] ports are set to all zeros).

Follow these steps to reset the GTH transceiver, when configured in full line rate mode:

1. Set PCS_MODE_LANE<n>[7:4] and PCS_MODE_LANE<n>[3:0] to the datapath mode used in the application for RX and TX, respectively.

2. Set PCS_RESET_LANE<n> to the datapath mode used in the application.

3. Set PCS_RESET_1_LANE<n> to the datapath mode used in the application.

4. Set TXPOWERDOWN<n>[1:0] and RXPOWERDOWN<n>[1:0] to 2'b10.

5. Assert GTHRESET for 1 DCLK clock cycle. The TXCTRLACK<n> and RXCTRLACK<n> ports from all four lanes are asserted.

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X-Ref Target - Figure 2-8

GTHINITDONE

GTHINIT

GTHRESET

TXPOWERDOWN<n>[1:0]

TXBUFRESET<n>

TXCTRLACK<n>

RXPOWERDOWN<n>[1:0]

RXCTRLACK<n>

RXBUFRESET<n>

UG371_c2_05_080809

2Õb10 2Õb00

2Õb10

(1)

2Õb00

Reset and Initialization

6. Wait for TXCTRLACK<n> and RXCTRLACK<n> from all four lanes to be deasserted and then assert GTHINIT for 1 DCLK clock cycle.

7. Wait for GTHINITDONE to go High. The PLL is locked after GTHINITDONE is asserted.

8. Pulse TXBUFRESET for one TXUSERCLKIN clock cycle.

9. Change TXPOWERDOWN<n>[1:0] to 2'b00 to power up the transmitter logic.

10. Wait for TXCTRLACK<n> to go High. The transmitter is ready for normal operation.

11. Change RXPOWERDOWN<n>[1:0] to 2'b00.

12. Wait for RXCTRLACK<n> to go High.

13. Pulse RXBUFRESET for one RXUSERCLKIN clock cycle. The receiver is ready for normal operation.

Figure 2-8: GTH Transceiver Reset when in Full Line Rate Mode

Notes relevant to Figure 2-8:

1. The TXCTRLACK<n> and RXCTRLACK<n> signals at this time refer to all four lanes within the Quad. The user must wait for all four TXCTRLACK<n> and RXCTRLACK<n> signals to be deasserted before asserting GTHINIT.

2. The TXCTRLACK<n> and RXCTRLACK<n> signals can be High for more than 1 DCLK clock cycle.

Figure 2-9 shows the reset sequence of the GTH Quad following the assertion of

GTHRESET when the GTH transceiver is configured in divided line rate mode (i.e., the TXRATE<n>[1:0], SAMPLERATE<n>[2:0], and RXRATE<n>[1:0] ports are set to non-zero values).

Follow these steps to initialize the GTH transceiver, when configured in divided line rate mode:

1. Set PCS_MODE_LANE<n>[7:4] and PCS_MODE_LANE<n>[3:0] to the datapath mode used in the application for RX and TX, respectively.

2. Set PCS_RESET_LANE<n> to the datapath mode used in the application.

3. Set PCS_RESET_1_LANE<n> to the datapath mode used in the application.

4. Set TXPOWERDOWN<n>[1:0] and RXPOWERDOWN<n>[1:0] to 2'b10.

5. Set TXRATE<n>[1:0] and RXRATE<n>[1:0] to 2'b00, and set SAMPLERATE<n>[2:0] to 3'b000.

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Chapter 2: Shared Transceiver Features

GTHINITDONE

GTHINIT

TXRATE <n>[1:0]

SAMPLERATE<n>[2:0]

TXPOWERDOWN<n>[1:0]

TXBUFRESET<n>

TXCTRLACK<n>

RXCTRLACK<n>

RXRATE<n>[1:0]

RXPOWERDOWN<n>[1:0]

RXBUFRESET<n>

UG371_c2_06_082609

2’b00 USER_TXRATE

3’b000 USER_SAMPLERATE

2’b10 2’b00

2’b00 USER_RXRATE

2’b10 2’b00

(1)

6. Assert GTHRESET for 1 DCLK clock cycle. TXCTRLACK<n> and RXCTRLACK<n> from all four lanes are asserted.

7. Wait for TXCTRLACK<n> and RXCTRLACK<n> from all four lanes to be deasserted and then assert GTHINIT for 1 DCLK clock cycle.

8. Wait for GTHINITDONE to go High. The PLL is locked after GTHINITDONE is asserted.

9. Change TXRATE<n>[1:0] to the value used for the application and wait for TXCTRLACK to go High.

10. Change SAMPLERATE<n>[2:0] to the value used for the application and wait for TXCTRLACK to go High.

11. Pulse TXBUFRESET for one TXUSERCLKIN clock cycle.

12. Change TXPOWERDOWN<n>[1:0] to 2'b00 to power up the transmitter logic.

13. Wait for TXCTRLACK<n> to go High. The transmitter is ready for normal operation.

14. Change RXRATE<n>[1:0] to the value used for the application and wait for RXCTRLACK signal to go High.

15. Change RXPOWERDOWN<n>[1:0] to 2'b00.

16. Wait for RXCTRLACK<n> to go High.

17. Pulse RXBUFRESET for one RXUSERCLKIN clock cycle. The receiver is ready for normal operation.

X-Ref Target - Figure 2-9

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Figure 2-9: GTH Transceiver Reset when in Divided Line Rate Mode

Notes relevant to Figure 2-9:

1. TXCTRLACK<n> and RXCTRLACK<n> at this time refers to all four lanes within the Quad. The user must wait for all four TXCTRLACK<n> and RXCTRLACK<n> signals to be deasserted before asserting GTHINIT.

2. The TXCTRLACK<n> and RXCTRLACK<n> signals can be High for more than 1 DCLK clock cycle.

UG371 (v2.0) February 16, 2010

Resetting the Transmit Datapath

UG371_c2_07_080809

2Õb002Õb00 2Õb10

TXCTRLACK<n>

TXPOWERDOWN[1:0]<n>

TXBUFRESET<n>

The transmit datapath of the GTH transceiver must be reset under these conditions:

•After a line rate change

• When the clock going into the TXUSERCLKIN port changes

Figure 2-10 shows the reset sequence for the transmit datapath.

X-Ref Target - Figure 2-10

Figure 2-10: GTH Reset for the Transmit Datapath

Note relevant to Figure 2-10:

1. The TXCTRLACK<n> signal can be High for more than 1 DCLK clock cycle.

Follow these steps to reset the transmit datapath in the GTH transceiver:

Reset and Initialization

1. Change TXPOWERDOWN<n>[1:0] to 2'b10 and wait for TXCTRLACK<n> to go High.

2. Assert TXBUFRESET<n> for one TXUSERCLKIN clock cycle.

3. Change TXPOWERDOWN<n>[1:0] to 2'b00. The transmitter is ready for normal operation.

Resetting the Receive Datapath

The reset datapath of the GTH transceiver must be reset under these conditions:

•After a line rate change

• When the clock going into the RXUSERCLKIN port changes

• When the receiver CDR loses lock as a result of:

• The remote link powering up

• Disconnecting and connecting RXN/RXP serial pins

Figure 2-11 shows the reset sequence for the receive datapath.

X-Ref Target - Figure 2-11

RXPOWERDOWN<n>[1:0]

RXCTRLACK<n>

RXBUFRESET<n>

Figure 2-11: GTH Reset for the Receive Datapath

2Õb002Õb00 2Õb10

UG371_c2_08_080809

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Note relevant to Figure 2-11:

1. The RXCTRLACK<n> signal can be High for more than 1 DCLK clock cycle.

Chapter 2: Shared Transceiver Features

Follow these steps to reset the receive datapath in the GTH transceiver:

1. Change RXPOWERDOWN<n>[1:0] to 2'b10 and wait for RXCTRLACK<n> to go High. The CDR is disabled.

2. Change RXPOWERDOWN<n>[1:0] to 2'b00 and wait for RXCTRLACK<n> to go High. The CDR is enabled.

3. Assert RXBUFRESET<n> for one RXUSERCLKIN clock cycle. The receiver is ready for normal operation.

Power Down

Functional Description

The GTH transceiver offers different levels of power control. Part of the power-down functionality includes resetting certain logic within the GTH transceiver.

Ports and Attributes

Tab le 2 -1 2 defines the power-down ports.

Table 2-12: Power-Down Ports

Port Dir Clock Domain Description

POWERDOWN0

POWERDOWN1

POWERDOWN2

POWERDOWN3

RXPOWERDOWN0[1:0]

RXPOWERDOWN1[1:0]

RXPOWERDOWN2[1:0]

RXPOWERDOWN3[1:0]

TXPOWERDOWN0[1:0]

TXPOWERDOWN1[1:0]

TXPOWERDOWN2[1:0]

TXPOWERDOWN3[1:0]

In TXUSERCLKIN0

TXUSERCLKIN1

TXUSERCLKIN2

TXUSERCLKIN3

TXUSERCLKIN1

TXUSERCLKIN2

TXUSERCLKIN3

TXUSERCLKIN1

TXUSERCLKIN2

TXUSERCLKIN3

This control signal powers off the corresponding lane. It is used to place individual lanes in a low power state. This port is used on a per-lane basis even when multiple lanes are configured as a single logical link.

This control signal requests the receiver power state:

00: Normal operation 10: Power-off receiver logic. The PLL continues to

operate in this state.

Th is port mus t always be set to 2'b10 during initialization and when GTHRESET is asserted.

If the Quad is configured as a x4 link, only the port from Lane 0 is valid.

This control signal requests the transmitter power state:

00: Normal operation 10: Power-off transmitter logic. The PLL continues to

operate in this state.

Th is port mus t always be set to 2'b10 during initialization and when GTHRESET is asserted.

If the Quad is configured as a x4 link, only the port from Lane 0 is valid.

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Using Power Down

Loopback

Tab le 2 -1 3 defines the power-down attributes.

Table 2-13: Power-Down Attributes

Attribute Type Description

GTH_CFG_PWRUP_LANE0

GTH_CFG_PWRUP_LANE1

GTH_CFG_PWRUP_LANE2

1-bit Binary This control attribute powers off the

corresponding lane. This attribute is set to 1'b1 to power up the corresponding GTH lane.

GTH_CFG_PWRUP_LANE3

To activate the power-down mode on a per lane basis, use either the POWERDOWN<n> port or the GTH_CFG_PWRUP_LANE<n> attribute.

The TXPOWERDOWN and RXPOWERDOWN ports are used to activate the power down on the transmitter or the receiver, respectively.

Functional Description

The GTH transceiver supports these loopback modes:

• Far-end Loopback (line loopback)

• Near-end PCS Loopback

• Near-end PMA Loopback

Far-end Loopback

The Far-end loopback mode uses external equipment to generate and check test data. The loopback occurs after passing the deserializer of the PMA. The entire PCS section is bypassed except for the data multiplexers closest to the PMA. The loopback path works only when the external test equipment uses the same reference clock as the PMA.

Figure 2-12 shows the Far-end loopback datapath.

X-Ref Target - Figure 2-12

TXN/TXP

Buffer

PMA

PCS

Serializer

Deserializer

RXN/RXP

Buffer

CDR

DFE

UG371_c2_09_020510

Figure 2-12: Far-end Loopback

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Chapter 2: Shared Transceiver Features

DFE

PMA

TXN/TXP

RXDATA

RXN/RXP

Buffer

Serializer

Deserializer

PCS

UG371_c2_10_120109

CDR

PRBS

Checker

TXDATA

PRBS

Generator

DFE

PMA

TXN/TXP

RXDATA

RXN/RXP

Buffer

Serializer

Deserializer

PCS

UG371_c2_11_120109

CDR

Pre-emphasis

Serial

Loopback

PRBS

Checker

TXDATA

PRBS

Generator

Linear EQ

Near-end PCS Loopback

In the Near-end PCS loopback mode, data is generated by user logic and looped back internal to the PCS. Then the data is checked by the user logic. Any PCS operating mode (8B/10B mode, raw mode, etc.) can be used. The PMA is not used.

Figure 2-13 shows the PCS internal loopback path.

X-Ref Target - Figure 2-13

X-Ref Target - Figure 2-14

Figure 2-13: Near-end PCS Loopback

Near-end PMA Loopback

This mode uses either user logic or the PRBS generator/checker to generate and check the test data. The serial loopback path to the RX buffer is either after the TX pre-driver (before the TX buffer) or after the TX buffer. In this mode, the operation for all enabled PCS and PMA functional blocks in the transmitter and receiver channel can be verified.

Figure 2-14 shows a simplified block diagram of the Near-end PMA loopback mode.

Figure 2-14: Near-end PMA Loopback

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Ports and Attributes

There are no loopback ports.

Tab le 2 -1 4 defines the loopback attributes.

Table 2-14: Loopback Attributes

Attribute Type Description

PMA_LPBK_CTRL_LANE0 PMA_LPBK_CTRL_LANE1 PMA_LPBK_CTRL_LANE2 PMA_LPBK_CTRL_LANE3

PCS_MODE_LANE0 PCS_MODE_LANE1 PCS_MODE_LANE2 PCS_MODE_LANE3

16-bit Hex This attribute configures the PMA loopback mode.

16-bit Hex This attribute sets the PCS mode.

Loopback

[15:2]: Reserved. Use the recommended values from the Virtex-6 FPGA GTH Transceiver Wizard.

[1:0]: Configure the source of the on-chip loopback connection to the RX:

2’b00: User loopback disabled 2’b01: TX output 2’b10: TX pre-driver 2’b11: Reserved

[15]: Loopback serializer/deserializer RX to serializer/deserializer TX [14]: Loopback PCS TX to PCS RX [13:11]: PRBS generator mode

000: None 001: PRBS7 010: PRBS9 011: PRBS11 100: PRBS23 101: PRBS31

Others: Reserved

[10:8]: PRBS checker mode

000: None 001: PRBS7 010: PRBS9 011: PRBS11 100: PRBS23 101: PRBS31

Others: Reserved

[7:4]: PCS RX mode

0000: Zero 0001: 64B/66B 0111: 8B/10B 1010: 16-bit raw data 1011: 20-bit raw data 1100: PRBS

Others: Reserved

[3:0]: PCS TX mode

0000: Zero 0001: 64B/66B 0111: 8B/10B 1010: 16-bit raw data 1011: 20-bit raw data 1100: PRBS

Others: Reserved

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Chapter 2: Shared Transceiver Features

Dynamic Reconfiguration Port

Functional Description

The dynamic reconfiguration port (DRP) allows the dynamic change of parameters of the GTHE1_QUAD primitive. The DRP interface is a processor-friendly synchronous interface with an address bus (DADDR) and separated data buses for reading (DO) and writing (DI) configuration data to the GTH Quad. An enable signal (DEN), a read/write signal (DWE), and a ready/valid signal (DRDY) are the control signals that implement read and write operations, indicate operation completion, or indicate the availability of data. Refer to

UG360

diagrams of the DRP operations.

Ports and Attributes

Tab le 2 -1 5 defines the DRP ports.

Table 2-15: DRP Ports

Port Dir Clock Domain Description

DADDR[15:0] In DCLK This input bus is the DRP address bus.

, Virtex-6 FPGA Configuration User Guide for detailed descriptions and timing

DCLK In N/A This input is the DRP interface clock. It is also used as the management

interface clock when the management interface is enabled. This clock must be connected and available all the time for the GTHE1_QUAD primitive to initialize properly, even if the DRP or the management interface is not used in the design.

DEN In DCLK This input is the DRP enable signal.

0: No read or write operation performed. 1: Enables a read or write operation.

DI[15:0] In DCLK This input bus is the data bus for writing configuration data from the FPGA

logic resources to the GTHE1_QUAD primitive.

DISABLEDRP In DCLK This input switches between the DRP and the management interface blocks.

0: DRP interface is selected. 1: Management interface is selected.

DRPDO[15:0] Out DCLK This output bus is the data bus for reading configuration data from the

GTHE1_QUAD primitive to the FPGA logic resources.

DRDY Out DCLK When asserted, this output indicates operation is complete for write

operations and data is valid for read operations.

DWE In DCLK This input is the DRP write enable:

0: Read operation when DEN is 1. 1: Write operation when DEN is 1.

Using the DRP Interface

To enable the DRP interface, the DISABLEDRP port is driven Low. When the DRP interface is enabled, the management interface must be disabled.

Note:

and the management interface, the user must wait two DCLK cycles for the change to take effect before accessing the registers.

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When the setting on the DISABLEDRP port is changed to switch between the DRP interface

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Management Interface

Functional Description

The management interface allows the dynamic change of parameters of the GTHE1_QUAD primitive. It also allows monitoring the status of certain blocks within the GTH transceiver.

The management interface has separate signals for the MMD, GTH lane, and register address fields. This interface is driven by DCLK. When the management interface is selected, the DRP interface must be disabled by setting the DISABLEDRP port.

Ports and Attributes

Tab le 2 -1 6 defines the management interface ports.

Table 2-16: Management Interface Ports

Port Dir Clock Domain Description

DCLK In N/A This input is the DRP interface clock. It is also used as the

DISABLEDRP In DCLK This input switches between the DRP and the management

interface blocks.

0: DRP interface is selected. 1: Management interface is selected.

MGMTPCSLANESEL[3:0] In DCLK These inputs select the GTH lane of the management interface:

0001: Select GTH lane 0. 0010: Select GTH lane 1. 0100: Select GTH lane 2. 1000: Select GTH lane 3.

The user can select more than one GTH lane for accessing the registers.

MGMTPCSMMDADDR[4:0] In DCLK This input bus is the MMD address bus.

MGMTPCSRDACK Out DCLK This output is the management interface read data valid signal.

It indicates when data is valid for read operations.

MGMTPCSRDDATA[15:0] Out DCLK This output bus is the management interface register read data

bus.

MGMTPCSREGADDR[15:0] In DCLK This input bus is the management interface register address bus.

MGMTPCSREGRD In DCLK This input is the management interface read request valid signal.

MGMTPCSREGWR In DCLK This input is the management interface write request valid

signal.

MGMTPCSWRDATA[15:0] In DCLK This input bus is the management interface register write data

bus.

There are no management interface attributes.

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Chapter 2: Shared Transceiver Features

Using the Management Interface

Follow these steps to enable the management interface:

1. Drive the DISABLEDRP port Low during GTH transceiver initialization.

2. When the GTHINITDONE signal goes High from completion of GTH transceiver initialization, drive the DISABLEDRP port High.

One example for implementing the above sequence in logic is to tie the DISABLEDRP port to the inverter of GTHINITDONE.

Note:

When the setting on the DISABLEDRP port is changed to switch between the DRP interface and the management interface, the user must wait two DCLK cycles for the change to take effect before accessing the registers.

Figure 2-15 is a timing diagram for reading the register through the management interface.

X-Ref Target - Figure 2-15

DISABLEDRP

DCLK

MGMTPCSLANESEL[3:0]

MGMTPCSMMDADDR[4:0]

MGMTPCSREGADDR[15:0]

MGMTPCSREGWR

MGMTPCSWRDATA[15:0]

MGMTPCSREGRD

MGMTPCSRDACK

(Select GTH Lane)

(Select MMD Address)

(Select Management Register Address)

16’h0000

(Event 1)

MGMTPCSRDDATA[15:0]

16’h0000

UG371_c2_12_020810

Figure 2-15: Management Interface Read Access Timing Diagram

The read access consists of MMD, GTH lane select, register address signals, and a single cycle pulse of the MGMTPCSREGRD signal. The read addresses must be held until the read access completes and returns an acknowledgment through the MGMTPCSRDACK signal. A read operation can be requested right after the acknowledgment indicator signal as shown in Event 1 of Figure 2-15. No read or write operation can be requested prior to the acknowledgment indicator signal.

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X-Ref Target - Figure 2-16

Management Interface

Figure 2-16 is a timing diagram for writing to the register through the management

interface.

DISABLEDRP

DCLK

MGMTPCSLANESEL[3:0]

MGMTPCSMMDADDR[4:0]

MGMTPCSREGADDR[15:0]

MGMTPCSREGWR

MGMTPCSWRDATA[15:0]

MGMTPCSREGRD

MGMTPCSRDACK

MGMTPCSRDDATA[15:0]

Figure 2-16: Management Interface Write Access Timing Diagram

The write access consists of the MMD, GTH lane select, and register address signals, the write data, and a single cycle pulse of the MGMTPCSREGWR signal. There is no acknowledgment indicator for a write operation. The management interface supports multiple write accesses by asserting the MGMTPCSREGWR signal as shown in Event 1 of

Figure 2-16.

(Select GTH Lane)

(Select MMD Address)

(Select Management Register Address)

D1 D2

(Event 1)

UG371_c2_13_020810

Multiple MGMTPCSLANESEL[3:0] signals can be asserted simultaneously for a write access.

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Chapter 2: Shared Transceiver Features

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UG371 (v2.0) February 16, 2010

Transmitter

This chapter describes how to configure and use each of the functional blocks inside the GTH transmitter (TX). Each GTH transceiver in the GTH Quad includes an independent transmitter, which consists of a PCS and a PMA.

The key elements within the GTH TX are:

• FPGA TX Interface, page 75

• TX 8B/10B Block, page 82

• TX 64B/66B Block, page 86

• TX Raw Mode, page 89

• TX Pattern Generator, page 93

• TX Polarity Control, page 96

• TX Configurable Driver, page 97

Chapter 3

FPGA TX Interface

Functional Description

The FPGA TX interface is the FPGA’s gateway to the TX datapath of the GTH transceiver. Applications transmit data through the GTH transceiver by writing data to the TXDATA port on the positive edge of TXUSERCLKIN. The width of the port can be configured depending on the mode chosen (see Tab le 3 -1 ).

Table 3-1: FPGA TX Interface Port Width

8B/10B mode • 16 bits

64B/66B mode • 64 bits

Mode Port Width

• 32 bits

• 64 bits

Raw mode • 16 bits

• 20 bits

• 32 bits

• 40 bits

• 64 bits

• 80 bits

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Chapter 3: Transmitter

The rate of the parallel clock, TXUSERCLKIN, at the interface is determined by the TX line rate, the width of the TXDATA port, and whether or not 8B/10B mode is used. A block inside the PCS handles the mapping of the internal data width to the fabric data width selected in the design.

A data width converter block is included in the transmit datapath. This block includes:

• A clock generator that takes the internal PCS clock and generates TXUSERCLKOUT

to the FPGA logic based on the external data width selected

• A four-byte-deep FIFO that handles the phase difference between the internal PCS

clock and the external user clock

• A data width converter between the internal PCS data interface and the external data

interface to the FPGA logic

The PCS_MODE_LANE<n>[3:0] attribute configures the internal data width, and the TX_FABRIC_WIDTH<n> attribute configures the external data width. Tab le 3 -2 shows how the interface width for the TX datapath is selected.

Table 3-2: FPGA TX Interface Datapath Configuration

TX Data Mode

Internal PCS Data

Width

Fabric Interface

Data Width

PCS_MODE_LANE<n>[3:0] TX_FABRIC_WIDTH<n>

8B/10B 20 bits 16 bits 0111 16

20 bits 32 bits 0111 32 20 bits 64 bits 0111 64

64B/66B 64 bits 64 bits 0001 6466 Raw 16 bits 16 bits 1010 16

16 bits 32 bits 1010 32 16 bits 64 bits 1010 64 20 bits 20 bits 1011 20 20 bits 40 bits 1011 40 20 bits 80 bits 1011 80

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X-Ref Target - Figure 3-1

UG371_c3_01_082709

RXDATA[63:0]

RXCTRL[7:0]

RXCODEERR[7:0]

8B/10B

64B/66B

Raw

PRBS

Checker

Receive

Data

Converter

PCS to Fabric

Interface

PCS

PMA

16, 20

TXDATA[63:0]

TXCTRL[7:0]

TXDATAMSB[7:0]

Raw

64B/66B

8B/10B

PRBS

Generator

Transmit

Data

Converter

16, 20

FPGA TX Interface

Figure 3-1 is a block diagram of the PCS logic. It shows the transmit datapath with the

different modes and the data converter block.

Figure 3-1: PCS B lock Diagram

The user must consider these restrictions when configuring the fabric data width:

• The fabric interface data width must be the same for both the transmitter and receiver

within a GTH lane.

• The data mode must be the same for both the transmitter and receiver within a GTH

lane.

• The data mode must be the same on all four GTH lanes within a Quad.

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Chapter 3: Transmitter

Ports and Attributes

Tab le 3 -3 defines the FPGA TX interface ports.

Table 3-3: FPGA TX Interface Ports

Port Dir Clock Domain Description

GTHX4LANE In Async When this port is asserted, GTH lanes 0, 1, 2, and 3 are

configured into a single x4 link.

TXBUFRESET0

TXBUFRESET1

TXBUFRESET2

TXBUFRESET3

TXCTRL0[7:0]

TXCTRL1[7:0]

TXCTRL2[7:0]

TXCTRL3[7:0]

TXDATA0[63:0]

TXDATA1[63:0]

TXDATA2[63:0]

TXDATA3[63:0]

In TXUSERCLKIN0

TXUSERCLKIN1

TXUSERCLKIN2

TXUSERCLKIN3

In TXUSERCLKIN0

TXUSERCLKIN1

TXUSERCLKIN2

TXUSERCLKIN3

In TXUSERCLKIN0

TXUSERCLKIN1

TXUSERCLKIN2

TXUSERCLKIN3

This port resets the buffer inside the TX data converter. Both the internal TX clock and TXUSERCLKIN<n> must be stable before a reset can be applied to the buffer.

These inputs either indicate control of TXDATA<n> or they are used as an extension of TXDATA<n> depending on the mode selected in the transmitter datapath:

8B/10B: These inputs are asserted when TXDATA<n> is an 8B/10B K character.

TXCTRL<n>[7] corresponds to TXDATA<n>[63:56]

TXCTRL<n>[6] corresponds to TXDATA<n>[55:48]

TXCTRL<n>[5] corresponds to TXDATA<n>[47:40]

TXCTRL<n>[4] corresponds to TXDATA<n>[39:32]

TXCTRL<n>[3] corresponds to TXDATA<n>[31:24]

TXCTRL<n>[2] corresponds to TXDATA<n>[23:16]

TXCTRL<n>[1] corresponds to TXDATA<n>[15:8]

TXCTRL<n>[0] corresponds to TXDATA<n>[7:0]

64B/66B: These inputs are 64B/66B control bits.

Raw mode: These inputs are used as part of TXDATA<n>[71:64].

This input bus is the transmit data bus of the transmit interface from the FPGA.

TXDATAMSB0[7:0]

TXDATAMSB1[7:0]

TXDATAMSB2[7:0]

TXDATAMSB3[7:0]

TXUSERCLKIN0

TXUSERCLKIN1

TXUSERCLKIN2

TXUSERCLKIN3

TXUSERCLKOUT0

TXUSERCLKOUT1

TXUSERCLKOUT2

TXUSERCLKOUT3

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In TXUSERCLKIN0

TXUSERCLKIN1

TXUSERCLKIN2

TXUSERCLKIN3

In N/A This port provides a clock for the internal transmitter PCS

Out N/A This port is the transmit parallel clock output based on the

This bus extends the transmit data bus as TXDATA<n>[79:72].

datapath. It is a buffered version of the TXUSERCLKOUT<n>.

This clock must be stable for the RXCTRLACK<n> and RXRATE<n> ports to be active.

transmitter data bus width, TXRATE<n>, and SAMPLERATE<n>. This clock is used to drive TXUSERCLKIN<n> through a buffer.

UG371 (v2.0) February 16, 2010

Tab le 3 -4 defines the FPGA TX interface attributes.

Table 3-4: FPGA TX Interface Attributes

Attribute Type Description

FPGA TX Interface

BUFFER_CONFIG_LANE0

BUFFER_CONFIG_LANE1

BUFFER_CONFIG_LANE2

BUFFER_CONFIG_LANE3

16-bit Hex This attribute defaults to 16’h4004.

[15:4]: TX_BUFFER_CONFIG[11:0] read pointer adjustment for TX buffer in the data converter.

• For auto adjustment mode, TX_BUFFER_CONFIG[11:0] =

12’h400.

• For manual adjustment mode, TX_BUFFER_CONFIG[11:0] settings depend on TX_FABRIC_WIDTH and if the GTH transceivers within a Quad are configured as a x4 link (GTHX4LANE = 1’b1):

• x4 (GTHX4LANE =

1’b1

): [TX_FABRIC_WIDTH] = [TX_BUFFER_CONFIG]

“16” or “20” (DRP value 3'b000): 12’h0A4 “32” (DRP value 3'b011): 12’h394 “40” (DRP value 3'b101): 12’h394 “64” (DRP value 3'b010): 12’h250 “80” (DRP value 3'b110): 12’h250 “6466” (DRP value 3'b111): 12’h0A4

x1 (GTHX4LANE = 1’b0): [

•

TX_FABRIC_WIDTH

“16” or “20” (DRP value 3'b000): 12’h23C “32” (DRP value 3'b011): 12’h0E8 “40” (DRP value 3'b101): 12’h0E8 “64” (DRP value 3'b010): 12’h3A8 “80” (DRP value 3'b110): 12’h3A8 “6466” (DRP value 3'b111): 12’h23C

[4:0]: RX_BUFFER_CONFIG[3:0] read pointer adjustment for RX buffer in the data converter.

• For auto adjustment mode, RX_BUFFER_CONFIG[3:0] = 0100.

• For manual adjustment mode, RX_BUFFER_CONFIG[3:0] settings depend on the RX_FABRIC_WIDTH:

[RX_FABRIC_WIDTH] = [RX_BUFFER_CONFIG] “16” or “20” (DRP value 3'b000): 4’b0001 “32” (DRP value 3'b011): 4’b0000 “40” (DRP value 3'b101): 4’b0000 “64” (DRP value 3'b010): 4’b0000 “80” (DRP value 3'b110): 4’b0000 “6466” (DRP value 3'b111): 4’b0001

] = [TX_BUFFER_CONFIG]

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Chapter 3: Transmitter

Table 3-4: FPGA TX Interface Attributes (Cont’d)

Attribute Type Description

PCS_MODE_LANE0

PCS_MODE_LANE1

PCS_MODE_LANE2

PCS_MODE_LANE3

16-bit Hex This attribute sets the PCS mode.

[15]: Loopback serializer/deserializer RX to serializer/deserializer TX

[14]: Loopback PCS TX to PCS RX

[13:11]: PRBS generator mode

000: None 001: PRBS7 010: PRBS9 011: PRBS11 100: PRBS23 101: PRBS31

Others: Reserved

[10:8]: PRBS checker mode

000: None 001: PRBS7 010: PRBS9 011: PRBS11 100: PRBS23 101: PRBS31

Others: Reserved

[7:4]: PCS RX mode

0000: Zero 0001: 64B/66B 0111: 8B/10B 1010: 16-bit raw data 1011: 20-bit raw data 1100: PRBS

Others: Reserved

[3:0]: PCS TX mode

0000: Zero 0001: 64B/66B 0111: 8B/10B 1010: 16-bit raw data 1011: 20-bit raw data 1100: PRBS

Others: Reserved

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Table 3-4: FPGA TX Interface Attributes (Cont’d)

UG371_c3_02_082809

Internal TX PCS Clock

TX_FABRIC_WIDTH

TXUSERCLKOUT

TXUSERCLKIN

TX Data and Control

TX PCS

to Fabric

Design

in FPGA

Transmit

Clock

Divider

Transmit

Data

Converter

GTH Transceiver

BUFG

or BUFR

Attribute Type Description

FPGA TX Interface

TX_FABRIC_WIDTH0

TX_FABRIC_WIDTH1

TX_FABRIC_WIDTH2

TX_FABRIC_WIDTH3

Transmit Clocking

Integer This attribute sets the mapping of the internal data width (PCS) to the

external data width (fabric) for the transmitter. Valid settings are:

”16” (DRP value 3'b000): PCS to Fabric 1:1 ”20” (DRP value 3'b000): PCS to Fabric 1:1 ”32” (DRP value 3'b011): PCS to Fabric 1:2 32 bits ”40” (DRP value 3'b101): PCS to Fabric 1:2 40 bits ”64” (DRP value 3'b010): PCS to Fabric 1:4 64 bits ”80” (DRP value 3'b110): PCS to Fabric 1:4 80 bits ”6466” (DRP value 3'b111): 64B/66B mode

The GTH transceiver provides a parallel clock to the FPGA TX interface, TXUSERCLKOUT. The user design must drive this clock to TXUSERCLKIN through either a BUFG or a BUFR. TXUSERCLKIN is the main synchronization clock for all signals into the TX side of the GTH transceiver.

Figure 3-2 is a block diagram of the FPGA TX interface clocking.

X-Ref Target - Figure 3-2

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UG371 (v2.0) February 16, 2010

Figure 3-2: FPGA TX Interface Clocking

The user must consider these restrictions for the transmit clocking on the GTH transceiver:

• Within a GTH Quad, the four transmitters can share one BUFG/BUFR as long as the line rate, fabric data width, and encoding are the same across the four transmitters.

• Between GTH Quads, a transmitter of one Quad can share one BUFG/BUFR with a transmitter from another Quad as long as the line rate, fabric data width, and encoding are the same across those transmitters.

• The transmitter cannot use the same clock as the receiver; that is, TXUSERCLKIN and RXUSERCLKIN cannot be sourced from the same clock.

Chapter 3: Transmitter

Configuring the Transmitter for Multi-lane Applications

The GTHX4LANE port in GTH transceivers is used for multi-lane applications that require minimum skew across channels. To configure four GTH lanes within a Quad into a single x4 link, GTHX4LANE must be tied High. When configured in a single x4 link, a change in the control settings on the master lane also causes the same effect on the slaves. An exception to this is the POWERDOWN port. In this x4 link configuration, the buffers across the four transmit data converter are synchronized for minimizing skew.

TX 8B/10B Block

Functional Description

Many protocols use 8B/10B encoding on outgoing data. 8B/10B is an industry-standard encoding scheme that trades two bits of overhead per byte for improved performance. The GTH transceiver includes an 8B/10B encoder to encode TX data without consuming FPGA resources.

Ports and Attributes

Tab le 3 -5 defines the TX 8B/10B block ports.

Table 3-5: TX 8B/10B Block Ports

Port Dir Clock Domain Description

TXCTRL0[7:0]

TXCTRL1[7:0]

TXCTRL2[7:0]

TXCTRL3[7:0]

TXDATA0[63:0]

TXDATA1[63:0]

TXDATA2[63:0]

TXDATA3[63:0]

In TXUSERCLKIN0

TXUSERCLKIN1

TXUSERCLKIN2

TXUSERCLKIN3

In TXUSERCLKIN0

TXUSERCLKIN1

TXUSERCLKIN2

TXUSERCLKIN3

These inputs indicate control of TXDATA<n> or they are used as an extension of TXDATA<n> depending on the mode selected in the transmitter datapath:

8B/10B: These inputs are asserted when TXDATA<n> is an 8B/10B K character.

TXCTRL<n>[7] corresponds to TXDATA<n>[63:56]

TXCTRL<n>[6] corresponds to TXDATA<n>[55:48]

TXCTRL<n>[5] corresponds to TXDATA<n>[47:40]

TXCTRL<n>[4] corresponds to TXDATA<n>[39:32]

TXCTRL<n>[3] corresponds to TXDATA<n>[31:24]

TXCTRL<n>[2] corresponds to TXDATA<n>[23:16]

TXCTRL<n>[1] corresponds to TXDATA<n>[15:8]

TXCTRL<n>[0] corresponds to TXDATA<n>[7:0]

64B/66B: These inputs are 64B/66B control bits.

Raw mode: These inputs are used as part of TXDATA<n>[71:64].

This input bus is the transmit data bus of the transmit interface from the FPGA.

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Tab le 3 -6 defines the TX 8B/10B block attributes.

Table 3-6: TX 8B/10B Block Attributes

Attribute Type Description

TX 8B/10B Block

PCS_MODE_LANE0

PCS_MODE_LANE1

PCS_MODE_LANE2

PCS_MODE_LANE3

16-bit Hex This attribute sets the PCS mode.

[15]: Loopback serializer/deserializer RX to serializer/deserializer TX.

[14]: Loopback PCS TX to PCS RX.

[13:11]: PRBS generator mode

000: None 001: PRBS7 010: PRBS9 011: PRBS11 100: PRBS23 101: PRBS31

Others: Reserved

[10:8]: PRBS checker mode

000: None 001: PRBS7 010: PRBS9 011: PRBS11 100: PRBS23 101: PRBS31

Others: Reserved

[7:4]: PCS RX mode

0000: Zero 0001: 64B/66B 0111: 8B/10B 1010: 16-bit raw data 1011: 20-bit raw data 1100: PRBS

Others: Reserved

[3:0]: PCS TX mode

0000: Zero 0001: 64B/66B 0111: 8B/10B 1010: 16-bit raw data 1011: 20-bit raw data 1100: PRBS

Others: Reserved

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Chapter 3: Transmitter

Table 3-6: TX 8B/10B Block Attributes (Cont’d)

Attribute Type Description

PCS_RESET_LANE0

PCS_RESET_LANE1

PCS_RESET_LANE2

PCS_RESET_LANE3

PCS_RESET_1_LANE0

PCS_RESET_1_LANE1

PCS_RESET_1_LANE2

PCS_RESET_1_LANE3

16-bit Hex This attribute controls the datapath resets. It varies by mode:

64B/66B: 0xF3FE 8B/10B: 0xFC5B Raw: 0xFF3B PRBS: 0xFFCE Default: 0xFFFF

[15:12]: Reserved

[11]: Reset 64B/66B receive

[10]: Reset 64B/66B transmit

[9]: Reset 8B/10B receive

[8]: Reset 8B/10B transmit

[7]: Reset RX FIFO

[6]: Reset RX Raw FIFO

[5]: Reset PRBS checker

[4]: Reset PRBS generator

[3]: Reserved

[2]: Reset 8B/10B TX FIFO

[1]: Reset RX loopback FIFO

[0]: Reset 64B/66B and PRBS TX FIFO

16-bit Hex [15:2]: Reserved. Use the recommended values from theVirtex-6

FPGA GTH Transceiver Wizard.

[1:0]: This attribute controls the datapath resets. It varies by mode:

64B/66B: 2'b10 8B/10B: 2'b00 Raw: 2'b00 PRBS: 2'b10 Default: 2'b11

TX_FABRIC_WIDTH0

TX_FABRIC_WIDTH1

TX_FABRIC_WIDTH2

TX_FABRIC_WIDTH3

Integer This attribute sets the mapping of the internal data width (PCS) to

the external data width (fabric) for the transmitter. Valid settings are:

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Enabling 8B/10B Mode

Follow these steps to enable the 8B/10B mode in the GTH transmitter:

1. Set PCS_MODE_LANE<n>[3:0] to 4'b0111.

2. Set PCS_RESET_LANE<n> to 0xFC5B.

• Set PCS_RESET_1_LANE<n>[1:0] to 2'b00.

• Set TX_FABRIC_WIDTH<n> to either “16”, “32”, or “64” depending on the application.

The 8B/10B table includes special characters (K characters) that are often used for control functions. To transmit TXDATA as a K character instead of regular data, the TXCTRL port must be driven High.

TX 8B/10B Block

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Chapter 3: Transmitter

TX 64B/66B Block

Functional Description

Some high-speed data rate protocols use 64B/66B encoding to reduce the overhead of 8B/10B encoding while retaining the benefits of an encoding scheme. The GTH transceiver implements the 64B/66B block based on the IEEE 802.3-2008 Clause 49, “Physical Sublayer (PCS) for 64B/66B, type 10GBASE-R.” The transmit 64B/66B block includes the scrambler and the gearbox.

Ports and Attributes

Tab le 3 -7 defines the TX 64B/66B block ports.

Table 3-7: TX 64B/66B Block Ports

Port Dir Clock Domain Description

TXCTRL0[7:0]

TXCTRL1[7:0]

TXCTRL2[7:0]

TXCTRL3[7:0]

TXDATA0[63:0]

TXDATA1[63:0]

TXDATA2[63:0]

TXDATA3[63:0]

In TXUSERCLKIN0

TXUSERCLKIN1

TXUSERCLKIN2

TXUSERCLKIN3

In TXUSERCLKIN0

TXUSERCLKIN1

TXUSERCLKIN2

TXUSERCLKIN3

These inputs indicate control of TXDATA<n> or they are used as an extension of TXDATA<n> depending on the mode selected in the transmitter datapath:

8B/10B: These inputs are asserted when TXDATA<n> is an 8B/10B K character.

TXCTRL<n>[7] corresponds to TXDATA<n>[63:56]

TXCTRL<n>[6] corresponds to TXDATA<n>[55:48]

TXCTRL<n>[5] corresponds to TXDATA<n>[47:40]

TXCTRL<n>[4] corresponds to TXDATA<n>[39:32]

TXCTRL<n>[3] corresponds to TXDATA<n>[31:24]

TXCTRL<n>[2] corresponds to TXDATA<n>[23:16]

TXCTRL<n>[1] corresponds to TXDATA<n>[15:8]

TXCTRL<n>[0] corresponds to TXDATA<n>[7:0]

64B/66B: These inputs are 64B/66B control bits.

Raw mode: These inputs are used as part of TXDATA<n>[71:64].

This input bus is the transmit data bus of the transmit interface from the FPGA.

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Tab le 3 -8 defines the TX 64B/66B block attributes.

Table 3-8: TX 64B/66B Block Attributes

Attribute Type Description

TX 64B/66B Block

PCS_MODE_LANE0

PCS_MODE_LANE1

PCS_MODE_LANE2

PCS_MODE_LANE3

16-bit Hex This attribute sets the PCS mode.

[15]: Loopback serializer/deserializer RX to serializer/deserializer TX.

[14]: Loopback PCS TX to PCS RX.

[13:11]: PRBS generator mode

000: None 001: PRBS7 010: PRBS9 011: PRBS11 100: PRBS23 101: PRBS31

Others: Reserved

[10:8]: PRBS checker mode

000: None 001: PRBS7 010: PRBS9 011: PRBS11 100: PRBS23 101: PRBS31

Others: Reserved

[7:4]: PCS RX mode

0000: Zero 0001: 64B/66B 0111: 8B/10B 1010: 16-bit raw data 1011: 20-bit raw data 1100: PRBS

Others: Reserved

[3:0]: PCS TX mode

0000: Zero 0001: 64B/66B 0111: 8B/10B 1010: 16-bit raw data 1011: 20-bit raw data 1100: PRBS

Others: Reserved

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Chapter 3: Transmitter

Table 3-8: TX 64B/66B Block Attributes (Cont’d)

Attribute Type Description

PCS_RESET_LANE0

PCS_RESET_LANE1

PCS_RESET_LANE2

PCS_RESET_LANE3

PCS_RESET_1_LANE0

PCS_RESET_1_LANE1

PCS_RESET_1_LANE2

PCS_RESET_1_LANE3

16-bit Hex This attribute controls the datapath resets. It varies by mode:

64B/66B: 0xF3FE 8B/10B: 0xFC5B Raw: 0xFF3B PRBS: 0xFFCE Default: 0xFFFF

[15:12]: Reserved

[11]: Reset 64B/66B receive

[10]: Reset 64B/66B transmit

[9]: Reset 8B/10B receive

[8]: Reset 8B/10B transmit

[7]: Reset RX FIFO

[6]: Reset RX raw shift pointer

[5]: Reset PRBS checker

[4]: Reset PRBS generator

[3]: Reserved

[2]: Reset TX FIFO

[1]: Reset RX loopback FIFO

[0]: Reserved

16-bit Hex [15:2]: Reserved. Use the recommended values from the Virtex-6

FPGA GTH Transceiver Wizard.

[1:0]: This attribute controls the datapath resets. It varies by mode:

64B/66B: 2'b10 8B/10B: 2'b00 Raw: 2'b00 PRBS: 2'b10 Default: 2'b11

TX_FABRIC_WIDTH0

TX_FABRIC_WIDTH1

TX_FABRIC_WIDTH2

TX_FABRIC_WIDTH3

Integer This attribute sets the mapping of the internal data width (PCS) to

the external data width (fabric) for the transmitter. Valid settings are:

The default for these attributes is

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“6466.”

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Enabling 64B/66B Mode

TX Raw Mode

Functional Description

Ports and Attributes

TX Raw Mode

Follow these steps to enable the 64B/66B mode in the GTH transmitter:

1. Set PCS_MODE_LANE<n>[3:0] to 4'b0001.

2. Set PCS_RESET_LANE<n> to 0xF3FE.

3. Set PCS_RESET_1_LANE<n>[1:0] to 2'b10.

4. Set TX_FABRIC_WIDTH<n> to “6466.”

The GTH transceiver provides another datapath mode for non-encoded applications or when the user wants to bypass the 8B/10B and 64B/66B blocks.

Tab le 3 -9 defines the TX raw mode ports.

Table 3-9: TX Raw Mode Ports

Port Dir Clock Domain Description

TXCTRL0[7:0]

TXCTRL1[7:0]

TXCTRL2[7:0]

TXCTRL3[7:0]

TXDATA0[63:0]

TXDATA1[63:0]

TXDATA2[63:0]

TXDATA3[63:0]

In TXUSERCLKIN0

TXUSERCLKIN1

TXUSERCLKIN2

TXUSERCLKIN3

TXUSERCLKIN1

TXUSERCLKIN2

TXUSERCLKIN3

These inputs indicate control of TXDATA<n> or they are used as an extension of TXDATA<n> depending on the mode selected in the transmitter datapath:

8B/10B: These inputs are asserted when TXDATA<n> is an 8B/10B K character.

TXCTRL<n>[7] corresponds to TXDATA<n>[63:56]

TXCTRL<n>[6] corresponds to TXDATA<n>[55:48]

TXCTRL<n>[5] corresponds to TXDATA<n>[47:40]

TXCTRL<n>[4] corresponds to TXDATA<n>[39:32]

TXCTRL<n>[3] corresponds to TXDATA<n>[31:24]

TXCTRL<n>[2] corresponds to TXDATA<n>[23:16]

TXCTRL<n>[1] corresponds to TXDATA<n>[15:8]

TXCTRL<n>[0] corresponds to TXDATA<n>[7:0]

64B/66B: These inputs are 64B/66B control bits.

Raw mode: These inputs are used as part of TXDATA<n>[71:64].

This input bus is the transmit data bus of the transmit interface from the FPGA.

TXDATAMSB0[7:0]

TXDATAMSB1[7:0]

TXDATAMSB2[7:0]

TXDATAMSB3[7:0]

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In TXUSERCLKIN0

TXUSERCLKIN1

TXUSERCLKIN2

TXUSERCLKIN3

This bus extends the transmit data bus as TXDATA<n>[79:72].

Chapter 3: Transmitter

Tab le 3 -1 0 defines the TX raw mode attributes.

Table 3-10: TX Raw Mode Attributes

Attribute Type Description

PCS_MODE_LANE0

PCS_MODE_LANE1

PCS_MODE_LANE2

PCS_MODE_LANE3

16-bit Hex This attribute sets the PCS mode.

[15]: Loopback serializer/deserializer RX to serializer/deserializer TX

[14]: Loopback PCS TX to PCS RX

[13:11]: PRBS generator mode

000: None 001: PRBS7 010: PRBS9 011: PRBS11 100: PRBS23 101: PRBS31

Others: Reserved

[10:8]: PRBS checker mode

000: None 001: PRBS7 010: PRBS9 011: PRBS11 100: PRBS23 101: PRBS31

Others: Reserved

[7:4]: PCS RX mode

0000: Zero 0001: 64B/66B 0111: 8B/10B 1010: 16-bit raw data 1011: 20-bit raw data 1100: PRBS

Others: Reserved

[3:0]: PCS TX mode

0000: Zero 0001: 64B/66B 0111: 8B/10B 1010: 16-bit raw data 1011: 20-bit raw data 1100: PRBS

Others: Reserved

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Table 3-10: TX Raw Mode Attributes (Cont’d)

Attribute Type Description

TX Raw Mode

PCS_RESET_LANE0

PCS_RESET_LANE1

PCS_RESET_LANE2

PCS_RESET_LANE3

PCS_RESET_1_LANE0

PCS_RESET_1_LANE1

PCS_RESET_1_LANE2

PCS_RESET_1_LANE3

16-bit Hex This attribute controls the datapath resets. It varies by mode:

64B/66B: 0xF3FE 8B/10B: 0xFC5B Raw: 0xFF3B PRBS: 0xFFCE Default: 0xFFFF

[15:12]: Reserved

[11]: Reset 64B/66B receive

[10]: Reset 64B/66B transmit

[9]: Reset 8B/10B receive

[8]: Reset 8B/10B transmit

[7]: Reset RX FIFO

[6]: Reset RX raw shift pointer

[5]: Reset PRBS checker

[4]: Reset PRBS generator

[3]: Reserved

[2]: Reset TX FIFO

[1]: Reset RX loopback FIFO

[0]: Reserved

16-bit Hex [15:2]: Reserved. Use the recommended values from the Virtex-6 FPGA

GTH Transceiver Wizard.

[1:0]: This attribute controls the datapath resets. It varies by mode:

64B/66B: 2'b10 8B/10B: 2'b00 Raw: 2'b00 PRBS: 2'b10 Default: 2'b11

TX_FABRIC_WIDTH0

TX_FABRIC_WIDTH1

TX_FABRIC_WIDTH2

TX_FABRIC_WIDTH3

Integer Defaults to

This attribute sets the mapping of the internal data width (PCS) to the external data width (fabric) for the transmitter. Valid settings are:

“16” (DRP value 3'b000): PCS to Fabric 1:1

“6466.”

“20” (DRP value 3'b000): PCS to Fabric 1:1 “32” (DRP value 3'b011): PCS to Fabric 1:2 32 bits “40” (DRP value 3'b101): PCS to Fabric 1:2 40 bits “64” (DRP value 3'b010): PCS to Fabric 1:4 64 bits “80” (DRP value 3'b110): PCS to Fabric 1:4 80 bits “6466” (DRP value 3'b111): 64B/66B mode

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Enabling Raw Mode

Follow these steps to enable the Raw mode in the GTH transmitter:

1. If the transmit fabric data width is configured to 16 bits, 32 bits, or 64 bits a. Set PCS_MODE_LANE<n>[3:0] to 4'b1010. b. Set PCS_RESET_LANE<n> to 0xFF3B. c. Set PCS_RESET_1_LANE<n>[1:0] to 2'b00.

d. Set TX_FABRIC_WIDTH<n> to “16”, “32”, or “64.”

2. If the transmit fabric data width is configured to 20 bits, 40 bits, or 80 bits a. Set PCS_MODE_LANE<n>[3:0] to 4'b1011. b. Set PCS_RESET_LANE<n> to 0xFF3B. c. Set PCS_RESET_1_LANE<n>[1:0] to 2'b00.

d. Set TX_FABRIC_WIDTH<n> to “20”, “40”, or “80.”

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TX Pattern Generator

Functional Description

The GTH transceiver pattern generator block can generate the industry-standard PRBS patterns listed in Ta bl e 3- 11 .

Table 3-11: PRBS Pattern

TX Pattern Generator

Name Polynomial

PRBS7 1 + X

PRBS9 1 + X

PRBS11 1 + X

PRBS23 1 + X

PRBS31 1 + X

Ports and Attributes

There are no ports in the TX pattern generator.

Tab le 3 -1 2 defines the TX pattern generator attributes.

Table 3-12: TX Pattern Generator Attributes

Attribute Type Description

PRBS_CFG_LANE0

PRBS_CFG_LANE1

PRBS_CFG_LANE2

PRBS_CFG_LANE3

16-bit Hex [15:4]: Reserved. Use the recommended values from the Virtex-6 FPGA

Length of

Sequence

+ X

27 – 1 bits Characteristics are similar to 8B/10B data.

29 – 1 bits Used by 10GBASE-LRM.

211 – 1 bits Used by 10BASE-KR link training.

223 – 1 bits PRBS23 is often used for non-8B/10B

231 – 1 bits Characteristics are similar to 64B/66B data.

GTH Transceiver Wizard.

[3:2]: PRBS generate width

2'b11: 20b 2'b10: 16b

Others: Reserved

[1:0]: PRBS checker width

2'b11: 20b 2'b10: 16b

Others: Reserved

Description

encoding schemes. This is one of the recommended test patterns in the SONET specification.

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Chapter 3: Transmitter

Table 3-12: TX Pattern Generator Attributes (Cont’d)

Attribute Type Description

PCS_MODE_LANE0

PCS_MODE_LANE1

PCS_MODE_LANE2

PCS_MODE_LANE3

16-bit Hex Sets the PCS mode.

[15]: Loopback serializer/deserializer RX to serializer/deserializer TX.

[14]: Loopback PCS TX to PCS RX.

[13:11]: PRBS generator mode

000: None 001: PRBS7 010: PRBS9 011: PRBS11 100: PRBS23 101: PRBS31

Others: Reserved

[10:8]: PRBS checker mode

000: None 001: PRBS7 010: PRBS9 011: PRBS11 100: PRBS23 101: PRBS31

Others: Reserved

[7:4]: PCS RX mode

0000: Zero 0001: 64B/66B 0111: 8B/10B 1010: 16-bit raw data 1011: 20-bit raw data 1100: PRBS

Others: Reserved

[3:0]: PCS TX mode

0000: Zero 0001: 64B/66B 0111: 8B/10B 1010: 16-bit raw data 1011: 20-bit raw data 1100: PRBS

Others: Reserved

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Table 3-12: TX Pattern Generator Attributes (Cont’d)

Attribute Type Description

TX Pattern Generator

PCS_RESET_LANE0

PCS_RESET_LANE1

PCS_RESET_LANE2

PCS_RESET_LANE3

PCS_RESET_1_LANE0

PCS_RESET_1_LANE1

PCS_RESET_1_LANE2

PCS_RESET_1_LANE3

16-bit Hex This attribute controls the datapath resets. It varies by mode:

64B/66B: 0xF3FE 8B/10B: 0xFC5B Raw: 0xFF3B PRBS: 0xFFCE Default: 0xFFFF

[15:12]: Reserved

[11]: Reset 64B/66B receive

[10]: Reset 64B/66B transmit

[9]: Reset 8B/10B receive

[8]: Reset 8B/10B transmit

[7]: Reset RX FIFO

[6]: Reset RX raw shift pointer

[5]: Reset PRBS checker

[4]: Reset PRBS generator

[3]: Reserved

[2]: Reset TX FIFO

[1]: Reset RX loopback FIFO

[0]: Reserved

16-bit Hex [15:2]: Reserved. Use the recommended values from the Virtex-6 FPGA

GTH Transceiver Wizard.

[1:0]: This attribute controls the datapath resets. It varies by mode:

64B/66B: 2'b10 8B/10B: 2'b00 Raw: 2'b00 PRBS: 2'b10 Default: 2'b11

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Chapter 3: Transmitter

TX Polarity Control

Functional Description

The GTH transceiver includes a TX polarity control function to invert outgoing data from the PCS before serialization and transmission.

Ports and Attributes

There are no TX polarity control ports.

Tab le 3 -1 3 defines the TX polarity control attributes.

Table 3-13: TX Polarity Control Attributes

Attribute Type Description

PCS_MISC_CFG_0_LANE0

PCS_MISC_CFG_0_LANE1

PCS_MISC_CFG_0_LANE2

PCS_MISC_CFG_0_LANE3

Using TX Polarity Control

If the TXP/TXN differential traces are swapped on a board, use either the DRP or the management interface to set PCS_MISC_CFG_0_LANE<n>[11] register to 1'b1. The register is located in:

• DRP Address

• Management Interface Address: 0x8001 with MMD Address 0x03

16-bit Hex This attribute sets the polarity and PRBS configuration.

[15:12]: Reserved. Use the recommended values from the Virtex-6 FPGA GTH Transceiver Wizard.

[11]: Invert TX polarity

[10]: RX polarity override enable

[9]: RX polarity override value

[8]: Reset the PRBS error counter when read

[7]: Revert bit order of parallel data to serializer/deserializer TX

[6]: Revert bit order of parallel data from serializer/deserializer RX

[5:0]: Reserved. Use the recommended values from the Virtex-6 FPGA GTH Transceiver Wizard.

• PCS_MISC_CFG_0_LANE0: 0x5001

• PCS_MISC_CFG_0_LANE1: 0x5101

• PCS_MISC_CFG_0_LANE2: 0x5201

• PCS_MISC_CFG_0_LANE3: 0x5301

• Use the Lane Address setting to specify which GTH lane to access

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TX Configurable Driver

UG371_c3_03_120809

Pre-Emphasis Pad Driver

tx_precursor[3:0]

MGTHAVTT_[L,R]

MGTTXP MGTTXN

tx_swing[3:0]

tx_postcursor[3:0]

TX Serial Clock = Data Rate / 2

Pre-Driver

Main Pad Driver

Pre-Driver

PISO

Pre-Driver

50Ω

Nominal

50Ω

Nominal

Functional Description

The GTH TX driver is a high-speed, current-mode differential output buffer. To maximize signal integrity, the TX driver includes these features:

• Differential voltage swing control

• Pre-cursor and post-cursor transmit emphasis

• Calibrated termination resistors

Figure 3-3 is a detailed diagram of the TX driver.

X-Ref Target - Figure 3-3

TX Configurable Driver

Figure 3-3: TX Driver Structure

The transmitter’s output level can vary depending on the state of the system. Here are some common scenarios:

• Power-up, before configuration

Differential zero: TXP is held Low; TXN is held High.

• During configuration

Differential zero: TXP is held Low; TXN is held High.

•Reset

Differential zero: TXP is held Low; TXN is held High.

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Chapter 3: Transmitter

Ports and Attributes

•Power down

Floating: TXP and TXN should float High to VTTX (assuming AC-coupled mode)

• Near-end PCS loopback and Near-end PMA loopback

TXP and TXN are transmitting live data

Tab le 3 -1 4 defines the TX configurable driver ports.

Table 3-14: TX Configurable Driver Ports

Port Dir Clock Domain Description

TXDEEMPH0

TXDEEMPH1

TXDEEMPH2

TXDEEMPH3

TXMARGIN0[2:0]

TXMARGIN1[2:0]

TXMARGIN2[2:0]

TXMARGIN3[2:0]

TXN0

TXN1

TXN2

TXN3

TXP0

TXP1

TXP2

TXP3

In TXUSERCLKIN0

TXUSERCLKIN1

TXUSERCLKIN2

TXUSERCLKIN3

In TXUSERCLKIN0

TXUSERCLKIN1

TXUSERCLKIN2

TXUSERCLKIN3

Out

(Pad)

TX Serial Clock TXP and TXN are the differential

Reserved. Tie this input to 0.

Reserved. Tie these inputs to 000.

output pairs for each of the transmitters in the GTHE1_QUAD primitive. These ports represent pads. The location of these ports must be constrained and brought to the top level of the design.

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Tab le 3 -1 5 defines the TX configurable driver attributes.

tx_swing

(Binary)

TX_CFG0_LANE

(Hex)

Voltage Swing

(mV

PPD

)

0000 0x0005 450

0001 0x000D 500

0010 0x0015 550

0011 0x001D 600

0100 0x0025 650

0101 0x002D 700

0110 0x0035 750

0111 0x003D 800

1000 0x0045 850

1001 0x004D 900

1010 0x0055 950

1011 0x005D 1000

1100 0x0065 1050

1101 0x006D 1100

1110 0x0075 1150

1111 0x007D 1200

Table 3-15: TX Configurable Driver Attributes

Attribute Type Description

TX Configurable Driver

TX_CFG0_LANE0

TX_CFG0_LANE1

TX_CFG0_LANE2

TX_CFG0_LANE3

16-bit Binary This attribute controls the differential voltage

swing.

[15:14]: Reserved: 2’h0

[13]: Active-High TX lane power down (tx_chpd)

[12:7]: Reserved: 6’h00

[6:3]: TX output swing control and main tap/cursor control (tx_swing)

[2:0]: TX current bias fine swing control (tx_ibias)

tx_bias = 0x7

(1)

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Chapter 3: Transmitter

Table 3-15: TX Configurable Driver Attributes (Cont’d)

Attribute Type Description

TX_CFG1_LANE0

TX_CFG1_LANE1

TX_CFG1_LANE2

TX_CFG1_LANE3

TX_PREEMPH_LANE0

TX_PREEMPH_LANE1

TX_PREEMPH_LANE2

TX_PREEMPH_LANE3

16-bit Binary This attribute enables the differential voltage

swing and the pre-cursor and post-cursor transmit emphasis.

[15:10]: Reserved. Tie these inputs to 6'b000011.

[9]: This bit gives control to tx_swing in the TX_CFG0_LANE<n> registers for voltage swing control (tx_swing_ovrrd_en). Set this bit to 1'b1.

[8]: This bit gives control to tx_postcursor and tx_precursor in the TX_PREEMPH_LANE<n> attribute for transmit post-cursor and pre-cursor emphasis (tx_premptap_ovrrd_en). Set this bit to 1'b1.

[7:0]: Reserved. Tie these inputs to 8'h00.

16-bit Binary This attribute controls the pre-cursor and

post-cursor transmit emphasis. For pre-emphasis and post-emphasis settings, see Setting the TX

Driver.

[15:8]: Reserved. Tie these inputs to 8'hA0.

[7:4]: Pre-emphasis settings for the first post-cursor (tx_postcursor).

[3:0]: Pre-emphasis settings for the pre-cursor or the second post-cursor (tx_precursor).

Notes:

1. The hexadecimal values for TX_CFG0_LANE<n> assume that the defaults for the other bits in the register are used and that the channel is powered up and not in reset.

Setting the TX Driver

The TX amplitude and swing controls are set via attributes using the DRP or the Management interface.

Amplitude (Swing)

The override bit has to be set as specified:

• TX_CFG1_LANE<n>[9] = tx_swing_ovrrd_en = 1'b1

• TX_CFG0_LANE<n>[6:3] = tx_swing (see Ta bl e 3- 15 for voltage swing control settings)

• TX_CFG0_LANE<n>[2:0] = tx_ibias (see Ta bl e 3 -1 5 for voltage swing control settings)

Post-Cursor Emphasis

The override bit has to be set as specified:

• TX_CFG1_LANE<n>[8] = tx_premptap_ovrrd_en = 1'b1

• TX_PREEMPH_LANE<n>[7:4] = tx_postcursor

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Xilinx Virtex-6 FPGA GTH Transceivers User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Revision History

Table of Contents

About This Guide

Guide Contents

Additional Documentation

Additional Resources

Transceiver and Tool Overview

Overview

Port and Attribute Summary

Virtex-6 FPGA GTH Transceiver Wizard

Simulation

Functional Description

Ports and Attributes

Implementation

Functional Description

FF1155 Package Diagrams

FF1923 and FF1924 Package Diagrams

Shared Transceiver Features

Reference Clock Input Structure

Functional Description

Ports and Attributes

Using the Reference Clock

Reference Clock Distribution and Selection

Functional Description

Ports and Attributes

Clocking from an External Source

Clocking from a Neighboring GTH Quad

Functional Description

Ports and Attributes

Reset and Initialization

PLL Settings for the Common Protocol

Functional Description

Ports and Attributes

GTH Quad Initialization in Response to Completion of Configuration

GTH Quad Reset in Response to GTHRESET

Resetting the Transmit Datapath

Resetting the Receive Datapath

Power Down

Functional Description

Ports and Attributes

Using Power Down

Loopback

Functional Description

Ports and Attributes

Dynamic Reconfiguration Port

Functional Description

Ports and Attributes

Using the DRP Interface

Management Interface

Functional Description

Ports and Attributes

Using the Management Interface

Transmitter

FPGA TX Interface

Functional Description

Ports and Attributes

Transmit Clocking

Configuring the Transmitter for Multi-lane Applications

TX 8B/10B Block

Functional Description

Ports and Attributes

Enabling 8B/10B Mode

TX 64B/66B Block

Functional Description

Ports and Attributes

Enabling 64B/66B Mode

TX Raw Mode

Functional Description

Ports and Attributes

Enabling Raw Mode

TX Pattern Generator

Functional Description

Ports and Attributes

TX Polarity Control

Functional Description

Ports and Attributes