Xilinx VIRTEX-6 FPGA CONNECTIVITY KIT Hardware Setup Manual

SFP DDR3

FMC

(LPC)

FMC (HPC)

Connectivity Daughter Card
Clock Generator
and Synthesizer

CX4 Connector

USB 2.0

(Host)

12V Wall Power

12V ATX Power

USB 2.0
(Device)

Push Buttons (SW5-SW9)

MGT Port (J26-J29)

16x2 LCD Character Display

X8 PCI Express

Ethernet

System ACE

Prog (SW4)

Switch S1

Switch S2

SystemACE RST (SW3)

CPU RST (SW10)

PMBus Controlle r

System Monitor Header s

PMBus (J3)

GPIO DI P Switch (SW1)

MGT Clock (J30 & J31)

USB to UART (J21)

USB JTAG (J22)

Platform Flash (U27)

DVI Output

User Clock

(J55-J58)

BPI Flash (U4)

GPIO LEDs

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This Hardware Setup Guide provides step-by-step instructions to setup the ML605 board, the FMC daughter card, and run the pre-built
Demo that uses the built-in block for PCI Express (x4Gen2 configuration), XAUI IP LogiCORE, a Virtual FI FO Memory controller interfacing
to the on-board DDR3 memory and a third-party PCIe DMA Controller.

Kit Cont ents

• ML605 board and FMC Connectivity Daughter Card

• CX4 Loopback Connector

• Universal 12V power supply

• 2 USB A / Mini-B cables

• 1 ethernet Cat5 cable

• 1 DVI-to-VGA adapter

• Four SMA cables

• 1 SATA cable, 1 SATA loopback cable

• 1 CompactFlash card (2GB)

• Xilinx ISE Design Suite DVDs - 11.1 and 11.4 Update

• 1 USB stick

• Fedora Core 10 Live CD

• Documents include a welcome letter, Hardware Setup Guide,
Getting Started Guide

What’s Nee ded f or D emon stra tion

• Xilinx Virtex-6 FPGA Connectivity Kit

• PC system with a x8/x16 PCIe slot on the motherboard, CDROM
drive and a USB port

• Keyboard & Mouse

• Monitor

VIRTEX-6 FPGA CON NECTIVI TY KITVIRTEX-6 FPGA CON NECTIVI TY KIT HARDWARE S ETUP G UIDEHARDWARE S ETUP G UIDE

VIRTEX6 FPGA CONNECTIVITY KIT HARDWARE SETUP GUIDE

BO ARD FEAT UR ESXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XX XXX XXX XXX XXX X

Congratulations! The Virtex-6 FPGA Connectivity Kit is now set up. The pre-built connectivity targeted reference design demonstration has
been tested, using the built-in block for PCI Express (x4 PCI Express Gen2 Endpoint), XAUI LogiCORE I P, a Virtual FIFO memory controller
designed to interface to the on-board DDR3 memory, and Northwest Logic’s high performance DMA controller for PCI Express.

Next, please refer the Getting Started Guide included in this kit. The guide provides further instructions on running the demo, evaluating and
modifying the design files – Hardware RTL design and Software Device Driver. For updated information on this Virtex-6 FPGA Connectivity
Kit, please visit www.xilinx.com/v6connkit.

Support Information

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© Copyright 2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States and other
countries. All other trademarks are the property of their respective owners. Printed in the U.S.A. Xilinx Part Number: PN0402827-01

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ST EP 10II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II III II II II

Performance Monitor Application: Verify Data Throughput
and Error Free Operation

A. Confirm PCIe Throughput.
B. Confirm DMA Channel throughput for the XAUI path.
C. Confirm DMA Channel throughput for the Raw Data path.
D. Confirm Error Free operation - no Buffer Descriptor Errors.

ST EP 9II II II II II II II II II II II II II II II II II II II II II II II II II II II II II III II II II II I

Performance Monitor Application: Start Data Traffic

A. Click on Start Test to begin XAUI data transfer.
B. Click on Start Test to begin Raw data transfer.

ST EP 2II II II II II II II II II II II II II II II II II II II II II II II II II II II II II III II II II II I ST EP 6II II II II II II II II II II II II II II II II II II II II II II II II II II II II II III II II II II I

ST EP 4II II II II II II II II II II II II II II II II II II II II II II II II II II II II II III II II II II I STE P 8 II III II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II III

Connect the Power Connector

A. Turn the PC system OFF.
B. Connect the PC systems’ 12V ATX power supply’s available 4-pin

disk drive-type power connector to the board (J25).

Warning: Using any other power supply connector other than the
4-pin in-line connector, will result in damage to the PC system
and the ML605 board.

C. The power switch SW2 should be switched to the ON position

(away from the bracket edge).

Performance Monitor Application: Verify Board Status

Click on the System Status tab to confirm board status and PCIe
settings:

A. Link Status: Up
B. Link Speed: 5.0Gbps
C. Link Width: x4

Load Driver and Launch Performance Monitor application

A. Navigate to the v6_pcie_10Gdma_ddr3_xaui folder.
B. Double-click v6_trd_quick_start. This will build kernel objects,

insert driver modules and launch the Performance Monitor
Application GUI.

C. Click Run in Terminal to proceed.

Copy Contents of USB Flash Drive

A. The reference design files are provided on the USB flash drive

delivered with the kit.
B. Insert the USB flash drive into a USB connector of the PC system.
C. Wait for the Fedora 10 OS to mount the USB flash. When the flash

is mounted, an icon pops up on the desktop.
D. Double-click on the USB flash drive icon and copy the v6_

pcie_10Gdma_ddr3_xaui folder into the live user’s home folder/

directory.
E. To unmount the USB flash, right-click on the USB flash drive icon

and select Unmount Volume.

Boot PC from CD-ROM

A. Configure the PC system to boot from the CD-ROM drive.
B. Place the Fedora 10 Live CD into the CD-ROM drive.
For further information, please refer to the Virtex-6 FPGA Connectivity

Kit Getting Started Guide for more details.

VIRTEX-6 FPGA CON NECTIVI TY KITVIRTEX-6 FPGA CON NECTIVI TY KIT HARDWARE S ETUP G UIDEHARDWARE S ETUP G UIDE

ST EP 1II II II II II II II II II II II II II II II II II II II II II II II II II II II II II III II II II II II ST EP 5II II II II II II II II II II II II II II II II II II II II II II II II II II II II II III II II II II II

ST EP 3II II II II II II II II II II II II II II II II II II II II II II II II II II II II II III II II II II II ST EP 7II II II II II II II II II II II II II II II II II II II II II II II II II II II II II III II II II II I

Board Setup and Configuration

The ML605 is shipped with the FMC Connectivity Daughter Card
module attached to the FMC_HPC connector. To run the demonstration,
you will need to externally loopback the XAUI data using a CX4
loopback connector provided in the kit.

A. Ensure correct Switch Settings:

• S1: 1-OFF, 2-OFF, 3-OFF, 4-ON

• S2: 1-ON, 2-OFF, 3-OFF, 4-ON, 5-ON, 6-OFF
B. Ensure Jumper J42 block: pins3-4 are shorted
C. Plug in the CX4 loopback connector:

• Plug the CX4 loopback connector on the FMC Connectivity

Daughter card’s J2 connector.

Boot Fedora 10 Live and Automatically Login

A. The screens above will appear on Power UP.
B. Wait two to three minutes depending on the system configuration

for the PC to boot completely.

Insert ML605 Board into PCIe Express Slot

A. Identify the x8 / x16 PCIe Express slot on the PC motherboard.
B. Insert the ML605 board into the PCI Express slot through the PCIe

x8 edge connector.

C. Turn the power ON. The PCIe 10GDMA DDR3 XAUI targeted

reference design will be loaded from the Platform Flash.