Xilinx Virtex-5 RocketIO GTP Transceiver User Manual

Virtex-5 RocketIO GTP Transceiver User Guide

UG196 (v1.3) May 25, 2007

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Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate
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copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Design.
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accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design.

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THE DESIGN TO YOU WITHOUT THESE LIMITATIONS OF LIABILITY.

The Design is not designed or intended for use in the development of on-line control equipment in hazardous environments requiring fail­safe controls, such as in the operation of nuclear facilities, aircraft navigation or communications systems, air traffic control, life support, or
weapons systems (“High-Risk Applications”). Xilinx specifically disclaims any express or implied warranties of fitness for such High-Risk
Applications. You represent that use of the Design in such High-Risk Applications is fully at your risk.

© 2006-2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx,
Inc. PowerPC is a trademark of IBM, Inc. All other trademarks are the property of their respective owners.

Revision History

The following table shows the revision history for this document.

Date Version Revision

09/06/06 1.0 Initial release to CD.

10/13/06 1.1 Initial release to www.xilinx.com

02/02/07 1.2 Added SXT packages to “Package Placement Information” in Chapter 4. Inserted RX

buffer overflow/underflow footnotes to Ta bl e 7 -2 8 and Ta b le 7 - 30 . Added “SelectIO-to-

GTP Crosstalk Guidelines” in Chapter 10. Added “SelectIO to Serial Transceiver
Crosstalk Guidelines” in Chapter 11. Added Appendix E, “Low Latency Design.”

Removed Virtex-II Pro X FPGA references.

Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007

Date Version Revision

05/25/07 1.3 Chapter 1: Revised line rates in the “Overview,” page 19. Added to RXBYTEISALIGNED

description and removed CRC ports in Tab le 1- 3 , pag e 2 4. Corrected
PCOMMA_DETECT entry and removed CRC_INIT[31:0] attribute in Tab le 1- 4. CRC
ports are not part of the GTP_DUAL primitive. See Chapter 8.

Chapter 3: Added “Providing Clocks In Simulation,” page 44. Added multirate clocking
design caveats and link to Appendix F.

Chapter 4: Added a note 2 to Tab le 4- 1 , pag e 49.

Chapter 5: Added to note 5 in Figure 5-1, page 60. Added PCS_COM_CFG and notes to

Figure 5-2, page 63. Revised Equation 5-1. Changed PLL clock frequency for FC1, FC2,

SFI-5, TFI-5, and the HD-SDI standard in Tab le 5 - 3, p age 6 3. Revised the notes for

Figure 5-5, page 71. Added PRBSCNTRESET and PLLPOWERDOWN, and revised

GTPRESET description in Tab l e 5-6, p age 7 3 . Revised “GTP Component-Level Resets”
and “Link Idle Reset Support,” page 75. Added note to RXPOWERDOWN in Tab l e 5- 9 ,

page 81. Added note to Table 5-11, page 83.

Chapter 6: Added a BUFG to Figure 6-5. Revised PMA_COM_CFG,
OVERSAMPLE_MODE, and added three attributes to Table 6-8, page 105. Revised the

“Using the TX Phase-Alignment Circuit to Bypass the TX Buffer,” page 106. Revised
Figure 6-12, page 107. Added INTDATAWIDTH to Table 6-12, page 109. Revised

OVERSAMPLE_MODE in Table 6-14, page 111. Revised TX_DIFF_BOOST in Table 6-16,

page 113. Added default value to Table 6-18, page 114.

Chapter 7: Revised Figure 7-2, page 126. Updated Tabl e 7- 3. Added OOB nominal values
to Ta bl e 7- 6. Added “Tuning the CDR,” page 139. Revised Table 7-12, page 141. Added
note 1 to Table 7-29, page 163. Revised CLK_COR_MAX_LAT

Chapter 8: Added clarification to the CRC block description.

Chapter 9: Made changes to “Near-End PCS Loopback,” “Near-End PMA Loopback,”

“Far-End PMA Loopback,” and “Far-End PCS Loopback,” including adding “Marginal
Conditions and Limitations.” Added Tab le 9 - 2.

Chapter 10: Clarified

“REFCLK Guidelines,” page 207. Added Figure 10-9. Added

TERMINATION_IMP to Table 10-2. Added note on analog supplies to Table 10-3,

Table 10-4, and Table 10-5. Added SelectIO Adjacent to MGTCLK tables at the end of the

chapter. Edited “AC Coupling,” page 210. Added an additional guideline to “Filter

Network Design Guidelines.”

Appendix D: Added PCS_COM_CFG to Ta bl e D -2 , Ta bl e D -7 , and Tabl e D- 8. Revised bit
4 and 6 in Tab le D -3 .

Appendix E: Added note 2 to Table E-2, page 311.

Added Appendix F.

UG196 (v1.3) May 25, 2007 www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide

Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007

Table of Contents

Preface: About This Guide

Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Additional Support Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Typographical Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Section 1: FPGA Level Design

Chapter 1: Introduction to the RocketIO GTP Transceiver

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Chapter 2: RocketIO GTP Transceiver Wizard

Chapter 3: Simulation

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

SmartModel Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

SIM_GTPRESET_SPEEDUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

SIM_PLL_PERDIV2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

SIM_RECEIVER_DETECT_PASS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Power-Up and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Link Idle Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Toggling GSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Providing Clocks In Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Simulating in Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Defining GSR/GTS in a Test Bench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Simulating in VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Simulation Environment Setup Example (ModelSim SE 6.1d on Linux) . . . . . . . . . . . . 46

SIM_PLL_PERDIV2 Calculation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Chapter 4: Implementation

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Example of a UCF for GTP_DUAL Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Package Placement Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com 5

UG196 (v1.3) May 25, 2007

Chapter 5: Tile Features

Tile Features Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Shared PMA PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Configuring the Shared PLL for XAUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Configuring the Shared PLL for OC-48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Configuring the Shared PLL for Gigabit Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Configuring Shared PLL for PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Clocking from an External Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Clocking from a Neighbor GTP_DUAL Tile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Clocking using GREFCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

GTP Reset in Response to Completion of Configuration . . . . . . . . . . . . . . . . . . . . . . . . 74

GTP Reset When the GTPRESET Port is Asserted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

GTP Component-Level Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Link Idle Reset Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Resetting the GTP_DUAL Tile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Generic GTP Power Control Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Power Control Features for PCI Express. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Powerdown Transition Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Dynamic Reconfiguration Port (DRP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

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Chapter 6: GTP Transmitter (TX)

Transmitter Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

FPGA TX Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Configuring the Width of the Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Connecting TXUSRCLK and TXUSRCLK2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

TXOUTCLK Driving a GTP TX in 1-Byte Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

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TXOUTCLK Driving GTP TX in 2-Byte Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

TXOUTCLK Driving Multiple Transceivers for a 2-Byte Datapath . . . . . . . . . . . . . . . . 95

REFCLKOUT Driving Multiple Transceivers with a 2-Byte Interface. . . . . . . . . . . . . . . 96

Configurable 8B/10B Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Enabling 8B/10B Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

8B/10B Bit and Byte Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

K Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Running Disparity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

8B/10B Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

TX Buffering, Phase Alignment, and Buffer Bypass . . . . . . . . . . . . . . . . . . . . . . . . . 102

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Using the TX Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Using the TX Phase-Alignment Circuit to Bypass the TX Buffer . . . . . . . . . . . . . . . . . 106

Using the TX Phase Alignment Circuit to Minimize TX Skew . . . . . . . . . . . . . . . . . . . 107

TX Polarity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

TX PRBS Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Parallel In to Serial Out (PISO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Configurable TX Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Differential Voltage Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Pre-Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Configurable Termination Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

TXINHIBIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

PCI Express Receive Detect Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

TX OOB/Beacon Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

PCI Express Beacon Signaling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

SATA OOB Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

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Chapter 7: GTP Receiver (RX)

Receiver Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

RX Termination and Equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Optional Built-In AC Coupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Configurable Termination Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Configurable Termination Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Optional Configurable RX Linear Equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

RX OOB/Beacon Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Detecting PCI Express Electrical Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

SATA OOB Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

RX Clock Data Recovery (CDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

CDR Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Tuning the CDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Horizontal Sample Point Shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Serial In to Parallel Out (SIPO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Oversampling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Configuring the 5x Line Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Configuring the PCS Internal Datapath and Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Activating and Operating the Oversampling Block . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

RX Polarity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

PRBS Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Configurable Comma Alignment and Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Enabling Comma Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Configuring Comma Patterns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Activating Comma Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Alignment Status Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

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Alignment Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Manual Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Configurable Loss-of-Sync State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Configurable 8B/10B Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Enabling the 8B/10B Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

8B/10B Decoder Bit and Byte Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

K Characters and 8B/10B Commas. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

RX Running Disparity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Disparity Errors and Not-in-Table Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Configurable RX Elastic Buffer and Phase Alignment. . . . . . . . . . . . . . . . . . . . . . . 161

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Using the RX Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Using RX Phase Alignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Bypassing the RX Buffer while Using Built-In Oversampling . . . . . . . . . . . . . . . . . . . 167

Configurable Clock Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Enabling Clock Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Setting RX Buffer Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Setting Clock Correction Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Clock Correction Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Monitoring Clock Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Configurable Channel Bonding (Lane Deskew). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Enabling Channel Bonding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Channel Bonding Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Connecting Channel Bonding Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Setting the Channel Bonding Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Setting the Maximum Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Precedence between Channel Bonding and Clock Correction . . . . . . . . . . . . . . . . . . . 181

FPGA RX Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Configuring the Width of the Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Connecting RXUSRCLK and RXUSRCLK2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Chapter 8: Cyclic Redundancy Check (CRC)

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

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Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

Using CRC for Error Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

The CRC Primitive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

Using the CRC Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

Integrating the CRC Blocks for TX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

Integrating the CRC Blocks for RX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

Implementation of the CRC Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

Chapter 9: Loopback

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Near-End PCS Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Near-End PMA Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Marginal Conditions and Limitations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Far-End PMA Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Marginal Conditions and Limitations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Far-End PCS Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

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Chapter 10: GTP-to-Board Interface

Analog Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

REFCLK Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

GTP Reference Clock Checklist. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Oscillator Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Sourcing More Than One Differential Clock Input Pair from One Oscillator . . . . . . . . 209

Switching between Two Different Reference Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . 210

AC Coupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

Unused Reference Clock Inputs of GTP_DUAL Tiles for Clock Forwarding . . . . . . . . 210

Examples of Vendors and Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

Providing Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Linear Regulator Selection Criteria . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Regulator Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Ferrite Selection Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Capacitor Selection Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

Filter Network Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

Special Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

SelectIO-to-GTP Crosstalk Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

Section 2: Board Level Design

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Chapter 11: Design Constraints Overview

Powering Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

Power Distribution Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

Regulator Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

Reference Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

Clock Traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

Coupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

DC Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

AC Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

External Capacitor Value Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

SelectIO to Serial Transceiver Crosstalk Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

Chapter 12: PCB Materials and Traces

How Fast is Fast? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

Dielectric Losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

Relative Permittivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

Loss Tangent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

Skin Effect and Resistive Losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

Choosing the Substrate Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

Traces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

Trace Geometry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

Trace Characteristic Impedance Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

Trace Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

Plane Splits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

Return Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

Simulating Lossy Transmission Lines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

Optimal Cable Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

Skew Between Conductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

Chapter 13: Design of Transitions

Excess Capacitance and Inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

Time Domain Reflectometry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

BGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

SMT Pads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

Differential Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

P/N Crossover Vias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

SMA Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

Backplane Connectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

Microstrip/Stripline Bends . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

Chapter 14: Guidelines and Examples

Summary of Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

BGA Escape Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

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Section 3: Appendices

Appendix A: MGT to GTP Transceiver Design Migration

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

Primary Differences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

MGTs per Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

Serial Rate Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

Encoding Support and Clock Multipliers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

Flexibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

Board Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

Power Supply Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

Other Minor Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

Serialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

Defining Clock Correction and Channel Bonding Sequences . . . . . . . . . . . . . . . . . . . 264

RXSTATUS Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

Pre-emphasis, Differential Swing, and Equalization . . . . . . . . . . . . . . . . . . . . . . . . 264

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Appendix B: OOB/Beacon Signaling

OOB Signaling in SATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

Beacon Signaling in PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

Appendix C: 8B/10B Valid Characters

Appendix D: DRP Address Map of the GTP_DUAL Tile

DRP Address by Attribute. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

DRP Address by Bit Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

Appendix E: Low Latency Design

GTP Transmitter Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309

GTP Receiver Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310

Appendix F: Advanced Clocking

Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315

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About This Guide

This document shows how to use the RocketIO™ GTP transceivers in Virtex™-5 FPGAs.
Complete and up-to-date documentation of the Virtex-5 family of FPGAs is available on
the Xilinx website at http://www.xilinx.com/virtex5

Guide Contents

This manual contains the following chapters and appendices:

• “Section 1: FPGA Level Design”

♦ Chapter 1, “Introduction to the RocketIO GTP Transceiver”
♦ Chapter 2, “RocketIO GTP Transceiver Wizard”
♦ Chapter 3, “Simulation”
♦ Chapter 4, “Implementation”
♦ Chapter 5, “Tile Features”
♦ Chapter 6, “GTP Transmitter (TX)”
♦ Chapter 7, “GTP Receiver (RX)”
♦ Chapter 8, “Cyclic Redundancy Check (CRC)”
♦ Chapter 9, “Loopback”
♦ Chapter 10, “GTP-to-Board Interface”

• “Section 2: Board Level Design”

♦ Chapter 11, “Design Constraints Overview”
♦ Chapter 12, “PCB Materials and Traces”
♦ Chapter 13, “Design of Transitions”
♦ Chapter 14, “Guidelines and Examples”

• “Section 3: Appendices”

♦ Appendix A, “MGT to GTP Transceiver Design Migration”
♦ Appendix B, “OOB/Beacon Signaling”
♦ Appendix C, “8B/10B Valid Characters”
♦ Appendix D, “DRP Address Map of the GTP_DUAL Tile”
♦ Appendix E, “Low Latency Design”

Preface

.

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Additional Documentation

The following documents are also available for download at

http://www.xilinx.com/virtex5

• Virtex-5 Family Overview

The features and product selection of the Virtex-5 family are outlined in this overview.

• Virtex-5 Data Sheet: DC and Switching Characteristics

This data sheet contains the DC and Switching Characteristic specifications for the
Virtex-5 fam ily.

• Virtex-5 User Guide

This user guide includes chapters on:

♦ Clocking Resources
♦ Clock Management Technology (CMT)
♦ Phase-Locked Loops (PLLs)
♦ Block RAM and FIFO memory
♦ Configurable Logic Blocks (CLBs)
♦ SelectIO™ Resources
♦ I/O Logic Resources
♦ Advanced I/O Logic Resources

• Virtex-5 Tri-Mode Ethernet Media Access Controller User Guide

This user guide describes the dedicated Tri-Mode Ethernet Media Access Controller
available in the Virtex-5 LXT and SXT platform devices.

R

.

• Virtex-5 Integrated Endpoint Block User Guide for PCI Express Designs

This user guide describes the integrated Endpoint blocks in the Virtex-5 LXT and SXT
platform devices for PCI Express

®

designs.

• XtremeDSP Design Considerations

This guide describes the XtremeDSP™ slice and includes reference designs for using
the DSP48E.

• Virtex-5 Configuration Guide

This all-encompassing configuration guide includes chapters on configuration
interfaces (serial and SelectMAP), bitstream encryption, Boundary-Scan and JTAG
configuration, reconfiguration techniques, and readback through the SelectMAP and
JTAG interfaces.

• Virtex-5 System Monitor User Guide

The System Monitor functionality available in all the Virtex-5 devices is outlined in
this guide.

• Virtex-5 Packaging Specifications

This specification includes the tables for device/package combinations and maximum
I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and
thermal specifications.

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Additional Support Resources

The following documents provide supplemental material useful to this user guide:

1. Synthesis and Simulation Design Guide

http://www.xilinx.com/support/sw_manuals/xilinx

2. Granberg, Tom. Handbook of Digital Techniques for High-Speed Design. Prentice-Hall. ISBN 0-

13-142291-X.

3. Grover, Frederick W., Ph.D. 1946. Inductance Calculations: Working Formulas and Tables. New

York: D. Van Nostrand Company, Inc.

4. Johnson, Howard. Signal Integrity Techniques and Loss Budgeting for RocketIO Transceivers

http://www.xilinx.com/products/design_resources/signal_integrity/resource/hojo_dvd.htm

5. Johnson, Howard, Martin Graham. High-Speed Signal Propagation: Advanced Black Magic.

Prentice-Hall. ISBN 0-13-084408-X.

6. Montrose, Mark I. 1999. EMC and the Printed Circuit Board. The Institute of Electrical and

Electronics Engineers, Inc. ISBN 0-7803-4703-X.

7. Smith, Larry D. November 1984. Decoupling Capacitor Calculations for CMOS Circuits.

Proceedings EPEP Conference.

8. Williams, Ross N. The Painless Guide to CRC Error Detection Algorithms.

http://www.ross.net/crc/

9. DS083

10. UG024

11. UG076, Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide

12. XAPP209, IEEE 802.3 Cyclic Redundancy Check

13. XAPP562

, Virtex-II Pro and Virtex-II Pro X Platform FPGAs Complete Data Sheet

, RocketIO Transceiver User Guide

, Configurable LocalLink CRC Reference Design

(CRC pitstop).

9/download/

Additional Support Resources

To search the database of silicon and software questions and answers, or to create a
technical support case in WebCase, see the Xilinx website at:

http://www.xilinx.com/support

Typographical Conventions

This document uses the following typographical conventions. An example illustrates each
convention.

Convention Meaning or Use Example

References to other documents

Italic font

Emphasis in text

Underlined Text

Indicates a link to a web page. http://www.xilinx.com/virtex5

.

See the Virtex-5 Configuration
Guide for more information.

The address (F) is asserted after
clock event 2.

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Preface: About This Guide

Online Document

The following conventions are used in this document:

Blue text

Convention Meaning or Use Example

See the section “Additional

Cross-reference link to a location
in the current document

Documentation” for details.

Refer to “Clock Management

Technology (CMT)” in
Chapter 2 for details.

R

Red text

Blue, underlined text

Cross-reference link to a location
in another document

Hyperlink to a website (URL)

See Figure 5 in the Virtex-5 Data

Sheet

Go to http://www.xilinx.com
for the latest documentation.

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Section 1: FPGA Level Design

This section provides the information needed to incorporate RocketIO™ GTP transceivers
into an FPGA design, including:

• The features and characteristics of the GTP transceivers

• How to use the RocketIO GTP Wizard to configure the transceivers

• Mapping of transceiver instances to device resources

• Simulation of GTP transceiver designs

• Board-level clocking and power requirements

This section includes the following chapters:

“Introduction to the RocketIO GTP Transceiver”

“RocketIO GTP Transceiver Wizard”

“Simulation”

“Implementation”

“Tile Features”

“GTP Transmitter (TX)”

“GTP Receiver (RX)”

“Cyclic Redundancy Check (CRC)”

“Loopback”

“GTP-to-Board Interface”

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Section 1: FPGA Level Design

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Chapter 1

Introduction to the RocketIO GTP Transceiver

Overview

The RocketIO GTP transceiver is a power-efficient transceiver for Virtex™-5 FPGAs. The
GTP transceiver is highly configurable and tightly integrated with the programmable logic
resources of the FPGA. It provides the following features to support a wide variety of
applications:

• Current Mode Logic (CML) serial drivers/buffers with configurable termination,

voltage swing, and coupling

• Programmable TX pre-emphasis and RX equalization for optimized signal integrity

• Line rates from 100 Mb/s to 3.2 Gb/s, with optional 5x digital oversampling required

for rates between 100 Mb/s and 500 Mb/s

• Optional built-in PCS features, such as 8B/10B encoding, comma alignment, channel

bonding, and clock correction

• Fixed latency modes for minimized, deterministic datapath latency

• Out of band signaling, including COM signal support for PCI Express and SATA

Tab le 1-1 lists some of the standard protocols designers can implement using the GTP

transceiver. The Xilinx CORE Generator™ tool includes a Wizard to automatically
configure GTP transceivers to support one of these protocols or perform custom
configuration (see Chapter 2, “RocketIO GTP Transceiver Wizard”).

Table 1-1: List of Standards Supported by the GTP_DUAL Tile

Protocols Supported

PCI Express Rev 1.0a

PCI Express Rev 1.1

XAUI 802.3ae D5p0 3.125 Gb/s • LOS

OC-12/48 622.08/2488.32 Mb/s • Allow bypassing FIFOs for synchronous

FC-1 Rev 4.0 1.0625 Gb/s • Rate negotiation (allows operating the TX and RX

FC-2 Rev 4.0 2.125 Gb/s

Protocol Data Rates

Supported

2.5 Gb/s • TX receive detect

• Loss of Signal (LOS)/Idle state detect

• Low power states

• Out Of Band Beacon

• Ground Referenced termination

Miscellaneous Features

operation (not jitter transfer compliant)

at different speeds)

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Chapter 1: Introduction to the RocketIO GTP Transceiver

Table 1-1: List of Standards Supported by the GTP_DUAL Tile (Continued)

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Protocols Supported

Protocol Data Rates

Supported

10GFC 3.1875 Gb/s

SDI

HD-SDI

DVB-ASI

143/176/270/360 Mb/s

1.485/1.4835 Gb/s

270 Mb/s

10G Base-CX4 802.3ak/D4.0 3.125 Gb/s

Gigabit Ethernet (1000BASE-CX

1.25 Gb/s

802.3z/D5.0)

SATA Gen 1/II (Rev 1.0a)

SATA Gen. 2 (Rev 1.0a)

1.5 Gb/s

3.0 Gb/s

SAS Rev 5 1.5/3.0 Gb/s

Serial RapidIO 1.25/2.5/3.125 Gb/s

CPRI (Ver 2.0) 614.4/1228.8/2457.6 Mb/s

Infiniband (Volume 2 Release 1.1) 2.5 Gb/s

SFI-5 2.488 – 3.125 Gb/s • Synchronous clocking (bypass FIFOs)

OBSAI RP3 (Spec Issue 1.0)

(1)

768/1536/3072 Mb/s

Miscellaneous Features

• Rate negotiation for Gen 2 (entire link operates at

Gen 1/Gen 2 speeds)

• LOS

• OOB Beacon

Aurora 100 Mb/s – 3.2 Gb/s

GTP transceivers are placed as dual transceiver GTP_DUAL tiles in Virtex-5 LXT and SXT
Platform devices. This configuration allows two transceivers to share a single PLL with the
TX and RX functions of both, reducing size and power consumption.

Figure 1-1 shows GTP_DUAL placement in an example Virtex-5 device (XCV5LX110T).

Additional information on the functional blocks in Figure 1-1 is available in the following
locations:

• Chapter 8, “Cyclic Redundancy Check (CRC),” provides more details on the CRC

blocks in Figure 1-1.

• The Virtex-5 Configuration Guide provides more on the Config and Clock, CMT, and

I/O blocks.

• The Virtex-5 Ethernet MAC User Guide provides detailed information on the Ethernet

MAC.

• The Virtex-5 Integrated Endpoint Block User Guide for PCI Express Designs provides

detailed information on PCI Express compliance.

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Overview

Virtex-5 LX110T

CRC

Blocks

GTP_
DUAL

X0_Y7

I/O

Column

CMT

CMT

CMT

Config

and

Clock

CMT

CMT

CMT

I/O

Column

Ethernet

MAC

Ethernet

MAC

PCI

Express

CRC

Blocks

CRC

Blocks

CRC

Blocks

CRC

Blocks

CRC

Blocks

GTP_
DUAL

X0_Y6

GTP_
DUAL

X0_Y5

GTP_
DUAL

X0_Y4

GTP_
DUAL

X0_Y3

GTP_
DUAL

X0_Y2

CRC

Blocks

CRC

Blocks

GTP_
DUAL

X0_Y1

GTP_
DUAL

X0_Y0

UG196_c1_01_051507

Notes:

1. This figure does NOT illustrate exact size, location or scale of the functional blocks to each other. It does show the correct
number of available resources.

Figure 1-1: GTP_DUAL Inside the Virtex-5 LX110T FPGA

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UG196 (v1.3) May 25, 2007

Chapter 1: Introduction to the RocketIO GTP Transceiver

Figure 1-2 shows a diagram of a GTP_DUAL tile, containing two GTP transceivers and a

shared resources block. GTP_DUAL is the HDL primitive used to operate GTP
transceivers in the FPGA.

GTP_DUAL

GTP0

TXP0MGTTXP0

TXN0MGTTXN0

GTP TX

TX-PMA TX-PCS

GTP RX

RX-PMA RX-PCS

GTP TX

TX-PMA TX-PCS

GTP RX

RX-PMA RX-PCS

MGTAVTTTX

MGTAVTTRX

MGTAVTTTX

MGTAVCC

MGTAVCCPLL

MGTAVCC

RXP0MGTRXP0

RXN0MGTRXN0

AVTTTX

AVTTRX

AVTTTX

AVC C

AVCCPLL

AVC C

TXP1MGTTXP1

TXN1MGTTXN1

RXP1MGTRXP1

RXN1MGTRXN1

1

Shared

PMA

PLL

PLL Lock
Detection

Notes:

1. CLKIN is a simplification for a clock source. See Figure 5-3, page 69 for details on CLKIN.

6

7

2

Reset

Control

Powe r

Control

4

GTP1

6

7

Shared Resources

3

Clocking

DRP

5

FPGA PinsPackage Pins

TXDATA0[15:0]
TXBYPASS8B10B0[1:0]
TXCHARISK0[1:0]
TXCHARDISPMODE0[1:0]
TXCHARDISPVAL0[1:0]

RXPOWERDOWN0[1:0]
RXSTATUS0[2:0]
RXDATA0[15:0]
RXNOTINTABLE0[1:0]
RXDISPERR0[1:0]
RXCHARISCOMMA0[1:0]
RXCHARISSK0[1:0]
RXRUNDISP0[1:0]
RXVALID0[1:0]

TXOUTCLK0
TXUSRCLK0
TXUSRCLK20
RXUSRCLK0
RXUSRCLK20
RXRECCLK0

(1)

CLKIN

TXOUTCLK1
TXUSRCLK1
TXUSRCLK21
RXUSRCLK1
RXUSRCLK21
RXRECCLK1

TXDATA1[15:0]
TXBYPASS8B10B1[1:0]
TXCHARISK1[1:0]
TXCHARDISPMODE1[1:0]
TXCHARDISPVAL1[1:0]

RXPOWERDOWN1[1:0]
RXSTATUS1[2:0]
RXDATA1[15:0]
RXNOTINTABLE1[1:0]
RXDISPERR1[1:0]
RXCHARISCOMMA1[1:0]
RXCHARISSK1[1:0]
RXRUNDISP1[1:0]
RXVALID1[1:0]

UG196_c1_02_041307

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Data From FPGA Data To FPGA

Data From FPGA

Data To FPGA

Figure 1-2: GTP_DUAL Tile Block Diagram

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The procedures for configuring and using each of the seven major blocks in the
GTP_DUAL tile shown in Figure 1-2 are discussed in detail in the following sections:

1. “Shared PMA PLL,” page 60 (Chapter 5)

2. “Reset,” page 72 (Chapter 5)

3. “Clocking,” page 68 (Chapter 5)

4. “Power Control,” page 81 (Chapter 5)

5. “Dynamic Reconfiguration Port (DRP),” page 87 (Chapter 5)

6. “GTP Transmitter (TX),” page 89 (Chapter 6)

7. “GTP Receiver (RX),” page 123 (Chapter 7)

Ports and Attributes

This section contains alphabetical tables of pins (Ta bl e 1 -2 ), ports (Tab le 1 -3 ), and attributes
(Tab le 1 -4 ) Tab le 1 -2 lists alphabetically the signal names, directions, and descriptions of
the GTP_DUAL analog pins. Tab le 1 -3 lists alphabetically the signal names, clock domains,
directions, and descriptions for the GTP_DUAL ports. Tab le 1 -4 lists alphabetically the
attribute names, default values, and directions of the GTP_DUAL attributes. In all Port and
Attribute tables in this guide, names that end with 0 are for the GTP0 transceiver on the
tile, and names that end with 1 are for the GTP1 transceiver. Names that do not end with 0
or 1 are shared.

Ports and Attributes

Tab le 1- 2 summarizes all GTP_DUAL analog pins and provides links to their detailed

descriptions.

Table 1-2: GTP_DUAL Analog Pin Summary

Pin Dir Description Section (Page)

Analog supply for the shared

MGTAVCCPLL In

MGTAVTTRX In

MGTAVTTRXC In

MGTAVTTTX In

MGTAVCC In

PLL and the clock routing and
muxing network of the
GTP_DUAL tile.

Analog supply for the receiver
circuits and termination of the
GTP_DUAL tile.

Analog supply for resistor
calibration and standby
circuit of the entire device.

Analog supply for the
transmitter termination and
driver circuits of the
GTP_DUAL tile.

Analog supply for the internal
analog circuits of the
GTP_DUAL tile.

Analog Design
Guidelines (page 201)

Analog Design
Guidelines (page 201)

Analog Design
Guidelines (page 201)

Analog Design
Guidelines (page 202)

Analog Design
Guidelines (page 201)

MGTREFCLKP

MGTREFCLKN

MGTRREF In

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In

Differential clock input pin
pair for the reference clock of
the GTP_DUAL tile.

Reference resistor input for
the entire device.

Analog Design
Guidelines (page 202)

Analog Design
Guidelines (page 202)

Chapter 1: Introduction to the RocketIO GTP Transceiver

Table 1-2: GTP_DUAL Analog Pin Summary (Continued)

Pin Dir Description Section (Page)

MGTRXN0

MGTRXP0

MGTRXN1

In

Differential complements
forming a differential receiver
input pair for each transceiver.

MGTRXP1

R

RX Termination and
Equalization (page 125)

MGTTXN0

MGTTXP0

MGTTXN1

MGTTXP1

In Pad

Differential complements
forming a differential
transmitter output pair for
each transceiver.

Tab le 1- 3 summarizes all GTP_DUAL ports and provides links to their detailed

descriptions.

Table 1-3: GTP_DUAL Port Summary

Port Dir Domain Description Section (Page)

CLKIN In Async

Reference clock input to the shared
PMA PLL.

DADDR[6:0] In DCLK DRP address bus.

DCLK In N/A DRP interface clock.

DEN In DCLK Enables DRP read or write operations.

Configurable TX Driver

(page 113)

Shared PMA PLL

(page 61), Clocking
(page 70), Power

Control (page 81)

Dynamic
Reconfiguration Port
(DRP) (page 87)

Dynamic
Reconfiguration Port
(DRP) (page 87)

Dynamic
Reconfiguration Port
(DRP) (page 87)

Data bus for writing configuration data

DI[15:0] In DCLK

from the FPGA fabric to the
GTP_DUAL tile.

Data bus for reading configuration data

DO[15:0] Out DCLK

from the GTP_DUAL tile to the FPGA
fabric.

Indicates the operation is complete

DRDY Out DCLK

for DRP write

operations and data is

valid for DRP read operations.

DWE In DCLK

GTPRESET In Async

GTPTEST[3:0] In Async

24 www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide

Indicates whether the DRP operation is
a read or a write.

Starts the full GTP_DUAL reset
sequence.

Factory test pins. Must be strapped
Low for normal operation.

Dynamic
Reconfiguration Port
(DRP) (page 87)

Dynamic
Reconfiguration Port
(DRP) (page 87)

Dynamic
Reconfiguration Port
(DRP) (page 87)

Dynamic
Reconfiguration Port
(DRP) (page 87)

Reset (page 73)

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Table 1-3: GTP_DUAL Port Summary (Continued)

Port Dir Domain Description Section (Page)

Sets the internal datapath width for the
GTP_DUAL tile.

INTDATAWIDTH In Async

0: 8-bit internal datapath width

1: 10-bit internal datapath width

Ports and Attributes

Shared PMA PLL

(page 61), FPGA TX

Interface (page 90),
Parallel In to Serial Out
(PISO) (page 110),
Configurable RX Elastic
Buffer and Phase
Alignment (page 162),
Configurable Clock
Correction (page 169),
Configurable Channel
Bonding (Lane Deskew)

(page 176), FPGA RX

Interface (page 182)

LOOPBACK0[2:0]

LOOPBACK1[2:0]

PHYSTATUS0

PHYSTATUS1

PLLLKDET Out Async

PLLLKDETEN In Async Enables the PLL lock detector.

In Async Sets the loopback mode. Loopback (page 196)

Out Async

Indicates completion of several PHY
functions, including power
management state transitions and
receiver detection.

Indicates that the VCO rate is within
acceptable tolerances of the desired
rate.

PCI Express Receive
Detect Support

(page 116)

Shared PMA PLL

(page 61)

Shared PMA PLL

(page 61)

PLLPOWERDOWN In Async Powers down the shared PMA PLL. Power Control (page 81)

PRBSCNTRESET0

PRBSCNTRESET1

In RXUSRCLK2 Resets the PRBS error counter.

PRBS Detection

(page 147)

Shared PMA PLL

(page 61), Clocking
(page 70), FPGA TX

Interface (page 90), TX
Buffering, Phase
Alignment, and Buffer

REFCLKOUT Out N/A

Provides access to the reference clock
provided to the shared PLL (CLKIN).

Bypass (page 104),
FPGA RX Interface

(page 182)

REFCLKPWRDNB In Async

RESETDONE0

RESETDONE1

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UG196 (v1.3) May 25, 2007

Out Async

Powers down the GTP reference clock
circuit (active Low).

Indicates when the GTP transceiver has
finished reset and is ready for use.

Power Control (page 81)

Reset (page 73), RX
Clock Data Recovery
(CDR) (page 136)

Chapter 1: Introduction to the RocketIO GTP Transceiver

Table 1-3: GTP_DUAL Port Summary (Continued)

Port Dir Domain Description Section (Page)

RXBUFRESET0

RXBUFRESET1

RXBUFSTATUS0[2:0]

RXBUFSTATUS1[2:0]

In Async Resets the RX buffer logic.

Out RXUSRCLK2

Indicates the overflow/underflow
status of the RX buffer.

Indicates if the parallel data stream is
properly aligned on byte boundaries
according to comma detection.

RXBYTEISALIGNED0

RXBYTEISALIGNED1

Out RXUSRCLK2

When PCOMMA_ALIGN = TRUE,
asserted for alignment to PCOMMA
value.
When MCOMMA_ALIGN = TRUE,
asserted for alignment to MCOMMA
value.

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Reset (page 73),
Configurable RX Elastic
Buffer and Phase
Alignment (page 162),
Configurable Clock
Correction (page 169)

Configurable RX Elastic
Buffer and Phase
Alignment (page 162),
Configurable Clock
Correction (page 169)

Configurable Comma
Alignment and
Detection (page 149)

RXBYTEREALIGN0

RXBYTEREALIGN1

RXCDRRESET0

RXCDRRESET1

RXCHANBONDSEQ0

RXCHANBONDSEQ1

RXCHANISALIGNED0

RXCHANISALIGNED1

RXCHANREALIGN0

RXCHANREALIGN1

RXCHARISCOMMA0[1:0]

RXCHARISCOMMA1[1:0]

RXCHARISK0[1:0]

RXCHARISK1[1:0]

RXCHBONDI0[2:0]

RXCHBONDI1[2:0]

Out RXUSRCLK2

In RXUSRCLK2

Out RXUSRCLK2

Out RXUSRCLK2

Out RXUSRCLK2

Out RXUSRCLK2

Out RXUSRCLK2

In RXUSRCLK

Indicates if the byte alignment within
the serial data stream has changed due
to a comma detection.

Reset for the RX CDR. Also resets the
rest of the RX PCS.

Indicates when RXDATA contains the
start of a channel bonding sequence.

Indicates if the channel is properly
aligned with the master transceiver
according to observed channel bonding
sequences in the data stream

Held High for at least one cycle when
the receiver has changed.

Asserted when RXDATA is an 8B/10B
comma.

Asserted when RXDATA is an 8B/10B
K character.

FPGA channel bonding control. Used
only by slaves.

Configurable Comma
Alignment and
Detection (page 149)

Reset (page 73), RX
Clock Data Recovery
(CDR) (page 136)

Configurable Channel
Bonding (Lane Deskew)

(page 176)

Configurable Channel
Bonding (Lane Deskew)

(page 176)

Configurable Channel
Bonding (Lane Deskew)

(page 176)

Configurable 8B/10B
Decoder (page 157)

Configurable 8B/10B
Decoder (page 157)

Configurable Channel
Bonding (Lane Deskew)

(page 176)

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Table 1-3: GTP_DUAL Port Summary (Continued)

Port Dir Domain Description Section (Page)

Ports and Attributes

RXCHBONDO0[2:0]

RXCHBONDO1[2:0]

RXCLKCORCNT0[2:0]

RXCLKCORCNT1[2:0]

RXCOMMADET0

RXCOMMADET1

RXCOMMADETUSE0

RXCOMMADETUSE1

RXDATA0

RXDATA1

RXDATAWIDTH0

RXDATAWIDTH1

RXDEC8B10BUSE0

RXDEC8B10BUSE1

RXDISPERR0[1:0]

RXDISPERR1[1:0]

RXELECIDLE0

RXELECIDLE1

Out RXUSRCLK FPGA channel bonding control.

Out RXUSRCLK2

Out RXUSRCLK2

In RXUSRCLK2

Out RXUSRCLK2

In RXUSRCLK2

Reports the status of the elastic buffer
clock correction.

Asserted when the comma alignment
block detects a comma.

Activates the comma detection and
alignment circuit.

Receive data bus of the receive interface
to the FPGA.

Selects the width of the RXDATA
receive data connection to the FPGA.

In RXUSRCLK2 Enables the 8B/10B decoder.

Out RXUSRCLK2

Indicates if RXDATA was received with
a disparity error.

Indicates the differential voltage

Out RXUSRCLK2

between RXN and RXP dropped below
the minimum threshold.

Configurable Channel
Bonding (Lane Deskew)

(page 176)

Configurable Clock
Correction (page 169)

Configurable Comma
Alignment and
Detection (page 150)

Configurable Comma
Alignment and
Detection (page 150)

FPGA RX Interface

(page 182)

FPGA RX Interface

(page 182)

Configurable 8B/10B
Decoder (page 157)

Configurable 8B/10B
Decoder (page 157)

RX OOB/Beacon
Signaling (page 130)

RXELECIDLERESET0

RXELECIDLERESET1

RXENCHANSYNC0

RXENCHANSYNC1

In Async

In RXUSRCLK2 Enables channel bonding.

RXENELECIDLERESETB In Async

RXENEQB0

RXENEQB1

RXENMCOMMAALIGN0

RXENMCOMMAALIGN1

RXENPCOMMAALIGN0

RXENPCOMMAALIGN1

RXENPRBSTST0[1:0]

RXENPRBSTST1[1:0]

In Async

In RXUSRCLK2

In RXUSRCLK2

In RXUSRCLK2 Receiver test pattern checker control.

Resets the RX Clock Data Recovery
circuit, used by the mandatory link idle
reset circuit.

Enables the RXELECIDLERESET
inputs, used by the mandatory Link
Idle Reset circuit (active Low).

Enables receiver equalization (active
Low).

Aligns the byte boundary when comma
minus is detected.

Aligns the byte boundary when comma
plus is detected.

Reset (page 73), RX
Clock Data Recovery
(CDR) (page 136)

Configurable Channel
Bonding (Lane Deskew)

(page 176)

Reset (page 73), RX
Clock Data Recovery
(CDR) (page 136)

RX Termination and
Equalization (page 125)

Configurable Comma
Alignment and
Detection (page 150)

Configurable Comma
Alignment and
Detection (page 150)

PRBS Detection

(page 147)

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Chapter 1: Introduction to the RocketIO GTP Transceiver

Table 1-3: GTP_DUAL Port Summary (Continued)

Port Dir Domain Description Section (Page)

When High, the 5X oversampler in the

RXENSAMPLEALIGN0

RXENSAMPLEALIGN1

In RXUSRCLK2

PCS continually adjusts its sample
point. When Low, it samples only at the
point that was active before the port
went Low.

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Oversampling

(page 143)

RXEQMIX0[1:0]

RXEQMIX1[1:0]

RXEQPOLE0[3:0]

RXEQPOLE1[3:0]

RXLOSSOFSYNC0[1:0]

RXLOSSOFSYNC1[1:0]

RXNOTINTABLE0[1:0]

RXNOTINTABLE1[1:0]

RXOVERSAMPLEERR0

RXOVERSAMPLEERR1

RXPMASETPHASE0

RXPMASETPHASE1

RXPOLARITY0

RXPOLARITY1

RXPOWERDOWN0[1:0]

RXPOWERDOWN1[1:0]

In Async

In Async

Sets the wideband/high-pass mix ratio
for the RX equalizer.

Sets high-pass filter pole location for
the RX equalizer.

FPGA status related to byte stream

Out RXUSRCLK2

synchronization, depending on the
state of the RX_LOSS_OF_SYNC_FSM
attribute.

Out RXUSRCLK2

Indicates if RXDATA is the result of an
illegal 8B/10B code and is in error.

Indicates the FIFO in oversampling

Out RXUSRCLK2

circuit has either overflowed or
underflowed.

Aligns the PMA receiver recovered

In RXUSRCLK2

clock with the PCS user clocks,
allowing the RX FIFO to be bypassed.

In RXUSRCLK2 Inverts the polarity of incoming data.

In Async Powers down RX lanes.

RX Termination and
Equalization (page 125)

RX Termination and
Equalization (page 125)

Configurable Loss-of­Sync State Machine

(page 155)

Configurable 8B/10B
Decoder (page 157)

Oversampling

(page 143)

Configurable RX Elastic
Buffer and Phase
Alignment (page 162)

RX Polarity Control

(page 146)

Power Control

(page 81), PCI Express

Receive Detect Support

(page 117)

Indicates if the number of errors in

RXPRBSERR0

RXPRBSERR1

Out RXUSRCLK2

PRBS testing exceeds the value set by
the PRBS_ERR_THRESHOLD

PRBS Detection

(page 147)

attribute.

Recovered clocks derived from the RX

RXRECCLK0

RXRECCLK1

Out N/A

Clock Data Recovery circuit. Clocks the
RX logic between the PMA and the RX

FPGA RX Interface

(page 182)

elastic buffer.

RXRESET0

RXRESET1

RXRUNDISP0[1:0]

RXRUNDISP1[1:0]

RXSLIDE0

RXSLIDE1

28 www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide

In Async Active-High reset for the RX PCS logic.

Shows the running disparity of the

Out RXUSRCLK2

8B/10B encoder when RXDATA is
received.

Implements a comma alignment bump

In RXUSRCLK2

control, allowing manual comma
alignment.

Reset (page 73), FPGA
RX Interface (page 182)

Configurable 8B/10B
Decoder (page 157)

Configurable Comma
Alignment and
Detection (page 150)

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Table 1-3: GTP_DUAL Port Summary (Continued)

Port Dir Domain Description Section (Page)

RXSTATUS0[2:0]

RXSTATUS1[2:0]

Out RXUSRCLK2

Shows status of PCI Express or SATA
operations. The decoding depends on
the setting of RX_STATUS_FMT.

Ports and Attributes

TX OOB/Beacon
Signaling (page 119), RX
OOB/Beacon Signaling

(page 130), PCI Express

Receive Detect Support

(page 116)

RXUSRCLK20

RXUSRCLK21

RXUSRCLK0

RXUSRCLK1

RXVALID0

RXVALID1

TXBUFDIFFCTRL0[2:0]
TXBUFDIFFCTRL1[2:0]

TXBUFSTATUS0[1:0]

TXBUFSTATUS1[1:0]

TXBYPASS8B10B0[1:0]

TXBYPASS8B10B1[1:0]

TXCHARDISPMODE0[1:0]

TXCHARDISPMODE1[1:0]

In N/A

In N/A

Out RXUSRCLK2

In Async

Out TXUSRCLK2

In TXUSRCLK2

In TXUSRCLK2

Input clock used for the interface
between the FPGA and the GTP
transceiver.

Input clock used for internal RX logic
after the RX FIFO.

Indicates symbol lock and valid data on
RXDATA and RXCHARISK[1:0] for
PCI Express.

Controls the strength of the TX pre­drivers. Tie this port to the same value
as TXDIFFCTRL.

TX buffer status. Indicates TX buffer
overflow or underflow.

Controls the operation of the TX
8B/10B encoder on a per-byte basis.

TXCHARDISPMODE and
TXCHARDISPVAL allow the 8B/10B
disparity of outgoing data to be
controlled when 8B/10B encoding is
enabled. When 8B/10B encoding is
disabled, TXCHARDISPMODE is used
to extend the data bus for TX interfaces
whose width is a multiple of 10.

FPGA RX Interface

(page 183)

FPGA RX Interface

(page 183)

RX OOB/Beacon
Signaling (page 130)

Configurable TX Driver

(page 113)

TX Buffering, Phase
Alignment, and Buffer
Bypass (page 104)

Configurable 8B/10B
Encoder (page 99)

Configurable 8B/10B
Encoder (page 99)

TXCHARDISPVAL and
TXCHARDISPMODE allow the
disparity of outgoing data to be

TXCHARDISPVAL0[1:0]

TXCHARDISPVAL1[1:0]

In TXUSRCLK2

controlled when 8B/10B encoding is
enabled. When 8B/10B encoding is

Configurable 8B/10B

Encoder (page 99)

disabled, TXCHARDISPVAL is used to
extend the data bus for 10- and 20-bit
TX interfaces.

TXCHARISK0[1:0]

TXCHARISK1[1:0]

TXCOMSTART0

TXCOMSTART1

TXCOMTYPE0

TXCOMTYPE1

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UG196 (v1.3) May 25, 2007

In TXUSRCLK2

In TXUSRCLK2

In TXUSRCLK2

Set High to send TXDATA as an
8B/10B K character.

Initiates the transmission of the COM
sequence selected by TXCOMTYPE
(SATA only).

Selects the type of COM signal to send
(SATA only).

Configurable 8B/10B

Encoder (page 99)

TX OOB/Beacon

Signaling (page 119)

TX OOB/Beacon

Signaling (page 119)

Chapter 1: Introduction to the RocketIO GTP Transceiver

Table 1-3: GTP_DUAL Port Summary (Continued)

Port Dir Domain Description Section (Page)

R

TXDATA0

TXDATA1

TXDATAWIDTH0

TXDATAWIDTH1

TXDETECTRX0

TXDETECTRX1

TXDIFFCTRL0[2:0]

TXDIFFCTRL1[2:0]

TXELECIDLE0

TXELECIDLE1

TXENC8B10BUSE0

TXENC8B10BUSE1

In TXUSRCLK2 Transmitting data bus.

In TXUSRCLK2 Selects the width of the TXDATA port.

In TXUSRCLK2

In Async

In TXUSRCLK2

In TXUSRCLK2 Enables the 8B/10B encoder.

TXENPMAPHASEALIGN In Async

Activates the receiver detection feature
for PCI Express.

Controls the transmitter differential
output swing.

Drives TXN and TXP to the same
voltage to perform PCI Express
electrical idle/beaconing.

Allows both GTP transceivers in a
GTP_DUAL tile to align their XCLKs
with their TXUSRCLKs, allowing their
TX buffers to be bypassed, and allows
the XCLKs in multiple GTPs to be
synchronized.

FPGA TX Interface

(page 90)

FPGA TX Interface

(page 90)

Power Control

(page 81), PCI Express

Receive Detect Support

(page 117)

Configurable TX Driver

(page 113)

Power Control

(page 81), TX

OOB/Beacon Signaling

(page 119)

Configurable 8B/10B

Encoder (page 100),

FPGA TX Interface

(page 90)

TX Buffering, Phase

Alignment, and Buffer

Bypass (page 104)

TXENPRBSTST0[1:0]

TXENPRBSTST1[1:0]

TXINHIBIT0

TXINHIBIT1

TXKERR0[1:0]

TXKERR1[1:0]

TXOUTCLK0

TXOUTCLK1

In TXUSRCLK2

In TXUSRCLK2 Inhibits data transmission.

Out TXUSRCLK2

Out N/A

TXPMASETPHASE In Async

TXPOLARITY0
TXPOLARITY1

In TXUSRCLK2

Transmitter test pattern generation
control.

Indicates if an invalid code for a K
character was specified.

Provides a parallel clock generated by
the internal dividers of the GTP
transceiver.

Note: When INTDATAWIDTH = 1, the

duty cycle is 60/40 instead of 50/50.
TXOUTCLK cannot drive TXUSRCLK
when the TX phase-alignment circuit is
used.

Aligns XCLK with TXUSRCLK for both
GTP transceivers in the GTP_DUAL
tile.

Specifies if the final transmitter output
is inverted.

TX PRBS Generator

(page 109)

Configurable 8B/10B

Encoder (page 100)

FPGA TX Interface

(page 91), TX Buffering,

Phase Alignment, and

Buffer Bypass (page 104)

TX Buffering, Phase

Alignment, and Buffer

Bypass (page 104)

TX Polarity Control

(page 108)

30 www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide

UG196 (v1.3) May 25, 2007