Xilinx Virtex-5 RocketIO GTP Transceiver User Manual

Virtex-5 RocketIO GTP Transceiver User Guide

UG196 (v1.3) May 25, 2007

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Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate
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copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Design.
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accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design.

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THE DESIGN TO YOU WITHOUT THESE LIMITATIONS OF LIABILITY.

The Design is not designed or intended for use in the development of on-line control equipment in hazardous environments requiring fail­safe controls, such as in the operation of nuclear facilities, aircraft navigation or communications systems, air traffic control, life support, or
weapons systems (“High-Risk Applications”). Xilinx specifically disclaims any express or implied warranties of fitness for such High-Risk
Applications. You represent that use of the Design in such High-Risk Applications is fully at your risk.

© 2006-2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx,
Inc. PowerPC is a trademark of IBM, Inc. All other trademarks are the property of their respective owners.

Revision History

The following table shows the revision history for this document.

Date Version Revision

09/06/06 1.0 Initial release to CD.

10/13/06 1.1 Initial release to www.xilinx.com

02/02/07 1.2 Added SXT packages to “Package Placement Information” in Chapter 4. Inserted RX

buffer overflow/underflow footnotes to Ta bl e 7 -2 8 and Ta b le 7 - 30 . Added “SelectIO-to-

GTP Crosstalk Guidelines” in Chapter 10. Added “SelectIO to Serial Transceiver
Crosstalk Guidelines” in Chapter 11. Added Appendix E, “Low Latency Design.”

Removed Virtex-II Pro X FPGA references.

Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007

Date Version Revision

05/25/07 1.3 Chapter 1: Revised line rates in the “Overview,” page 19. Added to RXBYTEISALIGNED

description and removed CRC ports in Tab le 1- 3 , pag e 2 4. Corrected
PCOMMA_DETECT entry and removed CRC_INIT[31:0] attribute in Tab le 1- 4. CRC
ports are not part of the GTP_DUAL primitive. See Chapter 8.

Chapter 3: Added “Providing Clocks In Simulation,” page 44. Added multirate clocking
design caveats and link to Appendix F.

Chapter 4: Added a note 2 to Tab le 4- 1 , pag e 49.

Chapter 5: Added to note 5 in Figure 5-1, page 60. Added PCS_COM_CFG and notes to

Figure 5-2, page 63. Revised Equation 5-1. Changed PLL clock frequency for FC1, FC2,

SFI-5, TFI-5, and the HD-SDI standard in Tab le 5 - 3, p age 6 3. Revised the notes for

Figure 5-5, page 71. Added PRBSCNTRESET and PLLPOWERDOWN, and revised

GTPRESET description in Tab l e 5-6, p age 7 3 . Revised “GTP Component-Level Resets”
and “Link Idle Reset Support,” page 75. Added note to RXPOWERDOWN in Tab l e 5- 9 ,

page 81. Added note to Table 5-11, page 83.

Chapter 6: Added a BUFG to Figure 6-5. Revised PMA_COM_CFG,
OVERSAMPLE_MODE, and added three attributes to Table 6-8, page 105. Revised the

“Using the TX Phase-Alignment Circuit to Bypass the TX Buffer,” page 106. Revised
Figure 6-12, page 107. Added INTDATAWIDTH to Table 6-12, page 109. Revised

OVERSAMPLE_MODE in Table 6-14, page 111. Revised TX_DIFF_BOOST in Table 6-16,

page 113. Added default value to Table 6-18, page 114.

Chapter 7: Revised Figure 7-2, page 126. Updated Tabl e 7- 3. Added OOB nominal values
to Ta bl e 7- 6. Added “Tuning the CDR,” page 139. Revised Table 7-12, page 141. Added
note 1 to Table 7-29, page 163. Revised CLK_COR_MAX_LAT

Chapter 8: Added clarification to the CRC block description.

Chapter 9: Made changes to “Near-End PCS Loopback,” “Near-End PMA Loopback,”

“Far-End PMA Loopback,” and “Far-End PCS Loopback,” including adding “Marginal
Conditions and Limitations.” Added Tab le 9 - 2.

Chapter 10: Clarified

“REFCLK Guidelines,” page 207. Added Figure 10-9. Added

TERMINATION_IMP to Table 10-2. Added note on analog supplies to Table 10-3,

Table 10-4, and Table 10-5. Added SelectIO Adjacent to MGTCLK tables at the end of the

chapter. Edited “AC Coupling,” page 210. Added an additional guideline to “Filter

Network Design Guidelines.”

Appendix D: Added PCS_COM_CFG to Ta bl e D -2 , Ta bl e D -7 , and Tabl e D- 8. Revised bit
4 and 6 in Tab le D -3 .

Appendix E: Added note 2 to Table E-2, page 311.

Added Appendix F.

UG196 (v1.3) May 25, 2007 www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide

Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com UG196 (v1.3) May 25, 2007

Table of Contents

Preface: About This Guide

Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Additional Support Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Typographical Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Section 1: FPGA Level Design

Chapter 1: Introduction to the RocketIO GTP Transceiver

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Chapter 2: RocketIO GTP Transceiver Wizard

Chapter 3: Simulation

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

SmartModel Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

SIM_GTPRESET_SPEEDUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

SIM_PLL_PERDIV2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

SIM_RECEIVER_DETECT_PASS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Power-Up and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Link Idle Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Toggling GSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Providing Clocks In Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Simulating in Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Defining GSR/GTS in a Test Bench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Simulating in VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Simulation Environment Setup Example (ModelSim SE 6.1d on Linux) . . . . . . . . . . . . 46

SIM_PLL_PERDIV2 Calculation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Chapter 4: Implementation

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Example of a UCF for GTP_DUAL Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Package Placement Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com 5

UG196 (v1.3) May 25, 2007

Chapter 5: Tile Features

Tile Features Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Shared PMA PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Configuring the Shared PLL for XAUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Configuring the Shared PLL for OC-48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Configuring the Shared PLL for Gigabit Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Configuring Shared PLL for PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Clocking from an External Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Clocking from a Neighbor GTP_DUAL Tile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Clocking using GREFCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

GTP Reset in Response to Completion of Configuration . . . . . . . . . . . . . . . . . . . . . . . . 74

GTP Reset When the GTPRESET Port is Asserted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

GTP Component-Level Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Link Idle Reset Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Resetting the GTP_DUAL Tile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Generic GTP Power Control Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Power Control Features for PCI Express. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Powerdown Transition Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Dynamic Reconfiguration Port (DRP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

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Chapter 6: GTP Transmitter (TX)

Transmitter Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

FPGA TX Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Configuring the Width of the Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Connecting TXUSRCLK and TXUSRCLK2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

TXOUTCLK Driving a GTP TX in 1-Byte Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

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TXOUTCLK Driving GTP TX in 2-Byte Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

TXOUTCLK Driving Multiple Transceivers for a 2-Byte Datapath . . . . . . . . . . . . . . . . 95

REFCLKOUT Driving Multiple Transceivers with a 2-Byte Interface. . . . . . . . . . . . . . . 96

Configurable 8B/10B Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Enabling 8B/10B Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

8B/10B Bit and Byte Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

K Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Running Disparity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

8B/10B Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

TX Buffering, Phase Alignment, and Buffer Bypass . . . . . . . . . . . . . . . . . . . . . . . . . 102

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Using the TX Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Using the TX Phase-Alignment Circuit to Bypass the TX Buffer . . . . . . . . . . . . . . . . . 106

Using the TX Phase Alignment Circuit to Minimize TX Skew . . . . . . . . . . . . . . . . . . . 107

TX Polarity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

TX PRBS Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Parallel In to Serial Out (PISO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Configurable TX Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Differential Voltage Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Pre-Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Configurable Termination Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

TXINHIBIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

PCI Express Receive Detect Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

TX OOB/Beacon Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

PCI Express Beacon Signaling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

SATA OOB Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

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Chapter 7: GTP Receiver (RX)

Receiver Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

RX Termination and Equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Optional Built-In AC Coupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Configurable Termination Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Configurable Termination Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Optional Configurable RX Linear Equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

RX OOB/Beacon Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Detecting PCI Express Electrical Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

SATA OOB Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

RX Clock Data Recovery (CDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

CDR Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Tuning the CDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Horizontal Sample Point Shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Serial In to Parallel Out (SIPO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Oversampling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Configuring the 5x Line Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Configuring the PCS Internal Datapath and Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Activating and Operating the Oversampling Block . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

RX Polarity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

PRBS Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Configurable Comma Alignment and Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Enabling Comma Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Configuring Comma Patterns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Activating Comma Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Alignment Status Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

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Alignment Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Manual Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Configurable Loss-of-Sync State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Configurable 8B/10B Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Enabling the 8B/10B Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

8B/10B Decoder Bit and Byte Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

K Characters and 8B/10B Commas. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

RX Running Disparity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Disparity Errors and Not-in-Table Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Configurable RX Elastic Buffer and Phase Alignment. . . . . . . . . . . . . . . . . . . . . . . 161

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Using the RX Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Using RX Phase Alignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Bypassing the RX Buffer while Using Built-In Oversampling . . . . . . . . . . . . . . . . . . . 167

Configurable Clock Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Enabling Clock Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Setting RX Buffer Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Setting Clock Correction Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Clock Correction Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Monitoring Clock Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Configurable Channel Bonding (Lane Deskew). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Enabling Channel Bonding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Channel Bonding Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Connecting Channel Bonding Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Setting the Channel Bonding Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Setting the Maximum Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Precedence between Channel Bonding and Clock Correction . . . . . . . . . . . . . . . . . . . 181

FPGA RX Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Configuring the Width of the Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Connecting RXUSRCLK and RXUSRCLK2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Chapter 8: Cyclic Redundancy Check (CRC)

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

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Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

Using CRC for Error Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

The CRC Primitive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

Using the CRC Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

Integrating the CRC Blocks for TX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

Integrating the CRC Blocks for RX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

Implementation of the CRC Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

Chapter 9: Loopback

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Near-End PCS Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Near-End PMA Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Marginal Conditions and Limitations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Far-End PMA Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Marginal Conditions and Limitations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Far-End PCS Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

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Chapter 10: GTP-to-Board Interface

Analog Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

REFCLK Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

GTP Reference Clock Checklist. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Oscillator Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Sourcing More Than One Differential Clock Input Pair from One Oscillator . . . . . . . . 209

Switching between Two Different Reference Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . 210

AC Coupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

Unused Reference Clock Inputs of GTP_DUAL Tiles for Clock Forwarding . . . . . . . . 210

Examples of Vendors and Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

Providing Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Linear Regulator Selection Criteria . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Regulator Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Ferrite Selection Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Capacitor Selection Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

Filter Network Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

Special Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

SelectIO-to-GTP Crosstalk Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

Section 2: Board Level Design

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Chapter 11: Design Constraints Overview

Powering Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

Power Distribution Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

Regulator Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

Reference Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

Clock Traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

Coupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

DC Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

AC Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

External Capacitor Value Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

SelectIO to Serial Transceiver Crosstalk Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

Chapter 12: PCB Materials and Traces

How Fast is Fast? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

Dielectric Losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

Relative Permittivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

Loss Tangent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

Skin Effect and Resistive Losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

Choosing the Substrate Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

Traces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

Trace Geometry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

Trace Characteristic Impedance Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

Trace Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

Plane Splits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

Return Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

Simulating Lossy Transmission Lines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

Optimal Cable Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

Skew Between Conductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

Chapter 13: Design of Transitions

Excess Capacitance and Inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

Time Domain Reflectometry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

BGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

SMT Pads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

Differential Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

P/N Crossover Vias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

SMA Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

Backplane Connectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

Microstrip/Stripline Bends . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

Chapter 14: Guidelines and Examples

Summary of Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

BGA Escape Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

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Section 3: Appendices

Appendix A: MGT to GTP Transceiver Design Migration

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

Primary Differences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

MGTs per Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

Serial Rate Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

Encoding Support and Clock Multipliers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

Flexibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

Board Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

Power Supply Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

Other Minor Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

Serialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

Defining Clock Correction and Channel Bonding Sequences . . . . . . . . . . . . . . . . . . . 264

RXSTATUS Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

Pre-emphasis, Differential Swing, and Equalization . . . . . . . . . . . . . . . . . . . . . . . . 264

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Appendix B: OOB/Beacon Signaling

OOB Signaling in SATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

Beacon Signaling in PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

Appendix C: 8B/10B Valid Characters

Appendix D: DRP Address Map of the GTP_DUAL Tile

DRP Address by Attribute. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

DRP Address by Bit Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

Appendix E: Low Latency Design

GTP Transmitter Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309

GTP Receiver Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310

Appendix F: Advanced Clocking

Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315

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About This Guide

This document shows how to use the RocketIO™ GTP transceivers in Virtex™-5 FPGAs.
Complete and up-to-date documentation of the Virtex-5 family of FPGAs is available on
the Xilinx website at http://www.xilinx.com/virtex5

Guide Contents

This manual contains the following chapters and appendices:

• “Section 1: FPGA Level Design”

♦ Chapter 1, “Introduction to the RocketIO GTP Transceiver”
♦ Chapter 2, “RocketIO GTP Transceiver Wizard”
♦ Chapter 3, “Simulation”
♦ Chapter 4, “Implementation”
♦ Chapter 5, “Tile Features”
♦ Chapter 6, “GTP Transmitter (TX)”
♦ Chapter 7, “GTP Receiver (RX)”
♦ Chapter 8, “Cyclic Redundancy Check (CRC)”
♦ Chapter 9, “Loopback”
♦ Chapter 10, “GTP-to-Board Interface”

• “Section 2: Board Level Design”

♦ Chapter 11, “Design Constraints Overview”
♦ Chapter 12, “PCB Materials and Traces”
♦ Chapter 13, “Design of Transitions”
♦ Chapter 14, “Guidelines and Examples”

• “Section 3: Appendices”

♦ Appendix A, “MGT to GTP Transceiver Design Migration”
♦ Appendix B, “OOB/Beacon Signaling”
♦ Appendix C, “8B/10B Valid Characters”
♦ Appendix D, “DRP Address Map of the GTP_DUAL Tile”
♦ Appendix E, “Low Latency Design”

Preface

.

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Additional Documentation

The following documents are also available for download at

http://www.xilinx.com/virtex5

• Virtex-5 Family Overview

The features and product selection of the Virtex-5 family are outlined in this overview.

• Virtex-5 Data Sheet: DC and Switching Characteristics

This data sheet contains the DC and Switching Characteristic specifications for the
Virtex-5 fam ily.

• Virtex-5 User Guide

This user guide includes chapters on:

♦ Clocking Resources
♦ Clock Management Technology (CMT)
♦ Phase-Locked Loops (PLLs)
♦ Block RAM and FIFO memory
♦ Configurable Logic Blocks (CLBs)
♦ SelectIO™ Resources
♦ I/O Logic Resources
♦ Advanced I/O Logic Resources

• Virtex-5 Tri-Mode Ethernet Media Access Controller User Guide

This user guide describes the dedicated Tri-Mode Ethernet Media Access Controller
available in the Virtex-5 LXT and SXT platform devices.

R

.

• Virtex-5 Integrated Endpoint Block User Guide for PCI Express Designs

This user guide describes the integrated Endpoint blocks in the Virtex-5 LXT and SXT
platform devices for PCI Express

®

designs.

• XtremeDSP Design Considerations

This guide describes the XtremeDSP™ slice and includes reference designs for using
the DSP48E.

• Virtex-5 Configuration Guide

This all-encompassing configuration guide includes chapters on configuration
interfaces (serial and SelectMAP), bitstream encryption, Boundary-Scan and JTAG
configuration, reconfiguration techniques, and readback through the SelectMAP and
JTAG interfaces.

• Virtex-5 System Monitor User Guide

The System Monitor functionality available in all the Virtex-5 devices is outlined in
this guide.

• Virtex-5 Packaging Specifications

This specification includes the tables for device/package combinations and maximum
I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and
thermal specifications.

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Additional Support Resources

The following documents provide supplemental material useful to this user guide:

1. Synthesis and Simulation Design Guide

http://www.xilinx.com/support/sw_manuals/xilinx

2. Granberg, Tom. Handbook of Digital Techniques for High-Speed Design. Prentice-Hall. ISBN 0-

13-142291-X.

3. Grover, Frederick W., Ph.D. 1946. Inductance Calculations: Working Formulas and Tables. New

York: D. Van Nostrand Company, Inc.

4. Johnson, Howard. Signal Integrity Techniques and Loss Budgeting for RocketIO Transceivers

http://www.xilinx.com/products/design_resources/signal_integrity/resource/hojo_dvd.htm

5. Johnson, Howard, Martin Graham. High-Speed Signal Propagation: Advanced Black Magic.

Prentice-Hall. ISBN 0-13-084408-X.

6. Montrose, Mark I. 1999. EMC and the Printed Circuit Board. The Institute of Electrical and

Electronics Engineers, Inc. ISBN 0-7803-4703-X.

7. Smith, Larry D. November 1984. Decoupling Capacitor Calculations for CMOS Circuits.

Proceedings EPEP Conference.

8. Williams, Ross N. The Painless Guide to CRC Error Detection Algorithms.

http://www.ross.net/crc/

9. DS083

10. UG024

11. UG076, Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide

12. XAPP209, IEEE 802.3 Cyclic Redundancy Check

13. XAPP562

, Virtex-II Pro and Virtex-II Pro X Platform FPGAs Complete Data Sheet

, RocketIO Transceiver User Guide

, Configurable LocalLink CRC Reference Design

(CRC pitstop).

9/download/

Additional Support Resources

To search the database of silicon and software questions and answers, or to create a
technical support case in WebCase, see the Xilinx website at:

http://www.xilinx.com/support

Typographical Conventions

This document uses the following typographical conventions. An example illustrates each
convention.

Convention Meaning or Use Example

References to other documents

Italic font

Emphasis in text

Underlined Text

Indicates a link to a web page. http://www.xilinx.com/virtex5

.

See the Virtex-5 Configuration
Guide for more information.

The address (F) is asserted after
clock event 2.

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Preface: About This Guide

Online Document

The following conventions are used in this document:

Blue text

Convention Meaning or Use Example

See the section “Additional

Cross-reference link to a location
in the current document

Documentation” for details.

Refer to “Clock Management

Technology (CMT)” in
Chapter 2 for details.

R

Red text

Blue, underlined text

Cross-reference link to a location
in another document

Hyperlink to a website (URL)

See Figure 5 in the Virtex-5 Data

Sheet

Go to http://www.xilinx.com
for the latest documentation.

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Section 1: FPGA Level Design

This section provides the information needed to incorporate RocketIO™ GTP transceivers
into an FPGA design, including:

• The features and characteristics of the GTP transceivers

• How to use the RocketIO GTP Wizard to configure the transceivers

• Mapping of transceiver instances to device resources

• Simulation of GTP transceiver designs

• Board-level clocking and power requirements

This section includes the following chapters:

“Introduction to the RocketIO GTP Transceiver”

“RocketIO GTP Transceiver Wizard”

“Simulation”

“Implementation”

“Tile Features”

“GTP Transmitter (TX)”

“GTP Receiver (RX)”

“Cyclic Redundancy Check (CRC)”

“Loopback”

“GTP-to-Board Interface”

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Section 1: FPGA Level Design

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Chapter 1

Introduction to the RocketIO GTP Transceiver

Overview

The RocketIO GTP transceiver is a power-efficient transceiver for Virtex™-5 FPGAs. The
GTP transceiver is highly configurable and tightly integrated with the programmable logic
resources of the FPGA. It provides the following features to support a wide variety of
applications:

• Current Mode Logic (CML) serial drivers/buffers with configurable termination,

voltage swing, and coupling

• Programmable TX pre-emphasis and RX equalization for optimized signal integrity

• Line rates from 100 Mb/s to 3.2 Gb/s, with optional 5x digital oversampling required

for rates between 100 Mb/s and 500 Mb/s

• Optional built-in PCS features, such as 8B/10B encoding, comma alignment, channel

bonding, and clock correction

• Fixed latency modes for minimized, deterministic datapath latency

• Out of band signaling, including COM signal support for PCI Express and SATA

Tab le 1-1 lists some of the standard protocols designers can implement using the GTP

transceiver. The Xilinx CORE Generator™ tool includes a Wizard to automatically
configure GTP transceivers to support one of these protocols or perform custom
configuration (see Chapter 2, “RocketIO GTP Transceiver Wizard”).

Table 1-1: List of Standards Supported by the GTP_DUAL Tile

Protocols Supported

PCI Express Rev 1.0a

PCI Express Rev 1.1

XAUI 802.3ae D5p0 3.125 Gb/s • LOS

OC-12/48 622.08/2488.32 Mb/s • Allow bypassing FIFOs for synchronous

FC-1 Rev 4.0 1.0625 Gb/s • Rate negotiation (allows operating the TX and RX

FC-2 Rev 4.0 2.125 Gb/s

Protocol Data Rates

Supported

2.5 Gb/s • TX receive detect

• Loss of Signal (LOS)/Idle state detect

• Low power states

• Out Of Band Beacon

• Ground Referenced termination

Miscellaneous Features

operation (not jitter transfer compliant)

at different speeds)

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Chapter 1: Introduction to the RocketIO GTP Transceiver

Table 1-1: List of Standards Supported by the GTP_DUAL Tile (Continued)

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Protocols Supported

Protocol Data Rates

Supported

10GFC 3.1875 Gb/s

SDI

HD-SDI

DVB-ASI

143/176/270/360 Mb/s

1.485/1.4835 Gb/s

270 Mb/s

10G Base-CX4 802.3ak/D4.0 3.125 Gb/s

Gigabit Ethernet (1000BASE-CX

1.25 Gb/s

802.3z/D5.0)

SATA Gen 1/II (Rev 1.0a)

SATA Gen. 2 (Rev 1.0a)

1.5 Gb/s

3.0 Gb/s

SAS Rev 5 1.5/3.0 Gb/s

Serial RapidIO 1.25/2.5/3.125 Gb/s

CPRI (Ver 2.0) 614.4/1228.8/2457.6 Mb/s

Infiniband (Volume 2 Release 1.1) 2.5 Gb/s

SFI-5 2.488 – 3.125 Gb/s • Synchronous clocking (bypass FIFOs)

OBSAI RP3 (Spec Issue 1.0)

(1)

768/1536/3072 Mb/s

Miscellaneous Features

• Rate negotiation for Gen 2 (entire link operates at

Gen 1/Gen 2 speeds)

• LOS

• OOB Beacon

Aurora 100 Mb/s – 3.2 Gb/s

GTP transceivers are placed as dual transceiver GTP_DUAL tiles in Virtex-5 LXT and SXT
Platform devices. This configuration allows two transceivers to share a single PLL with the
TX and RX functions of both, reducing size and power consumption.

Figure 1-1 shows GTP_DUAL placement in an example Virtex-5 device (XCV5LX110T).

Additional information on the functional blocks in Figure 1-1 is available in the following
locations:

• Chapter 8, “Cyclic Redundancy Check (CRC),” provides more details on the CRC

blocks in Figure 1-1.

• The Virtex-5 Configuration Guide provides more on the Config and Clock, CMT, and

I/O blocks.

• The Virtex-5 Ethernet MAC User Guide provides detailed information on the Ethernet

MAC.

• The Virtex-5 Integrated Endpoint Block User Guide for PCI Express Designs provides

detailed information on PCI Express compliance.

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Overview

Virtex-5 LX110T

CRC

Blocks

GTP_
DUAL

X0_Y7

I/O

Column

CMT

CMT

CMT

Config

and

Clock

CMT

CMT

CMT

I/O

Column

Ethernet

MAC

Ethernet

MAC

PCI

Express

CRC

Blocks

CRC

Blocks

CRC

Blocks

CRC

Blocks

CRC

Blocks

GTP_
DUAL

X0_Y6

GTP_
DUAL

X0_Y5

GTP_
DUAL

X0_Y4

GTP_
DUAL

X0_Y3

GTP_
DUAL

X0_Y2

CRC

Blocks

CRC

Blocks

GTP_
DUAL

X0_Y1

GTP_
DUAL

X0_Y0

UG196_c1_01_051507

Notes:

1. This figure does NOT illustrate exact size, location or scale of the functional blocks to each other. It does show the correct
number of available resources.

Figure 1-1: GTP_DUAL Inside the Virtex-5 LX110T FPGA

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UG196 (v1.3) May 25, 2007

Chapter 1: Introduction to the RocketIO GTP Transceiver

Figure 1-2 shows a diagram of a GTP_DUAL tile, containing two GTP transceivers and a

shared resources block. GTP_DUAL is the HDL primitive used to operate GTP
transceivers in the FPGA.

GTP_DUAL

GTP0

TXP0MGTTXP0

TXN0MGTTXN0

GTP TX

TX-PMA TX-PCS

GTP RX

RX-PMA RX-PCS

GTP TX

TX-PMA TX-PCS

GTP RX

RX-PMA RX-PCS

MGTAVTTTX

MGTAVTTRX

MGTAVTTTX

MGTAVCC

MGTAVCCPLL

MGTAVCC

RXP0MGTRXP0

RXN0MGTRXN0

AVTTTX

AVTTRX

AVTTTX

AVC C

AVCCPLL

AVC C

TXP1MGTTXP1

TXN1MGTTXN1

RXP1MGTRXP1

RXN1MGTRXN1

1

Shared

PMA

PLL

PLL Lock
Detection

Notes:

1. CLKIN is a simplification for a clock source. See Figure 5-3, page 69 for details on CLKIN.

6

7

2

Reset

Control

Powe r

Control

4

GTP1

6

7

Shared Resources

3

Clocking

DRP

5

FPGA PinsPackage Pins

TXDATA0[15:0]
TXBYPASS8B10B0[1:0]
TXCHARISK0[1:0]
TXCHARDISPMODE0[1:0]
TXCHARDISPVAL0[1:0]

RXPOWERDOWN0[1:0]
RXSTATUS0[2:0]
RXDATA0[15:0]
RXNOTINTABLE0[1:0]
RXDISPERR0[1:0]
RXCHARISCOMMA0[1:0]
RXCHARISSK0[1:0]
RXRUNDISP0[1:0]
RXVALID0[1:0]

TXOUTCLK0
TXUSRCLK0
TXUSRCLK20
RXUSRCLK0
RXUSRCLK20
RXRECCLK0

(1)

CLKIN

TXOUTCLK1
TXUSRCLK1
TXUSRCLK21
RXUSRCLK1
RXUSRCLK21
RXRECCLK1

TXDATA1[15:0]
TXBYPASS8B10B1[1:0]
TXCHARISK1[1:0]
TXCHARDISPMODE1[1:0]
TXCHARDISPVAL1[1:0]

RXPOWERDOWN1[1:0]
RXSTATUS1[2:0]
RXDATA1[15:0]
RXNOTINTABLE1[1:0]
RXDISPERR1[1:0]
RXCHARISCOMMA1[1:0]
RXCHARISSK1[1:0]
RXRUNDISP1[1:0]
RXVALID1[1:0]

UG196_c1_02_041307

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Data From FPGA Data To FPGA

Data From FPGA

Data To FPGA

Figure 1-2: GTP_DUAL Tile Block Diagram

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The procedures for configuring and using each of the seven major blocks in the
GTP_DUAL tile shown in Figure 1-2 are discussed in detail in the following sections:

1. “Shared PMA PLL,” page 60 (Chapter 5)

2. “Reset,” page 72 (Chapter 5)

3. “Clocking,” page 68 (Chapter 5)

4. “Power Control,” page 81 (Chapter 5)

5. “Dynamic Reconfiguration Port (DRP),” page 87 (Chapter 5)

6. “GTP Transmitter (TX),” page 89 (Chapter 6)

7. “GTP Receiver (RX),” page 123 (Chapter 7)

Ports and Attributes

This section contains alphabetical tables of pins (Ta bl e 1 -2 ), ports (Tab le 1 -3 ), and attributes
(Tab le 1 -4 ) Tab le 1 -2 lists alphabetically the signal names, directions, and descriptions of
the GTP_DUAL analog pins. Tab le 1 -3 lists alphabetically the signal names, clock domains,
directions, and descriptions for the GTP_DUAL ports. Tab le 1 -4 lists alphabetically the
attribute names, default values, and directions of the GTP_DUAL attributes. In all Port and
Attribute tables in this guide, names that end with 0 are for the GTP0 transceiver on the
tile, and names that end with 1 are for the GTP1 transceiver. Names that do not end with 0
or 1 are shared.

Ports and Attributes

Tab le 1- 2 summarizes all GTP_DUAL analog pins and provides links to their detailed

descriptions.

Table 1-2: GTP_DUAL Analog Pin Summary

Pin Dir Description Section (Page)

Analog supply for the shared

MGTAVCCPLL In

MGTAVTTRX In

MGTAVTTRXC In

MGTAVTTTX In

MGTAVCC In

PLL and the clock routing and
muxing network of the
GTP_DUAL tile.

Analog supply for the receiver
circuits and termination of the
GTP_DUAL tile.

Analog supply for resistor
calibration and standby
circuit of the entire device.

Analog supply for the
transmitter termination and
driver circuits of the
GTP_DUAL tile.

Analog supply for the internal
analog circuits of the
GTP_DUAL tile.

Analog Design
Guidelines (page 201)

Analog Design
Guidelines (page 201)

Analog Design
Guidelines (page 201)

Analog Design
Guidelines (page 202)

Analog Design
Guidelines (page 201)

MGTREFCLKP

MGTREFCLKN

MGTRREF In

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In

Differential clock input pin
pair for the reference clock of
the GTP_DUAL tile.

Reference resistor input for
the entire device.

Analog Design
Guidelines (page 202)

Analog Design
Guidelines (page 202)

Chapter 1: Introduction to the RocketIO GTP Transceiver

Table 1-2: GTP_DUAL Analog Pin Summary (Continued)

Pin Dir Description Section (Page)

MGTRXN0

MGTRXP0

MGTRXN1

In

Differential complements
forming a differential receiver
input pair for each transceiver.

MGTRXP1

R

RX Termination and
Equalization (page 125)

MGTTXN0

MGTTXP0

MGTTXN1

MGTTXP1

In Pad

Differential complements
forming a differential
transmitter output pair for
each transceiver.

Tab le 1- 3 summarizes all GTP_DUAL ports and provides links to their detailed

descriptions.

Table 1-3: GTP_DUAL Port Summary

Port Dir Domain Description Section (Page)

CLKIN In Async

Reference clock input to the shared
PMA PLL.

DADDR[6:0] In DCLK DRP address bus.

DCLK In N/A DRP interface clock.

DEN In DCLK Enables DRP read or write operations.

Configurable TX Driver

(page 113)

Shared PMA PLL

(page 61), Clocking
(page 70), Power

Control (page 81)

Dynamic
Reconfiguration Port
(DRP) (page 87)

Dynamic
Reconfiguration Port
(DRP) (page 87)

Dynamic
Reconfiguration Port
(DRP) (page 87)

Data bus for writing configuration data

DI[15:0] In DCLK

from the FPGA fabric to the
GTP_DUAL tile.

Data bus for reading configuration data

DO[15:0] Out DCLK

from the GTP_DUAL tile to the FPGA
fabric.

Indicates the operation is complete

DRDY Out DCLK

for DRP write

operations and data is

valid for DRP read operations.

DWE In DCLK

GTPRESET In Async

GTPTEST[3:0] In Async

24 www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide

Indicates whether the DRP operation is
a read or a write.

Starts the full GTP_DUAL reset
sequence.

Factory test pins. Must be strapped
Low for normal operation.

Dynamic
Reconfiguration Port
(DRP) (page 87)

Dynamic
Reconfiguration Port
(DRP) (page 87)

Dynamic
Reconfiguration Port
(DRP) (page 87)

Dynamic
Reconfiguration Port
(DRP) (page 87)

Reset (page 73)

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Table 1-3: GTP_DUAL Port Summary (Continued)

Port Dir Domain Description Section (Page)

Sets the internal datapath width for the
GTP_DUAL tile.

INTDATAWIDTH In Async

0: 8-bit internal datapath width

1: 10-bit internal datapath width

Ports and Attributes

Shared PMA PLL

(page 61), FPGA TX

Interface (page 90),
Parallel In to Serial Out
(PISO) (page 110),
Configurable RX Elastic
Buffer and Phase
Alignment (page 162),
Configurable Clock
Correction (page 169),
Configurable Channel
Bonding (Lane Deskew)

(page 176), FPGA RX

Interface (page 182)

LOOPBACK0[2:0]

LOOPBACK1[2:0]

PHYSTATUS0

PHYSTATUS1

PLLLKDET Out Async

PLLLKDETEN In Async Enables the PLL lock detector.

In Async Sets the loopback mode. Loopback (page 196)

Out Async

Indicates completion of several PHY
functions, including power
management state transitions and
receiver detection.

Indicates that the VCO rate is within
acceptable tolerances of the desired
rate.

PCI Express Receive
Detect Support

(page 116)

Shared PMA PLL

(page 61)

Shared PMA PLL

(page 61)

PLLPOWERDOWN In Async Powers down the shared PMA PLL. Power Control (page 81)

PRBSCNTRESET0

PRBSCNTRESET1

In RXUSRCLK2 Resets the PRBS error counter.

PRBS Detection

(page 147)

Shared PMA PLL

(page 61), Clocking
(page 70), FPGA TX

Interface (page 90), TX
Buffering, Phase
Alignment, and Buffer

REFCLKOUT Out N/A

Provides access to the reference clock
provided to the shared PLL (CLKIN).

Bypass (page 104),
FPGA RX Interface

(page 182)

REFCLKPWRDNB In Async

RESETDONE0

RESETDONE1

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UG196 (v1.3) May 25, 2007

Out Async

Powers down the GTP reference clock
circuit (active Low).

Indicates when the GTP transceiver has
finished reset and is ready for use.

Power Control (page 81)

Reset (page 73), RX
Clock Data Recovery
(CDR) (page 136)

Chapter 1: Introduction to the RocketIO GTP Transceiver

Table 1-3: GTP_DUAL Port Summary (Continued)

Port Dir Domain Description Section (Page)

RXBUFRESET0

RXBUFRESET1

RXBUFSTATUS0[2:0]

RXBUFSTATUS1[2:0]

In Async Resets the RX buffer logic.

Out RXUSRCLK2

Indicates the overflow/underflow
status of the RX buffer.

Indicates if the parallel data stream is
properly aligned on byte boundaries
according to comma detection.

RXBYTEISALIGNED0

RXBYTEISALIGNED1

Out RXUSRCLK2

When PCOMMA_ALIGN = TRUE,
asserted for alignment to PCOMMA
value.
When MCOMMA_ALIGN = TRUE,
asserted for alignment to MCOMMA
value.

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Reset (page 73),
Configurable RX Elastic
Buffer and Phase
Alignment (page 162),
Configurable Clock
Correction (page 169)

Configurable RX Elastic
Buffer and Phase
Alignment (page 162),
Configurable Clock
Correction (page 169)

Configurable Comma
Alignment and
Detection (page 149)

RXBYTEREALIGN0

RXBYTEREALIGN1

RXCDRRESET0

RXCDRRESET1

RXCHANBONDSEQ0

RXCHANBONDSEQ1

RXCHANISALIGNED0

RXCHANISALIGNED1

RXCHANREALIGN0

RXCHANREALIGN1

RXCHARISCOMMA0[1:0]

RXCHARISCOMMA1[1:0]

RXCHARISK0[1:0]

RXCHARISK1[1:0]

RXCHBONDI0[2:0]

RXCHBONDI1[2:0]

Out RXUSRCLK2

In RXUSRCLK2

Out RXUSRCLK2

Out RXUSRCLK2

Out RXUSRCLK2

Out RXUSRCLK2

Out RXUSRCLK2

In RXUSRCLK

Indicates if the byte alignment within
the serial data stream has changed due
to a comma detection.

Reset for the RX CDR. Also resets the
rest of the RX PCS.

Indicates when RXDATA contains the
start of a channel bonding sequence.

Indicates if the channel is properly
aligned with the master transceiver
according to observed channel bonding
sequences in the data stream

Held High for at least one cycle when
the receiver has changed.

Asserted when RXDATA is an 8B/10B
comma.

Asserted when RXDATA is an 8B/10B
K character.

FPGA channel bonding control. Used
only by slaves.

Configurable Comma
Alignment and
Detection (page 149)

Reset (page 73), RX
Clock Data Recovery
(CDR) (page 136)

Configurable Channel
Bonding (Lane Deskew)

(page 176)

Configurable Channel
Bonding (Lane Deskew)

(page 176)

Configurable Channel
Bonding (Lane Deskew)

(page 176)

Configurable 8B/10B
Decoder (page 157)

Configurable 8B/10B
Decoder (page 157)

Configurable Channel
Bonding (Lane Deskew)

(page 176)

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Table 1-3: GTP_DUAL Port Summary (Continued)

Port Dir Domain Description Section (Page)

Ports and Attributes

RXCHBONDO0[2:0]

RXCHBONDO1[2:0]

RXCLKCORCNT0[2:0]

RXCLKCORCNT1[2:0]

RXCOMMADET0

RXCOMMADET1

RXCOMMADETUSE0

RXCOMMADETUSE1

RXDATA0

RXDATA1

RXDATAWIDTH0

RXDATAWIDTH1

RXDEC8B10BUSE0

RXDEC8B10BUSE1

RXDISPERR0[1:0]

RXDISPERR1[1:0]

RXELECIDLE0

RXELECIDLE1

Out RXUSRCLK FPGA channel bonding control.

Out RXUSRCLK2

Out RXUSRCLK2

In RXUSRCLK2

Out RXUSRCLK2

In RXUSRCLK2

Reports the status of the elastic buffer
clock correction.

Asserted when the comma alignment
block detects a comma.

Activates the comma detection and
alignment circuit.

Receive data bus of the receive interface
to the FPGA.

Selects the width of the RXDATA
receive data connection to the FPGA.

In RXUSRCLK2 Enables the 8B/10B decoder.

Out RXUSRCLK2

Indicates if RXDATA was received with
a disparity error.

Indicates the differential voltage

Out RXUSRCLK2

between RXN and RXP dropped below
the minimum threshold.

Configurable Channel
Bonding (Lane Deskew)

(page 176)

Configurable Clock
Correction (page 169)

Configurable Comma
Alignment and
Detection (page 150)

Configurable Comma
Alignment and
Detection (page 150)

FPGA RX Interface

(page 182)

FPGA RX Interface

(page 182)

Configurable 8B/10B
Decoder (page 157)

Configurable 8B/10B
Decoder (page 157)

RX OOB/Beacon
Signaling (page 130)

RXELECIDLERESET0

RXELECIDLERESET1

RXENCHANSYNC0

RXENCHANSYNC1

In Async

In RXUSRCLK2 Enables channel bonding.

RXENELECIDLERESETB In Async

RXENEQB0

RXENEQB1

RXENMCOMMAALIGN0

RXENMCOMMAALIGN1

RXENPCOMMAALIGN0

RXENPCOMMAALIGN1

RXENPRBSTST0[1:0]

RXENPRBSTST1[1:0]

In Async

In RXUSRCLK2

In RXUSRCLK2

In RXUSRCLK2 Receiver test pattern checker control.

Resets the RX Clock Data Recovery
circuit, used by the mandatory link idle
reset circuit.

Enables the RXELECIDLERESET
inputs, used by the mandatory Link
Idle Reset circuit (active Low).

Enables receiver equalization (active
Low).

Aligns the byte boundary when comma
minus is detected.

Aligns the byte boundary when comma
plus is detected.

Reset (page 73), RX
Clock Data Recovery
(CDR) (page 136)

Configurable Channel
Bonding (Lane Deskew)

(page 176)

Reset (page 73), RX
Clock Data Recovery
(CDR) (page 136)

RX Termination and
Equalization (page 125)

Configurable Comma
Alignment and
Detection (page 150)

Configurable Comma
Alignment and
Detection (page 150)

PRBS Detection

(page 147)

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Chapter 1: Introduction to the RocketIO GTP Transceiver

Table 1-3: GTP_DUAL Port Summary (Continued)

Port Dir Domain Description Section (Page)

When High, the 5X oversampler in the

RXENSAMPLEALIGN0

RXENSAMPLEALIGN1

In RXUSRCLK2

PCS continually adjusts its sample
point. When Low, it samples only at the
point that was active before the port
went Low.

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Oversampling

(page 143)

RXEQMIX0[1:0]

RXEQMIX1[1:0]

RXEQPOLE0[3:0]

RXEQPOLE1[3:0]

RXLOSSOFSYNC0[1:0]

RXLOSSOFSYNC1[1:0]

RXNOTINTABLE0[1:0]

RXNOTINTABLE1[1:0]

RXOVERSAMPLEERR0

RXOVERSAMPLEERR1

RXPMASETPHASE0

RXPMASETPHASE1

RXPOLARITY0

RXPOLARITY1

RXPOWERDOWN0[1:0]

RXPOWERDOWN1[1:0]

In Async

In Async

Sets the wideband/high-pass mix ratio
for the RX equalizer.

Sets high-pass filter pole location for
the RX equalizer.

FPGA status related to byte stream

Out RXUSRCLK2

synchronization, depending on the
state of the RX_LOSS_OF_SYNC_FSM
attribute.

Out RXUSRCLK2

Indicates if RXDATA is the result of an
illegal 8B/10B code and is in error.

Indicates the FIFO in oversampling

Out RXUSRCLK2

circuit has either overflowed or
underflowed.

Aligns the PMA receiver recovered

In RXUSRCLK2

clock with the PCS user clocks,
allowing the RX FIFO to be bypassed.

In RXUSRCLK2 Inverts the polarity of incoming data.

In Async Powers down RX lanes.

RX Termination and
Equalization (page 125)

RX Termination and
Equalization (page 125)

Configurable Loss-of­Sync State Machine

(page 155)

Configurable 8B/10B
Decoder (page 157)

Oversampling

(page 143)

Configurable RX Elastic
Buffer and Phase
Alignment (page 162)

RX Polarity Control

(page 146)

Power Control

(page 81), PCI Express

Receive Detect Support

(page 117)

Indicates if the number of errors in

RXPRBSERR0

RXPRBSERR1

Out RXUSRCLK2

PRBS testing exceeds the value set by
the PRBS_ERR_THRESHOLD

PRBS Detection

(page 147)

attribute.

Recovered clocks derived from the RX

RXRECCLK0

RXRECCLK1

Out N/A

Clock Data Recovery circuit. Clocks the
RX logic between the PMA and the RX

FPGA RX Interface

(page 182)

elastic buffer.

RXRESET0

RXRESET1

RXRUNDISP0[1:0]

RXRUNDISP1[1:0]

RXSLIDE0

RXSLIDE1

28 www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide

In Async Active-High reset for the RX PCS logic.

Shows the running disparity of the

Out RXUSRCLK2

8B/10B encoder when RXDATA is
received.

Implements a comma alignment bump

In RXUSRCLK2

control, allowing manual comma
alignment.

Reset (page 73), FPGA
RX Interface (page 182)

Configurable 8B/10B
Decoder (page 157)

Configurable Comma
Alignment and
Detection (page 150)

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Table 1-3: GTP_DUAL Port Summary (Continued)

Port Dir Domain Description Section (Page)

RXSTATUS0[2:0]

RXSTATUS1[2:0]

Out RXUSRCLK2

Shows status of PCI Express or SATA
operations. The decoding depends on
the setting of RX_STATUS_FMT.

Ports and Attributes

TX OOB/Beacon
Signaling (page 119), RX
OOB/Beacon Signaling

(page 130), PCI Express

Receive Detect Support

(page 116)

RXUSRCLK20

RXUSRCLK21

RXUSRCLK0

RXUSRCLK1

RXVALID0

RXVALID1

TXBUFDIFFCTRL0[2:0]
TXBUFDIFFCTRL1[2:0]

TXBUFSTATUS0[1:0]

TXBUFSTATUS1[1:0]

TXBYPASS8B10B0[1:0]

TXBYPASS8B10B1[1:0]

TXCHARDISPMODE0[1:0]

TXCHARDISPMODE1[1:0]

In N/A

In N/A

Out RXUSRCLK2

In Async

Out TXUSRCLK2

In TXUSRCLK2

In TXUSRCLK2

Input clock used for the interface
between the FPGA and the GTP
transceiver.

Input clock used for internal RX logic
after the RX FIFO.

Indicates symbol lock and valid data on
RXDATA and RXCHARISK[1:0] for
PCI Express.

Controls the strength of the TX pre­drivers. Tie this port to the same value
as TXDIFFCTRL.

TX buffer status. Indicates TX buffer
overflow or underflow.

Controls the operation of the TX
8B/10B encoder on a per-byte basis.

TXCHARDISPMODE and
TXCHARDISPVAL allow the 8B/10B
disparity of outgoing data to be
controlled when 8B/10B encoding is
enabled. When 8B/10B encoding is
disabled, TXCHARDISPMODE is used
to extend the data bus for TX interfaces
whose width is a multiple of 10.

FPGA RX Interface

(page 183)

FPGA RX Interface

(page 183)

RX OOB/Beacon
Signaling (page 130)

Configurable TX Driver

(page 113)

TX Buffering, Phase
Alignment, and Buffer
Bypass (page 104)

Configurable 8B/10B
Encoder (page 99)

Configurable 8B/10B
Encoder (page 99)

TXCHARDISPVAL and
TXCHARDISPMODE allow the
disparity of outgoing data to be

TXCHARDISPVAL0[1:0]

TXCHARDISPVAL1[1:0]

In TXUSRCLK2

controlled when 8B/10B encoding is
enabled. When 8B/10B encoding is

Configurable 8B/10B

Encoder (page 99)

disabled, TXCHARDISPVAL is used to
extend the data bus for 10- and 20-bit
TX interfaces.

TXCHARISK0[1:0]

TXCHARISK1[1:0]

TXCOMSTART0

TXCOMSTART1

TXCOMTYPE0

TXCOMTYPE1

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In TXUSRCLK2

In TXUSRCLK2

In TXUSRCLK2

Set High to send TXDATA as an
8B/10B K character.

Initiates the transmission of the COM
sequence selected by TXCOMTYPE
(SATA only).

Selects the type of COM signal to send
(SATA only).

Configurable 8B/10B

Encoder (page 99)

TX OOB/Beacon

Signaling (page 119)

TX OOB/Beacon

Signaling (page 119)

Chapter 1: Introduction to the RocketIO GTP Transceiver

Table 1-3: GTP_DUAL Port Summary (Continued)

Port Dir Domain Description Section (Page)

R

TXDATA0

TXDATA1

TXDATAWIDTH0

TXDATAWIDTH1

TXDETECTRX0

TXDETECTRX1

TXDIFFCTRL0[2:0]

TXDIFFCTRL1[2:0]

TXELECIDLE0

TXELECIDLE1

TXENC8B10BUSE0

TXENC8B10BUSE1

In TXUSRCLK2 Transmitting data bus.

In TXUSRCLK2 Selects the width of the TXDATA port.

In TXUSRCLK2

In Async

In TXUSRCLK2

In TXUSRCLK2 Enables the 8B/10B encoder.

TXENPMAPHASEALIGN In Async

Activates the receiver detection feature
for PCI Express.

Controls the transmitter differential
output swing.

Drives TXN and TXP to the same
voltage to perform PCI Express
electrical idle/beaconing.

Allows both GTP transceivers in a
GTP_DUAL tile to align their XCLKs
with their TXUSRCLKs, allowing their
TX buffers to be bypassed, and allows
the XCLKs in multiple GTPs to be
synchronized.

FPGA TX Interface

(page 90)

FPGA TX Interface

(page 90)

Power Control

(page 81), PCI Express

Receive Detect Support

(page 117)

Configurable TX Driver

(page 113)

Power Control

(page 81), TX

OOB/Beacon Signaling

(page 119)

Configurable 8B/10B

Encoder (page 100),

FPGA TX Interface

(page 90)

TX Buffering, Phase

Alignment, and Buffer

Bypass (page 104)

TXENPRBSTST0[1:0]

TXENPRBSTST1[1:0]

TXINHIBIT0

TXINHIBIT1

TXKERR0[1:0]

TXKERR1[1:0]

TXOUTCLK0

TXOUTCLK1

In TXUSRCLK2

In TXUSRCLK2 Inhibits data transmission.

Out TXUSRCLK2

Out N/A

TXPMASETPHASE In Async

TXPOLARITY0
TXPOLARITY1

In TXUSRCLK2

Transmitter test pattern generation
control.

Indicates if an invalid code for a K
character was specified.

Provides a parallel clock generated by
the internal dividers of the GTP
transceiver.

Note: When INTDATAWIDTH = 1, the

duty cycle is 60/40 instead of 50/50.
TXOUTCLK cannot drive TXUSRCLK
when the TX phase-alignment circuit is
used.

Aligns XCLK with TXUSRCLK for both
GTP transceivers in the GTP_DUAL
tile.

Specifies if the final transmitter output
is inverted.

TX PRBS Generator

(page 109)

Configurable 8B/10B

Encoder (page 100)

FPGA TX Interface

(page 91), TX Buffering,

Phase Alignment, and

Buffer Bypass (page 104)

TX Buffering, Phase

Alignment, and Buffer

Bypass (page 104)

TX Polarity Control

(page 108)

30 www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide

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Table 1-3: GTP_DUAL Port Summary (Continued)

Port Dir Domain Description Section (Page)

TXPOWERDOWN0[1:0]

TXPOWERDOWN1[1:0]

In Async Powers down TX lanes.

Ports and Attributes

Power Control

(page 81), PCI Express

Receive Detect Support

(page 117), TX

OOB/Beacon Signaling

(page 119)

TXPREEMPHASIS0[2:0]

TXPREEMPHASIS1[2:0]

TXRESET0

TXRESET1

TXRUNDISP0[1:0]
TXRUNDISP1[1:0]

TXUSRCLK0

TXUSRCLK1

TXUSRCLK20
TXUSRCLK21

In Async

In Async

Out TXUSRCLK2

In N/A

In N/A

Tab le 1- 4 summarizes the GTP_DUAL tile attributes and provides links to their detailed

descriptions.

Table 1-4: GTP_DUAL Attribute Summary

Attribute Description Section (Page)

AC_CAP_DIS_0

AC_CAP_DIS_1

Disables built-in AC coupling capacitors on
receiver inputs when set to TRUE.

Controls the relative strength of the
main drive and the pre-emphasis.

Resets the PCS of the GTP transmitter,
including the phase adjust FIFO, the
8B/10B encoder, and the FPGA TX
interface.

Indicates the current running disparity
of the 8B/10B encoder.

Provides a clock for the internal TX PCS
datapath.

Synchronizes the FPGA logic with the
TX interface.

RX Termination and
Equalization (page 126)

Configurable TX Driver

(page 113)

Reset (page 73), FPGA

TX Interface (page 91)

Configurable 8B/10B

Encoder (page 100)

FPGA TX Interface

(page 91), TX Buffering,

Phase Alignment, and

Buffer Bypass (page 104)

FPGA TX Interface

(page 91)

ALIGN_COMMA_WORD_0

ALIGN_COMMA_WORD_1

CHAN_BOND_1_MAX_SKEW_0

CHAN_BOND_1_MAX_SKEW_1

CHAN_BOND_2_MAX_SKEW_0

CHAN_BOND_2_MAX_SKEW_1

CHAN_BOND_LEVEL_0

CHAN_BOND_LEVEL_1

CHAN_BOND_MODE_0

CHAN_BOND_MODE_1

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UG196 (v1.3) May 25, 2007

Controls alignment of detected commas
within a multi-byte datapath.

Sets the maximum amount of lane skew
allowed when using channel bonding. Must
be set less than 1/2 the minimum distance
between channel bonding sequences.

Indicates the amount of internal pipelining
used for the elastic buffer control signals.

Defines the channel bonding mode of
operation for the transceiver.

Configurable Comma
Alignment and Detection

(page 151)

Configurable Channel Bonding
(Lane Deskew) (page 176)

Configurable Channel Bonding
(Lane Deskew) (page 177)

Configurable Channel Bonding
(Lane Deskew) (page 177)

Chapter 1: Introduction to the RocketIO GTP Transceiver

Table 1-4: GTP_DUAL Attribute Summary (Continued)

Attribute Description Section (Page)

CHAN_BOND_SEQ_1_1_0

CHAN_BOND_SEQ_1_1_1

CHAN_BOND_SEQ_1_2_0

CHAN_BOND_SEQ_1_2_1

CHAN_BOND_SEQ_1_3_0

Used in conjunction with
CHAN_BOND_SEQ_1_ENABLE to define
channel bonding sequence 1.

CHAN_BOND_SEQ_1_3_1

CHAN_BOND_SEQ_1_4_0

CHAN_BOND_SEQ_1_4_1

R

Configurable Channel Bonding
(Lane Deskew) (page 177)

CHAN_BOND_SEQ_1_ENABLE_0

CHAN_BOND_SEQ_1_ENABLE_1

CHAN_BOND_SEQ_2_1_0

CHAN_BOND_SEQ_2_1_1

CHAN_BOND_SEQ_2_2_0

CHAN_BOND_SEQ_2_2_1

CHAN_BOND_SEQ_2_3_0

CHAN_BOND_SEQ_2_3_1

CHAN_BOND_SEQ_2_4_0

CHAN_BOND_SEQ_2_4_1

CHAN_BOND_SEQ_2_ENABLE_0

CHAN_BOND_SEQ_2_ENABLE_1

CHAN_BOND_SEQ_2_USE_0

CHAN_BOND_SEQ_2_USE_1

CHAN_BOND_SEQ_LEN_0

CHAN_BOND_SEQ_LEN_1

CLK_COR_ADJ_LEN_0

CLK_COR_ADJ_LEN_1

Sets which parts of channel bonding
sequence 1 are don't cares.

Used in conjunction with
CHAN_BOND_SEQ_2_ENABLE to define
the second channel bonding sequence.

Sets which parts of channel bonding
sequence 2 are don't cares.

Determines if the second channel bonding
sequence is to be used.

Defines the length in bytes of the channel
bonding sequence that the transceiver
matches to detect opportunities for channel
bonding.

Defines the size of the adjustment (number
of bytes repeated or skipped) in a clock
correction.

Configurable Channel Bonding
(Lane Deskew) (page 177)

Configurable Channel Bonding
(Lane Deskew) (page 177)

Configurable Channel Bonding
(Lane Deskew) (page 177)

Configurable Channel Bonding
(Lane Deskew) (page 177)

Configurable Channel Bonding
(Lane Deskew) (page 178)

Configurable Clock Correction

(page 169)

CLK_COR_DET_LEN_0

CLK_COR_DET_LEN_1

CLK_COR_INSERT_IDLE_FLAG_0

CLK_COR_INSERT_IDLE_FLAG_1

CLK_COR_KEEP_IDLE_0

CLK_COR_KEEP_IDLE_1

CLK_COR_MAX_LAT_0

CLK_COR_MAX_LAT_1

32 www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide

Defines the length of the sequence that the
transceiver matches to detect opportunities
for clock correction.

Controls whether RXRUNDISP input status
indicates running disparity or inserted-idle
(clock correction sequence) flag.

Controls whether the elastic buffer must
retain at least one clock correction sequence
in the byte stream.

Specifies the maximum elastic buffer
latency.

Configurable Clock Correction

(page 170)

Configurable Clock Correction

(page 170)

Configurable Clock Correction

(page 170)

Configurable Clock Correction

(page 170)

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Table 1-4: GTP_DUAL Attribute Summary (Continued)

Attribute Description Section (Page)

Ports and Attributes

CLK_COR_MIN_LAT_0

CLK_COR_MIN_LAT_1

CLK_COR_PRECEDENCE_0

CLK_COR_PRECEDENCE_1

CLK_COR_REPEAT_WAIT_0

CLK_COR_REPEAT_WAIT_1

CLK_COR_SEQ_1_1_0

CLK_COR_SEQ_1_1_1

CLK_COR_SEQ_1_2_0

CLK_COR_SEQ_1_2_1

CLK_COR_SEQ_1_3_0

CLK_COR_SEQ_1_3_1

CLK_COR_SEQ_1_4_1

CLK_COR_SEQ_1_ENABLE_0

CLK_COR_SEQ_1_ENABLE_1

CLK_COR_SEQ_2_1_0

CLK_COR_SEQ_2_1_1

CLK_COR_SEQ_2_2_0

CLK_COR_SEQ_2_2_1

CLK_COR_SEQ_2_3_0

CLK_COR_SEQ_2_3_1

CLK_COR_SEQ_2_4_0

CLK_COR_SEQ_2_4_1

Specifies the minimum elastic buffer latency.

Determines whether clock correction or
channel bonding takes precedence when
both operations are triggered at the same
time. Set to TRUE to give clock correction
precedence.

Specifies the minimum number of
RXUSRCLK cycles without clock correction
that must occur between successive clock
corrections.

The CLK_COR_SEQ_1 attributes are used
in conjunction with
CLK_COR_SEQ_1_ENABLE to define
clock correction sequence 1.

Sets which parts of clock correction
sequence 1 are don't cares.

Used in conjunction with
CLK_COR_SEQ_2_ENABLE to define the
second clock correction sequence.

Configurable Clock Correction

(page 170)

Configurable Clock Correction

(page 170)

Configurable Clock Correction

(page 170)

Configurable Clock Correction

(page 172)

Configurable Clock Correction

(page 172)

Configurable Clock Correction

(page 172)

CLK_COR_SEQ_2_ENABLE_0

CLK_COR_SEQ_2_ENABLE_1

CLK_COR_SEQ_2_USE_0

CLK_COR_SEQ_2_USE_1

CLK_CORRECT_USE_0

CLK_CORRECT_USE_1

CLK25_DIVIDER

Sets which parts of clock correction
sequence 2 are don't cares.

Determines if the second clock correction
sequence is to be used.

Set to TRUE to enable Clock Correction.

Sets the divider used to divide CLKIN
down to an internal rate close to 25 MHz.

Configurable Clock Correction

(page 172)

Configurable Clock Correction

(page 172)

Configurable Clock Correction

(page 172)

Clocking (page 70), Power
Control (page 82)

Must be set to TRUE. Oscillators driving the

CLKINDC_B

dedicated reference clock inputs must be

Clocking (page 70)

AC coupled.

COM_BURST_VAL_0[3:0]

COM_BURST_VAL_1[3:0]

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UG196 (v1.3) May 25, 2007

Number of bursts transmitted for a SATA
COM sequence.

TX OOB/Beacon Signaling

(page 120)

Chapter 1: Introduction to the RocketIO GTP Transceiver

Table 1-4: GTP_DUAL Attribute Summary (Continued)

Attribute Description Section (Page)

R

COMMA_10B_ENABLE_0
COMMA_10B_ENABLE_1

Sets which bits of MCOMMA/PCOMMA
must be matched to incoming data and
which bits are don't cares.

When TRUE, a PCOMMA match followed

COMMA_DOUBLE_0

COMMA_DOUBLE_1

immediately by an MCOMMA match is
required for comma detection. Used to
detect A1/A2 framing characters for
SONET.

DEC_MCOMMA_DETECT_0

DEC_MCOMMA_DETECT_1

DEC_PCOMMA_DETECT_0

DEC_PCOMMA_DETECT_1

DEC_VALID_COMMA_ONLY_0

DEC_VALID_COMMA_ONLY_1

MCOMMA_10B_VALUE_0

MCOMMA_10B_VALUE_1

MCOMMA_DETECT_0

MCOMMA_DETECT_1

Enables detection of negative 8B/10B
commas.

Enables detection of positive 8B/10B
commas.

Limits the set of commas to which
RXCHARISCOMMA responds.

Defines comma minus to raise
RXCOMMADET and align the parallel
data.

Set to TRUE to allow minus comma
detection and alignment.

OOB_CLK_DIVIDER Sets the squelch clock rate based on CLKIN.

Configurable Comma
Alignment and Detection

(page 151)

Configurable Comma
Alignment and Detection

(page 151)

Configurable 8B/10B Decoder

(page 158)

Configurable 8B/10B Decoder

(page 158)

Configurable 8B/10B Decoder

(page 158)

Configurable Comma
Alignment and Detection

(page 151)

Configurable Comma
Alignment and Detection

(page 151)

RX OOB/Beacon Signaling

(page 131)

Sets the minimum differential voltage

OOBDETECT_THRESHOLD_0

OOBDETECT_THRESHOLD_1

between RXN and RXP before a signal is
recognized as a valid PCI electrical idle or a

RX OOB/Beacon Signaling

(page 131)

SATA OOB signal.

TX Buffering, Phase Alignment,
and Buffer Bypass (page 105),
Parallel In to Serial Out (PISO)

OVERSAMPLE_MODE Enables 5X oversampling.

(page 111), Serial In to Parallel

Out (SIPO) (page 141),
Oversampling (page 144),
Configurable RX Elastic Buffer
and Phase Alignment (page 163)

PCI_EXPRESS_MODE_0

PCI_EXPRESS_MODE_1

PCOMMA_10B_VALUE_0

PCOMMA_10B_VALUE_1

PCOMMA_DETECT_0

PCOMMA_DETECT_1

Enables certain operations specific to PCI
Express.

Defines comma plus to raise
RXCOMMADET and align the parallel
data.

Set to TRUE to allow plus comma detection
and alignment.

Power Control (page 82),
Configurable Channel Bonding
(Lane Deskew) (page 178)

Configurable Comma
Alignment and Detection

(page 151)

Configurable Comma
Alignment and Detection

(page 152)

PCS_COM_CFG Shared PLL configuration settings. Shared PMA PLL (page 61)

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Table 1-4: GTP_DUAL Attribute Summary (Continued)

Attribute Description Section (Page)

Ports and Attributes

PLL_DIVSEL_FB

PLL_DIVSEL_REF

PLL_RXDIVSEL_OUT_0

PLL_RXDIVSEL_OUT_1

PLL_SATA_0

PLL_SATA_1

PLL_TXDIVSEL_COMM_OUT

PLL_TXDIVSEL_OUT_0

PLL_TXDIVSEL_OUT_1

PMA_CDR_SCAN_0

PMA_CDR_SCAN_1

Controls the feedback divider of the shared
PMA PLL.

Controls the reference clock divider of the
shared PMA PLL.

Defines the nominal line rate for the
receiver based on the shared PMA PLL rate.

Tie to FALSE. When FALSE, allows TX
SATA operations to work at the SATA1 or
SATA2 rate.

Sets a common line rate divider for both
GTP transceivers in a tile. Can be used
instead of PLL_TXDIVSEL_OUT if both
transceivers are using the same TX divider
value.

Sets the divider for the TX line rate for each
GTP transceiver.

Allows direct control of the CDR sampling
point

Shared PMA PLL (page 61)

Shared PMA PLL (page 61)

Shared PMA PLL (page 61),
Serial In to Parallel Out (SIPO)

(page 141)

TX OOB/Beacon Signaling

(page 120)

Shared PMA PLL (page 61),
Parallel In to Serial Out (PISO)

(page 111), TX OOB/Beacon

Signaling (page 120)

Shared PMA PLL (page 61),
Parallel In to Serial Out (PISO)

(page 111), TX OOB/Beacon

Signaling (page 120)

RX Clock Data Recovery (CDR)

(page 137)

PMA_COM_CFG

PMA_RX_CFG_0

PMA_RX_CFG_1

PRBS_ERR_THRESHOLD_0

PRBS_ERR_THRESHOLD_1

RCV_TERM_GND_0

RCV_TERM_GND_1

RCV_TERM_MID_0

RCV_TERM_MID_1

RCV_TERM_VTTRX_0

RCV_TERM_VTTRX_1

RX_BUFFER_USE_0

RX_BUFFER_USE_1

Common configuration attribute for the
PMA.

Adjusts CDR operation for oversampling
and PLL_RXDIVSEL_OUT settings.

Sets the error threshold for the PRBS
checker.

Sets the RX termination voltage to GND.
Used with internal and external AC
coupling to support PCI Express
TXDETECTRX functionality.

Activates the internal RX termination
voltage. Set to TRUE when RX built-in AC
coupling is used.

Sets RX termination voltage to VTTRX.

Set to TRUE to use the RX elastic buffer.

Marginal Conditions and
Limitations (page 197)

TX Buffering, Phase Alignment,
and Buffer Bypass (page 105)

RX Clock Data Recovery (CDR)

(page 137)

PRBS Detection (page 147)

RX Termination and
Equalization (page 126)

RX Termination and
Equalization (page 126)

RX Termination and
Equalization (page 126)

Configurable RX Elastic Buffer
and Phase Alignment (page 163)

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UG196 (v1.3) May 25, 2007

Chapter 1: Introduction to the RocketIO GTP Transceiver

Table 1-4: GTP_DUAL Attribute Summary (Continued)

Attribute Description Section (Page)

R

RX_DECODE_SEQ_MATCH_0

RX_DECODE_SEQ_MATCH_1

RX_LOS_INVALID_INCR_0

RX_LOS_INVALID_INCR_1

RX_LOS_THRESHOLD_0

RX_LOS_THRESHOLD_1

RX_LOSS_OF_SYNC_FSM_0

RX_LOSS_OF_SYNC_FSM_1

RX_SLIDE_MODE_0

RX_SLIDE_MODE_1

RX_STATUS_FMT_0

RX_STATUS_FMT_1

RX_XCLK_SEL_0

RX_XCLK_SEL_1

Determines whether sequences are
matched against 8B/10B decoded data or
undecoded data.

Defines the number of valid characters
required to decrement the error count by 1
for the purpose of loss-of-sync
determination.

Defines the error count required to move
the Loss of Sync state machine from the
SYNC_ACQUIRED to the SYNC_LOST
state.

Defines the behavior of the
RXLOSSOFSYNC outputs.

Selects between sliding in the PMA or in the
PCS.

Sets whether the RX_STATUS port is used
to report the status of PCI Express or SATA
features.

Selects which clock is used on the PMA side
of the RX FIFO. The default setting is
RXREC (RX recovered clock). RXUSR (RX
USRCLK) should be used when bypassing
the RX buffer.

Configurable Clock Correction

(page 172)

Configurable Loss-of-Sync State
Machine (page 155)

Configurable Loss-of-Sync State
Machine (page 155)

Configurable Loss-of-Sync State
Machine (page 155)

Configurable Comma
Alignment and Detection

(page 152)

RX OOB/Beacon Signaling

(page 131)

Configurable RX Elastic Buffer
and Phase Alignment (page 163)

SATA_BURST_VAL_0

SATA_BURST_VAL_1

SATA_IDLE_VAL_0

SATA_IDLE_VAL_1

SATA_MAX_BURST_0

SATA_MAX_BURST_1

SATA_MAX_INIT_0

SATA_MAX_INIT_1

SATA_MAX_WAKE_0

SATA_MAX_WAKE_1

SATA_MIN_BURST_0

SATA_MIN_BURST_1

SATA_MIN_INIT_0

SATA_MIN_INIT_1

Number of bursts required for the SATA
OOB detector to declare a COM match.

Number of idles required for the SATA
OOB detector to declare a COM match.

Sets the threshold for the SATA detector to
reject a burst in terms of squelch clock
cycles.

Sets the maximum time allowed for a
COMINIT/COMRESET idle for the SATA
detector in terms of squelch clock cycles.

Sets the maximum time allowed for a
COMWAKE idle for the SATA detector in
terms of squelch clock cycles.

Sets the threshold for the SATA detector to
reject a burst in terms of squelch clock
cycles.

Used to set the minimum time allowed for a
COMINIT/COMRESET Idle for the SATA
detector in terms of squelch clock cycles.

RX OOB/Beacon Signaling

(page 131)

RX OOB/Beacon Signaling

(page 131)

RX OOB/Beacon Signaling

(page 131)

RX OOB/Beacon Signaling

(page 131)

RX OOB/Beacon Signaling

(page 132)

RX OOB/Beacon Signaling

(page 132)

RX OOB/Beacon Signaling

(page 132)

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Table 1-4: GTP_DUAL Attribute Summary (Continued)

Attribute Description Section (Page)

Ports and Attributes

SATA_MIN_WAKE_0

SATA_MIN_WAKE_1

SIM_GTPRESET_SPEEDUP

SIM_PLL_PERDIV2

SIM_RECEIVER_DETECT_PASS0

SIM_RECEIVER_DETECT_PASS1

TERMINATION_CTRL[4:0]

TERMINATION_OVRD

TRANS_TIME_FROM_P2_0

TRANS_TIME_FROM_P2_1

TRANS_TIME_NON_P2_0

TRANS_TIME_NON_P2_1

Used to set the minimum time allowed for a
COMWAKE idle for the SATA detector in
terms of squelch clock cycles.

RX OOB/Beacon Signaling

(page 132)

Shortens the time it takes to finish the
GTPRESET sequence and PLL lock during

Simulation (page 42)

simulation.

Specifies the length of one symbol in
picoseconds for simulation.

Simulation (page 42)

Controls the receiver detect function. Simulation (page 42)

Controls internal termination calibration
circuit.

Analog Design Guidelines,

(page 202)

Selects whether the external 50Ω precision
resistor, connected to the MGTRREF pin, or
an override value is used, as defined by

Analog Design Guidelines,

(page 202)

TERMINATION_CTRL.

Transition time from the P2 powerdown
state in internal 25 MHz clock cycles. The
exact time depends on the CLKIN rate and

Power Control (page 82)

the setting of CLK25_DIVIDER.

Transition time to or from any powerdown
state except P2 in internal 25 MHz clock
cycles. The exact time depends on the

Power Control (page 82)

CLKIN rate and the setting of
CLK25_DIVIDER.

TRANS_TIME_TO_P2_0

TRANS_TIME_TO_P2_1

TX_BUFFER_USE_0

TX_BUFFER_USE_1

TX_DIFF_BOOST_0

TX_DIFF_BOOST_1

TX_SYNC_FILTERB

Transition time to the P2 powerdown state
in internal 25 MHz clock cycles. The exact
time depends on the CLKIN rate and the
setting of CLK25_DIVIDER.

Indicates whether the TX buffer is used.

Changes the strength of the TX driver and
pre-emphasis buffers. When set to TRUE,
the pre-emphasis percentage is boosted or
increased. See Table 6-18, page 114 for
nominal differential swing and pre­emphasis values.

Overall differential swing is reduced when
TX_DIFF_BOOST is TRUE.

This parameter must be left at its default
value of 1.

Power Control (page 82)

TX Buffering, Phase Alignment,

and Buffer Bypass (page 105)

Configurable TX Driver

(page 113)

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UG196 (v1.3) May 25, 2007

Chapter 1: Introduction to the RocketIO GTP Transceiver

Table 1-4: GTP_DUAL Attribute Summary (Continued)

Attribute Description Section (Page)

Selects the clock used to drive the clock

TX_XCLK_SEL_0

TX_XCLK_SEL_1

domain in the PCS following the TX buffer.
Set to TXOUT (TXOUTCLK) when using
the TX buffer. Set to TXUSR (TXUSRCLK)
when bypassing the TX buffer.

R

TX Buffering, Phase Alignment,

and Buffer Bypass (page 105)

TXRX_INVERT0

TXRX_INVERT1

Controls inverters that optimize the clock
paths within the GTP transceiver. When
bypassing the TX buffer, set to 00100.
Otherwise, set to 00000.

TX Buffering, Phase Alignment,

and Buffer Bypass (page 105)

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Chapter 2

RocketIO GTP Transceiver Wizard

The RocketIO GTP Transceiver Wizard is the preferred tool to generate a wrapper to
instantiate a GTP_DUAL primitive. The Wizard can be found in the Xilinx CORE
Generator tool. Be sure to download the most up-to-date IP Update before using the
Wizard. Details on how to use this wizard can be found in UG188
Transceiver Wizard User Guide.

1. Start the Xilinx CORE Generator tool.

2. Locate the RocketIO GTP Wizard in the taxonomy tree under:

/FPGA Features & Design/IO Interfaces

See Figure 2-1.

, RocketIO GTP

UG196_c2_01_100406

Figure 2-1: Locating the RocketIO GTP Wizard

3. Double click RocketIO GTP Wizard to launch the Wizard.

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Chapter 2: RocketIO GTP Transceiver Wizard

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Simulation

Overview

Simulations using GTP_DUAL tiles have specific prerequisites that the simulation
environment and the testbench must fulfill.

The Synthesis and Simulation Design Guide ([Ref 1]) explains how to set up the simulation
environment for supported simulators depending on the used Hardware Description
Language (HDL). This design guide can be downloaded from the Xilinx website at

http://www.xilinx.com/support/sw_manuals/xilinx

The prerequisites for simulating a design with GTP transceivers are:

• Simulator with a SWIFT interface to support SmartModels, which are encrypted

versions of the HDL used for implementation of the modeled block

• Installed SmartModel for GTP_DUAL

• Correct setting of the environment variable that points to the SmartModel installation

directory

• Correct setup of the simulator for SmartModel use (initialization file, environment

variable(s))

• Compilation of the SmartModel wrapper files into the UNISIM and SIMPRIM

libraries

• Compilation of the GTP_DUAL SmartModel into a simulation library

• Correct simulator resolution (Verilog)

• Correct compilation order of simulation libraries

Chapter 3

9/download/

The user guide of the simulator and the Synthesis and Simulation Design Guide provide a
detailed list of settings for SmartModel support. The compxlib tool with sl_admin
facilitates the setup of the supported simulator.

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Chapter 3: Simulation

Ports and Attributes

The GTP_DUAL primitive has attributes intended only for simulation. Ta bl e 3 -1 lists the

simulation-only attributes of the GTP_DUAL tile. The names of these attributes start with
SIM_.

Table 3-1: GTP_DUAL Simulation-Only Attributes

Attribute Description

This attribute shortens the time it takes to finish the GTPRESET sequence and
lock the shared PMA PLL during simulation.

TRUE: Shorten the GTPRESET cycle time (fast initialization is
approximately 300 ns). The value of SIM_PLL_PERDIV2 defines the PLL

SIM_GTPRESET_SPEEDUP

SIM_PLL_PERDIV2

frequency in this mode. Because SIM_PLL_PERDIV2 cannot be changed on
the fly during simulation, this mode cannot be used for multirate designs.

FALSE: The GTPRESET sequence is simulated with its original duration
(standard initialization is approximately 160 μs). This mode must be used
for multirate designs.

This attribute specifies a 9-bit hex value equal to half the period of the PLL
clock frequency in picoseconds [ps]. For example, 400 ps (decimal) is equal to
0x190 (hexadecimal), which is the default value.

If SIM_PLL_PERDIV2 is not set correctly, poor locking behavior and incorrect
clock frequencies will occur in simulation.

R

SIM_RECEIVER_DETECT_PASS0

SIM_RECEIVER_DETECT_PASS1

There are no simulation-only ports.

Description

The behavior of the GTP_DUAL tile is modeled using a SmartModel. The SmartModel
allows the design containing GTP_DUAL tiles to be simulated in the following design
phases:

• Register Transfer Level (RTL)/Pre-Synthesis Simulation

• Post-Synthesis Simulation/Pre-NGDBuild Simulation

• Post-NGDBuild/Pre-Map Simulation

• Post-Map/Partial Timing Simulation

• Post-Place and Route/Timing Simulation

Limitations

This attribute is used to simulate the TXDETECTRX feature in each GTP
transceiver.

TRUE (default): Simulates an RX connection to the TX serial ports.
TXDETECTRX reports that an RX port is connected.

FALSE: Simulates a disconnected TX port. TXDETECTRX will report that
the RX port is not detected.

The analog nature of some blocks inside the GTP_DUAL tile generates some restrictions
when simulated using an HDL simulator. Receiver detection and OOB/beacon signaling
are analog features of the GTP_DUAL tile that can only be modeled in a limited way with
an HDL simulator. The shared PMA PLL is another analog block in the GTP_DUAL that is

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difficult to model precisely. For this reason, several simulation-only attributes are provided
to work around these limitations.

SmartModel Attributes

SIM_GTPRESET_SPEEDUP

The SIM_GTPRESET_SPEEDUP attribute can be used to shorten the simulated lock time of
the shared PMA PLL.

If TXOUTCLK or RXRECCLK is used to generate clocks in the design, these clocks
occasionally flatline while the GTP_DUAL tile is locking. If a PLL or DCM is used to divide
TXOUTCLK or RXRECCLK, the final output clock is not ready until both the GTP_DUAL
tile and the PLL or DCM have locked. Equation 3-1 provides an estimate of the time
required before a stable source from TXOUTCLK or RXRECCLK is available in simulation,
including the time required for any PLLs or DCMs used.

Description

t

USRCLKstabletGTPRESETsequencetlocktimePLLtlocktimeDCM

If either the PLL or the DCM is not used, the respective term can be removed from the lock
time equation. When simulating multirate designs where the shared PMA PLL frequency
or REFCLK frequency change, SIM_GTPRESET_SPEEDUP must be set to FALSE.

Appendix F, “Advanced Clocking”illustrates multirate design examples.

++≅

Equation 3-1

SIM_PLL_PERDIV2

The GTP_DUAL tile contains an analog PLL to generate the transmit and receive clocks
out of a reference clock. Because HDL simulators do not fully model the analog PLL, the
GTP_DUAL Smartmodel includes an equivalent behavioral model to simulate the PLL
output. The SIM_PLL_PERDIV2 attribute is used by the behavioral model to generate the
PLL output as accurately as possible. It must be set to 1/2 the period of the shared PMA
PLL. See “Examples,” page 46 for how to calculate SIM_PLL_PERDIV2 for a given rate.

SIM_RECEIVER_DETECT_PASS

The GTP_DUAL includes a TXDETECTRX feature that allows the transmitter to detect
whether its serial ports are currently connected to a receiver by measuring rise time on the
TXP/TXN differential pin pair (see “PCI Express Receive Detect Support,” page 116).

The GTP_DUAL SmartModel includes an attribute for simulating TXDETECTRX called
SIM_RECEIVER_DETECT_PASS. This attribute allows TXDETECTRX to be simulated for
each GTP transceiver without modelling the measurement of rise time on the TXP/TXN
differential pin pair.

SIM_RECEIVER_DETECT_PASS should be set to TRUE by default. When TRUE, the
attribute models a connected receiver, and TXDETECTRX operations will indicate a
receiver is connected. To model a disconnected receiver, SIM_RECEIVER_DETECT_PASS
for the transceiver is set to FALSE.

Power-Up and Reset

Link Idle Reset

To simulate correctly, the Link Idle Reset circuit described in “Reset,” page 72 must be
implemented and connected to each GTP_DUAL instance. This circuit is included
automatically when the Wizard is used to configure the GTP_DUAL instance.

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Chapter 3: Simulation

Toggling GSR

Providing Clocks In Simulation

Simulating in Verilog

R

The GSR signal is a global routing of nets in the design that provide a means of setting or
resetting applicable components in the device during configuration.

The simulation behavior of this signal is modeled using the glbl module in Verilog and the
ROC/ROCBUF components in VHDL.

In simulation, the clocks inside the PMA are generated using the SIM_PERDIV2 parameter
(ps). Any other clocks driven into the user clock must have the same level of precision, or
TX buffer errors (and RX buffer errors in systems without clock correction) can result.
When generating USRCLK, USRCLK2, or reference clock signals in the testbench, the clock
periods must be related to SIM_PERDIV2 and also be a round number (ps). In some cases,
the simulation a clock rate is slightly different from the clock rate used in the actual design.

The GSR and global 3-state (GTS) signals are defined in the
$XILINX/verilog/src/glbl.v module. The glbl.v module connects the global
signals to the design, which is why it is necessary to compile this module with the other
design files and load it along with the design.v and testfixture.v files for
simulation.

Defining GSR/GTS in a Test Bench

There are two ways to handle GSR and GTS in a test bench:

1. In most cases, GSR and GTS do not need to be defined in the test bench. The glbl.v
file declares the GSR and GTS signals and automatically pulses GSR for 100 ns. This
handling is sufficient for back-end simulations and functional simulations as well.

2. If GSR or GTS needs to be emulated in the test bench, the following snippet of code
must be added to the testfixture.v file:

assign glbl.GSR = gsr_r;
assign glbl.GTS = gts_r;
initial
begin
gts_r = 1'b0;
gsr_r = 1'b1;
#(16*CLOCKPERIOD);
gsr_r = 1'b0;
end

Simulating in VHDL

The ROCBUF cell controls the emulated GSR signal in a test bench. This component creates
a buffer for the GSR signal and provides an input port on the buffer to drive GSR. This port
must be declared in the entity list and driven through the test bench.

The VHDL code for this cell, located in EX_ROCBUF.vhd, is listed below:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
library UNISIM;
use UNISIM.all;

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Description

entity EX_ROCBUF is
port (
CLOCK, ENABLE, SRP,RESET : in std_logic;
C_OUT: out std_logic_vector (3 downto 0)
);
end EX_ROCBUF;

architecture A of EX_ROCBUF is
signal GSR : std_logic;
signal COUNT : std_logic_vector (3 downto 0);
component ROCBUF
port (
I : in std_logic;
O : out std_logic
);
end component;

begin
U1 : ROCBUF port map (I => SRP, O => GSR);

//dummy process
COUNTER : process (CLOCK, ENABLE, RESET)
begin
………………………………
………………………………
end process COUNTER;
end A

The VHDL code for this test bench, located in EX_ROCBUF_tb.vhd, is listed below:

entity EX_ROCBUF_tb is
end EX_ROCBUF_tb;
architecture behavior of EX_ROCBUF_tb is
declare component EX_ROCBUF
declare signals
begin
EX_ROCBUF_inst: EX_ROCBUF PORT MAP(
CLOCK => CLOCK,
ENABLE => ENABLE,
SRP => SRP,
RESET => RESET,
COUT => COUT
);
Clk_generation: process
Begin
………………………
End process
reset <= '1', '0' after CLK_PERIOD * 30;
SRP <= '1', '0' after CLK_PERIOD * 25;
end

Further details can be found in the Synthesis and Simulation Design Guide, which can be
downloaded from the Xilinx website at

http://www.xilinx.com/support/sw_manuals/xilinx

9/download/

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Chapter 3: Simulation

Examples

Simulation Environment Setup Example (ModelSim SE 6.1d on Linux)

This section provides an example how to set up a simulation environment for SmartModel
support. This is a prerequisite for simulating designs containing GTP_DUAL tile(s).

This example uses ModelSim SE 6.1d, the HDL simulator from Mentor Graphics, with
RedHat Enterprise Linux 3.0 as the operating system and version 8.1i of the Xilinx ISE
Development System. The Synthesis and Simulation Guide provides guidelines and
examples for a different HDL simulator or Xilinx ISE development system

(1)

.

Use setenv to set the following environment variables:

• XILINX Location of the installed Xilinx ISE system (for example,

/opt/Xilinx/ise_8_1_i)

• MODEL_TECH Location of the installed ModelSim simulator (for example,

/edatools/mentor/modelsim/6.1d/)

• LMC_HOME $XILINX/smartmodel/lin/installed_lin

• LMC_CONFIG $LMC_HOME/data/linux.lmc

R

• LD_LIBRARY_PATH $LMC_HOME/lib/linux.lib:$LD_LIBRARY_PATH

The initialization file (Modelsim.ini) contains the following settings:

libsm = $MODEL_TECH/libsm.sl
libswift = $LMC_HOME/lib/linux.lib/libswift.so
Resolution = 1ps ;(one picosecond simulator resolution)

The location of SmartModel in the ISE directory tree is:

$XILINX/virtex5/smartmodel/lin/image

The selected options for the COMPXLIB tool are:

compxlib -s mti_se -l all –arch all -smartmodel_setup

These options use the compxlib tool to compile all libraries for all languages for the
ModelSim SE 6.1d HDL simulator. The default output directory is
$XILINX/language/target_simulator. The compiled libraries are specified to be
written to $XILINX/vhdl/mti_se and $XILINX/verilog/mti_se.

SIM_PLL_PERDIV2 Calculation Example

This section provides examples of how to calculate the correct value for the simulation­only attribute SIM_PLL_PERDIV2.

1. If there is a contradiction between this example and the documentation of your simulator, the simulator

documentation has precedence. If a newer version of the Xilinx ISE development system is used, check the
Xilinx website for additional information.

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Examples

The period of the PLL can be calculated using Equation 3-2 and Equation 3-3.

REFCLK

⎛⎞

PLL SPEED

---------------------------------------

⎝⎠

PLL_DIV_REF

DIV× PLL_DIVSEL_FB()×=

Equation 3-2

SIM_PLL_PERDIV2

1 PLL SPEED⁄()

-------------------------------------------=

2

Equation 3-3

The terms used in Equation 3-2 and Equation 3-3 are defined as follows:

• REFCLK is the speed of the clock tied to the CLKIN input of the GTP_DUAL tile in
MHz.

• PLL_DIVSEL_REF is an attribute that defines the dividing factor of the reference clock
divider of the shared PLL.

• PLL_DIVSEL_FB is an attribute that defines the dividing factor of the feedback
divider (which acts like a multiplication factor) of the shared PLL.

• DIV = 5 w hen INTDATAWIDTH = 1 (10-bit mode)

• DIV = 4 w hen INTDATAWIDTH = 0 (8-bit mode)

PCI Express Example

To calculate PLL SPEED and SIM_PLL_PERDIV2 for the PCI Express example, the
following values are assigned:

• REFCLK = 100 MHz

• PLL_DIVSEL_REF = 2

• DIV = 5

• PLL_DIVSEL_FB = 5

Using Equation 3-2, PLL SPEED is 1.25 GHz, meaning that the period is 800 ps. Using

Equation 3-3, SIM_PLL_PERDIV2 is 800 divided by 2 equal to 400 decimal or 190

hexadecimal.

Gigabit Ethernet Example

To calculate PLL SPEED and SIM_PLL_PERDIV2 for the Gigabit Ethernet example, the
following values are assigned:

• REFCLK = 125 MHz

• PLL_DIVSEL_REF = 1

• DIV = 5

• PLL_DIVSEL_FB = 2

Using Equation 3-2, PLL SPEED is 1.25 GHz, meaning that the period is 800 ps. Using

Equation 3-3, SIM_PLL_PERDIV2 is 800 divided by 2 or 400 decimal (190 hexadecimal).

XAUI Example

To calculate PLL SPEED and SIM_PLL_PERDIV2 for the XAUI example, the following
values are assigned:

• REFCLK = 156.25 MHz

• PLL_DIVSEL_REF = 1

• DIV = 5

• PLL_DIVSEL_FB = 2

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Chapter 3: Simulation

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Using Equation 3-2, PLL SPEED is 1.5625 GHz, meaning that the period is 640 ps. Using

Equation 3-3, SIM_PLL_PERDIV2 is 640 divided by 2 or 320 decimal (140 hexadecimal).

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Implementation

Overview

This chapter provides the information needed to map GTP_DUAL tiles instantiated in a
design to device resources, including:

• The location of the GTP_DUAL tiles on the available device and package
combinations.

• The pad numbers of external signals associated with each GTP_DUAL tile.

• How GTP_DUAL tiles and clocking resources instantiated in a design are mapped to

available locations with a user constraints file (UCF).

Chapter 4

It is a common practice to define the location of GTP transceivers early in the design
process to ensure correct usage of clock resources and to facilitate signal integrity analysis
during board design. The implementation flow facilitates this practice through the use of
location constraints in the UCF.

While this chapter describes how to instantiate GTP_DUAL clocking components, the
details of the different GTP_DUAL tile clocking options are discussed in “Clocking,” page

68.

Ports and Attributes

Tab le 4- 1 shows the external ports associated with each GTP_DUAL tile.

Table 4-1: GTP_DUAL Tile External Ports

MGTTXP0

MGTTXN0

MGTTXP1

MGTTXN1

MGTRXP0

MGTRXN0

MGTRXP1

MGTRXN1

Port Dir Domain Description

Out

In

Embedded

TX Clock

Embedded

RX Clock

Differential transmit data pairs for
GTP transceivers 0 and 1

Differential receive data pairs for GTP
transceivers 0 and 1

MGTREFCLKP

MGTREFCLKN

MGTAVCCPLL

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(2)

In N/A Differential reference clock input pair

Analog Analog Pad for 1.2V supply for PLL

Chapter 4: Implementation

Table 4-1: GTP_DUAL Tile External Ports (Continued)

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Port Dir Domain Description

Description

MGTAVCC

MGTAVTTRX

MGTAVTTTX

Notes:

1. These port names have the prefix MGT to identify them easily in a pad file that is very often used to

create symbols for board design schematics. In this document, the MGT prefix was removed from
those names; however, names with and without the MGT prefix are synonymous to each other.

2. Nominal values. Refer to DS202: Virtex-5 Data Sheet for exact values and marginal conditions.

(2)

(2)

(2)

Analog Analog

Analog Analog Pad for 1.2V supply for RX circuitry

Analog Analog

Two pads for 1.0V supply for
transceiver mixed signal circuitry

Two pads for 1.2V supply for TX
circuitry

There are no attributes for this section.

The position of GTP_DUAL tiles is specified by an XY coordinate system that describes the
column number and its relative position within that column. In current members of the
Virtex-5 LXT and SXT Platforms, all GTP_DUAL tiles are located in a single column along
one side of the die. As a result the X coordinate for all of the GTP_DUAL tiles is 0. “Package

Placement Information,” page 52 lists the GTP_DUAL tile position information for all

available device and package combinations along with the pad numbers for the external
signals associated with each tile.

There are two ways to create a UCF for designs that utilize GTP_DUAL tiles. The preferred
method is by using the RocketIO GTP Wizard. The Wizard (see Chapter 2, “RocketIO GTP

Transceiver Wizard”) automatically generates UCF templates that configure the

transceivers and contain placeholders for GTP_DUAL placement information. The UCFs
generated by the Wizard can then be edited to customize operating parameters and
placement information for the application.

The second approach is to create the UCF by hand. When using this approach, the designer
must enter both configuration attributes that control transceiver operation as well as tile
location parameters. Care must be taken to ensure that all of the parameters needed to
configure the GTP_DUAL tile are correctly entered.

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Example of a UCF for GTP_DUAL Placement

Example of a UCF for GTP_DUAL Placement

This section shows key elements of a UCF that instantiates seven GTP_DUAL tiles. The file
implements the example configuration shown in Figure 5-5, page 71. The device and
package combination chosen in this example is an XC5VLX110T-FF1136.

;
; Instantiate the GTP_DUAL tiles in locations X0Y7 to X0Y1
;
INST design_root/gtp_dual[1]/gtp_dual LOC=GTP_DUAL_X0Y1;
INST design_root/gtp_dual[2]/gtp_dual LOC=GTP_DUAL_X0Y2;
INST design_root/gtp_dual[3]/gtp_dual LOC=GTP_DUAL_X0Y3;
INST design_root/gtp_dual[4]/gtp_dual LOC=GTP_DUAL_X0Y4;
INST design_root/gtp_dual[5]/gtp_dual LOC=GTP_DUAL_X0Y5;
INST design_root/gtp_dual[6]/gtp_dual LOC=GTP_DUAL_X0Y6;
INST design_root/gtp_dual[7]/gtp_dual LOC=GTP_DUAL_X0Y7;
;
; Connect the REFCLK_PAD_(N/P) differential pair to the middle
; GTP_DUAL tile (GTP_DUAL_X0Y4)
;
NET refclk_pad_n LOC=P4;
NET refclk_pad_p LOC=P3;

The instantiation of the GTP_DUAL tiles and the IBUFDS primitive is typically done in
HDL code within the design hierarchy. That code also connects the output of the IBUFDS
primitive to the CLKIN inputs of the GTP_DUAL tiles, as illustrated by the following
Verilog code fragment:

//
// Instantiate the GTP_DUAL tiles
//
genvar tile_num;

generate for (tile_num = 1; tile_num <= 7; ++tile_num)

begin: gtp_dual

GTP_DUAL gtp_dual
(

.CLKIN(refclk),

… The remaining GTP_DUAL ports are not shown

)

end

endgenerate

//
// Instantiate the IBUFDS for the reference clock
//
IBUFDS ref_clk_buffer
(

.IN(refclk_pad_n),
.IP(refclk_pad_p),
.O(refclk)

)

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Chapter 4: Implementation

Package Placement Information

The diagrams in this section illustrate GTP_DUAL placement for the following packages:

• LXT packages:

♦ XC5VLX30T-FF665
♦ XC5VLX50T-FF665
♦ XC5VLX50T-FF1136
♦ XC5VLX85T-FF1136
♦ XC5VLX110T-FF1136
♦ XC5VLX110T-FF1738
♦ XC5VLX220T-FF1738
♦ XC5VLX330T-FF1738

• SXT packages:

♦ XC5VSX35T-FF665
♦ XC5VSX50T-FF665
♦ XC5VSX50T-FF1136
♦ XC5VSX95T-FF1136

R

Figure 4-1 illustrates the nomenclature used in each of these diagrams. The GTP_DUAL

placement name is the name used in the UCF to map GTP_DUAL tiles instantiated in the
design to specific tiles on the device. The board-level pin names and numbers are the
names placed in the PKG file generated by the ISE design flow. This file is typically used by
board-level schematic capture and layout tools to create component symbols and layout
footprints.

GTP_DUAL

Placement Name

GTP_DUAL_X0Y3

D3

C1
D1

F2

B2
C2

MGTREFCLKP_116
MGTREFCLKN_116

MGTRXP1_116
MGTRXN1_116

MGTRXP0_116
MGTRXN0_116

MGTTXP1_116
MGTTXN1_116

MGTTXP0_116
MGTTXN0_116

Board-Level

Pin Names

F3D4

E3F1
E4E1

C3

B3G2
G3

MGTAVCCPLL_116

MGTAVCC_116
MGTAVCC_116

MGTAVTTRX_116

MGTAVTTTX_116
MGTAVTTTX_116

Board-Level

Pin Numbers

UG196_c4_01_102006

Figure 4-1: Placement Diagram Nomenclature

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Package Placement Information

Right Edge of the Die

XC5VLX30T: GTP_DUAL_X0Y3
XC5VLX50T: GTP_DUAL_X0Y4

VSX35T: GTP_DUAL_X0Y3

XC5
XC5VSX50T: GTP_DUAL_X0Y3

XC5VLX30T: GTP_DUAL_X0Y2
XC5VLX50T: GTP_DUAL_X0Y3
XC5VSX35T: GTP_DUAL_X0Y2
XC5VSX50T: GTP_DUAL_X0Y2

D3

C1
D1

F2

B2
C2

K3

J1

K1

M2

H2

J2

MGTREFCLKP_116
MGTREFCLKN_116

MGTRXP1_116
MGTRXN1_116

MGTRXP0_116
MGTRXN0_116

MGTTXP1_116
MGTTXN1_116

MGTTXP0_116
MGTTXN0_116

MGTREFCLKP_112
MGTREFCLKN_112

MGTRXP1_112
MGTRXN1_112

MGTRXP0_112
MGTRXN

0_112

MGTTXP1_112
MGTTXN1_112

MGTTXP0_112

MGTTXN0_112

Power Pins

MGTAVCCPLL_116

F3D4

MGTAVCC_116

E3F1
E4E1

MGTAVCC_116

MGTAVTTRX_116

C3

MGTAVTTTX_116

B3G2

MGTAVTTTX_116

G3

MGTAVCCPLL_112

M3K4

MGTAVCC_112

L3M1

MGTAVCC_112

L4L1

MGTAVTTRX_112

J3

MGTAVTTTX_112

H3N2

MGTAVTTTX_112

N3

MGTAVCCPLL_114

V3T4

MGTAVCC_114

U3V1

MGTAVCC_114

U4U1

MGTAVTTRX_114

R3R1

MGTAVTTTX_114

P3W2
W3V2

MGTAVTTTX_114

AD3AB4

MGTAVCCPLL_118

AC3AD1

MGTAVCC_118

AC4AC1

MGTAVCC_118

AA3AA1

MGTAVTTRX_118

AE3AE2

MGTAVTTTX_118
MGTAVTTTX_118

Y3AD2

UG196_c4_02_012007

XC5VLX30T: GTP_DUAL_X0Y1
XC5VLX50T: GTP_DUAL_X0Y2
XC5VSX35T: GTP_DUAL_X0Y1
XC5VSX50T: GTP_DUAL_X0Y1

XC5VLX30T: GTP_DUAL_X0Y0
XC5VLX50T: GTP_DUAL_X0Y1
XC5VSX35T: GTP_DUAL_X0Y0
XC5VSX50T: GTP_DUAL_X0Y0

T3

T1

P2
R2

AB3

AB1

Y2

AA2

MGTREFCLKP_114
MGTREFCLKN_114

MGTRXP1_114
MGTRXN1_114

MGTRXP0_114
MGTRXN0_114

MGTTXP1_114
MGTTXN1_114

MGTTXP0_114

MGTTXN0_114

MGTREFCLKP_118
MGTREFCLKN_118

MGTRXP1_118

MGTRXN1_118

MGTRXP0_118

MGTRXN0_118

MGTTXP1_118

MGTTXN1_118

MGTTXP0_118

MGTTXN0_118

Figure 4-2: XC5VLX30T-FF665, XC5VLX50T-FF665, XC5VSX35T-FF665, and XC5VSX50T-FF665 GTP Placement

Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com 53

UG196 (v1.3) May 25, 2007

Chapter 4: Implementation

XC5VLX50T: Not Available
XC5VLX85T: Not Available
XC5VLX110T: GTP_DUAL_X0Y7
XC5VSX50T: Not Available
XC5VSX95T: GTP_DUAL_X0Y7

XC5VLX50T: GTP_DUAL_X0Y5
XC5VLX85T: GTP_DUAL_X0Y5
XC5VLX110T: GTP_DUAL_X0Y6
XC5VSX50T: GTP_DUAL_X0Y5
XC5VSX95T: GTP_DUAL_X0Y6

C8 MGTREFCLKN_124

A6 MGTRXP1_124
A7 MGTRXN1_124

A8 MGTRXN0_124

B5 MGTTXP1_124
B6 MGTTXN1_124

B10 MGTTXP0_124
B9 MGTTXN0_124

D4 MGTREFCLKN_120

D1 MGTRXP1_120
C1 MGTRXN1_120

A2 MGTRXN0_120

E2 MGTTXP1_120
D2 MGTTXN1_120

B4 MGTTXP0_120
B3 MGTTXN0_120

R

Power PinsRight Edge of the Die

C6 MGTAVCCPLL_124D8 MGTREFCLKP_124

C7 MGTAVCC_124
D7 MGTAVCC_124

C9 MGTAVTTRX_124A9 MGTRXP0_124

C10 MGTAVTTTX_124
C5 MGTAVTTTX_124

D3 MGTAVCCPLL_120E4 MGTREFCLKP_120

D5 MGTAVCC_120
F4 MGTAVCC_120

C3 MGTAVTTRX_120A3 MGTRXP0_120

C4 MGTAVTTTX_120
E3 MGTAVTTTX_120

K3 MGTAVCCPLL_116H4 MGTREFCLKP_116

H3 MGTREFCLKN_116

J3 MGTAVCC_116
J4 MGTAVCC_116

G3 MGTAVTTRX_116G1 MGTRXP0_116

F3 MGTAVTTTX_116
L3 MGTAVTTTX_116

XC5VLX50T: GTP_DUAL_X0Y4
XC5VLX85T: GTP_DUAL_X0Y4
XC5VLX110T: GTP_DUAL_X0Y5
XC5VSX50T: GTP_DUAL_X0Y4
XC5VSX95T: GTP_DUAL_X0Y5

K1 MGTRXP1_116
J1 MGTRXN1_116

H1 MGTRXN0_116

L2 MGTTXP1_116
K2 MGTTXN1_116

F2 MGTTXP0_116
G2 MGTTXN0_116

T3 MGTAVCCPLL_112P4 MGTREFCLKP_112

P3 MGTREFCLKN_112

R3 MGTAVCC_112
R4 MGTAVCC_112

N3MGTAVTTRX_112N1 MGTRXP0_112

U3 MGTAVTTTX_112
M3 MGTAVTTTX_112

XC5VLX50T: GTP_DUAL_X0Y3
XC5VLX85T: GTP_DUAL_X0Y3
XC5VLX110T: GTP_DUAL_X0Y4
XC5VSX50T: GTP_DUAL_X0Y3
XC5VSX95T: GTP_DUAL_X0Y4

T1 MGTRXP1_112
R1 MGTRXN1_112

P1 MGTRXN

0_112

U2 MGTTXP1_112
T2 MGTTXN1_112

M2 MGTTXP0_112
N2 MGTTXN0_112

UG196_c4_03_012007

Figure 4-3: XC5VLX50T-FF1136, XC5VLX85T-FF1136, XC5VLX110T-FF1136, XC5VSX50T-FF1136, and XC5VSX95T-FF1136 GTP Placement (1 of 2)

54 www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide

UG196 (v1.3) May 25, 2007

R

XC5VLX50T: GTP_DUAL_X0Y2
XC5VLX85T: GTP_DUAL_X0Y2
XC5VLX110T: GTP_DUAL_X0Y3
XC5VSX50T: GTP_DUAL_X0Y2
XC5VSX95T: GTP_DUAL_X0Y3

XC5VLX50T: GTP_DUAL_X0Y1
XC5VLX85T: GTP_DUAL_X0Y1
XC5VLX110T: GTP_DUAL_X0Y2
XC5VSX50T: GTP_DUAL_X0Y1
XC5VSX95T: GTP_DUAL_X0Y2

Y3 MGTREFCLKN_114

AB1 MGTRXP1_114
AA1 MGTRXN1_114

Y1 MGTRXN0_114

AC2 MGTTXP1_114
AB2 MGTTXN1_114

V2 MGTTXP0_114
W2 MGTTXN0_114

AF3 MGTREFCLKN_118

AH1 MGTRXP1_118
AG1 MGTRXN1_118

AF1 MGTRXN0_118

AJ2 MGTTXP1_118
AH2 MGTTXN1_118

AD2 MGTTXP0_118
AE2 MGTTXN0_118

Package Placement Information

Power PinsRight Edge of the Die

AB3 MGTAVCCPLL_114Y4 MGTREFCLKP_114

AA3 MGTAVCC_114
AA4 MGTAVCC_114

W3MGTAVTTRX_114W1 MGTRXP0_114

AC3 MGTAVTTTX_114
V3MGTAVTTTX_114

AH3 MGTAVCCPLL_118AF4 MGTREFCLKP_118

AG3 MGTAVCC_118
AG4 MGTAVCC_118

AE3 MGTAVTTRX_118AE1 MGTRXP0_118

AD3 MGTAVTTTX_118
AJ3 MGTAVTTTX_118

AM4 MGTAVCCPLL_122AL5 MGTREFCLKP_122

AL4 MGTREFCLKN_122

AJ4 MGTAVCC_122
AK5 MGTAVCC_122

AL3 MGTAVTTRX_122AL1 MGTRXP0_122

AK3 MGTAVTTTX_122
AM3 MGTAVTTTX_122

VLX50T: GTP_DUAL_X0Y0

XC5
XC5VLX85T: GTP_DUAL_X0Y0
XC5VLX110T: GTP_DUAL_X0Y1
XC5VSX50T: GTP_DUAL_X0Y0
XC5VSX95T: GTP_DUAL_X0Y1

AP3 MGTRXP1_122
AP2 MGTRXN1_122

AM1 MGTRXN0_122

AN4 MGTTXP1_122
AN3 MGTTXN1_122

AK2 MGTTXP0_122
AL2 MGTTXN0_122

AM9 MGTAVCCPLL_126AL7 MGTREFCLKP_126

AM7 MGTREFCLKN_126

AL8 MGTAVCC_126
AM8 MGTAVCC_126

AM6 MGTAVTTRX_126AP6 MGTRXP0_126

AM10 MGTAVTTTX_126
AM5 MGTAVTTTX_126

XC5VLX50T: Not Available
XC5VLX85T: Not Available
XC5VLX110T: GTP_DUAL_X0Y0
XC5VSX50T: Not Available
XC5VSX95T: GTP_DUAL_X0Y0

AP9 MGTRXP1_126
AP8 MGTRXN

1_126

AP7 MGTRXN0_126

AN10 MGTTXP1_126
AN9 MGTTXN1_126

AN5 MGTTXP0_126
AN6 MGTTXN0_126

UG196_c4_04_012007

Figure 4-4: XC5VLX50T-FF1136, XC5VLX85T-FF1136, XC5VLX110T-FF1136, XC5VSX50T-FF1136, and XC5VSX95T-FF1136 GTP Placement (2 of 2)

Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com 55

UG196 (v1.3) May 25, 2007

Chapter 4: Implementation

XC5VLX110T: Not Available
XC5VLX220T: Not Available
XC5VLX330T: GTP_DUAL_X0Y11

XC5VLX110T: Not Available
XC5VLX220T: Not Available
XC5VLX330T: GTP_DUAL_X0Y10

C16 MGTREFCLKN_132

A14 MGTRXP1_132
A15 MGTRXN1_132

A16 MGTRXN0_132

B13 MGTTXP1_132
B14 MGTTXN1_132

B18 MGTTXP0_132
B17

MGTTXN0_132

C10 MGTREFCLKN_128

A8 MGTRXP1_128
A9 MGTRXN1_128

A10 MGTRXN0_128

B7 MGTTXP1_128
B8 MGTTXN1_128

B12 MGTTXP0_128
B11 MGTTXN0_128

Power PinsRight Edge of the Die

C14

MGTAVCCPLL_132D16 MGTREFCLKP_132

C15

MGTAVCC_132

D15

MGTAVCC_132

C17

MGTAVTTRX_132A17 MGTRXP0_132

C13

MGTAVTTTX_132

C18

MGTAVTTTX_132

C8

MGTAVCCPLL_128D10 MGTREFCLKP_128

C9

MGTAVCC_128

D9

MGTAVCC_128

C11

MGTAVTTRX_128A11 MGTRXP0_128

C12

MGTAVTTTX_128

C7

MGTAVTTTX_128

R

C2

MGTAVCCPLL_124MGTREFCLKP_124

D4

MGTAVCC_124

D5

MGTAVCC_124

C5

MGTAVTTRX_124MGTRXP0_124

C1

MGTAVTTTX_124

C6

MGTAVTTTX_124

H3

MGTAVCCPLL_120MGTREFCLKP_120

G3

MGTAVCC_120

G4

MGTAVCC_120

E3

MGTAVTTRX_120MGTRXP0_120

D3

MGTAVTTTX_120

J3

MGTAVTTTX_120

UG196_c4_05_110906

XC5VLX110T: GTP_DUAL_X0Y7
XC5VLX220T: GTP_DUAL_X0Y7
XC5VLX330T: GTP_DUAL_X0Y9

XC5VLX110T: GTP_DUAL_X0Y6
XC5VLX220T: GTP_DUAL_X0Y6
XC5VLX330T: GTP_DUAL_X0Y8

C4
C3

A2
A3

A5
A4

B1
B2

B6
B5

F4
F3

H1
G1

E1
F1

J2
H2

D2
E2

MGTREFCLKN_124

MGTRXP1_124
MGTRXN1_124

MGTRXN

0_124

MGTTXP1_124
MGTTXN1_124

MGTTXP0_124
MGTTXN0_124

MGTREFCLKN_120

MGTRXP1_120
MGTRXN1_120

MGTRXN0_120

MGTTXP1_120
MGTTXN1_120

MGTTXP0_120
MGTTXN0_120

Figure 4-5: XC5VLX110T-FF1738, XC5VLX220T-FF1738, and XC5VLX330T-FF1738 GTP Placement (1 of 3)

56 www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide

UG196 (v1.3) May 25, 2007

R

XC5VLX110T: GTP_DUAL_X0Y5
XC5VLX220T: GTP_DUAL_X0Y5
XC5VLX330T: GTP_DUAL_X0Y7

XC5VLX110T: GTP_DUAL_X0Y4
XC5VLX220T: GTP_DUAL_X0Y4
XC5VLX330T: GTP_DUAL_X0Y6

M3 MGTREFCLKN_116

P1 MGTRXP1_116
N1 MGTRXN1_116

M1 MGTRXN0_116

R2 MGTTXP1_116
P2 MGTTXN1_116

K2 MGTTXP0_116
L2 MGTTXN0_116

V3 MGTREFCLKN_112

Y1 MGTRXP1_112

W1 MGTRXN1_112

V1 MGTRXN

0_112

AA2 MGTTXP1_112
Y2 MGTTXN1_112

T2 MGTTXP0_112
U2 MGTTXN0_112

Package Placement Information

Power PinsRight Edge of the Die

P3 MGTAVCCPLL_116M4 MGTREFCLKP_116

N3MGTAVCC_116
N4MGTAVCC_116

L3 MGTAVTTRX_116L1 MGTRXP0_116

R3 MGTAVTTTX_116
K3 MGTAVTTTX_116

Y3 MGTAVCCPLL_112V4 MGTREFCLKP_112

W3MGTAVCC_112
W4MGTAVCC_112

U3 MGTAVTTRX_112U1 MGTRXP0_112

AA3 MGTAVTTTX_112
T3 MGTAVTTTX_112

AF3 MGTAVCCPLL_114AD4 MGTREFCLKP_114

AD3 MGTREFCLKN_114

AE3 MGTAVCC_114
AE4 MGTAVCC_114

AC3 MGTAVTTRX_114AC1 MGTRXP0_114

AB3 MGTAVTTTX_114
AG3 MGTAVTTTX_114

XC5VLX110T: GTP_DUAL_X0Y3
XC5VLX220T: GTP_DUAL_X0Y3
XC5VLX330T: GTP_DUAL_X0Y5

AF1 MGTRXP1_114
AE1 MGTRXN1_114

AD1 MGTRXN0_114

AG2 MGTTXP1_114
AF2 MGTTXN1_114

AB2 MGTTXP0_114
AC2 MGTTXN0_114

AM3 MGTAVCCPLL_118AK4 MGTREFCLKP_118

AK3 MGTREFCLKN_118

AL3 MGTAVCC_118
AL4 MGTAVCC_118

AJ3 MGTAVTTRX_118AJ1 MGTRXP0_118

AH3 MGTAVTTTX_118
AN3MGTAVTTTX_118

XC5VLX110T: GTP_DUAL_X0Y2
XC5VLX220T: GTP_DUAL_X0Y2
XC5VLX330T: GTP_DUAL_X0Y4

AM1 MGTRXP1_118
AL1 MGTRXN1_118

AK1 MGTRXN0_118

AN2 MGTTXP1_118
AM2 MGTTXN1_118

AH2 MGTTXP0_118
AJ2 MGTTXN0_118

UG196_c4_06_110906

Figure 4-6: XC5VLX110T-FF1738, XC5VLX220T-FF1738, and XC5VLX330T-FF1738 GTP Placement (2 of 3)

Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com 57

UG196 (v1.3) May 25, 2007

Chapter 4: Implementation

XC5VLX110T: GTP_DUAL_X0Y1
XC5VLX220T: GTP_DUAL_X0Y1
XC5VLX330T: GTP_DUAL_X0Y3

XC5VLX110T: GTP_DUAL_X0Y0
XC5VLX220T: GTP_DUAL_X0Y0
XC5VLX330T: GTP_DUAL_X0Y2

AT3 MGTREFCLKN_122

AV1 MGTRXP1_122
AU1 MGTRXN1_122

AT1 MGTRXN0_122

AW2 MGTTXP1_122
AV2 MGTTXN1_122

AP2 MGTTXP0_122
AR2 MGTTXN0_122

AY4 MGTREFCLKN_126

BB5 MGTRXP1_126
BB4 MGTRXN1_126

BB3 MGTRXN0_126

BA6 MGTTXP1_126
BA5 MGTTXN1_126

BA1 MGTTXP0_126
BA2 MGTTXN0_126

Power PinsRight Edge of the Die

AV3MGTAVCCPLL_122AT4 MGTREFCLKP_122

AU3 MGTAVCC_122
AU4 MGTAVCC_122

AR3 MGTAVTTRX_122AR1 MGTRXP0_122

AP3 MGTAVTTTX_122
AW3MGTAVTTTX_122

AY 5 M GTAVCCPLL_126AW4 MGTREFCLKP_126

AW5MGTAVCC_126
AY 3 M GTA

VCC_126

AY 2 M GTAVTTRX_126BB2 MGTRXP0_126

AY 1 M GTAVTTTX_126
AY 6 M GTAVTTTX_126

R

AY 11 M GTAVCCPLL_130AW9 MGTREFCLKP_130

AY9 MGTREFCLKN_130

AY 10 M GTAVCC_130
AW10 MGTAVCC_130

AY 8 M GTAVTTRX_130BB8 MGTRXP0_130

AY 12 M GTAVTTTX_130
AY 7 M GTAVTTTX_130

XC5VLX110T: Not Available
XC5VLX220T: Not Available
XC5VLX330T: GTP_DUAL_X0Y1

BB11 MGTRXP1_130
BB10 MGTRXN1_130

BB9 MGTRXN0_130

BA12 MGTTXP1_130
BA11 MGTTXN1_130

BA7 MGTTXP0_130
BA8 MGTTXN0_130

W15 MGTREFCLKP_134

AY 17 M GTAVCCPLL_134A

AY15 MGTREFCLKN_134

AY 16 M GTAVCC_134
AW16 MGTAVCC_134

AY 14 M GTAVTTRX_134BB14 MGTRXP0_134

AY 13 M GTAVTTTX_134
AY 18 M GTAVTTTX_134

XC5VLX110T: Not Available
XC5VLX220T: Not Available
XC5VLX330T: GTP_DUAL_X0Y0

BB17 MGTRXP1_134
BB16 MGTRXN1_134

BB15 MGTRXN0_134

BA18 MGTTXP1_134
BA17 MGTTXN1_134

BA13 MGTTXP0_134
BA14 MGTTXN0_134

UG196_c4_07_110906

Figure 4-7: XC5VLX110T-FF1738, XC5VLX220T-FF1738, and XC5VLX330T-FF1738 GTP Placement (3 of 3)

58 www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide

UG196 (v1.3) May 25, 2007

R

Tile Features

Tile Features Overview

To minimize power consumption and area, many important GTP functions are shared
between two transceivers. These functions include the generation of a high-speed serial
clock, resets, power control, and dynamic reconfiguration.

Correct clocking and reset behavior is critical for any GTP transceiver design. This chapter
describes the following steps that must be performed when configuring the GTP_DUAL
tile:

• Set the shared PLL rate

• Set the reference clock source

• Implement the Link Idle Reset circuit

Chapter 5

These steps are performed automatically when the Wizard is used to configure the
GTP_DUAL tile.

Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com 59

UG196 (v1.3) May 25, 2007

Chapter 5: Tile Features

Shared PMA PLL

Overview

This section describes the shared PMA PLL of the GTP_DUAL tile, which is illustrated in

Figure 5-1. Each GTP_DUAL tile includes one shared PMA PLL used to generate a high-

speed serial clock from a high-quality reference clock (CLKIN). The high-speed clock from
this block drives the TX and RX PMA blocks for both GTP transceivers in the tile.

REFCLOCKOUT

GTP0 RX Serial Clock

(1)

x2

Divide

by

Divide

by

Divide

by

(4)

= [1,2,4]

CLKIN =

REFCLOCK

Shared PLL

PLLRESET
PLLPOWERDOWN
PLL_DIVSEL_FB
PLL_DIVSEL_REF = [1,2]
INTDATAWIDTH

(5)

= [1,2,3,4,5]

PLL_RXDIVSEL_OUT_0 = [1,2,4]

PLL

Clock

PLL_RXDIVSEL_OUT_1 = [1,2,4]

PLL_TXDIVSEL_COMM_OUT

Notes:

1. The Serial-In Parallel-Out (SIPO) block in each receiver uses both edges of the high-speed clock. As a result, the effective RX serial
clock rate is 2 x PLL Clock/PLL_RXDIVSEL_OUT_n.

2. The Parallel In Serial Out (PISO) block in each transmitter uses both edges of the high-speed clock. As a result, the effective TX
serial clock rate is 2 x PLL Clock/[PLL_TXDIVSEL_OUT_n, PLL_TXDIVSEL_COMM_OUT].

3. The parallel clock rate is divided to match the internal datapath width. When INTDATAWIDTH = 0 (8-bit internal width), W = 4.
When INTDATAWIDTH = 1 (10-bit internal width), W = 5.

4. Refer to Chapter 9, “Loopback,” about the correct setting of these attributes for specific loopback modes.

5. When INTDATAWIDTH = 0, PLL_DIVSEL_FB can only be set to 1, 2, or 4. For PLL_DIVSEL_FB = 1 set PCS_COM_CFG to
28’h1680A07, otherwise set to 28’h1680A0E (default).

x2

GTP0 RX Parallel Clock

(3)

/W

GTP1 RX Serial Clock

(1)

x2

GTP1 RX Parallel Clock

(3)

/W

Divide

PLL_TXDIVSEL_OUT_0

Divide

PLL_TXDIVSEL_OUT_1

GTP0 TX
Serial Clock

(2)

x2

by

(4)

= [1,2,4]

by

(4)

= [1,2,4]

GTP0 TX
Parallel Clock

(3)

/W

GTP1 TX
Serial Clock

(2)

x2

GTP1 TX
Parallel Clock

(3)

/W

UG196_c5_01_030307

R

Figure 5-1: Shared PMA PLL Detail

The shared PMA PLL generates the high-speed clock (PLL clock) used by both transceivers
in the GTP_DUAL tile. After the shared PMA PLL rate is set (PLL clock), the TX and RX
output dividers (dividers ending with _OUT) are set to determine the TX and RX line rates
for each transceiver.

Ports and Attributes

Tab le 5- 1 defines the shared PMA PLL ports.

60 www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide

UG196 (v1.3) May 25, 2007

R

Table 5-1: Shared PMA PLL Ports

Port Dir Domain Description

Shared PMA PLL

CLKIN In Async

Reference clock input to the shared PMA PLL. See “Clocking,” page 68 for
more information about the different ways this port can be driven.

Sets the internal datapath width for the GTP_DUAL. If set to 0, the internal

INTDATAWIDTH In Async

datapath width is set to 8 bits. If set to 1, the internal datapath width is set to
10 bits.

This port indicates that the VCO rate is within acceptable tolerances of the

PLLLKDET Out Async

desired rate when High. Neither GTP transceiver in the tile operates reliably
until this condition is met.

PLLLKDETEN In Async This port enables the PLL lock detector and should always be tied High.

The REFCLKOUT port from each GTP_DUAL tile provides direct access to

REFCLKOUT Out Async

the reference clock provided to the shared PLL (CLKIN). It can be routed for
use in the FPGA logic.

Tab le 5- 2 defines the shared PMA PLL attributes.

Table 5-2: Shared PMA PLL Attributes

Attribute Description

PCS_COM_CFG[27:0]

(1

For PLL_DIVSEL_FB = 1, set PCS_COM_CFG to 28’h1680A07, otherwise set to
28’h1680A0E (default).

Controls the feedback divider. Valid settings for PLL_DIVSEL_FB are 1, 2, 3, 4, and 5.
PLL_DIVSEL_FB is multiplied by 4 or 5, depending on the width of the internal

PLL_DIVSEL_FB

datapath as set by INTDATAWIDTH. If INTDATAWIDTH is Low, the feedback
divider N is set to PLL_DIVSEL_FB x 4. If INTDATAWIDTH is High, the feedback
divider N is set to PLL_DIVSEL_FB x 5.

PLL_DIVSEL_REF Controls the reference clock divider. Valid settings for PLL_DIVSEL_REF are 1 and 2.

Divides the PLL clock to produce a high-speed RX clock. Because both edges of the

PLL_RXDIVSEL_OUT_0

PLL_RXDIVSEL_OUT_1

clock are used, the divided clock must run at 1/2 the desired RX line rate. Permitted
divider settings are 1, 2, and 4. See “Serial In to Parallel Out (SIPO),” page 141 for
details.

Divides the PLL clock to produce a high-speed TX clock. Because both edges of the
clock are used, the divided clock must run at 1/2 the desired TX line rate. Permitted

PLL_TXDIVSEL_COMM_OUT

divider settings are 1, 2, and 4. This divider provides a clock to both GTP transceivers
and should be used when the same divider value is needed for both. When
PLL_TXDIVSEL_COMM_OUT is used, both PLL_TXDIVSEL_OUT attributes must
be set to 1. See “Parallel In to Serial Out (PISO),” page 110 for details.

Divides the PLL clock to produce a high-speed TX clock. Because both edges of the
clock are used, the divided clock must run at 1/2 the desired TX line rate. Permitted

PLL_TXDIVSEL_OUT_0

PLL_TXDIVSEL_OUT_1

divider settings are 1, 2, and 4. Each GTP transceiver has its own
PLL_TXDIVSEL_OUT. If the transceivers require different dividers, these attributes
must be used instead of PLL_TXDIVSEL_COMM_OUT, and
PLL_TXDIVSEL_COMM_OUT must be set to 1. See “Parallel In to Serial Out

(PISO),” page 110 for details.

Notes:

1. In ISE 9.2i and above, this attribute is included in the GTP_DUAL instance. Older ISE versions require setting this attribute with the
a user-constraints file (UCF) when a non-default value is needed.

Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com 61

UG196 (v1.3) May 25, 2007

Chapter 5: Tile Features

f

Description

R

The first step to using the GTP_DUAL tile is to set the output of the shared PLL (PLL clock)
to a rate that can be used by each G TP transceiver to generate an appropriate serial li ne rate
and corresponding parallel clock rate. Both GTP TX and RX blocks are equipped with an
independent divider that can divide the PLL clock by a factor of 1, 2, or 4. This divider
allows the TX and RX blocks of each GTP transceiver to run at different rates, related by an
integer multiple.

The PLL clock rate must be set to one-half the required line rate before the independent
dividers. For example, if an RX line rate of 2.5 Gb/s is desired in GTP0, and the
independent divider in the GTP RX block is set to 1, the PLL clock should be set to

1.25 GHz.

The shared PMA PLL has a nominal operation range. The Virtex-5 Data Sheet specifies the
operating range of the shared PLL including the marginal conditions. Set the PLL clock
must be within this operating range. Equation 5-1 shows how to set the PLL clock based on
CLKIN (the reference clock), PLL_DIVSEL_FB, PLL_DIVSEL_REF, and INTDATAWIDTH.
PLL_DIVSEL_FB and PLL_DIVSEL_REF control dividers inside the PLL.
INTDATAWIDTH controls the internal parallel data width of the entire GTP_DUAL tile.

Equation 5-1 shows how to set the rate of the PLL clock.

PLL ClockfCLKIN

----------------------------------------------------------------

×=

PLL_DIVSEL_REF

Equation 5-1

PLL_DIVSEL_FB DIV×

The following conditions apply to Equation 5-1:

• PLL_DIVSEL_REF = [1, 2]

• PLL_DIVSEL_FB = [1, 2, 3, 4, 5]; where 3 and 5 cannot be used when

INT DATAWIDTH = 0.

When PLL_DIVSEL_FB = 1, set PCS_COM_CFG to 28’h1680A07, otherwise set to
28

’h1680A0E (default)

• If INTDATAWIDTH = 1, DIV = 5, otherwise D I V = 4

• The PLL clock frequency range is as specified in the Virtex-5 Data Sheet

• The smallest possible divider values must be selected

The programmable dividers allow support for various standards.

Figure 5-2 shows a conceptual view of the shared PLL from which the PLL clock is

generated.

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Shared PMA PLL

REFCLKOUT

CLKIN

PLL_DIVSEL_REF

/[1,2]

Phase/

Frequency

Detector

Charge

Pump

Loop

Filter F(s)

VCO

(PFD)

PLL_DIVSEL_FB

/[1,2,3,4,5]

Note 1

DIV

/[4,5]

Notes:

1. Wh e n INTDATAW I DTH = 0, PLL_DIVSEL_FB can only be set to 1, 2, or 4.

Figure 5-2: Shared PLL Conceptual View

Tab le 5- 3 shows example settings for several standard protocols. The PLL clock frequency

values shown in Tab le 5 -3 are in the operation range of the shared PLL specified in the
Virtex-5 Data Sheet.

Table 5-3: Communication Standards

Standard

Line
Rate

[Gb/s]

TX/RX

USRCLK

Frequency

[MHz]

Reference

Clock

Frequency

REFCLK

[MHz]

PLL Clock

Frequency

[GHz]

Reference Clock

Divider Setting

PLL_DIVSEL_REF

Feedback Loop
Divider Setting

PLL_DIVSEL_FB

Divider Settings
PLL_RXDIVSEL_OUT_(0/1)
PLL_TXDIVSEL_OUT_(0/1)

PLL_TXDIVSEL_COMM_OUT

INTDATAWIDTH = 1 (10-bit internal datapath) → (DIV = 5)

FC2 2.125 212.5 212.5 1.0625 1 1 1

FC1 1.0625 106.25 106.25 1.0625 1 2 2

XAUI 3.125 312.5 156.25 1.5625 1 2 1

10G BASE-CX4 3.125 312.5 156.25 1.5625 1 2 1

GigE 1.25 125 125 1.25 1 2 2

3.125 312.5 156.25 1.5625 1 2 1

Aurora

Serial RapidIO

SATA II 3 300 150 1.5 1 2 1

SATA I 1.5 150 150 1.5 1 2 2

SAS II 3 300 150 1.5 1 2 1

SAS I 1.5 150 150 1.5 1 2 2

PCI Express 2.5 250 100 1.25 2 5 1

Infiniband 2.5 250 125 1.25 1 2 1

(4)

HD-SDI

2.5 250 125 1.25 1 2 1

1.25 125 125 1.25 1 2 2

3.125 312.5 156.25 1.5625 1 2 1

2.5 250 125 1.25 1 2 1

1.25 125 125 1.25 1 2 2

1.485 148.5 148.5 1.485 2 4 2

PLL Clock

UG196_c5_02_041907

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UG196 (v1.3) May 25, 2007

Chapter 5: Tile Features

Table 5-3: Communication Standards (Continued)

Reference

Clock

Frequency

REFCLK

[MHz]

PLL Clock

Frequency

[GHz]

Reference Clock

Divider Setting

PLL_DIVSEL_REF

Feedback Loop
Divider Setting

PLL_DIVSEL_FB

PLL_TXDIVSEL_COMM_OUT

Standard

(2)

CPRI

OBSAI

(3)

SFI-5

(3)

TFI-5

Line
Rate

[Gb/s]

2.4576 245.76 122.88 1.2288 1 2 1

1.2288 122.88 122.88 1.2288 1 2 2

0.6144 61.44 122.88 1.2288 1 2 4

(2)

1.536 153.6 153.6 1.536 1 2 2

0.768 76.8 153.6 1.536 1 2 4

3.125 312.5 156.25 1.5625 1 2 1

3.1104 311.04 155.52 1.5552 1 2 1

TX/RX

USRCLK

Frequency

[MHz]

INTDATAWIDTH = 0 (8-bit internal datapath) → (DIV = 4)

OC12 0.62208 77.76 155.52 1.24416 1 2 4

OC48 2.488 311.04 155.52 1.24416 1 2 1

(3)

SFI-5

SPI-5

TFI-5

(3)

(3)

2.488 311.04 155.52 1.24416 1 2 1

2.488 311.04 155.52 1.24416 1 2 1

2.488 311.04 155.52 1.24416 1 2 1

Divider Settings
PLL_RXDIVSEL_OUT_(0/1)
PLL_TXDIVSEL_OUT_(0/1)

R

(1)

Notes:

1. See “Parallel In to Serial Out (PISO),” page 110 and “Serial In to Parallel Out (SIPO),” page 141 for more details about the divider setting.

2. Synchronous system.

3. Maximum data rate.

4. Other frequency is 0.1% lower.

See “Clocking,” page 68 for details on supplying CLKIN to the shared PMA PLL.

Examples

Configuring the Shared PLL for XAUI

The three methods to configure the shared PLL for XAUI are described below:

1. Use the RocketIO GTP Wizard.

The wizard includes a protocol file for XAUI that allows it to automatically configure
the GTP_DUAL primitive for use in a XAUI design.

2. Use the settings from Ta bl e 5 -3 .

Tab le 5- 3 includes the settings for common configurations of popular protocols. XAUI

settings are included in Tab le 5 -3 , along with other protocols that use 8B/10B
encoding.

3. Use Equation 5-1 as described in the following steps:

a. Determine the required line rates.

For XAUI, both TX and RX use a line rate of 3.125 Gb/s.

b. Determine the internal datapath width.

Because XAUI is an 8B/10B-encoded standard, an internal datapath width of
10 bits is required. See “Configurable 8B/10B Encoder,” page 98 and

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Shared PMA PLL

“Configurable 8B/10B Decoder,” page 157 for more information about encoding

and internal datapath width requirements.

c. Determine the desired reference clock rate.

This example uses a reference clock running at 156.25 MHz, a common rate for
XAUI.

d. Calculate the required PLL clock rate.

Because the Serial-In Parallel-Out (SIPO) block uses both edges of the clock to
deserialize data, it must be fed a clock running at 3.125/2 = 1.5625 GHz. Because
this RX rate of 1.5625 GHz is within the PLL operation range, the external divider
(PLL_RXDIVSEL_OUT) must be one. The PLL clock rate is thus 1.5625 x 1 =

1.5625 GHz.

e. Calculate the required DIV value.

Because the internal datapath with must be 10 bits and INTDATAWIDTH = 1,
DIV = 5.

f. Calculate the required PLL divider ratio.

Using the values f

CLKIN

, DIV, and f

PLL_CLOCK

determined above, rearrange

Equation 5-1 to calculate the divider ratio as shown in Equation 5-2. The result is a

ratio of two.

PLL_DIVSEL_FB

-----------------------------------------------------

PLL_DIVSEL_REF

f

PLL_Clock

-----------------------------------

f

CLKIN

DIV×

1.565 GHz

-----------------------------------------

156.25 MHz 5×

2===

g. Select the PLL divider values.

Select the smallest divider values that result in the required PLL divider ratio. In
this case, using PLL_DIVSEL_FB = 2 and PLL_DIVSEL_REF = 1 results in a ratio
of two.

Configuring the Shared PLL for OC-48

This example shows how to set the shared PLL divider settings for OC-48 using

Equation 5-1. The RocketIO GTP Wizard and Tab le 5 -3 are simpler alternatives. This

example is provided only to illustrate the process with Equation 5-1.

Use Equation 5-1 as described in the following steps:

1. Determine the required line rates.

For OC-48, both TX and RX use a line rate of 2.488 Gb/s.

2. Determine the internal datapath width.

Because OC-48 uses no encoding and a datapath that is a multiple of eight bits, an
internal datapath width of eight bits is required.

3. Determine the desired reference clock rate.

This example uses a reference clock running at 155.5 MHz.

Equation 5-2

4. Calculate the required PLL clock rate.

Because the SIPO block uses both edges of the clock to deserialize data, it must be fed
a clock running at 2.488/2 = 1.244 GHz. Because this RX rate of 1.244 GHz is within the
operating range of the PLL, the external divider (PLL_RXDIVSEL_OUT) must be one.
The PLL clock rate is thus 1.244 x 1 = 1.244 GHz.

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Chapter 5: Tile Features

5. Calculate the required DIV value.

Because the internal datapath with must be eight bits and INTDATAWIDTH = 0,
DIV = 4.

6. Calculate the required PLL divider ratio

Using the values f

CLKIN

, DIV, and f

PLL_CLOCK

determined above, rearrange

Equation 5-1 to calculate the divider ratio as shown in Equation 5-3. The result is a

ratio of two.

R

PLL_DIVSEL_FB

-----------------------------------------------------

PLL_DIVSEL_REF

f

PLL_Clock

-----------------------------------

f

CLKIN

DIV×

1.244 GHz

--------------------------------------

155.5 MHz 4×

2===

Equation 5-3

7. Select the PLL divider values

Select the smallest divider values that result in the required PLL divider ratio. In this
case, using PLL_DIVSEL_FB = 2 and PLL_DIVSEL_REF = 1 results in a ratio of two.

Configuring the Shared PLL for Gigabit Ethernet

This example shows how to set the shared PLL divider settings for Gigabit Ethernet using

Equation 5-1. The RocketIO GTP Wizard and Tab le 5 -3 are simpler alternatives. This

example is provided only to illustrate the process with Equation 5-1.

Use Equation 5-1 as described in the following steps:

1. Determine the required line rates.

For Gigabit Ethernet, both TX and RX use a line rate of 1.25 Gb/s.

2. Determine the internal datapath width.

Because Gigabit Ethernet uses 8B/10B encoding, an internal datapath width of 10 bits
is required.

3. Determine the desired reference clock rate.

This example uses a reference clock running at 125 MHz.

4. Calculate the required PLL clock rate.

Because the SIPO block uses both edges of the clock to deserialize data, it must be fed
a clock running at 1.25/2 = 0.625 GHz. Because this RX rate of 0.625 GHz is below the
operating range of the PLL, the external divider (PLL_RXDIVSEL_OUT) must be two
to allow the PLL to run twice as fast (1.25 GHz). The PLL clock rate is thus 0.625 x 2 =

1.25 GHz.

5. Calculate the required DIV value.

Because the internal datapath with must be 10 bits and INTDATAWIDTH = 1, DIV = 5.

6. Calculate the required PLL divider ratio.

Using the values f

CLKIN

, DIV, and f

PLL_CLOCK

determined above, rearrange

Equation 5-1 to calculate the divider ratio as shown in Equation 5-4. The result is a

ratio of two.

f

PLL_DIVSEL_FB

-----------------------------------------------------

PLL_DIVSEL_REF

66 www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide

PLL_Clock

-----------------------------------

f

CLKIN

DIV×

1.25 GHz

----------------------------------

125 MHz 5×

2===

UG196 (v1.3) May 25, 2007

Equation 5-4

R

7. Select the PLL divider values

Select the smallest divider values that result in the required PLL divider ratio. In this
case, using PLL_DIVSEL_FB = 2 and PLL_DIVSEL_REF = 1 results in a ratio of two.

Configuring Shared PLL for PCI Express

This example shows how to set the shared PLL divider settings for PCI Express using

Equation 5-1. The RocketIO GTP Wizard and Tab le 5 -3 are simpler alternatives. This

example is provided only to illustrate the process with Equation 5-1.

Use Equation 5-1 as described in the following steps:

1. Determine the required line rates.

For PCI Express, both TX and RX use a line rate of 2.5 Gb/s.

2. Determine the internal datapath width.

Because PCI Express uses 8B/10B encoding, an internal datapath width of 10 bits is
required.

3. Determine the desired reference clock rate.

This example uses a reference clock running at 100 MHz.

Shared PMA PLL

4. Calculate the required PLL clock rate.

Because the SIPO block uses both edges of the clock to deserialize data, it must be fed
a clock running at 2.5/2 = 1.25 GHz. Because this RX rate of 1.25 GHz is within the
operating range of the PLL, the external divider (PLL_RXDIVSEL_OUT) must be one.
The PLL clock rate is thus 1.25 x 1 = 1.25 GHz.

5. Calculate the required DIV value

Because the internal datapath with must be 10 bits and INTDATAWIDTH = 1, DIV = 5.

6. Calculate the required PLL divider ratio

Using the values f

CLKIN

, DIV, and f

PLL_CLOCK

determined above, rearrange

Equation 5-1 to calculate the divider ratio as shown in Equation 5-5. The result is a

ratio of 2.5.

PLL_DIVSEL_FB

-----------------------------------------------------

PLL_DIVSEL_REF

f

PLL_Clock

-----------------------------------

f

CLKIN

DIV×

1.25 GHz

----------------------------------

100 MHz 5×

2.5===

Equation 5-5

7. Select the PLL divider values

Select the smallest divider values that result in the required PLL divider ratio. In this
case, using PLL_DIVSEL_FB = 5 and PLL_DIVSEL_REF = 2 results in a ratio of 2.5.

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Chapter 5: Tile Features

Clocking

Overview

R

For proper high-speed operation, the GTP transceiver requires a high-quality, low-jitter,
reference clock. Because of the shared PMA PLL architecture inside the GTP_DUAL tile,
each reference clock sources both channels. The reference clock is used to produce the PLL
clock, which is divided by one, two, or four to make individual TX and RX serial clocks and
parallel clocks for each GTP transceiver. See “Shared PMA PLL,” page 60 for details.

The GTP_DUAL reference clock is provided through the CLKIN port. There are three ways
to drive the CLKIN port (see Figure 5-3):

• Using an external oscillator to drive GTP dedicated clock routing

• Using a clock from a neighboring GTP_DUAL tile through GTP dedicated clock

routing

• Using a clock from inside the FPGA (GREFCLK)

Using the dedicated clock routing provides the best possible clock to the GTP_DUAL tiles.
Each GTP_DUAL tile has a pair of dedicated clock pins, represented by IBUFDS
primitives, that can be used to drive the dedicated clock routing. Refer to Chapter 10,

“GTP-to-Board Interface,” REFCLK Guidelines for IBUFDS details.

This clocking section shows how to select the dedicated clocks for use by one or more
GTP_DUAL tiles. Guidelines for driving these pins on the board are discussed in

Chapter 10, “GTP-to-Board Interface.”

When GREFCLK clocking is used for a specific GTP_DUAL tile, the dedicated clock
routing is not used. Instead, the global clock resources of the FPGA are connected to the
shared PMA PLL. GREFCLK clocking is not recommended for most designs because of the
increased jitter introduced by the FPGA clock nets.

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Clocking

GTP_DUAL Tile

GTP_DUAL Tile

GTP_DUAL Tile

GTP_DUAL Tile

GTP_DUAL Tile

PLL

PLL

PLL

PLL

PLL

CLKIN

CLKIN

CLKIN

CLKIN

CLKIN

Clock

Muxing

Clock

Muxing

Clock

Muxing

Clock

Muxing

Clock

Muxing

BUFG/

BUFR

BUFG/

BUFR

BUFG/

BUFR

BUFG/

BUFR

BUFG/

BUFR

GREFCLK

GREFCLK

GREFCLK

GREFCLK

GREFCLK

GTP

Dedicated

Clock

Routing

GTP

Dedicated

Clock

Routing

GTP

Dedicated

Clock

Routing

GTP

Dedicated

Clock

Routing

GTP

Dedicated

Clock

Routing

MGTREFCLKP

IBUFDS

MGTREFCLKN

MGTREFCLKP

IBUFDS

MGTREFCLKN

MGTREFCLKP

IBUFDS

MGTREFCLKN

MGTREFCLKP

IBUFDS

MGTREFCLKN

MGTREFCLKP

IBUFDS

MGTREFCLKN

GTP_DUAL Tile

PLL

CLKIN

Clock

Muxing

BUFG/

BUFR

GREFCLK

GTP

Dedicated

Clock

Routing

GTP_DUAL Tile

PLL

CLKIN

Clock

Muxing

BUFG/

BUFR

GREFCLK

GTP

Dedicated

Clock

Routing

GTP_DUAL Tile

PLL

CLKIN

Clock

Muxing

BUFG/

BUFR

GREFCLK

GTP

Dedicated

Clock

Routing

Note: Refer to Chapter 10, “GTP-to-Board Interface” REFCLK Guidelines for IBUFDS details.

Figure 5-3: GTP Transceiver Clocking

MGTREFCLKP

IBUFDS

MGTREFCLKN

MGTREFCLKP

IBUFDS

MGTREFCLKN

MGTREFCLKP

IBUFDS

MGTREFCLKN

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Chapter 5: Tile Features

Ports and Attributes

Tab le 5- 4 defines the shared clocking ports.

Table 5-4: Shared Clocking Ports

Port Dir Clock Domain Description

CLKIN In N/A Reference clock input to the shared PMA PLL.

The REFCLKOUT port from each GTP_DUAL

REFCLKOUT Out N/A

tile provides access to the reference clock
provided to the shared PLL (CLKIN). It can be
routed for use in the FPGA logic.

Tab le 5- 5 defines the shared clocking attributes.

Table 5-5: Shared Clocking Attributes

Attribute Description

The internal digital logic for GTP_DUAL tile management runs at about
25 MHz. CLK25_DIVIDER is set to get an internal clock for the tile.

CLK25_DIVIDER

1: CLKIN <
2: 25 MHz < CLKIN <
3: 50 MHz < CLKIN <
4: 75 MHz < CLKIN <
5: 100 MHz < CLKIN <
6: 125 MHz < CLKIN <
10: 150 MHz < CLKIN <

25 MHz

50 MHz
75 MHz
100 MHz

125 MHz
150 MHz

250 MHz

12: CLKIN > 250 MHz

R

Description

Clocking from an External Source

Each GTP_DUAL tile has a pair of dedicated pins that can be connected to an external
clock source. To use these pins, an IBUFDS primitive is instantiated. In the User
Constraints file, the IBUFDS input pins are constrained to the locations of the dedicated
clock pins for the GTP_DUAL tile. In the design, the output of the IBUFDS is connected to
the CLKIN port. The locations of the dedicated pins for all the GTP_DUAL tiles are
documented in Chapter 4, “Implementation.” Chapter 10, “GTP-to-Board Interface”
provides a selection of suitable external oscillators and describes the board-level
requirements for the dedicated reference clock. Figure 5-4 shows a differential GTP clock
pin pair sourced by an external oscillator on the board. Refer to Chapter 10, “GTP-to-Board

Interface,” REFCLK Guidelines for IBUFDS details.

CLKINDC_B

Must be set to TRUE. Oscillators driving the dedicated reference clock
inputs must be AC coupled.

GTP_DUAL

CLKIN

IBUFDS

MGTREFCLKP

MGTREFCLKN

UG196_c5_04_110306

Figure 5-4: Single GTP_DUAL Tile Clocked Externally

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Clocking from a Neighbor GTP_DUAL Tile

The external clock from one GTP_DUAL tile can be used to drive the CLKIN ports of
neighboring tiles. The example in Figure 5-5 uses the clock from one GTP_DUAL tile to
clock six neighboring tiles. A GTP_DUAL tile shares its clock with its neighbors using the
dedicated clock routing resources. Refer to Chapter 10, “GTP-to-Board Interface,” REFCLK

Guidelines for IBUFDS details.

GTP_DUAL Tile

GTP_DUAL Tile

GTP_DUAL Tile

Clocking

CLKIN

CLKIN

CLKIN

GTP_DUAL Tile

CLKIN

GTP_DUAL Tile

CLKIN

GTP_DUAL Tile

CLKIN

GTP_DUAL Tile

CLKIN

IBUFDS

MGTREFCLKP

MGTREFCLKN

UG196_c5_05_110306

Figure 5-5: Multiple GTP_DUAL Tiles with Shared Reference Clock

Note:

margins for high-speed designs are met:

1. The number of GTP_DUAL tiles above the sourcing GTP_DUAL tile must not exceed three.

2. The number of GTP_DUAL tiles below the sourcing GTP_DUAL tile must not exceed three.

3. The total number of GTP_DUAL tiles sourced by the external clock pin pair

4. All the GTP_DUAL tiles between the source of the reference clock and a tile using the reference

The following rules must be observed when sharing a reference clock to ensure that jitter

(MGTREFCLKN/MGTREFCLKP) must not exceed seven.

clock, including the tile with a IBUFDS in use, must be instantiated in the design.

The maximum number of GTP transceivers that can be sourced by a single clock pin pair is

14. Designs with more than 14 transceivers require the use of multiple external clock pins
to ensure that the rules for controlling jitter are followed. When multiple clock pins are
used, an external buffer can be used to drive them from the same oscillator. The same
oscillator must be used when the GTP transceivers are combined to form a single channel
using channel bonding (see “Configurable Channel Bonding (Lane Deskew),” page 175).

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Chapter 5: Tile Features

Clocking using GREFCLK

R

The internal clock nets of the FPGA can provide the reference clock for the GTP_DUAL by
connecting the output of a global clock buffer (BUFG) or a regional clock buffer (BUFR) to
the CLKIN port. This type of clocking, called GREFCLK clocking, has the lowest
performance of any of the three clocking methods, because FPGA clocking resources
introduce too much jitter for operation at high rates. GREFCLK clocking should be
avoided, if possible. See the Virtex-5 Data Sheet for the jitter margins at different speeds.

Figure 5-6 shows how a GTP_DUAL tile connects to a BUFR or a BUFG. If a BUFR is used,

it must be located in the same region as the GTP_DUAL tile.

Reset

Overview

GTP_DUAL

CLKIN

Notes:

1. Refer to the Virtex-5 Data Sheet and the Virtex-5 Configuration
Guide for the maximum clock frequency and jitter

limitations of BUFR.

BUFG or BUFR

UG196_c5_06_100606

(1)

Figure 5-6: Single GTP_DUAL Tile Clocked from the FPGA

The GTP_DUAL tile must be reset before any of the GTP transceivers can be used. There
are three ways to reset a GTP_DUAL tile:

1. Power up and configure the FPGA. Power-up reset is covered in this section.

2. Drive the GTPRESET port High to trigger a full asynchronous reset of the GTP_DUAL
tile. GTPRESET is covered in this section.

3. Assert one or more of the individual reset signals on the block to reset a specific
subcomponent of the tile. These resets are covered in detail in the sections for each
subcomponent.

This section also includes the instructions for implementing the Link Idle Reset circuit.
This circuit must be implemented with all instances of the GTP_DUAL tile to allow the RX
CDR circuit to operate correctly.

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Ports and Attributes

Tab le 5- 6 defines the shared tile reset ports.

Table 5-6: Shared Tile Reset Ports

Port Dir Domain Description

GTPRESET In Async

RESETDONE0
RESETDONE1

RXBUFRESET0

RXBUFRESET1

RXCDRRESET0

RXCDRRESET1

RXELECIDLERESET0

RXELECIDLERESET1

Out Async

In Async This active-High signal resets the RX buffer logic.

In RXUSRCLK2

In Async

Reset

This port is driven High to start the full GTP_DUAL reset sequence.
This sequence takes about 160 μs to complete, and systematically
resets all subcomponents of the GTP_DUAL tile.

This port goes High when the GTP transceiver has finished reset
and is ready for use. For this signal to work correctly, CLKIN and
all clock inputs on the individual GTP transceiver (TXUSRCLK,
TXUSRCLK2, RXUSRCLK, RXUSRCLK2) must be driven.

Individual reset signal for the RX CDR and the RX part of the PCS
for this channel. This signal is driven High to cause the CDR to give
up its current lock and return to the shared PLL frequency.

These active-High reset inputs reset the GTP transceiver receive
logic when the link is in a powerdown state. Figure 5-9 shows how
these signals are connected. If the link idle reset is not supported,
these signals are strapped Low.

When asserted, this active-Low signal enables the

RXENELECIDLERESETB In Async

RXELECIDLERESET0/1 inputs. Figure 5-9 shows how this signal is
connected when the link idle reset is supported. If
RXELECIDLERESET0/1 are not used, this signal is strapped High.

RXRESET0

RXRESET1

TXRESET0

TXRESET1

In Async Active-High reset for the RX PCS logic.

In Async

Resets the PCS of the GTP transmitter, including the phase adjust
FIFO, the 8B/10B encoder, and the FPGA TX interface.

PRBSCNTRESET In RXUSRCLK2 Resets the PRBS error counter.

PLLPOWERDOWN In Async

Powers down the shared PMA PLL. Driving PLLPOWERDOWN
from Low to High triggers a GTPRESET.

There are no attributes in this section.

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Chapter 5: Tile Features

Description

GTP Reset in Response to Completion of Configuration

R

Figure 5-7 shows the GTP_DUAL reset sequence following completion of configuration of

a powered-up GTP_DUAL tile. The same sequence is activated any time
PLLPOWERDOWN goes from High to Low during normal operation.

Refer to “Power Control,” page 81 on power-down for details about PLLPOWERDOWN.

cfg_reset_b

Global

Configuration

Signals

Internal TXRESET

Internal RXRESET

Internal RXBUFRESET

Notes:

1. The timing of the reset sequencer inside the GTP_DUAL tile depends on the frequency of CLK25.
The estimates given in this figure assume that the frequency of CLK25 is 25 MHz.

grestore_b

gwe_b

~160 μs

(1)

UG196_c5_07_100606

Figure 5-7: GTP_DUAL Reset Sequence Following Configuration

The following GTP_DUAL sections are affected by the reset sequence after configuration:

• Shared PLL

• GTP0 transmit section (PMA and PCS)

• GTP0 receive section (PMA and PCS)

• GTP1 transmit section (PMA and PCS)

• GTP1 receive section (PMA and PCS)

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GTP Reset When the GTPRESET Port is Asserted

Figure 5-8 is similar to Figure 5-7, showing the full reset sequence occurring in response to

a pulse on GTPRESET. GTPRESET acts as an asynchronous reset signal.

GTPRESET

Internal TXRESET

Internal RXRESET

Internal RXBUFRESET

Figure 5-8: Reset Sequence Triggered by the GTPRESET Pulse

The following GTP_DUAL sections are affected by the GTPRESET sequence:

• Shared PMA PLL

• GTP0 transmit section (PMA and PCS)

• GTP0 receive section (PMA and PCS)

• GTP1 transmit section (PMA and PCS)

• GTP1 receive section (PMA and PCS)

Reset

~160 μs

UG196_c5_08_100606

GTP Component-Level Resets

Component resets are primarily used for special cases. These resets are needed when only
the reset of a specific GTP_DUAL subsection is required. Table 5- 6 , pa ge 7 3 provides an
overview of component level resets. Tab le 5 -7 describes the component level resets.

All component resets are asynchronous with the exception of PRBSCNTRESET, which is
synchronous to RXUSRCLK2 and is effective only on its rising edge.

Link Idle Reset Support

During operation, an electrical idle condition can occur on the GTP receiver, causing
RXELECIDLE to be driven High. The following events can cause an RX electrical idle
condition:

• An open RXP/RXN differential input pair

• A transmitter on the other side of the communication link powers down

• An OOB/beacon signaling sequence

During an electrical idle condition the Clock Data Recovery (CDR) circuit in the receiver
can lose lock. To restart the CDR after an electrical idle condition, RXELECIDLERESET and
RXENELCIDLERESETB must be asserted. “RX Clock Data Recovery (CDR),” page 136
describes the RXELECIDLERESET, RXENELECIDLERESETB, and the CDR circuit in more
detail.

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Figure 5-9 shows the link idle reset circuit required in all GTP designs. Because

RESETDONE is used in the circuit, TXUSRCLK, TXUSRCLK2, RXUSRCLK, and
RXUSRCLK2 must all be clocked on active GTP transceivers.

GTP_DUAL Tile

RESETDONE0
RXELECIDLE0

RXELECIDLERESET0

RXENELECIDLERESETB

RXELECIDLERESET1

RESETDONE1
RXELECIDLE1

UG196_c5_09_082806

Figure 5-9: Link Idle Reset Implementation

Note:

condition occurs, the derived USRCLKs will flatline, because RXRECCLK flatlines when the
generating CDR is in reset. In this case RXELECIDLE(0/1) can be used as a selection signal of a
BUFGMUX to multiplex between the RXRECCLK(0/1) and a different CDR independent clock source.

If a RXRECCLK is used to generate or derive any of the USRCLKs and an Electrical Idle

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Resetting the GTP_DUAL Tile

Each GTP_DUAL tile offers several ways to reset its subcomponents. Ta bl e 5 -7 shows all
the different ways of resetting a GTP_DUAL tile, and the subcomponents that are affected
by each type of reset.

Reset

Table 5-7: Available Resets Pins and the Components Reset by These Reset Pins

PLLPOWERDOWN

Configuration

GTPRESET

(Falling Edge)

TXRESET

RXCDRRESET

RXRESET

Component

GTP to Board
Interface

Shared
Resources

Termination Resistor

✓

Calibration

Shared PLL ✓✓✓

PLL Lock Detection ✓✓✓

Reset Control ✓✓✓

Power Control ✓✓✓

Clocking ✓✓✓

DRP ✓

TX PCS FPGA TX Interface ✓✓✓✓

8B/10B Encoder ✓✓✓✓

RXBUFRESET

RXELECIDLERESET

PRBSCNTRESET

TX Buffer ✓✓✓✓

PRBS Generator ✓✓✓✓

Polarity Control ✓✓✓✓

TX PMA PISO ✓✓✓

TX Pre-emphasis ✓✓✓

TX OOB & PCI ✓✓✓

TX Driver ✓✓✓

RX PCS FPGA RX Interface ✓✓✓ ✓✓

RX Buffer ✓✓✓ ✓✓✓

RX Status Control ✓✓✓ ✓✓

8B/10B Decoder ✓✓✓ ✓✓

Comma Detect and Align ✓✓✓ ✓✓

RX LOS State Machine ✓✓✓ ✓✓

RX Polarity ✓✓✓ ✓✓

PRBS Checker ✓✓✓ ✓✓ ✓

5x Over-sampler ✓✓✓ ✓✓

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Table 5-7: Available Resets Pins and the Components Reset by These Reset Pins (Continued)

PLLPOWERDOWN

Configuration

GTPRESET

(Falling Edge)

TXRESET

RXCDRRESET

RXRESET

RXBUFRESET

RXELECIDLERESET

Component

RX PMA SIPO ✓✓✓ ✓ ✓

RX CDR ✓✓✓ ✓ ✓

RX Termination and

✓✓✓

Equalization

RX OOB ✓✓✓ ✓

Loopback Loopback paths ✓✓✓

The reset that occurs after configuration and the GTPRESET port are the most common
ways to prepare GTP_DUAL(s) for operation, but certain situations can require the use of
other reset ports. Tabl e 5-8 outlines some of these situations, and the recommended resets.

Table 5-8: Recommended Resets for Common Situations

Situation Components to be Reset Recommended Reset

PRBSCNTRESET

(1)

Power Up and Configuration Entire GTP_DUAL tile Reset after configuration is

automatic.

Turning on a reference clock Shared PLL GTPRESET

Changing a reference clock Shared PLL GTPRESET

Parallel clock source reset TX PCS, RX PCS, Phase Alignment TXRESET, RXRESET

Remote Power Up RX CDR RXELECIDLERESET

SATA OOB / PCI Express

RX CDR RXELECIDLERESET

Electrical Idle

Connecting RXN/RXP RX CDR RXELECIDLERESET

After a TX buffer error TX Buffer TXRESET

After an RX buffer error RX Buffer RXBUFRESET

Before channel bonding RX CDR, then RXBUFFER after CDR is locked RXELECIDLERESET,

RXBUFRESET

PRBS error PRBS Error counter PRBSCNTRESET

Over-sampler error Over-sampler RXRESET

Notes:

1. The recommended reset has the smallest impact on the other compents of the GTP_DUAL tile.

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Examples

Reset

Powerup and Configuration

All the GTP_DUAL tiles are reset automatically after configuration. The supplies for the
calibration resistor and calibration resistor reference must be powered up before
configuration to ensure correct calibration of all the transceivers termination impedance.

Turning on a Reference Clock

The reference clock source(s) and the power to the GTP_DUAL tile must be available
before configuring the FPGA. If the reference clock(s) or GTP_DUAL tile(s) are powered
up after configuration, apply GTPRESET to allow the shared PLL(s) to lock.

Changing a Reference Clock

Whenever the reference clock input to a GTP_DUAL tile is changed, the shared PLL must
be reset to ensure that it locks to the new frequency. The GTPRESET port must be used for
this purpose.

Parallel Clock Source Reset

The clocks driving TXUSRCLK, RXUSRCLK, TXUSRCLK2, and RXUSRCLK2 must be
stable for correct operation. These clocks are often driven from a PLL or DCM in the FPGA
to meet phase and frequency requirements. If the DCM or PLL loses lock, and begins
producing incorrect output, TXRESET and RXRESET must be used to hold transceiver PCS
in reset until the clock source is locked again.

If the TX or RX buffer is bypassed and phase alignment is in use, phase alignment must be
performed again after the clock source re-locks.

Remote Power Up

If the remote source of incoming data is powered up after the GTP transceiver receiving its
data is operating, the RX CDR must be reset to ensure a clean lock to the incoming data.
RXELECIDLERESET must be used for this purpose.

Electrical Idle Reset

When the differential voltage of the RX input to a GTP transceiver drops to OOB or
electrical idle levels, the RX CDR can be pulled out of lock by the apparent sudden change
in frequency. To ensure the CDR can re-lock, it must be held in reset until the signal returns
using RXELECIDLERESET.

Figure 5-9 shows the Link Idle reset circuit. This circuit is required for designs where

Electrical Idle or OOB/beacon signals are used, and is recommended for all designs. The
circuit asserts RXELECIDLERESET whenever RXELECIDLE is detected. RXELECIDLE is
asserted whenever the RXOOB circuit is reset. RESETDONE prevents the
RXELECIDLERESET signal from being asserted while another reset is in progress.

Connecting RXP/RXN

When the RX data to the GTP transceiver comes from a connector that can be plugged in
and unplugged, the RX CDR must be reset when the data source is plugged in to ensure
that it can lock to incoming data. Use RXELECIDLERESET to perform this reset.

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After a TX Buffer Error

When the TX buffer overflows or underflows, it must be reset using TXRESET to ensure
correct behavior.

After an RX Buffer Error

After an RX buffer overflow or underflow, the RX buffer must be reset using the
RXBUFRESET port to ensure correct behavior.

Before Channel Bonding

For successful channel bonding, the RX buffers of all the bonded transceivers must be
written using the same recovered frequency, and read using the same RXUSRCLK
frequency.

To provide the same RXUSRCLK frequency to all bonded transceivers, use a low skew
clock buffer (for example, a BUFG) to drive all the RXUSRCLK ports from the same clock
source. Bonding should not be attempted until the clock source is stable.

To provide the same recovered clock to all bonded transceivers:

• All of the TX data sources must be locked to the same reference clock

• All of the bonded transceivers must have CDR lock to the incoming data

The required reset for channel bonding is as follows:

• Assert RXELECIDLERESET to reset the CDR for all bonded transceivers

• Wait for CDR lock and bit alignment on all bonded transceivers

• Apply RXBUFRESET to all bonded transceivers

• Attempt channel bonding

See “RX Clock Data Recovery (CDR)” in Chapter 7 for recommended methods of detecting
CDR lock.

PRBS Error

To clear the RXPRBSERR signal after the PRBS error threshold is exceeded, assert
PRBSERRRESET.

Oversampler Error

If RXOVERSAMPLEERR goes High to indicate an overflow or underflow in the
Oversampling block, assert RXRESET to clear it.

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Power Control

Overview

The GTP_DUAL tiles support a range of power control modes. These modes support both
generic power management capabilities as well as those defined in the PCI Express and
SATA standards.

Ports and Attributes

Tab le 5- 9 defines the power ports.

Table 5-9: Power Por ts

Port Dir Domain Description

CLKIN In N/A

PLLPOWERDOWN In Async

Power Control

Reference clock input to the shared PMA PLL. The CLKIN rate in
conjunction with CLK25_DIVIDER determines the timing PCIe
powerdown state transitions.

Powers down the shared PMA PLL:

0: Shared PMA PLL is powered up
1: Shared PMA PLL is powered down

REFCLKPWRDNB In Async

RXPOWERDOWN0[1:0]

RXPOWERDOWN1[1:0]

TXDETECTRX0

TXDETECTRX1

TXELECIDLE0

TXELECIDLE1

TXPOWERDOWN0[1:0]

TXPOWERDOWN1[1:0]

In Async

In TXUSRCLK2

In TXUSRCLK2

In Async

Powers down the GTP reference clock circuit:

0: Reference clock circuit is powered down
1: Reference clock circuit is powered up

Powers down the RX lanes. The encoding complies with the PCI
Express encoding. TX and RX can be powered down separately,
however, for PCI Express compliance, TXPOWERDOWN and
RXPOWERDOWN have to be used together.

00: P0 (normal operation)
01: P0s (low recovery time powerdown)
10: P1 (longer recovery time; RecDet is still on)
11: P2 (lowest power state) In the P2 powerstate, RXRECCLK

of this GTP transceiver is indeterminate, it is either a static 1 or
a static 0.

Activates the receive detection sequence. The sequence ends when
PHYSTATUS is asserted to indicate that the results of the test are
ready on RXSTATUS.

Drives TXN and TXP to the same voltage to perform PCI Express
electrical idle/beaconing

Powers down the TX lanes. The encoding complies with the PCI
Express encoding. TX and RX can be powered down separately,
however, for PCI Express compliance, TXPOWERDOWN and
RXPOWERDOWN have to be used together.

00: P0 (normal operation)
01: P0s (low recovery time powerdown)
10: P1 (longer recovery time; RecDet is still on)
11: P2 (lowest power state)

Notes:

1. Because of the shared PMA PLL, a powerdown via PLLPOWERDOWN or REFCLKPWRDNB affects both channels.

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Tab le 5- 10 defines the power attributes.

Table 5-10: Power Attributes

Attribute Description

The internal digital logic for GTP_DUAL tile management
runs at about 25 MHz. CLK25_DIVIDER is set to get an

CLK25_DIVIDER

PCI_EXPRESS_MODE_0

PCI_EXPRESS_MODE_1

internal clock for the tile. The CLK25_DIVIDER in
conjunction with CLKIN determines the timing of PCIe
powerdown state transitions by adjusting the internal
25 MHz clock rate.

Setting this attribute to TRUE enables certain operations
specific to PCI Express, specifically, recognizing
TXELECIDLE = 1, TXCHARDISPMODE = 1,
TXCHARDISPVAL = 0 as a request to power down the
channel.

TXCHARDISPMODE = 1 and TXCHARDISPVAL = 0 encode
the PIPE interface signal TXCompliance = 1 of the PIPE (the
latter two values being the encoding for PIPE and enabling
special support for FTS lane deskew).

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Description

The GTP_DUAL tile offers different levels of power control. Each channel in each direction
can be powered down separately using TXPOWERDOWN and RXPOWERDOWN.
Additionally, the shared PMA PLL and the reference clock section can be powered down,
which affects both channels and both directions. The ports PLLPOWERDOWN and
REFCLKPWRDNB directly affect the shared PMA PLL and therefore both channels of the
GTP_DUAL tile.

Generic GTP Power Control Capabilities

TRANS_TIME_FROM_P2_0

TRANS_TIME_FROM_P2_1

TRANS_TIME_NON_P2_0

TRANS_TIME_NON_P2_1

TRANS_TIME_TO_P2_0

TRANS_TIME_TO_P2_1

Transition time from the P2 state in internal 25 MHz clock
cycles. The exact time depends on the CLKIN rate and the
setting of CLK25_DIVIDER. The P2 state is related to the PCI
Express power state definition.

Transition time to or from any state except P2 in internal
25 MHz clock cycles. The exact time depends on the CLKIN
rate and the setting of CLK25_DIVIDER. This setting is
related to the PCI Express power state definition.

Transition time to the P2 state in internal 25 MHz clock cycles.
The exact time depends on the CLKIN rate and the setting of
CLK25_DIVIDER. This setting is related to the PCI Express
power state definition.

The GTP_DUAL tile provides several power control features that can be used in a wide
variety of applications. Ta bl e 5- 11 summarizes these capabilities. The Recovery Time
column describes how long after a power control mode is disabled that normal operation
can resume.

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Power Control

Table 5-11: Basic Power Control Functions Summary

Relative

Function Controlled By

REFCLK Power Control REFCLKPOWERDNB TX and RX for both transceivers in a

PLL Power Control PLLPOWERDOWN TX and RX for both transceivers in a

TX Power Control TXPOWERDOWN[1:0] TX in a single transceiver

RX Power Control

Notes:

1. When RXPOWERDOWN[1:0] is set to 11, which is the lowest power state (P2), then RXRECCLK of this transceiver is
indeterminate. RXXRECCLK of this GTP transceiver is either a static 1 or a static 0.

(1)

RXPOWERDOWN[1:0] RX in a single transceiver.

Power

Savings

Affects

tile, and all downstream GTP_DUAL
tiles sharing that REFCLK

GTP_DUAL tile

REFCLK Power Control

To activate the REFCLK power control mode, the active-Low REFCLKPOWERDNB signal
is asserted. When REFCLKPOWERDNB is asserted, toggling of all circuitry clocked by the
REFCLK input is suppressed, including the shared PMA PLL and all clocks derived from
it. In addition, asserting REFCLKPOWERDNB disables the dedicated clock routing
circuitry associated with that tile. If the GTP_DUAL tiles share a common reference,
REFCLK is suppressed to tiles that are downstream in the clock routing chain. Figure 5-3
illustrates how the dedicated clock routing blocks forward REFCLKs between GTP_DUAL
tiles.

Recovery

Time

Recovery from this power state is indicated by the assertion of the

tile whose
clocks are affected.

REFCLKPOWERDNB signal is asserted and all downstream tiles whose reference

PLLLKDET signal on the

PLL Power Control

To activate the PLL power control mode, the active-High PLLPOWERDOWN signal is
asserted. When PLLPOWERDOWN is asserted, the shared PMA PLL and all clocks
derived from it are stopped.

Recovery from this power state is indicated by the assertion of the

tile whose

REFCLKPOWERDNB signal is asserted.

PLLLKDET signal on the

TX and RX Power Control

When the TX and RX power control signals are used in non-PCI Express implementations,
the TXPOWERDOWN and RXPOWERDOWN can be used independently. However,
when these interfaces are used in non-PCI Express applications, only two power states are
supported, as shown in Ta bl e 5- 12 . When using this power control mechanism, the
following must be True:

• TXPOWERDOWN[1] and TXPOWERDOWN[0] are connected together.

• RXPOWERDOWN[1] and RXPOWERDOWN[0] are connected together.

• TXDETECTRX must be strapped Low.

• TXELECIDLE must be strapped to TXPOWERDOWN[1] and TXPOWERDOWN[0].

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Table 5-12: TX and RX Power States for Non-PCI Express Operation

TXPOWERDOWN[1:0] or

RXPOWERDOWN[1:0]

00 P0 mode. Transceiver TX or RX is active sending or receiving data.

11 P2 mode. Transceiver TX or RX is idle.

Power Control Features for PCI Express

The GTP_DUAL tile implements all of the functions needed for power control states
compatible with those defined in the PCI Express and PIPE specifications. When
implementing PCI Express compatible power control, the following conditions must be
met:

• The TXPOWERDOWN and RXPOWERDOWN on each GTP transceiver must be

connected together to ensure that they are in the same state at all times.

• The REFCLKPOWERDNB and PLLPOWERDOWN signals must be held in an

inactive state.

Table 5-13: TX and RX Power States for PCI Express Operation

TXPOWERDOWN[1:0]

and

RXPOWERDOWN[1:0]

TXDETECTRX TXELECIDLE Description

00

The PHY is transmitting data. The MAC provides data
bytes to be sent every clock cycle.

Description

00 (P0 state)

01 (P0s state) Don’t Care

10 (P1 state)

11 (P2 state) Don’t Care

01

1 0 The PHY goes into loopback mode.

1 1 Not permitted.

Don’t Care 0

0 1 The PHY is idle.

1 1 The PHY does a receiver detection operation.

The GTP transceiver acknowledges changes in the PCI Express power mode by asserting
the PHYSTATUS signal for one clock cycle.

The PHY is not transmitting and is in the electrical idle
state.

The MAC should always put the PHY into the electrical

0

1

0 The PHY transmits beacon signaling

1 The PHY is idle.

idle state while in P0s. The PHY behavior is undefined if
TXELECIDLE is deasserted while in P0s or P1.

The PHY is not transmitting and is in the electrical idle
state.

Not permitted. The MAC must always put the PHY into the
electrical idle state while in P1. The PHY behavior is
undefined if TXELECIDLE is deasserted while in P0s or P1.

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Powerdown Transition Times

Examples

Power Control

The delays between changes in the powerdown state when TXPOWERDOWN and
RXPOWERDOWN are changed are controlled by the TRANS_TIME_FROM_P2,
TRANS_TIME_NON_P2, and TRANS_TIME_TO_P2 attributes as described in Tab le 5- 10 .

Each TRANS_TIME delay is set in terms of internal 25 MHz clock cycles. The internal
25 MHz clock rate is set using the CLK25_DIVIDER attribute and the reference clock rate.

Equation 5-6 is used to determine the actual rate.

Transition time in ns

-----------------------------------------------

⎝⎠

CLKIN

TRANS_TIME attribute×=

Equation 5-6

CLK25_DIVIDER

⎛⎞

The example shown in Figure 5-10 shows the recommended method to power down an
unused tile or an unused transceiver in a tile.

Disabled Tile Disabled Transceiver

GTP_DUAL Tile

GTP_DUAL Tile

1
1

1
1

1

0

1
1

1
1

RXPOWERDOWN0[1]
RXPOWERDOWN0[0]

TXPOWERDOWN0[1]
TXPOWERDOWN0[0]

PLLPOWERDOWN

REFCLKPWRDNB

TXPOWERDOWN1[1]
TXPOWERDOWN1[0]

RXPOWERDOWN1[1]
RXPOWERDOWN1[0]

Controlled

by

Application

1
1

1
1

RXPOWERDOWN0[1]
RXPOWERDOWN0[0]

TXPOWERDOWN0[1]
TXPOWERDOWN0[0]

PLLPOWERDOWN

REFCLKPWRDNB

WERDOWN1[1]

TXPO
TXPOWERDOWN1[0]

RXPOWERDOWN1[1]
RXPOWERDOWN1[0]

Disabled
Transceiver

UG196_c5_10_082906

Figure 5-10: Powering Down an Unused Tile

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Figure 5-11 shows how to connect power control signals for a four-lane PIPE compatible

configuration.

GTP_DUAL Tile

RXPOWERDOWN0[1]
RXPOWERDOWN0[0]

TXPOWERDOWN0[1]
TXPOWERDOWN0[0]

0

1

POWERDOWN[1]
POWERDOWN[0]

0

1

PLLPOWERDOWN

REFCLKPWRDNB

TXPOWERDOWN1[1]
TXPOWERDOWN

RXPOWERDOWN1[1]
RXPOWERDOWN1[0]

GTP_DUAL Tile

RXPOWERDOWN0[1]
RXPOWERDOWN0[0]

TXPOWERDOWN0[1]
TXPOWERDOWN0[0]

PLLPOWERDOWN

REFCLKPWRDNB

TXPOWERDOWN1[1]
TXPOWERDOWN1[0]

RXPOWERDOWN1[1]
RXPOWERDOWN1[0]

UG196_c5_11_082906

1[0]

Figure 5-11: 4x PIPE Compatible Configuration

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Dynamic Reconfiguration Port (DRP)

Overview

The DRP allows the dynamic change of parameters of the GTP_DUAL tile. The DRP
interface is a processor-friendly synchronous interface with an address bus (DADDR) and
separated data buses for reading (DO) and writing (DI) configuration data to the
GTP_DUAL tile. An enable signal (DEN), a read/write signal (DWE), and a ready/valid
signal (DRDY) are the control signals that implement read and write operations, indicate
operation completion, or indicate the availability of data.

Ports and Attributes

Tab le 5- 14 defines the DRP signals.

Table 5-14: DRP Ports

Port Dir Clock Domain Description

DADDR[6:0] In DCLK DRP address bus

Dynamic Reconfiguration Port (DRP)

There are no attributes in this section.

Description

The Virtex-5 Configuration Guide provides detailed information on the DRP interface. Refer
to Appendix D, “DRP Address Map of the GTP_DUAL Tile,” for a map of GTP_DUAL
DRP attributes sorted alphabetically by name and by address.

Stopping the reference clock during a DRP operation can prevent the correct termination of
the operation.

DCLK

DEN In DCLK

DI[15:0]

DO[15:0]

DRDY

DWE In DCLK

In N/A DRP interface clock

In DCLK

Out DCLK

Out DCLK

Set to 1 to enable a read or write operation. Set
to 0 on DCLK cycles where no operation is
required.

Data bus for writing configuration data from
the FPGA fabric to the GTP_DUAL tile.

Data bus for reading configuration data from
the GTP_DUAL tile to the FPGA fabric.

Indicates operation is complete for write

operations and data is valid for read
operations.

Set to 0 for read operations. Set to 1 for write
operations.

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GTP Transmitter (TX)

This chapter shows how to configure and use each of the functional blocks inside the GTP
transmitter.

Transmitter Overview

Each GTP transceiver in the GTP_DUAL tile includes an independent transmitter, made
up of a PCS and a PMA. Figure 6-1 shows the functional blocks of the transmitter. Parallel
data flows from the FPGA into the FPGA TX interface, through the PCS and PMA, and
then out the TX driver as high-speed serial data. Refer to Appendix E, “Low Latency

Design,” for latency information on this block diagram.

Chapter 6

9

7

TX

TX

OOB

Driver

Shared

PMA

PLL

Divider

From Shared PMA PLL

&

PCI

4

Polarity

TX

Preemp

Control

PISO

68

TX-PMA TX-PCS

Phase
Adjust

5

PRBS

Generator

FIFO

3

Figure 6-1: GTP TX Block Diagram

The key elements within the GTP transmitter are:

1. “FPGA TX Interface,” page 90

2. “Configurable 8B/10B Encoder,” page 98

3. “TX Buffering, Phase Alignment, and Buffer Bypass,” page 102

4. “TX Polarity Control,” page 108

5. “TX PRBS Generator,” page 109

6. “Parallel In to Serial Out (PISO),” page 110

7. “Configurable TX Driver,” page 112

8. “PCI Express Receive Detect Support,” page 116

9. “TX OOB/Beacon Signaling,” page 119

1

2

8B/10B
Encoder

FPGA

TX

Interface

TX PIPE Control

UG196_c6_01_042407

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Chapter 6: GTP Transmitter (TX)

FPGA TX Interface

Overview

The FPGA TX interface is the FPGA’s gateway to the TX datapath of the GTP transceiver.
Applications transmit data through the GTP transceiver by writing data to the TXDATA
port on the positive edge of TXUSRCLK2.

The width of the port can be configured to be one or two bytes wide. The actual width of
the port depends on the GTP_DUAL tile's INTDATAWIDTH setting (controls the width of
the internal datapath), and whether or not the 8B/10B encoder is enabled. Port widths can
be 8 bits, 10 bits, 16 bits, and 20 bits.

The rate of the parallel clock (TXUSRCLK2) at the interface is determined by the TX line
rate, the width of the TXDATA port, and whether or not 8B/10B encoding is enabled. A
second parallel clock (TXUSRCLK) must be provided for the internal PCS logic in the
transmitter. This chapter shows how to drive the parallel clocks and explains the
constraints on those clocks for correct operation.

Ports and Attributes

R

Tab le 6- 1 defines the FPGA TX interface ports.

Table 6-1: FPGA TX Interface Ports

Port Dir Clock Domain Description

INTDATAWIDTH In Async

REFCLKOUT Out N/A

TXDATA0[15:0]

TXDATA1[15:0]

TXDATAWIDTH0

TXDATAWIDTH1

In TXUSRCLK2

In TXUSRCLK2

Specifies the width of the internal datapath for the entire GTP_DUAL
tile. This shared port is also described in “Shared PMA PLL,” page 60.

• 0: Internal datapath is 8 bits wide

• 1: Internal datapath is 10 bits wide

The REFCLKOUT port from each GTP_DUAL tile provides direct
access to the reference clock provided to the shared PLL (CLKIN). It
can be routed for use in the FPGA logic.

The bus for transmitting data. The width of this port depends on
TXDATAWIDTH:

• TXDATAWIDTH = 0:

TXDATA[7:0] = 8 bits wide

• TXDATAWIDTH = 1:

TXDATA[15:0] = 16 bits wide

When a 10-bit or a 20-bit bus is required, the TXCHARDISPVAL and
TXCHARDISPMODE ports from the 8B/10B encoder are
concatenated with the TXDATA port. See Figure 6-3, page 92.

Selects the width of the TXDATA port.

• 0: TXDATA is 8 bits or 10 bits wide

• 1: TXDATA is 16 bits or 20 bits wide

TXENC8B10BUSE is set High to enable the 8B/10B encoder.

TXENC8B10BUSE In TXUSRCLK2

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INTDATAWIDTH must also be High.

0: 8B/10B encoder bypassed. This option reduces latency.

1: 8B/10B encoder enabled. INTDATAWIDTH must be 1.

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Table 6-1: FPGA TX Interface Ports (Continued)

Port Dir Clock Domain Description

This port provides a parallel clock generated by the GTP transceiver.
This clock can be used to drive TXUSRCLK for one or more GTP
transceivers. The rate of the clock depends on INTDATAWIDTH:

TXOUTCLK0

TXOUTCLK1

Out N/A

• INTDATAWIDTH = 0:

• INTDATAWIDTH = 1:

When INTDATAWIDTH = 1, the duty cycle is 60/40 instead of 50/50.

F

TXOUTCLK

F

TXOUTCLK

FPGA TX Interface

= Line Rate/8

= Line Rate/10

TXRESET0

TXRESET1

TXUSRCLK0

TXUSRCLK1

TXUSRCLK20

TXUSRCLK21

Description

In Async

Resets the PCS of the GTP transmitter, including the phase adjust
FIFO, the 8B/10B encoder, and the FPGA TX interface.

Use this port to provide a clock for the Internal TX PCS datapath. This
clock must always be provided. The rate depends on
INTDATAWIDTH:

In N/A

• INTDATAWIDTH = 0:

F

TXUSRCLK

= Line Rate/8

• INTDATAWIDTH = 1:

F

TXUSRCLK

= Line Rate/10

Use this port to synchronize the FPGA logic with the TX interface.
This clock must be positive-edge aligned to TXUSRCLK. The rate of

In N/A

this clock depends on F

• TXDATAWIDTH = 0:

F

TXUSRCLK2

= F

TXUSRCLK

TXUSRCLK

and TXDATAWIDTH:

• TXDATAWIDTH = 1:

F

TXUSRCLK2

= F

TXUSRCLK

/2

There are no attributes in this section.

The FPGA TX interface allows parallel data to be written to the GTP transceiver for
transmission as serial data. To use the interface:

• The width of the data interface must be configured

• TXUSRCLK2 and TXUSRCLK must be connected to clocks running at the correct rate

Configuring the Width of the Interface

Tab le 6- 2 shows how the interface width for the TX datapath is selected. 8B/10B encoding

is discussed in more detail in “Configurable 8B/10B Encoder,” page 98.

Table 6-2: TX Datapath Width Configuration

INTDATAWIDTH TXDATAWIDTH TXENC8B10BUSE FPGA TX Interface Width

00N/A 8 bits

01N/A 16 bits

10 0 10 bits

10 1 8 bits

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Chapter 6: GTP Transmitter (TX)

Table 6-2: TX Datapath Width Configuration (Continued)

INTDATAWIDTH TXDATAWIDTH TXENC8B10BUSE FPGA TX Interface Width

Figure 6-2 shows how TXDATA is transmitted serially when the internal datapath is 8 bits

(INTDATAWIDTH = 0) and 8B/10B encoding is disabled.

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11 0 20 bits

11 1 16 bits

TXDATA

Figure 6-3 shows how TXDATA is transmitted serially when the internal datapath is 10 bits

(INTDATAWIDTH = 1) and 8B/10B encoding is disabled. When TXDATA is 10 bits or
20 bits wide, the TXCHARDISPMODE and TXCHARDISPVAL ports are taken from the
8B/10B encoder interface and used to send the extra bits.

Transmitted

Last

TXDATA

TXCHARDISPMODE[1]

TXCHARDIPSVAL[1]

15141312111098 76543210 76543210

Transmitted

Last

1514131211109876543210 76543210

Transmitted

First

Transmitted

TXDATA

Figure 6-2: 8B/10B Bypassed, 8-Bit Internal Datapath

TXDATAWIDTH = 1 TXDATAWIDTH = 0

Transmitted

Last

TXDATA

TXCHARDIPSVAL[0]

TXCHARDISPMODE[0]

TXCHARDIPSVAL[0]

Transmitted

First

TXCHARDISPMODE[0]

Figure 6-3: 8B/10B Bypassed, 10-Bit Internal Datapath

Last

TXDATAWIDTH = 0TXDATAWIDTH = 1

Transmitted

First

UG196_c6_02_051206

Transmitted

First

UG196_c6_03_052406

When 8B/10B encoding is used, the data interface is a multiple of 8 bits (Figure 6-2), and
the data is encoded before it is transmitted serially. “Configurable 8B/10B Encoder,” page

98 provides more details about bit ordering when using 8B/10B encoding.

Connecting TXUSRCLK and TXUSRCLK2

The FPGA TX interface includes two parallel clocks: TXUSRCLK and TXUSRCLK2.
TXUSRCLK is the internal clock for the PCS logic in the GTP transmitter. The required rate
for TXUSRCLK depends on the internal datapath width of the GTP_DUAL tile
(INTDATAWIDTH), and the TX line rate of the GTP transmitter (“Parallel In to Serial Out

(PISO),” page 110 describes how the TX line rate is determined). Equation 6-1 shows how

to calculate the required rate for TXUSRCLK.

TXUSRCLK Rate

-----------------------------------------------------------------=

Internal Datapath Width

Line Rate

TXUSRCLK2 is the main synchronization clock for all signals into the TX side of the GTP
transceiver. Most signals into the TX side of the GTP transceiver are sampled on the

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Equation 6-1

R

FPGA TX Interface

positive edge of TXUSRCLK2. TXUSRCLK2 is the same rate at TXUSRCLK when
TXDATAWIDTH is 0, and one half the rate of TXUSRCLK when TXDATAWIDTH is 1.

Equation 6-2 shows how to calculate the required rate for TXUSRCLK2 based on

TXDATAWIDTH.

TXUSRCLK2 Rate TXUSRCLK (TXDATAWIDTH = 0)=

Equation 6-2

TXUSRCLK2 Rate

TXUSRCLK

-------------------------------

2

TXDATAWIDTH = 1()=

There are some rules about the relationships between clocks that must be observed for
TXUSRCLK, TXUSRCLK2, and CLKIN. First, TXUSRCLK and TXUSRCLK2 must be
positive edge aligned, with as little skew as possible between them. As a result, low-skew
clock resources (BUFGs and BUFRs) should be used to drive TXUSRCLK and
TXUSRCLK2. When TXUSRCLK and TXUSRCLK2 have the same frequency, the same
clock resource is used to drive both. When the two clocks have different frequencies,
TXUSRCLK is divided to get TXUSRCLK2. The designer must ensure that the two are
positive edge aligned. The “Examples” section shows various clock configurations that
meet this requirement.

Even though they might run at different frequencies, TXUSRCLK, TXUSRCLK2, and
CLKIN must have the same oscillator as their source. Thus TXUSRCLK and TXUSRCLK2
must be multiplied or divided versions of CLKIN. The GTP transceiver provides access to
CLKIN in two ways: the REFCLKOUT pin (shared by both GTP transceivers in the
GTP_DUAL tile), and the TXOUTCLK pin. The “Examples” section shows several clock
configurations with each pin.

Examples

TXOUTCLK Driving a GTP TX in 1-Byte Mode

REFCLKOUT is the same as CLKIN. It is free-running, meaning that it operates even
before the shared PMA PLL is locked. However, because REFCLKOUT uses the CLKIN
rate, it might require multiplication and division to produce the required rates for
TXUSRCLK and TXUSRCLK2.

TXOUTCLK provides a copy of CLKIN already divided to the TXUSRCLK rate, potentially
requiring fewer dividers. However, TXOUTCLK is not free-running: it is only valid after
the shared PMA PLL is locked, and cannot be used when TX phase alignment is turned on
(see “TX Buffering, Phase Alignment, and Buffer Bypass,” page 102).

Figure 6-4 through Figure 6-8 show different ways FPGA clock resources can be used to

drive the parallel clocks for the TX interface.

In Figure 6-4, TXOUTCLK is used to drive TXUSRCLK and TXUSRCLK2 for 1-byte mode
(TXDATAWIDTH = 0).

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Chapter 6: GTP Transmitter (TX)

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GTP

TXOUTCLK

Transceiver

TXDATA

8 or 10 Bits

TXUSRCLK

TXUSRCLK2

Notes:

1. Refer to the Virtex-5 Data Sheet and the Virtex-5 Configuration Guide for

the maximum clock frequency and jitter limitations of BUFR.

BUFG or

(1)

BUFR

UG196_c6_04_100406

Figure 6-4: TXOUTCLK Drives TXUSRCLK and TXUSRCLK2

TXOUTCLK Driving GTP TX in 2-Byte Mode

The examples in Figure 6-5 and Figure 6-6 use 2-byte datapaths (TXDATAWIDTH = 1). In
these cases, TXOUTCLK drives TXUSRCLK, and TXOUTCLK is divided by two using a
DCM or PLL to drive TXUSRCLK2.

DCM

GTP

Transceiver

CLK0

CLKDV

LOCKED

Design In

PLLLKDET

TXOUTCLK

BUFG

TXUSRCLK2

TXUSRCLK

TXDATA (16 or 20 bits)

CLKFB

RST

CLKIN

Figure 6-5: DCM Provides Clocks for 2-Byte Datapath

FPGA

UG196_c6_05_051507

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FPGA TX Interface

PLL_BASE

PLLLKDET

RST

CLKOUT0

CLKOUT1

LOCKED

Design in

GTP

Transceiver

TXOUTCLK

CLKIN

BUFG

TXUSRCLK2

TXUSRCLK

TXDATA (16 or 20 bits)

Figure 6-6: PLL Provides Clocks for a 2-Byte Datapath

TXOUTCLK Driving Multiple Transceivers for a 2-Byte Datapath

Figure 6-7 shows TXOUTCLK driving multiple GTP user clocks. In this situation, the

frequency must be correct for all GTP transceivers, and they must share the same reference
clock. In Figure 6-7, because the top GTP transceiver uses a two-byte interface, it requires a
divided clock for TXUSRCLK2.

FPGA

UG196_c6_06_032907

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Chapter 6: GTP Transmitter (TX)

TXUSRCLK

PLLLKDET

TXOUTCLK LOCKED

Selected

Divide-by-2

Solution

TXUSRCLK2

R

GTP

TXUSRCLK2

Transceiver

TXUSRCLK

TXDATA (16 or 20 bits)

Design in

FPGA

GTP

TXUSRCLK2

Transceiver

TXUSRCLK

TXDATA (16 or 20 bits)

Figure 6-7: TXOUTCLK Drives Multiple GTP Transceivers with a 2-Byte Interface

REFCLKOUT Driving Multiple Transceivers with a 2-Byte Interface

UG196_c6_07_040709

Figure 6-8 shows how REFCLKOUT can be used to generate USRCLK signals.

REFCLKOUT runs continuously, even when the GTP_DUAL tile is reset; however, extra
clocking resources might be needed to generate the correct USRCLK frequency. In

Figure 6-8, a PLL is used to generate the TXUSRCLK and TXUSRCLK2 frequencies from

REFCLKOUT. A DCM can be used instead of the PLL, but the PLL is more convenient
when the REFCLKOUT rate is not an integer multiple of the required TXUSRCLK rates.

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TXUSRCLK2

TXUSRCLK

FPGA TX Interface

GTP

Transceiver

GTP_DUAL

Tile

GTP

Transceiver

TXDATA (16 or 20 bits)

PLLLKDET

REFCLKOUT

TXUSRCLK2

TXUSRCLK

TXDATA (16 or 20 bits)

BUFG

PLL_BASE

RST

CLKIN

LOCKED

CLKOUT0

CLKOUT1

Design in

FPGA

Figure 6-8: REFCLKOUT Driving Multiple Transceivers with a 2-Byte Interface

UG196_c6_08_040907

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Chapter 6: GTP Transmitter (TX)

Configurable 8B/10B Encoder

Overview

Many protocols use 8B/10B encoding on outgoing data. 8B/10B is an industry-standard
encoding scheme that trades two bits of overhead per byte for improved performance.

Tab le 6- 3 outlines the benefits and costs of 8B/10B. Appendix C shows how 8-bit values

are mapped to 10-bit data and control sequences in 8B/10B.

Table 6-3: 8B/10B Trade-Offs

8B/10B Benefits 8B/10B Costs

R

• DC Balanced: No increase in bit errors due

to line charging on AC-coupled channels.

• Limited Run Lengths: The maximum

number of bits without a transition is 5,
making it easy for receivers to achieve and
maintain lock.

• Error Detection: All single-bit errors and

many multibit errors can be detected using
disparity and out of table error checking.

• Control Characters: 8B/10B allows bytes to

be marked as control characters. This
feature is heavily used in many standard
protocols.

• Two-bit overhead per byte: Every byte

transmitted is mapped to a 10-bit
character. As a result, 20% of the channel
bandwidth is consumed for overhead.

• Both sides of the channel must use

8B/10B: 8B/10B data must be decoded
before it can be used.

The GTP transceiver includes an 8B/10B encoder to encode TX data without consuming
FPGA resources. If encoding is not needed, the block can be disabled to minimize latency.

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Ports and Attributes

Tab le 6- 4 defines the TX encoder ports.

Table 6-4: TX Encoder Ports

Port Dir Clock Domain Description

TXBYPASS8B10B0[1:0]

TXBYPASS8B10B1[1:0]

TXCHARDISPMODE0[1:0]

TXCHARDISPMODE1[1:0]

In TXUSRCLK2

In TXUSRCLK2

Configurable 8B/10B Encoder

TXBYPASS8B10BUSE controls the operation of the TX 8B/10B
encoder on a per-byte basis. It is only effective when both
TXENC8B10B and INTDATWIDTH are High (8B/10B is
enabled).

TXBYPASS8B10BUSE[1] corresponds to TXDATA[15:8], and
TXBYPASS8B10BUSE[0] corresponds to TXDATA[7:0].

00: Both bytes are 8B/10B encoded

01: Only TXDATA[15:8] is 8B/10B encoded

10: Only TXDATA[7:0] is 8B/10B encoded

11: Neither byte is 8B/10B encoded

TXCHARDISPMODE and TXCHARDISPVAL allow the 8B/10B
disparity of outgoing data to be controlled when 8B/10B
encoding is enabled.

When 8B/10B encoding is disabled, TXCHARDISPMODE is
used to extend the data bus for TX interfaces whose width is a
multiple of 10 (see “FPGA TX Interface,” page 90 for details).

TXCHARDISPMODE[1] corresponds to TXDATA[15:8] and
TXCHARDISPMODE[0] corresponds to TXDATA[7:0].

Table 6-5, page 101 shows how TXCHARDISPMODE is used to

control the disparity of outgoing data when 8B/10B encoding is
enabled.

TXCHARDISPVAL0[1:0]

TXCHARDISPVAL1[1:0]

TXCHARISK0[1:0]

TXCHARISK1{1:0]

In TXUSRCLK2

In TXUSRCLK2

TXCHARDISPVAL and TXCHARDISPMODE allow the
disparity of outgoing data to be controlled when 8B/10B
encoding is enabled.

When 8B/10B encoding is disabled, TXCHARDISPVAL is used
to extend the data bus for 10- and 20-bit TX interfaces (see

“FPGA TX Interface,” page 90 for details).

TXCHARDISPVAL[1] corresponds to TXDATA[15:8]

TXCHARDISPVAL[0] corresponds to TXDATA[7:0]

Table 6-5, page 101 shows how TXCHARDISPVAL is used to

control the disparity of outgoing data when 8B/10B encoding is
enabled.

TXCHARISK is set High to send TXDATA as an 8B/10B
K character. TXCHARISK should only be asserted for TXDATA
values in the K-character table of the 8B/10B table in

Appendix C, “8B/10B Valid Characters.”

TXCHARISK[1] corresponds to TXDATA[15:8], and
TXCHARISK[0] corresponds to TXDATA[7:0].

TXCHARISK is undefined for bytes th

at bypass 8B/10B encoding.

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Chapter 6: GTP Transmitter (TX)

Table 6-4: TX Encoder Ports (Continued)

Port Dir Clock Domain Description

TXENC8B10BUSE0

TXENC8B10BUSE1

TXKERR0[1:0]

TXKERR1[1:0]

TXRUNDISP0[1:0]

TXRUNDISP1[1:0]

In TXUSRCLK2

Out TXUSRCLK2

Out TXUSRCLK2

There are no attributes in this section.

R

TXENC8B10BUSE is set High to enable the 8B/10B encoder.
INTDATAWIDTH must also be High.

0: 8B/10B encoder bypassed. This option reduces latency.

1: 8B/10B encoder enabled. INTDATAWIDTH must be 1.

TXKERR indicates an invalid code for a K character was
specified.

TXKERR[1] corresponds to TXDATA[15:8], and TXKERR[0]
corresponds to TXDATA[7:0].

TXRUNDISP indicates the current running disparity of the
8B/10B encoder. This disparity corresponds to TXDATA clocked
in several cycles earlier.

TXRUNDISP[1] corresponds to previous TXDATA[15:8] data,
and TXRUNDISP[0] corresponds to previous TXDATA[7:0] data.

Description

Enabling 8B/10B Encoding

To disable the 8B/10B encoder on a given GTP transceiver, TXENC8B10BUSE must be
driven Low. To enable the 8B/10B encoder, TXENC8B10BUSE must be driven High. When
the encoder is turned off, the operation of the TXDATA port is as described in “FPGA TX

Interface.”

8B/10B Bit and Byte Ordering

The order of the bits after the 8B/10B encoder is the opposite of the order shown in

Appendix C, “8B/10B Valid Characters,” because 8B/10B encoding requires bit a0 to be

transmitted first, and the GTP transceiver always transmits the right-most bit first. To
match with 8B/10B, the 8B/10B encoder in the GTP transceiver automatically reverses the
bit order.

For the same reason, when a two-byte interface is used, the first byte to be transmitted
(byte 0) must be placed on TXDATA[7:0], and the second placed on TXDATA[15:8]. This
placement ensures that the byte 0 bits are all sent before the byte 1 bits, as required by
8B/10B encoding.

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