Virtex-5
Virtex-5 LXT/SXT/FXT
LXT/SXT/FXT
FPGA Prototype Platform
FPGA Prototype
User Guide [optional]
User Guide
UG229 (v3.0.1) May 21, 2008 [optional]
UG229 (v3.0.1) May 21, 2008
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P/N 0402534-03
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Revision History
The following table shows the revision history for this document.
Date Version Revision
12/04/06 1.0 Initial Xilinx release.
02/16/07 2.0 Updated title and added support for Virtex-5 FPGA SXT devices.
Added support for Virtex-5 FPGA FXT devices and RocketIO GTX transceivers. Added
the supported Platforms to “Overview,” page 9. Updated “Features,” page 9. Removed
CD ROM Contents section. Added “Additional Information,” page 10. Updated
05/13/08 3.0
05/21/08 3.0.1 Updated link to
Figure 1, page 11. Added “Related Xilinx Documents,” page 12. Revised “1. Power
Switch,” page 13. Updated FF665 labels A13 and A14 in Table 13, page 26. Added
“23. Configuration Mode Pins,” page 29. Added “References,” page 30. Miscellaneous
typographical edits.
FF1738 platform product page in “Additional Information.”
Virtex-5 LXT/SXT/FXT FPGA Prototype Platform www.xilinx.com UG229 (v3.0.1) May 21, 2008
Table of Contents
Preface: About This Guide
Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Additional Support Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Typographical Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Virtex-5 LXT/SXT/FXT FPGA Prototype Platform
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Package Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Related Xilinx Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1. Power Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2. Power Supply Jacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3. Configuration Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4. JTAG Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5. JTAG Termination Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6. Upstream/Downstream Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7. Prototyping Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8. VCCO-Enable Supply Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
9. VBATT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
10. Oscillator Sockets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
11. Differential Clock Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
12. DUT Socket . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
13. Pin Breakout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
14. User LEDs (Active-High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
15. PROGRAM Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
16. RESET Switch (Active-Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
17. DONE LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
18. INIT LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
19. Platform Flash ISPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
20. SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
21. BPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
22. GTP/GTX Transceiver Clocks to SMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
23. Configuration Mode Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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About This Guide
This user guide describes the features and operation of the Virtex®-5 LXT/SXT/FXT FPGA
prototype platform and provides instructions to configure chains of FPGAs and serial
PROMs.
Complete and up-to-date documentation for the Virtex-5 LXT/SXT/FXT FPGA prototype
platform is available on the Xilinx website at
http://www.xilinx.com/onlinestore/v5_boards.htm
Additional Documentation
The following documents are also available for download at
http://www.xilinx.com/virtex5
Preface
.
.
• Virtex-5 Family Overview
The features and product selection of the Virtex-5 family are outlined in this overview.
• Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
This data sheet contains the DC and Switching Characteristic specifications for the
Virtex-5 family.
• Virtex-5 FPGA User Guide
Chapters in this guide cover the following topics:
♦ Clocking Resources
♦ Clock Management Technology (CMT)
♦ Phase-Locked Loops (PLLs)
♦ Block RAM
♦ Configurable Logic Blocks (CLBs)
♦ SelectIO™ Resources
♦ SelectIO Logic Resources
♦ Advanced SelectIO Logic Resources
• Virtex-5 FPGA RocketIO GTP Transceiver User Guide
This guide describes the RocketIO™ GTP transceivers available in the Virtex-5 LXT
and SXT platforms.
• Virtex-5 FPGA RocketIO GTX Transceiver User Guide
This guide describes the RocketIO GTX transceivers available in the Virtex-5 FXT
platform.
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Preface: About This Guide
• Virtex-5 FPGA Tri-Mode Ethernet Media Access Controller
• Virtex-5 FPGA Integrated Endpoint Block User Guide for PCI Express Designs
• XtremeDSP Design Considerations
• Virtex-5 FPGA Configuration Guide
• Virtex-5 FPGA System Monitor User Guide
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This guide describes the dedicated Tri-Mode Ethernet Media Access Controller
available in the Virtex-5 LXT, SXT, and FXT platforms.
This guide describes the integrated Endpoint blocks in the Virtex-5 LXT, SXT, and FXT
platforms used for PCI Express® designs.
This guide describes the XtremeDSP™ slice and includes reference designs for using
the DSP48E slice.
This all-encompassing configuration guide includes chapters on configuration
interfaces (serial and SelectMAP), bitstream encryption, Boundary-Scan and JTAG
configuration, reconfiguration techniques, and readback through the SelectMAP and
JTAG interfaces.
The System Monitor functionality available in all the Virtex-5 devices is outlined in
this guide.
• Virtex-5 FPGA Packaging and Pinout Specifications
This specification includes the tables for device/package combinations and maximum
I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and
thermal specifications.
• Virtex-5 FPGA PCB Designer’s Guide
This guide provides information on PCB design for Virtex-5 devices, with a focus on
strategies for making design decisions at the PCB and interface level.
Additional Support Resources
To search the database of silicon and software questions and answers, or to create a
technical support case in WebCase, see the Xilinx website at:
http://www.xilinx.com/support
Typographical Conventions
This document uses the following typographical conventions. An example illustrates each
convention.
Convention Meaning or Use Example
References to other documents
Italic font
Emphasis in text
See the Virtex-5 FPGA
Configuration User Guide for more
information.
The address (F) is asserted after
clock event 2.
Underlined Text
6 www.xilinx.com Virtex-5 LXT/SXT/FXT FPGA Prototype Platform
Indicates a link to a web page. http://www.xilinx.com/virtex5
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Online Document
The following conventions are used in this document:
Convention Meaning or Use Example
Blue text
Cross-reference link to a location
in the current document
Typographical Conventions
See the section “Additional
Support Resources” for details.
Refer to “Clock Management
Technology” in Chapter 2 for
details.
Red text
Blue, underlined text
Cross-reference link to a location
in another document
Hyperlink to a website (URL)
See Figure 2 in the Virtex-5 FPGA
Data Sheet
Go to http://www.xilinx.com
for the latest documentation.
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Virtex-5 LXT/SXT/FXT FPGA Prototype
Platform
Overview
The Virtex-5 FPGA prototype platform and demonstration boards enable designers to
investigate and experiment with the features of Virtex-5 FPGAs. This user guide describes
the features and operation of the Virtex-5 LXT/SXT/FXT prototype platform (“the
board”), including how to configure chains of FPGAs and serial PROMs.
This user guide covers the following platforms:
• FF665, FF1136, and FF1738
Caution!
follow standard ESD prevention measures when handling the board.
Note: Prototype platforms are intended strictly for evaluating the functionality of Virtex-5 FPGA
features and are not intended for A/C characterization or high-speed I/O evaluation.
To protect the Virtex-5 board from damage caused by electrostatic discharge (ESD),
Features
• Independent power supply jacks for VCCINT, VCCO, and VCCAUX
• Selectable VCCO-enable pins for each SelectIO™ bank
• Configuration port for use with Parallel Cable III and Parallel Cable IV cables
• 36 clock inputs
♦ 4 differential clock pairs
♦ 4 LVTTL-type oscillator sockets
♦ 20 breakout clock pins
♦ 2 pairs of RocketIO™ GTP/GTX transceiver clock inputs
• Power indicator LEDs
• Onboard Platform Flash ISPROM (32 Mb) for configuration
• Onboard power supplies for the Platform Flash ISPROM
• JTAG port for reprogramming the XCF32P series reconfigurable ISPROM and the user
FPGA, also known as the device under test (DUT)
• Upstream and downstream System ACE™ interface and configuration interface
connectors
• Serial Peripheral Interface (SPI) Serial Flash programming
• Byte-wide Peripheral Interface (BPI) programming
• SPI port for reprogramming the SPI Serial Flash
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