Xilinx Virtex-5 FPGA RocketIO GTP Transceiver IBIS-AMI Signal Integrity Simulation Kit User Manual
Virtex-5 FPGA RocketIO
GTP Transceiver IBIS-AMI
Signal Integrity Simulation
Kit User Guide
for SiSoft Quantum Channel Designer
UG587 (v1.1) June 21, 2012
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Revision History
The following table shows the revision history for this document.
Date Version Revision
03/02/10 1.0 Initial Xilinx release. The SIS Kit version for this release is 2.2.
06/21/12 1.1 Updated the Notice of Disclaimer. Changed the SIS Kit’s accessibility from restricted to
public. Updated Ta bl e 1 -1.
Virtex-5 FPGA GTP Transceiver SIS Kit (IBIS-AMI) www.xilinx.com UG587 (v1.1) June 21, 2012
Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Preface: About This Guide
Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Chapter 1: Virtex-5 FPGA GTP Transceiver IBIS-AMI SIS Kit
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Release Notes for the GTP Transceiver SIS Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Installation and Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Downloading the SIS Kit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Unpacking the Kit Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Creating a New Project from the Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Kit Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Schematic Sets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Transfer Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Transfer Net Properties. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Transfer Net Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SiSoft Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
IBIS Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
IBIS-AMI Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
IBIS-AMI Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Package Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Channel Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Simulation Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bit Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Validation Errors/Warnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
IBIS-AMI Model Control Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Getting Started. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Appendix A: HSPICE and Quantum Channel Designer/IBIS-AMI
Correlation Results
Transmitter Correlation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Correlation Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Correlation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Matched (100 wline) Case Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Matched (50W and 150 wline) Case Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Receiver Correlation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Correlation Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Correlation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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UG587 (v1.1) June 21, 2012
4 www.xilinx.com Virtex-5 FPGA GTP Transceiver SIS Kit (IBIS-AMI)
UG587 (v1.1) June 21, 2012
About This Guide
This signal integrity simulation kit provides a simulation environment for users to
evaluate their channel designs with the Virtex®-5 FPGA RocketIO™ GTP transceivers.
This document explains how to use the examples provided in the design kit and helps
users modify them for their own needs.
Guide Contents
This manual contains the following chapters:
• Chapter 1, Virtex-5 FPGA GTP Transceiver IBIS-AMI SIS Kit, explains how to install,
configure, and use SiSoft Quantum Channel Designer to simulate Virtex-5 FPGA
RocketIO transceivers.
• Appendix A, HSPICE and Quantum Channel Designer/IBIS-AMI Correlation
Results, explains how the correlation results were derived and displays results.
Preface
Additional Resources
To find additional documentation, see the Xilinx website at:
http://www.xilinx.com/literature
To search the Answer Database of silicon, software, and IP questions and answers, or to
create a technical support WebCase, see the Xilinx website at:
http://www.xilinx.com/support
.
.
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Preface: About This Guide
6 www.xilinx.com Virtex-5 FPGA GTP Transceiver SIS Kit (IBIS-AMI)
UG587 (v1.1) June 21, 2012
Virtex-5 FPGA GTP Transceiver
IBIS-AMI SIS Kit
Introduction
This document provides a complete overview of the Virtex®-5 FPGA RocketIO™ GTP
Transceiver IBIS-AMI Signal Integrity Simulation (SIS) Kit, including block diagrams,
system configurations, transfer nets, and libraries. It explains how to install the SIS kit and
the associated files, gives an overview of the SIS kit file hierarchy, and describes the steps
for getting started with simulations.
The Quantum Channel Designer from Signal Integrity Software, Inc. (SiSoft) was used to
simulate the models and example channels. With SiSoft’s Quantum Channel Designer
(QCD), designers can quickly implement and validate high-speed serializer/deserializer
interfaces for bit error rate (BER) and eye-mask compliance. Appendix A, HSPICE and
Quantum Channel Designer/IBIS-AMI Correlation Results, describes how the Quantum
Channel Designer IBIS-AMI simulation results were correlated with the HSPICE
simulations. Results are documented with waveform plots.
Chapter 1
Additional information on the models, ports, and options can be obtained from UG19
Virtex-5 FPGA RocketIO GTP Transceiver User Guide. Additional information regarding the
Quantum Channel Designer can be obtained from the SiSoft Quantum Channel Designer
User Guide (provided with the SIS Kit installation). Questions regarding Quantum Channel
Designer should be directed to SiSoft.
Release Notes for the GTP Transceiver SIS Kit
Tab le 1-1 shows the UG587 document version and the associated GTP Transceiver SIS Kit
version.
Table 1-1: Document and SIS Kit Version Correlation
UG587 Version SIS Kit Version
1.0 2.2
1.1 2.2
The TX and RX models are created to be used primarily in an AC-coupled environment.
6,
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UG587 (v1.1) June 21, 2012
Installation and Requirements
Installation and Requirements
Downloading the SIS Kit
The Virtex-5 FPGA GTP Transceiver IBIS-AMI SIS Kit can be downloaded at:
http://www.xilinx.com/support/download/index.htm
Requirements
• SiSoft Quantum Channel Designer 2009.08 or later
• Microsoft Windows XP Professional, version 2002, Service Pack 2
Unpacking the Kit Files
This kit is supplied as a SiSoft .klp file, which is installed using Quantum Channel
Designer. To install this kit:
1. Ensure the system environment variable QCD_KIT_PATH is defined and pointing to a
writable directory where the kit library is to be installed.
2. From the File menu, select Design Kits, then Install …
3. Browse to the .klp file provided and click Select.
4. Select Install to unpack the kit into the library directory.
Creating a New Project from the Kit
To create a new kit:
1. Select File Design Kits New Project From Kit ...
2. Ensure a writable directory is used for the project.
3. Select the Xilinx kit name on the left.
4. Click Create Project to create the project from the kit.
Kit Overview
This SIS Kit includes models and interconnect data for a sample GTP transceiver interface.
The transmitter and receiver models are provided as IBIS-AMI models. Each model
contains an analog model (used for network characterization) and a corresponding
algorithmic model (used for statistical and time-domain analysis). The receiver model
includes the Virtex-5 FPGA GTP peaking filter. S-parameter data is included for the Xilinx
package (transmit and receive signals), along with sample channel data for 22-inch,
36-inch, and 56-inch
data for their own channels and run link performance simulations
• Project name: v5_gtp_sis_kit_2_2_beta_qcd
• Interface name: GTP
• Target operating frequency: 3.75 Gb/s (266 ps)
Schematic Sets
Only one schematic set has been defined in this interface: set1.
8 www.xilinx.com Virtex-5 FPGA GTP Transceiver SIS Kit (IBIS-AMI)
links. The kit is set up so designers can quickly import S-parameter
.
UG587 (v1.1) June 21, 2012
Transfe r N e t s
Transfer nets are the primary net class data structure in Quantum Channel Designer. They
maintain continuity between pre- and post-layout simulations and can be reused in
multiple ways. Three transfer nets, contained in this kit, consist of two designators, each
with a single differential pin-pair:
• T1_TX_ONLY
• T2_RX_ONLY
• T3_XILINX_CHANNEL
• T4_XTALK_0_AGGRESSOR
• T5_XTALK_3_AGGRESSOR
Note:
User Guide.
Transfer Net Properties
Tab le 1- 2 lists the properties for each transfer net in the kit.
Table 1-2: Design Kit Transfer Net Properties
Kit Overview
For more information regarding transfer nets, refer to the SiSoft Quantum Channel Designer
Transfer Net Type Encoding Description
T1_TX_ONLY SerDes None
T2_RX_ONLY SerDes None
T3_XILINX_CHANNEL SerDes None
T4_XTALK_0_AGGRESSOR SerDes None
T5_XTALK_3_AGGRESSOR SerDes None
GTP transmitter with package into ideal
load
Ideal transmitter into GTP receiver
model
Base Transfer Net to be used for setup of
an actual Xilinx channel simulation
An example of a crosstalk channel with
no aggressors
An example of a crosstalk channel with
aggressors
Transfer Net Usage
The transfer nets in this kit are intended to be used as such:
• T1_TX_ONLY: This transfer net has the GTP transmitter and package driving an ideal
load. It is intended for measurement correlation of the standalone TX. The receiver
model should be replaced with a model of the scope input, and the 0.001 resistors
should be replaced with interconnect models for the test board and scope cable used.
• T2_RX_ONLY: This transfer net has an ideal transmitter driving the GTP receiver
model with the Xilinx package. This transfer net used to evaluate a test setup driving
into the receiver IP. The transmitter model should be replaced with a model of the
stimulus equipment used, and the 0.001 resistors should be replaced with models of
the test board and cabling.
• T3_XILINX_CHANNEL: This transfer net contains the GTP transmitter, receiver,
package models, and sample Xilinx channel data. The sample channel model can be
replaced with an actual channel model (either as a single block of S parameters or as a
collection of individual schematic elements) to simulate the behavior of the Xilinx IP
with the channel.
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