Xilinx Virtex-4 RocketIO Multi-Gigabit Transceiver User Manual

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Virtex-4 RocketIO
Multi-Gigabit
Transceiver

User Guide

UG076 (v4.1) November 2, 2008

Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development

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of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the
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without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves
the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors
contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with
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in the United States and other countries. All other trademarks are the property of their respective owners.

Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008

Revision History

The following table shows the revision history for this document.

Date Version Revision

03/01/05 1.0 Xilinx Initial Release.

03/10/05 1.1 Modified “Power Supply Requirements” in Chapter 6 and Table 6-1, page 176.

04/07/05 1.2 General typographical edits. Revised Ta bl e 2 -2 , Tab le 2- 8, Figure 2-7, Figure 2-8,

Figure 2-11, Figure 2-12, Figure 6-4, Figure 6-8, and Figure E-2. Added “Resetting the
Transceiver,” page 85 and Figure 2-12. Edited Ta ble 4 -1 , Tab le 4- 3, Ta bl e 4- 5 , Tab le 7 -3,
Ta bl e 7 -4 , Tab le 7- 5, Ta bl e 7 -6 , Ta bl e A -1 , Tab le C -1 4, and Ta bl e C- 2 8.

07/01/05 1.3 Changes in Figure 2-4, Figure 2-9, Figure 3-14, Figure 4-9, Figure 6-4 and Figure 6-8.

Revised Ta bl e 3 -2 3 and Ta bl e 3 -2 4. Added Ta b le 5 - 5, revised Ta bl e 5 -5 . Changes to

Ta bl e 7 -4 , Tab le 7- 5, Ta bl e 7 -6 . For clarity, revised all the notes in the tables in
Appendix C. Added a default value to DCDR_FILTER in Appendix F.

01/16/06 2.0 Major revision. All material completely revised and updated, substantial new material

added.

05/23/06 3.0 Major revision. Chapter 1: All Ports/Attributes tables reviewed and expanded. Chapter

2: New Reset section. Low-latency material removed. Chapter 8: New. Chapters 9-12
(Section II): New.

07/19/06 3.1 • Ta bl e 1 -3 : Corrected maximum reference clock frequency to 644 MHz for Aurora

protocols.

Ta bl e 1 -11 : Deleted instruction to set TXTERMTRIM to 0000.

•

• Chapter 2, section “Resetting the Transceiver”:

♦ Modified all references to LOCKUPDATE cycles to REFCLK cycles.
♦ Corrected state definitions in all flowcharts.

• Chapter 3, section “Channel Bonding”: Rewritten and enlarged.

• Chapter 8, section “RXSYNC”:

♦ Modified all references to LOCKUPDATE cycles to REFCLK cycles.

• Ta bl e C -6 and Tab le C- 19 : Corrected TXTERMTRIM default state to 1100.

09/29/06 3.2 • Removed references to the FF1760 package. Not supported.

• Removed references to 1-byte and 2-byte external fabric widths for PCS Bypass mode.

Not supported.

• Removed references to OC-48 protocol. Not supported.

• Removed references to Digital ReceiverLoopback. Not supported.

• Removed former Tables 4-6, 4-7, and Figure 4-12 from section “Out-of-Band (OOB)

Signals.”

• Added RX/TXFDCAL_CLOCK_DIVIDE setting of FOUR for RX/TX calibration with

reference clock speeds over 500 MHz (Tab le 4-4 , Tab le 4 -5 ).

• Added in several places throughout the Guide the recommendation to use the

RocketIO Wizard for MGT configuration.

• Added several new sections and diagrams to Chapter 6, “Analog and Board Design

Considerations” relating to powering MGTs. Existing material edited and updated.

• Added new section “SelectIO-to-MGT Crosstalk”to Chapter 6, “Analog and Board

Design Considerations.”

• Added Appendix D, “Special Analog Functions.” Previously part of Chapter 4.

UG076 (v4.1) November 2, 2008 www.xilinx.com Virtex-4 RocketIO MGT User Guide

Date Version Revision

08/17/07 4.0 Major revision. All material completely revised and updated.

• General typographical edits.

• Added no data encoding and NRZ signaling to “MGT Features.”

• Removed 64B/66B encoding from Preface, Chapter 1, Chapter 2, Chapter 3,

Chapter 4, Chapter 6, Chapter 7, and Appendix E.

• Removed Decision Feedback Equalizer (DFE) from Preface and Chapter 4.

• Changed ring buffer size to 13x64 in Figure 2-7, Figure 3-2, Figure 8-1, and Figure 8-16

to Figure 8-21.

Chapter 1:

• Added notes to Figure 1-1.

• In Ta bl e 1 -3 ; modified reference clock frequency values, added notes 2 through 5,

added new Aurora Transmit and Receive rows. Removed 64B/66B, OIF SxI-5, OIF SFI

4.2, and Aurora 64B/66B protocols.

• Rewrote text before Tab le 1 -4 .

• Modified port definitions in Ta bl e 1 -5 .

• Modified port definitions and end note in Tab le 1- 6.

• Modified attribute descriptions, and added RXCMADJ, POWER_ENABLE,

RXCPSEL, and TXCPSEL attributes in Ta bl e 1 -11 .

• Modified attribute descriptions and added end note after Ta bl e 1-1 2 and Ta bl e 1 -13 .

Chapter 2:

• Added note to Figure 2-1.

• Modified description of SYNCLK1IN and SYNCLK2IN, and added I/O column to

Ta bl e 2 -1 .

• Removed support of RXPCSHCLKOUT, TXPCSHCLKOUT, and RXMCLK in

Ta bl e 2 -2 .

• Modified notes before Figure 2-4, Figure 2-5

and Figure 2-9.

• Modified notes in Figure 2-4 and Figure 2-5.

• Added Tab le 2 -5 and Tab le 2 -7 .

• Added “RX and TX PLL Voltage-Controlled Oscillator (VCO) Operating Frequency.”

• Modified label in and added note to Figure 2-7.

• Added note to Figure 2-8.

• Modified labels in Figure 2-9.

• Modified Figure 2-11.

• Removed 64B/66B Scrambler/Descrambler and 10G BASE R

Gearbox/Decode/Block Sync from “TXRESET” and “RXRESET.”

• Modified last step in “Receive Reset Sequence: RX Buffer Bypassed.”

Chapter 3:

• Added note to Figure 3-1.

• Modified label in and added note to Figure 3-2.

• Modified overflow and underflow labels in Figure 3-3 and Figure 3-4.

• Relocated “RX Fabric Interface and Channel Bonding.”

• Modified text in “8B/10B Encoding/Decoding.”

• Modified text in paragraph before Figure 3-4.

• Removed 64B/66B from Tab le 3- 4.

• Removed PCS_BIT_SLIP from “Symbol Alignment and Detection (Comma

Detection).”

Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008

Date Version Revision

08/17/07

(cont’d)

4.0

(cont’d)

• Modified “10-Bit Alignment for 8B/10B Encoded Data.”

• Expanded SONET alignment sequence figure into Figure 3-15 and Figure 3-16.

• Removed support of RXSYNC functionality in “RXSLIDE.”

• Modified Figure 3-18.

• Modified last paragraph of “Clock Correction Sequences.”

• Removed RXBLOCKSYNC64B66BUSE column, last two rows (64B/66B), and note

from Tab l e 3- 1 4.

• Modified Figure 3-24.

• Modified nominal frequency and period in text following Ta bl e 3 -2 5.

• Removed Clocking in Buffer Bypass Mode section from Chapter 3.

• Removed Buffer Bypass Mode column from Ta bl e 3 -2 6 .

Chapter 4:

• Modified attribute definitions in Tab le 4 -1 .

• Removed description of TXUSRCLK from “Clock and Data Recovery.”

• Corrected references to RXAFEEQ in Figure 4-8.

• Removed description of MGT from “POWERDOWN.”

Chapter 5:

• Added description of CRC wakeup in “Latency and Timing.”

Chapter 6:

• Modified Figure 6-1 and Figure 6-4.

• Corrected equation references in “Determining Power Supply Budget.”

• Added additional bullet item to “Powering Unused MGTs.”

• Modified text in “Reference Clock” and Figure 6-7.

Chapter 7:

• Added “Reference Clock Period Restriction.”

• Rewrote description of TXENOOB and RXSIGDET in “Out-of-Band (OOB)

Signaling.”

• Deleted TXENOOB and RXSIGDET, and added RXSYNC to “MGT Ports that Cannot

Be Simulated.”

Chapter 8:

• Modified note 2 after Ta bl e 8- 1.

• Changed port name to RXBLOCKSYNC64B66BUSE in Ta bl e 8 -3 , Ta bl e 8 -11 , and

Ta bl e 8 -1 2.

• Added notes to say that 64B/66B encoding/decoding is not supported in Figure 8-1,

Figure 8-2, Figure 8-4 to Figure 8-11, Figure 8-13, Figure 8-14, Figure 8-16 to
Figure 8-21, Tab le 8 -1 to Tab l e 8- 9 , Tab le 8 -1 3 to Tab le 8 -17 .

• Added item 5 to “Usage.”

Chapter 9:

• Expanded description in “Clock Traces.”

Chapter 10:

• Rewrote “Optimal Cable Length.”

Appendix A:

• Removed 64B/66B from and modified descriptions of TXOUTCLK1/2 and

RXRECCLK1/2 in Ta bl e A- 1.

• Added notes to Figure A-1, Ta bl e A- 6, and Ta bl e A -7 .

UG076 (v4.1) November 2, 2008 www.xilinx.com Virtex-4 RocketIO MGT User Guide

Date Version Revision

08/17/07

(cont’d)

4.0

(cont’d)

Appendix C:

• Modified Tab le C -2 to Tab le C - 6, Ta bl e C- 8 to Tab le C- 11 , Tab le C -1 3 to Tab le C -1 5,

Ta bl e C -1 7 to Tab le C -2 0, Ta bl e C -2 3, Tab le C -2 4, Ta bl e C -2 6, and Ta bl e C -2 7.

• Modified notes 1 and 3 after Ta bl e C -6 and Ta bl e C -2 5 and expanded note 4 after

Ta bl e C -6 .

Appendix D:

• Expanded note in “Receiver Sample Phase Adjustment.”

Appendix E:

• Removed 64B/66B encoding scheme from Virtex-4 devices and added note 4 in

Ta bl e E -4 .

• Modified Figure E-2.

• Modified text in “Loopback.”

• Removed section on TKERR[0] vs. TKERR[3].

• Removed section on clock correction and channel bonding sequences and

accompanying table.

• Removed discrete equalization row from Tab le E -1 0.

Modified references in Appendix F.

11/02/08 4.1 Added a new paragraph regarding 2.5V power and filtering to “Powering Unused

MGTs” in Chapter 6.

Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008

Table of Contents

Preface: About This Guide

MGT Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

User Guide Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Related Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

User Guide Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Logical / Mathematical Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Port and Attribute Names. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Comma Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Jitter Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Total Jitter (DJ + RJ) Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

MGT Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Typographical. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Section I:
FPGA Level Design

Chapter 1: RocketIO Transceiver Overview

Basic Architecture and Capabilities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Configuring the RocketIO MGT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Available Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Byte Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Chapter 2: Clocking, Timing, and Resets

Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Tile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

MGT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

GT11CLK_MGT and Reference Clock Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

MGT Clock Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Common Reference Clock Use Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

High-Speed Dedicated MGT Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Fabric Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

PMA Transmit Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

PMA Receive Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

RX and TX PLL Voltage-Controlled Oscillator (VCO) Operating Frequency . . . . . . 72

PMA/PCS Clocking Domains and Data Paths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

PMA Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Common MGT Clocking Use Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Setting the Clocking Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Virtex-4 RocketIO MGT User Guide www.xilinx.com 7

UG076 (v4.1) November 2, 2008

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Special Clocking Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

RXCLKSTABLE and TXCLKSTABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

TXPMARESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

RXPMARESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

TXRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

RXRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

CRC Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Resetting the Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Transmit Reset Sequence: TX Buffer Used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Transmit Reset Sequence: TX Buffer Bypassed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Receive Reset Sequence: RX Buffer Used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Receive Reset Sequence: RX Buffer Bypassed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Reset Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

RX Reset Sequence Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Chapter 3: PCS Digital Design Considerations

Top-Level Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Transmit Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Receive Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Fabric Interface Synchronicity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

RX Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

External Bus Width Configuration (Fabric Interface). . . . . . . . . . . . . . . . . . . . . . . . . . 103

Internal Bus Width Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Fabric Interface Functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

PCS Bypass Byte Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

8B/10B Encoding/Decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

TXCHARDISPVAL and TXCHARDISPMODE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

TXCHARISK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

TXRUNDISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

TXKERR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

RXCHARISK and RXRUNDISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

RXDISPERR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

RXNOTINTABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

RXCHARISCOMMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Non-Standard Running Disparity Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Transmitting Vitesse Channel Bonding Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Receiving Vitesse Channel Bonding Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Symbol Alignment and Detection (Comma Detection) . . . . . . . . . . . . . . . . . . . . . . 116

Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

8-Bit / 10-Bit Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

10-Bit Alignment for 8B/10B Encoded Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Determining Barrel Shifter Position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

SONET Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Alignment Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Byte Alignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

ALIGN_COMMA_WORD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

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RXSLIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Clock Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Append/Remove Idle Clock Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Clock Correction Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

CLK_COR_SEQ_1_MASK, CLK_COR_SEQ_2_MASK,

CLK_COR_SEQ_LEN Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Determining Correct CLK_COR_MIN_LAT and CLK_COR_MAX_LAT . . . . . . . . 126

Channel Bonding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

CCCB_ARBITRATOR_DISABLE = TRUE, CLOCK_CORRECTION_USE = FALSE . . 127
CCCB_ARBITRATOR_DISABLE = FALSE, CLOCK_CORRECTION_USE = TRUE . . 127

CCCB_ARBITRATOR_DISABLE Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

CHAN_BOND_SEQ_1_MASK, CHAN_BOND_SEQ_2_MASK,

CHAN_BOND_SEQ_LEN, CHAN_BOND_SEQ_*_* Attributes

Disable Channel Bonding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Setting CHAN_BOND_LIMIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Implementation Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

RX Fabric Interface and Channel Bonding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

. . . . . . . . . . . . . . . 130

Status and Event Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Status Indication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Event Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

RXBUFERR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

TXBUFERR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

LOOPBACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Digital Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Clocking in Buffered Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Chapter 4: PMA Analog Design Considerations

Serial I/O Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Differential Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Output Swing and Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Differential Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Clock and Data Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Receiver Lock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Receive Equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Special Analog Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Out-of-Band (OOB) Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Calibration for the PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

POWERDOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

RXDCCOUPLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

RXPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

TXPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Chapter 5: Cyclic Redundancy Check (CRC)

Functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Handling End-of-Packet Residue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Latency and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

64-Bit Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

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32-Bit Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

16-Bit Transmission, Hold CRC, and Residue of 8-Bit Example. . . . . . . . . . . . . . . . . 160

Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Chapter 6: Analog and Board Design Considerations

Physical Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Power Conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Power Supply Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Determining Power Supply Budget . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Voltage Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Powering Unused MGTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

AC and DC Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

SelectIO-to-MGT Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

High-Speed Serial Trace Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Routing Serial Traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Differential Trace Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Chapter 7: Simulation and Implementation

Model Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Simulation Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

SmartModels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

HSPICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

SmartModel Simulation Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

After Reset or Power-Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Reference Clock Period Restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

RXP/RXN Period Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Reset After Changing Clock Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Out-of-Band (OOB) Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

1-Byte or 2-Byte Fabric Interface Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Toggling GSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Simulating in Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Simulating in VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Phase-Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Frequency Calibration and Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

SONET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

8B/10B Encoding/Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

MGT Ports that Cannot Be Simulated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

TXBUFFERR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Transceiver Location and Package Pin Relation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

MGT Package Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

Chapter 8: Low-Latency Design

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

PCS Clocking Domains and Data Paths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

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Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

PCS Data Path Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Synchronizing the PMA/PCS Clocks in Low-Latency Modes . . . . . . . . . . . . . . . . 197

Transmit Latency and Output Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

TX Low-Latency Buffered Mode without Channel Deskew . . . . . . . . . . . . . . . . . . . . 198

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Use Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

TX Low Latency Buffered Mode with Channel Deskew . . . . . . . . . . . . . . . . . . . . . . . 200

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

Use Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

TX Low Latency Buffer Bypass Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

Use Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

TXSYNC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

TX Channel Skew using TXSYNC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

Worst-Case TX Skew Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

Synchronization Clock = PCS TXCLK, TXPHASESEL = TRUE . . . . . . . . . . . . . . . . . . 215

Synchronization Clock = GREFCLK, TXPHASESEL = FALSE . . . . . . . . . . . . . . . . . . . 216

TX Skew Estimation Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

1.25 Gbit/s, Synchronization Clock = PCS TXCLK, TXPHASESEL = TRUE. . . . . . . . . 217

1.25 Gbit/s, Synchronization Clock = GREFCLK, TXPHASESEL = FALSE . . . . . . . . . 217

6.5 Gbit/s, Synchronization Clock = PCS TXCLK, TXPHASESEL = TRUE . . . . . . . . . 217

6.5 Gbit/s, Synchronization Clock = GREFCLK, TXPHASESEL = FALSE . . . . . . . . . . 217

RX Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

RX Low Latency Buffered Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

Use Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

RX Low Latency Buffer Bypass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

RXSYNC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

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Restrictions on Low Latency Buffer Bypass Modes. . . . . . . . . . . . . . . . . . . . . . . . . . 229

Example of a Reduced-Latency System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

XAUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

System Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

TX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

RX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

Section II:
Board Level Design

Chapter 9: Methodology Overview

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

Powering the RocketIO MGTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

Reference Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

Clock Traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

Coupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

DC Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

AC Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

External Capacitor Value Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

Chapter 10: PCB Materials and Traces

How Fast is Fast?. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

PCB Losses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

Relative Permittivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

Loss Tangent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

Skin Effect and Resistive Losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

Choosing the Substrate Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

Traces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

Trace Geometry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

Trace Characteristic Impedance Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

Trace Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

Plane Splits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

Simulating Lossy Transmission Lines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

Optimal Cable Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

Skew Between Conductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

Chapter 11: Design of Transitions

Excess Capacitance and Inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

Time Domain Reflectometry (TDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

SMT Pads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

Differential Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

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Microstrip/Stripline Bends . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

BGA Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

SMA Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

Chapter 12: Guidelines and Examples

Summary of Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

Channel Budgeting Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

BGA Escape Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

SMT XENPAK70 Connector Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

SMT XFP Connector Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

Tyco Z-PACK HM-Zd Connector Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . 264

SMT DC Blocking Capacitor Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

Section III:
Appendixes

Appendix A: RocketIO Transceiver Timing Model

Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

Timing Diagram and Timing Parameter Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

Input Setup/Hold Times Relative to Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

Clock to Output Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

Clock Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

Appendix B: 8B/10B Valid Characters

Valid Data and Control Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

Appendix C: Dynamic Reconfiguration Port

Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294

Appendix D: Special Analog Functions

Receiver Sample Phase Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321

Appendix E: Virtex-II Pro/Virtex-II Pro X to Virtex-4 RocketIO

Transceiver Design Migration

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325

Primary Differences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325

MGTs per Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325

Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326

Serial Rate Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

Encoding Support and Clock Multipliers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

Flexibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

Board Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328

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Power Supply Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328

Other Minor Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329

Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329

CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330

Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330

Serialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330

RXSTATUS Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331

Pre-emphasis, Differential Swing, and Equalization . . . . . . . . . . . . . . . . . . . . . . . . 331

Appendix F: References

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Schedule of Figures

Section I:
FPGA Level Design

Chapter 1: RocketIO Transceiver Overview

Figure 1-1: RocketIO Multi-Gigabit Transceiver Block Diagram. . . . . . . . . . . . . . . . . . . . 36

Chapter 2: Clocking, Timing, and Resets

Figure 2-1: MGT Column Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 2-2: High-Speed Dedicated Clocks (GT11CLK_MGT Instance) . . . . . . . . . . . . . . 66

Figure 2-3: REFCLK and GREFCLK Options for an MGT Tile . . . . . . . . . . . . . . . . . . . . . 67

Figure 2-4: MGT Transmit Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 2-5: MGT Receive Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 2-6: Transmitter and Receiver Line Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Figure 2-7: PCS Receive Clocking Domains and Datapaths . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 2-8: PCS Transmit Clocking Domains and Datapaths . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 2-9: Low-Latency Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 2-10: DCM Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Figure 2-11: Receive Clocking Decision Flow (Page 1 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 2-11 (Cont’d): Receive Clocking Decision Flow (Page 2 of 2). . . . . . . . . . . . . . . . . . 79

Figure 2-12: Transmit Clocking Decision Flow (Page 1 of 2). . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 2-12 (Cont’d): Transmit Clocking Decision Flow (Page 2 of 2) . . . . . . . . . . . . . . . . 81

Figure 2-13: External PLL Locked Signal for MGT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 2-14: Flow Chart of TX Reset Sequence Where TX Buffer Is Used . . . . . . . . . . . . 86

Figure 2-15: Resetting the Transmitter Where TX Buffer Is Used . . . . . . . . . . . . . . . . . . . 87

Figure 2-16: Flow Chart of TX Reset Sequence Where TX Buffer Is Bypassed . . . . . . . . 88

Figure 2-17: Flow Chart of TX Reset Sequence Where TX Buffer Is Bypassed

and tx_align_err Is Not Used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 2-18: Resetting the Transmitter Where TX Buffer Is Bypassed . . . . . . . . . . . . . . . 93

Figure 2-19: Flow Chart of Receiver Reset Sequence Where RX Buffer Is Used . . . . . . . 94

Figure 2-20: Resetting the Receiver in Digital CDR Mode Where RX Buffer Is Used . . 95

Figure 2-21: Resetting the Receiver in Analog CDR Mode Where RX Buffer Is Used . . 96

Figure 2-22: Flow Chart of Receiver Reset Sequence Where RX Buffer Is Bypassed

Figure 2-23: Resetting the Receiver in Analog CDR Mode Where

RX Buffer Is Bypassed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Figure 2-24: TXRESET for 8-Byte External Data Interface Width . . . . . . . . . . . . . . . . . . . 100

. . . 97

Chapter 3: PCS Digital Design Considerations

Figure 3-1: Transmit Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

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Figure 3-2: Receive Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 3-3: RX Ring Buffer Half-Full Upon Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 3-4: RX Ring Buffer Overflow and Underflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Figure 3-5: Fabric Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Figure 3-6: PCS Bypass Byte Mapping, 8-Byte External Fabric Width . . . . . . . . . . . . . . 107

Figure 3-7: PCS Bypass Byte Mapping, 4-Byte External Fabric Width . . . . . . . . . . . . . . 107

Figure 3-8: 8B/10B Parallel-to-Serial Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Figure 3-9: 4-Byte Serial Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Figure 3-10: 10-Bit TX Data Map with 8B/10B Bypassed . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Figure 3-11: 10-Bit RX Data Map with 8B/10B Bypassed . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure 3-12: 8B/10B Comma Detection Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 3-13: 6-Bit Alignment Mux Position. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 3-14: SONET Alignment Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Figure 3-15: SONET Alignment Sequence (4-Byte External Data Interface Width) . . . 119

Figure 3-16: SONET Alignment Sequence (2-Byte External Data Interface Width) . . . 120

Figure 3-17: Comma Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Figure 3-18: RXSLIDE Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Figure 3-19: Effects of CCCB_ARBITRATOR_DISABLE = TRUE. . . . . . . . . . . . . . . . . . 130

Figure 3-20: Daisy-Chained Transceiver CHBONDI/CHBONDO Buses . . . . . . . . . . . . 131

Figure 3-21: XC4VFX20/XC4VFX60 Device Implementation . . . . . . . . . . . . . . . . . . . . . . . 131

Figure 3-22: Loopback Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Figure 3-23: Digital Receiver Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Figure 3-24: PCS RXCLK Generation, Buffered Mode (Green) . . . . . . . . . . . . . . . . . . . . 136

Chapter 4: PMA Analog Design Considerations

Figure 4-1: Differential Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Figure 4-2: 3-Tap Pre-Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Figure 4-3: Effect of 3-Tap Pre-Emphasis on a Pulse Signal . . . . . . . . . . . . . . . . . . . . . . . 141

Figure 4-4: TX with Minimal Pre-Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Figure 4-5: RX after 36 Inches FR4 and Minimal Pre-Emphasis . . . . . . . . . . . . . . . . . . . . 144

Figure 4-6: TX with Maximal Pre-Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Figure 4-7: RX after 36 Inches FR4 and Maximal Pre-Emphasis . . . . . . . . . . . . . . . . . . . . 146

Figure 4-8: AC Response of Continuous-Time Linear Receiver Equalizer. . . . . . . . . . . 148

Figure 4-9: OOB Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Chapter 5: Cyclic Redundancy Check (CRC)

Figure 5-1: 32-bit CRC Inputs and Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Figure 5-2: 64-Bit to 32-Bit Core Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Figure 5-3: Max Data Rate Example (64-Bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Figure 5-4: Max Data Rate Example (32-Bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Figure 5-5: 16-Bit Transmission, Hold CRC, and Residue of 8-Bit Example . . . . . . . . . 160

Figure 5-6: CRC Generation Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

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Chapter 6: Analog and Board Design Considerations

Figure 6-1: MGT Tile Power and Serial I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Figure 6-2: Internal Receiver AC Coupling with External DC Coupling between

Transmitter and Receiver Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Figure 6-3: Power Supply Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Figure 6-4: Power Filtering Network for One MGT Tile . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Figure 6-5: Layout for Power Filtering Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Figure 6-6: Optimizing Filtering for an MGT Column. . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Figure 6-7: Reference Clock Oscillator Interface (Up to 400 MHz) . . . . . . . . . . . . . . . . . 170

Figure 6-8: Reference Clock VCSO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Figure 6-9: Transmit Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Figure 6-10: Simplified Receive Termination Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Figure 6-11: AC-Coupled Serial Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Figure 6-12: AC Coupling Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Figure 6-13: DC-Coupled Serial Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Figure 6-14: Single-Ended Trace Geometry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Figure 6-15: Obstacle Route Geometry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Figure 6-16: Microstrip Edge-Coupled Differential Pair . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Figure 6-17: Stripline Edge-Coupled Differential Pair. . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Chapter 7: Simulation and Implementation

Chapter 8: Low-Latency Design

Figure 8-1: PCS Receive Clocking Domains and Data Paths. . . . . . . . . . . . . . . . . . . . . . . 192

Figure 8-2: PCS Transmit Clocking Domains and Data Paths . . . . . . . . . . . . . . . . . . . . . 193

Figure 8-3: Using GREFCLK as Synchronization Clock (Use Models TX_2A-H) . . . . . 200

Figure 8-4: TX Low Latency Buffered Mode: Use Models TX_1A, TX_2A . . . . . . . . . . . 202

Figure 8-5: TX Low Latency Buffered Mode: Use Models TX_1B, TX_2B. . . . . . . . . . . . 203

Figure 8-6: TX Low Latency Buffered Mode: Use Models TX_1C, TX_2C . . . . . . . . . . . 204

Figure 8-7: TX Low Latency Buffered Mode: Use Models TX_1D, TX_2D. . . . . . . . . . . 205

Figure 8-8: TX Low Latency Buffered Mode: Use Model TX_2E. . . . . . . . . . . . . . . . . . . . 206

Figure 8-9: TX Low Latency Buffered Mode: Use Model TX_2F. . . . . . . . . . . . . . . . . . . . 207

Figure 8-10: TX Low Latency Buffered Mode: Use Model TX_2G . . . . . . . . . . . . . . . . . . 208

Figure 8-11: TX Low Latency Buffered Mode: Use Model TX_2H . . . . . . . . . . . . . . . . . . 209

Figure 8-12: Using PCS TXCLK as Synchronization Clock (Use Models TX_3A-B) . . . 210

Figure 8-13: TX Low Latency Buffer Bypass Mode: Use Model TX_3A . . . . . . . . . . . . . 212

Figure 8-14: TX Low Latency Buffer Bypass Mode: Use Model TX_3B. . . . . . . . . . . . . . 213

Figure 8-15: TXSYNC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Figure 8-16: RX Low Latency Buffered Mode: Use Model RX_1A . . . . . . . . . . . . . . . . . . 221

Figure 8-17: RX Low Latency Buffered Mode: Use Model RX_1B . . . . . . . . . . . . . . . . . . 222

Figure 8-18: RX Low Latency Buffered Mode: Use Model RX_1C . . . . . . . . . . . . . . . . . . 223

Figure 8-19: RX Low Latency Buffer Bypass Mode: Use Model RX_2A . . . . . . . . . . . . . 225

Figure 8-20: RX Low Latency Buffer Bypass Mode: Use Model RX_2B . . . . . . . . . . . . . 226

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Figure 8-21: RX Low Latency Buffer Bypass Mode: Use Model RX_2C . . . . . . . . . . . . . 227

Figure 8-22: RXSYNC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

Section II:
Board Level Design

Chapter 9: Methodology Overview

Figure 9-1: Two RocketIO MGTs Interconnected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

Chapter 10: PCB Materials and Traces

Figure 10-1: Differential Edge-Coupled Centered Stripline . . . . . . . . . . . . . . . . . . . . . . . 242

Figure 10-2: Differential Edge-Coupled Offset Stripline . . . . . . . . . . . . . . . . . . . . . . . . . . 242

Figure 10-3: Centered Broadside-Coupled Stripline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

Figure 10-4: Differential Microstrip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

Chapter 11: Design of Transitions

Figure 11-1: TDR Signature of Shunt Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

Figure 11-2: TDR Signature of Series Inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

Figure 11-3: Integration of Normalized TDR Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

Figure 11-4: 2D Field Solver Analysis of 5 Mil Trace and 28 Mil Pad . . . . . . . . . . . . . . . 247

Figure 11-5: Transition Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

Figure 11-6: Ansoft HFSS Model of Capacitor with a Pad Clear-Out . . . . . . . . . . . . . . . 248

Figure 11-7: Return Loss Comparison Between 0402 Pad Structures . . . . . . . . . . . . . . . . 248

Figure 11-8: Return Loss Comparison Between 0402 Pad Structures

on Log (Frequency) Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

Figure 11-9: TDR Results Comparing 0402 Pad Structures

with Excess Capacitance Reduced from 840 fF to 70 fF . . . . . . . . . . . . . . . . . . . . . . . . . 249

Figure 11-10: Differential Via Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

Figure 11-11: Differential GSSG Via in 16-layer PCB from Pins L11 and L6. . . . . . . . . 251

Figure 11-12: Simulated Return Loss Comparing Differential and Common-Mode

Losses for L11 and L6 GSSG Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

Figure 11-13: Example Design for 90 Degree Bends in Traces . . . . . . . . . . . . . . . . . . . . . 252

Figure 11-14: Simulated TDR of 45 Degree Bends with Jog-Outs . . . . . . . . . . . . . . . . . . 253

Figure 11-15: Simulated Return Loss of 45 Degree Bends with Jog-Outs. . . . . . . . . . . . 253

Figure 11-16: Simulated Phase Response of 45 Degree Bends with Jog-Outs . . . . . . . . 254

Figure 11-17: 90° Mitered Turns without and with Jog-Outs. . . . . . . . . . . . . . . . . . . . . . . 254

Figure 11-18: Measured TDR of Differential Pair with Four Mitered 90° Turns,

with and without Jog-Outs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

Chapter 12: Guidelines and Examples

Figure 12-1: Differential Via Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

Figure 12-2: BGA Escape Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

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Figure 12-3: Via Structures for BGA Adjacent SIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

Figure 12-4: XENPAK70 Connector Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

Figure 12-5: SMT XFP Connector Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

Figure 12-6: SMT XFP Connector Return Loss Simulation Results . . . . . . . . . . . . . . . . . 264

Figure 12-7: Tyco Z-PACK HM-Zd Press-Fit Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . 265

Figure 12-8: Tyco Z-PACK HM-Zd Press-Fit Connector Internals . . . . . . . . . . . . . . . . . . 265

Figure 12-9: Tyco Z-PACK HM-Zd Press-Fit Connector Design Example . . . . . . . . . . . 266

Figure 12-10: SMT DC Blocking Capacitor Design Example . . . . . . . . . . . . . . . . . . . . . . 267

Section III:
Appendixes

Appendix A: RocketIO Transceiver Timing Model

Figure A-1: RocketIO Multi-Gigabit Transceiver Block Diagram . . . . . . . . . . . . . . . . . . 273

Figure A-2: MGT Timing Relative to Clock Edge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

Appendix B: 8B/10B Valid Characters

Appendix C: Dynamic Reconfiguration Port

Appendix D: Special Analog Functions

Appendix E: Virtex-II Pro/Virtex-II Pro X to Virtex-4 RocketIO

Transceiver Design Migration

Figure E-1: Reference Clock Selection for Each Device . . . . . . . . . . . . . . . . . . . . . . . . . . . 326

Figure E-2: Virtex-II, Virtex-II Pro, and Virtex-4 Power Supply Filtering . . . . . . . . . . . 329

Appendix F: References

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UG076 (v4.1) November 2, 2008

Schedule of Tables

Section I:
FPGA Level Design

Chapter 1: RocketIO Transceiver Overview

Table 1-1: Number of MGT Cores per Device Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 1-2: Communications Standards Supported by the MGT. . . . . . . . . . . . . . . . . . . . . 35

Table 1-3: MGT Protocol Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 1-4: RocketIO MGT CRC Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 1-5: RocketIO MGT PMA Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 1-6: RocketIO MGT PCS Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 1-7: RocketIO MGT General Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 1-8: RocketIO MGT Dynamic Reconfiguration Ports . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 1-9: RocketIO MGT Communications Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 1-10: RocketIO MGT CRC Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 1-11: RocketIO MGT PMA Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 1-12: RocketIO MGT PCS Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 1-13: RocketIO MGT Digital Receiver Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 1-14: MGT Tile Communication Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 1-15: Control/Status Bus Association to Data Bus Byte Paths. . . . . . . . . . . . . . . . . . 60

Chapter 2: Clocking, Timing, and Resets

Table 2-1: MGTCLK Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 2-2: MGT Clock Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 2-3: Clock Selection for Three PLLs in a Tile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 2-4: TX PMA Attribute Values(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 2-5: Supported Transmitter PLL Divider Combinations. . . . . . . . . . . . . . . . . . . . . . 69

Table 2-6: RX PMA Attribute Values(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 2-7: Supported Receiver PLL Divider Combinations. . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 2-8: Supported VCO Operating Frequency Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 2-9: MGT Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Chapter 3: PCS Digital Design Considerations

Table 3-1: Selecting the External Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Table 3-2: Selecting the Internal Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Table 3-3: Fabric Interface Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Table 3-4: 8B/10B Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Table 3-5: Running Disparity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Table 3-6: 8B/10B Bypassed Signal Significance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

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Table 3-7: RXCHARISCOMMA Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Table 3-8: Deserializer Comma Detection Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Table 3-9: 8B/10B Comma Symbol Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Table 3-10: 8B/10B Decoder Byte-Mapped Status Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Table 3-11: SONET Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Table 3-12: SONET Attribute Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Table 3-13: ALIGN_COMMA_WORD Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Table 3-14: Definition of Clock Correction Sequence Bits 9-0. . . . . . . . . . . . . . . . . . . . . . 125

Table 3-15: Clock Correction Sequence/Data Correlation . . . . . . . . . . . . . . . . . . . . . . . . . 125

Table 3-16: Clock Correction Mask Example Settings (No Mask) . . . . . . . . . . . . . . . . . . 125

Table 3-17: Clock Correction Mask Example Settings (Mask Enabled). . . . . . . . . . . . . . 126

Table 3-18: Channel Bond Alignment Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Table 3-19: Maximum Time Required to Process Channel Bond Sequences . . . . . . . . . 128

Table 3-20: Channel Bonding and Clock Correction Character Spacing. . . . . . . . . . . . . 129

Table 3-21: Signal Values for a Pointer Difference Status . . . . . . . . . . . . . . . . . . . . . . . . . 132

Table 3-22: Signal Values for a Channel Bonding Skew . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Table 3-23: Signal Values for Event Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Table 3-24: Loopback Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Table 3-25: Variation of Recovered Clock Period. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Table 3-26: Digital Receiver Attribute Settings (Line Rates ≤ 1.25 Gb/s) . . . . . . . . . . . . . 136

Chapter 4: PMA Analog Design Considerations

Table 4-1: Attributes Controlling Pre-Emphasis Characteristics. . . . . . . . . . . . . . . . . . . . 140

Table 4-2: TXDAT_TAP_DAC and TXPOST_TAP_DAC Settings. . . . . . . . . . . . . . . . . . 141

Table 4-3: RXDIGRX Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Table 4-4: Transmit Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Table 4-5: Receive Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Table 4-6: PLL/Data Frequency Divergence as a Function of Lock and Hysteresis. . . . 151

Table 4-7: RocketIO Transceiver Power Control Description . . . . . . . . . . . . . . . . . . . . . . 151

Table 4-8: PMA Receiver Power Control Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Table 4-9: PMA Power Control Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Table 4-10: Power-Down of TX PMA Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Chapter 5: Cyclic Redundancy Check (CRC)

Table 5-1: Ports for the RX and TX CRC Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Table 5-2: CRC Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Table 5-3: Examples of Data Rates for CRC Calculation(1) . . . . . . . . . . . . . . . . . . . . . . . . 156

Table 5-4: Data Width and Active Data Bus Bits with RXDATA Mapping . . . . . . . . . . 157

Chapter 6: Analog and Board Design Considerations

Table 6-1: Case A Filtering Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Table 6-2: Case B Filtering Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Table 6-3: SelectIO Pin Guidance for XC4VFX60/40/20-FF672. . . . . . . . . . . . . . . . . . . . . . 175

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Table 6-4: SelectIO Pin Guidance for XC4VFX100/60/40-FF1152. . . . . . . . . . . . . . . . . . . . 175

Table 6-5: SelectIO Pin Guidance for XC4VFX140/100-FF1517 . . . . . . . . . . . . . . . . . . . . . 176

Chapter 7: Simulation and Implementation

Table 7-1: GT11_MODE Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Table 7-2: CRC Latency and CRCCLOCKDOUBLE Attribute . . . . . . . . . . . . . . . . . . . . . 181

Table 7-3: LOC Grid and Package Pins Correlation for FF672. . . . . . . . . . . . . . . . . . . . . . 186

Table 7-4: LOC Grid and Package Pins Correlation for FF1152. . . . . . . . . . . . . . . . . . . . . 187

Table 7-5: LOC Grid and Package Pins Correlation for FF1517. . . . . . . . . . . . . . . . . . . . . 188

Table 7-6: Bonded Out MGTCLK Sources for XC4VFX20 . . . . . . . . . . . . . . . . . . . . . . . . . 189

Table 7-7: Bonded Out MGTCLK Sources for XC4VFX40 . . . . . . . . . . . . . . . . . . . . . . . . . 189

Table 7-8: Bonded Out MGTCLK Sources for XC4VFX60 . . . . . . . . . . . . . . . . . . . . . . . . . 189

Table 7-9: Bonded Out MGTCLK Sources for XC4VFX100 . . . . . . . . . . . . . . . . . . . . . . . . 190

Table 7-10: Bonded Out MGTCLK Sources for XC4VFX140 . . . . . . . . . . . . . . . . . . . . . . . 190

Chapter 8: Low-Latency Design

Table 8-1: Latency through Various Receiver Components/Processes

Table 8-2: Latency through Various Transmitter Components/Processes

Table 8-3: RX Low-Latency Ports

Table 8-4: RX Low-Latency Attributes

Table 8-5: TX Low-Latency Ports

Table 8-6: TX Low-Latency Attributes

Table 8-7: TX Use Models: Low-Latency Buffered Mode w/out Channel Deskew . . . . 199

Table 8-8: TX Use Models: Low-Latency Buffered Mode with Channel Deskew . . . . . 201

Table 8-9: TX Use Models: Low-Latency Buffer Bypass w/out Channel Deskew . . . . . 211

Table 8-10: Worst-Case Skew Estimates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

Table 8-11: RX Use Models: Low-Latency Buffered Mode. . . . . . . . . . . . . . . . . . . . . . . . . 220

Table 8-12: RX Use Models: Low-Latency Buffer Bypass Mode . . . . . . . . . . . . . . . . . . . . 224

Table 8-13: Latency for Use Model TX_2B or TX_2F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

Table 8-14: Latency for Use Model TX_3A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

Table 8-15: Latency for Use Model TX_3A Using a 4-Byte Fabric Interface) . . . . . . . . . 231

Table 8-16: Latency for Use Model RX_1B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

Table 8-17: Latency for Use Model RX_2A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

(1,2)

. . . . . . . . . . . 194

(1)

. . . . . . . . . . 195

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Section II:
Board Level Design

Chapter 9: Methodology Overview

Chapter 10: PCB Materials and Traces

Chapter 11: Design of Transitions

Chapter 12: Guidelines and Examples

Table 12-1: Model-Derived Loss for Differential Vias of Various Dimensions . . . . . . 259

Section III:
Appendixes

Appendix A: RocketIO Transceiver Timing Model

Table A-1: MGT Clock Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

Table A-2: RocketIO DCLK Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

Table A-3: RocketIO RXCRCCLK Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . 276

Table A-4: RocketIO TXCRCCLK Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . 277

Table A-5: RocketIO RXUSRCLK Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . 277

Table A-6: RocketIO RXUSRCLK2 Switching Characteristics . . . . . . . . . . . . . . . . . . . . . 278

Table A-7: RocketIO TXUSRCLK Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . 280

Appendix B: 8B/10B Valid Characters

Table B-1: Valid Data Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

Table B-2: Valid Control “K” Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

Appendix C: Dynamic Reconfiguration Port

Table C-1: Dynamic Reconfiguration Port Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

Table C-2: Dynamic Reconfiguration Port Memory Map: MGTA Address 40–44. . . . . 294

Table C-3: Dynamic Reconfiguration Port Memory Map: MGTA Address 45–49. . . . . 295

Table C-4: Dynamic Reconfiguration Port Memory Map: MGTA Address 4A–4E . . . . 296

Table C-5: Dynamic Reconfiguration Port Memory Map: MGTA Address 4F–53 . . . . 297

Table C-6: Dynamic Reconfiguration Port Memory Map: MGTA Address 54–58. . . . . 298

Table C-7: Dynamic Reconfiguration Port Memory Map: MGTA Address 59–5D . . . . 299

Table C-8: Dynamic Reconfiguration Port Memory Map: MGTA Address 5E–62 . . . . 300

Table C-9: Dynamic Reconfiguration Port Memory Map: MGTA Address 63–67. . . . . 301

Table C-10: Dynamic Reconfiguration Port Memory Map: MGTA Address 68–6C . . . 302

Table C-11: Dynamic Reconfiguration Port Memory Map: MGTA Address 6D–71 . . . 303

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Table C-12: Dynamic Reconfiguration Port Memory Map: MGTA Address 72–76. . . . 304

Table C-13: Dynamic Reconfiguration Port Memory Map: MGTA Address 77–7B . . . 305

Table C-14: Dynamic Reconfiguration Port Memory Map: MGTA Address 7C–7F . . . 306

Table C-15: Dynamic Reconfiguration Port Memory Map: MGTB Address 40–44 . . . . 307

Table C-16: Dynamic Reconfiguration Port Memory Map: MGTB Address 45–49 . . . . 308

Table C-17: Dynamic Reconfiguration Port Memory Map: MGTB Address 4A–4E . . . 309

Table C-18: Dynamic Reconfiguration Port Memory Map: MGTB Address 4F–53. . . . 310

Table C-19: Dynamic Reconfiguration Port Memory Map: MGTB Address 54–58 . . . . 311

Table C-20: Dynamic Reconfiguration Port Memory Map: MGTB Address 59–5D . . . 312

Table C-21: Dynamic Reconfiguration Port Memory Map: MGTB Address 5E–62. . . . 313

Table C-22: Dynamic Reconfiguration Port Memory Map: MGTB Address 63–67 . . . . 314

Table C-23: Dynamic Reconfiguration Port Memory Map: MGTB Address 68–6C . . . 315

Table C-24: Dynamic Reconfiguration Port Memory Map: MGTB Address 6D–71 . . . 316

Table C-25: Dynamic Reconfiguration Port Memory Map: MGTB Address 72–76 . . . . 317

Table C-26: Dynamic Reconfiguration Port Memory Map: MGTB Address 77–7B . . . 318

Table C-27: Dynamic Reconfiguration Port Memory Map: MGTB Address 7C–7F . . . 319

Table C-28: PLL Configuration Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320

Appendix D: Special Analog Functions

Table D-1: Register Address Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321

Table D-2: Example RXSELDACTRAN and RXSELDACFIX Combinations. . . . . . . . . 321

Appendix E: Virtex-II Pro/Virtex-II Pro X to Virtex-4 RocketIO

Transceiver Design Migration

Table E-1: MGTs per Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325

Table E-2: Available Clock Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326

Table E-3: Serial Rate Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

Table E-4: Encoding Support and Clock Multipliers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

Table E-5: Power Pin Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328

Table E-6: Termination Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330

Table E-7: CRC Transceiver Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330

Table E-8: Loopback Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330

Table E-9: Status Bus Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331

Table E-10: Signal Optimization Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331

Appendix F: References

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About This Guide

The Virtex ®-4 RocketIO™ MGT User Guide provides the product designer with the detailed
technical information needed to successfully implement the RocketIO MGT in Virtex-4
Platform FPGA designs. For information on the Virtex-II Pro RocketIO and the
Virtex-II Pro X RocketIO X transceivers, see UG024

UG035

MGT Features

RocketIO MGTs have flexible, programmable features that allow a multi-gigabit serial
transceiver to be easily integrated into any Virtex-4 design:

• 622 Mb/s to 6.5 Gb/s data rates

• 8 to 24 transceivers per FPGA

• 3-tap transmitter pre-emphasis (pre-equalization)

• Receiver continuous time equalization

• Optional on-chip AC coupled receiver

• Digital oversampled receiver for data rates up to 1.25 Gb/s

• Receiver signal detect and loss of signal indicator and out-of-band (OOB) signal

• Transmit driver idle state for OOB signaling (both outputs at V

• 8B/10B encoding

• No data encoding (pass-through mode) with digital receiver

• Channel bonding

• Flexible Cyclic Redundancy Check (CRC) generation and checking

• Pins for transmitter and receiver termination voltage

• User reconfiguration using the Dynamic Reconfiguration Port

• Multiple loopback paths

• NRZ signaling

, RocketIO X Transceiver User Guide.

receiver

Preface

, RocketIO Transceiver User Guide, and

)

CM

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Preface: About This Guide

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User Guide Organization

This guide is organized as follows:

Section I: FPGA Level Design

• Chapter 1, “RocketIO Transceiver Overview” – MGT basic architecture and

capabilities. Includes available ports, primitive and modifiable attributes, byte
mapping.

• Chapter 2, “Clocking, Timing, and Resets” – Clock domain architecture, clock ports,

examples for clocking/reset schemes.

• Chapter 3, “PCS Digital Design Considerations” – Top-level architecture and block-

level functions, 8B/10B encoding/decoding, comma detection, channel bonding,
status/event bus, loopback, digital receiver.

• Chapter 4, “PMA Analog Design Considerations” – Serial I/O, output swing and

emphasis, differential receiver, analog functions.

• Chapter 5, “Cyclic Redundancy Check (CRC)”– CRC functionality, latency, timing.

• Chapter 6, “Analog and Board Design Considerations” – Power requirements,

termination options, AC/DC coupling, high-speed trace design.

• Chapter 7, “Simulation and Implementation” – Simulation models/considerations,

implementation tools, debugging and diagnostics, transceiver locations, package pin
assignments.

• Chapter 8, “Low-Latency Design” – Details of designing for minimum latency.

Section II: Board Level Design

• Chapter 9, “Methodology Overview” – Powering, clocking, and coupling MGTs.

• Chapter 10, “PCB Materials and Traces” – Handling PCB and interconnect

characteristics to maximize signal integrity.

• Chapter 11, “Design of Transitions” – Detailed analysis of PCB trace geometries and

their effect on signal integrity, impedance, and differential balance.

• Chapter 12, “Guidelines and Examples” – Practical guidelines for maximizing PCB

design success.

Section III: Appendixes

• Appendix A, “RocketIO Transceiver Timing Model” – Timing parameters associated

with the MGT core.

• Appendix B, “8B/10B Valid Characters” – Valid data and K-character table.

• Appendix C, “Dynamic Reconfiguration Port” – Parallel programming bus for

dynamically configuring the attribute settings. (For advanced users.)

• Appendix D, “Special Analog Functions” – Receiver Sample Phase Adjustment

function.

• Appendix E, “Virtex-II Pro/Virtex-II Pro X to Virtex-4 RocketIO Transceiver Design

Migration” – Important differences to be aware of when migrating designs from

Virtex-II Pro/ Virtex-II Pro X to Virtex-4 FPGAs.

• Appendix F, “References”

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Related Information

For a complete menu of online information resources available on the Xilinx website, visit

http://www.xilinx.com/virtex4/

For a comprehensive listing of available tutorials and resources on network technologies
and communications protocols, visit http://

Additional Resources

For additional information, go to http://support.xilinx.com. The following table lists
some of the resources available on this website. Use the URLs to access these resources
directly.

Resource Description/URL

Tutorials Tutorials covering Xilinx design flows, from design entry to verification

Answer Browser Database of Xilinx solution records

Related Information

.

www.iol.unh.edu/training/.

and debugging

http://support.xilinx.com/support/techsup/tutorials/index.htm

http://support.xilinx.com/xlnx/xil_ans_browser.jsp

Application Notes Descriptions of device-specific design techniques and approaches

Data Sheets Device-specific information on Xilinx device characteristics, including

Problem Solvers Interactive tools that allow the user to troubleshoot design issues

Tech Tips Latest news, design tips, and patch information for the Xilinx design

User Guide Conventions

This document uses the following conventions.

Logical / Mathematical Operators

• The asterisk * when used in a port or attribute name is a wildcard operator indicating

that more than one character could be represented.

Example: CLK_COR_SEQ_1_* could be CLK_COR_SEQ_1_1, CLK_COR_SEQ_1_2, etc.

• !

=

NOT EQUAL TO

•

≠

NOT EQUAL TO

•

≤

LESS THAN OR EQUAL TO

≥

•

•

GREATER THAN OR EQUAL TO

≈

APPROXIMATELY EQUAL TO

http://support.xilinx.com/apps/appsweb.htm

readback, boundary scan, configuration, length count, and debugging

http://support.xilinx.com/xlnx/xweb/xil_publications_index.jsp

http://support.xilinx.com/support/troubleshoot/psolvers.htm

environment

http://www.support.xilinx.com/xlnx/xil_tt_home.jsp

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Port and Attribute Names

All input and output ports of the RocketIO transceiver primitives are denoted in upper­case letters. Attributes of the RocketIO transceiver can be denoted in upper-case letters
with underscores or all upper-case letters.

When assumed to be the same frequency, RXUSRCLK and TXUSRCLK are referred to as
USRCLK and can be used interchangeably. This also holds true for RXUSRCLK2,
TXUSRCLK2, and USRCLK2.

Comma Definition

A comma is a “K” character used by the transceiver to align the serial data on a
byte/half-word boundary (depending on the protocol used), so that the serial data is
correctly decoded into parallel data.

Jitter Definition

Jitter is defined as the short-term variations of significant instants of a signal from their
ideal positions in time (ITU). Jitter is typically expressed in a decimal fraction of Unit
Interval (UI), for example, 0.3 UI.

Total Jitter (DJ + RJ) Definition

• Deterministic Jitter (DJ) – DJ is data pattern dependant jitter, attributed to a unique

source (for example, Inter Symbol Interference (ISI) due to loss effects of the media).
DJ is linearly additive.

• Random Jitter (RJ) – RJ is due to stochastic sources, such as thermal and flicker noise,

and so on. RJ is additive as the sum of squares and follows a normal distribution.

MGT Definition

The term MGT refers to the Virtex-4 RocketIO Multi-Gigabit Transceiver. Previous
generations are explicitly called out: Virtex-II Pro RocketIO or Virtex-II Pro X RocketIO X.

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