R
Virtex-4 RocketIO
Multi-Gigabit
Transceiver
User Guide
UG076 (v4.1) November 2, 2008
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R
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Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008
Revision History
The following table shows the revision history for this document.
Date Version Revision
03/01/05 1.0 Xilinx Initial Release.
03/10/05 1.1 Modified “Power Supply Requirements” in Chapter 6 and Table 6-1, page 176.
04/07/05 1.2 General typographical edits. Revised Ta bl e 2 -2 , Tab le 2- 8, Figure 2-7, Figure 2-8,
Figure 2-11, Figure 2-12, Figure 6-4, Figure 6-8, and Figure E-2. Added “Resetting the
Transceiver,” page 85 and Figure 2-12. Edited Ta ble 4 -1 , Tab le 4- 3, Ta bl e 4- 5 , Tab le 7 -3,
Ta bl e 7 -4 , Tab le 7- 5, Ta bl e 7 -6 , Ta bl e A -1 , Tab le C -1 4, and Ta bl e C- 2 8.
07/01/05 1.3 Changes in Figure 2-4, Figure 2-9, Figure 3-14, Figure 4-9, Figure 6-4 and Figure 6-8.
Revised Ta bl e 3 -2 3 and Ta bl e 3 -2 4. Added Ta b le 5 - 5, revised Ta bl e 5 -5 . Changes to
Ta bl e 7 -4 , Tab le 7- 5, Ta bl e 7 -6 . For clarity, revised all the notes in the tables in
Appendix C. Added a default value to DCDR_FILTER in Appendix F.
01/16/06 2.0 Major revision. All material completely revised and updated, substantial new material
added.
05/23/06 3.0 Major revision. Chapter 1: All Ports/Attributes tables reviewed and expanded. Chapter
2: New Reset section. Low-latency material removed. Chapter 8: New. Chapters 9-12
(Section II): New.
07/19/06 3.1 • Ta bl e 1 -3 : Corrected maximum reference clock frequency to 644 MHz for Aurora
protocols.
Ta bl e 1 -11 : Deleted instruction to set TXTERMTRIM to 0000.
•
• Chapter 2, section “Resetting the Transceiver”:
♦ Modified all references to LOCKUPDATE cycles to REFCLK cycles.
♦ Corrected state definitions in all flowcharts.
• Chapter 3, section “Channel Bonding”: Rewritten and enlarged.
• Chapter 8, section “RXSYNC”:
♦ Modified all references to LOCKUPDATE cycles to REFCLK cycles.
• Ta bl e C -6 and Tab le C- 19 : Corrected TXTERMTRIM default state to 1100.
09/29/06 3.2 • Removed references to the FF1760 package. Not supported.
• Removed references to 1-byte and 2-byte external fabric widths for PCS Bypass mode.
Not supported.
• Removed references to OC-48 protocol. Not supported.
• Removed references to Digital ReceiverLoopback. Not supported.
• Removed former Tables 4-6, 4-7, and Figure 4-12 from section “Out-of-Band (OOB)
Signals.”
• Added RX/TXFDCAL_CLOCK_DIVIDE setting of FOUR for RX/TX calibration with
reference clock speeds over 500 MHz (Tab le 4-4 , Tab le 4 -5 ).
• Added in several places throughout the Guide the recommendation to use the
RocketIO Wizard for MGT configuration.
• Added several new sections and diagrams to Chapter 6, “Analog and Board Design
Considerations” relating to powering MGTs. Existing material edited and updated.
• Added new section “SelectIO-to-MGT Crosstalk”to Chapter 6, “Analog and Board
Design Considerations.”
• Added Appendix D, “Special Analog Functions.” Previously part of Chapter 4.
UG076 (v4.1) November 2, 2008 www.xilinx.com Virtex-4 RocketIO MGT User Guide
Date Version Revision
08/17/07 4.0 Major revision. All material completely revised and updated.
• General typographical edits.
• Added no data encoding and NRZ signaling to “MGT Features.”
• Removed 64B/66B encoding from Preface, Chapter 1, Chapter 2, Chapter 3,
Chapter 4, Chapter 6, Chapter 7, and Appendix E.
• Removed Decision Feedback Equalizer (DFE) from Preface and Chapter 4.
• Changed ring buffer size to 13x64 in Figure 2-7, Figure 3-2, Figure 8-1, and Figure 8-16
to Figure 8-21.
Chapter 1:
• Added notes to Figure 1-1.
• In Ta bl e 1 -3 ; modified reference clock frequency values, added notes 2 through 5,
added new Aurora Transmit and Receive rows. Removed 64B/66B, OIF SxI-5, OIF SFI
4.2, and Aurora 64B/66B protocols.
• Rewrote text before Tab le 1 -4 .
• Modified port definitions in Ta bl e 1 -5 .
• Modified port definitions and end note in Tab le 1- 6.
• Modified attribute descriptions, and added RXCMADJ, POWER_ENABLE,
RXCPSEL, and TXCPSEL attributes in Ta bl e 1 -11 .
• Modified attribute descriptions and added end note after Ta bl e 1-1 2 and Ta bl e 1 -13 .
Chapter 2:
• Added note to Figure 2-1.
• Modified description of SYNCLK1IN and SYNCLK2IN, and added I/O column to
Ta bl e 2 -1 .
• Removed support of RXPCSHCLKOUT, TXPCSHCLKOUT, and RXMCLK in
Ta bl e 2 -2 .
• Modified notes before Figure 2-4, Figure 2-5
and Figure 2-9.
• Modified notes in Figure 2-4 and Figure 2-5.
• Added Tab le 2 -5 and Tab le 2 -7 .
• Added “RX and TX PLL Voltage-Controlled Oscillator (VCO) Operating Frequency.”
• Modified label in and added note to Figure 2-7.
• Added note to Figure 2-8.
• Modified labels in Figure 2-9.
• Modified Figure 2-11.
• Removed 64B/66B Scrambler/Descrambler and 10G BASE R
Gearbox/Decode/Block Sync from “TXRESET” and “RXRESET.”
• Modified last step in “Receive Reset Sequence: RX Buffer Bypassed.”
Chapter 3:
• Added note to Figure 3-1.
• Modified label in and added note to Figure 3-2.
• Modified overflow and underflow labels in Figure 3-3 and Figure 3-4.
• Relocated “RX Fabric Interface and Channel Bonding.”
• Modified text in “8B/10B Encoding/Decoding.”
• Modified text in paragraph before Figure 3-4.
• Removed 64B/66B from Tab le 3- 4.
• Removed PCS_BIT_SLIP from “Symbol Alignment and Detection (Comma
Detection).”
Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008
Date Version Revision
08/17/07
(cont’d)
4.0
(cont’d)
• Modified “10-Bit Alignment for 8B/10B Encoded Data.”
• Expanded SONET alignment sequence figure into Figure 3-15 and Figure 3-16.
• Removed support of RXSYNC functionality in “RXSLIDE.”
• Modified Figure 3-18.
• Modified last paragraph of “Clock Correction Sequences.”
• Removed RXBLOCKSYNC64B66BUSE column, last two rows (64B/66B), and note
from Tab l e 3- 1 4.
• Modified Figure 3-24.
• Modified nominal frequency and period in text following Ta bl e 3 -2 5.
• Removed Clocking in Buffer Bypass Mode section from Chapter 3.
• Removed Buffer Bypass Mode column from Ta bl e 3 -2 6 .
Chapter 4:
• Modified attribute definitions in Tab le 4 -1 .
• Removed description of TXUSRCLK from “Clock and Data Recovery.”
• Corrected references to RXAFEEQ in Figure 4-8.
• Removed description of MGT from “POWERDOWN.”
Chapter 5:
• Added description of CRC wakeup in “Latency and Timing.”
Chapter 6:
• Modified Figure 6-1 and Figure 6-4.
• Corrected equation references in “Determining Power Supply Budget.”
• Added additional bullet item to “Powering Unused MGTs.”
• Modified text in “Reference Clock” and Figure 6-7.
Chapter 7:
• Added “Reference Clock Period Restriction.”
• Rewrote description of TXENOOB and RXSIGDET in “Out-of-Band (OOB)
Signaling.”
• Deleted TXENOOB and RXSIGDET, and added RXSYNC to “MGT Ports that Cannot
Be Simulated.”
Chapter 8:
• Modified note 2 after Ta bl e 8- 1.
• Changed port name to RXBLOCKSYNC64B66BUSE in Ta bl e 8 -3 , Ta bl e 8 -11 , and
Ta bl e 8 -1 2.
• Added notes to say that 64B/66B encoding/decoding is not supported in Figure 8-1,
Figure 8-2, Figure 8-4 to Figure 8-11, Figure 8-13, Figure 8-14, Figure 8-16 to
Figure 8-21, Tab le 8 -1 to Tab l e 8- 9 , Tab le 8 -1 3 to Tab le 8 -17 .
• Added item 5 to “Usage.”
Chapter 9:
• Expanded description in “Clock Traces.”
Chapter 10:
• Rewrote “Optimal Cable Length.”
Appendix A:
• Removed 64B/66B from and modified descriptions of TXOUTCLK1/2 and
RXRECCLK1/2 in Ta bl e A- 1.
• Added notes to Figure A-1, Ta bl e A- 6, and Ta bl e A -7 .
UG076 (v4.1) November 2, 2008 www.xilinx.com Virtex-4 RocketIO MGT User Guide
Date Version Revision
08/17/07
(cont’d)
4.0
(cont’d)
Appendix C:
• Modified Tab le C -2 to Tab le C - 6, Ta bl e C- 8 to Tab le C- 11 , Tab le C -1 3 to Tab le C -1 5,
Ta bl e C -1 7 to Tab le C -2 0, Ta bl e C -2 3, Tab le C -2 4, Ta bl e C -2 6, and Ta bl e C -2 7.
• Modified notes 1 and 3 after Ta bl e C -6 and Ta bl e C -2 5 and expanded note 4 after
Ta bl e C -6 .
Appendix D:
• Expanded note in “Receiver Sample Phase Adjustment.”
Appendix E:
• Removed 64B/66B encoding scheme from Virtex-4 devices and added note 4 in
Ta bl e E -4 .
• Modified Figure E-2.
• Modified text in “Loopback.”
• Removed section on TKERR[0] vs. TKERR[3].
• Removed section on clock correction and channel bonding sequences and
accompanying table.
• Removed discrete equalization row from Tab le E -1 0.
Modified references in Appendix F.
11/02/08 4.1 Added a new paragraph regarding 2.5V power and filtering to “Powering Unused
MGTs” in Chapter 6.
Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008
Table of Contents
Preface: About This Guide
MGT Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
User Guide Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Related Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
User Guide Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Logical / Mathematical Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Port and Attribute Names. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Comma Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Jitter Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Total Jitter (DJ + RJ) Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
MGT Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Typographical. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Section I:
FPGA Level Design
Chapter 1: RocketIO Transceiver Overview
Basic Architecture and Capabilities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Configuring the RocketIO MGT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Available Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Byte Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Chapter 2: Clocking, Timing, and Resets
Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Tile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
MGT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
GT11CLK_MGT and Reference Clock Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
MGT Clock Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Common Reference Clock Use Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
High-Speed Dedicated MGT Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Fabric Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
PMA Transmit Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
PMA Receive Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
RX and TX PLL Voltage-Controlled Oscillator (VCO) Operating Frequency . . . . . . 72
PMA/PCS Clocking Domains and Data Paths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
PMA Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Common MGT Clocking Use Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Setting the Clocking Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Virtex-4 RocketIO MGT User Guide www.xilinx.com 7
UG076 (v4.1) November 2, 2008
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Special Clocking Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
RXCLKSTABLE and TXCLKSTABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
TXPMARESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
RXPMARESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
TXRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
RXRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
CRC Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Resetting the Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Transmit Reset Sequence: TX Buffer Used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Transmit Reset Sequence: TX Buffer Bypassed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Receive Reset Sequence: RX Buffer Used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Receive Reset Sequence: RX Buffer Bypassed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Reset Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
RX Reset Sequence Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Chapter 3: PCS Digital Design Considerations
Top-Level Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Transmit Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Receive Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Fabric Interface Synchronicity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
RX Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
External Bus Width Configuration (Fabric Interface). . . . . . . . . . . . . . . . . . . . . . . . . . 103
Internal Bus Width Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Fabric Interface Functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
PCS Bypass Byte Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
8B/10B Encoding/Decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
TXCHARDISPVAL and TXCHARDISPMODE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
TXCHARISK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
TXRUNDISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
TXKERR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
RXCHARISK and RXRUNDISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
RXDISPERR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
RXNOTINTABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
RXCHARISCOMMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Non-Standard Running Disparity Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Transmitting Vitesse Channel Bonding Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Receiving Vitesse Channel Bonding Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Symbol Alignment and Detection (Comma Detection) . . . . . . . . . . . . . . . . . . . . . . 116
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
8-Bit / 10-Bit Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
10-Bit Alignment for 8B/10B Encoded Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Determining Barrel Shifter Position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
SONET Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Alignment Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Byte Alignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
ALIGN_COMMA_WORD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
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RXSLIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Clock Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Append/Remove Idle Clock Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Clock Correction Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
CLK_COR_SEQ_1_MASK, CLK_COR_SEQ_2_MASK,
CLK_COR_SEQ_LEN Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Determining Correct CLK_COR_MIN_LAT and CLK_COR_MAX_LAT . . . . . . . . 126
Channel Bonding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
CCCB_ARBITRATOR_DISABLE = TRUE, CLOCK_CORRECTION_USE = FALSE . . 127
CCCB_ARBITRATOR_DISABLE = FALSE, CLOCK_CORRECTION_USE = TRUE . . 127
CCCB_ARBITRATOR_DISABLE Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
CHAN_BOND_SEQ_1_MASK, CHAN_BOND_SEQ_2_MASK,
CHAN_BOND_SEQ_LEN, CHAN_BOND_SEQ_*_* Attributes
Disable Channel Bonding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Setting CHAN_BOND_LIMIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Implementation Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
RX Fabric Interface and Channel Bonding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
. . . . . . . . . . . . . . . 130
Status and Event Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Status Indication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Event Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
RXBUFERR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
TXBUFERR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
LOOPBACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Digital Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Clocking in Buffered Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Chapter 4: PMA Analog Design Considerations
Serial I/O Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Differential Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Output Swing and Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Differential Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Clock and Data Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Receiver Lock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Receive Equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Special Analog Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Out-of-Band (OOB) Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Calibration for the PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
POWERDOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
RXDCCOUPLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
RXPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
TXPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Chapter 5: Cyclic Redundancy Check (CRC)
Functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Handling End-of-Packet Residue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Latency and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
64-Bit Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
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32-Bit Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
16-Bit Transmission, Hold CRC, and Residue of 8-Bit Example. . . . . . . . . . . . . . . . . 160
Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Chapter 6: Analog and Board Design Considerations
Physical Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Power Conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Power Supply Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Determining Power Supply Budget . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Voltage Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Powering Unused MGTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
AC and DC Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
SelectIO-to-MGT Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
High-Speed Serial Trace Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Routing Serial Traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Differential Trace Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Chapter 7: Simulation and Implementation
Model Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Simulation Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
SmartModels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
HSPICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
SmartModel Simulation Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
After Reset or Power-Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Reference Clock Period Restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
RXP/RXN Period Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Reset After Changing Clock Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Out-of-Band (OOB) Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
1-Byte or 2-Byte Fabric Interface Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Toggling GSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Simulating in Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Simulating in VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Phase-Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Frequency Calibration and Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
SONET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
8B/10B Encoding/Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
MGT Ports that Cannot Be Simulated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
TXBUFFERR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Transceiver Location and Package Pin Relation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
MGT Package Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Chapter 8: Low-Latency Design
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
PCS Clocking Domains and Data Paths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
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Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
PCS Data Path Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Synchronizing the PMA/PCS Clocks in Low-Latency Modes . . . . . . . . . . . . . . . . 197
Transmit Latency and Output Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
TX Low-Latency Buffered Mode without Channel Deskew . . . . . . . . . . . . . . . . . . . . 198
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Use Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
TX Low Latency Buffered Mode with Channel Deskew . . . . . . . . . . . . . . . . . . . . . . . 200
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Use Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
TX Low Latency Buffer Bypass Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Use Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
TXSYNC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
TX Channel Skew using TXSYNC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Worst-Case TX Skew Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Synchronization Clock = PCS TXCLK, TXPHASESEL = TRUE . . . . . . . . . . . . . . . . . . 215
Synchronization Clock = GREFCLK, TXPHASESEL = FALSE . . . . . . . . . . . . . . . . . . . 216
TX Skew Estimation Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
1.25 Gbit/s, Synchronization Clock = PCS TXCLK, TXPHASESEL = TRUE. . . . . . . . . 217
1.25 Gbit/s, Synchronization Clock = GREFCLK, TXPHASESEL = FALSE . . . . . . . . . 217
6.5 Gbit/s, Synchronization Clock = PCS TXCLK, TXPHASESEL = TRUE . . . . . . . . . 217
6.5 Gbit/s, Synchronization Clock = GREFCLK, TXPHASESEL = FALSE . . . . . . . . . . 217
RX Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
RX Low Latency Buffered Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Use Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
RX Low Latency Buffer Bypass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
RXSYNC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
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Restrictions on Low Latency Buffer Bypass Modes. . . . . . . . . . . . . . . . . . . . . . . . . . 229
Example of a Reduced-Latency System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
XAUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
System Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
TX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
RX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Section II:
Board Level Design
Chapter 9: Methodology Overview
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Powering the RocketIO MGTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Reference Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Clock Traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Coupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
DC Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
AC Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
External Capacitor Value Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Chapter 10: PCB Materials and Traces
How Fast is Fast?. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
PCB Losses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Relative Permittivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Loss Tangent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Skin Effect and Resistive Losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Choosing the Substrate Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Traces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Trace Geometry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Trace Characteristic Impedance Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Trace Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Plane Splits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Simulating Lossy Transmission Lines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Optimal Cable Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Skew Between Conductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Chapter 11: Design of Transitions
Excess Capacitance and Inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Time Domain Reflectometry (TDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
SMT Pads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Differential Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
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Microstrip/Stripline Bends . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
BGA Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
SMA Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Chapter 12: Guidelines and Examples
Summary of Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Channel Budgeting Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
BGA Escape Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
SMT XENPAK70 Connector Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
SMT XFP Connector Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Tyco Z-PACK HM-Zd Connector Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . 264
SMT DC Blocking Capacitor Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Section III:
Appendixes
Appendix A: RocketIO Transceiver Timing Model
Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Timing Diagram and Timing Parameter Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Input Setup/Hold Times Relative to Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Clock to Output Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Clock Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Appendix B: 8B/10B Valid Characters
Valid Data and Control Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Appendix C: Dynamic Reconfiguration Port
Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Appendix D: Special Analog Functions
Receiver Sample Phase Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Appendix E: Virtex-II Pro/Virtex-II Pro X to Virtex-4 RocketIO
Transceiver Design Migration
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
Primary Differences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
MGTs per Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
Serial Rate Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
Encoding Support and Clock Multipliers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
Flexibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
Board Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
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Power Supply Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
Other Minor Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
Serialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
RXSTATUS Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
Pre-emphasis, Differential Swing, and Equalization . . . . . . . . . . . . . . . . . . . . . . . . 331
Appendix F: References
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Schedule of Figures
Section I:
FPGA Level Design
Chapter 1: RocketIO Transceiver Overview
Figure 1-1: RocketIO Multi-Gigabit Transceiver Block Diagram. . . . . . . . . . . . . . . . . . . . 36
Chapter 2: Clocking, Timing, and Resets
Figure 2-1: MGT Column Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 2-2: High-Speed Dedicated Clocks (GT11CLK_MGT Instance) . . . . . . . . . . . . . . 66
Figure 2-3: REFCLK and GREFCLK Options for an MGT Tile . . . . . . . . . . . . . . . . . . . . . 67
Figure 2-4: MGT Transmit Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 2-5: MGT Receive Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 2-6: Transmitter and Receiver Line Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 2-7: PCS Receive Clocking Domains and Datapaths . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 2-8: PCS Transmit Clocking Domains and Datapaths . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 2-9: Low-Latency Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 2-10: DCM Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 2-11: Receive Clocking Decision Flow (Page 1 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 2-11 (Cont’d): Receive Clocking Decision Flow (Page 2 of 2). . . . . . . . . . . . . . . . . . 79
Figure 2-12: Transmit Clocking Decision Flow (Page 1 of 2). . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 2-12 (Cont’d): Transmit Clocking Decision Flow (Page 2 of 2) . . . . . . . . . . . . . . . . 81
Figure 2-13: External PLL Locked Signal for MGT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 2-14: Flow Chart of TX Reset Sequence Where TX Buffer Is Used . . . . . . . . . . . . 86
Figure 2-15: Resetting the Transmitter Where TX Buffer Is Used . . . . . . . . . . . . . . . . . . . 87
Figure 2-16: Flow Chart of TX Reset Sequence Where TX Buffer Is Bypassed . . . . . . . . 88
Figure 2-17: Flow Chart of TX Reset Sequence Where TX Buffer Is Bypassed
and tx_align_err Is Not Used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 2-18: Resetting the Transmitter Where TX Buffer Is Bypassed . . . . . . . . . . . . . . . 93
Figure 2-19: Flow Chart of Receiver Reset Sequence Where RX Buffer Is Used . . . . . . . 94
Figure 2-20: Resetting the Receiver in Digital CDR Mode Where RX Buffer Is Used . . 95
Figure 2-21: Resetting the Receiver in Analog CDR Mode Where RX Buffer Is Used . . 96
Figure 2-22: Flow Chart of Receiver Reset Sequence Where RX Buffer Is Bypassed
Figure 2-23: Resetting the Receiver in Analog CDR Mode Where
RX Buffer Is Bypassed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 2-24: TXRESET for 8-Byte External Data Interface Width . . . . . . . . . . . . . . . . . . . 100
. . . 97
Chapter 3: PCS Digital Design Considerations
Figure 3-1: Transmit Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
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Figure 3-2: Receive Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 3-3: RX Ring Buffer Half-Full Upon Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 3-4: RX Ring Buffer Overflow and Underflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 3-5: Fabric Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 3-6: PCS Bypass Byte Mapping, 8-Byte External Fabric Width . . . . . . . . . . . . . . 107
Figure 3-7: PCS Bypass Byte Mapping, 4-Byte External Fabric Width . . . . . . . . . . . . . . 107
Figure 3-8: 8B/10B Parallel-to-Serial Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 3-9: 4-Byte Serial Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 3-10: 10-Bit TX Data Map with 8B/10B Bypassed . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 3-11: 10-Bit RX Data Map with 8B/10B Bypassed . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 3-12: 8B/10B Comma Detection Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 3-13: 6-Bit Alignment Mux Position. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 3-14: SONET Alignment Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 3-15: SONET Alignment Sequence (4-Byte External Data Interface Width) . . . 119
Figure 3-16: SONET Alignment Sequence (2-Byte External Data Interface Width) . . . 120
Figure 3-17: Comma Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 3-18: RXSLIDE Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 3-19: Effects of CCCB_ARBITRATOR_DISABLE = TRUE. . . . . . . . . . . . . . . . . . 130
Figure 3-20: Daisy-Chained Transceiver CHBONDI/CHBONDO Buses . . . . . . . . . . . . 131
Figure 3-21: XC4VFX20/XC4VFX60 Device Implementation . . . . . . . . . . . . . . . . . . . . . . . 131
Figure 3-22: Loopback Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Figure 3-23: Digital Receiver Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Figure 3-24: PCS RXCLK Generation, Buffered Mode (Green) . . . . . . . . . . . . . . . . . . . . 136
Chapter 4: PMA Analog Design Considerations
Figure 4-1: Differential Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 4-2: 3-Tap Pre-Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Figure 4-3: Effect of 3-Tap Pre-Emphasis on a Pulse Signal . . . . . . . . . . . . . . . . . . . . . . . 141
Figure 4-4: TX with Minimal Pre-Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Figure 4-5: RX after 36 Inches FR4 and Minimal Pre-Emphasis . . . . . . . . . . . . . . . . . . . . 144
Figure 4-6: TX with Maximal Pre-Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Figure 4-7: RX after 36 Inches FR4 and Maximal Pre-Emphasis . . . . . . . . . . . . . . . . . . . . 146
Figure 4-8: AC Response of Continuous-Time Linear Receiver Equalizer. . . . . . . . . . . 148
Figure 4-9: OOB Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Chapter 5: Cyclic Redundancy Check (CRC)
Figure 5-1: 32-bit CRC Inputs and Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 5-2: 64-Bit to 32-Bit Core Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Figure 5-3: Max Data Rate Example (64-Bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 5-4: Max Data Rate Example (32-Bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Figure 5-5: 16-Bit Transmission, Hold CRC, and Residue of 8-Bit Example . . . . . . . . . 160
Figure 5-6: CRC Generation Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
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Chapter 6: Analog and Board Design Considerations
Figure 6-1: MGT Tile Power and Serial I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Figure 6-2: Internal Receiver AC Coupling with External DC Coupling between
Transmitter and Receiver Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Figure 6-3: Power Supply Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Figure 6-4: Power Filtering Network for One MGT Tile . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 6-5: Layout for Power Filtering Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 6-6: Optimizing Filtering for an MGT Column. . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Figure 6-7: Reference Clock Oscillator Interface (Up to 400 MHz) . . . . . . . . . . . . . . . . . 170
Figure 6-8: Reference Clock VCSO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 6-9: Transmit Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 6-10: Simplified Receive Termination Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 6-11: AC-Coupled Serial Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Figure 6-12: AC Coupling Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Figure 6-13: DC-Coupled Serial Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Figure 6-14: Single-Ended Trace Geometry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Figure 6-15: Obstacle Route Geometry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Figure 6-16: Microstrip Edge-Coupled Differential Pair . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Figure 6-17: Stripline Edge-Coupled Differential Pair. . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Chapter 7: Simulation and Implementation
Chapter 8: Low-Latency Design
Figure 8-1: PCS Receive Clocking Domains and Data Paths. . . . . . . . . . . . . . . . . . . . . . . 192
Figure 8-2: PCS Transmit Clocking Domains and Data Paths . . . . . . . . . . . . . . . . . . . . . 193
Figure 8-3: Using GREFCLK as Synchronization Clock (Use Models TX_2A-H) . . . . . 200
Figure 8-4: TX Low Latency Buffered Mode: Use Models TX_1A, TX_2A . . . . . . . . . . . 202
Figure 8-5: TX Low Latency Buffered Mode: Use Models TX_1B, TX_2B. . . . . . . . . . . . 203
Figure 8-6: TX Low Latency Buffered Mode: Use Models TX_1C, TX_2C . . . . . . . . . . . 204
Figure 8-7: TX Low Latency Buffered Mode: Use Models TX_1D, TX_2D. . . . . . . . . . . 205
Figure 8-8: TX Low Latency Buffered Mode: Use Model TX_2E. . . . . . . . . . . . . . . . . . . . 206
Figure 8-9: TX Low Latency Buffered Mode: Use Model TX_2F. . . . . . . . . . . . . . . . . . . . 207
Figure 8-10: TX Low Latency Buffered Mode: Use Model TX_2G . . . . . . . . . . . . . . . . . . 208
Figure 8-11: TX Low Latency Buffered Mode: Use Model TX_2H . . . . . . . . . . . . . . . . . . 209
Figure 8-12: Using PCS TXCLK as Synchronization Clock (Use Models TX_3A-B) . . . 210
Figure 8-13: TX Low Latency Buffer Bypass Mode: Use Model TX_3A . . . . . . . . . . . . . 212
Figure 8-14: TX Low Latency Buffer Bypass Mode: Use Model TX_3B. . . . . . . . . . . . . . 213
Figure 8-15: TXSYNC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Figure 8-16: RX Low Latency Buffered Mode: Use Model RX_1A . . . . . . . . . . . . . . . . . . 221
Figure 8-17: RX Low Latency Buffered Mode: Use Model RX_1B . . . . . . . . . . . . . . . . . . 222
Figure 8-18: RX Low Latency Buffered Mode: Use Model RX_1C . . . . . . . . . . . . . . . . . . 223
Figure 8-19: RX Low Latency Buffer Bypass Mode: Use Model RX_2A . . . . . . . . . . . . . 225
Figure 8-20: RX Low Latency Buffer Bypass Mode: Use Model RX_2B . . . . . . . . . . . . . 226
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Figure 8-21: RX Low Latency Buffer Bypass Mode: Use Model RX_2C . . . . . . . . . . . . . 227
Figure 8-22: RXSYNC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Section II:
Board Level Design
Chapter 9: Methodology Overview
Figure 9-1: Two RocketIO MGTs Interconnected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Chapter 10: PCB Materials and Traces
Figure 10-1: Differential Edge-Coupled Centered Stripline . . . . . . . . . . . . . . . . . . . . . . . 242
Figure 10-2: Differential Edge-Coupled Offset Stripline . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Figure 10-3: Centered Broadside-Coupled Stripline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Figure 10-4: Differential Microstrip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Chapter 11: Design of Transitions
Figure 11-1: TDR Signature of Shunt Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Figure 11-2: TDR Signature of Series Inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Figure 11-3: Integration of Normalized TDR Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Figure 11-4: 2D Field Solver Analysis of 5 Mil Trace and 28 Mil Pad . . . . . . . . . . . . . . . 247
Figure 11-5: Transition Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Figure 11-6: Ansoft HFSS Model of Capacitor with a Pad Clear-Out . . . . . . . . . . . . . . . 248
Figure 11-7: Return Loss Comparison Between 0402 Pad Structures . . . . . . . . . . . . . . . . 248
Figure 11-8: Return Loss Comparison Between 0402 Pad Structures
on Log (Frequency) Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Figure 11-9: TDR Results Comparing 0402 Pad Structures
with Excess Capacitance Reduced from 840 fF to 70 fF . . . . . . . . . . . . . . . . . . . . . . . . . 249
Figure 11-10: Differential Via Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Figure 11-11: Differential GSSG Via in 16-layer PCB from Pins L11 and L6. . . . . . . . . 251
Figure 11-12: Simulated Return Loss Comparing Differential and Common-Mode
Losses for L11 and L6 GSSG Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Figure 11-13: Example Design for 90 Degree Bends in Traces . . . . . . . . . . . . . . . . . . . . . 252
Figure 11-14: Simulated TDR of 45 Degree Bends with Jog-Outs . . . . . . . . . . . . . . . . . . 253
Figure 11-15: Simulated Return Loss of 45 Degree Bends with Jog-Outs. . . . . . . . . . . . 253
Figure 11-16: Simulated Phase Response of 45 Degree Bends with Jog-Outs . . . . . . . . 254
Figure 11-17: 90° Mitered Turns without and with Jog-Outs. . . . . . . . . . . . . . . . . . . . . . . 254
Figure 11-18: Measured TDR of Differential Pair with Four Mitered 90° Turns,
with and without Jog-Outs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Chapter 12: Guidelines and Examples
Figure 12-1: Differential Via Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Figure 12-2: BGA Escape Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
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Figure 12-3: Via Structures for BGA Adjacent SIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Figure 12-4: XENPAK70 Connector Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Figure 12-5: SMT XFP Connector Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Figure 12-6: SMT XFP Connector Return Loss Simulation Results . . . . . . . . . . . . . . . . . 264
Figure 12-7: Tyco Z-PACK HM-Zd Press-Fit Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Figure 12-8: Tyco Z-PACK HM-Zd Press-Fit Connector Internals . . . . . . . . . . . . . . . . . . 265
Figure 12-9: Tyco Z-PACK HM-Zd Press-Fit Connector Design Example . . . . . . . . . . . 266
Figure 12-10: SMT DC Blocking Capacitor Design Example . . . . . . . . . . . . . . . . . . . . . . 267
Section III:
Appendixes
Appendix A: RocketIO Transceiver Timing Model
Figure A-1: RocketIO Multi-Gigabit Transceiver Block Diagram . . . . . . . . . . . . . . . . . . 273
Figure A-2: MGT Timing Relative to Clock Edge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Appendix B: 8B/10B Valid Characters
Appendix C: Dynamic Reconfiguration Port
Appendix D: Special Analog Functions
Appendix E: Virtex-II Pro/Virtex-II Pro X to Virtex-4 RocketIO
Transceiver Design Migration
Figure E-1: Reference Clock Selection for Each Device . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
Figure E-2: Virtex-II, Virtex-II Pro, and Virtex-4 Power Supply Filtering . . . . . . . . . . . 329
Appendix F: References
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UG076 (v4.1) November 2, 2008
Schedule of Tables
Section I:
FPGA Level Design
Chapter 1: RocketIO Transceiver Overview
Table 1-1: Number of MGT Cores per Device Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 1-2: Communications Standards Supported by the MGT. . . . . . . . . . . . . . . . . . . . . 35
Table 1-3: MGT Protocol Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 1-4: RocketIO MGT CRC Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 1-5: RocketIO MGT PMA Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 1-6: RocketIO MGT PCS Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 1-7: RocketIO MGT General Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 1-8: RocketIO MGT Dynamic Reconfiguration Ports . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 1-9: RocketIO MGT Communications Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 1-10: RocketIO MGT CRC Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 1-11: RocketIO MGT PMA Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 1-12: RocketIO MGT PCS Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 1-13: RocketIO MGT Digital Receiver Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 1-14: MGT Tile Communication Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 1-15: Control/Status Bus Association to Data Bus Byte Paths. . . . . . . . . . . . . . . . . . 60
Chapter 2: Clocking, Timing, and Resets
Table 2-1: MGTCLK Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 2-2: MGT Clock Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 2-3: Clock Selection for Three PLLs in a Tile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 2-4: TX PMA Attribute Values(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 2-5: Supported Transmitter PLL Divider Combinations. . . . . . . . . . . . . . . . . . . . . . 69
Table 2-6: RX PMA Attribute Values(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 2-7: Supported Receiver PLL Divider Combinations. . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 2-8: Supported VCO Operating Frequency Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 2-9: MGT Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Chapter 3: PCS Digital Design Considerations
Table 3-1: Selecting the External Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 3-2: Selecting the Internal Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 3-3: Fabric Interface Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 3-4: 8B/10B Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 3-5: Running Disparity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 3-6: 8B/10B Bypassed Signal Significance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
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Table 3-7: RXCHARISCOMMA Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 3-8: Deserializer Comma Detection Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 3-9: 8B/10B Comma Symbol Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 3-10: 8B/10B Decoder Byte-Mapped Status Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 3-11: SONET Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 3-12: SONET Attribute Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 3-13: ALIGN_COMMA_WORD Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 3-14: Definition of Clock Correction Sequence Bits 9-0. . . . . . . . . . . . . . . . . . . . . . 125
Table 3-15: Clock Correction Sequence/Data Correlation . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 3-16: Clock Correction Mask Example Settings (No Mask) . . . . . . . . . . . . . . . . . . 125
Table 3-17: Clock Correction Mask Example Settings (Mask Enabled). . . . . . . . . . . . . . 126
Table 3-18: Channel Bond Alignment Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 3-19: Maximum Time Required to Process Channel Bond Sequences . . . . . . . . . 128
Table 3-20: Channel Bonding and Clock Correction Character Spacing. . . . . . . . . . . . . 129
Table 3-21: Signal Values for a Pointer Difference Status . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 3-22: Signal Values for a Channel Bonding Skew . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 3-23: Signal Values for Event Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 3-24: Loopback Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 3-25: Variation of Recovered Clock Period. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 3-26: Digital Receiver Attribute Settings (Line Rates ≤ 1.25 Gb/s) . . . . . . . . . . . . . 136
Chapter 4: PMA Analog Design Considerations
Table 4-1: Attributes Controlling Pre-Emphasis Characteristics. . . . . . . . . . . . . . . . . . . . 140
Table 4-2: TXDAT_TAP_DAC and TXPOST_TAP_DAC Settings. . . . . . . . . . . . . . . . . . 141
Table 4-3: RXDIGRX Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 4-4: Transmit Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Table 4-5: Receive Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 4-6: PLL/Data Frequency Divergence as a Function of Lock and Hysteresis. . . . 151
Table 4-7: RocketIO Transceiver Power Control Description . . . . . . . . . . . . . . . . . . . . . . 151
Table 4-8: PMA Receiver Power Control Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 4-9: PMA Power Control Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 4-10: Power-Down of TX PMA Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Chapter 5: Cyclic Redundancy Check (CRC)
Table 5-1: Ports for the RX and TX CRC Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 5-2: CRC Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 5-3: Examples of Data Rates for CRC Calculation(1) . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 5-4: Data Width and Active Data Bus Bits with RXDATA Mapping . . . . . . . . . . 157
Chapter 6: Analog and Board Design Considerations
Table 6-1: Case A Filtering Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 6-2: Case B Filtering Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 6-3: SelectIO Pin Guidance for XC4VFX60/40/20-FF672. . . . . . . . . . . . . . . . . . . . . . 175
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Table 6-4: SelectIO Pin Guidance for XC4VFX100/60/40-FF1152. . . . . . . . . . . . . . . . . . . . 175
Table 6-5: SelectIO Pin Guidance for XC4VFX140/100-FF1517 . . . . . . . . . . . . . . . . . . . . . 176
Chapter 7: Simulation and Implementation
Table 7-1: GT11_MODE Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Table 7-2: CRC Latency and CRCCLOCKDOUBLE Attribute . . . . . . . . . . . . . . . . . . . . . 181
Table 7-3: LOC Grid and Package Pins Correlation for FF672. . . . . . . . . . . . . . . . . . . . . . 186
Table 7-4: LOC Grid and Package Pins Correlation for FF1152. . . . . . . . . . . . . . . . . . . . . 187
Table 7-5: LOC Grid and Package Pins Correlation for FF1517. . . . . . . . . . . . . . . . . . . . . 188
Table 7-6: Bonded Out MGTCLK Sources for XC4VFX20 . . . . . . . . . . . . . . . . . . . . . . . . . 189
Table 7-7: Bonded Out MGTCLK Sources for XC4VFX40 . . . . . . . . . . . . . . . . . . . . . . . . . 189
Table 7-8: Bonded Out MGTCLK Sources for XC4VFX60 . . . . . . . . . . . . . . . . . . . . . . . . . 189
Table 7-9: Bonded Out MGTCLK Sources for XC4VFX100 . . . . . . . . . . . . . . . . . . . . . . . . 190
Table 7-10: Bonded Out MGTCLK Sources for XC4VFX140 . . . . . . . . . . . . . . . . . . . . . . . 190
Chapter 8: Low-Latency Design
Table 8-1: Latency through Various Receiver Components/Processes
Table 8-2: Latency through Various Transmitter Components/Processes
Table 8-3: RX Low-Latency Ports
Table 8-4: RX Low-Latency Attributes
Table 8-5: TX Low-Latency Ports
Table 8-6: TX Low-Latency Attributes
Table 8-7: TX Use Models: Low-Latency Buffered Mode w/out Channel Deskew . . . . 199
Table 8-8: TX Use Models: Low-Latency Buffered Mode with Channel Deskew . . . . . 201
Table 8-9: TX Use Models: Low-Latency Buffer Bypass w/out Channel Deskew . . . . . 211
Table 8-10: Worst-Case Skew Estimates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Table 8-11: RX Use Models: Low-Latency Buffered Mode. . . . . . . . . . . . . . . . . . . . . . . . . 220
Table 8-12: RX Use Models: Low-Latency Buffer Bypass Mode . . . . . . . . . . . . . . . . . . . . 224
Table 8-13: Latency for Use Model TX_2B or TX_2F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Table 8-14: Latency for Use Model TX_3A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Table 8-15: Latency for Use Model TX_3A Using a 4-Byte Fabric Interface) . . . . . . . . . 231
Table 8-16: Latency for Use Model RX_1B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Table 8-17: Latency for Use Model RX_2A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
(1,2)
. . . . . . . . . . . 194
(1)
. . . . . . . . . . 195
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Section II:
Board Level Design
Chapter 9: Methodology Overview
Chapter 10: PCB Materials and Traces
Chapter 11: Design of Transitions
Chapter 12: Guidelines and Examples
Table 12-1: Model-Derived Loss for Differential Vias of Various Dimensions . . . . . . 259
Section III:
Appendixes
Appendix A: RocketIO Transceiver Timing Model
Table A-1: MGT Clock Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Table A-2: RocketIO DCLK Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Table A-3: RocketIO RXCRCCLK Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . 276
Table A-4: RocketIO TXCRCCLK Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . 277
Table A-5: RocketIO RXUSRCLK Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . 277
Table A-6: RocketIO RXUSRCLK2 Switching Characteristics . . . . . . . . . . . . . . . . . . . . . 278
Table A-7: RocketIO TXUSRCLK Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . 280
Appendix B: 8B/10B Valid Characters
Table B-1: Valid Data Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Table B-2: Valid Control “K” Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Appendix C: Dynamic Reconfiguration Port
Table C-1: Dynamic Reconfiguration Port Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Table C-2: Dynamic Reconfiguration Port Memory Map: MGTA Address 40–44. . . . . 294
Table C-3: Dynamic Reconfiguration Port Memory Map: MGTA Address 45–49. . . . . 295
Table C-4: Dynamic Reconfiguration Port Memory Map: MGTA Address 4A–4E . . . . 296
Table C-5: Dynamic Reconfiguration Port Memory Map: MGTA Address 4F–53 . . . . 297
Table C-6: Dynamic Reconfiguration Port Memory Map: MGTA Address 54–58. . . . . 298
Table C-7: Dynamic Reconfiguration Port Memory Map: MGTA Address 59–5D . . . . 299
Table C-8: Dynamic Reconfiguration Port Memory Map: MGTA Address 5E–62 . . . . 300
Table C-9: Dynamic Reconfiguration Port Memory Map: MGTA Address 63–67. . . . . 301
Table C-10: Dynamic Reconfiguration Port Memory Map: MGTA Address 68–6C . . . 302
Table C-11: Dynamic Reconfiguration Port Memory Map: MGTA Address 6D–71 . . . 303
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Table C-12: Dynamic Reconfiguration Port Memory Map: MGTA Address 72–76. . . . 304
Table C-13: Dynamic Reconfiguration Port Memory Map: MGTA Address 77–7B . . . 305
Table C-14: Dynamic Reconfiguration Port Memory Map: MGTA Address 7C–7F . . . 306
Table C-15: Dynamic Reconfiguration Port Memory Map: MGTB Address 40–44 . . . . 307
Table C-16: Dynamic Reconfiguration Port Memory Map: MGTB Address 45–49 . . . . 308
Table C-17: Dynamic Reconfiguration Port Memory Map: MGTB Address 4A–4E . . . 309
Table C-18: Dynamic Reconfiguration Port Memory Map: MGTB Address 4F–53. . . . 310
Table C-19: Dynamic Reconfiguration Port Memory Map: MGTB Address 54–58 . . . . 311
Table C-20: Dynamic Reconfiguration Port Memory Map: MGTB Address 59–5D . . . 312
Table C-21: Dynamic Reconfiguration Port Memory Map: MGTB Address 5E–62. . . . 313
Table C-22: Dynamic Reconfiguration Port Memory Map: MGTB Address 63–67 . . . . 314
Table C-23: Dynamic Reconfiguration Port Memory Map: MGTB Address 68–6C . . . 315
Table C-24: Dynamic Reconfiguration Port Memory Map: MGTB Address 6D–71 . . . 316
Table C-25: Dynamic Reconfiguration Port Memory Map: MGTB Address 72–76 . . . . 317
Table C-26: Dynamic Reconfiguration Port Memory Map: MGTB Address 77–7B . . . 318
Table C-27: Dynamic Reconfiguration Port Memory Map: MGTB Address 7C–7F . . . 319
Table C-28: PLL Configuration Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
Appendix D: Special Analog Functions
Table D-1: Register Address Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Table D-2: Example RXSELDACTRAN and RXSELDACFIX Combinations. . . . . . . . . 321
Appendix E: Virtex-II Pro/Virtex-II Pro X to Virtex-4 RocketIO
Transceiver Design Migration
Table E-1: MGTs per Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
Table E-2: Available Clock Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
Table E-3: Serial Rate Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
Table E-4: Encoding Support and Clock Multipliers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
Table E-5: Power Pin Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
Table E-6: Termination Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
Table E-7: CRC Transceiver Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
Table E-8: Loopback Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
Table E-9: Status Bus Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
Table E-10: Signal Optimization Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
Appendix F: References
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About This Guide
The Virtex ®-4 RocketIO™ MGT User Guide provides the product designer with the detailed
technical information needed to successfully implement the RocketIO MGT in Virtex-4
Platform FPGA designs. For information on the Virtex-II Pro RocketIO and the
Virtex-II Pro X RocketIO X transceivers, see UG024
UG035
MGT Features
RocketIO MGTs have flexible, programmable features that allow a multi-gigabit serial
transceiver to be easily integrated into any Virtex-4 design:
• 622 Mb/s to 6.5 Gb/s data rates
• 8 to 24 transceivers per FPGA
• 3-tap transmitter pre-emphasis (pre-equalization)
• Receiver continuous time equalization
• Optional on-chip AC coupled receiver
• Digital oversampled receiver for data rates up to 1.25 Gb/s
• Receiver signal detect and loss of signal indicator and out-of-band (OOB) signal
• Transmit driver idle state for OOB signaling (both outputs at V
• 8B/10B encoding
• No data encoding (pass-through mode) with digital receiver
• Channel bonding
• Flexible Cyclic Redundancy Check (CRC) generation and checking
• Pins for transmitter and receiver termination voltage
• User reconfiguration using the Dynamic Reconfiguration Port
• Multiple loopback paths
• NRZ signaling
, RocketIO X Transceiver User Guide.
receiver
Preface
, RocketIO Transceiver User Guide, and
)
CM
Virtex-4 RocketIO MGT User Guide www.xilinx.com 27
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Preface: About This Guide
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User Guide Organization
This guide is organized as follows:
Section I: FPGA Level Design
• Chapter 1, “RocketIO Transceiver Overview” – MGT basic architecture and
capabilities. Includes available ports, primitive and modifiable attributes, byte
mapping.
• Chapter 2, “Clocking, Timing, and Resets” – Clock domain architecture, clock ports,
examples for clocking/reset schemes.
• Chapter 3, “PCS Digital Design Considerations” – Top-level architecture and block-
level functions, 8B/10B encoding/decoding, comma detection, channel bonding,
status/event bus, loopback, digital receiver.
• Chapter 4, “PMA Analog Design Considerations” – Serial I/O, output swing and
emphasis, differential receiver, analog functions.
• Chapter 5, “Cyclic Redundancy Check (CRC)”– CRC functionality, latency, timing.
• Chapter 6, “Analog and Board Design Considerations” – Power requirements,
termination options, AC/DC coupling, high-speed trace design.
• Chapter 7, “Simulation and Implementation” – Simulation models/considerations,
implementation tools, debugging and diagnostics, transceiver locations, package pin
assignments.
• Chapter 8, “Low-Latency Design” – Details of designing for minimum latency.
Section II: Board Level Design
• Chapter 9, “Methodology Overview” – Powering, clocking, and coupling MGTs.
• Chapter 10, “PCB Materials and Traces” – Handling PCB and interconnect
characteristics to maximize signal integrity.
• Chapter 11, “Design of Transitions” – Detailed analysis of PCB trace geometries and
their effect on signal integrity, impedance, and differential balance.
• Chapter 12, “Guidelines and Examples” – Practical guidelines for maximizing PCB
design success.
Section III: Appendixes
• Appendix A, “RocketIO Transceiver Timing Model” – Timing parameters associated
with the MGT core.
• Appendix B, “8B/10B Valid Characters” – Valid data and K-character table.
• Appendix C, “Dynamic Reconfiguration Port” – Parallel programming bus for
dynamically configuring the attribute settings. (For advanced users.)
• Appendix D, “Special Analog Functions” – Receiver Sample Phase Adjustment
function.
• Appendix E, “Virtex-II Pro/Virtex-II Pro X to Virtex-4 RocketIO Transceiver Design
Migration” – Important differences to be aware of when migrating designs from
Virtex-II Pro/ Virtex-II Pro X to Virtex-4 FPGAs.
• Appendix F, “References”
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Related Information
For a complete menu of online information resources available on the Xilinx website, visit
http://www.xilinx.com/virtex4/
For a comprehensive listing of available tutorials and resources on network technologies
and communications protocols, visit http://
Additional Resources
For additional information, go to http://support.xilinx.com. The following table lists
some of the resources available on this website. Use the URLs to access these resources
directly.
Resource Description/URL
Tutorials Tutorials covering Xilinx design flows, from design entry to verification
Answer Browser Database of Xilinx solution records
Related Information
.
www.iol.unh.edu/training/.
and debugging
http://support.xilinx.com/support/techsup/tutorials/index.htm
http://support.xilinx.com/xlnx/xil_ans_browser.jsp
Application Notes Descriptions of device-specific design techniques and approaches
Data Sheets Device-specific information on Xilinx device characteristics, including
Problem Solvers Interactive tools that allow the user to troubleshoot design issues
Tech Tips Latest news, design tips, and patch information for the Xilinx design
User Guide Conventions
This document uses the following conventions.
Logical / Mathematical Operators
• The asterisk * when used in a port or attribute name is a wildcard operator indicating
that more than one character could be represented.
Example: CLK_COR_SEQ_1_* could be CLK_COR_SEQ_1_1, CLK_COR_SEQ_1_2, etc.
• !
=
NOT EQUAL TO
•
≠
NOT EQUAL TO
•
≤
LESS THAN OR EQUAL TO
≥
•
•
GREATER THAN OR EQUAL TO
≈
APPROXIMATELY EQUAL TO
http://support.xilinx.com/apps/appsweb.htm
readback, boundary scan, configuration, length count, and debugging
http://support.xilinx.com/xlnx/xweb/xil_publications_index.jsp
http://support.xilinx.com/support/troubleshoot/psolvers.htm
environment
http://www.support.xilinx.com/xlnx/xil_tt_home.jsp
Virtex-4 RocketIO MGT User Guide www.xilinx.com 29
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Preface: About This Guide
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Port and Attribute Names
All input and output ports of the RocketIO transceiver primitives are denoted in uppercase letters. Attributes of the RocketIO transceiver can be denoted in upper-case letters
with underscores or all upper-case letters.
When assumed to be the same frequency, RXUSRCLK and TXUSRCLK are referred to as
USRCLK and can be used interchangeably. This also holds true for RXUSRCLK2,
TXUSRCLK2, and USRCLK2.
Comma Definition
A comma is a “K” character used by the transceiver to align the serial data on a
byte/half-word boundary (depending on the protocol used), so that the serial data is
correctly decoded into parallel data.
Jitter Definition
Jitter is defined as the short-term variations of significant instants of a signal from their
ideal positions in time (ITU). Jitter is typically expressed in a decimal fraction of Unit
Interval (UI), for example, 0.3 UI.
Total Jitter (DJ + RJ) Definition
• Deterministic Jitter (DJ) – DJ is data pattern dependant jitter, attributed to a unique
source (for example, Inter Symbol Interference (ISI) due to loss effects of the media).
DJ is linearly additive.
• Random Jitter (RJ) – RJ is due to stochastic sources, such as thermal and flicker noise,
and so on. RJ is additive as the sum of squares and follows a normal distribution.
MGT Definition
The term MGT refers to the Virtex-4 RocketIO Multi-Gigabit Transceiver. Previous
generations are explicitly called out: Virtex-II Pro RocketIO or Virtex-II Pro X RocketIO X.
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Typographical
The following typographical conventions are used in this document:
Courier font
Courier bold
Helvetica bold
Italic font
Square brackets [ ]
Braces { }
Vertical bar |
Ellipsis . . .
User Guide Conventions
Convention Meaning or Use Example
Messages and prompts that the
system displays
Literal commands to enter in a
syntactical statement
Commands to select from a
menu
speed grade: - 100
ngdbuild design_name
File → Open
Keyboard shortcuts Ctrl+C
Variables in syntax statements
for which the user must supply
ngdbuild design_name
values
References to other manuals
See the Virtex-II Pro User Guide
for more information.
If a wire is drawn so that it
Emphasis in text
overlaps the pin of a symbol, the
two nets are not connected.
Optional entry / parameter;
required in bus specifications,
such as bus[7:0]
A list of items from which the
user must choose one or more
Separates items in a list of
choices
Repetitive material that has
been omitted
ngdbuild [option_name]
design_name
lowpwr ={on|off}
lowpwr ={on|off}
allow block block_name
loc1 loc2 ... locn;
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Section I:
FPGA Level Design
Virtex-4 RocketIO
Multi-Gigabit Transceiver
Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008
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RocketIO Transceiver Overview
Basic Architecture and Capabilities
The RocketIO™ Multi-Gigabit Transceiver (MGT) block diagram is illustrated in
Figure 1-1, page 36. Depending on the device, a Virtex®-4 FPGA has between 8 and 24
transceiver modules, as shown in Tab le 1 -1 .
Table 1-1: Number of MGT Cores per Device Type
Device RocketIO MGT Cores
XC4VFX20 8
XC4VFX40 12
XC4VFX60 12 or 16
XC4VFX100 20
XC4VFX140 24
(1)
Chapter 1
Notes:
1. Number of MGTs depends on the package.
The transceiver module is designed to operate at any serial bit rate in the range of
622 Mb/s to 6.5 Gb/s per channel, including the specific bit rates used by the
communications standards listed in Tab le 1 -2 .
Table 1-2: Communications Standards Supported by the MGT
Mode Channels
SONET OC-12 1 0.622
Fibre Channel (1, 2, 4X) 1 1.06/2.12/4.25
Gigabit Ethernet 1 1.25
Infiniband 1/4/12 2.5
PCI Express 1/2/4/8/16 2.5
Serial RapidIO 1/4 1.25/2.5/3.125
Serial ATA 1 1.5/3
XAUI
(10 Gigabit Ethernet) 4 3.125
10 Gigabit Fibre Channel (4 x 3.1875G) 4 3.1875
Aurora Protocol
Notes:
1. One channel is considered to be one transceiver.
2. See www.xilinx.com/aurora
(2)
for details.
(1)
(Lanes) I/O Bit Rate (Gb/s)
1/2/3/4... 0.622 – 6.5
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Chapter 1: RocketIO Transceiver Overview
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8B/10B
Decoder
FPGA FABRIC
FPGA FABRIC
MULTI-GIGABIT TRANSCEIVER CORE
Serializer
RXP
TXP
Clock
Manager
PAC KAG E
PINS
Deserializer
Comma
Detect
Realign
TX
Ring
Buffer
Channel Bonding
and
Clock Correction
8B/10B
Encoder
RX
Ring
Buffer
RXN
GNDA
TXN
ug076_apA_01_071707
VTRX
AVCCAUXRX
VTTX
AVCCAUXTX
1.2V
TX/RX GND
Te r mi n ation
Supply RX
1.2V
Te r mi n ation
Supply TX
64B/66B
Descrambler
(1)
64B/66B
Block Sync
(1)
64B/66B
Decoder
(1)
64B/66B
Encoder
(1)
Gearbox
Scrambler
(1)
Pre-Driver Loopback Path
Power Down
Clock/
Reset
Dynamic
Reconfiguration
Por t
Fabric
Interface
CRC
Block
RXCRCCLK
RXCRCDATAVALID
RXCRCDATAWIDTH[2:0]
RXCRCIN[63:0]
RXCRCINIT
RXCRCINTCLK
RXCRCOUT[31:0]
RXCRCPD
RXCRCRESET
TXCRCCLK
TXCRCDATAVALID
TXCRCDATAWIDTH[2:0]
TXCRCIN[63:0]
TXCRCINIT
TXCRCINTCLK
TXCRCOUT[31:0]
TXCRCPD
TXCRCRESET
PLL
Calibration
Block
RXCYCLELIMIT
(3)
TXCYCLELIMIT
(3)
RXCLKSTABLE
TXCALFAIL
(3)
TXCLKSTABLE
VCCINT
Fabric Power
Supply
RXCALFAIL
(3)
CHBONDI[4:0]
CHBONDO[4:0]
RXRECCLK1
RXRECCLK2
RXPCSHCLKOUT
(2)
RXPOLARITY
RXREALIGN
RXCOMMADET
RXLOSSOFSYNC[1:0]
(1)
RXDATA[63:0]
RXNOTINTABLE[7:0]
RXDISPERR[7:0]
RXCHARISK[7:0]
RXCHARISCOMMA[7:0]
RXRUNDISP[7:0]
RXSTAT US[5:0]
RXBUFERR
ENCHANSYNC
TXBUFERR
TXDATA[63:0]
TXBYPASS8B10B[7:0]
TXCHARISK[7:0]
TXCHARDISPMODE[7:0]
TXCHARDISPVAL[7:0]
TXKERR[7:0]
TXRUNDISP[7:0]
TXPOLARITY
TXLOCK
TXINHIBIT
LOOPBACK[1:0]
ENPCOMMAALIGN
ENMCOMMAALIGN
RXRESET
RXUSRCLK
RXUSRCLK2
TXRESET
REFCLK1
REFCLK2
TXUSRCLK
GREFCLK
RXCOMMADETUSE
RXDATAWIDTH[1:0]
RXDESCRAM64B66BUSE
(1)
RXBLOCKSYNC64B66BUSE
(1)
RXSLIDE
TXSCRAM64B66BUSE
(1)
RXIGNOREBTF
(1)
RXINTDATAWIDTH[1:0]
TXDATAWIDTH[1:0]
TXENC64B66BUSE
(1)
TXENC8B10BUSE
TXGEARBOX64B66BUSE
(1)
POWERDOWN
RXLOCK
RXDECC64B66BUSE
(1)
RXDEC8B10BUSE
DI[15:0]
DADDR[7:0]
DCLK
DEN
DWE
DRDY
DO[15:0]
TXINTDATAWIDTH[1:0]
TXOUTCLK2
TXOUTCLK1/TXPCSHCLKOUT
(2)
RXPMARESET
TXUSRCLK2
TXPMARESET
Notes: (1) 64B/66B encoding/decoding is not supported.
(2) TXPCSHCLKOUT and RXPCSHCLKOUT ports are not suppor ted.
(3) RXCALFAIL, RXCYCLELIMIT, TXCALFAIL, and TXCYCLELIMIT ports are not supported.
PCS Parallel Loopback
Figure 1-1: RocketIO Multi-Gigabit Transceiver Block Diagram
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The RocketIO MGT transceiver consists of the Physical Media Attachment (PMA) and
Physical Coding Sublayer (PCS). The PMA contains the serializer/deserializer (SERDES),
TX and RX input/output buffers, clock generator, and clock recovery circuitry. The PCS
contains the 8B/10B encoder/decoder and the ring buffer supporting channel bonding
and clock correction. Refer to Figure 1-1 showing the MGT top-level block diagram and
FPGA interface signals.
Tab le 1- 3 lists supported standards and certain values used to support that standard. Data
widths of one, two, and four bytes (lower speeds) or four and eight bytes (higher speeds)
are selectable for the various protocols.
Table 1-3: MGT Protocol Settings
Basic Architecture and Capabilities
Standard/
Application
Custom 6.25 Gb/s 6.25 8B/10B 312.5
4X Fibre Channel 4.25 8B/10B 212.5
10G Fibre Channel
over 4 links
XAUI 3.125 8B/10B 312.5
Serial RapidIO Type 3 3.125 8B/10B 312.5
Serial RapidIO Type 2 2.5 8B/10B 250.0
(1)
Data Rate
(Gb/s)
3.1875 8B/10B 159.375
RocketIO MGT
Coding
Reference Clock
Frequency (Fin)
Parallel Data
Width
(bytes)
8 78.13
4 156.25
4 106.25
2 212.5
8 39.84
4 79.69
8 39.06
4 78.13
2 156.25
8 39.06
4 78.13
2 156.25
2 125.00
1 250.00
Parallel Data
Frequency (MHz)
Serial RapidIO Type 1 1.25 8B/10B 250.0
Serial ATA Type 2 3.0 8B/10B 300.0
Serial ATA Type 1 1.5 8B/10B 300.0
PCI Express 2.5 8B/10B 250.0
Infiniband 2.5 8B/10B 250.0
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(5)
2 62.50
1 125.00
8 37.50
4 75.00
2 150
2 75.00
1 150.00
2 125.00
1 250.00
2 125.00
1 250.00
Chapter 1: RocketIO Transceiver Overview
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Table 1-3: MGT Protocol Settings (Continued)
Standard/
Application
(1)
Data Rate
(Gb/s)
RocketIO MGT
Coding
Reference Clock
Frequency (F
2X Fibre Channel 2.125 8B/10B 212.5
1X Fibre Channel 1.0625 8B/10B 212.5
1000BASE-X 1.25 8B/10B 250.0
OC-12 0.622 None 155.52
0.622 – 1.075
155.52 – 537.5
1.24 – 2.15 124 – 537.5
Aurora (Transmit)
8B/10B
2.48 – 4.3 248 – 537.5
4.96 – 6.5 248 – 406.25
(5)
(2)
(2)
(2)
(2)
)
in
Parallel Data
Width
(bytes)
Frequency (MHz)
2 106.25
1 212.50
2 53.13
1 106.25
2 62.50
1 125.0
2 38.88
1 77.76
2 31.1 – 53.75
4 15.55 – 26.875
2 62 – 107.5
4 31 – 53.75
2 124 – 215
4 62 – 107.5
2 248 – 250
4 124 – 162.5
Parallel Data
(3)
0.622 – 1.25
(4)
124.4 – 625
(2)
2 31.1 – 62.5
4 15.55 – 31.25
1.25 – 2.15 124 – 537.5
(2)
2 62.5 – 107.5
4 31.25 – 53.75
Aurora (Receive)
2.48 – 4.3 248 – 537.5
8B/10B
(2)
2 124 – 215
4 62 – 107.5
(3)
4.96 – 6.5 248 – 406.25
(2)
2 248 – 250
4 124 – 162.5
Notes:
1. Any fabric I/F is possible. However, these are the best settings for the clocking domains and overall system performance, including
the 250 MHz maximum parallel speed of the MGT. Refer to the DS302
2. Refer to Ta b le 2 -5 and Ta bl e 2 -7 for selecting the appropriate reference clock frequency based on the chosen line rate.
3. Parallel data frequency is limited by the maximum USRCLK2 frequency of 250 MHz.
4. Receiver in digital CDR mode.
5. These protocols also allow a 125.0 MHz reference clock. A higher reference clock frequency yields lower wide-band jitter
generation.
: Virtex-4 Data Sheet, for details.
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Configuring the RocketIO MGT
There are two ways to configure a RocketIO transceiver:
1. Static configuration. The transceiver is configured using a combination of port tie-offs
and attribute settings at design time to support a specific protocol.
2. Dynamic configuration. The transceiver is configured by driving ports and operating
the Dynamic Reconfiguration Port (DRP) to modify the run-time configuration of the
MGT.
MGT configuration can be complex because of the large number of possible settings. There
are over 200 ports and attributes available, and many of them are interrelated. Xilinx
provides a RocketIO wizard to help manage the configuration process. The wizard is highly
recommended for any RocketIO design.
Unlike previous families, the RocketIO wizard for the Virtex-4 family is delivered as a core
from the CORE Generator™ tool. After opening the CORE Generator tool, start a CORE
Generator project for a Virtex-4 device with the desired HDL output format selected. If the
RocketIO wizard is not shown in the list of available cores, download it from the
IP Update Download Center at http://www.xilinx.com/support/
After the core is installed, use the RocketIO wizard to customize a wrapper for one or more
RocketIO transceivers, implementing whatever MGT features are required. Most protocols
supported by the RocketIO transceiver are provided as templates that can be loaded to
automatically configure the MGT. These templates can be used as-is, or modified as
necessary to create customized versions of common standards.
Configuring the RocketIO MGT
.
Available Ports
Tab le 1- 4 (CRC — see Chapter 5, “Cyclic Redundancy Check (CRC)” for additional
information about the CRC block of the transceiver), Tab le 1 -5 (PMA), Ta bl e 1 -6 (PCS),
Tab le 1- 7 (Global Signals), Tab le 1- 8 (Dynamic Reconfiguration), and Ta bl e 1 -9
(Communication) contain all the primitive port descriptions. The RocketIO MGT
primitives contain 105 ports. The differential serial data ports (RXN, RXP, TXN, and TXP)
are connected directly to external pads; the remaining
FPGA logic.
101 ports are all accessible from the
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Table 1-4: RocketIO MGT CRC Ports
Port I/O Port Size Definition
RXCRCCLK I 1 Receiver CRC logic clock.
RXCRCDATAVALID I 1 Signals that the RXCRCIN data is valid.
Determines the data width of the RXCRCIN:
000 = 8 bits RXCRCIN[63:56]
001 = 16 bits RXCRCIN[63:48]
010 = 24 bits RXCRCIN[63:40]
RXCRCDATAWIDTH I 3
011 = 32 bits RXCRCIN[63:32]
100 = 40 bits RXCRCIN[63:24]
101 = 48 bits RXCRCIN[63:16]
110 = 56 bits RXCRCIN[63:8]
111 = 64 bits RXCRCIN[63:0]
RXCRCIN I 64 Receiver CRC logic input data.
RXCRCINIT I 1 When set to logic 1, CRC logic initializes to the RXCRCINITVAL.
RXCRCINTCLK I 1 Receiver CRC/FPGA fabric interface clock.
RXCRCOUT O 32
Receiver CRC output data. This bus must be inverted to obtain
the valid CRC value.
RXCRCPD I 1 Powers down the RX CRC logic when set to logic 1.
RXCRCRESET I 1 Resets the RX CRC logic when set to logic 1.
TXCRCCLK I 1 Transmitter CRC logic clock.
TXCRCDATAVALID I 1 Signals that the TXCRCIN data is valid when set to a logic 1.
Determines the data width of the TXCRCIN:
000 = 8 bits TXCRCIN[63:56]
001 = 16 bits TXCRCIN[63:48]
010 = 24 bits TXCRCIN[63:40]
TXCRCDATAWIDTH I 3
011 = 32 bits TXCRCIN[63:32]
100 = 40 bits TXCRCIN[63:24]
101 = 48 bits TXCRCIN[63:16]
110 = 56 bits TXCRCIN[63:8]
111 = 64 bits TXCRCIN[63:0]
TXCRCIN I 64 Transmitter CRC logic input data.
TXCRCINIT I 1 When set to logic 1, CRC logic initializes to the TXCRCINITVAL.
TXCRCINTCLK I 1 Transmitter CRC/FPGA fabric interface clock.
TXCRCOUT O 32
Transmitter CRC output data. This bus must be inverted to
obtain the valid CRC value.
TXCRCPD I 1 Powers down the TX CRC logic when set to logic 1.
TXCRCRESET I 1 Resets the TX CRC logic when set to a logic 1.
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\
Table 1-5: RocketIO MGT PMA Ports
Port I/O Port Size Definition
Calibration
RXCALFAIL O 1 Reserved. This calibration port is not supported.
When set to a logic 1, indicates the clocks are stable and MGT RX
RXCLKSTABLE I 1
calibration can start. See Chapter 2, “Clocking, Timing, and
Resets,” for details.
RXCYCLELIMIT O 1 Reserved. This calibration port is not supported.
TXCALFAIL O 1 Reserved. This calibration port is not supported.
When set to a logic 1, indicates that the clocks are stable and
TXCLKSTABLE I 1
MGT TX calibration can start. See Chapter 2, “Clocking, Timing,
and Resets,” for details.
TXCYCLELIMIT O 1 Reserved. This calibration port is not supported.
Driver/Buffers
Available Ports
TXINHIBIT I 1
RXPOLARITY I 1
TXPOLARITY I 1
RXN I 1
RXP I 1
TXN O 1
TXP O 1
When set to a logic 1, the TX differential pairs are forced to be a
constant 1/0. TXN = 1, TXP = 0
Inverts the polarity of the parallel RX data at the interface of the
PMA and PCS. Receive data is inverted when set to logic 1.
Parallel loopback data is affected by this port.
Inverts the polarity of the parallel TX data at the interface of the
PMA and PCS. Transmit data is inverted when set to logic 1.
Parallel loopback data is affected by this port.
Differential serial input (external package pin). See Chapter 7,
“Simulation and Implementation,” for package pin correlation
to MGT location constraint.
Differential serial input (external package pin). See Chapter 7,
“Simulation and Implementation,” for package pin correlation
to MGT location constraint.
Differential serial output (external package pin). See Chapter 7,
“Simulation and Implementation,” for package pin correlation
to MGT location constraint.
Differential serial output (external package pin). See Chapter 7,
“Simulation and Implementation,” for package pin correlation
to MGT location constraint.
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Table 1-5: RocketIO MGT PMA Ports (Continued)
Port I/O Port Size Definition
Clocks/Clock Status
When set to logic 1, indicates that the receiver is locked to the
reference clock or locked to the input data.
Logic 0 indicates the receiver is not locked. Possible reasons
include no reference clock, incorrect reference clock frequency,
RXLOCK O 1
incorrect attribute configuration, PMA power was not applied,
or receiver was not able to lock to data and is in the process of
locking to the local reference clock again. A toggling RXLOCK
signal indicates successful “coarse” lock to the local reference
clock, but unsuccessful lock to incoming data.
RXPMARESET I 1 Resets the receiver PMA when set to logic 1.
RXRECCLK1 O 1
Recovered clock from incoming data. See “PMA Receive Clocks”
in Chapter 2.
Recovered clock from incoming data. Should not be used to clock
RXRECCLK2 O 1
user logic; instead use RXRECCLK1. See “PMA Receive Clocks”
in Chapter 2.
RXMCLK O 1 Reserved. This clock port is not supported.
When set to logic 1, indicates that the transmitter PLL is locked
to the reference clock.
This output cycles from between logic 0 and logic 1 during lock
TXLOCK O 1
acquisition. When the output maintains a logic 1 state, the
transmitter PLL is locked. Failure to acquire or maintain lock can
be due to no reference clock, incorrect reference clock frequency,
incorrect attribute configuration, or PMA power was not
applied.
TXOUTCLK1 O 1
Transmitter output clock derived from PLL based on transmitter
reference clock. See “PMA Transmit Clocks” in Chapter 2.
Transmit output clock from the PCS TXCLK domain in the PCS.
TXOUTCLK2 O 1
Source is dependant on the PCS clock configuration. See “PMA
Transmit Clocks” in Chapter 2.
Resets the transmitter PMA when set to a logic 1. Initializes the
TXPMARESET I 1
high-speed digital sections of each transmitter. TX VCO
calibration is controlled by TXPMARESET. See “Resets” in
Chapter 2.
RXPCSHCLKOUT O 1 Reserved. This clock port is not supported.
TXPCSHCLKOUT O 1 Reserved. This clock port is not supported.
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Table 1-5: RocketIO MGT PMA Ports (Continued)
Port I/O Port Size Definition
Special Signals
RXSIGDET O 1
RXSYNC I 1
TXENOOB I 1
TXSYNC I 1
Available Ports
When set to logic 1, indicates that an out-of-band (OOB) signal
has been detected. When proper differential signal input is being
received, RXSIGDET is logic 0. See Chapter 4, “PMA Analog
Design Considerations” for details.
Controls the RX PMA phase aligner used for clock phase
alignment in reduced latency modes. See “PMA/PCS Clocking
Domains and Data Paths” in Chapter 2.
Enables the transmitter to send electric idle signals on the
TXN/TXP pins when set to a logic 1. See Chapter 4, “PMA
Analog Design Considerations” for details.
Controls the TX PMA phase aligner used for clock phase
alignment in reduced latency modes and to reduce transmitter
output skew across MGTs for channel bonded applications. See
Chapter 3, “PCS Digital Design Considerations” for details.
Table 1-6: RocketIO MGT PCS Ports
Port I/O Port Size Definition
Channel Bonding
CHBONDI I 5
CHBONDO O 5
ENCHANSYNC I 1
64B/66B
(1)
RXBLOCKSYNC64B66BUSE
RXDEC64B66BUSE
RXDESCRAM64B66BUSE
RXIGNOREBTF
RXLOSSOFSYNC
TXENC64B66BUSE
TXGEARBOX64B66BUSE
TXSCRAM64B66BUSE
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
I 1 Reserved. Tie to logic 0.
I 1 Reserved. Tie to logic 0.
I 1 Reserved. Tie to logic 0.
I 1 Reserved. Tie to logic 0.
O 2 Reserved.
I 1 Reserved. Tie to logic 0.
I 1 Reserved. Tie to logic 0.
I 1 Reserved. Tie to logic 0.
The channel bonding control that is used only by “slaves”
which are driven by a transceiver's CHBONDO port.
Channel bonding control that passes channel bonding and
clock correction control to other transceivers.
Control from the fabric to the transceiver which enables the
transceiver to perform channel bonding.
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Table 1-6: RocketIO MGT PCS Ports (Continued)
Port I/O Port Size Definition
8B/10B
RXCHARISK O 8
RXCHARISCOMMA O 8
If 8B/10B decoding is enabled, it indicates that the received
data is a “K” character when asserted. (See Table 1-15, page 60
for association with RX data.) If 8B/10B decoding is bypassed,
it becomes the last bit received (Bit "j") of the 10-bit encoded
data.
Indicates the reception by the 8B/10B decoder of K28.1, K28.5,
K28.7 (see Table 1-15, page 60 for association with RX data),
and some out-of-band commas (depending on the setting of
DEC_VALID_COMMA_ONLY).
RXDEC8B10BUSE I 1
RXDISPERR O 8
RXNOTINTABLE O 8
RXRUNDISP O 8
TXBYPASS8B10B I 8
TXCHARDISPMODE I 8
If set to a logic 1, the 8B/10B decoder is used. If set to a logic 0,
the 8B/10B decoder is bypassed.
If 8B/10B encoding is enabled, it indicates whether a disparity
error has occurred on the serial line. Included in byte-mapping
scheme. (See Table 1-15, page 60 for association with RX data.)
Status bits are raised to logic 1 when a received 10-bit-encoded
data symbol is not found in the encode/decode table. When
an RXNOTINTABLE status bit is asserted, the raw undecoded
10-bit symbol corresponding to that bit is delivered to the
fabric instead of a decoded character. See Table 1-15, page 60
for association with RX data.
Signals the running disparity (0 = negative, 1 = positive) in the
received serial data. See Table 1-15, page 60 for association
with RX data. If 8B/10B encoding is bypassed, it remains as
the second-to-last bit received (Bit “h”) of the 10-bit encoded
data.
When asserted, signals the 8B/10B encoder to not encode the
associated data. See Table 1-15, page 60 for association with
RX data. See Chapter 3, “PCS Digital Design Considerations,”
for other details.
If 8B/10B encoding is enabled, this bus determines what mode
of disparity is to be sent. (See Table 1-1 5 , pag e 60 for
association with RX data.) When 8B/10B is bypassed, this
becomes the last bit transmitted (Bit “j”) of the 10-bit encoded
TXDATA bus section (see Figure 3-10, page 111) for each byte
specified by the byte-mapping. The bits have no meaning if
TXENC8B10BUSE is set to a logic 0.
TXCHARDISPVAL I 8
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If 8B/10B encoding is enabled, this bus determines what type
of disparity is to be sent. (See Table 1-1 5 , pag e 60 for
association with RX data.) When 8B/10B is bypassed, this
becomes the second to last bit transmitted (Bit “h”) of the 10bit encoded TXDATA bus section (see Figure 3-10, page 111)
for each byte specified by the byte-mapping section. The bits
have no meaning if TXENC8B10BUSE is set to a logic 0.
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Table 1-6: RocketIO MGT PCS Ports (Continued)
Port I/O Port Size Definition
TXCHARISK I 8
Available Ports
If TXENC8B10BUSE = 1 (8B/10B encoder enable), then
TXCHARISK[7:0] signals the K-definition of the TXDATA byte
in the corresponding byte lane.
TXENC8B10BUSE I 1
TXKERR O 8
TXRUNDISP O 8
Alignment
ENMCOMMAALIGN I 1
ENPCOMMAALIGN I 1
RXCOMMADET O 1
RXCOMMADETUSE I 1
RXREALIGN O 1
If set to a logic 1, the 8B/10B encoder is used. If set to a logic 0,
the 8B/10B encoder is bypassed.
In 8B/10B mode, indicates that an invalid K-character was
transmitted.
Signals the running disparity (0 = negative, 1 = positive) for its
corresponding byte after that byte is encoded.
Selects realignment of incoming serial bitstream on minuscomma. When set to logic 1, realigns serial bitstream byte
boundary to where minus-comma is detected.
Selects realignment of incoming serial bitstream on pluscomma. When set to logic 1, realigns the serial bitstream byte
boundary to where plus-comma is detected.
Indicates that the symbol defined by PCOMMA_32B_VALUE
(if PCOMMA_DETECT is asserted) and/or
MCOMMA_32B_VALUE (if MCOMMA_DETECT is asserted)
has been received.
If set to a logic 1, the comma detect is used. If set to a logic 0,
the comma detect is bypassed.
Signal from the PCS data aligner denoting that the byte
alignment with the serial data stream changed due to a comma
detection. Raised to a logic 1 when alignment occurs.
RXSLIDE I 1
Data Path
RXDATA O 64
RXDATAWIDTH I 2
RXINTDATAWIDTH I 2
TXDATA I 64
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Enables the “slip” of the PCS alignment block by 1 bit. To
enable a slide of 1 bit, it increments from a lower bit to a higher
bit. This signal must be set to logic 1 for at least one clock cycle
and then set to a logic 0 synchronous to RXUSRCKLK2.
RXSLIDE must be held Low for at least three RXUSRCLK2
clock cycles before being set to a logic 1 again.
Receive data at the FPGA user fabric. RXDATA[7:0] is always
the first byte received.
Indicates width of FPGA parallel bus. (See Tab le 3- 1,
page 104.)
Sets the internal mode of the receive PCS:
2’b10 = 32-bit
2’b11 = 40-bit
Transmit data from the FPGA user fabric that is 8 bytes wide.
TXDATA[7:0] is always the first byte transmitted.
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Table 1-6: RocketIO MGT PCS Ports (Continued)
Port I/O Port Size Definition
TXDATAWIDTH I 2
TXINTDATAWIDTH I 2
Status/Clocks
RXBUFERR O 1
RXRESET I 1
RXSTATUS O 6
RXUSRCLK I 1
Indicates width of FPGA parallel bus. (See Ta bl e 3- 1,
page 104.)
Sets the internal mode of the transmit PCS:
2’b10 = 32-bit
2’b11 = 40-bit
Provides status of the receiver buffer. If raised to a logic 1, an
overflow/underflow has occurred. When this bit becomes set,
it can only be reset by asserting RXRESET
Synchronous RX PCS reset that “recenters” the receive ring
buffer. It also resets 8B/10B decoder, comma detect, channel
bonding, clock correction logic, digital oversampling CDR,
and other internal receive registers. It does not reset the
receiver PLL or transmit PCS.
RXSTATUS[5] indicates a receiver has successfully completed
channel bonding when raised to logic 1. RXSTATUS[4:0]
indicates the status of the receive buffer pointers, channel
bonding skew, and clock correction events. See section“Status
Indication” in Chapter 3 for details.
Clock that is used for reading the RX ring buffer. It also clocks
CHBONDI and CHBONDO in and out of the transceiver.
Typically, the same as TXUSRCLK.
RXUSRCLK2 I 1
TXBUFERR O 1
TXRESET I 1
TXUSRCLK I 1
TXUSRCLK2 I 1
Notes:
1. 64B/66B encoding/decoding is not supported.
Clock output that clocks the receive data and status between
the transceiver and the FPGA core. Typically, the same as
TXUSRCLK2.
Provides status of the transmission buffer. If raised to logic 1,
an overflow/underflow has occurred. When this bit becomes
set, it can only be reset by setting TXRESET to logic 1.
Synchronous TX PCS reset that “recenters” the transmit buffer.
It also resets 8B/10B encoder and other internal transmission
registers. It does not reset the PMA including the PLL or
receive PCS.
Clock input that is clocked with the reference clock. This clock
is used for writing the TX buffer and must be frequencylocked to the reference clock.
Clock input that clocks the transmit data and status between
the FPGA core and the transceiver. Typically the same as
RXUSRCLK2.
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Table 1-7: RocketIO MGT General Ports
Port I/O Port Size Definition
LOOPBACK I 2
POWERDOWN I 1
Available Ports
Selects the two loopback test modes. These modes are PCS
parallel, and pre-driver serial loopback. See Chapter 3, “PCS
Digital Design Considerations” for details.
Shuts down entire PCS transceiver when set to logic 1.
This input is asynchronous. PMA powerdown is controlled via
attributes.
GREFCLK I 1
Reference clock (alternate clock not recommended for over 1G
operation).
REFCLK1 I 1 Reference clock (low jitter input clock).
REFCLK2 I 1 Reference clock (low jitter input clock).
Table 1-8: RocketIO MGT Dynamic Reconfiguration Ports
Port I/O Port Size Definition
DADDR I 8
Dynamic Reconfiguration Port address bus. See Appendix C,
“Dynamic Reconfiguration Port.”
DCLK I 1 Dynamic Reconfiguration Port bus clock.
DEN I 1
Dynamic Reconfiguration Port bus enable when set to a
logic 1.
DI I 16 Dynamic Reconfiguration Port input data bus.
DO O 16 Dynamic Reconfiguration Port output data bus.
DRDY O 1
DWE I 1
Indicates that the Dynamic Reconfiguration Port output data is
valid when raised to a logic 1.
Dynamic Reconfiguration Port write enable when set to a
logic 1.
Table 1-9: RocketIO MGT Communications Ports
Port I/O Port Size Definition
COMBUSOUT O 16
COMBUSIN I 16
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Connects to the COMBUSIN of the other GT11 in the tile to
allow proper simulation of shared clocks and PLLs.
Connects to the COMBUSOUT of the other GT11 in the tile to
allow proper simulation of shared clocks and PLLs.
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Attributes
An attribute is a control parameter used to configure the MGT. There are both primitive
ports (traditional I/O ports for control and status) and attributes. Transceiver attributes are
also controls to the transceiver that regulate data widths and encoding rules, but they are
controls that are configured as a group in “soft” form through the invocation of a primitive.
The MGT also contains attributes set by default to specific values. Included are channel
bonding settings and clock correction sequences. Ta bl e 1 -10 through Ta ble 1 -1 4 present a
brief description of each attribute. See the memory maps in Appendix C, “Dynamic
Reconfiguration Port” for the default values.
Tab le 1-1 0 through Tab le 1 -1 4 give all the modifiable attributes. Some attributes shown in
Appendix C, “Dynamic Reconfiguration Port” should not be changed from the default
settings. These attributes are indicated by footnotes in the DRP tables in Appendix C.
For all Boolean attributes shown as FALSE/TRUE, the FALSE state is the default. For
attributes shown as TRUE/FALSE, the TRUE state is the default.
Note:
dependencies between parameters and applies design-rule checks to prevent invalid configurations.
Xilinx recommends using the RocketIO wizard to set attributes. The wizard manages
Table 1-10: RocketIO MGT CRC Attributes
Attribute Type Description
RXCRCCLOCKDOUBLE Boolean
RXCRCINITVAL
32-bit
Hex
RXCRCSAMECLOCK Boolean
FALSE/TRUE. Selects clock frequency ratio between RXCRCCLK
and RXCRCINTCLK.
FALSE: Both clocks are at the same frequency.
TRUE: The fabric data interface clock RXCRCINTCLK is
operating at half the frequency of the internal clock RXCRCCLK.
See Chapter 5, “Cyclic Redundancy Check (CRC),” for more details.
Sets the receiver CRC initial value. This must be defined for each
protocol that uses 32-bit CRC:
Protocol Default Init Value
Ethernet
PCI-Express
Infiniband
Fibre Channel
Serial ATA 32’h 5232 5032
RapidIO
(1)
32’h 0000 0000
32’h FFFF FFFF
N/A
FALSE/TRUE. Select single clock mode for RX CRC.
FALSE: The clocks are being supplied to both the RXCRCCLK and
RXCRCINTCLK ports.
TRUE: The fabric interface clock rate is the same as the internal
clock rate (RXCRCCLOCKDOUBLE is FALSE); the CRC fabric
interface and internal logic are being clocked using
RXCRCINTCLK. This attribute is typically set to TRUE when
RXCRCCLOCKDOUBLE is set to FALSE.
See Chapter 5, “Cyclic Redundancy Check (CRC),” for more details.
RXCRCENABLE Boolean
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FALSE/TRUE. Enables the RX CRC block.
FALSE: RX CRC disabled.
TRUE: RX CRC enabled.
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Table 1-10: RocketIO MGT CRC Attributes (Continued)
Attribute Type Description
FALSE/TRUE. Inverts the receiver CRC clock.
RXCRCINVERTGEN Boolean
FALSE: CRC clock not inverted.
TRUE: CRC clock inverted.
During normal operation, this should always be set to FALSE.
FALSE/TRUE. Select clock frequency ratio between TXCRCCLK and
TXCRCINTCLK.
TXCRCCLOCKDOUBLE Boolean
FALSE: Both clocks are at the same frequency.
TRUE: The fabric data interface clock TXCRCINTCLK is
operating at half the frequency of the internal clock TXCRCCLK.
See Chapter 5, “Cyclic Redundancy Check (CRC),” for more details.
Sets the transmitter CRC initial value. This must be defined for each
protocol that uses 32-bit CRC:
Protocol Default Init Value
Ethernet
PCI-Express
Infiniband
Fibre Channel
Serial ATA 32’h 5232 5032
RapidIO
(1)
TXCRCINITVAL
32-bit
Hex
FALSE/TRUE. Selects single clock mode for TX CRC.
FALSE: The clocks are being supplied to both the TXCRCCLK and
TXCRCINTCLK ports.
TRUE: The fabric interface clock rate is the same as the internal
TXCRCSAMECLOCK Boolean
clock rate (TXCRCCLOCKDOUBLE is FALSE ); the CRC fabric
interface and internal logic are being clocked using
TXCRCINTCLK. This attribute is typically set to TRUE when
TXCRCCLOCKDOUBLE is set to FALSE.
See Chapter 5, “Cyclic Redundancy Check (CRC),” for more details.
Attributes
32’h FFFF FFFF
32’h 0000 0000
N/A
TXCRCENABLE Boolean
TXCRCINVERTGEN Boolean
Notes:
1. RapidIO uses a 16-bit CRC, which cannot be generated or checked using the MGT’s CRC-32 block.
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FALSE/TRUE. Enables the TX CRC block.
FALSE: TX CRC disabled.
TRUE: TX CRC enabled.
FALSE/TRUE. Inverts the transmitter CRC clock.
FALSE: CRC clock not inverted.
TRUE: CRC clock inverted.
During normal operation, this should always be set to FALSE.
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Table 1-11: RocketIO MGT PMA Attributes
Attribute Type Description
Calibration
FDET_HYS_CAL
FDET_HYS_SEL
FDET_LCK_CAL
FDET_LCK_SEL
LOOPCAL_WAIT
RXFDET_LCK_CAL
RXFDET_HYS_CAL
RXFDET_HYS_SEL
RXFDET_LCK_SEL
RXLOOPCAL_WAIT
RXFDET_CLOCK_DIVIDE
3-bit
Binary
3-bit
Binary
3-bit
Binary
3-bit
Binary
2-bit
Binary
3-bit
Binary
3-bit
Binary
3-bit
Binary
3-bit
Binary
2-bit
Binary
3-bit
Binary
Sets up the calibration circuitry. See “Calibration for the PLLs” in
Chapter 4 for more details.
Sets up the calibration circuitry. See “Calibration for the PLLs” in
Chapter 4 for more details.
Sets up the calibration circuitry. See “Calibration for the PLLs” in
Chapter 4 for more details.
Sets up the calibration circuitry. See “Calibration for the PLLs” in
Chapter 4 for more details.
Sets up the calibration circuitry.
Sets up the calibration circuitry. See “Calibration for the PLLs” in
Chapter 4 for more details.
Sets up the calibration circuitry. See “Calibration for the PLLs” in
Chapter 4 for more details.
Sets up the calibration circuitry. See “Calibration for the PLLs” in
Chapter 4for more details.
Sets up the calibration circuitry. See “Calibration for the PLLs” in
Chapter 4 for more details.
Sets up the calibration circuitry. See “Calibration for the PLLs” in
Chapter 4 for more details.
Sets up the calibration circuitry.
RXVCODAC_INIT
10-bit
Binary
Affects the characteristics of the calibration logic. See “Calibration for
the PLLs” in Chapter 4.
RXCPSEL Boolean Reserved. Use the RocketIO Wizard to set this attribute.
TXFDCAL_CLOCK_DIVIDE String None, two, four.
VCODAC_INIT
10-bit
Binary
Affects the characteristics of the calibration logic. See “Calibration for
the PLLs” in Chapter 4.
TXCPSEL Boolean Reserved. Use the RocketIO Wizard to set this attribute.
Drivers/Buffers
RXAFEEQ
9-bit
Binary
Receiver linear equalization control attributes. See “Receive
Equalization” in Chapter 4.
FALSE/TRUE.
RXDCCOUPLE Boolean
FALSE: Internal RX AC coupling capacitors enabled.
TRUE: Internal RX AC coupling capacitors bypassed.
RXEQ
TXDAT_TAP_DAC
64-bit
Hex
5-bit
Binary
Reserved. This feature is not supported. Use the RocketIO Wizard to
set this attribute.
Transmitter data amplitude control. See “Output Swing and
Emphasis” in Chapter 4.
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Table 1-11: RocketIO MGT PMA Attributes (Continued)
Attribute Type Description
Attributes
TXPOST_TAP_DAC
5-bit
Binary
TXHIGHSIGNALEN Boolean
TXPOST_TAP_PD Boolean
TXPRE_TAP_DAC
5-bit
Binary
TXPRE_TAP_PD Boolean
TXSLEWRATE Boolean
Transmitter post-cursor amplitude control. See “Output Swing and
Emphasis” in Chapter 4.
TRUE/FALSE. This attribute controls the line driver strength.
TRUE: XFP is not used
FALSE: XFP is used
See “Output Swing and Emphasis” in Chapter 4.
TRUE/FALSE. Transmitter post-cursor amplitude control.
TRUE: Disable post-cursor amplitude control
FALSE: Enable post-cursor amplitude control
See “Emphasis” in Chapter 4.
Note that this must be set FALSE for serial loopback to work
properly.
Transmitter pre-cursor amplitude control. See “Output Swing and
Emphasis” in Chapter 4.
TRUE/FALSE. Transmitter pre-cursor pre-emphasis control.
TRUE: Disable pre-cursor pre-emphasis
FALSE: Enable pre-cursor pre-emphasis
See “Emphasis” in Chapter 4.
FALSE/TRUE. Select reduced slew rate on transmitter output.
FALSE: Select standard output slew rate
TRUE: Select reduced output slew rate
TXTERMTRIM
Clocks
RXCLKMODE
RXOUTDIV2SEL Integer
RXPLLNDIVSEL Integer
RXPMACLKSEL String
RXRECCLK1_USE_SYNC Boolean
4-bit
Binary
6-bit
Binary
Resistive line driver termination trim. The default is 1100.
Sets the internal clocking modes. See Chapter 2, “Clocking, Timing,
and Resets.”
Frequency acquisition loop output divide. See Chapter 2, “Clocking,
Timing, and Resets” for setting the correct value.
Frequency acquisition loop feedback divide for the RX PLL. See
Chapter 2, “Clocking, Timing, and Resets” for setting the correct
value.
REFCLK1, REFCLK2, GREFCLK. Selects reference clock input for
receive PLL.
REFCLK1: Select REFCLK1 input (DRP value 00).
REFCLK2: Select REFCLK2 input (DRP value 01).
GREFCLK: Select GREFCLK input (DRP value 10).
See Chapter 2, “Clocking, Timing, and Resets” for more details.
FALSE/TRUE.
FALSE: RXRECCLK1 = synchronous PCS RXCLK
TRUE: RXRECCLK1 = asynchronous PCS RXCLK
See Chapter 2, “Clocking, Timing, and Resets” for more details.
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Table 1-11: RocketIO MGT PMA Attributes (Continued)
Attribute Type Description
REFCLK1, REFCLK2, GREFCLK. Selects reference clock input for
shared Tile transmit PLL.
TXABPMACLKSEL String
REFCLK1: Select REFCLK1 input (DRP value 00).
REFCLK2: Select REFCLK2 input (DRP value 01).
GREFCLK: Select GREFCLK input (DRP value 10).
See Chapter 2, “Clocking, Timing, and Resets” for more details.
TXCLKMODE
TXOUTCLK1_USE_SYNC Boolean
TXOUTDIV2SEL Integer
TXPHASESEL Boolean
TXPLLNDIVSEL Integer
Miscellaneous
RXCDRLOS
RXLKADJ
RXPD Boolean
4-bit
Binary
6-bit
Binary
5-bit
Binary
Sets the internal clocking mode. See Chapter 2, “Clocking, Timing,
and Resets”
FALSE/TRUE.
FALSE: TXOUTCLK1 = Asynchronous PCS TXCLK
TRUE: TXOUTCLK1 = Synchronous PCS TXCLK
See Chapter 2, “Clocking, Timing, and Resets” for more details.
Frequency acquisition loop output divide. See Chapter 2, “Clocking,
Timing, and Resets” for setting the correct value.
FALSE/TRUE.
FALSE: Selects GREFCLK for synchronization clock
TRUE: Selects PCS TXCLK for synchronization clock
Frequency acquisition loop feedback divide for TX PLL. See
Chapter 2, “Clocking, Timing, and Resets” for setting the correct
value.
These bits set the threshold value for the signal detector (OOB signal
detect). Use the RocketIO wizard to set this attribute.
Reserved. Use the RocketIO wizard to set this attribute.
FALSE/TRUE. Power-down selector for the receiver.
FALSE: Powers up receiver
TRUE: Powers down receiver
RXRSDPD Boolean
TXPD Boolean
PMACOREPWRENABLE Boolean
PMA_BIT_SLIP Boolean
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FALSE/TRUE. Signal detect logic power-down selector for the
receiver.
FALSE: Powers up receiver signal detect logic
TRUE: Powers down receiver signal detect logic
FALSE/TRUE. Power-down selector for the transmitter.
FALSE: Powers up transmitter
TRUE: Powers down transmitter
TRUE/FALSE.
TRUE: Powers up RXA, RXB, and TXAB
FALSE: Powers down RXA, RXB, and TXAB
FALSE/TRUE.
FALSE: Performs PCS clock phase alignment when RXSYNC is
set to logic 1.
TRUE: PCS clock phase alignment is disabled.
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Table 1-11: RocketIO MGT PMA Attributes (Continued)
Attribute Type Description
Attributes
RXCMADJ
2-bit
Binary
POWER_ENABLE Boolean
Reserved. Use the RocketIO wizard to set this attribute.
TRUE/FALSE.
TRUE: Powers up the PCS and Digital Receiver of the transceiver.
FALSE: Powers down the PCS and Digital Receiver of the
transceiver.
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Table 1-12: RocketIO MGT PCS Attributes
Attribute Type Description
Channel Bonding
CCCB_ARBITRATOR_DISABLE Boolean
CHAN_BOND_LIMIT
CHAN_BOND_MODE
CHAN_BOND_ONE_SHOT
CHAN_BOND_SEQ_1_1, 2, 3, 4
Integer
String
Boolean
11-bit
Binary
FALSE/TRUE. Determines if the clock correction/channel bonding
arbitrator is disabled or not.
FALSE: Arbitrator is enabled
When the arbitrator is enabled (default), clock correction and
channel bonding sequences are allowed to occur adjacently
without padding bytes. The clock correction always takes priority
over the channel bonding.
TRUE: Arbitrator disabled
Integer (1-31) defines maximum number of bytes a slave receiver can
read following a channel bonding sequence and still successfully
align to that sequence. The higher the CHAN_BOND_LIMIT, the
more skew the channel bonding circuit can tolerate.
CHAN_BOND_LIMIT must be less than one-half the minimum
spacing allowed between channel bonding sequences. For example,
the minimum number of characters between XAUI channel bonding
sequences is 16, so the CHAN_BOND_LIMIT must be less than 8.
STRING: NONE, MASTER, SLAVE_1_HOP, SLAVE_2_HOPS
NONE: No channel bonding involving this transceiver (DRP value
00).
MASTER: This transceiver is master for channel bonding. Its
CHBONDO port directly drives CHBONDI ports on one or more
SLAVE_1_HOP transceivers (DRP value 01).
SLAVE_1_HOP: This transceiver is a slave for channel bonding.
SLAVE_1_HOP’s CHBONDI is directly driven by a MASTER
transceiver CHBONDO port. SLAVE_1_HOP’s CHBONDO port can
directly drive CHBONDI ports on one or more SLAVE_2_HOPS
transceivers (DRP value 10).
SLAVE_2_HOPS: This transceiver is a slave for channel bonding.
SLAVE_2_HOPS CHBONDI is directly driven by a SLAVE_1_HOP
CHBONDO port (DRP value 11).
FALSE/TRUE. Controls repeated execution of channel bonding.
FALSE: Master transceiver initiates channel bonding whenever
possible (whenever channel-bonding sequence is detected in the
input) as long as input ENCHANSYNC is High and RXRESET is
Low.
TRUE: Slave transceiver initiates channel bonding only the first
time it is possible (channel bonding sequence is detected in input)
following negated RXRESET and asserted ENCHANSYNC. After
channel-bonding alignment is done, it does not occur again until
RXRESET is asserted and negated, or until ENCHANSYNC is
negated and reasserted.
These define the channel bonding sequence. The usage of these
vectors also depends on CHAN_BOND_SEQ_LEN and
CHAN_BOND_SEQ_2_USE. For details, see section entitled
“CHAN_BOND_SEQ_1_MASK, CHAN_BOND_SEQ_2_MASK,
CHAN_BOND_SEQ_LEN, CHAN_BOND_SEQ_*_* Attributes” in
Chapter 3.
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Table 1-12: RocketIO MGT PCS Attributes (Continued)
Attribute Type Description
Each bit of the mask determines if that particular sequence is
detected regardless of its value. For example, if bit 0 is High, then
CHAN_BOND_SEQ_1_1 is matched regardless of its value.
CHAN_BOND_SEQ_1_MASK
4-bit
Binary
These define the channel bonding sequence.The usage of these
vectors also depends on CHAN_BOND_SEQ_LEN and
CHAN_BOND_SEQ_2_1, 2, 3, 4
11-bit
Binary
CHAN_BOND_SEQ_2_USE. For details, see section entitled
“CHAN_BOND_SEQ_1_MASK, CHAN_BOND_SEQ_2_MASK,
CHAN_BOND_SEQ_LEN, CHAN_BOND_SEQ_*_* Attributes” in
Chapter 3.
Each bit of the mask determines if that particular sequence is
detected regardless of its value. For example, if bit 0 is High, then
CHAN_BOND_SEQ_2_1 is matched regardless of its value.
CHAN_BOND_SEQ_2_MASK
4-bit
Binary
FALSE/TRUE. Controls use of second channel bonding sequence.
FALSE: Channel bonding uses only one channel bonding
sequence defined by CHAN_BOND_SEQ_1_1... 4, OR one 8-byte
sequence defined by CHAN_BOND_SEQ_1...4 and
CHAN_BOND_SEQ_2_USE
Boolean
CHAN_BOND_SEQ_2_1...4 in combination.
TRUE: Channel bonding uses two channel bonding sequences
defined by CHAN_BOND_SEQ_1_1... 4 and
CHAN_BOND_SEQ_2_1... 4, as further constrained by
CHAN_BOND_SEQ_LEN.
Integer (1, 2, 3, 4, 8) defines length in bytes of channel bonding
CHAN_BOND_SEQ_LEN
Integer
sequence. This defines the length of the sequence the transceiver
matches to detect opportunities for channel bonding.
Clock Correction
FALSE/TRUE. Controls the use of clock correction logic.
FALSE: Permanently disable execution of clock correction (rate
CLK_CORRECT_USE Boolean
matching). Clock RXUSRCLK must be frequency-locked with
RXRECCLK1/RXRECCLK2 in this case.
TRUE: Enable clock correction (normal mode).
FALSE/TRUE. This signal selects if clock correction and channel
bonding occur relative to the encoded or decoded version of the
8B/10B stream.
CLK_COR_8B10B_DE
Boolean
FALSE: Encoded version is used. Must be set in conjunction with
RXDEC8B10BUSE. CLK_COR_8B10B_DE = RXDEC8B10BUSE.
TRUE: Decoded version is used
CLK_COR_MAX_LAT
CLK_COR_MIN_LAT
Integer
Integer
Integer (0-63) defines the upper threshold for clock correction in the
receive buffer.
Integer (0-63) defines the lower threshold for clock correction in the
receive buffer.
These define the sequence for clock correction. The attribute used
depends on the CLK_COR_SEQ_LEN and CLK_COR_SEQ_2_USE.
For details, see section “CLK_COR_SEQ_1_MASK,
CLK_COR_SEQ_2_MASK, CLK_COR_SEQ_LEN Attributes” in
CLK_COR_SEQ_1_1, 2, 3, 4
11-bit
Binary
Chapter 3.
Attributes
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Table 1-12: RocketIO MGT PCS Attributes (Continued)
Attribute Type Description
Each bit of the mask determines if that particular sequence is
detected regardless of its value. For example, if bit 0 is High, then
CLK_COR_SEQ_1_1 is matched regardless of its value.
CLK_COR_SEQ_1_MASK
4-bit
Binary
These define the sequence for clock correction. The attribute used
depends on the CLK_COR_SEQ_LEN and CLK_COR_SEQ_2_USE.
For details, see section “CLK_COR_SEQ_1_MASK,
CLK_COR_SEQ_2_MASK, CLK_COR_SEQ_LEN Attributes” in
CLK_COR_SEQ_2_1, 2, 3, 4
11-bit
Binary
Chapter 3.
Each bit of the mask determines if that particular sequence is
detected regardless of its value. For example, if bit 0 is High, then
CLK_COR_SEQ_2_1 is matched regardless of its value.
CLK_COR_SEQ_2_MASK
4-bit
Binary
FALSE/TRUE. Control use of second clock correction sequence.
FALSE: Clock correction uses only one clock correction sequence
defined by CLK_COR_SEQ_1_1... 4, OR one 8-byte sequence
CLK_COR_SEQ_2_USE
Boolean
defined by CLK_COR_SEQ_1_1... 4 and CLK_COR_SEQ_2_1... 4
in combination.
TRUE: Clock correction uses two clock correction sequences
defined by CLK_COR_SEQ_1_1... 4 and CLK_COR_SEQ_2_1... 4,
as further constrained by CLK_COR_SEQ_LEN.
Integer (1, 2, 3, 4, 8) that defines the length of the sequence the
transceiver matches to detect opportunities for clock correction. It
CLK_COR_SEQ_LEN
Integer
also defines the size of the correction, because the transceiver
executes clock correction by repeating or skipping entire clock
correction sequences.
Alignment
Integer (1, 2, 4) controls the alignment of detected commas within the
transceiver’s 4-byte-wide data path.
1 = Aligns commas within a 10-bit alignment range. As a result,
ALIGN_COMMA_WORD
Integer
the comma is aligned to any byte in the transceivers internal
data path.
2 = Aligns commas to any 2-byte boundary.
4 = Aligns commas to any 4-byte boundary.
FALSE/TRUE.
COMMA32 Boolean
FALSE: Comma alignment is set for 10 bits.
TRUE: Comma alignment is set for 32 bits. This is used for SONET
alignment applications.
These define the mask that is ANDed with the incoming serial
bitstream before comparison against PCOMMA_32B_VALUE and
MCOMMA_32B_VALUE.
COMMA_10B_MASK
10-bit
Hex
TRUE/FALSE.
TRUE: RXCOMMADET is raised when the data aligner matches
MCOMMA_DETECT Boolean
on MCOMMA_32B_VALUE.
FALSE: RXCOMMADET does not respond to
MCOMMA_32B_VALUE matches.
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Table 1-12: RocketIO MGT PCS Attributes (Continued)
Attribute Type Description
These define minus-comma for the purpose of raising
RXCOMMADET and realigning the serial bit stream byte boundary.
This definition does not affect 8B/10B encoding or decoding. Refer to
“8-Bit / 10-Bit Alignment” in Chapter 3 for more detailed
MCOMMA_32B_VALUE
32-bit
Hex
information. Also see COMMA_10B_MASK (above).
PCS_BIT_SLIP Boolean
Reserved. This feature is not supported. Use the RocketIO Wizard to
set this attribute.
TRUE/FALSE.
TRUE: RXCOMMADET is raised when the data aligner matches
PCOMMA_DETECT Boolean
on PCOMMA_32B_VALUE.
FALSE: RXCOMMADET does not respond to
PCOMMA_32B_VALUE matches.
These define plus-comma for the purpose of raising
RXCOMMADET and realigning the serial bit stream byte boundary.
This definition does not affect 8B/10B encoding or decoding. Refer to
“8-Bit / 10-Bit Alignment” in Chapter 3 for more detailed
PCOMMA_32B_VALUE
32-bit
Hex
information. Also see COMMA_10B_MASK (above).
8B/10B
TRUE/FALSE.
TRUE: Raises RXCHARISCOMMA if 10-bit data presented to
DEC_MCOMMA_DETECT Boolean
8B/10B Decoder matches a –ve disparity K-character as dictated
by DEC_VALID_COMMA_ONLY.
FALSE: RXCHARISCOMMA does not respond to –ve disparity
K-characters.
TRUE/FALSE.
TRUE: Raises RXCHARISCOMMA if 10-bit data presented to
DEC_PCOMMA_DETECT Boolean
8B/10B Decoder matches a +ve disparity K-character as dictated
by DEC_VALID_COMMA_ONLY.
FALSE: RXCHARISCOMMA does not respond to +ve disparity
K-characters.
TRUE/FALSE. Controls the raising of RXCHARISCOMMA on an
invalid comma.
TRUE: Raise RXCHARISCOMMA only on valid K28.1, K28.5 and
DEC_VALID_COMMA_ONLY Boolean
K28.7 characters.
FALSE: Raise RXCHARISCOMMA on:
xxx1111100 (if DEC_PCOMMA_DETECT is TRUE)
and/or on:
xxx0000011 (if DEC_MCOMMA_DETECT is TRUE)
64B/66B
(1)
SH_CNT_MAX
(1)
SH_INVALID_CNT_MAX
(1)
Integer Reserved. Use the RocketIO Wizard to set this attribute.
Integer Reserved. Use the RocketIO Wizard to set this attribute.
Attributes
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Table 1-12: RocketIO MGT PCS Attributes (Continued)
Attribute Type Description
Clocks
FALSE/TRUE. Determines if the PMA RXCLK0 or the RXUSRCLK is
chosen as the source for the PCS RXCLK in conjunction with
RX_CLOCK_DIVIDER and LOOPBACK[0].
FALSE:
♦ If RX_CLOCK_DIVIDER ≠ 00, PCS RXCLK is sourced by
RXUSRCLK
RXCLK0_FORCE_PMACLK Boolean
♦ If RX_CLOCK_DIVIDER = 00, PCS RXCLK is sourced by
PMA RXCLK0
♦ If LOOPBACK[0] = 1 and RX_CLOCK_DIVIDER = 00,
PCS RXCLK is sourced by PMA TXCLK0 (to facilitate parallel
loopback mode)
TRUE: PCS RXCLK is sourced by PMA RXCLK0
See Chapter 2, “Clocking, Timing, and Resets” and Figure 2-7,
page 74 for more details.
RX_CLOCK_DIVIDER
RXASYNCDIVIDE
2-bit
Binary
2-bit
Binary
RXUSRDIVISOR Integer
Controls the clock tree in the PCS. See Chapter 2, “Clocking, Timing,
and Resets” for more details.
Sets up the internal clocks. See Chapter 2, “Clocking, Timing, and
Resets” for setting to the correct value.
Selects the divisor for the clock received from the PMA. The divided
clock becomes RXRECCLK1. See Figure 2-5.
FALSE/TRUE. Determines if the PMA TXCLK0 or the TXUSRCLK is
chosen as the source for the PCS TXCLK in conjunction with
TX_CLOCK_DIVIDER.
FALSE:
♦ If TX_CLOCK_DIVIDER ≠ 00, PCS TXCLK is sourced by
TXCLK0_FORCE_PMACLK Boolean
TXUSRCLK
♦ If TX_CLOCK_DIVIDER = 00, PCS TXCLK is sourced by
PMA TXCLK0
TRUE: PCS TXCLK is sourced by PMA TXCLK0
See Chapter 2, “Clocking, Timing, and Resets” and Figure 2-8,
page 75 for more details.
TX_CLOCK_DIVIDER
TXASYNCDIVIDE
2-bit
Binary
2-bit
Binary
Controls the clock tree in the PCS. See Chapter 2, “Clocking, Timing,
and Resets” for more details.
Sets up the internal clocks. See Chapter 2, “Clocking, Timing, and
Resets” for setting to the correct value.
Buffers
TRUE/FALSE. Controls bypassing the RX ring buffer.
RX_BUFFER_USE Boolean
TRUE: RX ring buffer is used
FALSE: RX ring buffer is bypassed
TRUE/FALSE. Controls bypassing the TX buffer.
TX_BUFFER_USE Boolean
TRUE: TX buffer is used
FALSE: TX buffer is bypassed
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Table 1-12: RocketIO MGT PCS Attributes (Continued)
Attribute Type Description
Bypass Controls
RXDATA_SEL
TXDATA_SEL
Notes:
1. 64B/66B encoding/decoding is not supported.
2-bit
Binary
2-bit
Binary
Selects which blocks are bypassed in the RX PCS data path. See
“Ports and Attributes” in Chapter 8, “Low-Latency Design” for
more details.
Selects which blocks are bypassed in the TX PCS data path. See
“Ports and Attributes” in Chapter 8, “Low-Latency Design” for
more details.
Table 1-13: RocketIO MGT Digital Receiver Attributes
Attribute Type Description
DCDR_FILTER
DIGRX_FWDCLK
3-bit
Binary
2-bit
Binary
Attribute should be set to 000.
Selects receiver output clock when ENABLE_DCDR is TRUE. See
Chapter 2, “Clocking, Timing, and Resets” for details.
FALSE/TRUE.
FALSE: Disables the RX phase aligner. Should be set FALSE when
DIGRX_SYNC_MODE Boolean
RX Buffer is to be used.
TRUE: Enables the RX phase aligner. Should be set TRUE when
RX Buffer is to be bypassed
FALSE/TRUE. Select clock and data recovery (CDR) mode. Enables
the digital oversampling receiver.
ENABLE_DCDR Boolean
FALSE: Disables the oversampled digital receiver.
TRUE: Enables the oversampled digital receiver for data rates of
1.25 Gb/s and below.
FALSE/TRUE. Determines if internal data path is 40 or 32 bits for the
RXBY_32 Boolean
digital receiver.
FALSE: 40
TRUE: 32
(1)
Attributes
.
RXDIGRX Boolean
SAMPLE_8X Boolean
RXDIGRESET Boolean
Notes:
1. Buffer bypass mode used in conjunction with the digital receiver is not supported. DIGRX_SYNC_MODE must always be set to
FAL SE.
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FALSE/TRUE. Select clock and data recovery (CDR) mode.
FALSE: Allows PLL switch to lock to received data after lock to
the reference clock for data rates greater than 1.25 Gb/s.
TRUE: Enables PLL to lock continuously to the reference clock for
data rates of 1.25 Gb/s and below.
FALSE/TRUE. Determines the type of oversampling that is
implemented in the digital receiver. This should always be set to
TRUE.
FALSE/TRUE. Resets the deserializer.
FALSE: Enable receiver deserializer.
TRUE: Reset receiver deserializer.
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Table 1-14: MGT Tile Communication Attributes
Attribute Type Description
SINGLE, A, B, DONT CARE. Determines which MGT in the MGT
GT11_MODE String
tile is simulated. See Chapter 7, “Simulation and Implementation”
for details.
Byte Mapping
Most of the 8-bit wide status and control buses correlate to a specific byte of the TXDATA
or RXDATA. This scheme is shown in Tab le 1 -1 5. This creates a way to tie all the signals
together regardless of the data path width needed for the GT11_CUSTOM. Byte-mapped
signals always appear at the FPGA fabric interface on the same clock cycle.
Table 1-15: Control/Status Bus Association to Data Bus Byte Paths
Control/Status Bit Data Bits
[0] [7:0]
[1] [15:8]
[2] [23:16]
[3] [31:24]
[4] [39:32]
[5] [47:40]
[6] [55:48]
[7] [63:56]
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Clocking, Timing, and Resets
Clock Distribution
The RocketIO™ MGT clock distribution has changed from previous generations to
support the columnar architecture of the Virtex®-4 devices.
Column
A column consists of multiple MGT tiles containing two MGTs each. The MGT tile contains
routing for the PLL reference clocks and the clocks that are derived from the PLLs. The
clocks derived from the PLLs are forwarded to the FPGA global clock resources. Two lowjitter reference clock trees (SYNCLK1 and SYNCLK2) run the entire length of the column.
These SYNCLKs have the ability to route a clock completely up and down a column or to
become tile local clocks. See “GT11CLK_MGT and Reference Clock Routing,” page 63 for
more details.
Chapter 2
Tile
MGT
In a tile, each PLL can select its own RX reference clock and a shared TX reference clock.
This is because a single PLL is shared by the transmitters, whereas each receiver has an
independent PLL and CDR.
In a Virtex-4 device, there are eleven clock inputs into each Virtex-4 RocketIO MGT
instantiation. There are three reference inputs to choose from:
• Two column SYNCLKs, which drive the REFCLK1 and REFCLK2 inputs of the MGTs
• One tile local GREFCLK (for applications below 1 Gb/s).
The attributes in Figure 2-1 and Tab le 2- 3 show how to select the reference clock for the
three PLLs in a tile. These clocks are routed differentially in the FPGA to provide better
signal integrity.
The reference clock inputs should never be driven from a DCM because its output jitter is
too high. Only one of these reference clocks is needed to run the MGT. However, multiple
clocks can be used to implement multi-rate designs.
Most of the four user clocks (TXUSRCLK, TXUSRCLK2, RXUSRCLK, and RXUSRCLK2)
can be created within the MGT block without the use of a DCM. However, reference clocks
or several MGT clock outputs can be used to drive DCMs, which in turn create the
necessary clocks. Only DCM outputs CLK0 and DV are suitable; the FX output is not
supported. The clocking attributes and serial speed determine the reference clock speed, as
shown in Tab le 1- 3, “MGT Protocol Settings,” page 37.
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XC4VFX60 Reference Clock Selection
GREFCLK
Not
Connected
REFCLK
GREFCLK
MGTCLK
REFCLK
GREFCLK
Not
Connected
REFCLK
GT11CLK_MGT
REFCLKSEL
GT11CLK_MGT
REFCLKSEL
GT11CLK_MGT
REFCLKSEL
Reference Clock
Routing
Reference Clock
Routing
Reference Clock
Routing
REFCLK2
REFCLK1
REFCLK2
REFCLK1
REFCLK2
REFCLK1
Receive
PLL A
RXAPMACLKSEL
Shared
Transmit
PLL
TXABPMACLKSEL
Receive
PLL B
RXBPMACLKSEL
Receive
PLL A
RXAPMACLKSEL
Shared
Transmit
PLL
TXABPMACLKSEL
Receive
PLL B
RXBPMACLKSEL
Receive
PLL A
RXAPMACLKSEL
Shared
Transmit
PLL
TXABPMACLKSEL
Receive
PLL B
RXBPMACLKSEL
Dividers
Dividers
Dividers
Dividers
PMA RXBCLK
Dividers
Dividers
Dividers
Dividers
PMA RXBCLK
Dividers
Dividers
Dividers
Dividers
PMA RXBCLK
PMA RXCLK A
PMA TXCLK A
PMA TXCLK B
PMA RXCLK B
(1)
PMA RXCLK A
PMA TXCLK A
PMA TXCLK B
PMA RXCLK B
(1)
PMA RXCLK A
PMA TXCLK A
PMA TXCLK B
PMA RXCLK B
(1)
Tile 1
Tile 2
Tile 3
GREFCLK
GT11CLK_MGT
REFCLKSEL
MGTCLK
REFCLK
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REFCLK2
REFCLK1
Reference Clock
Routing
Note: (1) The PMA RXBCLK clock path is not suppor ted.
Receive
PLL A
RXAPMACLKSEL
Shared
Transmit
PLL
TXABPMACLKSEL
Receive
PLL B
RXBPMACLKSEL
Figure 2-1: MGT Column Clocking
Dividers
Dividers
Dividers
Dividers
PMA RXBCLK
PMA RXCLK A
PMA TXCLK A
PMA TXCLK B
PMA RXCLK B
(1)
Tile 4
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This chapter also includes several use models (see “Common Reference Clock Use
Models,” page 66). The use models illustrated here represent the most common
configurations, but other configurations are also possible.
GT11CLK_MGT and Reference Clock Routing
Each MGT tile contains a GT11CLK_MGT block implementable by instantiating either the
GT11CLK or GT11CLK_MGT ports and attributes shown in Tab le 2 -1 .
Clock Distribution
Note:
and GT11CLK module refer to the standard and advanced software primitives that access the block.
If no specific reference is made to “block” or “module,” the user should assume “module” is intended
and refers to the software primitives.
The term GT11CLK_MGT block refers to the hardware, whereas GT11CLK_MGT module
Each column must use its own dedicated MGTCLKP and MGTCLKN clock sources
implemented through the GT11CLK_MGT or GT11CLK module. MGTCLK signals cannot
be routed across the FPGA fabric, especially in designs where the data rate is 1 Gb/s or
higher, because excessive jitter results. MGTCLK source locations and package pinouts for
the various devices are shown in Tab le 7- 6 through Ta bl e 7 -1 0. To implement such a
connection, the GT11CLK_MGT should be instantiated. This is shown in Figure 2-2,
page 66.
In general, the GT11CLK_MGT module is always used. The GT11CLK module allows
more clocking options for MGTs in a given column, including feeding the fabric clock trees
via SYNCLK1 and SYNCLK2 to the REFCLK1 and REFCLK2 column buses. This
eliminates the need for individual connections through GREFCLK for multiple MGTs in
the same column.
Table 2-1: MGTCLK Ports and Attributes
GT11CLK GT11CLK_MGT I/O Description
Ports
SYNCLK1OUT SYNCLK1OUT O
SYNCLK2OUT SYNCLK2OUT O
This output drives the REFCLK1 column bus and the FPGA
clock trees.
This output drives the REFCLK2 column bus and the FPGA
clock trees.
MGTCLKN MGTCLKN I
MGTCLKP MGTCLKP I
REFCLK N/A I
RXBCLK N/A I Reserved. This clock port is not supported.
SYNCLK1IN N/A I
SYNCLK2IN N/A I
Attributes
REFCLKSEL N/A N/A
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This is the differential package input for the MGT column.
This input is from the FPGA fabric This reference clock should
only be used in sub-1 Gb/s operation. This allows a fabric clock
to access the SYNCLK buses.
This input is connected to SYNCLK1OUT of an adjacent
GT11CLK or GT11CLK_MGT.
This input is connected to SYNCLK2OUT of an adjacent
GT11CLK or GT11CLK_MGT.
Determines which clock input is used for the reference clock
(MGTCLK, RXBCLK, REFCLK, SYNCLK1IN, SYNCLK2IN).
Chapter 2: Clocking, Timing, and Resets
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Table 2-1: MGTCLK Ports and Attributes (Continued)
GT11CLK GT11CLK_MGT I/O Description
SYNCLK1OUTEN SYNCLK1OUTEN
SYNCLK2OUTEN SYNCLK2OUTEN
N/A
Allows the SYNCLK1OUT to drive the REFCLK1 column bus.
N/A Allows the SYNCLK2OUT to drive the REFCLK2 column bus.
MGT Clock Ports and Attributes
The RocketIO MGT has four groups of clocks: reference, user, MGT output, and CRC logic
clocks. The clock ports are shown in Tab le 2 -2 . Tab le 2-3 show how to select the reference
clock for the three PLLs in a tile.
Table 2-2: MGT Clock Ports
Clock I/O Description
Reference Clocks
GREFCLK I Alternate reference clock. (Used only for 1 Gb/s or slower applications.)
REFCLK1 I
REFCLK2 I
User Clocks
RXUSRCLK I Clocks the receiver PCS internal logic.
RXUSRCLK2 I Clocks the receiver PCS/ FPGA fabric interface.
Reference clock for the TX and RX PLLs. The multiplication ratio for parallel-toserial conversion is application dependent.
Reference clock for the TX and RX PLLs. The multiplication ratio for parallel-toserial conversion is application dependent.
TXUSRCLK I Clocks the transmitter PCS internal logic.
TXUSRCLK2 I Clocks the transmitter PCS/FPGA fabric interface.
MGT Output Clocks
RXRECCLK1 O
Fabric port that can be routed to the regional and global clock buffers using fabric
resources. Recovered clock from incoming data.
RXPCSHCLKOUT O Reserved. This clock port is not supported.
RXRECCLK2 O
Recovered clock from incoming data. Same as PCS RXCLK except in DCDR mode.
Please see section “Digital Receiver” in Chapter 3.
Fabric port that can be routed to the regional and global clock buffers using fabric
TXOUTCLK1 O
resources. Transmitter output clock derived from PLL based on transmitter
reference clock. Can be used to clock the FPGA.
TXPCSHCLKOUT O Reserved. This clock port is not supported.
TXOUTCLK2 O
Transmit output clock from the PCS TXCLK domain in the PCS. Source is
dependant on the PCS clock configuration.
RXMCLK O Reserved. This clock port is not supported.
CRC Clocks
RXCRCCLK I Clocks the internal receiver CRC logic.
RXCRCINTCLK I Clocks the CRC/FPGA fabric interface.
TXCRCCLK I Clocks the internal transmitter CRC logic.
TXCRCINTCLK I Clocks the CRC/FPGA fabric interface.
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Table 2-3: Clock Selection for Three PLLs in a Tile
Clock Distribution
Attribute String
Val ue
REFCLK1
REFCLK2
GREFCLK
Notes:
1. This attribute is only contained in MGTB for both MGTs in the tile.
2. Should only be used for 1 Gb/s or slower serial rates.
(2)
RXPMACLKSEL (MGTA) RXPMACLKSEL (MGTB)
REFCLK1 column bus
supplies MGTA RX PLL
REFCLK2 column bus
supplies MGTA RX PLL
GREFCLK column bus
supplies MGTA RX PLL
REFCLK1 column bus
supplies MGTB RX PLL
REFCLK2 column bus
supplies MGTB RX PLL
GREFCLK column bus
supplies MGTB RX PLL
The MGTCLK inputs drive the reference clocks that are low-jitter and must be used for the
fastest data rates (over 1 Gb/s).
Additionally, one of the FPGA fabric (global) clocks can be used as a reference clock for
single tiles at lower data rates (1 Gb/s or lower) via the GREFCLK input. If a fabric clock
needs to be routed along the REFCLK1 and REFCLK2 column busses, then the reference
clock input of the GT11CLK_MGT must be used.
Clocks derived from the MGT or from the MGT clock input can be forwarded to the FPGA
global clock resources. See “GT11CLK_MGT and Reference Clock Routing,” page 63.
The clock recovered from MGTB can be fed to GT11CLK to be used as a reference clock for
that tile or other tiles in the column. This implementation using the MGT’s RXMCLK
output and the GT11CLK module’s RXBCLK input is shown in Figure 2-1, page 62. This is
an unsupported test feature and is not recommended for normal operating modes.
TXPMACLKSEL
(MGT Tile – MGT A and MGT B)
REFCLK1 column bus supplies TX
PLL for both MGTs in the tile
REFCLK2 column bus supplies TX
PLL for both MGTs in the tile
GREFCLK column bus supplies TX
PLL for both MGTs in the tile
(1)
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GT11_inst1
REFCLK1
MGTCLK_P
MGTCLK_N
GT11CLK_MGT_inst1
SYNCLK1OUTEN = ENABLE
SYNCLK2OUTEN = DISABLE
GT11_inst2
REFCLK1
GT11_inst3
REFCLK1
MGTCLK_P
MGTCLK_N
GT11CLK_MGT_inst2
SYNCLK1OUTEN = DISABLE
SYNCLK2OUTEN = ENABLE
REFCLK2
REFCLK2
REFCLK2
UG076_CH2_04_021805
Common Reference Clock Use Models
High-Speed Dedicated MGT Clocks
Illustrated in Figure 2-2 is the common use case where the standard GT11CLK_MGT
module is used to route the dedicated MGTCLKP/N to the REFCLK1 and REFCLK2
inputs via the SYNCLK1 and SYNCLK2 column buses respectively.
Figure 2-2: High-Speed Dedicated Clocks (GT11CLK_MGT Instance)
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Fabric Clocks
There are two cases, illustrated here in Figure 2-3:
a. Direct connection to single tile (two MGTs) from GREFCLK pin, which does not
use the GT11CLK_MGT module.
b. REFCLK1 or REFCLK2 column bus routing by connecting the fabric clock to the
REFCLK input of the GT11CLK module.
(a) (b)
Clock from Global
Clock Tree Including
Other MGT Column
GT11_inst1
(MGTB of tile)
GREFCLK
GT11_inst2
(MGTA of tile)
Clock from Global
Clock Tree Including
Other MGT Column
SYNCLK1OUTEN = ENABLE
SYNCLK2OUTEN = DISABLE
REFCLKSEL = REFCLK
GT11CLK_inst1
Clock Distribution
GT11_inst1
REFCLK1
REFCLK2
GT11_inst2
REFCLK1
Clock from Global
Clock Tree Including
Other MGT Column
Note: inst1 cannot share GREFCLK
with inst2 and inst3 without using
fabric clocking resources.
GREFCLK
GT11_inst3
(MGTB of tile)
GREFCLK
Clock from Global
Clock Tree Including
Other MGT Column
SYNCLK1OUTEN = DISABLE
SYNCLK2OUTEN = ENABLE
REFCLKSEL = REFCLK
GT11CLK_inst2
GT11CLK input REFCLK
drives the entire column
via the SYNCLK clock trees.
Figure 2-3: REFCLK and GREFCLK Options for an MGT Tile
REFCLK2
GT11_inst3
REFCLK1
REFCLK2
UG076_CH2_06_050806
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Chapter 2: Clocking, Timing, and Resets
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PMA Transmit Clocks
The PMA transmit block has several clocking options. These options include several
dividers that determine the relationship between the parallel clocks (TXOUTCLK1 and
TXOUTCLK2) and the serial rates on TXP/TXN. These dividers are shown in Figure 2-4.
Tab le 2- 4 shows possible values of the TX PMA attributes that are used to create the
clocking relationships. Tab l e 2- 5 shows the possible combinations of the transmitter PLL
dividers.
Note:
Always use TXOUTCLK1, not TXOUTCLK2. TXOUTCLK2 is actually sourced from the PCS
TXCLK domain. For non-reduced-latency use models, this clock is sourced from the PMA parallel
clock driving the PISO. For reduced-latency use models, this clock is sourced from TXUSRCLK2 or
a derivative. Refer to Figure 2-8, page 75 for all of the PCS TXCLK muxing options.
TXCLKMODE[3]
TXCLKMODE [1]
Divider
/4
Divider
/5
Divider
/4
Divider
/5
Divider
/16.5
Serial Data
1
0
1
0
Note (4)
TXCLKMODE [0,2]
TXOUTCLK1_USE_SYNC
TXCLKSYNC
Note (1)
TXCLKASYNC
T
F
PCS
TXCLK
TREE
00
01
10
TXOUTCLK1
TXPCSHCLKOUT
TXP
TXN
ug076_ch2_02_061407
Note (5)
Note (6)
TXOUTCLK2
PLL
Ref Clk
Parallel Data
Phase
Frequency
Detector
Lock
Detect
Charge Pump
Loop Filter
VCO
Lock
Divide by 8,
10, 16, 20,
32 or 40
TXPLLNDIVSEL
TXOUTDIV2SEL
,
Divide by
1, 2, 4, 8,
,
16, or 32
TXASYNCDIVIDE[1:0]
Divider
Divider
Divider
Divider
Serial
Clock
Note (3)
PISO
/4
/1
00
01
/2
10
/4
Parallel Clock
Note (2)
Figure 2-4: MGT Transmit Clocking
Notes:
1. Refer to Figure 2-8, page 75 for PCS TXCLK domain muxing options.
2. This clock is always /32 or /40 of the line rate, or /16 or /20 of the serial clock.
Example: For 8B/10B data at 2.5 Gb/s, it should be set to /20 (TXCLKMODE[3] = 0).
3. The PISO is a 1/2-rate architecture, so the serial clock = 1/2 the line rate. Therefore, to determine the
proper settings for TXPLLNDIVSEL and TXOUTDIVSEL2, the appropriate VCO frequency must be
considered:
VCO Frequency = Reference Clock Frequency x TXPLLNSIVSEL
Serial Clock Frequency = VCO Frequency / TXOUTDIV2SEL
Examples:
For a 2.5 Gb/s application with 10-bit symbols and a 125 MHz reference clock:
2.5 Gb/s = 125 Mhz x TXPLLNSIVSEL
TXPLLNSIVSEL = 20
For a 2.5 Gb/s line rate, the serial clock = 1.25 Gb/s:
1.25 Gb/s = 2.5 Gb/s / TXOUTDIV2SEL
TXOUTDIV2SEL = 2
4. This path must be used if TXOUTCLK1 is used to generate the PCS user clocks for low-latency
applications requiring bypass of the PCS TXBUFFER. Refer to Chapter 8 for details.
5. TXOUTCLK1 is a fabric port.
6. TXPCSHCLKOUT port is not supported.
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Table 2-4: TX PMA Attribute Values
Attribute
TXPLLNDIVSEL
TXOUTDIV2SEL
TXASYNCDIVIDE
TXCLKMODE
TXOUTCLK1_USE_SYNC
Notes:
1. See Figure 2-12 for application-specific settings.
Available
40, 32, 20, 16,
1, 2, 4, 8, 16, 32
00, 01,
0110, 0100,
1000, 1001,
0000, 1110,
TRUE, FALSE
(1)
Val ues
10, 8
10, 11
1111
Definition
Transmit PLL feedback divide. This value
becomes the PLL multiplication factor for the
reference clock.
Transmitter PLL output divide. DRP values are
40 = 1010
32 = 1000
20 = 0110
16 = 0100
10 = 0010
8= 0000
TXOUTDIV2SEL value = DRP value:
1= 0001
2= 0010
4= 0011
8= 0100
16 = 0101
32 = 0110
Async Divide:
00= Divide by 1
01= Divide by 2
10= Divide by 4
11= Divide by 4
Divider Control for synchronous PCS TXCLK
and asynchronous PCS TXCLK. Refer to
Figure 2-4.
FALSE:
TXOUTCLK1 = Asynchronous PCS TXCLK
TRUE:
TXOUTCLK1 = Synchronous PCS TXCLK
:
Table 2-5: Supported Transmitter PLL Divider Combinations
Line Rate (Mb/s)
Min Max Min Max
4960 6500 1 8, 10 2480 3250
2480 4300 2 8, 10 2480 4300
3100 4300 2 16, 20 3100 4300
1240 2150 4 8, 10, 16, 20 2480 4300
622 1075 8 8, 10, 16, 20 2488 4300
Notes:
1. For lower wide-band jitter generation, choose a reference clock frequency that uses a lower feedback
divider.
2. Line Rate = VCO Frequency*2/TXOUTDIV2SEL.
3. Reference Clock = VCO Frequency/TXPLLNDIVSEL
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Output Divider
TXOUTDIV2SEL
Feedback Divider
TXPLLNDIVSEL
VCO Frequency (MHz)
Chapter 2: Clocking, Timing, and Resets
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PMA Receive Clocks
The PMA receive block has several clocking options. These options include several
dividers that determine the relationship between the parallel clocks (RXRECCLK1 and
RXRECCLK2) and the serial rates on RXP/RXN. These dividers are shown in Figure 2-5.
Tab le 2- 6 shows possible values of these RX PMA attributes that are used to create the
clocking relationships. Tab l e 2- 7 shows the possible combinations of the receiver PLL
dividers.
Note:
Always use RXRECCLK1, not RXRECCLK2. RXRECCLK2 is sourced from the digital
receiver input clock domain. For non-reduced-latency use models, this clock is sourced from the PMA
parallel clock driving the SIPO. For reduced-latency use models, this clock is sourced from
RXUSRCLK2 or a derivative. Refer to Figure 2-5 for all of the PCS RXCLK muxing options.
RXCLKMODE[2]
RXP
RXN
Ref Clk
Clock & Data
Recovery
Phase
Freq uency
Detector
Lock
Detect
Charge Pump
Lock
RXASYNCDIVIDE[1:0]
Divider
/1
Divider
/2
Divider
/4
Serial Clock
,
Loop Filter,
VCO
Divide by
8, 10, 16,
20, 32, or 40
RXPLLNDIVSEL
00
01
10
Divider
/4
Note (3)
Divide by
1, 2, 4, 8,
16, or 32
RXOUTDIV2SEL
PLL
Divider
/16.5
Divider
/4
Divider
/5
Divider
/4
Divider
/5
RXCLKMODE
1
Note (4)
0
1
0
SIPO
[5]
RXCLKMODE[4,1]
10
01
/1, /2, /4, /8, /16
00
Parallel
Clock
Note (2)
DigRx
1
0
RXCLKMODE[3]
RXUSRDIVISOR
Divider
DIGRX_FWDCLK
4XCLK
2XCLK
1XCLK
/8
0
1
RXCLKMODE[0]
[4:0]
RXRECCLK1_USE_SYNC
F
RXPCSHCLKOUT
T
10
01
Note (1)
00
RXDATA PARALLEL
ug076_ch2_24_071807
Note (5)
RXRECCLK1
Note (6)
RXRECCLK2
RXMCLK
Note (7)
Notes:
1. When DigRX block is disabled, the PMA parallel clock (PMA RXCLK0) is passed through but is affected
by RXRESET. Refer to Digrx section for details on how to configure this mux.
2. This clock is always /32 or /40 of the line rate, or /16 or /20 of the serial clock.
Example: For 8B/10B data at 2.5 Gb/s, it should be set to /20 (RXCLKMODE[5] = 0).
3. The SIPO is a 1/2-rate architecture, so the serial clock = 1/2 the line rate. Therefore, to determine the
proper settings for RXPLLNDIVSEL and RXOUTDIVSEL2, the appropriate VCO frequency must be
considered:
VCO Frequency = Reference Clock Frequency x RXPLLNSIVSEL
Serial Clock Frequency = VCO Frequency / RXOUTDIV2SEL
Examples:
For a 2.5 Gb/s application with 10-bit symbols and a 125 MHz reference clock:
2.5 Gb/s = 125 Mhz x RXPLLNSIVSEL
RXPLLNSIVSEL = 20
For a 2.5 Gb/s line rate, the serial clock = 1.25 Gb/s:
1.25 Gb/s = 2.5 Gb/s / RXOUTDIV2SEL
RXOUTDIV2SEL = 2
4. This path must be used if RXOUTCLK1 is used to generate the PCS user clocks for low-latency
applications requiring bypass of the PCS RXBUFFER. Refer to Chapter 8 for details.
5. RXRECCLK1 is a fabric port.
6. RXPCSHCLKOUT port is not supported.
7. RXMCLK port is not supported.
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Clock Distribution
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Table 2-6: RX PMA Attribute Values
Attribute
RXPLLNDIVSEL
Available
8, 10, 16, 20,
16, 32, 40
(1)
Val ues
RXOUTDIV2SEL 1, 2, 4, 8, 16, 32
RXUSRDIVISOR 1, 2, 4, 8, 16
See Figure 2-12
RXCLKMODE
and
Figure 2-11
RXASYNCDIVIDE
DIGRX_FWDCLK
00, 01,
10, 11
00, 01,
10, 11
RXRECCLK1_USE_SYNC FALSE/TRUE
Definition
Receive PLL feedback divide. This value
becomes the PLL multiplication factor for the
reference clock.
Receiver PLL output divide. DRP values are
:
40 = 1010
32 = 1000
20 = 0110
16 = 0100
10 = 0010
8= 0000
RXOUTDIV2SEL value = DRP value:
1= 0001
2= 0010
4= 0011
8= 0100
16 = 0101
32 = 0110
Selects the divisor for the clock received from
the PMA. The divided clock becomes
RXRECCLK1. See Figure 2-5.
RXUSRDIVISOR value = DRP value:
1= 00001
2= 00010
4= 00100
8= 01000
16 = 10000
Selects receiver output clocks and 32- or 40-bit
PMA output data path width. See “Setting the
Clocking Options” for correct settings.
Asynchronous Divider Ratios:
00=Divide by 1
01=Divide by 2
10=Divide by 4
11=Divide by 4
00= 1XCLK (4-byte clock)
01= 2XCLK (2-byte clock)
10= 4XCLK (1-byte clock)
FALSE:
RXRECCLK1 = synchronous PCS RXCLK
TRUE:
RXRECCLK1 = asynchronous PCS RXCLK
Notes:
1. See Figure 2-11 for application-specific settings.
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Table 2-7: Supported Receiver PLL Divider Combinations
Receiver
Mode
Line Rate
(Mb/s)
Output Divider
RXOUTDIV2SEL
Feedback Divider
RXPLLNDIVSEL
VCO Frequency
(MHz)
Min Max Min Max
4960 6500 1 8, 10 2480 3250
Analog
CDR
2480 4300 2 8, 10 2480 4300
3100 4300 2 16, 20 3100 4300
1250 2150 4 8, 10, 16, 20 2500 4300
Digital
CDR
Notes:
1. Line Rate (Analog CDR) = VCO Frequency*2/RXOUTDIV2SEL
2. Line Rate (Digital CDR) = VCO Frequency*2/8
3. Reference Clock = VCO Frequency/RXPLLNDIVSEL
622 1250 1 8, 10, 16, 20, 32, 40 2488 5000
RX and TX PLL Voltage-Controlled Oscillator (VCO) Operating Frequency
The minimum VCO operating frequency is 2480 MHz. The maximum VCO operating
frequency is limited by the value of the output divider. Tab le 2-8 defines the valid VCO
operating frequency ranges for each output divider value. VCO operating frequencies
outside of these ranges are not supported.
Table 2-8: Supported VCO Operating Frequency Ranges
Output Divider
[RX, TX]OUTDIV2SEL
VCO Frequency
Units
Minimum Maximum
1 2480 5000 MHz
2 2480
4 2480 MHz
8 2488
16
32
Notes:
1. When the output divider is equal to 8, the minimum VCO frequency is limited by the minimum data
rate of 622 Mb/s.
(1)
Not Supported —
4300
MHz
MHz
The VCO operating frequency ranges have a direct impact on line rate. Receiver operation
in analog CDR mode at line rates between 2.15 Gb/s–2.48 Gb/s and 4.3 Gb/s–4.96 Gb/s is
not supported. Transmitter operation at line rates between 1.075 Gb/s–1.24 Gb/s,
2.15 Gb/s–2.48 Gb/s, and 4.3 Gb/s–4.96 Gb/s is not supported.
Figure 2-6 illustrates the supported data rates for the Transmitter (Tx), the Receiver in
Digital CDR Mode (Rx DCDR), and the Receiver in Analog CDR Mode (Rx ACDR).
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Clock Distribution
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Rx
DCDR
Tx
622 Mb/s
1.075 Gb/s
Rx
ACDR
Tx Tx Tx
1.24 Gb/s
1.25 Gb/s
2.15 Gb/s
2.48 Gb/s
Rx
ACDR
4.3 Gb/s
Rx
ACDR
4.96 Gb/s
UG076_ch2_27_061407
6.5 Gb/s
Figure 2-6: Transmitter and Receiver Line Rates
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Chapter 2: Clocking, Timing, and Resets
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/
PMA/PCS Clocking Domains and Data Paths
There are several clocking domains within the PMA and PCS of the MGT’s receiver and
transmitter.
For the RX, there are four clock domains:
• PMA RXCLK0
• PCS RXCLK
• RXUSRCLK
• RXUSRCLK2
Similarly for the TX, there are four clock domains:
• TXUSRCLK2
• TXUSRCLK
• PCS TXCLK
• PMA TXCLK0
Figure 2-7 illustrates the four RX domains, and Figure 2-8 illustrates the TX domains.
Chapter 8, “Low-Latency Design” addresses use of the various bypass features and their
interaction with the clock domains.
00 11 01 10
Ring
Buffer
RX_BUFFER_USE
RX_CLOCK_DIVIDER
RXUSRCLK RXUSRCLK2
T
10GBASE-R
F
Decode
RXCLK0_FORCE_PMACLK, LOOPBACK[0],
RX_CLOCK_DIVIDE
PMA TXCLK0
1XXX 0100
0000 0X11 0X01 0X10
PMA RXCLK0
Sync Control Logic
10GBASE-R
RXP
RXN
SIPO
PCS
Dividers
& Phase
Align
PMA PCS
Note: (1) 64B/66B encoding/decoding is not supported.
Comma
Detect
Align
ENMCOMMAALIGN
ENPCOMMAALIGN
Block
(1)
Sync
Clock
Control
RXBLOCKSYNC64B66BUSE,
RXCOMMADETUSE
PCS
RXCLK
Channel Bonding &
Clock Correction
11
01
00
8B/10B
Decode
64B/66B
Descram
10
13x64 bit
01
(1)
00
RXDEC8B10BUSE,
RXDESCRAM64B66BUSE
Figure 2-7: PCS Receive Clocking Domains and Datapaths
÷2
÷4
000
100
(1)
011
010
001
RXDEC64B66BUSE,
RXDATA_SEL
RXUSRCLK
RXUSRCLK2
RXDATA
RXCHARISK
Fabric Interface
...ETC
RXRECCLK1
RXRECCLK2
ug076_ch8_01_061507
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PMA/PCS Clocking Domains and Data Paths
R
TXUSRCLK
÷2
TXUSRCLK2
TXUSRCLK2 TXUSRCLK
TXOUTCLK1/
TXOUTCLK2
TXDATA (2,4,8B)
TXCHARISK
ETC.
÷4
Fabric Interface
Note: (1) 64B/66B encoding/decoding is not supported.
TX_CLOCK_DIVIDER
8B/10B
Encode
10GBASE-R
(1)
Encode
TXENC8B10BUSE,
TXENC64B66BUSE
TXCLK0_FORCE_PMACLK,
TX_CLOCK_DIVIDER
00
110110
00
10
8x40 bit
Ring
01
Buffer
010
F
T
TX_BUFFER_USE
001 011 000
PCS
TXCLK
Clock Control
10GBASE-R
Gearbox
64B/66B
Scrambler
1XX
0001
0010
0000
(1)
1100
(1)
TXSCRAM64B66BUSE,
TXGEARBOX64B66BUSE,
TXDATA_SEL
PMA TXCLK0
PCS Dividers &
Phase Align
ug076_ch8_02_071807
PISO
TXP
TXN
PMAPCS
Figure 2-8: PCS Transmit Clocking Domains and Datapaths
PMA Configurations
There are several configurations of the PMA that also affect serial speeds and clocking
schemes.
with attributes. These settings are covered in Figure 2-11 and Figure 2-12.
These configurations can be modified by the Dynamic Reconfiguration Port or
Virtex-4 RocketIO MGT User Guide www.xilinx.com 75
UG076 (v4.1) November 2, 2008
Chapter 2: Clocking, Timing, and Resets
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Common MGT Clocking Use Cases
Figure 2-9 and Figure 2-10 show the common clocking use models that the MGT supports.
Note:
TXOUTCLK1/TXOUTCLK2 / RXRECCLK1/RXRECCLK2 connect to local and regional
clocking. A connection of these clocks to BUFG is possible with the use of fabric interconnect.
The PMA has parallel clock dividers
that can provide TXOUTCLK1 to the
1-byte, 2-byte, or 4-byte USRCLK2
Reference Clock
BUFR
User DATA
(1)
TX Fabric LogicRX Fabric Logic
REFCLK
TXOUTCLK1
TXDATA
TXCHARDISPMODE
TXCHARDISPVAL
TXCHARISK
ETC.
TXUSRCLK2
TXUSRCLK
RXUSRCLK2
RXUSRCLK
PCS has internal dividers
to generate the /1, /2, or
/4 USRCLKs.
User DATA
synchronous to
recovered clock
RXDATA
RXCHARISCOMMA
RXRUNDISP
RXCHARISK
ETC.
The PMA has parallel clock
dividers that can provide
RXRECCLK1 to the 1-byte,
2-byte,or 4-byte USRCLK2.
(1)
BUFR
No latency
requirement to regional
or global clock tree
since phase alignment is handled in MGT.
Notes: 1. BUFG connect is possible with TXOUTCLK1 or RXRECCLK1 with the use of fabric interconnect.
RXRECCLK1
GT11
ug076_ch2_10_061507
Figure 2-9: Low-Latency Clocking
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Setting the Clocking Options
R
Reference
Clock
Note: Only DCM outputs CLK0
and DV are suitable; the FX
output is not supported
User DATA
CLKIN
DCM
User DATA
REFCLK1
TXOUTCLK1
TXDATA
TXCHARDISPMODE
TXCHARDISPVAL
TXCHARISK
Etc.
TX Fabric LogicRX Fabric Logic
.
GT11
TXUSRCLK2
RXUSRCLK2
TXUSRCLK
RXUSRCLK
RXDATA
RXCHARISCOMMA
RXRUNDISP
RXCHARISK
Etc.
Interface
Width
1 Byte
2 Byte
4 Byte
8 Byte
USRCLK2 to
USRCLK Ratio
4:1
2:1
1:1
1:2
Setting the Clocking Options
Because of the MGT’s flexibility, there are many different clocking modes available. The
RocketIO wizard can automatically configure the MGT clocking options for any rate
supported by the device.
Note:
frequencies to clock data, it is recommended to use TXOUTCLK1 and RXRECCLK1 in conjunction
with the internal clock dividers.
The reference clock can directly drive the USRCLKs. Because most cases require multiple
RXRECCLK1
Figure 2-10: DCM Clocking
Note: DCM is not needed
for the 4-byte mode.
ug076_ch2_11_051106
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UG076 (v4.1) November 2, 2008
Chapter 2: Clocking, Timing, and Resets
R
is line
rate > 5 G
is line rate
>2.5G
NO
NO
NO
NO
RXOUTDIV 2 SEL
= / 1
VCO rate = line
rate / 2
= / 2
VCO rate = line
rate
= / 4
VCO rate = 2 * line
rate
= / 1
VCO rate = 4 * line
rate
= / 2
VCO rate =
8 * line rate
Set RXPLLNDIVSEL
(1)
= VCO rate/refclk
NO
YES
YES
YES
YES
YES
STA RT
line rate
SAMPLE _ 8 X
= TRUE
SAMPLE _ 8 X
= TRUE
ENABLE _ DCDR
= FA LSE
RXDIGRX = FA LSE
Turn off
RXMCLK
( 2 )
?
RXCLKMODE [ 0 ]
= 0
RXCLKMODE [ 3 ]
= 0
RXCLKMODE [ 0 ]
= 1
RXCLKMODE [ 3 ]
= 0
YES
NO
2 byte fabric
interface
DIGRX _ FWDCLK
= 00
DIGRX _ FWDCLK
= 01
DIGRX _ FWDCLK
= 10
1 byte fabric
interface
YES
YES
NO
NO
1. Modify refclk frequency for valid (8, 10, 16, 20, 32, 40)
RXPLLNDIVSEL values. The lower value generates better
performance.
2. RXMCLK clock port is not supported.
3. Channel Bonding, Clock Correction, and 8-byte fabric
interface are not available in low latency mode.
4. RXRECCLK1 and RXRECCLK2 are never the same in the
mode when RXRECCLK2_USE_SYNC is set to false
regardless of low latency mode usage. There is no use model
that needs these to be the sa
me.
5. Max serial rate for 1 byte I/F is 2.5 Gb/s.
Max serial rate for 2 byte I/F is 5.0 Gb/s.
6. This mode requires that USRCLK be provided by the fabric.
7. Channel Bonding requires that the USRCLK is provided via the
fabric.
8. 64B/66B encoding/decoding is not supported.
ug076_ch2_08a_071807
RXOUTDIV 2 SEL
RXOUTDIV 2 SEL
RXOUTDIV 2 SEL
RXOUTDIV 2 SEL
Is fabric
interface
4 bytes?
Is line rate
>1.25G
Is line rate
>0.625G
(cont'd on next page)
ENABLE_DCDR
= FALSE
RXDIGRX=FALSE
ENABLE_DCDR
= FALSE
RXDIGRX=FALSE
ENABLE_DCDR
= TRUE
RXDIGRX
= TRUE
<0.625G
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Figure 2-11: Receive Clocking Decision Flow (Page 1 of 2)
UG076 (v4.1) November 2, 2008
R
64B/66B
decoding?
(8)
RXCLKMODE[5:4] = 11
RXCLKMODE[2:1] = 10
RXCLKMODE[5:4] = 00
RXCLKMODE[2:1] = 01
RXCLKMODE[5:4] = 10
RXCLKMODE[2:1] = 11
NO
NO
NO
YES
YES
YES
RXASYNCDIVIDE
NO
NO
SONET or no
decoding
YES
YES
Provide
USRCLK?
(7)
exter nally?
1-byte fabric
interface
2-byte fabric
interface
4-byte fabric
interface
2-byte fabric
interface
(5)
8-byte fabric
interface
(6)
4-byte fabric
interface
Is it a 1-byte fabric
interface?
(5)
RX_CLOCK_DIVIDER
= 00
= 00 = 01 = 10 = 10
= 10 = 01 = 11
NO
NO
NO
YES
YES
YES
DONE with
RX
Settings
Is RXDIGRX =
TRUE?
DIGRX_SYNC_MODE = 1
DIGRX_SYNC_MODE = 0
ug076_ch2_08b_072607
(cont'd from previous page)
YES
YES
NO
NO
RX_CLOCK_DIVIDER = 00
RXCLK0_FORCE_PMACLK = TRUE
RXCLK0_FORCE_PMACLK = FALSE
RXCLK0_FORCE_PMACLK = TRUE
YES
NO
Does
RXDIGRX =
TRUE
RXRECCLK1_USE_SYNC
= FALSE
RXRECCLK1_USE_SYNC
= TRUE
8B/10B
decoding?
Low Latency
Mode?
(3)(4)
Setting the Clocking Options
Figure 2-11 (Cont’d): Receive Clocking Decision Flow (Page 2 of 2)
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UG076 (v4.1) November 2, 2008
Chapter 2: Clocking, Timing, and Resets
R
STA RT
is line
rate >5G
YES
TXOUTDIV2SEL
= /1
VCO rate = line
rate/2
Set TXPLLNDIVSEL
= VCO rate/refclk
(1)
YES
TXOUTCLK1_USE_SYNC
= FALSE
NO
is line rate
>2.5G
YES
TXOUTDIV2SEL
= /2
VCO rate = line
rate
NO
NO
is line rate
NO
>1.25G
YES
is line rate
NO
>0.625G
YES
TXOUTDIV2SEL
= /4
VCO rate = 2*line
rate
1. Modify refclk frequency for valid (8, 10, 16, 20, 32, 40)
TXPLLNDIVSEL values. The lower value
generates better performance.
2. Channel Bonding, Clock Corection, 64B66B,
and 8-byte fabric interface are not available
in low latency mode.
3. TXOUTCLK1 and TXOUTCLK2 are never the
same in the mode when TXOUTCLK1_USE_SYNC
is set to false regardless of low latency mode
usage. There is no use model that needs these to
be the same.
x serial rate for 1-byte I/F is 2.5 Gb/s.
4. Ma
Max serial rate for 2-byte I/F is 5.0 Gb/s.
5. This mode requires that USRCLK be provided by
the fabric.
6. When Channel Bonding, the RXUSRCLK must be
generated from the fabric for all bonded MGTs.
7. 64B/66B encoding/decoding is not supported.
TXOUTDIV2SEL
= /8
VCO rate = 4*line
rate
TXOUTDIV2SEL
VCO rate = 8*line
line rate
<0.625G
= /16
rate
Use 8B/10B?
YES
TXCLKMODE[3:0]
= 0100
(cont'd on next page)
Figure 2-12: Transmit Clocking Decision Flow (Page 1 of 2)
80 www.xilinx.com Virtex-4 RocketIO MGT User Guide
NO
Use
(7)
64B/66B?
YES
TXCLKMODE[3:0]
= 1001
NO
Use SONET
or no
encoding
TXCLKMODE[3:0]
= 1110
ug076_ch2_09a_061507
UG076 (v4.1) November 2, 2008
Setting the Clocking Options
R
FI
(cont's from previous page)
Is it a 1 -byte fabric
interface
?
( 4 )
YES
NO
2 -byte fabric
interface
( 4 )
YES
YES
TXASYNCDIVIDE
= 00 = 01 = 10 = 10
TX_CLOCK_DIVIDER = 00
TXCLK0_FORCE_PMACLK = TRUE
NO
Low latency mode?
YES
(2)(3)
TXCLK0_FORCE_PMACLK = TRUE
TXCLK0_FORCE_PMACLK = FALSE
NO
4 -byte fabric
interface
NO
8 -byte fabric
interface
( 5 )
Provide
USRCLK
externally?
YES
(6)
NO
-byte fabric
1
interface
YES
NO
2 -byte fabric
interface
YES
NO
4 -byte fabric
interface
TX _ CLOCK _ DIVIDER
= 00 = 10 = 01 = 11
DONE with TX
settings
ug076_ch2_09b_072607
Figure 2-12 (Cont’d): Transmit Clocking Decision Flow (Page 2 of 2)
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UG076 (v4.1) November 2, 2008
Chapter 2: Clocking, Timing, and Resets
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Special Clocking Considerations
RXCLKSTABLE and TXCLKSTABLE
In some systems, there are cases where the reference clock is not available when the MGT
and FPGA come out of configuration. The MGT PLL needs to know when its reference
clock is stable and when to try to lock. In one such case — when external cleanup PLLs are
used — RXCLKSTABLE and TXCLKSTABLE should be used as shown in Figure 2-13.
When the reference clock is known to be ready before the MGT, these signals should be set
to a logic 1.
CLKOUT
External
Clean-up PLL
REFCLK 1 REFCLK 1
GT11
RXCLKSTABLE
TXCLKSTABLE
LOCKED
GT11
RXCLKSTABLE
TXCLKSTABLE
CLKIN
Virtex-4 FX Device
RXRECCLK1/
RXRECCLK2
GT11
REFCLK 1
OSC
Figure 2-13: External PLL Locked Signal for MGT
ug076_ch2_14_050806
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R
Resets
Resets
The MGT has several different resets shown in Tab le 2- 9. The resets affect different
portions of the MGT. RXRESET and TXRESET reset the PCS portions of the transceiver.
RXPMARESET and TXPMARESET reset the PMA portion of the transceiver. There are also
two CRC logic resets (see Chapter 5, “Cyclic Redundancy Check (CRC)”).
Table 2-9: MGT Reset Signals
Reset Description
RXCRCRESET Resets the receiver CRC logic.
TXCRCRESET Resets the transmitter CRC logic.
RXPMARESET Resets the receiver PMA logic.
TXPMARESET Resets the transmitter PMA logic.
TXRESET Resets the transmitter PCS logic.
RXRESET Resets the receiver PCS logic.
TXPMARESET
The TXPMARESET port is used to reset the PMA and reinitialize the PMA functions.
Asserting this signal resets PLL control logic and the internal PMA dividers. It also causes
the transmit PLL lock signal TXLOCK to be deasserted and forces the TX PLL into
calibration. During the time TXPMARESET is asserted, the PMA parallel clocks
TXOUTCLK1 and TXOUTCLK2 output to the fabric remains at a constant 0. The data that
remains in the parallel-to-serial converter after asserting TXPMARESET is transmitted on
the serial lines (TXN/TXP ports). Since TXPMARESET forces the PLL into calibration, the
frequency of the transmitted data is not guaranteed to be correct until the PLL is locked.
Below is a list of requirements for TXPMARESET:
• Set TXPMARESET signal to logic 1 at startup for a minimum of three USRCLK cycles
(based on internal data width).
• Do not use the output clocks of the MGT for clocking this reset.
The parallel clock dividers used to generate each transmitter’s TXOUTCLK1 and
TXOUTCLK2 clocks are controlled by the TXPMARESET ports of MGTA and MGTB.
Calibration of the shared transmitter VCO is reset only by the TXPMARESET signal of
MGTA. (The MGT tile contains one Tx PLL and two separate parallel clock dividers.)
If the design uses:
• MGTA only: apply a TXPMARESET on MGTA.
• MGTB only: apply a TXPMARESET on both MGTA and MGTB.
RXPMARESET
The RXPMARESET port is used to reset the PMA and reinitialize the PMA functions.
Asserting this signal resets the PLL control logic. It also causes the receive PLL lock signal
RXLOCK to be deasserted and forces the RX PLL into calibration. During the time
RXPMARESET is asserted, the PMA parallel clocks RXRECCLK1 and RXRECCLK2 output
to the fabric does not remain at a constant 0, but its frequency is incorrect because the PLL
is not locked.
Following is a list of requirements for RXPMARESET:
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Chapter 2: Clocking, Timing, and Resets
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• Set RXPMARESET to logic 1 at startup for a minimum of three USRCLK cycles (based
on internal data width).
• Do not use the output clocks of the MGT for clocking this reset.
TXRESET
The TXRESET is used to bring every flip-flop in the TX PCS to a known value but does not
affect the PMA. When TXRESET is set to logic 1, the TX PCS is considered to be in reset.
Below is a list of requirements for TXRESET:
• Need to have stable clock on both the TXUSRCLK and PCS TXCLK domains on the
deassertion of TXRESET to obtain reliable pointer initialization of the TX buffer. (See
Figure 2-8, “PCS Transmit Clocking Domains and Datapaths,” page 75.)
• Set TXRESET signal to logic 1 for a minimum of three cycles of the slowest frequency
on TXUSRCLK or TXUSRCLK2.
• After deassertion of TXRESET, the TX PCS takes five cycles of the slowest frequency
on TXUSRCLK or TXUSRCLK2 for each clock domain to come out of reset.
• For 8-byte external data interface widths, TXRESET should be deasserted
synchronously to the falling edge of TXUSRCLK2 clock to ensure proper transmit
data ordering. See Figure 2-24, “TXRESET for 8-Byte External Data Interface Width,”
page 100.
RXRESET
The blocks affected by TXRESET are:
• Tx Fabric Interface — TXUSRCLK and TXUSRCLK2 domains
• 8B/10B Encode — TXUSRCLK domain
• Tx Buffer — TXUSRCLK and PCS TXCLK domains
See Figure 2-8, “PCS Transmit Clocking Domains and Datapaths,” page 75.
While TXRESET is asserted, the transmit data going into the PMA is all 0s.
The RXRESET is used to bring every flip-flop in the RX PCS to a known value but does not
affect the PMA. When the signal RXRESET is set to a logic 1, the RX PCS is considered in
reset. Below is a list of requirements for RXRESET:
• Need to have stable clock on both the RXUSRCLK and PCS RXCLK domains on the
deassertion of RXRESET to obtain reliable pointer initialization of the RX buffer. (See
Figure 2-7, “PCS Receive Clocking Domains and Datapaths,” page 74.)
• Set RXRESET signal to logic 1 for a minimum of three cycles of the slowest frequency
on RXUSRCLK or RXUSRCLK2.
• After deassertion of RXRESET, the RX PCS takes five cycles of the slowest frequency
on RXUSRCLK or RXUSRCLK2 for each clock domain to come out of reset.
• When channel bonding is used in conjunction with 1-byte and 2-byte external data
interface widths, RXRESET must be deasserted synchronously on all channel-bonded
MGTs with respect to RXUSRCLK2.
The blocks affected by RXRESET are:
• RX Fabric Interface — RXUSRCLK and RXUSRCLK2 domains
• 8B/10B Decode — RXUSRCLK domain
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R
• RX Buffer — RXUSRCLK and PCS RXCLK domains
• Channel Bonding & Clock Correction Logic — RXUSRCLK and PCS RXCLK domains
• Comma Detect Align — PCS RXCLK Domain
• Digital CDR
See Figure 2-7, “PCS Receive Clocking Domains and Datapaths,” page 74 for PCS receive
clocking domains and datapaths.
For Digital CDR, asserting RXRESET causes the PMA parallel clock RXRECCLK1 to stop
toggling (remain at a constant value).
CRC Reset
CRCRESET resets the CRC section of the transmitter (TXCRCRESET) and receiver
(RXCRCRESET). (See Chapter 5, “Cyclic Redundancy Check (CRC).”)
Proper assertion and deassertion of these resets are necessary to set up the CRC for use.
Resetting the Transceiver
This section describes different use cases of resetting the transceiver.
Resets
Transmit Reset Sequence: TX Buffer Used
Figure 2-14 provides a flow chart of the transmit reset sequence when the TX buffer is
used. Refer to the following points in conjunction with this figure:
• The flow chart uses TXUSRCLK as reference to the wait time for each state. Do not use
TXUSRCLK as the clock source for this block; this clock might not be present during
some states. Use a free-running clock (for example, the system's clock) and make sure
that the wait time for each state equals the specified number of TXUSRCLK cycles.
• It is assumed that the frequency of TXUSRCLK is slower than the frequency of
TXUSRCLK2. If TXUSRCLK2 is slower, use that clock as reference to the wait time for
each state.
• tx_usrclk_stable is a status signal from the user's application that is asserted High
when both TXUSRCLK and TXUSRCLK2 clocks are stable. For example, if a DCM is
used to generate both the TXUSRCLK and TXUSRCLK2 clocks, then the DCM
LOCKED signal can be used here.
• tx_pcs_reset_cnt is a counter from the user's application that is incremented every
time both TXBUFERR and TXLOCK signals are asserted. It is reset when the block
cycles back to the TX_PMA_RESET state.
• In synchronous systems like the GPON application where
RXRECCLK1/RXRECCLK2 is used for the TX PLL, the TX_SYSTEM_RESET state
should stall until there is a stable RXLOCK signal from the RX PLL (RXLOCK == 1 for
16K [16 x 1024] REFCLK cycles). The condition in going from TX_SYSTEM_RESET to
TX_PMA_RESET needs to be modified to:
♦ Analog CDR Mode:
!system_reset && (RXLOCK == 1 for 16K [16 x 1024] REFCLK cycles)
♦ Digital CDR Mode:
!system_reset && RXLOCK == 1
See “RX Reset Sequence Background,” page 100 for information on the 16K REFCLK cycles
requirement.
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Chapter 2: Clocking, Timing, and Resets
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TX_SYSTEM_RESET
system_reset==0
TX_PMA_RESET
TXPMARESET==1 for
3 TXUSRCLK cycles
TX_WAIT_LOCK
tx_usrclk_stable==1 && TXLOCK==1
TXLOCK==0
TXLOCK==0
TXLOCK==0
TXLOCK==0
TX_PCS_RESET
TXRESET==1 for
3 TXUSRCLK cycles
TX_WAIT_PCS
5 TXUSRCLK cycles
TX_ALMOST_READY
TXBUFERR==0 && TXLOCK==1
for 64 TXUSRCLK cycles
TX_READY
tx_pcs_reset_cnt==16 &&
TXBUFERR==1 &&
TXLOCK==1
tx_pcs_reset_cnt < 16 && TXBUFERR==1 && TXLOCK==1
TXBUFERR==1 && TXLOCK==1
Figure 2-14: Flow Chart of TX Reset Sequence Where TX Buffer Is Used
ug076_ch2_15_060606
Below are the steps describing the flow chart in Figure 2-14:
1. TX_SYSTEM_RESET: Upon TX system reset on this block, go to the TX_PMA_RESET
state.
TXPMARESET == 0
TXRESET == 0
2. TX_PMA_RESET: Assert TXPMARESET for three TXUSRCLK cycles.
TXPMARESET == 1
TXRESET == X
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Resets
R
TXUSRCLK
TXLOCK
TXRESET
TXBUFERR
Once T XBU FER R is monitored Low for some time, TX Link is READY
UG076_ch2_16_040606
3. TX_WAIT_LOCK: Stall until TXLOCK is High and until the clocks on TXUSRCLK and
TXUSRCLK2 are stable (tx_usrclk_stable == 1).
TXPMARESET == 0
TXRESET == X
4. TX_PCS_RESET: Assert TXRESET for three TXUSRCLK cycles. If TXLOCK is
deasserted, go back to TX_WAIT_LOCK state.
TXPMARESET == 0
TXRESET == 1
5. TX_WAIT_PCS: Wait for five TXUSRCLK cycles after deassertion of TXRESET. If
TXLOCK is deasserted, go back to TX_WAIT_LOCK state.
TXPMARESET == 0
TXRESET == 0
6. TX_ALMOST_READY: Wait for 64 TXUSRCLK cycles with no TX buffer errors and
TXLOCK High for this amount of time. This is to ensure that the TX MGT is stable after
start-up and ready for data transmission. If TXLOCK is deasserted, go back to
TX_WAIT_LOCK state. If there is a TXBUFERR detected while TXLOCK is High, the
reset sequence block should apply TXRESET by cycling back to the TX_PCS_RESET
state. If this step occurs 16 times, monitored by the tx_pcs_reset_cnt counter, apply a
TXPMARESET by cycling back to the TX_PMA_RESET state.
TXPMARESET == 0
TXRESET == 0
7. TX_READY: Once TXBUFERR is monitored Low for some time, the TX link is READY
for data transmission.
TXPMARESET == 0
TXRESET == 0
Figure 2-15 illustrates a timing diagram for resetting the transmitter when the TX buffer is
used. Refer to the flow chart in Figure 2-14 for more details.
Figure 2-15: Resetting the Transmitter Where TX Buffer Is Used
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UG076 (v4.1) November 2, 2008
Chapter 2: Clocking, Timing, and Resets
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Transmit Reset Sequence: TX Buffer Bypassed
Figure 2-16 provides a flow chart of the transmit reset sequence when the TX buffer is
bypassed.
TX_SYSTEM_RESET
system_reset==0
TX_PMA_RESET
TXPMARESET==1 for
3 TXUSRCLK cycles
TX_WAIT_LOCK
tx_usrclk_stable==1 && TXLOCK==1
for 12,000 TXUSRCLK2 cycles
TXLOCK==0
TXLOCK==0
TXLOCK==0
TXLOCK==0
TXLOCK==0
TX_SYNC
TXSYNC==1 for
64 synchronization clock cycles
TX_PCS_RESET
TXRESET==1 for
3 TXUSRCLK cycles
TX_WAIT_PCS
5 TXUSRCLK cycles
TX_ALMOST_READY
tx_align_err==0 && TXLOCK=1
for 64 TXUSRCLK cycles
TX_READY
tx_sync_cnt == 16 &&
tx_align_err==1 &&
TXLOCK==1
tx_sync_cnt < 16 && tx_align_err==1 && TXLOCK==1
tx_align_err==1 && TXLOCK==1
Figure 2-16: Flow Chart of TX Reset Sequence Where TX Buffer Is Bypassed
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Refer to the following points in conjunction with this figure:
• The flow chart uses TXUSRCLK and TXUSRCLK2 as reference to the wait time for
each state. Do not use TXUSRCLK and TXUSRCLK2 as the clock source for this block;
these clocks might not be present during some states. Use a free-running clock (for
example, the system's clock) and make sure the wait time for each state equals the
specified number of TXUSRCLK and TXUSRCLK2 cycles.
• It is assumed that the frequency on TXUSRCLK is slower than the one on
TXUSRCLK2. If TXUSRCLK2 is slower, use that clock as reference to the wait time for
each state. An exception to this requirement is the wait time between assertions of
TXLOCK and TXSYNC signals, from TX_WAIT_LOCK to TX_SYNC states; use the
specified TXUSRCLK2 in this step.
• See Figure 8-11, “TXSYNC Timing,” page 214 regarding the 12,000 TXUSRCLK2
cycles and the 64 synchronization clock cycles specified in this block.
• tx_usrclk_stable is a status signal from the user's application that is asserted High
when both TXUSRCLK and TXUSRCLK2 clocks are stable. For example, if a DCM is
used to generate both the TXUSRCLK and TXUSRCLK2 clocks, then the DCM
LOCKED signal can be used here.
• tx_align_err is a status from the user's application that is asserted High when there are
errors on the transmission of data as a result of the TX phase alignment not being
successful after TXSYNC is applied.
• tx_sync_cnt is a counter from the user's application that is incremented every time
both the tx_align_err and TXLOCK signals are asserted. It is reset when the block
cycles back to the TX_PMA_RESET state.
• In synchronous systems like the GPON application where
RXRECCLK1/RXRECCLK2 is used for the TX PLL, the TX_SYSTEM_RESET state
should stall until there is a stable RXLOCK signal from the RX PLL (RXLOCK == 1 for
16K [16 x 1024] REFCLK cycles). The condition in going from TX_SYSTEM_RESET to
TX_PMA_RESET needs to be modified to:
♦ Analog CDR Mode:
!system_reset && (RXLOCK == 1 for 16K [16 x 1024] REFCLK cycles)
♦ Digital CDR Mode:
!system_reset && RXLOCK == 1
See “RX Reset Sequence Background,” page 100 for information on the 16K REFCLK
cycles requirement.
Below are the steps describing the flow chart in Figure 2-16:
1. TX_SYSTEM_RESET: Upon TX system reset on this block, go to the TX_PMA_RESET
state.
TXPMARESET == 0
TXRESET == 0
TXSYNC == 0
2. TX_PMA_RESET: Assert TXPMARESET for three TXUSRCLK cycles.
TXPMARESET == 1
TXRESET == X
TXSYNC == 0
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3. TX_WAIT_LOCK: Stall until TXLOCK is High and until the clocks on TXUSRCLK and
TXUSRCLK2 are stable (tx_usrclk_stable == 1), then wait for 12,000 TXUSCLK2 cycles
and go to TX_SYNC state.
TXPMARESET == 0
TXRESET == X
TXSYNC == 0
4. TX_SYNC: Assert TXSYNC for 64 synchronization cycles. If TXLOCK is deasserted,
go back to TX_WAIT_LOCK state.
TXPMARESET == 0
TXRESET == X
TXSYNC == 1
5. TX_PCS_RESET: Assert TXRESET for three TXUSRCLK cycles. If TXLOCK is
deasserted, go back to TX_WAIT_LOCK state.
TXPMARESET == 0
TXRESET == 1
TXSYNC == 0
6. TX_WAIT_PCS: Wait for five TXUSRCLK cycles after deassertion of TXRESET. If
TXLOCK is deasserted, go back to TX_WAIT_LOCK state.
TXPMARESET == 0
TXRESET == 0
TXSYNC == 0
7. TX_ALMOST_READY: Wait for 64 TXUSRCLK cycles with TXLOCK High for this
amount of time. This is to ensure that the TX MGT is stable after start-up and ready for
data transmissi on. If TXLOCK is deasserted, go back to TX_WAIT_LOCK state. If there
is a TX alignment error from the user's application as a result of TXSYNC not being
successful, apply TXSYNC by cycling back to the TX_SYNC state. If this step occurs 16
times as monitored by the tx_sync_cnt counter, apply a TXPMARESET by cycling back
to TX_PMA_RESET state.
TXPMARESET == 0
TXRESET == 0
TXSYNC == 0
8. TX_READY: If the TX phase alignment is successful for some time, then the TX link is
ready.
TXPMARESET == 0
TXRESET == 0
TXSYNC == 0
In some systems, there might not be a feedback mechanism that can generate the
tx_align_err signal for the reset sequence. In those cases, users can implement the flow
illustrated in Figure 2-17 when the TX buffer is bypassed. The tx_align_err signal is not
strictly required, but it ensures stability in the user's system, preventing the system from
restarting while transmitting data.
Refer to the following points in conjunction with this figure:
• The flow chart uses TXUSRCLK and TXUSRCLK2 as reference to the wait time for
each state. Do not use TXUSRCLK and TXUSRCLK2 as the clock source for this block;
these clocks might not be present during some states. Use a free-running clock (for
example, the system's clock) and make sure that the wait time for each state equals the
specified number of TXUSRCLK and TXUSRCLK2 cycles.
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TX_SYSTEM_RESET
system_reset==0
TX_PMA_RESET
TXPMARESET==1 for
3 TXUSRCLK cycles
TX_WAIT_LOCK
tx_usrclk_stable==1 && TXLOCK==1
for 12,000 TXUSRCLK2 cycles
Resets
TXLOCK==0
TXLOCK==0
TXLOCK==0
TXLOCK==0
TX_SYNC
TXSYNC==1 for
64 synchronization clock cycles
TX_PCS_RESET
TXRESET==1 for
3 TXUSRCLK cycles
TX_WAIT_PCS
5 TXUSRCLK cycles
TX_READY
ug076_ch2_18_040406
Figure 2-17: Flow Chart of TX Reset Sequence Where TX Buffer Is Bypassed
and tx_align_err Is Not Used
• It is assumed that the frequency of TXUSRCLK is slower than the frequency of
TXUSRCLK2. If TXUSRCLK2 is slower, use that clock as reference to the wait time for
each state. An exception of this requirement is the wait time between assertions of
TXLOCK and TXSYNC signals, from TX_WAIT_LOCK to TX_SYNC states. Use the
specified TXUSRCLK2 in this step.
• See Figure 8-15, “TXSYNC Timing,” page 214 regarding the 12,000 TXUSRCLK2
cycles and the 64 synchronization clock cycles specified in this block.
• tx_usrclk_stable is a status signal from the user's application that is asserted High
when both TXUSRCLK and TXUSRCLK2 clocks are stable. For example, if a DCM is
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used to generate both the TXUSRCLK and TXUSRCLK2 clocks, then the DCM
LOCKED signal can be used here.
• In synchronous systems like the GPON application, where
RXRECCLK1/RXRECCLK2 is used for the TX PLL, the TX_SYSTEM_RESET state
should stall until there is a stable RXLOCK signal from the RX PLL (RXLOCK == 1 for
16K [16 x 1024] REFCLK cycles). The condition in going from TX_SYSTEM_RESET to
TX_PMA_RESET needs to be modified to
♦ Analog CDR Mode:
!system_reset && (RXLOCK == 1 for 16K [16 x 1024] REFCLK cycles)
♦ Digital CDR Mode:
!system_reset && RXLOCK == 1
See “RX Reset Sequence Background,” page 100 for information on the 16K REFCLK cycles
requirement.
Below are the steps describing the flow chart in Figure 2-17:
1. TX_SYSTEM_RESET: Upon TX system reset on this block, go to the TX_PMA_RESET
state.
TXPMARESET == 0
TXRESET == 0
TXSYNC == 0
2. TX_PMA_RESET: Assert TXPMARESET for three TXUSRCLK cycles.
TXPMARESET == 1
TXRESET == X
TXSYNC == 0
3. TX_WAIT_LOCK: Stall until TXLOCK is High and until the clocks on TXUSRCLK and
TXUSRCLK2 are stable (tx_usrclk_stable == 1), then wait for 12,000 TXUSCLK2 cycles
and go to TX_SYNC state.
TXPMARESET == 0
TXRESET == X
TXSYNC == 0
4. TX_SYNC: Assert TXSYNC for 64 synchronization cycles. If TXLOCK is deasserted,
go back to TX_WAIT_LOCK state.
TXPMARESET == 0
TXRESET == X
TXSYNC == 1
5. TX_PCS_RESET: Assert TXRESET for three TXUSRCLK cycles. If TXLOCK is
deasserted, go back to TX_WAIT_LOCK state.
TXPMARESET == 0
TXRESET == 1
TXSYNC == 0
6. TX_WAIT_PCS: Wait for five TXUSRCLK cycles after deassertion of TXRESET. If
TXLOCK is deasserted, go back to TX_WAIT_LOCK state.
TXPMARESET == 0
TXRESET == 0
TXSYNC == 0
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7. TX_READY: TX link is ready.
TXPMARESET == 0
TXRESET == 0
TXSYNC == 0
Figure 2-18 shows a timing diagram for resetting the transmitter when the TX buffer is
bypassed. Refer to Figure 2-16 and Figure 2-17 for more details.
TXUSRCLK
TXPMARESET
TXLOCK
TXSYNC
TXRESET
Once T X ph ase alignment error is monitored Low for some time, TX Link is READY
ug076_ch2_19_040606
Figure 2-18: Resetting the Transmitter Where TX Buffer Is Bypassed
Receive Reset Sequence: RX Buffer Used
Figure 2-19 provides a flow chart of the receive reset sequence when the RX buffer is used.
Refer to the following points in conjunction with this figure:
• The flow chart uses RXUSRCLK as reference to the wait time for each state. Do not use
RXUSRCLK as the clock source for this block; this clock might not be present during
some states. Use a free-running clock (for example, the system's clock) and make sure
that the wait time for each state equals the specified number of RXUSRCLK cycles.
• It is assumed that the frequency of RXUSRCLK is slower than the frequency of
RXUSRCLK2. If RXUSRCLK2 is slower, use that clock as reference to the wait time for
each state.
• rx_usrclk_stable is a status signal from the user's application that is asserted High
when both RXUSRCLK and RXUSRCLK2 clocks are stable. For example, if a DCM is
used to generate both the RXUSRCLK and RXUSRCLK2 clocks, then the DCM
LOCKED signal can be used here.
• rx_error is a status signal from the user's application that is asserted High to indicate
that there is either an RX buffer error (RXBUFERR==1) or a burst of errors on the
received data (RXDISPERR and/or RXNOTINTABLE signals are asserted).
• rx_pcs_reset_cnt is a counter from the user's application that is incremented every
time both the rx_error and RXLOCK signals are asserted. It is reset when the block
cycles back to the RX_PMA_RESET state.
• See “RX Reset Sequence Background,” page 100 for information on the 16K REFCLK
cycles requirement.
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RX_SYSTEM_RESET
system_reset==0
RX_PMA_RESET
RXPMARESET==1 for
3 RXUSRCLK cycles
RX_WAIT_LOCK
rx_usrclk_stable==1 && RXLOCK==1 for
16K (16 x 1024) REFCLK cycles
RXLOCK==0
RXLOCK==0
RXLOCK==0
RXLOCK==0
RX_PCS_RESET
RXRESET ==1 for
3 RXUSRCLK cycles
RX_WAIT_PCS
5 RXUSRCLK cycles
RX_ALMOST_READY
rx_error==0 && RXLOCK==1
for 64 RXUSRCLK cycles
RX_READY
rx_pcs_reset_cnt==16 &&
rx_error==1 &&
RXLOCK==1
rx_pcs_reset_cnt <16 && rx_error==1 && RXLOCK==1
rx_error==1 && RXLOCK==1
ug076_ch2_20_062806
Figure 2-19: Flow Chart of Receiver Reset Sequence Where RX Buffer Is Used
Below are the steps describing the flow chart in Figure 2-19:
1. RX_SYSTEM_RESET: Upon RX system reset on this block, go to the RX_PMA_RESET
state.
RXPMARESET == 0
RXRESET == 0
2. RX_PMA_RESET: Assert RXPMARESET for three RXUSRCLK cycles.
RXPMARESET == 1
RXRESET == X
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3. RX_WAIT_LOCK: Stall until RXLOCK is High and until the clocks on RXUSRCLK
and RXUSRCLK2 are stable (rx_usrclk_stable == 1). In addition:
♦ For Analog CDR mode, RX_WAIT_LOCK state should also stall until RXLOCK is
High for 16K (16 x 1024) REFCLK cycles. See “RX Reset Sequence Background,”
page 100 for information on the 16K REFCLK cycles requirement.
♦ For Digital CDR mode, since the RX PLL is locked to the reference clock, there is
no need to have RXLOCK be asserted High for a specific number of REFCLK
cycles.
RXPMARESET == 0
RXRESET == X
4. RX_PCS_RESET: Assert RXRESET for three RXUSRCLK cycles. If RXLOCK is
deasserted, go back to RX_WAIT_LOCK state.
RXPMARESET == 0
RXRESET == 1
5. RX_WAIT_PCS: Wait for five RXUSRCLK cycles after deassertion of RXRESET. If
RXLOCK is deasserted, go back to RX_WAIT_LOCK state.
RXPMARESET == 0
RXRESET == 0
6. RX_ALMOST_READY: Wait for 64 RXUSRCLK cycles with no error on the received
data and RXLOCK High for this amount of time. This is to ensure that the RX MGT is
stable after start-up and ready for data reception. If RXLOCK is deasserted, go back to
RX_WAIT_LOCK state. If there is an rx_error detected while RXLOCK is High, the
reset sequence block should apply RXRESET by cycling back to the RX_PCS_RESET
state. If this step occurs 16 times as monitored by the rx_pcs_reset_cnt counter, apply a
RXPMARESET by cycling back to the RX_PMA_RESET state.
RXPMARESET == 0
RXRESET == 0
7. RX_READY: Once rx_error is monitored Low for some time, the RX link is READY for
data reception.
RXPMARESET == 0
RXRESET == 0
Figure 2-20 and Figure 2-21 show timing diagrams of resetting the receiver where the RX
buffer is used. Refer to Figure 2-19 for more details.
RXUSRCLK
RXPMARESET
RXLOCK
RXRESET
RXBUF ERR
Figure 2-20: Resetting the Receiver in Digital CDR Mode Where RX Buffer Is Used
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Once R X er ror is monitored Low for some time, RX Link is READY
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RXUSRCLK
RXPMARESET
RXLOCK
RXRESET
RXBUF ERR
Once RX error is monitored Low for some time, RX Link is READY
Figure 2-21: Resetting the Receiver in Analog CDR Mode Where RX Buffer Is Used
Receive Reset Sequence: RX Buffer Bypassed
Figure 2-22 provides a flow chart of the receive reset sequence when the RX buffer is
bypassed.
Refer to the following points in conjunction with this figure.
• The flow chart uses RXUSRCLK as reference to the wait time for each state. Do not use
RXUSRCLK as the clock source for this block; this clock might not be present during
some states. Use a free-running clock (for example, the system's clock) and make sure
that the wait time for each state equals the specified number of RXUSRCLK cycles.
• It is assumed that the frequency of RXUSRCLK is slower than the frequency of
RXUSRCLK2. If RXUSRCLK2 is slower, use that clock as reference to the wait time for
each state.
• See Figure 8-22, “RXSYNC Timing,” page 228 regarding the 64 synchronization clock
cycles specified in this block.
• rx_usrclk_stable is a status signal from the user's application that is asserted High
when both RXUSRCLK and RXUSRCLK2 clocks are stable. For example, if a DCM is
used to generate both the RXUSRCLK and RXUSRCLK2 clocks, then the DCM
LOCKED signal can be used here.
• rx_error is a status signal from the user's application that is asserted High indicating
that there is a burst of errors on the received data (RXDISPERR and/or
RXNOTINTABLE are asserted). The errors observed in the received data also show if
an RX phase alignment has not been successful, so there is no need for a separate align
error signal from the user similar to the TX reset sequence.
• rx_sync_cnt is a counter from the user's application that is incremented every time
both rx_error and RXLOCK are asserted. It is reset when the block cycles back to the
RX_PMA_RESET state.
• See “RX Reset Sequence Background,” page 100 for information on the 16K REFCLK
cycles requirement.
• This RX reset sequence is for Analog CDR mode. The RX buffer bypass mode is not
supported with the digital receiver.
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RX_SYSTEM_RESET
system_reset==0
RX_PMA_RESET
RXPMARESET==1 for
3 RXUSRCLK cycles
RX_WAIT_LOCK
rx_usrclk_stable==1 && RXLOCK==1 for
16K (16 x 1024) REFCLK cycles
Resets
RXLOCK==0
RXLOCK==0
RXLOCK==0
RXLOCK==0
RXLOCK==0
RX_SYNC
RXSYNC==1 for
64 synchonization cycles
RX_PCS_RESET
RXRESET==1 for
3 RXUSRCLK cycles
RX_WAIT_PCS
5 RXUSRCLK cycles
RX_ALMOST_READY
rx_error==0 && RXLOCK==1
for 64 RXUSRCLK cycles
RX_READY
rx_sync_cnt==16 &&
rx_error==1 &&
RXLOCK==1
rx_sync_cnt < 16 && r x_error ==1 && RXLOCK==1
rx_error==1 && RXLOCK==1
ug076_ch2_23_060606
Figure 2-22: Flow Chart of Receiver Reset Sequence Where RX Buffer Is Bypassed
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Below are the steps describing the flow chart in Figure 2-22:
1. RX_SYSTEM_RESET: Upon RX system reset on this block, go to the RX_PMA_RESET
state.
RXPMARESET == 0
RXRESET == 0
RXSYNC == 0
2. RX_PMA_RESET: Assert RXPMARESET for three RXUSRCLK cycles.
RXPMARESET == 1
RXRESET == X
RXSYNC == 0
3. RX_WAIT_LOCK: Stall until RXLOCK is High and until the clocks on RXUSRCLK
and RXUSRCLK2 are stable (rx_usrclk_stable == 1), then wait for 16K (16 x 1024)
REFCLK cycles. The amount of wait from the REFCLK cycles covers the 12,000
RXUSRCLK2 cycles required by the RXSYNC timing waveform (see Figure 8-22,
“RXSYNC Timing,” page 228). Also, see “RX Reset Sequence Background,” page 100
for information on the 16K REFCLK cycles requirement.
RXPMARESET == 0
RXRESET == X
RXSYNC == 0
4. RX_SYNC: Assert RXSYNC for 64 synchronization cycles. If RXLOCK is deasserted,
go back to RX_WAIT_LOCK state.
RXPMARESET == 0
RXRESET == X
RXSYNC == 1
5. RX_PCS_RESET: Assert RXRESET for three RXUSRCLK cycles. If RXLOCK is
deasserted, go back to RX_WAIT_LOCK state.
RXPMARESET == 0
RXRESET == 1
RXSYNC == 0
6. RX_WAIT_PCS: Wait for five RXUSRCLK cycles after deassertion of RXRESET. If
RXLOCK is deasserted, go back to RX_WAIT_LOCK state.
RXPMARESET == 0
RXRESET == 0
RXSYNC == 0
7. RX_ALMOST_READY: Wait for 64 RXUSRCLK cycles with no error on the received
data and RXLOCK High for this amount of time; this is to ensure that the RX MGT is
stable after start-up and ready for data reception. If RXLOCK is deasserted, go back to
RX_WAIT_LOCK state. If an rx_error is detected while RXLOCK is High, the reset
sequence block should apply RXRESET by cycling back to the RX_PCS_RESET state. If
this step occurs 16 times as monitored by the rx_pcs_reset_cnt counter, apply a
RXPMARESET by cycling back to the RX_PMA_RESET state.
RXPMARESET == 0
RXRESET == 0
RXSYNC == 0
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8. RX_READY: Once rx_error is monitored Low for some time, the RX link is READY for
data reception.
RXPMARESET == 0
RXRESET == 0
RXSYNC == 0
Figure 2-23 shows a timing diagram for resetting the RX transceiver when the RX buffer is
used. Refer to Figure 2-22 for more details.
RXUSRCLK
RXPMARESET
RXLOCK
RXSYNC
RXRESET
Once RX error is monitored Low for some time, RX Link is READY
Figure 2-23: Resetting the Receiver in Analog CDR Mode Where
RX Buffer Is Bypassed
Reset Considerations
Below is a summary of items that need to be considered for resetting the transceiver:
• The configuration bits in the GT11 attributes accessed through the DRP are not
affected by any of the reset signals.
• All the blocks that implement the different reset sequences for the GT11 should use a
free-running clock from the user's design. Do not use any generated output clock from
the GT11 as the clock source for these blocks.
♦ TXOUTCLK1 and TXOUTCLK2 output clocks remain a constant 0 when
TXPMARESET is applied to the TX PLL.
♦ RXRECCLK1 and RXRECCLK2 output clocks are of the wrong frequency when
RXPMARESET is applied to the RX PLL.
• TXPMARESET of MGTA resets the shared transmitter VCO:
♦ If the design uses MGTA only, apply a TXPMARESET on MGTA
♦ If the design uses MGTB only, apply a TXPMARESET on both MGTA and MGTB.
• Both TXUSRCLK and TXUSRCLK2 must be stable before applying TXRESET.
• Both RXUSRCLK and RXUSRCLK2 must be stable before applying RXRESET.
• For 8-byte external data interface widths, TXRESET should be deasserted
synchronously with the falling edge of TXUSRCLK2 to ensure proper transmit data
ordering. See Figure 2-24.
ug076_ch2_25_040406
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TXUSRCLK
TXUSRCLK2
TXRESET
TXDATA
(based on TXUSRCLK2)
Internal txdata
(based on TXUSRCLK)
B A D C F E
ABCDEF
Figure 2-24: TXRESET for 8-Byte External Data Interface Width
• For Digital CDR, asserting RXRESET causes the PMA parallel clock RXRECCLK1 to
remain at a constant value.
• When channel bonding is used in conjunction with 1-byte and 2-byte external data
interface widths, RXRESET must be deasserted synchronously on all channel-bonded
MGTs with respect to RXUSRCLK2.
RX Reset Sequence Background
When the MGT is used in Analog CDR Mode, its RXLOCK port is asserted after the RX
PLL locks to the reference clock. The RXLOCK signal remains High for as few as 128
REFCLK cycles with the loosest receive calibration settings (see “Calibration for the PLLs,”
page 149). At this point, the receiver tries to lock onto incoming data. If no data is present
at the receiver or if the PLL is not able to lock to data, the RXLOCK signal transitions back
to Low in as few as 128 REFCLK cycles or as many as 16,384 REFCLK cycles, depending on
the receive calibration settings. The process repeats until lock-to-data is acquired. It is
recommended to wait 16K (16 x 1024) REFCLK periods for the reset sequence to ensure
that the PLL is locked to data.
ug076_ch2_26_040406
Because the RX PLL is locked to the reference clock in Digital CDR mode, there is no need
to assert RXLOCK High for a specific number of REFCLK cycles.
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