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09/10/041.1Chapters 11, 12, and 13 in the printed handbook are now Chapters 1, 2, and 3 in this
guide. Chapter 14 in the printed handbook is now Chapter 6 in this guide. There are now
eight chapters in this guide.
08/08/051.2System Monitor functions are not supported in Virtex-4 devices, removed references.
General typographical edits for correctness and clarity. Edited Table 1-1, Table 1-4,
Figure 1-11, Table 2-4, and Figure 2-11 to add information on Slave SelectMAP32 mode.
Removed the Virtex-4 bitstream length tables in favor of the exact numbers reported in
the ISE BitGen tool. Edited Table 1-3 and removed the Power-Up Timing table to
consolidate data in the Virtex-4 FPGA Data Sheet. Edited Figure 1-11. Removed the
Dynamic Reconfiguration Timing table to consolidate data in the Virtex-4 FPGA
Data Sheet.
08/16/051.3Due to a documentation error, all configuration I/O notations have been changed from
LVTTL to LVCMOS.
Virtex-4 FPGA Configuration User Guidewww.xilinx.comUG071 (v1.12) June 2, 2017
VersionRevision
01/19/061.4Completed grammatical and style edits for clarity and compliance to Xilinx
documentation standards.
Added preface, not included in previous versions. Corrected Table 1-1, page 13 (Note 2.).
Added “HSWPEN has a weak pull-up prior to and during configuration” to Table 1-2,
page 14. Clarified first paragraph of “Clear Configuration Memory (Step 2,
Initialization),” page 16. Clarified title of Table 1-10, page 22 (status register), to
differentiate from Figure 1-10 (signal sequencing). Added descriptions for GWE, GTS,
EOS, DCI_MATCH, and DCM_LOCK to Table 1-10, page 22. Added “ICAP is not
supported with an encrypted bitstream in the LX, SX, and FX12 devices” as last
paragraph in “Loading the Encryption Key,” page 24 and as last line in first paragraph
in “Bitstream Encryption and Internal Configuration Access Port (ICAP),” page 25.
Added third paragraph to “Loading Encrypted Bitstreams,” page 24. Clarified
SelectMAP Data Pin Description in Table 2-4, page 39. Added port width to “SelectMAP
Reconfiguration,” page 51. Added first paragraph to Chapter 4, “Frame ECC Logic,”
page 75. Updated the BitGen option to DONE_CYCLE:KEEP in Chapter 5, “User Access
Register,” page 77. Added “Frame Address Register (FAR),” page 92. Corrected
Configuration Data in Table 8-2, page 103 (step 4 and step 6). Changed DESYCH to
DESYNC (throughout).
01/12/071.5Updated notes relevant to Figure 2-5. Updated Table 2-4, Table 3-3, and the “Instruction
Updated the “Control Register (CTL)” section, Table 7-7, and Figure 8-2.
06/21/071.6Updated “Introduction,”Table 1-2, “Master Serial Configuration,”“SelectMAP Data
Loading,”Chapter 5, “User Access Register,”“Changing the Multiply and Divide
Values,”“Dynamic Phase Shifting Through the DRP in Direct Mode,”Table 7-1, CBC
address value in Table 7-5, “Configuration Memory Read Procedure (SelectMAP),” and
Table 8-2. Added
“Packet Types”section.
07/30/071.7Added TAP controller state definitions in the “TAP Controller” section and a NOOP note
to Table 8-1.
08/08/071.8Replaced instructions for setting a direct phase shift value in the “Dynamic Phase
Shifting Through the DRP in Direct Mode” section.
10/01/071.9Title: Updated corporate disclaimer.
Chapter 2: Updated notes relevant to Figure 2-3 and updated Figure 2-19.
Chapter 3: Updated “TAP Controller” section.
Chapter 8: Updated Table 8-5.
04/08/081.10Chapter 1: Updated Table 1-6 and “Loading Encrypted Bitstreams” section.
Chapter 3: Updated “Identification Register” section, including Table 3-4 and Table 3-5.
06/09/091.11Chapter 1:
• Interchanged phase events 5 and 6 in Table 1-9.
Chapter 2:
• Added cross reference to the Virtex-4 FPGA Data Sheet.
• Changed default oscillator frequency to 4 MHz in Note 3 following Figure 2-4.
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About This Guide
This document describes the Virtex®-4 Configuration. Complete and up-to-date
documentation of the Virtex-4 family of FPGAs is available on the Xilinx web site at
http://www.xilinx.com/products/virtex4/index.htm
Guide Contents
•Chapter 1, “Configuration Overview”
•Chapter 2, “Configuration Interfaces”
•Chapter 3, “Boundary-Scan and JTAG Configuration”
•Chapter 4, “Frame ECC Logic”
•Chapter 5, “User Access Register”
•Chapter 6, “Reconfiguration Techniques”
•Chapter 7, “Configuration Details”
•Chapter 8, “Readback and Configuration Verification”
Preface
.
Additional Documentation
The following documents are also available for download at
http://www.xilinx.com/products/virtex4/index.htm
•Virtex-4 Family Overview
The features and product selection of the Virtex-4 family are outlined in this overview.
•Virtex-4
This data sheet contains the DC and Switching Characteristic specifications for the
Virtex-4 family.
•Virtex-4
Chapters in this guide cover the following topics:
-Clocking Resources
-Digital Clock Manager (DCM)
-Phase-Matched Clock Dividers (PMCD)
-Block RAM and FIFO memory
-Configurable Logic Blocks (CLBs)
-SelectIO™ Resources
FPGA Data Sheet: DC and Switching Characteristics
FPGA User Guide
.
Virtex-4 FPGA Configuration User Guidewww.xilinx.com9
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Preface:About This Guide
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•XtremeDSP™ Design Considerations
-SelectIO Logic Resources
-Advanced SelectIO Logic Resources
This guide describes the XtremeDSP slice and includes reference designs for using
DSP48 math functions and various FIR filters.
•Virtex-4
This designer’s guide provides information on the design of PCBs for Virtex-4 devices.
It considers all aspects of the PCB from the system level down to the minute details.
This guide focuses on strategies for making design decisions at the PCB and interface
level.
•Virtex-4
This specification includes the tables for device/package combinations and maximum
I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and
thermal specifications.
•Virtex-4 RocketIO
This guide describes the RocketIO Multi-Gigabit Transceivers available in the
Virtex-4-FX family.
•Virtex-4
This guide describes the Tri-Mode Ethernet Media Access Controller available in the
Virtex-4 FX family.
•PowerPC®
This guide is updated to include the PowerPC 405 processor block available in the
Virtex-4 FX family.
Additional Resources
FPGA PCB Designers Guide
FPGA Packaging and Pinout Specification
™ Multi-Gigabit Transceiver User Guide
FPGA Embedded Tri-Mode Ethernet MAC User Guide
405 Processor Block Reference Guide
To search the database of silicon and software questions and answers, or to create a
technical support case in WebCase, see the Xilinx website at:
http://www.xilinx.com/support
Typographical Conventions
This document uses the following typographical conventions. An example illustrates each
convention.
ConventionMeaning or UseExample
Italic font
.
References to other documents
Emphasis in text
See the Virtex-4 Configuration Guide for more information.
The address (F) is asserted after
clock event 2.
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Online Document
The following conventions are used in this document:
ConventionMeaning or UseExample
Typographical Conventions
Blue text
Red text
Blue, underlined text
Cross-reference link to a
location in the current
document
Cross-reference link to a
location in another document
Hyperlink to a website (URL)
See the section “Additional
Resources” for details.
Refer to “Title Formats” in
Chapter 1 for details.
See the Virtex-4 User Guide.
Go to http://www.xilinx.com
for the latest speed files.
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Configuration Overview
Introduction
Virtex®-4 devices are configured by loading application-specific configuration data—the
bitstream—into internal memory. Because Xilinx® FPGA configuration memory is
volatile, it must be configured each time it is powered-up. The bitstream is loaded into the
device through special configuration pins. These configuration pins serve as the interface
for a number of different configuration modes:
•Master-serial configuration mode
•Slave-serial configuration mode
•Master SelectMAP (parallel) configuration mode
•Slave SelectMAP (parallel) configuration mode
In addition, the bitstream can be loaded through the JTAG interface:
Chapter 1
•JTAG/Boundary-Scan configuration mode
The configuration modes are explained in detail in Chapter 2 The configuration mode is
selected by setting the appropriate level on the dedicated MODE input pins. Table 1-1 lists
the Virtex-4 configuration modes.
Table 1-1:Virtex-4 Configuration Modes
Configuration ModeM2 M1M0Data WidthCCLK Direction
Master Serial 0001 bitOutput
Slave Serial1111 bitInput
Master SelectMAP011 8 bitsOutput
Slave SelectMAP8110 8 bitsInput
Slave SelectMAP32
JTAG/Boundary-Scan only
Notes:
1. JTAG configuration uses the JTAG TCK pin instead of the configuration clock (CCLK).
2. I/O pre-configuration pull-up resistors are disabled with the HSWAPEN pin.
3. In SelectMAP32 D0:D31 data bits are not swapped. D0 is the LSB. D31 is the MSB.
4. If the pins are left unconnected a weak pull-up resistor on the mode pins makes slave serial the default
mode.
(3)
(1)
001 32 bitsInput
1011 bit–
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Chapter 1:Configuration Overview
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The terms Master and Slave refer to the direction of the configuration clock (CCLK):
•In Master configuration modes, the Virtex-4 device drives the configuration clock
(CCLK) from an internal oscillator
•In Slave configuration modes, the configuration clock is an input.
The JTAG/Boundary-Scan configuration interface is always available, regardless of the
MODE pin settings. The JTAG/Boundary-Scan configuration mode disables all other
configuration modes. This prevents conflicts between configuration interfaces.
The JTAG interface is available after the mode pins are sampled. Activating PROGRAM_B
disables JTAG until INIT is completed.
Certain pins are dedicated to configuration, while others are dual-purpose (Table 1-2).
Dual-purpose pins serve both as configuration pins and as user I/O after configuration.
Dedicated configuration pins retain their function after configuration.
Table 1-2:Virtex-4 Configuration Pins
Pin NameType
M[2:0]InputDedicatedMode pins that determine configuration mode. Sampled on the rising
CCLKInput or
D_INInputDedicatedSerial data input for serial configuration modes.
DOUT_BUSYOutputDedicatedIn Serial configuration mode, pin acts as serial data output for daisy-chain
BidirectionalDual-PurposeParallel data inputs for SelectMAP modes.
(1)
Output
or Active
Output,
Dedicated or
Dual-Purpose
DedicatedConfiguration clock source for all configuration modes except JTAG.
DedicatedActive High signal indicating configuration is complete.
DedicatedBefore MODE pins are sampled, INIT_B is an input that can be held Low
(2)
edge of INIT_B.
configuration. In SelectMAP mode, pin acts as BUSY output.
0 = FPGA not configured
1 = FPGA configured
Refer to the “BitGen” section of the Development System Reference Guide for
software settings.
to delay configuration.
After MODE pins are sampled, INIT_B is an open-drain active Low
output indicating whether a CRC error occurred during configuration:
0 = CRC error
1 = No CRC error
For 8-bit SelectMAP:
D0 = MSB
D7 = LSB
For 32-bit SelectMAP:
D0 = LSB
D31 = MSB
Description
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Setup (Steps 1-3)
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Power-Up
Sample Mode
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Synchronization
Device ID
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Table 1-2:Virtex-4 Configuration Pins (Continued)
Pin NameType
(1)
HSWAPENInputDedicatedActive High input used to disable weak pre-configuration I/O pull-up
Notes:
1. The Bidirectional type describes a pin that is bidirectional under all conditions. If the pin is an input for some configuration modes or an
output for others, it is listed as an Input or Output type.
2. Dual-purpose pins can become user I/O after configuration. See “
HSWAPEN must be connected to either enable or disable the pull-up
resistors.
HSWAPEN has a weak pull-up prior to and during configuration. The
weak pull-up does not always provide a reliable 1.
PERSIST” in Chapter 7 for details.
Setup (Steps 1-3)
While each of the configuration interfaces is different, the basic steps for configuring a
Virtex-4 device are the same for all modes. Figure 1-1 shows the Virtex-4 configuration
process. Each step is described in detail in the following sections.
Steps
Start
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Device
Power-Up
Clear
Configuration
Memory
Sample Mode
Pins
Synchronization
Figure 1-1:Virtex-4 Configuration Process
Device Power-Up (Step 1)
Figure 1-2: Device Power-Up (Step 1)
For configuration, Virtex-4 devices require power on the V
V
All JTAG and serial configuration pins are located in a separate, dedicated bank with a
dedicated V
purpose pins, and are located in Bank 2 (V
V
voltage level with the output standard set to LVCMOS_12F. In SelectMAP mode, V
must be connected to the appropriate voltage to match the I/O standard of the
configuration device.
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pins. There are no power-supply sequencing requirements.
CCINT
CC_CONFIG
(V
) supply. The SelectMAP data pins are shared dual-
CCO_0
CCO_2
CC_CONFIG
LVCMOS level. All active dedicated output pins operate at the V
Device ID
Check
Configuration
Bitstream
Loading
Load
Data
CC_CONFIG
CRC Check
, V
CCAUX
Startup
Sequence
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, and
). All dedicated input pins operate at
CC_CONFIG
Finish
CCO_2
Chapter 1:Configuration Overview
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For power-up, the V
I/O voltage supplies (V
power pins must be supplied with a 1.2V source. None of the
CCINT
), except V
CCO
CCO_0 (VCC_CONFIG
), need to be powered for
Virtex-4 configuration in JTAG or serial modes. Table 1-3 shows the power supplies
required for configuration; for recommended operating conditions, see Table 2 of the
Virtex-4 FPGA Data Sheet. Table 41 of the Virtex-4 FPGA Data Sheet shows the configuration
power-up timing parameters. Table 7-1 shows the number of frames per Virtex-4 device.
Table 1-3:Power Supplies Required for Configuration
Pin NameDescription
V
CCINT
(1)
V
BATT
V
CC_CONFIG
V
CCAUX
Notes:
1. V
is required only when using bitstream encryption.
BATT
PROGRAM_B
CCLK Output or Input
Internal core voltage relative to GND.
Encryption Key battery supply.
Configuration output supply voltage (also known as V
CCO_0
)
Auxiliary power input for configuration logic and other FPGA functions.
V
CC
INIT_B
T
POR
T
PL
T
T
ICCK
M0, M1, M2*
(Required)
*Can be either 0 or 1, but must not toggle during and after configuration.
Figure 1-3: Device Power-Up Timing
V
should rise monotonically within the specified ramp rate. If this is not possible,
CCINT
delay configuration by holding the INIT_B pin or the PROGRAM_B pin Low (see
“Delaying Configuration”) while the system power reaches V
The configuration logic power input (V
(V
) are used as a logic input to the Power-On-Reset (POR) circuitry. If either of these
CCAUX
CC_CONFIG
) and the auxiliary voltage input
voltage planes dips below the specified level, POR can trigger.
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Setup (Steps 1-3)
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Power-Up
Sample Mode
Pins
Synchronization
Device ID
Check
CRC Check
Clear
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Memory
Startup
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Load
Configuration
Data
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Configuration memory is cleared sequentially any time the device is powered up, when
the PROGRAM_B pin is pulsed Low, or when the JTAG JPROGRAM instruction is used.
During this time, I/Os are placed in a high-Z state except for the dedicated Configuration
and JTAG pins. INIT_B is held Low by the device during initialization, then released after
T
(Figure 1-3.) If the INIT_B pin is held Low externally, the device waits at this point in
POR
the initialization process until the pin is released.
The minimum Low pulse time for PROGRAM_B is defined by the T
parameter. The PROGRAM_B pin can be held active (Low) for as long as necessary, and the
device remains held in the reset state.
Sample Mode Pins (Step 3)
When the INIT_B pin transitions to High, the device samples the MODE pins and begins
driving CCLK if in Master Serial or Master SelectMAP mode. At this point, the device
begins sampling the configuration data input pins (D
pins for SelectMAP modes on rising configuration clock signals).
Delaying Configuration
There are two ways to delay configuration for Virtex-4 devices:
Figure 1-5: Sample Mode Pins (Step 3)
pin for Serial Modes or the D0–D7
IN
PROGRAM
timing
•The first is to hold the INIT_B pin Low during initialization (Figure 1-3). This method
only works if INIT_B is prevented from going High. After INIT_B goes High,
configuration cannot be delayed by subsequently pulling INIT_B Low.
•The second is to hold the PROG pin Low, continuously clearing configuration
memory (“Clear Configuration Memory (Step 2, Initialization),” page 16). The signals
relating to initialization and delaying configuration (Table 1-4).
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Device
Power-Up
Sample Mode
Pins
Synchronization
Device ID
Check
CRC Check
Clear
Configuration
Memory
Startup
Sequence
Load
Configuration
Data
Start
Finish
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Table 1-4:Signals Relating to Initialization and Delaying Configuration
Signal NameType
(1)
Access
(2)
Description
PROGRAM_BInputExternally accessible via
the PROGRAM_B pin.
Global asynchronous chip reset.
Can be held Low to delay
configuration.
INIT_BInput or
Output
Externally accessible via
the INIT_B pin.
Before the MODE pins are
sampled, INIT_B is an input that
can be held Low to delay
configuration.
After the MODE pins are sampled,
INIT_B is an open-drain active
Low output indicating whether a
CRC error occurred during
configuration:
0 = CRC error
1 = No CRC error
INIT_COMPLETEStatusInternal signal,
accessible through the
Indicates whether INIT_B signal
has been internally released.
Virtex-4 status register.
MODE_STATUS[2:0]StatusInternal signals,
accessible through the
Virtex-4 status register.
Reflects the values sampled on the
MODE pins when INIT_B is
asserted High.
Notes:
1.
The Status type symbolizes an internal status signal without a corresponding pin.
2. Information on the Virtex-4 status register is available in Table 7-9. Information on accessing the
JTAG capture sequence is available in Table 8-4.
Bitstream Loading (Steps 4-7)
The bitstream loading process is similar for all configuration modes; the primary
difference between modes is the interface to the configuration logic. Details on the different
configuration interfaces are provided in Chapter 2.
The most important steps in the bitstream loading process are, synchronization, device ID
check, loading configuration data, and the CRC check. Each of these steps involves distinct
parts of the configuration bitstream. The steps prior to synchronization and after the CRC
check do not directly involve the configuration bitstream.
Synchronization (Step 4)
Figure 1-6: Synchronization (Step 4)
Before the configuration data frames can be loaded, a special 32-bit synchronization word
(0xAA995566) must be sent to the configuration logic. The synchronization word alerts
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Bitstream Loading (Steps 4-7)
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Power-Up
Sample Mode
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Device ID
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CRC Check
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Startup
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Data
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the device to upcoming configuration data and aligns the configuration data with the
internal configuration logic. Any data on the configuration input pins prior to
synchronization is ignored.
Synchronization is transparent to most users because all configuration bitstreams (.bit
files) generated by the Xilinx ISE® Bitstream Generator (BitGen) software include the
synchronization word. Table 1-5 shows signals relating to synchronization.
Table 1-5:Signals Relating to Synchronization
Signal NameTypeAccessDescription
DALIGNStatusOnly available through the
Check Device ID (Step 5)
Once the device is synchronized, a device ID check must pass before the configuration data
frames can be loaded. This prevents an attempted configuration with a bitstream that is
formatted for a different device.
For example, the device ID check should prevent an XC4VLX15 from being configured
with an XC4VLX80 bitstream.
SelectMAP interface during an
ABORT. (See “Configuration
Abort Sequence Description,”
page 49.)
Figure 1-7:Check Device ID (Step 5)
Indicates whether device
is synchronized.
The device ID check is built into the bitstream, making this step transparent to most
designers. Figure 1-7 shows the relative position of the device ID check, Table 1-6 shows
the Virtex-4 device IDs, and Table 1-7 shows the sig nals re latin g to the devic e ID che ck. The
device ID check is performed through commands in the bitstream to the configuration
logic, not through the JTAG IDCODE register in this case.
Table 1-6:Virtex-4 Device ID Codes
DeviceIDCODEDeviceIDCODEDeviceIDCODE
XC4VLX1501658093XC4VFX1201E58093
XC4VLX250167C093XC4VSX2502068093XC4VFX2001E64093
XC4VLX40016A4093XC4VSX3502088093XC4VFX4001E8C093
XC4VLX60016B4093XC4VSX55020B0093XC4VFX6001EB4093
XC4VLX80016D8093
XC4VLX10001700093XC4VFX10001EE4093
XC4VLX16001718093XC4VFX14001F14093
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Power-Up
Sample Mode
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Synchronization
Device ID
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CRC Check
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Configuration
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Startup
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Configuration
Data
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Finish
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Device
Power-Up
Sample Mode
Pins
Synchronization
Device ID
Check
CRC Check
Clear
Configuration
Memory
Startup
Sequence
Load
Configuration
Data
Start
Finish
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Table 1-6:Virtex-4 Device ID Codes (Continued)
DeviceIDCODEDeviceIDCODEDeviceIDCODE
XC4VLX20001734093
Notes:
1. Does not reflect the actual device array size.
Table 1-7:Signals Relating to the Device ID Check
Signal NameTypeAccess
ID_ErrStatusInternal signal. Accessed
Notes:
1. Information on the Virtex-4 status register is available in Table 7-9. Information on accessing the JTAG
capture sequence is available in Table 8-4.
Load Configuration Data Frames (Step 6)
(1)
only through the Virtex-4
status register.
Description
Indicates a mismatch between the
device ID specified in the bitstream
and the actual device ID.
Figure 1-8:Load Configuration Data Frames (Step 6)
After the synchronization word is loaded and the device ID has been checked, the
configuration data frames are loaded. This process is transparent to most users. For details,
refer to Chapter 7
Cyclic Redundancy Check (Step 7)
Figure 1-9: Cyclic Redundancy Check (Step 7)
As the configuration data frames are loaded, the device calculates a Cyclic Redundancy
Check (CRC) value from the configuration data packets. After the configuration data
frames are loaded, the configuration bitstream can issue a Check CRC instruction to the
device, followed by an expected CRC value. If the CRC value calculated by the device does
not match the expected CRC value in the bitstream, the device pulls INIT_B Low and
aborts configuration. The CRC check is included in the configuration bitstream by default,
although the designer can disable it if desired. (Refer to the Development System Reference
Guide, BitGen section.) If the CRC check is disabled, there is a risk of loading incorrect
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configuration data frames, causing incorrect design behavior, or even damaging the
device.
If a CRC error occurs during configuration, the device must be resynchronized and
reconfigured. In serial modes, the device can only be resynchronized by pulsing the
PROGRAM_B pin and restarting the configuration process from the beginning. In
SelectMAP modes, either the PROGRAM_B pin can be pulsed Low or an ABORT sequence
can be initiated (see “SelectMAP Configuration Interface” in Chapter 2).
Virtex-4 devices use a 32-bit CRC check. The CRC check is designed to catch errors in
transmitting the configuration bitstream. There is a scenario where errors in transmitting
the configuration bitstream can be missed by the CRC check:
Certain clocking errors, such as double-clocking, can cause loss of synchronization
between the 32-bit bitstream packets and the configuration logic. Once
synchronization is lost, any subsequent commands are not understood, including the
command to check the CRC. In this situation, configuration fails with DONE Low and
INIT_B High.
Virtex-4 configuration uses a standard CRC32C checksum algorithm. The CRC32C
polynomial is:
Startup (Step 8)
After the configuration frames are loaded, the bitstream instructs the device to enter the
startup sequence. The startup sequence is controlled by an 8-phase (phases 0–7) sequential
state machine. The startup sequencer performs the tasks outlined in Table 1-8.
Table 1-8:User-Selectable Cycle of Startup Events
Figure 1-10: Start-Up Sequence (Step 8)
PhaseEvent
1–6Wait for DCMs to Lock (optional)
1–6Wait for DCI to Match (optional)
1
–6Assert GWE (Global Write Enable), allowing RAMs and flip-flops to change state
1–6Negate GTS (Global 3-State), activating I/O
1–6Release DONE pin
7Assert EOS (End Of Startup)
The specific order of startup events (except for EOS assertion) is user-programmable
through BitGen options (refer to the Development System Reference Guide). Table 1-8 shows
the general sequence of events, although the specific phase for each of these startup events
is user-programmable (EOS is always asserted in the last phase). Refer to Chapter 2,
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“Configuration Interfaces” for important startup option guidelines. By default, startup
events occur as shown in Table 1-9.
Table 1-9:Default Sequence of Startup Events
PhaseEvent
4Release DONE pin
5Negate GTS, activating I/O
6Assert GWE, allowing RAMs and FFs to change state
7Assert EOS
The start-up sequence can be forced to wait for the DCMs to lock or for DCI to match with
the appropriate BitGen options. These options are typically set to prevent DONE, GTS, and
GWE from being asserted (preventing device operation) before the DCMs have locked
and/or DCI has matched.
The DONE signal is released by the start-up sequencer on the cycle indicated by the user,
but the start-up sequencer does not proceed until the DONE pin actually sees a logic High.
The DONE pin is an open-drain bidirectional signal by default. By releasing the DONE
pin, the device simply stops driving a logic Low and the pin goes into a high-Z state. An
external pull-up resistor is needed for the DONE pin to reach a logic High in this case.
Table 1-10 shows signals relating to the status register. Figure 1-11 shows the signals
relating to the start-up sequencer.
Table 1-10:Signals Relating to Status Register
Signal NameType
DONEBidirectional
Release_DONE
GWEGlobal Write Enable. When de asserted GWE
GTSGlobal Tri-State. When asserted, GTS
EOSEnd of Startup. EOS indicates the absolute
DCI_MATCHDCI_MATCH indicates when all the
DCM_LOCKDCM_LOCK indicates when all the Digital
Status
Access
(2)
DONE pin or
Virtex-4 Status
Register
Virtex-4
Status
Register
(1)
Indicates configuration is complete. Can be
held Low externally to synchronize startup
with other FPGAs.
Indicates whether device has released
DONE pin. If pin is held Low externally,
Release_DONE can differ from actual value
on DONE pin.
disables CLB and IOB flips-flops as well as
other synchronous elements on the FPGA.
disables all the I/O drivers except for
configuration pins.
end of the configuration and startup process.
Digitally Controlled Impedance (DCI)
controllers have matched their internal
resistor to the external reference resistor.
Clock Managers (DCMs) have locked. This
signal is asserted by default. It is active if the
LOCK_WAIT option is used on a DCM and
the LockCycle option is used when the
bitstream is generated.
Description
Notes:
1. Information on the Virtex-4 status register is available in Table 7-9. Information on accessing the JTAG
capture sequence is available in Table 8-4.
2. Open-drain output by default; optional driver enabled using BitGen drivedone option.
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POR
INIT_B
DONE
GWE
GTS
EOS
CCLK
Bitstream Encryption
InitializationConfigurationStartupEnd of Bitstream
Figure 1-11:Configuration Signal Sequencing (Default Startup Settings)
Bitstream Encryption
Virtex-4 devices have on-chip AES (Advanced Encryption Standard) decryption logic to
provide a high degree of design security. Without knowledge of the encryption key,
potential pirates cannot analyze an externally intercepted bitstream to understand or clone
the design. Encrypted Virtex-4 designs cannot be copied or reverse-engineered.
The Virtex-4 AES system consists of software-based bitstream encryption and on-chip
bitstream decryption with dedicated memory for storing the encryption key. Using the
Xilinx ISE software, the user generates the encryption key and the encrypted bitstream.
During configuration, the Virtex-4 device performs the reverse operation, decrypting the
incoming bitstream. The Virtex-4 AES encryption logic uses a 256-bit encryption key.
The on-chip AES decryption logic cannot be used for any purpose other than bitstream
decryption; i.e., the AES decryption logic is not available to the user design and cannot be
used to decrypt any data other than the configuration bitstream.
Virtex-4 devices store the encryption key internally in dedicated RAM, backed up by a
small externally connected battery. The encryption key can only be programmed onto the
device through the JTAG interface; once programmed, it is not possible to read the
encryption key out of the device through JTAG or any other means.
ICAP is not supported with an encrypted bitstream in the LX, SX, and FX12 devices.
ug071_11_080305
AES Overview
The Virtex-4 encryption system uses the Advanced Encryption Standard (AES) encryption
algorithm. AES is an official standard supported by the National Institute of Standards and
Technology (NIST) and the U.S. Department of Commerce
(http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf)
The Virtex-4 AES encryption system uses a 256-bit encryption key (the alternate key
lengths of 128- and 192- bits described by NIST are not implemented) to encrypt or decrypt
blocks of 128 bits of data at a time. According to NIST, there are 1.1 x 10
combinations for a 256-bit key.
Symmetric encryption algorithms such as AES use the same key for encryption and
decryption. The security of the data is therefore dependent on the secrecy of the key.
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.
77
possible key
Chapter 1:Configuration Overview
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Creating an Encrypted Bitstream
The Xilinx Bitstream Generator (BitGen, provided with the Xilinx ISE software) can
generate encrypted as well as non-encrypted bitstreams. For AES bitstream encryption, the
user specifies a 256-bit key as an input to BitGen. BitGen in turn generates an encrypted
bitstream file (.bit) and an encryption key file (.nky).
For specific BitGen commands and syntax, refer to the Development System Reference Guide.
Loading the Encryption Key
The encryption key can only be programmed onto a Virtex-4 device through the JTAG
interface. The iMPACT tool, provided with the Xilinx ISE software, can accept the .nky file
as an input and program the device with the key through JTAG, using a supported Xilinx
programming cable.
To program the key, the device enters a special key-access mode using the ISC_PROGRAM
instruction, as detailed in the JTAG 1532 specification. In this mode, all FPGA memory,
including the encryption key and configuration memory, is cleared. Once the key is
programmed and the key-access mode is exited, it cannot be read out of the device by any
means, and it cannot be reprogrammed without clearing the entire device. The key-access
mode is transparent to most users.
Loading Encrypted Bitstreams
Once the device has been programmed with the correct encryption key, the device can be
configured with an encrypted bitstream. After configuration with an encrypted bitstream,
it is not possible to read the configuration memory through JTAG or SelectMAP readback,
regardless of the BitGen security setting.
After loading the encryption key, a non-encrypted bitstream can be used to configure the
device; in this case the key is ignored. After configuring with a non-encrypted bitstream,
readback is possible (if allowed by the BitGen security setting). The encryption key still
cannot be read out of the device, preventing the use of Trojan Horse bitstreams to defeat the
Virtex-4 encryption scheme.
However, once an encrypted bitstream has been used to configure a device, the device
cannot be reconfigured with a non-encrypted bitstream unless a full-chip reset is
performed first by pulling the PROGRAM_B pin Low, cycling power, or issuing a
JPROGRAM instruction. Additional encrypted reconfigurations can be performed.
The method of configuration is not affected by encryption. The configuration bitstream can
be delivered in any mode (Serial, SelectMAP, or JTAG) from any configuration solution
(PROM, System ACE™ tool, etc.). Configuration timing and signaling are unaffected by
encryption.
The encrypted bitstream must configure the entire device, because partial reconfiguration
through the external configuration interfaces is not permitted for encrypted bitstreams.
After configuration, the device cannot be reconfigured without toggling the PROG pin,
cycling power, or issuing the JTAG JSTART or JPROG instruction. Readback is available
through the ICAP primitive (see “Bitstream Encryption and Internal Configuration Access
Port (ICAP)”). None of these events resets the key if V
BATT
or V
is maintained.
CCAUX
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A mismatch between the key in the encrypted bitstream and the key stored in the device
causes configuration to fail with the INIT pin remaining High and the DONE pin
remaining Low. A mismatch between the key and bitstream can result in a high current on
V
CCINT
.
Note:
1.Do not use or monitor BUSY when loading an encrypted bitstream.
2.SelectMAP-32 mode is not supported with encrypted bitstreams.
Bitstream Encryption and Internal Configuration Access Port (ICAP)
The Internal Configuration Access Port (ICAP) primitive provides the user logic with
access to the Virtex-4 configuration interface. The ICAP interface is similar to the
SelectMAP interface, although the restrictions on readback and reconfiguration for the
SelectMAP interface do not apply to the ICAP interface after configuration. Users can
perform readback and reconfiguration through the ICAP interface even if bitstream
encryption is used. Unless the designer wires the ICAP interface to user I/O, this does not
offer attackers a method for defeating the Virtex-4 AES encryption scheme. ICAP is not
supported with an encrypted bitstream in the LX, SX, and FX12 devices.
Users concerned about the security of their design should not:
V
BATT
•Wire the ICAP interface to user I/O
-or-
•Not instantiate the ICAP primitive.
Like the other configuration interfaces, the ICAP interface does not provide access to the
key register.
The encryption key memory cells are volatile and must receive continuous power to retain
their contents. During normal operation, these memory cells are powered by the auxiliary
voltage input (V
the key after V
CCAUX
), although a separate V
CCAUX
is removed. Because V
power input is provided for retaining
BATT
draws very little current (on the order of
BATT
nano amperes), a small watch battery is suitable for this supply. (To estimate the battery
life, refer to V
DC Characteristics in the Virtex-4 FPGA Data Sheet and the battery
BATT
specifications.) At less than a 100 nA load, the endurance of the battery should be limited
only by its shelf life.
V
does not draw any current and can be removed while V
BATT
cannot be used for any purpose other than retaining the encryption keys when V
CCAUX
is applied. V
CCAUX
BATT
is
removed.
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Configuration Interfaces
Virtex®-4 devices have three configuration interfaces. Each configuration interface
corresponds to one or more configuration modes, shown in Table 2-1. For detailed
interface timing information, see the Virtex-4 FPGA Data Sheet.
Table 2-1:Configuration Interfaces and Corresponding Configuration Modes
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Clocking Serial Configuration Data
PROGRAM_B
INIT_B
CCLK
DONE
Master DIN
Master CLK Begins Here
(2)
Databits clocked on rising edge of CCLK
ug071_016_073007
BIT 0
(1)
BIT 1BIT n BIT n+1
BIT n-63BIT n-64
Master DOUT /
Slave DIN
Xilinx
Serial PROM
Virtex-4
Master
Serial
DATADOUT
INIT_B
DIN
CCLK
PROGRAM_B
DONE
M2
M0 M1
CLK
CE
RESET/OE
PROGRAM_B
UG071_12_073007
(2)(1)
(7)
(7)
Figure 2-2 shows how configuration data are clocked into Virtex-4 devices in Slave serial
and Master serial modes.
Figure 2-2: Serial Daisy Chain Configuration Clocking Sequence
Notes relevant to Figure 2-2:
Serial Configuration Interface
1.In Figure 2-2, bit 0 represents the MSB of the first byte. For example, if the first byte is
0xAA (1010_1010), bit 0=1, bit 1=0, bit 2=1, etc.
2.For Master configuration mode, CCLK does not transition until after MODE pins are
sampled, as indicated by the arrow.
3.CCLK can be free-running in Slave serial mode.
Master Serial Configuration
The Master serial mode is designed so that the FPGA can be configured from a
Xilinx® serial configuration PROM, as shown in Figure 2-3.
Figure 2-3: Master Serial Mode Configuration
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Notes relevant to Figure 2-3:
1.The DONE pin is by default an open-drain output requiring an external pull-up
resistor. A 330Ω pull-up resistor is recommended. The DONE pin has a programmable
active driver. To enable it, enable the DriveDONE option in BitGen.
2.The INIT_B pin is a bidirectional, open-drain pin. An external pull-up resistor is
required.
3.The BitGen startup clock setting must be set for CCLK for serial configuration. The
oscillator frequency can be selected in BitGen (default is 4 MHz). Selectable
frequencies are 4, 5, 7, 8, 9, 10, 13, 15, 20, 26, 30, 34, 41, 45, 51, 55, and 60 MHz. Because
the oscillator can vary by ± 50%, select a maximum frequency not to exceed the F
of the configuration device.
4.The PROM in this diagram represents one or more Xilinx serial PROMs. Multiple serial
PROMs can be cascaded to increase the overall configuration storage capacity.
5.The .bit file must be reformatted into a PROM file before it can be stored on the serial
PROM. Refer to the “Generating PROM Files” section.
6.On XC17V00 PROMs, the reset polarity is programmable. RESET
active Low when using an XC17V00 device in this setup.
7.Connect pull-up resistors to V
8.The CCLK net requires Thevenin parallel termination. See “Board Layout for
Configuration Clock (CCLK),” page 34.
9.The CCLK pin is an output and an input.
CC_CONFIG
(identical to VCC Bank 0).
MAX
should be set for
Slave Serial Configuration
Slave serial configuration is typically used for devices in a serial daisy chain, or when
configuring a single device from an external microprocessor or CPLD. Design
considerations are similar to Master serial configuration except for the direction of CCLK.
A single device in Slave serial mode cannot simply be connected to a PROM, because
CCLK is an input on both devices.
Serial Daisy Chains
Multiple Virtex-4 devices can be configured from a single configuration source by
arranging the devices in a serial daisy chain. In a serial daisy chain, devices receive their
configuration data through their DIN pin, passing configuration data along to
downstream devices through their DOUT pin. The device closest to the configuration data
source is considered the most upstream device, while the device furthest from the
configuration data source is considered the most downstream device.
In a serial daisy chain, the configuration clock is typically provided by the most upstream
device in Master serial mode. All other devices are set for Slave serial mode. Figure 2-4
illustrates this configuration.
Alternatively, if a CPLD or microprocessor is used as a configuration controller, all devices
can be set for Slave serial mode. (See “Configuring a Serial Daisy Chain with a
Microprocessor or CPLD,” page 32.)
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Xilinx
Serial PROM
DATADOUT
CLK
CE
RESET/OE
PROGRAM
(7)
(7)
M0 M1
M2
DIN
CCLK
Virtex-4
Master
Serial
PROGRAM_B
DONE
INIT_B
M0 M1
M2
Virtex-4
Slave
Serial
DOUT
(1)
INIT_B
ug071_17_073007
DIN
CCLK
(2)
PROGRAM_B
DONE
Figure 2-4:Master/Slave Serial Mode Daisy Chain Configuration
Notes relevant to Figure 2-4:
1.The DONE pin is by default an open-drain output requiring an external pull-up
resistor. A 330Ω pull-up resistor is recommended. For all devices except the last, the
active driver on DONE must be disabled. For the last device in the chain, the active
driver on DONE can be enabled. See “Guidelines and Design Considerations for Serial
Daisy Chains.”
2.The INIT_B pin is a bidirectional, open-drain pin. An external pull-up resistor is
required.
3.The BitGen startup clock setting must be set for CCLK for serial configuration. The
oscillator frequency can be selected in BitGen (default is 4 MHz). Selectable
frequencies are 4, 5, 7, 8, 9, 10, 13, 15, 20, 26, 30, 34, 41, 45, 51, 55, and 60 MHz. Because
the oscillator can vary by ± 50%, select a maximum frequency not to exceed the F
MAX
of the configuration device.
4.The PROM in this diagram represents one or more Xilinx serial PROMs. Multiple serial
PROMs can be cascaded to increase the overall configuration storage capacity.
5.The .bit file must be reformatted into a PROM file before it can be stored on the serial
PROM. Separate bitstream files cannot be concatenated together to form a daisy-chain
bitstream. Refer to the “Generating PROM Files” section.
6.On XC17V00 PROMs, the reset polarity is programmable. RESET
should be set for
active Low when using an XC17V00 device in this setup.
7.The CCLK net requires Thevenin parallel termination. See “Board Layout for
Configuration Clock (CCLK),” page 34.
The first device in a serial daisy chain is the first to be configured. No data is passed onto
the DOUT pin until all the data frames, the start-up command, and CRC check have been
loaded. CRC checks only include the data for the current device, not for any others in the
chain. (See “Cyclic Redundancy Check (Step 7)” in Chapter 1.)
After the first device in the chain finishes configuration and passes its CRC check, it enters
the Start-Up sequence. At the Release DONE pin phase in the Start-Up sequence, the device
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places its DONE pin in a high-Z state while continuing to pass configuration data and
commands to downstream devices. After all devices release their DONE pins, the common
DONE signal is either pulled High externally or driven High by the last device in the chain.
On the next rising CCLK edge, all devices move out of the Release DONE pin phase and
complete their startup sequences.
It is important that all DONE pins in a Slave serial daisy chain be connected. Only the last
device in the serial daisy chain should have the DONE driver enabled. Enabling the DONE
driver on upstream devices causes contention on the DONE signal.
Configuring a Serial Daisy Chain with a Microprocessor or CPLD
If a microprocessor or CPLD is driving configuration instead of a Xilinx serial PROM, all
devices in the serial daisy chain can be set for Slave serial configuration mode, or the lead
FPGA can be set for Master serial, as shown in Figure 2-5.
Non-Xilinx
PROM (Parallel)
ADDRESS[18:0]
DATAOUT[7:0]
CE
OE
CPLD
ADDRESS[18:0]
DATAIN
ROM_CS
INIT_B
DOUT
CLKIN
LDC_DONE
V
CC
(6)
INIT_B
DIN
CCLK
V
CC
(6)
DONE
DOUT
Virtex-4
Master
Serial
INIT_B
DIN
CCLK
Virtex-4
Slave
Serial
DONE
PROGRAM_B
V
CC
PROGRAM_B
Control Signal
ug071_18_073007
Figure 2-5: Serial Daisy Chain Configuration from Parallel EPROM and CPLD
Notes relevant to Figure 2-5:
1.This schematic shows one of many possible implementations.
2.The DONE pin is by default an open-drain output requiring an external pull-up
resistor. A 330Ω pull-up resistor is recommended. For all devices except the first, the
active driver on DONE must be disabled. For the first device in the chain, the active
driver on DONE can be enabled. See “Guidelines and Design Considerations for Serial
Daisy Chains.”
3.The INIT_B pin is a bidirectional, open-drain pin. An external pull-up resistor is
required.
4.The BitGen startup clock setting must be set for CCLK for serial configuration.
5.The .bit file must be reformatted into a PROM file before it can be stored on the
PROM. Refer to the “Generating PROM Files” section.
6.The CCLK net requires Thevenin parallel termination. See “Board Layout for
Configuration Clock (CCLK),” page 34.
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Mixed Serial Daisy Chains
Virtex-4 devices can be daisy-chained with the Virtex, Spartan®-II, Virtex-E, Spartan-IIE,
Virtex-II, Virtex-II Pro, and Spartan-3 families. There are three important design
considerations when designing a mixed serial daisy chain:
•Many older devices cannot accept as fast a CCLK frequency as a Virtex-4 device can
generate. Select a configuration CCLK speed supported by all devices in the chain.
•Newer devices should be grouped at the beginning of the serial daisy chain, with
older devices located at the end of the chain.
•The number of configuration bits that a device can pass through its DOUT pin is
limited. This limit varies for different families (Table 2-3). The sum of the bitstream
lengths for all downstream devices must not exceed the number in this table for each
family.
Table 2-3:Maximum Number of Configuration Bits, Various Device Families
ArchitectureMaximum DOUT Bits
Virtex-432 x( 2
Virtex-II Pro, Virtex-II32 x( 2
Spartan-332 x (2
Virtex, Virtex-E, Spartan-II, Spartan-IIE32 x (2
27
– 1) = 4,294,967,264
27
– 1) = 4,294,967,264
27
– 1) = 4,294,967,264
20
– 1) = 33,554,216
Guidelines and Design Considerations for Serial Daisy Chains
There are a number of important considerations for serial daisy chains:
Startup Sequencing (GTS)
GTS should be released before DONE or during the same cycle as DONE to ensure the
Virtex-4 device is operational when all DONE pins have been released.
Active DONE Driver
All devices except the first should disable the driver on the DONE pin (refer to the BitGen
section of the Development System Reference Guide for software settings):
•DriveDone enabled (first device)
•DriveDone disabled (all devices except the first)
Alternatively, the driver can be disabled for all DONE pins and an external pull-up resistor
added to pull the signal High after all devices have released it.
Connect All DONE Pins
It is important to connect the DONE pins for all devices in a serial daisy chain. Failing to
connect the DONE pins can cause configuration to fail. For debugging purposes, it is often
helpful to have a way of disconnecting individual DONE pins from the common DONE
signal, so that devices can be individually configured through the serial or JTAG interface.
DONE Pin Rise Time
After all DONE pins are released, the DONE pin should rise from logic 0 to logic 1 in one
CCLK cycle. If there are several devices in the serial daisy chain or other loads on the
DONE signal (such as LEDs or microprocessor inputs), external pull-up resistors can be
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required. If additional time is required for the DONE signal to rise, the BitGen donepipe
option can be set for all devices in the serial daisy chain. (Refer to the BitGen section of the
Development System Reference Guide for software settings.)
Board Layout for Configuration Clock (CCLK)
The Virtex-4 output standard for all configuration I/Os, including CCLK, is different from
previous Xilinx FPGAs. To improve performance, the Virtex-4 configuration I/Os use the
LVCMOS fast slew rate standard of 12 mA. This change results in faster edge rates to
support higher configuration frequencies. This requires more attention to PCB trace
routing and termination for proper signal integrity.
These basic guidelines must be followed:
•Route the CCLK net as a 50Ω controlled impedance transmission line.
•Always route the CCLK net without any branching, do not use a star topology
(Figure 2-9).
•Stubs, if necessary, must be shorter than 8 mm (0.3 inches).
•Terminate the end of the CCLK transmission line with a parallel termination of 100Ω
to V
trace characteristic impedance of 50Ω).
, and 100Ω to GND (the Thevenin equivalent of V
CCO
/2, and assuming a
CCO
Xilinx recommends simulating the CCLK distribution with an IBIS simulator (such as
HyperLynx) to check for glitches on each CLK input, including the CCLK of the master
FPGA.
Figure 2-6 through Figure 2-8 show the recommended topologies for CCLK distribution.
Figure 2-6 shows the basic point-to-point topology for one CCLK driver (FPGA master)
Figure 2-6: Point-to-Point: One CCLK Output, One CCLK Input
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CCLK
Output
ug071_2_07_072505
Z0 (50 Ω)
CCLK
Input 2
Z
0
(50 Ω)
CCLK
Input 1
Z
0
(50 Ω)
2 x Z0 (100 Ω)
2 x Z0 (100 Ω)
V
CCO_0
Z
0
(50 Ω)
length < 8mm
CCLK
Output
Z0 (50 Ω)
CCLK
Input 4
Z
0
(50 Ω)
2 x Z0 (100 Ω)
2 x Z0 (100 Ω)
V
CCO_0
Z0 (50 Ω)
Z
0
(50 Ω)
CCLK
Input 2
length < 8mm
Z0 (50 Ω)
Z
0
(50 Ω)
CCLK
Input 3
length < 8mm
Z0 (50 Ω)
Z
0
(50 Ω)
CCLK
Input 1
length < 8mm
ug071_2_08_072505
Figure 2-7 shows the basic multi-drop flyby topology for one CCLK driver and two CCLK
receivers. The stub at CCLK input 1 has a length constraint.
Figure 2-7: Multi-Drop: One CCLK Output, Two CCLK Inputs
Figure 2-8 shows the multi-drop flyby topology for one CCLK driver and more than two
CCLK receivers (four in this example). All CCLK inputs except input 4 have length
constraints.
Figure 2-8: Multi-Drop: One CCLK Output, More Than Two CCLK Inputs
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CCLK
Output
ug071_2_09_080204
Z0
Impedance
Discontinuity
Z
0
CCLK
Input 1
Z
0
CCLK
Input 2
Figure 2-9 shows a star topology where the transmission line branches to the multiple
CCLK inputs. The branch point creates a significant impedance discontinuity. This
arrangement is Not Recommended.
Figure 2-9: Not Recommended
Star Topology: One CCLK Output, Two CCLK Inputs
Daisy-Chaining Virtex-4 with Earlier FPGA Generations
A serial daisy chain can include earlier generations of Xilinx FPGAs (Virtex-II, Virtex,
Spartan-II, 4000, etc.). In general, newer devices should appear upstream of older devices.
For example, a daisy chain consisting of a Virtex-4, a Virtex-II, a Virtex, and a 4000E device
should be arranged with the Virtex-4 device first in the chain, the Virtex-II device second,
the Virtex device third, and the 4000E device last.
BitGen Options for Mixed Daisy Chains
36www.xilinx.comVirtex-4 FPGA Configuration User Guide
All Virtex-based device families have similar BitGen options. The guidelines provided for
Virtex-4 BitGen options should be applied to all Virtex-based devices in a serial daisy
chain.
If 4000-series devices are included in the daisy chain, it is important to set the BitGen
SyncToDONE option for the startup settings.
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Maximum CCLK Rate Varies Between Xilinx Device Families
(1)
DATA
PROGRAM
CLK
DOUTDIN
M2
M1M0
M1M0
CCLK
PROGRAM_B
DONE
DIN
M2
CCLK
PROGRAM_B
DONE
INIT_B
DOUT
INIT_B
CE
RESET/OE
ug071_15_073007
Xilinx
Serial PROM
Virtex-4
Master
Serial
Virtex-4
Slave
Serial
(2)
(8)
(8)
Older Xilinx device families require slower CCLK rates than Virtex-4 devices. For mixed
serial daisy chains, ensure the Master device does not toggle CCLK faster than the slowest
device can tolerate.
PROM File Considerations
The PROM file for a serial daisy chain is larger than the sum of all bitstreams due to
additional configuration instructions. See “Generating PROM Files.”
Ganged Serial Configuration
More than one device can be configured simultaneously from the same bitstream using a
ganged serial configuration setup (Figure 2-10). In this arrangement, the serial
configuration pins are tied together such that each device sees the same signal transitions.
One device is typically set for Master serial mode (to drive CCLK) while the others are set
for Slave serial mode. For ganged serial configuration, all devices must be identical.
Configuration can be driven from a configuration PROM or from an external configuration
controller.
Serial Configuration Interface
Figure 2-10: Ganged Serial Configuration
Notes relevant to Figure 2-10:
1.For ganged serial configuration, the optional DONE driver must be disabled for all
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UG071 (v1.12) June 2, 2017
devices if one device is set for Master mode, because each device might not start up on
exactly the same CCLK cycle. An external pull-up resistor is required in this case.
2.The INIT_B pin is a bidirectional, open-drain pin. An external pull-up resistor is
required.
Chapter 2:Configuration Interfaces
R
3.The BitGen startup clock setting must be set for CCLK for serial configuration.
4.The PROM in this diagram represents one or more Xilinx serial PROMs. Multiple serial
PROMs can be cascaded to increase the overall configuration storage capacity.
5.The .bit file must be reformatted into a PROM file before it can be stored on the serial
PROM. Refer to the “Generating PROM Files” section.
6.On XC17V00 devices, the reset polarity is programmable. RESET
active Low when using an XC17V00 device in this setup.
7.For ganged serial configuration, all devices must be identical (same IDCODE) and
must be configured with the same bitstream.
8.The CCLK net requires Thevenin parallel termination. See “Board Layout for
Configuration Clock (CCLK),” page 34.
There are a number of important considerations for ganged serial configuration:
Startup Sequencing (GTS)
GTS should be released before DONE or during the same cycle as DONE to ensure all
devices are operational when all DONE pins have been released.
Disable the Active DONE Driver On for All Devices
should be set for
For ganged serial configuration, the active DONE driver must be disabled for all devices if
the DONE pins are tied together, because there can be variations in the startup sequencing
of each device. A pull-up resistor is therefore required on the common DONE signal.
-g DriveDone:no (BitGen option, all devices)
Connect All DONE Pins if Using a Master Device
It is important to connect the DONE pins for all devices in ganged serial configuration if
one FPGA is used as the Master device. Failing to connect the DONE pins can cause
configuration to fail for individual devices in this case. If all devices are set for Slave serial
mode, the DONE pins can be disconnected (if the external CCLK source continues toggling
until all DONE pins go High).
For debugging purposes, it is often helpful to have a way of disconnecting individual
DONE pins from the common DONE signal.
DONE Pin Rise Time
After all DONE pins are released, the DONE pin should rise from logic 0 to logic 1 in one
CCLK cycle. If additional time is required for the DONE signal to rise, the BitGen
donepipe option can be set for all devices in the serial daisy chain.
Configuration Clock (CCLK) as Clock Signal for Board Layout
The CCLK signal is an LVCMOS fast 12 mA driver (LVCMOS_P12.) Signal integrity issues
on the CCLK signal can cause configuration to fail. (Typical failure mode: DONE Low,
INIT_B High.) Therefore, careful attention to signal integrity, including signal integrity
simulation with IBIS, is recommended.
Signal Fanout
Special care must be taken in assuring good signal integrity when using ganged serial
configuration. Signal integrity simulation is recommended.
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PROM Files for Ganged Serial Configuration
BUSY
DONE
CCLK
PROGRAM_B
INIT_B
SelectMap Data
M[2:0]
CS_B
RDWR_B
ug071_21_073007
PROM files for ganged serial configuration are identical to the PROM files used to
configure single devices. There are no special PROM file considerations.
SelectMAP Configuration Interface
The SelectMAP configuration interface (Figure 2-11) provides an 8-bit bidirectional
data-bus interface to the Virtex-4 configuration logic that can be used for both
configuration and readback. (For details, refer to Chapter 8)
CCLK is an output in Master SelectMAP mode; in Slave SelectMAP, CCLK is an input. One
or more Virtex-4 devices can be configured through the SelectMAP bus.
There are four methods of configuring an FPGA in SelectMAP mode:
•Single device Master SelectMAP
•Single device Slave SelectMAP
•Multiple device SelectMAP bus
•Multiple device ganged SelectMAP
Table 2-4 describes the SelectMAP configuration interface.
SelectMAP Configuration Interface
Virtex-4 FPGA Configuration User Guidewww.xilinx.com39
Configuration clock source for all configuration
modes except JTAG
Byte-wide (SelectMAP 8 bit) configuration and
readback data bus, clocked on rising edge of
CCLK. D0 is the most-significant bit (MSB), D7 the
least-significant bit (LSB). In SelectMAP 32 bit,
configuring the data order is straight D0 = LSB
and D31 = MSB.
Indicates that the device is not ready to send
readback data. For Virtex-4 devices, the BUSY
signal is only needed for readback; it is not needed
for configuration (see “SelectMAP Data
Loading”).
Active High signal indicating configuration is
complete:
0 = FPGA not configured
1 = FPGA configured
DONE
Bidirectional,
Open-Drain
or active
Dedicated
Before MODE pins are sampled, INIT_B is an
input that can be held Low to delay configuration.
INIT_B
Input or
Output,
Open-Drain
Dedicated
After MODE pins are sampled, INIT_B is an opendrain active Low output indicating whether a CRC
error occurred during configuration:
0 = SelectMAP data bus enabled
1 = SelectMAP data bus disabled
(2)
Determines the direction of the SelectMAP data
bus (see “SelectMAP Data Loading”):
0 = inputs
RDWR_BInputDedicated
1 = outputs
RDWR_B input can only be changed while CS_B is
deasserted, otherwise an ABORT occurs (see
“SelectMAP ABORT”)
(2)
.
Notes:
1. If SelectMAP32 is used and the bitstream is compressed by the -g compress in BitGen then the
CONFIG_MODE constraint must be used. the values for the CONFIG_MODE constraint are either
S_SelectMAP32 or S_SelectMAP32+READBACK. S_SelectMAP32+READBACK preserves the
S_SelectMAP32 data pins for readback (also known as persist).
2. If the SelectMAP interface is not used, the CS_B and RDWR_B pins can be left unconnected. Weak
pullups pull these pins High, and their state is ignored.
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Single Device SelectMAP Configuration
The simplest way to configure a single device in SelectMAP mode is to connect it directly
to a parallel configuration PROM as shown in Figure 2-12. In this arrangement, the device
is set for Master SelectMAP mode, and the RDWR_B and CS_B pins are tied to Ground for
continuous data loading (see “SelectMAP Data Loading”).
Xilinx
Serial PROM
DATA[0:7]
CCLK
CF
(10)
(10)
SelectMAP Configuration Interface
Virtex-4
Master
SelectMAP
M0
M1
M2
D[0:7]
CCLK
PROGRAM_B
(2)(1)
CE
RESET/OE
DONE
INIT_B
RDWR_B
CS_B
ug071_22_073007
Figure 2-12: Single Device Master SelectMAP Configuration
Notes relevant to Figure 2-12:
1.The DONE pin is by default an open-drain output requiring an external pull-up
resistor. A 330Ω pull-up resistor is recommended. In this arrangement, the active
DONE driver can be enabled, eliminating the need for an external pull-up resistor.
2.The INIT_B pin is a bidirectional, open-drain pin. An external pull-up resistor is
required.
3.The BitGen startup clock setting must be set for CCLK for SelectMAP configuration.
4.The PROM in this diagram represents one or more Xilinx serial PROMs. Multiple serial
PROMs can be cascaded to increase the overall configuration storage capacity.
5.The .bit file must be reformatted into a PROM file before it can be stored on the serial
PROM. Refer to the “Generating PROM Files” section.
6.On XC17V00 devices, the reset polarity is programmable. RESET
should be set for
active Low when using an XC17V00 device in this setup.
7.The Xilinx PROM must be set for parallel mode. Note that this mode is not available
for all devices.
8.When configuring a Virtex-4 device in SelectMAP mode from a Xilinx configuration
PROM, the RDWR_B and CS_B signals can be tied Low (see “SelectMAP Data
Loading”).
9.The BUSY signal does not need to be monitored for this setup and can be left
unconnected (see “SelectMAP Data Loading”).
10. The CCLK net requires Thevenin parallel termination. See “Board Layout for
Configuration Clock (CCLK),” page 34.
11. The CCLK pin is an output and an input.
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For custom applications where a microprocessor or CPLD is used to configure a single
Virtex-4 device, either Master or Slave SelectMAP mode can be used (Figure 2-13). See
Xilinx Application Note XAPP502
microprocessor). Refer to “SelectMAP Data Loading” for details on handling the CS_B,
RDWR_B, and BUSY signals.
for information on configuring Virtex devices using a
(7)
ADDRESS
DATA
CSO
CS1
WE
OE
Microprocessor
CPLD
Program
Register
Config.
Register
Register
Memory
(7)
Input
Used for storage
of the configuration
bitstream
PROGRAM_B
CS_B
RDWR_B
CCLK
D[0:7]
(3)(2)
INIT_B
DONE
BUSY
Virtex-4
Slave
SelectMAP
ug071_19_073007
Figure 2-13: Single Slave Device SelectMAP Configuration
from Microprocessor and CPLD
Notes relevant to Figure 2-13:
1.This schematic is from Xilinx Application Note XAPP502
. It is one of many possible
implementations.
2.The DONE pin is by default an open-drain output requiring an external pull-up
resistor. A 330Ω pull-up resistor is recommended. In this arrangement, the active
DONE driver can be enabled, eliminating the need for an external pull-up resistor.
3.The INIT_B pin is a bidirectional, open-drain pin. An external pull-up resistor is
required.
4.The BitGen startup clock setting must be set for CCLK for SelectMAP configuration.
5.The BUSY signal can be left unconnected if readback is not needed.
6.The CS_B and RDWR_B signals can be tied to ground if only one FPGA is going to be
configured and readback is not needed.
7.The CCLK net requires Thevenin parallel termination. See “Board Layout for
Configuration Clock (CCLK),” page 34.
Multiple Device SelectMAP Configuration
Multiple Virtex-4 devices in Slave SelectMAP mode can be connected on a common
SelectMAP bus (Figure 2-14). In a SelectMAP bus, the data pins (SelectMAP data, CCLK,
RDWR_B, BUSY, PROGRAM_B, DONE, and INIT_B share a common connection between
all of the devices. To allow each device to be accessed individually, the CS_B (Chip Select)
inputs must not be tied together. External control of the CS_B signal is required and is
usually provided by a microprocessor or CPLD.
If Readback is going to be performed on the device after configuration, the RDWR_B and
BUSY signals must be handled appropriately. (For details, refer to Chapter 8)
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PROGRAM
INIT
DONE
Virtex-4
Slave
SelectMAP
INIT_B
D[0:7]
CCLK
RDWR_B
BUSY
CS_B
PROGRAM_B
DONE
M0
M1 M2
CS(1)
ug071_20_073007
Virtex-4
Slave
SelectMAP
INIT_B
D[0:7]
CCLK
RDWR_B
BUSY
CS_B
DATA[0:7]
CCLK
WRITE
BUSY
PROGRAM_B
DONE
M0
M1 M2
CS(0)
(1) (2)
(6)
(6)
Otherwise, RDWR_B can be tied Low and BUSY can be ignored. Unlike earlier Virtex
devices, the BUSY signal never needs to be monitored when configuring Virtex-4 devices.
Refer to “Bitstream Loading (Steps 4-7)” in Chapter 1 and to Chapter 8.
Figure 2-14: Multiple Slave Device Configuration on an 8-bit SelectMAP Bus
Notes relevant to Figure 2-14:
1.The DONE pin is by default an open-drain output requiring an external pull-up
resistor. A 330Ω pull-up resistor is recommended. In this arrangement, the active
DONE driver must be disabled.
2.The INIT_B pin is a bidirectional, open-drain pin. An external pull-up resistor is
required.
3.The BitGen startup clock setting must be set for CCLK for SelectMAP configuration.
4.The BUSY signals can be left unconnected if readback is not needed.
5.An external controller such as a microprocessor or CPLD is needed to control
configuration.
6.The CCLK net requires Thevenin parallel termination. See “Board Layout for
Configuration Clock (CCLK),” page 34.
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(2)
DATA[0:7]
CCLK
D[0:7]
CCLK
PROGRAM_B
D[0:7]
CCLK
PROGRAM_B
DONE
DONE
BUSY
BUSY
INIT_B
RDWR_B
CS_B
RDWR_B
CS_B
INIT_B
CE
RESET/OE
CF
ug071_24_073007
Xilinx
Serial PROM
Virtex-4
SelectMAP
Master
Virtex-4
SelectMAP
Slave
(1)
M2
M1 M0
M2
M1 M0
(10)
(10)
Ganged SelectMAP
It is also possible to configure simultaneously multiple devices with the same
configuration bitstream by using ganged SelectMAP configuration. In a ganged
SelectMAP arrangement, the CS_B pins of two or more devices are connected together (or
tied to ground), causing all devices to recognize data presented on the SelectMAP data
pins.
All devices can be set for Slave SelectMAP mode if an external oscillator is available, or one
device can be designated as the Master device, as illustrated in Figure 2-15.
Notes relevant to Figure 2-15:
1.The DONE pin is by default an open-drain output requiring an external pull-up
resistor. A 330Ω pull-up resistor is recommended. In this arrangement, the active
DONE driver must be disabled for both devices.
Figure 2-15: Ganged SelectMAP Configuration
2.The INIT_B pin is a bidirectional, open-drain pin. An external pull-up resistor is
required.
3.The BitGen startup clock setting must be set for CCLK for SelectMAP configuration.
4.The BUSY signal is not used for ganged SelectMAP configuration.
44www.xilinx.comVirtex-4 FPGA Configuration User Guide
5.The PROM in this diagram represents one or more Xilinx Platform Flash PROMs.
Multiple serial PROMs can be cascaded to increase the overall configurations storage
capacity.
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SelectMAP Configuration Interface
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6.The .bit file must be reformatted into a PROM file before it can be stored on the serial
PROM. Refer to the “Generating PROM Files” section.
7.On 17V00 devices, the reset polarity is programmable. Reset should be set for active
Low when using a 17V00 device in this setup.
8.The Xilinx PROM must be set for parallel mode. This mode is not available for all
devices.
9.When configuring a Virtex-4 device in SelectMAP mode from a Xilinx configuration
PROM, the RDWR_B and CS_B signals can be tied Low (see “SelectMAP Data
Loading”).
10. The CCLK net requires Thevenin parallel termination. See “Board Layout for
Configuration Clock (CCLK),” page 34.
If one device is designated as the Master, the DONE pins of all devices must be connected
and with the active DONE drivers disabled. An external pull-up resistor is required on the
common DONE signal. Careful attention must be paid to signal integrity due to the
increased fanout of the outputs from the PROM. Signal integrity simulation is
recommended.
Readback is not possible if the CS_B signals are tied together, as all devices simultaneously
attempt to drive the SelectMAP data signals.
SelectMAP Data Loading
The SelectMAP interface allows for either continuous or non-continuous data loading.
Data loading is controlled by the CS_B, RDWR_B, CCLK, and BUSY signals.
CS_B
The Chip Select input (CS_B) enables the SelectMAP bus. When CS_B is High, the Virtex-4
device ignores the SelectMAP interface, neither registering any inputs nor driving any
outputs. SelectMAP data and BUSY are placed in a high-Z state, and RDWR_B is ignored.
♦If CS_B = 0, the device's SelectMAP interface is enabled.
♦If CS_B = 1, the device's SelectMAP interface is disabled.
CS_B is used for arbitrating between two or more devices on a SelectMAP bus. The active
device is selected by asserting its CS_B signal, while all other devices are deactivated by
deasserting their CS_B signals. If used, the CS_B should be actively driven until the startup
cycle completes, as signaled by the EOS.
If only one device is being configured through the SelectMAP, or if ganged SelectMAP
configuration is used, the CS_B signal can be tied to ground, as illustrated in Figure 2-12
and Figure 2-15.
In Slave Serial mode, the CS_B pin can be left unconnected or can be pulled High in a noisy
environment.
RDWR_B
RDWR_B is an input to the Virtex-4 device that controls whether the SelectMAP data pins
are inputs or outputs:
♦If RDWR_B = 0, the data pins are inputs (writing to the FPGA).
♦If RDWR_B = 1, the data pins are outputs (reading from the FPGA).
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For configuration, RDWR_B must be set for write control (RDWR_B = 0). For readback,
RDWR_B must be set for read control (RDWR_B = 1) while CS_B is deasserted. (For
details, refer to Chapter 8)
Changing the value of RDWR_B while CS_B is asserted triggers an ABORT if the device
gets a rising CCLK edge (see “SelectMAP ABORT”). If readback is not needed, RDWR_B
can be tied to ground.
The RDWR_B signal is ignored while CS_B is deasserted. Read/write control of the data
pins is asynchronous. The FPGA actively drives SelectMAP data without regard to CCLK
if RDWR_B is set for read control (RDWR_B = 1, Readback) while CS_B is asserted.
CCLK
All activity on the SelectMAP data bus is synchronous to CCLK. When RDWR_B is set for
write control (RDWR_B = 0, Configuration), the FPGA samples the SelectMAP data pins
on rising CCLK edges. When RDWR_B is set for read control (RDWR_B = 1, Readback),
the FPGA updates the SelectMAP data pins on rising CCLK edges.
In Slave SelectMAP mode, configuration can be paused by stopping CCLK (see “Non-
Continuous SelectMAP Data Loading”).
BUSY
BUSY is an output from the FPGA indicating when the device is ready to drive readback
data. Unlike earlier Virtex devices, Virtex-4 FPGAs never drive the BUSY signal during
configuration, even at the maximum configuration frequency with an encrypted bitstream.
The Virtex-4 device only drives BUSY during readback. (For details, refer to Chapter 8)
♦If BUSY = 0 during readback, the SelectMAP data pins are driving valid readback
data.
♦If BUSY = 1 during readback, the SelectMAP data pins are not driving valid
readback data.
When CS_B is deasserted (CS_B = 1), the BUSY pin is placed in a high-Z state.
BUSY remains in a high-Z state until CS_B is asserted. If CS_B is asserted before power up
(that is, if the pin is tied to ground), BUSY initially is in a high-Z state, then driven Low
after POR finishes, usually a few milliseconds (T
BUSY
), after V
CCINT
reaches V
before INIT_B goes High.
Unless readback is used, the BUSY pin can be left unconnected.
Continuous SelectMAP Data Loading
Continuous data loading is used in applications where the configuration controller can
provide an uninterrupted stream of configuration data. After power-up, the configuration
controller sets the RDWR_B signal for write control (RDWR_B = 0) and asserts the CS_B
signal (CS_B = 0), causing the device to drive BUSY Low (this transition is asynchronous).
RDWR_B must be driven Low before CS_B is asserted, otherwise an ABORT occurs (see
“SelectMAP ABORT”).
POR
but
On the next rising CCLK edge, the device begins sampling the SelectMAP data pins.
Configuration begins after the synchronization word is clocked into the device.
After the configuration bitstream is loaded, the device enters the startup sequence. The
device asserts its DONE signal (DONE=1) in the phase of the startup sequence that is
specified by the bitstream (see “Startup (Step 8)” in Chapter 1). The configuration
controller should continue sending CCLK pulses until after the startup sequence has
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SelectMAP Configuration Interface
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PROGRAM_B
INIT_B
CCLK
CS_B
RDWR_B
DATA[0:7]
ug071_25_073007
Byte 0Byte 1Byte n
BUSY
DONE
(1)
(2)
(3)
(4)
(5)
(7)
(6)
(8)(9)(10)(11)
(12)
(13)
(14)
High-Z
finished. (This can require several CCLK pulses after DONE goes High. See “Startup (Step
8)” in Chapter 1 for details).
After configuration, the CS_B and RDWR_B signals can be deasserted, or they can remain
asserted. Because the SelectMAP port is inactive, toggling RDWR_B at this time does not
cause an abort. Figure 2-16 summarizes the timing of SelectMAP configuration with
continuous data loading.
Figure 2-16: Continuous SelectMAP Data Loading
Notes relevant to Figure 2-16:
1.CS_B signal can be tied Low if there is only one device on the SelectMAP bus. If CS_B
is not tied Low, it can be asserted at any time.
2.RDWR_B can be tied Low if readback is not needed. RDWR_B should not be toggled
after CS_B has been asserted, because this triggers an ABORT. (See “SelectMAP
ABORT”).
3.If CS_B is tied Low, BUSY is tristated and pulled up until INIT_B toggles High.
4.The MODE pins are sampled when INIT_B goes High.
5.RDWR_B should be asserted before CS_B to avoid causing an abort.
6.CS_B is asserted, enabling the SelectMAP interface.
7.BUSY remains in high-Z state until CS_B is asserted.
8.With 8-bit SelectMAP, the first byte is loaded on the first rising CCLK edge after CS_B
is asserted.
9.The configuration bitstream is loaded one byte per rising CCLK edge.
10. After the last byte is loaded, the device enters the startup sequence.
11. The startup sequence lasts a minimum of eight CCLK cycles. See “Startup (Step 8)” in
Chapter 1
12. The DONE pin goes High during the startup sequence. Additional CCLKs can be
required to complete the startup sequence. (See “Startup (Step 8)” in Chapter 1).
13. After configuration has finished, the CS_B signal can be deasserted.
14. After the CS_B signal is deasserted, RDWR_B can be deasserted.
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PROGRAM_B
INIT_B
CCLK
CS_B
RDWR_B
DATA[0:7]
ug071_26_073007
BUSY
(2)
(5)(6)(7)(8)(9)(10)(11)(12)(13)(14)
(1)
(3)
(4)
High-ZHigh-ZHigh-Z
Non-Continuous SelectMAP Data Loading
Non-continuous data loading is used in applications where the configuration controller
cannot provide an uninterrupted stream of configuration data—for example, if the
controller pauses configuration while it fetches additional data.
Configuration can be paused in two ways: by deasserting the CS_B signal (Free-Running
CCLK method, Figure 2-17) or by halting CCLK (Controlled CCLK method, Figure 2-18).
Figure 2-17: Non-Continuous SelectMAP Data Loading with Free-Running CCLK
Notes relevant to Figure 2-17:
1.RDWR_B is driven Low by the user, setting the SelectMAP data pins as inputs for
configuration. RDWR_B can be tied Low if readback is not needed. RDWR_B should
not be toggled after CS_B has been asserted, as this triggers an ABORT. (See
“SelectMAP ABORT”).
2.Device is ready for configuration after INIT_B toggles High.
3.The user asserts CS_B Low, enabling SelectMAP data bus. CS_B signal can be tied Low
if there is only one device on the SelectMAP bus. If CS_B is not tied Low, it can be
asserted at any time.
4.BUSY goes Low shortly after CS_B is asserted. If CS_B is tied Low, BUSY is d riven Low
before INIT_B toggles High.
5.Byte loaded on rising CCLK edge.
6.Byte loaded on rising CCLK edge.
7.The user deasserts CS_B; byte ignored.
8.The user deasserts CS_B; byte ignored.
9.Byte loaded on rising CCLK edge.
10. Byte loaded on rising CCLK edge.
11. The user deasserts CS_B; byte ignored.
12. Byte loaded on rising CCLK edge.
13. Byte loaded on rising CCLK edge.
14. Byte loaded on rising CCLK edge.
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CCLK
CS_B
RDWR_B
DATA[0:7]
ug071_27_080204
Byte 0Byte 1Byte
n
(1)
(2)
(3)
(4)(5)(6)
Figure 2-18: Non-Continuous SelectMAP Data Loading with Controlled CCLK
Notes relevant to Figure 2-18:
1.SelectMAP data pins are in High-Z state while CS_B is deasserted.
2.RDWR_B has no effect on the device while CS_B is deasserted.
3.CS_B is asserted by the user. Device begins loading configuration data on rising CCLK
edges.
4.Byte loaded on rising CCLK edge.
5.Byte loaded on rising CCLK edge.
6.Byte loaded on rising CCLK edge.
SelectMAP ABORT
An ABORT is an interruption in the SelectMAP configuration or readback sequence
occurring when the state of RDWR_B changes while CS_B is asserted. During a
configuration ABORT, an 8-bit status word is driven onto the SelectMAP data pins over the
next four CCLK cycles. After the ABORT sequence finishes, the user can resynchronize the
configuration logic and resume configuration. For applications that must de-assert
RDWR_B between bytes, see Controlled CCLK method, Figure 2-18.
Configuration Abort Sequence Description
An ABORT is signaled during configuration as follows:
1.The configuration sequence begins normally.
2.The user pulls the RDWR_B pin High while the device is selected (CS_B asserted Low).
3.BUSY goes High if CS_B remains asserted (Low). The FPGA drives the status word
onto the data pins if RDWR_B remains set for read control (logic High).
4.The ABORT lasts for four clock cycles and Status is updated.
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DATA[0:7]
BUSY
CCLK
STAT US
ABORT
ug071_028_091207
CS_B
RDWR_B
DATA[0:7]
BUSY
CCLK
FPGA
ABORT
ug071_029_031104
CS_B
RDWR_B
Figure 2-19: Configuration Abort Sequence
Readback Abort Sequence Description
An ABORT is signaled during readback as follows:
1.The readback sequence begins normally.
2.The user pulls the RDWR_B pin Low while the device is selected (CS_B asserted Low).
3.BUSY goes High if CS_B remains asserted (Low).
4.The ABORT ends when CS_B is deasserted.
Figure 2-20: Readback Abort Sequence
ABORTs during readback are not followed by a status word, because the RDWR_B signal
is set for write control (FPGA SelectMAP data pins are inputs).
ABORT Status Word
During the configuration ABORT sequence, the device drives a status word onto the
SelectMAP data pins. The key for that status word is given in Table 2-5.
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Table 2-5:ABORT Status Word
Bit NumberStatus Bit NameMeaning
Configuration error (active Low)
D7CFGERR_B
0 = A configuration error has occurred.
1 = No configuration error.
Sync word received (active High)
D6DALIGN
0 = No sync word received.
1 = Sync word received by interface logic.
Readback in progress (active High)
D5RIP
0 = No readback in progress.
1 = A readback is in progress.
ABORT in progress (active Low)
D4IN_ABORT_B
0 = Abort is in progress.
1 = No abort in progress.
D3-D01111
The ABORT sequence lasts four CCLK cycles. During those cycles, the status word changes
to reflect data alignment and ABORT status. A typical sequence might be:
After the last cycle, the synchronization word can be reloaded to establish data alignment.
Resuming Configuration or Readback After an Abort
There are two ways to resume configuration or readback after an ABORT:
•The device can be resynchronized after the ABORT completes.
•The device can be reset by pulsing PROGRAM_B Low at any time.
To resynchronize the device, CS_B must be deasserted, then reasserted. The configuration
synchronization word can then be sent. Configuration or readback can be resumed by
sending the last configuration or readback packet that was in progress when the ABORT
occurred. Alternatively, configuration or readback can be restarted from the beginning.
SelectMAP Reconfiguration
The term reconfiguration refers to reprogramming an FPGA after its DONE pin has gone
High. Reconfiguration can be initiated by pulsing the PROGRAM_B pin (this method is
identical to configuration), or by resynchronizing the device and sending configuration
data. The latter method is only available in SelectMAP and JTAG configuration modes.
To reconfigure a device in SelectMAP mode without pulsing PROGRAM_B, the BitGen
persist option must be set—otherwise, the SelectMAP data pins become user I/O after
configuration. Reconfiguration must be enabled in BitGen. The SelectMAP port width is
either 8 or 32 bits as selected by the mode pin settings.
Reconfiguration begins when the synchronization word is clocked into the SelectMAP
port. The remainder of the operation is identical to configuration as described above.
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SelectMAP Data Ordering
In many cases, SelectMAP configuration is driven by a user application residing on a
microprocessor, CPLD, or in some cases another FPGA. In these applications, it is
important to understand how the data ordering in the configuration data file corresponds
to the data ordering expected by the FPGA.
In SelectMAP 8-bit mode, configuration data is loaded at one byte per CCLK, with the MSB
of each byte presented to the D0 pin. This convention (D0 = MSB, D7 = LSB) differs from
many other devices. This can be a source of confusion when designing custom
configuration solutions. Table 2-6 shows how to load the hexadecimal value 0xABCD into
the SelectMAP data bus.
Table 2-6:Bit Ordering for SelectMAP 8-bit Mode
CCLK Cycle
Hex
Equivalent
D0D1D2D3D4D5D6D7
10xAB10101011
20xCD11001101
Notes:
1. D[0:7] represent the SelectMAP 8-bit mode data pins.
Some applications can accommodate the non-conventional data ordering without
difficulty. For other applications, it can be more convenient for the source configuration
data file to be byte-swapped, meaning that the bits in each byte of the data stream are
reversed. For these applications, the Xilinx PROM file generation software can generate
byte-swapped PROM files (see “Configuration Data Files”).
In SelectMAP 32-bit mode, configuring the data order is straight D0 = LSB and D31 = MSB.
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Configuration Data Files
Xilinx design tools can generate configuration data files in a number of different formats,
as described in Table 2-7. BitGen converts the post-PAR .ncd file into a configuration file,
or bitstream. The bitstream contains commands to the FPGA configuration logic as well as
configuration data. (For details on the bitstream format, refer to Chapter 7)
PROMGen, the PROM file generator, converts one or more bitstream files into a PROM file.
PROM files can be generated in a number of different file formats, and need not be used
with a PROM. They can be stored anywhere and delivered by any means.
Table 2-7:Xilinx Configuration File Formats
Configuration Data Files
File
Extension
.bit
.rbt
.bin
.mcs
.exo
.tek
Byte
Swapping
(1)
Not
byte-swapped
Not
byte-swapped
Not
byte-swapped
Byte-swapped
Xilinx Software
(2)
Tool
BitGen (generated
by default)
BitGen (generated if
-b option is set)
BitGen (generated if
-g binary:yes
option is set)
PROMGen or
iMPACT
Description
Binary configuration data file
containing header information that
does not need to be downloaded to
the FPGA. Used to program
devices from iMPACT with a
programming cable.
ASCII equivalent of the .bit file
containing a text header and ASCII
1s and 0s.
Binary configuration data file with
no header information. Similar to
.bit file. Can be used for custom
configuration solutions
(microprocessors, etc.), or in some
cases to program third-party
PROMs.
ASCII PROM file formats
containing address and checksum
information in addition to
configuration data. Used mainly
for device programmers and
iMPACT.
ASCII PROM file format
.hex
Determined
by user
PROMGen or
iMPACT
containing only configuration data.
Used mainly in custom
configuration solutions.
Notes:
1. Byte swapping is discussed in the “Byte Swapping” section.
2. For complete BitGen and PROMGen syntax, refer to the Development System Reference Guide.
Byte Swapping
The .mcs,.exo, and .tek PROM file formats are always byte-swapped. The .hex file
format can be byte-swapped or not byte-swapped, depending on user options. The
bitstream files (.bit,.rbt,.bin) are never byte-swapped.
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Hex:
Binary:
ByteSwapped
Binary:
ByteSwapped
Hex:
SelectMAP
Data Pin:
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1
A B C D
1 1 0 1 0 1 0 1 1 0 1 1 0 0 1 1
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
D 5 B 3
SelectMAP
Data Pin:
The .hex file format contains only configuration data. The other PROM file formats
include address and checksum information that should not be sent to the FPGA. The
address and checksum information is used by some third-party device programmers, but
is not programmed into the PROM.
Figure 2-17 shows how two bytes of data (0xABCD) are byte-swapped.
Figure 2-21: Byte Swapping Example
The MSB of each byte goes to the D0 pin regardless of the orientation of the data:
•In the byte-swapped version of the data, the bit that goes to D0 is the rightmost bit
•In the non-byte-swapped data, the bit that goes to D0 is the leftmost bit.
Whether or not data must be byte-swapped is entirely application-dependent, and is only
applicable for SelectMAP configuration applications. Non-byte-swapped data should be
used for Slave serial downloads.
Generating PROM Files
PROM files are generated from bitstream files with the PROMGen utility. Users can access
PROMGen directly from the command line, or indirectly through the iMPACT File
Generation Mode. For PROMGen syntax, refer to the Development System Reference Guide.
For information on iMPACT, refer to the ISE® Software Documentation). PROM files serve
to reformat bitstream files for PROM programming and combine bitstream files for serial
daisy chains (see “PROM Files for Serial Daisy Chains”).
PROM Files for Serial Daisy Chains
Configuration data for serial daisy chains requires special formatting in that separate .bit
files cannot simply be concatenated together to program the daisy chain. The special
formatting is performed by PROMGen (or iMPACT) when generating a PROM file from
multiple bitstreams. To generate the PROM file, specify multiple bitstreams using the
PROMGen -n option or the iMPACT File Generation Wizard. Refer to software
documentation for details.
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PROMGen reformats the configuration bitstreams by nesting downstream configuration
data into configuration packets for upstream devices. Attempting to program the chain by
sending multiple bitstreams to the first device causes the first device to configure and then
ignore the subsequent data.
PROM Files for SelectMAP Configuration
The .mcs file format is most commonly used to program Xilinx serial configuration
PROMs that in turn programs a single FPGA in SelectMAP mode. For custom
configuration solutions, the .bin and .hex files are the easiest PROM file formats to use
due to their raw data format. In some cases, additional formatting is required; refer to
Xilinx Application Note XAPP502
If multiple configuration bitstreams for SelectMAP configuration resides on a single
memory device, the bitstreams must not be combined into a serial daisy chain PROM file.
Instead, the target memory device should be programmed with multiple .bin or .hex files.
If a single PROM file with multiple, separate data streams is needed, one can be generated
in iMPACT by targeting a Parallel PROM, then selecting the appropriate number of data
streams. This can also be accomplished through the PROMGen command line. Refer to
software documentation for details.
for details.
Generating PROM Files
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Chapter 3
Boundary-Scan and JTAG Configuration
Introduction
Virtex®-4 devices support the new IEEE 1532 standard for In-System Configuration (ISC),
based on the IEEE 1149.1 standard. The IEEE 1149.1 Test Access Port and Boundary-Scan
Architecture is commonly referred to as JTAG. JTAG is an acronym for the Joint Test Action
Group, the technical subcommittee initially responsible for developing the standard. This
standard provides a means to ensure the integrity of individual components and the
interconnections between them at the board level. With multi-layer PC boards becoming
increasingly dense and more sophisticated surface mounting techniques in use, BoundaryScan testing is becoming widely used as an important debugging standard.
Devices containing Boundary-Scan logic can send data out on I/O pins in order to test
connections between devices at the board level. The circuitry can also be used to send
signals internally to test the device-specific behavior. These tests are commonly used to
detect opens and shorts at both the board and device level.
In addition to testing, Boundary-Scan offers the flexibility for a device to have its own set
of user-defined instructions. The added common vendor-specific instructions, such as
configure and verify, have increased the popularity of Boundary-Scan testing and
functionality.
Boundary-Scan for Virtex-4 Devices Using IEEE Standard 1149.1
The Virtex-4 family is fully compliant with the IEEE Standard 1149.1 Test Access Port and
Boundary-Scan Architecture. The architecture includes all mandatory elements defined in
the IEEE 1149.1 Standard. These elements include the Test Access Port (TAP), the TAP
controller, the instruction register, the instruction decoder, the Boundary-Scan register, and
the bypass register. The Virtex-4 family also supports a 32-bit identification register and a
configuration register in full compliance with the standard. Outlined in the following
sections are the details of the JTAG architecture for Virtex-4 devices.
Test Access Port
The Virtex-4 TAP contains four mandatory dedicated pins as specified by the protocol
given in Table 3-1 and illustrated in Figure 3-1, a typical JTAG architecture. Three input
pins and one output pin control the 1149.1 Boundary-Scan TAP controller. Optional control
pins, such as TRST (Test Reset) and enable pins might be found on devices from other
manufacturers. It is important to be aware of these optional signals when interfacing
Xilinx® devices with parts from different vendors, because they might need to be driven.
The TAP controller is a state machine (16-states) shown in Figure 3-2. The four mandatory
TAP pins are outlined below.
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IEEE Standard 1149.1 Compliant Device
TMS
Instruction Register
Instruction Decoder
Bypass[1] Register
IDCODE[32] Register
Boundary-Scan[N] Register
Select Data
Register
Shift-IR/Shift-DR
Select Next State
TAP State Machine
TCK
TDI
TDO
I/OI/OI/OI/O
Test-Logic-Reset
Run-Test/Idle
Select-DR
Capture-DR
Shift-DR
Exit1-DR
Pause-DR
Exit2-DR
Update-DR
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
Select-IR
Capture-IR
Shift-IR
Exit1-IR
Pause-IR
Exit2-IR
Update-IR
0
0
0
0
0
0
1
1
1
1
1
1
0
0
11
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Table 3-1:Virtex-4 TAP Controller Pins
PinDescription
TDITest Data In. This pin is the serial input to all JTAG instruction and data registers.
The state of the TAP controller and the current instruction determine the register that
is fed by the TDI pin for a specific operation. TDI has an internal resistive pull-up to
provide a logic High to the system if the pin is not driven. TDI is applied into the JTAG
registers on the rising edge of TCK.
TDOTest Data Out. This pin is the serial output for all JTAG instruction and data registers.
The state of the TAP controller and the current instruction determine the register
(instruction or data) that feeds TDO for a specific operation. TDO changes state on the
falling edge of TCK and is only active during the shifting of instructions or data
through the device. TDO is an active driver output.
TMSTest Mode Select. This pin determines the sequence of states through the TAP
controller on the rising edge of TCK.
TMS has an internal resistive pull-up to provide a logic High if the pin is not driven.
TCKTest Clock. This pin is the JTAG Test Clock.
TCK sequences the TAP controller and the JTAG registers in the Virtex-4 devices.
Notes:
1. As specified by the IEEE Standard, the TMS and TDI pins both have internal pull-up resistors. These
internal pull-up resistors of 50-150 kΩ are active, regardless of the mode selected.
For JTAG configuration mode, JTAG inputs use the V
Figure 3-1: Typical JTAG Architecture
CCO_CFG
supply.
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TAP Controller
Figure 3-2 diagrams a 16-state finite state machine. The four TAP pins control how data is
scanned into the various registers. The state of the TMS pin at the rising edge of TCK
determines the sequence of state transitions. There are two main sequences, one for
shifting data into the data register and the other for shifting an instruction into the
instruction register.
A transition between the states only occurs on the rising edge of TCK, and each state has a
different name. The two vertical columns with seven states each represent the Instruction
Path and the Datapath. The data registers operate in the states whose names end with
"DR," and the instruction register operates in the states whose names end in "IR." The states
are otherwise identical.
The operation of each state is described below.
Test-Logic-Reset:
All test logic is disabled in this controller state, enabling the normal operation of the IC.
The TAP controller state machine is designed so that regardless of the initial state of the
controller, the Test-Logic-Reset state can be entered by holding TMS High and pulsing
TCK five times. Consequently, the Test Reset (TRST) pin is optional.
Run-Test-Idle:
In this controller state, the test logic in the IC is active only if certain instructions are
present. For example, if an instruction activates the self test, then it is executed when the
controller enters this state. The test logic in the IC is idle otherwise.
Boundary-Scan for Virtex-4 Devices Using IEEE Standard 1149.1
Select-DR-Scan:
This controller state controls whether to enter the Datapath or the Select-IR-Scan state.
Select-IR-Scan:
This controller state controls whether or not to enter the Instruction Path. The controller
can return to the Test-Logic-Reset state otherwise.
Capture-IR:
In this controller state, the shift register bank in the Instruction Register parallel loads a
pattern of fixed values on the rising edge of TCK. The last two significant bits must always
be 01.
Shift-IR:
In this controller state, the instruction register gets connected between TDI and TDO, and
the captured pattern gets shifted on each rising edge of TCK. The instruction available on
the TDI pin is also shifted in to the instruction register. If the Shift-IR state is entered after
a Pause-IR state is used, then the first bit shifted is always 0. This does not occur if the
Pause-IR state is not used prior to a Shift-IR state, which is not fully compliant with the
JTAG 1149.1 specification.
Exit1-IR:
This controller state controls whether to enter the Pause-IR state or Update-IR state.
Pause-IR:
This state allows the shifting of the instruction register to be temporarily halted.
Exit2-DR:
This controller state controls whether to enter either the Shift-IR state or Update-IR state.
Update-IR:
In this controller state, the instruction in the instruction register is latched to the latch bank
of the Instruction Register on every falling edge of TCK. This instruction becomes the
current instruction after it is latched.
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TEST-LOGIC-RESET
0
RUN-TEST/IDLE
1
SELECT-DR-SCAN
0
1
0
CAPTURE-DRCAPTURE-IR
0
1
0
0
SHIFT-DRSHIFT-IR
1
0
1
0
EXIT1-DREXIT1-IR
0
1
0
PAUSE-DRPAUSE-IR
1
0
1
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
1
UPDATE-IR
1
SELECT-IR-SCAN
0
10
0
0
1
1
0
NOTE: The value shown adjacent to each state transition in this figure
represents the signal present at TMS at the time of a rising edge at TCK.
Capture-DR:
In this controller state, the data is parallel-loaded into the data registers selected by the
current instruction on the rising edge of TCK.
Shift-Dr, Exit1-DR, Pause-DR, Exit2-DR, and Update-DR:
These controller states are similar to the Shift-IR, Exit1-IR, Pause-IR, Exit2-IR, and UpdateIR states in the Instruction path.
Figure 3-2:Boundary-Scan Tap Controller
Virtex-4 devices support the mandatory IEEE 1149.1 commands, as well as several Xilinx
vendor-specific commands. The EXTEST, INTEST, SAMPLE/PRELOAD, BYPASS,
IDCODE, USERCODE, and HIGHZ instructions are all included. The TAP also supports
internal user-defined registers (USER1, USER2, USER3, and USER4) and
configuration/readback of the device.
The Virtex-4 Boundary-Scan operations are independent of mode selection. The BoundaryScan mode in Virtex-4 devices overrides other mode selections. For this reason, BoundaryScan instructions using the Boundary-Scan register (SAMPLE/PRELOAD, INTEST, and
EXTEST) must not be performed during configuration. All instructions except the userdefined instructions are available before a Virtex-4 device is configured. After
configuration, all instructions are available.
JSTART and JSHUTDOWN are instructions specific to the Virtex-4 architecture and
configuration flow.
For details on the standard Boundary-Scan instructions EXTEST, INTEST, and BYPASS,
refer to the IEEE Standard.
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Boundary-Scan Architecture
Virtex-4 device registers include all registers required by the IEEE 1149.1 Standard. In
addition to the standard registers, the family contains optional registers for simplified
testing and verification (Table 3-2).
User-Defined Registers
(USER1, USER2, USER3,
and USER4)
Controls and observes input,
output, and output enable.
Holds current instruction OPCODE
and captures internal device status.
Allows access to the configuration
bus when using the CFG_IN or
CFG_OUT instructions.
Design-specificDesign-specific.
Boundary-Scan Register
The test primary data register is the Boundary-Scan register. Boundary-Scan operation is
independent of individual IOB configurations. Each IOB, bonded or un-bonded, starts as
bidirectional with 3-state control. Later, it can be configured to be an input, output, or
3-state only. Therefore, three data register bits are provided per IOB (Figure 3-3).
When conducting a data register (DR) operation, the DR captures data in a parallel fashion
during the CAPTURE-DR state. The data is then shifted out and replaced by new data
during the SHIFT-DR state. For each bit of the DR, an update latch is used to hold the input
data stable during the next SHIFT-DR state. The data is then latched during the
UPDATE-DR state when TCK is Low. The internal DR CLK follows TCK when the TAP
controlle r is in the CAPTURE-DR state and SHIFT-DR state, however, it can toggle in other
states.
The update latch is opened each time the TAP controller enters the UPDATE-DR state. Care
is necess ary when exercis ing an INTEST or EXTEST to ensure that the proper data has been
latched before exercising the command. This is typically accomplished by using the
SAMPLE/PRELOAD instruction.
Consider internal pull-up and pull-down resistors when developing test vectors for testing
opens and shorts. The Boundary-Scan mode determines whether the IOB has a pull-up
resistor. Figure 3-3 is a representation of Virtex-4 Boundary-Scan architecture.
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DQ
1
0
1x
01
00
1x
01
00
1x
01
00
DQ
DQ
1
0
1
0
DQ
LE
sd
sd
LE
DQ
sd
LE
DQ
TDI
IOB.I
INTEST
IOB.O
IOB.T
EXTEST
SHIFTCLOCK DATA
REGISTER
TDO UPDATEINTEST is OR'd with EXTEST
ug071_39_121703
Figure 3-3: Virtex-4 Family Boundary-Scan Logic
Bit Sequence Boundary-Scan Register
The order of each non-TAP IOB is described in this section. The input is first, then the
output, and finally the 3-state IOB control. The 3-state IOB control is closest to the TDO.
The input-only pins contribute only the input bit to the Boundary-Scan I/O data register.
The bit sequence of the device is obtainable from the Boundary-Scan Description Language Files (BSDL files) for the Virtex-4 family. (These files can be obtained from the Xilinx
software download area.) The bit sequence always has the same bit order and the same
number of bits, and is independent of the design.
Instruction Register
The Instruction Register (IR) for the Virtex-4 device is connected between TDI and TDO
during an instruction scan sequence. In preparation for an instruction scan sequence, the
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instruction register is parallel-loaded with a fixed instruction capture pattern. This pattern
is shifted out onto TDO (LSB first), while an instruction is shifted into the instruction
register from TDI.
To determine the operation to be invoked, an OPCODE necessary for the Virtex-4
Boundary-Scan instruction set is loaded into the Instruction Register. The length of the IR
is device size-specific. The IR is 10 bits wide for all Virtex-4 LX, SX, and single-processor FX
devices. FX devices with two processors have a 14-bit IR. The bottom six bits of the
instruction codes are the same for all devices sizes to support the new IEEE Standard 1532
for In-System Configurable (ISC) devices. The additional IR bits for each instruction are 1s.
Table 3-3 lists the available instructions for Virtex-4 devices. Figure 3-4 shows the
instruction capture values loaded into the IR as part of an instruction scan sequence.
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Boundary-Scan for Virtex-4 Devices Using IEEE Standard 1149.1
ISC_PROGRAM_SECURITY1111010010Change security status from secure to non-secure mode and vice versa
ISC_ADDRESS_SHIFT1111010011For programming, key address is shifted first, before the key
ISC_NOOP1111010100No operation
ISC_READ1111010101Used to read back BBR
ISC_DISABLE1111010111Completes ISC configuration. Startup sequence is executed
BYPASS1111111111Enables BYPASS
RESERVED
Notes:
1. For FX devices with two processors, the instruction codes are MSB extended with 1s. For example, the CFG_IN instruction is
1111 1111 000101.
TDI →
IR[9:6]IR[5]IR[4]IR[3]IR[2]IR[1:0]
ReservedDONEINITISC_ENABLEDISC_DONE0 1
All other codes
Xilinx reserved instructions
→ TDO
Figure 3-4:Virtex-4 Instruction Capture Values Loaded into IR as Part of an Instruction Scan Sequence
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BYPASS Register
The other standard data register is the single flip-flop BYPASS register. It passes data
serially from the TDI pin to the TDO pin during a bypass instruction. This register is
initialized to zero when the TAP controller is in the CAPTURE-DR state.
Identification Register
Virtex devices have a 32-bit identification register called the IDCODE register. The
IDCODE is based on the IEEE 1149.1 standard, and is a fixed, vendor-assigned value that is
used to identify electrically the manufacturer and the type of device that is being
addressed. This register allows easy identification of the part being tested or programmed
by Boundary-Scan, and it can be shifted out for examination by using the IDCODE
instruction.
The Virtex-4 JTAG ID Code register has the following format:
vvvv:fffffff:aaaaaaaaa:ccccccccccc1
where
v = the revision code
f = the 7-bit family code (0001011 for Virtex-4 LX family, 0010000 for Virtex-4 SX family, 0001111 for Virtex-4 FX family)
a = the number of array rows plus columns in the part, expressed in 9 bits:
XC4VLX15 columns + rows=64 + 24 =88 =0x058
XC4VLX25 columns + rows=96 + 28 =124 =0x07C
XC4VLX40 columns + rows=128 + 36 =164 =0x0A4
XC4VLX60 columns + rows=128 + 52 =180 =0x0B4
XC4VLX80 columns + rows=160 + 56 =216 =0x0D8
XC4VLX100 columns + rows=192 + 64 =256 =0x100
XC4VLX160 columns + rows=192 + 88 =280 =0x118
XC4VLX200 columns + rows=192 + 116 =308 =0x134
XC4VSX25 columns + rows=64 + 40 =104=0x068
XC4VSX35 columns + rows=96 + 40 =136=0x088
XC4VSX55 columns + rows=128 + 48 =176=0x0B0
XC4VFX12 columns + rows=64 + 24 =88=0x058
XC4VFX20 columns + rows=64 + 36 =100 =0x064
XC4VFX40 columns + rows=96 + 52 =148=0x094
(1)
XC4VFX60 columns + rows=128 + 52 =180=0x0B4
XC4VFX100 columns + rows=160 + 68 =228=0x0E4
XC4VFX140 columns + rows=192 + 84 =276=0x114
Notes:
1. The actual array size is 148. The JTAG ID code reflects an array size of 96 + 44 = 140
(0x08C).
c = the company code.
The last bit of the IDCODE is always 1 (based on JTAG IEEE 1149.1). The last three hex
digits appear as 0x093. IDCODEs assigned to Virtex-4 FPGAs are shown in Table 3-4.
Note the similarity to the device ID codes in Table 1-6.
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Table 3-4:Virtex-4 Device JTAG ID Codes
DeviceIDCODEDeviceIDCODEDeviceIDCODE
XC4VLX1501658093XC4VFX1201E58093
XC4VLX250167C093XC4VSX2502068093XC4VFX2001E64093
XC4VLX40016A4093XC4VSX3502088093XC4VFX4001E8C093
XC4VLX60016B4093XC4VSX55020B0093XC4VFX6001EB4093
XC4VLX80016D8093
XC4VLX10001700093XC4VFX10001EE4093
XC4VLX16001718093XC4VFX14001F14093
XC4VLX20001734093
Notes:
1. Does not reflect the actual device array size.
Examples of how the binary digits translate into hex codes appear in Table 3-5.
Table 3-5:Example JTAG IDCODE Concatenation
vvvvfffffffaaaaaaaaaccccccccccc1
XC4VLX15bin<vvvv>0001011001011000000010010011
hex<v>1658093
XC4VLX25bin<vvvv>0001011001111100000010010011
hex<v>167C093
XC4VLX40bin<vvvv>0001011010100100000010010011
hex<v>16A4093
XC4VLX60bin<vvvv>0000011010110100000010010011
hex<v>16B4093
XC4VLX80bin<vvvv>0001011011011000000010010011
hex<v>16D8093
XC4VLX100bin<vvvv>0001011100000000000010010011
hex<v>1700093
XC4VLX160bin<vvvv>0001011100011000000010010011
hex<v>1718093
XC4VLX200bin<vvvv>0001011100110100000010010011
hex<v>1734093
XC4VSX25bin<vvvv>0010000001101000000010010011
hex<v>2068093
XC4VSX35bin<vvvv>0010000010001000000010010011
hex<v>2088093
XC4VSX55bin<vvvv>0010000010110000000010010011
hex<v>20B0093
XC4VFX12bin<vvvv>0001111001011000000010010011
hex<v>1E58093
XC4VFX20bin<vvvv>0001111001100100000010010011
(1)
Virtex-4 FPGA Configuration User Guidewww.xilinx.com65
The configuration register is a 64-bit register. This register allows access to the
configuration bus and readback operations.
USERCODE Register
The USERCODE instruction is supported in the Virtex-4 family. This register allows a user
to specify a design-specific identification code. The USERCODE can be programmed into
the device and can be read back for verification later. The USERCODE is embedded into
the bitstream during bitstream generation (BitGen -g UserID option) and is valid only
after configuration. If the device is blank or the USERCODE was not programmed, the
USERCODE register contains 0xFFFFFFFF.
USER1, USER2, USER3, and USER4 Registers
The USER1, USER2, USER3, and USER4 registers are only available after configuration.
These four registers must be defined by the user within the design. These registers can be
accessed after they are defined by the TAP pins.
The BSCAN_VIRTEX4 library macro is required when creating these registers. This symbol
is only required for driving internal scan chains (USER1, USER2, USER3, and USER4).
A common input pin (TDI) and shared output pins represent the state of the TAP controller
(RESET, SHIFT, and UPDATE). Unlike earlier FPGA families that required the BSCAN
macro to dedicate TAP pins for Boundary-Scan, Virtex-4 TAP pins are dedicated and do
not require the BSCAN_VIRTEX4 macro for normal Boundary-Scan instructions or
operations. For HDL, the BSCAN_VIRTEX4 macro must be instantiated in the design.
Using Boundary-Scan in Virtex-4 Devices
Characterization data for some of the most commonly requested timing parameters shown
in Figure 3-5 are listed in the Virtex-4 FPGA Data Sheet in the Configuration Switching
Characteristics table.
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ug071_35_121703
Data to be captured
Data to be driven out
TDO
TCK
TDI
TMS
Data Valid
Data Valid
T
TCKTDO
T
TAPTCK
T
TCKTAP
Figure 3-5: Virtex-4 Boundary-Scan Port Timing Waveforms
For further information on the startup sequence, bitstream, and internal configuration
registers referenced here, refer to “Setup (Steps 1-3)” in Chapter 1.
Configuring Through Boundary-Scan
One of the most common Boundary-Scan vendor-specific instructions is the configure
instruction. An individual Virtex-4 device can be configured through JTAG on power-up. If
the Virtex-4 device is configured on power-up, it is advisable to tie the mode pins to the
Boundary-Scan configuration mode settings: 101 (M2 = 1, M1 = 0, M0 = 1).
The configuration flow for Virtex-4 device configuration with JTAG is shown in Figure 3-6.
The sections that follow describe how the Virtex-4 device can be configured as a single
device through the Boundary-Scan or as part of a multiple-device scan chain.
A configured device can be reconfigured by toggling the TAP and entering a CFG_IN
instruction after pulsing the PROGRAM pin or issuing the shut-down sequence. (Refer to
Figure 3-6.)
Designers who wish to implement the Virtex-4 JTAG configuration algorithm are
encouraged to use the SVF-based flow provided in Xilinx Application Note XAPP058
.
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Chapter 3:Boundary-Scan and JTAG Configuration
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Sample
Mode Pins
JTAG Available
Keep Clearing
Configuration
Memory
No
No
Ye s
Ye s
Ye s
Ye s
No
Ye s
Clear Configuration
Memory Once More
Power-Up
V
CCINT
> 1.0 V
CRC
Correct?
Load CFG_IN
Instruction
Load
Bitstream
Abort Startup
Shutdown
Sequence
Reconfigure?
Load JSTA RT
Instruction
Synchronous
TAP Reset
Startup
Sequence
Operational
INIT_B = High?
PROGRAM_B
Low?
ug071_40_073007
Load
JSHUTDOWN
Instruction
No
(Clock five 1s
on TMS)
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Figure 3-6:Device Configuration Flow Diagram
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Single Device Configuration
Table 3-6 describes the TAP controller commands required to configure a Virtex-4 device.
Refer to Figure 3-2 for TAP controller states. These TAP controller commands are issued
automatically if configuring the part with the iMPACT software.
Table 3-6: Single Device Configuration Sequence
TAP Controller Step and Description
Set & Hold# of Clocks
TDITMSTCK
1.On power-up, place a logic 1 on the TMS, and clock
the TCK five times. This ensures starting in the TLR
X15
(Test-Logic-Reset) state.
2.Move into the RTI state.X01
3.Move into the SELECT-IR state.X12
4.Enter the SHIFT-IR state.X02
5.Start loading the CFG_IN instruction, LSB first:11100010109
6.Load the MSB of CFG_IN instruction when exiting
SHIFT-IR, as defined in the IEEE standard.
111
7.Enter the SELECT-DR state.X12
8.Enter the SHIFT-DR state.X02
9.Shift in the Virtex-4 bitstream. Bit
bit in the bitstream
(1)
.
10.Shift in the last bit of the bitstream. Bit0 (LSB) shifts
on the transition to EXIT1-DR.
(MSB) is the first
n
bit1... bit
bit
0
n
0
(bits in
bitstream)-1
11
11.Enter UPDATE-DR state.X11
12.Reset TAP by clocking five 1s on TMSX15
13.Enter the SELECT-IR state.X12
14.Move to the SHIFT-IR state.X02
15.Start loading the JSTART instruction. The JSTART
instruction initializes the startup sequence.
11100110009
16.Load the last bit of the JSTART instruction.111
17.Move to the UPDATE-IR state.X11
18.Move to the RTI state and clock the startup
sequence by applying a minimum of 12 clock cycles
X012
to the TCK.
19.Move to the TLR state. The device is now
functional.
Notes:
1. In the Configuration Register, data is shifted in from the right (TDI) to the left (TDO), MSB first. (Shifts into the Configuration Register are
different from shifts into the other registers in that they are MSB first.)
X13
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Multiple Device Configuration
It is possible to configure multiple Virtex-4 devices in a chain. (See Figure 3-7.) The devices
in the JTAG chain are configured one at a time. The multiple device configuration steps can
be applied to any size chain.
Refer to the state diagram in Figure 3-2 for the following TAP controller steps:
1.On power-up, place a logic 1 on the TMS and clock the TCK five times. This ensures
starting in the TLR (Test-Logic-Reset) state.
2.Load the CFG_IN instruction into the target device (and BYPASS in all other devices).
Go through the RTI state (RUN-TEST/IDLE).
3.Load in the configuration bitstream per step 7 through step 11 in Table 3-6.
4.Repeat step 2 and step 3 for each device.
5.Reset all TAPs by clocking five 1s on TMS.
6.Load the JSTART command into all devices.
7.Go to the RTI state and clock TCK 12 times.
All devices are active at this point.
JTAG Header
TDO
TDI
TMS
TCK
Virtex-4
FPGA
TDO
TDI
TMS
TCK
PROGRAM_B
Virtex-4
FPGA
TDI
TMS
TCK
PROGRAM_B
TDO
Device 0Device 1Device 2
Virtex-4
FPGA
TDOTDI
TMS
TCK
PROGRAM_B
ug071_36_073007
Figure 3-7:Boundary-Scan Chain of Devices
Reconfiguring through Boundary-Scan
The ability of Virtex-4 devices to perform partial reconfiguration is the reason that the
configuration memory is not cleared when reconfiguring the device. When reconfiguring a
chain of devices, refer to step 3 in Table 3-6. There are two methods to reconfigure Virtex-4
devices without possible internal contention. The first method is to pulse the
PROGRAM_B pin, resetting the internal configuration memory. The alternate method is to
perform a shutdown sequence, placing the device in a safe state. The following shutdown
sequence includes using internal registers. (For details on internal registers, refer to
Chapter 8)
1.Load the CFG_IN instruction.
2.In the SHIFT-DR state, load the synchronization word followed by the Reset CRC
Register (RCRC) command.
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Unprogrammed
(0,0)
Power
UP
ISC_ENABLE is executed
TLR & ISC_Done is clear
ISC_Accessed
(1,X)
Operational
(0,1)
ISC Complete
(0,X)
Any non-test instruction,
but ISC_ENABLE
executed
Any non-test instruction,
but ISC_ENABLE
executed
Any non-test instruction,
but ISC_DISABLE loaded
and ISC_DONE is set
Any non-test instruction,
but ISC_DISABLE loaded
and ISC_DONE is clear
TLR and
ISC_Done
is set
ISC_ENABLE
executed
(ISC_Enabled, ISC_Done)
ISC_Done is clear
ISC_Done is set
Any non-test
instruction, but
ISC_DISABLE
executed
ISC_DISABLE
loaded
ISC_DISABLE
executed
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3.Load JSHUTDOWN.
4.Go to the RTI state and clock TCK at least 12 times to clock the shutdown sequence.
5.Proceed to the SHIFT-IR state and load the CFG_IN instruction again.
6.Go to the SHIFT-DR state and load the configuration bits. Make sure the configuration
bits contain the AGHIGH command, asserting the global signal GHIGH_B. This
prevents contention while writing configuration data.
7.When all configuration bits have been loaded, reset the TAP by clocking five 1s on
TMS.
8.Go to the SHIFT-IR state and load the JSTART instruction.
9.Go to the RTI state and clock TCK at least 12 times to clock the startup sequence.
10. Go to the TLR state to complete the reconfiguration process.
Boundary-Scan for Virtex-4 Devices Using IEEE Standard 1532
ISC Modal States
Figure 3-8:ISC Modal States
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Once the device is powered up, it goes to the Unprogrammed state. The I/Os are all either
3-stated or pulled up. When ISC_ENABLE is successfully executed, the ISC_Enabled
signal is asserted, and the device moves to the ISC_Accessed state. When the device moves
Chapter 3:Boundary-Scan and JTAG Configuration
R
to the ISC_Accessed state from the Operational state, the shutdown sequence is executed.
The I/Os are all either 3-stated or pulled up.
The startup sequence is executed when in the ISC_Accessed state. At the end of the startup
sequence, ISC_Enabled is cleared and the device moves to ISC_Complete. The minimum
clock cycle requirement is the number of clock cycles required to complete the startup
sequence. At the completion of the minimum required clock cycles, ISC_Enabled is
deasserted.
Whether the startup sequence is successful or not is determined by CRC or configuration
error status from the configuration processor. If the startup is completed, ISC_Done is
asserted; otherwise, ISC_Done stays Low. The I/Os are either 3-stated or pulled up.
When ISC_Done is set in ISC_Complete state, the device moves to the Operational state.
Otherwise, if ISC_Done is clear, the device moves to the Un programmed state. H owever, if
the TAP controller goes to the TLR state while the device is in ISC_Accessed state, and if
ISC_Done is set, then the device moves to the Operational state.
Though Operational, the I/O is not active yet because the startup sequence has not been
performed. The startup sequence has to be performed in the Operational state to bring the
I/O active.
Clocking Startup and Shutdown Sequences (JTAG)
There are three clock sources for startup and shutdown sequence: CCLK, UserCLK, and
JTAGCLK. Clock selection is set by BitGen. The startup sequence is executed in the
ISC_Accessed state. When it is clocked by JTAGCLK, the startup sequence receives the
JTAGCLK in TAP Run/Test Idle state while ISC_DISABLE is the current JTAG instruction.
The number of clock cycles in Run/Test Idle state for successful completion of
ISC_DISABLE is determined by the number of clock cycles needed to complete the startup
sequence.
When UserCLK or CCLK is used to clock the startup sequence, the user should know how
many JTAGCLK cycles should be spent in Run/Test Idle to complete the startup sequence
successfully.
The shutdown sequence is executed when the device transitions from the Operational to
the ISC_Accessed state. Shutdown is done while executing the ISC_ENABLE instruction.
When the shutdown sequence is clocked using JTAGCLK, the clock is supplied in the
Run/Test Idle state of the ISC_ENABLE instruction. The number of clock cycles in
Run/Test Idle is determined by the number of clock cycles needed to complete the
shutdown sequence.
When the shutdown sequence is clocked by CCLK or UserCLK, the user is responsible for
knowing how many JTAGCLK cycles in Run/Test Idle are needed to complete the
shutdown sequence.
Note:
When configuring the device through JTAG, the startup and shutdown clock should
come from TCK, regardless of the selection in BitGen. In IEEE 1532 configuration
mode, the startup and shutdown clock source is always TCK.
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Configuration Flows Using JTAG
PROGRAM_B
Power-Up
Vcc > ?
Ye s
PROGRAM_B?
No
Clear Configuration
memory once more
INIT_B
= High?
Ye s
Sample mode pins
Load ISC_ENABLE
No
No
Ye s
Keep clearing
Configuration memory
A
Load 64 bits of
bitstream data
RTI
1 TCK cycles
No
End of
Data?
Ye s
CRC
correct?
Ye s
Load ISC_DISABLE
RTI minimum
12 TCK cycles
No
Pull INIT_B LowSTOP
Load 00000
RTI minimum
12 TCK cycles
Load ISC_PROGRAM
A
Operational
Ye s
Reconfigure?
Figure 3-9: IEEE 1532 Configuration Flow
No
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Chapter 3:Boundary-Scan and JTAG Configuration
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IDCODE
Unprog.ISC_Accessed
Disable (3-stated)
ISC_CompleteOperational
Active
Start-up
ISC_ENABLEAnything but ISC_DISABLEISC_DISABLEBYPASSTAP Instr.
ISC_Enabled
ISC_Done
End of Startup
Modal State
System
Output
ug071_37_121703
IDCODE
Operational
ISC_Accessed
Disabled
ISC_CompleteOperational
Active
Start-up
ISC_ENABLEAnything but ISC_DISABLEISC_DISABLEBYPASS
TAP Instr.
ISC_Enabled
ISC_Done
End of Startup
Modal State
System
Output
ug071_38_121703
Figure 3-10: Signal Diagram for Successful First Time ISC Configuration
Figure 3-11:Signal Diagram for Successful ISC Partial and Full Reconfiguration
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Frame ECC Logic
Using Frame ECC Logic
Configurable memory is highly reliable, however to provide extra reliability, the solution
explained in this chapter has been provided.
The Frame error correction code (ECC) logic of the Virtex®-4 FPGA is designed to detect
single- or double-bit errors in configuration frame data. It uses SECDED (Hamming code)
parity values based on the frame data generated by BitGen. During readback, the Frame
ECC logic calculates a syndrome value using all the bits in the frame, including the ECC
bits. If the bits have not changed from the original programmed values, then the syndrome
are all 0s. If a single bit has changed, including any of the ECC bits, then the location of the
bit is indicated by syndrome bits 10:0 and syndrome bit 11 is 1. If two bits have changed,
then syndrome bit 11 is 0 and the remaining bits is non-zero and meaningless. If more than
two bits have changed then the syndrome is indeterminate. The error output of the block is
asserted if one or two bits have changed, indicating that action needs to be taken.
Chapter 4
To use the Frame ECC logic, FRAME_ECC _VIRTEX4 must be instantiated in the user's
design, and readback must be performed through SelectMAP, JTAG, or ICAP. At the end of
each frame of readback, the syndrome_valid signal is asserted for one cycle of the readback
clock (CCLK, TCK, or ICAP_CLK). The number of cycles required to read back a frame
varies with the interface used. Refer to Chapter 8, “Readback and Configuration
Verification,” for further information.
The FRAME_ECC_VIRTEX4 logic does not repair changed bits; this requires a user design.
The design must be able to store at least one frame of data, or be able to fetch original
frames of data for reload. A single frame is 1,312 bits. Following is an example of a simple
repair implementation:
1.A frame is read out through ICAP and stored in block RAM. The frame address must
be generated as each frame is read.
2.If an error is indicated by the error output of the FRAME_ECC block, then the readback
is halted and the syndrome value saved. If bit 11 is 0, then the whole frame must be
restored. If bit 11 is 1, then bits 10:0 are used to locate the error bit in the saved frame,
and the bit inverted.
3.The repaired frame is then written back into the frame address generated in step 1.
4.Readback then begins again with the next frame address.
The syndrome bits S[10:0] are derived from the Hamming parity bits, while S[11] is derived
from the overall parity bit. The syndrome bit is interpreted as follows:
S[11]
= 0, S[10:0] = 0: no error.
S[11]
patch (indirectly).
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= 1, S[10:0] ≠ 0: single bit (SED) error; S[10:0] denotes location of bit to
Chapter 4:Frame ECC Logic
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S[11] = 1, S[10:0] = 0: single-bit error; overall parity bit p[11] is in error.
S[11]
= 0, S[10:0] ≠ 0: double-bit error, not correctable.
In case of a single-bi t error in the frame data, the s yndrome bits S[10:0] points t o the flipped
bit in the address space from 704 (location of the first bit in the frame) to 2047 (last bit in the
frame). To convert the syndrome value S[10:0] to the index of the flipped bit in the range 0
to 1311, subtract 704 decimal (2C0 hexadecimal or 01011000000 binary) if the syndrome
is less than 1,024 decimal; otherwise, subtract 736 decimal (2E0 hexadecimal or
01011100000 binary). This is equivalent to subtracting 22 or 23 decimal from S[10:5], and
can be calculated as bit_index = {S[10:5] –6'd22-S[10],S[5:0]}.
If S[10:0] is 0 or a power of 2, however, an error in a parity bit has occurred. The Hamming
parity bits are stored in locations 640-651. If bit S[11] indicates a single-bit error, then (in the
case of a Hamming code parity bit error) a 1 is presented in the appropriate power-of-2 bit
position, with the other syndrome bits set to 0:
100000000001 -> 640
100000000010 -> 641
100000000100 -> 642
100000001000 -> 643
100000010000 -> 644
100000100000 -> 645
100001000000 -> 646
100010000000 -> 647
100100000000 -> 648
101000000000 -> 649
110000000000 -> 650
100000000000 -> 651
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User Access Register
Using the User Access Register
The User Access Register (USR_ACCESS_VIRTEX4) is a 32-bit register that allows data
from the bitstream to be directly accessible by the FPGA fabric. The register has two
outputs: the 32-bit DATA bus and a data_valid signal that is asserted for one cycle of the
configuration-data source clock whenever a new value is available. The configuration-data
source clock can be CCLK or TCK.
The UAR allows data from a bitstream data storage source (e.g., PROM) to be accessed by
the fabric after the FPGA has been configured. To accomplish this, the STARTUP_VIRTEX4
block should also be instantiated.
The STARTUP_VIRTEX4 block has inputs that allow the user to take control of the CCLK
and DONE pins after the EOS (End-Of-Startup) signal has been asserted. These pins are
USR_CCLK_O, USR_CCLK_TS, USR_DONE_O, and USR_DONE_TS. The BitGen option
-g DONE_cycle:KEEP should be used to prevent the DONE pin from going High,
because that can reset or disable the configuration storage source. The USR_CCLK_O pin
should be connected to a controlled clock in the fabric. The configuration device should
contain data with the USR_ACCESS register as the target. After EOS has been asserted, the
data can be loaded by clocking the USR_CCLK_O pin while keeping USR_CCLK_TS Low
(it can be tied Low in this usage).
Chapter 5
The DATAVALID output indicates that a word is available on the data output port.
DATAVALID goes High for one CCLK cycle after the register is updated. A write to the
User Bitstream Access Register (AXSS) after configuration is required. Similar to other
configuration registers, the AXSS register can be accessed through the configuration
interface (e.g., JTAG, SelectMap, ICAP).
The USR_ACCESS register can be used to provide a single 32-bit constant value to the
fabric as an alternative to using a block RAM or LUTRAM to hold the constant.
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Reconfiguration Techniques
Dynamic Reconfiguration of Functional Blocks (DRP)
Background
In the Virtex® family of FPGAs, the Configuration Memory is used primarily to implement
user logic, connectivity and I/Os, but it is also used for other purposes. For example, it is
used to specify a variety of static conditions in functional blocks, such as Digital Clock
Managers (DCMs) and RocketIO™ Multi-Gigabit Transceivers (MGTs).
Sometimes an application requires a change in these conditions in the functional blocks
while the block is operational. This can be accomplished through the global Internal
Configuration Access Port (ICAP), or through partial dynamic reconfiguration using JTAG
or SelectMAP in the Persist mode. However, the reconfiguration port that is an integral
part of each functional block simplifies this process greatly. Such configuration ports exist
in the DCMs and RocketIO MGTs.
Chapter 6
Overview
This document describes the addressable, parallel write/read configuration memory that
is implemented in each functional block that might require reconfiguration. This memory
has the following attributes:
•It is directly accessible from the FPGA fabric. Configuration bits can be written to
and/or read from depending on their function.
•Each bit of memory is initialized with the value of the corresponding configuration
memory bit in the bitstream. Memory bits can also be changed later through the ICAP.
•The output of each memory bit drives the functional block logic, so the content of this
memory determines the configuration of the functional block.
The address space can include status (read-only) and function enables (write-only). Note
that read-only and write-only operations can share the same address space. Figure 6-1
shows how the configuration bits drive the logic in functional blocks directly in earlier
FPGA families, and Figure 6-2 shows how the reconfiguration logic changes the flow to
read or write the configuration bits.
All configuration bits
for this block
Configuration LogicFunctional Block (DCM or MGT)
Figure 6-1: Block Configuration Logic without Dynamic Interface
to block logic
ds071_46_071505
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Chapter 6:Reconfiguration Techniques
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CONTROLLER
Block Status
(Read-Only Ports)
Function Enables
(Write-Only Ports)
Reconfigurable Bits
All configuration bits
for this block
Non-reconfigurable Bits
to block logic
to block logic
Standard
Reconfiguration
Port (to fabric)
Configuration LogicFunctional Block (DCM or MGT)
Logic Plane
ds071_42_071705
CONTROLLER
Block Status
(Read-Only Ports)
Function Enables
(Write-Only Ports)
Reconfigurable Bits
All configuration bits
for this block
Non-reconfigurable Bits
to block logic
to block logic
Standard
Reconfiguration
Port (to fabric)
Configuration LogicFunctional Block (DCM or MGT)
Logic Plane
ds071_43_071705
DCLK
DRDY
DEN
DWE
DADDR[m:0]
DI[n:0]
DO[n:0]
Figure 6-2: Block Configuration Logic with Dynamic Interface
Figure 6-3 is the same as Figure 6-2, except the port between the Logic Plane and
Functional Block is expanded to show the actual signal names and directions.
FPGA Fabric Port Definition
Table 6-1, page 82, lists each signal on the FPGA Fabric port. The individual functional
blocks can implement all or only a subset of these signals. The DCM chapter in the
Virtex-4 FPGA User Guide and the Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide
shows the signals and functions implemented for the specific blocks. In general, the port is
a synchronous parallel memory port, with separate read and write buses similar to the
block RAM interface. Bus bits are numbered least-significant to most-significant, starting
at 0. All signals are active High.
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Figure 6-3:Block Configuration Logic Expanded to Show Signal Names
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bb
BB
DCLK
DEN
DRDY
DWE
DADDR[m:0]
DI[n:0]
DO[n:0]
ds071_44_123003
aa
AA
DCLK
DEN
DRDY
DWE
DADDR[m:0]
DI[n:0]
DO[n:0]
ds071_45_031804
Synchronous timing for the port is provided by the DCLK input, and all the other input
signals are registered in the functional block on the rising edge of DCLK. Input (write) data
is presented simultaneously with the write address and DWE and DEN signals prior to the
next positive edge of DCLK. The port asserts DRDY for one clock cycle when it is ready to
accept more data. The timing requirements relative to DCLK for all the other signals are the
same. The output data is not registered in the functional blocks. Output (read) data is
available after some cycles following the cycle that DEN and DADDR are asserted. The
availability of output data is indicated by the assertion of DRDY.
Figure 6-4 and Figure 6-5 show the timing relationships between the port signals for write
and read operations. Absolute timing parameters, such as maximum DCLK frequency,
setup time, etc., are defined in the Virtex-4 FPGA Data Sheet.
Figure 6-4: Write Timing with Wait States
Figure 6-5:Read Timing with Wait States
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Table 6-1:Port Signal Definitions
Signal NameDirection
DCLKInput
DENInput
(1)
Description
The rising edge of this signal is the timing reference for
all the other port signals. The required hold time for the
other input signals relative to the rising edge of DCLK
is zero (maximum). Normally, DCLK is driven with a
global clock buffer.
This signal enables all port operations. If DWE is
FALSE, it is a read operation, otherwise a write
operation. For any given DCLK cycle, all other input
signals are don't care if DEN is not active.
DWEInput
When active, this signal enables a write operation to the
port (see DEN, above).
The value on this bus specifies the individual cell that is
DADDR[m:0]Input
written or read on the next cycle of DCLK. The address
is presented in the cycle that DEN is active.
The value on this bus is the data that is written to the
addressed cell. The data is presented in the cycle that
DI[n:0]Input
DEN and DWE are active, and is captured in a register
at the end of that cycle, but the actual write occurs at an
unspecified time before DRDY is returned.
If DWE was inactive when DEN was activated, the
DO[n:0]Output
value on this bus when DRDY goes active is the data
read from the addressed cell. At all other times, the
value on DO[n:0] is undefined.
This signal is a response to DEN to indicate that the DRP
cycle is complete and another DRP cycle can be
initiated. In the case of a port read, the DO bus must be
DRDYOutput
captured on the rising edge of DCLK in the cycle that
DRDY is active. The earliest that DEN can go active to
start the next port cycle is the same clock cycle that
DRDY is active.
Notes:
1. Input denotes input (write) to the DRP.
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DRP DCM Implementation
The DRP implementation allows dynamic adjustment of M, D, and PS values (dire ct mode)
in the DCM. The following ports are available in DCM_ADV primitive (see Chapter 2 of
the Virtex-4 FPGA User Guide):
Inputs:
DI[15:0]
DADDR[6:0]
DWE
DEN
DCLK
Outputs:
DO[15:0]
DRDY
DADDR[6:0] is latched at DCLK rising edge while DEN is asserted. The DO output reflects
the status of that latched address location. After reset, the internal address is reset to 0, and
the DCM DRP DO outputs are used to signal the default status Phase Shift Overflow,
CLKIN Stopped, CLKFX Stopped, and CLKFB Stopped. However, if the DRP is used to
reprogram M, D, or PS value, the DO is no longer showing default status. To access default
status, the user must perform a DRP read with DADDR[6:0] = 0.
Dynamic Reconfiguration of Functional Blocks (DRP)
Changing the Multiply and Divide Values
The Multiply and Divide (M/D) values can be directly programmed in the DCM through
the DRP by writing to hex addresses 50h and 52h respectively. The five least-significant
data bits represent the multiply-minus-1 and divide-minus-1 values, as shown in Table 6-2
and Table 6-3. DRDY indicates that the new value has been written successfully.
The DCM must be held in reset by activating input RST while changing the M/D values.
At some point after RST is released, signal LOCKED goes true, indicating that the clock
outputs of the DCM are valid.
Table 6-2:Multiplier Settings
DADDR[15:0] DECDI[15:0]Function
50h00000000h (0000000000000000)N/A
50h00010001h (0000000000000001)Multiply by 2
50h00020002h (0000000000000010)Multiply by 3
50h00030003h (0000000000000011)Multiply by 4
50h00040004h (0000000000000100)Multiply by 5
•
•
•
•
•
•
50h0030001Eh (0000000000011110)Multiply by 31
•
•
•
•
•
•
50h0031001Fh (0000000000011111)Multiply by 32
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Table 6-3:Divider Settings
DADDR[15:0] DECDI[15:0]Function
52h00000000h (0000000000000000)N/A
52h00010001h (0000000000000001)Divide by 2
52h00020002h (0000000000000010)Divide by 3
52h00030003h (0000000000000011)Divide by 4
52h00040004h (0000000000000100)Divide by 5
•
•
•
•
•
•
•
•
•
52h0030001Eh (0000000000011110)Divide by 31
52h0031001Fh (0000000000011111)Divide by 32
If the M or D values are dynamically charged, then in some cases, the frequency mode
must also be charged to comply with the specifications in the data sheet. For the
DFS_FREQUENCY_MODE DRP address, 41h must be read and bit 6 (DI[5]) is then set to:
•0 for low frequency mode
•1 for high frequency mode
All other bits must remain unchanged.
For the DLL_FREQUENCY_MODE DRP address, 58h must be read and bits 7 and 8
(DI[7:6) are then set to:
•0 for low frequency mode
•1 for high frequency mode
Again, all other bits must be left undisturbed.
Dynamic Phase Shifting Through the DRP in Direct Mode
In addition to the phase shift modes already available in Virtex-II and Virtex-II Pro devices,
the Virtex-4 FPGA has implemented a Direct Phase Shift Mode (DPSM). This allows the
user to control the phase-shift delay line elements (tabs) directly. The DPSM can be
accessed through either the standard Phase Shift (PS) interface or the DRP. If the DCM
attribute CLKOUT_PHASE_SHIFT is set to DIRECT, then the PS interface is in direct mode
and controls individual taps. The initial tap value is 0 delay line elements. All four PS
interface signals act identically to the legacy-phase shift mode, thus allowing increment or
decrement of the tabs. The delay line element is inserted at the CLKIN path. CLKIN leads
CLKFB mode when more delay line elements are inserted until the delay elements are
equal to one clock period, at which time the dynamic phase starts over again.
•
•
•
If DLL_PHASE_SHIFT_LOCK_BY1 = 1, each increment/decrement changes one tab. If 0,
each increment/decrement changes eight tabs.
The DRP interface allows to the user to directly set an initial phase-shift value to a specified
number of taps. After RESET, the phase-shift delay line has no elements inserted. A value
between 0 and 3FFh (0-1023 taps) can be written to the DRP, then setting the tap target
value in the DCM. A write to a specific address of the DRP then initiates the adjustment
cycles necessary to set the proper delay value in the DPS. The DCM requires fewer clock
cycles to achieve the final value than in the other modes, where a phase shift is expressed
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as a percentage of the clock. Just as in legacy mode, PSDONE indicates completion of the
phase shift. If DLL_PHASE_SHIFT_LOCK_BY1 = 0, then the lower three bits of phase shift
value are ignored, because it works on eight tabs as a unit.
Phase shift overflow does not toggle in the Direct Mode if the end of the delay line is
reached.
It is recommended that the same clock be used for DCLK and PSCLK. Although the
PSDONE pin is a function of the PSCLK domain, the data written to the DRP is in the
DCLK domain. If this cannot be done, then the following two scenarios should be
considered:
1.Connect DCLK, but not PSCLK. PSDONE is not asserted. The phase shift value is
executed, although there is no indication when it is completed.
2.Connect PSCLK and DCLK to different sources. PSDONE is in the PSCLK domain
and can be asynchronous to DCLK.
Setting a direct phase shift value:
1.If the CLKOUT_PHASE_SHIFT was not set to DIRECT, then write 00Dh (DI) to
DADDR address 56h. (DRP should not be used to change configuration memory other
than phase shift value.)
2.Write the desired tab value 0-3FFh (DI) (0-1023 tabs) to DADDR 55h.
3.Write to DADDR 11h to start the phase shift. (Data on DI does not matter.)
4.PSDONE asserts for one PSCLK cycle to indicate that the phase shift is done.
ICAP - Internal Configuration Access Port
The Internal Configuration Access Port (ICAP) allows access to configuration data in the
same manner as SelectMAP. ICAP has the same interface signaling as SelectMAP other
than the data bus, which is separated into read and write data buses. ICAP has a chipselect signal (CS), a read-write control signal (RD), a clock (CLK), a write data bus (DIN),
and a read data bus (OUT). ICAP can be configured to two different data bus widths, 8 bits
or 32 bits. When the 8-bit ICAP interface is used, the data is byte-reversed like SelectMAP.
When the 32-bit interface is used, the data is not reversed,which is the same as
SelectMAP32.
The ICAP interface can be used to perform readback operations or partial reconfiguration.
When using ICAP for partial reconfiguration, the user must avoid changing the logic or
interconnect which the ICAP is itself connected to. ICAP can also be used to read or write
to the configuration registers, such as the STAT, CTL, or FAR registers. See “Accessing
Configuration Registers through the SelectMAP Interface” for details.
There are two ICAP sites in Virtex-4 devices: TOP and BOTTOM. The implementation has
the two interfaces share the same underlying logic. The only difference between them is
their location on the chip and the interconnect to which they can be connected. The two
interfaces can never be active at the same time. The default site for a single ICAP is the TOP
site, because the TOP site is active after configuration by default. If both sites are used, the
TOP site must be activated first before switching to the BOTTOM site. The process of
switching between the two sites is as follows:
1.Synchronize the current interface (if it's not already synched).
2.Write bit 30 of the MASK register with a 1.
3.Write bit 30 of the CTL register with a 1 if switching to the BOTTOM site or a 0 if
switching to the TOP site.
4.Write the DESYNCH command to the CMD register.
5.Synchronize the new ICAP site.
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Configuration Details
All user-programmable features inside Virtex®-4 devices are controlled by volatile
memory cells that must be configured at power-up.
These memory cells are collectively known as configuration memory. They define the LUT
equations, signal routing, IOB voltage standards, and all other aspects of the user design.
To program configuration memory, instructions for the configuration control logic and
data for the configuration memory are provided in the form of a bitstream. The bitstream
is delivered to the device through one of the configuration interfaces (JTAG, SelectMAP, or
Slave/Master Serial).
The composition of the bitstream is largely independent of the configuration method.
Certain operations, however, such as readback, can only be performed through the
SelectMAP and JTAG interfaces.
Chapter 7
Configuration Memory Frames
Virtex-4 configuration memory is arranged in frames that are tiled about the device. These
frames are the smallest addressable segments of the Virtex-4 configuration memory space,
and all operations must therefore act upon whole configuration frames. Virtex-4 frame
counts and configuration sizes are shown in Table 7-1. Depending on BitGen options,
additional overhead exists in the configuration bitstream. The exact bitstream length is
available in the .rbt (rawbits) file created by using the "-b" option with bitgen or selecting
"Create ASCII Configuration File" in the Generate Programming File options popup in
ISE® software. Bitstream length (words) are roughly equal to the configuration array size
(words) plus configuration overhead (words). Bitstream length (bits) are roughly equal to
the bitstream length in words times 32.
Table 7-1:Virtex-4 Frame Count, Frame Length, Overhead and Bitstream Size
Device
XC4VLX151403,6003,74041147,6001312
XC4VLX252345,9286,16241243,0481312
XC4VLX403769,3129,68841381,7921312
XC4VLX6053613,47214,00841552,3521312
XC4VLX8071017,72018,43041726,5201312
XC4VLX10094823,37624,32441958,4161312
XC4VLX1601,26030,72029,460411,259,5201312
XC4VLX2001,62039,12037,500411,603,9201312
Non-Configuration
Frames
(1)
Configuration
Frames
(2)
Device
Frames
Frame Length
(3)
(words)
(4)
Configuration
Array Size
(words)
(5)
Configuration
Overhead
(words)
(6)
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1. Non-configuration frames should be considered when calculating TPL (Program Latency) but do not contribute to the bitstream size.
See Table 41: Configuration Switching Characteristics in the Virtex-4 FPGA Data Sheet.
2. Configuration frames contribute to both the T
3. The number of device frames equals the number of non-configuration plus configuration frames, and is the number of frames to use
when calculating T
4. All Virtex-4 configuration frames consist of 41 32-bit words.
5. Configuration array size equals the number of configuration frames times the number of words per frame.
6. Configuration overhead consists of commands in the bitstream that are needed to perform configuration, but do not themselves
program any memory cells. Configuration overhead contributes to the overall bitstream size.
Non-Configuration
Frames
PL
(1)
.
Configuration
Frames
(2)
calculation and the overall bitstream size.
PL
Device
Frames
Frame Length
(3)
(words)
(4)
Configuration
Array Size
(words)
(5)
Configuration
Overhead
(words)
(6)
Configuration Control Logic
The Virtex-4 configuration logic consists of a packet processor, a set of registers, and global
signals that are controlled by the configuration registers. The packet processor controls the
flow of data from the configuration interface (SelectMAP, JTAG, or Serial) to the
appropriate register. The registers control all other aspects of configuration.
Packet Types
The FPGA bitstream consists of two packet types: Type 1 and Type 2. These packet types
and their usage are described below.
Type 1 Packet
The Type 1 packet is used for register reads and writes. Only 5 out of 14 register address
bits are used in Virtex-4 FPGAs. The header section is always a 32-bit word.
Following the Type 1 packet header is the Type 1 Data section, which contains the number
of 32-bit words specified by the word count portion of the header. See Table 7-2 and
Table 7-3.
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Table 7-2:Type 1 Packet Header Format
Configuration Control Logic
Header
Type
OpcodeRegister AddressReservedWord Count
[31:29][28:27] [26:13] [12:11][10:0]
001xxRRRRRRRRRxxxxxRRxxxxxxxxxxx
Notes:
1. "R" means the bit is not used and reserved for future use.
Table 7-3:Opcode Format
OpcodeFunction
00
NOP
01Read
10Write
11Reserved
Type 2 Packet
The Type 2 packet, which must follow a Type 1 packet, is used to write long blocks. No
address is presented here because it uses the previous Type 1 packet address. The header
section is always a 32-bit word.
Following the Type 2 packet header is the Type 2 Data section, which contains the number
of 32-bit words specified by the word count portion of the header. See Table 7-4.
Table 7-4:Type 2 Packet Header
Header
Type
OpcodeWord Count
[31:29][28:27][26:0]
010RRxxxxxxxxxxxxxxxxxxxxxxxxxx
Configuration Registers
All bitstream commands are executed by reading or writing to the configuration registers.
Table 7-5 summarizes these registers. A detailed explanation of selected registers follows.
Table 7-5:Configuration Registers
Reg. NameRead/Write AddressDescription
CRC
FAR
FDRI
FDRO
CMD
CTL
Read/Write00000
Read/Write00001
Read/Write00100
Read/Write00101
Write00010
Read00011
CRC register
Frame Address Register
Frame Data Register, Input (write configuration data)
Frame Data Register, Output register (read
configuration data)
Command Register
Control Register
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Table 7-5:Configuration Registers (Continued)
Reg. NameRead/Write AddressDescription
MASK
STAT
LOUT
COR
MFWR
CBC
IDCODE
AXSS
Read/Write00110
Read00111
Write01000
Read/Write01001
Write01010
Write01011
Read/Write01100
Read/Write01101
Masking Register for CTL
Status Register
Legacy Output Register (DOUT for daisy chain)
Configuration Option Register
Multiple Frame Write
Initial CBC value register
Device ID register
User bitstream access register
Command Register (CMD)
The Command Register is used to instruct the configuration control logic to strobe global
signals and perform other configuration functions. The command present in the CMD
register is executed each time the FAR is loaded with a new value. Table 7-6 gives the
Command Register commands and codes.
Table 7-6:Command Register Codes
CommandCodeDescription
NULL
WCFG
MFWR
LFRM
RCFG
START
RCAP
RCRC
0000
0001
0010
0011
0100
0101
0110
0111
Null Command
Write Configuration Data: used prior to writing configuration data to
the FDRI.
Multiple Frame Write: used to perform a write of a single frame data to
multiple frame addresses.
Last Frame: Deasserts the GHIGH_B signal, activating all interconnect.
The GHIGH_B signal is asserted with the AGHIGH command.
Read Configuration Data: used prior to reading configuration data
from the FDRO.
Begin Startup Sequence: initiates the startup sequence. The startup
sequence begins after a successful CRC check and a DESYNC
command are performed.
Reset Capture: resets the CAPTURE signal after performing readbackcapture in single-shot mode (see “Readback Capture,” page 113).
Reset CRC: resets the CRC register
Assert GHIGH_B Signal: places all interconnect in a high-Z state to
AGHIGH
SWITCH
GRESTORE
SHUTDOWN
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1000
1001
1010
1011
prevent contention when writing new configuration data. This
command is only used in shutdown reconfiguration. Interconnect is
reactivated with the LFRM command.
Switch CCLK Frequency: updates the frequency of the Master CCLK to
the value specified by the OFSEL bits in the COR.
Pulse the GRESTORE Signal: sets/resets (depending on user
configuration) IOB and CLB flip-flops.
Begin Shutdown Sequence: initiates the shutdown sequence, disabling
the device when finished. Shutdown activates on the next successful
CRC check or RCRC instruction (typically an RCRC instruction).
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Table 7-6:Command Register Codes (Continued)
CommandCodeDescription
Configuration Control Logic
GCAPTURE
DESYNC
Control Register (CTL)
The Control Register is used to set the configuration security level, the persist setting, and
to toggle the Global Three-State signal. Writes to the CTL register are masked by the value
in the MASK register (this allows the GTS_USR_B signal to be toggled without respecifying the Security and Persist bits). The default value of the GLUTMASK_B bit in the
CTL register is 1, which leads to corruption of SRL16 and distributed RAM (LUTRAM)
during active readback of the device. Active readback is defined as readback that occurs
while the device is not in the shutdown state. To prevent corruption of SRL16 and
distributed RAM during active readback, the user must set the GLUTMASK_B bit to 0.
This is accomplished by writing a 1 to bit 8 of the MASK register followed by writing a 0 to
bit 8 of the CTL register. The MASK register is cleared after each write to the CTL register,
which prevents inadvertent changes to the Control Register.
The fields are illustrated in Figure 7-1 and defined in Table 7-7.
Reserved
ICAP SEL
1100
1101
Pulse GCAPTURE: loads the capture cells with the current register
states (see “Readback Capture,” page 113).
Reset DALIGN Signal: used at the end of configuration to
desynchronize the device. After de-synchronization, all values on the
configuration data pins are ignored.
Figure 7-1: Control Register
Reserved
GLUTMASK_B
Reserved
SBITS
PERSIST
Reserved
GTS_USR_B
Description
Bit Index
Value0000000000000000x xxxxx xxxx xxxxx x
3130292827262524232221201918171615141312111
9 8 76543 210
0
Table 7-7:Control Register Description
NameBit IndexDescription
Reserved
ICAP_SEL
SBITS
VariousReserved CTL register bits. Always leave these bits set to 0.
ICAP Port Select.
30
5:4
0:Top ICAP Port Enabled (default)
1:Bottom ICAP Port Enabled
The configuration interface defined by M2:M0 remains after
configuration. Typically used only with the SelectMAP
3
8
0
interface to allow reconfiguration and readback. See also
“SelectMAP Reconfiguration” in Chapter 2.
0:No (default)
1:Yes
GLUTMASK affects how certain memory cells are read back.
This applies to SRL16 and distributed RAM (LUTRAM) bits
as well as configuration bits that are accessible through a
DRP port.
0=Readback all 0s from SRL16 and Distributed RAM. Use
with active device readback.
1=Readback dynamic values from SFR16 and Distributed
RAM. Use with shutdown readback.
Active Low high-Z state for I/Os.
0:I/Os placed in high-Z state
1:I/Os active
Frame Address Register (FAR)
The Virtex-4 devices are divided into two halves, the top, and the bottom. Frames in the
bottom half mirror images in the top half with the exception of the vertical HCLK rows that
contain the global and regional clocks. The HCLK title bits are in the same order in the both
of the top and bottom frames.
All Frames in Virtex-4 have a fixed, identical length of 1312 bits (41 32-bit words). One
Frame configures one HCLK with either 4 block RAMS, 32 IOBs or 4 DSPs.
The FAR is divided into five fields: top/bottom bit, block type, row address, column
address, and minor address. The address can be written directly or can be autoincremented at the end of each frame. The typical bitstream starts at address 0 and autoincrement to the final count.
Table 7-8:Frame Address Register Description
Address TypeBit IndexDescription
Top_B Bit22Select between top-half rows and bottom-half rows.
(001), block RAM content (010), CFG_CLB (011), and
CFG_BRAM (100). A normal bitstream stops at type 010.
Row Address18:14Selects a row of frames, for example, a row of 16 CLBs in height,
with an HCLK row in the middle. The row addresses increase
away from the middle (in both top and bottom).
Column Address13:6Selects a major column, such as a column of CLBs. Column
addresses start at 0 on the left and increase to the right.
Minor Address5:0Selects a memory-cell address line within a major column.
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Status Register (STAT)
The Status Register indicates the value of numerous global signals. The register can be read
through the SelectMAP or JTAG interfaces. Figure 7-2 gives the name of each bit position in
the STAT register; a detailed explanation of each bit position is given in Table 7-9.
Figure 7-2:Status Register
Reserved
DEC_ERROR
ID_ERROR
DONE
RELEASE_DONE
INIT
INIT_COMPLETE
MODE
GHIGH_B
GWE
GTS_CFG_B
EOS
DCI_MATCH
DCM_LOCK
PART_SECURED
CRC_ERROR
Description
Bit Index
Value0000000000000000x xxxxx xxxx xxxxx x
3130292827262524232221201918171615141312111
–
9 8 76543 210
0
Table 7-9: Status Register Description
NameBit IndexDescription
FDRI write attempted before or after decrypt operation.
DEC_ERROR
ID_ERROR
DONE
RELEASE_DONE
INIT
INIT_COMPLETE
16
15
14Value on DONE pin.
13
12Value on INIT pin
11
0:No DEC_ERROR
1:DEC_ERROR
Attempt to write to FDRI without successful DEVICE_ID
check.
0:No ID_ERROR
1:ID_ERROR
Value of internal DONE signal.
0:DONE signal not released (pin is actively held Low)
1:DONE signal released (can be held Low externally)
Internal signal indicating initialization has completed.
0:Initialization has not finished
1:Initialization finished
MODE
GHIGH_B
GWE
GTS_CFG_B
EOS
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10:8Status of the MODE pins (M2:M0).
Status of GHIGH_B.
7
6
5
4
0:GHIGH_B asserted
1:GHIGH_B deasserted
Status of GWE.
0:FFs and block RAM are write disabled
1:FFs and block RAM are write enabled
Status of GTS_CFG_B.
0:All I/Os are placed in high-Z state
1:All I/Os behave as configured
End of Startup signal from Startup Block.
0:Startup sequence has not finished
1:Startup sequence has finished
Chapter 7:Configuration Details
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Table 7-9: Status Register Description (Continued)
NameBit IndexDescription
DCI_MATCH
DCM_LOCK
0:DCI not matched
1:DCI is matched
3
2
This is a logical AND function of all the MATCH signals (one
per bank). If no DCI I/Os are in a particular bank, the bank's
MATCH signal = 1.
0:DCMs not locked
1:DCMs are locked
This is a logical AND function of all DCM LOCKED signals.
Unused DCM LOCKED signals = 1.
PART_SECURED
CRC_ERROR
1
0
0:Decryptor security not set
1:Decryptor security set
0:No CRC error
1:CRC error
Configuration Options Register (COR)
The Configuration Options Register is used to set certain configuration options for the
device. The name of each bit position in the COR is given in Figure 7-3 and described in
Configuration can begin after the device is powered and initialization has finished, as
indicated by the INIT pin being released. After initialization, the packet processor ignores
all data presented on the configuration interface until it receives the synchronization word.
After synchronization, the packet processor waits for a valid packet header to begin the
configuration process.
Default Initial Configuration Process
Initial configuration using a default bitstream (a bitstream generated using the default
BitGen settings) begins by pulsing the PROGRAM_B pin for SelectMAP and Serial
configuration modes or by issuing the JPROG_B instruction for JTAG configuration mode.
Configuration proceeds as shown in Table 7-11:
Table 7-11: Configuration Sequence
Configuration
Data (hex)
FFFFFFFFDummy word
AA995566Sync word
30008001Type 1 write 1 words to CMD
00000007RCRC command
20000000
20000000
Explanation
NO-OP
30012001Type 1 write 1 words to COR
XXXXXXXXData word 0
30018001Type 1 write 1 words to ID
0167C093Device_ID
30008001Type 1 write 1 words to CMD
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Table 7-11: Configuration Sequence (Continued)
Configuration
Data (hex)
Explanation
00000009SWITCH command
20000000NO-OP
30008001Type 1 write 1 words to CMD
00000000NULL command
20000000NO-OP
3000C001Type 1 write 1 words to MASK
XXXXXXXXData word 0
3000A001Type 1 write 1 words to CTL
XXXXXXXXData word 0
20000000NO-OP
...1149 more NO-OPs
3000C001Type 1 write 1 words to MASK
XXXXXXXXData word 0
3000A001Type 1 write 1 words to CTL
XXXXXXXXData word 0
30002001Type 1 write 1 words to FAR
00000000Data word 0
30008001Type 1 write 1 words to CMD
00000001WCFG command
30004000Type 1 write 0 words to FDRI
5003B568Type 2 write 243048 words to FDRI
XXXXXXXXData word 0
......
XXXXXXXXData word 243047
30000001Type 1 write 1 words to CRC
XXXXXXXXData word 0
30008001Type 1 write 1 words to CMD
0000000AGRESTORE command
20000000NO-OP
30008001Type 1 write 1 words to CMD
00000003LFRM command
20000000NO-OP
...99 more NO-Ops
30008001Type 1 write 1 words to CMD
0000000AGRESTORE command
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Chapter 7:Configuration Details
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Table 7-11: Configuration Sequence (Continued)
Configuration
Data (hex)
Explanation
20000000NO-OP
30008001Type 1 write 1 words to CMD
00000000NULL command
20000000NO-OP
30002001Type 1 write 1 words to FAR
00000000Data word 0
30008001Type 1 write 1 words to CMD
00000005START command
20000000NO-OP
3000C001Type 1 write 1 words to MASK
XXXXXXXXData word 0
3000A001Type 1 write 1 words to CTL
XXXXXXXXData word 0
30000001Type 1 write 1 words to CRC
XXXXXXXXData word 0
30008001Type 1 write 1 words to CMD
0000000DDESYNC command
20000000
20000000
20000000
20000000
20000000
20000000
20000000
20000000
Type 1 NO OP
20000000
20000000
20000000
20000000
20000000
20000000
20000000
20000000
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Chapter 8
Readback and Configuration Verification
Virtex®-4 devices allow users to read configuration memory through the SelectMAP or
JTAG interface. There are two styles of readback: Readback Verify and Readback Capture.
During Readback Verify, the user reads all configuration memory cells, including the
current values on all user memory elements (LUT RAM, SRL16, and block RAM).
Readback Capture is a superset of Readback Verify—in addition to reading all
configuration memory cells, the current state of all internal CLB and IOB registers is read,
and is useful for design debugging.
Note:
Xilinx does not support or recommend using configuration memory readback in flight applications.
The Correcting Single-Event Upsets in Virtex-4 FPGA Configuration Memory application note
(XAPP1088) describes the recommended solution to correct single event upsets (SEUs) for
Virtex-4QV FPGAs in flight. This application note is available on the High Reliability and Space
Developers’ Site.
To read configuration memory, users must send a sequence of commands to the device to
initiate the readback procedure; once initiated the device dumps the contents of its
configuration memory to the SelectMAP or JTAG interface. The configuration memory
read procedure sections for SelectMAP, IEEE 1149.1 JTAG, and IEEE 1532 JTAG describe
the steps for reading configuration memory
Users can send the readback command sequence from a custom microprocessor, CPLD, or
FPGA-based system, or use iMPACT to perform JTAG-based readback verify. iMPACT, the
device programming software provided with the ISE® tools, can perform all readback and
comparison functions for Virtex-4 devices and report to the user whether there were any
configuration errors. iMPACT cannot perform capture operations, although Readback
Capture is seldom used for design debugging because the Chipscope™ Integrated Logic
Analyzer (ILA), sold separately through the Xilinx website, provides superior design
debugging functionality in a user-friendly interface.
Once configuration memory has been read from the device, the next step is to determine if
there are any errors by comparing the readback bitstream to the configuration bitstream.
The “Verifying Readback Data” section explains how this is done.
Virtex-4QV device configuration memory readback is only supported during design debug.
Preparing a Design for Readback
There are two mandatory bitstream settings for readback: the BitGen security setting must
not prohibit readback (-g security:none), and bitstream encryption must not be used.
Additionally, if readback is to be performed through the SelectMAP interface, the port
must be set to retain its function after configuration by setting the persist option in BitGen
(-g Persist:Yes), otherwise the SelectMAP data pins revert to user I/O, precluding
further configuration operations. Beyond these security and encryption requirements, no
special considerations are necessary to enable readback through the Boundary-Scan port.
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Chapter 8:Readback and Configuration Verification
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CS_B
RDWR_B
DATA[0:7]
UG071_48_090704
WRITE
Byte
n
Byte
n
Byte 0
CCLK
Byte 0
READ
If capture functionality is needed, the CAPTURE_VIRTEX4 primitive can instantiated in
the user design (Figure 8-7, page 113). Alternatively, writing the GCAPTURE command to
the CMD register can be used (see Readback Capture). To capture the state of user
registers, the user design triggers the CAP input on this primitive, storing the current
register values in configuration memory. The register values are later read out of the device
along with all other configuration memory.
Readback Command Sequences
Virtex-4 configuration memory is read from the FDRO (Frame Data Register - Output)
configuration register and can be accessed from the JTAG and SelectMAP interfaces.
Readback is possible while the FPGA design is active or in a shutdown state, although
block RAMs cannot be accessed by the user design while they are being accessed by the
configuration logic.
Accessing Configuration Registers through the SelectMAP Interface
To read configuration memory through the SelectMAP interface, users must set the
interface for write control to send commands to the FPGA, and then switch the interface to
read control to read data from the device. Write and read control for the SelectMAP
interface is determined by the RDWR_B input: the SelectMAP data pins (D0:7) are inputs
when the interface is set for Write control (RDWR_B = 0); they are outputs when the
interface is set for Read control (RDWR_B = 1).
The CS_B signal must be deasserted (CS_B =1) before toggling the RDWR_B signal,
otherwise the user causes an abort (refer to “SelectMAP ABORT” in Chapter 2 for details).
The procedure for changing the SelectMAP interface from Write to Read Control, or vice
versa, is:
1.Deassert CS_B.
2.Toggle RDWR_B.
RDWR_B = 0: Write control
RDWR_B = 1: Read control
3.Assert CS_B.
4.This procedure is illustrated in Figure 8-1.
Figure 8-1:Changing the SelectMAP Port from Write to Read Control
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