Xilinx Virtex-4 FPGA Configuration User Manual
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Virtex-4 FPGA
Configuration
User Guide
UG071 (v1.12) June 2, 2017
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Revision History
The following table shows the revision history for this document.
Version Revision
08/02/04 1.0 Initial Xilinx release. Printed Handbook version.
09/10/04 1.1 Chapters 11, 12, and 13 in the printed handbook are now Chapters 1, 2, and 3 in this
guide. Chapter 14 in the printed handbook is now Chapter 6 in this guide. There are now
eight chapters in this guide.
08/08/05 1.2 System Monitor functions are not supported in Virtex-4 devices, removed references.
General typographical edits for correctness and clarity. Edited Table 1-1, Table 1-4,
Figure 1-11, Table 2-4, and Figure 2-11 to add information on Slave SelectMAP32 mode.
Removed the Virtex-4 bitstream length tables in favor of the exact numbers reported in
the ISE BitGen tool. Edited Table 1-3 and removed the Power-Up Timing table to
consolidate data in the Virtex-4 FPGA Data Sheet. Edited Figure 1-11. Removed the
Dynamic Reconfiguration Timing table to consolidate data in the Virtex-4 FPGA
Data Sheet.
08/16/05 1.3 Due to a documentation error, all configuration I/O notations have been changed from
LVTTL to LVCMOS.
Virtex-4 FPGA Configuration User Guide www.xilinx.com UG071 (v1.12) June 2, 2017
Version Revision
01/19/06 1.4 Completed grammatical and style edits for clarity and compliance to Xilinx
documentation standards.
Added preface, not included in previous versions. Corrected Table 1-1, page 13 (Note 2.).
Added “HSWPEN has a weak pull-up prior to and during configuration” to Table 1-2,
page 14. Clarified first paragraph of “Clear Configuration Memory (Step 2,
Initialization),” page 16. Clarified title of Table 1-10, page 22 (status register), to
differentiate from Figure 1-10 (signal sequencing). Added descriptions for GWE, GTS,
EOS, DCI_MATCH, and DCM_LOCK to Table 1-10, page 22. Added “ICAP is not
supported with an encrypted bitstream in the LX, SX, and FX12 devices” as last
paragraph in “Loading the Encryption Key,” page 24 and as last line in first paragraph
in “Bitstream Encryption and Internal Configuration Access Port (ICAP),” page 25.
Added third paragraph to “Loading Encrypted Bitstreams,” page 24. Clarified
SelectMAP Data Pin Description in Table 2-4, page 39. Added port width to “SelectMAP
Reconfiguration,” page 51. Added first paragraph to Chapter 4, “Frame ECC Logic,”
page 75. Updated the BitGen option to DONE_CYCLE:KEEP in Chapter 5, “User Access
Register,” page 77. Added “Frame Address Register (FAR),” page 92. Corrected
Configuration Data in Table 8-2, page 103 (step 4 and step 6). Changed DESYCH to
DESYNC (throughout).
01/12/07 1.5 Updated notes relevant to Figure 2-5. Updated Table 2-4, Table 3-3, and the “Instruction
Register” section. Added the “ICAP - Internal Configuration Access Port” section.
Updated the “Control Register (CTL)” section, Table 7-7, and Figure 8-2.
06/21/07 1.6 Updated “Introduction,”Table 1-2, “Master Serial Configuration,” “SelectMAP Data
Loading,” Chapter 5, “User Access Register,” “Changing the Multiply and Divide
Values,” “Dynamic Phase Shifting Through the DRP in Direct Mode,” Table 7-1, CBC
address value in Table 7-5, “Configuration Memory Read Procedure (SelectMAP),” and
Table 8-2. Added
“Packet Types”section.
07/30/07 1.7 Added TAP controller state definitions in the “TAP Controller” section and a NOOP note
to Table 8-1.
08/08/07 1.8 Replaced instructions for setting a direct phase shift value in the “Dynamic Phase
Shifting Through the DRP in Direct Mode” section.
10/01/07 1.9 Title: Updated corporate disclaimer.
Chapter 2: Updated notes relevant to Figure 2-3 and updated Figure 2-19.
Chapter 3: Updated “TAP Controller” section.
Chapter 8: Updated Table 8-5.
04/08/08 1.10 Chapter 1: Updated Table 1-6 and “Loading Encrypted Bitstreams” section.
Chapter 3: Updated “Identification Register” section, including Table 3-4 and Table 3-5.
06/09/09 1.11 Chapter 1:
• Interchanged phase events 5 and 6 in Table 1-9.
Chapter 2:
• Added cross reference to the Virtex-4 FPGA Data Sheet.
• Changed default oscillator frequency to 4 MHz in Note 3 following Figure 2-4.
• Updated “Single Device SelectMAP Configuration” section.
Chapter 8:
• Updated description of .rba and .rbb files in “Verifying Readback Data” section.
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Version Revision
06/02/17 1.12 Chapter 8:
• Added note after first paragraph to clarify that configuration memory readback is not
supported for flight applications in Virtex-4QV devices.
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Table of Contents
Preface: About This Guide
Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Typographical Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Chapter 1: Configuration Overview
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Setup (Steps 1-3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Device Power-Up (Step 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Clear Configuration Memory (Step 2, Initialization) . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Sample Mode Pins (Step 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Delaying Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Bitstream Loading (Steps 4-7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Synchronization (Step 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Check Device ID (Step 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Load Configuration Data Frames (Step 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Cyclic Redundancy Check (Step 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Startup (Step 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Bitstream Encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
AES Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Creating an Encrypted Bitstream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Loading the Encryption Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Loading Encrypted Bitstreams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Bitstream Encryption and Internal Configuration Access Port (ICAP) . . . . . . . . . . . . 25
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. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
BATT
Chapter 2: Configuration Interfaces
Serial Configuration Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Clocking Serial Configuration Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Master Serial Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Slave Serial Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Serial Daisy Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Configuring a Serial Daisy Chain with a Microprocessor or CPLD . . . . . . . . . . . . . . . . 32
Mixed Serial Daisy Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Guidelines and Design Considerations for Serial Daisy Chains . . . . . . . . . . . . . . . . . . . 33
Ganged Serial Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Startup Sequencing (GTS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Disable the Active DONE Driver On for All Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Connect All DONE Pins if Using a Master Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
DONE Pin Rise Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Configuration Clock (CCLK) as Clock Signal for Board Layout . . . . . . . . . . . . . . . . . . . 38
Signal Fanout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
PROM Files for Ganged Serial Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
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SelectMAP Configuration Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Single Device SelectMAP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Multiple Device SelectMAP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Ganged SelectMAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
SelectMAP Data Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Continuous SelectMAP Data Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Non-Continuous SelectMAP Data Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
SelectMAP ABORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Configuration Abort Sequence Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Readback Abort Sequence Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
ABORT Status Word. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Resuming Configuration or Readback After an Abort . . . . . . . . . . . . . . . . . . . . . . . . . . 51
SelectMAP Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
SelectMAP Data Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Configuration Data Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Byte Swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Generating PROM Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
PROM Files for Serial Daisy Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
PROM Files for SelectMAP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Chapter 3: Boundary-Scan and JTAG Configuration
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Boundary-Scan for Virtex-4 Devices Using IEEE Standard 1149.1 . . . . . . . . . . . . . 57
Test Access Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
TAP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Boundary-Scan Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Boundary-Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Instruction Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
BYPASS Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Identification Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Configuration Register (Boundary-Scan) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
USERCODE Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
USER1, USER2, USER3, and USER4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Using Boundary-Scan in Virtex-4 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Configuring Through Boundary-Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Reconfiguring through Boundary-Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Boundary-Scan for Virtex-4 Devices Using IEEE Standard 1532 . . . . . . . . . . . . . . 71
ISC Modal States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Clocking Startup and Shutdown Sequences (JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Configuration Flows Using JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Chapter 4: Frame ECC Logic
Using Frame ECC Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Chapter 5: User Access Register
Using the User Access Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Chapter 6: Reconfiguration Techniques
Dynamic Reconfiguration of Functional Blocks (DRP) . . . . . . . . . . . . . . . . . . . . . . . 79
Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
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Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
FPGA Fabric Port Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
DRP DCM Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Changing the Multiply and Divide Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Dynamic Phase Shifting Through the DRP in Direct Mode . . . . . . . . . . . . . . . . . . . . . 84
ICAP - Internal Configuration Access Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Chapter 7: Configuration Details
Configuration Memory Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Configuration Control Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Packet Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Type 1 Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Type 2 Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Command Register (CMD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Control Register (CTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Frame Address Register (FAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Status Register (STAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Configuration Options Register (COR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Bitstream Composition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Default Initial Configuration Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Chapter 8: Readback and Configuration Verification
Preparing a Design for Readback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Readback Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Accessing Configuration Registers through the SelectMAP Interface . . . . . . . . . . . . 100
Configuration Register Read Procedure (SelectMAP) . . . . . . . . . . . . . . . . . . . . . . . . . 101
Configuration Memory Read Procedure (SelectMAP) . . . . . . . . . . . . . . . . . . . . . . . . . 102
Accessing Configuration Registers through the JTAG Interface . . . . . . . . . . . . . . . . 104
Configuration Register Read Procedure - JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Configuration Memory Read Procedure (1149.1 JTAG) . . . . . . . . . . . . . . . . . . . . . . . . 106
Configuration Memory Read Procedure (1532 JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . 109
Verifying Readback Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Readback Capture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
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About This Guide
This document describes the Virtex®-4 Configuration. Complete and up-to-date
documentation of the Virtex-4 family of FPGAs is available on the Xilinx web site at
http://www.xilinx.com/products/virtex4/index.htm
Guide Contents
• Chapter 1, “Configuration Overview”
• Chapter 2, “Configuration Interfaces”
• Chapter 3, “Boundary-Scan and JTAG Configuration”
• Chapter 4, “Frame ECC Logic”
• Chapter 5, “User Access Register”
• Chapter 6, “Reconfiguration Techniques”
• Chapter 7, “Configuration Details”
• Chapter 8, “Readback and Configuration Verification”
Preface
.
Additional Documentation
The following documents are also available for download at
http://www.xilinx.com/products/virtex4/index.htm
• Virtex-4 Family Overview
The features and product selection of the Virtex-4 family are outlined in this overview.
• Virtex-4
This data sheet contains the DC and Switching Characteristic specifications for the
Virtex-4 family.
• Virtex-4
Chapters in this guide cover the following topics:
- Clocking Resources
- Digital Clock Manager (DCM)
- Phase-Matched Clock Dividers (PMCD)
- Block RAM and FIFO memory
- Configurable Logic Blocks (CLBs)
-SelectIO™ Resources
FPGA Data Sheet: DC and Switching Characteristics
FPGA User Guide
.
Virtex-4 FPGA Configuration User Guide www.xilinx.com 9
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Preface: About This Guide
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• XtremeDSP™ Design Considerations
- SelectIO Logic Resources
- Advanced SelectIO Logic Resources
This guide describes the XtremeDSP slice and includes reference designs for using
DSP48 math functions and various FIR filters.
• Virtex-4
This designer’s guide provides information on the design of PCBs for Virtex-4 devices.
It considers all aspects of the PCB from the system level down to the minute details.
This guide focuses on strategies for making design decisions at the PCB and interface
level.
• Virtex-4
This specification includes the tables for device/package combinations and maximum
I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and
thermal specifications.
• Virtex-4 RocketIO
This guide describes the RocketIO Multi-Gigabit Transceivers available in the
Virtex-4-FX family.
• Virtex-4
This guide describes the Tri-Mode Ethernet Media Access Controller available in the
Virtex-4 FX family.
• PowerPC®
This guide is updated to include the PowerPC 405 processor block available in the
Virtex-4 FX family.
Additional Resources
FPGA PCB Designers Guide
FPGA Packaging and Pinout Specification
™ Multi-Gigabit Transceiver User Guide
FPGA Embedded Tri-Mode Ethernet MAC User Guide
405 Processor Block Reference Guide
To search the database of silicon and software questions and answers, or to create a
technical support case in WebCase, see the Xilinx website at:
http://www.xilinx.com/support
Typographical Conventions
This document uses the following typographical conventions. An example illustrates each
convention.
Convention Meaning or Use Example
Italic font
.
References to other documents
Emphasis in text
See the Virtex-4 Configuration
Guide for more information.
The address (F) is asserted after
clock event 2.
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Online Document
The following conventions are used in this document:
Convention Meaning or Use Example
Typographical Conventions
Blue text
Red text
Blue, underlined text
Cross-reference link to a
location in the current
document
Cross-reference link to a
location in another document
Hyperlink to a website (URL)
See the section “Additional
Resources” for details.
Refer to “Title Formats” in
Chapter 1 for details.
See the Virtex-4 User Guide.
Go to http://www.xilinx.com
for the latest speed files.
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Configuration Overview
Introduction
Virtex®-4 devices are configured by loading application-specific configuration data—the
bitstream—into internal memory. Because Xilinx® FPGA configuration memory is
volatile, it must be configured each time it is powered-up. The bitstream is loaded into the
device through special configuration pins. These configuration pins serve as the interface
for a number of different configuration modes:
• Master-serial configuration mode
• Slave-serial configuration mode
• Master SelectMAP (parallel) configuration mode
• Slave SelectMAP (parallel) configuration mode
In addition, the bitstream can be loaded through the JTAG interface:
Chapter 1
• JTAG/Boundary-Scan configuration mode
The configuration modes are explained in detail in Chapter 2 The configuration mode is
selected by setting the appropriate level on the dedicated MODE input pins. Table 1-1 lists
the Virtex-4 configuration modes.
Table 1-1: Virtex-4 Configuration Modes
Configuration Mode M2 M1 M0 Data Width CCLK Direction
Master Serial 000 1 bit Output
Slave Serial 111 1 bit Input
Master SelectMAP 011 8 bits Output
Slave SelectMAP8 110 8 bits Input
Slave SelectMAP32
JTAG/Boundary-Scan only
Notes:
1. JTAG configuration uses the JTAG TCK pin instead of the configuration clock (CCLK).
2. I/O pre-configuration pull-up resistors are disabled with the HSWAPEN pin.
3. In SelectMAP32 D0:D31 data bits are not swapped. D0 is the LSB. D31 is the MSB.
4. If the pins are left unconnected a weak pull-up resistor on the mode pins makes slave serial the default
mode.
(3)
(1)
001 32 bits Input
101 1 bit –
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Chapter 1: Configuration Overview
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The terms Master and Slave refer to the direction of the configuration clock (CCLK):
• In Master configuration modes, the Virtex-4 device drives the configuration clock
(CCLK) from an internal oscillator
• In Slave configuration modes, the configuration clock is an input.
The JTAG/Boundary-Scan configuration interface is always available, regardless of the
MODE pin settings. The JTAG/Boundary-Scan configuration mode disables all other
configuration modes. This prevents conflicts between configuration interfaces.
The JTAG interface is available after the mode pins are sampled. Activating PROGRAM_B
disables JTAG until INIT is completed.
Certain pins are dedicated to configuration, while others are dual-purpose (Table 1-2).
Dual-purpose pins serve both as configuration pins and as user I/O after configuration.
Dedicated configuration pins retain their function after configuration.
Table 1-2: Virtex-4 Configuration Pins
Pin Name Type
M[2:0] Input Dedicated Mode pins that determine configuration mode. Sampled on the rising
CCLK Input or
D_IN Input Dedicated Serial data input for serial configuration modes.
DOUT_BUSY Output Dedicated In Serial configuration mode, pin acts as serial data output for daisy-chain
DONE Bidirectional,
Open-Drain
INIT_B Input or
Open-Drain
PROGRAM_B Input Dedicated Active Low asynchronous full-chip reset.
SelectMAP
Data
Bidirectional Dual-Purpose Parallel data inputs for SelectMAP modes.
(1)
Output
or Active
Output,
Dedicated or
Dual-Purpose
Dedicated Configuration clock source for all configuration modes except JTAG.
Dedicated Active High signal indicating configuration is complete.
Dedicated Before MODE pins are sampled, INIT_B is an input that can be held Low
(2)
edge of INIT_B.
configuration. In SelectMAP mode, pin acts as BUSY output.
0 = FPGA not configured
1 = FPGA configured
Refer to the “BitGen” section of the Development System Reference Guide for
software settings.
to delay configuration.
After MODE pins are sampled, INIT_B is an open-drain active Low
output indicating whether a CRC error occurred during configuration:
0 = CRC error
1 = No CRC error
For 8-bit SelectMAP:
D0 = MSB
D7 = LSB
For 32-bit SelectMAP:
D0 = LSB
D31 = MSB
Description
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Setup (Steps 1-3)
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Device
Power-Up
Sample Mode
Pins
Synchronization
Device ID
Check
CRC Check
Clear
Configuration
Memory
Startup
Sequence
Load
Configuration
Data
Start
Finish
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Table 1-2: Virtex-4 Configuration Pins (Continued)
Pin Name Type
(1)
HSWAPEN Input Dedicated Active High input used to disable weak pre-configuration I/O pull-up
Notes:
1. The Bidirectional type describes a pin that is bidirectional under all conditions. If the pin is an input for some configuration modes or an
output for others, it is listed as an Input or Output type.
2. Dual-purpose pins can become user I/O after configuration. See “
Dedicated or
Dual-Purpose
(2)
Description
resistors:
0 = weak pre-configuration I/O pull-up resistors enabled
1 = weak pre-configuration I/O pull-up resistors disabled
HSWAPEN must be connected to either enable or disable the pull-up
resistors.
HSWAPEN has a weak pull-up prior to and during configuration. The
weak pull-up does not always provide a reliable 1.
PERSIST” in Chapter 7 for details.
Setup (Steps 1-3)
While each of the configuration interfaces is different, the basic steps for configuring a
Virtex-4 device are the same for all modes. Figure 1-1 shows the Virtex-4 configuration
process. Each step is described in detail in the following sections.
Steps
Start
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Device
Power-Up
Clear
Configuration
Memory
Sample Mode
Pins
Synchronization
Figure 1-1: Virtex-4 Configuration Process
Device Power-Up (Step 1)
Figure 1-2: Device Power-Up (Step 1)
For configuration, Virtex-4 devices require power on the V
V
All JTAG and serial configuration pins are located in a separate, dedicated bank with a
dedicated V
purpose pins, and are located in Bank 2 (V
V
voltage level with the output standard set to LVCMOS_12F. In SelectMAP mode, V
must be connected to the appropriate voltage to match the I/O standard of the
configuration device.
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pins. There are no power-supply sequencing requirements.
CCINT
CC_CONFIG
(V
) supply. The SelectMAP data pins are shared dual-
CCO_0
CCO_2
CC_CONFIG
LVCMOS level. All active dedicated output pins operate at the V
Device ID
Check
Configuration
Bitstream
Loading
Load
Data
CC_CONFIG
CRC Check
, V
CCAUX
Startup
Sequence
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, and
). All dedicated input pins operate at
CC_CONFIG
Finish
CCO_2
Chapter 1: Configuration Overview
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For power-up, the V
I/O voltage supplies (V
power pins must be supplied with a 1.2V source. None of the
CCINT
), except V
CCO
CCO_0 (VCC_CONFIG
), need to be powered for
Virtex-4 configuration in JTAG or serial modes. Table 1-3 shows the power supplies
required for configuration; for recommended operating conditions, see Table 2 of the
Virtex-4 FPGA Data Sheet. Table 41 of the Virtex-4 FPGA Data Sheet shows the configuration
power-up timing parameters. Table 7-1 shows the number of frames per Virtex-4 device.
Table 1-3: Power Supplies Required for Configuration
Pin Name Description
V
CCINT
(1)
V
BATT
V
CC_CONFIG
V
CCAUX
Notes:
1. V
is required only when using bitstream encryption.
BATT
PROGRAM_B
CCLK Output or Input
Internal core voltage relative to GND.
Encryption Key battery supply.
Configuration output supply voltage (also known as V
CCO_0
)
Auxiliary power input for configuration logic and other FPGA functions.
V
CC
INIT_B
T
POR
T
PL
T
T
ICCK
M0, M1, M2*
(Required)
*Can be either 0 or 1, but must not toggle during and after configuration.
Figure 1-3: Device Power-Up Timing
V
should rise monotonically within the specified ramp rate. If this is not possible,
CCINT
delay configuration by holding the INIT_B pin or the PROGRAM_B pin Low (see
“Delaying Configuration”) while the system power reaches V
The configuration logic power input (V
(V
) are used as a logic input to the Power-On-Reset (POR) circuitry. If either of these
CCAUX
CC_CONFIG
) and the auxiliary voltage input
voltage planes dips below the specified level, POR can trigger.
Clear Configuration Memory (Step 2, Initialization)
Steps
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Clear
Configuration
Memory
Sample Mode
Pins
Synchronization
Device ID
Check
Bitstream
Loading
Figure 1-4: Initialization (Step 2)
Start
Device
Power-Up
POR
Load
Configuration
Data
VAL ID
.
CRC Check
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Startup
Sequence
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Setup (Steps 1-3)
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Device
Power-Up
Sample Mode
Pins
Synchronization
Device ID
Check
CRC Check
Clear
Configuration
Memory
Startup
Sequence
Load
Configuration
Data
Start
Finish
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Configuration memory is cleared sequentially any time the device is powered up, when
the PROGRAM_B pin is pulsed Low, or when the JTAG JPROGRAM instruction is used.
During this time, I/Os are placed in a high-Z state except for the dedicated Configuration
and JTAG pins. INIT_B is held Low by the device during initialization, then released after
T
(Figure 1-3.) If the INIT_B pin is held Low externally, the device waits at this point in
POR
the initialization process until the pin is released.
The minimum Low pulse time for PROGRAM_B is defined by the T
parameter. The PROGRAM_B pin can be held active (Low) for as long as necessary, and the
device remains held in the reset state.
Sample Mode Pins (Step 3)
When the INIT_B pin transitions to High, the device samples the MODE pins and begins
driving CCLK if in Master Serial or Master SelectMAP mode. At this point, the device
begins sampling the configuration data input pins (D
pins for SelectMAP modes on rising configuration clock signals).
Delaying Configuration
There are two ways to delay configuration for Virtex-4 devices:
Figure 1-5: Sample Mode Pins (Step 3)
pin for Serial Modes or the D0–D7
IN
PROGRAM
timing
• The first is to hold the INIT_B pin Low during initialization (Figure 1-3). This method
only works if INIT_B is prevented from going High. After INIT_B goes High,
configuration cannot be delayed by subsequently pulling INIT_B Low.
• The second is to hold the PROG pin Low, continuously clearing configuration
memory (“Clear Configuration Memory (Step 2, Initialization),” page 16). The signals
relating to initialization and delaying configuration (Table 1-4).
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Device
Power-Up
Sample Mode
Pins
Synchronization
Device ID
Check
CRC Check
Clear
Configuration
Memory
Startup
Sequence
Load
Configuration
Data
Start
Finish
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Table 1-4: Signals Relating to Initialization and Delaying Configuration
Signal Name Type
(1)
Access
(2)
Description
PROGRAM_B Input Externally accessible via
the PROGRAM_B pin.
Global asynchronous chip reset.
Can be held Low to delay
configuration.
INIT_B Input or
Output
Externally accessible via
the INIT_B pin.
Before the MODE pins are
sampled, INIT_B is an input that
can be held Low to delay
configuration.
After the MODE pins are sampled,
INIT_B is an open-drain active
Low output indicating whether a
CRC error occurred during
configuration:
0 = CRC error
1 = No CRC error
INIT_COMPLETE Status Internal signal,
accessible through the
Indicates whether INIT_B signal
has been internally released.
Virtex-4 status register.
MODE_STATUS[2:0] Status Internal signals,
accessible through the
Virtex-4 status register.
Reflects the values sampled on the
MODE pins when INIT_B is
asserted High.
Notes:
1.
The Status type symbolizes an internal status signal without a corresponding pin.
2. Information on the Virtex-4 status register is available in Table 7-9. Information on accessing the
JTAG capture sequence is available in Table 8-4.
Bitstream Loading (Steps 4-7)
The bitstream loading process is similar for all configuration modes; the primary
difference between modes is the interface to the configuration logic. Details on the different
configuration interfaces are provided in Chapter 2.
The most important steps in the bitstream loading process are, synchronization, device ID
check, loading configuration data, and the CRC check. Each of these steps involves distinct
parts of the configuration bitstream. The steps prior to synchronization and after the CRC
check do not directly involve the configuration bitstream.
Synchronization (Step 4)
Figure 1-6: Synchronization (Step 4)
Before the configuration data frames can be loaded, a special 32-bit synchronization word
(0xAA995566) must be sent to the configuration logic. The synchronization word alerts
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Bitstream Loading (Steps 4-7)
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Device
Power-Up
Sample Mode
Pins
Synchronization
Device ID
Check
CRC Check
Clear
Configuration
Memory
Startup
Sequence
Load
Configuration
Data
Start
Finish
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the device to upcoming configuration data and aligns the configuration data with the
internal configuration logic. Any data on the configuration input pins prior to
synchronization is ignored.
Synchronization is transparent to most users because all configuration bitstreams (.bit
files) generated by the Xilinx ISE® Bitstream Generator (BitGen) software include the
synchronization word. Table 1-5 shows signals relating to synchronization.
Table 1-5: Signals Relating to Synchronization
Signal Name Type Access Description
DALIGN Status Only available through the
Check Device ID (Step 5)
Once the device is synchronized, a device ID check must pass before the configuration data
frames can be loaded. This prevents an attempted configuration with a bitstream that is
formatted for a different device.
For example, the device ID check should prevent an XC4VLX15 from being configured
with an XC4VLX80 bitstream.
SelectMAP interface during an
ABORT. (See “Configuration
Abort Sequence Description,”
page 49.)
Figure 1-7: Check Device ID (Step 5)
Indicates whether device
is synchronized.
The device ID check is built into the bitstream, making this step transparent to most
designers. Figure 1-7 shows the relative position of the device ID check, Table 1-6 shows
the Virtex-4 device IDs, and Table 1-7 shows the sig nals re latin g to the devic e ID che ck. The
device ID check is performed through commands in the bitstream to the configuration
logic, not through the JTAG IDCODE register in this case.
Table 1-6: Virtex-4 Device ID Codes
Device IDCODE Device IDCODE Device IDCODE
XC4VLX15 01658093 XC4VFX12 01E58093
XC4VLX25 0167C093 XC4VSX25 02068093 XC4VFX20 01E64093
XC4VLX40 016A4093 XC4VSX35 02088093 XC4VFX40 01E8C093
XC4VLX60 016B4093 XC4VSX55 020B0093 XC4VFX60 01EB4093
XC4VLX80 016D8093
XC4VLX100 01700093 XC4VFX100 01EE4093
XC4VLX160 01718093 XC4VFX140 01F14093
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Chapter 1: Configuration Overview
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Device
Power-Up
Sample Mode
Pins
Synchronization
Device ID
Check
CRC Check
Clear
Configuration
Memory
Startup
Sequence
Load
Configuration
Data
Start
Finish
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Bitstream
Loading
Steps
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Device
Power-Up
Sample Mode
Pins
Synchronization
Device ID
Check
CRC Check
Clear
Configuration
Memory
Startup
Sequence
Load
Configuration
Data
Start
Finish
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Table 1-6: Virtex-4 Device ID Codes (Continued)
Device IDCODE Device IDCODE Device IDCODE
XC4VLX200 01734093
Notes:
1. Does not reflect the actual device array size.
Table 1-7: Signals Relating to the Device ID Check
Signal Name Type Access
ID_Err Status Internal signal. Accessed
Notes:
1. Information on the Virtex-4 status register is available in Table 7-9. Information on accessing the JTAG
capture sequence is available in Table 8-4.
Load Configuration Data Frames (Step 6)
(1)
only through the Virtex-4
status register.
Description
Indicates a mismatch between the
device ID specified in the bitstream
and the actual device ID.
Figure 1-8: Load Configuration Data Frames (Step 6)
After the synchronization word is loaded and the device ID has been checked, the
configuration data frames are loaded. This process is transparent to most users. For details,
refer to Chapter 7
Cyclic Redundancy Check (Step 7)
Figure 1-9: Cyclic Redundancy Check (Step 7)
As the configuration data frames are loaded, the device calculates a Cyclic Redundancy
Check (CRC) value from the configuration data packets. After the configuration data
frames are loaded, the configuration bitstream can issue a Check CRC instruction to the
device, followed by an expected CRC value. If the CRC value calculated by the device does
not match the expected CRC value in the bitstream, the device pulls INIT_B Low and
aborts configuration. The CRC check is included in the configuration bitstream by default,
although the designer can disable it if desired. (Refer to the Development System Reference
Guide, BitGen section.) If the CRC check is disabled, there is a risk of loading incorrect
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Startup (Step 8)
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x32x28x27x26x25x23x22x20x19x18x14x13x11x10x9x8x61+ + + + + + + + + + + + + ++++
Device
Power-Up
Sample Mode
Pins
Synchronization
Device ID
Check
CRC Check
Clear
Configuration
Memory
Startup
Sequence
Load
Configuration
Data
Start
Finish
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configuration data frames, causing incorrect design behavior, or even damaging the
device.
If a CRC error occurs during configuration, the device must be resynchronized and
reconfigured. In serial modes, the device can only be resynchronized by pulsing the
PROGRAM_B pin and restarting the configuration process from the beginning. In
SelectMAP modes, either the PROGRAM_B pin can be pulsed Low or an ABORT sequence
can be initiated (see “SelectMAP Configuration Interface” in Chapter 2).
Virtex-4 devices use a 32-bit CRC check. The CRC check is designed to catch errors in
transmitting the configuration bitstream. There is a scenario where errors in transmitting
the configuration bitstream can be missed by the CRC check:
Certain clocking errors, such as double-clocking, can cause loss of synchronization
between the 32-bit bitstream packets and the configuration logic. Once
synchronization is lost, any subsequent commands are not understood, including the
command to check the CRC. In this situation, configuration fails with DONE Low and
INIT_B High.
Virtex-4 configuration uses a standard CRC32C checksum algorithm. The CRC32C
polynomial is:
Startup (Step 8)
After the configuration frames are loaded, the bitstream instructs the device to enter the
startup sequence. The startup sequence is controlled by an 8-phase (phases 0–7) sequential
state machine. The startup sequencer performs the tasks outlined in Table 1-8.
Table 1-8: User-Selectable Cycle of Startup Events
Figure 1-10: Start-Up Sequence (Step 8)
Phase Event
1–6 Wait for DCMs to Lock (optional)
1–6 Wait for DCI to Match (optional)
1
–6 Assert GWE (Global Write Enable), allowing RAMs and flip-flops to change state
1–6 Negate GTS (Global 3-State), activating I/O
1–6Release DONE pin
7 Assert EOS (End Of Startup)
The specific order of startup events (except for EOS assertion) is user-programmable
through BitGen options (refer to the Development System Reference Guide). Table 1-8 shows
the general sequence of events, although the specific phase for each of these startup events
is user-programmable (EOS is always asserted in the last phase). Refer to Chapter 2,
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Chapter 1: Configuration Overview
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“Configuration Interfaces” for important startup option guidelines. By default, startup
events occur as shown in Table 1-9.
Table 1-9: Default Sequence of Startup Events
Phase Event
4Release DONE pin
5 Negate GTS, activating I/O
6 Assert GWE, allowing RAMs and FFs to change state
7Assert EOS
The start-up sequence can be forced to wait for the DCMs to lock or for DCI to match with
the appropriate BitGen options. These options are typically set to prevent DONE, GTS, and
GWE from being asserted (preventing device operation) before the DCMs have locked
and/or DCI has matched.
The DONE signal is released by the start-up sequencer on the cycle indicated by the user,
but the start-up sequencer does not proceed until the DONE pin actually sees a logic High.
The DONE pin is an open-drain bidirectional signal by default. By releasing the DONE
pin, the device simply stops driving a logic Low and the pin goes into a high-Z state. An
external pull-up resistor is needed for the DONE pin to reach a logic High in this case.
Table 1-10 shows signals relating to the status register. Figure 1-11 shows the signals
relating to the start-up sequencer.
Table 1-10: Signals Relating to Status Register
Signal Name Type
DONE Bidirectional
Release_DONE
GWE Global Write Enable. When de asserted GWE
GTS Global Tri-State. When asserted, GTS
EOS End of Startup. EOS indicates the absolute
DCI_MATCH DCI_MATCH indicates when all the
DCM_LOCK DCM_LOCK indicates when all the Digital
Status
Access
(2)
DONE pin or
Virtex-4 Status
Register
Virtex-4
Status
Register
(1)
Indicates configuration is complete. Can be
held Low externally to synchronize startup
with other FPGAs.
Indicates whether device has released
DONE pin. If pin is held Low externally,
Release_DONE can differ from actual value
on DONE pin.
disables CLB and IOB flips-flops as well as
other synchronous elements on the FPGA.
disables all the I/O drivers except for
configuration pins.
end of the configuration and startup process.
Digitally Controlled Impedance (DCI)
controllers have matched their internal
resistor to the external reference resistor.
Clock Managers (DCMs) have locked. This
signal is asserted by default. It is active if the
LOCK_WAIT option is used on a DCM and
the LockCycle option is used when the
bitstream is generated.
Description
Notes:
1. Information on the Virtex-4 status register is available in Table 7-9. Information on accessing the JTAG
capture sequence is available in Table 8-4.
2. Open-drain output by default; optional driver enabled using BitGen drivedone option.
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POR
INIT_B
DONE
GWE
GTS
EOS
CCLK
Bitstream Encryption
Initialization Configuration StartupEnd of Bitstream
Figure 1-11: Configuration Signal Sequencing (Default Startup Settings)
Bitstream Encryption
Virtex-4 devices have on-chip AES (Advanced Encryption Standard) decryption logic to
provide a high degree of design security. Without knowledge of the encryption key,
potential pirates cannot analyze an externally intercepted bitstream to understand or clone
the design. Encrypted Virtex-4 designs cannot be copied or reverse-engineered.
The Virtex-4 AES system consists of software-based bitstream encryption and on-chip
bitstream decryption with dedicated memory for storing the encryption key. Using the
Xilinx ISE software, the user generates the encryption key and the encrypted bitstream.
During configuration, the Virtex-4 device performs the reverse operation, decrypting the
incoming bitstream. The Virtex-4 AES encryption logic uses a 256-bit encryption key.
The on-chip AES decryption logic cannot be used for any purpose other than bitstream
decryption; i.e., the AES decryption logic is not available to the user design and cannot be
used to decrypt any data other than the configuration bitstream.
Virtex-4 devices store the encryption key internally in dedicated RAM, backed up by a
small externally connected battery. The encryption key can only be programmed onto the
device through the JTAG interface; once programmed, it is not possible to read the
encryption key out of the device through JTAG or any other means.
ICAP is not supported with an encrypted bitstream in the LX, SX, and FX12 devices.
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AES Overview
The Virtex-4 encryption system uses the Advanced Encryption Standard (AES) encryption
algorithm. AES is an official standard supported by the National Institute of Standards and
Technology (NIST) and the U.S. Department of Commerce
(http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf)
The Virtex-4 AES encryption system uses a 256-bit encryption key (the alternate key
lengths of 128- and 192- bits described by NIST are not implemented) to encrypt or decrypt
blocks of 128 bits of data at a time. According to NIST, there are 1.1 x 10
combinations for a 256-bit key.
Symmetric encryption algorithms such as AES use the same key for encryption and
decryption. The security of the data is therefore dependent on the secrecy of the key.
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possible key
Chapter 1: Configuration Overview
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Creating an Encrypted Bitstream
The Xilinx Bitstream Generator (BitGen, provided with the Xilinx ISE software) can
generate encrypted as well as non-encrypted bitstreams. For AES bitstream encryption, the
user specifies a 256-bit key as an input to BitGen. BitGen in turn generates an encrypted
bitstream file (.bit) and an encryption key file (.nky).
For specific BitGen commands and syntax, refer to the Development System Reference Guide.
Loading the Encryption Key
The encryption key can only be programmed onto a Virtex-4 device through the JTAG
interface. The iMPACT tool, provided with the Xilinx ISE software, can accept the .nky file
as an input and program the device with the key through JTAG, using a supported Xilinx
programming cable.
To program the key, the device enters a special key-access mode using the ISC_PROGRAM
instruction, as detailed in the JTAG 1532 specification. In this mode, all FPGA memory,
including the encryption key and configuration memory, is cleared. Once the key is
programmed and the key-access mode is exited, it cannot be read out of the device by any
means, and it cannot be reprogrammed without clearing the entire device. The key-access
mode is transparent to most users.
Loading Encrypted Bitstreams
Once the device has been programmed with the correct encryption key, the device can be
configured with an encrypted bitstream. After configuration with an encrypted bitstream,
it is not possible to read the configuration memory through JTAG or SelectMAP readback,
regardless of the BitGen security setting.
After loading the encryption key, a non-encrypted bitstream can be used to configure the
device; in this case the key is ignored. After configuring with a non-encrypted bitstream,
readback is possible (if allowed by the BitGen security setting). The encryption key still
cannot be read out of the device, preventing the use of Trojan Horse bitstreams to defeat the
Virtex-4 encryption scheme.
However, once an encrypted bitstream has been used to configure a device, the device
cannot be reconfigured with a non-encrypted bitstream unless a full-chip reset is
performed first by pulling the PROGRAM_B pin Low, cycling power, or issuing a
JPROGRAM instruction. Additional encrypted reconfigurations can be performed.
The method of configuration is not affected by encryption. The configuration bitstream can
be delivered in any mode (Serial, SelectMAP, or JTAG) from any configuration solution
(PROM, System ACE™ tool, etc.). Configuration timing and signaling are unaffected by
encryption.
The encrypted bitstream must configure the entire device, because partial reconfiguration
through the external configuration interfaces is not permitted for encrypted bitstreams.
After configuration, the device cannot be reconfigured without toggling the PROG pin,
cycling power, or issuing the JTAG JSTART or JPROG instruction. Readback is available
through the ICAP primitive (see “Bitstream Encryption and Internal Configuration Access
Port (ICAP)”). None of these events resets the key if V
BATT
or V
is maintained.
CCAUX
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Bitstream Encryption
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A mismatch between the key in the encrypted bitstream and the key stored in the device
causes configuration to fail with the INIT pin remaining High and the DONE pin
remaining Low. A mismatch between the key and bitstream can result in a high current on
V
CCINT
.
Note:
1. Do not use or monitor BUSY when loading an encrypted bitstream.
2. SelectMAP-32 mode is not supported with encrypted bitstreams.
Bitstream Encryption and Internal Configuration Access Port (ICAP)
The Internal Configuration Access Port (ICAP) primitive provides the user logic with
access to the Virtex-4 configuration interface. The ICAP interface is similar to the
SelectMAP interface, although the restrictions on readback and reconfiguration for the
SelectMAP interface do not apply to the ICAP interface after configuration. Users can
perform readback and reconfiguration through the ICAP interface even if bitstream
encryption is used. Unless the designer wires the ICAP interface to user I/O, this does not
offer attackers a method for defeating the Virtex-4 AES encryption scheme. ICAP is not
supported with an encrypted bitstream in the LX, SX, and FX12 devices.
Users concerned about the security of their design should not:
V
BATT
• Wire the ICAP interface to user I/O
-or-
• Not instantiate the ICAP primitive.
Like the other configuration interfaces, the ICAP interface does not provide access to the
key register.
The encryption key memory cells are volatile and must receive continuous power to retain
their contents. During normal operation, these memory cells are powered by the auxiliary
voltage input (V
the key after V
CCAUX
), although a separate V
CCAUX
is removed. Because V
power input is provided for retaining
BATT
draws very little current (on the order of
BATT
nano amperes), a small watch battery is suitable for this supply. (To estimate the battery
life, refer to V
DC Characteristics in the Virtex-4 FPGA Data Sheet and the battery
BATT
specifications.) At less than a 100 nA load, the endurance of the battery should be limited
only by its shelf life.
V
does not draw any current and can be removed while V
BATT
cannot be used for any purpose other than retaining the encryption keys when V
CCAUX
is applied. V
CCAUX
BATT
is
removed.
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Configuration Interfaces
Virtex®-4 devices have three configuration interfaces. Each configuration interface
corresponds to one or more configuration modes, shown in Table 2-1. For detailed
interface timing information, see the Virtex-4 FPGA Data Sheet.
Table 2-1: Configuration Interfaces and Corresponding Configuration Modes
Configuration Interface Corresponding Configuration Mode(s)
Serial Master Serial, Slave Serial
SelectMAP (8-bit or 32-bit) Master SelectMAP, Slave SelectMAP
JTAG JTAG
Serial Configuration Interface
Chapter 2
In serial configuration modes, the FPGA is configured by loading one configuration bit per
CCLK cycle:
• In Master serial mode, CCLK is an output.
• In Slave serial mode, CCLK is an input.
Figure 2-1 shows the basic Virtex-4 serial configuration interface.
There are four methods of configuring an FPGA in serial mode:
• Master serial configuration
• Slave serial configuration
• Serial daisy chain configuration
• Ganged serial configuration
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Table 2-2 describes the Serial Configuration Interface.
Table 2-2: Virtex-4 Serial Configuration Interface Pins
Pin Name Type
M[2:0]
DOUT
D_IN
INIT_B
PROGRAM_B
DONE
CCLK
ug071_14_073007
Figure 2-1: Virtex-4 Serial Configuration Interface
Dedicated
or Dual-
Description
Purpose
M[2:0] Input Dedicated Mode Pins – determine configuration mode.
CCLK
Input or
Output
Dedicated
D_IN Input Dedicated
DOUT_BUSY Output Dedicated
Configuration clock source for all configuration
modes except JTAG.
Serial configuration data input, synchronous to
rising CCLK edge.
Serial data output for downstream daisy-chained
devices.
Active High signal indicating configuration is
complete:
DONE
Bidirectional,
open-drain
or active
Dedicated
0 = FPGA not configured
1 = FPGA configured
Refer to the “BitGen” section of the Development
System Reference Guide for software settings.
Before the MODE pins are sampled, INIT_B is an
input that can be held Low to delay configuration.
INIT_B
Input or
Output,
open-drain
Dedicated
After the MODE pins are sampled, INIT_B is an
open-drain active Low output indicating whether
a CRC error occurred during configuration:
0 = CRC error
1 = No CRC error
PROGRAM_B Input Dedicated Active-Low asynchronous full-chip reset.
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Clocking Serial Configuration Data
PROGRAM_B
INIT_B
CCLK
DONE
Master DIN
Master CLK Begins Here
(2)
Data bits clocked on rising edge of CCLK
ug071_016_073007
BIT 0
(1)
BIT 1 BIT n BIT n+1
BIT n-63BIT n-64
Master DOUT /
Slave DIN
Xilinx
Serial PROM
Virtex-4
Master
Serial
DATA DOUT
INIT_B
DIN
CCLK
PROGRAM_B
DONE
M2
M0 M1
CLK
CE
RESET/OE
PROGRAM_B
UG071_12_073007
(2)(1)
(7)
(7)
Figure 2-2 shows how configuration data are clocked into Virtex-4 devices in Slave serial
and Master serial modes.
Figure 2-2: Serial Daisy Chain Configuration Clocking Sequence
Notes relevant to Figure 2-2:
Serial Configuration Interface
1. In Figure 2-2, bit 0 represents the MSB of the first byte. For example, if the first byte is
0xAA (1010_1010), bit 0=1, bit 1=0, bit 2=1, etc.
2. For Master configuration mode, CCLK does not transition until after MODE pins are
sampled, as indicated by the arrow.
3. CCLK can be free-running in Slave serial mode.
Master Serial Configuration
The Master serial mode is designed so that the FPGA can be configured from a
Xilinx® serial configuration PROM, as shown in Figure 2-3.
Figure 2-3: Master Serial Mode Configuration
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Notes relevant to Figure 2-3:
1. The DONE pin is by default an open-drain output requiring an external pull-up
resistor. A 330Ω pull-up resistor is recommended. The DONE pin has a programmable
active driver. To enable it, enable the DriveDONE option in BitGen.
2. The INIT_B pin is a bidirectional, open-drain pin. An external pull-up resistor is
required.
3. The BitGen startup clock setting must be set for CCLK for serial configuration. The
oscillator frequency can be selected in BitGen (default is 4 MHz). Selectable
frequencies are 4, 5, 7, 8, 9, 10, 13, 15, 20, 26, 30, 34, 41, 45, 51, 55, and 60 MHz. Because
the oscillator can vary by ± 50%, select a maximum frequency not to exceed the F
of the configuration device.
4. The PROM in this diagram represents one or more Xilinx serial PROMs. Multiple serial
PROMs can be cascaded to increase the overall configuration storage capacity.
5. The .bit file must be reformatted into a PROM file before it can be stored on the serial
PROM. Refer to the “Generating PROM Files” section.
6. On XC17V00 PROMs, the reset polarity is programmable. RESET
active Low when using an XC17V00 device in this setup.
7. Connect pull-up resistors to V
8. The CCLK net requires Thevenin parallel termination. See “Board Layout for
Configuration Clock (CCLK),” page 34.
9. The CCLK pin is an output and an input.
CC_CONFIG
(identical to VCC Bank 0).
MAX
should be set for
Slave Serial Configuration
Slave serial configuration is typically used for devices in a serial daisy chain, or when
configuring a single device from an external microprocessor or CPLD. Design
considerations are similar to Master serial configuration except for the direction of CCLK.
A single device in Slave serial mode cannot simply be connected to a PROM, because
CCLK is an input on both devices.
Serial Daisy Chains
Multiple Virtex-4 devices can be configured from a single configuration source by
arranging the devices in a serial daisy chain. In a serial daisy chain, devices receive their
configuration data through their DIN pin, passing configuration data along to
downstream devices through their DOUT pin. The device closest to the configuration data
source is considered the most upstream device, while the device furthest from the
configuration data source is considered the most downstream device.
In a serial daisy chain, the configuration clock is typically provided by the most upstream
device in Master serial mode. All other devices are set for Slave serial mode. Figure 2-4
illustrates this configuration.
Alternatively, if a CPLD or microprocessor is used as a configuration controller, all devices
can be set for Slave serial mode. (See “Configuring a Serial Daisy Chain with a
Microprocessor or CPLD,” page 32.)
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