Xilinx VCU1525 User Manual

VCU1525
Reconfigurable
Acceleration Platform

User Guide

UG1268 (v1.3) August 7, 2018

Revision History

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The following table shows the revision history for this document.

Date Version Revision

08/07/2018 1.3 Revised Step 4: Program the Base Platform.

07/09/2018 1.2 Revised Board Features, Board Specifications, Table 2-1 , Installing the VCU1525 Board

in a Server Chassis, and Figure 3-11. Removed Xilinx constraints file information.

Added Appendix A, Board Installation.

04/02/2018 1.1 Revised Board Specifications and Installing the VCU1525 Board in a Server Chassis.

Updated Tab le 2 -1, Table 2 -2 , and Table 3- 9. Revised paragraph after Ta bl e 3-2.
Added Figure 3-13. Updated Figure 3-14, Figure 3-15, and Figure 3-16. Revised

Appendix B, Regulatory and Compliance Information.

11/13/2017 1.0 Initial Xilinx release.

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Table of Contents

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Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Chapter 1: Introduction

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Board Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Board Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Environmental . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Operating Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Chapter 2: Board Setup and Configuration

Board Component Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Default Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Installing the VCU1525 Board in a Server Chassis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

FPGA Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Chapter 3: Board Component Descriptions

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Component Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Virtex UltraScale+ XCVU9P-L2FSGD2104E FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

I/O Voltage Rails . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

DDR4 DIMM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Quad SPI Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

USB JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

FT4232HQ USB-UART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

System Clock and QSFP0 Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

QSFP1 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Programmable MGT and User Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

GTY Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

PCI Express Endpoint Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

28 Gb/s QSFP+ Module Connectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

User I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Board Management Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Board Management Controller Voltage Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

VCU1525 Board Power System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

. . .43

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Monitoring Voltage and Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

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Vccint Regulator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Cooling Fan Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Appendix A: Board Installation

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Installing a Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Step 1: Set Up the Card and Computer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Step 2: Prepare Board Installation Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Step 3: Install Board Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Step 4: Program the Base Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Step 5: Verify Successful Board Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Debugging the Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

SDx Debug Command Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

dmatest Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Example Output using VCU1525 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Failure to Create a Compute Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Useful Debug Operating System Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Other OS Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Appendix B: Regulatory and Compliance Information

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

CE Directives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

CE Standards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Electromagnetic Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Appendix C: Additional Resources and Legal Notices

Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Documentation Navigator and Design Hubs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

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Introduction

X20017-110217

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Overview

The VCU1525 Reconfigurable Acceleration Platform is a peripheral component interconnect
express (PCIe®) Gen3 x16 compliant board featuring the Xilinx® Virtex® UltraScale+™
XCVU9P-L2FSGD2104E FPGA. This Xilinx FPGA-based PCIe accelerator board is designed to
accelerate compute-intensive applications like machine learning, data analytics, and video
processing.

The VCU1525 board is available in both active and passive cooling configurations and
designed to be used in cloud data center servers.

Figure 1-1 shows the VCU1525 active cooling configuration (PC applications).

Chapter 1

X-Ref Target - Figure 1-1

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Figure 1-1: VCU1525 Reconfigurable Acceleration Platform (Active Cooling)

X-Ref Target - Figure 1-2

X20018-110217

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Chapter 1: Introduction

Figure 1-2 shows the VCU1525 passive cooling configuration (data center server

applications).

Figure 1-2: VCU1525 Reconfigurable Acceleration Platform (Passive Cooling)

CAUTION! The VCU1525 board with passive cooling is designed to be installed into a data center

server, where controlled air flow provides direct cooling. The VCU1525 board with active cooling is
designed to be installed into a PC environment where the air flow is uncontrolled, hence this
configuration has the heat sink and fan enclosure cover installed to provide appropriate cooling. In
either cooling configuration, due to the board enclosure, switches are not accessible, nor are LEDs
visible (except the triple-LED module DS3 which protrudes through the left front end PCIe bracket).
Board details revealed in this user guide are provided to aid understanding of board features. If the
cooling enclosure is removed from either configuration of the board and it is powered-up, external fan
cooling airflow MUST be applied to prevent over-temperature shut-down and possible damage to the
board electronics.

See Appendix C, Additional Resources and Legal Notices for references to documents, files,
and resources relevant to the VCU1525 board.

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X-Ref Target - Figure 1-3

244-pin DIMM interface
64-bit + ECC dual rank support
x4/x8 UDIMM support
PC4-2400 compatible

C0

244-pin DIMM interface
64-bit + ECC dual rank support
x4/x8 UDIMM support
PC4-2400 compatible

C2

244-pin DIMM interface
64-bit + ECC dual rank support
x4/x8 UDIMM support
PC4-2400 compatible

C3

244-pin DIMM interface
64-bit + ECC dual rank support
x4/x8 UDIMM support
PC4-2400 compatible

C1

DIP SW POWER

QSPI1

QSPI2

PCIe GEN1/2/3 x 1/2/4/8/16

PCIe GEN4 x 8

QSFP #2

QSFP #1

XADC

LEDs

Clocks

VU9P

D2104

X19964-110617

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Chapter 1: Introduction

Block Diagram

A block diagram of the VCU1525 board is shown in Figure 1-3.

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Figure 1-3: VCU1525 Board Block Diagram

Chapter 1: Introduction

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Board Features

The VCU1525 board features are listed in this section. Detailed information for each feature
is provided in Component Descriptions in Chapter 3.

• Virtex UltraScale+ XCVU9P-L2FSGD2104E FPGA

• Memory (four independent dual-rank DDR4 interfaces)

48 gigabyte (GB) DDR4 memory

°

4x DDR4 16 GB, 2400 mega-transfers per second (MT/s), 64-bit with error correcting

°

code (ECC) DIMM

x4/x8 unregistered dual inline memory module (UDIMM) support

°

• Configuration options

1 gigabit (Gb) Quad Serial Peripheral Interface (SPI) flash memory

°

Micro-AB universal serial bus (USB) J13 JTAG configuration port (FT4232HQ U65

°

bridge)

• 76 GTY transceivers (19 Quads)

16-lane PCI Express (16 GTY)

°

Two QSFP28 100G interfaces (8 GTY)

°

52 GTY not used

°

•Clock sources

Two Si5335A Quad clock generators

°

Si570 I2C programmable LVDS clock generator

°

• USB-to-UART FT4232HQ bridge with Micro-AB USB connector

• PCIe integrated Endpoint block connectivity

Gen1, 2 or 3 x1/x2/x4/x8/x16

°

Gen4 x8

°

•I2C bus

• Status LEDs

• User I/O (4-pole user dual-inline package (DIP) SW3, CPU_RESET PB SW1)

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• Power management with system management bus (SMBus) voltage, current, and
temperature monitoring

• Dynamic power sourcing based on external power supplied

• 75W PCIe slot functional with 35 A max V

current PCIe slot power only

CCINT

Chapter 1: Introduction

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• 150 W PCIe slot functional with 110 A max V
PCIe Aux power cable connected

• 225 W PCIe slot functional with 160 A max V
PCIe Aux power cable connected

• Two QSFP28 100G interfaces

• Onboard reprogrammable flash configuration memory

• Front panel JTAG and universal asynchronous receiver-transmitter (UART) access
through the USB port

• FPGA configurable over USB/JTAG and Quad SPI configuration flash memory

• Thermal management with variable rate fan for minimal fan noise

current PCIe slot power and 6-pin

CCINT

current PCIe slot power and 8-pin

CCINT

Board Specifications

Dimensions

Height: 4.2 inch (10.67 cm)

PCB thickness (±5%): 0.062 inch (0.157 cm)

Board length, passive heat sink: 9.2 inch (23.4 cm)

Board length, active heat sink: 11.4 inch (29 cm)

Board thickness with heat sink enclosure installed:

Active: 1.52 inch (3.86 cm)

Passive: 1.44 inch (3.66 cm)

Dual slot PCIe full-length, full height form-factor compliant

Note:

A 3D model of this board is not available.

Environmental

Temperature

Operating: 0°C to +45°C

Storage: –25°C to +60°C

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Humidity

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10% to 90% non-condensing

Operating Voltage

Chapter 1: Introduction

PCIe slot +12 VDC, +3.3 VDC, +3.3 V

, External +12 V

AUXDC

DC

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Board Setup and Configuration

00

Round callout references a component
on the front side of the board

Square callout references a component
on the back side of the board

00

1

2

3

4

5

16

17

8

9

19 20

18

13

14

7

12

12

6

15

X19972-031618

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Board Component Location

Figure 2-1 shows the location of components on the VCU1525 board. Each component

shown is keyed to Tab le 2- 1 . Ta ble 2- 1 identifies the components, references the respective
schematic page numbers, and links to a detailed functional description of the component
and board features in Chapter 3, Board Component Descriptions.

X-Ref Target - Figure 2-1

Chapter 2

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IMPORTANT: Figure 2-1 is for visual reference only and might not reflect the current revision of the

Figure 2-1: VCU1525 Board Components

board.

CAUTION! The VCU1525 board can be damaged by electrostatic discharge (ESD). Follow standard ESD

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prevention measures when handling the board.

Table 2-1: VCU1525 Board Component Descriptions

Chapter 2: Board Setup and Configuration

Number Ref. Des.

1U13Virtex UltraScale+

XCVU9P-L2FSGD2104E FPGA

2 J14 C0 DDR4 72-bit DIMM memory

(16 GB)

(DDR4 DIMM Memory)

3 J12 C1 DDR4 72-bit DIMM memory

(16 GB)

(DDR4 DIMM Memory)

4 J5 C2 DDR4 72-bit DIMM memory

(16 GB)

(DDR4 DIMM Memory)

5 J2 C3 DDR4 72-bit DIMM memory

(16 GB)

(DDR4 DIMM Memory)

6 U17, U58 Quad SPI Flash Memory (1Gb total) Micron MT25QU01GBBA8E12-0SIT 12

7 U27, J13 USB JTAG bridge w/ USB Micro-AB

connector

(FT4232HQ USB-UART Interface)

Feature

(Link)

Notes

XCVU9P-L2FSGD2104E —

Micron MTA18ASF2G72PZ-2G3B1IG 33

Micron MTA18ASF2G72PZ-2G3B1IG 34

Micron MTA18ASF2G72PZ-2G3B1IG 35

Micron MTA18ASF2G72PZ-2G3B1IG 36

FTDI FT4232HQ-REEL

HIROSE ZX62D-AB-5P8

Schematic

Page

31

8 J1 SMBUS 2X5 1.27mm pitch connector

(Monitoring Voltage and Current)

9 J3 BMC CTLR. JTAG 2 X 5 1.27 mm pitch

connector

(Figure 3-18 U19 MSP432 I2C

Connectivity)

10 U9 SYSCLK_300 300MHz, QSFP0_CLOCK

156.25MHz, 1.8V LVDS

(System Clock and QSFP0 Clock)

11 U12 QSFP1_CLOCK 156.25MHz, 1.8V

LVDS (QSFP1 Clock)

12 U14, U43 USER_SI570_CLOCK, 156.25MHz,

3.3V LVDS

+1 to 4 clock buffer

(Programmable MGT and User

Clock)

13 J7 QSFP0 (28 Gb/s QSFP+ Module

Connectors)

14 J9 QSFP1 (28 Gb/s QSFP+ Module

Connectors)

SAMTEC FTSH-105-01-F-D-K 16

SAMTEC FTSH-105-01-F-D-K 24

SI5335A-B06201-GM 23

SI5335A-B06201-GM 27

Silicon Labs SI570BAB000544DG

Silicon Labs SI53340-B-GM

AMPHENOL FS1-Z38-20Z6-60 23

AMPHENOL FS1-Z38-20Z6-60 27

23

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Table 2-1: VCU1525 Board Component Descriptions (Cont’d)

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Chapter 2: Board Setup and Configuration

Number Ref. Des.

15 U19 Board Management Controller

(BMC)

16 JP1 Auxiliary 12V power connector

(Vccint Regulator Circuit)

17 J4 Cooling Fan Connector JST SALES S4B-PH-K-S(LF)(SN) 11

Feature

(Link)

Notes

TI MSP432P401RIPZ 24

LIGHT JIE AARRA001-08MTTRH 17

Default Switch Settings

Default switch settings are listed in Tab l e 2 -2. Switch locations are shown in Figure 2-1.

Table 2-2: Default Switch Settings

Switch Function Default Comments Figure 2-1 Callout Schematic Page

SW3 4-pole GPIO DIP ON, ON, ON, ON 4-pole user DIP 18 11

Tab le 2 -3 shows other visible switch locations.

Table 2-3: Other Visible Switches

Schematic

Page

Component Function Comments Figure 2-1 Callout Schematic Page

SW1 Pushbutton switch CPU_RESET_B 19 11

SW2 Pushbutton switch PROGRAM_B 20 11

Installing the VCU1525 Board in a Server Chassis

Because each server or PC vendors hardware is different, for physical card installation
guidance, see the manufacturer’s PCIe card installation instructions.

For programming and start-up details, see Appendix A, Board Installation.

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Chapter 2: Board Setup and Configuration

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FPGA Configuration

The VCU1525 board supports two UltraScale+ FPGA configuration modes:

• Quad SPI flash memory

• JTAG using USB JTAG configuration port (USB J13/FT4232H U27)

The FPGA bank 0 mode pins are hardwired to M[2:0] = 001 Master SPI mode with
pull-up/down resistors.

At power up, the FPGA is configured by the Quad SPI NOR Flash U17 device (Micron
MT25QU01GBBA8E12-0SIT) with the FPGA_CCLK operating at clock rate of 105 MHz
(EMCCLK) using the Master Serial Configuration mode.

The Quad SPI flash memory NOR device has a capacity of 1 Gb.

While the FPGA default mode selects Quad SPI configuration, JTAG mode overrides it if
invoked. JTAG mode is always available independent of the Mode pin settings.

M0 is pulled up, however it is also connected to the I2C I/O port U2 PCA9536 device (port
P1, pin 2 ). This con nection al lows M0 to b e driven lo w by the MSP432 U19 BMC over I2C (via
the I2C PCS9536 U2 port expander), disabling the Master SPI mode.

For complete details on configuring the FPGA, see UltraScale Architecture Configuration
User Guide (UG570) [Ref 1].

Table 2-4: Configuration Modes

Configuration Mode M[2:0] Bus Width CCLKL Direction

Master SPI 001 x1, x2, x4 FPGA output

JTAG Not applicable - JTAG overrides x1 Not applicable

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X-Ref Target - Figure 2-2

X19973-103017

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Chapter 2: Board Setup and Configuration

The configuration circuit is shown in Figure 2-2.

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Figure 2-2: VCU1525 Configuration Circuit

Board Component Descriptions

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Overview

This chapter provides a detailed functional description of board components and features.

Tab le 2 -1 identifies the components, references the respective schematic page numbers,

and links to the corresponding detailed functional description in this chapter. Component
locations are shown in Tab le 2 -1.

Component Descriptions

Chapter 3

Virtex UltraScale+ XCVU9P-L2FSGD2104E FPGA

[Figure 2-1, callout 1]

The VCU1525 board is populated with the Virtex® UltraScale+™ XCVU9P-L2FSGD2104E
FPGA.

For more information on Virtex UltraScale+ FPGAs, see Virtex UltraScale+ FPGA Data Sheet:
DC and AC Switching Characteristics (DS923) [Ref 2].

I/O Voltage Rails

There are 13 I/O banks available on the XCVU9P-L2FSGD2104E FPGA and the VCU1525
board.

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X-Ref Target - Figure 3-1

MGTY233

MGTY232

MGTY231

MGTY230

MGTY229

MGTY228

MGTY227

MGTY226

MGTY225

MGTY224

MGTY133

MGTY131

MGTY130

MGTY129

MGTY128

MGTY123

MGTY122

MGTY121

MGTY120

72 73 74 71 70 69

66 64 65 61 62 63

67

X19971-103017

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Chapter 3: Board Component Descriptions

Figure 3-1 shows the XCVU9P-L2FSGD2104E bank arrangement.

Figure 3-1: XCVU9P-L2FSGD2104E Bank Arrangement

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Chapter 3: Board Component Descriptions

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The voltages applied to the XCVU9P-L2FSGD2104E U13 FPGA I/O banks are listed in

Tab le 3 -1.

Table 3-1: I/O Bank Voltage Rails

XCVU9P-L2FSGD2104E Power Net Name Voltage Connected To

Bank 61 VCC1V2_BTM 1.2V DDR4 C0 DQ[0:15], DQ[40:55]

Bank 62 VCC1V2_BTM 1.2V DDR4 C0 DQ[16:39], DQ[56:63]

Bank 63 VCC1V2_BTM 1.2V DDR4 C0 DQ[64:71], ADDR/CTRL

Bank 64 VCC1V2_BTM 1.2V USB, QSFP0,QSFP1, I2C, GPIO_MSP, SW_DP

Bank 65 VCC1V2_BTM 1.2V DDR4 C1 DQ[64:71], ADDR/CTRL

Bank 66 VCC1V2_BTM 1.2V DDR4 C1 DQ[32:63]

Bank 67 VCC1V8_BTM 1.2V DDR4 C1 DQ[0:31]

Bank 69 VCC1V2_TOP 1.2V DDR4_C2 DQ[32:71]

Bank 70 VCC1V2_TOP 1.2V DDR4 C2 DQ[40:47], ADDR/CTRL

Bank 71 VCC1V2_TOP 1.2V DDR4_C2 DQ[0:31

Bank 72 VCC1V2_TOP 1.2V DDR4 C3 DQ[64:71], ADDR/CTRL

Bank 73 VCC1V2_TOP 1.2V DDR4_C3 DQ[16:31], DQ[40:55]

Bank 74 VCC1V2_TOP 1.2V DDR4_C3 DQ[0:15], DQ[32:39], DQ[56:63]

DDR4 DIMM Memory

[Figure 2-1, callout 2, 3, 4, 5]

Four independent dual-rank DDR4 interfaces are available on the VCU1525 board. The
VCU1525 board is populated with four socketed single-rank Micron
MTA18ASF2G72PZ-2G3B1IG or Samsung M393A2K40BB1-CRC 16GB DDR4 UDIMMs. Each
DDR4 is 72-bits wide (64-bits plus support for ECC).

Memory interface-to-FPGA bank assignment is shown in Ta ble 3- 1. The DDR4 0.6V V
termination voltages are sourced from four independent TI TPS51200DR regulator circuits.

The VCU1525 DDR4 memory interfaces adhere to the constraints guidelines documented in
the "DDR3/DDR4 Design Guidelines" section of the UltraScale Architecture-Based FPGAs
Memory IP LogiCORE IP Product Guide (PG150) [Ref 3]. The VCU1525 board DDR4 memory
interfaces are 40 Ω impedance implementations.

For more details about the Micron DDR4 DIMM, see the Micron MTA18ASF2G72PZ-2G3B1IG
data sheet at the Micron website [Ref 7].

TT

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For more details about the Samsung DDR4 DIMM, see the Samsung M393A2K40BB1-CRC
data sheet at the Samsung website [Ref 8].

Chapter 3: Board Component Descriptions

X20038-110617

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Quad SPI Flash Memory

[Figure 2-1, callout 6]

Two Quad Serial Peripheral Interface (SPI) flash memory devices of the same type and wired
in parallel are provided on the VCU1525 board (U17 and U58). A field effect transistor (FET)
switch structure (U57 and U61) implements a chip-select enable mechanism, controlled by
the MSP432 board management controller (BMC). Only one Quad SPI device can be
enabled at a time.

The default selected (bank 0 configuration) Quad SPI flash memory is U17. Each Quad SPI
device provides 1 Gb of nonvolatile storage.

• Part number: MT25QU01GBB8E12-0SIT (Micron)

• Supply voltage: 1.8V

• Datapath width: 4 bits

• Data rate: variable

X-Ref Target - Figure 3-2

Figure 3-2 shows the linear Quad SPI flash memory circuitry on the VCU1525 board. For

more flash memory details, see the Micron MT25QU01GBB8E12-0SIT data sheet at the
Micron website [Ref 7].

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Figure 3-2: Quad SPI 1Gb Flash Memory

X-Ref Target - Figure 3-3

FT4232HQ

USB AB

J13

U27

ADBUS0
ADBUS1
ADBUS2
ADBUS3
ADBUS5

TXBN0304

U35

B1
B3
B2
B4

A1
A3
A2
A4
OE_B

3.3V L/S 1.8V

FT TCK
FT TDO
FT TDI

FT TMS
FT OE

XCVU9PFSGD2104

U13R

TCK
TDI
TDO
TMS

BANK 0

TCK
TDI
TDO

TMS

MSP432

U19

P3_0
P3_1
P3_2
P3_3
P3_4

TXBN0304

U33

B1
B3
B2
B4

A1
A3
A2
A4
OE_B

3.3V L/S 1.8V

MSP TCK
MSP TDI
MSP TDO

MSP TMS
MSP EN

PCIe EDGE

CN1

A5
A6
A7
A8

TXBN0304

U34

B1
B3
B2
B4

A1
A3
A2
A4

OE_B

3.3V L/S 1.8V

PEX TCK
PEX TDI
PEX TDO

PEX TMS

P10_4

BD. MGMT.

CONTROLLER

PEX OE

TCK
TDI
TDO

TMS

GPIO
PORT

TCK
TDI
TDO
TMS

X19965-031418

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Chapter 3: Board Component Descriptions

For details on bank 0 pins, see UltraScale Architecture Configuration User Guide (UG570)

[Ref 1].

USB JTAG Interface

[Figure 2-1, callout 7]

The VCU1525 board XCVU9P-L2FSGD2104E FPGA U13 is the only component in the Joint
Test Action Group (JTAG) chain. JTAG configuration is available through the USB-to-JTAG
FTDI FT4232HQ U27 bridge device connected to Micro-AB USB connector J13. The FTDI
JTAG signals are level-shifted through TXBN0304 device U35. The PCIe 16-lane edge
connector CN1 JTAG port is connected in parallel through level-shifter U34. GPIO port 3 of
the U19 MSP432 BMC is also connected through level-shifter U33. Each level-shifter enable
pin is controlled by the BMC to allow only one JTAG connection at a time.

JTAG configuration is allowed at any time regardless of the FPGA mode pin settings.

The JTAG chain block diagram is shown in Figure 3-3.

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Figure 3-3: VCU1525 JTAG Chain Block Diagram