Xilinx VCU128 User Manual

VCU128 Evaluaon Board

User Guide

UG1302 (v1.0) December 21, 2018

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Revision History...............................................................................................................4

Chapter 1: Introduction.............................................................................................. 5

Overview.......................................................................................................................................5

Additional Resources.................................................................................................................. 5

Block Diagram..............................................................................................................................6

Board Features............................................................................................................................ 6

Board Specifications....................................................................................................................8

Chapter 2: Board Setup and Configuration......................................................9

Electrostatic Discharge Caution.................................................................................................9

Board Component Location.......................................................................................................9

Default Switch and Jumper Settings....................................................................................... 13

Installing the Board in a PC Chassis........................................................................................14

FPGA Configuration...................................................................................................................16

Chapter 3: Board Component Descriptions................................................... 18

Overview.....................................................................................................................................18

Component Descriptions......................................................................................................... 18

UG1302 (v1.0) December 21, 2018 www.xilinx.com VCU128 Board User Guide 2

Appendix A: VITA 57.4 FMCP Connector Pinouts......................................... 93

Overview.....................................................................................................................................93

Appendix B: Xilinx Constraints File.................................................................... 94

Overview.....................................................................................................................................94

Appendix C: Regulatory and Compliance Information........................... 95

Overview.....................................................................................................................................95

CE Directives.............................................................................................................................. 95

CE Standards..............................................................................................................................95

Compliance Markings............................................................................................................... 96

Appendix D: Additional Resources and Legal Notices.............................97

Xilinx Resources.........................................................................................................................97

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Documentation Navigator and Design Hubs.........................................................................97

References..................................................................................................................................98

Please Read: Important Legal Notices................................................................................. 100

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Revision History

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The following table shows the revision history for this document.

Revision History

Section

12/21/2018 Version 1.0

Initial Xilinx release. N/A

Revision Summary

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Introduction

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Overview

The VCU128 board incorporates the VU37P high bandwidth memory (HBM) FPGA, which ulizes stacked silicon interconnect (SSI) technology to add HBM die next to the FPGA die on the package substrate. The VCU128 evaluaon board for the Xilinx® Virtex® UltraScale+™ FPGA provides a hardware environment for developing and evaluang designs targeng the UltraScale + XCVU37P-2FSVH2892E device. The VCU128 evaluaon board is equipped with many of the common board-level features needed for design development as listed here.

• DDR4, RLD-3, and QDR-IV component memory

• Ganged small form-factor pluggable (QSFP28) connectors

Chapter 1

• Sixteen-lane PCI Express® interface

• Ethernet PHY

• General purpose I/O

• UART interface

Addional features can be supported using modules compable with the VITA-57.4 (FMCP HSPC) connector on the VCU128 board.

Additional Resources

See Appendix D: Addional Resources and Legal Noces for references to documents, les, and resources relevant to the VCU128 evaluaon board.

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Chapter 1: Introduction

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Block Diagram

A block diagram of the VCU128 evaluaon board is shown in the following gure.

Figure 1: Evaluation Board Block Diagram

PCIE_EP_TX/RX[0:3] PCIE_CLK2

PCIE_EP_TX/RX[4:7]

PCIE_EP_TX/RX[8:11] PCIE_CLK1

PCIE_EP_TX/RX[12:15]

INIT LED DONE LED PROG_B PB

1.5V BATT. QSPI 2Gb

36-bit QDR-IV SDRAM

(shown at banks 68, 69)

36-bit DQB-port

235

not used

234

not used

233

not used

232

not used

231

not used

230

not used

229

not used

228

not used

227

226

225

224

36-bit DQA-port + common

36-bit QDR-IV SDRAM 4Mx36 Dual-Port

CY7C4142KV13_106FCXC

36-bit DQB-port

Bank 70

70 71 72 75 74 73 135

FMCP HSPC

LA[00:33]

XCVU37P-FSVH2892

HBM_43_PWR HBM_43_PWR

HBM_83

used

67 64

Not

GPIO 1.8V

ENET LED[0:7] PL_I2C0 BUS UART0, UART1 QSFP1, QSFP4 CTRL SMA_CLK OUT(P/N) SYSCTLR_UCA1 (TX/RX)

72-bit RLD-3 (2x32Mx36)

MT44K32M36RB-107E

Not

used

65 66

72-bit DDR4 Comp. Memory

MT40A512M16LY-075E

HBM_43

Not used

134

133

not used

132

131

130

not used

129

128

127

126

125

124

(4.5X512MX16)

QSFP1 TX/RX[1:4] QSFP1_SI570_CLOCK

QSFP2 TX/RX[1:4] QSFP2_SI570_CLOCK SI5328_CLOCK1

QSFP3 TX/RX[1:4] QSFP3_SI570_CLOCK SI5328_CLOCK2

QSFP4 TX/RX[1:4] QSFP4_SI570_CLOCK SMA_REFCLK_INPUT

FMCP_HSPC_DP[20:23] FMCP_HSPC_GBTCLK5

FMCP_HSPC_DP[16:19] FMCP_HSPC_GBTCLK4

FMCP_HSPC_DP[12:15] FMCP_HSPC_GBTCLK3

FMCP_HSPC_DP[8:11] FMCP_HSPC_GBTCLK2

FMCP_HSPC_DP[4:7] FMCP_HSPC_GBTCLK1

FMCP_HSPC_DP[0:3] FMCP_HSPC_GBTCLK0

System Controller

XC7Z010CLG225

GPIO

X21647-112818

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Board Features

The VCU128 evaluaon board features are listed here. Detailed informaon for each feature is provided in Chapter 3: Board Component Descripons.

• Virtex® UltraScale+™ XCVU37P-2FSVH2892E device

• Zynq®-7000 SoC XC7Z010 based system controller

• 4.5 GB DDR4 72-bit component memory interface (4.5 x [512 Mb x 16])

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• 144 Mb 36-bit dual-port QDR-IV component memory interface (1 x [4M x 36])

• 288 MB 72-bit RLD3 component memory interface (2 x [1.125 Gb x 36])

• 2 Gb Quad SPI ash conguraon memory

• QSFPF28 - Sixteen (16) GTY transceivers are allocated for a 1x4 QSFP cage

• USB JTAG interface (FTDI FT4232HL with a micro-AB USB connector)

• Clock sources:

○ SMA I/F clocks:

- FPGA bank 67 SMA clock P/N

○ QSFP clocks:

- Four Si570 I2C programmable clock oscillators (156.25 MHz default)

- QSFP clock recovery Si5328 input to GTY132 and GTY134

- QSFP external SMA di. clock input to GTY131

○ Memory I/F clocks:

- Three SiT9120A xed 100 MHz LVDS clock oscillators

○ PCIe

I/F clock:

- Fixed 100 MHz HCSL clock from PCI Express® edge input to 1-to-2 clock buer wired to GTY225 and GTY227

○ System controller clock:

- SiT8008A 33.33 MHz single-ended clock oscillator

• 96 GTY transceivers (24 Quads)

○ FMCP HSPC connector (twenty-four GTY transceivers)

○ 4x28 Gb/s QSFP+ connectors (eight GTY transceivers)

○ PCIe 16-lane edge connector (sixteen GTY transceivers)

○ Not used (forty-eight GTY transceivers)

• PCI Express® Endpoint connecvity

○ Gen1 (x1, x2, x4, x8, x16)

○ Gen2 (x1, x2, x4, x8, x16)

UG1302 (v1.0) December 21, 2018 www.xilinx.com VCU128 Board User Guide 7

○ Gen3 (x1, x2, x4, x8, x16)

○ Dual Gen4 (x1, x2, x4, x8)

• Ethernet PHY SGMII interface with RJ-45 connector

• Dual USB-to-UART bridge with micro-B USB connector (shared FTDI FT4232HL)

Chapter 1: Introduction

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• I2C bus

• Status LEDs

• User I/O (1 x push-buon switch, 8 x LED)

• VITA 57.4 FMC+ HSPC connector (DP[0:23], LA[0:33])

• Power management with I2C voltage monitoring through Intersil power controllers and GUI

• Conguraon opons:

○ Quad SPI ash memory

○ USB JTAG I/F (FTDI FT4232HL)

○ Plaorm cable USB II interface 2x7 2 mm keyed connector

Board Specifications

Dimensions

Height: 7.53 inch (19.14 cm)

Length: 9.50 inch (24.13 cm)

Thickness (±5%): 0.061 inch (0.1549 cm)

Note: A 3D model of this board is not available.

IMPORTANT

PCI Express® card.

! The VCU128 board height exceeds the standard 4.376-inch (11.15 cm) height of a

Environmental

Temperature

Operang: 0°C to +45°C, Storage: -25°C to +60°C

Humidity

10% to 90% non-condensing

UG1302 (v1.0) December 21, 2018 www.xilinx.com VCU128 Board User Guide 8

Operating Voltage

+12 VDC

Chapter 2

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Board Setup and Configuration

Electrostatic Discharge Caution

CAUTION! ESD can damage electronic components when they are improperly handled, and can result in total or intermient failures. Always follow ESD-prevenon procedures when removing and replacing components.

To prevent ESD damage:

• Use an ESD wrist or ankle strap and ensure that it makes skin contact. Connect the equipment end of the strap to an unpainted metal surface on the chassis.

• Avoid touching the adapter against your clothing. The wrist strap protects components from ESD on the body only.

• Handle the adapter by its bracket or edges only. Avoid touching the printed circuit board or the connectors.

• Put the adapter down only on an anstac surface such as the bag supplied in your kit.

• If you are returning the adapter to Xilinx® Product Support, place it back in its anstac bag immediately.

Board Component Location

The following gure shows the VCU128 board component locaons. Each numbered component shown in the gure is keyed to the table in Board Component Descripons.

IMPORTANT! The board component locaons gure is for visual reference only and might not reect the current revision of the board.

IMPORTANT! There could be mulple revisions of this board. The specic details concerning the dierences between revisions are not captured in this document. This document is not intended to be a reference design guide and the informaon herein should not be used as such. Always refer to the schemac, layout, and XDC les of the specic VCU128 version of interest for such details.

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Chapter 2: Board Setup and Configuration

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Figure 2: Evaluation Board Component Locations

Round callout references a component

on the front side of the board

Square callout references a component

on the back side of the board

X22144-121718

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Chapter 2: Board Setup and Configuration

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Board Component Descriptions

The following table idenes the components, references the respecve schemac page numbers, and links to a detailed funconal descripon of the components and board features in

Chapter 3: Board Component Descripons.

Table 1: Board Component Descriptions

Schematic

Callout Feature [U#] = Bottom Notes

1 Virtex UltraScale+ XCVU37P-2FSVH2892E

Device (with fan-sink on soldered FPGA)

2 GTY transceivers, Right-side Quads (twelve

quads)

3 GTY transceivers, Left-side Quads (twelve

quads)

4 DDR4 Component Memory, 72-bit DDR4

component memory I/F, (U17-U19), [U73, U74]

5 RLD3 Component Memory, RLD3 72-bit

component memory I/F (U37, U39)

6 QDR4 Component Memory (U40) Cypress CY7C4142KV13-106FCXC 27

7 Quad SPI Flash Memory (U46) Micron MT25QU02GCBB8E12-0SIT 3

8 System Controller, Zynq®-7000 SoC (U42) XC7Z010CLG225 48-50

9 System Controller Quad SPI Flash Memory

[U89]

10 DDR4 Component Memory I/F clock, fixed

100 MHz LVDS [U76]

11 RLD3 Component Memory I/F clock, fixed

100 MHz LVDS (U45)

12 QDR4 Component Memory I/F clock, fixed

100 MHz LVDS [U96]

13 Programmable QSFP1 Clock I2C, LVDS

[U95]

14 Programmable QSFP2 Clock I2C, LVDS

[U90]

15 Programmable QSFP3 Clock I2C, LVDS

[U82]

16 Programmable QSFP4 Clock I2C, LVDS

[U80]

17 QSFP Jitter Attenuated Clock, [U87] Silicon Labs SI5328B-C-GMR 40

18 User QSFP SMA Clock pair J24(P)/J26(N)

input to XCVU37P U1 GTY131 MGTREFCLK1P/N

19 Four 28 Gb/s zQSFP+ Module Connectors,

QSFP1-4 (J42), (J39), (J35), (J32) + 1x4 ganged cage

XCVU37P-2FSVH2892E Cofan 30-4811

Embedded within FPGA U1 14-15

Embedded within FPGA U1 16-17

5 x Micron MT40A256M16GE-075E 24-26

2 x Micron MT44K32M36RB-107E 29-30

Micron MT25QU02GCBB8E12-0SIT 49

SiTime SIT9120AI-2D3-33E100.0000 32

Silicon Labs SI570BAB0000544DG (default 156.250 MHz)

Rosenberger 32K10K-400L5 12

4 x TE 1551920-2 connectors with TE 2170745-2 cage with heatsink

Page

Number

38, 39

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Chapter 2: Board Setup and Configuration

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Table 1: Board Component Descriptions (cont'd)

Callout Feature [U#] = Bottom Notes

20 PCI Express Endpoint Connectivity,

PCI Express® 16-lane connector (P1)

21 PCI Express Endpoint Connectivity 100

MHz REFCLK 1-to-2 clock buffer, differential-to-LVDS [U94]

22 10/100/1000 Mb/s Tri-speed Ethernet PHY

with RJ45, SGMII mode only, [U62], (P2)

23 Ethernet PHY Status LEDs, LEDs are

integrated into P2 bezel

24 USB JTAG Interface, USB bridge (U8) with

mini-B USB connector (J2) and 2x7 2 mm prog. cable connector (J4)

25 I2C Bus, Topology, and Switches I2C0 bus

topology: I2C bus MUX [U55], 16-bit expansion port [U65]

26 I2C Bus, Topology, and Switches I2C0 bus

topology: 2 x I2C bus MUX [U53, U54]

28 User GPIO LEDs (DS2-DS9), active-High Lumex SML-LX0603GW-TR 47

29 User GPIO pushbutton, CPU reset (SW4),

active-High

30 Switches, program_B pushbutton, (SW2),

active-Low

31 FMCP Connector J18, (J18) Samtec ASP_184329_01 42-46

32 Board Power System Power Input

Connector, (J16)

33 Board Power System power input switch,

on/off slide switch (SW5)

34 Board Power System, power management

system (top and bottom)

35 Monitoring Voltage and Current, PMBus

2x3 R.A. male pin header (J1)

36 Configuration Options, FPGA U1

configuration mode DIP switch, (SW1)

37 PCI Express Endpoint Connectivity, lane

width select header, (J46)

38 Jumpers, FPGA POR_OVERRIDE select

header, (J14)

39 Jumpers, FPGA VCCINT select header, (J25) 1x3 0.1-inch male header Sullins PBC36SAAN 54

40 Jumpers, SYS CTLR RE-PROG header, (J43) 1x2 0.1-inch male header Sullins PBC36SAAN 50

16-lane card edge connector 41

ICS ICS85411AMLF 14

TI DP83867ISRGZ with Wurth 7499111221A RJ45 (with magnetics)

Wurth 7499111221A RJ45 integrated status LEDs 37

FTDI FT4232HL bridge Hirose ZX62D-AB-5P8 connector Molex 87832-1420

TI PCA9544ARGYR TI TCA6416APWR

2 x TI TCA9548APWR 36

E-Switch TL3301EF100QG 47

E-Switch TL3301EF100QG 3

2x6 Molex-39-30-1060 52

C&K 1201M2S3AQE2 52

Intersil power system 54-65

Amphenol 68021-406HLF 54

4-pole CTS 218-4LPSTRF 3

2x4 0.1-inch male header Sullins PBC36DAAN 41

1x3 0.1-inch male header Sullins PBC36SAAN 3

Schematic

Page

Number

UG1302 (v1.0) December 21, 2018 www.xilinx.com VCU128 Board User Guide 12

The VCU128 board schemacs are available for download from the VCU128 Evaluaon Kit website.

Chapter 2: Board Setup and Configuration

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Default Switch and Jumper Settings

Switches

Default switch sengs are listed in the following table. The switch locaons are shown in Figure

2. The following table also references the respecve schemac page numbers.

Table 2: Default Switch Settings

Switch Function Default Comments

SW5 On/Off SPST slide switch OFF Board shipped with power switch off 33 52

SW1 4-pole configuration

Default = SPI

SW2 FPGA_PROG_B P.B. NA U1 XCVU37P PROG_B (active low) 30 3

SW3 SYSCTLR_POR_B P.B. NA U42 XC7Z010 POR_B (active low) Near

SW4 CPU_RESET P.B. NA U1 XCVU37P USER P.B. (active high) 29 47

Notes:

1. DIP switch sections are active-High (connected net is pulled High when DIP switch is closed = 1).

SW1[1:4] =

0001

Position 1 = System Controller Enable SW1[2:4] = FPGA U1 mode M[2:0] = 001

Figure 2

Callout

36 3

Schematic

Page

Jumpers

Default jumper sengs are listed in the following table. Jumper header locaons are shown in

Figure 2. The following table also references the respecve schemac page numbers.

Table 3: Default Jumper Settings

Jumper Function Default Comments

J14 Power on reset (POR)

override

J25 VCCINT select 1-2 1-2: 0.85V; 2-3: 0.72V

J46 PCIe lane size select 7-8 16-lane configuration 37 41

J43 SYSCTLR RE-PROG Off U42 XCZU7010 MIO5 pin

Notes:

1. VCCINT select header J25 should always have a jumper block installed.

2-3 U1 POR_OVERRIDE pin

BG15 to GND

Figure 2

Callout

38 3

39 54

40 50

Schematic

Page

UG1302 (v1.0) December 21, 2018 www.xilinx.com VCU128 Board User Guide 13

Chapter 2: Board Setup and Configuration

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Installing the Board in a PC Chassis

The VCU128 board 12V power input circuitry allows 12V to be applied through one of two connectors, J16 (typically used with the stand-alone VCU128 power adapter) or JP1, as shown in the following gure.

Figure 3: 12V Power Entry

UG1302 (v1.0) December 21, 2018 www.xilinx.com VCU128 Board User Guide 14

Installaon of the VCU128 board inside a computer chassis is required when developing or tesng PCI Express® funconality. When the VCU128 board is used inside a computer chassis

(i.e., plugged in to a PCIe® slot), power is provided by choosing one of two mutually exclusive ATX power supply cables as described in this secon (use one cable or the other).

• The ATX power supply 4-pin (1x4) peripheral connector, which requires using the ATX adapter cable (see the following gure) to connect to J16 on the VCU128 board. The Xilinx part number for this cable is 2600304. See ATX Power Supply Adapter Cable.

X22058-121318

Chapter 2: Board Setup and Configuration

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Figure 4: ATX Power Supply Adapter Cable

To ATX 4-Pin Peripheral

Power Connector

To J16 on VCU128 Board

X21955-121918

• The ATX supply 8-pin (2x4) PCIe power connector, which plugs into JP1 on the VCU128 board.

Steps to Install Board

To install the board in a PC chassis:

1. On the VCU128 board, remove the ve screws retaining the ve rubber feet and standos,

and the PCIe bracket. Reinstall the PCIe® bracket using two of the previously removed screws.

2. Power down the host computer and remove the power cord from the PC.

3. Open the PC chassis following the instrucons provided with the PC.

4. The VCU128 board has a large cooling fan that requires two adjacent PCIe slots. Ensure the

slot adjacent to the front of the board is free of obstrucons.

5. Remove the PCIe expansion slot cover (at the back of the chassis) which aligns with the

VCU128 PCIe bracket, by removing the screws on the top and boom of the cover.

6. Plug the VCU128 board into the appropriate open slot.

7. Install the top mounng bracket screw into the PC expansion cover retainer bracket to secure

the VCU128 board in its slot.

8. If using the ATX supply 4-pin (1x4) peripheral connector, connect power to the VCU128

board using the ATX power supply adapter cable as shown in Figure 4.

a. Plug the 6-pin 2 x 3 Molex connector end of the adapter cable into J16 on the VCU128

board.

b. Plug the 4-pin 1 x 4 peripheral power connector from the ATX power supply into the 4-

pin adapter connector end of the cable.

CAUTION

! Do NOT plug a PC ATX power supply 6-pin connector into J16 on the VCU128 evaluaon board. The ATX 6-pin connector has a dierent pinout than J16. Connecng an ATX 6-pin connector into J16 damages the VCU128 evaluaon board and voids the board warranty.

c. Slide the VCU128 board power switch SW5 to the ON posion. The PC can now be

powered on.

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Chapter 2: Board Setup and Configuration

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9. If using the ATX supply 8-pin (2x4) PCIe power connector, plug the connector into VCU128

board JP1. The PC can now be powered on.

FPGA Configuration

The VCU128 board supports two of the ve UltraScale+™ FPGA conguraon modes:

• Quad SPI ash memory (2 Gb)

•

JTAG using:

○ USB JTAG conguraon port (U8 FT4232HL + USB J2 micro-AB)

○ Xilinx

Plaorm Cable USB II, 2 mm, keyed at cable header (J4)

Each conguraon interface corresponds to one or more conguraon modes and bus widths, as listed in the following table. The mode switches M2, M1, and M0 are on SW1 posions 2, 3, and 4, respecvely. The FPGA default mode seng M[2:0] = 001 selects the master SPI conguraon mode.

Table 4: Configuration Modes

Configuration Mode

Master SPI

JTAG

SW1 DIP Switch

Settings M[2:0]

101

Bus Width CCLK Direction

x1, x2, x4 Output

x1 NA

For complete details on conguring the FPGA, see UltraScale Architecture Conguraon User Guide (UG570). The following gure shows the conguraon mode DIP switch SW1 JTAG switch

posions.

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Chapter 2: Board Setup and Configuration

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Figure 5: SW1 JTAG Mode Settings

ON Position = 1

OFF Position = 0

SCEM2M1

1 2 3 4

SW1

X21648-121918

JTAG

The Vivado®, Xilinx® SDK, or third-party tools can establish a JTAG connecon to the XCVU37P FPGA through the FTDI FT4232 USB-to-JTAG/USB UART device (U8) connected to the microUSB connector (J2). Alternavely, a JTAG cable can be connected to the keyed at cable header (J4). JTAG iniated conguraon takes priority over the conguraon method selected through the FPGA mode pins M[2:0], wired to SW1 posions [2:4].

Quad SPI

To boot from the dual Quad SPI non-volale conguraon memory, follow these steps.

1. Store a valid XCVU37P FPGA boot image in the 2 Gbit Quad SPI ash device (U46)

connected to the FPGA bank 0 Quad SPI interface. See the VCU128 Restoring Flash Tutorial (XTP533) for informaon on programming the QSPI.

2. Set the boot mode pins SW1 M[2:0] as indicated in the conguraon modes table in FPGA

Conguraon for master SPI.

3. Power-cycle the VCU128 board. Mode SW1 is callout 36 in Figure 2.

See the VCU128 Soware Install and Board Setup Tutorial (XTP535) for more informaon.

See System Controller for an overview of query and control of select programmable board features such as clocks, FMCP funconality, and power systems. See the VCU128 System Controller Tutorial (XTP534) for more informaon.

UG1302 (v1.0) December 21, 2018 www.xilinx.com VCU128 Board User Guide 17

Chapter 3: Board Component Descriptions

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Chapter 3

Board Component Descriptions

Overview

This chapter provides a detailed funconal descripon of the board’s components and features.

Table 1 idenes the components, references the respecve schemac page numbers, and links

to the corresponding detailed funconal descripon in this chapter. Component locaons are shown in Figure 2.

Component Descriptions

Virtex UltraScale+ XCVU37P-2FSVH2892E Device

[Figure 2, callout 1]

The VCU128 board incorporates the VU37P high bandwidth memory (HBM) FPGA, which ulizes stacked silicon interconnect (SSI) technology to add HBM die next to the FPGA die on the package substrate. The VCU128 board is populated with the Virtex® UltraScale+™ XCVU37P-2FSVH2892E device. For more informaon on Virtex UltraScale+ FPGAs, see Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteriscs (DS923).

Encryption Key Battery Backup Circuit

The XCVU37P device U1 implements bitstream encrypon key technology. The VCU128 board provides the encrypon key backup baery circuit shown in the following gure.

UG1302 (v1.0) December 21, 2018 www.xilinx.com VCU128 Board User Guide 18

Chapter 3: Board Component Descriptions

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Figure 6: Encryption Key Backup Circuit

X21956-112918

The Seiko TS621E rechargeable 1.5V lithium buon-type baery B1 is soldered to the board with the posive output connected to the XCVU37P device U1 VBATT pin BD13. The baery supply current IBATT specicaon is 150 nA maximum when the board power is o. B1 is charged from the VCC1V8_BUS 1.8V rail through a series diode with a typical forward voltage drop of 0.38V and 4.7 KΩ current limit resistor. The nominal charging voltage is 1.42V.

I/O Voltage Rails

There are 12 I/O banks and 2 high-bandwidth memory (HBM) banks available on the XCVU37P device. The VCU128 board does not use the HBM banks. The voltages applied to the FPGA I/O banks on the VCU128 board are listed in the following table.

Table 5: I/O Bank Voltage Rails

FPGA (U1) Bank Power Supply Rail Net Name Voltage

Bank 0 VCC1V8 1.8V

HP bank 64 DDR4_VDDQ_1V2 1.2V

HP bank 65 DDR4_VDDQ_1V2 1.2V

HP bank 66 DDR4_VDDQ_1V2 1.2V

HP bank 67 VCC1V8 1.8V

HP bank 68 QDR4_VDDQ_1V2 1.2V

HP bank 69 QDR4_VDDQ_1V2 1.2V

HP bank 70 QDR4_VDDQ_1V2 1.2V

HP bank 71 VADJ 1.8V

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Table 5: I/O Bank Voltage Rails (cont'd)

FPGA (U1) Bank Power Supply Rail Net Name Voltage

HP bank 72 VADJ 1.8V

HP bank 73 RLD3_VDDQ_1V2 1.2V

HP bank 74 RLD3_VDDQ_1V2 1.2V

HP bank 75 RLD3_VDDQ_1V2 1.2V

HBM_43 (not used) VCCHBM/VCCAUX_HBM 1.2V/1.8V

HBM_83 (not used) VCCHBM/VCCAUX_HBM 1.2V/1.8V

DDR4 Component Memory

[Figure 2, callout 4]

The 4.5 GB DDR4 component memory system is comprised of ve 512 Mb x 16 DDR4 SDRAM devices implemented in clam-shell fashion located at U17-U19 (top) and U73-U74 (boom). Half of the U19 16-bits are used (4.5 x 16-bits = 72-bit wide interface).

• Manufacturer: Micron

• Part Number: MT40A512M16LY-075E

• Descripon:

○ 8 Gb (512 Mb x 16)

○ 1.2V 96-ball TFBGA

○ DDR4-2666

The VCU128 XCVU37P FPGA DDR4 interface performance is documented in the Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteriscs (DS923).

The 72-bit wide DDR4 memory system is connected to XCVU37P U1 HP banks 64, 65 and 66. The DDR4 0.6V VTT terminaon voltage (net DDR4_VTERM_0V6) is sourced from the TI TPS51200DR linear regulator U71. The DDR4 memory interface bank VREF pins are not connected, which, coupled with an XDC set_property INTERNAL VREF constraint, invoke the INTERNAL VREF mode. The connecons between the 72-bit interface DDR4 component memories and XCVU37P banks 64, 65, and 66 are listed in the following table.

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Table 6: DDR4 Memory 72-bit I/F to FPGA U1 Banks 64, 65, and 66

FPGA (U1) Pin

BM45 PL_DDR4_DQ0 POD12_DCI A3 DQ8 U74

BP44 PL_DDR4_DQ1 POD12_DCI B8 DQ9 U74

BP47 PL_DDR4_DQ2 POD12_DCI C3 DQ10 U74

BN45 PL_DDR4_DQ3 POD12_DCI C7 DQ11 U74

BM44 PL_DDR4_DQ4 POD12_DCI C2 DQ12 U74

BN44 PL_DDR4_DQ5 POD12_DCI C8 DQ13 U74

BN47 PL_DDR4_DQ6 POD12_DCI D3 DQ14 U74

BP43 PL_DDR4_DQ7 POD12_DCI D7 DQ15 U74

BN46 PL_DDR4_DQS0_T DIFF_POD12_DCI B7 UDQS_T U74

BP46 PL_DDR4_DQS0_C DIFF_POD12_DCI A7 UDQS_C U74

BN42 PL_DDR4_DM0_B POD12_DCI E2 NF/UDM_B/UDBI_B U74

BL45 PL_DDR4_DQ8 POD12_DCI G2 DQ0 U17

BK44 PL_DDR4_DQ9 POD12_DCI F7 DQ1 U17

BL46 PL_DDR4_DQ10 POD12_DCI H3 DQ2 U17

BK43 PL_DDR4_DQ11 POD12_DCI H7 DQ3 U17

BL43 PL_DDR4_DQ12 POD12_DCI H2 DQ4 U17

BJ44 PL_DDR4_DQ13 POD12_DCI H8 DQ5 U17

BL42 PL_DDR4_DQ14 POD12_DCI J3 DQ6 U17

BJ43 PL_DDR4_DQ15 POD12_DCI J7 DQ7 U17

BK45 PL_DDR4_DQS1_T DIFF_POD12_DCI G3 LDQS_T U17

BK46 PL_DDR4_DQS1_C DIFF_POD12_DCI F3 LDQS_C U17

BL47 PL_DDR4_DM1_B POD12_DCI E7 NF/LDM_B/LDBI_B U17

BK41 PL_DDR4_DQ16 POD12_DCI G2 DQ0 U74

BG44 PL_DDR4_DQ17 POD12_DCI F7 DQ1 U74

BG42 PL_DDR4_DQ18 POD12_DCI H3 DQ2 U74

BH44 PL_DDR4_DQ19 POD12_DCI H7 DQ3 U74

BH45 PL_DDR4_DQ20 POD12_DCI H2 DQ4 U74

BG45 PL_DDR4_DQ21 POD12_DCI H8 DQ5 U74

BG43 PL_DDR4_DQ22 POD12_DCI J3 DQ6 U74

BJ41 PL_DDR4_DQ23 POD12_DCI J7 DQ7 U74

BH46 PL_DDR4_DQS2_T DIFF_POD12_DCI G3 LDQS_T U74

BJ46 PL_DDR4_DQS2_C DIFF_POD12_DCI F3 LDQS_C U74

BH42 PL_DDR4_DM2_B POD12_DCI E7 NF/LDM_B/LDBI_B U74

BE43 PL_DDR4_DQ24 POD12_DCI G2 DQ0 U18

BF42 PL_DDR4_DQ25 POD12_DCI F7 DQ1 U18

BC42 PL_DDR4_DQ26 POD12_DCI H3 DQ2 U18

BF43 PL_DDR4_DQ27 POD12_DCI H7 DQ3 U18

BD42 PL_DDR4_DQ28 POD12_DCI H2 DQ4 U18

Schematic Net

Name

I/O Standard

Pin # Pin Name Ref. Des.

Component Memory

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Table 6: DDR4 Memory 72-bit I/F to FPGA U1 Banks 64, 65, and 66 (cont'd)

FPGA (U1) Pin

BF45 PL_DDR4_DQ29 POD12_DCI H8 DQ5 U18

BE44 PL_DDR4_DQ30 POD12_DCI J3 DQ6 U18

BF46 PL_DDR4_DQ31 POD12_DCI J7 DQ7 U18

BE45 PL_DDR4_DQS3_T DIFF_POD12_DCI G3 LDQS_T U18

BE46 PL_DDR4_DQS3_C DIFF_POD12_DCI F3 LDQS_C U18

BD41 PL_DDR4_DM3_B DIFF_POD12_DCI E7 NF/LDM_B/LDBI_B U18

BP32 PL_DDR4_DQ32 POD12_DCI G2 DQ0 U73

BP29 PL_DDR4_DQ33 POD12_DCI F7 DQ1 U73

BP31 PL_DDR4_DQ34 POD12_DCI H3 DQ2 U73

BP28 PL_DDR4_DQ35 POD12_DCI H7 DQ3 U73

BN32 PL_DDR4_DQ36 POD12_DCI H2 DQ4 U73

BM30 PL_DDR4_DQ37 POD12_DCI H8 DQ5 U73

BN31 PL_DDR4_DQ38 POD12_DCI J3 DQ6 U73

BL30 PL_DDR4_DQ39 POD12_DCI J7 DQ7 U73

BN29 PL_DDR4_DQS4_T DIFF_POD12_DCI G3 LDQS_T U73

BN30 PL_DDR4_DQS4_C DIFF_POD12_DCI F3 LDQS_C U73

BM28 PL_DDR4_DM4_B POD12_DCI E7 NF/LDM_B/LDBI_B U73

BL32 PL_DDR4_DQ40 POD12_DCI G2 DQ0 U19

BP34 PL_DDR4_DQ41 POD12_DCI F7 DQ1 U19

BN34 PL_DDR4_DQ42 POD12_DCI H3 DQ2 U19

BK33 PL_DDR4_DQ43 POD12_DCI H7 DQ3 U19

BL31 PL_DDR4_DQ44 POD12_DCI H2 DQ4 U19

BL33 PL_DDR4_DQ45 POD12_DCI H8 DQ5 U19

BM33 PL_DDR4_DQ46 POD12_DCI J3 DQ6 U19

BK31 PL_DDR4_DQ47 POD12_DCI J7 DQ7 U19

BL35 PL_DDR4_DQS5_T DIFF_POD12_DCI G3 LDQS_T U19

BM35 PL_DDR4_DQS5_C DIFF_POD12_DCI F3 LDQS_C U19

BM34 PL_DDR4_DM5_B POD12_DCI E7 NF/LDM_B/LDBI_B U19

BJ34 PL_DDR4_DQ48 POD12_DCI A3 DQ8 U18

BG35 PL_DDR4_DQ49 POD12_DCI B8 DQ9 U18

BH34 PL_DDR4_DQ50 POD12_DCI C3 DQ10 U18

BH35 PL_DDR4_DQ51 POD12_DCI C7 DQ11 U18

BJ33 PL_DDR4_DQ52 POD12_DCI C2 DQ12 U18

BF35 PL_DDR4_DQ53 POD12_DCI C8 DQ13 U18

BG34 PL_DDR4_DQ54 POD12_DCI D3 DQ14 U18

BF36 PL_DDR4_DQ55 POD12_DCI D7 DQ15 U18

BK34 PL_DDR4_DQS6_T DIFF_POD12_DCI B7 UDQS_T U18

BK35 PL_DDR4_DQS6_C DIFF_POD12_DCI A7 UDQS_C U18

Schematic Net

Name

I/O Standard

Pin # Pin Name Ref. Des.

Component Memory

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Table 6: DDR4 Memory 72-bit I/F to FPGA U1 Banks 64, 65, and 66 (cont'd)

FPGA (U1) Pin

BH32 PL_DDR4_DM6_B POD12_DCI E2 NF/UDM_B/UDBI_B U18

BF31 PL_DDR4_DQ56 POD12_DCI A3 DQ8 U73

BH30 PL_DDR4_DQ57 POD12_DCI B8 DQ9 U73

BJ31 PL_DDR4_DQ58 POD12_DCI C3 DQ10 U73

BG32 PL_DDR4_DQ59 POD12_DCI C7 DQ11 U73

BH31 PL_DDR4_DQ60 POD12_DCI C2 DQ12 U73

BF32 PL_DDR4_DQ61 POD12_DCI C8 DQ13 U73

BH29 PL_DDR4_DQ62 POD12_DCI D3 DQ14 U73

BF33 PL_DDR4_DQ63 POD12_DCI D7 DQ15 U73

BJ29 PL_DDR4_DQS7_T DIFF_POD12_DCI B7 UDQS_T U73

BK30 PL_DDR4_DQS7_C DIFF_POD12_DCI A7 UDQS_C U73

BG29 PL_DDR4_DM7_B POD12_DCI E2 NF/UDM_B/UDBI_B U73

BN51 PL_DDR4_DQ64 POD12_DCI A3 DQ8 U17

BM52 PL_DDR4_DQ65 POD12_DCI B8 DQ9 U17

BN50 PL_DDR4_DQ66 POD12_DCI C3 DQ10 U17

BL52 PL_DDR4_DQ67 POD12_DCI C7 DQ11 U17

BM48 PL_DDR4_DQ68 POD12_DCI C2 DQ12 U17

BL53 PL_DDR4_DQ69 POD12_DCI C8 DQ13 U17

BN49 PL_DDR4_DQ70 POD12_DCI D3 DQ14 U17

BL51 PL_DDR4_DQ71 POD12_DCI D7 DQ15 U17

BM49 PL_DDR4_DQS8_T DIFF_POD12_DCI B7 UDQS_T U17

BM50 PL_DDR4_DQS8_C DIFF_POD12_DCI A7 UDQS_C U17

BP48 PL_DDR4_DM8_B POD12_DCI E2 NF/UDM_B/UDBI_B U17

BF50 PL_DDR4_A0 SSTL12_DCI P3 A0 U17-U19 U73-U74

BD51 PL_DDR4_A1 SSTL12_DCI P7 A1 U17-U19 U73-U74

BG48 PL_DDR4_A2 SSTL12_DCI R3 A2 U17-U19 U73-U74

BE50 PL_DDR4_A3 SSTL12_DCI N7 A3 U17-U19 U73-U74

BE49 PL_DDR4_A4 SSTL12_DCI N3 A4 U17-U19 U73-U74

BE51 PL_DDR4_A5 SSTL12_DCI P8 A5 U17-U19 U73-U74

BF53 PL_DDR4_A6 SSTL12_DCI P2 A6 U17-U19 U73-U74

BG50 PL_DDR4_A7 SSTL12_DCI R8 A7 U17-U19 U73-U74

BF51 PL_DDR4_A8 SSTL12_DCI R2 A8 U17-U19 U73-U74

BG47 PL_DDR4_A9 SSTL12_DCI R7 A9 U17-U19 U73-U74

BF47 PL_DDR4_A10 SSTL12_DCI M3 A10/AP U17-U19 U73-U74

BG49 PL_DDR4_A11 SSTL12_DCI T2 A11 U17-U19 U73-U74

BF48 PL_DDR4_A12 SSTL12_DCI M7 A12/BC_B U17-U19 U73-U74

BF52 PL_DDR4_A13 SSTL12_DCI T8 A13 U17-U19 U73-U74

Schematic Net

Name

I/O Standard

Pin # Pin Name Ref. Des.

COMMON

Component Memory

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Table 6: DDR4 Memory 72-bit I/F to FPGA U1 Banks 64, 65, and 66 (cont'd)

FPGA (U1) Pin

BE54 PL_DDR4_BA0 SSTL12_DCI N2 BA0 U17-U19 U73-U74

BE53 PL_DDR4_BA1 SSTL12_DCI N8 BA1 U17-U19 U73-U74

BG54 PL_DDR4_BG0 SSTL12_DCI M2 BG0 U17-U19 U73-U74

BG53 PL_DDR4_WE_B SSTL12_DCI L2 WE_B/A14 U17-U19 U73-U74

BJ54 PL_DDR4_RAS_B SSTL12_DCI L8 RAS_B/A16 U17-U19 U73-U74

BH54 PL_DDR4_CAS_B SSTL12_DCI M8 CAS_B_A15 U17-U19 U73-U74

BK53 PL_DDR4_CK_T DIFF_SSTL12_DCI K7 CK_T U17-U19 U73-U74

BK54 PL_DDR4_CK_C DIFF_SSTL12_DCI K8 CK_C U17-U19 U73-U74

BH52 PL_DDR4_CKE SSTL12_DCI K2 CKE U17-U19 U73-U74

BG52 PL_DDR4_ACT_B SSTL12_DCI L3 ACT_B U17-U19 U73-U74

BJ53 PL_DDR4_TEN SSTL12_DCI N9 TEN U17-U19 U73-U74

BJ52 PL_DDR4_ALERT_B SSTL12_DCI P9 ALERT_B U17-U19 U73-U74

BL48 PL_DDR4_PARITY SSTL12_DCI T3 PAR U17-U19 U73-U74

BH50 PL_DDR4_RESET_B LVCMOS12 P1 RESET_B U17-U19 U73-U74

BH49 PL_DDR4_ODT SSTL12_DCI K3 ODT U17-U19 U73-U74

BP49 PL_DDR4_CS_B SSTL12_DCI L7 CS_B U17-U19 U73-U74

Schematic Net

Name

I/O Standard

Pin # Pin Name Ref. Des.

Component Memory

The VCU128 DDR4 memory component interfaces adhere to the constraints guidelines documented in the “DDR3/DDR4 Design Guidelines” secon of the UltraScale Architecture-Based FPGAs Memory IP LogiCORE IP Product Guide (PG150). The VCU128 board DDR4 memory component interface is a 40Ω impedance implementaon.

For more informaon on the internal VREF, see the “Supply Voltages for the SelectIO Pins VREF” and the “Internal VREF” secons in the UltraScale Architecture SelectIO Resources User Guide (UG571). For more details about the Micron DDR4 component memory, see the Micron MT40A512M16LY data sheet at the Micron Technology website.

RLD3 Component Memory

[Figure 2, callout 5]

The 288 MB RLD3 72-bit wide component memory system is comprised of two 36-bit 1.125 Gb RLDRAM3 devices located at U39 and U37.

• Manufacturer: Micron

• Part Number: MT44K32M36RB-107E

• Descripon:

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○ 1.125 Gb (32 Mb x 36)

Chapter 3: Board Component Descriptions

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○ 1.2V 168-ball BGA

○ Up to RL3-1866

The VCU128 XCVU37P FPGA RLDRAM3 interface performance is documented in the Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteriscs (DS923).

This memory system is connected to the XCVU37P HP banks 73, 74, and 75. The RLD3 0.6V VTT terminaon voltage (net RLD3_VTERM_0V6) is sourced from TI TPS51200DR linear regulator U92. The RLD3 memory interface bank VREF pins are not connected, which, coupled with an XDC set_property INTERNAL_VREF constraint, invoke the INTERNAL VREF mode. The connecons between the RLD3 component memories and XCVU37P banks 73, 74, and 75 are listed in the following table.

Table 7: RLD3 Memory 72-bit I/F to FPGA U1 Banks 73, 74, and 75

FPGA (U1)

K29 RLD3_72B_DQ0 SSTL12 D11 DQ0 U39

J30 RLD3_72B_DQ1 SSTL12 E10 DQ1 U39

K32 RLD3_72B_DQ2 SSTL12 C8 DQ2 U39

J31 RLD3_72B_DQ3 SSTL12 C10 DQ3 U39

L29 RLD3_72B_DQ4 SSTL12 C12 DQ4 U39

L31 RLD3_72B_DQ5 SSTL12 B9 DQ5 U39

L30 RLD3_72B_DQ6 SSTL12 B11 DQ6 U39

J32 RLD3_72B_DQ7 SSTL12 A8 DQ7 U39

K31 RLD3_72B_DQ8 SSTL12 A10 DQ8 U39

G30 RLD3_72B_DQ9 SSTL12 J10 DQ9 U39

H30 RLD3_72B_DQ10 SSTL12 K11 DQ10 U39

F31 RLD3_72B_DQ11 SSTL12 K13 DQ11 U39

G28 RLD3_72B_DQ12 SSTL12 L8 DQ12 U39

H29 RLD3_72B_DQ13 SSTL12 L10 DQ13 U39

G31 RLD3_72B_DQ14 SSTL12 L12 DQ14 U39

G32 RLD3_72B_DQ15 SSTL12 M9 DQ15 U39

H32 RLD3_72B_DQ16 SSTL12 M11 DQ16 U39

F28 RLD3_72B_DQ17 SSTL12 N8 DQ17 U39

E33 RLD3_72B_DQ18 SSTL12 D3 DQ18 U39

F29 RLD3_72B_DQ19 SSTL12 E4 DQ19 U39

E29 RLD3_72B_DQ20 SSTL12 C6 DQ20 U39

C32 RLD3_72B_DQ21 SSTL12 C4 DQ21 U39

F33 RLD3_72B_DQ22 SSTL12 C2 DQ22 U39

D30 RLD3_72B_DQ23 SSTL12 B5 DQ23 U39

D32 RLD3_72B_DQ24 SSTL12 B3 DQ24 U39

D29 RLD3_72B_DQ25 SSTL12 A6 DQ25 U39

Schematic Net

Name

I/O Standard

Pin # Pin Name Ref. Des.

Component Memory

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Table 7: RLD3 Memory 72-bit I/F to FPGA U1 Banks 73, 74, and 75 (cont'd)

FPGA (U1)

D31 RLD3_72B_DQ26 SSTL12 A4 DQ26 U39

A31 RLD3_72B_DQ27 SSTL12 J4 DQ27 U39

B32 RLD3_72B_DQ28 SSTL12 K3 DQ28 U39

A33 RLD3_72B_DQ29 SSTL12 K1 DQ29 U39

B30 RLD3_72B_DQ30 SSTL12 L6 DQ30 U39

A30 RLD3_72B_DQ31 SSTL12 L4 DQ31 U39

C28 RLD3_72B_DQ32 SSTL12 L2 DQ32 U39

C29 RLD3_72B_DQ33 SSTL12 M5 DQ33 U39

A29 RLD3_72B_DQ34 SSTL12 M3 DQ34 U39

B28 RLD3_72B_DQ35 SSTL12 N6 DQ35 U39

G42 RLD3_72B_DQ36 SSTL12 D11 DQ0 U37

G41 RLD3_72B_DQ37 SSTL12 E10 DQ1 U37

H42 RLD3_72B_DQ38 SSTL12 C8 DQ2 U37

G40 RLD3_72B_DQ39 SSTL12 C10 DQ3 U37

H43 RLD3_72B_DQ40 SSTL12 C12 DQ4 U37

J42 RLD3_72B_DQ41 SSTL12 B9 DQ5 U37

H40 RLD3_72B_DQ42 SSTL12 B11 DQ6 U37

J40 RLD3_72B_DQ43 SSTL12 A8 DQ7 U37

J41 RLD3_72B_DQ44 SSTL12 A10 DQ8 U37

D44 RLD3_72B_DQ45 SSTL12 J10 DQ9 U37

F45 RLD3_72B_DQ46 SSTL12 K11 DQ10 U37

F44 RLD3_72B_DQ47 SSTL12 K13 DQ11 U37

D46 RLD3_72B_DQ48 SSTL12 L8 DQ12 U37

F46 RLD3_72B_DQ49 SSTL12 L10 DQ13 U37

E44 RLD3_72B_DQ50 SSTL12 L12 DQ14 U37

E46 RLD3_72B_DQ51 SSTL12 M9 DQ15 U37

G45 RLD3_72B_DQ52 SSTL12 M11 DQ16 U37

H45 RLD3_72B_DQ53 SSTL12 N8 DQ17 U37

B46 RLD3_72B_DQ54 SSTL12 D3 DQ18 U37

A46 RLD3_72B_DQ55 SSTL12 E4 DQ19 U37

C43 RLD3_72B_DQ56 SSTL12 C6 DQ20 U37

B45 RLD3_72B_DQ57 SSTL12 C4 DQ21 U37

A45 RLD3_72B_DQ58 SSTL12 C2 DQ22 U37

C45 RLD3_72B_DQ59 SSTL12 B5 DQ23 U37

C44 RLD3_72B_DQ60 SSTL12 B3 DQ24 U37

D42 RLD3_72B_DQ61 SSTL12 A6 DQ25 U37

A43 RLD3_72B_DQ62 SSTL12 A4 DQ26 U37

D40 RLD3_72B_DQ63 SSTL12 J4 DQ27 U37

Schematic Net

Name

I/O Standard

Pin # Pin Name Ref. Des.

Component Memory

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Table 7: RLD3 Memory 72-bit I/F to FPGA U1 Banks 73, 74, and 75 (cont'd)

FPGA (U1)

C40 RLD3_72B_DQ64 SSTL12 K3 DQ28 U37

A39 RLD3_72B_DQ65 SSTL12 K1 DQ29 U37

A41 RLD3_72B_DQ66 SSTL12 L6 DQ30 U37

B41 RLD3_72B_DQ67 SSTL12 L4 DQ31 U37

B40 RLD3_72B_DQ68 SSTL12 L2 DQ32 U37

D41 RLD3_72B_DQ69 SSTL12 M5 DQ33 U37

B42 RLD3_72B_DQ70 SSTL12 M3 DQ34 U37

E41 RLD3_72B_DQ71 SSTL12 N6 DQ35 U37

J29 RLD3_72B_DM0 SSTL12 B7 DM0 U39

A28 RLD3_72B_DM1 SSTL12 M7 DM1 U39

G43 RLD3_72B_DM2 SSTL12 B7 DM0 U37

A40 RLD3_72B_DM3 SSTL12 M7 DM1 U37

D39 RLD3_72B_A0 SSTL12 E2 A0 U37, U39

A38 RLD3_72B_A1 SSTL12 F5 A1 U37, U39

B38 RLD3_72B_A2 SSTL12 F4 A2 U37, U39

J34 RLD3_72B_A3 SSTL12 F9 A3 U37, U39

K34 RLD3_72B_A4 SSTL12 F10 A4 U37, U39

K37 RLD3_72B_A5 SSTL12 F12 A5 U37, U39

C38 RLD3_72B_A6 SSTL12 G3 A6 U37, U39

E36 RLD3_72B_A7 SSTL12 F1 A7 U37, U39

B35 RLD3_72B_A8 SSTL12 G11 A8 U37, U39

L35 RLD3_72B_A9 SSTL12 F13 A9 U37, U39

D34 RLD3_72B_A10 SSTL12 H13 A10 U37, U39

E39 RLD3_72B_A11 SSTL12 D1 A11 U37, U39

A35 RLD3_72B_A12 SSTL12 H11 A12 U37, U39

C35 RLD3_72B_A13 SSTL12 D13 A13 U37, U39

E37 RLD3_72B_A14 SSTL12 H3 A14 U37, U39

E38 RLD3_72B_A15 SSTL12 G2 A15 U37, U39

C37 RLD3_72B_A16 SSTL12 H4 A16 U37, U39

B36 RLD3_72B_A17 SSTL12 H10 A17 U37, U39

F34 RLD3_72B_A18 SSTL12 G12 A18 U37, U39

J37 RLD3_72B_A19 SSTL12 H1 A19 U37, U39

C39 RLD3_72B_A20 SSTL12 F2 NF_A20 U37, U39

C34 RLD3_72B_BA0 SSTL12 G9 BA0 U37, U39

B37 RLD3_72B_BA1 SSTL12 G5 BA1 U37, U39

A36 RLD3_72B_BA2 SSTL12 H8 BA2 U37, U39

D36 RLD3_72B_BA3 SSTL12 H6 BA3 U37, U39

D37 RLD3_72B_WE_B SSTL12 F6 WE_B U37, U39

Schematic Net

Name

I/O Standard

Pin # Pin Name Ref. Des.

Component Memory

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Chapter 3: Board Component Descriptions

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Table 7: RLD3 Memory 72-bit I/F to FPGA U1 Banks 73, 74, and 75 (cont'd)

FPGA (U1)

E34 RLD3_72B_REF_B SSTL12 F8 REF_B U37, U39

G37 RLD3_72B_CK_P SSTL12 H7 CK U37, U39

F38 RLD3_72B_CK_N SSTL12 G7 CK_B U37, U39

D35 RLD3_72B_RESET_B SSTL12 A13 RESET_B U37, U39

A34 RLD3_72B_CS_B SSTL12 E12 CS_B U37, U39

H37 RLD3_72B_DK0_P DIFF_SSTL12 D7 DK0 U39

H38 RLD3_72B_DK0_N DIFF_SSTL12 C7 DK0_B U39

H34 RLD3_72B_DK1_P DIFF_SSTL12 K7 DK1 U39

H35 RLD3_72B_DK1_N DIFF_SSTL12 L7 DK1_B U39

G38 RLD3_72B_DK2_P DIFF_SSTL12 D7 DK0 U37

F39 RLD3_72B_DK2_N DIFF_SSTL12 C7 DK0_B U37

G35 RLD3_72B_DK3_P DIFF_SSTL12 K7 DK1 U37

G36 RLD3_72B_DK3_N DIFF_SSTL12 L7 DK1_B U37

L33 RLD3_72B_QK0_P DIFF_SSTL12 D9 QK0 U39

K33 RLD3_72B_QK0_N DIFF_SSTL12 E8 QK0_B U39

H33 RLD3_72B_QK1_P DIFF_SSTL12 K9 QK1 U39

G33 RLD3_72B_QK1_N DIFF_SSTL12 J8 QK1_B U39

E31 RLD3_72B_QK2_P DIFF_SSTL12 D5 QK2 U39

E32 RLD3_72B_QK2_N DIFF_SSTL12 E6 QK2_B U39

C30 RLD3_72B_QK3_P DIFF_SSTL12 K5 QK3 U39

B31 RLD3_72B_QK3_N DIFF_SSTL12 J6 QK3_B U39

K41 RLD3_72B_QK4_P DIFF_SSTL12 D9 QK0 U37

K42 RLD3_72B_QK4_N DIFF_SSTL12 E8 QK0_B U37

J44 RLD3_72B_QK5_P DIFF_SSTL12 K9 QK1 U37

H44 RLD3_72B_QK5_N DIFF_SSTL12 J8 QK1_B U37

E42 RLD3_72B_QK6_P DIFF_SSTL12 D5 QK2 U37

E43 RLD3_72B_QK6_N DIFF_SSTL12 E6 QK2_B U37

F40 RLD3_72B_QK7_P DIFF_SSTL12 K5 QK3 U37

F41 RLD3_72B_QK7_N DIFF_SSTL12 J6 QK3_B U37

F30 RLD3_72B_QVLD0 SSTL12 J12 QVLD0 U39

E28 RLD3_72B_QVLD1 SSTL12 J2 QVLD1 U39

D45 RLD3_72B_QVLD2 SSTL12 J12 QVLD0 U37

A44 RLD3_72B_QVLD3 SSTL12 J2 QVLD1 U37

Schematic Net

Name

I/O Standard

Pin # Pin Name Ref. Des.

Component Memory

UG1302 (v1.0) December 21, 2018 www.xilinx.com VCU128 Board User Guide 28

The VCU128 RLD3 72-bit memory component interface adheres to the constraints guidelines documented in the "RLD3 Design Guidelines" secon of the UltraScale Architecture-Based FPGAs Memory IP LogiCORE IP Product Guide (PG150). The VCU128 RLD3 memory component interface is a 40Ω impedance implementaon.

Chapter 3: Board Component Descriptions

Send Feedback

For more informaon on the internal VREF, see the "Supply Voltages for the SelectIO Pins", “VREF”, and “Internal VREF” secons in the UltraScale Architecture SelectIO Resources User Guide (UG571). For more details about the Micron RLD3 component memory, see the Micron MT44K32M36RB Data Sheet at the Micron Technology website.

QDR4 Component Memory

[Figure 2, callout 6]

The 4.5 GB QDR4 component memory system is comprised of one 144-Mbit density (4M × 36) QDR4 SRAM device located at U40.

•

Manufacturer: Cypress

•

Part Number: CY7C4142KV13_106FCXC

•

Descripon:

○ 144-Mbit density (4M × 36)

○ Dual independent 36-bit bidireconal double data rate (DDR) data ports

○ Supports concurrent read/write transacons on both ports

○ Single address port used to control both data ports

○ 1.2V 361-ball FCBGA

○ Maximum operang frequency of 1066 MHz

The VCU128 XCVU37P FPGA QDR IV interface performance is documented in the Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteriscs (DS923).

The 72-bit wide QDR4 memory is connected to XCVU37P U1 HP banks 68, 69, and 70. The QDR4 memory interface bank VREF pins are not connected, which, coupled with an XDC set_property INTERNAL VREF constraint, invoke the INTERNAL VREF mode. The connecons between the 72-bit interface QDR4 component memories and XCVU37P banks 68, 69, and 70 are listed in the following table.

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Chapter 3: Board Component Descriptions

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Table 8: QDR4 Memory 72-bit I/F to FPGA U1 Banks 68, 69, and 70

FPGA (U1) Pin

BM14 QDR4_DQA0 C8 DQA0

BM13 QDR4_DQA1 B7 DQA1

BN15 QDR4_DQA2 C6 DQA2

BN12 QDR4_DQA3 D5 DQA3

BM15 QDR4_DQA4 D7 DQA4

BP13 QDR4_DQA5 A4 DQA5

BP14 QDR4_DQA6 F5 DQA6

BM12 QDR4_DQA7 A6 DQA7

BL15 QDR4_DQA8 A8 DQA8

BM9 QDR4_DQA9 H3 DQA9

BK9 QDR4_DQA10 H5 DQA10

BL10 QDR4_DQA11 J2 DQA11

BK10 QDR4_DQA12 J4 DQA12

BL8 QDR4_DQA13 B2 DQA13

BN10 QDR4_DQA14 E2 DQA14

BM10 QDR4_DQA15 G2 DQA15

BN9 QDR4_DQA16 G4 DQA16

BJ9 QDR4_DQA17 B5 DQA17

BL12 QDR4_DQA18 C12 DQA18

BK14 QDR4_DQA19 B13 DQA19

BJ12 QDR4_DQA20 C14 DQA20

BK15 QDR4_DQA21 D15 DQA21

BL13 QDR4_DQA22 D13 DQA22

BH14 QDR4_DQA23 A16 DQA23

BH15 QDR4_DQA24 F15 DQA24

BJ14 QDR4_DQA25 A14 DQA25

BJ13 QDR4_DQA26 A12 DQA26

BE9 QDR4_DQA27 H17 DQA27

BE10 QDR4_DQA28 H15 DQA28

BG13 QDR4_DQA29 J18 DQA29

BE11 QDR4_DQA30 J16 DQA30

BF10 QDR4_DQA31 B18 DQA31

BG12 QDR4_DQA32 E18 DQA32

BG9 QDR4_DQA33 G18 DQA33

BG10 QDR4_DQA34 G16 DQA34

BF12 QDR4_DQA35 B15 DQA35

Schematic Net

Name

I/O Standard

QDR4 A-side Data

Component Memory

Pin # Pin Name

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Chapter 3: Board Component Descriptions

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Table 8: QDR4 Memory 72-bit I/F to FPGA U1 Banks 68, 69, and 70 (cont'd)

FPGA (U1) Pin

BP12 QDR4_DKA0_P F4 DKA0_P

BP11 QDR4_DKA0_N F3 DKA0_N

BH10 QDR4_DKA1_P F16 DKA1_P

BH9 QDR4_DKA1_N F17 DKA1_N

BP9 QDR4_QKA0_P C4 QKA0_P

BP8 QDR4_QKA0_N D3 QKA0_N

BJ11 QDR4_QKA1_P C16 QKA1_P

BK11 QDR4_QKA1_N D17 QKA1_N

BM8 QDR4_QVLDA0 C3 QVLDA0

BK13 QDR4_QVLDA1 C17 QVLDA1

BM3 QDR4_LDA_N H8 LDA_N

BM4 QDR4_RWA_N H10 RWA_N

R522(GND)

R519(GND)

H15 QDR4_DQB0 U8 DQB0

J15 QDR4_DQB1 V7 DQB1

J12 QDR4_DQB2 U6 DQB2

J11 QDR4_DQB3 T5 DQB3

H14 QDR4_DQB4 T7 DQB4

G13 QDR4_DQB5 W4 DQB5

J14 QDR4_DQB6 P5 DQB6

H12 QDR4_DQB7 W6 DQB7

H13 QDR4_DQB8 W8 DQB8

G11 QDR4_DQB9 M3 DQB9

E12 QDR4_DQB10 M5 DQB10

F10 QDR4_DQB11 L2 DQB11

E11 QDR4_DQB12 L4 DQB12

D10 QDR4_DQB13 V2 DQB13

E9 QDR4_DQB14 R2 DQB14

F9 QDR4_DQB15 N2 DQB15

F11 QDR4_DQB16 N4 DQB16

D11 QDR4_DQB17 V5 DQB17

E14 QDR4_DQB18 U12 DQB18

A14 QDR4_DQB19 V13 DQB19

D15 QDR4_DQB20 U14 DQB20

B15 QDR4_DQB21 T15 DQB21

Schematic Net

Name

QDR4_DINVA0 D8 DINVA0

QDR4_DINVA1 D12 DINVA1

I/O Standard

QDR4 A-side Control

QDR4 B-side Data

Component Memory

Pin # Pin Name

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Chapter 3: Board Component Descriptions

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Table 8: QDR4 Memory 72-bit I/F to FPGA U1 Banks 68, 69, and 70 (cont'd)

FPGA (U1) Pin

F13 QDR4_DQB22 T13 DQB22

C15 QDR4_DQB23 W16 DQB23

F15 QDR4_DQB24 P15 DQB24

A15 QDR4_DQB25 W14 DQB25

F14 QDR4_DQB26 W12 DQB26

C12 QDR4_DQB27 M17 DQB27

A11 QDR4_DQB28 M15 DQB28

B13 QDR4_DQB29 L18 DQB29

B12 QDR4_DQB30 L16 DQB30

A8 QDR4_DQB31 V18 DQB31

A9 QDR4_DQB32 R18 DQB32

B11 QDR4_DQB33 N18 DQB33

B10 QDR4_DQB34 N16 DQB34

A10 QDR4_DQB35 V15 DQB35

K14 QDR4_DKB0_P P4 DKB0_P

K13 QDR4_DKB0_N P3 DKB0_N

C10 QDR4_DKB1_P P16 DKB1_P

C9 QDR4_DKB1_N P17 DKB1_N

H10 QDR4_QKB0_P U4 QKB0_P

G10 QDR4_QKB0_N T3 QKB0_N

E13 QDR4_QKB1_P U16 QKB1_P

D12 QDR4_QKB1_N T17 QKB1_N

D9 QDR4_QVLDB0 U3 QVLDB0

D14 QDR4_QVLDB1 U17 QVLDB1

BL2 QDR4_LDB_N H12 LDB_N

BL3 QDR4_RWB_N L10 RWB_N

R606(GND)

R602(GND)

BF5 QDR4_A0 F10 A0

BF1 QDR4_A1 G10 A1

BE1 QDR4_A2 N10 A2

BE3 QDR4_A3 G7 A3

BE4 QDR4_A4 G13 A4

BE5 QDR4_A5 J7 A5

BE6 QDR4_A6 J13 A6

BF2 QDR4_A7 L7 A7

Schematic Net

Name

QDR4_DINVB0 T8 DINVB0

QDR4_DINVB1 T12 DINVB1

I/O Standard

QDR4 B-side Control

Common

Component Memory

Pin # Pin Name

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Chapter 3: Board Component Descriptions

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Table 8: QDR4 Memory 72-bit I/F to FPGA U1 Banks 68, 69, and 70 (cont'd)

FPGA (U1) Pin

BF3 QDR4_A8 L13 A8

BG2 QDR4_A9 N7 A9

BG3 QDR4_A10 N13 A10

BG4 QDR4_A11 M8 A11

BG5 QDR4_A12 M12 A12

BF7 QDR4_A13 F8 A13

BF8 QDR4_A14 F12 A14

BG7 QDR4_A15 P8 A15

BG8 QDR4_A16 P12 A16

BJ7 QDR4_A17 L9 A17

BH7 QDR4_A18 L11 A18_36M

BK8 QDR4_A19 J9 A19_72M

BJ8 QDR4_A20 J11 A20_144M

BJ6 QDR4_A21 G9 A21_288M

BK5 QDR4_A22 G11 A22_576M

BH6 QDR4_A23 N9 A23_1152M

BK4 QDR4_A24 N11 A24_2304M

BK6 QDR4_AP P10 AP

BJ1 QDR4_AINV M10 AINV

BH5 QDR4_CK_P J10 CK_P

BH4 QDR4_CK_N K10 CK_N

BJ3 QDR4_LBK0_N A10 LBK0_N

BH1 QDR4_LBK1_N B10 LBK1_N

BH2 QDR4_CFG_N D10 CFG_N

BJ2 QDR4_PE_N V10 PE_N

BK1 QDR4_RST_N K18 RST_N

Notes:

1. Resistors to GND are 100Ω.

Schematic Net

Name

QDR4 U40 ZQ_ZT pin W10 is wired to 220Ω R604 to GND

I/O Standard

Pin # Pin Name

Component Memory

UG1302 (v1.0) December 21, 2018 www.xilinx.com VCU128 Board User Guide 33

The VCU128 QDR-IV dual independent 36-bit bidireconal data port memory component interfaces adhere to the constraints guidelines documented in the "QDR-IV Design Guidelines" secon of the UltraScale Architecture-Based FPGAs Memory IP LogiCORE IP Product Guide (PG150). The VCU128 QDR-IV memory component interface is a 40Ω impedance implementaon.

For more informaon on the internal VREF, see the "Supply Voltages for the SelectIO Pins", “VREF”, and “Internal VREF” secons in the UltraScale Architecture SelectIO Resources User Guide (UG571). For more details about the Cypress QDR-IV component memory, see the Cypress CY7C4142KV13_106FCXC Data Sheet at the Cypress Semiconductor website.

Chapter 3: Board Component Descriptions

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Quad SPI Flash Memory

[Figure 2, callout 7]

VCU128 boards host a Micron MT25QU02GCBB8E12-0SIT serial NOR ash Quad SPI ash memory capable of holding the boot image for the XCVU37P FPGA. This interface supports the QSPI32 boot mode as dened in the UltraScale Architecture Conguraon User Guide (UG570).

The Quad SPI ash memory U46 provides 2 Gb of non-volale storage that can be used for conguraon and data storage.

• Part number: MT25QU02GCBB8E12-0SIT (Micron)

• Supply voltage: 1.8V

• Datapath width: 4 bits

• Data rate: various depending on single/dual/quad mode

The Quad SPI circuitry is shown in the following gure.

Figure 7: Quad SPI (2 Gbit) Flash Memory

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UG1302 (v1.0) December 21, 2018 www.xilinx.com VCU128 Board User Guide 34

The connecons between the Quad SPI ash memory and the XCVU37P FPGA are listed in the following table.

Chapter 3: Board Component Descriptions

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Table 9: Quad-SPI Component Connections to FPGA U1

XCVC37P (U1) Pin Net Name

Pin # Pin Name

AW15 QSPI_DQ0 D3 DQ0

AY15 QSPI_DQ1 D2 DQ1

AY14 QSPI_DQ2 C4 DQ2_W_B

AY13 QSPI_DQ3 D4 DQ3_RST_HLD_B

BD14 QSPI _CLK B2 C

BC15 QSPI_CS_B C2 S_B

U46 Quad SPI

The UltraScale Architecture Conguraon User Guide (UG570) provides FPGA conguraon details. For more Quad SPI component informaon, see the Micron MT25QU02GCBB8E12-0SIT data sheet at the Micron Technology website.

USB JTAG Interface

[Figure 2, callout 24]

JTAG conguraon is provided through a dual-funcon FTDI FT4232HL USB-to-JTAG/UART bridge device (U8) where a host computer accesses the VCU128 board JTAG chain through a type-A (PC host side) to micro-AB (VCU128 board side J2) USB cable.

A 2 mm JTAG header (J4) is also provided in parallel for access by Xilinx® download cables, such as the Plaorm Cable USB II. JTAG iniated conguraon takes priority over the conguraon method selected through the FPGA mode pins M[2:0], wired to SW1 posions [2:4]. The JTAG chain of the VCU128 board is shown in the following gure.

UG1302 (v1.0) December 21, 2018 www.xilinx.com VCU128 Board User Guide 35

FTDI

Send Feedback

USB JTAG (U8)

JTAG 2 mm Conn.

(J4)

TCK

TMS

TDI

TDO

TDI

TMS

TCK

Chapter 3: Board Component Descriptions

Figure 8: JTAG Chain Block Diagram

U50

1.8V3.3V

Level-shift

TCK TMS

TDI TDO

FPGA

SPST Bus Switch U72

J18

FMC+ HSPC

Connector

TMS TCK TDO

U75

1.8V 3.3V Level-shift

N.C.

TDI

X21649-110618

FMCP Connector JTAG Bypass

When an FMC is aached to the VCU128 board FMC+ HSPC connector J18, it is automacally added to the JTAG chain through the electronically controlled single-pole single-throw (SPST) switch U72. The SPST switch is in a normally closed state and transions to an open state when the FMC is aached. Switch U72 adds an aached FMC to the FPGA JTAG chain as determined by the FMCP_HSPC_PRSNT_M2C_B signal.

IMPORTANT

bypass jumper to ensure that the JTAG chain connects to the FPGA U1.

The JTAG connecvity on the VCU128 board allows a host computer to download bitstreams to the FPGA using the Xilinx® tools. In addion, the JTAG connector allows debug tools such as the Vivado® serial I/O analyzer or a soware debugger to access the FPGA. The Xilinx tools can also program the Quad SPI ash memory.

! The aached FMC must implement a TDI-to-TDO connecon through a device or

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Chapter 3: Board Component Descriptions

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USB UART Interface

[Figure 2, callout 24]

The FT4232HL U8 mul-funcon USB-UART on the VCU128 board provides three level-shied UART connecons through the single micro-AB USB connector J2.

• Channel A is congured in JTAG mode to support the JTAG chain

• Channel B implements 4-wire UART0 (level-shied) FPGA U1 bank 67 connecons

• Channel C implements 4-wire UART1 (level-shied) FPGA U1 bank 67 connecons

• Channel D implements 2-wire (level-shied) SYSCTLR U42 bank 501 connecons

The USB UART interface circuit is shown in the following gure. The FTDI FT4232HL data sheet is available on the Future Technology Devices Internaonal Ltd. website.

Figure 9: FTDI USB JTAG/UART Circuit

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Clock Generation

[Figure 2, callout 10-18]

The VCU128 evaluaon board clock sources to the FPGA are listed in the following table.

Table 10: Board Clock Sources

Clock Name Clock Ref. Des. Description

Memory Interface Clocks

DDR4 clock 100 MHz U76 SiTime SiT9120AI 3.3V fixed frequency

QDR4 clock 100 MHz U96 SiTime SiT9120AI 3.3V fixed frequency

RLD3 clock 100 MHz U45 SiTime SiT9120AI 3.3V fixed frequency

QSFP Interface Clocks

QSFP1 clock 156.250 MHz U95 Silicon Labs Si570 3.3V LVDS I2C

QSFP2 clock 156.250 MHz U90 Silicon Labs Si570 3.3V LVDS I2C

QSFP3 clock 156.250 MHz U82 Silicon Labs Si570 3.3V LVDS I2C

QSFP4 clock 156.250 MHz U80 Silicon Labs Si570 3.3V LVDS I2C

SMA GTY REFCLK and User Clock

QSFP GTY131 REFCLK1 SMA clock SMA J24 (P)/SMA J26 (N) Bank 131 series capacitor coupled SMA clock

FPGA U1 bank 67 GPIO user SMA clock SMA J12 (P)/SMA J13 (N) Bank 67 QBC direct connect GPIO

QSFP1/2 recovery clocks

QSFP1/2 jitter attenuated clock U87 Silicon Labs Si5328B LVDS precision clock,

100.000 MHz (DDR4_CLK_100MHZ_P/N)

100.000 MHz (QDR4_CLK_100MHZ_P/N)

100.000 MHz (RLD3_CLK_100MHZ_P/N)

programmable oscillator, 156.250 MHz default. (QSFP1_SI570_CLOCK_P/N)

programmable oscillator, 156.250 MHz default. (QSFP2_SI570_CLOCK_P/N)

programmable oscillator, 156.250 MHz default. (QSFP3_SI570_CLOCK_P/N)

programmable oscillator, 156.250 MHz default. (QSFP4_SI570_CLOCK_P/N)

(SMA_REFCLK_INPUT_P/N)

SMA )SMA_CLK_OUTPUT_P/N)

multiplier/jitter attenuator. See Jitter Attenuated Clock (SI5328_CLOCK1/2_P/N)

UG1302 (v1.0) December 21, 2018 www.xilinx.com VCU128 Board User Guide 38

The following table lists the VCU128 clock sources-to-FPGA U1 connecons.

Table 11: Clock Sources to XCVU37P FPGA U1 Connections

Clock Source Device/

U#.Pin#

SIT9120AI/U76.4 DDR4_CLK_100MHZ_P LVDS BH51

SIT9120AI/U76.5 DDR4_CLK_100MHZ_N LVDS BJ51

SIT9120AI/U96.4 QDR4_CLK_100MHZ_P LVDS BJ4

Schematic Net Name I/O Standard FPGA (U1) Pin

Memory Interface Clocks

Chapter 3: Board Component Descriptions

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Table 11: Clock Sources to XCVU37P FPGA U1 Connections (cont'd)

Clock Source Device/

U#.Pin#

Schematic Net Name I/O Standard FPGA (U1) Pin

SIT9120AI/U96.5 QDR4_CLK_100MHZ_N LVDS BK3

SIT9120AI/U45.4 RLD3_CLK_100MHZ_P LVDS F35

SIT9120AI/U45.5 RLD3_CLK_100MHZ_N LVDS F36

QSFP Interface Clocks

SI570/U95.4 QSFP1_SI570_CLOCK_P

SI570/U95.5 QSFP1_SI570_CLOCK_N

SI570/U90.4 QSFP2_SI570_CLOCK_P

SI570/U90.5 QSFP2_SI570_CLOCK_N

SI570/U82.4 QSFP3_SI570_CLOCK_P

SI570/U82.5 QSFP3_SI570_CLOCK_N

SI570/U80.4 QSFP4_SI570_CLOCK_P

SI570/U80.5 QSFP4_SI570_CLOCK_N

SMA GTY REFCLK and User Clock

SMA J24.1 SMA_REFCLK_INPUT_P

SMA J26.1 SMA_REFCLK_INPUT_N

SMA J12.1 SMA_CLK_OUTPUT_P

SMA J13.1 SMA_CLK_OUTPUT_N

QSFP1/2 Recovery Clocks

SI5328B/U87.29 SI5328_CLOCK1_P

SI5328B/U87.28 SI5328_CLOCK1_P

SI5328B/U87.35 SI5328_CLOCK2_P

SI5328B/U87.34 SI5328_CLOCK2_P

Notes:

1. Series capacitor coupled, MGT connections I/O standard is not applicable.

2. Signal amplitude not to exceed FPGA U1 bank 67 VCCO = VCC1V8 rail = 1.8V.

P42

P43

T42

T43

Y42

Y43

AB42

AB43

AA40

AA41

BK26

BL25

R40

R41

W40

W41

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DDR4 Interface Clock

[Figure 2, callout 10]

The VCU128 evaluaon board has a SiTime 100 MHz xed frequency low-jier 3.3V LVDS dierenal oscillator (U76) connected to FPGA U1 HP bank 66 DDR4 interface GC pins BH51 (P) and BJ51 (N) and is series capacitor coupled.

• Fixed frequency oscillator: SiTime SIT9120AI-2D3-33E100.0000 (100 MHz)

• 0.6 ps RMS phase jier (random) over 12 kHz to 20 MHz bandwidth

• 3.3V LVDS dierenal output

The DDR4 interface xed frequency clock circuit is shown in the following gure.

Figure 10: DDR4 Interface Clock

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[Figure 2, callout 18]

The VCU128 board provides a pair of SMAs for dierenal user clock input into FPGA U1 GTY bank 131. The P-side SMA J24 signal SMA_REFCLK_INPUT_P is connected to FPGA U1 GTY bank 131 MGTREFCLK1P pin AA40, with the N-side SMA J26 signal SMA_REFCLK_INPUT_N connected to U1 GTY bank 131 MGTREFCLK1N pin AA41. The transceiver reference clock pin absolute input voltage range is –0.5V min. to 1.3V max. The user SMA MGT clock circuit is shown in the following gure.

Figure 17: QSFP SMA Clock

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User SMA Clock

[Figure 2, callout 27]

The VCU128 board provides a pair of SMAs for dierenal user clock I/O on FPGA U1 HP bank

67. The P-side SMA J12 net SMA_CLK_OUTPUT_P is connected to FPGA U1 HP bank 67 QBC pin BK26. The N-side SMA J13 net SMA_CLK_OUTPUT_N is connected to FPGA U1 HP bank 67 QBC pin BL25. Bank 67 VCC1V8 VCCO is nominally 1.8V. Any signal connected to the SMA_CLK_OUTPUT SMA connectors in input mode must be equal to or less than the VCCO for bank 67. This value must be conrmed prior to applying signals to the SMA_CLK_OUTPUT connectors.

Figure 18: User SMA Clock

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Jitter Attenuated Clock

[Figure 2, callout 17]

The VCU128 board includes a Silicon Labs Si5328B jier aenuator U87 on the back side of the board. FPGA U1 bank 67 implements two QSFP RX dierenal clocks (QSFP1_RECCLK_P, pin BH26 and QSFP1_RECCLK_N, pin BH25, and QSFP2_RECCLK_P, pin BJ26 and QSFP2_RECCLK_N, pin BK25) for jier aenuaon.

The jier aenuated clock pair (SI5328_CLOCK1_C_P (U87 output pin 28), SI5328_CLOCK1_C_N (U87 output pin 29) is routed as a reference clock to FPGA U1 QSFP2 I/F GTY Quad 134 inputs MGTREFCLK1P (U1 pin R40) and MGTREFCLK1N (U1 pin R41).

The jier aenuated clock pair (SI5328_CLOCK2_C_P (U87 output pin 35), SI5328_CLOCK2_C_N (U87 output pin 34) is routed as a reference clock to FPGA U1 QSFP3 I/F GTY Quad 132 inputs MGTREFCLK1P (U1 pin W40) and MGTREFCLK1N (U1 pin W41).

The primary purpose of this clock is to support synchronous protocols, such as common packet radio interface (CPRI) or open base staon architecture iniave (OBSAI). These synchronous protocols perform clock recovery from user-supplied QSFP/QSFP+ modules, and use the jier aenuated recovered clock to drive the reference clock inputs of a GTY transceiver.

The jier aenuated clock circuit is shown in the following gure.

Figure 19: QSFP Recovery Clock

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The SI5328B U87 I2C interface is connected to port 1 of the I2C0 bus TCA9548A U53 bus switch and can be congured by either the U42 system controller or U1 FPGA IP.

The system controller congures SI5328B U87 in free-run mode or automacally switches over to one of two recovered clock inputs for synchronous operaon. Enabling the jier aenuaon feature requires addional user programming through the I2C bus. The Silicon Labs Si570 and Si5328B data sheets are available on the Silicon Labs website.

GTY Transceivers

The GTY transceivers in the XCVU37P are grouped into four channels or quads. The XCVU37P has twelve GTY quads on the le side of the device and twelve GTY Quads on the right side of the device.

The VCU128 board provides access to 14 of the 24 GTY Quads:

• Four of the GTY Quads are wired to QSFP[1:4] Module Connectors (J42, J39, J35, J32)

• Six of the GTY Quads are wired to FMC+ HSPC connector DP[0:23] (J18)

• Four of the GTY Quads are wired to the PCIe 16-lane edge connector (P1)

• Ten GTY Quads are not used (GTYs 130, 133, 228-235)

The reference clock for a Quad can be sourced from the Quad above or the Quad below the GTY Quad of interest.

Right-side Quads

The ten connected GTY Quads on the right side of the XCVU37P FPGA are described in this secon (MGTY133 and MGTY130 are not used).

Quad 135

• MGTREFCLK0 – QSFP1_SI570_CLOCK_P/N

• MGTREFCLK1 – NC

• Four GTY transceivers allocated to QSFP1_TX/RX[1:4]_P/N

Quad 134

• MGTREFCLK0 – QSFP2_SI570_CLOCK_P/N

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• MGTREFCLK1 – SI5328_CLOCK1_C_P/N

• Four GTY transceivers allocated to QSFP2_TX/RX[1:4]_P/N

Quad 132

MGTREFCLK0 – QSFP3_SI570_CLOCK_P/N

•

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• MGTREFCLK1 – SI5328_CLOCK2_C_P/N

• Four GTY transceivers allocated to QSFP3_TX/RX[1:4]_P/N

Quad 131

• MGTREFCLK0 – QSFP4_SI570_CLOCK_P/N

• MGTREFCLK1 – SMA_REFCLK_INPUT_P/N

• Four GTY transceivers allocated to QSFP4_TX/RX[1:4]_P/N

Quad 129

• MGTREFCLK0 - FMCP_HSPC_GBTCLK5_M2C_P/N

• NC

• Four GTY transceivers allocated to FMCP_HSPC_DP[20:23]

Quad 128

• MGTREFCLK0 - FMCP_HSPC_GBTCLK4_M2C_P/N

• NC

• Four GTY transceivers allocated to FMCP_HSPC_DP[16:19]

Quad 127

• MGTREFCLK0 – FMCP_HSPC_GBTCLK3_M2C_P/N

• NC

• Four GTY transceivers allocated to FMCP_HSPC_DP[12:15]

Quad 126

• MGTREFCLK0 – FMCP_HSPC_GBTCLK2_M2C_P/N

• NC

• Four GTY transceivers allocated to FMCP_HSPC_DP[8:11]

Quad 125

• MGTREFCLK0 – FMCP_HSPC_GBTCLK1_M2C_P/N

• NC

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• Four GTY transceivers allocated to FMCP_HSPC_DP[4:7]

Quad 124

• MGTREFCLK0 – FMCP_HSPC_GBTCLK0_M2C_P/N

• NC

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• Four GTY transceivers allocated to FMCP_HSPC_DP[0:3]

The XCVU37P right-side GTY transceiver interface assignments are shown in the following

gure.

Figure 20: XCVU37P Right-side GTY Transceiver Assignments

BANK 135

MGTY_135_0 MGTY_135_1 MGTY_135_2

MGTY_135_3 MGTY_135_REFCLK0 MGTY_135_REFCLK1

BANK 134

MGTY_134_0

MGTY_134_1

MGTY_134_2

MGTY_134_3 MGTY_134_REFCLK0 MGTY_134_REFCLK1

BANK 132

MGTY_132_0

MGTY_132_1

MGTY_132_2

MGTY_132_3 MGTY_132_REFCLK0 MGTY_132_REFCLK1

BANK 131

MGTY_131_0

MGTY_131_1

MGTY_131_2

MGTY_131_3 MGTY_131_REFCLK0 MGTY_131_REFCLK1

QSFP1_TX1/RX1 QSFP1_TX2/RX2 QSFP1_TX3/RX3 QSFP1_TX4/RX4 QSFP1_SI570_CLOCK NC

QSFP2_TX1/RX1 QSFP2_TX2/RX2 QSFP2_TX3/RX3 QSFP2_TX4/RX4 QSFP2_SI570_CLOCK SI5328_CLOCK1_C

QSFP3_TX1/RX1 QSFP3_TX2/RX2 QSFP3_TX3/RX3 QSFP3_TX4/RX4 QSFP3_SI570_CLOCK SI5328_CLOCK2_C

QSFP4_TX1/RX1 QSFP4_TX2/RX2 QSFP4_TX3/RX3 QSFP4_TX4/RX4 QSFP4_SI570_CLOCK SMA_REFCLK_INPUT

BANK 128

MGTY_128_0 MGTY_128_1 MGTY_128_2

MGTY_128_3 MGTY_128_REFCLK0 MGTY_128_REFCLK1

BANK 127

MGTY_127_0

MGTY_127_1

MGTY_127_2

MGTY_127_3 MGTY_127_REFCLK0 MGTY_127_REFCLK1

BANK 126

MGTY_126_0

MGTY_126_1

MGTY_126_2

MGTY_126_3 MGTY_126_REFCLK0 MGTY_126_REFCLK1

BANK 125

MGTY_125_0

MGTY_125_1

MGTY_125_2

MGTY_125_3 MGTY_125_REFCLK0 MGTY_125_REFCLK1

FMCP_HSPC_DP16 FMCP_HSPC_DP17 FMCP_HSPC_DP18 FMCP_HSPC_DP19 FMCP_HSPC_GBTCLK4_M2C NC

FMCP_HSPC_DP12 FMCP_HSPC_DP13 FMCP_HSPC_DP14 FMCP_HSPC_DP15 FMCP_HSPC_GBTCLK3_M2C NC

FMCP_HSPC_DP8 FMCP_HSPC_DP9 FMCP_HSPC_DP10 FMCP_HSPC_DP11 FMCP_HSPC_GBTCLK2_M2C NC

FMCP_HSPC_DP4 FMCP_HSPC_DP5 FMCP_HSPC_DP6 FMCP_HSPC_DP7 FMCP_HSPC_GBTCLK1_M2C NC

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BANK 129

MGTY_129_0 MGTY_129_1 MGTY_129_2

MGTY_129_3 MGTY_129_REFCLK0 MGTY_129_REFCLK1

FMCP_HSPC_DP20 FMCP_HSPC_DP21 FMCP_HSPC_DP22 FMCP_HSPC_DP23 FMCP_HSPC_GBTCLK5_M2C NC

BANK 124

MGTY_124_0 MGTY_124_1 MGTY_124_2

MGTY_124_3 MGTY_124_REFCLK0 MGTY_124_REFCLK1

FMCP_HSPC_DP0 FMCP_HSPC_DP1 FMCP_HSPC_DP2 FMCP_HSPC_DP3 FMCP_HSPC_GBTCLK0_M2C NC

Right-side GTY Transceiver Connectivity

The following tables list the connecvity of the ten XCVU37P FPGA U1 right-side GTY transceivers.

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Table 12: XCVU37P U1 GTY Transceiver Bank 135 Connections

MGT

Bank

GTY bank

135

Notes:

1. Series 0.01 μF capacitor coupled.

FPGA

(U1)

G48 MGTYTXP0_135 QSFP1_TX1_P 36 TX1P

G49

G53 MGTYRXP0_135 QSFP1_RX1_P 17 RX1P

G54 MGTYRXN0_135 QSFP1_RX1_N 18 RX1N

E48 MGTYTXP1_135 QSFP1_TX2_P 3 TX2P

E49 MGTYTXN1_135 QSFP1_TX2_N 2 TX2N

F51 MGTYRXP1_135 QSFP1_RX2_P 22 RX2P

F52 MGTYRXN1_135 QSFP1_RX2_N 21 RX2N

C48 MGTYTXP2_135 QSFP1_TX3_P 33 TX3P

C49 MGTYTXN2_135 QSFP1_TX3_N 34 TX3N

E53 MGTYRXP2_135 QSFP1_RX3_P 14 RX3P

E54 MGTYRXN2_135 QSFP1_RX3_N 15 RX3N

A49 MGTYTXP3_135 QSFP1_TX4_P 6 TX4P

A50 MGTYTXN3_135 QSFP1_TX4_N 5 TX4N

D51 MGTYRXP3_135 QSFP1_RX4_P 25 RX4P

D52 MGTYRXN3_135 QSFP1_RX4_N 24 RX4N

P42 MGTREFCLK0P_135 QSFP_SI570_CLOCK_P

P43 MGTREFCLK0N_135 QSFP_SI570_CLOCK_N

M42 MGTREFCLK1P_135

M43 MGTREFCLK1N_135

FPGA (U1) Pin

Name

MGTYTXN0_135 QSFP1_TX1_N 37 TX1N

Schematic Net

Name

NC NC NC NC

Connected

4 OUT

5 OUT_B

Pin Name

Connected

Device

QSFP1 J42

U95 SI570 I2C

prog. osc.

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Table 13: XCVU37P U1 GTY Transceiver Bank 134 Connections

MGT

Bank

GTY bank

134

Notes:

1. Series 0.01uF capacitor coupled.

FPGA

(U1)

L48 MGTYTXP0_134 QSFP2_TX1_P 36 TX1P

L49 MGTYTXN0_134 QSFP2_TX1_N 37 TX1N

L53 MGTYRXP0_134 QSFP2_RX1_P 17 RX1P

L54 MGTYRXN0_134 QSFP2_RX1_N 18 RX1N

L44 MGTYTXP1_134 QSFP2_TX2_P 3 TX2P

L45 MGTYTXN1_134 QSFP2_TX2_N 2 TX2N

K51 MGTYRXP1_134 QSFP2_RX2_P 22 RX2P

K52 MGTYRXN1_134 QSFP2_RX2_N 21 RX2N

K46 MGTYTXP2_134 QSFP2_TX3_P 33 TX3P

K47 MGTYTXN2_134 QSFP2_TX3_N 34 TX3N

J53 MGTYRXP2_134 QSFP2_RX3_P 14 RX3P

J54 MGTYRXN2_134 QSFP2_RX3_N 15 RX3N

J48 MGTYTXP3_134 QSFP2_TX4_P 6 TX4P

J49 MGTYTXN3_134 QSFP2_TX4_N 5 TX4N

H51 MGTYRXP3_134 QSFP2_RX4_P 25 RX4P

H52 MGTYRXN3_134 QSFP2_RX4_N 24 RX4N

T42 MGTREFCLK0P_134 QSFP2_SI570_CLOCK_P

T43 MGTREFCLK0N_134 QSFP2_SI570_CLOCK_N

R40 MGTREFCLK1P_134 SI5328_CLOCK1_C_P

R41 MGTREFCLK1N_134 SI5328_CLOCK1_C_N

FPGA (U1) Pin

Name

Schematic Net

Name

Connected

4 OUT

5 OUT_B

28 CKOUT1_P

29 CKOUT1_N

Pin Name

Connected

Device

U90 SI570 I2C

prog. osc.

U87 SI5328B

jitter atten.

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Table 14: XCVU37P U1 GTY Transceiver Bank 132 Connections

MGT

Bank

GTY bank

132

Notes:

1. Series 0.01uF capacitor coupled.

FPGA

(U1)

V46 MGTYTXP0_132 QSFP3_TX1_P 36 TX1P

V47

U53 MGTYRXP0_132 QSFP3_RX1_P 17 RX1P

U54 MGTYRXN0_132 QSFP3_RX1_N 18 RX1N

U44 MGTYTXP1_132 QSFP3_TX2_P 3 TX2P

U45 MGTYTXN1_132 QSFP3_TX2_N 2 TX2N

U49 MGTYRXP1_132 QSFP3_RX2_P 22 RX2P

U50 MGTYRXN1_132 QSFP3_RX2_N 21 RX2N

T46 MGTYTXP2_132 QSFP3_TX3_P 33 TX3P

T47 MGTYTXN2_132 QSFP3_TX3_N 34 TX3N

T51 MGTYRXP2_132 QSFP3_RX3_P 14 RX3P

T52 MGTYRXN2_132 QSFP3_RX3_N 15 RX3N

R44 MGTYTXP3_132 QSFP3_TX4_P 6 TX4P

R45 MGTYTXN3_132 QSFP3_TX4_N 5 TX4N

R53 MGTYRXP3_132 QSFP3_RX4_P 25 RX4P

R54 MGTYRXN3_132 QSFP3_RX4_N 24 RX4N

Y42 MGTREFCLK0P_132 QSFP3_SI570_CLOCK_P

Y43 MGTREFCLK0N_132 QSFP3_SI570_CLOCK_N

W40 MGTREFCLK1P_132 SI5328_CLOCK2_C_P

W41 MGTREFCLK1N_132 SI5328_CLOCK2_C_N

FPGA (U1) Pin

Name

MGTYTXN0_132 QSFP3_TX1_N 37 TX1N

Schematic Net

Name

Connected

4 OUT

5 OUT_B

35 CKOUT2_P

34 CKOUT2_N

Pin Name

Connected

Device

QSFP2 J35

U82 SI570 I2C

prog. osc.

U87 SI5328B

jitter atten.

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Table 15: XCVU37P U1 GTY Transceiver Bank 131 Connections

MGT

Bank

GTY bank

131

Notes:

1. Series 0.01uF capacitor coupled.

FPGA

(U1)

AA44 MGTYTXP0_131 QSFP4_TX1_P 36 TX1P

AA45

AA53 MGTYRXP0_131 QSFP4_RX1_P 17 RX1P

AA54 MGTYRXN0_131 QSFP4_RX1_N 18 RX1N

Y46 MGTYTXP1_131 QSFP4_TX2_P 3 TX2P

Y47 MGTYTXN1_131 QSFP4_TX2_N 2 TX2N

Y51 MGTYRXP1_131 QSFP4_RX2_P 22 RX2P

Y52 MGTYRXN1_131 QSFP4_RX2_N 21 RX2N

W48 MGTYTXP2_131 QSFP4_TX3_P 33 TX3P

W49 MGTYTXN2_131 QSFP4_TX3_N 34 TX3N

W53 MGTYRXP2_131 QSFP4_RX3_P 14 RX3P

W54 MGTYRXN2_131 QSFP4_RX3_N 15 RX3N

W44 MGTYTXP3_131 QSFP4_TX4_P 6 TX4P

W45 MGTYTXN3_131 QSFP4_TX4_N 5 TX4N

V51 MGTYRXP3_131 QSFP4_RX4_P 25 RX4P

V52 MGTYRXN3_131 QSFP4_RX4_N 24 RX4N

AB42 MGTREFCLK0P_131 QSFP4_SI570_CLOCK_P

AB43 MGTREFCLK0N_131 QSFP4_SI570_CLOCK_N

AA40 MGTREFCLK1P_131 SMA_REFCLK_INPUT_P

AA41 MGTREFCLK1N_131 SMA_REFCLK_INPUT_N

FPGA (U1) Pin

Name

MGTYTXN0_131 QSFP4_TX1_N 37 TX1N

Schematic Net

Name

Connected

4 OUT

5 OUT_B

1 SIG

Pin Name

Connected

Device

QSFP2 J32

U80 SI570 I2C

prog. osc.

SMA J24 (P) SMA J26 (N)

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Table 16: XCVU37P U1 GTY Transceiver Bank 129 Connections

GTY

129

FPGA

(U1)

AG48 MGTYTXP0_129 FMCP_HSPC_DP20_C2M_P Z8 DP20_C2M_P

AG49 MGTYTXN0_129 FMCP_HSPC_DP20_C2M_N Z9 DP20_C2M_N

AG53 MGTYRXP0_129 FMCP_HSPC_DP20_M2C_P M14 DP20_M2C_P

AG54 MGTYRXN0_129 FMCP_HSPC_DP20_M2C_N M15 DP20_M2C_N

AG44 MGTYTXP1_129 FMCP_HSPC_DP21_C2M_P Y6 DP21_C2M_P

AG45 MGTYTXN1_129 FMCP_HSPC_DP21_C2M_N Y7 DP21_C2M_N

AF51 MGTYRXP1_129 FMCP_HSPC_DP21_M2C_P M10 DP21_M2C_P

AF52 MGTYRXN1_129 FMCP_HSPC_DP21_M2C_N M11 DP21_M2C_N

AF46 MGTYTXP2_129 FMCP_HSPC_DP22_C2M_P Z4 DP22_C2M_P

AF47 MGTYTXN2_129 FMCP_HSPC_DP22_C2M_N Z5 DP22_C2M_N

AE53 MGTYRXP2_129 FMCP_HSPC_DP22_M2C_P M6 DP22_M2C_P

AE54 MGTYRXN2_129 FMCP_HSPC_DP22_M2C_N M7 DP22_M2C_N

AE44 MGTYTXP3_129 FMCP_HSPC_DP23_C2M_P Y2 DP23_C2M_P

AE45 MGTYTXN3_129 FMCP_HSPC_DP23_C2M_N Y3 DP23_C2M_N

AE49 MGTYRXP3_129 FMCP_HSPC_DP23_M2C_P M2 DP23_M2C_P

AE50 MGTYRXN3_129 FMCP_HSPC_DP23_M2C_N M3 DP23_M2C_N

AG40 MGTREFCLK0P_129 FMCP_HSPC_GBTCLK5_M2C_P

AG41 MGTREFCLK0N_129 FMCP_HSPC_GBTCLK5_M2C_N

AF42 MGTREFCLK1P_129

AF43 MGTREFCLK1N_129

FPGA (U1) Pin

Name

MGT

Bank

bank

Notes:

1. Series 0.01uF capacitor coupled.

Schematic Net Name

NC NC NC NC

Connected

Z20 GBTCLK5_M2C_P

Z21 GBTCLK5_M2C_N

Pin Name

Connected

Device

FMCP HSPC

J18

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Table 17: XCVU37P U1 GTY Transceiver Bank 128 Connections

GTY

128

FPGA

(U1)

AK46 MGTYTXP0_128 FMCP_HSPC_DP16_C2M_P M26 DP16_C2M_P

AK47 MGTYTXN0_128 FMCP_HSPC_DP16_C2M_N M27 DP16_C2M_N

AL49 MGTYRXP0_128 FMCP_HSPC_DP16_M2C_P Z32 DP16_M2C_P

AL50 MGTYRXN0_128 FMCP_HSPC_DP16_M2C_N Z33 DP16_M2C_N

AJ48 MGTYTXP1_128 FMCP_HSPC_DP17_C2M_P M30 DP17_C2M_P

AJ49 MGTYTXN1_128 FMCP_HSPC_DP17_C2M_N M31 DP17_C2M_N

AK51 MGTYRXP1_128 FMCP_HSPC_DP17_M2C_P Y34 DP17_M2C_P

AK52 MGTYRXN1_128 FMCP_HSPC_DP17_M2C_N Y35 DP17_M2C_N

AJ44 MGTYTXP2_128 FMCP_HSPC_DP18_C2M_P M34 DP18_C2M_P

AJ45 MGTYTXN2_128 FMCP_HSPC_DP18_C2M_N M35 DP18_C2M_N

AJ53 MGTYRXP2_128 FMCP_HSPC_DP18_M2C_P Z36 DP18_M2C_P

AJ54 MGTYRXN2_128 FMCP_HSPC_DP18_M2C_N Z37 DP18_M2C_N

AH46 MGTYTXP3_128 FMCP_HSPC_DP19_C2M_P M38 DP19_C2M_P

AH47 MGTYTXN3_128 FMCP_HSPC_DP19_C2M_N M39 DP19_C2M_N

AH51 MGTYRXP3_128 FMCP_HSPC_DP19_M2C_P Y38 DP19_M2C_P

AH52 MGTYRXN3_128 FMCP_HSPC_DP19_M2C_N Y39 DP19_M2C_N

AJ40 MGTREFCLK0P_128 FMCP_HSPC_GBTCLK4_M2C_P

AJ41 MGTREFCLK0N_128 FMCP_HSPC_GBTCLK4_M2C_N

AH42 MGTREFCLK1P_128

AH43 MGTREFCLK1N_128

FPGA (U1) Pin

Name

MGT

Bank

bank

Notes:

1. Series 0.01uF capacitor coupled.

Schematic Net Name

NC NC NC NC

Connected

L4 GBTCLK4_M2C_P

L5 GBTCLK4_M2C_N

Pin Name

Connected

Device

FMCP HSPC

J18

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Table 18: XCVU37P U1 GTY Transceiver Bank 127 Connections

GTY

127

FPGA

(U1)

AP46 MGTYTXP0_127 FMCP_HSPC_DP12_C2M_P Z28 DP12_C2M_P

AP47 MGTYTXN0_127 FMCP_HSPC_DP12_C2M_N Z29 DP12_C2M_N

AN53 MGTYRXP0_127 FMCP_HSPC_DP12_M2C_P Y14 DP12_M2C_P

AN54 MGTYRXN0_127 FMCP_HSPC_DP12_M2C_N Y15 DP12_M2C_N

AN44 MGTYTXP1_127 FMCP_HSPC_DP13_C2M_P Y30 DP13_C2M_P

AN45 MGTYTXN1_127 FMCP_HSPC_DP13_C2M_N Y31 DP13_C2M_N

AN49 MGTYRXP1_127 FMCP_HSPC_DP13_M2C_P Z16 DP13_M2C_P

AN50 MGTYRXN1_127 FMCP_HSPC_DP13_M2C_N Z17 DP13_M2C_N

AM46 MGTYTXP2_127 FMCP_HSPC_DP14_C2M_P M18 DP14_C2M_P

AM47 MGTYTXN2_127 FMCP_HSPC_DP14_C2M_N M19 DP14_C2M_N

AM51 MGTYRXP2_127 FMCP_HSPC_DP14_M2C_P Y18 DP14_M2C_P

AM52 MGTYRXN2_127 FMCP_HSPC_DP14_M2C_N Y19 DP14_M2C_N

AL44 MGTYTXP3_127 FMCP_HSPC_DP15_C2M_P M22 DP15_C2M_P

AL45 MGTYTXN3_127 FMCP_HSPC_DP15_C2M_N M23 DP15_C2M_N

AL53 MGTYRXP3_127 FMCP_HSPC_DP15_M2C_P Y22 DP15_M2C_P

AL54 MGTYRXN3_127 FMCP_HSPC_DP15_M2C_N Y23 DP15_M2C_N

AL40 MGTREFCLK0P_127 FMCP_HSPC_GBTCLK3_M2C_P

AL41 MGTREFCLK0N_127 FMCP_HSPC_GBTCLK3_M2C_N

AK42 MGTREFCLK1P_127

AK43 MGTREFCLK1N_127

FPGA (U1) Pin

Name

MGT

Bank

bank

Notes:

1. Series 0.01uF capacitor coupled.

Schematic Net Name

NC NC NC NC

Connected

L8 GBTCLK3_M2C_P

L9 GBTCLK3_M2C_N

Pin Name

Connected

Device

FMCP HSPC

J18

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Table 19: XCVU37P U1 GTY Transceiver Bank 126 Connections

GTY

126

FPGA

(U1)

AU48 MGTYTXP0_126 FMCP_HSPC_DP8_C2M_P B28 DP8_C2M_P

AU49 MGTYTXN0_126 FMCP_HSPC_DP8_C2M_N B29 DP8_C2M_N

AU53 MGTYRXP0_126 FMCP_HSPC_DP8_M2C_P B8 DP8_M2C_P

AU54 MGTYRXN0_126 FMCP_HSPC_DP8_M2C_N B9 DP8_M2C_N

AT46 MGTYTXP1_126 FMCP_HSPC_DP9_C2M_P B24 DP9_C2M_P

AT47 MGTYTXN1_126 FMCP_HSPC_DP9_C2M_N B25 DP9_C2M_N

AT51 MGTYRXP1_126 FMCP_HSPC_DP9_M2C_P B4 DP9_M2C_P

AT52 MGTYRXN1_126 FMCP_HSPC_DP9_M2C_N B5 DP9_M2C_N

AR48 MGTYTXP2_126 FMCP_HSPC_DP10_C2M_P Z24 DP10_C2M_P

AR49 MGTYTXN2_126 FMCP_HSPC_DP10_C2M_N Z25 DP10_C2M_N

AR53 MGTYRXP2_126 FMCP_HSPC_DP10_M2C_P Y10 DP10_M2C_P

AR54 MGTYRXN2_126 FMCP_HSPC_DP10_M2C_N Y11 DP10_M2C_N

AR44 MGTYTXP3_126 FMCP_HSPC_DP11_C2M_P Y26 DP11_C2M_P

AR45 MGTYTXN3_126 FMCP_HSPC_DP11_C2M_N Y27 DP11_C2M_N

AP51 MGTYRXP3_126 FMCP_HSPC_DP11_M2C_P Z12 DP11_M2C_P

AP52 MGTYRXN3_126 FMCP_HSPC_DP11_M2C_N Z13 DP11_M2C_N

AN40 MGTREFCLK0P_126 FMCP_HSPC_GBTCLK2_M2C_P

AN41 MGTREFCLK0N_126 FMCP_HSPC_GBTCLK2_M2C_N1 L13 GBTCLK2_M2C_N

AM42 MGTREFCLK1P_126

AM43 MGTREFCLK1N_126

FPGA (U1) Pin

Name

MGT

Bank

bank

Notes:

1. Series 0.01uF capacitor coupled.

Schematic Net Name

NC NC NC NC

Connected

L12 GBTCLK2_M2C_P

Pin Name

Connected

Device

FMCP HSPC

J18

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Table 20: XCVU37P U1 GTY Transceiver Bank 125 Connections

GTY

125

FPGA

(U1)

AY46 MGTYTXP0_125 FMCP_HSPC_DP4_C2M_P A34 DP4_C2M_P

AY47 MGTYTXN0_125 FMCP_HSPC_DP4_C2M_N A35 DP4_C2M_N

AY51 MGTYRXP0_125 FMCP_HSPC_DP4_M2C_P A14 DP4_M2C_P

AY52 MGTYRXN0_125 FMCP_HSPC_DP4_M2C_N A15 DP4_M2C_N

AW44 MGTYTXP1_125 FMCP_HSPC_DP5_C2M_P A38 DP5_C2M_P

AW45 MGTYTXN1_125 FMCP_HSPC_DP5_C2M_N A39 DP5_C2M_N

AW53 MGTYRXP1_125 FMCP_HSPC_DP5_M2C_P A18 DP5_M2C_P

AW54 MGTYRXN1_125 FMCP_HSPC_DP5_M2C_N A19 DP5_M2C_N

AV46 MGTYTXP2_125 FMCP_HSPC_DP6_C2M_P B36 DP6_C2M_P

AV47 MGTYTXN2_125 FMCP_HSPC_DP6_C2M_N B37 DP6_C2M_N

AW49 MGTYRXP2_125 FMCP_HSPC_DP6_M2C_P B16 DP6_M2C_P

AW50 MGTYRXN2_125 FMCP_HSPC_DP6_M2C_N B17 DP6_M2C_N

AU44 MGTYTXP3_125 FMCP_HSPC_DP7_C2M_P B32 DP7_C2M_P

AU45 MGTYTXN3_125 FMCP_HSPC_DP7_C2M_N B33 DP7_C2M_N

AV51 MGTYRXP3_125 FMCP_HSPC_DP7_M2C_P B12 DP7_M2C_P

AV52 MGTYRXN3_125 FMCP_HSPC_DP7_M2C_N B13 DP7_M2C_N

AR40 MGTREFCLK0P_125 FMCP_HSPC_GBTCLK1_M2C_P

AR41 MGTREFCLK0N_125 FMCP_HSPC_GBTCLK1_M2C_N

AP42 MGTREFCLK1P_125

AP43 MGTREFCLK1N_125

FPGA (U1) Pin

Name

MGT

Bank

bank

Notes:

1. Series 0.01uF capacitor coupled.

Schematic Net Name

NC NC NC NC

Connected

B20 GBTCLK1_M2C_P

B21 GBTCLK1_M2C_N

Pin Name

Connected

Device

FMCP HSPC

J18

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Chapter 3: Board Component Descriptions

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Table 21: XCVU37P U1 GTY Transceiver Bank 124 Connections

GTY

124

FPGA

(U1)

BC48 MGTYTXP0_124 FMCP_HSPC_DP0_C2M_P C2 DP0_C2M_P

BC49 MGTYTXN0_124 FMCP_HSPC_DP0_C2M_N C3 DP0_C2M_N

BC53 MGTYRXP0_124 FMCP_HSPC_DP0_M2C_P C6 DP0_M2C_P

BC54 MGTYRXN0_124 FMCP_HSPC_DP0_M2C_N C7 DP0_M2C_N

BC44 MGTYTXP1_124 FMCP_HSPC_DP1_C2M_P A22 DP1_C2M_P

BC45 MGTYTXN1_124 FMCP_HSPC_DP1_C2M_N A23 DP1_C2M_N

BB51 MGTYRXP1_124 FMCP_HSPC_DP1_M2C_P A2 DP1_M2C_P

BB52 MGTYRXN1_124 FMCP_HSPC_DP1_M2C_N A3 DP1_M2C_N

BB46 MGTYTXP2_124 FMCP_HSPC_DP2_C2M_P A26 DP2_C2M_P

BB47 MGTYTXN2_124 FMCP_HSPC_DP2_C2M_N A27 DP2_C2M_N

BA53 MGTYRXP2_124 FMCP_HSPC_DP2_M2C_P A6 DP2_M2C_P

BA54 MGTYRXN2_124 FMCP_HSPC_DP2_M2C_N A7 DP2_M2C_N

BA44 MGTYTXP3_124 FMCP_HSPC_DP3_C2M_P A30 DP3_C2M_P

BA45 MGTYTXN3_124 FMCP_HSPC_DP3_C2M_N A31 DP3_C2M_N

BA49 MGTYRXP3_124 FMCP_HSPC_DP3_M2C_P A10 DP3_M2C_P

BA50 MGTYRXN3_124 FMCP_HSPC_DP3_M2C_N A11 DP3_M2C_N

AV42 MGTREFCLK0P_124 FMCP_HSPC_GBTCLK0_M2C_P

AV43 MGTREFCLK0N_124 FMCP_HSPC_GBTCLK0_M2C_N

AT42 MGTREFCLK1P_124

AT43 MGTREFCLK1N_124

FPGA (U1) Pin

Name

MGT

Bank

Notes:

1. Series 0.01uF capacitor coupled.

Schematic Net Name

NC NC NC NC

Connected

D4 GBTCLK0_M2C_P

D5 GBTCLK0_M2C_N

Pin Name

Connected

Device

FMCP HSPC

J18

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Left-side Quads

The four connected GTY Quads on the le side of the XCVU37P FPGA are described in this secon (MGTY235- MGTY228 are not used).

• Quad 227

○ MGTREFCLK0 - PCIE_CLK2_P/N (U94)

○ MGTREFCLK1 - not connected

○ Four GTY transceivers allocated to PCIe lanes 3:0 PCIE_EP_TX/RX[3:0]

• Quad 226

○ MGTREFCLK0 - not connected

○ MGTREFCLK1 - not connected

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○ Four GTY transceivers allocated to PCIe lanes 7:4 PCIE_EP_TX/RX[7:4]

• Quad 225

○ MGTREFCLK0 - PCIE_CLK1_P/N (U94)

○ MGTREFCLK1 - not connected

○ Four GTY transceivers allocated to PCIe lanes 11:8 PCIE_EP_TX/RX[11:8]

• Quad 224

○ MGTREFCLK0 - not connected

○ MGTREFCLK1 - not connected

○ Four GTY transceivers allocated to PCIe lanes 15:12 PCIE_EP_TX/RX[15:12]

The XCVU37P le-side GTY transceiver interface assignments are shown in the following gure.

Figure 21: XCVU37P Left-side GTY Transceiver Assignments

BANK 227

MGTY_227_0 MGTY_227_1 MGTY_227_2

MGTY_227_3 MGTY_227_REFCLK0 MGTY_227_REFCLK1

BANK 226

MGTY_226_0

MGTY_226_1

MGTY_226_2

MGTY_226_3 MGTY_226_REFCLK0 MGTY_226_REFCLK1

PCIE_EP_TX/RX_3 PCIE_EP_TX/RX_2 PCIE_EP_TX/RX_1 PCIE_EP_TX/RX_0 PCIE_CLK2 NC

PCIE_EP_TX/RX_7 PCIE_EP_TX/RX_6 PCIE_EP_TX/RX_5 PCIE_EP_TX/RX_4 NC NC

BANK 225

MGTY_225_0 MGTY_225_1 MGTY_225_2

MGTY_225_3 MGTY_225_REFCLK0 MGTY_225_REFCLK1

BANK 224

MGTY_224_0

MGTY_224_1

MGTY_224_2

MGTY_224_3 MGTY_224_REFCLK0 MGTY_224_REFCLK1

PCIE_EP_TX/RX_11 PCIE_EP_TX/RX_10 PCIE_EP_TX/RX_9 PCIE_EP_TX/RX_8 PCIE_CLK1 NC

PCIE_EP_TX/RX_15 PCIE_EP_TX/RX_14 PCIE_EP_TX/RX_13 PCIE_EP_TX/RX_12 NC NC

X21651-092618

Left-side GTY Transceiver Connectivity

The following tables list the XCVU37P FPGA U1 GTY transceiver banks 227, 226, 225, and 224 connecons, respecvely.

For addional informaon on GTY transceivers, see the UltraScale Architecture GTY Transceivers User Guide (UG578). Also see the UltraScale FPGAs Transceivers Wizard LogiCORE IP Product Guide (PG182). For addional informaon about the quad small form factor pluggable (28 Gb/s QSFP28) module, see the SFF-8663 and SFF-8679 specicaons for the 28 Gb/s QSFP+ at the

SNIA Technology Aliates website.

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Table 22: XCVU37P U1 GTY Transceiver Bank 227 Connections

MGT

Bank

GTY bank

227

Notes:

1. Series 0.01uF capacitor coupled.

FPGA

(U1)

AP9 MGTYTXP0_227 PCIE_EP_TX3_P A29 PERP3

AP8

AN2 MGTYRXP0_227 PCIE_EP_RX3_P B27 PETP3

AN1 MGTYRXN0_227 PCIE_EP_RX3_N B28 PETN3

AN11 MGTYTXP1_227 PCIE_EP_TX2_P A25 PERP2

AN10 MGTYTXN1_227 PCIE_EP_TX2_N A26 PERN2

AN6 MGTYRXP1_227 PCIE_EP_RX2_P B23 PETP2

AN5 MGTYRXN1_227 PCIE_EP_RX2_N B24 PETN2

AM9 MGTYTXP2_227 PCIE_EP_TX1_P A21 PERP1

AM8 MGTYTXN2_227 PCIE_EP_TX1_N A22 PERN1

AM4 MGTYRXP2_227 PCIE_EP_RX1_P B19 PETP1

AM3 MGTYRXN2_227 PCIE_EP_RX1_N B20 PETN1

AL11 MGTYTXP3_227 PCIE_EP_TX0_P A16 PERP0

AL10 MGTYTXN3_227 PCIE_EP_TX0_N A17 PERN0

AL2 MGTYRXP3_227 PCIE_EP_RX0_P B14 PETP0

AL1 MGTYRXN3_227 PCIE_EP_RX0_N B15 PETN0

AL15 MGTREFCLK0P_227 PCIE_CLK2_P

AL14 MGTREFCLK0N_227 PCIE_CLK2_N

AK13 MGTREFCLK1P_227

AK12 MGTREFCLK1N_227

FPGA (U1) Pin

Name

MGTYTXN0_227 PCIE_EP_TX3_N A30 PERN3

Schematic Net

Name TX

NC NC NC NC

Connected

3 Q1 ICS85411A

4 NQ1

Connected

Pin Name

Connected

Device

PCIE 16-lane

edge conn. P1

U94 clock

buffer

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Table 23: XCVU37P U1 GTY Transceiver Bank 226 Connections

MGT

Bank

GTY bank

226

Notes:

1. Series 0.01uF capacitor coupled.

FPGA

(U1)

AU11 MGTYTXP0_226 PCIE_EP_TX7_P A47 PERP7

AU10

AU2 MGTYRXP0_226 PCIE_EP_RX7_P B45 PETP7

AU1 MGTYRXN0_226 PCIE_EP_RX7_N B46 PETN7

AT9 MGTYTXP1_226 PCIE_EP_TX6_P A43 PERP6

AT8 MGTYTXN1_226 PCIE_EP_TX6_N A44 PERN6

AT4 MGTYRXP1_226 PCIE_EP_RX6_P B41 PETP6

AT3 MGTYRXN1_226 PCIE_EP_RX6_N B42 PETN6

AR7 MGTYTXP2_226 PCIE_EP_TX5_P A39 PERP5

AR6 MGTYTXN2_226 PCIE_EP_TX5_N A40 PERN5

AR2 MGTYRXP2_226 PCIE_EP_RX5_P B37 PETP5

AR1 MGTYRXN2_226 PCIE_EP_RX5_N B38 PETN5

AR11 MGTYTXP3_226 PCIE_EP_TX4_P A35 PERP4

AR10 MGTYTXN3_226 PCIE_EP_TX4_N A36 PERN4

AP4 MGTYRXP3_226 PCIE_EP_RX4_P B33 PETP4

AP3 MGTYRXN3_226 PCIE_EP_RX4_N B34 PETN4

AN15 MGTREFCLK0P_226

AN14 MGTREFCLK0N_226

AM13 MGTREFCLK1P_226

AM12 MGTREFCLK1N_226

FPGA (U1) Pin

Name

MGTYTXN0_226 PCIE_EP_TX7_N A48 PERN7

Schematic Net

Name TX

NC NC NC NC

Connected

Pin Name

Connected

Device

PCIE 16-lane

edge conn. P1

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Table 24: XCVU37P U1 GTY Transceiver Bank 225 Connections

MGT

Bank

GTY bank

225

Notes:

1. Series 0.01uF capacitor coupled.

FPGA

(U1)

AY9 MGTYTXP0_225 PCIE_EP_TX11_P A64 PERP11

AY8

AY4 MGTYRXP0_225 PCIE_EP_RX11_P B62 PETP11

AY3 MGTYRXN0_225 PCIE_EP_RX11_N B63 PETN11

AW11 MGTYTXP1_225 PCIE_EP_TX10_P A60 PERP10

AW10 MGTYTXN1_225 PCIE_EP_TX10_N A61 PERN10

AW2 MGTYRXP1_225 PCIE_EP_RX10_P B58 PETP10

AW1 MGTYRXN1_225 PCIE_EP_RX10_N B59 PETN10

AV9 MGTYTXP2_225 PCIE_EP_TX9_P A56 PERP9

AV8 MGTYTXN2_225 PCIE_EP_TX9_N A57 PERN9

AW6 MGTYRXP2_225 PCIE_EP_RX9_P B54 PETP9

AW5 MGTYRXN2_225 PCIE_EP_RX9_N B55 PETN9

AU7 MGTYTXP3_225 PCIE_EP_TX8_P A52 PERP8

AU6 MGTYTXN3_225 PCIE_EP_TX8_N A53 PERN8

AV4 MGTYRXP3_225 PCIE_EP_RX8_P B50 PETP8

AV3 MGTYRXN3_225 PCIE_EP_RX8_N B51 PETN8

AR15 MGTREFCLK0P_225 PCIE_CLK1_P

AR14 MGTREFCLK0N_225 PCIE_CLK1_N

AP13 MGTREFCLK1P_225

AP12 MGTREFCLK1N_225

FPGA (U1) Pin

Name

MGTYTXN0_225 PCIE_EP_TX11_N A65 PERN11

Schematic Net

Name TX

NC NC NC NC

Connected

1 Q0 ICS85411A

2 NQ0

Connected

Pin Name

Connected

Device

PCIE 16-lane

edge conn. P1

U94 clock

buffer

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Table 25: XCVU37P U1 GTY Transceiver Bank 224 Connections

MGT

bank

GTY bank

224

Notes:

1. Series 0.01uF capacitor coupled.

FPGA

(U1)

BC7 MGTYTXP0_224 PCIE_TX15_P A80 PERP15

BC6

BC2 MGTYRXP0_224 PCIE_RX15_P B78 PETP15

BC1 MGTYRXN0_224 PCIE_RX15_N B79 PETN15

BC11 MGTYTXP1_224 PCIE_TX14_P A76 PERP14

BC10 MGTYTXN1_224 PCIE_TX14_N A77 PERN14

BB4 MGTYRXP1_224 PCIE_RX14_P B74 PETP14

BB3 MGTYRXN1_224 PCIE_RX14_N B75 PETN14

BB9 MGTYTXP2_224 PCIE_TX13_P A72 PERP13

BB8 MGTYTXN2_224 PCIE_TX13_N A73 PERN13

BA2 MGTYRXP2_224 PCIE_RX13_P B70 PETP13

BA1 MGTYRXN2_224 PCIE_RX13_N B71 PETN13

BA11 MGTYTXP3_224 PCIE_TX12_P A68 PERP12

BA10 MGTYTXN3_224 PCIE_TX12_N A69 PERN12

BA6 MGTYRXP3_224 PCIE_RX12_P B66 PETP12

BA5 MGTYRXN3_224 PCIE_RX12_N B67 PETN12

AV13 MGTREFCLK0P_224

AV12 MGTREFCLK0N_224

AT13 MGTREFCLK1P_224

AT12 MGTREFCLK1N_224

FPGA (U1) Pin

Name

MGTYTXN0_224 PCIE_TX15_N A81 PERN15

Schematic Net

Name TX

NC NC NC NC

Connected

Pin Name

Connected

device

PCIE 16-lane

edge conn. P1

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PCI Express Endpoint Connectivity

[Figure 2, callout 20]

The 16-lane PCI Express® edge connector P1 performs data transfers at the rate of 2.5 GT/s for Gen1 applicaons, 5.0 GT/s for Gen2 applicaons, 8.0 GT/s for Gen3 applicaons and 16.0 GT/s for Gen4 applicaons. The PCIe® transmit and receive signal data paths have a characterisc impedance of 85Ω ±10%. The PCIe clock is routed as a 100Ω dierenal pair.

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The XCVU37P-2FSVH2892E (-2 speed grade) is deployed on the VCU128 to support up to Gen4 x8. User selectable as PCIe Gen3 x16 or dual Gen4 x8. The PCIe reference clock is input from the P1 edge connector. The PCIe clock is routed from P1 pin A16 (P) and pin A17 (N) to a 1-to-2 ICS85411A clock buer U94. The Q0 output of U94 is wired to the GTY225 MGTHREFCLK0 input (see Table 24). The Q1 output of U94 is wired to the GTY227 MGTHREFCLK0 input (see

Table 22). PCIe lane width/size is selected by jumper J46. The default lane size selecon is 16-

lane (J46 pins 7 and 8 jumpered). The 1-to-2 U94 PCIe clock buer circuit and J46 lane size jumper are shown in the following gure.

Figure 22: PCI Express Lane Clock Circuit and Size Select Jumper J46

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X21969-112818

The tables in Le-side GTY Transceiver Connecvity list the PCIe P1 edge connector wiring to the XCVU37P FPGA U1 MGTY transceiver banks 227-224. The two PCIe P1 edge connector control signals PCIE_EP_WAKE (P1 pin B11) and PCIE_EP_PERST (P1 pin A11) are level-shied by SN74AVC2T245 U70 and connected to the XCVU39P U1 bank 65 pin BJ42 and pin BF41,

respecvely. For addional informaon about UltraScale™ PCIe funconality, see the UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156). Addional

informaon about the PCI Express standard is available on the PCI Express standard website.

Chapter 3: Board Component Descriptions

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28 Gb/s zQSFP+ Module Connectors

[Figure 2, callout 19]

The VCU128 board hosts four QSFP28 small form-factor pluggable (28 Gb/s QSFP+) connectors: QSFP1 J42, QSFP2 J39, QSFP3 J35, and QSFP4 J32, which accept 28 Gb/s QSFP+ opcal modules. The four connectors are housed within a single 1x4 ganged 28 Gb/s QSFP+ cage assembly J37. The following gure shows a typical implementaon of the 28 Gb/s QSFP28 module connector circuitry.

Table 12 through Table 15 in Right-side GTY Transceiver Connecvity list the QSFP28

connecons to the XCVU37P FPGA U1 MGTY transceiver banks 135 (QSFP1), 134 (QSFP2), 132 (QSFP3), and 131 (QSFP4).

Figure 23: 28 Gb/s QSFP28 Module Connector

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X21970-112818

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QSFP28 Connections to Transceiver Banks 67 and 69

The following table lists the QSFP28 module level-shied control signal connecons to XCVU37P FPGA U1 bank 67 (QSFP1, QSFP4) and bank 69 (QSFP2, QSFP3).

Table 26: XCVU37P U1 to QSFP28 Module Control and I2C Connections

FPGA (U1) Pin

BM24 QSFP1_MODSKLL_LS Output 8 MODSELL

BN25 QSFP1_RESETL_LS Output 9 RESETL

BM25 QSFP1_MODPRSL_LS Output 27 MODPRSL

BP24 QSFP1_INTL_LS Input 28 INTL

BN24 QSFP1_LPMODE_LS Output 31 LPMODE

U54.13 QSFP1_I2C_SDA BiDir 12 SDA

U54.14 QSFP1_I2C_SCL Output 11 SCL

BN5 QSFP2_MODSKLL_LS Output 8 MODSELL

BN6 QSFP2_RESETL_LS Output 9 RESETL

BN7 QSFP2_MODPRSL_LS Output 27 MODPRSL

BP6 QSFP2_INTL_LS Input 28 INTL

BP7 QSFP2_LPMODE_LS Output 31 LPMODE

U54.15 QSFP2_I2C_SDA BiDir 12 SDA

U54.16 QSFP2_I2C_SCL Output 11 SCL

BM5 QSFP3_MODSKLL_LS Output 8 MODSELL

BL6 QSFP3_RESETL_LS Output 9 RESETL

BM7 QSFP3_MODPRSL_LS Output 27 MODPRSL

BL7 QSFP3_INTL_LS Input 28 INTL

BN4 QSFP3_LPMODE_LS Output 31 LPMODE

U54.17 QSFP3_I2C_SDA BiDir 12 SDA

U54.18 QSFP3_I2C_SCL Output 11 SCL

BK23 QSFP4_MODSKLL_LS Output 8 MODSELL

BK24 QSFP4_RESETL_LS Output 9 RESETL

BL22 QSFP4_MODPRSL_LS Output 27 MODPRSL

BH21 QSFP4_INTL_LS Input 28 INTL

BH21 QSFP4_LPMODE_LS Output 31 LPMODE

U54.19 QSFP4_I2C_SDA BiDir 12 SDA

Schematic Net

Name1,

FPGA (U1)

Direction

QSFP1 J42 (U1 bank 67)

QSFP2 J39 (U1 bank 69)

QSFP3 J35 (U1 bank 69)

QSFP4 J32 (U1 bank 67)

Module Pin Num Module Pin Name

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Table 26: XCVU37P U1 to QSFP28 Module Control and I2C Connections (cont'd)

FPGA (U1) Pin

U54.20 QSFP4_I2C_SCL Output 11 SCL

Notes:

1. The QSFP28 connector control signals are level-shifted.

2. The four QSFP28 connector I2C SCL/SDA signals are connected via I2C switch U54 to the I2C1_SCL/SDA bus. See I2C

Bus, Topology, and Switches section

Schematic Net

Name1,

FPGA (U1)

Direction

Module Pin Num Module Pin Name

For addional informaon about the quad small form factor pluggable (28 Gb/s QSFP28) module, see the SFF-8663 and SFF-8679 specicaons for the 28 Gb/s QSFP+ on the SNIA Technology

Aliates website.

10/100/1000 Mb/s Tri-speed Ethernet PHY

[Figure 2, callout 22]

The VCU128 evaluaon board uses the TI PHY device DP83867ISRGZ (U62) for Ethernet communicaons at 10 Mb/s, 100 Mb/s, or 1000 Mb/s. The board supports SGMII mode only. The PHY connecon to a user-provided Ethernet cable is through RJ-45 connector P2, a Wurth 7499111221A with built-in magnecs and status LEDs. On power-up, or on reset, the PHY is congured to operate in SGMII mode with PHY address[4:0] = 00011. The following table lists the FPGA U1 to U62 DP83867ISRGZ Ethernet PHY connecons. This table also shows the net names for the connecons from the FPGA to the Ethernet PHY. ENET_SGMII_IN correlates with the SGMII_TX ports in the FPGA design, and ENET_SGMII_OUT correlates with the SGMII_RX ports.

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Table 27: XCVC37P U1 to Ethernet PHY U62 Connections

FPGA

(U1) Pin

BG23 ENET_MDIO LVCMOS18 17 MDIO

BN27 ENET_MDC LVCMOS18 16 MDC

BF22 ENET_PDWN_B_I_INT_B_O LVCMOS18 44 INT_PWDN

BH22 ENET_SGMII_IN_N LVCMOS18 28 TX_D1_SGMII_SIP

BG22 ENET_SGMII_IN_P LVCMOS18 27 TX_D0_SGMII_SIN

BJ21 ENET_SGMII_OUT_N LVCMOS18 36 RX_D3_SGMII_SON

BH21 ENET_SGMII_OUT_P LVCMOS18 35 RX_D2_SGMII_SOP

BK22 ENET_SGMII_CLK_N LVCMOS18 34 RX_D1_SGMII_CON

BK23 ENET_SGMII_CLK_P LVCMOS18 33 RX_D0_SGMII_COP

U65.10 GEM3_ENET_RESET_B NA 43 RESET_B

BP27 ENET_COL_GPIO LVCMOS18 39 GPIO_2

BJ23 ENET_CLKOUT LVCMOS18 18 CLK_OUT

Net Name I/O Standard

DP83867ISRGZ U62

Pin Name

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Ethernet PHY Status LEDs

[Figure 2, callout 23]

Two Ethernet PHY status LEDs are integrated into the metal frame of the P2 RJ-45 connector, installed on the top edge and towards the back of the VCU128 board. The two PHY status LEDs are visible within the frame of the RJ45 Ethernet jack as shown in the following gure. As viewed from the front opening, the le green LED is the link acvity indicator and the right green LED is the 1000BASE-T link mode indicator.

Figure 24: Ethernet PHY Status LEDs

X21971-112818

A separate discrete LED on top of the board (DS19, near item 38 in Figure 2) indicates link established. Details about the tri-mode Ethernet MAC core are provided in the Tri-Mode Ethernet MAC LogiCORE IP Product Guide (PG051). The TI DP83867ISRGZ data sheet is on the TI website.

I2C Bus, Topology, and Switches

[Figure 2, callout 25, 26]

The VCU128 evaluaon board I2C bus implementaon consists of I2C bus I2C0. The FPGA U1 HP bank 67 (VCCO VCC1V8) and system controller U42 bank 501 are wired to I2C0 via level- shiers. I2C bus I2C0 is routed to a 1-to-4 channel TI PCA9544A bus switch U55 (address 0x75) and a dual 8-bit port TI TCA6416A IO expander U65 (address 0x20). I2C bus I2C0 is also routed to a pair of 1-to-8 channel TI TCA9548A bus switches U53 (address 0x74) and U54 (address 0x76). The bus switches can operate at speeds up to 400 kHz. The VCU128 evaluaon board I2C0 I2C bus topology is shown in the following gures.

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IMPORTANT! The TCA9548 U53 and U54 RESET_B pin 3 control signal IIC_MUX_RESET_B is connected to the I2C0 bus TCA6416A U65 port expander (Addr 0x20) port P05 pin 9. The IIC_MUX_RESET_B signal must be driven hi-Z or High to enable I2C bus transacons with the target devices connected to U53 and U54.

Figure 25: I2C0 Bus Topology

XCVU37P

BANK 65 BE41/BP42

BANK 67 BL28/BM27

U42

XC7Z010

BANK 501

D11/A15

U49

L/S

U60

L/S

U58

L/S

SYSMON_SDA/SCL

I2C0_SDA/SCL

U65

SDA/

SCL

0X20

U55

SDA/ SCL

0X75

TCA64 16A

PCA9544A

SD0/SC0

SD1/SC1

SD2/SC2

SD3/SC3

MAX6643-OT_B

P00

MAX6643_FANFAIL_B

P01

VCCINT_VCCBRAM_HOT_N

P02

PMIC_INTR

P03

SI5328_INT_ALM

P04

ICC_MUX_RESET-B

P05

GEM3_EXP_RESET_B

P06

MAX6643_FULL_SPEED

P07

FMC_HSPC_PRSNT_M2C_B

P10

MAIN_PMBUS_ALERT_B

P16

INA226_PMBUS_ALERT

P17

INA226_PMBUS_ALERT

INT0_B

INA226_PMBUS_SDA/SCL

INT1_B

INT2_B

INT3_B

NC NC

MAIN_PMBUS_ALERT_B MAIN_PMBUS_SDA/SCL

SYSMON_SDA/SCL

U53

SDA/ SCL

0X74

U54

SDA/ SCL

0X76

TCA9548A

SD0/SC0 SD1/SC1 SD2/SC2 SD3/SC3 SD4/SC4 SD5/SC5 SD6/SC6 SD7/SC7

TCA9548A

SD0/SC0 SD1/SC1 SD2/SC2 SD3/SC3 SD4/SC4 SD5/SC5 SD6/SC6 SD7/SC7

IIC-EEPROM-SDA/SCL

SI5328_SDA/SCL

NOT CONNECTED QSFP1_SI570_SDA/SCL QSFP2_SI570_SDA/SCL

QSFP3_SI570_SDA/SCL

QSFP4_SI570_SDA/SCL

NOT CONNECTED

FMCP_HSPC_IIC_SDA/SCL

NOT CONNECTED

SYSMON_SDA/SCL

NOT CONNECTED

QSFP1_I2C_SDA/SCL QSFP2_I2C_SDA/SCL QSFP3_I2C_SDA/SCL

QSFP4_I2C_SDA/SCL

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X21652-112918

I2C Bus Addresses

User applicaons that communicate with any of the I2C bus I2C0 downstream devices must rst set up a path to the desired target device through the appropriate bus switch: I2C0 U55 PCA9544A, address 0x75 (0b111101); U53 TCA9548A, address 0x74 (0b1110100), or U54 TCA9548A, address 0x76 (0b111110), respecvely. The following table lists the address for each bus.

Table 28: I2C Bus Addresses

Send Feedback

Chapter 3: Board Component Descriptions

I2C Devices

PCA9544A 4-channel bus switch N/A

PMBus INA226 power monitor

Not used 1 N/A N/A N/A

PMBus regulators

FPGA SYSMON

TCA9548 8-channel bus switch N/A

I2C EEPROM 0

SI5328 clock 1

Not used 2 N/A N/A N/A

QSFP1 Si570 clock 3

QSFP2 Si570 clock 4

QSFP3 Si570 clock 5

QSFP4 Si570 clock 6

Not used 7 N/A N/A N/A

TCA9548 8-channel bus switch N/A

FMCP HSPC (FMC Plus) 0

Not used 1 N/A N/A N/A

FPGA SYSMON 2

Not used 3 N/A N/A N/A

QSFP1 module 4

QSFP2 module 5

QSFP3 module 6

QSFP4 module 7

Notes:

1. See Onboard Power System Devices.

I2C Switch

Position

Binary

Format

I2C0 Bus

0b1110101

0b0110010 0x32

I2C0 Bus

0b1110100 0x74

0b1010100 0x54

0b1101000

0b1011101 0x5D

I2C0 Bus

0b1110101 0x76

0bXXXXXXX 0x##

0b0110010 0x32

0b1010000 0x50

Hex Format

0x75 U55 PCA9544A

0x40-0x42

0x46-0x48

0x4C-0x4D

0x60-0x65

0x68-0x6B

0x68 U87 SI5328B

U14,U16,U20,U21,

U79,U84,U85,U86

Various Intersil

regulators U3,U12,U15,U22,U24,U2 5,U29,U31,U36,U44,U67,

U1 BANK 65

U53 TCA9548A

U48 M24C08

U54 TCA9548A

J18 FMCP HSPC

U1 BANK 65

J42 28 Gb/s QSFP+

J39 28 Gb/s QSFP+

J35 28 Gb/s QSFP+

J32 28 Gb/s QSFP+

Device

INA226

U68

U95 SI570

U90 SI570

U82 SI570

U80 SI570

I2C Address

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Informaon about the PCA9544A, TCA9548, and TCA6416A is available on the TI

Semiconductor website.

Chapter 3: Board Component Descriptions

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Status and User LEDs

[Figure 2, callout 24]

The following table denes VCU128 board status and user LEDs.

Table 29: Board Status and User LEDs

Description

Reference Designator

DS1 Combined power good (red/green)

DS2 GPIO_LED_1

DS3 GPIO_LED_0

DS4 GPIO_LED_2

DS5 GPIO_LED_5

DS6 GPIO_LED_4

DS7 GPIO_LED_5

DS8 GPIO_LED_6

DS9 GPIO_LED_7

DS10 FPGA INIT (red/green)

DS11 VCCINT 0.85V Mode

DS12 VCCINT 0.72V Mode

DS13 FPGA done

DS14 VADJ_PG

DS15 SYSTEM CTLR INIT (red/green)

DS16 SYSTEM CTLR error (red)

DS17 SYSTEM CTLR status

DS18 SYSTEM CTLR done

DS19 ENET PHY link

DS20 12V On

EPHY P2 RT ENET LINK1000

EPHY P2 LFT ENET link activity

(Green unless otherwise noted)

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User GPIO

[Figure 2, callout 27, 28, 29]

The VCU128 board provides the following user and general purpose I/O capabilies.

• Eight user LEDs (callout 28)

○ GPIO_LED[7-0]: DS9, DS8, DS7, DS6, DS5, DS4, DS3, DS2

• CPU_RESET/GPIO pushbuon switch (callout 29)

○ CPU_RESET: SW4

The following gure shows the GPIO circuits.

Figure 26: User GPIO

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X21972-112918

GPIO Connections to FPGA U1

The following table lists the GPIO connecons to FPGA U1.

Table 30: GPIO Connections to FPGA U1

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Chapter 3: Board Component Descriptions

FPGA (U1) Pin

GPIO LEDs (Active-High) GPIO_LED signals are wired to LED driver U56

BANK 67 BH24 GPIO_LED_0 Output LVCMOS18 DS2

BANK 67 BG24 GPIO_LED_1 Output LVCMOS18 DS3

BANK 67 BG25 GPIO_LED_2 Output LVCMOS18 DS4

BANK 67 BF25 GPIO_LED_3 Output LVCMOS18 DS5

BANK 67 BF26 GPIO_LED_4 Output LVCMOS18 DS6

BANK 67 BF27 GPIO_LED_5 Output LVCMOS18 DS7

BANK 67 BG27 GPIO_LED_6 Output LVCMOS18 DS8

BANK 67 BG28 GPIO_LED_7 Output LVCMOS18 DS9

BANK 64 BM29 CPU_RESET Input LVCMOS12 SW4.3

GPIO SMA pair (applied voltage should not exceed 1.8V)

BANK 67 BH27 SMA_CLK_OUTPUT_P I/O LVCMOS18 J12.1

BANK 67 BJ27 SMA_CLK_OUTPUT_N I/O LVCMOS18 J13.1

Schematic Net

Name

CPU reset pushbutton (active-high)

FPGA (U1)

Direction

I/O Standard Device

Switches

[Figure 2, callouts 30, 33]

The VCU118 evaluaon board includes a power on/o slide switch and a conguraon pushbuon switch.

• FPGA Program_B SW4, acve-Low (callout 30)

• Power on/o slide switch SW5 (callout 33)

Power On/Off Slide Switch SW5

[Figure 2, callout 33]

The VCU118 board power switch is SW5. Sliding the switch actuator from the o to the on posion applies 12VDC power from the 6-pin mini-t power input connector J16, normally used in bench-top applicaons with the provided power adapter. The green LED DS20 illuminates when the VCU128 board power switch is on. See Board Power System for details on the onboard power system. The following gure shows the power connector J16, power switch SW5, and indicator LED DS20.

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Figure 27: Power On/Off Switch SW5

X21973-112818

When the VCU128 board is used inside a computer chassis (i.e., plugged in to a PCIe® slot), power is normally provided from the PC ATX supply 2x4 PCIe power connector. See Installing

the Board in a PC Chassis.

Program_B Pushbutton Switch

[Figure 2, callout 30]

Switch SW2 grounds the XCVU37P FPGA U1 PROGRAM_B pin when pressed. This acon clears the FPGA conguraon. The FPGA_PROG_B signal is connected to XCVU37P FPGA U1 pin BB15. See the UltraScale Architecture Conguraon User Guide (UG570) for further conguraon details. The following gure shows SW2.

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Chapter 3: Board Component Descriptions

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Figure 28: Program_B Pushbutton Switch SW2

X21974-112918

FPGA Mezzanine Card Interface

[Figure 2, callout 31]

The VCU128 evaluaon board supports the VITA 57.4 FPGA mezzanine card plus (FMC+ or FMCP) specicaon by providing a subset implementaon of the high pin count connector at J18 (HSPC, high serial pin connector). The VITA 57.4 standard extends the VITA 57.1 FMC standard by specifying two new connectors that increase the number of mul-gigabit interfaces from 10 to 24. Also, there is an oponal extension connector (the high serial pin connector extension, or HSPCe) to boost pin-count by 80 posions, arranged in a 4x20 array. The VCU128 board does not implement the high serial pin connector/HSPCe extension.

FMC+ connectors use a 14 x 40 form factor, populated with 560 pins. The connector is keyed so that a mezzanine card, when installed on the VCU128 evaluaon board, faces away from the board.

J18 FMC+/FMCP Connectors

This secon describes the J18 FMC+/FMCP connectors.

UG1302 (v1.0) December 21, 2018 www.xilinx.com VCU128 Board User Guide 79

• Samtec SEAF series, 1.27 mm (0.050 in) pitch. Mates with SEAM series connector. More informaon about SEAF series connectors is available on the Samtec website.

• The 560-pin FMC+ connector dened by the FMC specicaon (see Appendix A: VITA 57.4

FMCP Connector Pinouts) provides connecvity for up to:

○ 160 single-ended or 80 dierenal user-dened signals

Chapter 3: Board Component Descriptions

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○ 24 transceiver dierenal pairs

○ 6 transceiver dierenal clocks

○ 4 dierenal clocks

○ 239 ground and 17 power connecons

FMCP Connector J18

[Figure 2, callout 33]

The HSPC connector at J18 implements a subset of the full FMCP connecvity:

• 68 single-ended or 34 dierenal user-dened pairs (full LA-bus: LA[00:33])

• 24 transceiver dierenal pairs

• 6 transceiver dierenal clocks

• 2 dierenal clocks

• 239 ground and 14 power connecons

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J18 VITA 57.4 FMCP HSCP Connections

The FMCP J18 connecons to FPGA U1 are listed in the following table. The net names shown in the table are connected to FMCP HSCP J18 pins.

Table 31: J18 VITA 57.4 FMCP HSCP Connections

J18

FMCP

HSCP

A2 FMCP_HSPC_DP1_M2C_P LVDS BB51 B1 NC

A3 FMCP_HSPC_DP1_M2C_N LVDS BB52 B4 FMCP_HSPC_DP9_M2C_P LVDS AT51

A6 FMCP_HSPC_DP2_M2C_P LVDS BA53 B5 FMCP_HSPC_DP9_M2C_N LVDS AT52

A7 FMCP_HSPC_DP2_M2C_N LVDS BA54 B8 FMCP_HSPC_DP8_M2C_P LVDS AU53

A10 FMCP_HSPC_DP3_M2C_P LVDS BA49 B9 FMCP_HSPC_DP8_M2C_N LVDS AU54

A11 FMCP_HSPC_DP3_M2C_N LVDS BA50 B12 FMCP_HSPC_DP7_M2C_P LVDS AV51

A14 FMCP_HSPC_DP4_M2C_P LVDS AY51 B13 FMCP_HSPC_DP7_M2C_N LVDS AV52

A15 FMCP_HSPC_DP4_M2C_N LVDS AY52 B16 FMCP_HSPC_DP6_M2C_P LVDS AW49

A18 FMCP_HSPC_DP5_M2C_P LVDS AW53 B17 FMCP_HSPC_DP6_M2C_N LVDS AW50

A19 FMCP_HSPC_DP5_M2C_N LVDS AW54 B20 FMCP_HSPC_GBTCLK1_M2C_

A22 FMCP_HSPC_DP1_C2M_P LVDS BC44 B21 FMCP_HSPC_GBTCLK1_M2C_

A23 FMCP_HSPC_DP1_C2M_N LVDS BC45 B24 FMCP_HSPC_DP9_C2M_P LVDS AT46

A26 FMCP_HSPC_DP2_C2M_P LVDS BB46 B25 FMCP_HSPC_DP9_C2M_N LVDS AT47

A27 FMCP_HSPC_DP2_C2M_N LVDS BB47 B28 FMCP_HSPC_DP8_C2M_P LVDS AU48

A30 FMCP_HSPC_DP3_C2M_P LVDS BA44 B29 FMCP_HSPC_DP8_C2M_N LVDS AU49

A31 FMCP_HSPC_DP3_C2M_N LVDS BA45 B32 FMCP_HSPC_DP7_C2M_P LVDS AU44

A34 FMCP_HSPC_DP4_C2M_P LVDS AY46 B33 FMCP_HSPC_DP7_C2M_N LVDS AU45

A35 FMCP_HSPC_DP4_C2M_N LVDS AY47 B36 FMCP_HSPC_DP6_C2M_P LVDS AV46

A38 FMCP_HSPC_DP5_C2M_P LVDS AW44 B37 FMCP_HSPC_DP6_C2M_N LVDS AV47

A39 FMCP_HSPC_DP5_C2M_N LVDS AW45 B40 NC

Schematic

Net Name

I/O

Standard

J18 Sections A/B Connections to FPGA U1

FPGA

(U1)

J18 FMCP HSCP

Schematic Net Name

I/O

Standard

LVDS AR40

LVDS AR41

FPGA

(U1)

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Table 31: J18 VITA 57.4 FMCP HSCP Connections (cont'd)

J18

FMCP

HSCP

C2 FMCP_HSPC_DP0_C2M_P LVDS BC53 D1 VADJ_PG

C3 FMCP_HSPC_DP0_C2M_N LVDS BC54 D4 FMCP_HSPC_GBTCLK0_M2C_

C6 FMCP_HSPC_DP0_M2C_P LVDS BC48 D5 FMCP_HSPC_GBTCLK0_M2C_

C7 FMCP_HSPC_DP0_M2C_N LVDS BC49 D8 FMCP_HSPC_LA01_CC_P LVDS F26

C10 FMCP_HSPC_LA06_P LVDS E22 D9 FMCP_HSPC_LA01_CC_N LVDS F25

C11 FMCP_HSPC_LA06_N LVDS D22 D11 FMCP_HSPC_LA05_P LVDS H27

C14 FMCP_HSPC_LA10_P LVDS B23 D12 FMCP_HSPC_LA05_N LVDS G27

C15 FMCP_HSPC_LA10_N LVDS A23 D14 FMCP_HSPC_LA09_P LVDS E26

C18 FMCP_HSPC_LA14_P LVDS C23 D15 FMCP_HSPC_LA09_N LVDS D26

C19 FMCP_HSPC_LA14_N LVDS B22 D17 FMCP_HSPC_LA13_P LVDS A25

C22 FMCP_HSPC_LA18_CC_P LVDS E19 D18 FMCP_HSPC_LA13_N LVDS A24

C23 FMCP_HSPC_LA18_CC_N LVDS E18 D20 FMCP_HSPC_LA17_CC_P LVDS F18

C26 FMCP_HSPC_LA27_P LVDS E21 D21 FMCP_HSPC_LA17_CC_N LVDS E17

C27 FMCP_HSPC_LA27_N LVDS D21 D23 FMCP_HSPC_LA23_P LVDS B21

C30 FMCP_HSPC_IIC_SCL D24 FMCP_HSPC_LA23_N LVDS B20

C31 FMCP_HSPC_IIC_SDA D26 FMCP_HSPC_LA26_P LVDS D17

C34 GA0 = 0 = GND D27 FMCP_HSPC_LA26_N LVDS D16

C35 VCC12_SW D29 FMCP_HSPC_TCK_BUF

C37 VCC12_SW D30 FPGA_TDO_FMC_TDI_BUF

C39 UTIL_3V3 D31 FMCP_HSPC_TDO_HPC1_TDI

Schematic

Net Name

I/O

Standard

J18 Sections C/D Connections to FPGA U1

FPGA

(U1)

J18 FMCP HSCP

Schematic Net Name

D32 UTIL_3V3

D33 FMCP_HSPC_TMS_BUF

D34 NC

D35 GA1 = 0 = GND

D36 UTIL_3V3

D38 UTIL_3V3

D40 UTIL_3V3

I/O

Standard

LVDS AV42

LVDS AV43

FPGA

(U1)

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Table 31: J18 VITA 57.4 FMCP HSCP Connections (cont'd)

J18

FMCP

HSCP

G2 FMCP_HSPC_CLK1_M2C_P LVDS G18 H1 FMCP_HSPC_VREF_A_M2C

G3 FMCP_HSPC_CLK1_M2C_N LVDS G17 H2 FMCP_HSPC_PRSNT_M2C_B

G6 FMCP_HSPC_LA00_CC_P LVDS E24 H4 FMCP_HSPC_CLK0_M2C_P LVDS F24

G7 FMCP_HSPC_LA00_CC_N LVDS E23 H5 FMCP_HSPC_CLK0_M2C_N LVDS F23

G9 FMCP_HSPC_LA03_P LVDS B27 H7 FMCP_HSPC_LA02_P LVDS L23

G10 FMCP_HSPC_LA03_N LVDS A26 H8 FMCP_HSPC_LA02_N LVDS K22

G12 FMCP_HSPC_LA08_P LVDS E27 H10 FMCP_HSPC_LA04_P LVDS C25

G13 FMCP_HSPC_LA08_N LVDS D27 H11 FMCP_HSPC_LA04_N LVDS C24

G15 FMCP_HSPC_LA12_P LVDS J22 H13 FMCP_HSPC_LA07_P LVDS K27

G16 FMCP_HSPC_LA12_N LVDS H22 H14 FMCP_HSPC_LA07_N LVDS J27

G18 FMCP_HSPC_LA16_P LVDS K24 H16 FMCP_HSPC_LA11_P LVDS B26

G19 FMCP_HSPC_LA16_N LVDS K23 H17 FMCP_HSPC_LA11_N LVDS B25

G21 FMCP_HSPC_LA20_P LVDS A21 H19 FMCP_HSPC_LA15_P LVDS J26

G22 FMCP_HSPC_LA20_N LVDS A20 H20 FMCP_HSPC_LA15_N LVDS J25

G24 FMCP_HSPC_LA22_P LVDS B16 H22 FMCP_HSPC_LA19_P LVDS B18

G25 FMCP_HSPC_LA22_N LVDS A16 H23 FMCP_HSPC_LA19_N LVDS B17

G27 FMCP_HSPC_LA25_P LVDS D20 H25 FMCP_HSPC_LA21_P LVDS A19

G28 FMCP_HSPC_LA25_N LVDS D19 H26 FMCP_HSPC_LA21_N LVDS A18

G30 FMCP_HSPC_LA29_P LVDS H19 H28 FMCP_HSPC_LA24_P LVDS C18

G31 FMCP_HSPC_LA29_N LVDS H18 H29 FMCP_HSPC_LA24_N LVDS C17

G33 FMCP_HSPC_LA31_P LVDS H17 H31 FMCP_HSPC_LA28_P LVDS G21

G34 FMCP_HSPC_LA31_N LVDS G16 H32 FMCP_HSPC_LA28_N LVDS F21

G36 FMCP_HSPC_LA33_P LVDS K21 H34 FMCP_HSPC_LA30_P LVDS J20

G37 FMCP_HSPC_LA33_N LVDS J21 H35 FMCP_HSPC_LA30_N LVDS J19

G39 VADJ_1V8_FPGA H37 FMCP_HSPC_LA32_P LVDS H20

Schematic

Net Name

I/O

Standard

J18 Sections G/H Connections to FPGA U1

FPGA

(U1)

J18 FMCP HSCP

Schematic Net Name

I/O

Standard

H38 FMCP_HSPC_LA32_N LVDS G20

H40 VADJ

FPGA

(U1)

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Table 31: J18 VITA 57.4 FMCP HSCP Connections (cont'd)

J18

FMCP

HSCP

L1 NC M2 FMCP_HSPC_DP23_M2C_P LVDS AE49

L4 FMCP_HSPC_GBTCLK4_M2C

L5 FMCP_HSPC_GBTCLK4_M2C

L8 FMCP_HSPC_GBTCLK3_M2C

L9 FMCP_HSPC_GBTCLK3_M2C

L12 FMCP_HSPC_GBTCLK2_M2C

L13 FMCP_HSPC_GBTCLK2_M2C

L16 FMCP_HSPC_SYNC_C2M_P LVDS D25 M15 FMCP_HSPC_DP20_M2C_N LVDS AG54

L17 FMCP_HSPC_SYNC_C2M_N LVDS D24 M18 FMCP_HSPC_DP14_C2M_P LVDS AM46

L20 FMCP_HSPC_REFCLK_C2M_

L21 FMCP_HSPC_REFCLK_C2M_

L24 FMCP_HSPC_REFCLK_M2C_

L25 FMCP_HSPC_REFCLK_M2C_

L28 FMCP_HSPC_SYNC_M2C_P LVDS G23 M27 FMCP_HSPC_DP16_C2M_N LVDS AK47

L29 FMCP_HSPC_SYNC_M2C_N LVDS G22 M30 FMCP_HSPC_DP17_C2M_P LVDS AJ48

L32 NC M31 FMCP_HSPC_DP17_C2M_N LVDS A J49

L33 NC M34 FMCP_HSPC_DP18_C2M_P LVDS AJ44

L36 VCC12_SW M35 FMCP_HSPC_DP18_C2M_N LVDS AJ45

L37 VCC12_SW M38 FMCP_HSPC_DP19_C2M_P LVDS AH46

L40 VCC12_SW M39 FMCP_HSPC_DP19_C2M_N LVDS AH47

Schematic

Net Name

_P(5)

_N(5)

_P(5)

_N(5)

_P(5)

_N(5)

I/O

Standard

J18 Sections L/M Connections to FPGA U1

LVDS AJ40 M3 FMCP_HSPC_DP23_M2C_N LVDS AE50

LVDS AJ41 M6 FMCP_HSPC_DP22_M2C_P LVDS AE53

LVDS AL40 M7 FMCP_HSPC_DP22_M2C_N LVDS AE54

LVDS AL41 M10 FMCP_HSPC_DP21_M2C_P LVDS AF51

LVDS AN40 M11 FMCP_HSPC_DP21_M2C_N LVDS AF52

LVDS AN41 M14 FMCP_HSPC_DP20_M2C_P LVDS AG53

LVDS H24 M19 FMCP_HSPC_DP14_C2M_N LVDS AM47

LVDS H23 M22 FMCP_HSPC_DP15_C2M_P LVDS AL44

LVDS G26 M23 FMCP_HSPC_DP15_C2M_N LVDS AL45

LVDS G25 M26 FMCP_HSPC_DP16_C2M_P LVDS AK46

FPGA

(U1)

J18 FMCP HSCP

Schematic Net Name

I/O

Standard

FPGA

(U1)

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Table 31: J18 VITA 57.4 FMCP HSCP Connections (cont'd)

J18

FMCP

HSCP

Y2 FMCP_HSPC_DP23_C2M_P LVDS AE44 Z1 FMCP_HSPC_PRSNT_M2C_B

Y3 FMCP_HSPC_DP23_C2M_N LVDS AE45 Z4 FMCP_HSPC_DP22_C2M_P LVDS AF46

Y6 FMCP_HSPC_DP21_C2M_P LVDS AG44 Z5 FMCP_HSPC_DP22_C2M_N LVDS AF47

Y7 FMCP_HSPC_DP21_C2M_N LVDS AG45 Z8 FMCP_HSPC_DP20_C2M_P LVDS AG48

Y10 FMCP_HSPC_DP10_M2C_P LVDS AR53 Z9 FMCP_HSPC_DP20_C2M_N LVDS AG49

Y11 FMCP_HSPC_DP10_M2C_N LVDS AR54 Z12 FMCP_HSPC_DP11_M2C_P LVDS AP51

Y14 FMCP_HSPC_DP12_M2C_P LVDS AN53 Z13 FMCP_HSPC_DP11_M2C_N LVDS AP52

Y15 FMCP_HSPC_DP12_M2C_N LVDS AN54 Z16 FMCP_HSPC_DP13_M2C_P LVDS AN49

Y18 FMCP_HSPC_DP14_M2C_P LVDS AM51 Z17 FMCP_HSPC_DP13_M2C_N LVDS AN50

Y19 FMCP_HSPC_DP14_M2C_N LVDS AM52 Z20 FMCP_HSPC_GBTCLK5_M2C_

Y22 FMCP_HSPC_DP15_M2C_P LVDS AL53 Z21 FMCP_HSPC_GBTCLK5_M2C_

Y23 FMCP_HSPC_DP15_M2C_N LVDS AL54 Z24 FMCP_HSPC_DP10_C2M_P LVDS AR48

Y26 FMCP_HSPC_DP11_C2M_P LVDS AR44 Z25 FMCP_HSPC_DP10_C2M_N LVDS AR49

Y27 FMCP_HSPC_DP11_C2M_N LVDS AR45 Z28 FMCP_HSPC_DP12_C2M_P LVDS AP46

Y30 FMCP_HSPC_DP13_C2M_P LVDS AN44 Z29 FMCP_HSPC_DP12_C2M_N LVDS AP47

Y31 FMCP_HSPC_DP13_C2M_N LVDS AN45 Z32 FMCP_HSPC_DP16_M2C_P LVDS AL49

Y34 FMCP_HSPC_DP17_M2C_P LVDS AK51 Z33 FMCP_HSPC_DP16_M2C_N LVDS AL50

Y35 FMCP_HSPC_DP17_M2C_N LVDS AK52 Z36 FMCP_HSPC_DP18_M2C_P LVDS AJ53

Y38 FMCP_HSPC_DP19_M2C_P LVDS AH51 Z37 FMCP_HSPC_DP18_M2C_N LVDS AJ54

Y39 FMCP_HSPC_DP19_M2C_N LVDS AH52 Z40 UTIL_3V3

Schematic

Net Name

I/O

Standard

J18 Sections Y/Z Connections to FPGA U1

FPGA

(U1)

J18 FMCP HSCP

Schematic Net Name

I/O

Standard

LVDS AG40

LVDS AG41

FPGA

(U1)

UG1302 (v1.0) December 21, 2018 www.xilinx.com VCU128 Board User Guide 85

More informaon about the VITA 57.4 FMC+ specicaon is available on the VITA FMC

Markeng Alliance website.

Board Power System

[Figure 2, callout 34]

The VCU128 board has an Intersil power system. The following gure shows the VCU128 board power system block diagram.

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Figure 29: Power System Block Diagram

12V Vin

252W (PCIe

brick option)

*Wattage calculations based on XPE requirements plus 25%

UTIL_3V3

3.3V @ 20A ISL68301 + ISL919227B

UTIL_5V0

5.0V @ 20A ISL68301 + ISL919227B

overhead for soft IP flexibility

DDR4_VTERM_0V6

0.6V @ 3A TPS51200

RLD3_VTERM_0V6

0.6V @ 3A TPS51200

62W

VCC1V8

1.8V @ 6A

ISL91302B (A+B)

VADJ

1.8V @ 6A

ISL91302B (C+D)

SYS_1V8

1.8V @ 1A

ISL91211 (A)

MGTVCCAUX

1.8V @ 1A

ISL91211A (B)

MGTAVCC

0.9V @ 10A

ISL91211A (C+D)

QDR4_VDDQ_1V2

1.2V @ 6A

ISL91302 (A+B)

UTIL_1V30

1.30V @ 6A

ISL91302B (C+D)

16W

11W

12W

Current

Shunt

Current

Shunt

Current

Shunt

VCCHBM

1.2V @ 25A ISL68301 + ISL919227B

MGTAVTT

1.2V @ 20A ISL68301 + ISL919227B

VCCINT

0.85V @ 125A ISL68127 +

ISL919227 (5)

VCCBRAM

0.85V @ 30A ISL68127 +

ISL919227 (1)

22W

18W

103W

DDR4_VDDQ_1V2

1.2V @ 3A

ISL91302 (A+B+D)

RLD3_VDDQ_1V2

1.2V @ 10A

ISL91302 (C)

UTIL_1V35

1.35V @ 10A

ISL91302B (A+B+D)

SYS_1V0

1.0V @ 2A

ISL91302B (C)

VCCAUX_HBM

2.5V @ 1.5A ISL80019

11W

10W

Current

Shunt

Current

Shunt

Current

Shunt

Current

Shunt

Current

Shunt

X21654-121718

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Onboard Power System Devices

The VCU128 evaluaon board uses programmable power regulators from Intersil Corporaon to supply the core and auxiliary voltages listed in the following table.

Table 32: Onboard Power System Devices

Schematic

Page

54 VCCINT (PWM[2:6]) ISL68127IRAZ-TR5823 U31 0.72 -

54 VCCBRAM (PWM[0]) ISL68127IRAZ-TR5823 U31 0.72 -

56 VCC1V8 (PH_A/B) ISL91302BIKZ-TR5814 U15 1.8 4 - 6 0x63 U14 0X42

56 VADJ (PH_C/D) ISL91302BIKZ-TR5814 U15 0, 0.3

57 VCCHBM ISL68301IRAZ-TR5823 U36 1.2 25 0x68 U85 0x4C

57 MGTAVTT ISL68301IRAZ-TR5823 U24 1.2 20 0x69 U21 0x47

58 SYS_1V8 (PH_A) ISL91211AIKZ-TR5818 U22 1.8 0.75 - 1 0x60 NA NA

58 MGTVCCAUX (PH_B) ISL91211AIKZ-TR5818 U22 1.8 0.75 - 1 0x60 U20 0x48

58 MGTAVCC (PH_C/D) ISL91211AIKZ-TR5818 U22 0.9 8 - 10 0x60 U16 0x46

59 QDR4_VDDQ (PH_A/B) ISL91302BIKZ-TR5815 U44 1.2 5 - 6 0x62 NA NA

59 UTIL_1V30 (PH_C/D) ISL91302BIKZ-TR5815 U44 1.3 4.5 - 6 0x62 NA NA

60 RLD3_VDDQ (PH_A/B/D) ISL91302BIKZ-TR5816 U67 1.2 7 - 10 0x64 NA NA

60 DDR4_VDDQ (PH_C) ISL91302BIKZ-TR5816 U67 1.2 2.5 - 3 0x64 NA NA

61 UTIL_1V35 (PH_A/B/D) ISL91302BIKZ-TR5817 U68 1.35 6.5 - 10 0x61 NA NA

61 SYS_1V0 (PH_C) ISL91302BIKZ-TR5817 U68 1 1.75 - 2 0x61 NA NA

62 UTIL_3V3 ISL68301IRAZ-TR5826 U3 3.3 30 0x6A NA NA

62 UTIL_5V0 ISL68301IRAZ-TR5825 U12 5 20 0x6B NA NA

63 VCCAUX_HBM SL80019FRZ-T7A U29 2.5 1.5 NA U79 0x4D

65 VCC_3V3 ISL85415FRZ-T7A U25 3.3 20 NA NA NA

33 DDR4_VTERM_0V6 TPS51200DR U71 0.6 3 NA NA NA

33 RLD3_VTERM_0V6 TPS51200DR U92 0.6 3 NA NA NA

Notes:

1. Jumper selectable at 3-pin header J25: 1-2=0.85V (default); 2-3=0.72V.

Rail Name Regulator Type U#

Programmable Regulators and INA226 Map

Programmable Regulators

Non-I2C Regulators

Vout

(V)

0.85

-1.8

Iout

Range

(A)

125 0X65 U84 0x40

30 0X65 U86 0x41

4.5 - 6 0x63 NA NA

I2C

Address

INA226

I2C

Address

UG1302 (v1.0) December 21, 2018 www.xilinx.com VCU128 Board User Guide 87

Documentaon describing the programming of the Intersil power controllers is available on the Intersil website (see References). The PCB layout and power system design meet the recommended criteria described in the UltraScale Architecture PCB Design User Guide (UG583).

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FMCP HSPC Connector J18 VADJ Power Rail

The VCU128 evaluaon board implements the ANSI/VITA 57.4 IPMI support funconality. The power control of the VADJ power rail is managed by the U42 system controller. This rail powers both the FMCP HSPC (J18) VADJ pins, as well as XCVU37P U1 HP banks 71 and 72 (see I/O

Voltage Rails). The valid values of the VADJ rail are 1.2V, 1.5V, and 1.8V.

At power on, the system controller detects if an FMC module is connected to FMCP J18:

• If no FMC card is aached to the FMC port, the VADJ voltage is set to 0V

•

When an FMC card is aached, its IIC EEPROM is read to nd a VADJ voltage supported by both the VCU128 board and the FMC module, within the available choices of 1.2V, 1.5V, 1.8V, and 0.0V

•

If no valid informaon is found in the IIC EEPROM, the VADJ rail is set to 0V

The system controller user interface allows the FMC IPMI roune to be overridden and an explicit value to be set for the VADJ rail.

Monitoring Voltage and Current

[Figure 2, callout 35]

Voltage and current monitoring and control for the Intersil power system is available through either the VCU128 system controller or the Intersil PowerNavigator soware GUI. The VCU128 system controller is a simple and convenient way to monitor the voltage and current values for the power rails listed in the following table. The Intersil programmable power controllers listed in the table can also be accessed through the 2x3 male pin header J1. Using this connector requires the Intersil ZLUSBEVAL3Z USB to PMBus adapter. This adapter cable can be ordered from the Intersil website (see References). The associated Intersil PowerNavigator soware GUI can be downloaded from the Intersil website. The Intersil programmable controller and INA226 power monitor I2C bus mapping is shown in the following table.

Table 33: Programmable Controller and INA226 Power Monitor I2C Bus Mapping

Schematic

Page

54 VCCINT (PWM[2:6]) ISL68127IRAZ-TR5823 U31 0.72 -

54 VCCBRAM (PWM[0]) ISL68127IRAZ-TR5823 U31 0.72 -

56 VCC1V8 (PH_A/B) ISL91302BIKZ-TR5814 U15 1.8 4 - 6 0x63 U14 0X42

Rail Name Regulator Type U#

Programmable Regulators and INA226 Map

Programmable Regulators

Vout

(V)

0.85

Iout

Range

(A)

125 0X65 U84 0x40

30 0X65 U86 0x41

I2C

Address

INA226

I2C

Address

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Table 33: Programmable Controller and INA226 Power Monitor I2C Bus Mapping (cont'd)