Xilinx VCU128 User Manual
VCU128 Evaluaon Board
User Guide
UG1302 (v1.0) December 21, 2018
Table of Contents
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Revision History...............................................................................................................4
Chapter 1: Introduction.............................................................................................. 5
Overview.......................................................................................................................................5
Additional Resources.................................................................................................................. 5
Block Diagram..............................................................................................................................6
Board Features............................................................................................................................ 6
Board Specifications....................................................................................................................8
Chapter 2: Board Setup and Configuration......................................................9
Electrostatic Discharge Caution.................................................................................................9
Board Component Location.......................................................................................................9
Default Switch and Jumper Settings....................................................................................... 13
Installing the Board in a PC Chassis........................................................................................14
FPGA Configuration...................................................................................................................16
Chapter 3: Board Component Descriptions................................................... 18
Overview.....................................................................................................................................18
Component Descriptions......................................................................................................... 18
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VCU128 Board User Guide 2
Appendix A: VITA 57.4 FMCP Connector Pinouts......................................... 93
Overview.....................................................................................................................................93
Appendix B: Xilinx Constraints File.................................................................... 94
Overview.....................................................................................................................................94
Appendix C: Regulatory and Compliance Information........................... 95
Overview.....................................................................................................................................95
CE Directives.............................................................................................................................. 95
CE Standards..............................................................................................................................95
Compliance Markings............................................................................................................... 96
Appendix D: Additional Resources and Legal Notices.............................97
Xilinx Resources.........................................................................................................................97
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Documentation Navigator and Design Hubs.........................................................................97
References..................................................................................................................................98
Please Read: Important Legal Notices................................................................................. 100
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VCU128 Board User Guide 3
Revision History
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The following table shows the revision history for this document.
Revision History
Section
12/21/2018 Version 1.0
Initial Xilinx release. N/A
Revision Summary
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VCU128 Board User Guide 4
Introduction
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Overview
The VCU128 board incorporates the VU37P high bandwidth memory (HBM) FPGA, which
ulizes stacked silicon interconnect (SSI) technology to add HBM die next to the FPGA die on the
package substrate. The VCU128 evaluaon board for the Xilinx® Virtex® UltraScale+™ FPGA
provides a hardware environment for developing and evaluang designs targeng the UltraScale
+ XCVU37P-2FSVH2892E device. The VCU128 evaluaon board is equipped with many of the
common board-level features needed for design development as listed here.
• DDR4, RLD-3, and QDR-IV component memory
• Ganged small form-factor pluggable (QSFP28) connectors
Chapter 1
• Sixteen-lane PCI Express® interface
• Ethernet PHY
• General purpose I/O
• UART interface
Addional features can be supported using modules compable with the VITA-57.4 (FMCP
HSPC) connector on the VCU128 board.
Additional Resources
See Appendix D: Addional Resources and Legal Noces for references to documents, les, and
resources relevant to the VCU128 evaluaon board.
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VCU128 Board User Guide 5
Chapter 1: Introduction
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Block Diagram
A block diagram of the VCU128 evaluaon board is shown in the following gure.
Figure 1: Evaluation Board Block Diagram
PCIE_EP_TX/RX[0:3]
PCIE_CLK2
PCIE_EP_TX/RX[4:7]
PCIE_EP_TX/RX[8:11]
PCIE_CLK1
PCIE_EP_TX/RX[12:15]
INIT LED
DONE LED
PROG_B PB
1.5V BATT.
QSPI 2Gb
36-bit QDR-IV SDRAM
(shown at banks 68, 69)
36-bit DQB-port
235
not used
234
not used
233
not used
232
not used
231
not used
230
not used
229
not used
228
not used
227
226
225
224
69
36-bit DQA-port + common
36-bit QDR-IV SDRAM 4Mx36 Dual-Port
CY7C4142KV13_106FCXC
36-bit DQB-port
Bank 70
70 71 72 75 74 73 135
68
FMCP HSPC
LA[00:33]
0
XCVU37P-FSVH2892
HBM_43_PWR HBM_43_PWR
0
HBM_83
used
67 64
Not
GPIO 1.8V
ENET
LED[0:7]
PL_I2C0 BUS
UART0, UART1
QSFP1, QSFP4 CTRL
SMA_CLK OUT(P/N)
SYSCTLR_UCA1 (TX/RX)
72-bit RLD-3 (2x32Mx36)
MT44K32M36RB-107E
NC
Not
used
65 66
72-bit DDR4 Comp. Memory
MT40A512M16LY-075E
HBM_43
Not used
Not used
134
133
not used
132
131
130
not used
129
128
127
126
125
124
(4.5X512MX16)
QSFP1 TX/RX[1:4]
QSFP1_SI570_CLOCK
QSFP2 TX/RX[1:4]
QSFP2_SI570_CLOCK
SI5328_CLOCK1
QSFP3 TX/RX[1:4]
QSFP3_SI570_CLOCK
SI5328_CLOCK2
QSFP4 TX/RX[1:4]
QSFP4_SI570_CLOCK
SMA_REFCLK_INPUT
FMCP_HSPC_DP[20:23]
FMCP_HSPC_GBTCLK5
FMCP_HSPC_DP[16:19]
FMCP_HSPC_GBTCLK4
FMCP_HSPC_DP[12:15]
FMCP_HSPC_GBTCLK3
FMCP_HSPC_DP[8:11]
FMCP_HSPC_GBTCLK2
FMCP_HSPC_DP[4:7]
FMCP_HSPC_GBTCLK1
FMCP_HSPC_DP[0:3]
FMCP_HSPC_GBTCLK0
System Controller
XC7Z010CLG225
GPIO
X21647-112818
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VCU128 Board User Guide 6
Board Features
The VCU128 evaluaon board features are listed here. Detailed informaon for each feature is
provided in Chapter 3: Board Component Descripons.
• Virtex® UltraScale+™ XCVU37P-2FSVH2892E device
• Zynq®-7000 SoC XC7Z010 based system controller
• 4.5 GB DDR4 72-bit component memory interface (4.5 x [512 Mb x 16])
Chapter 1: Introduction
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• 144 Mb 36-bit dual-port QDR-IV component memory interface (1 x [4M x 36])
• 288 MB 72-bit RLD3 component memory interface (2 x [1.125 Gb x 36])
• 2 Gb Quad SPI ash conguraon memory
• QSFPF28 - Sixteen (16) GTY transceivers are allocated for a 1x4 QSFP cage
• USB JTAG interface (FTDI FT4232HL with a micro-AB USB connector)
• Clock sources:
○ SMA I/F clocks:
- FPGA bank 67 SMA clock P/N
○ QSFP clocks:
- Four Si570 I2C programmable clock oscillators (156.25 MHz default)
- QSFP clock recovery Si5328 input to GTY132 and GTY134
- QSFP external SMA di. clock input to GTY131
○ Memory I/F clocks:
- Three SiT9120A xed 100 MHz LVDS clock oscillators
○ PCIe
®
I/F clock:
- Fixed 100 MHz HCSL clock from PCI Express® edge input to 1-to-2 clock buer wired
to GTY225 and GTY227
○ System controller clock:
- SiT8008A 33.33 MHz single-ended clock oscillator
• 96 GTY transceivers (24 Quads)
○ FMCP HSPC connector (twenty-four GTY transceivers)
○ 4x28 Gb/s QSFP+ connectors (eight GTY transceivers)
○ PCIe 16-lane edge connector (sixteen GTY transceivers)
○ Not used (forty-eight GTY transceivers)
• PCI Express® Endpoint connecvity
○ Gen1 (x1, x2, x4, x8, x16)
○ Gen2 (x1, x2, x4, x8, x16)
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VCU128 Board User Guide 7
○ Gen3 (x1, x2, x4, x8, x16)
○ Dual Gen4 (x1, x2, x4, x8)
• Ethernet PHY SGMII interface with RJ-45 connector
• Dual USB-to-UART bridge with micro-B USB connector (shared FTDI FT4232HL)
Chapter 1: Introduction
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• I2C bus
• Status LEDs
• User I/O (1 x push-buon switch, 8 x LED)
• VITA 57.4 FMC+ HSPC connector (DP[0:23], LA[0:33])
• Power management with I2C voltage monitoring through Intersil power controllers and GUI
• Conguraon opons:
○ Quad SPI ash memory
○ USB JTAG I/F (FTDI FT4232HL)
○ Plaorm cable USB II interface 2x7 2 mm keyed connector
Board Specifications
Dimensions
Height: 7.53 inch (19.14 cm)
Length: 9.50 inch (24.13 cm)
Thickness (±5%): 0.061 inch (0.1549 cm)
Note: A 3D model of this board is not available.
IMPORTANT
PCI Express® card.
! The VCU128 board height exceeds the standard 4.376-inch (11.15 cm) height of a
Environmental
Temperature
Operang: 0°C to +45°C, Storage: -25°C to +60°C
Humidity
10% to 90% non-condensing
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VCU128 Board User Guide 8
Operating Voltage
+12 VDC
Chapter 2
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Board Setup and Configuration
Electrostatic Discharge Caution
CAUTION! ESD can damage electronic components when they are improperly handled, and can result
in total or intermient failures. Always follow ESD-prevenon procedures when removing and replacing
components.
To prevent ESD damage:
• Use an ESD wrist or ankle strap and ensure that it makes skin contact. Connect the equipment
end of the strap to an unpainted metal surface on the chassis.
• Avoid touching the adapter against your clothing. The wrist strap protects components from
ESD on the body only.
• Handle the adapter by its bracket or edges only. Avoid touching the printed circuit board or
the connectors.
• Put the adapter down only on an anstac surface such as the bag supplied in your kit.
• If you are returning the adapter to Xilinx® Product Support, place it back in its anstac bag
immediately.
Board Component Location
The following gure shows the VCU128 board component locaons. Each numbered component
shown in the gure is keyed to the table in Board Component Descripons.
IMPORTANT! The board component locaons gure is for visual reference only and might not reect
the current revision of the board.
IMPORTANT! There could be mulple revisions of this board. The specic details concerning the
dierences between revisions are not captured in this document. This document is not intended to be a
reference design guide and the informaon herein should not be used as such. Always refer to the
schemac, layout, and XDC les of the specic VCU128 version of interest for such details.
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VCU128 Board User Guide 9
Chapter 2: Board Setup and Configuration
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Figure 2: Evaluation Board Component Locations
15
16
24
Round callout references a component
00
on the front side of the board
24
18
19
5
31
Square callout references a component
00
on the back side of the board
27
35
4
4
34
25
26
2
1
3
36
10
34
22
38
23
22
28
30
29
32
39
33
17
14
13
37
11
20
20
21
6
7
12
9
40
8
X22144-121718
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VCU128 Board User Guide 10
Chapter 2: Board Setup and Configuration
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Board Component Descriptions
The following table idenes the components, references the respecve schemac page
numbers, and links to a detailed funconal descripon of the components and board features in
Chapter 3: Board Component Descripons.
Table 1: Board Component Descriptions
Schematic
Callout Feature [U#] = Bottom Notes
1 Virtex UltraScale+ XCVU37P-2FSVH2892E
Device (with fan-sink on soldered FPGA)
2 GTY transceivers, Right-side Quads (twelve
quads)
3 GTY transceivers, Left-side Quads (twelve
quads)
4 DDR4 Component Memory, 72-bit DDR4
component memory I/F, (U17-U19), [U73,
U74]
5 RLD3 Component Memory, RLD3 72-bit
component memory I/F (U37, U39)
6 QDR4 Component Memory (U40) Cypress CY7C4142KV13-106FCXC 27
7 Quad SPI Flash Memory (U46) Micron MT25QU02GCBB8E12-0SIT 3
8 System Controller, Zynq®-7000 SoC (U42) XC7Z010CLG225 48-50
9 System Controller Quad SPI Flash Memory
[U89]
10 DDR4 Component Memory I/F clock, fixed
100 MHz LVDS [U76]
11 RLD3 Component Memory I/F clock, fixed
100 MHz LVDS (U45)
12 QDR4 Component Memory I/F clock, fixed
100 MHz LVDS [U96]
13 Programmable QSFP1 Clock I2C, LVDS
[U95]
14 Programmable QSFP2 Clock I2C, LVDS
[U90]
15 Programmable QSFP3 Clock I2C, LVDS
[U82]
16 Programmable QSFP4 Clock I2C, LVDS
[U80]
17 QSFP Jitter Attenuated Clock, [U87] Silicon Labs SI5328B-C-GMR 40
18 User QSFP SMA Clock pair J24(P)/J26(N)
input to XCVU37P U1 GTY131
MGTREFCLK1P/N
19 Four 28 Gb/s zQSFP+ Module Connectors,
QSFP1-4 (J42), (J39), (J35), (J32) + 1x4
ganged cage
XCVU37P-2FSVH2892E
Cofan 30-4811
Embedded within FPGA U1 14-15
Embedded within FPGA U1 16-17
5 x Micron MT40A256M16GE-075E 24-26
2 x Micron MT44K32M36RB-107E 29-30
Micron MT25QU02GCBB8E12-0SIT 49
SiTime SIT9120AI-2D3-33E100.0000 32
SiTime SIT9120AI-2D3-33E100.0000 32
SiTime SIT9120AI-2D3-33E100.0000 32
Silicon Labs SI570BAB0000544DG
(default 156.250 MHz)
Silicon Labs SI570BAB0000544DG
(default 156.250 MHz)
Silicon Labs SI570BAB0000544DG
(default 156.250 MHz)
Silicon Labs SI570BAB0000544DG
(default 156.250 MHz)
Rosenberger 32K10K-400L5 12
4 x TE 1551920-2 connectors with TE 2170745-2
cage with heatsink
Page
Number
40
40
40
40
38, 39
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VCU128 Board User Guide 11
Chapter 2: Board Setup and Configuration
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Table 1: Board Component Descriptions (cont'd)
Callout Feature [U#] = Bottom Notes
20 PCI Express Endpoint Connectivity,
PCI Express® 16-lane connector (P1)
21 PCI Express Endpoint Connectivity 100
MHz REFCLK 1-to-2 clock buffer,
differential-to-LVDS [U94]
22 10/100/1000 Mb/s Tri-speed Ethernet PHY
with RJ45, SGMII mode only, [U62], (P2)
23 Ethernet PHY Status LEDs, LEDs are
integrated into P2 bezel
24 USB JTAG Interface, USB bridge (U8) with
mini-B USB connector (J2) and 2x7 2 mm
prog. cable connector (J4)
25 I2C Bus, Topology, and Switches I2C0 bus
topology: I2C bus MUX [U55], 16-bit
expansion port [U65]
26 I2C Bus, Topology, and Switches I2C0 bus
topology: 2 x I2C bus MUX [U53, U54]
28 User GPIO LEDs (DS2-DS9), active-High Lumex SML-LX0603GW-TR 47
29 User GPIO pushbutton, CPU reset (SW4),
active-High
30 Switches, program_B pushbutton, (SW2),
active-Low
31 FMCP Connector J18, (J18) Samtec ASP_184329_01 42-46
32 Board Power System Power Input
Connector, (J16)
33 Board Power System power input switch,
on/off slide switch (SW5)
34 Board Power System, power management
system (top and bottom)
35 Monitoring Voltage and Current, PMBus
2x3 R.A. male pin header (J1)
36 Configuration Options, FPGA U1
configuration mode DIP switch, (SW1)
37 PCI Express Endpoint Connectivity, lane
width select header, (J46)
38 Jumpers, FPGA POR_OVERRIDE select
header, (J14)
39 Jumpers, FPGA VCCINT select header, (J25) 1x3 0.1-inch male header Sullins PBC36SAAN 54
40 Jumpers, SYS CTLR RE-PROG header, (J43) 1x2 0.1-inch male header Sullins PBC36SAAN 50
16-lane card edge connector 41
ICS ICS85411AMLF 14
TI DP83867ISRGZ with Wurth 7499111221A RJ45
(with magnetics)
Wurth 7499111221A RJ45 integrated status LEDs 37
FTDI FT4232HL bridge
Hirose ZX62D-AB-5P8 connector
Molex 87832-1420
TI PCA9544ARGYR
TI TCA6416APWR
2 x TI TCA9548APWR 36
E-Switch TL3301EF100QG 47
E-Switch TL3301EF100QG 3
2x6 Molex-39-30-1060 52
C&K 1201M2S3AQE2 52
Intersil power system 54-65
Amphenol 68021-406HLF 54
4-pole CTS 218-4LPSTRF 3
2x4 0.1-inch male header Sullins PBC36DAAN 41
1x3 0.1-inch male header Sullins PBC36SAAN 3
Schematic
Page
Number
37
34
35
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VCU128 Board User Guide 12
The VCU128 board schemacs are available for download from the VCU128 Evaluaon Kit
website.
Chapter 2: Board Setup and Configuration
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Default Switch and Jumper Settings
Switches
Default switch sengs are listed in the following table. The switch locaons are shown in Figure
2. The following table also references the respecve schemac page numbers.
Table 2: Default Switch Settings
Switch Function Default Comments
SW5 On/Off SPST slide switch OFF Board shipped with power switch off 33 52
SW1 4-pole configuration
Default = SPI
SW2 FPGA_PROG_B P.B. NA U1 XCVU37P PROG_B (active low) 30 3
SW3 SYSCTLR_POR_B P.B. NA U42 XC7Z010 POR_B (active low) Near
SW4 CPU_RESET P.B. NA U1 XCVU37P USER P.B. (active high) 29 47
Notes:
1. DIP switch sections are active-High (connected net is pulled High when DIP switch is closed = 1).
1
SW1[1:4] =
0001
Position 1 = System Controller Enable
SW1[2:4] = FPGA U1 mode M[2:0] = 001
Figure 2
Callout
36 3
29
Schematic
Page
50
Jumpers
Default jumper sengs are listed in the following table. Jumper header locaons are shown in
Figure 2. The following table also references the respecve schemac page numbers.
Table 3: Default Jumper Settings
Jumper Function Default Comments
J14 Power on reset (POR)
override
J25 VCCINT select 1-2 1-2: 0.85V; 2-3: 0.72V
J46 PCIe lane size select 7-8 16-lane configuration 37 41
J43 SYSCTLR RE-PROG Off U42 XCZU7010 MIO5 pin
Notes:
1. VCCINT select header J25 should always have a jumper block installed.
2-3 U1 POR_OVERRIDE pin
BG15 to GND
1
A9
Figure 2
Callout
38 3
39 54
40 50
Schematic
Page
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VCU128 Board User Guide 13
Chapter 2: Board Setup and Configuration
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Installing the Board in a PC Chassis
The VCU128 board 12V power input circuitry allows 12V to be applied through one of two
connectors, J16 (typically used with the stand-alone VCU128 power adapter) or JP1, as shown in
the following gure.
Figure 3: 12V Power Entry
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VCU128 Board User Guide 14
Installaon of the VCU128 board inside a computer chassis is required when developing or
tesng PCI Express® funconality. When the VCU128 board is used inside a computer chassis
(i.e., plugged in to a PCIe® slot), power is provided by choosing one of two mutually exclusive
ATX power supply cables as described in this secon (use one cable or the other).
• The ATX power supply 4-pin (1x4) peripheral connector, which requires using the ATX
adapter cable (see the following gure) to connect to J16 on the VCU128 board. The Xilinx
part number for this cable is 2600304. See ATX Power Supply Adapter Cable.
X22058-121318
®
Chapter 2: Board Setup and Configuration
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Figure 4: ATX Power Supply Adapter Cable
To ATX 4-Pin Peripheral
Power Connector
To J16 on VCU128 Board
X21955-121918
• The ATX supply 8-pin (2x4) PCIe power connector, which plugs into JP1 on the VCU128
board.
Steps to Install Board
To install the board in a PC chassis:
1. On the VCU128 board, remove the ve screws retaining the ve rubber feet and standos,
and the PCIe bracket. Reinstall the PCIe® bracket using two of the previously removed
screws.
2. Power down the host computer and remove the power cord from the PC.
3. Open the PC chassis following the instrucons provided with the PC.
4. The VCU128 board has a large cooling fan that requires two adjacent PCIe slots. Ensure the
slot adjacent to the front of the board is free of obstrucons.
5. Remove the PCIe expansion slot cover (at the back of the chassis) which aligns with the
VCU128 PCIe bracket, by removing the screws on the top and boom of the cover.
6. Plug the VCU128 board into the appropriate open slot.
7. Install the top mounng bracket screw into the PC expansion cover retainer bracket to secure
the VCU128 board in its slot.
8. If using the ATX supply 4-pin (1x4) peripheral connector, connect power to the VCU128
board using the ATX power supply adapter cable as shown in Figure 4.
a. Plug the 6-pin 2 x 3 Molex connector end of the adapter cable into J16 on the VCU128
board.
b. Plug the 4-pin 1 x 4 peripheral power connector from the ATX power supply into the 4-
pin adapter connector end of the cable.
CAUTION
! Do NOT plug a PC ATX power supply 6-pin connector into J16 on the VCU128 evaluaon
board. The ATX 6-pin connector has a dierent pinout than J16. Connecng an ATX 6-pin connector
into J16 damages the VCU128 evaluaon board and voids the board warranty.
c. Slide the VCU128 board power switch SW5 to the ON posion. The PC can now be
powered on.
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VCU128 Board User Guide 15
Chapter 2: Board Setup and Configuration
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9. If using the ATX supply 8-pin (2x4) PCIe power connector, plug the connector into VCU128
board JP1. The PC can now be powered on.
FPGA Configuration
The VCU128 board supports two of the ve UltraScale+™ FPGA conguraon modes:
• Quad SPI ash memory (2 Gb)
•
JTAG using:
○ USB JTAG conguraon port (U8 FT4232HL + USB J2 micro-AB)
○ Xilinx
®
Plaorm Cable USB II, 2 mm, keyed at cable header (J4)
Each conguraon interface corresponds to one or more conguraon modes and bus widths, as
listed in the following table. The mode switches M2, M1, and M0 are on SW1 posions 2, 3, and
4, respecvely. The FPGA default mode seng M[2:0] = 001 selects the master SPI
conguraon mode.
Table 4: Configuration Modes
Configuration Mode
Master SPI
JTAG
SW1 DIP Switch
Settings M[2:0]
1
101
Bus Width CCLK Direction
x1, x2, x4 Output
x1 NA
For complete details on conguring the FPGA, see UltraScale Architecture Conguraon User Guide
(UG570). The following gure shows the conguraon mode DIP switch SW1 JTAG switch
posions.
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VCU128 Board User Guide 16
Chapter 2: Board Setup and Configuration
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Figure 5: SW1 JTAG Mode Settings
ON Position = 1
OFF Position = 0
SCEM2M1
1 2 3 4
M0
SW1
X21648-121918
JTAG
The Vivado®, Xilinx® SDK, or third-party tools can establish a JTAG connecon to the XCVU37P
FPGA through the FTDI FT4232 USB-to-JTAG/USB UART device (U8) connected to the microUSB connector (J2). Alternavely, a JTAG cable can be connected to the keyed at cable header
(J4). JTAG iniated conguraon takes priority over the conguraon method selected through
the FPGA mode pins M[2:0], wired to SW1 posions [2:4].
Quad SPI
To boot from the dual Quad SPI non-volale conguraon memory, follow these steps.
1. Store a valid XCVU37P FPGA boot image in the 2 Gbit Quad SPI ash device (U46)
connected to the FPGA bank 0 Quad SPI interface. See the VCU128 Restoring Flash Tutorial
(XTP533) for informaon on programming the QSPI.
2. Set the boot mode pins SW1 M[2:0] as indicated in the conguraon modes table in FPGA
Conguraon for master SPI.
3. Power-cycle the VCU128 board. Mode SW1 is callout 36 in Figure 2.
See the VCU128 Soware Install and Board Setup Tutorial (XTP535) for more informaon.
See System Controller for an overview of query and control of select programmable board
features such as clocks, FMCP funconality, and power systems. See the VCU128 System
Controller Tutorial (XTP534) for more informaon.
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VCU128 Board User Guide 17
Chapter 3: Board Component Descriptions
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Chapter 3
Board Component Descriptions
Overview
This chapter provides a detailed funconal descripon of the board’s components and features.
Table 1 idenes the components, references the respecve schemac page numbers, and links
to the corresponding detailed funconal descripon in this chapter. Component locaons are
shown in Figure 2.
Component Descriptions
Virtex UltraScale+ XCVU37P-2FSVH2892E Device
[Figure 2, callout 1]
The VCU128 board incorporates the VU37P high bandwidth memory (HBM) FPGA, which
ulizes stacked silicon interconnect (SSI) technology to add HBM die next to the FPGA die on the
package substrate. The VCU128 board is populated with the Virtex® UltraScale+™
XCVU37P-2FSVH2892E device. For more informaon on Virtex UltraScale+ FPGAs, see Virtex
UltraScale+ FPGA Data Sheet: DC and AC Switching Characteriscs (DS923).
Encryption Key Battery Backup Circuit
The XCVU37P device U1 implements bitstream encrypon key technology. The VCU128 board
provides the encrypon key backup baery circuit shown in the following gure.
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VCU128 Board User Guide 18
Chapter 3: Board Component Descriptions
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Figure 6: Encryption Key Backup Circuit
X21956-112918
The Seiko TS621E rechargeable 1.5V lithium buon-type baery B1 is soldered to the board
with the posive output connected to the XCVU37P device U1 VBATT pin BD13. The baery
supply current IBATT specicaon is 150 nA maximum when the board power is o. B1 is
charged from the VCC1V8_BUS 1.8V rail through a series diode with a typical forward voltage
drop of 0.38V and 4.7 KΩ current limit resistor. The nominal charging voltage is 1.42V.
I/O Voltage Rails
There are 12 I/O banks and 2 high-bandwidth memory (HBM) banks available on the XCVU37P
device. The VCU128 board does not use the HBM banks. The voltages applied to the FPGA I/O
banks on the VCU128 board are listed in the following table.
Table 5: I/O Bank Voltage Rails
FPGA (U1) Bank Power Supply Rail Net Name Voltage
Bank 0 VCC1V8 1.8V
HP bank 64 DDR4_VDDQ_1V2 1.2V
HP bank 65 DDR4_VDDQ_1V2 1.2V
HP bank 66 DDR4_VDDQ_1V2 1.2V
HP bank 67 VCC1V8 1.8V
HP bank 68 QDR4_VDDQ_1V2 1.2V
HP bank 69 QDR4_VDDQ_1V2 1.2V
HP bank 70 QDR4_VDDQ_1V2 1.2V
HP bank 71 VADJ 1.8V
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Table 5: I/O Bank Voltage Rails (cont'd)
FPGA (U1) Bank Power Supply Rail Net Name Voltage
HP bank 72 VADJ 1.8V
HP bank 73 RLD3_VDDQ_1V2 1.2V
HP bank 74 RLD3_VDDQ_1V2 1.2V
HP bank 75 RLD3_VDDQ_1V2 1.2V
HBM_43 (not used) VCCHBM/VCCAUX_HBM 1.2V/1.8V
HBM_83 (not used) VCCHBM/VCCAUX_HBM 1.2V/1.8V
DDR4 Component Memory
[Figure 2, callout 4]
The 4.5 GB DDR4 component memory system is comprised of ve 512 Mb x 16 DDR4 SDRAM
devices implemented in clam-shell fashion located at U17-U19 (top) and U73-U74 (boom). Half
of the U19 16-bits are used (4.5 x 16-bits = 72-bit wide interface).
• Manufacturer: Micron
• Part Number: MT40A512M16LY-075E
• Descripon:
○ 8 Gb (512 Mb x 16)
○ 1.2V 96-ball TFBGA
○ DDR4-2666
The VCU128 XCVU37P FPGA DDR4 interface performance is documented in the Virtex
UltraScale+ FPGA Data Sheet: DC and AC Switching Characteriscs (DS923).
The 72-bit wide DDR4 memory system is connected to XCVU37P U1 HP banks 64, 65 and 66.
The DDR4 0.6V VTT terminaon voltage (net DDR4_VTERM_0V6) is sourced from the TI
TPS51200DR linear regulator U71. The DDR4 memory interface bank VREF pins are not
connected, which, coupled with an XDC set_property INTERNAL VREF constraint, invoke the
INTERNAL VREF mode. The connecons between the 72-bit interface DDR4 component
memories and XCVU37P banks 64, 65, and 66 are listed in the following table.
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Table 6: DDR4 Memory 72-bit I/F to FPGA U1 Banks 64, 65, and 66
FPGA (U1) Pin
BM45 PL_DDR4_DQ0 POD12_DCI A3 DQ8 U74
BP44 PL_DDR4_DQ1 POD12_DCI B8 DQ9 U74
BP47 PL_DDR4_DQ2 POD12_DCI C3 DQ10 U74
BN45 PL_DDR4_DQ3 POD12_DCI C7 DQ11 U74
BM44 PL_DDR4_DQ4 POD12_DCI C2 DQ12 U74
BN44 PL_DDR4_DQ5 POD12_DCI C8 DQ13 U74
BN47 PL_DDR4_DQ6 POD12_DCI D3 DQ14 U74
BP43 PL_DDR4_DQ7 POD12_DCI D7 DQ15 U74
BN46 PL_DDR4_DQS0_T DIFF_POD12_DCI B7 UDQS_T U74
BP46 PL_DDR4_DQS0_C DIFF_POD12_DCI A7 UDQS_C U74
BN42 PL_DDR4_DM0_B POD12_DCI E2 NF/UDM_B/UDBI_B U74
BL45 PL_DDR4_DQ8 POD12_DCI G2 DQ0 U17
BK44 PL_DDR4_DQ9 POD12_DCI F7 DQ1 U17
BL46 PL_DDR4_DQ10 POD12_DCI H3 DQ2 U17
BK43 PL_DDR4_DQ11 POD12_DCI H7 DQ3 U17
BL43 PL_DDR4_DQ12 POD12_DCI H2 DQ4 U17
BJ44 PL_DDR4_DQ13 POD12_DCI H8 DQ5 U17
BL42 PL_DDR4_DQ14 POD12_DCI J3 DQ6 U17
BJ43 PL_DDR4_DQ15 POD12_DCI J7 DQ7 U17
BK45 PL_DDR4_DQS1_T DIFF_POD12_DCI G3 LDQS_T U17
BK46 PL_DDR4_DQS1_C DIFF_POD12_DCI F3 LDQS_C U17
BL47 PL_DDR4_DM1_B POD12_DCI E7 NF/LDM_B/LDBI_B U17
BK41 PL_DDR4_DQ16 POD12_DCI G2 DQ0 U74
BG44 PL_DDR4_DQ17 POD12_DCI F7 DQ1 U74
BG42 PL_DDR4_DQ18 POD12_DCI H3 DQ2 U74
BH44 PL_DDR4_DQ19 POD12_DCI H7 DQ3 U74
BH45 PL_DDR4_DQ20 POD12_DCI H2 DQ4 U74
BG45 PL_DDR4_DQ21 POD12_DCI H8 DQ5 U74
BG43 PL_DDR4_DQ22 POD12_DCI J3 DQ6 U74
BJ41 PL_DDR4_DQ23 POD12_DCI J7 DQ7 U74
BH46 PL_DDR4_DQS2_T DIFF_POD12_DCI G3 LDQS_T U74
BJ46 PL_DDR4_DQS2_C DIFF_POD12_DCI F3 LDQS_C U74
BH42 PL_DDR4_DM2_B POD12_DCI E7 NF/LDM_B/LDBI_B U74
BE43 PL_DDR4_DQ24 POD12_DCI G2 DQ0 U18
BF42 PL_DDR4_DQ25 POD12_DCI F7 DQ1 U18
BC42 PL_DDR4_DQ26 POD12_DCI H3 DQ2 U18
BF43 PL_DDR4_DQ27 POD12_DCI H7 DQ3 U18
BD42 PL_DDR4_DQ28 POD12_DCI H2 DQ4 U18
Schematic Net
Name
I/O Standard
Pin # Pin Name Ref. Des.
Component Memory
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Table 6: DDR4 Memory 72-bit I/F to FPGA U1 Banks 64, 65, and 66 (cont'd)
FPGA (U1) Pin
BF45 PL_DDR4_DQ29 POD12_DCI H8 DQ5 U18
BE44 PL_DDR4_DQ30 POD12_DCI J3 DQ6 U18
BF46 PL_DDR4_DQ31 POD12_DCI J7 DQ7 U18
BE45 PL_DDR4_DQS3_T DIFF_POD12_DCI G3 LDQS_T U18
BE46 PL_DDR4_DQS3_C DIFF_POD12_DCI F3 LDQS_C U18
BD41 PL_DDR4_DM3_B DIFF_POD12_DCI E7 NF/LDM_B/LDBI_B U18
BP32 PL_DDR4_DQ32 POD12_DCI G2 DQ0 U73
BP29 PL_DDR4_DQ33 POD12_DCI F7 DQ1 U73
BP31 PL_DDR4_DQ34 POD12_DCI H3 DQ2 U73
BP28 PL_DDR4_DQ35 POD12_DCI H7 DQ3 U73
BN32 PL_DDR4_DQ36 POD12_DCI H2 DQ4 U73
BM30 PL_DDR4_DQ37 POD12_DCI H8 DQ5 U73
BN31 PL_DDR4_DQ38 POD12_DCI J3 DQ6 U73
BL30 PL_DDR4_DQ39 POD12_DCI J7 DQ7 U73
BN29 PL_DDR4_DQS4_T DIFF_POD12_DCI G3 LDQS_T U73
BN30 PL_DDR4_DQS4_C DIFF_POD12_DCI F3 LDQS_C U73
BM28 PL_DDR4_DM4_B POD12_DCI E7 NF/LDM_B/LDBI_B U73
BL32 PL_DDR4_DQ40 POD12_DCI G2 DQ0 U19
BP34 PL_DDR4_DQ41 POD12_DCI F7 DQ1 U19
BN34 PL_DDR4_DQ42 POD12_DCI H3 DQ2 U19
BK33 PL_DDR4_DQ43 POD12_DCI H7 DQ3 U19
BL31 PL_DDR4_DQ44 POD12_DCI H2 DQ4 U19
BL33 PL_DDR4_DQ45 POD12_DCI H8 DQ5 U19
BM33 PL_DDR4_DQ46 POD12_DCI J3 DQ6 U19
BK31 PL_DDR4_DQ47 POD12_DCI J7 DQ7 U19
BL35 PL_DDR4_DQS5_T DIFF_POD12_DCI G3 LDQS_T U19
BM35 PL_DDR4_DQS5_C DIFF_POD12_DCI F3 LDQS_C U19
BM34 PL_DDR4_DM5_B POD12_DCI E7 NF/LDM_B/LDBI_B U19
BJ34 PL_DDR4_DQ48 POD12_DCI A3 DQ8 U18
BG35 PL_DDR4_DQ49 POD12_DCI B8 DQ9 U18
BH34 PL_DDR4_DQ50 POD12_DCI C3 DQ10 U18
BH35 PL_DDR4_DQ51 POD12_DCI C7 DQ11 U18
BJ33 PL_DDR4_DQ52 POD12_DCI C2 DQ12 U18
BF35 PL_DDR4_DQ53 POD12_DCI C8 DQ13 U18
BG34 PL_DDR4_DQ54 POD12_DCI D3 DQ14 U18
BF36 PL_DDR4_DQ55 POD12_DCI D7 DQ15 U18
BK34 PL_DDR4_DQS6_T DIFF_POD12_DCI B7 UDQS_T U18
BK35 PL_DDR4_DQS6_C DIFF_POD12_DCI A7 UDQS_C U18
Schematic Net
Name
I/O Standard
Pin # Pin Name Ref. Des.
Component Memory
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Chapter 3: Board Component Descriptions
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Table 6: DDR4 Memory 72-bit I/F to FPGA U1 Banks 64, 65, and 66 (cont'd)
FPGA (U1) Pin
BH32 PL_DDR4_DM6_B POD12_DCI E2 NF/UDM_B/UDBI_B U18
BF31 PL_DDR4_DQ56 POD12_DCI A3 DQ8 U73
BH30 PL_DDR4_DQ57 POD12_DCI B8 DQ9 U73
BJ31 PL_DDR4_DQ58 POD12_DCI C3 DQ10 U73
BG32 PL_DDR4_DQ59 POD12_DCI C7 DQ11 U73
BH31 PL_DDR4_DQ60 POD12_DCI C2 DQ12 U73
BF32 PL_DDR4_DQ61 POD12_DCI C8 DQ13 U73
BH29 PL_DDR4_DQ62 POD12_DCI D3 DQ14 U73
BF33 PL_DDR4_DQ63 POD12_DCI D7 DQ15 U73
BJ29 PL_DDR4_DQS7_T DIFF_POD12_DCI B7 UDQS_T U73
BK30 PL_DDR4_DQS7_C DIFF_POD12_DCI A7 UDQS_C U73
BG29 PL_DDR4_DM7_B POD12_DCI E2 NF/UDM_B/UDBI_B U73
BN51 PL_DDR4_DQ64 POD12_DCI A3 DQ8 U17
BM52 PL_DDR4_DQ65 POD12_DCI B8 DQ9 U17
BN50 PL_DDR4_DQ66 POD12_DCI C3 DQ10 U17
BL52 PL_DDR4_DQ67 POD12_DCI C7 DQ11 U17
BM48 PL_DDR4_DQ68 POD12_DCI C2 DQ12 U17
BL53 PL_DDR4_DQ69 POD12_DCI C8 DQ13 U17
BN49 PL_DDR4_DQ70 POD12_DCI D3 DQ14 U17
BL51 PL_DDR4_DQ71 POD12_DCI D7 DQ15 U17
BM49 PL_DDR4_DQS8_T DIFF_POD12_DCI B7 UDQS_T U17
BM50 PL_DDR4_DQS8_C DIFF_POD12_DCI A7 UDQS_C U17
BP48 PL_DDR4_DM8_B POD12_DCI E2 NF/UDM_B/UDBI_B U17
BF50 PL_DDR4_A0 SSTL12_DCI P3 A0 U17-U19 U73-U74
BD51 PL_DDR4_A1 SSTL12_DCI P7 A1 U17-U19 U73-U74
BG48 PL_DDR4_A2 SSTL12_DCI R3 A2 U17-U19 U73-U74
BE50 PL_DDR4_A3 SSTL12_DCI N7 A3 U17-U19 U73-U74
BE49 PL_DDR4_A4 SSTL12_DCI N3 A4 U17-U19 U73-U74
BE51 PL_DDR4_A5 SSTL12_DCI P8 A5 U17-U19 U73-U74
BF53 PL_DDR4_A6 SSTL12_DCI P2 A6 U17-U19 U73-U74
BG50 PL_DDR4_A7 SSTL12_DCI R8 A7 U17-U19 U73-U74
BF51 PL_DDR4_A8 SSTL12_DCI R2 A8 U17-U19 U73-U74
BG47 PL_DDR4_A9 SSTL12_DCI R7 A9 U17-U19 U73-U74
BF47 PL_DDR4_A10 SSTL12_DCI M3 A10/AP U17-U19 U73-U74
BG49 PL_DDR4_A11 SSTL12_DCI T2 A11 U17-U19 U73-U74
BF48 PL_DDR4_A12 SSTL12_DCI M7 A12/BC_B U17-U19 U73-U74
BF52 PL_DDR4_A13 SSTL12_DCI T8 A13 U17-U19 U73-U74
Schematic Net
Name
I/O Standard
Pin # Pin Name Ref. Des.
COMMON
Component Memory
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VCU128 Board User Guide 23
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Table 6: DDR4 Memory 72-bit I/F to FPGA U1 Banks 64, 65, and 66 (cont'd)
FPGA (U1) Pin
BE54 PL_DDR4_BA0 SSTL12_DCI N2 BA0 U17-U19 U73-U74
BE53 PL_DDR4_BA1 SSTL12_DCI N8 BA1 U17-U19 U73-U74
BG54 PL_DDR4_BG0 SSTL12_DCI M2 BG0 U17-U19 U73-U74
BG53 PL_DDR4_WE_B SSTL12_DCI L2 WE_B/A14 U17-U19 U73-U74
BJ54 PL_DDR4_RAS_B SSTL12_DCI L8 RAS_B/A16 U17-U19 U73-U74
BH54 PL_DDR4_CAS_B SSTL12_DCI M8 CAS_B_A15 U17-U19 U73-U74
BK53 PL_DDR4_CK_T DIFF_SSTL12_DCI K7 CK_T U17-U19 U73-U74
BK54 PL_DDR4_CK_C DIFF_SSTL12_DCI K8 CK_C U17-U19 U73-U74
BH52 PL_DDR4_CKE SSTL12_DCI K2 CKE U17-U19 U73-U74
BG52 PL_DDR4_ACT_B SSTL12_DCI L3 ACT_B U17-U19 U73-U74
BJ53 PL_DDR4_TEN SSTL12_DCI N9 TEN U17-U19 U73-U74
BJ52 PL_DDR4_ALERT_B SSTL12_DCI P9 ALERT_B U17-U19 U73-U74
BL48 PL_DDR4_PARITY SSTL12_DCI T3 PAR U17-U19 U73-U74
BH50 PL_DDR4_RESET_B LVCMOS12 P1 RESET_B U17-U19 U73-U74
BH49 PL_DDR4_ODT SSTL12_DCI K3 ODT U17-U19 U73-U74
BP49 PL_DDR4_CS_B SSTL12_DCI L7 CS_B U17-U19 U73-U74
Schematic Net
Name
I/O Standard
Pin # Pin Name Ref. Des.
Component Memory
The VCU128 DDR4 memory component interfaces adhere to the constraints guidelines
documented in the “DDR3/DDR4 Design Guidelines” secon of the UltraScale Architecture-Based
FPGAs Memory IP LogiCORE IP Product Guide (PG150). The VCU128 board DDR4 memory
component interface is a 40Ω impedance implementaon.
For more informaon on the internal VREF, see the “Supply Voltages for the SelectIO Pins VREF”
and the “Internal VREF” secons in the UltraScale Architecture SelectIO Resources User Guide
(UG571). For more details about the Micron DDR4 component memory, see the Micron
MT40A512M16LY data sheet at the Micron Technology website.
RLD3 Component Memory
[Figure 2, callout 5]
The 288 MB RLD3 72-bit wide component memory system is comprised of two 36-bit 1.125 Gb
RLDRAM3 devices located at U39 and U37.
• Manufacturer: Micron
• Part Number: MT44K32M36RB-107E
• Descripon:
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VCU128 Board User Guide 24
○ 1.125 Gb (32 Mb x 36)
Chapter 3: Board Component Descriptions
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○ 1.2V 168-ball BGA
○ Up to RL3-1866
The VCU128 XCVU37P FPGA RLDRAM3 interface performance is documented in the Virtex
UltraScale+ FPGA Data Sheet: DC and AC Switching Characteriscs (DS923).
This memory system is connected to the XCVU37P HP banks 73, 74, and 75. The RLD3 0.6V
VTT terminaon voltage (net RLD3_VTERM_0V6) is sourced from TI TPS51200DR linear
regulator U92. The RLD3 memory interface bank VREF pins are not connected, which, coupled
with an XDC set_property INTERNAL_VREF constraint, invoke the INTERNAL VREF mode. The
connecons between the RLD3 component memories and XCVU37P banks 73, 74, and 75 are
listed in the following table.
Table 7: RLD3 Memory 72-bit I/F to FPGA U1 Banks 73, 74, and 75
FPGA (U1)
Pin
K29 RLD3_72B_DQ0 SSTL12 D11 DQ0 U39
J30 RLD3_72B_DQ1 SSTL12 E10 DQ1 U39
K32 RLD3_72B_DQ2 SSTL12 C8 DQ2 U39
J31 RLD3_72B_DQ3 SSTL12 C10 DQ3 U39
L29 RLD3_72B_DQ4 SSTL12 C12 DQ4 U39
L31 RLD3_72B_DQ5 SSTL12 B9 DQ5 U39
L30 RLD3_72B_DQ6 SSTL12 B11 DQ6 U39
J32 RLD3_72B_DQ7 SSTL12 A8 DQ7 U39
K31 RLD3_72B_DQ8 SSTL12 A10 DQ8 U39
G30 RLD3_72B_DQ9 SSTL12 J10 DQ9 U39
H30 RLD3_72B_DQ10 SSTL12 K11 DQ10 U39
F31 RLD3_72B_DQ11 SSTL12 K13 DQ11 U39
G28 RLD3_72B_DQ12 SSTL12 L8 DQ12 U39
H29 RLD3_72B_DQ13 SSTL12 L10 DQ13 U39
G31 RLD3_72B_DQ14 SSTL12 L12 DQ14 U39
G32 RLD3_72B_DQ15 SSTL12 M9 DQ15 U39
H32 RLD3_72B_DQ16 SSTL12 M11 DQ16 U39
F28 RLD3_72B_DQ17 SSTL12 N8 DQ17 U39
E33 RLD3_72B_DQ18 SSTL12 D3 DQ18 U39
F29 RLD3_72B_DQ19 SSTL12 E4 DQ19 U39
E29 RLD3_72B_DQ20 SSTL12 C6 DQ20 U39
C32 RLD3_72B_DQ21 SSTL12 C4 DQ21 U39
F33 RLD3_72B_DQ22 SSTL12 C2 DQ22 U39
D30 RLD3_72B_DQ23 SSTL12 B5 DQ23 U39
D32 RLD3_72B_DQ24 SSTL12 B3 DQ24 U39
D29 RLD3_72B_DQ25 SSTL12 A6 DQ25 U39
Schematic Net
Name
I/O Standard
Pin # Pin Name Ref. Des.
Component Memory
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Table 7: RLD3 Memory 72-bit I/F to FPGA U1 Banks 73, 74, and 75 (cont'd)
FPGA (U1)
Pin
D31 RLD3_72B_DQ26 SSTL12 A4 DQ26 U39
A31 RLD3_72B_DQ27 SSTL12 J4 DQ27 U39
B32 RLD3_72B_DQ28 SSTL12 K3 DQ28 U39
A33 RLD3_72B_DQ29 SSTL12 K1 DQ29 U39
B30 RLD3_72B_DQ30 SSTL12 L6 DQ30 U39
A30 RLD3_72B_DQ31 SSTL12 L4 DQ31 U39
C28 RLD3_72B_DQ32 SSTL12 L2 DQ32 U39
C29 RLD3_72B_DQ33 SSTL12 M5 DQ33 U39
A29 RLD3_72B_DQ34 SSTL12 M3 DQ34 U39
B28 RLD3_72B_DQ35 SSTL12 N6 DQ35 U39
G42 RLD3_72B_DQ36 SSTL12 D11 DQ0 U37
G41 RLD3_72B_DQ37 SSTL12 E10 DQ1 U37
H42 RLD3_72B_DQ38 SSTL12 C8 DQ2 U37
G40 RLD3_72B_DQ39 SSTL12 C10 DQ3 U37
H43 RLD3_72B_DQ40 SSTL12 C12 DQ4 U37
J42 RLD3_72B_DQ41 SSTL12 B9 DQ5 U37
H40 RLD3_72B_DQ42 SSTL12 B11 DQ6 U37
J40 RLD3_72B_DQ43 SSTL12 A8 DQ7 U37
J41 RLD3_72B_DQ44 SSTL12 A10 DQ8 U37
D44 RLD3_72B_DQ45 SSTL12 J10 DQ9 U37
F45 RLD3_72B_DQ46 SSTL12 K11 DQ10 U37
F44 RLD3_72B_DQ47 SSTL12 K13 DQ11 U37
D46 RLD3_72B_DQ48 SSTL12 L8 DQ12 U37
F46 RLD3_72B_DQ49 SSTL12 L10 DQ13 U37
E44 RLD3_72B_DQ50 SSTL12 L12 DQ14 U37
E46 RLD3_72B_DQ51 SSTL12 M9 DQ15 U37
G45 RLD3_72B_DQ52 SSTL12 M11 DQ16 U37
H45 RLD3_72B_DQ53 SSTL12 N8 DQ17 U37
B46 RLD3_72B_DQ54 SSTL12 D3 DQ18 U37
A46 RLD3_72B_DQ55 SSTL12 E4 DQ19 U37
C43 RLD3_72B_DQ56 SSTL12 C6 DQ20 U37
B45 RLD3_72B_DQ57 SSTL12 C4 DQ21 U37
A45 RLD3_72B_DQ58 SSTL12 C2 DQ22 U37
C45 RLD3_72B_DQ59 SSTL12 B5 DQ23 U37
C44 RLD3_72B_DQ60 SSTL12 B3 DQ24 U37
D42 RLD3_72B_DQ61 SSTL12 A6 DQ25 U37
A43 RLD3_72B_DQ62 SSTL12 A4 DQ26 U37
D40 RLD3_72B_DQ63 SSTL12 J4 DQ27 U37
Schematic Net
Name
I/O Standard
Pin # Pin Name Ref. Des.
Component Memory
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Table 7: RLD3 Memory 72-bit I/F to FPGA U1 Banks 73, 74, and 75 (cont'd)
FPGA (U1)
Pin
C40 RLD3_72B_DQ64 SSTL12 K3 DQ28 U37
A39 RLD3_72B_DQ65 SSTL12 K1 DQ29 U37
A41 RLD3_72B_DQ66 SSTL12 L6 DQ30 U37
B41 RLD3_72B_DQ67 SSTL12 L4 DQ31 U37
B40 RLD3_72B_DQ68 SSTL12 L2 DQ32 U37
D41 RLD3_72B_DQ69 SSTL12 M5 DQ33 U37
B42 RLD3_72B_DQ70 SSTL12 M3 DQ34 U37
E41 RLD3_72B_DQ71 SSTL12 N6 DQ35 U37
J29 RLD3_72B_DM0 SSTL12 B7 DM0 U39
A28 RLD3_72B_DM1 SSTL12 M7 DM1 U39
G43 RLD3_72B_DM2 SSTL12 B7 DM0 U37
A40 RLD3_72B_DM3 SSTL12 M7 DM1 U37
D39 RLD3_72B_A0 SSTL12 E2 A0 U37, U39
A38 RLD3_72B_A1 SSTL12 F5 A1 U37, U39
B38 RLD3_72B_A2 SSTL12 F4 A2 U37, U39
J34 RLD3_72B_A3 SSTL12 F9 A3 U37, U39
K34 RLD3_72B_A4 SSTL12 F10 A4 U37, U39
K37 RLD3_72B_A5 SSTL12 F12 A5 U37, U39
C38 RLD3_72B_A6 SSTL12 G3 A6 U37, U39
E36 RLD3_72B_A7 SSTL12 F1 A7 U37, U39
B35 RLD3_72B_A8 SSTL12 G11 A8 U37, U39
L35 RLD3_72B_A9 SSTL12 F13 A9 U37, U39
D34 RLD3_72B_A10 SSTL12 H13 A10 U37, U39
E39 RLD3_72B_A11 SSTL12 D1 A11 U37, U39
A35 RLD3_72B_A12 SSTL12 H11 A12 U37, U39
C35 RLD3_72B_A13 SSTL12 D13 A13 U37, U39
E37 RLD3_72B_A14 SSTL12 H3 A14 U37, U39
E38 RLD3_72B_A15 SSTL12 G2 A15 U37, U39
C37 RLD3_72B_A16 SSTL12 H4 A16 U37, U39
B36 RLD3_72B_A17 SSTL12 H10 A17 U37, U39
F34 RLD3_72B_A18 SSTL12 G12 A18 U37, U39
J37 RLD3_72B_A19 SSTL12 H1 A19 U37, U39
C39 RLD3_72B_A20 SSTL12 F2 NF_A20 U37, U39
C34 RLD3_72B_BA0 SSTL12 G9 BA0 U37, U39
B37 RLD3_72B_BA1 SSTL12 G5 BA1 U37, U39
A36 RLD3_72B_BA2 SSTL12 H8 BA2 U37, U39
D36 RLD3_72B_BA3 SSTL12 H6 BA3 U37, U39
D37 RLD3_72B_WE_B SSTL12 F6 WE_B U37, U39
Schematic Net
Name
I/O Standard
Pin # Pin Name Ref. Des.
Component Memory
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VCU128 Board User Guide 27
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Table 7: RLD3 Memory 72-bit I/F to FPGA U1 Banks 73, 74, and 75 (cont'd)
FPGA (U1)
Pin
E34 RLD3_72B_REF_B SSTL12 F8 REF_B U37, U39
G37 RLD3_72B_CK_P SSTL12 H7 CK U37, U39
F38 RLD3_72B_CK_N SSTL12 G7 CK_B U37, U39
D35 RLD3_72B_RESET_B SSTL12 A13 RESET_B U37, U39
A34 RLD3_72B_CS_B SSTL12 E12 CS_B U37, U39
H37 RLD3_72B_DK0_P DIFF_SSTL12 D7 DK0 U39
H38 RLD3_72B_DK0_N DIFF_SSTL12 C7 DK0_B U39
H34 RLD3_72B_DK1_P DIFF_SSTL12 K7 DK1 U39
H35 RLD3_72B_DK1_N DIFF_SSTL12 L7 DK1_B U39
G38 RLD3_72B_DK2_P DIFF_SSTL12 D7 DK0 U37
F39 RLD3_72B_DK2_N DIFF_SSTL12 C7 DK0_B U37
G35 RLD3_72B_DK3_P DIFF_SSTL12 K7 DK1 U37
G36 RLD3_72B_DK3_N DIFF_SSTL12 L7 DK1_B U37
L33 RLD3_72B_QK0_P DIFF_SSTL12 D9 QK0 U39
K33 RLD3_72B_QK0_N DIFF_SSTL12 E8 QK0_B U39
H33 RLD3_72B_QK1_P DIFF_SSTL12 K9 QK1 U39
G33 RLD3_72B_QK1_N DIFF_SSTL12 J8 QK1_B U39
E31 RLD3_72B_QK2_P DIFF_SSTL12 D5 QK2 U39
E32 RLD3_72B_QK2_N DIFF_SSTL12 E6 QK2_B U39
C30 RLD3_72B_QK3_P DIFF_SSTL12 K5 QK3 U39
B31 RLD3_72B_QK3_N DIFF_SSTL12 J6 QK3_B U39
K41 RLD3_72B_QK4_P DIFF_SSTL12 D9 QK0 U37
K42 RLD3_72B_QK4_N DIFF_SSTL12 E8 QK0_B U37
J44 RLD3_72B_QK5_P DIFF_SSTL12 K9 QK1 U37
H44 RLD3_72B_QK5_N DIFF_SSTL12 J8 QK1_B U37
E42 RLD3_72B_QK6_P DIFF_SSTL12 D5 QK2 U37
E43 RLD3_72B_QK6_N DIFF_SSTL12 E6 QK2_B U37
F40 RLD3_72B_QK7_P DIFF_SSTL12 K5 QK3 U37
F41 RLD3_72B_QK7_N DIFF_SSTL12 J6 QK3_B U37
F30 RLD3_72B_QVLD0 SSTL12 J12 QVLD0 U39
E28 RLD3_72B_QVLD1 SSTL12 J2 QVLD1 U39
D45 RLD3_72B_QVLD2 SSTL12 J12 QVLD0 U37
A44 RLD3_72B_QVLD3 SSTL12 J2 QVLD1 U37
Schematic Net
Name
I/O Standard
Pin # Pin Name Ref. Des.
Component Memory
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VCU128 Board User Guide 28
The VCU128 RLD3 72-bit memory component interface adheres to the constraints guidelines
documented in the "RLD3 Design Guidelines" secon of the UltraScale Architecture-Based FPGAs
Memory IP LogiCORE IP Product Guide (PG150). The VCU128 RLD3 memory component interface
is a 40Ω impedance implementaon.
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For more informaon on the internal VREF, see the "Supply Voltages for the SelectIO Pins",
“VREF”, and “Internal VREF” secons in the UltraScale Architecture SelectIO Resources User Guide
(UG571). For more details about the Micron RLD3 component memory, see the Micron
MT44K32M36RB Data Sheet at the Micron Technology website.
QDR4 Component Memory
[Figure 2, callout 6]
The 4.5 GB QDR4 component memory system is comprised of one 144-Mbit density (4M × 36)
QDR4 SRAM device located at U40.
•
Manufacturer: Cypress
•
Part Number: CY7C4142KV13_106FCXC
•
Descripon:
○ 144-Mbit density (4M × 36)
○ Dual independent 36-bit bidireconal double data rate (DDR) data ports
○ Supports concurrent read/write transacons on both ports
○ Single address port used to control both data ports
○ 1.2V 361-ball FCBGA
○ Maximum operang frequency of 1066 MHz
The VCU128 XCVU37P FPGA QDR IV interface performance is documented in the Virtex
UltraScale+ FPGA Data Sheet: DC and AC Switching Characteriscs (DS923).
The 72-bit wide QDR4 memory is connected to XCVU37P U1 HP banks 68, 69, and 70. The
QDR4 memory interface bank VREF pins are not connected, which, coupled with an XDC
set_property INTERNAL VREF constraint, invoke the INTERNAL VREF mode. The connecons
between the 72-bit interface QDR4 component memories and XCVU37P banks 68, 69, and 70
are listed in the following table.
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VCU128 Board User Guide 29
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Table 8: QDR4 Memory 72-bit I/F to FPGA U1 Banks 68, 69, and 70
FPGA (U1) Pin
BM14 QDR4_DQA0 C8 DQA0
BM13 QDR4_DQA1 B7 DQA1
BN15 QDR4_DQA2 C6 DQA2
BN12 QDR4_DQA3 D5 DQA3
BM15 QDR4_DQA4 D7 DQA4
BP13 QDR4_DQA5 A4 DQA5
BP14 QDR4_DQA6 F5 DQA6
BM12 QDR4_DQA7 A6 DQA7
BL15 QDR4_DQA8 A8 DQA8
BM9 QDR4_DQA9 H3 DQA9
BK9 QDR4_DQA10 H5 DQA10
BL10 QDR4_DQA11 J2 DQA11
BK10 QDR4_DQA12 J4 DQA12
BL8 QDR4_DQA13 B2 DQA13
BN10 QDR4_DQA14 E2 DQA14
BM10 QDR4_DQA15 G2 DQA15
BN9 QDR4_DQA16 G4 DQA16
BJ9 QDR4_DQA17 B5 DQA17
BL12 QDR4_DQA18 C12 DQA18
BK14 QDR4_DQA19 B13 DQA19
BJ12 QDR4_DQA20 C14 DQA20
BK15 QDR4_DQA21 D15 DQA21
BL13 QDR4_DQA22 D13 DQA22
BH14 QDR4_DQA23 A16 DQA23
BH15 QDR4_DQA24 F15 DQA24
BJ14 QDR4_DQA25 A14 DQA25
BJ13 QDR4_DQA26 A12 DQA26
BE9 QDR4_DQA27 H17 DQA27
BE10 QDR4_DQA28 H15 DQA28
BG13 QDR4_DQA29 J18 DQA29
BE11 QDR4_DQA30 J16 DQA30
BF10 QDR4_DQA31 B18 DQA31
BG12 QDR4_DQA32 E18 DQA32
BG9 QDR4_DQA33 G18 DQA33
BG10 QDR4_DQA34 G16 DQA34
BF12 QDR4_DQA35 B15 DQA35
Schematic Net
Name
I/O Standard
QDR4 A-side Data
Component Memory
Pin # Pin Name
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VCU128 Board User Guide 30
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