Please Read: Important Legal Notices................................................................................. 100
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VCU128 Board User Guide 3
Revision History
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The following table shows the revision history for this document.
Revision History
Section
12/21/2018 Version 1.0
Initial Xilinx release.N/A
Revision Summary
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VCU128 Board User Guide 4
Introduction
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Overview
The VCU128 board incorporates the VU37P high bandwidth memory (HBM) FPGA, which
ulizes stacked silicon interconnect (SSI) technology to add HBM die next to the FPGA die on the
package substrate. The VCU128 evaluaon board for the Xilinx® Virtex® UltraScale+™ FPGA
provides a hardware environment for developing and evaluang designs targeng the UltraScale
+ XCVU37P-2FSVH2892E device. The VCU128 evaluaon board is equipped with many of the
common board-level features needed for design development as listed here.
• DDR4, RLD-3, and QDR-IV component memory
• Ganged small form-factor pluggable (QSFP28) connectors
Chapter 1
• Sixteen-lane PCI Express® interface
• Ethernet PHY
• General purpose I/O
• UART interface
Addional features can be supported using modules compable with the VITA-57.4 (FMCP
HSPC) connector on the VCU128 board.
Additional Resources
See Appendix D: Addional Resources and Legal Noces for references to documents, les, and
resources relevant to the VCU128 evaluaon board.
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VCU128 Board User Guide 5
Chapter 1: Introduction
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Block Diagram
A block diagram of the VCU128 evaluaon board is shown in the following gure.
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VCU128 Board User Guide 7
○Gen3 (x1, x2, x4, x8, x16)
○Dual Gen4 (x1, x2, x4, x8)
• Ethernet PHY SGMII interface with RJ-45 connector
• Dual USB-to-UART bridge with micro-B USB connector (shared FTDI FT4232HL)
Chapter 1: Introduction
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• I2C bus
• Status LEDs
• User I/O (1 x push-buon switch, 8 x LED)
• VITA 57.4 FMC+ HSPC connector (DP[0:23], LA[0:33])
• Power management with I2C voltage monitoring through Intersil power controllers and GUI
• Conguraonopons:
○Quad SPI ash memory
○USB JTAG I/F (FTDI FT4232HL)
○Plaorm cable USB II interface 2x7 2 mm keyed connector
Board Specifications
Dimensions
Height: 7.53 inch (19.14 cm)
Length: 9.50 inch (24.13 cm)
Thickness (±5%): 0.061 inch (0.1549 cm)
Note: A 3D model of this board is not available.
IMPORTANT
PCI Express® card.
! The VCU128 board height exceeds the standard 4.376-inch (11.15 cm) height of a
Environmental
Temperature
Operang: 0°C to +45°C, Storage: -25°C to +60°C
Humidity
10% to 90% non-condensing
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VCU128 Board User Guide 8
Operating Voltage
+12 VDC
Chapter 2
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Board Setup and Configuration
Electrostatic Discharge Caution
CAUTION! ESD can damage electronic components when they are improperly handled, and can result
in total or intermient failures. Always follow ESD-prevenon procedures when removing and replacing
components.
To prevent ESD damage:
• Use an ESD wrist or ankle strap and ensure that it makes skin contact. Connect the equipment
end of the strap to an unpainted metal surface on the chassis.
• Avoid touching the adapter against your clothing. The wrist strap protects components from
ESD on the body only.
• Handle the adapter by its bracket or edges only. Avoid touching the printed circuit board or
the connectors.
• Put the adapter down only on an anstac surface such as the bag supplied in your kit.
• If you are returning the adapter to Xilinx® Product Support, place it back in its anstac bag
immediately.
Board Component Location
The following gure shows the VCU128 board component locaons. Each numbered component
shown in the gure is keyed to the table in Board Component Descripons.
IMPORTANT! The board component locaons gure is for visual reference only and might not reect
the current revision of the board.
IMPORTANT! There could be mulple revisions of this board. The specic details concerning the
dierences between revisions are not captured in this document. This document is not intended to be areference design guide and the informaon herein should not be used as such. Always refer to the
schemac, layout, and XDC les of the specic VCU128 version of interest for such details.
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VCU128 Board User Guide 9
Chapter 2: Board Setup and Configuration
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Figure 2: Evaluation Board Component Locations
15
16
24
Round callout references a component
00
on the front side of the board
24
18
19
5
31
Square callout references a component
00
on the back side of the board
27
35
4
4
34
25
26
2
1
3
36
10
34
22
38
23
22
28
30
29
32
39
33
17
14
13
37
11
20
20
21
6
7
12
9
40
8
X22144-121718
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VCU128 Board User Guide 10
Chapter 2: Board Setup and Configuration
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Board Component Descriptions
The following table idenes the components, references the respecve schemac page
numbers, and links to a detailed funconaldescripon of the components and board features in
SW4CPU_RESET P.B.NAU1 XCVU37P USER P.B. (active high)2947
Notes:
1.DIP switch sections are active-High (connected net is pulled High when DIP switch is closed = 1).
1
SW1[1:4] =
0001
Position 1 = System Controller Enable
SW1[2:4] = FPGA U1 mode M[2:0] = 001
Figure 2
Callout
363
29
Schematic
Page
50
Jumpers
Default jumper sengs are listed in the following table. Jumper header locaons are shown in
Figure 2. The following table also references the respecve schemac page numbers.
Table 3: Default Jumper Settings
JumperFunctionDefaultComments
J14Power on reset (POR)
override
J25VCCINT select1-21-2: 0.85V; 2-3: 0.72V
J46PCIe lane size select7-816-lane configuration3741
J43SYSCTLR RE-PROGOffU42 XCZU7010 MIO5 pin
Notes:
1.VCCINT select header J25 should always have a jumper block installed.
2-3U1 POR_OVERRIDE pin
BG15 to GND
1
A9
Figure 2
Callout
383
3954
4050
Schematic
Page
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VCU128 Board User Guide 13
Chapter 2: Board Setup and Configuration
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Installing the Board in a PC Chassis
The VCU128 board 12V power input circuitry allows 12V to be applied through one of two
connectors, J16 (typically used with the stand-alone VCU128 power adapter) or JP1, as shown in
the following gure.
Figure 3: 12V Power Entry
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VCU128 Board User Guide 14
Installaon of the VCU128 board inside a computer chassis is required when developing or
tesng PCI Express® funconality. When the VCU128 board is used inside a computer chassis
(i.e., plugged in to a PCIe® slot), power is provided by choosing one of two mutually exclusive
ATX power supply cables as described in this secon (use one cable or the other).
• The ATX power supply 4-pin (1x4) peripheral connector, which requires using the ATX
adapter cable (see the following gure) to connect to J16 on the VCU128 board. The Xilinx
part number for this cable is 2600304. See ATX Power Supply Adapter Cable.
X22058-121318
®
Chapter 2: Board Setup and Configuration
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Figure 4: ATX Power Supply Adapter Cable
To ATX 4-Pin Peripheral
Power Connector
To J16 on VCU128 Board
X21955-121918
• The ATX supply 8-pin (2x4) PCIe power connector, which plugs into JP1 on the VCU128
board.
Steps to Install Board
To install the board in a PC chassis:
1. On the VCU128 board, remove the ve screws retaining the ve rubber feet and standos,
and the PCIe bracket. Reinstall the PCIe® bracket using two of the previously removed
screws.
2. Power down the host computer and remove the power cord from the PC.
3. Open the PC chassis following the instrucons provided with the PC.
4. The VCU128 board has a large cooling fan that requires two adjacent PCIe slots. Ensure the
slot adjacent to the front of the board is free of obstrucons.
5. Remove the PCIe expansion slot cover (at the back of the chassis) which aligns with the
VCU128 PCIe bracket, by removing the screws on the top and boom of the cover.
6. Plug the VCU128 board into the appropriate open slot.
7. Install the top mounng bracket screw into the PC expansion cover retainer bracket to secure
the VCU128 board in its slot.
8. If using the ATX supply 4-pin (1x4) peripheral connector, connect power to the VCU128
board using the ATX power supply adapter cable as shown in Figure 4.
a.Plug the 6-pin 2 x 3 Molex connector end of the adapter cable into J16 on the VCU128
board.
b. Plug the 4-pin 1 x 4 peripheral power connector from the ATX power supply into the 4-
pin adapter connector end of the cable.
CAUTION
! Do NOT plug a PC ATX power supply 6-pin connector into J16 on the VCU128 evaluaon
board. The ATX 6-pin connector has a dierent pinout than J16. Connecng an ATX 6-pin connector
into J16 damages the VCU128 evaluaon board and voids the board warranty.
c.Slide the VCU128 board power switch SW5 to the ON posion. The PC can now be
powered on.
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VCU128 Board User Guide 15
Chapter 2: Board Setup and Configuration
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9. If using the ATX supply 8-pin (2x4) PCIe power connector, plug the connector into VCU128
board JP1. The PC can now be powered on.
FPGA Configuration
The VCU128 board supports two of the ve UltraScale+™ FPGA conguraon modes:
• Quad SPI ash memory (2 Gb)
•
JTAG using:
○USB JTAG conguraon port (U8 FT4232HL + USB J2 micro-AB)
○Xilinx
®
Plaorm Cable USB II, 2 mm, keyed at cable header (J4)
Each conguraon interface corresponds to one or more conguraon modes and bus widths, as
listed in the following table. The mode switches M2, M1, and M0 are on SW1 posions 2, 3, and
4, respecvely. The FPGA default mode seng M[2:0] = 001 selects the master SPIconguraon mode.
Table 4: Configuration Modes
Configuration Mode
Master SPI
JTAG
SW1 DIP Switch
Settings M[2:0]
1
101
Bus WidthCCLK Direction
x1, x2, x4Output
x1NA
For complete details on conguring the FPGA, see UltraScale Architecture Conguraon User Guide
(UG570). The following gure shows the conguraon mode DIP switch SW1 JTAG switch
posions.
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VCU128 Board User Guide 16
Chapter 2: Board Setup and Configuration
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Figure 5: SW1 JTAG Mode Settings
ON Position = 1
OFF Position = 0
SCEM2M1
1234
M0
SW1
X21648-121918
JTAG
The Vivado®, Xilinx® SDK, or third-party tools can establish a JTAG connecon to the XCVU37P
FPGA through the FTDI FT4232 USB-to-JTAG/USB UART device (U8) connected to the microUSB connector (J2). Alternavely, a JTAG cable can be connected to the keyed at cable header
(J4). JTAG iniatedconguraon takes priority over the conguraon method selected through
the FPGA mode pins M[2:0], wired to SW1 posions [2:4].
Quad SPI
To boot from the dual Quad SPI non-volaleconguraon memory, follow these steps.
1. Store a valid XCVU37P FPGA boot image in the 2 Gbit Quad SPI ash device (U46)
connected to the FPGA bank 0 Quad SPI interface. See the VCU128 Restoring Flash Tutorial
(XTP533) for informaon on programming the QSPI.
2. Set the boot mode pins SW1 M[2:0] as indicated in the conguraon modes table in FPGA
Conguraon for master SPI.
3. Power-cycle the VCU128 board. Mode SW1 is callout 36 in Figure 2.
See the VCU128 Soware Install and Board Setup Tutorial (XTP535) for more informaon.
See System Controller for an overview of query and control of select programmable board
features such as clocks, FMCP funconality, and power systems. See the VCU128 SystemController Tutorial (XTP534) for more informaon.
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VCU128 Board User Guide 17
Chapter 3: Board Component Descriptions
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Chapter 3
Board Component Descriptions
Overview
This chapter provides a detailed funconaldescripon of the board’s components and features.
Table 1idenes the components, references the respecve schemac page numbers, and links
to the corresponding detailed funconaldescripon in this chapter. Component locaons are
shown in Figure 2.
Component Descriptions
Virtex UltraScale+ XCVU37P-2FSVH2892E Device
[Figure 2, callout 1]
The VCU128 board incorporates the VU37P high bandwidth memory (HBM) FPGA, which
ulizes stacked silicon interconnect (SSI) technology to add HBM die next to the FPGA die on the
package substrate. The VCU128 board is populated with the Virtex® UltraScale+™
XCVU37P-2FSVH2892E device. For more informaon on Virtex UltraScale+ FPGAs, see VirtexUltraScale+ FPGA Data Sheet: DC and AC Switching Characteriscs (DS923).
Encryption Key Battery Backup Circuit
The XCVU37P device U1 implements bitstream encrypon key technology. The VCU128 board
provides the encrypon key backup baery circuit shown in the following gure.
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VCU128 Board User Guide 18
Chapter 3: Board Component Descriptions
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Figure 6: Encryption Key Backup Circuit
X21956-112918
The Seiko TS621E rechargeable 1.5V lithium buon-typebaery B1 is soldered to the board
with the posive output connected to the XCVU37P device U1 VBATT pin BD13. The baery
supply current IBATT specicaon is 150 nA maximum when the board power is o. B1 is
charged from the VCC1V8_BUS 1.8V rail through a series diode with a typical forward voltage
drop of 0.38V and 4.7 KΩ current limit resistor. The nominal charging voltage is 1.42V.
I/O Voltage Rails
There are 12 I/O banks and 2 high-bandwidth memory (HBM) banks available on the XCVU37P
device. The VCU128 board does not use the HBM banks. The voltages applied to the FPGA I/O
banks on the VCU128 board are listed in the following table.
Table 5: I/O Bank Voltage Rails
FPGA (U1) BankPower Supply Rail Net NameVoltage
Bank 0VCC1V81.8V
HP bank 64DDR4_VDDQ_1V21.2V
HP bank 65DDR4_VDDQ_1V21.2V
HP bank 66DDR4_VDDQ_1V21.2V
HP bank 67VCC1V81.8V
HP bank 68QDR4_VDDQ_1V21.2V
HP bank 69QDR4_VDDQ_1V21.2V
HP bank 70QDR4_VDDQ_1V21.2V
HP bank 71VADJ1.8V
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VCU128 Board User Guide 19
Chapter 3: Board Component Descriptions
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Table 5: I/O Bank Voltage Rails (cont'd)
FPGA (U1) BankPower Supply Rail Net NameVoltage
HP bank 72VADJ1.8V
HP bank 73RLD3_VDDQ_1V21.2V
HP bank 74RLD3_VDDQ_1V21.2V
HP bank 75RLD3_VDDQ_1V21.2V
HBM_43 (not used)VCCHBM/VCCAUX_HBM1.2V/1.8V
HBM_83 (not used)VCCHBM/VCCAUX_HBM1.2V/1.8V
DDR4 Component Memory
[Figure 2, callout 4]
The 4.5 GB DDR4 component memory system is comprised of ve 512 Mb x 16 DDR4 SDRAM
devices implemented in clam-shell fashion located at U17-U19 (top) and U73-U74 (boom). Half
of the U19 16-bits are used (4.5 x 16-bits = 72-bit wide interface).
• Manufacturer: Micron
• Part Number: MT40A512M16LY-075E
• Descripon:
○8 Gb (512 Mb x 16)
○1.2V 96-ball TFBGA
○DDR4-2666
The VCU128 XCVU37P FPGA DDR4 interface performance is documented in the VirtexUltraScale+ FPGA Data Sheet: DC and AC Switching Characteriscs (DS923).
The 72-bit wide DDR4 memory system is connected to XCVU37P U1 HP banks 64, 65 and 66.
The DDR4 0.6V VTT terminaon voltage (net DDR4_VTERM_0V6) is sourced from the TI
TPS51200DR linear regulator U71. The DDR4 memory interface bank VREF pins are not
connected, which, coupled with an XDC set_property INTERNAL VREF constraint, invoke the
INTERNAL VREF mode. The connecons between the 72-bit interface DDR4 component
memories and XCVU37P banks 64, 65, and 66 are listed in the following table.
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VCU128 Board User Guide 20
Chapter 3: Board Component Descriptions
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Table 6: DDR4 Memory 72-bit I/F to FPGA U1 Banks 64, 65, and 66
FPGA (U1) Pin
BM45PL_DDR4_DQ0POD12_DCIA3DQ8U74
BP44PL_DDR4_DQ1POD12_DCIB8DQ9U74
BP47PL_DDR4_DQ2POD12_DCIC3DQ10U74
BN45PL_DDR4_DQ3POD12_DCIC7DQ11U74
BM44PL_DDR4_DQ4POD12_DCIC2DQ12U74
BN44PL_DDR4_DQ5POD12_DCIC8DQ13U74
BN47PL_DDR4_DQ6POD12_DCID3DQ14U74
BP43PL_DDR4_DQ7POD12_DCID7DQ15U74
BN46PL_DDR4_DQS0_TDIFF_POD12_DCIB7UDQS_TU74
BP46PL_DDR4_DQS0_CDIFF_POD12_DCIA7UDQS_CU74
BN42PL_DDR4_DM0_BPOD12_DCIE2NF/UDM_B/UDBI_BU74
BL45PL_DDR4_DQ8POD12_DCIG2DQ0U17
BK44PL_DDR4_DQ9POD12_DCIF7DQ1U17
BL46PL_DDR4_DQ10POD12_DCIH3DQ2U17
BK43PL_DDR4_DQ11POD12_DCIH7DQ3U17
BL43PL_DDR4_DQ12POD12_DCIH2DQ4U17
BJ44PL_DDR4_DQ13POD12_DCIH8DQ5U17
BL42PL_DDR4_DQ14POD12_DCIJ3DQ6U17
BJ43PL_DDR4_DQ15POD12_DCIJ7DQ7U17
BK45PL_DDR4_DQS1_TDIFF_POD12_DCIG3LDQS_TU17
BK46PL_DDR4_DQS1_CDIFF_POD12_DCIF3LDQS_CU17
BL47PL_DDR4_DM1_BPOD12_DCIE7NF/LDM_B/LDBI_BU17
BK41PL_DDR4_DQ16POD12_DCIG2DQ0U74
BG44PL_DDR4_DQ17POD12_DCIF7DQ1U74
BG42PL_DDR4_DQ18POD12_DCIH3DQ2U74
BH44PL_DDR4_DQ19POD12_DCIH7DQ3U74
BH45PL_DDR4_DQ20POD12_DCIH2DQ4U74
BG45PL_DDR4_DQ21POD12_DCIH8DQ5U74
BG43PL_DDR4_DQ22POD12_DCIJ3DQ6U74
BJ41PL_DDR4_DQ23POD12_DCIJ7DQ7U74
BH46PL_DDR4_DQS2_TDIFF_POD12_DCIG3LDQS_TU74
BJ46PL_DDR4_DQS2_CDIFF_POD12_DCIF3LDQS_CU74
BH42PL_DDR4_DM2_BPOD12_DCIE7NF/LDM_B/LDBI_BU74
BE43PL_DDR4_DQ24POD12_DCIG2DQ0U18
BF42PL_DDR4_DQ25POD12_DCIF7DQ1U18
BC42PL_DDR4_DQ26POD12_DCIH3DQ2U18
BF43PL_DDR4_DQ27POD12_DCIH7DQ3U18
BD42PL_DDR4_DQ28POD12_DCIH2DQ4U18
Schematic Net
Name
I/O Standard
Pin #Pin NameRef. Des.
Component Memory
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VCU128 Board User Guide 21
Chapter 3: Board Component Descriptions
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Table 6: DDR4 Memory 72-bit I/F to FPGA U1 Banks 64, 65, and 66 (cont'd)
The VCU128 DDR4 memory component interfaces adhere to the constraints guidelines
documented in the “DDR3/DDR4 Design Guidelines” secon of the UltraScale Architecture-BasedFPGAs Memory IP LogiCORE IP Product Guide (PG150). The VCU128 board DDR4 memory
component interface is a 40Ω impedance implementaon.
For more informaon on the internal VREF, see the “Supply Voltages for the SelectIO Pins VREF”
and the “Internal VREF” secons in the UltraScale Architecture SelectIO Resources User Guide
(UG571). For more details about the Micron DDR4 component memory, see the Micron
MT40A512M16LY data sheet at the Micron Technology website.
RLD3 Component Memory
[Figure 2, callout 5]
The 288 MB RLD3 72-bit wide component memory system is comprised of two 36-bit 1.125 Gb
RLDRAM3 devices located at U39 and U37.
• Manufacturer: Micron
• Part Number: MT44K32M36RB-107E
• Descripon:
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VCU128 Board User Guide 24
○1.125 Gb (32 Mb x 36)
Chapter 3: Board Component Descriptions
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○1.2V 168-ball BGA
○Up to RL3-1866
The VCU128 XCVU37P FPGA RLDRAM3 interface performance is documented in the VirtexUltraScale+ FPGA Data Sheet: DC and AC Switching Characteriscs (DS923).
This memory system is connected to the XCVU37P HP banks 73, 74, and 75. The RLD3 0.6V
VTT terminaon voltage (net RLD3_VTERM_0V6) is sourced from TI TPS51200DR linear
regulator U92. The RLD3 memory interface bank VREF pins are not connected, which, coupled
with an XDC set_property INTERNAL_VREF constraint, invoke the INTERNAL VREF mode. The
connecons between the RLD3 component memories and XCVU37P banks 73, 74, and 75 are
listed in the following table.
Table 7: RLD3 Memory 72-bit I/F to FPGA U1 Banks 73, 74, and 75
FPGA (U1)
Pin
K29RLD3_72B_DQ0SSTL12D11DQ0U39
J30RLD3_72B_DQ1SSTL12E10DQ1U39
K32RLD3_72B_DQ2SSTL12C8DQ2U39
J31RLD3_72B_DQ3SSTL12C10DQ3U39
L29RLD3_72B_DQ4SSTL12C12DQ4U39
L31RLD3_72B_DQ5SSTL12B9DQ5U39
L30RLD3_72B_DQ6SSTL12B11DQ6U39
J32RLD3_72B_DQ7SSTL12A8DQ7U39
K31RLD3_72B_DQ8SSTL12A10DQ8U39
G30RLD3_72B_DQ9SSTL12J10DQ9U39
H30RLD3_72B_DQ10SSTL12K11DQ10U39
F31RLD3_72B_DQ11SSTL12K13DQ11U39
G28RLD3_72B_DQ12SSTL12L8DQ12U39
H29RLD3_72B_DQ13SSTL12L10DQ13U39
G31RLD3_72B_DQ14SSTL12L12DQ14U39
G32RLD3_72B_DQ15SSTL12M9DQ15U39
H32RLD3_72B_DQ16SSTL12M11DQ16U39
F28RLD3_72B_DQ17SSTL12N8DQ17U39
E33RLD3_72B_DQ18SSTL12D3DQ18U39
F29RLD3_72B_DQ19SSTL12E4DQ19U39
E29RLD3_72B_DQ20SSTL12C6DQ20U39
C32RLD3_72B_DQ21SSTL12C4DQ21U39
F33RLD3_72B_DQ22SSTL12C2DQ22U39
D30RLD3_72B_DQ23SSTL12B5DQ23U39
D32RLD3_72B_DQ24SSTL12B3DQ24U39
D29RLD3_72B_DQ25SSTL12A6DQ25U39
Schematic Net
Name
I/O Standard
Pin #Pin NameRef. Des.
Component Memory
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VCU128 Board User Guide 25
Chapter 3: Board Component Descriptions
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Table 7: RLD3 Memory 72-bit I/F to FPGA U1 Banks 73, 74, and 75 (cont'd)
FPGA (U1)
Pin
D31RLD3_72B_DQ26SSTL12A4DQ26U39
A31RLD3_72B_DQ27SSTL12J4DQ27U39
B32RLD3_72B_DQ28SSTL12K3DQ28U39
A33RLD3_72B_DQ29SSTL12K1DQ29U39
B30RLD3_72B_DQ30SSTL12L6DQ30U39
A30RLD3_72B_DQ31SSTL12L4DQ31U39
C28RLD3_72B_DQ32SSTL12L2DQ32U39
C29RLD3_72B_DQ33SSTL12M5DQ33U39
A29RLD3_72B_DQ34SSTL12M3DQ34U39
B28RLD3_72B_DQ35SSTL12N6DQ35U39
G42RLD3_72B_DQ36SSTL12D11DQ0U37
G41RLD3_72B_DQ37SSTL12E10DQ1U37
H42RLD3_72B_DQ38SSTL12C8DQ2U37
G40RLD3_72B_DQ39SSTL12C10DQ3U37
H43RLD3_72B_DQ40SSTL12C12DQ4U37
J42RLD3_72B_DQ41SSTL12B9DQ5U37
H40RLD3_72B_DQ42SSTL12B11DQ6U37
J40RLD3_72B_DQ43SSTL12A8DQ7U37
J41RLD3_72B_DQ44SSTL12A10DQ8U37
D44RLD3_72B_DQ45SSTL12J10DQ9U37
F45RLD3_72B_DQ46SSTL12K11DQ10U37
F44RLD3_72B_DQ47SSTL12K13DQ11U37
D46RLD3_72B_DQ48SSTL12L8DQ12U37
F46RLD3_72B_DQ49SSTL12L10DQ13U37
E44RLD3_72B_DQ50SSTL12L12DQ14U37
E46RLD3_72B_DQ51SSTL12M9DQ15U37
G45RLD3_72B_DQ52SSTL12M11DQ16U37
H45RLD3_72B_DQ53SSTL12N8DQ17U37
B46RLD3_72B_DQ54SSTL12D3DQ18U37
A46RLD3_72B_DQ55SSTL12E4DQ19U37
C43RLD3_72B_DQ56SSTL12C6DQ20U37
B45RLD3_72B_DQ57SSTL12C4DQ21U37
A45RLD3_72B_DQ58SSTL12C2DQ22U37
C45RLD3_72B_DQ59SSTL12B5DQ23U37
C44RLD3_72B_DQ60SSTL12B3DQ24U37
D42RLD3_72B_DQ61SSTL12A6DQ25U37
A43RLD3_72B_DQ62SSTL12A4DQ26U37
D40RLD3_72B_DQ63SSTL12J4DQ27U37
Schematic Net
Name
I/O Standard
Pin #Pin NameRef. Des.
Component Memory
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Chapter 3: Board Component Descriptions
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Table 7: RLD3 Memory 72-bit I/F to FPGA U1 Banks 73, 74, and 75 (cont'd)
FPGA (U1)
Pin
C40RLD3_72B_DQ64SSTL12K3DQ28U37
A39RLD3_72B_DQ65SSTL12K1DQ29U37
A41RLD3_72B_DQ66SSTL12L6DQ30U37
B41RLD3_72B_DQ67SSTL12L4DQ31U37
B40RLD3_72B_DQ68SSTL12L2DQ32U37
D41RLD3_72B_DQ69SSTL12M5DQ33U37
B42RLD3_72B_DQ70SSTL12M3DQ34U37
E41RLD3_72B_DQ71SSTL12N6DQ35U37
J29RLD3_72B_DM0SSTL12B7DM0U39
A28RLD3_72B_DM1SSTL12M7DM1U39
G43RLD3_72B_DM2SSTL12B7DM0U37
A40RLD3_72B_DM3SSTL12M7DM1U37
D39RLD3_72B_A0SSTL12E2A0U37, U39
A38RLD3_72B_A1SSTL12F5A1U37, U39
B38RLD3_72B_A2SSTL12F4A2U37, U39
J34RLD3_72B_A3SSTL12F9A3U37, U39
K34RLD3_72B_A4SSTL12F10A4U37, U39
K37RLD3_72B_A5SSTL12F12A5U37, U39
C38RLD3_72B_A6SSTL12G3A6U37, U39
E36RLD3_72B_A7SSTL12F1A7U37, U39
B35RLD3_72B_A8SSTL12G11A8U37, U39
L35RLD3_72B_A9SSTL12F13A9U37, U39
D34RLD3_72B_A10SSTL12H13A10U37, U39
E39RLD3_72B_A11SSTL12D1A11U37, U39
A35RLD3_72B_A12SSTL12H11A12U37, U39
C35RLD3_72B_A13SSTL12D13A13U37, U39
E37RLD3_72B_A14SSTL12H3A14U37, U39
E38RLD3_72B_A15SSTL12G2A15U37, U39
C37RLD3_72B_A16SSTL12H4A16U37, U39
B36RLD3_72B_A17SSTL12H10A17U37, U39
F34RLD3_72B_A18SSTL12G12A18U37, U39
J37RLD3_72B_A19SSTL12H1A19U37, U39
C39RLD3_72B_A20SSTL12F2NF_A20U37, U39
C34RLD3_72B_BA0SSTL12G9BA0U37, U39
B37RLD3_72B_BA1SSTL12G5BA1U37, U39
A36RLD3_72B_BA2SSTL12H8BA2U37, U39
D36RLD3_72B_BA3SSTL12H6BA3U37, U39
D37RLD3_72B_WE_BSSTL12F6WE_BU37, U39
Schematic Net
Name
I/O Standard
Pin #Pin NameRef. Des.
Component Memory
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Chapter 3: Board Component Descriptions
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Table 7: RLD3 Memory 72-bit I/F to FPGA U1 Banks 73, 74, and 75 (cont'd)
FPGA (U1)
Pin
E34RLD3_72B_REF_BSSTL12F8REF_BU37, U39
G37RLD3_72B_CK_PSSTL12H7CKU37, U39
F38RLD3_72B_CK_NSSTL12G7CK_BU37, U39
D35RLD3_72B_RESET_BSSTL12A13RESET_BU37, U39
A34RLD3_72B_CS_BSSTL12E12CS_BU37, U39
H37RLD3_72B_DK0_PDIFF_SSTL12D7DK0U39
H38RLD3_72B_DK0_NDIFF_SSTL12C7DK0_BU39
H34RLD3_72B_DK1_PDIFF_SSTL12K7DK1U39
H35RLD3_72B_DK1_NDIFF_SSTL12L7DK1_BU39
G38RLD3_72B_DK2_PDIFF_SSTL12D7DK0U37
F39RLD3_72B_DK2_NDIFF_SSTL12C7DK0_BU37
G35RLD3_72B_DK3_PDIFF_SSTL12K7DK1U37
G36RLD3_72B_DK3_NDIFF_SSTL12L7DK1_BU37
L33RLD3_72B_QK0_PDIFF_SSTL12D9QK0U39
K33RLD3_72B_QK0_NDIFF_SSTL12E8QK0_BU39
H33RLD3_72B_QK1_PDIFF_SSTL12K9QK1U39
G33RLD3_72B_QK1_NDIFF_SSTL12J8QK1_BU39
E31RLD3_72B_QK2_PDIFF_SSTL12D5QK2U39
E32RLD3_72B_QK2_NDIFF_SSTL12E6QK2_BU39
C30RLD3_72B_QK3_PDIFF_SSTL12K5QK3U39
B31RLD3_72B_QK3_NDIFF_SSTL12J6QK3_BU39
K41RLD3_72B_QK4_PDIFF_SSTL12D9QK0U37
K42RLD3_72B_QK4_NDIFF_SSTL12E8QK0_BU37
J44RLD3_72B_QK5_PDIFF_SSTL12K9QK1U37
H44RLD3_72B_QK5_NDIFF_SSTL12J8QK1_BU37
E42RLD3_72B_QK6_PDIFF_SSTL12D5QK2U37
E43RLD3_72B_QK6_NDIFF_SSTL12E6QK2_BU37
F40RLD3_72B_QK7_PDIFF_SSTL12K5QK3U37
F41RLD3_72B_QK7_NDIFF_SSTL12J6QK3_BU37
F30RLD3_72B_QVLD0SSTL12J12QVLD0U39
E28RLD3_72B_QVLD1SSTL12J2QVLD1U39
D45RLD3_72B_QVLD2SSTL12J12QVLD0U37
A44RLD3_72B_QVLD3SSTL12J2QVLD1U37
Schematic Net
Name
I/O Standard
Pin #Pin NameRef. Des.
Component Memory
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VCU128 Board User Guide 28
The VCU128 RLD3 72-bit memory component interface adheres to the constraints guidelines
documented in the "RLD3 Design Guidelines" secon of the UltraScale Architecture-Based FPGAsMemory IP LogiCORE IP Product Guide (PG150). The VCU128 RLD3 memory component interface
is a 40Ω impedance implementaon.
Chapter 3: Board Component Descriptions
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For more informaon on the internal VREF, see the "Supply Voltages for the SelectIO Pins",
“VREF”, and “Internal VREF” secons in the UltraScale Architecture SelectIO Resources User Guide
(UG571). For more details about the Micron RLD3 component memory, see the Micron
MT44K32M36RB Data Sheet at the Micron Technology website.
QDR4 Component Memory
[Figure 2, callout 6]
The 4.5 GB QDR4 component memory system is comprised of one 144-Mbit density (4M × 36)
QDR4 SRAM device located at U40.
•
Manufacturer: Cypress
•
Part Number: CY7C4142KV13_106FCXC
•
Descripon:
○144-Mbit density (4M × 36)
○Dual independent 36-bit bidireconal double data rate (DDR) data ports
○Supports concurrent read/write transacons on both ports
○Single address port used to control both data ports
○1.2V 361-ball FCBGA
○Maximum operang frequency of 1066 MHz
The VCU128 XCVU37P FPGA QDR IV interface performance is documented in the VirtexUltraScale+ FPGA Data Sheet: DC and AC Switching Characteriscs (DS923).
The 72-bit wide QDR4 memory is connected to XCVU37P U1 HP banks 68, 69, and 70. The
QDR4 memory interface bank VREF pins are not connected, which, coupled with an XDC
set_property INTERNAL VREF constraint, invoke the INTERNAL VREF mode. The connecons
between the 72-bit interface QDR4 component memories and XCVU37P banks 68, 69, and 70
are listed in the following table.
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Table 8: QDR4 Memory 72-bit I/F to FPGA U1 Banks 68, 69, and 70
FPGA (U1) Pin
BM14QDR4_DQA0C8DQA0
BM13QDR4_DQA1B7DQA1
BN15QDR4_DQA2C6DQA2
BN12QDR4_DQA3D5DQA3
BM15QDR4_DQA4D7DQA4
BP13QDR4_DQA5A4DQA5
BP14QDR4_DQA6F5DQA6
BM12QDR4_DQA7A6DQA7
BL15QDR4_DQA8A8DQA8
BM9QDR4_DQA9H3DQA9
BK9QDR4_DQA10H5DQA10
BL10QDR4_DQA11J2DQA11
BK10QDR4_DQA12J4DQA12
BL8QDR4_DQA13B2DQA13
BN10QDR4_DQA14E2DQA14
BM10QDR4_DQA15G2DQA15
BN9QDR4_DQA16G4DQA16
BJ9QDR4_DQA17B5DQA17
BL12QDR4_DQA18C12DQA18
BK14QDR4_DQA19B13DQA19
BJ12QDR4_DQA20C14DQA20
BK15QDR4_DQA21D15DQA21
BL13QDR4_DQA22D13DQA22
BH14QDR4_DQA23A16DQA23
BH15QDR4_DQA24F15DQA24
BJ14QDR4_DQA25A14DQA25
BJ13QDR4_DQA26A12DQA26
BE9QDR4_DQA27H17DQA27
BE10QDR4_DQA28H15DQA28
BG13QDR4_DQA29J18DQA29
BE11QDR4_DQA30J16DQA30
BF10QDR4_DQA31B18DQA31
BG12QDR4_DQA32E18DQA32
BG9QDR4_DQA33G18DQA33
BG10QDR4_DQA34G16DQA34
BF12QDR4_DQA35B15DQA35
Schematic Net
Name
I/O Standard
QDR4 A-side Data
Component Memory
Pin #Pin Name
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Table 8: QDR4 Memory 72-bit I/F to FPGA U1 Banks 68, 69, and 70 (cont'd)
FPGA (U1) Pin
BP12QDR4_DKA0_PF4DKA0_P
BP11QDR4_DKA0_NF3DKA0_N
BH10QDR4_DKA1_PF16DKA1_P
BH9QDR4_DKA1_NF17DKA1_N
BP9QDR4_QKA0_PC4QKA0_P
BP8QDR4_QKA0_ND3QKA0_N
BJ11QDR4_QKA1_PC16QKA1_P
BK11QDR4_QKA1_ND17QKA1_N
BM8QDR4_QVLDA0C3QVLDA0
BK13QDR4_QVLDA1C17QVLDA1
BM3QDR4_LDA_NH8LDA_N
BM4QDR4_RWA_NH10RWA_N
R522(GND)
R519(GND)
1
1
H15QDR4_DQB0U8DQB0
J15QDR4_DQB1V7DQB1
J12QDR4_DQB2U6DQB2
J11QDR4_DQB3T5DQB3
H14QDR4_DQB4T7DQB4
G13QDR4_DQB5W4DQB5
J14QDR4_DQB6P5DQB6
H12QDR4_DQB7W6DQB7
H13QDR4_DQB8W8DQB8
G11QDR4_DQB9M3DQB9
E12QDR4_DQB10M5DQB10
F10QDR4_DQB11L2DQB11
E11QDR4_DQB12L4DQB12
D10QDR4_DQB13V2DQB13
E9QDR4_DQB14R2DQB14
F9QDR4_DQB15N2DQB15
F11QDR4_DQB16N4DQB16
D11QDR4_DQB17V5DQB17
E14QDR4_DQB18U12DQB18
A14QDR4_DQB19V13DQB19
D15QDR4_DQB20U14DQB20
B15QDR4_DQB21T15DQB21
Schematic Net
Name
QDR4_DINVA0D8DINVA0
QDR4_DINVA1D12DINVA1
I/O Standard
QDR4 A-side Control
QDR4 B-side Data
Component Memory
Pin #Pin Name
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Chapter 3: Board Component Descriptions
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Table 8: QDR4 Memory 72-bit I/F to FPGA U1 Banks 68, 69, and 70 (cont'd)
FPGA (U1) Pin
F13QDR4_DQB22T13DQB22
C15QDR4_DQB23W16DQB23
F15QDR4_DQB24P15DQB24
A15QDR4_DQB25W14DQB25
F14QDR4_DQB26W12DQB26
C12QDR4_DQB27M17DQB27
A11QDR4_DQB28M15DQB28
B13QDR4_DQB29L18DQB29
B12QDR4_DQB30L16DQB30
A8QDR4_DQB31V18DQB31
A9QDR4_DQB32R18DQB32
B11QDR4_DQB33N18DQB33
B10QDR4_DQB34N16DQB34
A10QDR4_DQB35V15DQB35
K14QDR4_DKB0_PP4DKB0_P
K13QDR4_DKB0_NP3DKB0_N
C10QDR4_DKB1_PP16DKB1_P
C9QDR4_DKB1_NP17DKB1_N
H10QDR4_QKB0_PU4QKB0_P
G10QDR4_QKB0_NT3QKB0_N
E13QDR4_QKB1_PU16QKB1_P
D12QDR4_QKB1_NT17QKB1_N
D9QDR4_QVLDB0U3QVLDB0
D14QDR4_QVLDB1U17QVLDB1
BL2QDR4_LDB_NH12LDB_N
BL3QDR4_RWB_NL10RWB_N
R606(GND)
R602(GND)
1
1
BF5QDR4_A0F10A0
BF1QDR4_A1G10A1
BE1QDR4_A2N10A2
BE3QDR4_A3G7A3
BE4QDR4_A4G13A4
BE5QDR4_A5J7A5
BE6QDR4_A6J13A6
BF2QDR4_A7L7A7
Schematic Net
Name
QDR4_DINVB0T8DINVB0
QDR4_DINVB1T12DINVB1
I/O Standard
QDR4 B-side Control
Common
Component Memory
Pin #Pin Name
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Table 8: QDR4 Memory 72-bit I/F to FPGA U1 Banks 68, 69, and 70 (cont'd)
FPGA (U1) Pin
BF3QDR4_A8L13A8
BG2QDR4_A9N7A9
BG3QDR4_A10N13A10
BG4QDR4_A11M8A11
BG5QDR4_A12M12A12
BF7QDR4_A13F8A13
BF8QDR4_A14F12A14
BG7QDR4_A15P8A15
BG8QDR4_A16P12A16
BJ7QDR4_A17L9A17
BH7QDR4_A18L11A18_36M
BK8QDR4_A19J9A19_72M
BJ8QDR4_A20J11A20_144M
BJ6QDR4_A21G9A21_288M
BK5QDR4_A22G11A22_576M
BH6QDR4_A23N9A23_1152M
BK4QDR4_A24N11A24_2304M
BK6QDR4_APP10AP
BJ1QDR4_AINVM10AINV
BH5QDR4_CK_PJ10CK_P
BH4QDR4_CK_NK10CK_N
BJ3QDR4_LBK0_NA10LBK0_N
BH1QDR4_LBK1_NB10LBK1_N
BH2QDR4_CFG_ND10CFG_N
BJ2QDR4_PE_NV10PE_N
BK1QDR4_RST_NK18RST_N
Notes:
1.Resistors to GND are 100Ω.
Schematic Net
Name
QDR4 U40 ZQ_ZT pin W10 is wired to 220Ω R604 to GND
I/O Standard
Pin #Pin Name
Component Memory
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VCU128 Board User Guide 33
The VCU128 QDR-IV dual independent 36-bit bidireconal data port memory component
interfaces adhere to the constraints guidelines documented in the "QDR-IV Design Guidelines"
secon of the UltraScale Architecture-Based FPGAs Memory IP LogiCORE IP Product Guide (PG150).
The VCU128 QDR-IV memory component interface is a 40Ω impedance implementaon.
For more informaon on the internal VREF, see the "Supply Voltages for the SelectIO Pins",
“VREF”, and “Internal VREF” secons in the UltraScale Architecture SelectIO Resources User Guide
(UG571). For more details about the Cypress QDR-IV component memory, see the Cypress
CY7C4142KV13_106FCXC Data Sheet at the Cypress Semiconductor website.
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Quad SPI Flash Memory
[Figure 2, callout 7]
VCU128 boards host a Micron MT25QU02GCBB8E12-0SIT serial NOR ash Quad SPI ash
memory capable of holding the boot image for the XCVU37P FPGA. This interface supports the
QSPI32 boot mode as dened in the UltraScale Architecture Conguraon User Guide (UG570).
The Quad SPI ash memory U46 provides 2 Gb of non-volale storage that can be used for
conguraon and data storage.
• Part number: MT25QU02GCBB8E12-0SIT (Micron)
• Supply voltage: 1.8V
• Datapath width: 4 bits
• Data rate: various depending on single/dual/quad mode
The Quad SPI circuitry is shown in the following gure.
Figure 7: Quad SPI (2 Gbit) Flash Memory
X21957-121918
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VCU128 Board User Guide 34
The connecons between the Quad SPI ash memory and the XCVU37P FPGA are listed in the
following table.
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Table 9: Quad-SPI Component Connections to FPGA U1
XCVC37P (U1) PinNet Name
Pin #Pin Name
AW15QSPI_DQ0D3DQ0
AY15QSPI_DQ1D2DQ1
AY14QSPI_DQ2C4DQ2_W_B
AY13QSPI_DQ3D4DQ3_RST_HLD_B
BD14QSPI _CLKB2C
BC15QSPI_CS_BC2S_B
U46 Quad SPI
The UltraScale Architecture Conguraon User Guide (UG570) provides FPGA conguraon details.
For more Quad SPI component informaon, see the Micron MT25QU02GCBB8E12-0SIT data
sheet at the Micron Technology website.
USB JTAG Interface
[Figure 2, callout 24]
JTAG conguraon is provided through a dual-funcon FTDI FT4232HL USB-to-JTAG/UART
bridge device (U8) where a host computer accesses the VCU128 board JTAG chain through a
type-A (PC host side) to micro-AB (VCU128 board side J2) USB cable.
A 2 mm JTAG header (J4) is also provided in parallel for access by Xilinx® download cables, such
as the Plaorm Cable USB II. JTAG iniatedconguraon takes priority over the conguraon
method selected through the FPGA mode pins M[2:0], wired to SW1 posions [2:4]. The JTAG
chain of the VCU128 board is shown in the following gure.
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VCU128 Board User Guide 35
FTDI
SendFeedback
USB
JTAG
(U8)
JTAG
2 mm
Conn.
(J4)
TCK
TMS
TDI
TDO
TDO
TDI
TMS
TCK
Chapter 3: Board Component Descriptions
Figure 8: JTAG Chain Block Diagram
U1
U50
1.8V3.3V
Level-shift
TCK
TMS
TDITDO
FPGA
SPST Bus Switch
U72
J18
FMC+
HSPC
Connector
TMS
TCK
TDO
U75
1.8V3.3V
Level-shift
N.C.
TDI
X21649-110618
FMCP Connector JTAG Bypass
When an FMC is aached to the VCU128 board FMC+ HSPC connector J18, it is automacally
added to the JTAG chain through the electronically controlled single-pole single-throw (SPST)
switch U72. The SPST switch is in a normally closed state and transions to an open state when
the FMC is aached. Switch U72 adds an aached FMC to the FPGA JTAG chain as determined
by the FMCP_HSPC_PRSNT_M2C_B signal.
IMPORTANT
bypass jumper to ensure that the JTAG chain connects to the FPGA U1.
The JTAG connecvity on the VCU128 board allows a host computer to download bitstreams to
the FPGA using the Xilinx® tools. In addion, the JTAG connector allows debug tools such as the
Vivado® serial I/O analyzer or a soware debugger to access the FPGA. The Xilinx tools can also
program the Quad SPI ash memory.
! The aached FMC must implement a TDI-to-TDO connecon through a device or
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USB UART Interface
[Figure 2, callout 24]
The FT4232HL U8 mul-funcon USB-UART on the VCU128 board provides three level-shied
UART connecons through the single micro-AB USB connector J2.
• Channel A is congured in JTAG mode to support the JTAG chain
• Channel B implements 4-wire UART0 (level-shied) FPGA U1 bank 67 connecons
• Channel C implements 4-wire UART1 (level-shied) FPGA U1 bank 67 connecons
• Channel D implements 2-wire (level-shied) SYSCTLR U42 bank 501 connecons
The USB UART interface circuit is shown in the following gure. The FTDI FT4232HL data sheet
is available on the Future Technology Devices Internaonal Ltd. website.
Figure 9: FTDI USB JTAG/UART Circuit
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VCU128 Board User Guide 37
X21958-121918
Chapter 3: Board Component Descriptions
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Clock Generation
[Figure 2, callout 10-18]
The VCU128 evaluaon board clock sources to the FPGA are listed in the following table.
Table 10: Board Clock Sources
Clock NameClock Ref. Des.Description
Memory Interface Clocks
DDR4 clock 100 MHzU76SiTime SiT9120AI 3.3V fixed frequency
QDR4 clock 100 MHzU96SiTime SiT9120AI 3.3V fixed frequency
RLD3 clock 100 MHzU45SiTime SiT9120AI 3.3V fixed frequency
multiplier/jitter attenuator. See Jitter
Attenuated Clock (SI5328_CLOCK1/2_P/N)
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VCU128 Board User Guide 38
The following table lists the VCU128 clock sources-to-FPGA U1 connecons.
Table 11: Clock Sources to XCVU37P FPGA U1 Connections
Clock Source Device/
U#.Pin#
SIT9120AI/U76.4DDR4_CLK_100MHZ_PLVDSBH51
SIT9120AI/U76.5DDR4_CLK_100MHZ_NLVDSBJ51
SIT9120AI/U96.4QDR4_CLK_100MHZ_PLVDSBJ4
Schematic Net NameI/O StandardFPGA (U1) Pin
Memory Interface Clocks
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Table 11: Clock Sources to XCVU37P FPGA U1 Connections (cont'd)
Clock Source Device/
U#.Pin#
Schematic Net NameI/O StandardFPGA (U1) Pin
SIT9120AI/U96.5QDR4_CLK_100MHZ_NLVDSBK3
SIT9120AI/U45.4RLD3_CLK_100MHZ_PLVDSF35
SIT9120AI/U45.5RLD3_CLK_100MHZ_NLVDSF36
QSFP Interface Clocks
SI570/U95.4QSFP1_SI570_CLOCK_P
SI570/U95.5QSFP1_SI570_CLOCK_N
SI570/U90.4QSFP2_SI570_CLOCK_P
SI570/U90.5QSFP2_SI570_CLOCK_N
SI570/U82.4QSFP3_SI570_CLOCK_P
SI570/U82.5QSFP3_SI570_CLOCK_N
SI570/U80.4QSFP4_SI570_CLOCK_P
SI570/U80.5QSFP4_SI570_CLOCK_N
1
1
1
1
1
1
1
1
SMA GTY REFCLK and User Clock
SMA J24.1SMA_REFCLK_INPUT_P
SMA J26.1SMA_REFCLK_INPUT_N
SMA J12.1SMA_CLK_OUTPUT_P
SMA J13.1SMA_CLK_OUTPUT_N
1
1
2
2
QSFP1/2 Recovery Clocks
SI5328B/U87.29SI5328_CLOCK1_P
SI5328B/U87.28SI5328_CLOCK1_P
SI5328B/U87.35SI5328_CLOCK2_P
SI5328B/U87.34SI5328_CLOCK2_P
1
1
1
1
Notes:
1.Series capacitor coupled, MGT connections I/O standard is not applicable.
2.Signal amplitude not to exceed FPGA U1 bank 67 VCCO = VCC1V8 rail = 1.8V.
P42
P43
T42
T43
Y42
Y43
AB42
AB43
AA40
AA41
BK26
BL25
R40
R41
W40
W41
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DDR4 Interface Clock
[Figure 2, callout 10]
The VCU128 evaluaon board has a SiTime 100 MHz xed frequency low-jier 3.3V LVDSdierenal oscillator (U76) connected to FPGA U1 HP bank 66 DDR4 interface GC pins BH51
(P) and BJ51 (N) and is series capacitor coupled.
• Fixed frequency oscillator: SiTime SIT9120AI-2D3-33E100.0000 (100 MHz)
• 0.6 ps RMS phase jier (random) over 12 kHz to 20 MHz bandwidth
• 3.3V LVDS dierenal output
The DDR4 interface xed frequency clock circuit is shown in the following gure.
Figure 10: DDR4 Interface Clock
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QDR4 Interface Clock
[Figure 2, callout 12]
The VCU128 evaluaon board has a SiTime 100 MHz xed frequency low-jier 3.3V LVDSdierenal oscillator (U96) connected to FPGA U1 HP bank 69 QDR4 interface GC pins BJ4 (P)
and BK3 (N) and is series capacitor coupled.
• Fixed frequency oscillator: SiTime SIT9120AI-2D3-33E100.0000 (100 MHz)
• 0.6 ps RMS phase jier (random) over 12 kHz to 20 MHz bandwidth
• 3.3V LVDS dierenal output
The QDR4 interface xed frequency clock circuit is shown in the following gure.
Figure 11: QDR4 Interface Clock
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RLD3 Interface Clock
[Figure 2, callout 11]
The VCU128 evaluaon board has a SiTime 100 MHz xed frequency low-jier 3.3V LVDSdierenal oscillator (U45) connected to FPGA U1 HP bank 74 RLD3 interface GC pins F35 (P)
and F36 (N) and is series capacitor coupled.
• Fixed frequency oscillator: SiTime SIT9120AI-2D3-33E100.0000 (100 MHz)
• 0.6 ps RMS phase jier (random) over 12 kHz to 20 MHz bandwidth
• 3.3V LVDS dierenal output
The RLD3 interface xed frequency clock circuit is shown in the following gure.
The SiTime SiT9120AI data sheet is available on the SiTime Corp. website.
Figure 12: RLD3 Interface Clock
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Programmable QSFP1 Clock
[Figure 2, callout 13]
The VCU128 evaluaon board has a SI570 I2C programmable low-jier 3.3V LVDS dierenal
oscillator (U95) connected to FPGA U1 GTY bank 135 MGTREFCLK0 P/N pins P42 and P43
(series capacitor coupled), respecvely.
On power-up, the U95 SI570 user clock defaults to an output frequency of 156.250 MHz. The
Zynq-7000 SoC system controller or FPGA implemented user IP can change the output
frequency within the range of 10 MHz to 810 MHz through an I2C interface. Power cycling the
VCU128 evaluaon board resets the QSFP1 clock to the default frequency of 156.250 MHz.
The programmable QSFP1 clock circuit is shown in the following gure.
Figure 13: QSFP1 Clock
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Programmable QSFP2 Clock
[Figure 2, callout 14]
The VCU128 evaluaon board has a SI570 I2C programmable low-jier 3.3V LVDS dierenal
oscillator (U90) connected to FPGA U1 GTY bank 134 MGTREFCLK0 P/N pins T42 and T43
(series capacitor coupled), respecvely.
On power-up, the U90 SI570 user clock defaults to an output frequency of 156.250 MHz. The
Zynq-7000 SoC system controller or FPGA implemented user IP can change the output
frequency within the range of 10 MHz to 810 MHz through an I2C interface. Power cycling the
VCU128 evaluaon board resets the QSFP2 clock to the default frequency of 156.250 MHz.
The programmable QSFP2 clock circuit is shown in the following gure.
Figure 14: QSFP2 Clock
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Programmable QSFP3 Clock
[Figure 2, callout 15]
The VCU128 evaluaon board has a SI570 I2C programmable low-jier 3.3V LVDS dierenal
oscillator (U82) connected to FPGA U1 GTY bank 132 MGTREFCLK0 P/N pins Y42 and Y43
(series capacitor coupled), respecvely.
On power-up, the U82 SI570 user clock defaults to an output frequency of 156.250 MHz. The
Zynq-7000 SoC system controller or FPGA implemented user IP can change the output
frequency within the range of 10 MHz to 810 MHz through an I2C interface. Power cycling the
VCU128 evaluaon board resets the QSFP3 clock to the default frequency of 156.250 MHz.
The programmable QSFP3 clock circuit is shown in the following gure.
Figure 15: QSFP3 Clock
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Programmable QSFP4 Clock
[Figure 2, callout 16]
The VCU128 evaluaon board has a SI570 I2C programmable low-jier 3.3V LVDS dierenal
oscillator (U80) connected to FPGA U1 GTY bank 131 MGTREFCLK0 P/N pins AB42 and AB43
(series capacitor coupled), respecvely.
On power-up, the U80 SI570 user clock defaults to an output frequency of 156.250 MHz. The
Zynq-7000 SoC system controller or FPGA implemented user IP can change the output
frequency within the range of 10 MHz to 810 MHz through an I2C interface. Power cycling the
VCU128 evaluaon board resets the QSFP4 clock to the default frequency of 156.250 MHz
The programmable QSFP4 clock circuit is shown in the following gure.
Figure 16: QSFP4 Clock
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QSFP SMA Clock
[Figure 2, callout 18]
The VCU128 board provides a pair of SMAs for dierenal user clock input into FPGA U1 GTY
bank 131. The P-side SMA J24 signal SMA_REFCLK_INPUT_P is connected to FPGA U1 GTY
bank 131 MGTREFCLK1P pin AA40, with the N-side SMA J26 signal SMA_REFCLK_INPUT_N
connected to U1 GTY bank 131 MGTREFCLK1N pin AA41. The transceiver reference clock pin
absolute input voltage range is –0.5V min. to 1.3V max. The user SMA MGT clock circuit is
shown in the following gure.
Figure 17: QSFP SMA Clock
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User SMA Clock
[Figure 2, callout 27]
The VCU128 board provides a pair of SMAs for dierenal user clock I/O on FPGA U1 HP bank
67. The P-side SMA J12 net SMA_CLK_OUTPUT_P is connected to FPGA U1 HP bank 67 QBC
pin BK26. The N-side SMA J13 net SMA_CLK_OUTPUT_N is connected to FPGA U1 HP bank
67 QBC pin BL25. Bank 67 VCC1V8 VCCO is nominally 1.8V. Any signal connected to the
SMA_CLK_OUTPUT SMA connectors in input mode must be equal to or less than the VCCO for
bank 67. This value must be conrmed prior to applying signals to the SMA_CLK_OUTPUT
connectors.
Figure 18: User SMA Clock
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Jitter Attenuated Clock
[Figure 2, callout 17]
The VCU128 board includes a Silicon Labs Si5328B jieraenuator U87 on the back side of the
board. FPGA U1 bank 67 implements two QSFP RX dierenal clocks (QSFP1_RECCLK_P, pin
BH26 and QSFP1_RECCLK_N, pin BH25, and QSFP2_RECCLK_P, pin BJ26 and
QSFP2_RECCLK_N, pin BK25) for jieraenuaon.
The jieraenuated clock pair (SI5328_CLOCK1_C_P (U87 output pin 28),
SI5328_CLOCK1_C_N (U87 output pin 29) is routed as a reference clock to FPGA U1 QSFP2 I/F
GTY Quad 134 inputs MGTREFCLK1P (U1 pin R40) and MGTREFCLK1N (U1 pin R41).
The jieraenuated clock pair (SI5328_CLOCK2_C_P (U87 output pin 35),
SI5328_CLOCK2_C_N (U87 output pin 34) is routed as a reference clock to FPGA U1 QSFP3 I/F
GTY Quad 132 inputs MGTREFCLK1P (U1 pin W40) and MGTREFCLK1N (U1 pin W41).
The primary purpose of this clock is to support synchronous protocols, such as common packet
radio interface (CPRI) or open base staon architecture iniave (OBSAI). These synchronous
protocols perform clock recovery from user-supplied QSFP/QSFP+ modules, and use the jieraenuated recovered clock to drive the reference clock inputs of a GTY transceiver.
The jieraenuated clock circuit is shown in the following gure.
Figure 19: QSFP Recovery Clock
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The SI5328B U87 I2C interface is connected to port 1 of the I2C0 bus TCA9548A U53 bus
switch and can be congured by either the U42 system controller or U1 FPGA IP.
The system controller congures SI5328B U87 in free-run mode or automacally switches over
to one of two recovered clock inputs for synchronous operaon. Enabling the jieraenuaon
feature requires addional user programming through the I2C bus. The Silicon Labs Si570 and
Si5328B data sheets are available on the Silicon Labs website.
GTY Transceivers
The GTY transceivers in the XCVU37P are grouped into four channels or quads. The XCVU37P
has twelve GTY quads on the le side of the device and twelve GTY Quads on the right side of
the device.
The VCU128 board provides access to 14 of the 24 GTY Quads:
• Four of the GTY Quads are wired to QSFP[1:4] Module Connectors (J42, J39, J35, J32)
• Six of the GTY Quads are wired to FMC+ HSPC connector DP[0:23] (J18)
• Four of the GTY Quads are wired to the PCIe 16-lane edge connector (P1)
• Ten GTY Quads are not used (GTYs 130, 133, 228-235)
The reference clock for a Quad can be sourced from the Quad above or the Quad below the GTY
Quad of interest.
Right-side Quads
The ten connected GTY Quads on the right side of the XCVU37P FPGA are described in this
secon (MGTY133 and MGTY130 are not used).
Quad 135
• MGTREFCLK0 – QSFP1_SI570_CLOCK_P/N
• MGTREFCLK1 – NC
• Four GTY transceivers allocated to QSFP1_TX/RX[1:4]_P/N
Quad 134
• MGTREFCLK0 – QSFP2_SI570_CLOCK_P/N
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• MGTREFCLK1 – SI5328_CLOCK1_C_P/N
• Four GTY transceivers allocated to QSFP2_TX/RX[1:4]_P/N
Quad 132
MGTREFCLK0 – QSFP3_SI570_CLOCK_P/N
•
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• MGTREFCLK1 – SI5328_CLOCK2_C_P/N
• Four GTY transceivers allocated to QSFP3_TX/RX[1:4]_P/N
Quad 131
• MGTREFCLK0 – QSFP4_SI570_CLOCK_P/N
• MGTREFCLK1 – SMA_REFCLK_INPUT_P/N
• Four GTY transceivers allocated to QSFP4_TX/RX[1:4]_P/N
Quad 129
• MGTREFCLK0 - FMCP_HSPC_GBTCLK5_M2C_P/N
• NC
• Four GTY transceivers allocated to FMCP_HSPC_DP[20:23]
Quad 128
• MGTREFCLK0 - FMCP_HSPC_GBTCLK4_M2C_P/N
• NC
• Four GTY transceivers allocated to FMCP_HSPC_DP[16:19]
Quad 127
• MGTREFCLK0 – FMCP_HSPC_GBTCLK3_M2C_P/N
• NC
• Four GTY transceivers allocated to FMCP_HSPC_DP[12:15]
Quad 126
• MGTREFCLK0 – FMCP_HSPC_GBTCLK2_M2C_P/N
• NC
• Four GTY transceivers allocated to FMCP_HSPC_DP[8:11]
Quad 125
• MGTREFCLK0 – FMCP_HSPC_GBTCLK1_M2C_P/N
• NC
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• Four GTY transceivers allocated to FMCP_HSPC_DP[4:7]
Quad 124
• MGTREFCLK0 – FMCP_HSPC_GBTCLK0_M2C_P/N
• NC
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• Four GTY transceivers allocated to FMCP_HSPC_DP[0:3]
The XCVU37P right-side GTY transceiver interface assignments are shown in the following
The following tables list the XCVU37P FPGA U1 GTY transceiver banks 227, 226, 225, and 224
connecons,respecvely.
For addionalinformaon on GTY transceivers, see the UltraScale Architecture GTY TransceiversUser Guide (UG578). Also see the UltraScale FPGAs Transceivers Wizard LogiCORE IP Product Guide
(PG182). For addionalinformaon about the quad small form factor pluggable (28 Gb/s
QSFP28) module, see the SFF-8663 and SFF-8679 specicaons for the 28 Gb/s QSFP+ at the
SNIA Technology Aliates website.
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Table 22: XCVU37P U1 GTY Transceiver Bank 227 Connections
MGT
Bank
GTY bank
227
Notes:
1.Series 0.01uF capacitor coupled.
FPGA
(U1)
Pin
AP9MGTYTXP0_227PCIE_EP_TX3_PA29PERP3
AP8
AN2MGTYRXP0_227PCIE_EP_RX3_PB27PETP3
AN1MGTYRXN0_227PCIE_EP_RX3_NB28PETN3
AN11MGTYTXP1_227PCIE_EP_TX2_PA25PERP2
AN10MGTYTXN1_227PCIE_EP_TX2_NA26PERN2
AN6MGTYRXP1_227PCIE_EP_RX2_PB23PETP2
AN5MGTYRXN1_227PCIE_EP_RX2_NB24PETN2
AM9MGTYTXP2_227PCIE_EP_TX1_PA21PERP1
AM8MGTYTXN2_227PCIE_EP_TX1_NA22PERN1
AM4MGTYRXP2_227PCIE_EP_RX1_PB19PETP1
AM3MGTYRXN2_227PCIE_EP_RX1_NB20PETN1
AL11MGTYTXP3_227PCIE_EP_TX0_PA16PERP0
AL10MGTYTXN3_227PCIE_EP_TX0_NA17PERN0
AL2MGTYRXP3_227PCIE_EP_RX0_PB14PETP0
AL1MGTYRXN3_227PCIE_EP_RX0_NB15PETN0
AL15MGTREFCLK0P_227PCIE_CLK2_P
AL14MGTREFCLK0N_227PCIE_CLK2_N
AK13MGTREFCLK1P_227
AK12MGTREFCLK1N_227
FPGA (U1) Pin
Name
MGTYTXN0_227PCIE_EP_TX3_NA30PERN3
Schematic Net
Name TX
1
1
1
NCNCNCNC
Connected
Pin
3Q1ICS85411A
4NQ1
Connected
Pin Name
Connected
Device
PCIE 16-lane
edge conn. P1
U94 clock
buffer
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Table 23: XCVU37P U1 GTY Transceiver Bank 226 Connections
MGT
Bank
GTY bank
226
Notes:
1.Series 0.01uF capacitor coupled.
FPGA
(U1)
Pin
AU11MGTYTXP0_226PCIE_EP_TX7_PA47PERP7
AU10
AU2MGTYRXP0_226PCIE_EP_RX7_PB45PETP7
AU1MGTYRXN0_226PCIE_EP_RX7_NB46PETN7
AT9MGTYTXP1_226PCIE_EP_TX6_PA43PERP6
AT8MGTYTXN1_226PCIE_EP_TX6_NA44PERN6
AT4MGTYRXP1_226PCIE_EP_RX6_PB41PETP6
AT3MGTYRXN1_226PCIE_EP_RX6_NB42PETN6
AR7MGTYTXP2_226PCIE_EP_TX5_PA39PERP5
AR6MGTYTXN2_226PCIE_EP_TX5_NA40PERN5
AR2MGTYRXP2_226PCIE_EP_RX5_PB37PETP5
AR1MGTYRXN2_226PCIE_EP_RX5_NB38PETN5
AR11MGTYTXP3_226PCIE_EP_TX4_PA35PERP4
AR10MGTYTXN3_226PCIE_EP_TX4_NA36PERN4
AP4MGTYRXP3_226PCIE_EP_RX4_PB33PETP4
AP3MGTYRXN3_226PCIE_EP_RX4_NB34PETN4
AN15MGTREFCLK0P_226
AN14MGTREFCLK0N_226
AM13MGTREFCLK1P_226
AM12MGTREFCLK1N_226
FPGA (U1) Pin
Name
MGTYTXN0_226PCIE_EP_TX7_NA48PERN7
Schematic Net
Name TX
1
NCNCNCNC
NCNCNCNC
Connected
Pin
Connected
Pin Name
Connected
Device
PCIE 16-lane
edge conn. P1
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Table 24: XCVU37P U1 GTY Transceiver Bank 225 Connections
MGT
Bank
GTY bank
225
Notes:
1.Series 0.01uF capacitor coupled.
FPGA
(U1)
Pin
AY9MGTYTXP0_225PCIE_EP_TX11_PA64PERP11
AY8
AY4MGTYRXP0_225PCIE_EP_RX11_PB62PETP11
AY3MGTYRXN0_225PCIE_EP_RX11_NB63PETN11
AW11MGTYTXP1_225PCIE_EP_TX10_PA60PERP10
AW10MGTYTXN1_225PCIE_EP_TX10_NA61PERN10
AW2MGTYRXP1_225PCIE_EP_RX10_PB58PETP10
AW1MGTYRXN1_225PCIE_EP_RX10_NB59PETN10
AV9MGTYTXP2_225PCIE_EP_TX9_PA56PERP9
AV8MGTYTXN2_225PCIE_EP_TX9_NA57PERN9
AW6MGTYRXP2_225PCIE_EP_RX9_PB54PETP9
AW5MGTYRXN2_225PCIE_EP_RX9_NB55PETN9
AU7MGTYTXP3_225PCIE_EP_TX8_PA52PERP8
AU6MGTYTXN3_225PCIE_EP_TX8_NA53PERN8
AV4MGTYRXP3_225PCIE_EP_RX8_PB50PETP8
AV3MGTYRXN3_225PCIE_EP_RX8_NB51PETN8
AR15MGTREFCLK0P_225PCIE_CLK1_P
AR14MGTREFCLK0N_225PCIE_CLK1_N
AP13MGTREFCLK1P_225
AP12MGTREFCLK1N_225
FPGA (U1) Pin
Name
MGTYTXN0_225PCIE_EP_TX11_NA65PERN11
Schematic Net
Name TX
1
1
NCNCNCNC
Connected
Pin
1Q0ICS85411A
2NQ0
Connected
Pin Name
Connected
Device
PCIE 16-lane
edge conn. P1
U94 clock
buffer
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Table 25: XCVU37P U1 GTY Transceiver Bank 224 Connections
MGT
bank
GTY bank
224
Notes:
1.Series 0.01uF capacitor coupled.
FPGA
(U1)
Pin
BC7MGTYTXP0_224PCIE_TX15_PA80PERP15
BC6
BC2MGTYRXP0_224PCIE_RX15_PB78PETP15
BC1MGTYRXN0_224PCIE_RX15_NB79PETN15
BC11MGTYTXP1_224PCIE_TX14_PA76PERP14
BC10MGTYTXN1_224PCIE_TX14_NA77PERN14
BB4MGTYRXP1_224PCIE_RX14_PB74PETP14
BB3MGTYRXN1_224PCIE_RX14_NB75PETN14
BB9MGTYTXP2_224PCIE_TX13_PA72PERP13
BB8MGTYTXN2_224PCIE_TX13_NA73PERN13
BA2MGTYRXP2_224PCIE_RX13_PB70PETP13
BA1MGTYRXN2_224PCIE_RX13_NB71PETN13
BA11MGTYTXP3_224PCIE_TX12_PA68PERP12
BA10MGTYTXN3_224PCIE_TX12_NA69PERN12
BA6MGTYRXP3_224PCIE_RX12_PB66PETP12
BA5MGTYRXN3_224PCIE_RX12_NB67PETN12
AV13MGTREFCLK0P_224
AV12MGTREFCLK0N_224
AT13MGTREFCLK1P_224
AT12MGTREFCLK1N_224
FPGA (U1) Pin
Name
MGTYTXN0_224PCIE_TX15_NA81PERN15
Schematic Net
Name TX
NCNCNCNC
NCNCNCNC
Connected
Pin
Connected
Pin Name
Connected
device
PCIE 16-lane
edge conn. P1
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PCI Express Endpoint Connectivity
[Figure 2, callout 20]
The 16-lane PCI Express® edge connector P1 performs data transfers at the rate of 2.5 GT/s for
Gen1 applicaons, 5.0 GT/s for Gen2 applicaons, 8.0 GT/s for Gen3 applicaons and 16.0 GT/s
for Gen4 applicaons. The PCIe® transmit and receive signal data paths have a characterisc
impedance of 85Ω ±10%. The PCIe clock is routed as a 100Ω dierenal pair.
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The XCVU37P-2FSVH2892E (-2 speed grade) is deployed on the VCU128 to support up to Gen4
x8. User selectable as PCIe Gen3 x16 or dual Gen4 x8. The PCIe reference clock is input from the
P1 edge connector. The PCIe clock is routed from P1 pin A16 (P) and pin A17 (N) to a 1-to-2
ICS85411A clock buer U94. The Q0 output of U94 is wired to the GTY225 MGTHREFCLK0
input (see Table 24). The Q1 output of U94 is wired to the GTY227 MGTHREFCLK0 input (see
Table 22). PCIe lane width/size is selected by jumper J46. The default lane size selecon is 16-
lane (J46 pins 7 and 8 jumpered). The 1-to-2 U94 PCIe clock buer circuit and J46 lane size
jumper are shown in the following gure.
Figure 22: PCI Express Lane Clock Circuit and Size Select Jumper J46
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The tables in Le-side GTY Transceiver Connecvity list the PCIe P1 edge connector wiring to
the XCVU37P FPGA U1 MGTY transceiver banks 227-224. The two PCIe P1 edge connector
control signals PCIE_EP_WAKE (P1 pin B11) and PCIE_EP_PERST (P1 pin A11) are level-shied
by SN74AVC2T245 U70 and connected to the XCVU39P U1 bank 65 pin BJ42 and pin BF41,
respecvely. For addionalinformaon about UltraScale™ PCIe funconality, see the UltraScale
Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156). Addional
informaon about the PCI Express standard is available on the PCI Express standard website.
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28 Gb/s zQSFP+ Module Connectors
[Figure 2, callout 19]
The VCU128 board hosts four QSFP28 small form-factor pluggable (28 Gb/s QSFP+) connectors:
QSFP1 J42, QSFP2 J39, QSFP3 J35, and QSFP4 J32, which accept 28 Gb/s QSFP+ opcal
modules. The four connectors are housed within a single 1x4 ganged 28 Gb/s QSFP+ cage
assembly J37. The following gure shows a typical implementaon of the 28 Gb/s QSFP28
module connector circuitry.
Table 12 through Table 15 in Right-side GTY Transceiver Connecvity list the QSFP28
connecons to the XCVU37P FPGA U1 MGTY transceiver banks 135 (QSFP1), 134 (QSFP2), 132
(QSFP3), and 131 (QSFP4).
Figure 23: 28 Gb/s QSFP28 Module Connector
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QSFP28 Connections to Transceiver Banks 67 and 69
The following table lists the QSFP28 module level-shied control signal connecons to
XCVU37P FPGA U1 bank 67 (QSFP1, QSFP4) and bank 69 (QSFP2, QSFP3).
Table 26: XCVU37P U1 to QSFP28 Module Control and I2C Connections
FPGA (U1) Pin
BM24QSFP1_MODSKLL_LSOutput8MODSELL
BN25QSFP1_RESETL_LSOutput9RESETL
BM25QSFP1_MODPRSL_LSOutput27MODPRSL
BP24QSFP1_INTL_LSInput28INTL
BN24QSFP1_LPMODE_LSOutput31LPMODE
U54.13QSFP1_I2C_SDABiDir12SDA
U54.14QSFP1_I2C_SCLOutput11SCL
BN5QSFP2_MODSKLL_LSOutput8MODSELL
BN6QSFP2_RESETL_LSOutput9RESETL
BN7QSFP2_MODPRSL_LSOutput27MODPRSL
BP6QSFP2_INTL_LSInput28INTL
BP7QSFP2_LPMODE_LSOutput31LPMODE
U54.15QSFP2_I2C_SDABiDir12SDA
U54.16QSFP2_I2C_SCLOutput11SCL
BM5QSFP3_MODSKLL_LSOutput8MODSELL
BL6QSFP3_RESETL_LSOutput9RESETL
BM7QSFP3_MODPRSL_LSOutput27MODPRSL
BL7QSFP3_INTL_LSInput28INTL
BN4QSFP3_LPMODE_LSOutput31LPMODE
U54.17QSFP3_I2C_SDABiDir12SDA
U54.18QSFP3_I2C_SCLOutput11SCL
BK23QSFP4_MODSKLL_LSOutput8MODSELL
BK24QSFP4_RESETL_LSOutput9RESETL
BL22QSFP4_MODPRSL_LSOutput27MODPRSL
BH21QSFP4_INTL_LSInput28INTL
BH21QSFP4_LPMODE_LSOutput31LPMODE
U54.19QSFP4_I2C_SDABiDir12SDA
Schematic Net
Name1,
2
FPGA (U1)
Direction
QSFP1 J42 (U1 bank 67)
QSFP2 J39 (U1 bank 69)
QSFP3 J35 (U1 bank 69)
QSFP4 J32 (U1 bank 67)
Module Pin NumModule Pin Name
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Chapter 3: Board Component Descriptions
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Table 26: XCVU37P U1 to QSFP28 Module Control and I2C Connections (cont'd)
FPGA (U1) Pin
U54.20QSFP4_I2C_SCLOutput11SCL
Notes:
1.The QSFP28 connector control signals are level-shifted.
2.The four QSFP28 connector I2C SCL/SDA signals are connected via I2C switch U54 to the I2C1_SCL/SDA bus. See I2C
Bus, Topology, and Switches section
Schematic Net
Name1,
2
FPGA (U1)
Direction
Module Pin NumModule Pin Name
For addionalinformaon about the quad small form factor pluggable (28 Gb/s QSFP28) module,
see the SFF-8663 and SFF-8679 specicaons for the 28 Gb/s QSFP+ on the SNIA Technology
Aliates website.
10/100/1000 Mb/s Tri-speed Ethernet PHY
[Figure 2, callout 22]
The VCU128 evaluaon board uses the TI PHY device DP83867ISRGZ (U62) for Ethernet
communicaons at 10 Mb/s, 100 Mb/s, or 1000 Mb/s. The board supports SGMII mode only.
The PHY connecon to a user-provided Ethernet cable is through RJ-45 connector P2, a Wurth
7499111221A with built-in magnecs and status LEDs. On power-up, or on reset, the PHY is
congured to operate in SGMII mode with PHY address[4:0] = 00011. The following table lists
the FPGA U1 to U62 DP83867ISRGZ Ethernet PHY connecons. This table also shows the net
names for the connecons from the FPGA to the Ethernet PHY. ENET_SGMII_IN correlates with
the SGMII_TX ports in the FPGA design, and ENET_SGMII_OUT correlates with the SGMII_RX
ports.
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VCU128 Board User Guide 71
Table 27: XCVC37P U1 to Ethernet PHY U62 Connections
FPGA
(U1) Pin
BG23ENET_MDIOLVCMOS1817MDIO
BN27ENET_MDCLVCMOS1816MDC
BF22ENET_PDWN_B_I_INT_B_OLVCMOS1844INT_PWDN
BH22ENET_SGMII_IN_NLVCMOS1828TX_D1_SGMII_SIP
BG22ENET_SGMII_IN_PLVCMOS1827TX_D0_SGMII_SIN
BJ21ENET_SGMII_OUT_NLVCMOS1836RX_D3_SGMII_SON
BH21ENET_SGMII_OUT_PLVCMOS1835RX_D2_SGMII_SOP
BK22ENET_SGMII_CLK_NLVCMOS1834RX_D1_SGMII_CON
BK23ENET_SGMII_CLK_PLVCMOS1833RX_D0_SGMII_COP
U65.10GEM3_ENET_RESET_BNA43RESET_B
BP27ENET_COL_GPIOLVCMOS1839GPIO_2
BJ23ENET_CLKOUTLVCMOS1818CLK_OUT
Net NameI/O Standard
DP83867ISRGZ U62
PinName
Chapter 3: Board Component Descriptions
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Ethernet PHY Status LEDs
[Figure 2, callout 23]
Two Ethernet PHY status LEDs are integrated into the metal frame of the P2 RJ-45 connector,
installed on the top edge and towards the back of the VCU128 board. The two PHY status LEDs
are visible within the frame of the RJ45 Ethernet jack as shown in the following gure. As viewed
from the front opening, the le green LED is the link acvity indicator and the right green LED is
the 1000BASE-T link mode indicator.
Figure 24: Ethernet PHY Status LEDs
X21971-112818
A separate discrete LED on top of the board (DS19, near item 38 in Figure 2) indicates link
established. Details about the tri-mode Ethernet MAC core are provided in the Tri-Mode EthernetMAC LogiCORE IP Product Guide (PG051). The TI DP83867ISRGZ data sheet is on the TI website.
I2C Bus, Topology, and Switches
[Figure 2, callout 25, 26]
The VCU128 evaluaon board I2C bus implementaon consists of I2C bus I2C0. The FPGA U1
HP bank 67 (VCCO VCC1V8) and system controller U42 bank 501 are wired to I2C0 via level-shiers. I2C bus I2C0 is routed to a 1-to-4 channel TI PCA9544A bus switch U55 (address 0x75)
and a dual 8-bit port TI TCA6416A IO expander U65 (address 0x20). I2C bus I2C0 is also routed
to a pair of 1-to-8 channel TI TCA9548A bus switches U53 (address 0x74) and U54 (address
0x76). The bus switches can operate at speeds up to 400 kHz. The VCU128 evaluaon board
I2C0 I2C bus topology is shown in the following gures.
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VCU128 Board User Guide 72
Chapter 3: Board Component Descriptions
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IMPORTANT! The TCA9548 U53 and U54 RESET_B pin 3 control signal IIC_MUX_RESET_B is
connected to the I2C0 bus TCA6416A U65 port expander (Addr 0x20) port P05 pin 9. The
IIC_MUX_RESET_B signal must be driven hi-Z or High to enable I2C bus transacons with the target
devices connected to U53 and U54.
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VCU128 Board User Guide 73
X21652-112918
I2C Bus Addresses
User applicaons that communicate with any of the I2C bus I2C0 downstream devices must rst
set up a path to the desired target device through the appropriate bus switch: I2C0 U55
PCA9544A, address 0x75 (0b111101); U53 TCA9548A, address 0x74 (0b1110100), or U54
TCA9548A, address 0x76 (0b111110), respecvely. The following table lists the address for
each bus.
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VCU128 Board User Guide 76
X21972-112918
GPIO Connections to FPGA U1
The following table lists the GPIO connecons to FPGA U1.
Table 30: GPIO Connections to FPGA U1
SendFeedback
Chapter 3: Board Component Descriptions
FPGA (U1) Pin
GPIO LEDs (Active-High) GPIO_LED signals are wired to LED driver U56
BANK 67BH24GPIO_LED_0OutputLVCMOS18DS2
BANK 67BG24GPIO_LED_1OutputLVCMOS18DS3
BANK 67BG25GPIO_LED_2OutputLVCMOS18DS4
BANK 67BF25GPIO_LED_3OutputLVCMOS18DS5
BANK 67BF26GPIO_LED_4OutputLVCMOS18DS6
BANK 67BF27GPIO_LED_5OutputLVCMOS18DS7
BANK 67BG27GPIO_LED_6OutputLVCMOS18DS8
BANK 67BG28GPIO_LED_7OutputLVCMOS18DS9
BANK 64BM29CPU_RESETInputLVCMOS12SW4.3
GPIO SMA pair (applied voltage should not exceed 1.8V)
BANK 67BH27SMA_CLK_OUTPUT_PI/OLVCMOS18J12.1
BANK 67BJ27SMA_CLK_OUTPUT_NI/OLVCMOS18J13.1
Schematic Net
Name
CPU reset pushbutton (active-high)
FPGA (U1)
Direction
I/O StandardDevice
Switches
[Figure 2, callouts 30, 33]
The VCU118 evaluaon board includes a power on/o slide switch and a conguraonpushbuon switch.
• FPGA Program_B SW4, acve-Low (callout 30)
• Power on/o slide switch SW5 (callout 33)
Power On/Off Slide Switch SW5
[Figure 2, callout 33]
The VCU118 board power switch is SW5. Sliding the switch actuator from the o to the on
posion applies 12VDC power from the 6-pin mini-t power input connector J16, normally used
in bench-top applicaons with the provided power adapter. The green LED DS20 illuminates
when the VCU128 board power switch is on. See Board Power System for details on the onboard
power system. The following gure shows the power connector J16, power switch SW5, and
indicator LED DS20.
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VCU128 Board User Guide 77
Chapter 3: Board Component Descriptions
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Figure 27: Power On/Off Switch SW5
X21973-112818
When the VCU128 board is used inside a computer chassis (i.e., plugged in to a PCIe® slot),
power is normally provided from the PC ATX supply 2x4 PCIe power connector. See Installing
the Board in a PC Chassis.
Program_B Pushbutton Switch
[Figure 2, callout 30]
Switch SW2 grounds the XCVU37P FPGA U1 PROGRAM_B pin when pressed. This acon clears
the FPGA conguraon. The FPGA_PROG_B signal is connected to XCVU37P FPGA U1 pin
BB15. See the UltraScale Architecture Conguraon User Guide (UG570) for further conguraon
details. The following gure shows SW2.
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VCU128 Board User Guide 78
Chapter 3: Board Component Descriptions
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Figure 28: Program_B Pushbutton Switch SW2
X21974-112918
FPGA Mezzanine Card Interface
[Figure 2, callout 31]
The VCU128 evaluaon board supports the VITA 57.4 FPGA mezzanine card plus (FMC+ or
FMCP) specicaon by providing a subset implementaon of the high pin count connector at J18
(HSPC, high serial pin connector). The VITA 57.4 standard extends the VITA 57.1 FMC standard
by specifying two new connectors that increase the number of mul-gigabit interfaces from 10
to 24. Also, there is an oponal extension connector (the high serial pin connector extension, or
HSPCe) to boost pin-count by 80 posions, arranged in a 4x20 array. The VCU128 board does
not implement the high serial pin connector/HSPCe extension.
FMC+ connectors use a 14 x 40 form factor, populated with 560 pins. The connector is keyed so
that a mezzanine card, when installed on the VCU128 evaluaon board, faces away from the
board.
J18 FMC+/FMCP Connectors
This secon describes the J18 FMC+/FMCP connectors.
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VCU128 Board User Guide 79
• Samtec SEAF series, 1.27 mm (0.050 in) pitch. Mates with SEAM series connector. More
informaon about SEAF series connectors is available on the Samtec website.
• The 560-pin FMC+ connector dened by the FMC specicaon (see Appendix A: VITA 57.4
FMCP Connector Pinouts) provides connecvity for up to:
○160 single-ended or 80 dierenaluser-dened signals
Chapter 3: Board Component Descriptions
SendFeedback
○24 transceiver dierenal pairs
○6 transceiver dierenal clocks
○4 dierenal clocks
○239 ground and 17 power connecons
FMCP Connector J18
[Figure 2, callout 33]
The HSPC connector at J18 implements a subset of the full FMCP connecvity:
• 68 single-ended or 34 dierenaluser-dened pairs (full LA-bus: LA[00:33])
• 24 transceiver dierenal pairs
• 6 transceiver dierenal clocks
• 2 dierenal clocks
• 239 ground and 14 power connecons
UG1302 (v1.0) December 21, 2018www.xilinx.com
VCU128 Board User Guide 80
Chapter 3: Board Component Descriptions
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J18 VITA 57.4 FMCP HSCP Connections
The FMCP J18 connecons to FPGA U1 are listed in the following table. The net names shown
in the table are connected to FMCP HSCP J18 pins.
UG1302 (v1.0) December 21, 2018www.xilinx.com
VCU128 Board User Guide 85
More informaon about the VITA 57.4 FMC+ specicaon is available on the VITA FMC
Markeng Alliance website.
Board Power System
[Figure 2, callout 34]
The VCU128 board has an Intersil power system. The following gure shows the VCU128 board
power system block diagram.
Chapter 3: Board Component Descriptions
SendFeedback
Figure 29: Power System Block Diagram
12V Vin
252W (PCIe
brick option)
*Wattage calculations based on XPE requirements plus 25%
UTIL_3V3
3.3V @ 20A
ISL68301 +
ISL919227B
UTIL_5V0
5.0V @ 20A
ISL68301 +
ISL919227B
overhead for soft IP flexibility
DDR4_VTERM_0V6
0.6V @ 3A
TPS51200
RLD3_VTERM_0V6
0.6V @ 3A
TPS51200
62W
VCC1V8
1.8V @ 6A
ISL91302B (A+B)
VADJ
1.8V @ 6A
ISL91302B (C+D)
SYS_1V8
1.8V @ 1A
ISL91211 (A)
MGTVCCAUX
1.8V @ 1A
ISL91211A (B)
MGTAVCC
0.9V @ 10A
ISL91211A (C+D)
QDR4_VDDQ_1V2
1.2V @ 6A
ISL91302 (A+B)
UTIL_1V30
1.30V @ 6A
ISL91302B (C+D)
16W
11W
12W
Current
Shunt
Current
Shunt
Current
Shunt
VCCHBM
1.2V @ 25A
ISL68301 +
ISL919227B
MGTAVTT
1.2V @ 20A
ISL68301 +
ISL919227B
VCCINT
0.85V @ 125A
ISL68127 +
ISL919227 (5)
VCCBRAM
0.85V @ 30A
ISL68127 +
ISL919227 (1)
22W
18W
103W
DDR4_VDDQ_1V2
1.2V @ 3A
ISL91302 (A+B+D)
RLD3_VDDQ_1V2
1.2V @ 10A
ISL91302 (C)
UTIL_1V35
1.35V @ 10A
ISL91302B (A+B+D)
SYS_1V0
1.0V @ 2A
ISL91302B (C)
VCCAUX_HBM
2.5V @ 1.5A
ISL80019
11W
10W
2W
Current
Shunt
Current
Shunt
Current
Shunt
Current
Shunt
Current
Shunt
X21654-121718
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VCU128 Board User Guide 86
Chapter 3: Board Component Descriptions
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Onboard Power System Devices
The VCU128 evaluaon board uses programmable power regulators from Intersil Corporaon to
supply the core and auxiliary voltages listed in the following table.
1.Jumper selectable at 3-pin header J25: 1-2=0.85V (default); 2-3=0.72V.
Rail NameRegulator TypeU#
Programmable Regulators and INA226 Map
Programmable Regulators
Non-I2C Regulators
Vout
(V)
0.85
0.85
-1.8
Iout
Range
(A)
1250X65U840x40
1
300X65U860x41
1
4.5 - 60x63NANA
I2C
Address
U#
INA226
I2C
Address
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VCU128 Board User Guide 87
Documentaon describing the programming of the Intersil power controllers is available on the
Intersil website (see References). The PCB layout and power system design meet the
recommended criteria described in the UltraScale Architecture PCB Design User Guide (UG583).
Chapter 3: Board Component Descriptions
SendFeedback
FMCP HSPC Connector J18 VADJ Power Rail
The VCU128 evaluaon board implements the ANSI/VITA 57.4 IPMI support funconality. The
power control of the VADJ power rail is managed by the U42 system controller. This rail powers
both the FMCP HSPC (J18) VADJ pins, as well as XCVU37P U1 HP banks 71 and 72 (see I/O
Voltage Rails). The valid values of the VADJ rail are 1.2V, 1.5V, and 1.8V.
At power on, the system controller detects if an FMC module is connected to FMCP J18:
• If no FMC card is aached to the FMC port, the VADJ voltage is set to 0V
•
When an FMC card is aached, its IIC EEPROM is read to nd a VADJ voltage supported by
both the VCU128 board and the FMC module, within the available choices of 1.2V, 1.5V, 1.8V,
and 0.0V
•
If no valid informaon is found in the IIC EEPROM, the VADJ rail is set to 0V
The system controller user interface allows the FMC IPMI roune to be overridden and an
explicit value to be set for the VADJ rail.
Monitoring Voltage and Current
[Figure 2, callout 35]
Voltage and current monitoring and control for the Intersil power system is available through
either the VCU128 system controller or the Intersil PowerNavigator soware GUI. The VCU128
system controller is a simple and convenient way to monitor the voltage and current values for
the power rails listed in the following table. The Intersil programmable power controllers listed in
the table can also be accessed through the 2x3 male pin header J1. Using this connector requires
the Intersil ZLUSBEVAL3Z USB to PMBus adapter. This adapter cable can be ordered from the
Intersil website (see References). The associated Intersil PowerNavigator soware GUI can be
downloaded from the Intersil website. The Intersil programmable controller and INA226 power
monitor I2C bus mapping is shown in the following table.
Table 33: Programmable Controller and INA226 Power Monitor I2C Bus Mapping
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VCU128 Board User Guide 89
Cooling Fan
The XCVU37P FPGA U1 cooling fan connector is shown in the following gure. The VCU128 fan
circuit uses a Maxim MAX6643 fan controller that autonomously monitors the FPGA die
temperature pins DXP and DXN. The fan circuit is set up to increase fan speed as the FPGA
temperature increases.
Note: At inial power on, it is normal for the fan controller to energize at full speed for a few seconds
System Controller
SendFeedback
Chapter 3: Board Component Descriptions
Figure 30: Cooling Fan Circuit
X21975-112818
[Figure 2, callout 8]
The VCU128 board includes an onboard Zynq®-7000 SoC U42 as the system controller. A host
PC resident graphical user interface for the system controller (SCUI) is provided on the VCU128
website. The SCUI can be used to query and control select programmable features such as
clocks, FMC funconality, and power systems. The VCU128 evaluaon kit website also includes
a VCU128 System Controller Tutorial (XTP534) and the VCU128 Soware Install and Board SetupTutorial (XTP535). A summary of the steps is as follows.
1. Ensure the Silicon Labs VCP USB-UART drivers are installed on the host PC. See the SiliconLabs CP210x USB-to-UART Installaon Guide (UG1033).
2. Download the SCUI host PC applicaon.
3. Connect the micro-B USB cable between the VCU128 board USB-UART connector (J2) and
the host PC.
4. Power-cycle the VCU128 board.
5. Launch the SCUI as shown in the following example.
UG1302 (v1.0) December 21, 2018www.xilinx.com
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Chapter 3: Board Component Descriptions
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X21976-112818
See the VCU128 System Controller Tutorial (XTP534) and the VCU128 Soware Install and Board
Setup Tutorial (XTP535) for more informaon on installing and using the System Controller ulity.
Configuration Options
[Figure 2, callout 36]
The VCU128 board supports two of the seven UltraScale™ FPGA conguraon modes.
• Master SPI using the onboard 2 Gbit Quad SPI ash memory
• JTAG using:
○USB JTAG conguraon port J2 (FTDI FT4232H bridge U8)
○Xilinx
Each conguraon interface corresponds to one or more conguraon modes and bus widths as
listed in the following table. The mode switches M2, M1, and M0 are on 4-pole DIP SW1
posions 2, 3, and 4, respecvely. The FPGA default mode seng M[2:0] = 001, selecng the
master SPI conguraon mode.
Table 34: Board FPGA Configuration Modes
Configuration Mode
®
plaorm cable 2 mm, keyed at cable header (J4)
SW16 DIP Switch
Settings (M[2:0])
Master SPI1x1, x2, x4Output
JTAG101x1Not applicable
Bus WidthCCLK Direction
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VCU128 Board User Guide 91
The following gure shows mode switch SW1.
Chapter 3: Board Component Descriptions
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Figure 31: SW1 JTAG Settings
X21977-112818
The mode pins sengs on SW1 determine if the Quad SPI ash is used for conguring the
FPGA. DIP switch SW1 also includes a system controller enable switch in posion 1. See the
UltraScale Architecture Conguraon User Guide (UG570) for further details on conguraon
modes.
UG1302 (v1.0) December 21, 2018www.xilinx.com
VCU128 Board User Guide 92
Appendix A
SendFeedback
VITA 57.4 FMCP Connector Pinouts
Overview
The following gure shows the pinout of the FPGA mezzanine card plus (FMCP) connector J18
dened by the VITA 57.4 FMC specicaon. For a descripon of how the VCU128 evaluaonboard implements the FMCP specicaon, see FPGA Mezzanine Card Interface.
Figure 32: FMCP Connector Pinouts
UG1302 (v1.0) December 21, 2018www.xilinx.com
VCU128 Board User Guide 93
X21978-112818
Xilinx Constraints File
SendFeedback
Overview
The Xilinx® design constraints (XDC) le template for the VCU128 board provides for designs
targeng the VCU128 evaluaon board. Net names in the constraints listed correlate with net
names on the latest VCU128 evaluaon board schemac.Idenfy the appropriate pins and
replace the net names with the net names in the user RTL. See the Vivado Design Suite User Guide:Using Constraints (UG903) for more informaon.
Appendix B: Xilinx Constraints File
Appendix B
The FMCP connector J18 (HSCP) is connected to 1.8V (nominal) VADJ banks 70 and 71. Because
dierent FMC cards implement dierent circuitry, the FMC bank I/O standards must be uniquely
dened by each customer.
IMPORTANT
! See VCU128 board documentaon for the XDC le.
UG1302 (v1.0) December 21, 2018www.xilinx.com
VCU128 Board User Guide 94
Regulatory and Compliance
SendFeedback
Information
Overview
This product is designed and tested to conform to the European Union direcves and standards
described in this secon.
VCU128 Evaluaon Kit - Master Answer Record 71849
For Technical Support, open a Support Service Request.
EN standards are maintained by the European Commiee for Electrotechnical Standardizaon
(CENELEC). IEC standards are maintained by the Internaonal Electrotechnical Commission (IEC).
Electromagnetic Compatibility
EN 55022:2010, Informaon Technology Equipment Radio Disturbance Characteriscs – Limits and
Methods of Measurement
EN 55024:2010, Informaon Technology Equipment Immunity Characteriscs – Limits and Methods
of Measurement
UG1302 (v1.0) December 21, 2018www.xilinx.com
VCU128 Board User Guide 95
Appendix C: Regulatory and Compliance Information
SendFeedback
This is a Class A product. In a domesc environment, this product can cause radio interference, in
which case the user might be required to take adequate measures.
Safety
IEC 60950-1:2005, Informaon technology equipment – Safety, Part 1: General requirements
EN 60950-1:2006, Informaon technology equipment – Safety, Part 1: General requirements
Compliance Markings
In August of 2005, the European Union (EU) implemented the EU WEEE Directive
2002/96/EC and later the WEEE Recast Directive 2012/19/EU requiring Producers
of electronic and electrical equipment (EEE) to manage and finance the collection,
reuse, recycling and to appropriately treat WEEE that the Producer places on the
EU market after August 13, 2005. The goal of this directive is to minimize the
volume of electrical and electronic waste disposal and to encourage re-use and
recycling at the end of life.
Xilinx has met its national obligations to the EU WEEE Directive by registering in
those countries to which Xilinx is an importer. Xilinx has also elected to join WEEE
Compliance Schemes in some countries to help manage customer returns at
end-of-life.
If you have purchased Xilinx-branded electrical or electronic products in the EU
and are intending to discard these products at the end of their useful life, please
do not dispose of them with your other household or municipal waste. Xilinx has
labeled its branded electronic products with the WEEE Symbol to alert our
customers that products bearing this label should not be disposed of in a landfill
or with municipal or household waste in the EU.
UG1302 (v1.0) December 21, 2018www.xilinx.com
VCU128 Board User Guide 96
This product complies with Directive 2002/95/EC on the restriction of hazardous
substances (RoHS) in electrical and electronic equipment.
This product complies with CE Directives 2006/95/EC, Low Voltage Directive (LVD)
and 2004/108/EC, Electromagnetic Compatibility (EMC) Directive.
Appendix D
SendFeedback
Additional Resources and Legal
Notices
Xilinx Resources
For support resources such as Answers, Documentaon, Downloads, and Forums, see Xilinx
Support.
Documentation Navigator and Design
Hubs
Xilinx® Documentaon Navigator (DocNav) provides access to Xilinx documents, videos, and
support resources, which you can lter and search to ndinformaon. To open DocNav:
• From the Vivado® IDE, select Help → Documentaon and Tutorials.
• On Windows, select Start → All Programs → Xilinx Design Tools → DocNav.
• At the Linux command prompt, enter docnav.
Xilinx Design Hubs provide links to documentaon organized by design tasks and other topics,
which you can use to learn key concepts and address frequently asked quesons. To access the
Design Hubs:
• In DocNav, click the Design Hubs View tab.
• On the Xilinx website, see the Design Hubs page.
Note: For more informaon on DocNav, see the Documentaon Navigator page on the Xilinx website.
UG1302 (v1.0) December 21, 2018www.xilinx.com
VCU128 Board User Guide 97
Appendix D: Additional Resources and Legal Notices
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References
The most up to date informaon related to the VCU128 board and its documentaon is available
on the following websites.
VCU128 Evaluaon Kit
VCU128 Evaluaon Kit - Master Answer Record 71849
These documents provide supplemental material useful with this guide:
1. Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteriscs (DS923)
2. UltraScale Architecture Conguraon User Guide (UG570)
3. UltraScale Architecture SelectIO Resources User Guide (UG571)
4. UltraScale Architecture-Based FPGAs Memory IP LogiCORE IP Product Guide (PG150)
5. UltraScale Architecture Clocking Resources User Guide (UG572)
6. UltraScale Architecture GTY Transceivers User Guide (UG578)
7. UltraScale FPGAs Transceivers Wizard LogiCORE IP Product Guide (PG182)
8. UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156)
9. Tri-Mode Ethernet MAC LogiCORE IP Product Guide (PG051)
10. AXI UART Lite LogiCORE IP Product Guide (PG142)
11. Vivado Design Suite User Guide: Using Constraints (UG903)
12. UltraScale Architecture PCB Design User Guide (UG583)
(FPGA Mezzanine Card (FMC) VITA 57.4 specicaon) This standard extends the VITA 57.1 FMC
standard by specifying two new connectors that enable addional Gigabit Transceiver interfaces
that run at up to 28 Gb/s. It also describes FMC+ I/O modules that support this enhanced version
of the FMC electro-mechanical standard. This is between the front panel I/O, on the mezzanine
module, and an FPGA processing device on the carrier card, which accepts the mezzanine module.
Addional signals to support backplane reference clock and synchronizaon have been added. The
VITA 57.4 specicaon is backwards compable in that a VITA 57.4 carrier card can sll support a
VITA 57 FMC.
29. Intersil Corporaon (a wholly owned subsidiary of Renesas Electronics Corporaon)
The Intersil PowerNavigator soware is available at: hps://www.intersil.com/en/products/power-
The Intersil USB to PMBUS ZLUSBEVAL3Z Dongle is available at: hps://www.intersil.com/en/
tools/reference-designs/zlusbeval3z.html
ATX Power Supply Adapter Cable
The Xilinx ATX cable part number 2600304 is manufactured by Sourcegate Technologies and is
equivalent to the Sourcegate Technologies part number AZCBL-WH-11009.
Sourcegate only manufactures the latest revision, which is currently A4. To order, contact Aries
Ang, aries.ang@sourcegate.net, +65 6483 2878 for price and availability. This is a custom cable
and cannot be ordered from the Sourcegate website.
UG1302 (v1.0) December 21, 2018www.xilinx.com
VCU128 Board User Guide 99
Appendix D: Additional Resources and Legal Notices
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Please Read: Important Legal Notices
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