Xilinx VCU118 User Manual

VCU118 Evaluation Board

User Guide

UG1224 (v1.0) December 15, 2016

Revision History

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The following table shows the revision history for this document.

Date Version Revision

12/15/2016 1.0 Initial Xilinx release.

VCU118 Board User Guide 2

UG1224 (v1.0) December 15, 2016

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Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Chapter 1: Introduction

Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Board Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Board Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Environmental . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Operating Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Chapter 2: Board Setup and Configuration

Board Component Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Default Switch and Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Installing the VCU118 Board in a PC Chassis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

FPGA Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Chapter 3: Board Component Descriptions

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Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Component Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Virtex UltraScale+ XCVU9P-L2FLGA2104 Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

DDR4 Component Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

RLD3 Component Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Linear BPI Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Micro-SD Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Digilent USB JTAG Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

FMC Connector JTAG Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Programmable User Clock 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Programmable User Clock 2 (QSFP Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

250 MHz Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

User SMA Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Jitter Attenuated Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

GTY Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

PCI Express Endpoint Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

28 Gb/s QSFP+ Module Connectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

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FireFly Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

10/100/1000 Mb/s Tri-Speed Ethernet PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

Ethernet PHY Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Dual USB-to-UART Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

I2C Bus, Topology, and Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

Status and User LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

User I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

User GPIO LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

User Pushbuttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

CPU Reset Pushbutton . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

GPIO DIP Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

User Pmod GPIO Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

FPGA Mezzanine Card Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

VCU118 Board Power System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106

FMC VADJ_1V8 Power Rail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108

Monitoring Voltage and Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108

Cooling Fan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110

System Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

Configuration Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112

Appendix A: VITA 57.1 and 57.4 FMC Connector Pinouts

Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Appendix B: Master Constraints File Listing

Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

VCU118 Board Constraints File Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Appendix C: Regulatory and Compliance Information

Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Declaration of Conformity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Electromagnetic Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161

Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161

Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Appendix D: Additional Resources and Legal Notices

Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

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Introduction

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Overview

The VCU118 evaluation board for the Xilinx® Virtex® UltraScale+™ FPGA provides a hardware environment for developing and evaluating designs targeting the UltraScale+ XCVU9P-L2FLGA2104 device. The VCU118 evaluation board provides features common to many evaluation systems, including:

• DDR4 and RLD3 component memory

• Dual small form-factor pluggable (QSFP+) connector

• Sixteen-lane PCI Express

interface

Chapter 1

• Ethernet PHY

• General purpose I/O

•Two UART interfaces

™

• FireFly

Other features can be supported using modules compatible with the VITA-57.1 FPGA mezzanine card (FMC) and VITA-57.4 FPGA mezzanine card plus high serial pin (FMC+ HSPC) connectors on the VCU118 board.

Optical x4 28 G connector

Additional Resources

See Appendix D, Additional Resources and Legal Notices for references to documents, files, and resources relevant to the VCU118 evaluation board.

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X-Ref Target - Figure 1-1

X18010-100416

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Chapter 1: Introduction

Block Diagram

A block diagram of the VCU118 evaluation board is shown in Figure 1-1.

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Figure 1-1: VCU118 Evaluation Board Block Diagram

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Chapter 1: Introduction

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Board Features

The VCU118 evaluation board features are listed here. Detailed information for each feature is provided in Component Descriptions in Chapter 3.

• Virtex UltraScale+ XCVU9P-L2FLGA2104 device

•Zynq

• Two 2.5 GB DDR4 80-bit component memory interfaces (five [256 Mb x 16] devices each)

• 288 MB 72-bit RLD3 memory interface comprised of two 1.125 Gb 36-bit devices

• 1 Gb (128 MB) linear x16 BPI flash memory

• USB JTAG interface using a Digilent module with separate micro-B USB connector

• Clock sources:

-7000 AP SoC XC7Z010 based system controller

Si5335A quad clock generator

Three Si570 I2C programmable LVDS clock generators

One SG5032 fixed 250 MHz LVDS clock generator

Si5328B clock multiplier and jitter attenuator for QSFP

Subminiature version A (SMA) connectors (differential)

• 52 GTY transceivers (13 Quads)

FMC+ HSPC connector (twenty-four GTY transceivers)

2x28 Gb/s QSFP+ connectors (eight GTY transceivers)

Samtec Firefly connector (four GTY transceiver)

PCIe 16-lane edge connector (sixteen GTY transceivers)

• PCI Express endpoint connectivity

Gen1 16-lane (x16)

Gen2 16-lane (x16)

Gen3 8-lane (x8)

• Ethernet PHY SGMII interface with RJ-45 connector

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• Dual USB-to-UART bridge with micro-B USB connector

C bus

•I

•Status LEDs

• User I/O (4-pole DIP switch, 6 each push-button switches, 8 x LED)

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Chapter 1: Introduction

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• Two Pmod 2x6 connectors (one male pin header, one right-angle receptacle)

• VITA 57.4 FMC+ HSPC connector J22

•VITA 57.1 FMC HPC1 connector J2

• Power management with PMBus voltage monitoring through Maxim power controllers and GUI

• 10-bit 0.2 MSPS SYSMON analog-to-digital front end

• Configuration options:

BPI linear flash memory

Digilent USB configuration module

Platform cable USB II interface 2x7 2 mm connector

Board Specifications

Dimensions

Height: 6.927 inch (17.59 cm)

Thickness (±5%): 0.061 inch (0.1549 cm)

Length: 9.5 inch (24.13 cm)

Note:

IMPORTANT: The VCU118 board height exceeds the standard 4.376 inch (11.15 cm) height of a PCI

Express® card.

A 3D model of this board is not available.

Environmental

Temp erature

Operating: 0°C to +45°C

Storage: -25°C to +60°C

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Humidity

10% to 90% non-condensing

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Operating Voltage

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Chapter 1: Introduction

+12 V

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Board Setup and Configuration

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Board Component Location

Figure 2-1 shows the VCU118 board component locations. Each numbered component

shown in the figure is keyed to Table 2-1. Table 2-1 identifies the components, references the respective schematic page numbers, and links to a detailed functional description of the components and board features in Chapter 3.

IMPORTANT: Figure 2-1 is for visual reference only and might not reflect the current revision of the

board.

CAUTION! The VCU118 board can be damaged by electrostatic discharge (ESD). Follow standard ESD

prevention measures when handling the board.

Chapter 2

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X-Ref Target - Figure 2-1

Round callout references a component on the front side of the board

Square callout references a component on the backside side of the board

13 12 35

6 10

X18022-102616

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Chapter 2: Board Setup and Configuration

Table 2-1: VCU118 Board Component Descriptions

Callout Feature Notes

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Virtex UltraScale+ XCVU9P-L2FLGA2104

Device, (with fan-sink on soldered FPGA)

GTY transceivers, Right Side Quads (six

quads)

GTY transceivers, Left Side Quads (seven

quads)

DDR4 Component Memory, two 80-bit DDR4

component memory I/F, C1 (U60-U64)

Figure 2-1: VCU118 Evaluation Board Components

(bottom) and C2 (U135-U139) (top)

RLD3 Component Memory, RLD3 72-bit

component memory I/F C3 (U141-U142)

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XCVU9P-L2FLGA2104E Cofan 30-5530-03

Embedded within FPGA U1 14-15

Embedded within FPGA U1 16-17

C1: 5 x Micron MT40A256M16GE-075E, C2: 5 x Micron MT40A256M16GE-075E

Micron MT44K32M36RB-083F 31-32

Schematic

Page Number

25-27,

28-30

Table 2-1: VCU118 Board Component Descriptions (Cont’d)

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Chapter 2: Board Setup and Configuration

Callout Feature Notes

Linear BPI Flash Memory, BPI 16-bit

configuration memory 1 Gb (U133)

Micro-SD Card Interface, (bottom)

Micro-SD card interface connector (J83)

Digilent USB JTAG Module, USB JTAG micro-B

connector (J106)

Digilent USB JTAG Module (U115), with

micro-B connector

Clock Generation, multi-output clock

generator, SYSCLK and other clocks, 1.8V LVDS (U122)

System Clock, programmable user clock

Si570_0, I LVDS (U18) (bottom) with 1-to-2 LVDS MUX/buffer (U157) (top)

Programmable User Clock 1, programmable

user clock Si570_1, I clock, 3.3V LVDS (U32) with 1-to-2 LVDS MUX/buffer (U104)

C programmable user clock, 3.3V

C programmable user

Micron MT28GU01GAAA1EGC-0SIT 54

Molex 5025700893 49

Hirose ZX62D-AB-5P8 24

Digilent JTAG-SMT2-NC 24

SI5335A-B02436-GM, 4 outputs: 300 MHz, 125 MHz, 90 MHz, 33.33 MHz

Silicon Labs SI570BAB0000544DG (default 156.250 MHz) with Si53340 MUX/buffer

Schematic

Page Number

Programmable User Clock 2 (QSFP Clock),

15 User SMA Clock pair J34(P)/J35(N) Rosenberger 32K10K-400L5 45

programmable user clock Si570_2, I programmable user clock, 3.3V LVDS (U38)

250 MHz Clock, fixed SG5032 250 MHz user

clock, 3.3V LVDS (U14) (bottom) with 1-to-2 LVDS MUX/buffer (U21) (bottom)

Jitter Attenuated Clock, jitter attenuated

QSFP clock (U57)

PCI Express Endpoint Connectivity, PCI

Express connector (P1)

Two 28 Gb/s QSFP+ Module Connectors, QSFP1 (U145), QSFP2 (U123)

10/100/1000 Mb/s Tri-Speed Ethernet PHY

with RJ45, SGMII mode only, (U7, J10)

Ethernet PHY Status LEDs, LEDs are

integrated into J10 bezel

Dual USB-to-UART Bridge, bridge device

(U34) with mini-B connector (J4)

I2C Bus, Topology, and Switches, I

C bus MUX (U28) (bottom)

I2C Bus, Topology, and Switches, I

C bus MUX (U80)

C bus,

Silicon Labs SI570BAB0000544DG (default 156.250 MHz)

Epson SG5032VAN_250.000000M-KEGA3 with ICS85411AMLF 1-to-2 buffer

Silicon Labs SI5328B 51

8-lane card edge connector 43

Amphenol FS1-Z38-20Z6-10 50

TI DP83867ISRGZ with Wurth 7499111221A RJ45 (with magnetics)

Wurth 7499111221A RJ45 integrated status LEDs

Silicon Labs CP2105-F01-GM bridge, Hirose ZX62D-AB-5P8 connector

TI TCA9548APWR 58

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Table 2-1: VCU118 Board Component Descriptions (Cont’d)

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Chapter 2: Board Setup and Configuration

Callout Feature Notes

30 Switches, power on/off slide switch SW1 C&K 1201M2S3AQE2 59

User GPIO LEDs (DS6-DS10, DS12, DS13,

DS18)

User Pushbuttons, (SW10, SW17, SW9, SW6,

SW7), CPU reset pushbutton (SW5) all active-High

GPIO DIP Switch, GPIO DIP switch (SW12)

(bottom)

Program_B Pushbutton Switch, program_B

pushbutton switch, FPGA PROG pushbutton (SW4)

VCU118 XC7Z010 system controller, mode switch DIP, switch (SW15)

User Pmod GPIO Headers, (J52 right-angle

receptacle, J53 male pin header) (top) with level shifters (U41,U42) (bottom)

VCU118 Board Power System, power

management system (top and bottom)

Monitoring Voltage and Current, power

management voltage and current sensing

GPIO LEDs, green 0603 Lumex SML-LX0603GW-TR

E-Switch TL3301EF100QG (north, south, east, west, center pattern)

4-pole CTS 218-4LPSTRF 55

E-Switch TL3301EF100QG 55

4-pole CTS 218-4LPSTRF 49

J52 Sullins PPPC062LJBN-RC, J53 Sullins PBC36DAAN, NXP NVT2008PW

Maxim MAX20751E and MAX15301 dig-ital P.O.L. controllers

TI Current and Power Monitor INA226AIDGS

Page Number

Schematic

60-75

60-67

33 GTY Transceivers, FMCP HSPC connector J22 Samtec ASP_184329_01 34-38

34 FMC HPC1 Connector J2 Samtec ASP_134486_01 39-42

41 FireFly Connector, signal and power pair (J6)

Notes:

1. The VCU118 board schematics are available for download. See the VCU118 Evaluation Kit.

2. The VCU118 board jumper header locations are shown in Figure 2-2.

Configuration Options, FPGA U1

configuration mode DIP switch, (SW16)

System Controller, VCU118 Zynq-7000 AP

SoC XC7Z010CLG225 (U111)

Monitoring Voltage and Current, VCU118

board power system 2x8 shrouded PMBus connector (J39)

Digilent USB JTAG Module, USB JTAG

module, shrouded JTAG cable connector (J3)

Power On/Off Slide Switch SW1, power input

connector (J15)

PCI Express Endpoint Connectivity, lane

width select header, (J7)

4-pole CTS 218-4LPSTRF 3

XC7Z010CLG225 46-49

ASSMAN AWHW16G-0202 59

2x7 2 mm Molex 87832-1420 24

2x6 Molex-39-30-1060 59

Samtec Signal: UEC5-019-2-H-D-RA-1, Samtec Power: UCC8-10-1-H-S-1-A

2x4 0.1 inch male header Sullins PBC36DAAN

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Default Switch and Jumper Settings

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Switches

Default switch settings are listed in Table 2-2. Switch locations are shown in Figure 2-1.

Table 2-2 also references the respective schematic page numbers.

Table 2-2: Default Switch Settings

Chapter 2: Board Setup and Configuration

Switch Function Default Comments

SW1 SPST slide switch OFF Board shipped with power switch off 30 59

SW12 4-pole GPIO 0000 Positions 1-4, GPIO 26 55

SW15 4-pole configuration 0000

SW16 4-pole configuration 0101

Notes:

1. DIP switches are active-High (connected net is pulled High when DIP switch is closed).

Positions 1-4, Zynq-7000 AP SoC System Controller U111

Position 1, System Controller Enable Positions 2-4, FPGA U1 mode M[2:0]

Figure 2-1

Callout

28 49

35 3

Schematic

Page

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X-Ref Target - Figure 2-2

X18026-100416

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Chapter 2: Board Setup and Configuration

Jumpers

Figure 2-2 shows the VCU118 board jumper header locations. Each numbered component

shown in the figure is keyed to Table 2-3, which identifies the default jumper settings and references the respective schematic page numbers.

Table 2-3: Default Jumper Settings

Jumper Function Default Comments

J12 Maxim regulator inhibit Off Used when programming PWR. SYS. 5 59

J14 U30 VADJ_1V8 enable Off

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Figure 2-2: VCU118 Board Header Jumper Locations

J5 Power on reset (POR) override 2-3 U1 POR_OVERRIDE pin AG12 to GND 1 3

J7 PCIe lane size select 7-8 16-lane configuration 2 43

J8 SYSCLK source select Off SI5335A 300 MHz default 3 44

J9 USER/MGT_SI570 source select Off SI570 U32 156.250 MHz 4 45

Input to U25 AND, VADJ_1V8 enabled

Figure 2-2

Schematic

Callout

663

Page

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Table 2-3: Default Jumper Settings (Cont’d)

X17987-100416

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Chapter 2: Board Setup and Configuration

Jumper Function Default Comments

J29 BPI Flash A25 source select 1-2 A25 connected to FPGA U1 pin BE17 7 54

J110

Zynq-7000 AP SoC System

Controller U111 QSPI_IO3

Off

QSPI_IO3 P/U w/20K (On = P/D to GND)

Figure 2-2

Callout

847

Installing the VCU118 Board in a PC Chassis

Installation of the VCU118 board inside a computer chassis is required when developing or testing PCI Express® functionality.

When the VCU118 board is used inside a computer chassis (that is, plugged in to the PCIe® slot), power is provided from the ATX power supply 4-pin peripheral connector through the ATX adapter cable (Figure 2-3) to J15 on the VCU118 board. The Xilinx part number for this cable is 2600304. See [Ref 29] for ordering information.

X-Ref Target - Figure 2-3

Schematic

Page

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Figure 2-3: ATX Power Supply Adapter Cable

To install the VCU118 board in a PC chassis:

1. On the VCU118 board, remove the six screws retaining the six rubber feet with their standoffs, and the PCIe bracket. Reinstall the PCIe bracket using two of the previously removed screws.

2. Power down the host computer and remove the power cord from the PC.

3. Open the PC chassis following the instructions provided with the PC.

4. Select a vacant PCIe expansion slot and remove the expansion cover (at the back of the chassis) by removing the screws on the top and bottom of the cover.

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5. The VCU118 board requires three adjacent PCIe slots. The VCU118 board has a large cooling fan that exceeds the PCIe top side component height restriction and has several spring loaded screws on the back side of the board. Ensure the slots closest to the front and back of the board are free of obstructions.

6. Plug the VCU118 board into the center of the three open slots.

7. Install the top mounting bracket screw into the PC expansion cover retainer bracket to secure the VCU118 board in its slot.

8. Connect the ATX power supply to the VCU118 board using the ATX power supply adapter cable as shown in Figure 2-3.

a. Plug the 6-pin 2 x 3 Molex connector on the adapter cable into J15 on the VCU118

board.

b. Plug the 4-pin 1 x 4 peripheral power connector from the ATX power supply into the

4-pin adapter cable connector.

CAUTION! Do NOT plug a PC ATX power supply 6-pin connector into J15 on the VCU118 evaluation

board. The ATX 6-pin connector has a different pin out than J15. Connecting an ATX 6-pin connector into J15 damages the VCU118 evaluation board and voids the board warranty.

9. Slide the VCU118 board power switch SW1 to the ON position. The PC can now be powered on.

FPGA Configuration

The VCU118 board supports two of the seven UltraScale FPGA configuration modes:

• Master BPI using the onboard linear BPI flash memory

•JTAG using:

USB JTAG configuration port (Digilent module U115)

Platform cable USB 2.0, 2 mm, keyed flat cable header (J3)

Each configuration interface corresponds to one or more configuration modes and bus widths, as listed in Table 2-4. The mode switches M2, M1, and M0 are on SW16 positions 2, 3, and 4, respectively. The FPGA default mode setting M[2:0] = 101 selects the JTAG configuration mode.

Table 2-4: Configuration Modes

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Configuration Mode

Master BPI 010 x8,x16 Output

JTAG 101 x1 Not Applicable

SW16 DIP Switch

Settings M[2:0]

Bus Width CCLK Direction

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Chapter 2: Board Setup and Configuration

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For complete details on configuring the FPGA, see UltraScale Architecture Configuration User Guide (UG570) [Ref 2].

Figure 2-4 shows the configuration mode DIP switch SW16 default switch positions.

X-Ref Target - Figure 2-4

Figure 2-4: SW16 Default Settings

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Board Component Descriptions

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Overview

This chapter provides a detailed functional description of the board’s components and features. Table 2-1, page 11 identifies the components, references the respective schematic page numbers, and links to the corresponding detailed functional description in this chapter. Component locations are shown in Figure 2-1, page 11.

Component Descriptions

Chapter 3

Virtex UltraScale+ XCVU9P-L2FLGA2104 Device

[Figure 2-1, callout 1]

The VCU118 board is populated with the Virtex UltraScale+ XCVU9P-L2FLGA2104 device. For more information on Virtex UltraScale+ FPGAs, see Virtex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics (DS923) [Ref 1].

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Chapter 3: Board Component Descriptions

To VBATT pin

U1.AT11

X18008-100416

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Encryption Key Battery Backup Circuit

The XCVU9P device U1 implements bitstream encryption key technology. The VCU118 board provides the encryption key backup battery circuit shown in Figure 3-1. The Seiko TS518FE rechargeable 1.5V lithium button-type battery B1 is soldered to the board with the positive output connected to the XCVU9P device U1 VBATT pin AT11. The battery supply current I from the SYS_1V8 1.8V rail through a series diode with a typical forward voltage drop of

0.38V and 4.7 KΩ current limit resistor. The nominal charging voltage is 1.42V.

X-Ref Target - Figure 3-1

specification is 150 nA maximum when the board power is off. B1 is charged

BATT

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Figure 3-1: Encryption Key Backup Circuit

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I/O Voltage Rails

There are 16 I/O banks available on the XCVU9P device and the VCU118 board. The voltages applied to the FPGA I/O banks used by the VCU118 board are listed in Table 3-1.

Table 3-1: I/O Bank Voltage Rails

FPGA (U1) Bank Power Supply Rail Net Name Voltage

Bank 0 VCC1V8_FPGA 1.8V

HP Bank 40 VCC1V2_FPGA 1.2V

HP Bank 41 VCC1V2_FPGA 1.2V

HP Bank 42 VCC1V2_FPGA 1.2V

HP Bank 43 VADJ_1V8_FPGA 1.8V

HP Bank 45 VADJ_1V8_FPGA 1.8V

HP Bank 46 VCC1V2_FPGA 1.2V

HP Bank 47 VCC1V2_FPGA 1.2V

HP Bank 48 VCC1V2_FPGA 1.2V

HP Bank 64 VCC1V8_FPGA 1.8V

HP Bank 65 VCC1V8_FPGA 1.8V

HP Bank 66 VADJ_1V8_FPGA 1.8V

HP Bank 67 VADJ_1V8_FPGA 1.8V

HP Bank 70 VADJ_1V8_FPGA 1.8V

HP Bank 71 VCC1V2_FPGA 1.2V

HP Bank 72 VCC1V2_FPGA 1.2V

HR Bank 73 VCC1V2_FPGA 1.2V

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Chapter 3: Board Component Descriptions

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DDR4 Component Memory

[Figure 2-1, callout 4]

The 2.5 GB DDR4 component memory system is comprised of two sets of five 256 Mb x 16 (80-bit wide) DDR4 SDRAM devices (Micron MT40A256M16GE-075E) located at U60-U64 (C1) and U135-U139 (C2). This dual memory system is connected in 80-bit wide interfaces to the U1 XCVU9P HP banks 71, 72, 73 (C1) and 40, 41, 42 (C2). The DDR4 0.6V VTT termination voltages (nets DDR4_C1_VTT and DDR4_C2_VTT) are sourced from the TI TPS51200DR linear regulators U24 and U134. The DDR4 memory interface bank VREF pins are not connected, which, coupled with an XDC set_property INTERNAL_VREF constraint, invoke the INTERNAL VREF mode. The connections between the C1 80-bit interface DDR4 component memories and XCVU9P banks 71, 72, and 73 are listed in Table 3-2.

Table 3-2: DDR4 Memory 80-bit I/F C1 to FPGA U1 Banks 71, 72, and 73

FPGA (U1)

F11 DDR4_C1_DQ0 POD12_DCI G2 DQL0 U60

E11 DDR4_C1_DQ1 POD12_DCI F7 DQL1 U60

F10 DDR4_C1_DQ2 POD12_DCI H3 DQL2 U60

F9 DDR4_C1_DQ3 POD12_DCI H7 DQL3 U60

H12 DDR4_C1_DQ4 POD12_DCI H2 DQL4 U60

G12 DDR4_C1_DQ5 POD12_DCI H8 DQL5 U60

E9 DDR4_C1_DQ6 POD12_DCI J3 DQL6 U60

D9 DDR4_C1_DQ7 POD12_DCI J7 DQL7 U60

R19 DDR4_C1_DQ8 POD12_DCI A3 DQU0 U60

P19 DDR4_C1_DQ9 POD12_DCI B8 DQU1 U60

M18 DDR4_C1_DQ10 POD12_DCI C3 DQU2 U60

M17 DDR4_C1_DQ11 POD12_DCI C7 DQU3 U60

N19 DDR4_C1_DQ12 POD12_DCI C2 DQU4 U60

N18 DDR4_C1_DQ13 POD12_DCI C8 DQU5 U60

N17 DDR4_C1_DQ14 POD12_DCI D3 DQU6 U60

Schematic Net Name I/O Standard

Pin # Pin Name Ref. Des.

Component Memory

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M16 DDR4_C1_DQ15 POD12_DCI D7 DQU7 U60

D11 DDR4_C1_DQS0_T DIFF_POD12_DCI G3 DQSL_T U60

D10 DDR4_C1_DQS0_C DIFF_POD12_DCI F3 DQSL_C U60

P17 DDR4_C1_DQS1_T DIFF_POD12_DCI B7 DQSU_T U60

P16 DDR4_C1_DQS1_C DIFF_POD12_DCI A7 DQSU_C U60

G11 DDR4_C1_DM0 POD12_DCI E7 DML_B/DBIL_B U60

R18 DDR4_C1_DM1 POD12_DCI E2 DMU_B/DBIU_B U60

L16 DDR4_C1_DQ16 POD12_DCI G2 DQL0 U61

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Table 3-2: DDR4 Memory 80-bit I/F C1 to FPGA U1 Banks 71, 72, and 73 (Cont’d)

FPGA (U1)

K16 DDR4_C1_DQ17 POD12_DCI F7 DQL1 U61

L18 DDR4_C1_DQ18 POD12_DCI H3 DQL2 U61

K18 DDR4_C1_DQ19 POD12_DCI H7 DQL3 U61

J17 DDR4_C1_DQ20 POD12_DCI H2 DQL4 U61

H17 DDR4_C1_DQ21 POD12_DCI H8 DQL5 U61

H19 DDR4_C1_DQ22 POD12_DCI J3 DQL6 U61

H18 DDR4_C1_DQ23 POD12_DCI J7 DQL7 U61

F19 DDR4_C1_DQ24 POD12_DCI A3 DQU0 U61

F18 DDR4_C1_DQ25 POD12_DCI B8 DQU1 U61

E19 DDR4_C1_DQ26 POD12_DCI C3 DQU2 U61

E18 DDR4_C1_DQ27 POD12_DCI C7 DQU3 U61

G20 DDR4_C1_DQ28 POD12_DCI C2 DQU4 U61

F20 DDR4_C1_DQ29 POD12_DCI C8 DQU5 U61

E17 DDR4_C1_DQ30 POD12_DCI D3 DQU6 U61

D16 DDR4_C1_DQ31 POD12_DCI D7 DQU7 U61

Schematic Net Name I/O Standard

Pin # Pin Name Ref. Des.

Component Memory

K19 DDR4_C1_DQS2_T DIFF_POD12_DCI G3 DQSL_T U61

J19 DDR4_C1_DQS2_C DIFF_POD12_DCI F3 DQSL_C U61

F16 DDR4_C1_DQS3_T DIFF_POD12_DCI B7 DQSU_T U61

E16 DDR4_C1_DQS3_C DIFF_POD12_DCI A7 DQSU_C U61

K17 DDR4_C1_DM2 POD12_DCI E7 DML_B/DBIL_B U61

G18 DDR4_C1_DM3 POD12_DCI E2 DMU_B/DBIU_B U61

D17 DDR4_C1_DQ32 POD12_DCI G2 DQL0 U62

C17 DDR4_C1_DQ33 POD12_DCI F7 DQL1 U62

C19 DDR4_C1_DQ34 POD12_DCI H3 DQL2 U62

C18 DDR4_C1_DQ35 POD12_DCI H7 DQL3 U62

D20 DDR4_C1_DQ36 POD12_DCI H2 DQL4 U62

D19 DDR4_C1_DQ37 POD12_DCI H8 DQL5 U62

C20 DDR4_C1_DQ38 POD12_DCI J3 DQL6 U62

B20 DDR4_C1_DQ39 POD12_DCI J7 DQL7 U62

N23 DDR4_C1_DQ40 POD12_DCI A3 DQU0 U62

M23 DDR4_C1_DQ41 POD12_DCI B8 DQU1 U62

R21 DDR4_C1_DQ42 POD12_DCI C3 DQU2 U62

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P21 DDR4_C1_DQ43 POD12_DCI C7 DQU3 U62

R22 DDR4_C1_DQ44 POD12_DCI C2 DQU4 U62

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Table 3-2: DDR4 Memory 80-bit I/F C1 to FPGA U1 Banks 71, 72, and 73 (Cont’d)

FPGA (U1)

P22 DDR4_C1_DQ45 POD12_DCI C8 DQU5 U62

T23 DDR4_C1_DQ46 POD12_DCI D3 DQU6 U62

R23 DDR4_C1_DQ47 POD12_DCI D7 DQU7 U62

A19 DDR4_C1_DQS4_T DIFF_POD12_DCI G3 DQSL_T U62

A18 DDR4_C1_DQS4_C DIFF_POD12_DCI F3 DQSL_C U62

N22 DDR4_C1_DQS5_T DIFF_POD12_DCI B7 DQSU_T U62

M22 DDR4_C1_DQS5_C DIFF_POD12_DCI A7 DQSU_C U62

B18 DDR4_C1_DM4 POD12_DCI E7 DML_B/DBIL_B U62

P20 DDR4_C1_DM5 POD12_DCI E2 DMU_B/DBIU_B U62

K24 DDR4_C1_DQ48 POD12_DCI G2 DQL0 U63

J24 DDR4_C1_DQ49 POD12_DCI F7 DQL1 U63

M21 DDR4_C1_DQ50 POD12_DCI H3 DQL2 U63

L21 DDR4_C1_DQ51 POD12_DCI H7 DQL3 U63

K21 DDR4_C1_DQ52 POD12_DCI H2 DQL4 U63

J21 DDR4_C1_DQ53 POD12_DCI H8 DQL5 U63

Schematic Net Name I/O Standard

Pin # Pin Name Ref. Des.

Component Memory

K22 DDR4_C1_DQ54 POD12_DCI J3 DQL6 U63

J22 DDR4_C1_DQ55 POD12_DCI J7 DQL7 U63

H23 DDR4_C1_DQ56 POD12_DCI A3 DQU0 U63

H22 DDR4_C1_DQ57 POD12_DCI B8 DQU1 U63

E23 DDR4_C1_DQ58 POD12_DCI C3 DQU2 U63

E22 DDR4_C1_DQ59 POD12_DCI C7 DQU3 U63

F21 DDR4_C1_DQ60 POD12_DCI C2 DQU4 U63

E21 DDR4_C1_DQ61 POD12_DCI C8 DQU5 U63

F24 DDR4_C1_DQ62 POD12_DCI D3 DQU6 U63

F23 DDR4_C1_DQ63 POD12_DCI D7 DQU7 U63

M20 DDR4_C1_DQS6_T DIFF_POD12_DCI G3 DQSL_T U63

L20 DDR4_C1_DQS6_C DIFF_POD12_DCI F3 DQSL_C U63

H24 DDR4_C1_DQS7_T DIFF_POD12_DCI B7 DQSU_T U63

G23 DDR4_C1_DQS7_C DIFF_POD12_DCI A7 DQSU_C U63

L23 DDR4_C1_DM6 POD12_DCI E7 DML_B/DBIL_B U63

G22 DDR4_C1_DM7 POD12_DCI E2 DMU_B/DBIU_B U63

A24 DDR4_C1_DQ64 POD12_DCI G2 DQL0 U64

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A23 DDR4_C1_DQ65 POD12_DCI F7 DQL1 U64

C24 DDR4_C1_DQ66 POD12_DCI H3 DQL2 U64

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Table 3-2: DDR4 Memory 80-bit I/F C1 to FPGA U1 Banks 71, 72, and 73 (Cont’d)

FPGA (U1)

C23 DDR4_C1_DQ67 POD12_DCI H7 DQL3 U64

B23 DDR4_C1_DQ68 POD12_DCI H2 DQL4 U64

B22 DDR4_C1_DQ69 POD12_DCI H8 DQL5 U64

B21 DDR4_C1_DQ70 POD12_DCI J3 DQL6 U64

A21 DDR4_C1_DQ71 POD12_DCI J7 DQL7 U64

D7 DDR4_C1_DQ72 POD12_DCI A3 DQU0 U64

C7 DDR4_C1_DQ73 POD12_DCI B8 DQU1 U64

B8 DDR4_C1_DQ74 POD12_DCI C3 DQU2 U64

B7 DDR4_C1_DQ75 POD12_DCI C7 DQU3 U64

C10 DDR4_C1_DQ76 POD12_DCI C2 DQU4 U64

B10 DDR4_C1_DQ77 POD12_DCI C8 DQU5 U64

B11 DDR4_C1_DQ78 POD12_DCI D3 DQU6 U64

A11 DDR4_C1_DQ79 POD12_DCI D7 DQU7 U64

D22 DDR4_C1_DQS8_T DIFF_POD12_DCI G3 DQSL_T U64

C22 DDR4_C1_DQS8_C DIFF_POD12_DCI F3 DQSL_C U64

Schematic Net Name I/O Standard

Pin # Pin Name Ref. Des.

Component Memory

A9 DDR4_C1_DQS9_T DIFF_POD12_DCI B7 DQSU_T U64

A8 DDR4_C1_DQS9_C DIFF_POD12_DCI A7 DQSU_C U64

E24 DDR4_C1_DM8 POD12_DCI E7 DML_B/DBIL_B U64

C9 DDR4_C1_DM9 POD12_DCI E2 DMU_B/DBIU_B U64

D14 DDR4_C1_A0 SSTL12_DCI P3 A0 U60-U64

B15 DDR4_C1_A1 SSTL12_DCI P7 A1 U60-U64

B16 DDR4_C1_A2 SSTL12_DCI R3 A2 U60-U64

C14 DDR4_C1_A3 SSTL12_DCI N7 A3 U60-U64

C15 DDR4_C1_A4 SSTL12_DCI N3 A4 U60-U64

A13 DDR4_C1_A5 SSTL12_DCI P8 A5 U60-U64

A14 DDR4_C1_A6 SSTL12_DCI P2 A6 U60-U64

A15 DDR4_C1_A7 SSTL12_DCI R8 A7 U60-U64

A16 DDR4_C1_A8 SSTL12_DCI R2 A8 U60-U64

B12 DDR4_C1_A9 SSTL12_DCI R7 A9 U60-U64

C12 DDR4_C1_A10 SSTL12_DCI M3 A10/AP U60-U64

B13 DDR4_C1_A11 SSTL12_DCI T2 A11 U60-U64

C13 DDR4_C1_A12 SSTL12_DCI M7 A12/BC_B U60-U64

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D15 DDR4_C1_A13 SSTL12_DCI T8 A13 U60-U64

G15 DDR4_C1_BA0 SSTL12_DCI N2 BA0 U60-U64

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Table 3-2: DDR4 Memory 80-bit I/F C1 to FPGA U1 Banks 71, 72, and 73 (Cont’d)

FPGA (U1)

G13 DDR4_C1_BA1 SSTL12_DCI N8 BA1 U60-U64

H13 DDR4_C1_BG0 SSTL12_DCI M2 BG0 U60-U64

H14 DDR4_C1_A14_WE_B SSTL12_DCI L2 WE_B/A14 U60-U64

H15 DDR4_C1_A15_CAS_B SSTL12_DCI M8 CAS_B_A15 U60-U64

F15 DDR4_C1_A16_RAS_B SSTL12_DCI L8 RAS_B/A16 U60-U64

F14 DDR4_C1_CK_T DIFF_SSTL12_DCI K7 CK_T U60-U64

E14 DDR4_C1_CK_C DIFF_SSTL12_DCI K8 CK_C U60-U64

A10 DDR4_C1_CKE SSTL12_DCI K2 CKE U60-U64

E13 DDR4_C1_ACT_B SSTL12_DCI L3 ACT_B U60-U64

G10 DDR4_C1_PAR SSTL12_DCI T3 PAR U60-U64

C8 DDR4_C1_ODT SSTL12_DCI K3 ODT U60-U64

F13 DDR4_C1_CS_B SSTL12_DCI L7 CS_B U60-U64

R17 DDR4_C1_ALERT_B SSTL12_DCI P9 ALERT_B U60-U64

N20 DDR4_C1_RESET_B LVCMOS12 P1 RESET_B U60-U64

A20 DDR4_C1_TEN SSTL12_DCI N9 TEN U60-U64

Schematic Net Name I/O Standard

Pin # Pin Name Ref. Des.

Component Memory

The connections between the C2 80-bit interface DDR4 component memories (U135-U139) and XCVU9P banks 40, 41, and 42 are listed in Table 3-3.

Table 3-3: DDR4 Memory 80-bit I/F C2 to FPGA U1 Banks 40, 41, and 42

FPGA (U1)

BD30 DDR4_C2_DQ0 POD12_DCI G2 DQL0 U135

BE30 DDR4_C2_DQ1 POD12_DCI F7 DQL1 U135

BD32 DDR4_C2_DQ2 POD12_DCI H3 DQL2 U135

BE33 DDR4_C2_DQ3 POD12_DCI H7 DQL3 U135

BC33 DDR4_C2_DQ4 POD12_DCI H2 DQL4 U135

BD33 DDR4_C2_DQ5 POD12_DCI H8 DQL5 U135

BC31 DDR4_C2_DQ6 POD12_DCI J3 DQL6 U135

BD31 DDR4_C2_DQ7 POD12_DCI J7 DQL7 U135

BA32 DDR4_C2_DQ8 POD12_DCI A3 DQU0 U135

BB33 DDR4_C2_DQ9 POD12_DCI B8 DQU1 U135

BA30 DDR4_C2_DQ10 POD12_DCI C3 DQU2 U135

BA31 DDR4_C2_DQ11 POD12_DCI C7 DQU3 U135

Schematic Net Name I/O Standard

Pin # Pin Name Ref. Des.

Component Memory

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Table 3-3: DDR4 Memory 80-bit I/F C2 to FPGA U1 Banks 40, 41, and 42 (Cont’d)

FPGA (U1)

AW31 DDR4_C2_DQ12 POD12_DCI C2 DQU4 U135

AW32 DDR4_C2_DQ13 POD12_DCI C8 DQU5 U135

AY32 DDR4_C2_DQ14 POD12_DCI D3 DQU6 U135

AY33 DDR4_C2_DQ15 POD12_DCI D7 DQU7 U135

BF30 DDR4_C2_DQS0_T DIFF_POD12_DCI G3 DQSL_T U135

BF31 DDR4_C2_DQS0_C DIFF_POD12_DCI F3 DQSL_C U135

AY34 DDR4_C2_DQS1_T DIFF_POD12_DCI B7 DQSU_T U135

BA34 DDR4_C2_DQS1_C DIFF_POD12_DCI A7 DQSU_C U135

BE32 DDR4_C2_DM0 POD12_DCI E7 DML_B/DBIL_B U135

BB31 DDR4_C2_DM1 POD12_DCI E2 DMU_B/DBIU_B U135

AV30 DDR4_C2_DQ16 POD12_DCI G2 DQL0 U136

AW30 DDR4_C2_DQ17 POD12_DCI F7 DQL1 U136

AU33 DDR4_C2_DQ18 POD12_DCI H3 DQL2 U136

AU34 DDR4_C2_DQ19 POD12_DCI H7 DQL3 U136

AT31 DDR4_C2_DQ20 POD12_DCI H2 DQL4 U136

Schematic Net Name I/O Standard

Pin # Pin Name Ref. Des.

Component Memory

AU32 DDR4_C2_DQ21 POD12_DCI H8 DQL5 U136

AU31 DDR4_C2_DQ22 POD12_DCI J3 DQL6 U136

AV31 DDR4_C2_DQ23 POD12_DCI J7 DQL7 U136

AR33 DDR4_C2_DQ24 POD12_DCI A3 DQU0 U136

AT34 DDR4_C2_DQ25 POD12_DCI B8 DQU1 U136

AT29 DDR4_C2_DQ26 POD12_DCI C3 DQU2 U136

AT30 DDR4_C2_DQ27 POD12_DCI C7 DQU3 U136

AP30 DDR4_C2_DQ28 POD12_DCI C2 DQU4 U136

AR30 DDR4_C2_DQ29 POD12_DCI C8 DQU5 U136

AN30 DDR4_C2_DQ30 POD12_DCI D3 DQU6 U136

AN31 DDR4_C2_DQ31 POD12_DCI D7 DQU7 U136

AU29 DDR4_C2_DQS2_T DIFF_POD12_DCI G3 DQSL_C U136

AV29 DDR4_C2_DQS2_C DIFF_POD12_DCI F3 DQSL_T U136

AP31 DDR4_C2_DQS3_T DIFF_POD12_DCI B7 DQSU_C U136

AP32 DDR4_C2_DQS3_C DIFF_POD12_DCI A7 DQSU_T U136

AV33 DDR4_C2_DM2 POD12_DCI E7 DML_B/DBIL_B U136

AR32 DDR4_C2_DM3 POD12_DCI E2 DMU_B/DBIU_B U136

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BE34 DDR4_C2_DQ32 POD12_DCI G2 DQL0 U137

BF34 DDR4_C2_DQ33 POD12_DCI F7 DQL1 U137

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Table 3-3: DDR4 Memory 80-bit I/F C2 to FPGA U1 Banks 40, 41, and 42 (Cont’d)

FPGA (U1)

BC35 DDR4_C2_DQ34 POD12_DCI H3 DQL2 U137

BC36 DDR4_C2_DQ35 POD12_DCI H7 DQL3 U137

BD36 DDR4_C2_DQ36 POD12_DCI H2 DQL4 U137

BE37 DDR4_C2_DQ37 POD12_DCI H8 DQL5 U137

BF36 DDR4_C2_DQ38 POD12_DCI J3 DQL6 U137

BF37 DDR4_C2_DQ39 POD12_DCI J7 DQL7 U137

BD37 DDR4_C2_DQ40 POD12_DCI A3 DQU0 U137

BE38 DDR4_C2_DQ41 POD12_DCI B8 DQU1 U137

BC39 DDR4_C2_DQ42 POD12_DCI C3 DQU2 U137

BD40 DDR4_C2_DQ43 POD12_DCI C7 DQU3 U137

BB38 DDR4_C2_DQ44 POD12_DCI C2 DQU4 U137

BB39 DDR4_C2_DQ45 POD12_DCI C8 DQU5 U137

BC38 DDR4_C2_DQ46 POD12_DCI D3 DQU6 U137

BD38 DDR4_C2_DQ47 POD12_DCI D7 DQU7 U137

BE35 DDR4_C2_DQS4_T DIFF_POD12_DCI G3 DQSL_T U137

Schematic Net Name I/O Standard

Pin # Pin Name Ref. Des.

Component Memory

BF35 DDR4_C2_DQS4_C DIFF_POD12_DCI F3 DQSL_C U137

BE39 DDR4_C2_DQS5_T DIFF_POD12_DCI B7 DQSU_T U137

BF39 DDR4_C2_DQS5_C DIFF_POD12_DCI A7 DQSU_C U137

BC34 DDR4_C2_DM4 POD12_DCI E7 DML_B/DBIL_B U137

BE40 DDR4_C2_DM5 POD12_DCI E2 DMU_B/DBIU_B U137

BB36 DDR4_C2_DQ48 POD12_DCI G2 DQL0 U138

BB37 DDR4_C2_DQ49 POD12_DCI F7 DQL1 U138

BA39 DDR4_C2_DQ50 POD12_DCI H3 DQL2 U138

BA40 DDR4_C2_DQ51 POD12_DCI H7 DQL3 U138

AW40 DDR4_C2_DQ52 POD12_DCI H2 DQL4 U138

AY40 DDR4_C2_DQ53 POD12_DCI H8 DQL5 U138

AY38 DDR4_C2_DQ54 POD12_DCI J3 DQL6 U138

AY39 DDR4_C2_DQ55 POD12_DCI J7 DQL7 U138

AW35 DDR4_C2_DQ56 POD12_DCI A3 DQU0 U138

AW36 DDR4_C2_DQ57 POD12_DCI B8 DQU1 U138

AU40 DDR4_C2_DQ58 POD12_DCI C3 DQU2 U138

AV40 DDR4_C2_DQ59 POD12_DCI C7 DQU3 U138

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AU38 DDR4_C2_DQ60 POD12_DCI C2 DQU4 U138

AU39 DDR4_C2_DQ61 POD12_DCI C8 DQU5 U138

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Table 3-3: DDR4 Memory 80-bit I/F C2 to FPGA U1 Banks 40, 41, and 42 (Cont’d)

FPGA (U1)

AV38 DDR4_C2_DQ62 POD12_DCI D3 DQU6 U138

AV39 DDR4_C2_DQ63 POD12_DCI D7 DQU7 U138

BA35 DDR4_C2_DQS6_T DIFF_POD12_DCI G3 DQSL_C U138

BA36 DDR4_C2_DQS6_C DIFF_POD12_DCI F3 DQSL_T U138

AW37 DDR4_C2_DQS7_T DIFF_POD12_DCI B7 DQSU_C U138

AW38 DDR4_C2_DQS7_C DIFF_POD12_DCI A7 DQSU_T U138

AY37 DDR4_C2_DM6 POD12_DCI E7 DML_B/DBIL_B U138

AV35 DDR4_C2_DM7 POD12_DCI E2 DMU_B/DBIU_B U138

BF26 DDR4_C2_DQ64 POD12_DCI G2 DQL0 U139

BF27 DDR4_C2_DQ65 POD12_DCI F7 DQL1 U139

BD28 DDR4_C2_DQ66 POD12_DCI H3 DQL2 U139

BE28 DDR4_C2_DQ67 POD12_DCI H7 DQL3 U139

BD27 DDR4_C2_DQ68 POD12_DCI H2 DQL4 U139

BE27 DDR4_C2_DQ69 POD12_DCI H8 DQL5 U139

BD25 DDR4_C2_DQ70 POD12_DCI J3 DQL6 U139

Schematic Net Name I/O Standard

Pin # Pin Name Ref. Des.

Component Memory

BD26 DDR4_C2_DQ71 POD12_DCI J7 DQL7 U139

BC25 DDR4_C2_DQ72 POD12_DCI A3 DQU0 U139

BC26 DDR4_C2_DQ73 POD12_DCI B8 DQU1 U139

BB28 DDR4_C2_DQ74 POD12_DCI C3 DQU2 U139

BC28 DDR4_C2_DQ75 POD12_DCI C7 DQU3 U139

AY27 DDR4_C2_DQ76 POD12_DCI C2 DQU4 U139

AY28 DDR4_C2_DQ77 POD12_DCI C8 DQU5 U139

BA27 DDR4_C2_DQ78 POD12_DCI D3 DQU6 U139

BB27 DDR4_C2_DQ79 POD12_DCI D7 DQU7 U139

BE25 DDR4_C2_DQS8_T DIFF_POD12_DCI G3 DQSL_C U139

BF25 DDR4_C2_DQS8_C DIFF_POD12_DCI F3 DQSL_T U139

BA26 DDR4_C2_DQS9_T DIFF_POD12_DCI B7 DQSU_C U139

BB26 DDR4_C2_DQS9_C DIFF_POD12_DCI A7 DQSU_T U139

BE29 DDR4_C2_DM8 POD12_DCI E7 DML_B/DBIL_B U139

BA29 DDR4_C2_DM9 POD12_DCI E2 DMU_B/DBIU_B U139

AM27 DDR4_C2_A0 SSTL12_DCI P3 A0 U135-U139

AL27 DDR4_C2_A1 SSTL12_DCI P7 A1 U135-U139

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AP26 DDR4_C2_A2 SSTL12_DCI R3 A2 U135-U139

AP25 DDR4_C2_A3 SSTL12_DCI N7 A3 U135-U139

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Table 3-3: DDR4 Memory 80-bit I/F C2 to FPGA U1 Banks 40, 41, and 42 (Cont’d)

FPGA (U1)

AN28 DDR4_C2_A4 SSTL12_DCI N3 A4 U135-U139

AM28 DDR4_C2_A5 SSTL12_DCI P8 A5 U135-U139

AP28 DDR4_C2_A6 SSTL12_DCI P2 A6 U135-U139

AP27 DDR4_C2_A7 SSTL12_DCI R8 A7 U135-U139

AN26 DDR4_C2_A8 SSTL12_DCI R2 A8 U135-U139

AM26 DDR4_C2_A9 SSTL12_DCI R7 A9 U135-U139

AR28 DDR4_C2_A10 SSTL12_DCI M3 A10/AP U135-U139

AR27 DDR4_C2_A11 SSTL12_DCI T2 A11 U135-U139

AV25 DDR4_C2_A12 SSTL12_DCI M7 A12/BC_B U135-U139

AT25 DDR4_C2_A13 SSTL12_DCI T8 A13 U135-U139

AR25 DDR4_C2_BA0 SSTL12_DCI N2 BA0 U135-U139

AU28 DDR4_C2_BA1 SSTL12_DCI N8 BA1 U135-U139

AU27 DDR4_C2_BG0 SSTL12_DCI M2 BG0 U135-U139

AV28 DDR4_C2_A14_WE_B SSTL12_DCI L2 WE_B/A14 U135-U139

AU26 DDR4_C2_A15_CAS_B SSTL12_DCI M8 CAS_B_A15 U135-U139

Schematic Net Name I/O Standard

Pin # Pin Name Ref. Des.

Component Memory

AV26 DDR4_C2_A16_RAS_B SSTL12_DCI L8 RAS_B/A16 U135-U139

AT26 DDR4_C2_CK_T DIFF_SSTL12_DCI K7 CK_T U135-U139

AT27 DDR4_C2_CK_C DIFF_SSTL12_DCI K8 CK_C U135-U139

AW28 DDR4_C2_CKE SSTL12_DCI K2 CKE U135-U139

AN25 DDR4_C2_ACT_B SSTL12_DCI L3 ACT_B U135-U139

BF29 DDR4_C2_PAR SSTL12_DCI P9 ALERT_B U135-U139

BB29 DDR4_C2_ODT SSTL12_DCI T3 PAR U135-U139

AY29 DDR4_C2_CS_B SSTL12_DCI K3 ODT U135-U139

AR29 DDR4_C2_ALERT_B SSTL12_DCI L7 CS_B U135-U139

BD35 DDR4_C2_RESET_B LVCMOS12 P1 RESET_B U135-U139

AY35 DDR4_C2_TEN SSTL12_DCI N9 TEN U135-U139

The VCU118 dual DDR4 80-bit memory component interfaces adhere to the constraints guidelines documented in the “DDR3/DDR4 Design Guidelines” section of the UltraScale Architecture-Based FPGAs Memory IP LogiCORE IP Product Guide (PG150) [Ref 4]. The VCU118 board DDR4 memory component interface is a 40Ω impedance implementation.

For more information on the internal VREF, see the “Supply Voltages for the SelectIO Pins VREF” and the “Internal VREF” sections in the UltraScale Architecture SelectIO Resources User Guide (UG571) [Ref 3]. For more details about the Micron DDR4 component memory, see the Micron MT40A256M16GE data sheet at the Micron website [Ref 18].

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