Xilinx UG518 User Manual
SP601 Hardware
User Guide
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UG518 (v1.1) August 19, 2009 [optional]
UG518 (v1.1) August 19, 2009
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SP601 Hardware User Guide www.xilinx.com UG518 (v1.1) August 19, 2009
Revision History
The following table shows the revision history for this document.
Date Version Revision
07/15/2009 1.0 Initial Xilinx release.
08/19/2009 1.1 • Added Appendix C, “VITA 57.1 FMC Connections.”
• Updated Figure 1-18 and Figure 1-32.
• Updated Tabl e 1- 4, Ta bl e 1 -17 , and Ta bl e 1 -2 0.
• Added introductory paragraph to Appendix D, “SP601 Master UCF.”
• Miscellaneous typographical edits and new user guide template.
UG518 (v1.1) August 19, 2009 www.xilinx.com SP601 Hardware User Guide
SP601 Hardware User Guide www.xilinx.com UG518 (v1.1) August 19, 2009
Table of Contents
Preface: About This Guide
Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typographical. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chapter 1: SP601 Evaluation Board
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Related Xilinx Documents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1. Spartan-6 XC6SLX16-2CSG324 FPGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
I/O Voltage Rails . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2. 128 MB DDR2 Component Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3. SPI x4 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4. Linear Flash BPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5. 10/100/1000 Tri-Speed Ethernet PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6. USB-to-UART Bridge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7. IIC Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8-Kb NV Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8. Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Oscillator (Differential) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Oscillator Socket (Single-Ended, 2.5V or 3.3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
SMA Connectors (Differential) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9. VITA 57.1 FMC-LPC Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
10. Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
11. FPGA Awake LED and Suspend Jumper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
12. FPGA INIT and DONE LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
13. User I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
14. FPGA_PROG_B Pushbutton Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
AC Adapter and 5V Input Power Jack/Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Onboard Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
JTAG Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
SP601 Hardware User Guide www.xilinx.com 5
UG518 (v1.1) August 19, 2009
Appendix A: References
Appendix B: Default Jumper and Switch Settings
Appendix C: VITA 57.1 FMC Connections
Appendix D: SP601 Master UCF
6 www.xilinx.com SP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
About This Guide
This manual accompanies the Spartan®-6 FPGA SP601 Evaluation Board and contains
information about the SP601 hardware and software tools.
Guide Contents
This manual contains the following chapters:
• Chapter 1, “SP601 Evaluation Board,” provides an overview of the embedded
development board and details the components and features of the SP601 board.
• Appendix A, “References.”
• Appendix B, “Default Jumper and Switch Settings.”
• Appendix D, “SP601 Master UCF.”
Preface
Additional Resources
To search the database of silicon and software questions and answers, or to create a
technical support case in WebCase, see the Xilinx website at:
http://www.xilinx.com/support
Conventions
This document uses the following conventions. An example illustrates each convention.
Typographical
The following typographical conventions are used in this document:
Convention Meaning or Use Example
Courier font
Courier bold
Helvetica bold
.
Messages, prompts, and
program files that the system
displays
Literal commands that you enter
in a syntactical statement
Commands that you select from
a menu
Keyboard shortcuts Ctrl+C
speed grade: - 100
ngdbuild design_name
File → Open
SP601 Hardware User Guide www.xilinx.com 7
UG518 (v1.1) August 19, 2009
Preface: About This Guide
Convention Meaning or Use Example
Variables in a syntax statement
for which you must supply
values
ngdbuild design_name
Italic font
Dark Shading
Square brackets [ ]
Braces { }
Vertical bar |
Angle brackets < >
Vertical ellipsis
.
.
.
References to other manuals
Emphasis in text
Items that are not supported or
reserved
An optional entry or parameter.
However, in bus specifications,
such as bus[7:0], they are
required.
A list of items from which you
must choose one or more
Separates items in a list of
choices
User-defined variable or in code
samples
Repetitive material that has
been omitted
See the User Guide for more
information.
If a wire is drawn so that it
overlaps the pin of a symbol, the
two nets are not connected.
This feature is not supported
ngdbuild [option_name]
design_name
lowpwr ={on|off}
lowpwr ={on|off}
<directory name>
IOB #1: Name = QOUT’
IOB #2: Name = CLKIN’
.
.
.
Horizontal ellipsis . . .
Notations
Online Document
The following conventions are used in this document:
Convention Meaning or Use Example
Blue text
Blue, underlined text
Repetitive material that has
been omitted
The prefix ‘0x’ or the suffix ‘h’
indicate hexadecimal notation
An ‘_n’ means the signal is
active low
Cross-reference link to a location
in the current document
Hyperlink to a website (URL)
allow block block_name loc1
loc2 ... locn;
A read of address 0x00112975
returned 45524943h.
usr_teof_n
See the section “Additional
Resources” for details.
Refer to “Title Formats” in
Chapter 1 for details.
Go to http://www.xilinx.com
for the latest speed files.
is active low.
8 www.xilinx.com SP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
SP601 Evaluation Board
Overview
The SP601 board enables hardware and software developers to create or evaluate designs
targeting the Spartan®-6 XC6SLX16-2CSG324 FPGA.
The SP601 provides board features for evaluating the Spartan-6 family that are common to
most entry-level development environments. Some commonly used features include a
DDR2 memory controller, a parallel linear flash, a tri-mode Ethernet PHY, generalpurpose I/O (GPIO), and a UART. Additional functionality can be added through the
VITA 57.1.1 expansion connector. “Features,” page 10 provides a general listing of the
board features with details provided in “Detailed Description,” page 12.
Additional Information
Additional information and support material is located at:
Chapter 1
• http://www.xilinx.com/sp601
This information includes:
• Current version of this user guide in PDF format
• Example design files for demonstration of Spartan-6 FPGA features and technology
• Demonstration hardware and software configuration files for the SP601 linear and SPI
memory devices
• Reference Design Files
• Schematics in PDF format and DxDesigner schematic format
• Bill of materials (BOM)
• Printed-circuit board (PCB) layout in Allegro PCB format
• Gerber files for the PCB (Many free or shareware Gerber file viewers are available on
the internet for viewing and printing these files.)
• Additional documentation, errata, frequently asked questions, and the latest news
For information about the Spartan-6 family of FPGA devices, including product
highlights, data sheets, user guides, and application notes, see the Spartan-6 FPGA website
at http://www.xilinx.com/support/documentation/spartan-6.htm
.
SP601 Hardware User Guide www.xilinx.com 9
UG518 (v1.1) August 19, 2009
Chapter 1: SP601 Evaluation Board
Features
The SP601 board provides the following features:
• 1. Spartan-6 XC6SLX16-2CSG324 FPGA
• 2. 128 MB DDR2 Component Memory
• 3. SPI x4 Flash
• 4. Linear Flash BPI
• 5. 10/100/1000 Tri-Speed Ethernet PHY
• 7. IIC Bus
♦ 8Kb NV memory
♦ External access 2-pin header
♦ VITA 57.1 FMC-LPC connector
• 8. Clock Generation
♦ Oscillator (Differential)
♦ Oscillator Socket (Single-Ended, 2.5V or 3.3V)
• SMA Connectors (Differential)
• 9. VITA 57.1 FMC-LPC Connector
• 10. Status LEDs
♦ FPGA_AWAKE
♦ INIT
♦ DONE
• 13. User I/O
♦ User LEDs
♦ User DIP switch
♦ User pushbuttons
♦ GPIO male pin header
• 14. FPGA_PROG_B Pushbutton Switch
• Configuration Options
♦ 3. SPI x4 Flash (both onboard and off-board)
♦ 4. Linear Flash BPI
♦ JTAG Configuration
• Power Management - AC Adapter and 5V Input Power Jack/Switch, Onboard Power
Supplies
10 www.xilinx.com SP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
X-Ref Target - Figure 1-1
Block Diagram
Figure 1-1 shows a high-level block diagram of the SP601 and its peripherals.
LEDs
DIP Switch
GPIO Header
FMC LPC
Expansion Connector
Related Xilinx Documents
10/100/1000
Ethernet GMII
USB
JTAG Connector
DDR2
Pushbuttons
DED
IIC EEPROM
and Header
Bank 3
1.8V
MODE
DIP Switch
Bank 0
2.5 V
Spartan-6
XC6SLX16
U1
Bank 2
2.5V
SPI x4 or
External Config
Parallel Flash
Bank 1
2.5V
Differential Clock
Clock Socket
SMA Clock
USB UART
UG518_01_070809
Figure 1-1: SP601 Features and Banking
Related Xilinx Documents
Prior to using the SP601 Evaluation Board, users should be familiar with Xilinx resources.
See the following locations for additional documentation on Xilinx tools and solutions:
• ISE: www.xilinx.com/ise
• Answer Browser: www.xilinx.com/support
• Intellectual Property: www.xilinx.com/ipcenter
SP601 Hardware User Guide www.xilinx.com 11
UG518 (v1.1) August 19, 2009
Chapter 1: SP601 Evaluation Board
Detailed Description
Figure 1-2 shows a board photo with numbered features corresponding to Tab le 1-1 and
the section headings in this document.
X-Ref Target - Figure 1-2
1414
1313
1515
99
22
77
1111
11
88
55
1212
88
1616
44
33
1010
66
1313
Figure 1-2: SP601 Board Photo
The numbered features in Figure 1-2 correlate to the features and notes listed in Ta bl e 1 -1 .
Table 1-1: SP601 Features
Number Feature Notes
1 Spartan-6 FPGA XC6SLX16-2CSG324
Schematic
Page
2 DDR2 Component Hard memory controller w/ OCT 5
3 SPI x4 Flash and Headers SPI select and External Headers 8
4 Linear Flash BPI StrataFlash 8-bit (J3 device), 3 pins
shared w/ SPI x4
5 10/100/1000 Ethernet PHY GMII Marvell Alaska PHY 7
6 RS232 UART (USB Bridge) Uses CP2103 Serial-to-USB connection 10
7 IIC Goes to Header and VITA 57.1 FMC 10
8 Clock, socket, SMA Differential, Single-Ended, Differential 9
12 www.xilinx.com SP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
8
Table 1-1: SP601 Features (Cont’d)
Detailed Description
Number Feature Notes
9 VITA 57.1 FMC-LPC
connector
10 LEDs Ethernet PHY Status 7
11 LED, Header FPGA Awake LED, Suspend Header 8
12 LEDs FPGA INIT, DONE 9
LED User I/O (active-High) 9
DIP Switch User I/O (active-High) 9
13
Pushbutton User I/O, CPU_RESET (active-High) 9
12-pin (8 I/O) Header 6 pins x 2 male header with 8 I/Os
14 Pushbutton FPGA_PROG_B 9
15 USB JTAG Cypress USB to JTAG download cable
16 Onboard Power Power Management 11,12,13
LVDS signals, clocks, PRSNT 6
(active-High)
logic
1. Spartan-6 XC6SLX16-2CSG324 FPGA
Schematic
Page
10
14, 15
A Xilinx Spartan-6 XC6SLX16-2CSG324 FPGA is installed on the Embedded Development
Board.
Configuration
The SP601 supports configuration in the following modes:
• Master SPI x4
• Master SPI x4 with off-board device
• BPI
• JTAG (using the included USB-A to Mini-B cable)
For details on configuring the FPGA, see “Configuration Options.”
I/O Voltage Rails
There are four available banks on the LX16-CS324 device. Banks 0, 1, and 2 are connected
for 2.5V I/O. Bank 3 is used for the 1.8V DDR2 component memory interface of Spartan-6
FPGA’s hard memory controller. The voltage applied to the FPGA I/O banks used by the
SP601 board is summarized in Tab le 1 -2 .
Table 1-2: I/O Voltage Rail of FPGA Banks
FPGA Bank I/O Voltage Rail
02.5V
12.5V
SP601 Hardware User Guide www.xilinx.com 13
UG518 (v1.1) August 19, 2009
Chapter 1: SP601 Evaluation Board
Table 1-2: I/O Voltage Rail of FPGA Banks (Cont’d)
FPGA Bank I/O Voltage Rail
References
See the Xilinx Spartan-6 FPGA documentation for more information at
http://www.xilinx.com/support/documentation/spartan-6.htm
2. 128 MB DDR2 Component Memory
There are 128 MB of DDR2 memory available on the SP601 board. A 1-Gb Elpida
EDE1116ACBG (84-ball) DDR2 memory component is accessible through Bank 3 of the
LX16 device. The Spartan-6 FPGA hard memory controller is used for data transfer across
the DDR2 memory interface's 16-bit data path using SSTL18 signaling. The maximum data
rate supported is 800 Mb/s with a memory clock running at 400 MHz. Signal integrity is
maintained through DDR2 resistor terminations and memory on-die terminations (ODT),
as shown in Ta bl e 1- 3 and Tab le 1 -4 .
Table 1-3: Termination Resistor Requirements
22.5V
31.8V
.
Signal Name Board Termination On-Die Termination
DDR2_A[14:0] 49.9 ohms to V
DDR2_BA[2:0] 49.9 ohms to V
DDR2_RAS_N 49.9 ohms to V
DDR2_CAS_N 49.9 ohms to V
DDR2_WE_N 49.9 ohms to V
DDR2_CS_N 100 ohms to GND
DDR2_CKE 4.7K ohms to GND
DDR2_ODT 4.7K ohms to GND
DDR2_DQ[15:0] ODT
DDR2_UDQS[P,N],
DDR2_LDQS[P,N]
DDR2_UDM, DDR2_LDM ODT
DDR2_CK[P,N]
Notes:
1. Nominal value of VTT for DDR2 interface is 0.9V.
100 ohm differential at
memory component
TT
TT
TT
TT
TT
ODT
Table 1-4: FPGA On-Chip (OCT) Termination External Resistor Requirements
FPGA U1 Pin FPGA Pin Number Board Connection for OCT
ZIO L6 No Connect
RZQ C2 100 ohms to GROUND
14 www.xilinx.com SP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
Detailed Description
Tab le 1- 5 shows the connections and pin numbers for the DDR2 Component Memory.
Table 1-5: DDR2 Component Memory Connections
FPGA U1 Schematic Netname
Pin Number Name
J7 DDR2_A0 M8 A0
J6 DDR2_A1 M3 A1
H5 DDR2_A2 M7 A2
L7 DDR2_A3 N2 A3
F3 DDR2_A4 N8 A4
H4 DDR2_A5 N3 A5
H3 DDR2_A6 N7 A6
H6 DDR2_A7 P2 A7
D2 DDR2_A8 P8 A8
D1 DDR2_A9 P3 A9
F4 DDR2_A10 M2 A10
D3 DDR2_A11 P7 A11
G6 DDR2_A12 R2 A12
Memory U2
L2 DDR2_DQ0 G8 DQ0
L1 DDR2_DQ1 G2 DQ1
K2 DDR2_DQ2 H7 DQ2
K1 DDR2_DQ3 H3 DQ3
H2 DDR2_DQ4 H1 DQ4
H1 DDR2_DQ5 H9 DQ5
J3 DDR2_DQ6 F1 DQ6
J1 DDR2_DQ7 F9 DQ7
M3 DDR2_DQ8 C8 DQ8
M1 DDR2_DQ9 C2 DQ9
N2 DDR2_DQ10 D7 DQ10
N1 DDR2_DQ11 D3 DQ11
T2 DDR2_DQ12 D1 DQ12
T1 DDR2_DQ13 D9 DQ13
U2 DDR2_DQ14 B1 DQ14
U1 DDR2_DQ15 B9 DQ15
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UG518 (v1.1) August 19, 2009
Chapter 1: SP601 Evaluation Board
Table 1-5: DDR2 Component Memory Connections (Cont’d)
FPGA U1 Schematic Netname
Memory U2
Pin Number Name
F2 DDR2_BA0 L2 BA0
F1 DDR2_BA1 L3 BA1
E1 DDR2_BA2 L1 BA2
E3 DDR2_WE_B K3 WE
L5 DDR2_RAS_B K7 RAS
K5 DDR2_CAS_B L7 CAS
K6 DDR2_ODT K9 ODT
G3 DDR2_CLK_P J8 CK
G1 DDR2_CLK_N K8 CK
H7 DDR2_CKE K2 CKE
L4 DDR2_LDQS_P F7 LDQS
L3 DDR2_LDQS_N E8 LDQS
P2 DDR2_UDQS_P B7 UDQS
P1 DDR2_UDQS_N A8 UDQS
K3 DDR2_LDM F3 LDM
K4 DDR2_UDM B3 UDM
Figure 1-3 provides the user constraints file (UCF) for the DDR2 SDRAM address pins,
including the I/O pin assignment and the I/O standard used.
X-Ref Target - Figure 1-3
NET "DDR2_A12" LOC ="G6";| IOSTANDARD = SSTL18_II ;
NET "DDR2_A11" LOC ="D3";| IOSTANDARD = SSTL18_II ;
NET "DDR2_A10" LOC ="F4";| IOSTANDARD = SSTL18_II ;
NET "DDR2_A9" LOC ="D1"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_A8" LOC ="D2"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_A7" LOC ="H6"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_A6" LOC ="H3"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_A5" LOC ="H4"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_A4" LOC ="F3"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_A3" LOC ="L7"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_A2" LOC ="H5"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_A1" LOC ="J6"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_A0" LOC ="J7"; | IOSTANDARD = SSTL18_II ;
Figure 1-3: UCF Location Constraints for DDR2 SDRAM Address Inputs
16 www.xilinx.com SP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
Detailed Description
Figure 1-4 provides the UCF constraints for the DDR2 SDRAM data pins, including the
I/O pin assignment and I/O standard used.
X-Ref Target - Figure 1-4
NET "DDR2_DQ15" LOC ="U1";| IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ14" LOC ="U2";| IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ13" LOC ="T1";| IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ12" LOC ="T2";| IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ11" LOC ="N1";| IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ10" LOC ="N2";| IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ9" LOC ="M1"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ8" LOC ="M3"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ7" LOC ="J1"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ6" LOC ="J3"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ5" LOC ="H1"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ4" LOC ="H2"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ3" LOC ="K1"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ2" LOC ="K2"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ1" LOC ="L1"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ0" LOC ="L2"; | IOSTANDARD = SSTL18_II ;
Figure 1-4: UCF Location Constraints for DDR2 SDRAM Data I/O Pins
Figure 1-5 provides the UCF constraints for the DDR2 SDRAM control pins, including the
I/O pin assignment and the I/O standard used.
X-Ref Target - Figure 1-5
NET "DDR2_WE_B" LOC ="E3"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_UDQS_P" LOC ="P2";| IOSTANDARD = SSTL18_II ;
NET "DDR2_UDQS_N" LOC ="P1";| IOSTANDARD = SSTL18_II ;
NET "DDR2_UDM" LOC ="K4"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_RAS_B" LOC ="L5"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_ODT" LOC ="K6"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_LDQS_P" LOC ="L4";| IOSTANDARD = SSTL18_II ;
NET "DDR2_LDQS_N" LOC ="L3";| IOSTANDARD = SSTL18_II ;
NET "DDR2_LDM" LOC ="K3"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_CLK_P" LOC ="G3"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_CLK_N" LOC ="G1"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_CKE" LOC ="H7"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_CAS_B" LOC ="K5"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_BA2" LOC ="E1"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_BA1" LOC ="F1"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_BA0" LOC ="F2"; | IOSTANDARD = SSTL18_II ;
Figure 1-5: UCF Location Constraints for DDR2 SDRAM Control Pins
References
See the Elpida DDR2 specifications for more information at
http://www.elpida.com/en/products/details/EDE1116ACBG.html
Also, see the Spartan-6 FPGA embedded hard memory controller block user guide at
http://www.xilinx.com/support/documentation/user_guides/ug388.pdf
SP601 Hardware User Guide www.xilinx.com 17
UG518 (v1.1) August 19, 2009
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