Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development
of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the
Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise,
without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves
the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors
contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with
technical support or assistance that may be provided to you in connection with the Information.
THE DOCUMENTATION IS DISCLOSED TO YOU “AS-IS” WITH NO WARRANTY OF ANY KIND. XILINX MAKES NO OTHER
WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DOCUMENTATION, INCLUDING ANY
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY
RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL
DAMAGES, INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OF THE DOCUMENTATION.
This manual accompanies the Spartan®-6 FPGA SP601 Evaluation Board and contains
information about the SP601 hardware and software tools.
Guide Contents
This manual contains the following chapters:
•Chapter 1, “SP601 Evaluation Board,” provides an overview of the embedded
development board and details the components and features of the SP601 board.
•Appendix A, “References.”
•Appendix B, “Default Jumper and Switch Settings.”
•Appendix D, “SP601 Master UCF.”
Preface
Additional Resources
To search the database of silicon and software questions and answers, or to create a
technical support case in WebCase, see the Xilinx website at:
http://www.xilinx.com/support
Conventions
This document uses the following conventions. An example illustrates each convention.
Typographical
The following typographical conventions are used in this document:
ConventionMeaning or UseExample
Courier font
Courier bold
Helvetica bold
.
Messages, prompts, and
program files that the system
displays
Literal commands that you enter
in a syntactical statement
Commands that you select from
a menu
Keyboard shortcutsCtrl+C
speed grade: - 100
ngdbuilddesign_name
File → Open
SP601 Hardware User Guidewww.xilinx.com7
UG518 (v1.1) August 19, 2009
Preface: About This Guide
ConventionMeaning or UseExample
Variables in a syntax statement
for which you must supply
values
ngdbuild design_name
Italic font
Dark Shading
Square brackets [ ]
Braces { }
Vertical bar |
Angle brackets < >
Vertical ellipsis
.
.
.
References to other manuals
Emphasis in text
Items that are not supported or
reserved
An optional entry or parameter.
However, in bus specifications,
such as bus[7:0], they are
required.
A list of items from which you
must choose one or more
Separates items in a list of
choices
User-defined variable or in code
samples
Repetitive material that has
been omitted
See the User Guide for more
information.
If a wire is drawn so that it
overlaps the pin of a symbol, the
two nets are not connected.
This feature is not supported
ngdbuild [option_name]
design_name
lowpwr ={on|off}
lowpwr ={on|off}
<directory name>
IOB #1: Name = QOUT’
IOB #2: Name = CLKIN’
.
.
.
Horizontal ellipsis . . .
Notations
Online Document
The following conventions are used in this document:
ConventionMeaning or UseExample
Blue text
Blue, underlined text
Repetitive material that has
been omitted
The prefix ‘0x’ or the suffix ‘h’
indicate hexadecimal notation
An ‘_n’ means the signal is
active low
Cross-reference link to a location
in the current document
Hyperlink to a website (URL)
allow block block_name loc1
loc2 ... locn;
A read of address 0x00112975
returned 45524943h.
usr_teof_n
See the section “Additional
Resources” for details.
Refer to “Title Formats” in
Chapter 1 for details.
Go to http://www.xilinx.com
for the latest speed files.
is active low.
8www.xilinx.comSP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
SP601 Evaluation Board
Overview
The SP601 board enables hardware and software developers to create or evaluate designs
targeting the Spartan®-6 XC6SLX16-2CSG324 FPGA.
The SP601 provides board features for evaluating the Spartan-6 family that are common to
most entry-level development environments. Some commonly used features include a
DDR2 memory controller, a parallel linear flash, a tri-mode Ethernet PHY, generalpurpose I/O (GPIO), and a UART. Additional functionality can be added through the
VITA 57.1.1 expansion connector. “Features,” page 10 provides a general listing of the
board features with details provided in “Detailed Description,” page 12.
Additional Information
Additional information and support material is located at:
Chapter 1
•http://www.xilinx.com/sp601
This information includes:
•Current version of this user guide in PDF format
•Example design files for demonstration of Spartan-6 FPGA features and technology
•Demonstration hardware and software configuration files for the SP601 linear and SPI
memory devices
•Reference Design Files
•Schematics in PDF format and DxDesigner schematic format
•Bill of materials (BOM)
•Printed-circuit board (PCB) layout in Allegro PCB format
•Gerber files for the PCB (Many free or shareware Gerber file viewers are available on
the internet for viewing and printing these files.)
•Additional documentation, errata, frequently asked questions, and the latest news
For information about the Spartan-6 family of FPGA devices, including product
highlights, data sheets, user guides, and application notes, see the Spartan-6 FPGA website
at http://www.xilinx.com/support/documentation/spartan-6.htm
.
SP601 Hardware User Guidewww.xilinx.com9
UG518 (v1.1) August 19, 2009
Chapter 1: SP601 Evaluation Board
Features
The SP601 board provides the following features:
•1. Spartan-6 XC6SLX16-2CSG324 FPGA
•2. 128 MB DDR2 Component Memory
•3. SPI x4 Flash
•4. Linear Flash BPI
•5. 10/100/1000 Tri-Speed Ethernet PHY
•7. IIC Bus
♦8Kb NV memory
♦External access 2-pin header
♦VITA 57.1 FMC-LPC connector
•8. Clock Generation
♦Oscillator (Differential)
♦Oscillator Socket (Single-Ended, 2.5V or 3.3V)
•SMA Connectors (Differential)
•9. VITA 57.1 FMC-LPC Connector
•10. Status LEDs
♦FPGA_AWAKE
♦INIT
♦DONE
•13. User I/O
♦User LEDs
♦User DIP switch
♦User pushbuttons
♦GPIO male pin header
•14. FPGA_PROG_B Pushbutton Switch
•Configuration Options
♦3. SPI x4 Flash (both onboard and off-board)
♦4. Linear Flash BPI
♦JTAG Configuration
•Power Management - AC Adapter and 5V Input Power Jack/Switch, Onboard Power
Supplies
10www.xilinx.comSP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
X-Ref Target - Figure 1-1
Block Diagram
Figure 1-1 shows a high-level block diagram of the SP601 and its peripherals.
LEDs
DIP Switch
GPIO Header
FMC LPC
Expansion Connector
Related Xilinx Documents
10/100/1000
Ethernet GMII
USB
JTAG Connector
DDR2
Pushbuttons
DED
IIC EEPROM
and Header
Bank 3
1.8V
MODE
DIP Switch
Bank 0
2.5 V
Spartan-6
XC6SLX16
U1
Bank 2
2.5V
SPI x4 or
External Config
Parallel Flash
Bank 1
2.5V
Differential Clock
Clock Socket
SMA Clock
USB UART
UG518_01_070809
Figure 1-1: SP601 Features and Banking
Related Xilinx Documents
Prior to using the SP601 Evaluation Board, users should be familiar with Xilinx resources.
See the following locations for additional documentation on Xilinx tools and solutions:
•ISE: www.xilinx.com/ise
•Answer Browser: www.xilinx.com/support
•Intellectual Property: www.xilinx.com/ipcenter
SP601 Hardware User Guidewww.xilinx.com11
UG518 (v1.1) August 19, 2009
Chapter 1: SP601 Evaluation Board
Detailed Description
Figure 1-2 shows a board photo with numbered features corresponding to Tab le 1-1 and
the section headings in this document.
X-Ref Target - Figure 1-2
1414
1313
1515
99
22
77
1111
11
88
55
1212
88
1616
44
33
1010
66
1313
Figure 1-2: SP601 Board Photo
The numbered features in Figure 1-2 correlate to the features and notes listed in Ta bl e 1 -1 .
Table 1-1: SP601 Features
NumberFeatureNotes
1 Spartan-6 FPGAXC6SLX16-2CSG324
Schematic
Page
2DDR2 ComponentHard memory controller w/ OCT5
3SPI x4 Flash and HeadersSPI select and External Headers8
12-pin (8 I/O) Header6 pins x 2 male header with 8 I/Os
14PushbuttonFPGA_PROG_B9
15USB JTAGCypress USB to JTAG download cable
16Onboard PowerPower Management11,12,13
LVDS signals, clocks, PRSNT6
(active-High)
logic
1. Spartan-6 XC6SLX16-2CSG324 FPGA
Schematic
Page
10
14, 15
A Xilinx Spartan-6 XC6SLX16-2CSG324 FPGA is installed on the Embedded Development
Board.
Configuration
The SP601 supports configuration in the following modes:
•Master SPI x4
•Master SPI x4 with off-board device
•BPI
•JTAG (using the included USB-A to Mini-B cable)
For details on configuring the FPGA, see “Configuration Options.”
I/O Voltage Rails
There are four available banks on the LX16-CS324 device. Banks 0, 1, and 2 are connected
for 2.5V I/O. Bank 3 is used for the 1.8V DDR2 component memory interface of Spartan-6
FPGA’s hard memory controller. The voltage applied to the FPGA I/O banks used by the
SP601 board is summarized in Tab le 1 -2 .
Table 1-2: I/O Voltage Rail of FPGA Banks
FPGA BankI/O Voltage Rail
02.5V
12.5V
SP601 Hardware User Guidewww.xilinx.com13
UG518 (v1.1) August 19, 2009
Chapter 1: SP601 Evaluation Board
Table 1-2: I/O Voltage Rail of FPGA Banks (Cont’d)
FPGA BankI/O Voltage Rail
References
See the Xilinx Spartan-6 FPGA documentation for more information at
There are 128 MB of DDR2 memory available on the SP601 board. A 1-Gb Elpida
EDE1116ACBG (84-ball) DDR2 memory component is accessible through Bank 3 of the
LX16 device. The Spartan-6 FPGA hard memory controller is used for data transfer across
the DDR2 memory interface's 16-bit data path using SSTL18 signaling. The maximum data
rate supported is 800 Mb/s with a memory clock running at 400 MHz. Signal integrity is
maintained through DDR2 resistor terminations and memory on-die terminations (ODT),
as shown in Ta bl e 1- 3 and Tab le 1 -4 .
Table 1-3: Termination Resistor Requirements
22.5V
31.8V
.
Signal NameBoard TerminationOn-Die Termination
DDR2_A[14:0]49.9 ohms to V
DDR2_BA[2:0]49.9 ohms to V
DDR2_RAS_N49.9 ohms to V
DDR2_CAS_N49.9 ohms to V
DDR2_WE_N49.9 ohms to V
DDR2_CS_N100 ohms to GND
DDR2_CKE4.7K ohms to GND
DDR2_ODT4.7K ohms to GND
DDR2_DQ[15:0]ODT
DDR2_UDQS[P,N],
DDR2_LDQS[P,N]
DDR2_UDM, DDR2_LDMODT
DDR2_CK[P,N]
Notes:
1. Nominal value of VTT for DDR2 interface is 0.9V.
Figure 1-3 provides the user constraints file (UCF) for the DDR2 SDRAM address pins,
including the I/O pin assignment and the I/O standard used.
X-Ref Target - Figure 1-3
NET "DDR2_A12" LOC ="G6";| IOSTANDARD = SSTL18_II ;
NET "DDR2_A11" LOC ="D3";| IOSTANDARD = SSTL18_II ;
NET "DDR2_A10" LOC ="F4";| IOSTANDARD = SSTL18_II ;
NET "DDR2_A9" LOC ="D1"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_A8" LOC ="D2"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_A7" LOC ="H6"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_A6" LOC ="H3"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_A5" LOC ="H4"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_A4" LOC ="F3"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_A3" LOC ="L7"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_A2" LOC ="H5"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_A1" LOC ="J6"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_A0" LOC ="J7"; | IOSTANDARD = SSTL18_II ;
Figure 1-3: UCF Location Constraints for DDR2 SDRAM Address Inputs
16www.xilinx.comSP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
Detailed Description
Figure 1-4 provides the UCF constraints for the DDR2 SDRAM data pins, including the
I/O pin assignment and I/O standard used.
X-Ref Target - Figure 1-4
NET "DDR2_DQ15" LOC ="U1";| IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ14" LOC ="U2";| IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ13" LOC ="T1";| IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ12" LOC ="T2";| IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ11" LOC ="N1";| IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ10" LOC ="N2";| IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ9" LOC ="M1"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ8" LOC ="M3"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ7" LOC ="J1"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ6" LOC ="J3"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ5" LOC ="H1"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ4" LOC ="H2"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ3" LOC ="K1"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ2" LOC ="K2"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ1" LOC ="L1"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_DQ0" LOC ="L2"; | IOSTANDARD = SSTL18_II ;
Figure 1-4: UCF Location Constraints for DDR2 SDRAM Data I/O Pins
Figure 1-5 provides the UCF constraints for the DDR2 SDRAM control pins, including the
I/O pin assignment and the I/O standard used.
X-Ref Target - Figure 1-5
NET "DDR2_WE_B" LOC ="E3"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_UDQS_P" LOC ="P2";| IOSTANDARD = SSTL18_II ;
NET "DDR2_UDQS_N" LOC ="P1";| IOSTANDARD = SSTL18_II ;
NET "DDR2_UDM" LOC ="K4"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_RAS_B" LOC ="L5"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_ODT" LOC ="K6"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_LDQS_P" LOC ="L4";| IOSTANDARD = SSTL18_II ;
NET "DDR2_LDQS_N" LOC ="L3";| IOSTANDARD = SSTL18_II ;
NET "DDR2_LDM" LOC ="K3"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_CLK_P" LOC ="G3"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_CLK_N" LOC ="G1"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_CKE" LOC ="H7"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_CAS_B" LOC ="K5"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_BA2" LOC ="E1"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_BA1" LOC ="F1"; | IOSTANDARD = SSTL18_II ;
NET "DDR2_BA0" LOC ="F2"; | IOSTANDARD = SSTL18_II ;
Figure 1-5: UCF Location Constraints for DDR2 SDRAM Control Pins
References
See the Elpida DDR2 specifications for more information at
The Xilinx Spartan-6 FPGA hosts a SPI interface which is visible to the Xilinx iMPACT
configuration tool. The SPI memory device operates at 3.0V; the Spartan-6 FPGA I/Os are
3.3V tolerant and provide electrically compatible logic levels to directly access the SPI flash
through a 2.5V bank. The XC6SLX16-2CSG324 is a master device when accessing an
external SPI flash memory device.
The SP601 SPI interface has two parallel connected configuration options (see Figure 1-7):
an SPI X4 (Winbond W25Q64VSFIG) 64-Mb flash memory device and a flash
programming header (J12). J12 supports a user-defined SPI mezzanine board. The SPI
configuration source is selected via SPI select jumper J15. For details on configuring the
FPGA, see “Configuration Options.”
X-Ref Target - Figure 1-6
Silkscreen
TMS
TDI
TDO
TCK
GND
3V3
J12
FPGA_PROG_B
1
2
FPGA_D2_MISO3
3
FPGA_D1_MISO2
SPI_CS_B
4
FPGA_MOSI_CSI_B_MISO0
5
FPGA_D0_DIN_MISO_MISO1
6
7
FPGA_CCLK
8
GND
9
VCC3V3
HDR_1X9
UG518_06_070809
Figure 1-6: J12 SPI Flash Programming Header
18www.xilinx.comSP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
X-Ref Target - Figure 1-7
Detailed Description
U1
FPGA SPI INTERFACE
U17
SPI X4
DIN,DOUT,CCLK
FLASH
MEMORY
SPIX4_CS_B
WINBOND
W25Q64VSFIG
ON = SPI X4 U17
OFF = SPI EXT. J12
Figure 1-7: SPI Flash Interface Topology
Table 1-6: SPI x4 Memory Connections
FPGA U1
Pin
Schematic Netname
J12
SPI_CS_B
2
1
SPI PROGRAM
J15
HEADER
SPI SELECT
JUMPER
UG518_07_070809
SPI MEM U17SPI HDR J12
Pin #Pin NamePin #Pin Name
V2FPGA_PROG_B1
V14FPGA_D2_MISO31IO3_HOLD_B2
T14FPGA_D1_MISO2_R9IO2_WP_B3
V3SPI_CS_B4TMS
T13FPGA_MOSI_CSI_B_MISO015DIN5TDI
R13FPGA_D0_DIN_MISO_MISO18IO1_DOUT6TDO
R15FPGA_CCLK16CLK7TCK
8GND
9VCC3V3
J15.2SPIX4_CS_B7CS_B
SP601 Hardware User Guidewww.xilinx.com19
UG518 (v1.1) August 19, 2009
Chapter 1: SP601 Evaluation Board
Figure 1-8 provides the UCF constraints for the SPI serial flash PROM.
X-Ref Target - Figure 1-8
NET "FPGA_D2_MISO3" LOC = "V14";
NET "SPI_CS_B" LOC = "V3";
NET "FPGA_D0_DIN_MISO_MISO1" LOC = "R13";
NET "FPGA_D1_MISO2" LOC = "T14";
NET "FPGA_MOSI_CSI_B_MISO0" LOC = "T13";
NET "FPGA_CCLK" LOC = "R15";
Figure 1-8: UCF Location Constraints for BPI Flash Connections
References
See the Winbond Serial Flash specifications for more information athttp://www.winbond-
An 8-bit (16 MB) Numonyx linear flash memory (TE 28F128J3D-75) (J3D type) is used to
provide non-volatile bitstream, code, and data storage. The J3D devices operate at 3.0V; the
Spartan-6 FPGA I/Os are 3.3V tolerant and provide electrically compatible logic levels to
directly access the linear flash BPI through a 2.5V bank. For details on configuring the
FPGA, see “Configuration Options.”
X-Ref Target - Figure 1-9
.
U1U10
FPGA
BPI FLASH
INTERFACE
ADDR, DATA, CTRL
Figure 1-9: Linear Flash BPI Interface
Table 1-7: BPI Memory Connections
FPGA U1 PinSchematic Netname
K18FLASH_A032A0
K17FLASH_A128A1
J18FLASH_A227A2
J16FLASH_A326A3
G18FLASH_A425A4
G16FLASH_A524A5
NUMONYX TYPE J3vD
T28F128J3D-75
UG518_09_070809
BPI Memory U10
Pin NumberPin
20www.xilinx.comSP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
Table 1-7: BPI Memory Connections (Cont’d)
Detailed Description
FPGA U1 PinSchematic Netname
H16FLASH_A623A6
H15FLASH_A722A7
H14FLASH_A820A8
H13FLASH_A919A9
F18FLASH_A1018A10
F17FLASH_A1117A11
K13FLASH_A1213A12
K12FLASH_A1312A13
E18FLASH_A1411A14
E16FLASH_A1510A15
G13FLASH_A168A16
H12FLASH_A177A17
D18FLASH_A186A18
D17FLASH_A195A19
BPI Memory U10
Pin NumberPin
G14FLASH_A204A20
F14FLASH_A213A21
C18FLASH_A221A22
C17FLASH_A2330A23
F16FLASH_A2456A24
R13FPGA_D0_DIN_MISO_MISO133DQ0
T14FPGA_D1_MISO235DQ1
V14FPGA_D2_MISO338DQ2
U5FLASH_D340DQ3
V5FLASH_D444DQ4
R3FLASH_D546DQ5
T3FLASH_D649DQ6
R5FLASH_D751DQ7
M16FLASH_WE_B 55WE_B
L18FLASH_OE_B54OE_B
SP601 Hardware User Guidewww.xilinx.com21
UG518 (v1.1) August 19, 2009
Chapter 1: SP601 Evaluation Board
Table 1-7: BPI Memory Connections (Cont’d)
FPGA U1 PinSchematic Netname
BPI Memory U10
Pin NumberPin
L17FLASH_CE_B14CE0
B3FMC_PWR_GOOD_FLASH_RST_B16RP_B
Note: Memory U10 pin 56 address A24 is not connected on the 16 MB device. It is made available
for larger density devices.
X-Ref Target - Figure 1-10
NET "FLASH_A0" LOC = "K18";
NET "FLASH_A1" LOC = "K17";
NET "FLASH_A2" LOC = "J18";
NET "FLASH_A3" LOC = "J16";
NET "FLASH_A4" LOC = "G18";
NET "FLASH_A5" LOC = "G16";
NET "FLASH_A6" LOC = "H16";
NET "FLASH_A7" LOC = "H15";
NET "FLASH_A8" LOC = "H14";
NET "FLASH_A9" LOC = "H13";
NET "FLASH_A10" LOC = "F18";
NET "FLASH_A11" LOC = "F17";
NET "FLASH_A12" LOC = "K13";
NET "FLASH_A13" LOC = "K12";
NET "FLASH_A14" LOC = "E18";
NET "FLASH_A15" LOC = "E16";
NET "FLASH_A16" LOC = "G13";
NET "FLASH_A17" LOC = "H12";
NET "FLASH_A18" LOC = "D18";
NET "FLASH_A19" LOC = "D17";
NET "FLASH_A20" LOC = "G14";
NET "FLASH_A21" LOC = "F14";
NET "FLASH_A22" LOC = "C18";
NET "FLASH_A23" LOC = "C17";
NET "FLASH_A24" LOC = "F16";
NET "FPGA_D0_DIN_MISO_MISO1" LOC = "R13";
NET "FPGA_D1_MISO2" LOC = "T14";
NET "FPGA_D2_MISO3" LOC = "V14";
NET "FLASH_D3" LOC = "U5";
NET "FLASH_D4" LOC = "V5";
NET "FLASH_D5" LOC = "R3";
NET "FLASH_D6" LOC = "T3";
NET "FLASH_D7" LOC = "R5";
NET "FLASH_WE_B" LOC = "M16";
NET "FLASH_OE_B" LOC = "L18";
NET "FLASH_CE_B" LOC = "L17";
NET "FMC_PWR_GOOD_FLASH_RST_B" LOC = "B3";
Figure 1-10: UCF Location Constraints for BPI Flash Connections
References
See the Numonyx Flash Memory specifications for more information at
The SP601 uses the onboard Marvell Alaska PHY device (88E1111) for Ethernet
communications at 10, 100, or 1000 Mb/s. The board supports a GMII/MII interface from
the FPGA to the PHY. The PHY connection to a user-provided Ethernet cable is through a
Halo HFJ11-1G01E RJ-45 connector with built-in magnetics.
On power-up, or on reset, the PHY is configured to operate in GMII mode with PHY
address 0b00111 using the settings shown in Tab le 1- 8. These settings can be overwritten
via software commands passed over the MDIO interface.
Table 1-8: PHY Configuration Pins
Detailed Description
Connection on
Pin
CFG0V
Board
2.5VPHYADR[2] = 1PHYADR[1] = 1PHYADR[0] = 1
CC
Definition and Value
Bit[2]
Bit[1]
Definition and Value
Bit[0]
Definition and Value
CFG1GroundENA_PAUSE = 0PHYADR[4] = 0PHYADR[3] = 0
CFG2V
CFG3V
CFG4V
CFG5V
2.5VANEG[3] = 1ANEG[2] = 1ANEG[1] = 1
CC
2.5VANEG[0] = 1ENA_XC = 1DIS_125 = 1
CC
2.5VHWCFG_MD[2] = 1HWCFG_MD[1] = 1HWCFG_MD[0] = 1
CC
2.5VDIS_FC = 1DIS_SLEEP = 1HWCFG_MD[3] = 1
CC
CFG6PHY_LED_RXSEL_BDT = 0INT_POL = 175/50 OHM = 0
Table 1-9: PHY Connections
FPGA U1
Pin
Schematic NetnameU3 M88E111
P16PHY_MDIO33
N14PHY_MDC35
J13PHY_INT32
L13PHY_RESET36
M13PHY_CRS115
L14PHY_COL114
L16PHY_RXCLK7
P17PHY_RXER8
N18PHY_RXCTL_RXDV4
M14PHY_RXD03
U18PHY_RXD1128
U17PHY_RXD2126
T18PHY_RXD3125
T17PHY_RXD4124
N16PHY_RXD5123
N15PHY_RXD6121
SP601 Hardware User Guidewww.xilinx.com23
UG518 (v1.1) August 19, 2009
Chapter 1: SP601 Evaluation Board
Table 1-9: PHY Connections (Cont’d)
FPGA U1
Pin
Schematic NetnameU3 M88E111
P18PHY_RXD7120
A9PHY_TXC_GTXCLK14
B9PHY_TXCLK10
A8PHY_TXER13
B8PHY_TXCTL_TXEN16
F8PHY_TXD018
G8PHY_TXD119
A6PHY_TXD220
B6PHY_TXD324
E6PHY_TXD425
F7PHY_TXD526
A5PHY_TXD628
C5PHY_TXD729
X-Ref Target - Figure 1-11
NET "PHY_COL" LOC = "L14";
NET "PHY_CRS" LOC = "M13";
NET "PHY_INT" LOC = "J13";
NET "PHY_MDC" LOC = "N14";
NET "PHY_MDIO" LOC = "P16";
NET "PHY_RESET" LOC = "L13";
NET "PHY_RXCLK" LOC = "L16";
NET "PHY_RXCTL_RXDV" LOC = "N18";
NET "PHY_RXD0" LOC = "M14";
NET "PHY_RXD1" LOC = "U18";
NET "PHY_RXD2" LOC = "U17";
NET "PHY_RXD3" LOC = "T18";
NET "PHY_RXD4" LOC = "T17";
NET "PHY_RXD5" LOC = "N16";
NET "PHY_RXD6" LOC = "N15";
NET "PHY_RXD7" LOC = "P18";
NET "PHY_RXER" LOC = "P17";
NET "PHY_TXCLK" LOC = "B9";
NET "PHY_TXCTL_TXEN" LOC = "B8";
NET "PHY_TXC_GTXCLK" LOC = "A9";
NET "PHY_TXD0" LOC = "F8";
NET "PHY_TXD1" LOC = "G8";
NET "PHY_TXD2" LOC = "A6";
NET "PHY_TXD3" LOC = "B6";
NET "PHY_TXD4" LOC = "E6";
NET "PHY_TXD5" LOC = "F7";
NET "PHY_TXD6" LOC = "A5";
NET "PHY_TXD7" LOC = "C5";
NET "PHY_TXER" LOC = "A8";
Figure 1-11: UCF Location Constraints for PHY Connections
24www.xilinx.comSP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
References
See the Marvell Alaska Gigabit Ethernet Transceiver product page for more information at
The SP601 contains a Silicon Labs CP2103GM USB-to-UART bridge device (U4) which
allows connection to a host computer with a USB cable. The USB cable is supplied in this
evaluation kit (Type A end to host computer, Type Mini-B end to SP601 connector J9).
Tab le 1-1 0 details the SP601 J9 pinout.
Xilinx UART IP is expected to be implemented in the FPGA fabric. The FPGA supports the
USB-to-UART bridge using four signal pins, transmit (TX), receive (RX), Request to Send
(RTS), and Clear to Send (CTS).
Silicon Labs provides royalty-free Virtual COM Port (VCP) drivers which permit the
CP2103GM USB-to-UART bridge to appear as a COM port to host computer
communications application software (for example, HyperTerm or TeraTerm). The VCP
device driver must be installed on the host PC prior to establishing communications with
the SP601. Refer to the SP601 Getting Started Guide for driver installation instructions.
Table 1-10: USB Type B Pin Assignments and Signal Definitions
Detailed Description
.
USB Connector
Pin
1VBUS+5V from host system (not used)
2USB_DATA_NBidirectional differential serial data (N-side)
3USB_DATA_PBidirectional differential serial data (P-side)
4GROUNDSignal ground
Signal NameDescription
Table 1-11: CP2103GM Connections
FPGA U1
Pin
U10USB_1_CTS22
T5USB_1_RTS23
L12USB_1_RX24
K14USB_1_TX25
X-Ref Target - Figure 1-12
NET "USB_1_CTS" LOC = "U10";
NET "USB_1_RTS" LOC = "T5";
NET "USB_1_RX" LOC = "L12";
NET "USB_1_TX" LOC = "K14";
Schematic NetnameU4 CP2103GM
Figure 1-12: UCF Location Constraints for CP2103GM Connections
SP601 Hardware User Guidewww.xilinx.com25
UG518 (v1.1) August 19, 2009
Chapter 1: SP601 Evaluation Board
References
Technical information on the Silicon Labs CP2103GM and the VCP drivers can be found on
their website at https://www.silabs.com/Pages/default.aspx
In addition, see some of the Xilinx UART IP specifications at:
The SP601 IIC bus topology is shown in Figure 1-13.
X-Ref Target - Figure 1-13
U1
VITA 57.1
FMC-LPC
C30C31
.
FMC-LPC
GA0=1
GA1=0
J1
U7
ST MICRO
M24 C08-WDW6TP
Address range
54-56
0b1010100-
0b1010110
UG518_13_070809
FPGA IIC
INTERFACE
IIC_SDA_MAIN
IIC_SCL_MAIN
IIC EXTERNAL
CONNECTOR
2
1
ACCESS
J16
Figure 1-13: IIC Bus Topology
The IIC Bus on the SP601 provides access to a 2-pin header, the onboard 8-Kb EEPROM,
and the VITA 57.1 FMC interface. The user must ensure there are no IIC address conflicts
with the onboard EEPROM address when attaching additional IIC devices via FMC or the
IIC 2-pin header. Note that FMC Mezzanine cards are designed with 2-Kb IIC EEPROMs
and will not conflict with the Carrier Card (SP601) 8-Kb EEPROM address range. This is
because 2-Kb EEPROMs reside below the 8-Kb EEPROM space. See the VITA 57.1
specification along with any IIC 2-Kbit EEPROM data sheet for more details.
26www.xilinx.comSP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
Detailed Description
8-Kb NV Memory
The SP601 hosts a 8-Kb ST Microelectronics M24C08-WDW6TP IIC parameter storage
memory device (U7). The IIC address of U7 is 0b1010100, and U7 is not write protected
(WP pin 7 is tied to GND).
Table 1-12: IIC Memory Connections
FPGA U1 Pin
Number
Not ApplicableTied to GND1A0
Not ApplicableTied to GND2A1
Not ApplicablePulled up (0 ohm) to VCC3V33A2
N10IIC_SDA_MAIN5SDA
P11IIC_SCL_MAIN6SCL
Not ApplicableTied to GND7WP
X-Ref Target - Figure 1-14
NET "IIC_SCL_MAIN" LOC = "P11";
NET "IIC_SDA_MAIN" LOC = "N10";
Schematic Netname
Pin NumberPin
SPI Memory U7
Figure 1-14: UCF Location Constraints for IIC Connections
References
See the ST Micro M24C08-WDW6TP data sheet for more information at
One populated single-ended clock socket (X2) is provided for user applications. The option
of 3.3V or 2.5V power may be selected via a 0 ohm resistor selection. The SP601 board is
shipped with a 27MHz 2.5V oscillator installed.
X-Ref Target - Figure 1-16
NET "USER_CLOCK" LOC = "V10";
Figure 1-16: UCF Location Constraints for Oscillator Socket Connections
SMA Connectors (Differential)
A high-precision clock signal can be provided to the FPGA using differential clock signals
through the onboard 50-ohm SMA connectors J7(P)/J8(N).
X-Ref Target - Figure 1-17
NET "SMACLK_N" LOC = "H18";
NET "SMACLK_P" LOC = "H17";
Figure 1-17: UCF Location Constraints for SMA Connectors Connections
9. VITA 57.1 FMC-LPC Connector
The VITA 57.1 FMC expansion connector (J1) on the SP601 implements the VITA 57.1.1 LPC
format of the VITA 57.1 FMC standard specification. The VITA 57.1 FMC-LPC connector
provides 68 single-ended (34 differential) user-defined signals (Tab le 1-1 3). The VITA 57.1
FMC standard calls for two connector densities: a High Pin Count (HPC) and a Low Pin
Count (LPC) implementation. A common 10 x 40 position (400 pin locations) connector
form factor is used for both versions. The HPC version has 400 pins present, the LPC
version, 160 pins. The Samtec connector system is rated for signaling speeds up to 9 GHz
(18 Gb/s) based on a -3dB insertion loss point within a two-level signaling environment.
Refer to theSamtec website
for data sheets and characterization information for the RoHS-
compliant VITA 57.1 FMC-LPC connector (ASP-134603-01) and its mate.
Note that the SP601 board FMC-LPC connector J1 VADJ voltage is FIXED at 2.5V (nonadjustable). This rail cannot be turned off. The SP601 VITA 57.1 FMC interface is
compatible with 2.5V Mezzanine Cards capable of supporting 2.5V VADJ.
The SP601 supports all FMC LA Bus connections available on the FMC LPC connector,
(LA[00:33]) along with all available FMC M2C clock pairs (CLK0_M2C_P/N and
CLK1_M2C_P/N). The SP601 does not support the FMC DP Bus connections since the
SP601 does not support any Gigabit Transceivers on the FMC DP Bus. Therefore,
DP0_C2M_P/N, DP0_M2C_P/N and GBTCLK0_M2C_P/N are not supported by the
SP601 FMC interface.
For more details about FMC, see the VITA57.1 specification available at
http://www.vita.com/fmc.html
.
28www.xilinx.comSP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
Detailed Description
Table 1-13: LPC Pinout
KJHGFEDCBA
NCNCVREF_A_M2CGNDNCNCPG_C2MGNDNCNC
1
NCNCPRSNT_M2C_LCLK1_M2C_PNCNCGNDDP0_C2M_PNCNC
2
3
NCNCGNDCLK1_M2C_NNCNCGNDDP0_C2M_NNCNC
NCNCCLK0_M2C_PGNDNCNCGBTCLK0_M2C_PGNDNCNC
4
NCNCCLK0_M2C_NGNDNCNCGBTCLK0_M2C_NGNDNCNC
5
NCNCGNDLA00_P_CCNCNCGNDDP0_M2C_PNCNC
6
NCNCLA02_PLA00_N_CCNCNCGNDDP0_M2C_NNCNC
7
NCNCLA02_NGNDNCNCLA01_P_CCGNDNCNC
8
9
NCNCGNDLA03_PNCNCLA01_N_CCGNDNCNC
NCNCLA04_PLA03_NNCNCGNDLA06_PNCNC
10
NCNCLA04_NGNDNCNCLA05_PLA06_NNCNC
11
NCNCGNDLA08_PNCNCLA05_NGNDNCNC
12
NCNCLA07_PLA08_NNCNCGNDGNDNCNC
13
NCNCLA07_NGNDNCNCLA09_PLA10_PNCNC
14
NCNCGNDLA12_PNCNCLA09_NLA10_NNCNC
15
NCNCLA11_PLA12_NNCNCGNDGNDNCNC
16
NCNCLA11_NGNDNCNCLA13_PGNDNCNC
17
NCNCGNDLA16_PNCNCLA13_NLA14_PNCNC
18
NCNCLA15_PLA16_NNCNCGNDLA14_NNCNC
19
NCNCLA15_NGNDNCNCLA17_P_CCGNDNCNC
20
NCNCGNDLA20_PNCNCLA17_N_CCGNDNCNC
21
NCNCLA19_PLA20_NNCNCGNDLA18_P_CCNCNC
22
23
NCNCLA19_NGNDNCNCLA23_PLA18_N_CCNCNC
NCNCGNDLA22_PNCNCLA23_NGNDNCNC
24
NCNCLA21_PLA22_NNCNCGNDGNDNCNC
25
26
NCNCLA21_NGNDNCNCLA26_PLA27_PNCNC
NCNCGNDLA25_PNCNCLA26_NLA27_NNCNC
27
NCNCLA24_PLA25_NNCNCGNDGNDNCNC
28
29
NCNCLA24_NGNDNCNCTCKGNDNCNC
NCNCGNDLA29_PNCNCTDISCLNCNC
30
NCNCLA28_PLA29_NNCNCTDOSDANCNC
31
32
NCNCLA28_NGNDNCNC3P3VAUXGNDNCNC
NCNCGNDLA31_PNCNCTMSGNDNCNC
33
SP601 Hardware User Guidewww.xilinx.com29
UG518 (v1.1) August 19, 2009
Chapter 1: SP601 Evaluation Board
Table 1-13: LPC Pinout (Cont’d)
KJHGFEDCBA
34NCNCLA30_PLA31_NNCNCTRST_LGA0NCNC
NCNCLA30_NGNDNCNCGA112P0VNCNC
35
NCNCGNDLA33_PNCNC3P3VGNDNCNC
36
NCNCLA32_PLA33_NNCNCGND12P0VNCNC
37
NCNCLA32_NGNDNCNC3P3VGNDNCNC
38
NCNCGNDVA D JNCNCGND3P3VNCNC
39
NCNCVA D JGNDNCNC3P3VGNDNCNC
40
30www.xilinx.comSP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
Detailed Description
X-Ref Target - Figure 1-18
NET "FMC_CLK0_M2C_N" LOC = "A10";
NET "FMC_CLK0_M2C_P" LOC = "C10";
NET "FMC_CLK1_M2C_N" LOC = "V9";
NET "FMC_CLK1_M2C_P" LOC = "T9";
NET "FMC_LA00_CC_N" LOC = "C9";
NET "FMC_LA00_CC_P" LOC = "D9";
NET "FMC_LA01_CC_N" LOC = "C11";
NET "FMC_LA01_CC_P" LOC = "D11";
NET "FMC_LA02_N" LOC = "A15";
NET "FMC_LA02_P" LOC = "C15";
NET "FMC_LA03_N" LOC = "A13";
NET "FMC_LA03_P" LOC = "C13";
NET "FMC_LA04_N" LOC = "A16";
NET "FMC_LA04_P" LOC = "B16";
NET "FMC_LA05_N" LOC = "A14";
NET "FMC_LA05_P" LOC = "B14";
NET "FMC_LA06_N" LOC = "C12";
NET "FMC_LA06_P" LOC = "D12";
NET "FMC_LA07_N" LOC = "E8";
NET "FMC_LA07_P" LOC = "E7";
NET "FMC_LA08_N" LOC = "E11";
NET "FMC_LA08_P" LOC = "F11";
NET "FMC_LA09_N" LOC = "F10";
NET "FMC_LA09_P" LOC = "G11";
NET "FMC_LA10_N" LOC = "C8";
NET "FMC_LA10_P" LOC = "D8";
NET "FMC_LA11_N" LOC = "A12";
NET "FMC_LA11_P" LOC = "B12";
NET "FMC_LA12_N" LOC = "C6";
NET "FMC_LA12_P" LOC = "D6";
NET "FMC_LA13_N" LOC = "A11";
NET "FMC_LA13_P" LOC = "B11";
NET "FMC_LA14_N" LOC = "A2";
NET "FMC_LA14_P" LOC = "B2";
NET "FMC_LA15_N" LOC = "F9";
NET "FMC_LA15_P" LOC = "G9";
NET "FMC_LA16_N" LOC = "A7";
NET "FMC_LA16_P" LOC = "C7";
NET "FMC_LA17_CC_N" LOC = "T8";
NET "FMC_LA17_CC_P" LOC = "R8";
NET "FMC_LA18_CC_N" LOC = "T10";
NET "FMC_LA18_CC_P" LOC = "R10";
NET "FMC_LA19_N" LOC = "P7";
NET "FMC_LA19_P" LOC = "N6";
NET "FMC_LA20_N" LOC = "P8";
NET "FMC_LA20_P" LOC = "N7";
NET "FMC_LA21_N" LOC = "V4";
NET "FMC_LA21_P" LOC = "T4";
NET "FMC_LA22_N" LOC = "T7";
NET "FMC_LA22_P" LOC = "R7";
NET "FMC_LA23_N" LOC = "P6";
NET "FMC_LA23_P" LOC = "N5";
NET "FMC_LA24_N" LOC = "V8";
NET "FMC_LA24_P" LOC = "U8";
NET "FMC_LA25_N" LOC = "N11";
NET "FMC_LA25_P" LOC = "M11";
NET "FMC_LA26_N" LOC = "V7";
NET "FMC_LA26_P" LOC = "U7";
NET "FMC_LA27_N" LOC = "T11";
NET "FMC_LA27_P" LOC = "R11";
NET "FMC_LA28_N" LOC = "V11";
NET "FMC_LA28_P" LOC = "U11";
NET "FMC_LA29_N" LOC = "N8";
NET "FMC_LA29_P" LOC = "M8";
NET "FMC_LA30_N" LOC = "V12";
NET "FMC_LA30_P" LOC = "T12";
NET "FMC_LA31_N" LOC = "V6";
NET "FMC_LA31_P" LOC = "T6";
NET "FMC_LA32_N" LOC = "V15";
NET "FMC_LA32_P" LOC = "U15";
NET "FMC_LA33_N" LOC = "N9";
NET "FMC_LA33_P" LOC = "M10";
NET "FMC_PRSNT_M2C_L" LOC = "U13";
NET "FMC_PWR_GOOD_FLASH_RST_B" LOC = "B3";
Figure 1-18: UCF Location Constraints for VITA 57.1 FMC-LPC Connections
SP601 Hardware User Guidewww.xilinx.com31
UG518 (v1.1) August 19, 2009
Chapter 1: SP601 Evaluation Board
10. Status LEDs
Tab le 1-1 4 defines the status LEDs.
Table 1-14: Status LEDs
Reference
Designator
DS1
DS2PHY_LED_LINK10Green10
DS3PHY_LED_LINK100Green100
DS4PHY_LED_LINK100
DS5PHY_LED_DUPLEXGreenDUP
DS6PHY_LED_RXGreenRX
DS7PHY_LED_TXGreenTX
DS8FPGA_AWAKEGreenAWAKE
DS9
DS10
Signal NameColorLabelDescription
FMC_PWR_GOOD_
FLASH_RST_B
0
FPGA_DONEGreenDONE
FPGA_INITRedINIT
Green
Green1000
PWR
GOOD
Indicates power available for
VITA 57.1 FMC expansion
connector.
Illuminates to indicate the
status of the DONE pin when
the FPGA is successfully
configured.
Illuminates after power-up to
indicate that the FPGA has
successfully powered up and
completed its internal poweron process.
DS15
DS16LED_GRN,
DS17
VCC5Green
LED_RED
LTC_PWR_GOOD Green
Green/
Red
STATUS
Illuminates when 5V supply is
applied.
USB to JTAG logic.
Illuminates to indicate that the
board power is good.
32www.xilinx.comSP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
X-Ref Target - Figure 1-19
Detailed Description
11. FPGA Awake LED and Suspend Jumper
The suspend mode jumper permits the FPGA to enter an inactive, "suspend" mode. The
FPGA Awake LED DS8 will go out when the FPGA enters this mode.
The typical Xilinx FPGA power up and configuration status LEDs are present on the
SP601. The INIT LED DS10 comes on after the FPGA powers up and completes its internal
power-on process. The DONE LED DS9 comes on after the FPGA programming bitstream
has been downloaded and the FPGA successfully configured.
X-Ref Target - Figure 1-21
VCC2V5
FPGA DONE
VCC2V5
1
R113
332
1%
2
1/16W
INIT_B = 0, LED: ON
INIT_B = 1, LED: OFF
FPGA INIT B
Table 1-16: FPGA INIT and DONE LED Connections
X-Ref Target - Figure 1-22
LED-RED-SMT
DS10
VCC2V5
12
1
2
R23
4.7K
5%
1/16W
1
2
R90
27.4
1%
1/16W
Figure 1-21: FPGA INIT and DONE LEDs
FPGA U1 Pin Schematic Netname Controlled LED
U3FPGA_INIT_BDS10 INIT
V17FPGA_DONEDS9 DONE
NET "FPGA_INIT_B" LOC = "U3";
NET "FPGA_DONE" LOC = "V17";
Figure 1-22: UCF Location Constraints for FPGA INIT and DONE
LED-GRN-SMT
1
2
2
DS9
1
R89
27.4
1%
1/16W
UG518_21_070809
34www.xilinx.comSP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
13. User I/O
The SP601 provides the following user and general purpose I/O capabilities:
•User LEDs
•User DIP switch
•Pushbutton switches
•CPU Reset pushbutton switch
•GPIO male pin header
Note:
User LEDs
The SP601 provides four active high, green LEDs, as described in Figure 1-23 and
Tab le 1-1 7.
X-Ref Target - Figure 1-23
Detailed Description
All GPIO location constraints are collected in one partial UCF in Figure 1-27.
GPIO LED 3
GPIO LED 2
GPIO LED 1
GPIO LED 0
LED-GRN-SMT
LED-GRN-SMT
2
DS12
1
1
R92
27.4
1%
2
1/16W
2
DS11
1
1
R91
27.4
1%
2
1/16W
Figure 1-23: User LEDs
LED-GRN-SMT
2
DS13
1
1
R93
27.4
1%
2
1/16W
2
LED-GRN-SMT
1
1
2
UG518_23_070809
DS14
R94
27.4
1%
1/16W
Table 1-17: User LEDs
Reference
Designator
DS11GPIO_LED_0Green
Signal NameColorLabelFPGA Pin
E13
DS12GPIO_LED_1GreenC14
SP601 Hardware User Guidewww.xilinx.com35
UG518 (v1.1) August 19, 2009
Chapter 1: SP601 Evaluation Board
Table 1-17: User LEDs (Cont’d)
X-Ref Target - Figure 1-24
Reference
Designator
DS13GPIO_LED_2GreenC4
DS14GPIO_LED_3GreenA4
User DIP switch
The SP601 includes an active high four pole DIP switch, as described in Figure 1-24 and
The SP601 provides five active high pushbutton switches: SW6, SW4, SW5, SW7 and SW9.
The five pushbuttons all have the same topology as the sample shown in Figure 1-25. Four
pushbuttons are assigned as GPIO, and the fifth is assigned as a CPU_RESET. Figure 1-25
and Ta bl e 1 -1 9 describe the pushbutton switches.
X-Ref Target - Figure 1-25
VCC1V8
Pushbutton
CPU_RESET
1
P1
2
P2P3
P4
4
3
SW9
Figure 1-25: User Pushbutton Switch (Typical)
Table 1-19: Pushbutton Switch Connections
FPGA U1 PinSchematic NetnameSwitch Pin
P4GPIO_BUTTON_0SW6.2
F6GPIO_BUTTON_1SW4.2
1
R188
4.7K
5%
1/16W
2
UG518_25_070809
E4GPIO_BUTTON_2SW5.2
F5GPIO_BUTTON_3SW7.2
N4CPU_RESETSW9.2
SP601 Hardware User Guidewww.xilinx.com37
UG518 (v1.1) August 19, 2009
Chapter 1: SP601 Evaluation Board
GPIO Male Pin Header
The SP601 provides a 2X6 GPIO male pin header supporting 3.3V power, GND and eight
I/Os. Figure 1-26 and Tab le 1- 20 describe the J13 GPIO Male Pin Header.
X-Ref Target - Figure 1-26
GPIO HDR0
GPIO HDR1
GPIO HDR2
GPIO HDR3
1/16W
5%
2
1/16W
5%
2
200
200
R102R103
1
1
1/16W1/16W
2
2
5%5%
200200
R100R101
1
R99
2005%1/16W
1
12
1
34
56
R97
1
78
910
2
R98
2005%1/16W
2
R96
11
2005%1/16W
2005%1/16W
GPIO HDR4
GPIO HDR5
2
GPIO HDR6
GPIO HDR7
2
1112
J13
VCC3V3
Figure 1-26: GPIO Male Pin Header Topology
Table 1-20: GPIO Header Pins
FPGA U1 PinSignal NameJ13 Pin
N17GPIO_HDR01
M18GPIO_HDR13
A3GPIO_HDR25
L15GPIO_HDR37
F15GPIO_HDR42
B4GPIO_HDR54
F13GPIO_HDR66
P12GPIO_HDR78
UG518_24_070809
38www.xilinx.comSP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
X-Ref Target - Figure 1-27
NET "GPIO_LED_0" LOC = "E13";
NET "GPIO_LED_1" LOC = "C14";
NET "GPIO_LED_2" LOC = "C4";
NET "GPIO_LED_3" LOC = "A4";
NET "GPIO_SWITCH_0" LOC = "D14";
NET "GPIO_SWITCH_1" LOC = "E12";
NET "GPIO_SWITCH_2" LOC = "F12";
NET "GPIO_SWITCH_3" LOC = "V13";
NET "GPIO_BUTTON0" LOC = "P4";
NET "GPIO_BUTTON1" LOC = "F6";
NET "GPIO_BUTTON2" LOC = "E4";
NET "GPIO_BUTTON3" LOC = "F5";
NET "CPU_RESET" LOC = "N4";
NET "GPIO_HDR0" LOC = "N17";
NET "GPIO_HDR1" LOC = "M18";
NET "GPIO_HDR2" LOC = "A3";
NET "GPIO_HDR3" LOC = "L15";
NET "GPIO_HDR4" LOC = "F15";
NET "GPIO_HDR5" LOC = "B4";
NET "GPIO_HDR6" LOC = "F13";
NET "GPIO_HDR7" LOC = "P12";
Detailed Description
Figure 1-27: UCF Location Constraints for User and General-Purpose I/O
SP601 Hardware User Guidewww.xilinx.com39
UG518 (v1.1) August 19, 2009
Chapter 1: SP601 Evaluation Board
14. FPGA_PROG_B Pushbutton Switch
The SP601 provides one dedicated, active low FPGA_PROG_B pushbutton switch, as
shown in Figure 1-28.
Figure 1-29: UCF Location Constraints for BPI Flash Connections
AC Adapter and 5V Input Power Jack/Switch
The SP601 is powered from a 5V source that is connected through a 2.1mm x 5.5mm type
plug (center positive).
switch. When the switch is in the on position, a green LED (DS15) is illuminated.
SP601 power can be turned on or off through a board mounted slide
Onboard Power Supplies
The diagram in Figure 1-30 shows the power supply architecture and maximum current
handling on each supply. The typical operating currents are significantly below the
maximum capable. The board is normally shipped with a 15W power supply, which
should be sufficient for most applications.
40www.xilinx.comSP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
Power Management
The SP601 uses power solutions from LTC. An estimate of the current draw on the various
power supply rails is shown in Tab le 1- 22 .
X-Ref Target - Figure 1-30
5V
PWR
Jack
Dual Switcher LTM4616
3. 3V@8A max
2. 5V@8A max
Dual Switcher LTM4616
1. 2V@8A max
1. 8V@8A max
Linear Regulator LT1763
3. 0V@500mA max
Buck-Boost Regulator LT1731
12V@1A max
Monolithic Regulator
0.9V@3A max
UG518_30 _070809
Figure 1-30: Power Supply
Table 1-22: Estimated Current Draw
Rail (V) Estimated Current (A)
FMC
LX16
Int/Aux
LX16
V
CCO
DDR2
BPI/SPI
Flash
USB
CP2103
Clock
Socket
Marvell
EPHY
Estimated
Totals
LTC
µModule
121.0 1.0LT173112V, 3A
3.33.0 2.0 0.30.1 0.1 5.5
2.5 0.11.01.1
1.8 1.0 1.3
1.2 3.02.0 5.0
0.91.01.0 LTC34130.9V, 1.0A
V
TT
(1/2)
LTM4616
(1/2)
LTM4616
(1/2)
LTM4616
(1/2)
LTM4616
Comments
3.3V, 8A
2.5V, 8A
1.8V, 8A
1.2V, 8A
SP601 Hardware User Guidewww.xilinx.com41
UG518 (v1.1) August 19, 2009
Chapter 1: SP601 Evaluation Board
Configuration Options
The FPGA on the SP601 Evaluation Board can be configured by the following methods:
•“3. SPI x4 Flash,” page 18
•“4. Linear Flash BPI,” page 20
•“JTAG Configuration,” page 42
For more information, refer to the Spartan-6 FPGA Configuration User Guide. [Ref 2]
Table 1-23: Mode Pin Settings (M2 = 0)
Mode Pins (M1, M0)Configuration Mode
00Master Byte Peripheral Interface (BPI)
01Master SPI x1, x2, or x4
10Not implemented on SP601
11Not implemented on SP601
JTAG Configuration
JTAG configuration is provided through onboard USB-to-JTAG configuration logic where
a computer host accesses the SP601 JTAG chain through a Type-A (computer host side) to
Type-Mini-B (SP601 side) USB cable.
The JTAG chain of the board is illustrated in Figure 1-31. JTAG configuration is allowable
at any time under any mode pin setting. JTAG initiated configuration takes priority over
the mode pin settings.
FMC bypass jumper J4 must be connected between pins 1-2 for JTAG access to the FPGA
on the basic SP601 board, as shown in Figure 1-31. When the VITA 57.1 FMC expansion
connector is populated with an expansion module that has a JTAG chain, then jumper J4
must be set to connect pins 2-3 in order to include the FMC expansion module's JTAG
chain in the main SP601 JTAG chain.
X-Ref Target - Figure 1-31
TDI
FPGA
U1
TDO
FMC LPC Expansion
TDI
J4
1
*Default jumper setting excludes FMC.
To include FMC, jumper pins 2-3.
TDO
J1
UG518_31_070809
J10
Connector
USB Mini-B
Figure 1-31: JTAG Chain
42www.xilinx.comSP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
Configuration Options
X-Ref Target - Figure 1-32
J4
Bypass FMC LPC J1 = Jumper 1-2
Include FMC LPC J1 = Jumper 2-3
1
2
3
H - 1x3
FPGA_TD0
JTAG_TD0
FMC_TD0
UG518_32_081909
Figure 1-32: VITA 57.1 FMC JTAG Bypass Jumper
The JTAG chain can be used to program the FPGA and access the FPGA for hardware and
software debug.
The JTAG connector (USB Mini-B J10) allows a host computer to download bitstreams to
the FPGA using the iMPACT software tool, and also allows debug tools such as the
ChipScope™ Pro Analyzer tool or a software debugger to access the FPGA.
The iMPACT software tool can also program the SPI x4 flash or the BPI flash via the USB
J10 connection. iMPACT can download a temporary design to the FPGA through the
JTAG. This provides a connection within the FPGA from the FPGA's JTAG port to the
FPGA's SPI or BPI interface. Through the connection made by the temporary design in the
FPGA, iMPACT can indirectly program the SPI flash or BPI flash from the JTAG USB J10
connector.
SP601 Hardware User Guidewww.xilinx.com43
UG518 (v1.1) August 19, 2009
Chapter 1: SP601 Evaluation Board
44www.xilinx.comSP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
References
This section provides references to documentation supporting Spartan-6 FPGAs, tools,
and IP. For additional information, see
www.xilinx.com/support/documentation/index.htm
Documents supporting the SP601 Evaluation Board:
1.UG138, LogiCORE™ IP Tri-Mode Ethernet MAC v4.2 User Guide
2.UG380
3.UG381
4.UG388
5.DS614
6.DS643
Appendix A
.
, Spartan-6 FPGA Configuration User Guide
, Spartan-6 FPGA SelectIO Resources User Guide
, Spartan-6 FPGA Memory Controller User Guide
, Clock Generator (v3.01a) Data Sheet
, Multi-Port Memory Controller (MPMC) (v5.02a) Data Sheet
SP601 Hardware User Guidewww.xilinx.com45
UG518 (v1.1) August 19, 2009
Appendix A: References
46www.xilinx.comSP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
Appendix B
Default Jumper and Switch Settings
Tab le B- 1 shows the default jumper and switch settings for the SP601.
Tab le B -1 :Default Jumper and Switch Settings
REFDESType/Function Default
SW1SLIDE, POWER ON-OFF OFF
SW2 DIP, 2-POLE, MODE
1M0 ON (1)
2M1OFF (0)
SW8DIP, 4-POLE, GPIO
1OFF
2OFF
3OFF
4OFF
J4 HDR_1X3, JTAG BYPASSJUMP 1-2 (EXCLUDE FMC)
J14HDR_1X2, SUSPEND OPEN (0 = AWAKE)
J15HDR_1X2, SPI SELECT ON (U17 SPI MEM SELECTED)
SP601 Hardware User Guidewww.xilinx.com47
UG518 (v1.1) August 19, 2009
Appendix B: Default Jumper and Switch Settings
48www.xilinx.comSP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
VITA 57.1 FMC Connections
Tab le C- 1 shows the VITA 57.1 FMC LPC connections.
Table C-1: VITA 57.1 FMC LPC Connections
Appendix C
J1 FMC
LPC Pin
C10FMC_LA06_PD12D1FMC_PWR_GOOD_FLASH_RST_BB3
C11FMC_LA06_NC12D8FMC_LA01_CC_PD11
C14FMC_LA10_PD8D9FMC_LA01_CC_NC11
C15FMC_LA10_NC8D11FMC_LA05_PB14
C18FMC_LA14_PB2D12FMC_LA05_NA14
C19FMC_LA14_NA2D14FMC_LA09_PG11
C22FMC_LA18_CC_PR10D15FMC_LA09_NF10
C23FMC_LA18_CC_NT10D17FMC_LA13_PB11
C26FMC_LA27_PR11D18FMC_LA13_NA11
C27FMC_LA27_NT11D20FMC_LA17_CC_PR8
C30IIC_SCL_MAINP11D21FMC_LA17_CC_NT8
C31IIC_SDA_MAINN10D23FMC_LA23_PN5
Schematic Netname
U1 FPGA
Pin
J1 FMC
LPC Pin
D24FMC_LA23_NP6
D26FMC_LA26_PU7
D27FMC_LA26_NV7
Schematic Netname
U1 FPGA
Pin
G2FMC_CLK1_M2C_PT9H2FMC_PRSNT_M2C_LU13
G3FMC_CLK1_M2C_NV9H4FMC_CLK0_M2C_PC10
G6FMC_LA00_CC_PD9H5FMC_CLK0_M2C_NA10
G7FMC_LA00_CC_NC9H7FMC_LA02_PC15
G9FMC_LA03_PC13H8FMC_LA02_NA15
G10FMC_LA03_NA13H10FMC_LA04_PB16
G12FMC_LA08_PF11H11FMC_LA04_NA16
SP601 Hardware User Guidewww.xilinx.com49
UG518 (v1.1) August 19, 2009
Appendix C: VITA 57.1 FMC Connections
Table C-1: VITA 57.1 FMC LPC Connections (Cont’d)
J1 FMC
LPC Pin
G13FMC_LA08_NE11H13FMC_LA07_PE7
G15FMC_LA12_PD6H14FMC_LA07_NE8
G16FMC_LA12_NC6H16FMC_LA11_PB12
G18FMC_LA16_PC7H17FMC_LA11_NA12
G19FMC_LA16_NA7H19FMC_LA15_PG9
G21FMC_LA20_PN7H20FMC_LA15_NF9
G22FMC_LA20_NP8H22FMC_LA19_PN6
G24FMC_LA22_PR7H23FMC_LA19_NP7
G25FMC_LA22_NT7H25FMC_LA21_PT4
G27FMC_LA25_PM11H26FMC_LA21_NV4
G28FMC_LA25_NN11H28FMC_LA24_PU8
G30FMC_LA29_PM8H29FMC_LA24_NV8
G31FMC_LA29_NN8H31FMC_LA28_PU11
G33FMC_LA31_PT6H32FMC_LA28_NV11
G34FMC_LA31_NV6H34FMC_LA30_PT12
Schematic Netname
U1 FPGA
Pin
J1 FMC
LPC Pin
Schematic Netname
U1 FPGA
Pin
G36FMC_LA33_PM10H35FMC_LA30_NV12
G37FMC_LA33_NN9H37FMC_LA32_PU15
H38FMC_LA32_NV15
50www.xilinx.comSP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
SP601 Master UCF
The UCF template is provided for designs that target the SP601. Net names provided in the
constraints below correlate with net names on the SP601 rev. C schematic. On identifying
the appropriate pins, the net names below should be replaced with net names in the user
RTL. See the Constraints Guide
NET "CPU_RESET" LOC = "N4";
NET "DDR2_A0" LOC = "J7";
NET "DDR2_A1" LOC = "J6";
NET "DDR2_A2" LOC = "H5";
NET "DDR2_A3" LOC = "L7";
NET "DDR2_A4" LOC = "F3";
NET "DDR2_A5" LOC = "H4";
NET "DDR2_A6" LOC = "H3";
NET "DDR2_A7" LOC = "H6";
NET "DDR2_A8" LOC = "D2";
NET "DDR2_A9" LOC = "D1";
NET "DDR2_A10" LOC = "F4";
NET "DDR2_A11" LOC = "D3";
NET "DDR2_A12" LOC = "G6";
NET "DDR2_BA0" LOC = "F2";
NET "DDR2_BA1" LOC = "F1";
NET "DDR2_BA2" LOC = "E1";
NET "DDR2_CAS_B" LOC = "K5";
NET "DDR2_CKE" LOC = "H7";
NET "DDR2_CLK_N" LOC = "G1";
NET "DDR2_CLK_P" LOC = "G3";
NET "DDR2_DQ0" LOC = "L2";
NET "DDR2_DQ1" LOC = "L1";
NET "DDR2_DQ2" LOC = "K2";
NET "DDR2_DQ3" LOC = "K1";
NET "DDR2_DQ4" LOC = "H2";
NET "DDR2_DQ5" LOC = "H1";
NET "DDR2_DQ6" LOC = "J3";
NET "DDR2_DQ7" LOC = "J1";
NET "DDR2_DQ8" LOC = "M3";
NET "DDR2_DQ9" LOC = "M1";
NET "DDR2_DQ10" LOC = "N2";
NET "DDR2_DQ11" LOC = "N1";
NET "DDR2_DQ12" LOC = "T2";
NET "DDR2_DQ13" LOC = "T1";
NET "DDR2_DQ14" LOC = "U2";
NET "DDR2_DQ15" LOC = "U1";
NET "DDR2_LDM" LOC = "K3";
NET "DDR2_LDQS_N" LOC = "L3";
Appendix D
for more information.
SP601 Hardware User Guidewww.xilinx.com51
UG518 (v1.1) August 19, 2009
Appendix D: SP601 Master UCF
NET "DDR2_LDQS_P" LOC = "L4";
NET "DDR2_ODT" LOC = "K6";
NET "DDR2_RAS_B" LOC = "L5";
NET "DDR2_UDM" LOC = "K4";
NET "DDR2_UDQS_N" LOC = "P1";
NET "DDR2_UDQS_P" LOC = "P2";
NET "DDR2_WE_B" LOC = "E3";
NET "FLASH_A0" LOC = "K18";
NET "FLASH_A1" LOC = "K17";
NET "FLASH_A2" LOC = "J18";
NET "FLASH_A3" LOC = "J16";
NET "FLASH_A4" LOC = "G18";
NET "FLASH_A5" LOC = "G16";
NET "FLASH_A6" LOC = "H16";
NET "FLASH_A7" LOC = "H15";
NET "FLASH_A8" LOC = "H14";
NET "FLASH_A9" LOC = "H13";
NET "FLASH_A10" LOC = "F18";
NET "FLASH_A11" LOC = "F17";
NET "FLASH_A12" LOC = "K13";
NET "FLASH_A13" LOC = "K12";
NET "FLASH_A14" LOC = "E18";
NET "FLASH_A15" LOC = "E16";
NET "FLASH_A16" LOC = "G13";
NET "FLASH_A17" LOC = "H12";
NET "FLASH_A18" LOC = "D18";
NET "FLASH_A19" LOC = "D17";
NET "FLASH_A20" LOC = "G14";
NET "FLASH_A21" LOC = "F14";
NET "FLASH_A22" LOC = "C18";
NET "FLASH_A23" LOC = "C17";
NET "FLASH_A24" LOC = "F16";
NET "FLASH_CE_B" LOC = "L17";
NET "FLASH_D3" LOC = "U5";
NET "FLASH_D4" LOC = "V5";
NET "FLASH_D5" LOC = "R3";
NET "FLASH_D6" LOC = "T3";
NET "FLASH_D7" LOC = "R5";
NET "FLASH_OE_B" LOC = "L18";
NET "FLASH_WE_B" LOC = "M16";
NET "FMC_CLK0_M2C_N" LOC = "A10";
NET "FMC_CLK0_M2C_P" LOC = "C10";
NET "FMC_CLK1_M2C_N" LOC = "V9";
NET "FMC_CLK1_M2C_P" LOC = "T9";
NET "FMC_LA00_CC_N" LOC = "C9";
NET "FMC_LA00_CC_P" LOC = "D9";
NET "FMC_LA01_CC_N" LOC = "C11";
NET "FMC_LA01_CC_P" LOC = "D11";
NET "FMC_LA02_N" LOC = "A15";
NET "FMC_LA02_P" LOC = "C15";
NET "FMC_LA03_N" LOC = "A13";
NET "FMC_LA03_P" LOC = "C13";
NET "FMC_LA04_N" LOC = "A16";
NET "FMC_LA04_P" LOC = "B16";
NET "FMC_LA05_N" LOC = "A14";
NET "FMC_LA05_P" LOC = "B14";
NET "FMC_LA06_N" LOC = "C12";
NET "FMC_LA06_P" LOC = "D12";
NET "FMC_LA07_N" LOC = "E8";
52www.xilinx.comSP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
NET "FMC_LA07_P" LOC = "E7";
NET "FMC_LA08_N" LOC = "E11";
NET "FMC_LA08_P" LOC = "F11";
NET "FMC_LA09_N" LOC = "F10";
NET "FMC_LA09_P" LOC = "G11";
NET "FMC_LA10_N" LOC = "C8";
NET "FMC_LA10_P" LOC = "D8";
NET "FMC_LA11_N" LOC = "A12";
NET "FMC_LA11_P" LOC = "B12";
NET "FMC_LA12_N" LOC = "C6";
NET "FMC_LA12_P" LOC = "D6";
NET "FMC_LA13_N" LOC = "A11";
NET "FMC_LA13_P" LOC = "B11";
NET "FMC_LA14_N" LOC = "A2";
NET "FMC_LA14_P" LOC = "B2";
NET "FMC_LA15_N" LOC = "F9";
NET "FMC_LA15_P" LOC = "G9";
NET "FMC_LA16_N" LOC = "A7";
NET "FMC_LA16_P" LOC = "C7";
NET "FMC_LA17_CC_N" LOC = "T8";
NET "FMC_LA17_CC_P" LOC = "R8";
NET "FMC_LA18_CC_N" LOC = "T10";
NET "FMC_LA18_CC_P" LOC = "R10";
NET "FMC_LA19_N" LOC = "P7";
NET "FMC_LA19_P" LOC = "N6";
NET "FMC_LA20_N" LOC = "P8";
NET "FMC_LA20_P" LOC = "N7";
NET "FMC_LA21_N" LOC = "V4";
NET "FMC_LA21_P" LOC = "T4";
NET "FMC_LA22_N" LOC = "T7";
NET "FMC_LA22_P" LOC = "R7";
NET "FMC_LA23_N" LOC = "P6";
NET "FMC_LA23_P" LOC = "N5";
NET "FMC_LA24_N" LOC = "V8";
NET "FMC_LA24_P" LOC = "U8";
NET "FMC_LA25_N" LOC = "N11";
NET "FMC_LA25_P" LOC = "M11";
NET "FMC_LA26_N" LOC = "V7";
NET "FMC_LA26_P" LOC = "U7";
NET "FMC_LA27_N" LOC = "T11";
NET "FMC_LA27_P" LOC = "R11";
NET "FMC_LA28_N" LOC = "V11";
NET "FMC_LA28_P" LOC = "U11";
NET "FMC_LA29_N" LOC = "N8";
NET "FMC_LA29_P" LOC = "M8";
NET "FMC_LA30_N" LOC = "V12";
NET "FMC_LA30_P" LOC = "T12";
NET "FMC_LA31_N" LOC = "V6";
NET "FMC_LA31_P" LOC = "T6";
NET "FMC_LA32_N" LOC = "V15";
NET "FMC_LA32_P" LOC = "U15";
NET "FMC_LA33_N" LOC = "N9";
NET "FMC_LA33_P" LOC = "M10";
NET "FMC_PRSNT_M2C_L" LOC = "U13";
NET "FMC_PWR_GOOD_FLASH_RST_B" LOC = "B3";
NET "FPGA_AWAKE" LOC = "P15";
NET "FPGA_CCLK" LOC = "R15";
NET "FPGA_CMP_CLK" LOC = "U16";
NET "FPGA_CMP_CS_B" LOC = "P13";
SP601 Hardware User Guidewww.xilinx.com53
UG518 (v1.1) August 19, 2009
Appendix D: SP601 Master UCF
NET "FPGA_CMP_MOSI" LOC = "V16";
NET "FPGA_D0_DIN_MISO_MISO1" LOC = "R13";
NET "FPGA_D1_MISO2" LOC = "T14";
NET "FPGA_D2_MISO3" LOC = "V14";
NET "FPGA_DONE" LOC = "V17";
NET "FPGA_HSWAPEN" LOC = "D4";
NET "FPGA_INIT_B" LOC = "U3";
NET "FPGA_M0_CMP_MISO" LOC = "T15";
NET "FPGA_M1" LOC = "N12";
NET "FPGA_MOSI_CSI_B_MISO0" LOC = "T13";
NET "FPGA_ONCHIP_TERM1" LOC = "L6";
NET "FPGA_ONCHIP_TERM2" LOC = "C2";
NET "FPGA_PROG_B" LOC = "V2";
NET "FPGA_SUSPEND" LOC = "R16";
NET "FPGA_TCK_BUF" LOC = "A17";
NET "FPGA_TDI_BUF" LOC = "D15";
NET "FPGA_TDO" LOC = "D16";
NET "FPGA_TMS_BUF" LOC = "B18";
NET "FPGA_VTEMP" LOC = "P3";
NET "GPIO_BUTTON0" LOC = "P4";
NET "GPIO_BUTTON1" LOC = "F6";
NET "GPIO_BUTTON2" LOC = "E4";
NET "GPIO_BUTTON3" LOC = "F5";
NET "GPIO_HDR0" LOC = "N17";
NET "GPIO_HDR1" LOC = "M18";
NET "GPIO_HDR2" LOC = "A3";
NET "GPIO_HDR3" LOC = "L15";
NET "GPIO_HDR4" LOC = "F15";
NET "GPIO_HDR5" LOC = "B4";
NET "GPIO_HDR6" LOC = "F13";
NET "GPIO_HDR7" LOC = "P12";
NET "GPIO_LED_0" LOC = "E13";
NET "GPIO_LED_1" LOC = "C14";
NET "GPIO_LED_2" LOC = "C4";
NET "GPIO_LED_3" LOC = "A4";
NET "GPIO_SWITCH_0" LOC = "D14";
NET "GPIO_SWITCH_1" LOC = "E12";
NET "GPIO_SWITCH_2" LOC = "F12";
NET "GPIO_SWITCH_3" LOC = "V13";
NET "IIC_SCL_MAIN" LOC = "P11";
NET "IIC_SDA_MAIN" LOC = "N10";
NET "PHY_COL" LOC = "L14";
NET "PHY_CRS" LOC = "M13";
NET "PHY_INT" LOC = "J13";
NET "PHY_MDC" LOC = "N14";
NET "PHY_MDIO" LOC = "P16";
NET "PHY_RESET" LOC = "L13";
NET "PHY_RXCLK" LOC = "L16";
NET "PHY_RXCTL_RXDV" LOC = "N18";
NET "PHY_RXD0" LOC = "M14";
NET "PHY_RXD1" LOC = "U18";
NET "PHY_RXD2" LOC = "U17";
NET "PHY_RXD3" LOC = "T18";
NET "PHY_RXD4" LOC = "T17";
NET "PHY_RXD5" LOC = "N16";
NET "PHY_RXD6" LOC = "N15";
NET "PHY_RXD7" LOC = "P18";
NET "PHY_RXER" LOC = "P17";
NET "PHY_TXCLK" LOC = "B9";
54www.xilinx.comSP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
NET "PHY_TXCTL_TXEN" LOC = "B8";
NET "PHY_TXC_GTXCLK" LOC = "A9";
NET "PHY_TXD0" LOC = "F8";
NET "PHY_TXD1" LOC = "G8";
NET "PHY_TXD2" LOC = "A6";
NET "PHY_TXD3" LOC = "B6";
NET "PHY_TXD4" LOC = "E6";
NET "PHY_TXD5" LOC = "F7";
NET "PHY_TXD6" LOC = "A5";
NET "PHY_TXD7" LOC = "C5";
NET "PHY_TXER" LOC = "A8";
NET "SMACLK_N" LOC = "H18";
NET "SMACLK_P" LOC = "H17";
NET "SPI_CS_B" LOC = "V3";
NET "SYSCLK_N" LOC = "K16";
NET "SYSCLK_P" LOC = "K15";
NET "USB_1_CTS" LOC = "U10";
NET "USB_1_RTS" LOC = "T5";
NET "USB_1_RX" LOC = "L12";
NET "USB_1_TX" LOC = "K14";
NET "USER_CLOCK" LOC = "V10";
SP601 Hardware User Guidewww.xilinx.com55
UG518 (v1.1) August 19, 2009
Loading...
+ hidden pages
You need points to download manuals.
1 point = 1 manual.
You can buy points or you can get point for every manual you upload.