Xilinx ML365 User Manual

Product Not Recommended for New Designs

ML365 Virtex-II Pro
QDR II SRAM (200 MHz)
Memory Board User Guide

UG066 (v1.0) June 29, 2004

R

Product Not Recommended for New Designs

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ML365 Virtex-II Pro QDR II SRAM Memory Board User Guide
UG066 (v1.0) June 29, 2004)

The following table shows the revision history for this document.

Version Revision

06/29/04 1.0 Initial Xilinx Release

ML365 Virtex-II Pro QDR II SRAM Mem. Board www.xilinx.com UG066 (v1.0) June 29, 2004

1-800-255-7778

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About This Guide

This document describes the design of the ML365 V irtex-II Pro™ QDR II SRAM (200 MHz)
Memory Board, which connects a V irtex-II Pro FPGA to Quad Data Ra te (Q DR) memories .

Guide Contents

This manual contains the following chapters:

• Chapter 1, “Introduction,” describes the purpose of the ML365 board and provides its

key features.

• Chapter 2, “Architecture,” provides a block diagram of the memory board and

describes the key components.

• Chapter 3, “Electrical Requirements,” lists the electrical specif ications for the memory

board.

• Chapter 4, “Signal Integrity Recommendations and Simulations,” provides

information on termination, transmission lines, and duty cycles. It also gives the
results of several IBIS simulations.

• Chapter 5, “Board Layout Guidelines,” provides information on decoupling

capacitors, ground signals, and PCB layout.

• Appendix 1, “Related Documentation,” lists data sheet and external website

references specific to the ML365 components.

• Appendix 2, “FPGA Pinout,” provides the pinout of the Virtex-II Pro FPGA.

• Appendix 3, “Memory Board Schematics and Characterization Results” shows the

schematics for the board.

Preface

Additional Resources

For additional information, go to http://support.xilinx.com. The following table lists
some of the resources you can access from this website. You can also directly access these
resources using the provided URLs.

Resource Description/URL

Tutorials Tutorials covering Xilinx design flows, from design entry to

verification and debugging:

http://support.xilinx.com/support/techsup/tutorials/index.htm

Answer Browser Database of Xilinx so luti on records:

http://support.xilinx.com/xlnx/xil_ans_browser.jsp

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Conventions

Resource Description/URL

Application Notes Descriptions of device-specific design techniques and approaches:

http://support.xilinx.com/apps/appsweb.htm

Data Sheets Device-specific information on Xilinx device characteristics,

including readback, boundary scan, configuration, length count,
and debugging:

http://support.xilinx.com/xlnx/xweb/xil_publications_index.jsp

Problem Solvers Interactive tools that allow you to troubleshoot your design issues:

http://support.xilinx.com/support/troubleshoot/psolvers.htm

Tech Tips Latest news, design tips, and patch information for the Xilinx

design environment:

http://www.support.xilinx.com/xlnx/xil_tt_home.jsp

This document uses the following conventions. An example illustrates each convention.

Typographical

The following typographical conventions are used in this document:

Convention Meaning or Use Example

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Online Document

The following conventions are used in this document:

Convention Meaning or Use Example

Blue text

References to other manuals

Emphasis in text

Cross -reference link to a
location in the current
document

See the Development System
Reference Guide for more
information.

If a wire is drawn so that it
overlaps the pin of a symbol,
the two nets are not connected.

See the section “Additional

Resources” for details.

Refer to “Title Formats” in

Chapter 1 for details.

Blue, underlined text

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Go to http://www.xilinx.com
for the latest speed files.

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Table of Contents

Preface: About This Guide

Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Typographical. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Schedule of Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Schedule of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Chapter 1: Introduction

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Chapter 2: Architecture

ML365 Board Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Block Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Memories. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

QDR II SRAM (U5, Banks 6 and 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

QDR II SRAM (U11, Banks 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

QDR II SRAM (U12, Banks 0 and 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

RS232 (J5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

200 MHz LVPECL Clock (Y1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

250 MHz LVPECL Clock (Y2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

SMA Clock Connectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

User I/Os. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

GPIO (P19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

DIP Switch (SW3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Push Buttons. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Rotary Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Power On or Off Slide Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Jumper Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Grounded I/Os. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Liquid Crystal Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Write Cycle for the LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Display Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Power Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.3 V Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

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2.5 V Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

1.8 V Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

1.5 V Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

FPGA Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Selecting the Configuration Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Serial Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Master Serial Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Slave Serial Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

SystemAce Configuration (Default Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

SelectMap Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

JTAG Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Chapter 3: Electrical Requirements

Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

FPGA Internal Power Budget. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Chapter 4: Signal Integrity Recommendations and Simulations

Termination and Transmission Line Summaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Terminations and Transmission Lines for QDR Components . . . . . . . . . . . . . . . . 34

Data and Clock Signals (D, Q, CQ, CQ
Address and Control Signals (A, R

IBIS Simulations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Notes on the Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Data Signal Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Data Signals from the FPGA to the Memory (HSTL_18_C2 at FPGA) . . . . . . . . . . . . 37

Data Signals from the QDR II SRAM, Component U11 to the FPGA Measured at the FPGA39

Eye Diagram for the Component U11, Bit 4 Signal Measured at the FPGA . . . . . . . . 40

Clock Signal Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Typical, Slow, and Fast Cases for Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Address and Control Signal Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Typical Case Simulation at All Memory Components. . . . . . . . . . . . . . . . . . . . . . . . . . 44

, and CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

, W, BW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Chapter 5: Board Layout Guidelines

Decoupling Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Providing Additional Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Board Stackup Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Appendix 1: Related Documentation

Appendix 2: FPGA Pinout

Appendix 3: Memory Board Schematics and Characterization Results

Schematics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Characterization Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Long-Term Runs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Corners Results Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

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Schedule of Figures

Chapter 1: Introduction

Figure 1-1: Simplified Block Diagram of Memory Board Interface. . . . . . . . . . . . . . . . . . 11

Chapter 2: Architecture

Figure 2-1: ML365 Board Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 2-2: LCD Write Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 2-3: Display Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 2-4: LCD Panel Character Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 2-5: SelectMap Connectors P99 and P111 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 2-6: SystemAce and JTAG Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 2-7: JTAG I/O Connector P103. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Chapter 3: Electrical Requirements

Chapter 4: Signal Integrity Recommendations and Simulations

Figure 4-1: Signal Terminations for Transmitted and Received Data. . . . . . . . . . . . . . . . 36

Figure 4-2: Data Signal Bit 4 from the FPGA to the Memory (Typical Case). . . . . . . . . . 37

Figure 4-3: Eye Diagram for Data Bit 4 from the FPGA to the QDR II SRAM, U11. . . . 38

Figure 4-4: Data Signals from the QDR II SRAM U11 at the FPGA (Typical,

Slow/Weak and Fast/Strong Cases) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 4-5: Eye Diagram for Data Bit 4 at the FPGA from Component U11. . . . . . . . . . . 40

Figure 4-6: Clock Signal Terminations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 4-7: Clock K Signal from the FPGA to the QDR II SRAM, Component U11 . . . 42
Figure 4-8: Clock CQ Signal from the FPGA to the QDR II SRAM Component U11 . . 43

Figure 4-9: Address and Control Signal Terminations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 4-10: Address/Control Signals for the QDR II SRAM, Component U11, Bit 4 . . 45

Chapter 5: Board Layout Guidelines

Figure 5-1: Picture of the Top Layer of the ML365 Revision 1.0b Board. . . . . . . . . . . . . . 50

Figure 5-2: Picture of the Bottom Layer of the ML365 Revision 1.0b Board . . . . . . . . . . . 51

Appendix 1: Related Documentation

Appendix 2: FPGA Pinout

Appendix 3: Memory Board Schematics and Characterization Results

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Schedule of Tables

Chapter 1: Introduction

Chapter 2: Architecture

Table 2-1: GPIO Header Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 2-2: DIP Switch Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 2-3: Power-On Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 2-4: FPGA Configuration Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 2-5: SystemAce Configuration Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 2-6: Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 2-7: LCD Pin Descriptions and PFGA Connections . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 2-8: LCD Write Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 2-9: Instruction Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 2-10: Configuration Modes Supported on the QDR II SRAM Demonstration Board 24

Table 2-11: Jumper Positions for SystemAce Configuration . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 2-12: JTAG Connector Pins (P1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Chapter 3: Electrical Requirements

Table 3-1: ML365 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 3-2: XC2VP20FF1152 Estimated Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 3-3: XC2VP20FF1152 Temperature Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 3-4: Device Quiescent Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 3-5: CLB Logic Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 3-6: Digital Clock Manager Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 3-7: Input/Output Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Chapter 4: Signal Integrity Recommendations and Simulations

Table 4-1: QDR SRAM Terminations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Chapter 5: Board Layout Guidelines

Table 5-1: Decoupling Capacitor Recommendations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 5-2: Suggested Stackup for a 12-layer board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Appendix 1: Related Documentation

Appendix 2: FPGA Pinout

Table 2-1: FPGA Pin Out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Appendix 3: Memory Board Schematics and Characterization Results

Table 3-1: Corners Results Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

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Introduction

Overview

The ML365 Virtex-II Pro QDR II SRAM Memory Board provides a communications
platform between a Virtex-II Pro FPGA and high-speed, quad data-rate (QDR) memories
with operating speeds up to 200 MHz. The ML365 has three major functions:

• Test and verify the interoperability of Virtex-II Pro devices with high-speed QDR II
SRAM memories

• Serve as a development platform for Xilinx and its customers to use for building
memory interfaces

• Provide a means by which Xilinx can demonstrate high-speed QDR II SRAM memory
interoperability

Chapter 1

This document describes the functional blocks within the ML365. It also provides various
recommend ations an d requirements for usage of the board, including electrical
requirements, logic analyzer requirements, and signal integrity issues. Simulation results
using IBIS also are included.

Figure 1-1 shows a simplified block diagram of the ML365 memory interfaces.

QDR II SRAM

1M x 36

FBGA 165

4-Word Burst

C,

QDR II SRAM

1M x 36

FBGA 165

4-Word Burst

(36-bits)

D (36-bits)

C, C

K, K

Addr, Ctrl

Q (36-bits)

CQ, CQ

D

Addr,

K,

C

Ctrl

K

Virtex-II Pro FPGA

XC2VP20FF1152-6

CQ,
CQ

Q
(36-bits)

D (36-bits)

Addr, Ctrl

Q (36-bits)

C, C

K, K

CQ, CQ

QDR II SRAM

1M x 36

FBGA 165

4-Word Burst

ug124_01_062204

Figure 1-1: Simplified Block Diagram of Memory Board Interface

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Features

Product Not Recommended for New Designs

The ML365 demonstrates a 36-bit interface to a 36 MByte, 200 MHz QDR II SRAM
component. There are thr ee independent 36-bit interfaces on the board; one on the le ft side
of the FPGA, the second on the right side of the FPGA, and the third on top of the FPGA.

The key features of the ML365 are summarized as follows:

• One Virtex-II Pro FPGA (XC2VP20FF1152)

• Three QDR II SRAM Components (Samsung K7R323684M or NEC UPD44165364F5)

♦ 18 MBytes
♦ 36-bit Data interface

• Three separate controllers for each 36-bit memory interface

• Characterized 200 MHz clock operation for interfaces A (interface to the FPGA on the

right side, U5) and B (interface to the FPGA on the left side, U11)

• One additional memory interface on the top banks of the FPGA (interface C, U12)

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Architecture

This chapter provides functional descriptio ns of the major blocks wi thin the ML365 board
design. For additional detailed information on the design, refer to the schematics, which
are located at http://www.xilinx.com/bvdocs/userguides/ug06

ML365 Board Block Diagram

Figure 2-1 shows a block diagram of the ML365 board. Refer to “Block Descriptions” for

additional information on the major blocks.

Chapter 2

6.zip.

RS-232
Serial
Por t

On / Off
Switch

DC 5V
Input Jack

FPGA
Reset

PROG

QDR II SRAM

Mode

DIP
SW

1M x 36

SMA

QDR II SRAM

1M x 36

XC2VP20

FF1152C

Clock
250 MHz

SMA

USER1
Switch

USER2
Switch

QDR II SRAM

Clock
200 MHz

GPIO Header

1M x 36

USER1
LED

USER2
LED

TPS54810

1.8V, 8A
Regulator

SYSTEM ACE

Controller
TQFP144

JTAG
Jumpers

SelectMap
Header

XCONFIG

Header

SystemAce
Reset

JTAG
Header

JTAG

Parallel

PC-IV

Por t

SystemAce
File Select
Rotary Switch

SEIKO 1X16
LCD Display
L167100J000

PT5502N

2.5V, 3A
Regulator

PT5505N

1.5V, 3A
Regulator

PT5501N

3.3V, 3A
Regulator

ug066_c2_01_060804

Figure 2-1: ML365 Board Block Diagram

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Block Descriptions

This section describes the major blocks of the ML365 board.

FPGA

The ML365 uses a Xilinx XC2VP20FF1152C-6 Virtex-II Pro device. This device is packaged
in a 1152-pin BGA package with a -6 speed grade. Refer to Appendix 2, “FPGA Pinout,”for
a complete pinout of the Virtex-II Pro device.

Memories

The ML365 board supports three types of memories in two speed grades.

QDR II SRAM (U5, Banks 6 and 7)

The QDR II SRAM component connected to FPGA I/O banks 6 and 7 is a 165-pin, 200 MHz
Samsung K7R323684M or NEC UPD44165364F5 SRAM in a Ball Grid Array package. This
component has a 36-bit wide data interface.

Chapter 2: Architecture

QDR II SRAM (U11, Banks 2 and 3)

The QDR II SRAM component connected to FPGA I/O banks 2 and 3 is a 165-pin, 200 MHz
Samsung K7R323684M or NEC UPD44165364F5 SRAM. This component has a 36-bit wide
data interface.

QDR II SRAM (U12, Banks 0 and 1)

The QDR II SRAM component connected to FPGA I/O banks 0 and 1 is a 165-pin, 250 MHz
Samsung K7R323684M or NEC UPD44165364F5 SRAM. This component has a 36-bit wide
data interface.

RS232 (J5)

The ML365 board provides an RS232 serial interface using a Maxim MAX3316ECUP
device. The maximum speed of this device is 460 Kb/s. The RS232 interface is accessible
through a male DB9 serial connector.

Clocks

The ML365 board has 200 MHz and 250 MHz LVPECL (2.5 V) clock oscillators on board. It
also has two SMA connectors for external differential clock inputs.

200 MHz LVPECL Clock (Y1)

The LVPECL clock is an Epson EG-2121CA-200 MHz oscillator with a differential output.
The oscillator runs at 200 MHz ± 100 PPM with an operating voltage of 2.5 V ± 5%. It is
terminated at the FPGA with a 50 ohm resistor. FPGA pins AH17 and AJ17 in Bank 4 serve
as the OSC_200M_N and OSC_200M_P inputs, respectively.

250 MHz LVPECL Clock (Y2)

The LVPECL clock is an Epson EG-2121CA-250 MHz clock oscillator with a differential
output. This oscillator runs at 250 MHz ± 100 PPM with an operating voltage of 2.5 V ± 5%.

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Block Descriptions

SMA Clock Connectors

User I/Os

GPIO (P19)

R

FPGA pins AK17 and AL17 in Bank 4 serve as the OSC_250M_N and OSC_250M_P inputs,
respectively.

Two SMA connectors are provided for the input of an off-board differential clock. The
traces from the SMAs are run as a pair to the FPGA where they are terminated with a
50 ohm resistor. AK18 serves as the EXT CLK1 _P input, and AL18 serves as the
EXTCLK1_N input for the SMA connector pair.

This subsection describes the devices that connect to the User I/Os of the ML365 board.

The ML365 board contains 16 General-Purpose I/Os (GPIOs) that are accessible thr ough a
2 x 16 .100" pin header (P19). The odd-numbered pins on each header are connected to an
FPGA pin, and the even-numbered pins on each header are connected to GND (refer to

Table 2-1). The GPIO header pins are accessed through I/Os in Bank 0. The header pins

each have a pull-down resistor of 51 ohms.

Table 2-1: GPIO Header Pins

GPIO Header Pin # FPGA I/O Pin

G1 AL13 G2
G3 AL12 G4
G5 AD16 G6
G7 AE16 G8

G9 AM14 G10
G11 AM13 G12
G13 AF16 G14
G15 AG16 G16
G17 AH15 G18
G19AJ15G20
G21AD17G22
G23 AE17 G24
G25 AH16 G26

GPIO Header Pin #

Ground Connections

G27AJ16G28
G29AK16G30
G31 AF17 G32

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DIP Switch (SW3)

One 3-position DIP switch (SW3) is connected to the FPGA I/O as shown in Table 2-2.
These switches are used to set the FPGA configuration mode pins M0, M1, and M2.

Table 2-2: DIP Switch Connections

DIP Switch Input FPGA I/O Pin #

DIP1 AF26 (M0)
DIP2 AE26 (M1)
DIP3 AE25 (M2)

LEDs

Eleven surface-mounted blue LEDs are installed as status indicators. Refer to Table 2-3,

Table 2-4, and Table 2-5.

Chapter 2: Architecture

Table 2-3: Power-On Status

Status Indication FPGA I/O Pin #

5.0V on D9

2.5V on D7

3.3V on D5

1.8V on D8

1.5V on D6

Table 2-4: FPGA Configuration Status

Configuration INIT D3

Configuration DONE D4

Table 2-5: SystemAce Configuration Status

System Ace LEDs

User LEDs

Error D2

Status D1
USER1 AF15
USER2 AE15

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Block Descriptions

Push Buttons

Rotary Switch

Power On or Off Slide Switch

R

The ML365 board contains five momentary push buttons. Their functions are as follows:

• Program the FPGA

• Reset FPGA

• Reset SystemAce

• USER1

• USER2

The ML365 board contains one eight-position rotary switch used to select the SystemAce
file address. One of eight configuration fi le images is loaded f r om the Compact Flash card
present in the socket.

The power on or off slide switch is a DPST s lide switch used to apply 5V input power to the
board.

Jumper Settings

Table 2-6 list s the jumper settings for the complete PCB.

Table 2-6: Jumper Settings

Pin # Purpose

P6 QDR II U5 DLL enable DLL enable DLL bypass

P7 QDR II U5 ZQ select Minimum Z mode 0.2RQ = 50 ohm
P20 QDR II U11 DLL enable DLL enable DLL bypass
P21 QDR II U11 ZQ select Minimum Z mode 0.2RQ = 50 ohm
P22 QDR II U12 DLL enable DLL enable DLL bypass
P23 QDR II U 12 ZQ select Minimum Z mode 0.2RQ = 50 ohm

P2 System Ace On = Disable after reset

Grounded I/Os

Unused I/Os are connected to GND in all FPGA banks. This was done to improve power
dissipation and SSO ground bounce. Users must not drive any unused I/Os that are
connected to GND.

Jumper Position

1 - 2 2 - 3

Off = Enable after reset

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Liquid Crystal Display

The Seiko L167100J000 Liquid Crystal Display (LCD) is a 5V, 1-line X16 character display
without a backlight. The LCD is connected to the PCB using two rows of 1 x 16 pin SIP
headers placed 31 mm. apart. The LCD interfaces uses bank 5 of the FPGA. The LCD pin
descriptions and FPGA pinouts are listed in Table 2-7.

Table 2-7: LCD Pin Descriptions and PFGA Connections

Symbol Function FPGA Pin #

Chapter 2: Architecture

V

SS

V

DD

V

O

Power supply (GND) N/A

Power supply (+5V) N/A
Contrast adjustment N/A

RS Register selection AF22

R/W Read / Write selection AG22

E Read / Write enable AE22

DB (0-7) Data bus AF25 (DB0), AL28, AM28, AE24,

AF24, AG25, AH25, AK27 (DB7)

The information needed to control the LCD panel is provided in the following figures and
tables. Figure 2-2 shows the LCD write timing diagram, and Table 2-8 lists the LCD write
timing parameters.

Table 2-9 shows the instruction codes for the LCD. Figure 2-3 shows the Display

Initialization Sequence, and Figure 2-7, the LCD panel character set. For complete
information, refer to the manufacturer’s data sheet.

Write Cycle for the LCD

Reading from the LCD panel memory is not implemented on this demonstration board.

RS

R / W

DB[7:0]

t

AS

PW

EH

E

t

ER

t

DSW

t

t

CYC

EF

t

AH

t

H

E

ug066_c2_02_060704

Figure 2-2: LCD Write Timing Diagram

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Block Descriptions

R

Table 2-8: LCD Write Timing Parameters

Enable pause width / High Level PW

Address setup time / RS, R/W - E t

Display Commands

Table 2-9 provides display commands or instruction code for the LCD. Refer to the Table

Notes for additional information.

Table 2-9: Instruction Code

Instruction

Item Symbol

Enable cycle time t

Enable rise and fall time t

Address hold time t

Data setup time t

Data hold time t

Code

Standard

Unit

Minimum Maximum

E500 ns

CYC

230 ns

20 ns
40 ns
10 ns
80 ns
10 ns

ER

DSW

, t

AS

AH

H

EH

EF

Maximum

Execution

Description

(Notes 2 and 3)

Time

(Note 1)

Clear

Display

Return

Home

Entry
Mode

Set

Display

On/Off

Control

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

000000 0 0 0 1Clears entire display and sets

Data Display RAM (DDR)
address 0 in the address
counter.

000000 0 0 1 *Sets DDR address0 in the

address counter. Also returns
display being shifted to
original position. DDR
contents remain unchanged.

000000 0 1I/DSSets cursor move direction

and specifies shift of display.
These operations are
performed during data write
and read.

000000 1 D CBSets ON/OFF of entire

display (D), cursor ON/OFF
(C), and blink of cursor
position character (B).

µs -

82

1.64 ms

µs -

40

1.6 ms

µs –

40

1.64 ms

µs

40

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Table 2-9: Instruction Code

Instruction

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Code

Chapter 2: Architecture

Description

(Notes 2 and 3)

Maximum

Execution

Time

(Note 1)

Cursor or

Display

Shift

Function

Set

Set
CG RAM
Address

Set
DD RAM
Address

Read

Busy Flag

and

Address

Write Data

to CG

or DDR

000001S/CR/L* *Moves cursor and shifts

40 µs
display without changing
DDR contents.

00001DLN F * *Sets interface data length (DL),

40

number of display lines (L),
and character fonts (F).

0001 A

CC

Sets Character Generator

40 µs
RAM (CGR) address. CGR
data is sent and received after
this setting.

00 1 A

DD

Sets DDR address. CGR data

40 µs
is sent and received after this
setting.

01BF A

C

Reads Busy flag (BF)

1 µs
indicating internal operation
is being performed and reads
address counter contents.

1 0 Write Data Writes data into DDR or CGR. 40

µs

µs

*Not applicable

Notes:

1.Maximum execution time is when f
changes.

2.DD RAM: Display data RAM
CG RAM: Character generator RAM
A

: CG RAM address

CG

A

: DDR address - corresponds to cursor address

DD

A

: Address counter used for both DDR and CG RAM address

C

I/D = 1: Increment or I/D = 0: Decrement
S = 1: Display shi ft or S = 0: No Display shift
D=1: Display ON or D=0: Display OFF
C = 1: Cursor ON or C = 0: Cursor OFF
B = 1: Blink ON or B = 0: Blink OFF
S/C = 1: Display shift or S/C = 0: Cursor move
R/L = 1: Shift to the right or R/L = 0: Shift to the left
DL = 1: 8 bits or DL = 0: 4 bits
N=1: 2lines
F=0: 5x 7 dots
BF = 1: In ternally operatin g or BF = 0: Can accept instruction

cp

or f

is 250 kHz. Execution time changes when frequency

osc

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Block Descriptions

R

Initialization
Flow Chart

Power On

≥ 15 mS

38 (Hex)

≥ 4.1 mS

38 (Hex)

≥ 100 uS

38 (Hex)

≥ 40 uS

38 (Hex)

≥ 40 uS

06 (Hex)

≥ 40 uS

0E (Hex)

≥ 40 uS

01 (Hex)

≥ 1.64 uS

End of
Initialization

80 (Hex)

≥ 40 uS

Hex Code D

R
E
S
E
T

S
E
Q
U
E
N
C
E

(1)

(2)

38 (Hex)

06 (Hex)

(1)

(2)

(3)

0E (Hex)

(3)

(4)

(4)

01 (Hex)

(5)

80 (Hex)

(5)

7D6D5D4D3D2D1D0

0

01

0000

0

00

1

00000

0

00

1

1000

00

1

0

0000

11

1

1

Function Set

8-bit Data Length

2 Line

5 x 7 Dot Format

Entry Mode Set

Increment One

No Shift

000

Display On/Off Control

Display On

Cursor On

Blink Off

1

Display Clear

Figure 2-3: Display Initialization Sequence

DD RAM Address Set

1st Digit

ug066_c2_03_060804

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Chapter 2: Architecture

Figure 2-4: LCD Panel Character Set

ug066_c2_04_060704

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Power

Power

Product Not Recommended for New Designs

Power Distribution

The ML365 board uses a 5V +/- 10% input voltage source to generate all the on-board
voltages (1.5V, 1.8V, 2.5V, and 3.3V).

Input Voltage

The input voltage is specified at 5 V @ 6.5 A. The recommended power supply is a CUI Inc.
DTS050650UTC-PSP-SZ. The jack used is a 2 mm. barrel jack. The slide switch turns the
power on or off. Four regulators on the board provide different voltages required by
various components on the board.

3.3 V Generation

The Texas Instruments PT5501N voltage regulator generat es the 3.3 V @ 3 A power. This
power regulator is packaged in a 5-pin, thermally-efficient copper case that is solderable,
and provides the auxiliary supply for some of the FPGA I/Os (V

CCO

).

R

2.5 V Generation

The Texas Instruments PT5502N voltage regulator generat es the 2.5 V @ 3 A power. This
power regulator is packaged in a 5-pin, thermally-ef ficient copper case that is solderable. It
supplies the clock oscillators, System Ace device, LCD Display unit, and for some of the
FPGA I/Os (V

CCAUX

).

1.8 V Generation

The Texas Instruments TSP54810 voltage regulator generates the 1.8 V @ 8 A power. This
power regulator has a thermally-enhanced 28-pin TSSOP package, and supplies the
memory devices.

1.5 V Generation

The Texas Instruments PT5505N voltage regulator generat es the 1.5 V @ 3 A power. This
power regulator is packaged in a 5-pin, thermally-efficient copper case that is solderable,
and provides the core voltage to the FPGA (V

CCINT

).

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FPGA Configuration

The demonstration board FPGA programming options are very flexible (refer to the
following five configuration modes). For a detailed explanation of the basic Virtex-II
configurations, refer to the Virtex-II Platform FPGA User Guide. The five Virtex-II
configuration modes are:

• Master Serial mode (not used on QDR II Demo Board)

• Slave Serial / SystemAce mode (QDR II Demo Board default)

• Master SelectMap mode

• Slave SelectMap mode

• JT AG mode

Selecting the Configuration Mode

The FPGA programming modes are set with the mode lines (M0, M1, M2) by means of the
3-pole DIP switch (SW5). Table 2-10 shows the programming modes.

Chapter 2: Architecture

Table 2-10: Configuration Modes Supported on the QDR II SRAM Demonstration Board

Mode M2 M1 M0 CCLK Data Width Data DOUT

Master Serial

Slave Serial 1 1 1 In 1 Yes

SystemAce

Master SelectMap 011 Out 8 No

Slave SelectMap 110 In 8 No

JTAG 101 N/A 1 No

(1)

(2)

1. Not used on QDR II Demonstration Board.

2. SystemAce is a Slave Serial configuration mode, and is the default for the QDR II Demonstration Board.

An LED on the Done pin adds a visual aid to detect a good FPGA configuration. If the LED
is “on”, the FPGA configuration is complete.

000 Out 1 Yes

111 N/A N/A N/A

Serial Configuration

The Virtex-II is programmable in serial mode in one of two ways:

Master Serial Mode

This mode is not used in the QDR II Demonstration Board.

Slave Serial Mode

In Slave Serial Mode, the FPGA CCLK pin is driven by an external source. The FPGA is
configured by loading one bit per CCLK cycle in the DIN pin.

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FPGA Configuration

SystemAce Configuration (Default Mode)

R

SystemAce is a Slave Serial configuration mode, and is the default mode for the QDR II
Demonstration Board.

If the SystemAce Controller (U2) detects a Compact Flash card present in sock et P2, it
attempts to load a configuration file from the Compact Flash card into the FPGA.

Table 2-11 shows the allowable correct jumper positions.

Table 2-11: Jumper Positions for SystemAce Configuration

Pins Jumpered Function

P1.4 to P113 TCK from SystemAce connected to TCK input of the FPGA
P1.7 to P114 TMS from SystemAce connected to TMS input of the FPGA
P1.5 to P1.6 SystemAce TDO connected to the TDI input of the FPGA

1. Recommended SW5 switch setting for the SystemAce mode is 111; refer to Table 2-10.

SelectMap Configuration

The Virtex-II FPGA is programmable us ing SelectMap, a parallel configuration mode. In
this mode, two possibilities of programming exist:

• Master Mode: FPGA delivers the CCLK download clock

• Slave Mode: FPGA must receive the CCLK clock from the external device

The demonstration board can be programmed in both modes using the SelectMap
connectors; P99 and P111. The FPGA on the demonstration board can be programmed in
slave mode using a MultiLINX cable, or in Master mode when an external device is
plugged into these connectors.

The SelectMap connector P99 carries FPGA bits [7:0]. When SelectMap is not used, the
SelectMap connector pins can also be used as normal I/O.

Figure 2-5 shows the layout of the SelectMap connectors P99 and P111.

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Chapter 2: Architecture

FPGA CS#

FPGA RFWR#

P99

1

3

5

7

9

11 12

13 14

15

17

SelectMAP Header

2

4

6

8

10

16

18

FPGA BUSY

FPGA D0

FPGA D1

FPGA D2

FPGA D3

FPGA D4

FPGA D5

FPGA D6

FPGA D7

1

2

3

4

5

6

7

8

9

Header 9

Figure 2-5: SelectMap Connectors P99 and P111

P111

5V

GND

CCLK

DONE

DIN

PROG

INIT

ug066_c2_05_060804

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FPGA Configuration

JTAG Configuration

The Virtex-II FPGA is programmable in JTAG mode. The JTAG chain contains two on­board devices (FPGA and SystemAce).

The JT AG input connector is P103, wir ed to the TSTCFG pins of the Sys temAce Contr oller
U2. The JT AG input connector is the start of the JT AG chain. The configuration output port
of the SystemAce Controller is wired to the FPGA via P1, P113, and P114 pins as shown in

Table 2-11. The FPGA can be isolated from the JTAG chain by removing the jumper blocks

from the P1 pins as specified in Table 2-11. Figure 2-6 shows how to build the JTAG chain,
and Table 2-12 shows the connections for the JTAG connector P1.

+5 V +2.5 V

P111

1
2

P26

PROG_B

CCLK

DIN

PROG

INIT

3
4
5
6
7
8
9

SYSACE_TDO

TCK

TMS

FPGA_TDO

+3.3 V

R

+3.3 V

Pushbutton

SW6

1

DIP Switch

SW5

SYSACE_CFGPROG#

SYSACE_CFGINIT#

10K
Resistors (4)

AH8

CCLK

D30

PROG_B

AL5

IO_L01P_4/INIT_B

AJ7

DONE

AH27

M0

AJ28

M1

AK29

M2

F29

HSWAP_EN

F7

TCK

U1I

XC2V3000

Figure 2-6: SystemAce and JTAG Connectors

Table 2-12: JTAG Connector Pins (P1)

Pin

Number

Function

1 3.3 Volts
2GND
3N/C

TDI
TDO
TMS

PWRDWN_B

DXN

DXP

VBATT

RSVD

D5
F6
AK6
F28
G27
C4
G8

FPGA_TDIC31

FPGA_TDO

TMS

TDO
TCK

ug066_c2_06_062804

P1
7
6
5
4
3
2
1

4TCK
5TDO
6FPGA_TDI
7TMS

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Figure 2-7 shows the JTAG connector P103.

Chapter 2: Architecture

NC

NC

NC

1

2

3

4

5

P103

6

7

8

9

3.3V

GND

TCK

TDO

TDI

TMS

ug124_07_0603_04

Figure 2-7: JTAG I/O Connector P103

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Electrical Requirements

Power Consumption

Table 3-1 lists the operating voltages, maximum currents, and power consumption used by

the ML365 board devices. Refer to Appendix 1, “Related Documentation,” for more
information on the source material.

Table 3-1: ML365 Power Consumption

Chapter 3

1

Voltag e

(V)

1.8 7236 1 3 Virtex-II Pro User Guide

Device Quantity

Total Available Power

Power Supply 1 5 6500 32.5

FPGA Power (Based on Design)

FPGA (XC2VP20-6 FF1152) 1 6.87 Power Estimator Tool
Board Power
Static Power-on Termination

Resistors (Split 100 ohms)
QDR SRAM (108-bit interface) 3 1.8 800 4.32 Samsung QDR SRAM Data Sheet
200 MHz LVPECL Clock

Oscillator
16-pin GPIO Header 2 2.6 160 .42 Average 10 mA * 16 pins
LEDs 11 — — 0.5 LED Circuits
DIP Switch 1 — — .06 Eight 3.3 kohm pullups
RS232 Serial Port 1 3.3 40 0.13 Maxim MAX3316ECUP Data Sheet
LCD — 2.5/3.3 100 0.33 LCD Datasheet

402

2 4 80 0.64 EPSON EG2121CA Data Sheet

Current

(mA)

Power

(W)

Source

System Ace Compact Flash — 2.5/3.3 150 .049 SystemACE Datasheet

Worst Case Power Consumption: 23.0

1. The resistor count is distributed as follows per devices, and multiplied by the number of devices (3):

- data bus D: 36 (x2 (split termination))

- clocks: CQ, C, K: 6 (x2 (split termination) )

- address bus A: 18 (x2 (split termination))

- R_n_int: 1 (x2 (split termination))

- Control signals: 6 (x2 (split termination))

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FPGA Internal Power Budget

The following tables show the power consumption values inside the FPGA based on the
complete QDR design. These results are derived using the Xilinx Power Estimator tool.
Block Select RAM, Block Multiplier, Processor, and MGT Power tables are not included in
this section as they are not used in this application.

• Table 3-2, “XC2VP20FF1152 Estimated Power Consumption,” page 30

• Table 3-3, “XC2VP20FF1152 Temperature Specifications,” page 30

• Table 3-4, “Device Quiescent Power,” page 30

• Table 3-5, “CLB Logic Power,” page 31

• Table 3-6, “D ig ital Clock Manager Power,” page 31

• Table 3-7, “Input/Output Power,” page 31

Table 3-2: XC2VP20FF1152 Estimated Power Consumption

Parameter Value Units

Total Estimated Design Power 6500 mW
Estimated Design VCC
Estimated Design VCC
Estimated Design VCCO 3.3 V Power 100 mW
Estimated Design VCCO 2.5 V Power 173 mW
Estimated Design VCCO 1.8V Power 7859 mW
Estimated Design VCCO 1.5 V Power 0 mW
Estimated Design VCCO 1.2 V Power 0 mW

Table 3-3: XC2VP20FF1152 Temperature Specifications

Parameter Value Units

Ambient Temperature 25 °C
Air Flow 0 LFM
Junction Temperature 107 °C

Table 3-4: Device Quiescent Power

VCC

Subtotal (mW) VCC

INT

1.5 V Power 3500 mW

INT

2.5 V Power 417 mW

AUX

Subtotal (mW)

AUX

450 417

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