Xilinx MIPI CSI-2 Product Manual
MIPI CSI-2 Receiver
Subsystem v4.0
Product Guide
Vivado Design Suite
PG232 July 02, 2019
Table of Contents
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IP Facts
Chapter 1: Overview
Sub-Core Details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Unsupported Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Licensing and Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Chapter 2: Product Specification
Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Resource Utilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Register Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Chapter 3: Designing with the Subsystem
General Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Shared Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
I/O Planning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Protocol Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Chapter 4: Design Flow Steps
Customizing and Generating the Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Constraining the Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Synthesis and Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Chapter 5: Application Example Design
Application Example Design Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Setup Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Implementing the Example Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
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Appendix A: Verification, Compliance, and Interoperability
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Hardware Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Appendix B: Debugging
Finding Help on Xilinx.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Debug Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Hardware Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Interface Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Appendix C: Additional Resources and Legal Notices
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Documentation Navigator and Design Hubs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
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IP Facts
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Introduction
The Mobile Industry Processor Interface (MIPI)
Camera Serial Interface (CSI-2) RX subsystem
implements a CSI-2 receive interface according
to the MIPI CSI-2 standard v2.0 [Ref 1] with
underlying MIPI D-PHY standard v1.2. The
subsystem captures images from MIPI CSI-2
camera sensors and outputs AXI4-Stream video
data ready for image processing. The
subsystem allows fast selection of the top level
parameters and automates most of the lower
level parameterization. The AXI4-Stream video
interface allows a seamless interface to other
AXI4-Stream-based subsystems.
Features
• Support for 1 to 4 D-PHY lanes
• Line rates ranging from 80 to 2500Mb/s
• Multiple Data Type support (RAW, RGB, YUV)
• AXI IIC support for Camera Control
Interface (CCI)
• Filtering based on Virtual Channel Identifier
• Support for 1, 2, or 4 pixels per sample at
the output as defined in the Xilinx
AXI4-Stream Video IP and System Design
Guide (UG934) [Ref 2] format
• AXI4-Lite interface for register access to
configure different subsystem options
• Dynamic selection of active lanes within the
configured lanes during subsystem
generation.
• Support for MIPI CSI-2 standard v2.0
features such as VCX, RAW16, and RAW20
IP Facts Table
Subsystem Specifics
UltraScale+™,
Supported
Device Family
Supported User
Interfaces
Resources Performance and Resource Utilization web page
(1)
Zynq® UltraScale+ MPSoC,
Zynq®-7000 SoC,
7 Series FPGAs
AXI4-Lite, AXI4-Stream
Provided with Subsystem
Design Files Encrypted RTL
Example Design Vivado IP Integrator
Test Bench Not Provided
Constraints File XDC
Simulation
Model
Supported
S/W Driver
(2)
Tested Design Flows
Design Entry Vivado® Design Suite
Simulation
Synthesis Vivado Synthesis
For supported simulators, see the
Xilinx Design Tools: Release Notes Guide.
Not Provided
Standalone and Linux
(3)
Support
Provided by Xilinx at the Xilinx Support web page
Notes:
1. For a complete list of supported devices, see the Vivado IP
catalog.
2. Standalone driver details can be found in the SDK directory
(<install_directory>/SDK/<release>/data/embeddedsw/doc/
xilinx_drivers.htm). Linux OS and driver support information
is available from the
Xilinx Wiki page.
3. For the supported versions of the tools, see the
Xilinx Design Tools: Release Notes Guide.
• Interrupt generation to indicate subsystem
status information
• Internal D-PHY allows direct connection to
image sources
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Overview
AXI Crossbar
AXI IIC
Video
Format
Bridge
MIPI CSI-2 RX
Controller
MIPI D-PHY
Video Interface
(AXI4-Stream)
Embedded Non-Image
Interface (AXI4-Stream)
csirxss_csi_irq
csirxss_iic_irq
Serial Interface
AXI4-Lite Interface
IIC Interface
PPI
dphy_clk_200M
lite_aclk
lite_aresetn
video_aclk
video_aresetn
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The MIPI CSI-2 RX subsystem allows you to quickly create systems based on the MIPI
protocol. It interfaces between MIPI-based image sensors and an image sensor pipe. An
internal high speed physical layer design, D-PHY, is provided that allows direct connection
to image sources. The top level customization parameters select the required hardware
blocks needed to build the subsystem. Figure 1-1 shows the subsystem architecture.
X-Ref Target - Figure 1-1
Chapter 1
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Figure 1-1: Subsystem Architecture
The subsystem consists of the following sub-cores:
•MIPI D-PHY
• MIPI CSI-2 RX Controller
• AXI CrossbarVideo Format Bridge
•AXI IIC
Chapter 1: Overview
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Sub-Core Details
MIPI D-PHY
The MIPI D-PHY IP core implements a D-PHY RX interface and provides PHY protocol layer
support compatible with the CSI-2 RX interface. The MIPI D-PHY IP core also supports the
deskew pattern detection for line rates >1.5 Gb/s. See the MIPI D-PHY LogiCORE IP Product
Guide (PG202) [Ref 3] for details. MIPI D-PHY implementation differs for the UltraScale+
devices and the 7 Series devices with respect to I/O.
For UltraScale+ devices, the Vivado IDE provides a Pin Assignment Tab to select the
required I/O. However, for the 7 series devices the clock capable I/O should be selected
manually. In addition, the 7 series devices do not have a native MIPI IOB support. You will
have to target either HR bank I/O or HP bank I/O for the MIPI IP implementation. For more
information on MIPI IOB compliant solution and guidance, refer D-PHY Solutions (XAPP894)
[Ref 15].
MIPI CSI-2 RX Controller
The MIPI CSI-2 RX Controller core consists of multiple layers defined in the MIPI CSI-2 RX
1.1 specification, such as the lane management layer, low level protocol and byte to pixel
conversion.
The MIPI CSI-2 RX Controller core receives 8-bit data per lane, with support for up to 4
lanes, from the MIPI D-PHY core through the PPI. As shown in Figure 1-1 the byte data
received on the PPI is then processed by the low level protocol module to extract the real
image information. The final extracted image is made available to the user/processor
interface using the AXI4-Stream protocol. The lane management block always operates on
32-bit data received from PPI irrespective number of lanes.
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Chapter 1: Overview
PHY Protocol
Interface
(PPI)
Lane
Management
Control
FSM
PHECC
Processing
Data
Processing
CRC
Checker
Buffer
AXI4-
Stream
Register
Interface
AXI4-Stream
PPI
AXI4-Lite
Interrupt
X16317-031116
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X-Ref Target - Figure 1-2
Figure 1-2: MIPI CSI-2 RX Controller Core
Features of this core include:
• 1–4 lane support, with register support to select active lanes (the actual number of
available lanes to be used)
• Short and long packets with all word count values supported
• Primary and many secondary video formats supported
• Data Type (DT) interleaving
• Virtual Channel Identifier (VC) interleaving
• Combination of Data Type and VC interleaving
• Multi-lane interoperability
• Error Correction Code (ECC) for 1-bit error correction and 2-bit error detection in
packet header
• CRC check for payload data
• Long packet ECC/CRC forwarding capability for downstream IPs
• Maximum data rate of 2.5 Gb/s
• Pixel byte packing based on data format
• AXI4-Lite interface to access core registers
• Low power state detection
• Error detection (D-PHY Level Errors, Packet Level Errors, Protocol Decoding Level Errors)
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• AXI4-Stream interface with 32/64-bit TDATA width support to offload pixel information
externally
• Interrupt support for indicating internal status/error information
Chapter 1: Overview
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As shown in Tab le 1-1 the embedded non-image (with data type code 0x12) AXI4-Stream
interface data width is selected based on the Data Type selected.
Table 1-1: Embedded Non-Image AXI4-Stream Interface TDATA Widths
Data Type (DT) AXI4-Stream Interface TDATA Width
RAW6 32
RAW7 32
RAW8 32
RAW10 64
RAW12 64
RAW14 64
RAW16 64
RAW20 64
All RGB 64
YUV 422 8–bit 64
YUV 422 10–bit 64
Abrupt termination events such as a soft reset, disabling a core while a packet is being
written to the line buffer, or a line buffer full condition results in early termination. The
termination is implemented by assertion of EOL on the video interface or TLAST and
TUSER[1] on the embedded non-image interface, based on the current long packet being
processed.
ECC/CRC Forwarding
Sideband signals of AXI4-Stream interface [Include/Exclude Video Format Bridge and
Embedded non-image interface] report E CC an d CRC data receive d from th e source [s e nsor]
to downstream IPs. This allows to re-calculate ECC/CRC by the downstream IPs in certain
functional safety applications. See Port Descriptions for details on signal mapping.
In error scenarios like abrupt termination due to soft reset, disabling the core while packet
transfer in progress, line buffer in full condition, word count of received packet is greater
than the actual payload, these sideband signals do not report the correct ECC and CRC.
VCX Support
The MIPI CSI-2 standard v2.0 specific VCX support feature is used to extend the maximum
number of available virtual channels to 16. When this feature is enabled, the virtual channel
is deduced by combining the 2-bit VC field (LSB) and the 2-bit VCX field (MSB) from the
packet header.
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Chapter 1: Overview
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AXI Crossbar
The AXI Crossbar core is used in the subsystem to route AXI4-Lite requests to
corresponding sub-cores based on the address. See the AXI Interconnect LogiCORE IP
Product Guide [Ref 4] for details.
Video Format Bridge
The Video Format Bridge core uses the user-selected VC and Data Type information to filter
onl y the re quired AXI4- Stre am dat a beats . This AXI4-Strea m data is further processed based
on the Data Type information and the output is based on the requested number of pixels
per beat. The output interface adheres to the protocol defined in the AXI4-Stream Video IP
and System Design Guide (UG934) [Ref 2].
The Video Format Bridge core processes the data type selected in the Vivado Integrated
Design Environment (IDE) and filters out all other data types except for RAW8 and User
Defined Byte-based Data types (0x30 to 0x37) received from the CSI-2 RX Controller.
Irrespective of the Vivado IDE selection, RAW8 and User Defined Byte-based Data types are
always processed by the Video Format Bridge core. This allows multiple data-type support,
one main data-type from the Vivado IDE for pixel data and a User Defined Byte-based Data
type for metadata. When multiple data types are transferred (for example, RAW10 and User
Defined Byte-based Data) the actual placement pixel data bits are defined in the
AXI4-Stream Video IP and System Design Guide (UG934) [Ref 2].
For unaligned transfers there is no way to specify the partial final output (TKEEP) for the
output interface. Ensure that you take this into consideration and discard the unintended
bytes in the last beats when there are un-aligned transfers.
video_out Port Width
The width of the data port in the video_out interface depends on the data type selected
and number of pixels per beat selected. The width is a maximum of the RAW8 and the data
type selected in the Vivado IDE multiplied by number of pixels per beat. This is then
rounded to the nearest byte boundary as per the AXI4-Stream protocol.
Example 1: RAW10 and Two Pixels per Clock Selected in the Vivado IDE
• Single pixel width of RAW10 =10
• Single pixel width of RAW8 = 8
For the selected two pixels per clock, the effective pixels widths are 20 and 16 for RAW10
and RAW8 respectively. The video_out port width is configured as the maximum of the
individual pixel widths, and rounded to the nearest byte boundary. This results in a
video_out port width of 24.
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Chapter 1: Overview
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Example 2: RAW7 and Four Pixels per Clock Selected in the Vivado IDE
• Single pixel width of RAW7 = 7
• Single pixel width of RAW8 = 8
With four pixels per clock selected, the effective pixels widths are 28 and 32 for RAW7 and
RAW8 respectively. The video_out port width is configured as the maximum of the
individual pixel widths, and rounded to nearest byte boundary. This results in a video_out
port width of 32.
Pixel Packing for Multiple Data Types
When multiple pixels are transferred with different pixel width, the pixels with lower width
are justified to most significant bits.
Example 1
When RAW12 and RAW8 are transferred with two pixels per clock, the data port width of the
video_out interface is 24-bits. Within the 24-bits the RAW8 pixels are aligned to the most
significant bits as shown in the following table:
IMPORTANT: In a multi pixel scenario pixel width varies, pixels with lower width are justified to the
most significant bit.
Table 1-2: Pixel Packing for RAW12 and RAW8 Data Types
Bit Positions23222120191817161514131211109876543210
RAW12
RAW8
Notes:
1. p0 to p11 is the 1st pixel bits of RAW12; q0 to q11 is the 2nd pixel bits of RAW12.
2. p0 to p7 is the 1st pixel bits of RAW8; q0 to q7 is the 2nd pixel bits of RAW8.
q11 q10 q9 q8 q7 q6 q5 q4 q3 q2 q1 q0 p11 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 p0
q7 q6 q5 q4 q3 q2 q1 q0 p7 p6 p5 p4 p3 p2 p1 p0
Example 2
When the core is configured with RAW6 and two pixels per clock, the video_out port
width is set to 16-bits. Within the 16-bits the RAW6 and RAW8 pixels are aligned to the
most significant bits as shown in the following table:
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Table 1-3: Pixel Packing for RAW8 and RAW6 Data Types
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Chapter 1: Overview
Bit
Positions
RAW8
RAW6
Notes:
1. p0 to p7 is the 1st pixel bits of RAW8; q0 to q7 is the 2nd pixel bits of RAW8.
2. p0 to p5 is the 1st pixel bits of RAW6; q0 to q5 is the 2nd pixel bits of RAW6.
15141312111098765 4 3 2 1 0
q7 q6 q5 q4 q3 q2 q1 q0 p7 p6 p5 p4 p3 p2 p1 p0
q5 q4
q3 q2 q1 q0
p5 p4 p3 p2 p1 p0
Pixel Packing for Embedded Non-Image Data Types
AXI4-Stream TDATA width is based on main data type selected from the Vivado® IDE. The
position of embedded non-image data type bytes on emb_nonimg_tdata are listed
below:
• 1st byte on emb_nonimg_tdata[7:0]
•2nd byte on emb_nonimg_tdata[15:8] and so on.
Pixel Packing When Video Format Bridge is Not Present
The width of the data port in the video_out can be selected from Vivado IDE, under CSI-2
Options TDATA width. MI P I CSI-2 RX Subsyste m follows t he Recommended Memory Storage
section of the MIPI CSI-2 specifications to output pixels, when a video format bridge is not
present.
For more information the data type packing, refer MIPI Alliance Standard for Camera Serial
Interface CSI-2 Specification [Ref 1].
Example
Pixel mapping for different data types are shown in the following table:
Table 1-4: Pixel Packing for RAW8 Data Type
Bit
Position
RAW8
Notes:
1. p0 to p7 is the 1st pixel bits of RAW8; q0 to q7 is the 2nd pixel bits of RAW8.
Table 1-5: Pixel Packing for RAW10 Data Type
Position
RAW10
RAW10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
s7 s6 s5 s4 s3 s2 s1 s0 r7 r6 r5 r4 r3 r2 r1 r0 q7 q6 q5 q4 q3 q2 q1 q0 p7 p6 p5 p4 p3 p2 p1 p0
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
s9 s8 s7 s6 s5 s4 s3 s2 r9 r8 r7 r6 r5 r4 r3 r2 q9 q8 q7 q6 q5 q4 q3 q2 p9 p8 p7 p6 p5 p4 p3 p2
v9 v8 v7 v6 v5 v4 v3 v2 u9 u8 u7 u6 u5 u4 u3 u2 t9 t8 t7 t6 t5 t4 t3 t2 s1 s0 r1 r0 q1 q0 p1 p0
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Chapter 1: Overview
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Table 1-5: Pixel Packing for RAW10 Data Type
Bit
Position
RAW10
Notes:
1. In RAW10, MSB 8-bits of 4 pixels are transferred first, followed by LSB 2-bits of each pixel.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
y9 y8 y7 y6 y5 y4 y3 y2 x9 x8 x7 x6 x5 x4 x3 x2 w1 w0 v1 v0 u1 u0 t1 t0 w9 w8 w7 w6 w5 w4 w3 w2
Table 1-6: Pixel Packing for RGB888 Data Type
Bit
Position
RGB888
RGB888
Notes:
1. In RGB888, a0 to a7 represents the B component, b0 to b7 represents the G component and c0 to c7 represents the R
313029282726252423222120191817161514131211109876543210
d7 d6 d5 d4 d3 d2 d1 d0 c7 c6 c5 c4 c3 c2 c1 c0 b7 b6 b5 b4 b3 b2 b1 b0 a7 a6 a5 a4 a3 a2 a1 a0
h7 h6 h5 h4 h3 h2 h1 h0 g7 g6 g5 g4 g3 g2 g1 g0 f7 f6 f5 f4 f3 f2 f1 f0 e7 e6 e5 e4 e3 e2 e1 e0
component.
AXI IIC
The Camera Control Interface (CCI) of the MIPI CSI-2 specification is compatible with the
fast mode variant of the I2C interface with 400 kHz operation and 7-bit slave addressing.
The AXI IIC is made available as part of this subsystem depending on user selections. See
the AXI IIC Bus Interface v2.0 LogiCORE IP Product Guide (PG090) [Ref 5] for details.
Applications
The Xilinx MIPI CSI-2 RX controller implements a Camera Serial Interface between a camera
sensor and a programmable device performing baseband processing. Bandwidth
requirement for the camera sensor interface has gone up due to the development of higher
resolution cameras. Traditional parallel interfaces require an increasing number of signal
lines resulting in higher power consumption. The new high speed serial interfaces, such as
MIPI CSI specifications, address these expanding bandwidth requirements without
sacrificing power. MIPI is a group of protocols defined by the mobile industry group to
standardize all interfaces within mobile platforms such as mobile phones and tablets.
However the large volumes and the economies of scale of the mobile industry is forcing
other applications to also adopt these standards. As such MIPI-based camera sensors are
being increasingly used in applications such as driver assistance technologies in automotive
applications, video security surveillance cameras, video conferencing and emerging
applications such as virtual and augmented reality.
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Chapter 1: Overview
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Unsupported Features
• Some YUV Data Types (YUV 420 (8-bit and 10-bit)) are not supported when the Video
Format Bridge is included.
• Dynamic linerate is not supported.
• 8 lanes support is not included.
• Data scramble feature is not supported.
• Latency reduction and transport efficiency features are not supported.
Licensing and Ordering
License Checkers
If the IP requires a license key, the key must be verified. The Vivado® design tools have
several license checkpoints for gating licensed IP through the flow. If the license check
succeeds, the IP can continue generation. Otherwise, generation halts with error. License
checkpoints are enforced by the following tools:
• Vivado synthesis
• Vivado implementation
• write_bitstream (Tcl command)
IMPORTANT: IP license level is ignored at checkpoints. The test confirms a valid license exists. It does
not check IP license level.
License Type
This Xilinx module is provided under the terms of the Xilinx Core License Agreement. The
module is shipped as part of the Vivado® Design Suite. For full access to all core
functionalities in simulation and in hardware, you must purchase a license for the core.
Contact your local Xilinx sales representative for information about pricing and availability.
For more information, visit the MIPI CSI-2 RX Subsystem product web page.
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Product Specification
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Standards
• MIPI Alliance Standard for Camera Serial Interface CSI-2 v1.1 [Ref 1]
•MIPI Alliance Physical Layer Specifications, D-PHY Specification v1.1 [Ref 6]
• Processor Interface, AXI4-Lite: see the Vivado Design Suite: AXI Reference Guide
(UG1037) [Ref 7]
• Output Pixel Interface: see the AXI4-Stream Video IP and System Design Guide (UG934)
[Ref 2]
Chapter 2
Performance
This section details the performance information for various core configurations.
Latency
The CSI2 RX Subsystem core latency is the time from the start-of-transmission (SoT) pattern
on the serial lines to the tvalid signal assertion at CSI-2 Rx Subsystem output. This includes
the D-PHY latency, MIPI RX Controller latency and VFB latency (if Video Format Bridge is
included in the Subsystem).
Figure 2-1 represents the latency calculation for the subsystem
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Chapter 2: Product Specification
D-PHY latency:
The MIPI D-PHY RX core latency is the time from the start-of-transmission (SoT) pattern on
the serial lines to the activehs signal assertion on the PPI .The HS_SETTLE period contributes
significantly in the D-PHY latency calculation.
Tab le 2-1 provides the latency numbers for various core configurations.
Table 2-1: D-PHY Latency
Data Type Pixel Mode Line Rate
RAW20 Single
RAW8 Single
RAW8 Dual
RAW8 Quad
RAW10 Single
Figure 2-1: MIPI CSI2 RX Subsystem Latency Calculation
Latency in
rxbyteclk
(HS_SETTLE +
internal latency)
1000 26(23+3)
1000 26(23+3)
1000 26(23+3)
1000 26(23+3)
1000 26(23+3)
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RAW10 Dual
RAW10 Quad
Notes: All the calculations are made for a single lane design with a fixed
video clock of 148 MHz.
1200 30(26+4)
800 22(20+2)
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MIPI CSI-2 RX Controller latency:
The MIPI CSI-2 RX Controller core latency is the time from the activehs assertion on the PPI
Interface to valid signal assertion on the controller output.
Tab le 2-2 provides the latency numbers for various core configurations.
Table 2-2: MIPI CSI2 RX Controller latency
Data Type Pixel Mode Line Rate
RAW20 Single
RAW8 Single
RAW8 Dual
RAW8 Quad
RAW10 Single
RAW10 Dual
RAW10 Quad
Notes: All the calculations are made for a single lane design with a fixed video clock of 148
MHz.
1000 25 60
1000 21 49
1000 21 49
1000 21 49
1000 25 60
1200 26 63
800 24 56
Latency in
rxbyteclk
Latency in Video
Clock
Video Format Bridge (VFB) latency:
The VFB core latency is the time time from the VFB input stream interface ‘tvalid’ to VFB
output stream interface ‘tvalid’.
Tab le 2-3 provides the latency numbers for various core configurations.
Table 2-3: VFB latency
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Data Type Pixel Mode Line Rate
RAW20 Single
RAW8 Single
RAW8 Dual
RAW8 Quad
RAW10 Single
RAW10 Dual
RAW10 Quad
Notes: All the calculations are made for a fixed video clock of 148 MHz.
1000 10 24
1000 1 3
1000 1 3
1000 1 4
1000 2 6
1200 3 6
800 1 3
Latency in
rxbyteclk
Latency in Video
Clock
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Tab le 2-4 provides the overall latency numbers of MIPI CSI2 RX Subsystem for various core
configurations.
Table 2-4: MIPI CSI2 RX Subsystem Latency
Data Type Pixel Mode Line Rate
RAW20 Single
RAW8 Single
RAW8 Dual
RAW8 Quad
RAW10 Single
RAW10 Dual
RAW10 Quad
Notes:
1. All the calculations are made for a single lane design with a fixed video
clock of 148 MHz.
2. The latency is improved by increasing the number of lanes.
1000 61
1000 48
1000 48
1000 48
1000 53
1200 59
800 47
Latency in
rxbyteclk
Resource Utilization
For full details about performance and resource utilization, visit the Performance and
Resource Utilization web page.
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Port Descriptions
The MIPI CSI-2 RX Subsystem I/O signals are described in Ta ble 2 - 5.
Table 2-5: Port Descriptions
Signal Name Direction Description
lite_aclk Input AXI clock
lite_aresetn Input AXI reset. Active-Low
S00_AXI*
dphy_clk_200M Input Clock for D-PHY core. Must be 200 MHz.
video_aclk Input Subsystem clock
video_aresetn
(1)
Input Subsystem reset. Active-Low.
AXI4-Stream Video Interface when Video Format Bridge is Present
video_out_tvalid Output Data valid
AXI4-Lite interface, defined in the Vivado Design Suite: AXI
Reference Guide (UG1037) [Ref 7]
Table 2-5: Port Descriptions (Cont’d)
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Signal Name Direction Description
video_out_tready Input Slave ready to accept the data
n is based on TUSER width selected in the Vivado IDE
95-80 CRC
79-72 ECC
71-70 Reserved
69-64 Data Type
(3)
Chapter 2: Product Specification
video_out_tuser[n-1:0] Output
video_out_tlast Output End of line
video_out_tdata[n-1:0] Output
video_out_tdest[9:0] Output
63-48 Word Count
47-32 Line Number
31-16 Frame Number
15-2 Reserved
1 Packet Error
0Start of Frame
Data
n is based on Data type and number of pixels selected in the
Vivado IDE (see video_out Port Width).
9-4 Data Type
3-0 Virtual Channel Identifier (VC)
(2)
AXI4-Stream Interface when Embedded Non-image Interface is Selected
Data
emb_nonimg_tdata[n-1:0] output
emb_nonimg_tdest[3:0] Output
n is based on Data type selected in the Vivado IDE (see
Tabl e 1- 1).
Specifies the Virtual Channel Identifier (VC) value of the
embedded non-image packet
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emb_nonimg_tkeep[n/8-1:0] Output Specifies valid bytes
emb_nonimg_tlast Output End of line
emb_nonimg_tready Input Slave ready to accept data
Table 2-5: Port Descriptions (Cont’d)
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Signal Name Direction Description
95-80 CRC
79-72 ECC
71-70 Reserved
69-64 Data Type
(3)
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emb_nonimg_tuser[95:0] Output
emb_nonimg_tvalid Output Data valid
63-48 Word Count
47-32 Line Number
31-16 Frame Number
15-2 Reserved
1 Packet Error
0 Start of frame
AXI4-Stream Interface when Video Format Bridge is Not Present
video_out_tdata[n-1:0] Output
video_out_tdest[n-1:0] Output
video_out_tkeep[n/8-1:0] Output Specifies valid bytes
video_out_tlast Output End of line
video_out_tready Input Slave ready to accept data
Data
n is based on TDATA width selected in the Vivado IDE.
n is based on TDEST width selected in the Vivado IDE:
9-4 Data type
3-0 Virtual Channel Identifier (VC)
n is based on TUSER width selected in the Vivado IDE
95-80 CRC
(3)
(2)
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79-72 ECC
71-70 Reserved
69-64 Data Type
video_out_tuser[n-1:0] Output
video_out_tvalid Output Data valid
63-48 Word Count
47-32 Line Number
31-16 Frame Number
15-2 Reserved
1 Packet Error
0 Start of frame
(2)
Other Signals
csirxss_csi_irq Output Interrupt (active-High) from CSI-2 RX Controller
csirxss_iic_irq Output Interrupt (active-High) from AXI IIC
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Table 2-5: Port Descriptions (Cont’d)
Signal Name Direction Description
Xilinx 7 series FPGA
mipi_dphy_if Output DPHY interface
rxbyteclkhs Output PPI high-speed receive byte clock
system_rst_out Output Reset indication due to PLL reset (active-High)
dlyctrl_rdy_out Output
clk_300m Input 300 MHz clock for IDELAYCTRL
Ready signal output from IDEALYCTRL, stating delay values
are adjusted as per vtc changes
UltraScale+ Shared Logic outside Subsystem
mipi_phy_if Output DPHY interface
rxbyteclkhs Output PPI high-speed receive byte clock
clkoutphy_out Output PHY serial clock
system_rst_out Output Reset indication due to PLL reset (active-High)
pll_lock_out Output PLL lock indication (active-High)
UltraScale+ Shared logic in the Subsystem
mipi_phy_if Output DPHY interface
Inferred bitslice ports. The core infers bitslice0 of a nibble for
strobe propagation within the byte group; <x> indicates byte
group (0,1,2,3); <y> indicates bitslice0 position (0 for the
lower nibble, 6 for the upper nibble)
bg<x>_pin<y>_nc Input
• RTL Design: There is no need to drive any data on these
ports.
• IP Integrator: These ports must be brought to the top level
of the design to properly apply the constraints.
Note:
Pins are available only for UltraScale+ families.
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clkoutphy_in Input PHY serial clock
pll_lock_in Input PLL Lock indication
rxbyteclkhs Output PPI high-speed receive byte clock
Notes:
1. The active-High reset for the MIPI D-PHY core is generated internally by setting the external
active-Low reset (video_aresetn) to 0.
2. Each frame start packet with Virtual Channel (VC) identifier will be mapped to the first image packet and the first
embedded non-image with the corresponding VC.
3. As CRC appears at the end of the MIPI packet, ECC and CRC are reported ONLY during the last beat of the stream
transfer when TLAST and TVALID are asserted. You need to ignore ECC/CRC reported during other beats of the
transfer. See Interface Debug for more details.
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Register Space
This section details registers available in the MIPI CSI-2 RX Subsystem. The address map is
split into following regions:
• MIPI CSI-2 RX Controller core
•AXI IIC core
•MIPI D-PHY core
Each IP core is given an address space of 64K. Example offset addresses from the system
base address when the AXI IIC and MIPI D-PHY registers are enabled are shown in Tabl e 2-6.
Table 2-6: Sub-Core Address Offsets
IP Cores Offset
MIPI CSI-2 RX Controller 0x0_0000
AXI IIC 0x1_0000
MIPI D-PHY 0x2_0000
(1)
Notes:
1. When the AXI IIC core is not present, the MIPI D-PHY offset moves up and starts at 0x1_0000. The software driver
handles this seamlessly.
MIPI CSI-2 RX Controller Core Registers
Tab le 2-7 specifies the name, address, and description of each firmware addressable
register within the MIPI CSI-2 RX controller core.
Table 2-7: MIPI CSI-2 RX Controller Core Registers
Address Offset Register Name Description
0x00 Core Configuration Register Core configuration options
0x04
0x08 Reserved
0x0C Reserved
0x10 Core Status Register Internal status of the core
0x14 Reserved
0x18 Reserved
0x1C Reserved
Protocol Configuration
Register
(1)
Protocol configuration options
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0x20
0x24 Interrupt Status Register Interrupt status register
Global Interrupt Enable
Register
Global interrupt enable registers
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Table 2-7: MIPI CSI-2 RX Controller Core Registers (Cont’d)
Address Offset Register Name Description
0x28 Interrupt Enable Register Interrupt enable register
0x2C Reserved
0x30 Generic Short Packet Register Short packet data
0x34 VCX Frame Error Register VCX Frame Error Register
0x38 Reserved
0x3C
Lane<n> Information Registers
0x40 Lane0 Information Lane 0 status information
0x44 Lane1 Information Lane 1 status information
0x48 Lane2 Information Lane 2 status information
0x4C Lane3 Information Lane 3 status information
0x50 Reserved
0x54 Reserved
0x58 Reserved
0x5C Reserved
Image Information 1 Registers (VC0 to VC15) and Image Information 2 Registers (VC0 to VC15)
0x60 Image Information 1 for VC0
0x64 Image Information 2 for VC0
0x68 Image Information 1 for VC1
Clock Lane Information
Register
Clock lane status information
Image information 1 of the current processing packet
with VC of 0
Image information 2 of the current processing packet
with VC of 0
Image information 1 of the current processing packet
with VC of 1
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0x6C Image Information 2 for VC1
0x70 Image Information 1 for VC2
0x74 Image Information 2 for VC2
0x78 Image Information 1 for VC3
0x7C Image Information 2 for VC3
0x80 Image Information 1 for VC4
0x84 Image Information 2 for VC4
0x88 Image Information 1 for VC5
Image information 2 of the current processing packet
with VC of 1
Image information 1 of the current processing packet
with VC of 2
Image information 2 of the current processing packet
with VC of 2
Image information 1 of the current processing packet
with VC of 3
Image information 2 of the current processing packet
with VC of 3
Image information 1 of the current processing packet
with VC of 4
Image information 2 of the current processing packet
with VC of 4
Image information 1 of the current processing packet
with VC of 5
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Table 2-7: MIPI CSI-2 RX Controller Core Registers (Cont’d)
Address Offset Register Name Description
0x8C Image Information 2 for VC5
0x90 Image Information 1 for VC6
0x94 Image Information 2 for VC6
0x98 Image Information 1 for VC7
0x9C Image Information 2 for VC7
0xA0 Image Information 1 for VC8
0xA4 Image Information 2 for VC8
0xA8 Image Information 1 for VC9
0xAC Image Information 2 for VC9
0xB0
0xB4
Image Information 1 for
VC10
Image Information 2 for
VC10
Image information 2 of the current processing packet
with VC of 5
Image information 1 of the current processing packet
with VC of 6
Image information 2 of the current processing packet
with VC of 6
Image information 1 of the current processing packet
with VC of 7
Image information 2 of the current processing packet
with VC of 7
Image information 1 of the current processing packet
with VC of 8
Image information 2 of the current processing packet
with VC of 8
Image information 1 of the current processing packet
with VC of 9
Image information 2 of the current processing packet
with VC of 9
Image information 1 of the current processing packet
with VC of 10
Image information 2 of the current processing packet
with VC of 10
0xB8
0xBC
0xC0
0xC4
0xC8
0xCC
0xD0
0xD4
0xD8
Image Information 1 for
VC11
Image Information 2 for
VC11
Image Information 1 for
VC12
Image Information 2 for
VC12
Image Information 1 for
VC13
Image Information 2 for
VC13
Image Information 1 for
VC14
Image Information 2 for
VC14
Image Information 1 for
VC15
Image information 1 of the current processing packet
with VC of 11
Image information 2 of the current processing packet
with VC of 11
Image information 1 of the current processing packet
with VC of 12
Image information 2 of the current processing packet
with VC of 12
Image information 1 of the current processing packet
with VC of 13
Image information 2 of the current processing packet
with VC of 13
Image information 1 of the current processing packet
with VC of 14
Image information 2 of the current processing packet
with VC of 14
Image information 1 of the current processing packet
with VC of 15
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Table 2-7: MIPI CSI-2 RX Controller Core Registers (Cont’d)
Address Offset Register Name Description
0xDC
Notes:
1. Access type and reset value for all the reserved bits in the registers is read-only with value 0.
2. Register accesses should be word aligned and there is no support for a write strobe. WSTRB is not used internally.
3. Only the lower 7-bits (6:0) of the read and write address of the AXI4-Lite interface are decoded. This means that
accessing address 0x00 and 0x80 results in reading the same address of 0x00.
4. Reads and writes to addresses outside this table do not return an error.
Image Information 2 for
VC15
Image information 2 of the current processing packet
with VC of 15
Core Configuration Register
The Core Configuration register is described in Ta ble 2 -8 and allows you to enable and
disable the MIPI CSI-2 RX Controller core and apply a soft reset during core operation.
Table 2-8: Core Configuration Register (0x00)
Bits Name Reset Value Access Description
31–2 Reserved N/A N/A Reserved
1: Resets the core
0: Takes core out of soft reset
All registers reset to their default value (except for this
bit, Core Enable and Active lanes configuration).
In addition to resetting registers when this bit is set to 1:
1 Soft Reset 0x0 R/W
• Shut down port is not asserted on the PPI lanes
• Internal FIFOs (PPI, Packet, Generic Short Packet) are
flushed
• Control Finite State Machine (FSM) stops processing
current packet. Any partially written packet to
memory is marked as errored. This packet, when
made available through the AXI4-Stream interface,
reports the error on TUSER[1].
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1: Enables the core to receive and process packets
0: Disables the core for operation
When disabled:
• Shuts down port assertion on the PPI lanes
0Core Enable0x1 R/W
Notes:
1. The short packet and line buffer FIFO full conditions take a few clocks to reflect in the register clock domain from
the core clock domain due to Clock Domain Crossing (CDC) blocks.
• Internal FIFOs (PPI, Packet, Generic Short Packet) are
flushed
• Control FSM stops processing current packet
Any partially written packet to memory is marked as
errored. This packet, when made available through
the AXI4-Stream interface, reports the error on
TUSER[1].
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Protocol Configuration Register
The Protocol Configuration register is described in Ta ble 2 -9 and allows you to configure
protocol specific options such as the number of lanes to be used.
Table 2-9: Protocol Configuration Register (0x04)
Bits Name Reset Value Access Description
31–5 Reserved N/A N/A Reserved
Maximum lanes of the core
Number of lanes configured
4–3 Maximum Lanes
2 Reserved N/A Reserved
1–0 Active Lanes
(1)
during core generation
Number of lanes configured
during core generation
R
(2)
/W
R
0x0—1 Lane
0x1—2 Lanes
0x2—3 Lanes
0x3—4 Lanes
Active lanes in the core
0x0—1 Lane
0x1—2 Lanes
0x2 —3 Lanes
0x3—4 Lanes
(3)
Notes:
1. M ax im um La ne s can no t exceed the number of lanes as set by the Serial Data Lanes parameter at generation time.
2. A read from this register reflects the current number of lanes being used by core. This is useful when dynamically
updating the active lanes during core operation to ensure that the core is using the new active lanes information.
See Chapter 3, Designing with the Subsystem for more information.
3. Active Lanes cannot exceed the Maximum Lanes as set in the Protocol Configuration register setting of bits 4–3.
Core Status Register
The Core Status register is described in Tabl e 2-10 .
Table 2-10: Core Status Register (0x10)
Bits Name Reset Value Access Description
Counts number of long packets written to
the line buffer
31–16 Packet Count 0x0 R
15–4 Reserved N/A N/A N/A
3 Short packet FIFO Full 0x0 R
• No roll-over of this counter reported/
supported
• Count includes error packets (if any)
Indicates the current status of short packet
FIFO full condition
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2 Short packet FIFO not empty 0x0 R
FIFO not empty: Indicates the current status
of short packet FIFO not empty condition
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Table 2-10: Core Status Register (0x10) (Cont’d)
Bits Name Reset Value Access Description
1 Stream Line buffer Full 0x0 R
Soft reset/Core disable
0
in progress
0x0 R
Indicates the current status of line buffer
full condition
Set to 1 by the core to indicate that
internal soft reset/core disable activities
are in progress
Global Interrupt Enable Register
The Global Interrupt Enable register is described in Ta bl e 2- 1 1.
Table 2-11: Global Interrupt Enable Register (0x20)
Bits Name Reset Value Access Description
31–1 Reserved N/A N/A Reserved
Master enable for the device interrupt output to
the system
0 Global Interrupt enable 0x0 R/W
1: Enabled—the corresponding Interrupt Enable
register (IER) bits are used to generate interrupts
0: Disabled—Interrupt generation blocked
irrespective of IER bits
Interrupt Status Register
The Interrupt Status register (ISR) is described in Tabl e 2 -12 and captures the error and
status information for the core.
Table 2-12: Interrupt Status Register (0x24)
Bits Name
31 Frame Received 0x0 R/W1C
30 VCX Frame Error RO 0x0
30–23 Reserved N/A N/A N/A
22 Word Count (WC) corruption 0x0 R/W1C
Reset
Value
Access
(1)
Asserted when the Frame End (FE) short
packet is received for the current frame
Asserted when the VCX Frame error is
detected
Asserted when WC field of packet header
corrupted and core receives less bytes than
indicated in WC field. Such a case can occur
only where more than 2-bits of header are
corr upted which E CC algorithm cannot report
and the corruption is such that the ECC
algorithm reports a higher Word Count (WC)
value as part of ECC correction.
In such case core limits processing of the
packet on reduced number of bytes received
through PPI interface.
Description
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Table 2-12: Interrupt Status Register (0x24) (Cont’d)
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Bits Name
21 Incorrect lane configuration 0x0 R/W1C
20 Short packet FIFO full 0x0 R/W1C
19 Short packet FIFO not empty 0x0 R/W1C
18 Stream line buffer full 0x0 R/W1C Asserts when the line buffer is full
17 Stop state 0x0 R/W1C
16 Reserved N/A N/A N/A
15 Reserved N/A N/A N/A
14 Reserved N/A N/A N/A
SoT error
13
(ErrSoTHS)
SoT sync error
12
(ErrSotSyncHS)
ECC 2-bit error
11
(ErrEccDouble)
Reset
Access
Value
0x0 R/W1C
0x0 R/W1C
0x0 R/W1C
(1)
Asserted when Active lanes is greater than
Maximum lanes in the protocol configuration
register
Active-High signal asserted when the short
packet FIFO full condition detected
Active-High signal asserted when short
packet FIFO not empty condition detected
Active-High signal indicates that the lane
module is currently in Stop state
Indicates Start-of-Transmission (SoT) error
detected
Indicates SoT synchronization completely
failed
As serte d when an ECC syndrome is compu ted
and two bit errors detected in the received
packet header
(3)
(3)
Description
(2)
(3)
ECC 1-bit error
(Detected and Corrected)
10
(ErrEccCorrected)
CRC error
9
(ErrCrc)
Unsupported Data Type
8
(ErrID)
Frame synchronization
7
error for VC3
(ErrFrameSync)
Frame level error for VC3
6
(ErrFrameData)
Frame synchronization
5
error for VC2
(ErrFrameSync)
Frame level error for VC2
4
(ErrFrameData)
0x0 R/W1C
0x0 R/W1C
0x0 R/W1C
0x0 R/W1C
0x0 R/W1C
0x0 R/W1C
0x0 R/W1C
Asserted when an ECC syndrome was
computed and a single bit error in the packet
header was detected and corrected
Asserted when the computed CRC code is
different from the received CRC code
Asserted when a packet header is decoded
with an unrecognized or not implemented
data ID
Asserted when an FE is not paired with a
Frame Start (FS) on the same virtual channel
Asserted after an FE when the data payload
received between FS and FE contains errors.
The data payload errors are CRC errors.
Ass erted when an FE i s not paire d wit h a FS o n
the same virtual channel
Asserted after an FE when the data payload
received between FS and FE contains errors.
The data payload errors are CRC errors.
(4)
(4)
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