Xilinx MicroBlaze Processor Reference Guide

MicroBlaze Processor Reference Guide

UG984 (v2018.2) June 21, 2018

Revision History

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06/21/2018: Released with Vivado® Design Suite 2018.2 without changes from 2018.1.

The following table shows the revision history for this document.

Date Version Revision

04/04/2018

10/04/2017

04/05/2017

10/05/2016

2018.1

2017.3

2017.1

2016.3

Updated for Vivado 2018.1 release:

• Included information about instruction pipeline hazards and forwarding.

• Clarified that software break does not set the BIP bit in MSR.

• Explained memory scrubbing behavior.

• Added more detailed description of sleep and pause usage.

• Clarified use of parallel debug clock and reset.

Updated for Vivado 2017.3 release:

• Added automotive UltraScale+ Zynq and Spartan-7 devices.

• Updated description of debug trace, to add event trace, new in version 10.0.

• Added 4PB extended address size.

• Clarified description of cache trace signals.

Updated for Vivado 2017.1 release:

• Added description of MMU Physical Address Extension (PAE), new in version 10.0.

• Extended privileged instruction list, and updated instruction descriptions.

• Updated information on debug program trace.

• Added reference to the Triple Modular Redundancy (TMR) subsystem.

• Corrected description of BSIFI instruction.

• Updated MFSE instruction description with PAE information.

• Added MTSE instruction used with PAE, new in version 10.0.

• Updated WDC instruction for external cache invalidate and flush.

Updated for Vivado 2016.3 release:

• Added description of frequency optimized 8-stage pipeline, new in version 10.0.

• Describe bit field instructions, new in version 10.0.

• Include information on parallel debug interface, new in version 10.0.

• Added version 10.0 to MicroBlaze release version code in PVR.

• Included Spartan-7 target architecture in PVR.

• Updated description of MSR reset value.

• Updated Xilinx

04/06/2016

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2016.1

Updated for Vivado 2016.1 release:

• Included description of address extension, new in version 9.6.

• Included description of pipeline pause functionality, new in version 9.6

• Included description of non-secure AXI access support, new in version 9.6.

• Included description of hibernate and suspend instructions, new in version 9.6.

• Added version 9.6 to MicroBlaze release version code in PVR.

• Corrected references to Table 2-46 and Table 2-47.

• Replaced references to the deprecated Xilinx Microprocessor Debugger (XMD) with Xilinx System Debugger (XSDB).

• Removed C code function attributes svc_handler and svc_table_handler.

Date Version Revision

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04/15/2015

10/01/2014

04/02/2014

2015.1

2014.3

2014.1

Updated for Vivado 2015.1 release:

• Included description of 16 word cache line length, new in version 9.5.

• Added version 9.5 to MicroBlaze release version code in PVR.

• Corrected description of supported endianness and parameter C_ENDIANNESS.

• Corrected description of outstanding reads for instruction and data cache.

• Updated FPGA configuration memory protection document reference [Ref 5].

• Corrected Bus Index Range definitions for Lockstep Comparison in Table 3-14.

• Clarified registers altered for IDIV instruction.

• Corrected PVR assembler mnemonics for MFS instruction.

• Updated performance and resource utilization for 2015.1.

• Added references to training resources.

Updated for Vivado 2014.3 release:

• Corrected semantic description for PCMPEQ and PCMPNE in Table 2.1.

• Added version 9.4 to MicroBlaze release version code in PVR.

• Included description of external program trace, new in version 9.4

Updated for Vivado 2014.1 release:

• Added v9.3 to MicroBlaze release version code in PVR.

• Clarified availability and behavior of stack protection registers.

• Corrected description of LMB instruction and data bus exception.

• Included description of extended debug features, new in version 9.3: performance monitoring, program trace and non-intrusive profiling.

• Included definition of Reset Mode signals, new in version 9.3.

• Clarified how the AXI4-Stream TLAST signal is handled.

• Added UltraScale and updated performance and resource utilization for 2014.1.

12/18/2013

10/02/2013

06/19/2013

03/20/2013

2013.4

2013.3

2013.2

2013.1

Updated for Vivado 2013.4 release.

Updated for Vivado 2013.3 release.

Updated for Vivado 2013.2 release.

Initial Xilinx release. This User Guide is derived from UG081.

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Table of Contents

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Chapter 1: Introduction

Guide Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Chapter 2: MicroBlaze Architecture

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Data Types and Endianness. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Pipeline Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Privileged Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Virtual-Memory Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Reset, Interrupts, Exceptions, and Break . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Instruction Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Data Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Floating-Point Unit (FPU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Stream Link Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Debug and Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Fault Tolerance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Lockstep Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Coherency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Data and Instruction Address Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

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Chapter 3: MicroBlaze Signal Interface Description

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

MicroBlaze I/O Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

AXI4 and ACE Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Local Memory Bus (LMB) Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Lockstep Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Debug Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Trace Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

MicroBlaze Core Configurability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

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Chapter 4: MicroBlaze Application Binary Interface

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

Register Usage Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Stack Convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

Memory Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

Interrupt, Break and Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

Chapter 5: MicroBlaze Instruction Set Architecture

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Appendix A: Performance and Resource Utilization

Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305

Resource Utilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306

IP Characterization and fMAX Margin System Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

Appendix B: Additional Resources and Legal Notices

Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315

Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315

Documentation Navigator and Design Hubs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316

Training Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

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Introduction

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The MicroBlaze™ Processor Reference Guide provides information about the 32-bit soft processor, MicroBlaze, which is included in Vivado. The document is intended as a guide to the MicroBlaze hardware architecture.

Guide Contents

This guide contains the following chapters:

• Chapter 2, MicroBlaze Architecture contains an overview of MicroBlaze features as well as information on Big-Endian and Little-Endian bit-reversed format, 32-bit general purpose registers, cache software support, and AXI4-Stream interfaces.

Chapter 1

• Chapter 3, MicroBlaze Signal Interface Description describes the types of signal interfaces that can be used to connect MicroBlaze.

• Chapter 4, MicroBlaze Application Binary Interface describes the Application Binary Interface important for developing software in assembly language for the processor.

• Chapter 5, MicroBlaze Instruction Set Architecture provides notation, formats, and instructions for the Instruction Set Architecture (ISA) of MicroBlaze.

• Appendix A, Performance and Resource Utilization contains maximum frequencies and resource utilization numbers for different configurations and devices.

• Appendix B, Additional Resources and Legal Notices provides links to documentation and additional resources.

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MicroBlaze Architecture

Bus

I-Cache

Instruction

Buffer

Instruction

Buffer

Branch Target

Cache

Program

Counter

M_AXI_IC

Memory Management Unit (MMU)

ITLB DTLBUTLB

Bus

D-Cache

M_AXI_DC

M_AXI_DP

DLMB

M0_AXIS .. M15_AXIS

S0_AXIS .. S15_AXIS

Special

Purpose

Registers

Instruction

Decode

32 x 32b

ALU

Shift

Barrel Shift

Multiplier

Divider

FPU

Instruction-side

Bus interface

Data-side

Bus interface

Optional MicroBlaze feature

M_AXI_IP

ILMB

M_ACE_DC

M_ACE_IC

X19738-090717

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Introduction

This chapter contains an overview of MicroBlaze™ features and detailed information on MicroBlaze architecture including Big-Endian or Little-Endian bit-reversed format, 32-bit general purpose registers, virtual-memory management, cache software support, and AXI4-Stream interfaces.

Overview

The MicroBlaze embedded processor soft core is a reduced instruction set computer (RISC) optimized for implementation in Xilinx® Field Programmable Gate Arrays (FPGAs). The following figure shows a functional block diagram of the MicroBlaze core.

Chapter 2

X-Ref Target - Figure 2-1

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Figure 2-1: MicroBlaze Core Block Diagram

Chapter 2: MicroBlaze Architecture

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Features

The MicroBlaze soft core processor is highly configurable, allowing you to select a specific set of features required by your design.

The fixed feature set of the processor includes:

• Thirty-two 32-bit general purpose registers

• 32-bit instruction word with three operands and two addressing modes

• Default 32-bit address bus, extensible to 64 bits

• Single issue pipeline

In addition to these fixed features, the MicroBlaze processor is parameterized to allow selective enabling of additional functionality. Older (deprecated) versions of MicroBlaze support a subset of the optional features described in this manual. Only the latest (preferred) version of MicroBlaze (v10.0) supports all options.

RECOMMENDED: Xilinx recommends that all new designs use the latest preferred version of the

MicroBlaze processor.

The following table provides an overview of the configurable features by MicroBlaze versions.

Table 2-1: Configurable Feature Overview by MicroBlaze Version

MicroBlaze versions

Feature

v9.2 v9.3 v9.4 v9.5 v9.6 v10.0

Version Status

Processor pipeline depth

Local Memory Bus (LMB) data side interface

Local Memory Bus (LMB) instruction side interface

Hardware barrel shifter

Hardware divider

Hardware debug logic

Stream link interfaces

Machine status set and clear instructions

Cache line word length

Hardware exception support

Pattern compare instructions

Floating-point unit (FPU)

deprecated deprecated deprecated deprecated deprecated preferred

3/5 3/5 3/5 3/5 3/5 3/5/8

option option option option option option

0-16 AXI 0-16 AXI 0-16 AXI 0-16 AXI 0-16 AXI 0-16 AXI

option option option option option option

4, 8 4, 8 4, 8 4, 8, 16 4, 8, 16 4, 8, 16

option option option option option option

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Chapter 2: MicroBlaze Architecture

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Table 2-1: Configurable Feature Overview by MicroBlaze Version (Cont’d)

Feature

Disable hardware multiplier

Hardware debug readable ESR and EAR

Processor Version Register (PVR)

Area or speed optimized

Hardware multiplier 64-bit result

LUT cache memory

Floating-point conversion and square root instructions

Memory Management Unit (MMU)

Extended stream instructions

Use Cache Interface for All I-Cache Memory Accesses

Use Cache Interface for All D-Cache Memory Accesses

Use Write-back Caching Policy for D-Cache

Branch Target Cache (BTC)

Streams for I-Cache

Victim handling for I-Cache

Victim handling for D-Cache

AXI4 (M_AXI_DP) data side interface

AXI4 (M_AXI_IP) instruction side interface

AXI4 (M_AXI_DC) protocol for DCache

AXI4 (M_AXI_IC) protocol for ICache

AXI4 protocol for stream accesses

Fault tolerant features

Force distributed RAM for cache tags

Configurable cache data widths

Count Leading Zeros instruction

Memory Barrier instruction

Stack overflow and underflow detection

Allow stream instructions in user mode

MicroBlaze versions

v9.2 v9.3 v9.4 v9.5 v9.6 v10.0

option option option option option option

Yes Yes Yes Yes Yes Yes

option option option option option option

Yes Yes Yes Yes Yes Yes

option option option option option option

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Chapter 2: MicroBlaze Architecture

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Table 2-1: Configurable Feature Overview by MicroBlaze Version (Cont’d)

Feature

v9.2 v9.3 v9.4 v9.5 v9.6 v10.0

Lockstep support

Configurable use of FPGA primitives

Low-latency interrupt mode

Swap instructions

Sleep mode and sleep instruction

Relocatable base vectors

ACE (M_ACE_DC) protocol for DCache

ACE (M_ACE_IC) protocol for ICache

Extended debug: performance monitoring, program trace, nonintrusive profiling

Reset mode: enter sleep or debug halt at reset

Extended debug: external program trace

Extended data addressing

Pipeline pause functionality

Hibernate and suspend instructions

Non-secure mode

Bit field instructions

Parallel debug interface

MMU Physical Address Extension

1. Used for saving DSP48E primitives.

2. Bit field instructions are available when C_USE_BARREL = 1.

option option option option option option

Yes Yes Yes Yes Yes Yes

option option option option option option

option option option option option

MicroBlaze versions

option option option option

option option

Yes Yes

option

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Chapter 2: MicroBlaze Architecture

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Data Types and Endianness

The MicroBlaze processor uses Big-Endian or Little-Endian format to represent data, depending on the selected endianness. The parameter endian) by default.

The hardware supported data types for MicroBlaze are word, half word, and byte. When using the reversed load and store instructions LHUR, LWR, SHR, and SWR, the bytes in the data are reversed, as indicated by the byte-reversed order.

The following tables show the bit and byte organization for each type.

Table 2-2: Word Data Type

Big-Endian Byte Address n n+1 n+2 n+3

Big-Endian Byte Significance MSByte LSByte

Big-Endian Byte Order n n+1 n+2 n+3

Big-Endian Byte-Reversed Order n+3 n+2 n+1 n

Little-Endian Byte Address n+3 n+2 n+1 n

Little-Endian Byte Significance MSByte LSByte

Little-Endian Byte Order n+3 n+2 n+1 n

Little-Endian Byte-Reversed Order n n+1 n+2 n+3

Bit Label 0 31

Bit Significance MSBit LSBit

C_ENDIANNESS is set to 1 (little-

Table 2-3: Half Word Data Type

Big-Endian Byte Address n n+1

Big-Endian Byte Significance MSByte LSByte

Big-Endian Byte Order n n+1

Big-Endian Byte-Reversed Order n+1 n

Little-Endian Byte Address n+1 n

Little-Endian Byte Significance MSByte LSByte

Little-Endian Byte Order n+1 n

Little-Endian Byte-Reversed Order n n+1

Bit Label 0 15

Bit Significance MSBit LSBit

Table 2-4: Byte Data Type

Byte Address n

Bit Label 0 7

Bit Significance MSBit LSBit

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Instructions

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Instruction Summary

All MicroBlaze instructions are 32 bits and are defined as either Type A or Type B. Type A instructions have up to two source register operands and one destination register operand. Type B instructions have one source register and a 16-bit immediate operand (which can be extended to 32 bits by preceding the Type B instruction with an imm instruction).

Type B instructions have a single destination register operand. Instructions are provided in the following functional categories: arithmetic, logical, branch, load/store, and special. The following table describes the instruction set nomenclature used in the semantics of each instruction.

Instruction Set Architecture, for more information on these instructions.

Table 2-5: Instruction Set Nomenclature

Symbol Description

Table 2-5 lists the MicroBlaze instruction set. See Chapter 5, MicroBlaze

Chapter 2: MicroBlaze Architecture

Ra R0 - R31, General Purpose Register, source operand a

Rb R0 - R31, General Purpose Register, source operand b

Rd R0 - R31, General Purpose Register, destination operand

SPR[x] Special Purpose Register number x

MSR Machine Status Register = SPR[1]

ESR Exception Status Register = SPR[5]

EAR Exception Address Register = SPR[3]

FSR Floating-point Unit Status Register = SPR[7]

PVRx Processor Version Register, where x is the register number = SPR[8192 + x]

BTR Branch Target Register = SPR[11]

PC Execute stage Program Counter = SPR[0]

x[y] Bit y of register x

x[y:z] Bit range y to z of register x

x Bit inverted value of register x

Imm 16 bit immediate value

Immx x bit immediate value

FSLx 4 bit AXI4-Stream port designator, where x is the port number

C Carry flag, MSR[29]

Sa Special Purpose Register, source operand

Sd Special Purpose Register, destination operand

s(x) Sign extend argument x to 32-bit value

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Table 2-5: Instruction Set Nomenclature (Cont’d)

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Symbol Description

*Addr Memory contents at location Addr (data-size aligned)

:= Assignment operator

= Equality comparison

!= Inequality comparison

> Greater than comparison

>= Greater than or equal comparison

< Less than comparison

<= Less than or equal comparison

+ Arithmetic add

* Arithmetic multiply

/ Arithmetic divide

>> x Bit shift right x bits

<< x Bit shift left x bits

Chapter 2: MicroBlaze Architecture

and Logic AND

or Logic OR

xor Logic exclusive OR

op1 if cond else op2 Perform op1 if condition cond is true, else perform op2

& Concatenate. For example “0000100 & Imm7” is the concatenation of the fixed field

“0000100” and a 7 bit immediate value.

signed Operation performed on signed integer data type. All arithmetic operations are

performed on signed word operands, unless otherwise specified

unsigned Operation performed on unsigned integer data type

float Operation performed on floating-point data type

clz(r) Count leading zeros

Table 2-6: MicroBlaze Instruction Set Summary

Type A 0-5 6-10 11-15 16-20 21-31

Semantics

Type B 0-5 6-10 11-15 16-31

ADD Rd,Ra,Rb 000000 Rd Ra Rb 00000000000 Rd := Rb + Ra

RSUB Rd,Ra,Rb 000001 Rd Ra Rb 00000000000 Rd := Rb + Ra + 1

ADDC Rd,Ra,Rb 000010 Rd Ra Rb 00000000000 Rd := Rb + Ra + C

RSUBC Rd,Ra,Rb 000011 Rd Ra Rb 00000000000 Rd := Rb + Ra + C

ADDK Rd,Ra,Rb 000100 Rd Ra Rb 00000000000 Rd := Rb + Ra

RSUBK Rd,Ra,Rb 000101 Rd Ra Rb 00000000000 Rd := Rb + Ra + 1

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Table 2-6: MicroBlaze Instruction Set Summary (Cont’d)

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Chapter 2: MicroBlaze Architecture

Type A 0-5 6-10 11-15 16-20 21-31

Semantics

Type B 0-5 6-10 11-15 16-31

CMP Rd,Ra,Rb 000101 Rd Ra Rb 00000000001 Rd := Rb + Ra + 1

Rd[0] := 0 if (Rb >= Ra) else

Rd[0] := 1

CMPU Rd,Ra,Rb 000101 Rd Ra Rb 00000000011 Rd := Rb + Ra + 1 (unsigned)

Rd[0] := 0 if (Rb >= Ra, unsigned) else Rd[0] := 1

ADDKC Rd,Ra,Rb 000110 Rd Ra Rb 00000000000 Rd := Rb + Ra + C

RSUBKC Rd,Ra,Rb 000111 Rd Ra Rb 00000000000 Rd := Rb + Ra + C

ADDI Rd,Ra,Imm 001000 Rd Ra Imm Rd := s(Imm) + Ra

RSUBI Rd,Ra,Imm 001001 Rd Ra Imm Rd := s(Imm) + Ra + 1

ADDIC Rd,Ra,Imm 001010 Rd Ra Imm Rd := s(Imm) + Ra + C

RSUBIC Rd,Ra,Imm 001011 Rd Ra Imm Rd := s(Imm) + Ra + C

ADDIK Rd,Ra,Imm 001100 Rd Ra Imm Rd := s(Imm) + Ra

RSUBIK Rd,Ra,Imm 001101 Rd Ra Imm Rd := s(Imm) + Ra + 1

ADDIKC Rd,Ra,Imm 001110 Rd Ra Imm Rd := s(Imm) + Ra + C

RSUBIKC Rd,Ra,Imm 001111 Rd Ra Imm Rd := s(Imm) + Ra + C

MUL Rd,Ra,Rb 010000 Rd Ra Rb 00000000000 Rd := Ra * Rb

MULH Rd,Ra,Rb 010000 Rd Ra Rb 00000000001 Rd := (Ra * Rb) >> 32 (signed)

MULHU Rd,Ra,Rb 010000 Rd Ra Rb 00000000011 Rd := (Ra * Rb) >> 32 (unsigned)

MULHSU Rd,Ra,Rb 010000 Rd Ra Rb 00000000010 Rd := (Ra, signed * Rb, unsigned) >>

32 (signed)

BSRL Rd,Ra,Rb 010001 Rd Ra Rb 00000000000 Rd := 0 & (Ra >> Rb)

BSRA Rd,Ra,Rb 010001 Rd Ra Rb 01000000000 Rd := s(Ra >> Rb)

BSLL Rd,Ra,Rb 010001 Rd Ra Rb 10000000000 Rd := (Ra << Rb) & 0

IDIV Rd,Ra,Rb 010010 Rd Ra Rb 00000000000 Rd := Rb/Ra

IDIVU Rd,Ra,Rb 010010 Rd Ra Rb 00000000010 Rd := Rb/Ra, unsigned

TNEAGETD Rd,Rb 010011 Rd 00000 Rb 0N0TAE

00000

TNAPUTD Ra,Rb 010011 00000 Ra Rb 0N0TA0

00000

TNECAGETD Rd,Rb 010011 Rd 00000 Rb 0N1TAE

00000

Rd := FSL Rb[28:31] (data read)

MSR[FSL] := 1 if (FSL_S_Control = 1)

MSR[C] := not FSL_S_Exists if N = 1

FSL Rb[28:31] := Ra (data write)

MSR[C] := FSL_M_Full if N = 1

Rd := FSL Rb[28:31] (control read)

MSR[FSL] := 1 if (FSL_S_Control = 0)

MSR[C] := not FSL_S_Exists if N = 1

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Table 2-6: MicroBlaze Instruction Set Summary (Cont’d)

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Chapter 2: MicroBlaze Architecture

Type A 0-5 6-10 11-15 16-20 21-31

Semantics

Type B 0-5 6-10 11-15 16-31

TNCAPUTD Ra,Rb 010011 00000 Ra Rb 0N1TA0

00000

FADD Rd,Ra,Rb 010110 Rd Ra Rb 00000000000 Rd := Rb+Ra, float

FRSUB Rd,Ra,Rb 010110 Rd Ra Rb 00010000000 Rd := Rb-Ra, float

FMUL Rd,Ra,Rb 010110 Rd Ra Rb 00100000000 Rd := Rb*Ra, float

FDIV Rd,Ra,Rb 010110 Rd Ra Rb 00110000000 Rd := Rb/Ra, float

FCMP.UN Rd,Ra,Rb 010110 Rd Ra Rb 01000000000 Rd := 1 if (Rb = NaN or Ra = NaN,

FCMP.LT Rd,Ra,Rb 010110 Rd Ra Rb 01000010000 Rd := 1 if (Rb < Ra, float1) else

FCMP.EQ Rd,Ra,Rb 010110 Rd Ra Rb 01000100000 Rd := 1 if (Rb = Ra, float1) else

FCMP.LE Rd,Ra,Rb 010110 Rd Ra Rb 01000110000 Rd := 1 if (Rb <= Ra, float1) else

FCMP.GT Rd,Ra,Rb 010110 Rd Ra Rb 01001000000 Rd := 1 if (Rb > Ra, float1) else

FSL Rb[28:31] := Ra (control write)

MSR[C] := FSL_M_Full if N = 1

) else

float

Rd := 0

FCMP.NE Rd,Ra,Rb 010110 Rd Ra Rb 01001010000 Rd := 1 if (Rb != Ra, float1) else

Rd := 0

FCMP.GE Rd,Ra,Rb 010110 Rd Ra Rb 01001100000 Rd := 1 if (Rb >= Ra, float1) else

Rd := 0

FLT Rd,Ra 010110 Rd Ra 0 01010000000 Rd := float (Ra)

FINT Rd,Ra 010110 Rd Ra 0 01100000000 Rd := int (Ra)

FSQRT Rd,Ra 010110 Rd Ra 0 01110000000 Rd := sqrt (Ra)

MULI Rd,Ra,Imm 011000 Rd Ra Imm Rd := Ra * s(Imm)

BSRLI Rd,Ra,Imm 011001 Rd Ra 00000000000 &

Rd : = 0 & (Ra >> Imm5)

Imm5

BSRAI Rd,Ra,Imm 011001 Rd Ra 00000010000 &

Rd := s(Ra >> Imm5)

Imm5

BSLLI Rd,Ra,Imm 011001 Rd Ra 00000100000 &

Rd := (Ra << Imm5) & 0

Imm5

BSEFI Rd,Ra,

ImmW,Imm

011001 Rd Ra 01000 &

Imm

& 0 & Imm

Rd[0:31-ImmW] := 0

Rd[32-ImmW:31] := (Ra >> ImmS)

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Table 2-6: MicroBlaze Instruction Set Summary (Cont’d)

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Chapter 2: MicroBlaze Architecture

Type A 0-5 6-10 11-15 16-20 21-31

Type B 0-5 6-10 11-15 16-31

BSIFI Rd,Ra,

Width,Imm

TNEAGET Rd,FSLx 011011 Rd 00000 0N0TAE000000 &

TNAPUT Ra,FSLx 011011 00000 Ra 1N0TA0000000 &

TNECAGET Rd,FSLx 011011 Rd 00000 0N1TAE000000 &

TNCAPUT Ra,FSLx 011011 00000 Ra 1N1TA0000000 &

011001 Rd Ra 10000 &

Imm

& 0 & Imm

FSLx

Semantics

M := (0xffffffff << (ImmW + 1)) xor

(0xffffffff << ImmS)

Rd := ((Ra << ImmS) and M) xor

(Rd and M) ImmW := ImmS + Width - 1

Rd := FSLx (data read, blocking if N = 0)

MSR[FSL] := 1 if (FSLx_S_Control = 1)

MSR[C] := not FSLx_S_Exists if N = 1

FSLx := Ra (data write, block if N = 0)

MSR[C] := FSLx_M_Full if N = 1

Rd := FSLx (control read, block if N =

MSR[FSL] := 1 if (FSLx_S_Control = 0)

MSR[C] := not FSLx_S_Exists if N = 1

FSLx := Ra (control write, block if N =

MSR[C] := FSLx_M_Full if N = 1

OR Rd,Ra,Rb 100000 Rd Ra Rb 00000000000 Rd := Ra or Rb

PCMPBF Rd,Ra,Rb 100000 Rd Ra Rb 10000000000 Rd := 1 if (Rb[0:7] = Ra[0:7]) else

Rd := 2 if (Rb[8:15] = Ra[8:15]) else

Rd := 3 if (Rb[16:23] = Ra[16:23]) else

Rd := 4 if (Rb[24:31] = Ra[24:31]) else

Rd := 0

AND Rd,Ra,Rb 100001 Rd Ra Rb 00000000000 Rd := Ra and Rb

XOR Rd,Ra,Rb 100010 Rd Ra Rb 00000000000 Rd := Ra xor Rb

PCMPEQ Rd,Ra,Rb 100010 Rd Ra Rb 10000000000 Rd := 1 if (Rb = Ra) else

Rd := 0

ANDN Rd,Ra,Rb 100011 Rd Ra Rb 00000000000 Rd := Ra and Rb

PCMPNE Rd,Ra,Rb 100011 Rd Ra Rb 10000000000 Rd := 1 if (Rb != Ra) else

Rd := 0

SRA Rd,Ra 100100 Rd Ra 0000000000000001 Rd := s(Ra >> 1)

C := Ra[31]

SRC Rd,Ra 100100 Rd Ra 0000000000100001 Rd := C & (Ra >> 1)

C := Ra[31]

SRL Rd,Ra 100100 Rd Ra 0000000001000001 Rd := 0 & (Ra >> 1)

C := Ra[31]

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Table 2-6: MicroBlaze Instruction Set Summary (Cont’d)

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Chapter 2: MicroBlaze Architecture

Type A 0-5 6-10 11-15 16-20 21-31

Semantics

Type B 0-5 6-10 11-15 16-31

SEXT8 Rd,Ra 100100 Rd Ra 0000000001100000 Rd := s(Ra[24:31])

SEXT16 Rd,Ra 100100 Rd Ra 0000000001100001 Rd := s(Ra[16:31])

CLZ Rd, Ra 100100 Rd Ra 0000000011100000 Rd = clz(Ra)

SWAPB Rd, Ra 100100 Rd Ra 0000000111100000 Rd = (Ra)[24:31, 16:23, 8:15, 0:7]

SWAPH Rd, Ra 100100 Rd Ra 0000000111100010 Rd = (Ra)[16:31, 0:15]

WIC Ra,Rb 100100 00000 Ra Rb 00001101000 ICache_Line[Ra >> 4].Tag := 0 if

C_ICACHE_LINE_LEN = 4)

(

ICache_Line[Ra >> 5].Tag := 0 if

C_ICACHE_LINE_LEN = 8)

(

ICache_Line[Ra >> 6].Tag := 0 if

C_ICACHE_LINE_LEN = 16)

(

WDC Ra,Rb 100100 00000 Ra Rb 00001100100 Cache line is cleared, discarding

stored data.

DCache_Line[Ra >> 4].Tag := 0 if

C_DCACHE_LINE_LEN = 4)

(

DCache_Line[Ra >> 5].Tag := 0 if

C_DCACHE_LINE_LEN = 8)

(

DCache_Line[Ra >> 6].Tag := 0 if

C_DCACHE_LINE_LEN = 16)

(

WDC.FLUSH Ra,Rb 100100 00000 Ra Rb 00001110100 Cache line is flushed, writing stored

data to memory, and then cleared. Used when

C_DCACHE_USE_WRITEBACK = 1.

WDC.CLEAR Ra,Rb 100100 00000 Ra Rb 00001100110 Cache line with matching address is

cleared, discarding stored data. Used when

C_DCACHE_USE_WRITEBACK = 1.

WDC.CLEAR.EA Ra,Rb

100100 00000 Ra Rb 00011100110 Cache line with matching extended

address Ra & Rb is cleared. Used when

C_DCACHE_USE_WRITEBACK = 1.

MTS Sd,Ra 100101 00000 Ra 11 & Sd SPR[Sd] := Ra, where:

· SPR[0x0001] is MSR

· SPR[0x0007] is FSR

· SPR[0x0800] is SLR

· SPR[0x0802] is SHR

· SPR[0x1000] is PID

· SPR[0x1001] is ZPR

· SPR[0x1002] is TLBX

· SPR[0x1003] is TLBLO[LSH]

· SPR[0x1004] is TLBHI

· SPR[0x1005] is TLBSX

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Table 2-6: MicroBlaze Instruction Set Summary (Cont’d)

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Chapter 2: MicroBlaze Architecture

Type A 0-5 6-10 11-15 16-20 21-31

Semantics

Type B 0-5 6-10 11-15 16-31

MTSE Sd,Ra 100101 01000 Ra 11 & Sd SPR[Sd} := Ra, where:

· SPR[0x1003] is TLBLO[MSH]

MFS Rd,Sa 100101 Rd 00000 10 & Sa Rd := SPR[Sa], where:

· SPR[0x0000] is PC

· SPR[0x0001] is MSR

· SPR[0x0003] is EAR[LSH]

· SPR[0x0005] is ESR

· SPR[0x0007] is FSR

· SPR[0x000B] is BTR

· SPR[0x000D] is EDR

· SPR[0x0800] is SLR

· SPR[0x0802] is SHR

· SPR[0x1000] is PID

· SPR[0x1001] is ZPR

· SPR[0x1002] is TLBX

· SPR[0x1003] is TLBLO[LSH]

· SPR[0x1004] is TLBHI

· SPR[0x2000-200B] is PVR[012][LSH]

MFSE Rd,Sa 100101 Rd 01000 10 & Sa Rd := SPR[Sa][MSH], where:

· SPR[0x0003] is EAR[MSH]

· SPR[0x1003] is TLBLO[MSH]

· SPR[0x2006-2009] is PVR[69][MSH]

MSRCLR Rd,Imm 100101 Rd 00001 00 & Imm14 Rd := MSR

MSR := MSR and Imm14

MSRSET Rd,Imm 100101 Rd 00000 00 & Imm14 Rd := MSR

MSR := MSR or Imm14

BR Rb 100110 00000 00000 Rb 00000000000 PC := PC + Rb

BRD Rb 100110 00000 10000 Rb 00000000000 PC := PC + Rb

BRLD Rd,Rb 100110 Rd 10100 Rb 00000000000 PC := PC + Rb

Rd := PC

BRA Rb 100110 00000 01000 Rb 00000000000 PC := Rb

BRAD Rb 100110 00000 11000 Rb 00000000000 PC := Rb

BRALD Rd,Rb 100110 Rd 11100 Rb 00000000000 PC := Rb

Rd := PC

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Table 2-6: MicroBlaze Instruction Set Summary (Cont’d)

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Chapter 2: MicroBlaze Architecture

Type A 0-5 6-10 11-15 16-20 21-31

Semantics

Type B 0-5 6-10 11-15 16-31

BRK Rd,Rb 100110 Rd 01100 Rb 00000000000 PC := Rb

Rd := PC

MSR[BIP] := 1

BEQ Ra,Rb 100111 00000 Ra Rb 00000000000 PC := PC + Rb if Ra = 0

BNE Ra,Rb 100111 00001 Ra Rb 00000000000 PC := PC + Rb if Ra != 0

BLT Ra,Rb 100111 00010 Ra Rb 00000000000 PC := PC + Rb if Ra < 0

BLE Ra,Rb 100111 00011 Ra Rb 00000000000 PC := PC + Rb if Ra <= 0

BGT Ra,Rb 100111 00100 Ra Rb 00000000000 PC := PC + Rb if Ra > 0

BGE Ra,Rb 100111 00101 Ra Rb 00000000000 PC := PC + Rb if Ra >= 0

BEQD Ra,Rb 100111 10000 Ra Rb 00000000000 PC := PC + Rb if Ra = 0

BNED Ra,Rb 100111 10001 Ra Rb 00000000000 PC := PC + Rb if Ra != 0

BLTD Ra,Rb 100111 10010 Ra Rb 00000000000 PC := PC + Rb if Ra < 0

BLED Ra,Rb 100111 10011 Ra Rb 00000000000 PC := PC + Rb if Ra <= 0

BGTD Ra,Rb 100111 10100 Ra Rb 00000000000 PC := PC + Rb if Ra > 0

BGED Ra,Rb 100111 10101 Ra Rb 00000000000 PC := PC + Rb if Ra >= 0

ORI Rd,Ra,Imm 101000 Rd Ra Imm Rd := Ra or s(Imm)

ANDI Rd,Ra,Imm 101001 Rd Ra Imm Rd := Ra and s(Imm)

XORI Rd,Ra,Imm 101010 Rd Ra Imm Rd := Ra xor s(Imm)

ANDNI Rd,Ra,Imm 101011 Rd Ra Imm Rd := Ra and s(Imm)

IMM Imm 101100 00000 00000 Imm Imm[0:15] := Imm

RTSD Ra,Imm 101101 10000 Ra Imm PC := Ra + s(Imm)

RTID Ra,Imm 101101 10001 Ra Imm PC := Ra + s(Imm)

MSR[IE] := 1

RTBD Ra,Imm 101101 10010 Ra Imm PC := Ra + s(Imm)

MSR[BIP] := 0

RTED Ra,Imm 101101 10100 Ra Imm PC := Ra + s(Imm)

MSR[EE] := 1, MSR[EIP] := 0

ESR := 0

BRI Imm 101110 00000 00000 Imm PC := PC + s(Imm)

MBAR Imm 101110 Imm 00010 0000000000000100 PC := PC + 4; Wait for memory

accesses.

BRID Imm 101110 00000 10000 Imm PC := PC + s(Imm)

BRLID Rd,Imm 101110 Rd 10100 Imm PC := PC + s(Imm)

Rd := PC

BRAI Imm 101110 00000 01000 Imm PC := s(Imm)

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Table 2-6: MicroBlaze Instruction Set Summary (Cont’d)

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Chapter 2: MicroBlaze Architecture

Type A 0-5 6-10 11-15 16-20 21-31

Semantics

Type B 0-5 6-10 11-15 16-31

BRAID Imm 101110 00000 11000 Imm PC := s(Imm)

BRALID Rd,Imm 101110 Rd 11100 Imm PC := s(Imm)

Rd := PC

BRKI Rd,Imm 101110 Rd 01100 Imm PC := s(Imm)

Rd := PC MSR[BIP] := 1

BEQI Ra,Imm 101111 00000 Ra Imm PC := PC + s(Imm) if Ra = 0

BNEI Ra,Imm 101111 00001 Ra Imm PC := PC + s(Imm) if Ra != 0

BLTI Ra,Imm 101111 00010 Ra Imm PC := PC + s(Imm) if Ra < 0

BLEI Ra,Imm 101111 00011 Ra Imm PC := PC + s(Imm) if Ra <= 0

BGTI Ra,Imm 101111 00100 Ra Imm PC := PC + s(Imm) if Ra > 0

BGEI Ra,Imm 101111 00101 Ra Imm PC := PC + s(Imm) if Ra >= 0

BEQID Ra,Imm 101111 10000 Ra Imm PC := PC + s(Imm) if Ra = 0

BNEID Ra,Imm 101111 10001 Ra Imm PC := PC + s(Imm) if Ra != 0

BLTID Ra,Imm 101111 10010 Ra Imm PC := PC + s(Imm) if Ra < 0

BLEID Ra,Imm 101111 10011 Ra Imm PC := PC + s(Imm) if Ra <= 0

BGTID Ra,Imm 101111 10100 Ra Imm PC := PC + s(Imm) if Ra > 0

BGEID Ra,Imm 101111 10101 Ra Imm PC := PC + s(Imm) if Ra >= 0

LBU Rd,Ra,Rb

LBUR Rd,Ra,Rb

LBUEA Rd,Ra,Rb 110000 Rd Ra Rb 00010000000 Addr := Ra & Rb

LHU Rd,Ra,Rb

LHUR Rd,Ra,Rb

LHUEA Rd,Ra,Rb 110001 Rd Ra Rb 00010000000 Addr := Ra & Rb

LW Rd,Ra,Rb

LWR Rd,Ra,Rb

LWX Rd,Ra,Rb 110010 Rd Ra Rb 10000000000 Addr := Ra + Rb

110000 Rd Ra Rb 00000000000

01000000000

110001 Rd Ra Rb 00000000000

01000000000

110010 Rd Ra Rb 00000000000

01000000000

Addr := Ra + Rb

Rd[0:23] := 0

Rd[24:31] := *Addr[0:7]

Rd[0:23] := 0

Rd[24:31] := *Addr[0:7]

Addr := Ra + Rb

Rd[0:15] := 0

Rd[16:31] := *Addr[0:15]

Rd[0:15] := 0

Rd[16:31] := *Addr[0:15]

Addr := Ra + Rb

Rd := *Addr

Rd := *Addr Reservation := 1

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Table 2-6: MicroBlaze Instruction Set Summary (Cont’d)

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Chapter 2: MicroBlaze Architecture

Type A 0-5 6-10 11-15 16-20 21-31

Semantics

Type B 0-5 6-10 11-15 16-31

LWEA Rd,Ra,Rb 110010 Rd Ra Rb 00010000000 Addr := Ra & Rb

Rd := *Addr

SB Rd,Ra,Rb

SBR Rd,Ra,Rb

SBEA Rd,Ra,Rb 110100 Rd Ra Rb 00010000000 Addr := Ra & Rb

SH Rd,Ra,Rb

SHR Rd,Ra,Rb

SHEA Rd,Ra,Rb 110101 Rd Ra Rb 00010000000 Addr := Ra & Rb

SW Rd,Ra,Rb

SWR Rd,Ra,Rb

SWX Rd,Ra,Rb 110110 Rd Ra Rb 10000000000 Addr := Ra + Rb

SWEA Rd,Ra,Rb 110110 Rd Ra Rb 00010000000 Addr := Ra & Rb

110100 Rd Ra Rb 00000000000

01000000000

110101 Rd Ra Rb 00000000000

01000000000

110110 Rd Ra Rb 00000000000

01000000000

Addr := Ra + Rb

*Addr[0:8] := Rd[24:31]

Addr := Ra + Rb

*Addr[0:16] := Rd[16:31]

Addr := Ra + Rb

*Addr := Rd

*Addr := Rd if Reservation = 1

Reservation := 0

*Addr := Rd

LBUI Rd,Ra,Imm 111000 Rd Ra Imm Addr := Ra + s(Imm)

Rd[0:23] := 0

Rd[24:31] := *Addr[0:7]

LHUI Rd,Ra,Imm 111001 Rd Ra Imm Addr := Ra + s(Imm)

Rd[0:15] := 0 Rd[16:31] := *Addr[0:15]

LWI Rd,Ra,Imm 111010 Rd Ra Imm Addr := Ra + s(Imm)

Rd := *Addr

SBI Rd,Ra,Imm 111100 Rd Ra Imm Addr := Ra + s(Imm)

*Addr[0:7] := Rd[24:31]

SHI Rd,Ra,Imm 111101 Rd Ra Imm Addr := Ra + s(Imm)

*Addr[0:15] := Rd[16:31]

SWI Rd,Ra,Imm 111110 Rd Ra Imm Addr := Ra + s(Imm)

*Addr := Rd

1. Due to the many different corner cases involved in floating-point arithmetic, only the normal behavior is described. A full description of the behavior can be found in Chapter 5, “MicroBlaze Instruction Set Architecture.”

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Chapter 2: MicroBlaze Architecture

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Semaphore Synchronization

The LWX and SWX instructions are used to implement common semaphore operations, including test and set, compare and swap, exchange memory, and fetch and add. They are also used to implement spinlocks.

These instructions are typically used by system programs and are called by application programs as needed.

Generally, a program uses LWX to load a semaphore from memory, causing the reservation to be set (the processor maintains the reservation internally). The program can compute a result based on the semaphore value and conditionally store the result back to the same memory location using the SWX instruction. The conditional store is performed based on the existence of the reservation established by the preceding LWX instruction. If the reservation exists when the store is executed, the store is performed and MSR[C] is cleared to 0. If the reservation does not exist when the store is executed, the target memory location is not modified and MSR[C] is set to 1.

If the store is successful, the sequence of instructions from the semaphore load to the semaphore store appear to be executed atomically—no other device modified the semaphore location between the read and the update. Other devices can read from the semaphore location during the operation.

For a semaphore operation to work properly, the LWX instruction must be paired with an SWX instruction, and both must specify identical addresses.

The reservation granularity in MicroBlaze is a word. For both instructions, the address must be word aligned. No unaligned exceptions are generated for these instructions.

The conditional store is always attempted when a reservation exists, even if the store address does not match the load address that set the reservation.

Only one reservation can be maintained at a time. The address associated with the reservation can be changed by executing a subsequent LWX instruction.

The conditional store is performed based upon the reservation established by the last LWX instruction executed. Executing an SWX instruction always clears a reservation held by the processor, whether the address matches that established by the LWX or not.

Reset, interrupts, exceptions, and breaks (including the BRK and BRKI instructions) all clear the reservation.

The following provides general guidelines for using the LWX and SWX instructions:

• The LWX and SWX instructions should be paired and use the same address.

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• An unpaired SWX instruction to an arbitrary address can be used to clear any reservation held by the processor.

Chapter 2: MicroBlaze Architecture

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• A conditional sequence begins with an LWX instruction. It can be followed by memory accesses and/or computations on the loaded value. The sequence ends with an SWX instruction. In most cases, failure of the SWX instruction should cause a branch back to the LWX for a repeated attempt.

• An LWX instruction can be left unpaired when executing certain synchronization primitives if the value loaded by the LWX is not zero. An implementation of Test and Set exemplifies this:

loop: lwx r5,r3,r0 ; load and reserve

bnei r5,next ; branch if not equal to zero addik r5,r5,1 ; increment value swx r5,r3,r0 ; try to store non-zero value addic r5,r0,0 ; check reservation bnei r5,loop ; loop if reservation lost

• Performance can be improved by minimizing looping on an LWX instruction that fails to return a desired value. Performance can also be improved by using an ordinary load instruction to do the initial value check. An implementation of a spinlock exemplifies this:

loop: lw r5,r3,r0 ; load the word

bnei r5,loop ; loop back if word not equal to 0 lwx r5,r3,r0 ; try reserving again bnei r5,loop ; likely that no branch is needed addik r5,r5,1 ; increment value swx r5,r3,r0 ; try to store non-zero value addic r5,r0,0 ; check reservation bnei r5,loop ; loop if reservation lost

• Minimizing the looping on an LWX/SWX instruction pair increases the likelihood that forward progress is made. The old value should be tested before attempting the store. If the order is reversed (store before load), more SWX instructions are executed and reservations are more likely to be lost between the LWX and SWX instructions.

Self-modifying Code

When using self-modifying code software must ensure that the modified instructions have been written to memory prior to fetching them for execution. There are several aspects to consider:

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• The instructions to be modified could already have been fetched prior to modification:

Into the instruction prefetch buffer

Into the instruction cache, if it is enabled

Into a stream buffer, if instruction cache stream buffers are used

Into the instruction cache, and then saved in a victim buffer, if victim buffers are

used.

To ensure that the modified code is always executed instead of the old unmodified code, software must handle all these cases.

• If one or more of the instructions to be modified is a branch, and the branch target cache is used, the branch target address might have been cached.

To avoid using the cached branch target address, software must ensure that the branch target cache is cleared prior to executing the modified code.

• The modified instructions might not have been written to memory prior to execution:

They might be en-route to memory, in temporary storage in the interconnect or the

memory controller.

They might be stored in the data cache, if write-back cache is used.

They might be saved in a victim buffer, if write-back cache and victim buffers are

used.

Software must ensure that the modified instructions have been written to memory before being fetched by the processor.

The annotated code below shows how each of the above issues can be addressed. This code assumes that both instruction cache and write-back data cache is used. If not, the corresponding instructions can be omitted.

The following code exemplifies storing a modified instruction:

swi r5,r6,0 ; r5 = new instruction

; r6 = physical instruction address wdc.flush r6,r0 ; flush write-back data cache line mbar 1 ; ensure new instruction is written to memory wic r7,r0 ; invalidate line, empty stream & victim buffers

; r7 = virtual instruction address mbar 2 ; empty prefetch buffer, clear branch target cache

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The physical and virtual addresses above are identical, unless MMU virtual mode is used. If the MMU is enabled, the code sequences must be executed in real mode, because WIC and WDC are privileged instructions. The first instruction after the code sequences above must not be modified, because it might have been prefetched.

X-Ref Target - Figure 2-2

R0 – R31

0 31

X19739-091117

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Chapter 2: MicroBlaze Architecture

Registers

MicroBlaze has an orthogonal instruction set architecture. It has thirty-two 32-bit general purpose registers and up to eighteen 32-bit special purpose registers, depending on configured options.

General Purpose Registers

The thirty-two 32-bit General Purpose Registers are numbered R0 through R31. The register file is reset on bit stream download (reset value is 0x00000000). The following figure is a representation of a General Purpose Register and register and the register reset value (if existing).

Note: The register file is not reset by the external reset inputs: Reset and Debug_Rst.

Table 2-7 provides a description of each

Figure 2-2: R0-R31

Table 2-7: General Purpose Registers (R0-R31)

Bits Name Description Reset Value

0:31 R0 Always has a value of zero. Anything written to R0 is

discarded

0:31 R1 through R13 32-bit general purpose registers -

0:31 R14 32-bit register used to store return addresses for

interrupts.

0:31 R15 32-bit general purpose register. Recommended for storing

return addresses for user vectors.

0:31 R16 32-bit register used to store return addresses for breaks. -

0:31 R17 If MicroBlaze is configured to support hardware

exceptions, this register is loaded with the address of the instruction following the instruction causing the HW exception, except for exceptions in delay slots that use BTR instead (see general purpose register.

0:31 R18 through R31 R18 through R31 are 32-bit general purpose registers. -

Branch Target Register (BTR)); if not, it is a

0x00000000

See Table 4-2 for software conventions on general purpose register usage.

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X-Ref Target - Figure 2-3

X19740-082517

RES

ReservedCC

3029282726252423222120191817

IECBIPFSLICEDZODCEEEEIPPVRUMUMSVMVMS

X19741-091117

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Chapter 2: MicroBlaze Architecture

Special Purpose Registers

Program Counter (PC)

The program counter (PC) is the 32-bit address of the execution instruction. It can be read with an MFS instruction, but it cannot be written with an MTS instruction. When used with the MFS instruction the PC register is specified by setting Sa = 0x0000. The following figure illustrates the PC and

Table 2-8: Program Counter (PC)

Bits Name Description Reset Value

Table 2-8 provides a description and reset value.

Figure 2-3: PC

X-Ref Target - Figure 2-4

0:31 PC Program Counter

Address of executing instruction, that is, “mfs r2, 0” stores the address of the mfs instruction itself in R2.

0x00000000

Machine Status Register (MSR)

The Machine Status Register contains control and status bits for the processor. It can be read with an MFS instruction. When reading the MSR, bit 29 is replicated in bit 0 as the carry copy. MSR can be written using either an

MSRCLR instructions.

When writing to the MSR using MSRSET or MSRCLR, the Carry bit takes effect immediately and the remaining bits take effect one clock cycle later. When writing using MTS, all bits take effect one clock cycle later. Any value written to bit 0 is discarded.

When used with an MTS or MFS instruction, the MSR is specified by setting Sx = 0x0001. The following table illustrates the MSR register and and reset values.

MTS instruction or the dedicated MSRSET and

Table 2-9 provides the bit description

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Figure 2-4: MSR

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Table 2-9: Machine Status Register (MSR)

Bits Name Description Reset Value

0 CC Arithmetic Carry Copy

Copy of the Arithmetic Carry (bit 29). CC is always the same as bit C.

1:16 Reserved

17 VMS Virtual Protected Mode Save

Only available when configured with an MMU

(if C_USE_MMU > 1 and C_AREA_OPTIMIZED = 0 or 2)

Read/Write

18 VM Virtual Protected Mode

0 = MMU address translation and access protection disabled, with

C_USE_MMU = 3 (Virtual). Access protection disabled with C_USE_MMU = 2 (Protection)

1 = MMU address translation and access protection enabled, with

C_USE_MMU = 3 (Virtual). Access protection enabled, with C_USE_MMU = 2 (Protection).

Only available when configured with an MMU

(if C_USE_MMU > 1 and C_AREA_OPTIMIZED = 0 or 2)

Read/Write

19 UMS User Mode Save

Only available when configured with an MMU

(if C_USE_MMU > 0 and C_AREA_OPTIMIZED = 0 or 2)

Read/Write

20 UM User Mode

0 = Privileged Mode, all instructions are allowed

1 = User Mode, certain instructions are not allowed

Only available when configured with an MMU

(if C_USE_MMU > 0 and C_AREA_OPTIMIZED = 0 or 2)

Read/Write

21 PVR Processor Version Register exists

0 = No Processor Version Register

1 = Processor Version Register exists

Read only

22 EIP Exception In Progress

0 = No hardware exception in progress

1 = Hardware exception in progress

Only available if configured with exception support

C_*_EXCEPTION or C_USE_MMU > 0)

(

Read/Write

Based on

parameter

C_PVR

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Table 2-9: Machine Status Register (MSR) (Cont’d)

Bits Name Description Reset Value

23 EE Exception Enable

0 = Hardware exceptions disabled

1 = Hardware exceptions enabled

Only available if configured with exception support

C_*_EXCEPTION or C_USE_MMU > 0)

(

Read/Write

24 DCE Data Cache Enable

0 = Data Cache disabled

1 = Data Cache enabled

Only available if configured to use data cache (C_USE_DCACHE = 1)

Read/Write

25 DZO Division by Zero or Division Overflow

0 = No division by zero or division overflow has occurred

1 = Division by zero or division overflow has occurred

Only available if configured to use hardware divider

(C_USE_DIV = 1)

Read/Write

26 ICE Instruction Cache Enable

0 = Instruction Cache disabled

1 = Instruction Cache enabled

Only available if configured to use instruction cache

(C_USE_ICACHE = 1)

Read/Write

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27 FSL AXI4-Stream Error

0 = get or getd had no error 1 = get or getd control type mismatch

This bit is sticky, that is it is set by a get or getd instruction when a control bit mismatch occurs. To clear it an MTS or MSRCLR instruction must be used.

Only available if configured to use stream links (C_FSL_LINKS > 0)

Read/Write

28 BIP Break in Progress

0 = No Break in Progress

1 = Break in Progress

Break Sources can be software break instruction or hardware break

Ext_Brk or Ext_NM_Brk pin.

from

Read/Write

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C_ADDR_SIZE - 1

EAR

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Table 2-9: Machine Status Register (MSR) (Cont’d)

Bits Name Description Reset Value

29 C Arithmetic Carry

0 = No Carry (Borrow)

1 = Carry (No Borrow)

Read/Write

30 IE Interrupt Enable

0 = Interrupts disabled

1 = Interrupts enabled

Read/Write

31 - Reserved 0

1. The MMU exceptions (Data Storage Exception, Instruction Storage Exception, Data TLB Miss Exception, Instruction TLB Miss Exception) cannot be disabled, and are not affected by this bit.

2. This bit is only used for integer divide-by-zero or divide overflow signaling. There is a floating-point equivalent in the FSR. The DZO-bit flags divide by zero or divide overflow conditions regardless if the processor is configured with exception handling or not.

Exception Address Register (EAR)

The Exception Address Register stores the full load/store address that caused the exception for the following:

• An unaligned access exception that specifies the unaligned access data address

X-Ref Target - Figure 2-5

•An

M_AXI_DP exception that specifies the failing AXI4 data access address

• A data storage exception that specifies the (virtual) effective address accessed

• An instruction storage exception that specifies the (virtual) effective address read

• A data TLB miss exception that specifies the (virtual) effective address accessed

• An instruction TLB miss exception that specifies the (virtual) effective address read

The contents of this register is undefined for all other exceptions. When read with the MFS or MFSE instruction, the EAR is specified by setting Sa = 0x0003. The EAR register is illustrated in the following figure and

Table 2-10 provides bit descriptions and reset values.

With extended data addressing is enabled (parameter C_ADDR_SIZE > 32), the 32 least significant bits of the register are read with the MFS instruction, and the most significant bits with the MFSE instruction.

Figure 2-5: EAR

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Reserved

2726

ESS

X19743-082517

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Chapter 2: MicroBlaze Architecture

Table 2-10: Exception Address Register (EAR)

Bits Name Description Reset Value

0:C_ADDR_SIZE-1 EAR Exception Address Register 0

Exception Status Register (ESR)

The Exception Status Register contains status bits for the processor. When read with the MFS instruction, the ESR is specified by setting Sa = 0x0005. The ESR register is illustrated in the following figure, provides the Exception Specific Status (ESS).

Table 2-11 provides bit descriptions and reset values, and Table 2-12

Figure 2-6: ESR

Table 2-11: Exception Status Register (ESR)

Bits Name Description Reset Value

0:18 Reserved

19 DS Delay Slot Exception.

0 = not caused by delay slot instruction

1 = caused by delay slot instruction

Read-only

20:26 ESS Exception Specific Status

For details, see Table 2-12.

Read-only

Table 2-12

See

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