Xilinx MicroBlaze Development Kit Spartan-3E 1600E User Manual

MicroBlaze Development Kit Spartan-3E 1600E Edition User Guide
UG257 (v1.1) December 5, 2007
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Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of the Design may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes.
Xilinx does not assume any liability arising out of the application or use of the Design; nor does Xilinx convey any license under its patents, copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Design. Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design.
THE DESIGN IS PROVIDED “AS IS” WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH YOU. YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE, WHETHER GIVEN BY XILINX, OR ITS AGENTS OR EMPLOYEES. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DESIGN, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND NONINFRINGEMENT OF THIRD-PARTY RIGHTS.
IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIA L, OR INCIDEN TAL DAMAGES, INCLUDING ANY LOST DATA AND LOST PROFITS, ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN, EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THE TOTAL CUMULATIVE LIABILITY OF XILINX IN CONNECTION WITH YOUR USE OF THE DESIGN, WHETHER IN CONTRACT OR TORT OR OTHERWISE, WILL IN NO EVENT EXCEED THE AMOUNT OF FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE DESIGN. YOU ACKNOWLEDGE THAT THE FEES, IF ANY, REFLECT THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE AVAILABLE THE DESIGN TO YOU WITHOUT THESE LIMITATIONS OF LIABILITY.
The Design is not designed or intended for use in the development of on-line control equipment in hazardous environments requiring fail­safe controls, such as in the operation of nuclear facilities, aircraft navigation or communications systems, air traffic control, life support, or weapons systems (“High-Risk Applications”). Xilinx specifically disclaims any express or implied warranties of fitness for such High-Risk Applications. You represent that use of the Design in such High-Risk Applications is fully at your risk.
© 2002-2006 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners.
Revision History
The following table shows the revision history for this document.
Date Version Revision
6/23/06 1.0 Initial release.
12/5/07 1.1 Updated Figures 15-8, 15-9, and 15-10 to comply with UCF I/O location constraints.
MicroBlaze Development Kit Spartan-3E 1600E Edition User Guidewww.xilinx.com UG257 (v1.1) December 5, 2007
Table of Contents
Preface: About This Guide
Acknowledgements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chapter 1: Introduction and Overview
Choose the Starter Kit Board for Your Needs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Spartan-3E FPGA Features and Embedded Processing Functions. . . . . . . . . . . . . . . . . 9
Learning Xilinx FPGA, CPLD, and ISE Development Software Basics . . . . . . . . . . . . . 9
Advanced Spartan-3 Generation Development Boards . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Key Components and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Design Trade-Offs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Configuration Methods Galore! . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Voltages for all Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Chapter 2: Switches, Buttons, and Knob
Slide Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Locations and Labels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Push-Button Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Locations and Labels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Rotary Push-Button Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Locations and Labels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Discrete LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Locations and Labels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Chapter 3: Clock Sources
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Clock Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Voltage Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
50 MHz On-Board Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Auxiliary Clock Oscillator Socket . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
SMA Clock Input or Output Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
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UCF Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Clock Period Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Chapter 4: FPGA Configuration Options
Configuration Mode Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
PROG Push Button. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
DONE Pin LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Programming the FPGA, CPLD, or Platform Flash PROM via USB . . . . . . . . . . . 27
Connecting the USB Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Programming via iMPACT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Programming Platform Flash PROM via USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Chapter 5: Character LCD Screen
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Character LCD Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Voltage Compatibility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Interaction with Intel StrataFlash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
LCD Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Four-Bit Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Transferring 8-Bit Data over the 4-Bit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Initializing the Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Writing Data to the Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Disabling the Unused LCD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
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Chapter 6: VGA Display Port
Signal Timing for a 60 Hz, 640x480 VGA Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
VGA Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Chapter 7: RS-232 Serial Ports
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Chapter 8: PS/2 Mouse/Keyboard Port
Keyboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Mouse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Voltage Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
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UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Chapter 9: Digital to Analog Converter (DAC)
SPI Communication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Disable Other Devices on the SPI Bus to Avoid Contention . . . . . . . . . . . . . . . . . . . . . 70
SPI Communication Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Communication Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Specifying the DAC Output Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
DAC Outputs A and B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
DAC Outputs C and D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Chapter 10: Analog Capture Circuit
Digital Outputs from Analog Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Programmable Pre-Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Programmable Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
SPI Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Analog to Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
SPI Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Disable Other Devices on the SPI Bus to Avoid Contention . . . . . . . . . . . . . . . . . . 81
Connecting Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Chapter 11: Intel StrataFlash Parallel NOR Flash PROM
StrataFlash Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Shared Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Character LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Xilinx XC2C64A CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
SPI Data Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Setting the FPGA Mode Select Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Chapter 12: SPI Serial Flash
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Configuring from SPI Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Setting the FPGA Mode Select Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
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Creating an SPI Serial Flash PROM File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Downloading the Design to SPI Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Downloading the SPI Flash using XSPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Additional Design Details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Shared SPI Bus with Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Other SPI Flash Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Variant Select Pins, VS[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Jumper Block J11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Programming Header J12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Multi-Package Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Chapter 13: DDR SDRAM
DDR SDRAM Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Reserve FPGA VREF Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
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Chapter 14: 10/100 Ethernet Physical Layer Interface
Ethernet PHY Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
MicroBlaze Ethernet IP Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Chapter 15: Expansion Connectors
Hirose 100-pin FX2 Edge Connector (J3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Voltage Supplies to the Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Connector Pinout and FPGA Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Compatible Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Mating Receptacle Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Differential I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Six-Pin Accessory Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Header J1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Header J2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Header J4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Connectorless Debugging Port Landing Pads (J6) . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Chapter 16: XC2C64A CoolRunner-II CPLD
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
FPGA Connections to CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
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Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Chapter 17: DS2432 1-Wire SHA-1 EEPROM
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Appendix A: Schematics
FX2 Expansion Header, 6-pin Headers, and Connectorless Probe Header . . . . 134
RS-232 Ports, VGA Port, and PS/2 Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Ethernet PHY, Magnetics, and RJ-11 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Voltage Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
FPGA Configurations Settings, Platform Flash PROM, SPI Serial Flash, JTAG
Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
FPGA I/O Banks 0 and 1, Oscillators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
FPGA I/O Banks 2 and 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Power Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
XC2C64A CoolRunner-II CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Linear Technology ADC and DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Intel StrataFlash Parallel NOR Flash Memory and Micron DDR SDRAM . . . 154
Buttons, Switches, Rotary Encoder, and Character LCD . . . . . . . . . . . . . . . . . . . . . 156
DDR SDRAM Series Termination and FX2 Connector Differential Termination 158
Appendix B: Example User Constraints File (UCF)
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About This Guide
This user guide provides basic information on the MicroBlaze Development Kit board capabilities, functions, and design. It includes general information on how to use the various peripheral functions included on the board. For detailed reference designs, including VHDL or Verilog source code, please visit the following web link.
x Spartan™-3E Starter Kit Board Reference Page
http://www.xilinx.com/
Acknowledgements
Xilinx wishes to thank the following companies for their support of the MicroBlaze Development Kit board:
Preface
sp3e1600e
x Intel Corporation for the 128 Mbit StrataFlash memory
x Linear Technology for the SPI-compatible A/D and D/A converters, the
x Micron Technology, Inc. for the 32M x 16 DDR SDRAM
x SMSC for the 10/100 Ethernet PHY
x STMicroelectronics for the 16M x 1 SPI serial Flash PROM
x Tex as I ns tr um en ts I nc orp or at ed f or th e th ree-rail TPS75003 regulator supplying most
x Xilinx, Inc. Configuration Solutions Division for the XCF04S Platform Flash PROM
x Xilinx, Inc. CPLD Division for the XC2C64A CoolRunner™-II CPLD
Guide Contents
This manual contains the following chapters:
x Chapter 1, “Introduction and Overview,” provides an overview of the key features of
x Chapter 2, “Switches, Buttons, and Knob,” defines the switches, buttons, and knobs
x Chapter 3, “Clock Sources,” describes the various clock sources available on the
x Chapter 4, “FPGA Configuration Options,” describes the configuration options for
programmable pre-amplifier, and the power regulators for the non-FPGA components
of the FPGA supply voltages
and their support for the embedded USB programmer
the MicroBlaze Development Kit board.
present on the MicroBlaze Development Kit board.
MicroBlaze Development Kit board.
the FPGA on the MicroBlaze Development Kit board.
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Preface: About This Guide
x Chapter 5, “Character LCD Screen,” describes the functionality of the character LCD
x Chapter 6, “VGA Display Port,” describes the functionality of the VGA port.
x Chapter 7, “RS-232 Serial Ports,” describes the functionality of the RS-232 serial ports.
x Chapter 8, “PS/2 Mouse/Keyboard Port,” describes the functionality of the PS/2
x Chapter 9, “Digital to Analog Converter (DAC),” describes the functionality of the
x Chapter 10, “Analog Capture Circuit,” describes the functionality of the A/D
x Chapter 11, “Intel StrataFlash Parallel NOR Flash PROM,” describes the functionality
x Chapter 12, “SPI Serial Flash,” describes the functionality of the SPI Serial Flash
x Chapter 13, “DDR SDRAM,” describes the functionality of the DDR SDRAM.
x Chapter 14, “10/100 Ethernet Physical Layer Interface,” describes the functionality of
x Chapter 15, “Expansion Connectors,” describes the various connectors available on
x Chapter 16, “XC2C64A CoolRunner-II CPLD” describes how the CPLD is involved in
x Chapter 17, “DS2432 1-Wire SHA-1 EEPROM” provides a brief introduction to the
x Appendix A, “Schematics,” lists the schematics for the MicroBlaze Development Kit
x Appendix B, “Example User Constraints File (UCF),” provides example code from a
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screen.
mouse and keyboard port.
DAC.
converter with a programmable gain pre-amplifier.
of the StrataFlash PROM.
memory.
the 10/100Base-T Ethernet physical layer interface.
the MicroBlaze Development Kit board.
FPGA configuration when using Master Serial and BPI mode.
SHA-1 secure EEPROM for authenticating or copy-protecting FPGA configuration bitstreams.
board.
UCF.
Additional Resources
To fi nd a dd ti on al r es ou rc es fo r th e Mi croBlaze Processor or the Xilinx Embedded development tools, see the Xilinx website at:
http://www.Xilinx.com/Microblaze
To fi nd a dd it io na l do cum en ta ti on, see the Xilinx website at:
http://www.xilinx.com/literature
To se ar ch t he A nsw er D at ab as e of s il ico n, s of tw ar e, a nd I P qu es ti on s an d ans we rs , or t o create a technical support WebCase, see the Xilinx website at:
http://www.xilinx.com/support
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Introduction and Overview
Thank you for purchasing the Xilinx MicroBlaze™ Development Kit Spartan™-3E 1600E Edition. You will find it useful in developing your Spartan-3E FPGA application.
Choose the Starter Kit Board for Your Needs
Depending on specific requirements, choose the Xilinx development board that best suits your needs.
Spartan-3E FPGA Features and Embedded Processing Functions
Chapter 1
The MicroBlaze Development Kit board highlights the unique features of the Spartan-3E FPGA family and provides a convenient development board for embedded processing applications. The board highlights these features:
x Spartan-3E specific features
i Parallel NOR Flash configuration
i MultiBoot FPGA configuration from Parallel NOR Flash PROM
i SPI serial Flash configuration
x Embedded development
i MicroBlaze 32-bit embedded RISC processor
i PicoBlaze™ 8-bit embedded controller
i DDR memory interfaces
i 10-100 Ethernet
i UART
Learning Xilinx FPGA, CPLD, and ISE Development Software Basics
The MicroBlaze Development Kit board is more advanced and complex compared to other Spartan development boards.
Advanced Spartan-3 Generation Development Boards
The MicroBlaze Development Kit board demonstrates the basic capabilities of the MicroBlaze embedded processor and the Xilinx Embedded Development Kit (EDK). For more advanced development on a board with additional peripherals and FPGA logic, consider the V4 FX12 Board:
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Chapter 1: Introduction and Overview
x http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=DO-
ML403-EDK-ISE
Also consider the capable boards offered by Xilinx partners:
x h
ttp://www.xilinx.com/products/devboards/index.htm
Key Components and Features
The key features of the MicroBlaze Development Kit board are:
x Xilinx XC3S1600E Spartan-3E FPGA
i Up to 250
i user-I/O pins
i 320-pin FBGA package
i Over 33,000 logic cells
x Two X il in x 4 Mb it P la tf or m Fl as h co nf ig ur at io n P RO M
x Xilinx 64-macrocell XC2C64A CoolRunner CPLD
x 64 MByte (512 Mbit) of DDR SDRAM, x16 data interface, 100+ MHz
x 16 MByte (128 Mbit) of parallel NOR Flash (Intel StrataFlash)
i FPGA configuration storage
i MicroBlaze code storage/shadowing
x 16 Mbits of SPI serial Flash (STMicro)
i FPGA configuration storage
i MicroBlaze code shadowing
x 2 x 16 LCD display screen
x PS/2 mouse or keyboard port
x VGA display port
x 10/100 Ethernet PHY (requires Ethernet MAC in FPGA)
x Two 9 -p in R S- 232 p or ts ( DT E- a nd D CE- st yl e)
x On-board USB-based FPGA/CPLD download/debug interface
x 50 MHz and 66 MHz clock oscillators
x SHA-1 1-wire serial EEPROM for bitstream copy protection
x Hirose FX2 expansion connector with 40-user I/O
x Three Digilent 6-pin expansion connectors
x Four-output, SPI-based Digital-to-Analog Converter (DAC)
x Two -i np ut , SP I- ba se d An al og -to-Digital Converter (ADC) with programmable-gain
pre-amplifier
x ChipScope™ SoftTouch debugging port
x Rotary-encoder with push-button shaft
x Eight discrete LEDs
x Four slide switches
x Four push-button switches
x SMA clock input
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x 8-pin DIP socket for auxiliary clock oscillator
Design Trade-Offs
A few system-level design trade-offs were required in order to provide the MicroBlaze Development Kit board with the most functionality.
Configuration Methods Galore!
A typical FPGA application uses a single non-volatile memory to store configuration images. To demonstrate new Spartan-3E capabilities, the MicroBlaze Development Kit board has three different configuration memory sources that all need to function well together. The extra configuration functions make the starter kit board more complex than typical Spartan-3E applications.
The starter kit board also includes an on-board USB-based JTAG programming interface. The on-chip circuitry simplifies the device programming experience. In typical applications, the JTAG programming hardware resides off-board or in a separate programming module, such as the Xilinx Platform USB cable. This USB port is for programming only and can not be used as an independent USB interface.
Design Trade-Offs
Volta ges fo r all Ap plicatio ns
The MicroBlaze Development Kit board showcases a triple-output regulator developed by Tex as I ns tr um en ts , th e TPS75003 This regulator is sufficient for most stand-alone FPGA applications. However, the starter kit board includes DDR SDRAM, which requires its own high-current supply. Similarly, the USB-based JTAG download solution requires a separate 1.8V supply.
Related Resources
x Xilinx MicroBlaze Soft Processor
http://www.xilinx.com/microblaze
x Xilinx PicoBlaze Soft Processor
http://www.xilinx.com/picoblaze
x Xilinx Embedded Development Kit
http://www.xilinx.com/ise/embedded_design_prod/platform_studio.htm
x Xilinx software tutorials
http://www.xilinx.com/support/techsup/tutorials/
x Tex as I ns tr um en ts T PS 75 00 3
http://focus.ti.com/docs/prod/folders/print/tps75003.html
specifically to power Spartan-3 and Spartan-3E FPGAs.
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Switches, Buttons, and Knob
Slide Switches
Locations and Labels
The MicroBlaze Development Kit board has four slide switches, as shown in Figure 2-1. The slide switches are located in the lower right corner of the board and are labeled SW3 through SW0. Switch SW3 is the left-most switch, and SW0 is the right-most switch.
Spartan-3E Development Board
Chapter 2
Operation
When in the UP or ON position, a switch connects the FPGA pin to 3.3V, a logic High. When DOWN or in the OFF position, the switch connects the FPGA pin to ground, a logic Low. The switches typically exhibit about 2 ms of mechanical bounce and there is no active debouncing circuitry, although such circuitry could easily be added to the FPGA design programmed on the board.
UCF Location Constraints
Figure 2-2 provides the UCF constraints for the four slide switches, including the I/O pin
assignment and the I/O standard used. The PULLUP resistor is not required, but it defines the input value when the switch is in the middle of a transition.
SW3
Figure 2-1: Four Slide Switches
SW0
HIGH
LOW
UG257_02_01_061306
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NET "SW<0>" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ; NET "SW<1>" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ; NET "SW<2>" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ; NET "SW<3>" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP ;
Push-Button Switches
Locations and Labels
The MicroBlaze Development Kit board has four momentary-contact push-button switches, shown in Figure 2-3. The push buttons are located in the lower left corner of the board and are labeled BTN_NORTH, BTN_EAST, BTN_SOUTH, and BTN_WEST. The FPGA pins that connect to the push buttons appear in parentheses in Figure 2-3 and the associated UCF appears in Figure 2-5.
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UG257_02_060206
Figure 2-2: UCF Constraints for Slide Switches
Operation
Rotary Push Button Switch ROT_A:(K18) requires an internal pull-up
BTN_NORTH (V4)
BTN_WEST (D18)
BTN_SOUTH (K17)
BTN_EAST (H13)
Notes:
1. All BTN_* push-button inputs require an internal pull-down resistor.
2. BTN_SOUTH is also used as a soft reset in some FPGA applications
ROT_B:(G18) requires an internal pull-up ROT_Center:(V16) requires an internal pull-down
Spartan-3E Development Board
UG257_02_03_061306
Figure 2-3: Four Push-Button Switches Surround Rotary Push-Button Switch
Pressing a push button connects the associated FPGA pin to 3.3V, as shown in Figure 2-4. Use an internal pull-down resistor within the FPGA pin to generate a logic Low when the button is not pressed. Figure 2-5 shows how to specify a pull-down resistor within the UCF. There is no active debouncing circuitry on the push button.
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Rotary Push-Button Switch
3.3V
Figure 2-4: Push-Button Switches Require an Internal Pull-Down Resistor in FPGA
In some applications, the BTN_SOUTH push-button switch is also a soft reset that selectively resets functions within the FPGA.
UCF Location Constraints
Figure 2-5 provides the UCF constraints for the four push-button switches, including the
I/O pin assignment and the I/O standard used, and defines a pull-down resistor on each input.
NET "BTN_EAST" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN ; NET "BTN_NORTH" LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN ; NET "BTN_SOUTH" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ; NET "BTN_WEST" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN ;
Push Button
FPGA I/O Pin
BTN_* Signal
UG227_02_04_060206
Input Pin
UG257_02_05_060206
Figure 2-5: UCF Constraints for Push-Button Switches
Rotary Push-Button Switch
Locations and Labels
The rotary push-button switch is located in the center of the four individual push-button switches, as shown in Figure 2-3. The switch produces three outputs. The two shaft encoder outputs are ROT_A and ROT_B. The center push-button switch is ROT_CENTER.
Operation
The rotary push-button switch integrates two different functions. The switch shaft rotates and outputs values whenever the shaft turns. The shaft can also be pressed, acting as a push-button switch.
Push-Button Switch
Pressing the knob on the rotary/push-button switch connects the associated FPGA pin to
3.3V, as shown in Figure 2-6. Use an internal pull-down resistor within the FPGA pin to generate a logic Low. Figure 2-9 shows how to specify a pull -down resistor within the UCF. There is no active debouncing circuitry on the push button.
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Rotary / Push Button
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3.3V
FPGA I/O Pin
ROT_CENTER Signal
UG257_02_06_060906
Figure 2-6: Push-Button Switches Require Internal Pull-up Resistor in FPGA Input
Pin
Rotary Shaft Encoder
In principal, the rotary shaft encoder behaves much like a cam, connected to central shaft. Rotating the shaft then operates two push-button switches, as shown in Figure 2-7. Depending on which way the shaft is rotated, one of the switches opens before the other. Likewise, as the rotation continues, one switch closes before the other. However, when the shaft is stationary, also called the detent position, both switches are closed.
A pull-up resistor in each input pin generates a ‘1’ for an open switch. See the UCF file for details on specifying the pull-up resistor.
A=‘0’
FPGA
Vcco
Vcco
Rotary Shaft
Encoder
B=‘1’
GND
UG257_02_07_060206
Figure 2-7: Basic example of rotary shaft encoder circuitry
Closing a switch connects it to ground, generating a logic Low. When the switch is open, a pull-up resistor within the FPGA pin pulls the signal to a logic High. The UCF constraints in Figure 2-9 describe how to define the pull-up resistor.
The FPGA circuitry to decode the ‘A’ and ‘B’ inputs is simple, but must consider the mechanical switching noise on the inputs, also called chatter. As shown in Figure 2-8, the chatter can falsely indicate extra rotation events or even indicate rotations in the opposite direction! See the Rotary Encoder Interface reference design in“Related Resources” for an example.
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Discrete LEDs
Rising edge on ‘A’ when ‘B’ is Low indicates RIGHT (clockwise) rotation
Rotating RIGHT
A
B
Detent
Figure 2-8: Outputs from Rotary Shaft Encoder May Include Mechanical Chatter
UCF Location Constraints
Figure 2-9 provides the UCF constraints for the four push-button switches, including the
I/O pin assignment and the I/O standard used, and defines a pull-down resistor on each input.
NET "ROT_A" LOC = "K18" | IOSTANDARD = LVTTL | PULLUP ; NET "ROT_B" LOC = "G18" | IOSTANDARD = LVTTL | PULLUP ; NET "ROT_CENTER" LOC = "V16" | IOSTANDARD = LVTTL | PULLDOWN ;
Switch opening chatter on ‘A’ injects false “clicks” to the RIGHT
Switch closing chatter on ‘B’ injects false “clicks” to the LEFT (’B’ rising edge when ‘A’ is Low)
Detent
UG257_02_08_060206
UG257_03_060206
Discrete LEDs
Locations and Labels
Figure 2-9: UCF Constraints for Rotary Push-Button Switch
The MicroBlaze Development Kit board has eight individual surface-mount LEDs located above the slide switches as shown in Figure 2-10. The LEDs are labeled LED7 through LED0. LED7 is the left-most LED, LED0 the right-most LED.
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Spartan-3E Development Board
Operation
Each LED has one side connected to ground and the other side connected to a pin on the Spartan-3E device via a 390: current limiting resistor. To light an individual LED, drive the associated FPGA control signal High.
UCF Location Constraints
Figure 2-11 provides the UCF constraints for the four push-button switches, including the
I/O pin assignment, the I/O standard used, the output slew rate, and the output drive current.
LED7
Figure 2-10: Eight Discrete LEDs
LED0
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NET "LED<7>" LOC = "A8" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; NET "LED<6>" LOC = "G9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; NET "LED<5>" LOC = "A7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; NET "LED<4>" LOC = "D13" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; NET "LED<3>" LOC = "E6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; NET "LED<2>" LOC = "D6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; NET "LED<1>" LOC = "C3" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; NET "LED<0>" LOC = "D4” | IOSTANDARD = SSTL2_I ;
Related Resources
x Rotary Encoder Interface for Spartan-3E Starter Kit (Reference Design)
http://www.xilinx.com/s3estarter
http://www.xilinx.com/sp3e1600E
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Figure 2-11: UCF Constraints for Eight Discrete LEDs
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Clock Sources
Overview
As shown in Figure 3-1, the MicroBlaze Development Kit board supports three primary clock input sources, all of which are located below the Xilinx logo, near the Spartan-3E logo.
x The board includes an on-board 50 MHz clock oscillator.
x The user clock socket is populated with a 66 MHz oscillator
x Clocks can be supplied off-board via an SMA-style connector. Alternatively, the FPGA
can generate clock signals or other high-speed signals on the SMA-style connector.
x Optionally install a separate 8-pin DIP-style clock oscillator in the supplied socket
Chapter 3
.
8-Pin DIP Oscillator Socket
Bank 0, Oscillator Voltage
(Controlled by Jumper JP9)
Spartan-3E Development Board
On-Board 50 MHz Oscillator
CLK_50MHz:[C9]
CLK_AUX:[B8]
SMA Connector
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Figure 3-1: Available Clock Inputs
Chapter 3: Clock Sources
Clock Connections
Each of the clock inputs connect directly to a global buffer input in I/O Bank 0, along the top of the FPGA. As shown in Table 3-1, each of the clock inputs also optimally connects to an associated DCM.
Ta bl e 3 - 1: Clock Inputs and Associated Global Buffers and DCMs
Clock Input FPGA Pin Global Buffer Associated DCM
CLK_50MHZ C9 GCLK10 DCM_X0Y1
CLK_AUX B8 GCLK8 DCM_X0Y1
CLK_SMA A10 GCLK7 DCM_X1Y1
Voltage Control
The voltage for all I/O pins in FPGA I/O Bank 0 is controlled by jumper JP9. Consequently, these clock resources are also controlled by jumper JP9. By default, JP9 is set for 3.3V. The on-board oscillator is a 3.3V device and might not perform as expected when jumper JP9 is set for 2.5V.
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50 MHz On-Board Oscillator
The board includes a 50 MHz oscillator with a 40% to 60% output duty cycle. The oscillator is accurate to
±2500 Hz or ±50 ppm.
Auxiliary Clock Oscillator Socket
The provided 8-pin socket accepts clock oscillators that fit the 8-pin DIP footprint. Use this socket if the FPGA application requires a frequency other than 50 MHz. This socket is populated with a 66 MHz oscillator. This clock input is used for some of the reference designs provided with the board. Alternatively, use the FPGA’s Digital Clock Manager (DCM) to generate or synthesize other frequencies from the on-board 50 MHz oscillator.
SMA Clock Input or Output Connector
To pr ov id e a cl oc k fr om a n ex te rna l so urc e, c onn ec t th e in put c lo ck s ig na l to th e SM A connector. The FPGA can also generate a single-ended clock output or other high-speed signal on the SMA clock connector for an external device.
UCF Constraints
The clock input sources require two different types of constraints. The location constraints define the I/O pin assignments and I/O standards. The period constraints define the clock period—and consequently the clock frequency—and the duty cycle of the incoming clock signal.
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Location
Figure 3-2 provides the UCF constraints for the three clock input sources, including the
I/O pin assignment and the I/O standard used. The settings assume that jumper JP9 is set for 3.3V. If JP9 is set for 2.5V, adjust the IOSTANDARD settings accordingly.
NET "CLK_50MHZ" LOC = "C9" | IOSTANDARD = LVCMOS33 ; NET "CLK_SMA" LOC = "A10" | IOSTANDARD = LVCMOS33 ; NET "CLK_AUX" LOC = "B8" | IOSTANDARD = LVCMOS33 ;
Figure 3-2: UCF Location Constraints for Clock Sources
Clock Period Constraints
The Xilinx ISE development software uses timing-driven logic placement and routing. Set the clock PERIOD constraint as appropriate. An example constraint appears in Figure 3-3 for the on-board 50 MHz clock oscillator. The CLK_50MHZ frequency is 50 MHz, which equates to a 20 ns period. The output duty cycle from the oscillator ranges between 40% to 60%.
Related Resources
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Related Resources
x Epson SG-8002JF Series Oscillator Data Sheet (50 MHz Oscillator)
http://www.eea.epson.com/go/Prod_Admin/Categories/EEA/QD/Crystal_Oscillators/ prog_oscillators/go/Resources/TestC2/SG8002JF
# Define clock period for 50 MHz oscillator NET "CLK_50MHZ" PERIOD = 20.0ns HIGH 40%;
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Figure 3-3: UCF Clock PERIOD Constraint
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Chapter 3: Clock Sources
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FPGA Configuration Options
The MicroBlaze Development Kit board supports a variety of FPGA configuration options:
x Download FPGA designs directly to the Spartan-3E FPGA via JTAG, using the on-
board USB interface. The on-board USB-JTAG logic also provides in-system programming for the on-board Platform Flash PROM and the Xilinx XC2C64A CPLD. SPI serial Flash and StrataFlash programming are performed separately.
x Program the on-board 4 Mbit Xilinx XCF04S serial Platform Flash PROM, then
configure the FPGA from the image stored in the Platform Flash PROM using Master Serial mode.
x Program the on-board 16 Mbit ST Microelectronics SPI serial Flash PROM, then
configure the FPGA from the image stored in the SPI serial Flash PROM using SPI mode.
x Program the on-board 128 Mbit Intel StrataFlash parallel NOR Flash PROM, then
configure the FPGA from the image stored in the Flash PROM using BPI Up or BPI Down configuration modes. Further, an FPGA application can dynamically load two different FPGA configurations using the Spartan-3E FPGA’s MultiBoot mode. See the Spartan-3E data sheet (DS312
) for additional details on the MultiBoot feature.
Chapter 4
Figure 4-1 indicates the position of the USB download/programming interface and the on-
board non-volatile memories that potentially store FPGA configuration images. Figure 4-2 provides additional details on configuration options.
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Chapter 4: FPGA Configuration Options
16 Mbit ST Micro SPI Serial Flash
Uses Peripheral Interface (SPI) Mode
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Configuration Options
PROG_B button, Platform Flash PROM, mode pins
USB-based Download and Debug Port
Uses standard USB cable
128 Mbit Intel StrataFlash
Parallel NOR Flash Memory Byte Peripheral Interface (BPI) mode
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Figure 4-1: MicroBlaze Development Kit Board FPGA Configuration Options
Configuration Mode Jumper Settings (Header J30)
DONE Pin LED
Spartan-3E Development Board
4 Mbit Xilinx Platform Flash PROM
Configuration storage for Master Serial
mode (one XC04S on front and
one on the back of the board”
64 Macrocell Xilinx XC2C64A CoolRunner CPLD
Controller upper address lines in BPI mode and
Platform Flash chip select (User programmable)
PROG_B Push Button Switch
Press and release to restart configuration
Lights up when FPGA successfully configured
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Figure 4-2: Detailed Configuration Options
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The configuration mode jumpers determine which configuration mode the FPGA uses when power is first applied, or whenever the PROG button is pressed.
The DONE pin LED lights when the FPGA successfully finishes configuration.
Pressing the PROG button forces the FPGA to restart its configuration process.
The 4 Mbit Xilinx Platform Flash PROM provides easy, JTAG-programmable configuration storage for the FPGA. The FPGA configures from the Platform Flash using Master Serial mode.
The 64-macrocell XC2C64A CoolRunner II CPLD provides additional programming capabilities and flexibility when using the BPI Up, BPI Down, or MultiBoot configuration modes and loading the FPGA from the StrataFlash parallel Flash PROM. The CPLD is user­programmable.
Configuration Mode Jumpers
As shown in Table 4-1, the J30 jumper block settings control the FPGA’s configuration mode. Inserting a jumper grounds the associated mode pin. Insert or remove individual jumpers to select the FPGA’s configuration mode and associated configuration memory source.
Configuration Mode Jumpers
Ta bl e 4 - 1: MicroBlaze Development Kit Board Configuration Mode Jumper Settings
(Header J30 in Figure 4-2)
Configuration
Mode
Master Serial 000 Platform Flash PROM
SPI
(see
Chapter 12, “SPI Serial Flash”)
BPI Up
(see
Chapter 11, “Intel StrataFlash Parallel NOR
Mode Pins
M2:M1:M0 FPGA Configuration Image Source Jumper Settings
M0 M1 M2
J30
001 SPI Serial Flash PROM starting at
address 0
010 StrataFlash parallel Flash PROM,
starting at address 0 and incrementing through address space. The CPLD controls address lines A[24:20] during BPI configuration.
M0 M1 M2
J30
M0 M1 M2
J30
Flash PROM”)
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Chapter 4: FPGA Configuration Options
Ta bl e 4 - 1: MicroBlaze Development Kit Board Configuration Mode Jumper Settings
(Header J30 in Figure 4-2)
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Configuration
Mode
BPI Down
(see
Chapter 11, “Intel StrataFlash Parallel NOR Flash PROM”)
JTAG 101 Downloaded from host via USB-
PROG Push Button
The PROG push button, shown in Figure 4-2, page 24, forces the FPGA to reconfigure from the selected configuration memory source. Press and release this button to restart the FPGA configuration process at any time.
Mode Pins
M2:M1:M0 FPGA Configuration Image Source Jumper Settings
011 StrataFlash parallel Flash PROM,
starting at address 0x1FF_FFFF and decrementing through address space. The CPLD controls address lines A[24:20] during BPI configuration.
JTAG port
M0 M1 M2
J30
M0 M1 M2
J30
DONE Pin LED
The DONE pin LED, shown in Figure 4-2, page 24, lights whenever the FPGA is successfully configured. If this LED is not lit, then the FPGA is not configured.
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Programming the FPGA, CPLD, or Platform Flash PROM via USB
Programming the FPGA, CPLD, or Platform Flash PROM via USB
As shown in Figure 4-1, page 24, the MicroBlaze Development Kit board includes embedded USB-based programming logic and an USB endpoint with a Type B connector. Via a USB cable connection with the host PC, the iMPACT programming software directly programs the FPGA, the Platform Flash PROM, or the on-board CPLD. Direct programming of the parallel or serial Flash PROMs is not presently supported.
Connecting the USB Cable
The kit includes a standard USB Type A/Type B cable, similar to the one shown in
Figure 4-3. The actual cable color might vary from the picture.
USB Type B Connector
Connects to USB connector on Starter Kit
USB Type A Connector
Connects to USB connector on computer
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Figure 4-3: Standard USB Type A/Type B Cable
The wider and narrower Type A connector fits the USB connector at the back of the computer.
After installing the Xilinx software, connect the square Type B connector to the MicroBlaze Development Kit board, as shown in Figure 4-4. The USB connector is on the left side of the board, immediately next to the Ethernet connector. When the board is powered on, the Windows operating system should recognize and install the associated driver software.
Figure 4-4: Connect the USB Type B Connector to the MicroBlaze Development Kit
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Board Connector
Chapter 4: FPGA Configuration Options
0
When the USB cable driver is successfully installed and the board is correctly connected to the PC, a green LED lights up, indicating a good connection.
Programming via iMPACT
After successfully compiling an FPGA design using the Xilinx development software, the design can be downloaded using the iMPACT programming software and the USB cable.
To be gi n p ro gr am mi ng , co nn ec t th e U SB c ab le t o the starter kit board and apply power to the board. Then, double-click Configure Device (iMPACT) from within Project Navigator, as shown in Figure 4-5.
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Figure 4-5: Double-Click to Invoke iMPACT
If the board is connected properly, the iMPACT p ro gr am mi ng so ft ware automatically recognizes the three devices in the JTAG programming file, as shown in Figure 4-6. If not already prompted, click the first device in the chain, the Spartan-3E FPGA, to highlight it. Right-click the FPGA and select Assign New Configuration File. Select the desired FPGA configuration file and click OK.
Figure 4-6: Right-Click to Assign a Configuration File to the Spartan-3E FPGA
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Programming the FPGA, CPLD, or Platform Flash PROM via USB
If the original FPGA configuration file used the default StartUp clock source, CCLK, iMPACT issues the warning message shown in Figure 4-7. This message can be safely ignored. When downloading via JTAG, the iMPACT software must change the StartUP clock source to use the TCK JTAG clock source.
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Figure 4-7: iMPACT Issues a Warning if the StartUp Clock Was Not CCLK
To st ar t pr og ra mm in g th e FP GA , ri gh t-c li ck t he F PG A an d se le ct Program. The iMPACT software reports status during programming process. Direct programming to the FPGA takes a few seconds to less than a minute, depending on the speed of the PC’s USB port and the iMPACT settings.
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Figure 4-8: Right-Click to Program the Spartan-3E FPGA
When the FPGA successfully programs, the iMPACT software indicates success, as shown in Figure 4-9. The FPGA application is now executing on the board and the DONE pin LED (see Figure 4-2) lights up.
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Chapter 4: FPGA Configuration Options
Figure 4-9: iMPACT Programming Succeeded, the FPGA’s DONE Pin is High
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Programming Platform Flash PROM via USB
The on-board USB-JTAG circuitry also programs the two Xilinx XCF04S serial Platform Flash PROM. The steps provided in this section describe how to set up the PROM file and how to download it to the board to ultimately program the FPGA.
Generating the FPGA Configuration Bitstream File
Before generating the PROM file, create the FPGA bitstream file. The FPGA provides an output clock, CCLK, when loading itself from an external PROM. The FPGA’s internal CCLK oscillator always starts at its slowest setting, approximately 1.5 MHz. Most external PROMs support a higher frequency. Increase the CCLK frequency as appropriate to reduce the FPGA’s configuration time. The Xilinx XCF04S Platform Flash supports a 25 MHz CCLK frequency.
Right-click Generator Programming File in the Processes pane, as shown in
Figure 4-10. Left-click Properties.
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Programming the FPGA, CPLD, or Platform Flash PROM via USB
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Figure 4-10: Set Properties for Bitstream Generator
Click Configuration Options as shown in Figure 4-11. Using the Configuration Rate drop list, choose 25 to increase the internal CCLK oscillator to approximately
25 MHz, the fastest frequency when using an XCF04S Platform Flash PROM. Click OK when finished.
Figure 4-11: Set CCLK Configuration Rate under Configuration Options
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Chapter 4: FPGA Configuration Options
To re ge ne ra te t he p ro gr am mi ng f ile , do ub le -c li ck Generate Programming File, as shown in Figure 4-12.
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Figure 4-12: Double-Click Generate Programming File
Generating the PROM File
After generating the program file, double-click Generate PROM, ACE, or JTAG File to launch the iMPACT software, as shown in Figure 4-13.
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After iMPACT starts, double-click PROM File Formatter, as shown in Figure 4-14.
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Figure 4-13: Double-Click Generate PROM, ACE, or JTAG File
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Programming the FPGA, CPLD, or Platform Flash PROM via USB
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Figure 4-14: Double-Click PROM File Formatter
Choose Xilinx PROM as the target PROM type, as shown in Figure 4-15. Select from any of the PROM File Formats; the Intel Hex format (MCS) is popular. Enter the Location of the directory and the PROM File Name. Click Next > when finished.
Figure 4-15: Choose the PROM Target Type, the, Data Format, and File Location
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Chapter 4: FPGA Configuration Options
The Spartan-3E Starter Kit board has an XCF04S Platform Flash PROM. Select xcf04s from the drop list, as shown in Figure 4-16. Click Add, then click Next >.
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Figure 4-16: Choose the XCF04S Platform Flash PROM
The PROM Formatter then echoes the settings, as shown in Figure 4-17. Click Finish.
Figure 4-17: Click Finish after Entering PROM Formatter Settings
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Programming the FPGA, CPLD, or Platform Flash PROM via USB
The PROM Formatter then prompts for the name(s) of the FPGA configuration bitstream file. As shown in Figure 4-18, click OK to start selecting files. Select an FPGA bitstream file (*.bit). Choose No after selecting the last FPGA file. Finally, click OK to continue.
When PROM formatting is complete, the iMPACT software presents the present settings by showing the PROM, the select FPGA bitstream(s), and the amount of PROM space consumed by the bitstream. Figure 4-19 shows an example for a single XC3S500E FPGA bitstream stored in an XCF04S Platform Flash PROM.
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Figure 4-18: Enter FPGA Configuration Bitstream File(s)
Chapter 4: FPGA Configuration Options
To generate the actual PROM file, click Operations Æ Generate File as shown in
Figure 4-20.
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Figure 4-19: PROM Formatting Completed
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Figure 4-20: Click Operations Æ Generate File to Create the Formatted PROM File
The iMPACT software indicates that the PROM file was successfully created, as shown in
Figure 4-21.
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Programming the FPGA, CPLD, or Platform Flash PROM via USB
Figure 4-21: PROM File Formatter Succeeded
Programming the Platform Flash PROM
To p ro gr am t he f or ma tt ed P ROM f il e in to t he Platform Flash PROM via the on-board USB­JTAG circuitry, follow the steps outlined in this subsection.
Place the iMPACT software in the JTAG Boundary Scan mode, either by choosing Boundary Scan in the iMPACT Modes pane, as shown in Figure 4-22, or by clicking on the Boundary Scan tab.
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Figure 4-22: Switch to Boundary Scan Mode
Chapter 4: FPGA Configuration Options
Assign the PROM file to the XCF04S Platform Flash PROM on the JTAG chain, as shown in
Figure 4-23. Right-click the PROM icon, then click Assign New Configuration File.
Select a previously generated PROM format file and click OK.
Figure 4-23: Assign the PROM File to the XCF04S Platform Flash PROM
To st ar t p ro gr am mi ng t he PR OM , ri gh t-c li ck t he P ROM i co n an d the n cl ic k Program..
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The programming software again prompts for the PROM type to be programmed. Select xcf04s and click OK, as shown in Figure 4-25.
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Figure 4-24: Program the XCF04S Platform Flash PROM
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Figure 4-25: Select XCF04S Platform Flash PROM
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Programming the FPGA, CPLD, or Platform Flash PROM via USB
Before programming, choose the programming options available in Figure 4-26. Checking the Erase Before Programming option erases the Platform Flash PROM completely before programming, ensuring that no previous data lingers. The Verify option checks that the PROM was correctly programmed and matches the downloaded configuration bitstream. Both these options are recommended even though they increase overall programming time.
The Load FPGA option immediately forces the FPGA to reconfigure after programming the Platform Flash PROM. The FPGA’s configuration mode pins must be set for Master Serial mode, as defined in Table 4-1, page 25. Click OK when finished.
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Figure 4-26: PROM Programming Options
The iMPACT software indicates if programming was successful or not. If programming was successful and the Load FPGA option was left unchecked, push the PROG_B push­button switch shown in Figure 4-2, page 24 to force the FPGA to reconfigure from the newly programmed Platform Flash PROM. If the FPGA successfully configures, the DONE LED, also shown in Figure 4-2, lights up.
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Chapter 4: FPGA Configuration Options
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Character LCD Screen
Overview
The Spartan-3E MicroBlaze Development Kit board has been designed with a 16 pin female header connector. The Spartan-3E MicroBlaze Development board is shipped with a 2x16 LCD display attached, but any standard LCD display can be attached to this connector.
The Spartan-3E MicroBlaze Development Kit board prominently features a 2-line by 16­character liquid crystal display (LCD). The FPGA controls the LCD via the 4-bit data interface or 8 bit data interface in shown Figure 5-1.
Chapter 5
Spartan-3E
FPGA
(L17) (L18)
(E3)
(M18)
(R15)
(R16)
(P17)
(M15)
(M16)
(P6)
(R8)
(T8) (P3)
(P4)
PSWT GND
LCD_RW
LCD_D / i
LCD_RET
LCD_E
SF_D8
SF_D9
SF_D10
SF_D11
SF_D12
SF_D13
SF_D14
SF_D15
LCD_CS1 LCD_CS2
SF_CEO
1
LCD
Header (J13)
1 2
3
4
5
6
7
8
9 10
11
12
13
14 15
16
Intel StrataFlash
D[15:8]
CE0
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Figure 5-1: Character LCD Interface
Chapter 5: Character LCD Screen
Once mastered, the LCD is a practical way to display a variety of information using standard ASCII and custom characters. However, these displays are not fast. Scrolling the display at half-second intervals tests the practical limit for clarity. Compared with the 50 MHz clock available on the board, the display is slow. A PicoBlaze processor efficiently controls display timing plus the actual content of the display.
Character LCD Interface Signals
Table 5-1 shows the interface character LCD interface signals.
Ta bl e 5 - 1: Character LCD Interface
Signal Name FPGA Pin Function
SF_D<15> T8 Data bit DB7
SF_D<14> R8 Data bit DB6
SF_D<13> P6 Data bit DB5
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SF_D<12> M16 Data bit DB4
SF_D<11> M15 Data bit DB3
SF_D<10> P17 Data bit DB2
SF_D<9> R16 Data bit DB1
SF_D<8> R15 Data bit DB0
LCD_E M18 Read/Write Enable Pulse
0: Disabled 1: Read/Write operation enabled
LCD_RS L18 Register Select
0: Instruction register during write operations. Busy Flash during read operations 1: Data for read or write operations
LCD_RW L17 Read/Write Control
0: WRITE, LCD accepts data 1: READ, LCD presents data
LCD_RET E3
LCD_CS1 P3
LCD_CS2 P4
Shared with StrataFlash pins SF_D<15:8>
Voltage Compat ibility
The character LCD is power by +5V. The FPGA I/O signals are powered by 3.3V. However, the FPGA’s output levels are recognized as valid Low or High logic levels by the LCD. The LCD controller accepts 5V TTL signal levels and the 3.3V LVCMOS outputs provided by the FPGA meet the 5V TTL voltage level requirements.
The 390: series resistors on the data lines prevent overstressing on the FPGA and StrataFlash I/O pins when the character LCD drives a High logic value. The character LCD drives the data lines when LCD_RW is High. Most applications treat the LCD as a write­only peripheral and never read from from the display.
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Interaction with Intel StrataFlash
As shown in Figure 5-1, the four LCD data signals are also shared with StrataFlash data lines SF_D<11:8>. As shown in Table 5-2, the LCD/StrataFlash interaction depends on the application usage in the design. When the StrataFlash memory is disabled (SF_CE0 = High), then the FPGA application has full read/write access to the LCD. Conversely, when LCD read operations are disabled (LCD_RW = Low), then the FPGA application has full read/write access to the StrataFlash memory
Ta bl e 5 - 2: LCD/StrataFlash Control Interaction
SF_CE0 SF_BYTE LCD_RW Operation
1XXStrataFlash disabled. Full read/write access to LCD.
X X 0 LCD write access only. Full access to StrataFlash.
X0XStrataFlash in byte-wide (x8) mode. Upper address lines
Notes:
1. ‘X’ indicates a don’t care, can be either 0 or 1.
Interaction with Intel StrataFlash
are not used. Full access to both LCD and StrataFlash.
If the StrataFlash memory is in byte-wide (x8) mode (SF_BYTE = Low), the FPGA application has full simultaneous read/write access to both the LCD and the StrataFlash memory. In byte-wide mode, the StrataFlash memory does not use the SF_D<15:8> data lines.
UCF Location Constraints
Figure 5-2 provides the UCF constraints for the Character LCD, including the I/O pin
assignment and the I/O standard used.
# ==== Character LCD (LCD) ==== NET "LCD_E" LOC = "M18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "LCD_DI" LOC = "L18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "LCD_RW" LOC = "L17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "LCD_RET" LOC = "E3" | IOSTANDARD = SSTL2_I ; NET "LCD_CS1" LOC = "P3" | IOSTANDARD = SSTL2_I ; NET "LCD_CS2" LOC = "P4" | IOSTANDARD = SSTL2_I ;
# LCD data connections are shared with StrataFlash connections SF_D<15:8> NET "SF_D<8>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_D<9>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_D<10>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_D<11>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_D<12>" LOC = "M16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_D<13>" LOC = "P6" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_D<14>" LOC = "R8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_D<15>" LOC = "T8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
UG257_05_02_061306
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Figure 5-2: UCF Location Constraints for the Character LCD
Chapter 5: Character LCD Screen
LCD Controller
The 2 x 16 character LCD has an internal Sitronix ST7066U graphics controller that is functionally equivalent with the following devices.
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x Samsung S6A0069X
x Hitachi HD44780
x SMOS SED1278
Memory Map
The controller has three internal memory regions, each with a specific purpose. The display must be initialized before accessing any of these memory regions.
DD RAM
The Display Data RAM (DD RAM) stores the character code to be displayed on the screen. Most applications interact primarily with DD RAM. The character code stored in a DD RAM location references a specific character bitmap stored either in the predefined CG
ROM character set or in the user-defined CG RAM character set.
Figure 5-3shows the default address for the 32 character locations on the display. The
upper line of characters is stored between addresses 0x00 and 0x0F. The second line of characters is stored between addresses 0x40 and 0x4F.
or KS0066U
Character Display Addresses
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
1
40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F
2
123 4 5 6 7 8 9 10 11 12 13 14 15 16 17 40
Undisplayed Addresses
10 27 50 67
UG257_05_03_061206
. . . . . .
. . .
Figure 5-3: DD RAM Hexadecimal Addresses (No Display Shifting)
Physically, there are 80 total character locations in DD RAM with 40 characters available per line. Locations 0x10 through 0x27 and 0x50 through 0x67 can be used to store other non-display data. Alternatively, these locations can also store characters that can only displayed using controller’s display shifting functions.
The Set DD RAM Address command initializes the address counter before reading or writing to DD RAM. Write DD RAM data using the Write Data to CG R AM or DD R AM command, and read DD RAM using the Read Data from CG RAM or DD RAM command.
The DD RAM address counter either remains constant after read or write operations, or auto-increments or auto-decrements by one location, as defined by the I/D set by the Entry
Mode Set command.
CG ROM
The Character Generator ROM (CG ROM) contains the font bitmap for each of the predefined characters that the LCD screen can display, shown in Figure 5-4. The character code stored in DD RAM for each c harac ter l ocati on sub sequently references a position with the CG ROM. For example, a hexadecimal character code of 0x53 stored in a DD RAM location displays the character ‘S’. The upper nibble of 0x53 equates to DB[7:4]=”0101”
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LCD Controller
binary and the lower nibble equates to DB[3:0] = “0011” binary. As shown in Figure 5-4, the character ‘S’ appears on the screen.
English/Roman characters are stored in CG ROM at their equivalent ASCII code address.
DB7 DB6 DB5 DB4
Lower Data Nibble
Upper Data Nibble
The character ROM contains the ASCII English character set and Japanese kana characters.
The controller also provides for eight custom character bitmaps, stored in CG RAM. These eight custom characters are displayed by storing character codes 0x00 through 0x07 in a
DD RAM location.
CG RAM
The Character Generator RAM (CG RAM) provides space to create eight custom character bitmaps. Each custom character location consists of a 5-dot by 8-line bitmap, as shown in
Figure 5-5.
The Set CG RAM Address command initializes the address counter before reading or writing to CG RAM. Write CG RAM data using the Write Da ta to CG R AM or DD R AM command, and read CG RAM using the Read Data from CG RAM or DD RAM command.
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DB3
DB2
DB1
DB0
Figure 5-4: LCD Character Set
UG257_05_04_061206
Chapter 5: Character LCD Screen
The CG RAM address counter can either remain constant after read or write operations, or auto-increments or auto-decrements by one location, as defined by the I/D set by the Entry
Mode Set command.
Figure 5-5 provides an example, creating a special checkerboard character. The custom
character is stored in the fourth CG RAM character location, which is displayed when a DD RAM location is 0x03. To write the custom character, the CG RAM address is first initialized using the Set CG RAM Address command. The upper three address bit s point to the custom character location. The lower three address bits point to the row address for the character bitmap. The Write Data to CG RAM or DD RAM command is used to write each character bitmap row. A ‘1’ lights a bit on the display. A ‘0’ leaves the bit unlit. Only the lower five data bits are used; the upper three data bits are don’t care positions. The eighth row of bitmap data is usually left as all zeros to accommodate the cursor.
A5 A2 A0A1 D7 D5D6 D4 D2D3 D0D1A4 A3
001011
000111
001111
011011
011111
Character
Addresses
Row
Addresses
Upper Nibble Lower Nibble
Write Data to CG RAM or DD RAM
Character BitmapDont Care
—— —
—— —
—— —
——
—— —
——
—— —
——
0
0
0
0
000
00000011
00
00
00
00010011
00
00010111
00
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Figure 5-5: Example Custom Checkerboard Character with Character Code 0x03
Command Set
Table 5-3 summarizes the available LCD controller commands and bit definitions. Because
the display is set up for 4-bit operation, each 8-bit command is sent as two 4-bit nibbles. The upper nibble is transferred first, followed by the lower nibble.
Ta bl e 5 - 3: LCD Character Display Command Set
Clear Display 0000000001
Return Cursor Home 000000001
Entry Mode Set 00000001I/DS
Display On/Off 0000001DCB
Cursor and Display Shift 000001S/CR/L
Function Set 00001010
Function
LCD_RS
LCD_RW
Upper Nibble Lower Nibble
DB7
DB6
DB5
DB4
DB3
DB2
DB1
- -
- -
DB0
-
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LCD Controller
Ta bl e 5 - 3: LCD Character Display Command Set (Continued)
Upper Nibble Lower Nibble
Function
LCD_RS
Set CG RAM Address 0001A5A4A3A2A1A0
Set DD RAM Address 001A6A5A4A3A2A1A0
LCD_RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Read Busy Flag and Address
Write Dat a to CG RAM or DD RAM
Read Data from CG RAM or DD RAM
0 1 BF A6 A5 A4 A3 A2 A1 A0
10D7D6D5D4D3D2D1D0
11D7D6D5D4D3D2D1D0
Disabled
If the LCD_E enable signal is Low, all other inputs to the LCD are ignored.
Clear Display
Clear the display and return the cursor to the home position, the top-left corner.
This command writes a blank space (ASCII/ANSI character code 0x20) into all DD RAM addresses. The address counter is reset to 0, location 0x00 in DD RAM. Clears all option settings. The I/D control bit is set to 1 (increment address counter mode) in the Entry Mode
Set command.
Execution Time: 82 Ps – 1.64 ms
Return Cursor Home
Return the cursor to the home position, the top-left corner. DD RAM contents are unaffected. Also returns the display being shifted to the original position, shown in
Figure 5-3.
The address counter is reset to 0, location 0x00 in DD RAM. The display is returned to its original status if it was shifted. The cursor or blink move to the top-left character location.
Execution Time: 40 Ps – 1.6 ms
Entry Mode Set
Sets the cursor move direction and specifies whether or not to shift the display.
These operations are performed during data reads and writes.
Execution Time: 40 Ps
Bit DB1: (I/D) Increment/Decrement
0Auto-decrement address counter. Cursor/blink moves to left.
1Auto-increment address counter. Cursor/blink moves to right.
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Chapter 5: Character LCD Screen
This bit either auto-increments or auto-decrements the DD RAM and CG RAM address counter by one location after each Wri te Dat a to CG RAM or DD RAM or Read Data from
CG RAM or DD RAM command. The cursor or blink position moves accordingly.
Bit DB0: (S) Shift
0Shifting disabled
1During a DD RAM write operation, shift the entire display value in the direction
controlled by Bit DB1 (I/D). Appears as though the cursor position remains constant and the display moves.
Display On/Off
Display is turned on or off, controlling all characters, cursor and cursor position character (underscore) blink.
Execution Time: 40 Ps
Bit DB2: (D) Display On/Off
0No characters displayed. However, data stored in DD RAM is retained
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1 Display characters stored in DD RAM
Bit DB1: (C) Cursor On/Off
The cursor uses the five dots on the bottom line of the character. The cursor appears as a line under the displayed character.
0No cursor
1 Display cursor
Bit DB0: (B) Cursor Blink On/Off
0No cursor blinking
1Cursor blinks on and off approximately every half second
Cursor and Display Shift
Moves the cursor and shifts the display without changing DD RAM contents. Shift cursor position or display to the right or left without writing or reading display data.
This function positions the cursor in order to modify an individual character, or to scroll the display window left or right to reveal additional data stored in the DD RAM, beyond the 16th character on a line. The cursor automatically moves to the second line when it shifts beyond the 40th character location of the first line. The first and second line displays shift at the same time.
When the displayed data is shifted repeatedly, both lines move horizontally. The second display line does not shift into the first display line.
Execution Time: 40 Ps
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LCD Controller
Ta bl e 5 - 4: Shift Patterns According to S/C and R/L Bits
DB3
DB2
(S/C)
(R/L)
00Shift the cursor position to the left. The address counter is decremented by one.
01Shift the cursor position to the right. The address counter is incremented by one.
Operation
10
11
Shift the entire display to the left. The cursor follows the display shift. The address counter is unchanged.
Shift the entire display to the right. The cursor follows the display shift. The address counter is unchanged.
Function Set
Sets interface data length, number of display lines, and character font.
The Starter Kit board supports a single function set with value 0x28.
Execution Time: 40 Ps
Set CG RAM Address
Set the initial CG RAM address.
After this command, all subsequent read or write operations to the display are to or from CG RAM.
Execution Time: 40 Ps
Set DD RAM Address
Set the initial DD RAM address.
After this command, all subsequentsubsequent read or write operations to the display are to or from DD RAM. The addresses for displayed characters appear in Figure 5-3.
Execution Time: 40 Ps
Read Busy Flag and Address
Read the Busy flag (BF) to determine if an internal operation is in progress, and read the current address counter contents.
BF = 1 indicates that an internal operation is in progress. The next instruction is not accepted until BF is cleared or until the current instruction is allowed the maximum time to execute.
This command also returns the present value of address counter. The address counter is used for both CG RAM and DD RAM addresses. The specific context depends on the most recent Set CG RAM Address or Set DD RAM Address command issued.
Execution Time: 1 Ps
Write Data to CG RAM or DD RAM
Write data into DD RA M if the c ommand foll ows a previou s Set DD RAM Address command, or write data into CG RAM if the command follows a previous Set CG RAM
Address command.
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Chapter 5: Character LCD Screen
After the write operation, the address is automatically incremented or decremented by 1 according to the Entry Mode Set command. The entry mode also determines display shift.
Execution Time: 40 Ps
Read Data from CG RAM or DD RAM
Read data from DD RAM if the command follows a previous Set DD RAM Address command, or read data from CG RAM if the command follows a previous Set CG RAM
Address command.
After the read operation, the address is automatically incremented or decremented by 1 according to the Entry Mode Set command. However, a display shift is not executed during read operations.
Execution Time: 40 Ps
Operation
Four-Bit Data Interface
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The board uses a 4-bit data interface to the character LCD.
Figure 5-6 illustrates a write operation to the LCD, showing the minimum times allowed
for setup, hold, and enable pulse length relative to the 50 MHz clock (20 ns period) provided on the board.
CLOCK
LCD_RS
LCD_RS
SF_D[11:8]
LCD_RW
LCD_E
Upper 4 bits
40 ns 10 ns
Lower 4 bits
0 = Command, 1 = Data
Valid Data
230 ns
SF_D[11:8]
LCD_RW
LCD_E
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1 µs 40 µs
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Figure 5-6: Character LCD Interface Timing
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The data values on SF_D<11:8>, and the register select (LCD_RS) and the read/write (LCD_RW) control signals must be set up and stable at least 40 ns before the enable LCD_E goes High. The enable signal must remain High for 230 ns or longer—the equivalent of 12 or more clock cycles at 50 MHz.
In many applications, the LCD_RW signal can be tied Low permanently because the FPGA generally has no reason to read information from the display.
Tr an s fe rr i n g 8-Bit Data over the 4-Bit Interface
After initializing the display and establishing communication, all commands and data transfers to the character display are via 8 bits, transferred using two sequential 4-bit operations. Each 8-bit transfer must be decomposed into two 4-bit transfers, spaced apart by at least 1 Ps, as shown in Figure 5-6. The upper nibble is transferred first, followed by the lower nibble. An 8-bit write operation must be spaced least 40 Ps before the next communication. This delay must be increased to 1.64 ms following a Clear Display command.
Initializing the Display
After power-on, the display must be initialized to establish the required communication protocol. The initialization sequence is simple and ideally suited to the highly-efficient 8­bit PicoBlaze for more complex control or computation beyond simply driving the display.
embedded controller. After initialization, the PicoBlaze controller is available
Operation
Power-On Initialization
The initialization sequence first establishes that the FPGA application wishes to use the four-bit data interface to the LCD as follows:
x Wait 15 ms or longer, although the display is generally ready when the FPGA finishes
configuration. The 15 ms interval is 750,000 clock cycles at 50 MHz.
x Write SF_D<11:8> = 0x3, pulse LCD_E High for 12 clock cycles.
x Wait 4.1 ms or longer, which is 205,000 clock cycles at 50 MHz.
x Write SF_D<11:8> = 0x3, pulse LCD_E High for 12 clock cycles.
x Wait 100 Ps or longer, which is 5,000 clock cycles at 50 MHz.
x Write SF_D<11:8> = 0x3, pulse LCD_E High for 12 clock cycles.
x Wait 40 Ps or longer, which is 2,000 clock cycles at 50 MHz.
x Write SF_D<11:8> = 0x2, pulse LCD_E High for 12 clock cycles.
x Wait 40 Ps or longer, which is 2,000 clock cycles at 50 MHz.
Display Configuration
After the power-on initialization is completed, the four-bit interface is now established. The next part of the sequence configures the display:
x Issue a Function Set command, 0x28, to configure the display for operation on the
Spartan-3E Starter Kit board.
x Issue an Entry Mode Set command, 0x06, to set the display to automatically
increment the address pointer.
x Issue a Display On/Off command, 0x0C, to turn the display on and disables the
cursor and blinking.
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Chapter 5: Character LCD Screen
x Finally, issue a Clear Display command. Allow at least 1.64 ms (82,000 clock cycles)
after issuing this command.
Writing Data to the Display
To w ri te d at a to t he d is pl ay, sp ec if y th e st ar t address, followed by one or more data values.
Before writing any data, issue a Set DD RAM Address command to specify the initial 7-bit address in the DD RAM. See Figure 5-3 for DD RAM locations.
Write data to the displa y u sin g a Write Dat a to C G RAM or D D RAM command. The 8-bit data value represents the look-up address into the CG ROM or CG RAM, shown in
Figure 5-4. The stored bitmap in the CG ROM or CG RAM drives the 5 x 8 dot matrix to
represent the associated character.
If the address counter is configured to auto-increment, as described earlier, the application can sequentially write multiple character codes and each character is automatically stored and displayed in the next available location.
Continuing to write characters, however, eventually falls off the end of the first display line. The additional characters do not automatically appear on the second line because the DD RAM map is not consecutive from the first line to the second.
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Disabling the Unused LCD
If the FPGA application does not use the character LCD screen, drive the LCD_E pin Low to disable it. Also drive the LCD_RW pin Low to prevent the LCD screen from presenting data.
Related Resources
x Initial Design for Spartan-3E MicroBlaze Development Kit (Reference Design)
http://www.xilinx.com/
x PowerTip PC1602-D Character LCD (Basic Electrical and Mechanical Data)
http://www.powertipusa.com/pdf/pc1602d.pdf
x Sitronix ST7066U Character LCD Controller
http://www.sitronix.com.tw/sitronix/product.nsf/Doc/ST7066U?OpenDocument
x Detailed Data Sheet on PowerTip Character LCD
http://www.rapidelectronics.co.uk/images/siteimg/57-0910e.PDF
x Samsung S6A0069X Character LCD Controller
http://www.samsung.com/Products/Semiconductor/DisplayDriverIC/MobileDDI/BWSTN /S6A0069X/S6A0069X.htm
s3e1600e
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VGA Display Port
The MicroBlaze Development Kit board includes a VGA display port via a J15 connector. Connect this port directly to most PC monitors or flat-panel LCDs using a standard monitor cable. As shown in Figure 6-1, the VGA connector is the left-most connector along the top of the board.
Chapter 6
Pin 5
in 10
15
DB15 VGA Connector
(front view)
DB15 Connector
1
6
11
2
7
12
3
8
13
4
9
14
5
10
15
Pin 1
Pin 6
Pin 11
Red
Green
Blue
Horizontal Sync
Vertical Sync
270W
270W
270W
82.5W
82.5W
DB15 VGA Connector
VGA_RED
(H14)
VGA_GREEN
(H15)
VGA_BLUE
(G15)
VGA_HSYNC
(F15)
VGA_VSYNC
(F14)
The Spartan-3E FPGA directly drives the five VGA signals via resistors. Each color line has a series resistor, with one bit each for VGA_RED, VGA_GREEN, and VGA_BLUE. The series resistor, in combination with the 75: termination built into the VGA cable, ensures that the color signals remain in the VGA-specified 0V to 0.7V range. The VGA_HSYNC and VGA_VSYNC signals using LVTTL or LVCMOS33 I/O standard drive levels. Drive
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GND
UG257_06_01_060506
Figure 6-1: VGA Connections from Spartan-3E Starter Kit Board
Chapter 6: VGA Display Port
the VGA_RED, VGA_GREEN, and VGA_BLUE signals High or Low to generate the eight colors shown in Table 6-1.
Ta bl e 6 - 1: 3-Bit Display Color Codes
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VGA_RED VGA_GREEN VGA_BLUE Resulting Color
00 0
00 1
01 0
01 1 Cyan
10 0
10 1
11 0
11 1 White
VGA signal timing is specified, published, copyrighted, and sold by the Video Electronics Standards Association (VESA). The following VGA system and timing information is provided as an example of how the FPGA might drive VGA monitor in 640 by 480 mode. For more precise information or for information on higher VGA frequencies, refer to documents available on the VESA website or other electronics websites (see “Related
Resources,” page 57).
Signal Timing for a 60 Hz, 640x480 VGA Display
CRT-based VGA displays use amplitude-modulated, moving electron beams (or cathode rays) to display information on a phosphor-coated screen. LCDs use an array of switches that can impose a voltage across a small amount of liquid crystal, thereby changing light permittivity through the crystal on a pixel-by-pixel basis. Although the following description is limited to CRT displays, LCDs have evolved to use the same signal timings as CRT displays. Consequently, the following discussion pertains to both CRTs and LCDs.
Black
Blue
Green
Red
Magenta
Yellow
Within a CRT display, current waveforms pass through the coils to produce magnetic fields that deflect electron beams to transverse the display surface in a raster pattern, horizontally from left to right and vertically from top to bottom. As shown in Figure 6-2, information is only displayed when the beam is moving in the forward direction—left to right and top to bottom—and not during the time the beam returns back to the left or top edge of the display. Much of the potential display time is therefore lost in blanking periods when the beam is reset and stabilized to begin a new horizontal or vertical display pass.
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"
6
Signal Timing for a 60 Hz, 640x480 VGA Display
Current
through the
horizontal deflection
coil
time
"front porch"
pixel 0,0
640 pixels are displayed each time the beam traverses the screen
VGA Display
pixel 479,0
Stable current ramp: Information is displayed during this time
Total horizontal time
Horizontal display time
pixel 479,639
pixel 0,639
Retrace: No information is displayed during this time
retrace time
"front porch
HS
Horizontal sync signal sets the retrace frequency
"back porch"
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Figure 6-2: CRT Display Timing Example
The display resolution defines the size of the beams, the frequency at which the beam traces across the display, and the frequency at which the electron beam is modulated.
Modern VGA displays support multiple display resolutions, and the VGA controller dictates the resolution by producing timing signals to control the raster patterns. The controller produces TTL-level synchronizing pulses that set the frequency at which current flows through the deflection coils, and it ensures that pixel or video data is applied to the electron guns at the correct time.
Video data typically comes from a video refresh memory with one or more bytes assigned to each pixel location. The MicroBlaze Development Kit board uses three bits per pixel, producing one of the eight possible colors shown in Table 6-1. The controller indexes into the video data buffer as the beams move across the display. The controller then retrieves and applies video data to the display at precisely the time the electron beam is moving across a given pixel.
As shown in Figure 6-2, the VGA controller generates the horizontal sync (HS) and vertical sync (VS) timings signals and coordinates the delivery of video data on each pixel clock. The pixel clock defines the time available to display one pixel of information. The VS signal defines the refresh frequency of the display, or the frequency at which all information on the
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display is redrawn. The minimum refresh frequency is a function of the display’s phosphor and electron beam intensity, with practical refresh frequencies in the 60 Hz to 120 Hz range. The number of horizontal lines displayed at a given refresh frequency defines the horizontal retrace frequency.
VGA Signal Timing
The signal timings in Table 6-2 are derived for a 640-pixel by 480-row display using a 25 MHz pixel clock and 60 Hz ± 1 refresh. Figure 6-3 shows the relation between each of the timing symbols. The timing for the sync pulse width (T intervals (T and back porch intervals are the pre- and post-sync pulse times. Information cannot be displayed during these times.
Ta bl e 6 - 2: 640x480 Mode VGA Timing
) and front and back porch
and TBP) are based on observations from various VGA displays. The front
FP
PW
R
Symbol Parameter
Vertical Sync Horizontal Sync
Time Clocks Lines Time Clocks
T
Sync pulse time 16.7 ms 416,800 521 32 µs 800
S
T
Display time 15.36 ms 384,000 480 25.6 µs 640
DISP
T
Pulse width 64 µs 1,600 2 3.84 µs 96
PW
T
Front porch 320 µs 8,000 10 640 ns 16
FP
T
Back porch 928 µs 23,200 29 1.92 µs 48
BP
T
S
T
T
disp
T
pw
Figure 6-3: VGA Control Timing
fp
T
bp
UG257_06_03_060506
Generally, a counter clocked by the pixel clock controls the horizontal timing. Decoded counter values generate the HS signal. This counter tracks the current pixel display location on a given row.
A separate counter tracks the vertical timing. The vertical-sync counter increments with each HS pulse and decoded values generate the VS signal. This counter tracks the current display row. These two continuously running counters form the address into a video display buffer. For example, the on-board DDR SDRAM provides an ideal display buffer.
No time relationship is specified between the onset of the HS pulse and the onset of the VS pulse. Consequently, the counters can be arranged to easily form video RAM addresses, or to minimize decoding logic for sync pulse generation.
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UCF Location Constraints
Figure 6-4 provides the UCF constraints for the VGA display port, including the I/O pin
assignment, the I/O standard used, the output slew rate, and the output drive current.
NET "VGA_RED" LOC = "H14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; NET "VGA_GREEN" LOC = "H15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; NET "VGA_BLUE" LOC = "G15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; NET "VGA_HSYNC" LOC = "F15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; NET "VGA_VSYNC" LOC = "F14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
Figure 6-4: UCF Constraints for VGA Display Port
Related Resources
x VESA
http://www.vesa.org
x VGA timing information
http://www.epanorama.net/documents/pc/vga_timing.html
UCF Location Constraints
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RS-232 Serial Ports
Overview
As shown in Figure 7-1, the MicroBlaze Development Kit board has two RS-232 serial ports: a female DB9 DCE connector and a male DTE connector. The DCE-style port connects directly to the serial port connector available on most personal computers and workstations via a standard straight-through serial cable. Null modem, gender changers, or crossover cables are not required.
Use the DTE-style connector to control other RS-232 peripherals, such as modems or printers, or perform simple loopback testing with the DCE connector.
Figure 7-1 shows the connection between the FPGA and the two DB9 connectors. The
FPGA supplies serial output data using LVTTL or LVCMOS levels to the Maxim device, which in turn, converts the logic value to the appropriate RS-232 voltage level. Likewise, the Maxim device converts the RS-232 serial input data to LVTTL levels for the FPGA. A series resistor between the Maxim output pin and the FPGA’s RXD pin protects against accidental logic conflicts.
Chapter 7
Hardware flow control is not supported on the connector. The port’s DCD, DTR, and DSR signals connect together, as shown in Figure 7-1. Similarly, the port’s RTS and CTS signals connect together.
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Pin 5
Pin 9
DB9 Serial Port Connector
(front view)
Std 9-Pin Serial cable
Pin 1
Pin 6
Std 9-Pin Serial cable
To DTE
RS-232 Peripheral
TALK/DATA
TALK
Null Modem Serial cable
RS CS TR RD TD CD
OR
To DCE
DTE
DTE
Male DB9
DCE
Female DB9
DCE
12345
6789
J9 J10
To DTE
12345
6789
GND
GND
RS-232 Voltage Translator (IC2)
RS232_DCE_RXD
RS232_DCE_TXD
Spartan-3E FPGA
Figure 7-1: RS-232 Serial Ports
RS232_DTE_TXD
RS232_DTE_RXD
(M13)(U8)(M14)(R7)
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UCF Location Constraints
Figure 7-2 and Figure 7-3 provide the UCF constraints for the DTE and DCE RS-232 ports,
respectively, including the I/O pin assignment and the I/O standard used.
NET "RS232_DTE_RXD" LOC = "U8" | IOSTANDARD = LVTTL ; NET "RS232_DTE_TXD" LOC = "M13" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
Figure 7-2: UCF Location Constraints for DTE RS-232 Serial Port
NET "RS232_DCE_RXD" LOC = "R7" | IOSTANDARD = LVTTL ; NET "RS232_DCE_TXD" LOC = "M14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
Figure 7-3: UCF Location Constraints for DCE RS-232 Serial Port
UCF Location Constraints
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PS/2 Mouse/Keyboard Port
The MicroBlaze Development Kit board includes a PS/2 mouse/keyboard port and the standard 6-pin mini-DIN connector, labeled J14 on the board. Figure 8-1 shows the PS/2 connector, and Table 8-1 shows the signals on the connector. Only pins 1 and 5 of the connector attach to the FPGA.
Chapter 8
270W
PS2_DATA: (G13)
3
270
PS2_CLK: (G14)
PCB Top Surface
J14
Front View
2
4
6
1
5
Figure 8-1: PS/2 Connector Location and Signals
Ta bl e 8 - 1: PS/2 Connector Pinout
PS/2 DIN Pin Signal FPGA Pin
1 DATA (PS2_DATA) G13
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2 Reserved G13
3 GND GND
4 +5V
5 CLK (PS2_CLK) G14
6 Reserved G14
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Chapter 8: PS/2 Mouse/Keyboard Port
Both a PC mouse and keyboard use the two-wire PS/2 serial bus to communicate with a host device, the Spartan-3E FPGA in this case. The PS/2 bus includes both clock and data. Both a mouse and keyboard drive the bus with identical signal timings and both use 11-bit words that include a start, stop and odd parity bit. However, the data packets are organized differently for a mouse and keyboard. Furthermore, the keyboard interface allows bidirectional data transfers so the host device can illuminate state LEDs on the keyboard.
The PS/2 bus timing appears in Table 8-2 and Figure 8-2. The clock and data signals are only driven when data transfers occur; otherwise they are held in the idle state at logic High. The timing defines signal requirements for mouse-to-host communications and bidirectional keyboard communications. As shown in Figure 8-2, the attached keyboard or mouse writes a bit on the data line when the clock signal is High, and the host reads the data line when the clock signal is Low.
Ta bl e 8 - 2: PS/2 Bus Timing
Symbol Parameter Min Max
R
Keyboard
T
T
CK
T
SU
HLD
Clock High or Low Time 30 Ps 50 Ps
Data-to-clock Setup Time 5 Ps 25 Ps
Clock-to-data Hold Time 5 Ps 25 Ps
T
CK
Edge 10
UG257_08_02_060506
CLK (PS2C)
DATA (PS2D)
0 start bit
Edge 0
T
SU
T
CK
T
HLD
1 stop bit
Figure 8-2: PS/2 Bus Timing Waveforms
The keyboard uses open-collector drivers so that either the keyboard or the host can drive the two-wire bus. If the host never sends data to the keyboard, then the host can use simple input pins.
A PS/2-style keyboard uses scan codes to communicate key press data. Nearly all keyboards in use today are PS/2 style. Each key has a single, unique scan code that is sent whenever the corresponding key is pressed. The scan codes for most keys appear in
Figure 8-3.
If the key is pressed and held, the keyboard repeatedly sends the scan code every 100 ms or so. When a key is released, the keyboard sends an “F0” key-up code, followed by the scan code of the released key. The keyboard sends the same scan code, regardless if a key has different shift and non-shift characters and regardless whether the Shift key is pressed or not. The host determines which character is intended.
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Keyboard
Some keys, called extended keys, send an “E0” ahead of the scan code and furthermore, they might send more than one scan code. When an extended key is released, an “E0 F0” key-up code is sent, followed by the scan code.
ESC
76
` ~
0E
TA B
0D
Caps L o c k
58
Shift
Ctrl
14
F105F206F304F4
1 !162 @1E3 #264 $255 %
Q15W1DE24R2DT
A1CS1BD23F2BG
Z1ZX22C21V2AB
12
Alt
11
0C
2E
F503F60BF783F8
6 ^367 &3D8 *3E9 (460 )45- _4E= +
Y35U3CI
2C
H33J3BK42L4B; :4C' "
34
N31M3A, <41> .49/ ?
32
Space
29
0A
43O44P4D
F901F1009F1178F12
55
[ {54] }
5B
52
4A
Alt
E0 11
07
Back Space
66
\ |
5D
Enter
5A
Shift
59
Ctrl
E0 14
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E0 75
E0 74
E0 6B
E0 72
Figure 8-3: PS/2 Keyboard Scan Codes
The host can also send commands and data to the keyboard. Table 8-3 provides a short list of some often-used commands.
Ta bl e 8 - 3: Common PS/2 Keyboard Commands
Command Description
ED Tu r n o n / o f f N u m L o c k , C a p s L o c k , a n d S c r o l l L o c k L E D s . The keyboard
acknowledges receipt of an “ED” command by replying with an “FA”, after which the host sends another byte to set LED status. The bit positions for the keyboard LEDs are shown below. Write a ‘1’ to the specific bit to illuminate the associated keyboard LED.
76543210
Ignored
Caps Lock
Num Lock
Scroll
Lock
EE Echo. Upon receiving an echo command, the keyboard replies with the same scan
code “EE”.
F3 Set scan code repeat rate. The keyboard acknowledges receipt of an “F3” by
returning an “FA”, after which the host sends a second byte to set the repeat rate.
FE Resend. Upon receiving a resend command, the keyboard resends the last scan
code sent.
FF Reset. Resets the keyboard.
The keyboard sends commands or data to the host only when both the data and clock lines are High, the Idle state.
Because the host is the bus master, the keyboard checks whether the host is sending data before driving the bus. The clock line can be used as a clear to send signal. If the host pulls the clock line Low, the keyboard must not send any data until the clock is released.
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The keyboard sends data to the host in 11-bit words that contain a ‘0’ start bit, followed by eight bits of scan code (LSB first), followed by an odd parity bit and terminated with a ‘1’ stop bit. When the keyboard sends data, it generates 11 clock transitions at around 20 to 30 kHz, and data is valid on the falling edge of the clock as shown in Figure 8-2.
Mouse
A mouse generates a clock and data signal when moved; otherwise, these signals remain High, indicating the Idle state. Each time the mouse is moved, the mouse sends three 11-bit words to the host. Each of the 11-bit words contains a ‘0’ start bit, followed by 8 data bits (LSB first), followed by an odd parity bit, and terminated with a ‘1’ stop bit. Each data transmission contains 33 total bits, where bits 0, 11, and 22 are ‘0’ start bits, and bits 10, 21, and 32 are ‘1’ stop bits. The three 8-bit data fields contain movement data as shown in
Figure 8-4. Data is valid at the falling edge of the clock, and the clock period is 20 to 30 kHz.
Mouse stat us byte X direction byte Y direction byte
R
LR 0 1XS YS XV YV P X0 X1 X2 X3 X4 X5 X6 X7 P Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 P
0 11
Start bit
Idle state
Stop bit
10 10
Start bit
Stop bit
Start bit
Stop bit
Idle state
U257_08_04_060506
Figure 8-4: PS/2 Mouse Transaction
A PS/2-style mouse employs a relative coordinate system (see Figure 8-5), wherein moving the mouse to the right generates a positive value in the X field, and moving to the left generates a negative value. Likewise, moving the mouse up generates a positive value in the Y field, and moving it down represents a negative value. The XS and YS bits in the status byte define the sign of each value, where a ‘1’ indicates a negative value.
+Y values
(XS=1) (XS=0)
(YS=0)
+X values-X values
Figure 8-5: The Mouse Uses a Relative Coordinate System to Track Movement
The magnitude of the X and Y values represent the rate of mouse movement. The larger the value, the faster the mouse is moving. The XV and YV bits in the status byte indicate when
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Mouse Arrow
(YS=1)
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the X or Y values exceed their maximum value, an overflow condition. A ‘1’ indicates when an overflow occurs. If the mouse moves continuously, the 33-bit transmiss ions repeat every 50 ms or so.
The L and R fields in the status byte indicate Left and Right button presses. A ‘1’ indicates that the associated mouse button is being pressed.
Voltage Supply
The PS/2 port on the MicroBlaze Development Kit board is powered by 5V. Although the Spartan-3E FPGA is not a 5V-tolerant device, it can communicate with a 5V device using series current-limiting resistors, as shown in Figure 8-1.
UCF Location Constraints
Figure 8-6 provides the UCF constraints for the PS/2 port connecting, including the I/O
pin assignment and the I/O standard used.
NET "PS2_CLK" LOC = "G14" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; NET "PS2_DATA" LOC = "G13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
Volt ag e S up ply
U257_08_06_060506
Related Resources
x PS/2 Mouse/Keyboard Protocol
http://www.computer-engineering.org/ps2protocol/
x PS/2 Keyboard Interface
http://www.computer-engineering.org/ps2keyboard/
x PS/2 Mouse Interface
http://www.computer-engineering.org/ps2mouse/
Figure 8-6: UCF Location Constraints for PS/2 Port
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Chapter 9
Digital to Analog Converter (DAC)
The MicroBlaze Development Kit board includes an SPI-compatible, four-channel, serial Digital-to-Analog Converter (DAC). The DAC device is a Linear Technology LTC2624 quad DAC with 12-bit unsigned resolution. The four outputs from the DAC appear on the J5 header, which uses the Digilent 6-pin Peripheral Module header are located immediately above the Ethernet RJ-45 connector, as shown in
Figure 9-1.
Linear Tech LTC2624 Quad DAC SPI_MOSI: (T4) SPI_MISO: (N10) SPI_SCK: (U16)
6-pin DAC Header (J5)
DAC_CS: (N8) DAC_CLR: (P8)
format. The DAC and the
Spartan-3E Development Board
SPI Communication
As shown in Figure 9-2, the FPGA uses a Serial Peripheral Interface (SPI) to communicate digital values to each of the four DAC channels. The SPI bus is a full-duplex, synchronous, character-oriented channel employing a simple four-wire interface. A bus master—the FPGA in this example—drives the bus clock signal (SPI_SCK) and transmits serial data (SPI_MOSI) to the selected bus slave—the DAC in this example. At the same time, the bus slave provides serial data (SPI_MISO) back to the bus master.
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Figure 9-1: Digital-to-Analog Converter and Associated Header
Chapter 9: Digital to Analog Converter (DAC)
3.3V
2.5V
Spartan-3E FPGA
(N8)
(U16)
(P8)
SPI_MOSI
DAC_CS
SPI_SCK
DAC_CLR
(N10) (T4)
REF A
REF B
REF C
REF D
SDI CS/LD SCK
CLR
LTC 2624 DAC
DAC A
12
DAC B
12
DAC C
12
DAC D
12
SPI Control Interface
VOUTA
VOUTB
VOUTC
VOUTD
SDO
Header J5
A
B
C
D
GND
VCC (3.3V)
R
Interface Signals
Table 9-1 lists the interface signals between the FPGA and the DAC. The SPI_MOSI,
SPI_MISO, and SPI_SCK signals are shared with other devices on the SPI bus. The DAC_CS signal is the active-Low slave select input to the DAC. The DAC_CLR signal is the active-Low, asynchronous reset input to the DAC.
Ta bl e 9 - 1: DAC Interface Signals
Signal FPGA Pin Direction Description
SPI_MOSI T4 FPGAÆDAC Serial data: Master Output, Slave Input
DAC_CS N8 FPGAÆDAC Active-Low chip-select. Digital-to-analog
SPI_SCK U16 FPGAÆDAC Clock
DAC_CLR P8 FPGAÆDAC Asynchronous, active-Low reset input
SPI_MISO N10 FPGAÅDAC Serial data: Master Input, Slave Output
The serial data output from the DAC is primarily used to cascade multiple DACs. This signal can be ignored in most applications although it does demonstrate full-duplex communication over the SPI bus.
SPI_MISO
Figure 9-2: Digital-to-Analog Connection Schematics
conversion starts when signal returns High.
UG257_09_02_060606
Disable Other Devices on the SPI Bus to Avoid Contention
The SPI bus signals are shared by other devices on the board. It is vital that other devices are disabled when the FPGA communicates with the DAC to avoid bus contention.
Table 9-2 provides the signals and logic values required to disable the other devices.
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Although the StrataFlash PROM is a parallel device, its least-significant data bit is shared with the SPI_MISO signal.
Ta bl e 9 - 2: Disabled Devices on the SPI Bus
Signal Disabled Device Disable Value
SPI_SS_B SPI serial Flash 1
AMP_CS Programmable pre-amplifier 1
AD_CONV Analog-to-Digital Converter (ADC) 0
SF_CE0 StrataFlash Parallel Flash PROM 1
FPGA_INIT_B Platform Flash PROM 1
SPI Communication Details
Figure 9-3 shows a detailed example of the SPI bus timing. Each bit is transmitted or
received relative to the SPI_SCK clock signal. The bus is fully static and supports clocks rate up to the maximum of 50 MHz. However, check all timing parameters using the LTC2624 data sheet if operating at or close to the maximum speed.
SPI Communication
DAC_CS
SPI_MOSI
SPI_SCK
SPI_MISO Previous 31
After driving the DAC_CS slave select signal Low, the FPGA transmits data on the SPI_MOSI signal, MSB first. The LTC2624 captures input data (SPI_MOSI) on the rising edge of SPI_SCK; the data must be valid for at least 4 ns relative to the rising clock edge.
The LTC2624 DAC transmits its data on the SPI_MISO signal on the falling edge of SPI_SCK. The FPGA captures this data on the next rising SPI_SCK edge. The FPGA must read the first SPI_MISO value on the first rising SPI_SCK edge after DAC_CS goes Low. Otherwise, bit 31 is missed.
After transmitting all 32 data bits, the FPGA completes the SPI bus transaction by returning the DAC_CS slave select signal High. The High-going edge starts the actual digital-to-analog conversion process within the DAC.
Communication Protocol
31 30 29
Previous 30 Previous 29
UG257_09_03_060606
Figure 9-3: SPI Communication Waveforms
Figure 9-4 shows the communications protocol required to interface with the LTC2624
DAC. The DAC supports both a 24-bit and 32-bit protocol. The 32-bit protocol is shown.
Inside the D/A converter, the SPI interface is formed by a 32-bit shift register. Each 32-bit command word consists of a command, an address, followed by data value. As a new command enters the DAC, the previous 32-bit command word is echoed back to the
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Chapter 9: Digital to Analog Converter (DAC)
master. The response from the DAC can be ignored although it is a useful to confirm correct communication.
SPI_MISO
R
SPI_MOSI
DAC_CS
SPI_SCK
Master Spartan-3E FPGA
0
Dont Care
Figure 9-4: SPI Communications Protocol to LTC2624 DAC
The FPGA first sends eight dummy or “don’t care” bits, followed by a 4-bit command. The most commonly used command with the board is COMMAND[3:0] = “0011”, which immediately updates the selected DAC output with the specified data value. Following the command, the FPGA selects one or all the DAC output channels via a 4-bit address field. Following the address field, the FPGA sends a 12-bit unsigned data value that the DAC converts to an analog value on the selected output(s). Finally, four additional dummy or don’t care bits pad the 32-bit command word.
Specifying the DAC Output Voltage
Slave: LTC2624 DAC
12-bit Unsigned
DATA
a2a1a
0
0000
0001
0010
0011
1111
9 10 11876543210
msblsb
a
ADDRESS
3
DAC A DAC B DAC C DAC D
All
31
a
a
a1a
2
0
c
c1c
3
0
COMMAND
c
2
3
Dont Care
UG257_09_04_060606
xxxxxxxxxxxx
As shown in Figure 9-2, each DAC output level is the analog equivalent of a 12-bit unsigned digital value, D[11:0], written by the FPGA to the DAC via the SPI interface.
The voltage on a specific output is generally described in Equation 9-1. The reference voltage, V
REFERENCE
3.3V reference voltage and Channels C and D use a 2.5V reference. The reference voltages themselves have a r5% tolerance, so there will be slight corresponding variances in the output voltage.
DAC Outputs A and B
Equation 9-2 provides the output voltage equation for DAC outputs A and B. The
reference voltage associated with DAC outputs A and B is 3.3V r 5%.
, is different between the four DAC outputs. Channels A and B use a
D 11:0>@
V
OUT
V
OUTA
-------------------- -
4096
D 11:0>@
-------------------- -
u=
4096
V
REFERENCE
3.3V 5%ru=
Equation 9-1
Equation 9-2
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DAC Outputs C and D
Equation 9-3 provides the output voltage equation for DAC outputs A and B. The
reference voltage associated with DAC outputs A and B is 2.5V r 5%.
UCF Location Constraints
Figure 9-5 provides the UCF constraints for the DAC interface, including the I/O pin
assignment and the I/O standard used.
NET "SPI_MISO" LOC = "N10" | IOSTANDARD = LVCMOS33 ; NET "SPI_MOSI" LOC = "T4" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; NET "SPI_SCK" LOC = "U16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; NET "DAC_CS" LOC = "N8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; NET "DAC_CLR" LOC = "P8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
Figure 9-5: UCF Location Constraints for the DAC Interface
V
OUTC
D 11:0>@
----------------- --- -
4096
UCF Location Constraints
2.5V 5%ru=
Equation 9-3
UG257_09_05_060606
Related Resources
x LTC2624 Quad DAC Data S heet
x http://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1155,C1005,C1156,
P2048,D2170
x PicoBlaze Based D/A Converter Control for the Spartan-3E Starter Kit (Reference
Design)
x http://www.xilinx.com/
x Xilinx PicoBlaze Soft Processor
x http://www.xilinx.com/picoblaze
x Digilent, Inc. Peripheral Modules
http://www.digilentinc.com/Products/Catalog.cfm?Nav1=Products Nav2=Peripheral&Cat=Peripheral
sp3e1600e
&
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Analog Capture Circuit
The MicroBlaze Development Kit board includes a two-channel analog capture circuit, consisting of aprogrammable scaling pre-amplifier and an analog-to-digital converter (ADC), as shown in Figure 10-1. Analog inputs are supplied on the J7 header.
6-pin DAC Header (J5)
Chapter 10
Linear Tech LTC6912 Dual A/D
SPI_MOSI: (T4) SPI_MISO: (N10) SPI_SCK: (U16) DAC_CS: (N8) DAC_CLR: (P8)
Linear Tech LTC1407A-1 Dual A/D
SPI_SCK: (U16) AD_CONV: (P11) SPI_MISO: (N10)
Spartan-3E Development Board
The analog capture circuit consists of a Linear Technology LTC6912-1 programmable pre­amplifier that scales the incoming analog signal on header J7 (see Figure 10-2). The output of pre-amplifier connects to a Linear Technology LTC1407A-1 ADC. Both the pre-amplifier and the ADC are serially programmed or controlled by the FPGA.
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Figure 10-1: Two-Channel A nalog Capture Circuit
Chapter 10: Analog Capture Circuit
Header J7
REFAB
(3.3V)
REFCD
(2.5V)
VINA
VINB
GND
VCC
(3.3V)
Spartan-3E FPGA
(N10) (T4)
(N7)
(E18)
(U16)
(P7)
REF = 1.65V
SPI_MOSI
AMP_CS
SPI_SCK
AMP_SHDN
LTC 6912-1 AMP
A
+
DIN
A GAIN B GAIN
CS/LD
SCK
SPI Control Interface
SHDN
LTC 1407A-1 ADC
+
A/D
Channel 0
B
+
DOUT
32103210130 ... 130 ...
+
A/D
Channel 1
CHANNEL 1 CHANNEL 0
SCK
CONV
R
14
14
SDO
SPI Control Interface
AD_CONV
(P11)
AMP_DOUT
SPI_MISO
Figure 10-2: Detailed View of Analog Capture Circuit
Digital Outputs from Analog Inputs
The analog capture circuit converts the analog voltage on VINA or VINB and converts it to a 14-bit digital representation, D[13:0], as expressed by Equation 10-1.
D 13:0>@GAIN
The GAIN is the current setting loaded into the programmable pre-amplifier. The various allowable settings for GAIN and allowable voltages applied to the VINA and VINB inputs appear in Table 10-2.
The reference voltage for the amplifier and the ADC is 1.65V, generated via a voltage divider shown in Figure 10-2. Consequently, 1.65V is subtracted from the input voltage on VINA or VINB.
The maximum range of the ADC is r1.25V, centered around the reference voltage, 1.65V. Hence, 1.25V appears in the denominator to scale the analog input accordingly.
Finally, the ADC presents a 14-bit, two’s complement digital output. A 14-bit, two’s complement number represents values between -2 scaled by 8192, or 2
13
.
1.65V
V
IN
----------------------------------- -
u 8192u=
1.25V
UG257_10_02_060706
Equation 10-1
13
and 213-1. Therefore, the quantity is
See “Programmable Pre-Amplifier” to control the GAIN settings on the programmable pre-amplifier.
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The reference design files provide more information on converting the voltage applied on VINA or VINB to a digital representation (see “Related Resources,” page 81).
Programmable Pre-Amplifier
The LTC6912-1 provides two independent inverting amplifiers with programmable gain. The purpose of the amplifier is to scale the incoming voltage on VINA or VINB so that it maximizes the conversion range of the DAC, namely 1.65 r 1.25V.
Interface
Table 10-1 lists the interface signals between the FPGA and the amplifier. The SPI_MOSI,
SPI_MISO, and SPI_SCK signals are shared with other devices on the SPI bus. The AMP_CS signal is the active-Low slave select input to the amplifier.
Ta bl e 1 0 -1 : AMP Interface Signals
Signal FPGA Pin Direction Description
SPI_MOSI T4 FPGAÆAD Serial data: Master Output, Slave Input.
Programmable Pre-Amplifier
Presents 8-bit programmable gain settings, as defined in Table 10-2.
AMP_CS N7 FPGAÆAMP Active-Low chip-select. The amplifier gain is
SPI_SCK U16 FPGAÆAMP Clock
AMP_SHDN P7 FPGAÆAMP Active-High shutdown, reset
AMP_DOUT E18 FPGAÅAMP Serial data. Echoes previous amplifier gain
Programmable Gain
Each analog channel has an associated programmable gain amplifier (see Figure 10-2). Analog signals presented on the VINA or VINB inputs on header J7 are amplified relative to 1.65V. The 1.65V reference is generated using a voltage divider of the 3.3V voltage supply.
The gain of each amplifier is programmable from -1 to -100, as shown in Table 10-2.
Ta bl e 1 0 -2 : Programmable Gain Settings for Pre-Amplifier
Gain
00000
-1 0 0 0 1 0.4 2.9
set when signal returns High.
settings. Can be ignored in most applications.
A3 A2 A1 A0 Input Voltage Range
B3 B2 B1 B0 Minimum Maximum
-2 0 0 1 0 1.025 2.275
-5 0 0 1 1 1.4 1.9
-10 0 1 0 0 1.525 1.775
-20 0 1 0 1 1.5875 1.7125
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Ta bl e 1 0 -2 : Programmable Gain Settings for Pre-Amplifier (Continued)
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Gain
-50 0 1 1 0 1.625 1.675
-100 0 1 1 1 1.6375 1.6625
SPI Control Interface
Figure 10-3 highlights the SPI-bas ed communications interface with the amplifier. The gain
for each amplifier is sent as an 8-bit command word, consisting of two 4-bit fields. The most-significant bit, B3, is sent first.
A3 A2 A1 A0 Input Voltage Range
B3 B2 B1 B0 Minimum Maximum
AMP_DOUT
Spartan-3E
FPGA
Master
SPI_MOSI
AMP_CS
SPI_SCK
0
A
Slave: LTC2624-1
A1A2A
0
3
A Gain B Gain
B
0
B1B2B
7
3
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Figure 10-3: SPI Serial Interface to Amplifier
The AMP_DOUT output from the amplifier echoes the previous gain settings. These values can be ignored for most applications.
The SPI bus transaction starts when the FPGA asserts AMP_CS Low (see Figure 10-4). The amplifier captures serial data on SPI_MOSI on the rising edge of the SPI_SCK clock signal. The amplifier presents serial data on AMP_DOUT on the falling edge of SPI_SCK.
AMP_CS
30
SPI_SCK
30
SPI_MOSI
(from FPGA)
AMP_DOUT
(from AMP)
All timing is minimum in nanoseconds unless otherwise noted.
76543 2
85 max
Previous 7
50
50
UG570_10_04_060706
Figure 10-4: SPI Timing When Communicating with Amplifier
The amplifier interface is relatively slow, supporting only about a 10 MHz clock frequency.
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UCF Location Constraints
Figure 10-5 provides the User Constraint File (UCF) constraints for the amplifier interface,
including the I/O pin assignment and I/O standard used.
NET "SPI_MOSI" LOC = "T4" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ; NET "AMP_CS" LOC = "N7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ; NET "SPI_SCK" LOC = "U16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; NET "AMP_SHDN" LOC = "P7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ; NET "AMP_DOUT" LOC = "E18" | IOSTANDARD = LVCMOS33 ;
Figure 10-5: UCF Location Constraints for the DAC Interface
Analog to Digital Converter (ADC)
The LTC1407A-1 provides two ADCs. Both analog inputs are sampled simultaneously when the AD_CONV signal is applied.
Interface
Analog to Digital Converter (ADC)
UG570_10_05_060706
Table 10-3 lists the interface signals between the FPGA and the ADC. The SPI_MOSI,
SPI_MISO, and SPI_SCK signals are shared with other devices on the SPI bus. The DAC_CS signal is the active-Low slave select input to the DAC. The DAC_CLR signal is the active-Low, asynchronous reset input to the DAC.
Ta bl e 1 0 -3 : ADC Interface Signals
Signal FPGA Pin Direction Description
SPI_SCK U16 FPGAÆADC Clock
AD_CONV P11 FPGAÆADC Active-High shutdown and reset.
SPI_MISO N10 FPGAÅADC Serial data: Master Input, Serial Output. Presents
SPI Control Interface
Figure 10-6 provides an example SPI bus transaction to the ADC.
When the AD_CONV signal goes High, the ADC simultaneously samples both analog channels. The results of this conversion are not presented until the next time AD_CONV is asserted, a latency of one sample. The maxim sample rate is approximately 1.5 MHz.
The ADC presents the digital representation of the sampled analog values as a 14-bit, two’s complement binary value.
the digital representation of the sample analog values as two 14-bit two’s complement binary values.
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Chapter 10: Analog Capture Circuit
SPI_MISO
AD_CONV
SPI_SCK
Spartan-3E
FPGA Master
Sample point
AD_CONV
SPI_SCK
SPI_MISO
Figure 10-7 shows detailed transaction timing. The AD_CONV signal is not a traditional
SPI slave select enable. Be sure to provide enough SPI_SCK clock cycles so that the ADC leaves the SPI_MISO signal in the high-impedance state. Otherwise, the ADC blocks communication to the other SPI peripherals. As shown in Figure 10-6, use a 34-cycle communications sequence. The ADC 3-states its data output for two clock cycles before and after each 14-bit data transfer.
Slave: LTC1407A-1 A/D Converter
616
6
0
Z
Converted data is presented with a latency of one sample. The sampled analog value is converted to digital data 32 SPI_SCK cycles after asserting AD_CONV. The converted values is then presented after the next AD_CONV pulse.
6
6
2
3
676
656
4
6
Channel 1 Channel 0
6116
696
8
12
10
6136
616
0
6
6
656
2
4
3
Z
676
6
Channel 0 Channel 0Channel 1
13
0
13
0
Figure 10-6: Analog-to-Digital Conversion Interface
696
8
10
Sample point
UG257_10_06_060706
6116
R
6
12
13
Z
13
4ns min
AD_CONV
3ns
SPI_SCK
SPI_MISO
AD_CONV
SPI_SCK
Channel 1
SPI_MISO
The A/D converter sets its SDO output line to high impedance after 33 SPI_SCK clock cycles
UCF Location Constraints
Figure 10-8 provides the User Constraint File (UCF) constraints for the amplifier interface,
including the I/O pin assignment and I/O standard used.
12
High-Z
3
2
3
Channel 0
32
10
4
13
45ns min
333130
Figure 10-7: Detailed SPI Timing to ADC
19.6ns min
5
8ns
12 11
34
6ns
6
High-Z
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NET "AD_CONV" LOC = "P11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ; NET "SPI_SCK" LOC = "U16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; NET "SPI_MISO" LOC = "N10" | IOSTANDARD = LVCMOS33 ;
Disable Other Devices on the SPI Bus to Avoid Contention
Figure 10-8: UCF Location Constraints for the ADC Interface
Disable Other Devices on the SPI Bus to Avoid Contention
The SPI bus signals are shared by other devices on the board. It is vital that other devices are disabled when the FPGA communicates with the AMP or ADC to avoid bus contention. Table 10-4 provides the signals and logic values required to disable the other devices. Although the StrataFlash PROM is a parallel device, its least-significant data bit is shared with the SPI_MISO signal. The Platform Flash PROM is only potentially enabled if the FPGA is set up for Master Serial mode configuration.
Ta bl e 1 0 -4 : Disable Other Devices on SPI Bus
Signal Disabled Device Disable Value
UG257_10_08_061406
SPI_SS_B SPI Serial Flash 1
AMP_CS Programmable Pre-Amplifier 1
DAC_CS DAC 1
SF_CE0 StrataFlash Parallel Flash PROM 1
FPGA_INIT_B Platform Flash PROM 1
Connecting Analog Inputs
Connect AC signals to VINA or VINB via a DC blocking capacitor.
Related Resources
x Amplifier and A/D Converter Control for the Spartan-3E Starter Kit (Reference
Design)
x http://www.xilinx.com/s
x Xilinx PicoBlaze Soft Processor
x
http://www.xilinx.com/picoblaze
x LTC6912 Dual Programm able Gain A mplif iers with Serial Digital Interface
x http://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1154,C1009,C1121,
P7596,D5359
x LTC1407 A-1 Seria l 14-b it Sim ultan eous Sampling ADCs with Shutdown
x
http://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1155,C1001,C1158, P2420,D1295
p3e1600e
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Chapter 11
Intel StrataFlash Parallel NOR Flash PROM
As shown in Figure 11-1, the MicroBlaze Development Kit boards includes a 128 Mbit (16 Mbyte) Intel StrataFlash parallel NOR Flash PROM. As indicated, some of the StrataFlash connections are shared with other components on the board.
Spartan-3E FPGA
LDC0
LDC1
HDC
LDC2
User I/O
User I/O
D[7:1] D[7:1]
D[0]
User I/O
A[19:0]
A[23:20]
CoolRunner-II
CPLD
SF_CE0
SF_OE
SF_WE
SF_BYTE
SF_STS
SF_D<15:8>
SF_D<7:1>
SPI_MISO
SF_A<24:20>
SF_A<19:0>
[15:8]
Intel StrataFlash
CE2
CE1
CE0
OE#
WE#
BYTE#
STS
D[15:8]
D[0]
A[24:20]
A[19:0]
LCD Header
DB[7:0]
SPI Serial Flash
Q
ADC
SDO
DAC
SDO
Platform Flash
D0
UG257_11_01_062106
The StrataFlash PROM provides various functions:
x Stores a single FPGA configuration in the StrataFlash device.
x Stores two different FPGA configurations in the StrataFlash device and dynamically
switch between the two using the Spartan-3E FPGA’s MultiBoot feature.
x Stores and executes MicroBlaze processor code directly from the StrataFlash device.
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Figure 11-1: Connections to Intel StrataFlash Flash Memory
Chapter 11: Intel StrataFlash Parallel NOR Flash PROM
x Stores MicroBlaze processor code in the StrataFlash device and shadows the code into
the DDR memory before executing the code.
x Stores non-volatile data from the FPGA.
StrataFlash Connections
Table 11-1 shows the connections between the FPGA and the StrataFlash device.
Although the XC1600E FPGA only requires just slightly under 6 Mbits per configuration image, the FPGA-to-StrataFlash interface on the board support up to a 256 Mbit StrataFlash. The MicroBlaze Development Kit board ships with a 128 Mbit device. Address line SF_A24 is not used.
In general, the StrataFlash device connects to the XC1600E to support Byte Peripheral Interface (BPI) configuration. The upper four address bits from the FPGA, A[23:19] do not connect directly to the StrataFlash device. Instead, the XC2C64 CPLD controls the pins during configuration. As described in Table 11-1 and Shared Connections, some of the StrataFlash connections are shared with other components on the board.
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StrataFlash Connections
Ta bl e 1 1 -1 : FPGA-to-StrataFlash Connections
Category
StrataFlash
Signal Name
FPGA Pin
Number Function
SF_A24 A11 Shared with XC2C64A CPLD. The CPLD
SF_A23 N11
SF_A22 V12
SF_A21 V13
actively drives these pins during FPGA configuration, as described in Chapter 16,
“XC2C64A CoolRunner-II CPLD”. Also
connects to FPGA user-I/O pins. SF_A24 is the same as FX2 connector signal FX2_IO<32>.
SF_A20 T12
SF_A19 V15 Connects to FPGA pins A[19:0] to support the
SF_A18 U15
BPI configuration.
SF_A17 T16
SF_A16 U18
SF_A15 T17
SF_A14 R18
SF_A13 T18
SF_A12 L16
Address
SF_A11 L15
SF_A10 K13
SF_A9 K12
SF_A8 K15
SF_A7 K14
SF_A6 J17
SF_A5 J16
SF_A4 J15
SF_A3 J14
SF_A2 J12
SF_A1 J13
SF_A0 H17
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Chapter 11: Intel StrataFlash Parallel NOR Flash PROM
Ta bl e 1 1 -1 : FPGA-to-StrataFlash Connections
Category
StrataFlash
Signal Name
FPGA Pin
Number Function
SF_D15 T8 Upper 8 bits of a 16-bit
SF_D14 R8
SF_D13 P6
SF_D12 M16
SF_D11 M15
SF_D10 P17
SF_D9 R16
SF_D8 R15
SF_D7 N9 Upper 7 bits of a data byte or lower 8 bits of a
Data
SF_D6 M9
SF_D5 R9
SF_D4 U9
halfword when StrataFlash is configured for x16 data (SF_BYTE=High). Connects to FPGA
Signals SF_D<15:8> connect to character LCD pins DB[7:0].
user I/O.
16-bit halfword. Connects to FPGA pins D[7:1] to support the BPI configuration.
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SF_D3 V9
SF_D2 R10
SF_D1 P10
SPI_MISO N10 Bit 0 of data byte and 16-bit halfword.
Connects to FPGA pin D0/DIN to support the BPI configuration. Shared with other SPI peripherals and Platform Flash PROM.
SF_CE0 D16 StrataFlash Chip Enable. Connects to FPGA
pin LDC0 to support the BPI configuration.
SF_WE D17 StrataFlash Write Enable. Connects to FPGA
pin HDC to support the BPI configuration.
SF_OE C18 StrataFlash Chip Enable. Connects to FPGA
pin LDC1 to support the BPI configuration.
Control
SF_BYTE C17 StrataFlash Byte Enable. Connects to FPGA pin
LDC2 to support the BPI configuration.
0: x8 data
1: x16 data
SF_STS B18 StrataFlash Status signal. Connects to FPGA
user-I/O pin.
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Shared Connections
Besides the connections to the FPGA, the StrataFlash memory shares some connections to other components.
Character LCD
The LCD supports an 8-bit or a 4-bit data interface. The eight display data connections are also shared with the SF_D<15:8> signals on the StrataFlash PROM. As shown in Table 11-2, the FPGA controls access to the StrataFlash PROM or the character LCD using the SF_CE0 and LCD_RW signals.
Ta bl e 1 1 -2 : FPGA Control for StrataFlash and LCD
SF_CE0 LCD_RW Function
11The FPGA reads from the character LCD.
00The FPGA accesses the StrataFlash PROM.
Xilinx XC2C64A CPLD
Shared Connections
The Xilinx XC2C64A CoolRunner CPLD controls the five upper StrataFlash address lines, SF_A<24:20> during configuration. The four upper BPI-mode address lines from the FPGA, A<23:20> are not connected. Instead, four FPGA user-I/O pins connect to the StrataFlash PROM upper address lines SF_A<23:0>. See Chapter 16, “XC2C64A
CoolRunner-II CPLD” for more information.
The most-significant address line, SF_A<24>, is not physically used on the 16 Mbyte StrataFlash PROM. It is provided for upward migration to a larger StrataFlash PROM in the same package footprint. Likewsie, the SF_A<24> signal is also connected to the FX2_IO<32> signal on the FX2 expansion connector.
SPI Data Line
The least-significant StrataFlash data line, SF_D<0>, is shared with data output signals from serial SPI peripherals, SPI_MISO, and the serial output from the Platform Flash PROM as shown in Tab le 1 1- 3. To avoid contention, the FPGA application must ensure that only one data source is active at any time.
Ta bl e 1 1 -3 : Possible Contention on SPI_MISO (SF_D<0>) Data
FPGA_M2 = Low
FPGA_M1 = Low
FPGA_M0 = Low
INIT_B = High
SF_CE0 = Low
SF_OE = Low
AD_CONV = High
SPI_SCK
DAC_CS = Low
SPI_SCK
Condition Function
Platform Flash outputs data on D0.
StrataFlash outputs data.
Serial data is clocked out of the A/D converter
DAC outputs previous command in response to SPI_SCK transitions.
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Chapter 11: Intel StrataFlash Parallel NOR Flash PROM
UCF Location Constraints
Address
Figure 11-2 provides the UCF constraints for the StrataFlash address pins, including the
I/O pin assignment and the I/O standard used.
NET "SF_A<24>" LOC = "A11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_A<23>" LOC = "N11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_A<22>" LOC = "V12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_A<21>" LOC = "V13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_A<20>" LOC = "T12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_A<19>" LOC = "V15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_A<18>" LOC = "U15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_A<17>" LOC = "T16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_A<16>" LOC = "U18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_A<15>" LOC = "T17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_A<14>" LOC = "R18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_A<13>" LOC = "T18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_A<12>" LOC = "L16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_A<11>" LOC = "L15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_A<10>" LOC = "K13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_A<9>" LOC = "K12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_A<8>" LOC = "K15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_A<7>" LOC = "K14" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_A<6>" LOC = "J17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_A<5>" LOC = "J16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_A<4>" LOC = "J15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_A<3>" LOC = "J14" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_A<2>" LOC = "J12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_A<1>" LOC = "J13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_A<0>" LOC = "H17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
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Data
Figure 11-2: UCF Location Constraints for StrataFlash Address Inputs
Figure 11-3 provides the UCF constraints for the StrataFlash data pins, including the I/O
pin assignment and the I/O standard used.
NET "SF_D<15>" LOC = "T8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_D<14>" LOC = "R8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_D<13>" LOC = "P6" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_D<12>" LOC = "M16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_D<11>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_D<10>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_D<9>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_D<8>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_D<7>" LOC = "N9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_D<6>" LOC = "M9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_D<5>" LOC = "R9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_D<4>" LOC = "U9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_D<3>" LOC = "V9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_D<2>" LOC = "R10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_D<1>" LOC = "P10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SPI_MISO" LOC = "N10" | IOSTANDARD = LVCMOS33 | DRIVE = 6 | SLEW = SLOW ;
UG257_11_03_060706
Figure 11-3: UCF Location Constraints for StrataFlash Data I/Os
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Control
Figure 11-4 provides the UCF constraints for the StrataFlash control pins, including the
I/O pin assignment and the I/O standard used.
NET "SF_BYTE" LOC = "C17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_CE0" LOC = "D16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_OE" LOC = "C18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_STS" LOC = "B18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_WE" LOC = "D17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
Figure 11-4: UCF Location Constraints for StrataFlash Control Pins
Setting the FPGA Mode Select Pins
Set the FPGA configuration mode pins for either BPI Up or BPI down mode, as shown in
Table 11-4. See
Ta bl e 1 1 -4 : Selecting BPI-Up or BPI-Down Configuration Modes (Header J30 in
Chapter 4, “FPGA Configuration Options”, Figure 4-2)
Setting the FPGA Mode Select Pins
UG257_11_04_060706
Configuration
Mode
BPI Up 0:1:0 FPGA starts at address 0 and
BPI Down 0:1:1 FPGA starts at address 0xFF_FFFF
Related Resources
x Intel J3 StrataFlash Data Sheet
http://www.intel.com/design/flcomp/products/j3/techdocs.htm#datasheets
x Application Note 827, Intel StrataFlash
Design Guide
http://www.intel.com/design/flcomp/applnots/307257.htm
Mode Pins
M2:M1:M0
FPGA Configuration Image in
StrataFlash Jumper Settings
increments through address space. The CPLD controls address lines A[24:20] during BPI configuration.
and decrements through address space. The CPLD controls address lines A[24:20] during BPI configuration.
®
Memory (J3) to Xilinx Spartan-3E FPGA
M0 M1 M2
J30
M0 M1 M2
J30
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SPI Serial Flash
The MicroBlaze Development Kit board includes a STMicroelectronics M25P16 16 Mbit SPI serial Flash, useful in a variety of applications. The SPI Flash provides an alternative means to configure the FPGA—a new feature of Spartan-3E FPGAs as shown in
Figure 12-1. The SPI Flash is also available to the FPGA after configuration for a variety of
purposes, such as:
x Simple non-volatile data storage
x Storage for identifier codes, serial numbers, IP addresses, etc.
x Storage of MicroBlaze processor code that can be shadowed into DDR SDRAM.
Chapter 12
Spartan-3E FPGA
MOSI/CSI_B
DIN/D0
CCLK
CSO_B
(N10)
(U16)
(T4)
(U3)
SPI_MOSI
SPI_MISO
SPI_SCK
SPI_SS_B
SPI Serial Flash STMicro M25P16
D
Q
C
S
UG257_12_01_060706
Figure 12-1: Spartan-3E FPGAs Have an Optional SPI Flash Configuration Interface
Ta bl e 1 2 -1 : SPI Flash Interface Signals
Signal FPGA Pin Direction Description
SPI_MOSI T4 FPGAÆSPI Serial data: Master Output, Slave Input
SPI_MISO N10 FPGAÅSPI Serial data: Master Input, Slave Output
SPI_SCK U16 FPGAÆSPI Clock
SPI_SS_B U3 FPGAÆSPI Asynchronous, active-Low slave select input
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Chapter 12: SPI Serial Flash
UCF Location Constraints
Figure 12-2 provides the UCF constraints for the SPI serial Flash PROM, including the I/O
pin assignment and the I/O standard used.
# some connections shared with SPI Flash, DAC, ADC, and AMP NET "SPI_MISO" LOC = "N10" | IOSTANDARD = LVCMOS33 ; NET "SPI_MOSI" LOC = "T4" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ; NET "SPI_SCK" LOC = "U16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ; NET "SPI_SS_B" LOC = "U3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ; NET "SPI_ALT_CS_JP11" LOC = "R12" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
Figure 12-2: UCF Location Constraints for SPI Flash Connections
Configuring from SPI Flash
To co nf ig ur e th e FP GA f ro m SP I Fl as h, t he FPGA mode select pins must be set appropriately and the SPI Flash must contain a valid configuration image.
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Select SPI Mode using
the Jumper Settings table.
(Remove top jumper and
insert the bottom two)
Spartan-3E Development Board
DONE Pin LED
(Lights up when FPGA successfully configured)
(When programming SPI Flash using the XSPI
utility, insert jumper to hold PROG_B pin low.)
Figure 12-3: Configuration Options for SPI Mode
(XSPI Programming)
Header J12
Jumper JP8 (XPSI)
PROG_B Push Button Switch
(Press and release to
restart configuration.)
Jumper J11
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Setting the FPGA Mode Select Pins
Set the FPGA configuration mode pins for SPI mode, as shown in Figure 12-4. The location of the configuration mode jumpers (J30) appears in Figure 12-3.
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M0
M1
M2
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Figure 12-4: Set Mode Pins for SPI Mode
Creating an SPI Serial Flash PROM File
The following steps describe how to format an FPGA bitstream for an SPI Serial Flash PROM.
Setting the Configuration Clock Rate
The FPGA supports a 12 MHz configuration clock rate when connected to an M25P16 SPI serial Flash. Set the Properties for Generate Programming File so that the Configuration Rate is 12, as shown in Figure 12-5. See “Generating the FPGA Configuration Bitstream File” in the FPGA Configuration Options chapter for a more detailed description.
Configuring from SPI Flash
J30
Regenerate the FPGA bitstream programming file with the new settings.
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Figure 12-5: Set Configuration Rate to 12 MHz When Using the M25P16 SPI Flash
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Chapter 12: SPI Serial Flash
Formatting an SPI Flash PROM File
After generating the program file, double-click Generate PROM, ACE, or JTAG File to launch the iMPACT software, as shown in Figure 12-6.
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Figure 12-6: Double-Click Generate PROM, ACE, or JTAG File
After iMPACT starts, double-click PROM File Formatter, as shown in Figure 12-7.
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Figure 12-7: Double-Click PROM File Formatter
Choose 3rd Party SPI PROM as the target PROM type, as shown in Figure 12-8. Select from any of the PROM File Formats; the Intel Hex format (MCS) is popular. The PROM Formatter automatically swaps the bit direction as SPI Flash PROMs shift out the most­significant bit (MSB) first. Enter the Location of the directory and the PROM File Name. Click Next > when finished.
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Configuring from SPI Flash
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Figure 12-8: Choose the PROM Target Type, the, Data Format, and File Location
The Spartan-3E Starter Kit board has a 16 Mbit SPI serial Flash PROM. Select 16M from the drop list, as shown in Figure 12-9. Click Next >.
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Figure 12-9: Choose 16M
Chapter 12: SPI Serial Flash
The PROM Formatter then echoes the settings, as shown in Figure 12-10. Click Finish.
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Figure 12-10: Click Finish after Entering PROM Formatter Settings
The PROM Formatter then prompts for the name(s) of the FPGA configuration bitstream file. As shown in Figure 12-11, click OK to start selecting files. Select an FPGA bitstream file (*.bit). Choose No after selecting the last FPGA file. Finally, click OK to continue.
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Figure 12-11: Enter FPGA Configuration Bitstream File(s)
When PROM formatting is complete, the iMPACT software presents the present settings by showing the PROM, the select FPGA bitstream(s), and the amount of PROM space consumed by the bitstream. Figure 12-12 shows an example for a single XC1600E FPGA bitstream stored in an XCF04S Platform Flash PROM.
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Configuring from SPI Flash
Figure 12-12: PROM Formatting Completed
To generate the actual PROM file, click Operations Æ Generate File as shown in
Figure 12-13.
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Figure 12-13: Click Operations Æ Generate File to Create the Formatted PROM File
As shown in Figure 12-14, the iMPACT software indicates that the PROM file was successfully created. The PROM Formatter creates an output file based on the settings shown in Figure 12-8. In this example, the output file is called MySPIFlash.mcs.
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Chapter 12: SPI Serial Flash
Downloading the Design to SPI Flash
There multiple methods to program the SPI Flash, as listed below.
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Figure 12-14: PROM File Formatter Succeeded
x Use the XSPI programming software provided with XAPP445. Download the SPI
Flash via the parallel port using a JTAG parallel programming cable (not provided with the kit).
x Use the PicoBlaze based SPI Flash programmer reference designs. Use a terminal
emulator, such as Hyperlink, to download SPI Flash programming data via the PC’s serial port to the FPGA. The embedded PicoBlaze processor then programs the attached SPI serial Flash. See “Related Resources,” page 104.
x Via the FPGA’s JTAG chain, use a JTAG tool to program the SPI Flash connected to the
FPGA. See the link to the Universal Scan SPI Flash programming tutorial in “Related
Resources,” page 104.
x Additional programming support will be provided in the ISE 8.2i software.
Downloading the SPI Flash using XSPI
The following steps describe how to download the SPI Flash PROM using the XSPI programming utility.
Download and Install the XSPI Programming Utility
Download application note XAPP445 and the associated XSPI programming software (see
“Related Resources,” page 104). Unzip the XSPI software onto the PC.
Attach a JTAG Parallel Programming Cable
The XSPI programming utility uses a JTAG parallel programming cable, such as:
x Xilinx Parallel Cable IV
x Digilent JTAG3 programming cable
These cables are not provided with the MicroBlaze Development Kit board , but can be purchased separately, either from the Xilinx Online Store or from Digilent, Inc. (see
“Related Resources,” page 104).
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