Texas Instruments TLV5627IPWR, TLV5627IPW, TLV5627IDR, TLV5627ID, TLV5627CPWR Datasheet

TLV5627C, TLV5627I

2.7-V TO 5.5-V 8-BIT 4-CHANNEL DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN

SLAS232 – JUNE1999

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Four 8-Bit D/A Converters

D

Programmable Settling Time
of 3 µs or 9 µs Typ

D

TMS320, (Q)SPI, and Microwire Compatible
Serial Interface

D

Low Power Consumption:

7 mW, Slow Mode – 5-V Supply
3 mW, Slow Mode – 3-V Supply

D

Reference Input Buffers

D

Monotonic Over Temperature

D

Dual 2.7-V to 5.5-V Supply (Separate Digital
and Analog Supplies)

D

Hardware Power Down

D

Software Power Down

D

Simultaneous Update

applications

D

Battery Powered Test Instruments

D

Digital Offset and Gain Adjustment

D

Industrial Process Controls

D

Machine and Motion Control Devices

D

Arbitrary Waveform Generation

description

The TLV5627 is a four channel, 8-bit voltage
output digital-to-analog converter (DAC) with a
flexible 4-wire serial interface. The 4-wire serial
interface allows glueless interface to TMS320,
SPI, QSPI, and Microwire serial ports. The
TL V5627 is programmed with a 16-bit serial word
comprised of a DAC address, individual DAC
control bits, and an 8-bit DAC value.

The device has provision for two supplies: one
digital supply for the serial interface (via pins
DV

DD

and DGND), and one for the DACs,

reference buffers and output buffers (via pins AV

DD

and AGND). Each supply is independent of the other, and
can be any value between 2.7 V and 5.5 V . The dual supplies allow a typical application where the DAC will be
controlled via a microprocessor operating on a 3-V supply (also used on pins DV

DD

and DGND), with the DACs

operating on a 5-V supply. The digital and analog supplies can be tied together.
The resistor string output voltage is buffered by an x2 gain rail-to-rail output buffer. The buffer features a

Class AB output stage to improve stability and reduce settling time. A rail-to-rail output stage and a power-down
mode make it ideal for single voltage, battery based applications. The settling time of the DAC is programmable
to allow the designer to optimize speed versus power dissipation. The settling time is chosen by the control bits
within the 16-bit serial input string. A high-impedance buffer is integrated on the REFINAB and REFINCD
terminals to reduce the need for a low source impedance drive to the terminal. REFINAB and REFINCD allow
DACs A and B to have a different reference voltage than DACs C and D.

The device, implemented with a CMOS process, is available in 16-terminal SOIC and TSSOP packages. The
TL V5627C is characterized for operation from 0 °C to 70°C. The TLV5627I is characterized for operation from
–40°C to 85°C.

Copyright  1999, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1
2
3
4
5
6
7
8

16
15
14
13
12
11
10

9

DV

DD

PD

LDAC

DIN

SCLK

CS

FS

DGND

AV

DD

REFINAB
OUTA
OUTB
OUTC
OUTD
REFINCD
AGND

(TOP VIEW)

D OR PW PACKAGE

TLV5627C, TLV5627I

2.7-V TO 5.5-V 8-BIT 4-CHANNEL DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN

SLAS232 – JUNE1999

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

AVAILABLE OPTIONS

PACKAGE

T

A

SOIC

(D)

TSSOP

(PW)

0°C to 70°C TLV5627CD TLV5627CPW

–40°C to 85°C TLV5627ID TLV5627IPW

functional block diagram

7
5

Power-On

Reset

10-Bit

Data

and

Control

Register

REFINAB

AGND

CS

DIN

DAC A

Serial

Input

Register

6

9

8-Bit
DAC

Latch

2-Bit

Control

Data

Latch

Power Down/

Speed Control

_

+

8

2

2

8

10

OUTA

DAC

Select/

Control

Logic

FS

DAC B

DAC C

DAC D

OUTB

OUTC

OUTD

LDAC

PD

DGND

AV

DD

DV

DD

4

15 16 1

8

32

11

12

13

14

REFINCD

SCLK

2

x2

TLV5627C, TLV5627I

2.7-V TO 5.5-V 8-BIT 4-CHANNEL DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN

SLAS232 – JUNE1999

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NAME NO.

I/O

DESCRIPTION

AGND 9 Analog ground
AV

DD

16 Analog supply
CS 6 I Chip select. This terminal is active low.
DGND 8 Digital ground
DIN 4 I Serial data input
DV

DD

1 Digital supply

FS 7 I Frame sync input. The falling edge of the frame sync pulse indicates the start of a serial data frame shifted out

to the TLV5627.

PD 2 I Power-down pin. Powers down all DACs (overriding their individual power down settings), and all output stages.

This terminal is active low.

LDAC 3 I Load DAC. When the LDAC signal is high, no DAC output updates occur when the input digital data is read into

the serial interface. The DAC outputs are only updated when LDAC

is low.
REFINAB 15 I Voltage reference input for DACs A and B.
REFINCD 10 I Voltage reference input for DACs C and D.
SCLK 5 I Serial clock input
OUTA 14 O DAC A output
OUTB 13 O DAC B output
OUTC 12 O DAC C output
OUTD 11 O DAC D output

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage, (DV

DD

, AVDD to GND) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Supply voltage difference, (AV

DD

to DVDD) –2.8 V to 2.8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage range –0.3 V to DV

DD

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference input voltage range –0.3 V to AV

DD

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T

A

: TLV5627C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TLV5627I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150° C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

TLV5627C, TLV5627I

2.7-V TO 5.5-V 8-BIT 4-CHANNEL DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN

SLAS232 – JUNE1999

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended operating conditions

MIN NOM MAX UNIT

pp

5-V supply 4.5 5 5.5

Suppl

y v

oltage, AV

DD

,

DV

DD

3-V supply 2.7 3 3.3

V

High-level digital input, V

IH

DVDD = 2.7 V to 5.5 V 2 V

Low-level digital input, V

IL

DVDD = 2.7 V to 5.5 V 0.8 V
5-V supply (see Note 1) 0 2.048 AVDD–1.5

Reference voltage, V

ref

to REFINAB, REFINCD terminal

3-V supply (see Note 1) 0 1.024 AVDD–1.5

V

Load resistance, R

L

2 10 kΩ

Load capacitance, C

L

100 pF

Serial clock rate, SCLK 20 MHz

p

p

TLV5627C 0 70

°

Operating free-air temperature

TLV5627I –40 85

°C

NOTE 1: Voltages greater than AVDD/2 will cause output saturation for large DAC codes.

electrical characteristics over recommended operating free-air temperature range
(unless otherwise noted)

static DAC specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Resolution 8 bits
Integral nonlinearity (INL), end point adjusted See Note 2 ±0.3 ±0.5 LSB
Differential nonlinearity (DNL) See Note 3 ±0.03 ±0.5 LSB

E

ZS

Zero scale error (offset error at zero scale) See Note 4 ±10 mV
Zero scale error temperature coefficient See Note 5 10 ppm/°C

E

G

Gain error See Note 6 ±0.6

%of FS
voltage

Gain error temperature coefficient See Note 7 10 ppm/°C

NOTES: 2. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error , is the maximum deviation of the output

from the line between zero and full scale excluding the effects of zero code and full-scale errors.

3. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal
1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains
constant) as a change in the digital input code.

4. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.

5. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (T

max

) – EZS (T

min

)]/V

ref

× 106/(T

max

– T

min

).

6. Gain error is the deviation from the ideal output (2V

ref

– 1 LSB) with an output load of 10 kΩ excluding the effects of the zero-error.

7. Gain temperature coef ficient is given by: EG TC = [EG(T

max

) – EG (T

min

)]/V

ref

× 106/(T

max

– T

min

).

TLV5627C, TLV5627I

2.7-V TO 5.5-V 8-BIT 4-CHANNEL DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN

SLAS232 – JUNE1999

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range
(unless otherwise noted) (continued)

individual DAC output specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

O

Voltage output RL = 10 kΩ 0 AVDD–0.1 V
Output load regulation accuracy RL = 2 kΩ vs 10 kΩ 0.1 0.25

% of FS

voltage

reference input (REFINAB, REFINCD)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

I

Input voltage range See Note 8 0 AVDD–1.5 V

R

I

Input resistance 10 MΩ

C

I

Input capacitance 5 pF
Reference feed through

REFIN = 1 Vpp at 1 kHz + 1.024 V dc
(see Note 9)

–75 dB

p

Slow 0.5

Reference input bandwidth

REFIN

= 0.2

V

pp

+ 1.

024 V dc

Fast 1

MH

z

NOTES: 8. Reference input voltages greater than VDD/2 will cause output saturation for large DAC codes.

9. Reference feedthrough is measured at the DAC output with an input code = 000 hex and a V

ref(REFINAB or REFINCD)

input = 1.024 Vdc + 1 Vpp at 1 kHz.

digital inputs (D0–D11, CS, WEB, LDAC, PD)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

I

IH

High-level digital input current VI = DV

DD

±1 µA

I

IL

Low-level digital input current VI = 0 V ±1 µA

C

I

Input capacitance 3 pF

power supply

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

pp

Slow 1.4 2.2

pp

5-V suppl

y, No

load, Clock running

Fast 3.5 5.5

mA

IDDPower supply current

pp

Slow 1 1.5

3-V suppl

y, No

load, Clock running

Fast 3 4.5

mA

Power down supply current, See Figure 12 1 µA

pp

Zero scale gain

–68

PSRR

Power supply rejection ratio

Gain

See Notes 10 and 11

–68

dB

10. Zero-scale-error rejection ratio (EZS–RR) is measured by varying the AVDD from 5 ±0.5 V and 3 ±0.5 V dc, and measuring the
proportion of this signal imposed on the zero-code output voltage.

11. Gain-error rejection ratio (EG-RR) is measured by varying the A VDD from 5 ±0.5 V and 3 ±0.5 V dc and measuring the proportion
of this signal imposed on the full-scale output voltage after subtracting the zero scale change.

TLV5627C, TLV5627I

2.7-V TO 5.5-V 8-BIT 4-CHANNEL DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN

SLAS232 – JUNE1999

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range
(unless otherwise noted) (continued)

analog output dynamic performance

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

p

CL = 100 pF, RL = 10 kΩ,

Fast 5 V/µs

SR

Output slew rate

V

O

=

10% to 90%

,

V

ref

= 2.048 V , 1024 V

Slow 1 V/µs

p

To ± 0.1 LSB, C

= 100 pF,

Fast 2.5 4

tsOutput settling time

,

L

,

RL = 10 kΩ, See Notes 12 and 14

Slow 8.5 18

µ

s

p

To ± 0.1 LSB, C

= 100 pF,

Fast 1

t

s(c)

Output settling time, code to code

,

L

,

RL = 10 kΩ, See Notes 13 and 14

Slow 2

µ

s

Glitch energy Code transition from 7F0 to 800 10 nV-sec

SNR Signal-to-noise ratio

57

S/(N+D) Signal to noise + distortion

Sinewave generated by DAC

,

Reference volta

g

e = 1.024 at 3 V and 2.048 at 5 V ,

49

THD Total harmonic distortion

g,

fs = 400 KSPS, f

OUT

= 1.1 kHz sinewave,

–50

dB

SFDR Spurious free dynamic range

C

L

=

100 pF

,

R

L

= 10 kΩ, BW = 20 kHz

60

NOTES: 12. Settling time is the time for the output signal to remain within ± 0.1 LSB of the final measured value for a digital input code change

of 0x020 to 0xFF0 or 0xFF0 to 0x020.

13. Settling time is the time for the output signal to remain within ± 0.1 LSB of the final measured value for a digital input code change
of one count.

14. Limits are ensured by design and characterization, but are not production tested.

digital input timing requirements

MIN NOM MAX UNIT

t

su(CS–FS)

Setup time, CS low before FS↓ 10 ns

t

su(FS–CK)

Setup time, FS low before first negative SCLK edge 8 ns

t

su(C16–FS)

Setup time, sixteenth negative edge after FS low on which bit D0 is sampled before rising
edge of FS

10 ns

t

su(C16–CS)

Setup time, sixteenth positive SCLK edge (first positive after D0 is sampled) before CS rising
edge. If FS is used instead of the sixteenth positive edge to update the DAC, then the setup
time is between the FS rising edge and CS

rising edge.

10 ns

t

wH

Pulse duration, SCLK high 25 ns

t

wL

Pulse duration, SCLK low 25 ns

t

su(D)

Setup time, data ready before SCLK falling edge 8 ns

t

h(D)

Hold time, data held valid after SCLK falling edge 5 ns

t

wH(FS)

Pulse duration, FS high 20 ns