Texas Instruments TLC5540IPWR, TLC5540IPW, TLC5540INSR, TLC5540INSLE, TLC5540INS Datasheet

TLC5540

8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER

SLAS105C – JANUARY 1995 – REVISED MAY 1999

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

features

D

8-Bit Resolution

D

Differential Linearity Error
– ±0.3 LSB Typ, ±1 LSB Max (25°C)
– ±1 LSB Max

D

Integral Linearity Error
– ±0.6 LSB, ±0.75 LSB Max (25°C)
– ±1 LSB Max

D

Maximum Conversion Rate of
40 Megasamples Per Second (MSPS) Max

D

Internal Sample and Hold Function

D

5-V Single Supply Operation

D

Low Power Consumption...85 mW Typ

D

Analog Input Bandwidth...≥75 MHz Typ

D

Internal Reference Voltage Generators

applications

D

Quadrature Amplitude Modulation (QAM)
and Quadrature Phase Shift Keying (QPSK)
Demodulators

D

Digital Television

D

Charge-Coupled Device (CCD) Scanners

D

Video Conferencing

D

Digital Set-Top Box

D

Digital Down Converters

D

High-Speed Digital Signal Processor
Front End

description

The TLC5540 is a high-speed, 8-bit analog-to-digital converter (ADC) that converts at sampling rates up to
40 megasamples per second (MSPS). Using a semiflash architecture and CMOS process, the TLC5540 is able
to convert at high speeds while still maintaining low power consumption and cost. The analog input bandwidth
of 75 MHz (typ) makes this device an excellent choice for undersampling applications. Internal resistors are
provided to generate 2-V full-scale reference voltages from a 5-V supply, thereby reducing external
components. The digital outputs can be placed in a high impedance mode. The TLC5540 requires only a single
5-V supply for operation.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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24
23
22
21
20
19
18
17
16
15
14
13

OE

DGND

D1(LSB)

D2
D3
D4
D5
D6
D7

D8(MSB)

V

DDD

CLK

DGND
REFB
REFBS
AGND
AGND
ANALOG IN
V

DDA

REFT
REFTS
V

DDA

V

DDA

V

DDD

PW OR NS PACKAGE

(TOP VIEW)

AVAILABLE OPTIONS

–0°C to 70°C

SOP (NS)

T

A

TLC5540CNSLE

PACKAGE

TSSOP (PW)

TLC5540CPW

–40°C to 85°C

TLC5540INSLE

TLC5540IPW

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Copyright  1999, Texas Instruments Incorporated

TLC5540
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER

SLAS105C – JANUARY 1995 – REVISED MAY 1999

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

Lower Sampling

Comparators

(4 Bit)

Lower Encoder

(4 Bit)

Lower Data

Latch

Lower Sampling

Comparators

(4 Bit)

Lower Encoder

(4 Bit)

Upper Sampling

Comparators

(4 Bit)

Upper Encoder

(4 Bit)

Upper Data

Latch

Clock

Generator

OE

D1(LSB)
D2
D3
D4

D5
D6
D7
D8(MSB)

CLK

REFB

REFT

REFBS

AGND
AGND

ANALOG IN

V

DDA

REFTS

270 Ω
NOM

80 Ω
NOM

320 Ω
NOM

Resistor

Reference

Divider

schematics of inputs and outputs

EQUIVALENT OF ANALOG INPUT

V

DDA

AGND

ANALOG IN

EQUIVALENT OF EACH DIGITAL INPUT

V

DDD

DGND

OE, CLK

EQUIVALENT OF EACH DIGITAL OUTPUT

V

DDD

DGND

D1–D8

TLC5540

8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER

SLAS105C – JANUARY 1995 – REVISED MAY 1999

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NAME NO.

I/O

DESCRIPTION

AGND 20, 21 Analog ground
ANALOG IN 19 I Analog input
CLK 12 I Clock input
DGND 2, 24 Digital ground
D1–D8 3–10 O Digital data out. D1:LSB, D8:MSB
OE 1 I Output enable. When OE = L, data is enabled. When OE = H, D1–D8 is high impedance.
V

DDA

14, 15, 18 Analog V

DD

V

DDD

11, 13 Digital V

DD

REFB 23 I ADC reference voltage in (bottom)
REFBS 22 Reference voltage (bottom). When using the internal voltage divider to generate a nominal 2-V reference,

the REFBS terminal is shorted to the REFB terminal and the REFTS terminal is shorted to the REFT terminal

(see Figure 13 and Figure 14).
REFT 17 I Reference voltage in (top)
REFTS 16 Reference voltage (top). When using the internal voltage divider to generate a nominal 2-V reference, the

REFTS terminal is shorted to the REFT terminal and the REFBS terminal is shorted to the REFB terminal

(see Figure 13 and Figure 14).

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage, V

DDA

, V

DDD

7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference voltage input range, V

I(REFT)

, V

I(REFB)

, V

I(REFBS)

, V

I(REFTS)

AGND to V

DDA

. . . . . . . . . . . . . . .

Analog input voltage range, V

I(ANLG)

AGND to V

DDA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage range, V

I(DGTL)

DGND to V

DDD

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital output voltage range, V

O(DGTL)

DGND to V

DDD

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T

A

: TLC5540C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TLC5540I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

TLC5540
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER

SLAS105C – JANUARY 1995 – REVISED MAY 1999

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended operating conditions

MIN NOM MAX UNIT

V

DDA

–AGND 4.75 5 5.25

Supply voltage

V

DDD

–AGND 4.75 5 5.25

V

AGND–DGND –100 0 100 mV

Reference input voltage (top), V

I(REFT)

V

I(REFB)

+1.8 V

I(REFB)

+2 V

DDA

V

Reference input voltage (bottom), V

I(REFB)

0 0.6 V

I(REFT)

–1.8 V

Analog input voltage range, V

I(ANLG)

(see Note 1) V

I(REFB)

V

I(REFT)

V

Full scale voltage, V

I(REFT)

– V

I(REFB)

1.8 5 V

High-level input voltage, V

IH

4 V

Low-level input voltage, V

IL

1 V

Pulse duration, clock high, t

w(H)

12.5 ns

Pulse duration, clock low, t

w(L)

12.5 ns

p

p

TLC5540C 0 70 °C

Operating free-air temperature, T

A

TLC5540I –40 85 °C

NOTE 1: 1.8 V ≤ V

I(REFT)

– V

I(REFB)

< V

DD

TLC5540

8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER

SLAS105C – JANUARY 1995 – REVISED MAY 1999

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics at VDD = 5 V, V

I(REFT)

= 2.6 V, V

I(REFB)

= 0.6 V, fs = 40 MSPS, TA = 25°C

(unless otherwise noted)

PARAMETER TEST CONDITIONS

†

MIN TYP MAX UNIT

TA = 25°C ±0.6 ±1

ELLinearity error, integral

f

= 40 MSPS,

TA = MIN to MAX ±1

s

,

VI = 0.6 V to 2.6 V

TA = 25°C ±0.3 ±0.75

LSB

EDLinearity error, differential

TA = MIN to MAX ±1

Self bias (1), V

RB

Short REFB to REFBS

0.57 0.61 0.65

Self bias (1), V

RT

Short REFT to REFTS

See Figure 13

2.47 2.63 2.80

Self bias (2), V

RB

Short REFB to AGND

AGND

V

Self bias (2), V

RT

Short REFT to REFTS

See Figure 14

2.18 2.29 2.4

I

ref

Reference-voltage current V

I(REFT)

– V

I(REFB)

= 2 V 5.2 7.5 12 mA

R

ref

Reference-voltage resistor Between REFT and REFB terminals 165 270 350 Ω

C

i

Analog input capacitance V

I(ANLG)

= 1.5 V + 0.07 V

rms

4 pF

E

ZS

Zero-scale error

–18 –43 –68

E

FS

Full-scale error

V

I(REFT)

–

V

I(REFB)

= 2

V

–25 0 25

mV

I

IH

High-level input current VDD = 5.25 V , VIH = V

DD

5

I

IL

Low-level input current VDD = 5.25 V , VIL = 0 5

µ

A

I

OH

High-level output current OE = GND, VDD = 4.75 V , VOH = VDD–0.5 V –1.5

I

OL

Low-level output current OE = GND, VDD = 4.75 V , VOL = 0.4 V 2.5

mA

I

OZH(lkg)

High-level
high-impedance-state
output leakage current

OE = VDD, VDD = 5.25, VOH = V

DD

16

I

OZL(lkg)

Low-level
high-impedance-state
output leakage current

OE = VDD, VDD = 4.75, VOL = 0 16

µ

A

I

DD

Supply current

fs = 40 MSPS,
CL 25 pF,

NTSC‡ ramp wave input,
See Note 2

17 27 mA

†

Conditions marked MIN or MAX are as stated in recommended operating conditions.

‡

National Television System Committee

NOTE 2: Supply current specification does not include I

ref

.

TLC5540
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER

SLAS105C – JANUARY 1995 – REVISED MAY 1999

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

operating characteristics at VDD = 5 V, VRT = 2.6 V, VRB = 0.6 V, fs = 40 MSPS, TA = 25°C (unless
otherwise noted)

PARAMETER TEST CONDITIONS

†

MIN TYP MAX UNIT

f

s

Maximum conversion rate TA = MIN to MAX 40 MSPS

f

s

Minimum conversion rate TA = MIN to MAX 5 MSPS

BW Analog input full-power bandwidth At – 3 dB, V

I(ANLG)

= 2 V

pp

75 MHz

t

pd

Delay time, digital output CL ≤ 10 pF (see Note 3) 9 15 ns

t

PHZ

Disable time, output high to Hi-Z CL ≤ 15 pF, IOH = –4.5 mA 20 ns

t

PLZ

Disable time, output low to Hi-Z CL ≤ 15 pF, IOL = 5 mA 20 ns

t

PZH

Enable time, Hi-Z to output high CL ≤ 15 pF, IOH = –4.5 mA 15 ns

t

PZL

Enable time, Hi-Z to output low CL ≤ 15 pF, IOL = 5 mA 15 ns
Differential gain

NTSC 40 IRE‡ modulation wave

,

1%

Differential phase

NTSC 40 IRE modulation wave,

fs = 14.3 MSPS

0.7 degrees

t

AJ

Aperture jitter time 30 ps

t

d(s)

Sampling delay time 4 ns

fI = 1 MHz 47
fI = 3 MHz 44 47

f

s

=

20 MSPS

fI = 6 MHz 46

SNR Signal-to-noise ratio

fI = 10 MHz 45

dB

fI = 3 MHz 45.2

fs = 40 MSPS

fI = 6 MHz 42 44
fI = 10 MHz 42
fI = 1 MHz 7.64
fI = 3 MHz 7.61

f

s

= 20

MSPS

fI = 6 MHz 7.47

ENOB

Effective number of bits

fI = 10 MHz 7.16

Bits

fI = 3 MHz 7

f

s

= 40

MSPS

fI = 6 MHz 6.8
fI = 1 MHz 43
fI = 3 MHz 35 42

f

s

= 20

MSPS

fI = 6 MHz 41

THD

Total harmonic distortion

fI = 10 MHz 38

dBc

fI = 3 MHz 40

f

s

= 40

MSPS

fI = 6 MHz 38

p

fs = 20 MSPS

41 46

Spurious free dynamic range

fs = 40 MSPS

f

I

=

3 MH

z

42

dBc

†

Conditions marked MIN or MAX are as stated in recommended operating conditions.

‡

Institute of Radio Engineers

NOTE 3: CL includes probe and jig capacitance.