TEXAS INSTRUMENTS TLC5510, TLC5510A Technical data

MAXIMUM FULL-SCALE

20°C to 75°C

TLC5510, TLC5510A

8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS

SLAS095K – SEPTEMBER 1994 – REVISED MA Y 1999

D

features

D

Analog Input Range
– TLC5510...2 V Full Scale
– TLC5510A...4 V Full Scale

D

8-Bit Resolution

D

Integral Linearity Error

±0.75 LSB Max (25°C)
±1 LSB Max (–20°C to 75°C)

D

Differential Linearity Error

±0.5 LSB Max (25°C)
±0.75 LSB Max (–20°C to 75°C)

D

Maximum Conversion Rate

20 Mega-Samples per Second
(MSPS) Max

description

The TLC5510 and TLC5510A are CMOS, 8-bit, 20
MSPS analog-to-digital converters (ADCs) that
utilize a semiflash architecture. The TLC5510 and
TLC5510A operate with a single 5-V supply and
typically consume only 130 mW of power.
Included is an internal sample-and-hold circuit,
parallel outputs with high-impedance mode, and
internal reference resistors.

The semiflash architecture reduces power
consumption and die size compared to flash
converters. By implementing the conversion in a
2-step process, the number of comparators is
significantly reduced. The latency of the data
output valid is 2.5 clocks.

The TLC5510 uses the three internal reference
resistors to create a standard, 2-V, full-scale
conversion range using V
need for external reference resistors. The TLC5510A uses only the center internal resistor section with an
externally applied 4-V reference such that a 4-V input signal can be used. Differential linearity is 0.5 LSB at 25°C
and a maximum of 0.75 LSB over the full operating temperature range. Typical dynamic specifications include
a differential gain of 1% and differential phase of 0.7 degrees.

. Only external jumpers are required to implement this option and eliminates the

DDA

5-V Single-Supply Operation

D

Low Power Consumption
TLC5510 . . . 127.5 mW Typ
TLC5510A . . . 150 mW Typ

(includes reference resistor dissipation)

D

TLC5510 is Interchangeable With Sony
CXD1175

applications

D

Digital TV

D

Medical Imaging

D

Video Conferencing

D

High-Speed Data Conversion

D

QAM Demodulators

PW OR NS PACKAGE

(TOP VIEW)

OE

1

DGND

D1(LSB)

D8(MSB)

V

†

Available in tape and reel only and ordered
as the shown in the Available Options table
below.

D2
D3
D4
D5
D6
D7

DDD

CLK

2
3
4
5
6
7
8
9
10
11
12

DGND

24

REFB

23

REFBS

22

AGND

21

AGND

20

ANALOG IN

19

V

18

REFT

17

REFTS

16

V

15

V

14

V

13

†

DDA

DDA
DDA
DDD

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

The TLC5510 and TLC5510A are characterized for operation from –20°C to 75°C.

AVAILABLE OPTIONS

PACKAGE

T

A

°

–

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

°

TSSOP (PW)

TLC5510IPW TLC5510INSLE 2 V

– TLC5510AINSLE 4 V

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SOP (NS)

(TAPE AND REEL ONLY)

INPUT VOLTAGE

Copyright  1999, Texas Instruments Incorporated

1

TLC5510, TLC5510A
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS

SLAS095K – SEPTEMBER 1994 – REVISED MA Y 1999

functional block diagram

Resistor

Reference

Divider

REFB

270 Ω
NOM

REFT

REFBS

AGND
AGND

V

DDA

REFTS

ANALOG IN

CLK

80 Ω
NOM

320 Ω
NOM

Clock

Generator

Lower Sampling

Comparators

(4-Bit)

Lower Sampling

Comparators

(4-Bit)

Upper Sampling

Comparators

(4-Bit)

Lower Encoder

(4-Bit)

Lower Encoder

(4-Bit)

Upper Encoder

(4-Bit)

OE

Lower Data

Latch

Upper Data

Latch

D1(LSB)
D2
D3
D4

D5
D6
D7
D8(MSB)

schematics of inputs and outputs

EQUIVALENT OF ANALOG INPUT

V

DDA

ANALOG IN

AGND

EQUIVALENT OF EACH DIGITAL INPUT

OE, CLK

V

DDD

DGND

EQUIVALENT OF EACH DIGITAL OUTPUT

V

DDD

D1–D8

DGND

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

I/O

DESCRIPTION

V

TLC5510, TLC5510A

8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS

SLAS095K – SEPTEMBER 1994 – REVISED MA Y 1999

Terminal Functions

TERMINAL

NAME NO.

AGND 20, 21 Analog ground
ANALOG IN 19 I Analog input
CLK 12 I Clock input
DGND 2, 24 Digital ground
D1–D8 3–10 O Digital data out. D1 = LSB, D8 = MSB
OE 1 I Output enable. When OE = low, data is enabled. When OE = high, D1–D8 is in high-impedance state.
V

DDA

V

DDD

REFB 23 I Reference voltage in bottom
REFBS 22 Reference voltage in bottom. When using the TLC5510 internal voltage divider to generate a nominal 2-V

REFT 17 I Reference voltage in top
REFTS 16 Reference voltage in top. When using the TLC5510 internal voltage divider to generate a nominal 2-V

14, 15, 18 Analog supply voltage

11, 13 Digital supply voltage

reference, REFBS is shorted to REFB (see Figure 3). When using the TLC5510A, REFBS is connected to
ground.

reference, REFTS is shorted to REFT (see Figure 3). When using the TLC5510A, REFTS is connected to
V

.

DDA

, V

†

7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DDD

I(ANLG)

I(DGTL)

O(DGTL)

stg

, V

REFT

AGND to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DGND to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DGND to V

A

AGND to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

REFB

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–20°C to 75°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

absolute maximum ratings

Supply voltage, V
Reference voltage input range, V
Analog input voltage range, V
Digital input voltage range, V
Digital output voltage range, V
Operating free-air temperature range, T
Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

DDA

recommended operating conditions

MIN NOM MAX UNIT

V

–AGND 4.75 5 5.25

DDA

Supply voltage

Reference input voltage (top), V
Reference input voltage (bottom), V
Analog input voltage range, V
High-level input voltage, V
Low-level input voltage, V
Pulse duration, clock high, t
Pulse duration, clock low, t

‡

The reference voltage levels for the TLC5510 are derived through an internal resistor divider between V
derived from a separate external voltage source (see the electrical characteristics and text). For the 4 V input range of the TLC5510A, the
reference voltage is externally applied across the center divider resistor.

IH

IL

w(H)

w(L)

‡

ref(T)

I(ANLG)

(see Figure 1) 25 ns

(see Figure 1) 25 ns

ref(B)

‡

V

–AGND 4.75 5 5.25

DDD

AGND–DGND –100 0 100 mV
TLC5510A V
TLC5510A 0 V

+2 4 V

REFB

REFT

V

REFB

4 V

and ground and therefore are not

DDA

V

REFT

–4 V

V

1 V

DDA
DDA
DDD
DDD

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

TLC5510, TLC5510A

A

mA

A

I

Reference voltage current

Short REFB to REFBS

Short REFT to REFTS

TLC5510

(CLK)

,

Integral nonlinearity (INL)

TLC5510A

(CLK)

,

LSB

TLC5510

(CLK)

,

Differential nonlinearity (DNL)

TLC5510A

(CLK)

,

EZSZero-scale error

EFSFull-scale error

8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS

SLAS095K – SEPTEMBER 1994 – REVISED MA Y 1999

electrical characteristics at VDD = 5 V , V

REFT

= 2.5 V , V

REFB

otherwise noted)

digital I/O

PARAMETER TEST CONDITIONS

I

IH

I

IL

I

OH

I

OL

I

OZH

I

OZL

†

Conditions marked MIN or MAX are as stated in recommended operating conditions.

power

I

DD

ref

†

Conditions marked MIN or MAX are as stated in recommended operating conditions.

static performance

R

ref

C

i

†

Conditions marked MIN or MAX are as stated in recommended operating conditions.

High-level input current VDD = MAX, VIH = V
Low-level input current VDD = MAX, VIL = 0 5
High-level output current OE = GND, VDD = MIN, VOH = VDD–0.5 V –1.5
Low-level output current OE = GND, VDD = MIN, VOL = 0.4 V 2.5
High-level high-impedance-state

output leakage current
Low-level high-impedance-state

output leakage current

PARAMETER TEST CONDITIONS

Supply current

PARAMETER TEST CONDITIONS

Self-bias (1), at REFB
Self-bias (2), REFT – REFB
Self-bias (3), at REFT Short REFB to AGND, Short REFT to REFTS 2.18 2.29 2.4
Reference voltage resistor Between REFT and REFB 190 270 350 Ω
Analog input capacitance V

OE = VDD, VDD = MAX VOH = V

OE = VDD, VDD = MIN VOL = 0 16

f

= 20 MHz, National Television System Committee (NTSC)

(CLK)

ramp wave input, reference resistor dissipation is separate
TLC5510 V

TLC5510A V

= 1.5 V + 0.07 V

I(ANLG)

f

= 20 MHz,

VI = 0.5 V to 2.5 V
f

= 20 MHz,

VI = 0 to 4 V
f

= 20 MHz,

VI = 0.5 V to 2.5 V
f

= 20 MHz,

VI = 0 to 4 V

TLC5510 V
TLC5510A V
TLC5510 V

TLC5510A V

= REFT – REFB = 2 V –18 –43 –68 mV

ref

= REFT – REFB = 4 V –36 –86 –136 mV

ref

= REFT – REFB = 2 V –20 0 20 mV

ref

= REFT – REFB = 4 V –40 0 40 mV

ref

DD

= REFT – REFB = 2 V 5.2 7.5 10.5 mA

ref

= REFT – REFB = 4 V 10.4 15 21 mA

ref

,

= 0.5 V , f

†

DD

†

†

rms

TA = 25°C ±0.4 ±0.75
TA = –20°C to 75°C ±1
TA = 25°C ±0.4 ±0.75
TA = –20°C to 75°C ±1
TA = 25°C ±0.3 ±0.5
TA = –20°C to 75°C ±0.75
TA = 25°C ±0.3 ±0.5
TA = –20°C to 75°C ±0.75

= 20 MHz, TA = 25°C (unless

(CLK)

MIN TYP MAX UNIT

MIN TYP MAX UNIT

18 27 mA

MIN TYP MAX UNIT

0.57 0.61 0.65

1.9 2.02 2.15

16 pF

16

5

µ

µ

V

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

f

Maximum conversion rate

f

1-kHz ramp

g()

Input tone

Input tone

Spurious free dynamic range (SFDR)

dB

Input tone

Input tone

SNR

Signal-to-noise ratio

dB

TLC5510, TLC5510A

8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS

SLAS095K – SEPTEMBER 1994 – REVISED MA Y 1999

operating characteristics at VDD = 5 V , V

REFT

= 2.5 V , V

REFB

= 0.5 V , f

= 20 MHz, TA = 25°C (unless

(CLK)

otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

conv

BW Analog input bandwidth At – 1 dB 14 MHz
t

Digital output delay time CL ≤ 10 pF (see Note 1 and Figure 1) 18 30 ns

d(D)

Differential gain
Differential phase

t

Aperture jitter time 30 ps

AJ

t

Sampling delay time 4 ns

d(s)

t

Enable time, OE↓ to valid data CL = 10 pF 5 ns

en

t

Disable time, OE↑ to high impedance CL = 10 pF 7 ns

dis

p

NOTE 1: CL includes probe and jig capacitance.

TLC5510
TLC5510A

=

I

NTSC 40 Institute of Radio Engineers (IRE)
modulation wave, f

p

p

p

p

TA = 25°C 46
Full range 44

p

= 1 MHz

= 3 MHz

= 6 MHz

= 10 MHz

V
V

conv

TA = 25°C 45
Full range 43
TA = 25°C 45
Full range 46
TA = 25°C 43
Full range 42
TA = 25°C 39
Full range 39

= 0.5 V – 2.5 V 20 MSPS

I(ANLG)

= 0 V – 4 V 20 MSPS

I(ANLG)

1%

= 14.3 MSPS

0.7 degrees

CLK (clock)

ANALOG IN

(input signal)

D1–D8

(output data)

t

w(H)

t

d(s)

t

w(L)

N

N–3 N–2 N–1 N N+1

t

d(D)

N+1

N+2

N+3

N+4

Figure 1. I/O Timing Diagram

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5