TEXAS INSTRUMENTS TLC551, TLC551Y Technical data

TLC551, TLC551Y

LinCMOS TIMERS

SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997

D

Very Low Power Consumption

1 mW Typ at VDD = 5 V

D

Capable of Operation in Astable Mode

D

CMOS Output Capable of Swinging Rail
to Rail

D

High Output-Current Capability

D, DB, P, OR PW PACKAGE

(TOP VIEW)

GND

TRIG

OUT

RESET

1
2
3
4

8
7
6
5

V

DD

DISCH
THRES
CONT

Sink 100 mA Typ
Source 10 mA Typ

D

Output Fully Compatible With CMOS, TTL,
and MOS

D

Low Supply Current Reduces Spikes
During Output Transitions

D

Single-Supply Operation From 1 V to 15 V

D

Functionally Interchangeable With the

unctional block diagram

HRES

CONT

V

DD

8

R

6

R

RESET

5

4

R1
R
S

1

NE555; Has Same Pinout

2

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015.2

description

The TLC551 is a monolithic timing circuit
fabricated using the TI LinCMOSprocess. The

TRIG

R

1

GND

RESET can override TRIG, which can override THRES.

timer is fully compatible with CMOS, TTL, and MOS logic and operates at frequencies up to 2 MHz. Compared
to the NE555 timer, this device uses smaller timing capacitors because of its high input impedance. As a result,
more accurate time delays and oscillations are possible. Power consumption is low across the full range of
power supply voltage.

7

3

OUT

DISCH

Like the NE555, the TLC551 has a trigger level equal to approximately one-third of the supply voltage and a
threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of
the control voltage terminal (CONT). When the trigger input (TRIG) falls below the trigger level, the flip-flop is
set and the output goes high. If TRIG is above the trigger level and the threshold input (THRES) is above the
threshold level, the flip-flop is reset and the output is low. The reset input (RESET) can override all other inputs
and can be used to initiate a new timing cycle. If RESET is low, the flip-flop is reset and the output is low.
Whenever the output is low, a low-impedance path is provided between DISCH and GND. All unused inputs
should be tied to an appropriate logic level to prevent false triggering.

While the CMOS output is capable of sinking over 100 mA and sourcing over 10 mA, the TLC551 exhibits greatly
reduced supply-current spikes during output transitions. This minimizes the need for the large decoupling
capacitors required by the NE555.

The TLC551C is characterized for operation from 0°C to 70°C.

This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These
circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,
Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated
voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device
should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level,
preferably either supply voltage or ground. Specific guidelines for handling devices of this type are contained in the publication

Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies

LinCMOS is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

available from Texas Instruments.

Copyright  1997, Texas Instruments Incorporated

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1

TLC551, TLC551Y
LinCMOS TIMERS

SLFS044A – FEBRUARY 1984 – REVISED MAY 1997

V

T

A

0°C to 70°C 1 V to 16 V TLC551CD TLC551CDBLE TLC551CP TLC551CPWLE TLC551Y

The D package is available taped and reeled. Add the suffix R (e.g., TLC551CDR). The DB and PW packages are only
available left-end taped and reeled (indicated by the LE suffix on the device type; e.g., TLC551CDBLE). Chips are
tested at 25°C.

†

DD

RANGE

RESET

VOLTAGE

For conditions shown as MIN or MAX, use the appropriate value specified under
electrical characteristics.

†

<MIN Irrelevant Irrelevant Low On
>MAX <MIN Irrelevant High Off
>MAX >MAX >MAX Low On
>MAX >MAX <MIN As previously established

AVAILABLE OPTIONS

PACKAGED DEVICES

SMALL

OUTLINE

(D)

FUNCTION TABLE

TRIGGER

VOLTAGE

THRESHOLD

†

SSOP

(DB)

VOLTAGE

PLASTIC DIP

†

(P)

OUTPUT

TSSOP

(PW)

DISCHARGE

SWITCH

CHIP FORM

(Y)

TLC551Y chip information

This chip, when properly assembled, displays characteristics similar to the TLC551. Thermal compression or
ultrasonic bonding may be used on the doped aluminum bonding pads. Chips may be mounted with conductive
epoxy or a gold-silicon preform.

50

BONDING PAD ASSIGNMENTS

64

V

DD

(8)

R

THRES

(6)

R

(2)

TRIG

R

(1)

GND

RESET can override TRIG, which can override THRES.

CHIP THICKNESS: 15 TYPICAL
BONDING PADS: 4 × 4 MINIMUM
TJmax = 150°C
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN MILS.
PIN (1) IS INTERNALLY CONNECTED

TO BACKSIDE OF CHIP.

(5)

RESETCONT

(4)

R1

1

R
S

(7)

(3)

OUT

DISCH

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

• 3

equivalent schematic

CONT

THRES

COMPONENT COUNT

V

OUT

39

DD

Transistors
Resistors

5

TRIG RESET

SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997

DISCH

LinCMOS

TLC551, TLC551Y

TM

TIMERS

GND

TLC551, TLC551Y
LinCMOS TIMERS

SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, VDD (see Note 1) 18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI (any input) –0.3 to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Sink current, discharge or output 150 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Source current, output, I

15 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to network GND.

DISSIPATION RATING TABLE

PACKAGE

D

DB

P

PW

TA ≤ 25°C

POWER RATING

725 mW
525 mW

1000 mW

525 mW

DERATING FACTOR

ABOVE TA = 25°C

5.8 mW/°C

4.2 mW/°C

8.0 mW/°C

4.2 mW/°C

TA = 70°C

POWER RATING

464 mW
336 mW
640 mW
336 mW

recommended operating conditions

MIN MAX UNIT

Supply voltage, V
Operating free-air temperature range, T

DD

A

1 15 V
0 70 °C

†

DD

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

VITThreshold voltage

V

IITThreshold current

pA

V

Trigger voltage

V

I

Trigger current

pA

V

Reset voltage

V

I

Reset current

pA

Discharge switch on-stage voltage

I

100 µA

V

Discharge switch off-stage voltage

nA

VOHHigh-level output voltage

I

A

V

VOLLow-level output voltage

I

100 µA

V

IDDSupply current

See Note 2

A

TLC551, TLC551Y

LinCMOS TIMERS

SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997

electrical characteristics at specified free-air temperature, VDD = 1 V

PARAMETER TEST CONDITIONS T

I(TRIG)

I(TRIG)

I(RESET)

I(RESET)

Control voltage (open circuit) as a percentage of
supply voltage

=

OL

p

p

pp

†

Full range is 0°C to 70°C.

NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or to TRIG.

OH

OL

= –10 µ

=

†

A

25°C 0.475 0.67 0.85

Full range 0.45 0.875

25°C 10
70°C 75
25°C 0.15 0.33 0.425

Full range 0.1 0.45

25°C 10
70°C 75
25°C 0.4 0.7 1

Full range 0.3 1

25°C 10
70°C 75

70°C 66.7%
25°C 0.02 0.15

Full range 0.2

25°C 0.1
70°C 0.5
25°C 0.6 0.98

Full range 0.6

25°C 0.03 0.2

Full range 0.25

25°C 15 100

Full range 150

MIN TYP MAX UNIT

p

p

p

µ

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

TLC551, TLC551Y

VITThreshold voltage

V

IITThreshold current

pA

V

Trigger voltage

V

I

Trigger current

pA

V

Reset voltage

V

I

Reset current

pA

Discharge switch on-stage voltage

I

mA

V

Discharge switch off-stage voltage

nA

VOHHigh-level output voltage

I

300 µA

V

VOLLow-level output voltage

I

mA

V

IDDSupply current

See Note 2

A

LinCMOS TIMERS

SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997

electrical characteristics at specified free-air temperature, VDD = 2 V

PARAMETER TEST CONDITIONS T

I(TRIG)

I(TRIG)

I(RESET)

I(RESET)

Control voltage (open circuit) as a percentage of
supply voltage

= 1

OL

p

p

pp

†

Full range is 0°C to 70°C.

NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or to TRIG.

OH

OL

= –

= 1

†

A

25°C 0.95 1.33 1.65

Full range 0.85 1.75

25°C 10
70°C 75
25°C 0.4 0.67 0.95

Full range 0.3 1.05

25°C 10
70°C 75
25°C 0.4 1.1 1.5

Full range 0.3 1.8

25°C 10
70°C 75

70°C 66.7%
25°C 0.03 0.2

Full range 0.25

25°C 0.1
70°C 0.5
25°C 1.5 1.9

Full range 1.5

25°C 0.07 0.3

Full range 0.35

25°C 65 250

Full range 400

MIN TYP MAX UNIT

p

p

p

µ

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

VITThreshold voltage

V

IITThreshold current

pA

V

Trigger voltage

V

I

Trigger current

pA

V

Reset voltage

V

I

Reset current

pA

Discharge switch on-stage voltage

I

mA

V

Discharge switch off-stage voltage

nA

VOHHigh-level output voltage

I

mA

V

I

mA

VOLLow-level output voltage

I

mA

V

I

mA

IDDSupply current

See Note 2

A

TLC551, TLC551Y

LinCMOS TIMERS

SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997

electrical characteristics at specified free-air temperature, VDD = 5 V

PARAMETER TEST CONDITIONS T

I(TRIG)

I(TRIG)

I(RESET)

I(RESET)

Control voltage (open circuit) as a percentage of
supply voltage

= 10

OL

p

p

pp

†

Full range is 0°C to 70°C.

NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or to TRIG.

OH

OL

OL

OL

= –1

= 8

= 5

= 3.2

†

A

25°C 2.8 3.3 3.8

Full range 2.7 3.9

25°C 10
70°C 75
25°C 1.36 1.66 1.96

Full range 1.26 2.06

25°C 10
70°C 75
25°C 0.4 1.1 1.5

Full range 0.3 1.8

25°C 10
70°C 75

70°C 66.7%
25°C 0.14 0.5

Full range 0.6

25°C 0.1
70°C 0.5
25°C 4.1 4.8

Full range 4.1

25°C 0.21 0.4

Full range 0.5

25°C 0.13 0.3

Full range 0.4

25°C 0.08 0.3

Full range 0.35

25°C 170 350

Full range 500

MIN TYP MAX UNIT

p

p

p

µ

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7

TLC551, TLC551Y

VITThreshold voltage

V

IITThreshold current

pA

V

Trigger voltage

V

I

Trigger current

pA

V

Reset voltage

V

I

Reset current

pA

Discharge switch on-stage voltage

I

100 mA

V

Discharge switch off-stage voltage

nA

I

mA

VOHHigh-level output voltage

I

mA

V

I

mA

I

100 mA

VOLLow-level output voltage

I

mA

V

I

mA

IDDSupply current

See Note 2

A

DD

,

AB

,

R

C

pF

ns

LinCMOS TIMERS

SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997

electrical characteristics at specified free-air temperature, VDD = 15 V

PARAMETER TEST CONDITIONS T

I(TRIG)

I(TRIG)

I(RESET)

I(RESET)

Control voltage (open circuit) as a percentage of
supply voltage

=

OL

= –10

OH

p

p

pp

†

Full range is 0°C to 70°C.

NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or to TRIG.

OH

OH

OL

OL

OL

= –5

= –1

=

= 50

= 10

†

A

25°C 9.45 10.55

Full range 9.35 10.65

25°C 10
70°C 75
25°C 4.65 5 5.35

Full range 4.55 5.45

25°C 10
70°C 75
25°C 0.4 1.1 1.5

Full range 0.3 1.8

25°C 10
70°C 75

70°C 66.7%
25°C 0.77 1.7

Full range 1.8

25°C 0.1
70°C 0.5
25°C 12.5 14.2

Full range 12.5

25°C 13.5 14.6

Full range 13.5

25°C 14.2 14.9

Full range 14.2

25°C 1.28 3.2

Full range 3.6

25°C 0.63 1

Full range 1.3

25°C 0.12 0.3

Full range 0.4

25°C 360 600

Full range 800

MIN TYP MAX UNIT

p

p

p

µ

operating characteristics, VDD = 5 V, TA = 25°C (unless otherwise noted)

PARAMETER

Initial error of timing interval
Supply voltage sensitivity of timing interval

t

Rise time, output pulse

r

t

Fall time, output pulse

f

f

Maximum frequency in astable mode

max

‡

Timing interval error is defined as the difference between the measured value and the average value of a random sample from each process
run.

NOTE 3: RA, RB, and CT are as defined in Figure 3.

8

TEST CONDITIONS MIN TYP MAX UNIT

‡

V

= 5 V to 15 V, R

CT = 0.1 µF,

= 10 MΩ,

L

RA = 470 Ω,
CT = 200 pF

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

= R

See Note 3

RB = 200 Ω,
See Note 3

= 1 kΩ to 100 kΩ,

p

= 10

L

1% 3%

0.1 0.5 %/V
20 75
15 60

1.2 1.8 MHz

TLC551, TLC551Y

LinCMOS TIMERS

SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997

electrical characteristics at VDD = 5 V, TA = 25°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

IT

I

IT

V

I(TRIG)

I

I(TRIG)

V

I(RESET)

I

I(RESET)

V

OH

V

OL

I

DD

NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or to TRIG.

Threshold voltage 2.8 3.3 3.8 V
Threshold current 10 pA
Trigger voltage 1.36 1.66 1.96 V

Trigger current 10 pA
Reset voltage 0.4 1.1 1.5 V

Reset current 10 pA
Control voltage (open circuit) as a percentage of supply voltage 66.7%
Discharge switch on-state voltage IOL = 10 mA 0.14 0.5 V
Discharge switch off-state current 0.1 nA
High-level output voltage IOH = – 1 mA 4.1 4.8 V

IOL = 8 mA 0.21 0.4

Low-level output voltage

Supply current See Note 2 170 350 µA

IOL = 5 mA
IOL = 3.2 mA 0.08 0.3

0.13 0.3

V

TYPICAL CHARACTERISTICS

DISCHARGE SWITCH ON-STATE RESISTANCE

vs

FREE-AIR TEMPERATURE

100

70

Ω

40

20

10

7

4

2

Discharge Switch On-State Resistance –

1

025 75

VDD = 2 V, IO = 1 mA

VDD = 5 V, IO = 10 mA

VDD = 15 V, IO = 100 mA

50 100

TA – Free-Air Temperature – °C

PROPAGATION DELAY TIMES (TO DISCHARGE

OUTPUT FROM TRIGGER AND THRESHOLD

SHORTED TOGETHER)

vs

SUPPLY VOLTAGE

600

I

≥ 1 mA

O(on)

500

400

300

200

PLH

t – Propagation Delay Times – ns

100

PHL

t,

0

0 2 4 6 8 12 16

VDD – Supply Voltage – V

‡

The effects of the load resistance on these values must be
taken into account separately.

10 14

CL ≈ 0
TA = 25°C

t

PHL

t

PLH

‡

2018

Figure 1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Figure 2

9

TLC551, TLC551Y
LinCMOS TIMERS

SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997

APPLICATION INFORMATION

V

DD

0.1 µF

R

A

R

B

0.1 µF

CONT

4

RESET

7

6
2

C

T

TLC551

DISCH

THRES
TRIG

GND

1

CIRCUIT TRIGGER AND THRESHOLD VOLTAGE WAVEFORM

V

DD

OUT

85

R

L

Output

3

C

L

2/3 V

1/3 V

V

DD

DD

DD

GND

t

PHL

t

c(H)

t

PLH

t

c(L)

Figure 3. Astable Operation

Connecting TRIG to THRES, as shown in Figure 3, causes the timer to run as a multivibrator. The capacitor C
charges through RA and RB to the threshold voltage level (approximately 0.67 VDD) and then discharges through R
only to the value of the trigger voltage level (approximately 0.33 VDD). The output is high during the charging cycle
(t

) and low during the discharge cycle (t

c(H)

). The duty cycle is controlled by the values of RA, and RB, and CT, as

c(L)

shown in the equations below.

t

[

c(H)

t

c(L)

Period+t

CT(RA)

[

CTRBIn 2

c(H)

Output driver duty cycle

Output waveform duty cycle

RB)In2 (In2+0.693)

)

t

[

c(L)

CT(RA)

+

t

c(H)

+

t

c(L)

t

c(H)

)

2RB)In2

t

c(L)

t

c(H)

)

t

c(L)

[

1–

[

RA)

R

RA)

R

B

2R

B

B

2R

B

T
B

The 0.1-µF capacitor at CONT in Figure 3 decreases the period by about 10%.
The formulas shown above do not allow for any propagation delay times from TRIG and THRES to DISCH. These

delay times add directly to the period and create differences between calculated and actual values that increase with
frequency . In addition, the internal on-state resistance ron during discharge adds to RB to provide another source of
timing error in the calculation when R

10

is very low or ron is very high.

B

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC551, TLC551Y

LinCMOS TIMERS

SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997

APPLICATION INFORMATION

The equations below provide better agreement with measured values.

–t

t

+

c(H)

t

c(L)

These equations and those given earlier are similar in that a time constant is multiplied by the logarithm of a number
or function. The limit values of the logarithmic terms must be between In 2 at low frequencies and In 3 at extremely
high frequencies. For a duty cycle close to 50%, an appropriate constant for the logarithmic terms can be substituted

with good results. Duty cycles less than 50%

conditions can be difficult to obtain.
In monostable applications, the trip point of the trigger input can be set by a voltage applied to CONT . An input voltage

between 10% and 80% of the supply voltage from a resistor divider with at least 500-µA bias provides good results.

CT(RA)

+

CT(RB)

RB)Inƪ3–exp

ron)In

3–exp

ƪ

t

c(H)

ǒ

CT(RB)

ǒ

CT(RA)

t

c(H)

)

PLH

–t

PHL

require that

t

c(L)

ron)

RB)

Ǔ

)

t

ƫ

PHL

Ǔ

)

t

ƫ

PLH

t

c(H)

<1 and possibly RA ≤ ron. These

t

c(L)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

11

TLC551, TLC551Y
LinCMOS TIMERS

SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997

MECHANICAL INFORMATION

D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PIN SHOWN

14

1

0.069 (1,75) MAX

0.050 (1,27)

A

0.020 (0,51)

0.014 (0,35)

0.010 (0,25)

0.004 (0,10)

8

7

0.010 (0,25)

0.157 (4,00)

0.150 (3,81)

M

0.244 (6,20)

0.228 (5,80)

Seating Plane

0.004 (0,10)

PINS **

DIM

A MAX

A MIN

0.008 (0,20) NOM

Gage Plane

0°–8°

8

0.197

(5,00)

0.189

(4,80)

14

0.344

(8,75)

0.337

(8,55)

0.010 (0,25)

0.044 (1,12)

0.016 (0,40)

4040047/D 10/96

16

0.394

(10,00)

0.386

(9,80)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012

12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC551, TLC551Y

LinCMOS TIMERS

SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997

MECHANICAL INFORMATION

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

28 PIN SHOWN

0,65

28

1

2,00 MAX

0,38
0,22

15

14

A

0,05 MIN

0,15

M

5,60
5,00

Seating Plane

8,20
7,40

0,10

0,15 NOM

Gage Plane

0°–8°

0,25

1,03
0,63

PINS **

DIM

A MAX

A MIN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150

8

3,30

2,70

14

6,50

6,50

5,905,90

2016

7,50

6,90

24

8,50

28

10,50

9,907,90

30

10,50

9,90

38

12,90

12,30

4040065 /C 10/95

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

13

TLC551, TLC551Y
LinCMOS TIMERS

SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997

MECHANICAL INFORMATION

P (R-PDIP-T8) PLASTIC DUAL-IN-LINE PACKAGE

0.400 (10,60)

0.355 (9,02)

58

0.260 (6,60)

0.240 (6,10)

41

0.070 (1,78) MAX

0.020 (0,51) MIN

0.200 (5,08) MAX

0.125 (3,18) MIN

0.100 (2,54)

0.021 (0,53)

0.015 (0,38)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001

0.010 (0,25)

M

0.310 (7,87)

0.290 (7,37)

Seating Plane

0°–15°

0.010 (0,25) NOM

4040082/B 03/95

14

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC551, TLC551Y

LinCMOS TIMERS

SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997

MECHANICAL INFORMATION

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PIN SHOWN

0,65

14

1

1,20 MAX

A

7

0,05 MIN

0,30
0,19

8

6,60

4,50
4,30

6,20

M

0,10

Seating Plane

0,10

0,15 NOM

Gage Plane

0,25

0°–8°

0,75
0,50

PINS **

DIM

A MAX

A MIN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153

8

3,10

2,90

14

5,10

4,90

16

5,10

20

6,60

6,404,90

24

7,90

7,70

28

9,80

9,60

4040064/E 08/96

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

15

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