Texas Instruments TL16C550AN, TL16C550AFN, TL16C550AFNR Datasheet

TL16C550A

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Capable of Running With All Existing TL16C450 Software

After Reset, All Registers Are Identical to the TL16C450 Register Set

In the FIFO Mode, Transmitter and Receiver Are Each Buffered With 16-Byte FIFOs to Reduce the Number of Interrupts to the CPU

In the TL16C450 Mode, Holding and Shift Registers Eliminate the Need for Precise

Synchronization Between the CPU and Serial Data

Programmable Baud Rate Generator Allows Division of Any Input Reference Clock by 1 to (2

–1) and Generates an Internal 16×

Clock

Standard Asynchronous Communication Bits (Start, Stop, and Parity) Added to or Deleted From the Serial Data Stream

Independent Receiver Clock Input

Transmit, Receive, Line Status, and Data Set Interrupts Independently Controlled

Fully Programmable Serial Interface Characteristics: – 5-, 6-, 7-, or 8-Bit Characters – Even-, Odd-, or No-Parity Bit Generation

and Detection – 1-, 1 1/2-, or 2-Stop Bit Generation – Baud Generation (dc to 256 Kbit/s)

False-Start Bit Detection

Complete Status Reporting Capabilities

3-State TTL Drive Capabilities for Bidirectional Data Bus and Control Bus

Line Break Generation and Detection

Internal Diagnostic Capabilities: – Loopback Controls for Communications

Link Fault Isolation – Break, Parity , Overrun, Framing Error

Simulation

Fully Prioritized Interrupt System Controls

Modem Control Functions (CTS, RTS, DSR, DTR, RI, and DCD)

Faster Plug-In Replacement for National Semiconductor NS16550A

description

The TL16C550A is a functional upgrade of the TL16C450 asynchronous communications element (ACE). Functionally identical to the TL16C450 on power up (character mode

†

), the TL16C550A can be placed in an

alternate mode (FIFO) to relieve the CPU of excessive software overhead. In this mode, internal FIFOs are activated allowing 16 bytes (plus 3 bits of error data per byte in the receiver

FIFO) to be stored in both receive and transmit modes. To minimize system overhead and maximize system efficiency , all logic is on the chip. Two of the TL16C450 terminal functions (terminals 24 and 29 on the N package and terminals 27 and 32 on the FN package) have been changed to allow signalling of direct memory address (DMA) transfers.

The TL16C550A performs serial-to-parallel conversion on data received from a peripheral device or modem and parallel-to-serial conversion on data received from its CPU. The CPU can read and report on the status of the ACE at any point in the ACE’s operation. Reported status information includes the type of transfer operation in progress, the status of the operation, and any error conditions encountered.

The TL16C550A ACE includes a programmable, on-board, baud rate generator. This generator is capable of dividing a reference clock input by divisors from 1 to (2

–1) and producing a 16× clock for driving the internal transmitter logic. Provisions are included to use this 16× clock to drive the receiver logic. Also included in the ACE is a complete modem control capability and a processor interrupt system that may be software tailored to the user’s requirements to minimize the computing required to handle the communications link.

†

The TL16C550A can also be reset to the TL16C450 mode under software control.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

TL16C550A ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D0 D1 D2 D3 D4 D5 D6 D7

RCLK

SIN

SOUT

CS0 CS1 CS2

BAUDOUT

XIN

XOUT

WR1 WR2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

RI DCD DSR CTS MR OUT1 DTR RTS OUT2 INTRPT RXRDY A0 A1 A2 ADS TXRDY DDIS RD2 RD1

N PACKAGE

(TOP VIEW)

MR OUT1 DTR RTS OUT2 NC INTRPT RXRDY A0 A1 AS

39 38 37 36 35 34 33 32 31 30 29

1819

7 8 9 10 11 12 13 14 15 16 17

D5 D6 D7

RCLK

SIN

SOUT

CS0 CS1 CS2

BAUDOUT

20 21 22 23

FN PACKAGE

(TOP VIEW)

DCD

DSR

CTS

54 321644

D4D3D2D1D0NCV

RD2

DDIS

TXRDY

ADS

XIN

XOUT

WR1

WR2

RD1

42 41 4043

24 25 26 27 28

NC–No internal connection

TL16C550A

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

block diagram

Receiver

Buffer

Divisor

Latch (LS)

Divisor

Latch (MS)

Baud

Generator

Receiver

FIFO

Line

Status

Transmitter

Holding

Modem

Control

Modem

Status

Receiver

Buffer

Line

Control

Receiver

Timing and

Control

Line

Control

Transmitter

FIFO

S e

l e c

Line

Control

Modem Control

Logic

Interrupt

Enable

Interrupt

I/O

FIFO

Control

Select

and

Control

Logic

Power Supply

Interrupt

Control

Logic

S e

l e c

Line

Control

BAUDOUT

SIN

RCLK

SOUT

RTS CTS DTR DSR DCD RI OUT1 OUT2

INTRPT

32 36 33 37 38 39 34 31

CS0 CS1 CS2

ADS

MR RD1 RD2

WR1

12 13 14 25 35 21 22 18

WR2

DDIS

TXRDY

XIN

XOUT

RXRDY

19 23 24 16 17 29

A0 A1 A2

28 27 26

D7–D0

8–1

Internal

Data Bus

40 20

NOTE A: Terminal numbers shown are for the N package.

TL16C550A ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NAME NO.

†

I/O

DESCRIPTION

A0 A1 A2

28 [31] 27 [30] 26 [29]

I Register select. A0, A1, and A2 are used during read and write operations to select the ACE register to read from

or write to. Refer to Table 1 for register addresses, also refer to the address strobe (ADS

) signal description.

ADS

25 [28] I

Address strobe. When ADS is active (low), the register select signals (A0, A1, and A2) and chip select signals (CS0, CS1, CS2

) drive the internal select logic directly; when high, the register select and chip select signals are held in

the state they were in when the low-to-high transition of ADS

occurred.

BAUDOUT

15 [17] O

Baud out. BAUDOUT is a 16× clock signal for the transmitter section of the ACE. The clock rate is established by the reference oscillator frequency divided by a divisor specified by the baud generator divisor latches. BAUDOUT may also be used for the receiver section by tying this output to the RCLK input.

CS0 CS1 CS2

12 [14] 13 [15] 14 [16]

Chip select. When CSx is active (high, high, and low respectively), the ACE is selected. If any of these inputs are inactive, the ACE remains inactive. Refer to the ADS

(address strobe) signal description.

CTS

36 [40] I

Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of the modem status register. Bit 0 (DCTS) of the modem status register indicates that this signal has changed states since the last read from the modem status register. If the modem status interrupt is enabled when CTS

changes state, an

interrupt is generated.

D0 – D7 1 – 8

[2 – 9]

I/O Data bus. Eight 3-state data lines provide a bidirectional path for data, control, and status information between the

ACE and the CPU.

DCD

38 [42] I

Data carrier detect. DCD is a modem status signal. Its condition can be checked by reading bit 7 (DCD) of the modem status register. Bit 3 (DDCD) of the modem status register indicates that this signal has changed states since the last read from the modem status register. If the modem status interrupt is enabled when the DCD

changes

state, an interrupt is generated.

DDIS 23 [26] O Driver disable. This output is active (high) when the CPU is not reading data. When active, this output can disable

an external transceiver.

DSR

37 [41] I

Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of the modem status register. Bit 1 (DDSR) of the modem status register indicates that this signal has changed states since the last read from the modem status register. If the modem status interrupt is enabled when the DSR

changes state,

an interrupt is generated.

DTR

33 [37] O

Data terminal ready. When active (low), DTR informs a modem or data set that the ACE is ready to establish communication. DTR

is placed in the active state by setting the DTR bit of the modem control register to a high level.

DTR

is placed in the inactive state either as a result of a master reset or during loop mode operation or clearing

bit 0 (DTR) of the modem control register.

INTRPT 30 [33] O Interrupt. When active (high), INTRPT informs the CPU that the ACE has an interrupt to be serviced. Four

conditions that cause an interrupt to be issued are: a receiver error, received data is available or timeout (FIFO mode only), transmitter holding register empty, or an enabled modem status interrupt. The INTRPT output is reset (deactivated) either when the interrupt is serviced or as a result of a master reset.

MR 35 [39] I Master reset. When active (high), MR clears most ACE registers and sets the state of various output signals. Refer

to Table 2.

OUT1 OUT2

34 [38] 31 [35]

Outputs 1 and 2. OUT1 and OUT2 are user-designated output terminals that are set to their active states by setting their respective modem control register bits (OUT1 and OUT2) high. OUT1

and OUT2 are set to their inactive (high) states as a result of master reset or during loop mode operations or by clearing bit 2 (OUT1) or bit 3 (OUT2) of the modem control register.

RCLK 9 [10] I Receiver clock. RCLK is the 16× baud rate clock for the receiver section of the ACE. RD1

RD2

21 [24] 22 [25]

Read inputs. When either RD1 or RD2 are active (high or low respectively) while the ACE is selected, the CPU is allowed to read status information or data from a selected ACE register. Only one of these inputs is required for the transfer of data during a read operation; the other input should be tied in its inactive state (i.e., RD2 tied low or RD1

tied high).

†

Terminal numbers shown in brackets are for the FN package.

TL16C550A

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions (continued)

TERMINAL

NAME NO.

†

I/O

DESCRIPTION

39 [43] I Ring indicator . RI is a modem status signal. Its condition can be checked by reading bit 6 (RI) of the modem status

input has transitioned from a low to a high state since the last read from the modem status register. If the modem status interrupt is enabled when this transition occurs, an interrupt is generated.

RTS

32 [36] O

Request to send. When active, RTS informs the modem or data set that the ACE is ready to transmit data. RTS is set to its active state by setting the RTS modem control register bit, and is set to its inactive (high) state either as a result of a master reset or during loop mode operations or by clearing bit 1 (RTS) of the modem control register .

RXRDY

29 [32] O

Receiver ready output. Receiver direct memory access (DMA) signalling is available with RXRDY . When operating in the FIFO mode, one of two types of DMA signalling can be selected with FCR3. When operating in the TL16C450 mode, only DMA mode 0 is allowed. Mode 0 supports single-transfer DMA in which a transfer is made between CPU bus cycles. Mode 1 supports multitransfer DMA in which multiple transfers are made continuously until the receiver FIFO has been emptied. In DMA mode 0 (FCR0 = 0 or FCR0 = 1, FCR3 = 0), if there is at least 1 character in the receiver FIFO or receiver holding register, RXRDY

is active (low). When RXRDY has been active but there

are no characters in the FIFO or holding register, RXRDY

goes inactive (high). In DMA mode 1 (FCR0 = 1, FCR3

= 1), when the trigger level or the timeout has been reached, RXRDY

goes active (low); when it has been active

but there are no more characters in the FIFO or holding register, it goes inactive (high).

SIN 10 [11] I Serial input. SIN is a serial data input from a connected communications device. SOUT 11 [13] O Serial output. SOUT is a composite serial data output to a connected communication device. SOUT is set to the

marking (high) state as a result of master reset.

TXRDY

24 [27] O

Transmitter ready output. T ransmitter DMA signalling is available with TXRDY . When operating in the FIFO mode, one of two types of DMA signalling can be selected with FCR3. When operating in the TL16C450 mode, only DMA mode 0 is allowed. Mode 0 supports single-transfer DMA in which a transfer is made between CPU bus cycles. Mode 1 supports multitransfer DMA in which multiple transfers are made continuously until the transmit FIFO has been filled.

40 [44] 5-V supply voltage

20 [22] Supply common

WR1 WR2

18 [20] 19 [21]

Write inputs. When either WR1 or WR2 are active (high or low respectively) while the ACE is selected, the CPU is allowed to write control words or data into a selected ACE register. Only one of these inputs is required to transfer data during a write operation; the other input should be tied in its inactive state (i.e., WR2 tied low or WR1

tied high).

XIN XOUT

16 [18] 17 [19]

I/O External clock. XIN and XOUT connect the ACE to the main timing reference (clock or crystal).

†

Terminal numbers shown in brackets are for the FN package.

TL16C550A ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over free-air temperature range (unless otherwise noted)

†

Supply voltage range, V

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range at any input, V

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, V

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T

0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Case temperature for 10 seconds, T

: FN package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package 260°C. . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to VSS.

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage, V

4.75 5 5.25 V

High-level input voltage, V

2 V

Low-level input voltage, V

–0.5 0.8 V

Operating free-air temperature, T

0 70 °C

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

‡

High-level output voltage IOH = –1 mA 2.4 V

‡

Low-level output voltage IOL = 1.6 mA 0.4 V

VCC = 5.25 V , VSS = 0,

In ut leakage current

VI = 0 to 5.25 V,

All other terminals floating

±10

µA

= 5.25 V,

IOZHigh-im edance out ut current

= 0 to 5.25 V,

±20

µA

Chi

p selected in write mode or chip deselecte

= 5.25 V,

25 C

SIN, DSR, DCD, CTS

, and RI at 2 V,

ICCSu ly current

,,,, ,

All other in uts at 0.8 V,XTAL1 at 4 MHz

No load

on outputs,

Baud

rate = 50

kbit/

XIN

Clock input capacitance

15 20 pF

XOUT

Clock output capacitance

VCC = 0, VSS = 0,

20 30 pF

Input capacitance

All other terminals grounded

f = 1 MHz

= 25°

6 10 pF

Output capacitance

f = 1 MHz

25 C

10 20 pF

†

All typical values are at VCC = 5 V, TA = 25°C.

‡

These parameters apply for all outputs except XOUT.

TL16C550A

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

system timing requirements over recommended ranges of supply voltage and operating free-air temperature

ALT. SYMBOL FIGURE MIN MAX UNIT

Cycle time, read (tw7 + td8 + td9) RC 175 ns

Cycle time, write (tw6 + td5 + td6) WC 175 ns

Pulse duration, ADS low

ADS

2, 3 15 ns

Pulse duration, write strobe t

2 80 ns

Pulse duration, read strobe tRD 3 80 ns

Pulse duration, master reset t

1 µs

su1

Setup time, address valid before ADS↑ t

2, 3 15 ns

su2

Setup time, CS before ADS↑ t

2, 3 15 ns

su3

Setup time, data valid before WR1↓ or WR2↑ t

2 15 ns

Hold time, address low after ADS↑ t

2, 3 0 ns

Hold time, CS valid after ADS↑ t

2, 3 0 ns

Hold time, CS valid after WR1↑ or WR2↓ t

WCS

2 20 ns

Hold time, address valid after WR1↑ or WR2↓ t

2 20 ns

Hold time, data valid after WR1↑ or WR2↓ t

2 15 ns

Hold time, CS valid after RD1↑orRD2↓

RCS

3 20 ns

Hold time, address valid after RD1↑ or RD2↓ t

3 20 ns

Delay time, CS valid before WR1↓ or WR2↑ t

CSW

2 15 ns

Delay time, address valid before WR1↓ or WR2↑ t

2 15 ns

Delay time, write cycle, WR1↑ or WR2↓ to ADS↓ t

2 80 ns

Delay time, CS valid to RD1↓

or RD2

↑

CSR

3 15 ns

Delay time, address valid to RD1↓ or RD2↑ t

3 15 ns

Delay time, read cycle, RD1↑ or RD2↓ to ADS↓ tRC 3 80 ns

Applicable only when ADS is tied low.

system switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see Note 2)

PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT

Pulse duration, clock high t

1 f = 9 MHz maximum 50 ns

Pulse duration, clock low t

1 f = 9 MHz maximum 50 ns

d10

Delay time, RD1↓ or RD2↑ to data valid t

RVD

3 CL = 100 pF 60 ns

d11

Delay time, RD1↑ or RD2↓ to floating data t

3 CL = 100 pF 0 60 ns

dis(R)

Disable time, RD1↓↑ or RD2↑↓ to DDIS↑↓ t

RDD

3 CL = 100 pF 60 ns

NOTE 2: Charge and discharge time is determined by VOL, VOH, and external loading.

baud generator switching characteristics over recommended ranges of supply voltage and operating free-air temperature

PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT

Pulse duration, BAUDOUT low t

f = 9 MHz, CLK ÷ 2,

CL = 100 pF

80 ns

Pulse duration, BAUDOUT high t

f = 9 MHz, CLK ÷ 2,

CL = 100 pF

100 ns

Delay time, XIN↑ to BAUDOUT↑ t

BLD

1 CL = 100 pF 125 ns

Delay time, XIN↑↓ to BAUDOUT↓ t

BHD

1 CL = 100 pF 125 ns

TL16C550A ASYNCHRONOUS COMMUNICATIONS ELEMENT

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receiver switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see Note 3)

PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT

d12

Delay time, RCLK to sample clock t

SCD

4 100 ns

d13

Delay time, stop to set RCV error interrupt or read RBR to LSI interrupt or stop to RXRDY

↓

SINT

4,5,6,7,8 1

RCLK cycles

d14

Delay time, read RBR/LSR to reset interrupt t

RINT

4,5,6,7,8 CL = 100 pF 150 ns

NOTE 3: In FIFO mode RC = 425 ns (minimum) between reads of the receiver FIFO and the status registers (interrupt identification register or

line status register).

transmitter switching characteristics over recommended ranges of supply voltage and operating free-air temperature

PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT

d15

Delay time, INTRPT to transmit start t

IRS

9 8 24

baudout

cycles

d16

Delay time, start to interrupt t

STI

9 8 8

baudout

cycles

d17

Delay time, WR THR to reset interrupt t

9 CL = 100 pF 140 ns

d18

Delay time, initial write to interrupt (THRE) t

9 16 32

baudout

cycles

d19

Delay time, read IIR to reset interrupt (THRE) t

9 CL = 100 pF 140 ns

d20

Delay time, write to TXRDY inactive t

WXI

10,11 CL = 100 pF 195 ns

d21

Delay time, start to TXRDY active t

SXA

10,11 CL = 100 pF 8

baudout

cycles

modem control switching characteristics over recommended ranges of supply voltage and operating free-air temperature

PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT

d22

Delay time, WR MCR to output t

MDO

12 CL = 100 pF 100 ns

d23

Delay time, modem interrupt to set interrupt t

SIM

12 CL = 100 pF 170 ns

d24

Delay time, RD MSR to reset interrupt t

RIM

12 CL = 100 pF 140 ns

TL16C550A

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

XIN or RCLK

(9 MHz Max)

BAUDOUT

(1/1)

XIN

BAUDOUT

(1/2)

BAUDOUT

(1/3)

BAUDOUT

(1/N)

(N > 3)

2 XIN Cycles

(N-2) XIN Cycles

2.4 V

0.4 V

0.8 V

2 V

Figure 1. Baud Generator Timing Waveforms

TL16C550A ASYNCHRONOUS COMMUNICATIONS ELEMENT

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

ADS

su1

su2

su3

†

Valid Data

Valid Valid

†

Valid Valid

†

Active

A0–A2

CS0, CS1, CS2

WR1, WR2

D7–D0

50%50%

50%

50%50%

50% 50%

50%

†

Applicable only when ADS is tied low.

Figure 2. Write Cycle Timing Waveforms

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