TEXAS INSTRUMENTS TL16C550A Technical data

查询TL16C550供应商

Capable of Running With All Existing TL16C450 Software

After Reset, All Registers Are Identical to the TL16C450 Register Set

In the FIFO Mode, Transmitter and Receiver Are Each Buffered With 16-Byte FIFOs to Reduce the Number of Interrupts to the CPU

In the TL16C450 Mode, Holding and Shift Registers Eliminate the Need for Precise

Synchronization Between the CPU and Serial Data

Programmable Baud Rate Generator Allows Division of Any Input Reference Clock by 1

to (2 Clock

Standard Asynchronous Communication Bits (Start, Stop, and Parity) Added to or Deleted From the Serial Data Stream

Independent Receiver Clock Input

Transmit, Receive, Line Status, and Data Set Interrupts Independently Controlled

description

–1) and Generates an Internal 16×

TL16C550A

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

Fully Programmable Serial Interface Characteristics:

– 5-, 6-, 7-, or 8-Bit Characters – Even-, Odd-, or No-Parity Bit Generation

and Detection – 1-, 1 1/2-, or 2-Stop Bit Generation – Baud Generation (dc to 256 Kbit/s)

False-Start Bit Detection

Complete Status Reporting Capabilities

3-State TTL Drive Capabilities for Bidirectional Data Bus and Control Bus

Line Break Generation and Detection

Internal Diagnostic Capabilities: – Loopback Controls for Communications

Link Fault Isolation – Break, Parity, Overrun, Framing Error

Simulation

Fully Prioritized Interrupt System Controls

Modem Control Functions (CTS, RTS, DSR, DTR, RI, and DCD)

Faster Plug-In Replacement for National Semiconductor NS16550A

The TL16C550A is a functional upgrade of the TL16C450 asynchronous communications element (ACE). Functionally identical to the TL16C450 on power up (character mode alternate mode (FIFO) to relieve the CPU of excessive software overhead.

In this mode, internal FIFOs are activated allowing 16 bytes (plus 3 bits of error data per byte in the receiver FIFO) to be stored in both receive and transmit modes. To minimize system overhead and maximize system efficiency , all logic is on the chip. Two of the TL16C450 terminal functions (terminals 24 and 29 on the N package and terminals 27 and 32 on the FN package) have been changed to allow signalling of direct memory address (DMA) transfers.

The TL16C550A performs serial-to-parallel conversion on data received from a peripheral device or modem and parallel-to-serial conversion on data received from its CPU. The CPU can read and report on the status of the ACE at any point in the ACE’s operation. Reported status information includes the type of transfer operation in progress, the status of the operation, and any error conditions encountered.

The TL16C550A ACE includes a programmable, on-board, baud rate generator. This generator is capable of dividing a reference clock input by divisors from 1 to (2 transmitter logic. Provisions are included to use this 16× clock to drive the receiver logic. Also included in the ACE is a complete modem control capability and a processor interrupt system that may be software tailored to the user’s requirements to minimize the computing required to handle the communications link.

†

The TL16C550A can also be reset to the TL16C450 mode under software control.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

–1) and producing a 16× clock for driving the internal

†

), the TL16C550A can be placed in an

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C550A ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

D0 D1 D2 D3 D4 D5 D6 D7

RCLK

SIN

SOUT

CS0 CS1 CS2

BAUDOUT

XIN

XOUT

WR1 WR2

N PACKAGE

(TOP VIEW)

RI DCD DSR CTS MR OUT1 DTR RTS OUT2 INTRPT RXRDY A0 A1 A2 ADS TXRDY DDIS RD2 RD1

D4D3D2D1D0NCV

D5 D6 D7

RCLK

SIN

SOUT

CS0 CS1 CS2

BAUDOUT

54 321644

7 8 9 10 11 12 13 14 15 16 17

1819

XIN

XOUT

NC–No internal connection

FN PACKAGE

(TOP VIEW)

20 21 22 23

WR1

WR2

DCD

42 41 4043

24 25 26 27 28

RD2

RD1

DDIS

DSR

CTS

OUT1

DTR

RTS

OUT2

INTRPT

33 32

RXRDY

ADS

TXRDY

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

block diagram

Data Bus

Internal

TL16C550A

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

S e

l e c

Receiver

FIFO

D7–D0

A0 A1 A2

CS0 CS1 CS2

ADS

MR RD1 RD2

WR1 WR2

DDIS

TXRDY

XIN

XOUT

RXRDY

8–1

28 27 26

12 13 14 25 35 21 22 18 19 23 24 16 17 29

40 20

Line

Control

Select

and

Control

Logic

Power Supply

Receiver

Buffer

Line

Control

Divisor

Latch (LS)

Divisor

Latch (MS)

Line

Status

Transmitter

Holding

Modem Control

Modem

Status

Interrupt

Enable

Baud

Generator

Transmitter

FIFO

Interrupt

Control

Logic

Receiver

Buffer

Receiver

Timing and

Control

Line

Control

S e

l e c

Line

Control

Modem Control

Logic

SIN

RCLK

BAUDOUT

SOUT

RTS

CTS

DTR

DSR

DCD

OUT1

OUT2

INTRPT

Interrupt

I/O

FIFO

Control

NOTE A: Terminal numbers shown are for the N package.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C550A

I/O

DESCRIPTION

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

Terminal Functions

TERMINAL

NAME NO.

A0 A1 A2

ADS

BAUDOUT

CS0 CS1 CS2

CTS

D0 – D7 1 – 8

DCD

DDIS 23 [26] O Driver disable. This output is active (high) when the CPU is not reading data. When active, this output can disable

DSR

DTR

INTRPT 30 [33] O Interrupt. When active (high), INTRPT informs the CPU that the ACE has an interrupt to be serviced. Four

MR 35 [39] I Master reset. When active (high), MR clears most ACE registers and sets the state of various output signals. Refer

OUT1 OUT2

RCLK 9 [10] I Receiver clock. RCLK is the 16× baud rate clock for the receiver section of the ACE. RD1

RD2

†

Terminal numbers shown in brackets are for the FN package.

†

28 [31] 27 [30] 26 [29]

25 [28] I

15 [17] O

12 [14] 13 [15] 14 [16]

36 [40] I

I/O Data bus. Eight 3-state data lines provide a bidirectional path for data, control, and status information between the

[2 – 9]

38 [42] I

37 [41] I

33 [37] O

34 [38] 31 [35]

21 [24] 22 [25]

I Register select. A0, A1, and A2 are used during read and write operations to select the ACE register to read from

or write to. Refer to Table 1 for register addresses, also refer to the address strobe (ADS

Address strobe. When ADS is active (low), the register select signals (A0, A1, and A2) and chip select signals (CS0, CS1, CS2 the state they were in when the low-to-high transition of ADS

Baud out. BAUDOUT is a 16× clock signal for the transmitter section of the ACE. The clock rate is established by the reference oscillator frequency divided by a divisor specified by the baud generator divisor latches. BAUDOUT may also be used for the receiver section by tying this output to the RCLK input.

Chip select. When CSx is active (high, high, and low respectively), the ACE is selected. If any of these inputs are inactive, the ACE remains inactive. Refer to the ADS

Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of the modem status register. Bit 0 (DCTS) of the modem status register indicates that this signal has changed states since the last read from the modem status register. If the modem status interrupt is enabled when CTS interrupt is generated.

ACE and the CPU. Data carrier detect. DCD is a modem status signal. Its condition can be checked by reading bit 7 (DCD) of the

modem status register. Bit 3 (DDCD) of the modem status register indicates that this signal has changed states since the last read from the modem status register. If the modem status interrupt is enabled when the DCD state, an interrupt is generated.

an external transceiver. Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of the modem

status register. Bit 1 (DDSR) of the modem status register indicates that this signal has changed states since the last read from the modem status register. If the modem status interrupt is enabled when the DSR an interrupt is generated.

Data terminal ready. When active (low), DTR informs a modem or data set that the ACE is ready to establish communication. DTR DTR bit 0 (DTR) of the modem control register.

conditions that cause an interrupt to be issued are: a receiver error, received data is available or timeout (FIFO mode only), transmitter holding register empty, or an enabled modem status interrupt. The INTRPT output is reset (deactivated) either when the interrupt is serviced or as a result of a master reset.

to Table 2.

Outputs 1 and 2. OUT1 and OUT2 are user-designated output terminals that are set to their active states by setting their respective modem control register bits (OUT1 and OUT2) high. OUT1 states as a result of master reset or during loop mode operations or by clearing bit 2 (OUT1) or bit 3 (OUT2) of the modem control register.

Read inputs. When either RD1 or RD2 are active (high or low respectively) while the ACE is selected, the CPU is allowed to read status information or data from a selected ACE register. Only one of these inputs is required for the transfer of data during a read operation; the other input should be tied in its inactive state (i.e., RD2 tied low or RD1

) drive the internal select logic directly; when high, the register select and chip select signals are held in

occurred.

(address strobe) signal description.

is placed in the active state by setting the DTR bit of the modem control register to a high level.

is placed in the inactive state either as a result of a master reset or during loop mode operation or clearing

and OUT2 are set to their inactive (high)

tied high).

) signal description.

changes state, an

changes

changes state,

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C550A

I/O

DESCRIPTION

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

Terminal Functions (continued)

TERMINAL

NAME NO.

RTS

RXRDY

SIN 10 [11] I Serial input. SIN is a serial data input from a connected communications device. SOUT 11 [13] O Serial output. SOUT is a composite serial data output to a connected communication device. SOUT is set to the

TXRDY

SS WR1 WR2

XIN XOUT

†

Terminal numbers shown in brackets are for the FN package.

†

39 [43] I Ring indicator . RI is a modem status signal. Its condition can be checked by reading bit 6 (RI) of the modem status

register. Bit 2 (TERI) of the modem status register indicates that the RI state since the last read from the modem status register. If the modem status interrupt is enabled when this transition occurs, an interrupt is generated.

32 [36] O

29 [32] O

24 [27] O

40 [44] 5-V supply voltage 20 [22] Supply common 18 [20]

19 [21]

16 [18] 17 [19]

Request to send. When active, RTS informs the modem or data set that the ACE is ready to transmit data. RTS is set to its active state by setting the RTS modem control register bit, and is set to its inactive (high) state either as a result of a master reset or during loop mode operations or by clearing bit 1 (RTS) of the modem control register .

Receiver ready output. Receiver direct memory access (DMA) signalling is available with RXRDY . When operating in the FIFO mode, one of two types of DMA signalling can be selected with FCR3. When operating in the TL16C450 mode, only DMA mode 0 is allowed. Mode 0 supports single-transfer DMA in which a transfer is made between CPU bus cycles. Mode 1 supports multitransfer DMA in which multiple transfers are made continuously until the receiver FIFO has been emptied. In DMA mode 0 (FCR0 = 0 or FCR0 = 1, FCR3 = 0), if there is at least 1 character in the receiver FIFO or receiver holding register, RXRDY are no characters in the FIFO or holding register, RXRDY = 1), when the trigger level or the timeout has been reached, RXRDY but there are no more characters in the FIFO or holding register, it goes inactive (high).

marking (high) state as a result of master reset. Transmitter ready output. T ransmitter DMA signalling is available with TXRDY . When operating in the FIFO mode,

one of two types of DMA signalling can be selected with FCR3. When operating in the TL16C450 mode, only DMA mode 0 is allowed. Mode 0 supports single-transfer DMA in which a transfer is made between CPU bus cycles. Mode 1 supports multitransfer DMA in which multiple transfers are made continuously until the transmit FIFO has been filled.

Write inputs. When either WR1 or WR2 are active (high or low respectively) while the ACE is selected, the CPU is allowed to write control words or data into a selected ACE register. Only one of these inputs is required to transfer data during a write operation; the other input should be tied in its inactive state (i.e., WR2 tied low or WR1

I/O External clock. XIN and XOUT connect the ACE to the main timing reference (clock or crystal).

is active (low). When RXRDY has been active but there

goes inactive (high). In DMA mode 1 (FCR0 = 1, FCR3

input has transitioned from a low to a high

goes active (low); when it has been active

tied high).

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C550A

In ut leakage current

±10

µA

IOZHigh-im edance out ut current

±20

µA

Chi

25 C

SIN, DSR, DCD, CTS

ICCSu ly current

,,,, ,

All other in uts at 0.8 V,XTAL1 at 4 MHz

No load

Baud

kbit/

All other terminals grounded

f = 1 MHz

25 C

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

absolute maximum ratings over free-air temperature range (unless otherwise noted)

Supply voltage range, V Input voltage range at any input, V Output voltage range, V Operating free-air temperature range, T Storage temperature range, T Case temperature for 10 seconds, T

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

: FN package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package 260°C. . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to VSS.

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage, V High-level input voltage, V Low-level input voltage, V Operating free-air temperature, T

4.75 5 5.25 V 2 V

–0.5 0.8 V

0 70 °C

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

‡

XIN

XOUT

†

All typical values are at VCC = 5 V, TA = 25°C.

‡

These parameters apply for all outputs except XOUT.

High-level output voltage IOH = –1 mA 2.4 V

‡

Low-level output voltage IOL = 1.6 mA 0.4 V

Clock input capacitance Clock output capacitance Input capacitance Output capacitance

VCC = 5.25 V, VSS = 0, VI = 0 to 5.25 V,

= 5.25 V,

= 0 to 5.25 V,

p selected in write mode or chip deselecte

= 5.25 V,

on outputs,

VCC = 0, VSS = 0,

f = 1 MHz

All other terminals floating

, and RI at 2 V,

rate = 50

= 25°

15 20 pF 20 30 pF

6 10 pF

10 20 pF

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C550A

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

system timing requirements over recommended ranges of supply voltage and operating free-air temperature

ALT. SYMBOL FIGURE MIN MAX UNIT

su1

su2

su3

Applicable only when ADS is tied low.

Cycle time, read (tw7 + td8 + td9) RC 175 ns Cycle time, write (tw6 + td5 + td6) WC 175 ns Pulse duration, ADS low Pulse duration, write strobe t Pulse duration, read strobe tRD 3 80 ns Pulse duration, master reset t Setup time, address valid before ADS↑ t Setup time, CS before ADS↑ t Setup time, data valid before WR1↓ or WR2↑ t Hold time, address low after ADS↑ t Hold time, CS valid after ADS↑ t Hold time, CS valid after WR1↑ or WR2↓ t

Hold time, address valid after WR1↑ or WR2↓ t Hold time, data valid after WR1↑ or WR2↓ t Hold time, CS valid after RD1↑orRD2↓

Hold time, address valid after RD1↑ or RD2↓ t

Delay time, CS valid before WR1↓ or WR2↑ t

Delay time, address valid before WR1↓ or WR2↑ t

Delay time, write cycle, WR1↑ or WR2↓ to ADS↓ t

Delay time, CS valid to RD1↓

Delay time, address valid to RD1↓ or RD2↑ t Delay time, read cycle, RD1↑ or RD2↓ to ADS↓ tRC 3 80 ns

or RD2

↑

ADS

AS CS DS AH CH

WCS

RCS

CSW

AW WC

CSR

2, 3 15 ns

2 80 ns

1 µs 2, 3 15 ns 2, 3 15 ns

2 15 ns 2, 3 0 ns 2, 3 0 ns

2 20 ns

2 15 ns

3 20 ns

2 15 ns

2 80 ns

3 15 ns

system switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see Note 2)

PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT

d10

d11

dis(R)

NOTE 2: Charge and discharge time is determined by VOL, VOH, and external loading.

Pulse duration, clock high t Pulse duration, clock low t Delay time, RD1↓ or RD2↑ to data valid t Delay time, RD1↑ or RD2↓ to floating data t Disable time, RD1↓↑ or RD2↑↓ to DDIS↑↓ t

RVD

RDD

1 f = 9 MHz maximum 50 ns 1 f = 9 MHz maximum 50 ns 3 CL = 100 pF 60 ns 3 CL = 100 pF 0 60 ns 3 CL = 100 pF 60 ns

baud generator switching characteristics over recommended ranges of supply voltage and operating free-air temperature

PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT

t t

w4 d1

Pulse duration, BAUDOUT low t

Pulse duration, BAUDOUT high t Delay time, XIN↑ to BAUDOUT↑ t

Delay time, XIN↑↓ to BAUDOUT↓ t

BLD

BHD

1 1 CL = 100 pF 125 ns

1 CL = 100 pF 125 ns

f = 9 MHz, CLK ÷ 2,

CL = 100 pF

f = 9 MHz, CLK ÷ 2,

CL = 100 pF

80 ns

100 ns

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C550A ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

receiver switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see Note 3)

PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT

d12

d13

d14

NOTE 3: In FIFO mode RC = 425 ns (minimum) between reads of the receiver FIFO and the status registers (interrupt identification register or

transmitter switching characteristics over recommended ranges of supply voltage and operating free-air temperature

d15

d16

d17

d18

d19

d20

d21

Delay time, RCLK to sample clock t Delay time, stop to set RCV error interrupt or

read RBR to LSI interrupt or stop to

↓

RXRDY Delay time, read RBR/LSR to reset interrupt t

line status register).

PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT

Delay time, INTRPT to transmit start t

Delay time, start to interrupt t Delay time, WR THR to reset interrupt t Delay time, initial write to interrupt (THRE) t Delay time, read IIR to reset interrupt (THRE) t

Delay time, write to TXRDY inactive t Delay time, start to TXRDY active t

SCD

SINT

RINT

IRS

STI HR

SI IR

WXI

SXA

4 100 ns

4,5,6,7,8 1

4,5,6,7,8 CL = 100 pF 150 ns

9 8 24

9 8 8 9 CL = 100 pF 140 ns 9 16 32 9 CL = 100 pF 140 ns

10,11 CL = 100 pF 195 ns 10,11 CL = 100 pF 8

RCLK cycles

baudout

cycles

baudout

cycles

baudout

cycles

baudout

cycles

modem control switching characteristics over recommended ranges of supply voltage and operating free-air temperature

PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT

d22

d23

d24

Delay time, WR MCR to output t Delay time, modem interrupt to set interrupt t Delay time, RD MSR to reset interrupt t

MDO

SIM RIM

12 CL = 100 pF 100 ns 12 CL = 100 pF 170 ns 12 CL = 100 pF 140 ns

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION

TL16C550A

XIN or RCLK

(9 MHz Max)

BAUDOUT

XIN

(1/1)

(1/2)

(1/3)

2 V

0.8 V

2.4 V

0.4 V

BAUDOUT

(1/N)

(N > 3)

2 XIN Cycles

(N-2) XIN Cycles

Figure 1. Baud Generator Timing Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C550A ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION

ADS

A0–A2

CS0, CS1, CS2

WR1, WR2

D7–D0

†

Applicable only when ADS is tied low.

50%

50% 50%

50%50%

su1

Valid Valid

su2

Valid Valid

†

50% 50%

su3

Active

Valid Data

50%

†

50%50%

†

Figure 2. Write Cycle Timing Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

+ 21 hidden pages

TEXAS INSTRUMENTS TL16C550A Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual