TEXAS INSTRUMENTS TL16C550A Technical data

查询TL16C550供应商

Capable of Running With All Existing TL16C450 Software

After Reset, All Registers Are Identical to the TL16C450 Register Set

In the FIFO Mode, Transmitter and Receiver Are Each Buffered With 16-Byte FIFOs to Reduce the Number of Interrupts to the CPU

In the TL16C450 Mode, Holding and Shift Registers Eliminate the Need for Precise

Synchronization Between the CPU and Serial Data

Programmable Baud Rate Generator Allows Division of Any Input Reference Clock by 1

to (2 Clock

Standard Asynchronous Communication Bits (Start, Stop, and Parity) Added to or Deleted From the Serial Data Stream

Independent Receiver Clock Input

Transmit, Receive, Line Status, and Data Set Interrupts Independently Controlled

description

–1) and Generates an Internal 16×

TL16C550A

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

Fully Programmable Serial Interface Characteristics:

– 5-, 6-, 7-, or 8-Bit Characters – Even-, Odd-, or No-Parity Bit Generation

and Detection – 1-, 1 1/2-, or 2-Stop Bit Generation – Baud Generation (dc to 256 Kbit/s)

False-Start Bit Detection

Complete Status Reporting Capabilities

3-State TTL Drive Capabilities for Bidirectional Data Bus and Control Bus

Line Break Generation and Detection

Internal Diagnostic Capabilities: – Loopback Controls for Communications

Link Fault Isolation – Break, Parity, Overrun, Framing Error

Simulation

Fully Prioritized Interrupt System Controls

Modem Control Functions (CTS, RTS, DSR, DTR, RI, and DCD)

Faster Plug-In Replacement for National Semiconductor NS16550A

The TL16C550A is a functional upgrade of the TL16C450 asynchronous communications element (ACE). Functionally identical to the TL16C450 on power up (character mode alternate mode (FIFO) to relieve the CPU of excessive software overhead.

In this mode, internal FIFOs are activated allowing 16 bytes (plus 3 bits of error data per byte in the receiver FIFO) to be stored in both receive and transmit modes. To minimize system overhead and maximize system efficiency , all logic is on the chip. Two of the TL16C450 terminal functions (terminals 24 and 29 on the N package and terminals 27 and 32 on the FN package) have been changed to allow signalling of direct memory address (DMA) transfers.

The TL16C550A performs serial-to-parallel conversion on data received from a peripheral device or modem and parallel-to-serial conversion on data received from its CPU. The CPU can read and report on the status of the ACE at any point in the ACE’s operation. Reported status information includes the type of transfer operation in progress, the status of the operation, and any error conditions encountered.

The TL16C550A ACE includes a programmable, on-board, baud rate generator. This generator is capable of dividing a reference clock input by divisors from 1 to (2 transmitter logic. Provisions are included to use this 16× clock to drive the receiver logic. Also included in the ACE is a complete modem control capability and a processor interrupt system that may be software tailored to the user’s requirements to minimize the computing required to handle the communications link.

†

The TL16C550A can also be reset to the TL16C450 mode under software control.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

–1) and producing a 16× clock for driving the internal

†

), the TL16C550A can be placed in an

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C550A ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

D0 D1 D2 D3 D4 D5 D6 D7

RCLK

SIN

SOUT

CS0 CS1 CS2

BAUDOUT

XIN

XOUT

WR1 WR2

N PACKAGE

(TOP VIEW)

RI DCD DSR CTS MR OUT1 DTR RTS OUT2 INTRPT RXRDY A0 A1 A2 ADS TXRDY DDIS RD2 RD1

D4D3D2D1D0NCV

D5 D6 D7

RCLK

SIN

SOUT

CS0 CS1 CS2

BAUDOUT

54 321644

7 8 9 10 11 12 13 14 15 16 17

1819

XIN

XOUT

NC–No internal connection

FN PACKAGE

(TOP VIEW)

20 21 22 23

WR1

WR2

DCD

42 41 4043

24 25 26 27 28

RD2

RD1

DDIS

DSR

CTS

OUT1

DTR

RTS

OUT2

INTRPT

33 32

RXRDY

ADS

TXRDY

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

block diagram

Data Bus

Internal

TL16C550A

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

S e

l e c

Receiver

FIFO

D7–D0

A0 A1 A2

CS0 CS1 CS2

ADS

MR RD1 RD2

WR1 WR2

DDIS

TXRDY

XIN

XOUT

RXRDY

8–1

28 27 26

12 13 14 25 35 21 22 18 19 23 24 16 17 29

40 20

Line

Control

Select

and

Control

Logic

Power Supply

Receiver

Buffer

Line

Control

Divisor

Latch (LS)

Divisor

Latch (MS)

Line

Status

Transmitter

Holding

Modem Control

Modem

Status

Interrupt

Enable

Baud

Generator

Transmitter

FIFO

Interrupt

Control

Logic

Receiver

Buffer

Receiver

Timing and

Control

Line

Control

S e

l e c

Line

Control

Modem Control

Logic

SIN

RCLK

BAUDOUT

SOUT

RTS

CTS

DTR

DSR

DCD

OUT1

OUT2

INTRPT

Interrupt

I/O

FIFO

Control

NOTE A: Terminal numbers shown are for the N package.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C550A

I/O

DESCRIPTION

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

Terminal Functions

TERMINAL

NAME NO.

A0 A1 A2

ADS

BAUDOUT

CS0 CS1 CS2

CTS

D0 – D7 1 – 8

DCD

DDIS 23 [26] O Driver disable. This output is active (high) when the CPU is not reading data. When active, this output can disable

DSR

DTR

INTRPT 30 [33] O Interrupt. When active (high), INTRPT informs the CPU that the ACE has an interrupt to be serviced. Four

MR 35 [39] I Master reset. When active (high), MR clears most ACE registers and sets the state of various output signals. Refer

OUT1 OUT2

RCLK 9 [10] I Receiver clock. RCLK is the 16× baud rate clock for the receiver section of the ACE. RD1

RD2

†

Terminal numbers shown in brackets are for the FN package.

†

28 [31] 27 [30] 26 [29]

25 [28] I

15 [17] O

12 [14] 13 [15] 14 [16]

36 [40] I

I/O Data bus. Eight 3-state data lines provide a bidirectional path for data, control, and status information between the

[2 – 9]

38 [42] I

37 [41] I

33 [37] O

34 [38] 31 [35]

21 [24] 22 [25]

I Register select. A0, A1, and A2 are used during read and write operations to select the ACE register to read from

or write to. Refer to Table 1 for register addresses, also refer to the address strobe (ADS

Address strobe. When ADS is active (low), the register select signals (A0, A1, and A2) and chip select signals (CS0, CS1, CS2 the state they were in when the low-to-high transition of ADS

Baud out. BAUDOUT is a 16× clock signal for the transmitter section of the ACE. The clock rate is established by the reference oscillator frequency divided by a divisor specified by the baud generator divisor latches. BAUDOUT may also be used for the receiver section by tying this output to the RCLK input.

Chip select. When CSx is active (high, high, and low respectively), the ACE is selected. If any of these inputs are inactive, the ACE remains inactive. Refer to the ADS

Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of the modem status register. Bit 0 (DCTS) of the modem status register indicates that this signal has changed states since the last read from the modem status register. If the modem status interrupt is enabled when CTS interrupt is generated.

ACE and the CPU. Data carrier detect. DCD is a modem status signal. Its condition can be checked by reading bit 7 (DCD) of the

modem status register. Bit 3 (DDCD) of the modem status register indicates that this signal has changed states since the last read from the modem status register. If the modem status interrupt is enabled when the DCD state, an interrupt is generated.

an external transceiver. Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of the modem

status register. Bit 1 (DDSR) of the modem status register indicates that this signal has changed states since the last read from the modem status register. If the modem status interrupt is enabled when the DSR an interrupt is generated.

Data terminal ready. When active (low), DTR informs a modem or data set that the ACE is ready to establish communication. DTR DTR bit 0 (DTR) of the modem control register.

conditions that cause an interrupt to be issued are: a receiver error, received data is available or timeout (FIFO mode only), transmitter holding register empty, or an enabled modem status interrupt. The INTRPT output is reset (deactivated) either when the interrupt is serviced or as a result of a master reset.

to Table 2.

Outputs 1 and 2. OUT1 and OUT2 are user-designated output terminals that are set to their active states by setting their respective modem control register bits (OUT1 and OUT2) high. OUT1 states as a result of master reset or during loop mode operations or by clearing bit 2 (OUT1) or bit 3 (OUT2) of the modem control register.

Read inputs. When either RD1 or RD2 are active (high or low respectively) while the ACE is selected, the CPU is allowed to read status information or data from a selected ACE register. Only one of these inputs is required for the transfer of data during a read operation; the other input should be tied in its inactive state (i.e., RD2 tied low or RD1

) drive the internal select logic directly; when high, the register select and chip select signals are held in

occurred.

(address strobe) signal description.

is placed in the active state by setting the DTR bit of the modem control register to a high level.

is placed in the inactive state either as a result of a master reset or during loop mode operation or clearing

and OUT2 are set to their inactive (high)

tied high).

) signal description.

changes state, an

changes

changes state,

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C550A

I/O

DESCRIPTION

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

Terminal Functions (continued)

TERMINAL

NAME NO.

RTS

RXRDY

SIN 10 [11] I Serial input. SIN is a serial data input from a connected communications device. SOUT 11 [13] O Serial output. SOUT is a composite serial data output to a connected communication device. SOUT is set to the

TXRDY

SS WR1 WR2

XIN XOUT

†

Terminal numbers shown in brackets are for the FN package.

†

39 [43] I Ring indicator . RI is a modem status signal. Its condition can be checked by reading bit 6 (RI) of the modem status

register. Bit 2 (TERI) of the modem status register indicates that the RI state since the last read from the modem status register. If the modem status interrupt is enabled when this transition occurs, an interrupt is generated.

32 [36] O

29 [32] O

24 [27] O

40 [44] 5-V supply voltage 20 [22] Supply common 18 [20]

19 [21]

16 [18] 17 [19]

Request to send. When active, RTS informs the modem or data set that the ACE is ready to transmit data. RTS is set to its active state by setting the RTS modem control register bit, and is set to its inactive (high) state either as a result of a master reset or during loop mode operations or by clearing bit 1 (RTS) of the modem control register .

Receiver ready output. Receiver direct memory access (DMA) signalling is available with RXRDY . When operating in the FIFO mode, one of two types of DMA signalling can be selected with FCR3. When operating in the TL16C450 mode, only DMA mode 0 is allowed. Mode 0 supports single-transfer DMA in which a transfer is made between CPU bus cycles. Mode 1 supports multitransfer DMA in which multiple transfers are made continuously until the receiver FIFO has been emptied. In DMA mode 0 (FCR0 = 0 or FCR0 = 1, FCR3 = 0), if there is at least 1 character in the receiver FIFO or receiver holding register, RXRDY are no characters in the FIFO or holding register, RXRDY = 1), when the trigger level or the timeout has been reached, RXRDY but there are no more characters in the FIFO or holding register, it goes inactive (high).

marking (high) state as a result of master reset. Transmitter ready output. T ransmitter DMA signalling is available with TXRDY . When operating in the FIFO mode,

one of two types of DMA signalling can be selected with FCR3. When operating in the TL16C450 mode, only DMA mode 0 is allowed. Mode 0 supports single-transfer DMA in which a transfer is made between CPU bus cycles. Mode 1 supports multitransfer DMA in which multiple transfers are made continuously until the transmit FIFO has been filled.

Write inputs. When either WR1 or WR2 are active (high or low respectively) while the ACE is selected, the CPU is allowed to write control words or data into a selected ACE register. Only one of these inputs is required to transfer data during a write operation; the other input should be tied in its inactive state (i.e., WR2 tied low or WR1

I/O External clock. XIN and XOUT connect the ACE to the main timing reference (clock or crystal).

is active (low). When RXRDY has been active but there

goes inactive (high). In DMA mode 1 (FCR0 = 1, FCR3

input has transitioned from a low to a high

goes active (low); when it has been active

tied high).

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C550A

In ut leakage current

±10

µA

IOZHigh-im edance out ut current

±20

µA

Chi

25 C

SIN, DSR, DCD, CTS

ICCSu ly current

,,,, ,

All other in uts at 0.8 V,XTAL1 at 4 MHz

No load

Baud

kbit/

All other terminals grounded

f = 1 MHz

25 C

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

absolute maximum ratings over free-air temperature range (unless otherwise noted)

Supply voltage range, V Input voltage range at any input, V Output voltage range, V Operating free-air temperature range, T Storage temperature range, T Case temperature for 10 seconds, T

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

: FN package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package 260°C. . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to VSS.

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage, V High-level input voltage, V Low-level input voltage, V Operating free-air temperature, T

4.75 5 5.25 V 2 V

–0.5 0.8 V

0 70 °C

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

‡

XIN

XOUT

†

All typical values are at VCC = 5 V, TA = 25°C.

‡

These parameters apply for all outputs except XOUT.

High-level output voltage IOH = –1 mA 2.4 V

‡

Low-level output voltage IOL = 1.6 mA 0.4 V

Clock input capacitance Clock output capacitance Input capacitance Output capacitance

VCC = 5.25 V, VSS = 0, VI = 0 to 5.25 V,

= 5.25 V,

= 0 to 5.25 V,

p selected in write mode or chip deselecte

= 5.25 V,

on outputs,

VCC = 0, VSS = 0,

f = 1 MHz

All other terminals floating

, and RI at 2 V,

rate = 50

= 25°

15 20 pF 20 30 pF

6 10 pF

10 20 pF

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C550A

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

system timing requirements over recommended ranges of supply voltage and operating free-air temperature

ALT. SYMBOL FIGURE MIN MAX UNIT

su1

su2

su3

Applicable only when ADS is tied low.

Cycle time, read (tw7 + td8 + td9) RC 175 ns Cycle time, write (tw6 + td5 + td6) WC 175 ns Pulse duration, ADS low Pulse duration, write strobe t Pulse duration, read strobe tRD 3 80 ns Pulse duration, master reset t Setup time, address valid before ADS↑ t Setup time, CS before ADS↑ t Setup time, data valid before WR1↓ or WR2↑ t Hold time, address low after ADS↑ t Hold time, CS valid after ADS↑ t Hold time, CS valid after WR1↑ or WR2↓ t

Hold time, address valid after WR1↑ or WR2↓ t Hold time, data valid after WR1↑ or WR2↓ t Hold time, CS valid after RD1↑orRD2↓

Hold time, address valid after RD1↑ or RD2↓ t

Delay time, CS valid before WR1↓ or WR2↑ t

Delay time, address valid before WR1↓ or WR2↑ t

Delay time, write cycle, WR1↑ or WR2↓ to ADS↓ t

Delay time, CS valid to RD1↓

Delay time, address valid to RD1↓ or RD2↑ t Delay time, read cycle, RD1↑ or RD2↓ to ADS↓ tRC 3 80 ns

or RD2

↑

ADS

AS CS DS AH CH

WCS

RCS

CSW

AW WC

CSR

2, 3 15 ns

2 80 ns

1 µs 2, 3 15 ns 2, 3 15 ns

2 15 ns 2, 3 0 ns 2, 3 0 ns

2 20 ns

2 15 ns

3 20 ns

2 15 ns

2 80 ns

3 15 ns

system switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see Note 2)

PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT

d10

d11

dis(R)

NOTE 2: Charge and discharge time is determined by VOL, VOH, and external loading.

Pulse duration, clock high t Pulse duration, clock low t Delay time, RD1↓ or RD2↑ to data valid t Delay time, RD1↑ or RD2↓ to floating data t Disable time, RD1↓↑ or RD2↑↓ to DDIS↑↓ t

RVD

RDD

1 f = 9 MHz maximum 50 ns 1 f = 9 MHz maximum 50 ns 3 CL = 100 pF 60 ns 3 CL = 100 pF 0 60 ns 3 CL = 100 pF 60 ns

baud generator switching characteristics over recommended ranges of supply voltage and operating free-air temperature

PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT

t t

w4 d1

Pulse duration, BAUDOUT low t

Pulse duration, BAUDOUT high t Delay time, XIN↑ to BAUDOUT↑ t

Delay time, XIN↑↓ to BAUDOUT↓ t

BLD

BHD

1 1 CL = 100 pF 125 ns

1 CL = 100 pF 125 ns

f = 9 MHz, CLK ÷ 2,

CL = 100 pF

f = 9 MHz, CLK ÷ 2,

CL = 100 pF

80 ns

100 ns

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C550A ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

receiver switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see Note 3)

PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT

d12

d13

d14

NOTE 3: In FIFO mode RC = 425 ns (minimum) between reads of the receiver FIFO and the status registers (interrupt identification register or

transmitter switching characteristics over recommended ranges of supply voltage and operating free-air temperature

d15

d16

d17

d18

d19

d20

d21

Delay time, RCLK to sample clock t Delay time, stop to set RCV error interrupt or

read RBR to LSI interrupt or stop to

↓

RXRDY Delay time, read RBR/LSR to reset interrupt t

line status register).

PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT

Delay time, INTRPT to transmit start t

Delay time, start to interrupt t Delay time, WR THR to reset interrupt t Delay time, initial write to interrupt (THRE) t Delay time, read IIR to reset interrupt (THRE) t

Delay time, write to TXRDY inactive t Delay time, start to TXRDY active t

SCD

SINT

RINT

IRS

STI HR

SI IR

WXI

SXA

4 100 ns

4,5,6,7,8 1

4,5,6,7,8 CL = 100 pF 150 ns

9 8 24

9 8 8 9 CL = 100 pF 140 ns 9 16 32 9 CL = 100 pF 140 ns

10,11 CL = 100 pF 195 ns 10,11 CL = 100 pF 8

RCLK cycles

baudout

cycles

baudout

cycles

baudout

cycles

baudout

cycles

modem control switching characteristics over recommended ranges of supply voltage and operating free-air temperature

PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT

d22

d23

d24

Delay time, WR MCR to output t Delay time, modem interrupt to set interrupt t Delay time, RD MSR to reset interrupt t

MDO

SIM RIM

12 CL = 100 pF 100 ns 12 CL = 100 pF 170 ns 12 CL = 100 pF 140 ns

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION

TL16C550A

XIN or RCLK

(9 MHz Max)

BAUDOUT

XIN

(1/1)

(1/2)

(1/3)

2 V

0.8 V

2.4 V

0.4 V

BAUDOUT

(1/N)

(N > 3)

2 XIN Cycles

(N-2) XIN Cycles

Figure 1. Baud Generator Timing Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C550A ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION

ADS

A0–A2

CS0, CS1, CS2

WR1, WR2

D7–D0

†

Applicable only when ADS is tied low.

50%

50% 50%

50%50%

su1

Valid Valid

su2

Valid Valid

†

50% 50%

su3

Active

Valid Data

50%

†

50%50%

†

Figure 2. Write Cycle Timing Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION

TL16C550A

ADS

A0–A2

CS0, CS1, CS2

RD1, RD2

DDIS

50%

50%50%

su1

Valid Valid

†

td8†

50% 50%

dis(R)

50% 50%

su2

50%

Active

50% 50%

50%

†

50%

†

dis(R)

D7–D0

†

Applicable only when ADS is tied low.

Figure 3. Read Cycle Timing Waveforms

d10

Valid Data

d11

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C550A ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION

RCLK

8 Clocks

Sample Clock

TL16C450 Mode:

d12

SIN

Sample Clock

INTRPT

(data ready)

INTRPT

(RCV error)

RD1

, RD2

(read RBR)

RD1

, RD2

(read LSR)

Parity StopStart Data Bits 5–8

d13

50%

Figure 4. Receiver Timing Waveforms

d14

Active

d14

50%

50%50%

Active

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION

TL16C550A

SIN

Sample Clock

Trigger-Level

Interrupt

(FCR6, 7 = 0, 0)

LSI Interrupt

RD1

(RD LSR)

RD1

(RD RBR)

NOTE A: For a timeout interrupt, t

Figure 5. Receiver FIFO First Byte (Sets DR Bit) Waveforms

SIN

= 8 RCLKs.

d13

Data Bits 5-8

(see Note A)

d13

Stop

d14

Stop

Active

d14

(FIFO at or Above Trigger Level)

(FIFO Below Trigger Level)

Active

Sample Clock

Time Out or

Trigger Level

Interrupt

LSI Interrupt

RD1, RD2

(RDLSR)

RD1, RD2

(RDRBR)

NOTE A: For a timeout interrupt, t

(see Note A)

d13

Previous Byte

Read From FIFO

= 8 RCLKs.

d14

Top Byte of FIFO

d14

Active Active

(FIFO at or Above Trigger Level)

(FIFO Below Trigger Level)

Figure 6. Receiver FIFO Bytes Other Than the First Byte (DR Internal Bit Already Set) Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C550A ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION

(RD RBR)

SIN

(first byte)

Sample Clock

(see Note B)

RXRDY

NOTES: A. This is the reading of the last byte in the FIFO.

B. For a timeout interrupt, t

= 8 RCLKs.

d13

Stop

Figure 7. Receiver Ready (RXRDY) Waveforms, FCR0 = 0 or FCR0 = 1 and FCR3 = 0 (mode 0)

(RD RBR)

(first byte that reaches

the trigger level)

SIN

d14

Active

See Note A

Active

See Note A

Sample Clock

(see Note B)

RXRDY

NOTES: A. This is the reading of the last byte in the FIFO.

B. For a timeout interrupt, t

d13

= 8 RCLKs.

Figure 8. Receiver Ready (RXRDY) Waveforms, FCR = 1 or FCR3 = 1 (mode 1)

d14

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION

TL16C550A

SOUT

INTRPT

(THRE)

WR THR

RD IIR

Start

50%

d15

50% 50% 50% 50% 50%

d18

d17

50%

Data Bits

50%

d17

Parity Stop

d16

Start

50%

Figure 9. Transmitter Timing Waveforms

(WR THR)

Byte #1

d19

50%

SOUT

TXRDY

Data

d20

Parity

Stop

d21

Start

Figure 10. Transmitter Ready (TXRDY) Waveforms, FCR0 = 0 or FCR0 = 1 and FCR3 = 0 (mode 0)

(WR THR)

SOUT

TXRDY

Data

Byte #16

d20

Parity

FIFO Full

Stop

d21

Start

Figure 11. Transmitter Ready (TXRDY) Waveforms, FCR0 = 1 and FCR3 = 1 (mode 1)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C550A ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION

(WR MCR)

RTS, DTR,

OUT1

, OUT2

CTS, DSR, DCD

INTRPT

(modem)

RD2

(RD MSR)

50% 50%

d22

50% 50%

50%

d23

d24

50%

d22

50%

d23

Figure 12. Modem Control Timing Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ASYNCHRONOUS COMMUNICATIONS ELEMENT

APPLICATION INFORMATION

TL16C550A

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

C P U

B u

D7–D0

MEMR

or I/OR

MEMW or I/ON

INTR

RESET

A0 A1 A2

Figure 13. Basic TL16C550A Configuration

D7–D0

RD1 WR1

INTRPT MR

A0 A1 A2

ADS WR2 RD2

CS2 CS1 CS0

TL16C550A

(ACE)

BAUDOUT

SOUT

SIN RTS DTR DSR

DCD

CTS

XIN

XOUT

RCLK

Receiver Disable

EIA

232-D Drivers

and Receivers

3.072 MHz

WR1

Microcomputer

System

Figure 14. Typical Interface for a High-Capacity Data Bus

Data Bus Data Bus

8-Bit

Bus Transceiver

Driver Disable

TL16C550A

(ACE)

D7–D0

DDIS

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C550A ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

APPLICATION INFORMATION

A16–A23

CPU

ADS

RSI/ABT

AD0–AD15

PHI1 PHI2

Address Decoder

Buffer

A16–A23

AD0–AD7

12 13 14

TL16C550A

CS0 CS1 CS2

ADS

A0–A2

D0–D2

†

XIN

XOUT

BAUDOUT

RCLK

DTR

RTS

OUT1 OUT2

DCD DSR

CTS

Alternate

17 15 9

33 32 34 31

38 37 36

XTAL Control

8 6 5

RSTO

PHI1 PHI2

†

Terminal numbers for the TL16C550A are for the N package.

ADS

TCU

AD0–AD15

Figure 15. Typical TL16C550A Connection to a CPU

GND

RD1

WR1

RD2 WR2

SS)

SOUT

SIN

INTRPT

TXRDY

DDIS

RXRDY

20 40

5 V

CC)

10 30 24 23 2919

7 1

EIA-232-D

Connector

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

PRINCIPLES OF OPERATION

Table 1. Register Selection

†

DLAB

0 L L L Receiver buffer (read), transmitter holding register (write) 0 L L H Interrupt enable register X L H L Interrupt identification register (read only) X L H L FIFO control register (write) X L H H Line control register X H L L Modem control register X H L H Line status register X H H L Modem status register X H H H Scratch register 1 L L L Divisor latch (LSB) 1 L L H Divisor latch (MSB)

†

The divisor latch access bit (DLAB) is the most significant bit of the line control register . The DLAB signal is controlled by writing to this bit location (see Table 3).

A2 A1 A0 REGISTER

Table 2. ACE Reset Functions

TL16C550A

Interrupt Enable Register Master Reset All bits cleared (0–3 forced and 4–7 permanent) Interrupt Identification Register Master Reset FIFO Control Register Master Reset All bits cleared

Line Control Register Master Reset All bits cleared Modem Control Register Master Reset All bits cleared (5–7 permanent) Line Status Register Master Reset Bits 5 and 6 are set, all other bits are cleared Modem Status Register Master Reset Bits 0–3 are cleared, bits 4–7 are input signals SOUT Master Reset High INTRPT (receiver error flag) Read LSR/MR Low INTRPT (received data available) Read RBR/MR Low

INTRPT (transmitter holding register empty) INTRPT (modem status changes) Read MSR/MR Low

OUT2 RTS DTR OUT1 Scratch Register Master Reset No effect

Divisor Latch (LSB and MSB) Registers Master Reset No effect Receiver Buffer Registers Master Reset No effect Transmitter Holding Registers Master Reset No effect

RCVR FIFO

XMIT FIFO

RESET

CONTROL

Read IR/Write

THR/MR

Master Reset High Master Reset High Master Reset High Master Reset High

MR/FCR1-FCR0/

∆FCR0

MR/FCR2-FCR0/

∆FCR0

RESET STATE

Bit 0 is set, bits 1–3 are cleared, and bits 4–7 are permanently cleared

Low

All bits low

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C550A ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

PRINCIPLES OF OPERATION

accessible registers

The system programmer, using the CPU, has access to and control over any of the ACE registers that are summarized in Table 3. These registers control ACE operations, receive data, and transmit data. Descriptions of these registers follow Table 3.

Table 3. Summary of Accessible Registers

0DLAB=0 0 DLAB = 0 1DLAB=0 2 2 3 4 5 6 7 0 DLAB = 1 1 DLAB = 1

Receiver

Bit

Buffer

No.

(Read Only)

RBR THR IER IIR FCR LCR MCR LSR MSR SCR DLL DLM

0 Data Bit 0†Data Bit 0

1 Data Bit 1 Data Bit 1

2 Data Bit 2 Data Bit 2

3 Data Bit 3 Data Bit 3

4 Data Bit 4 Data Bit 4 0 0 Reserved

5 Data Bit 5 Data Bit 5 0 0 Reserved

6 Data Bit 6 Data Bit 6 0

7 Data Bit 7 Data Bit 7 0

†

Bit 0 is the least significant bit. It is the first bit serially transmitted or received.

NOTE 4: These bits are always cleared in the TL16C450 mode.

Transmitter

Holding

(Write

Only)

Interrupt

Enable

Received

Data

Available

Interrupt

(ERB)

Enable

Transmitter

Holding

Empty Interrupt (ETBEI)

Enable

Receiver

Line Status

Interrupt

(ELSI)

Enable

Modem

Status Interrupt (EDSSI)

Interrupt

Ident.

(Read Only)

”0“ If Interrupt Pending

Interrupt

Bit 0

Interrupt

Bit (1)

Interrupt

Bit (2)

(Note 4)

FIFOs Enabled (Note 4)

FIFO

Control

(Write

Only)

FIFO

Enable

Receiver

FIFO

Reset

Transmitter

FIFO

Reset

DMA

Mode

Select

Receiver

Trigger

(LSB)

Receiver

Trigger

(MSB)

Line

Control

Word

Length

Select

Bit 0

(WLS0)

Word

Length

Select

Bit 1

(WLS1)

Number

Stop Bits

(STB)

Parity

Enable

(PEN)

Even Parity Select (EPS)

Stick Parity

Set

Break

Divisor

Latch

Access

Bit

(DLAB)

Modem Control

Data

Terminal

Ready (DTR)

Request

to Send

(RTS)

Out1

Out2

Loop

Line

Status

Data

Ready

(DR)

Overrun

Error (OE)

Parity

Error (PE)

Framing

Error (FE)

Break

Interrupt

(BI)

Transmitter

Holding

(THRE)

Transmitter

Empty

(TEMT) Error in

RCVR

FIFO

(Note 4)

Modem

Status

Delta

Clear

to Send

∆CTS)

(

Delta

Data

Set

Ready

∆DSR)

(

Trailing

Edge Ring

Indicator

(TERI)

Delta

Data Carrier Detect

∆DCD)

(

Clear

Send

(CTS)

Data

Set

Ready

(DSR)

Ring

Indicator

(RI)

Data Carrier Detect

(DCD)

Scratch Register

Bit 0 Bit 0 Bit 8

Bit 1 Bit 1 Bit 9

Bit 2 Bit 2 Bit 10

Bit 3 Bit 3 Bit 11

Bit 4 Bit 4 Bit 12

Bit 5 Bit 5 Bit 13

Bit 6 Bit 6 Bit 14

Bit 7 Bit 7 Bit 15

Divisor

Latch (LSB)

Latch

(MSB)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C550A

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

PRINCIPLES OF OPERATION

FIFO control register (FCR)

The FCR is a write-only register at the same location as the IIR, which is a read-only register. The FCR enables the FIFOs, clears the FIFOs, sets the receiver FIFO trigger level, and selects the type of DMA signalling.

Bit 0: This bit (FCR0), when set, enables the transmit and receive FIFOs. Bit 0 must be set when other FCR bits are written to or they are not programmed. Changing this bit clears the FIFOs.

Bit 1: This bit (FCR1), when set, clears all bytes in the receiver FIFO and clears its counter . The shift register is not cleared. The 1 that is written to this bit position is self clearing.

Bit 2: This bit (FCR2), when set, clears all bytes in the transmit FIFO and clears its counter . The shift register is not cleared. The 1 that is written to this bit position is self clearing.

Bit 3: When this bit (FCR0) and FCR3 are set, RXRDY and TXRDY change from mode 0 to mode 1.

Bits 4 and 5: These two bits (FCR4 and FCR5) are reserved for future use.

Bits 6 and 7: These two bits (FCR6 and FCR7) set the trigger level for the receiver FIFO interrupt. Table 4 shows the trigger level for the receiver FIFO interrupt.

Table 4. Receiver FIFO Trigger Level

BIT 7 BIT 6

0 0 01 0 104 1008 1114

RECEIVER FIFO

TRIGGER LEVEL (BYTES)

FIFO interrupt mode operation

When the receiver FIFO and receiver interrupts are enabled (FCR0 = 1, IER0 = 1) receiver interrupts occur as follows:

1. The receive data available interrupt is issued to the microprocessor when the FIFO has reached its programmed trigger level. It is cleared as soon as the FIFO drops below its programmed trigger level.

2. The IIR receive data available indication also occurs when the FIFO trigger level is reached, and, like the interrupt, it is cleared when the FIFO drops below the trigger level.

3. The receiver line status interrupt (IIR = 06), as before, has higher priority than the received data available (IIR = 04) interrupt.

4. The data ready bit (LSR0) is set as soon as a character is transferred from the shift register to the receiver FIFO. It is cleared when the FIFO is empty.

When the receiver FIFO and receiver interrupts are enabled, receiver FIFO timeout interrupts occur as follows:

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C550A ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

PRINCIPLES OF OPERATION

FIFO interrupt mode operation (continued)

1. FIFO timeout interrupt occurs when the following conditions exist: a. At least one character is in the FIFO. b. The most recent serial character received was longer than 4 continuous character times ago (when

2 stop bits are programmed, the second one is included in this time delay).

c. The most recent microprocessor read of the FIFO was longer than 4 continuous character times

ago. This causes a maximum character received to interrupt issued delay of 160 ms at 300 baud with 12-bit characters.

2. Character times are calculated by using the RCLK input for a clock signal (this makes the delay proportional to the baud rate).

3. When a timeout interrupt has occurred, it is cleared and the timer reset when the microprocessor reads one character from the receiver FIFO.

4. When a timeout interrupt has not occurred, the timeout timer is reset after a new character is received or after the microprocessor reads the receiver FIFO.

When the transmit FIFO and transmitter interrupts are enabled (FCR0 = 1, IER1 = 1), transmit interrupts occur as follows:

1. The THR interrupt (02) occurs when the transmit FIFO is empty. It is cleared as soon as the THR is written to (1 to 16 characters may be written to the transmit FIFO while servicing this interrupt) or the IIR is read.

2. The transmit FIFO empty indications are delayed 1 character time minus the last stop bit time when the following occurs: THRE = 1 and there have not been at least two bytes at the same time in the transmit FIFO since the last THRE = 1. The first transmitter interrupt after changing FCR0 is immediate, if it is enabled.

Character timeout interrupt and receiver FIFO trigger level interrupts have the same priority as the current received data available interrupt. The transmit FIFO empty interrupt has the same priority as the current THRE interrupt.

FIFO polled mode operation

When FCR0 is set, clearing IER0, IER1, IER2, IER3, or all four puts the ACE in the FIFO polled mode of operation. Since the receiver and transmitter are controlled separately , either one or both can be in the polled mode of operation.

In this mode, the user program checks the receiver and transmitter status using the LSR.

LSR0 is set as long as there is one byte in the receiver FIFO.

LSR1 – LSR4 specify which error(s) have occurred. Character error status is handled the same way as when in the interrupt mode and the IIR is not affected since IER2 = 0.

LSR5 indicates when the transmit FIFO is empty.

LSR6 indicates that both the transmit FIFO and shift registers are empty.

LSR7 indicates whether there are any errors in the receiver FIFO.

There is no trigger level reached or timeout conditions indicated in the FIFO polled mode. However, the receiver and transmitter FIFOs are still fully capable of holding characters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C550A

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

PRINCIPLES OF OPERATION

interrupt enable register (IER)

The IER enables each of the four types of interrupts (refer to T able 5) and the INTRPT output signal in response to an interrupt generation. The IER can also disable the interrupt system by clearing bits 0 through 3. The contents of this register are summarized in Table3 and are described in the following bulleted list.

Bit 0: This bit, when set, enables the received data available interrupt.

Bit 1: This bit, when set, enables the THRE interrupt.

Bit 2: This bit, when set, enables the receiver line status interrupt.

Bit 3: This bit, when set, enables the modem status interrupt.

Bits 4 – 7: These bits in the IER are not used and are always cleared.

interrupt identification register (IIR)

The ACE has an on-chip interrupt generation and prioritization capability that permits a flexible interface with most popular microprocessors.

The ACE provides four prioritized levels of interrupts:

Priority 1– Receiver line status (highest priority)

Priority 2– Receiver data ready or receiver character time out

Priority 3–Transmitter holding register empty

Priority 4–Modem status (lowest priority)

When an interrupt is generated, the IIR indicates that an interrupt is pending and the type of interrupt is defined by the interrupt’s three least significant bits (bits 0, 1, and 2). The contents of this register are summarized in Table 3 and described in Table 4. Details of each bit are as follows:

Bit 0: This bit can be used either in a hardwire prioritized or polled interrupt system. When this bit is cleared, an interrupt is pending. When bit 0 is set, no interrupt is pending.

Bits 1 and 2: These two bits identify the highest priority interrupt pending as indicated in Table 5.

Bit 3: This bit is always cleared in the TL16C450 mode. In FIFO mode, this bit is set with bit 2 to indicate that a timeout interrupt is pending.

Bits 4 thru 5: These two bits are not used and are always cleared.

Bits 6 and 7: These two bits are always cleared in the TL16C450 mode. They are set when bit 0 of the FCR is set.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C550A ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

PRINCIPLES OF OPERATION

interrupt identification register (IIR) (continued)

Table 5. Interrupt Control Functions

INTERRUPT

IDENTIFICATION

BIT 3 BIT 2 BIT 1 BIT 0

0 0 0 1 None None None – 0 1 1 0 1 Receiver line status

0 1 0 0 2 Received data available

1 1 0 0 2

0 0 1 0 3

0 0 0 0 4 Modem status

PRIORITY

LEVEL

INTERRUPT TYPE INTERRUPT SOURCE

Overrun error, parity error, framing error, or break interrupt

Receiver data available in the TL16C450 mode or trigger level reached in the FIFO mode.

No characters have been

removed from or input to the Character timeout indication

Transmitter holding register empty

receiver FIFO during the last

four character times and there

is at least one character in it

during this time

Transmitter holding register

empty

Clear to send, data set ready,

ring indicator, or data carrier

detect

INTERRUPT RESET

Reading the line status register (LSR)

Reading the receiver buffer register (RBR)

Reading the interrupt identification register (IIR) (if source of interrupt) or writing into the transmitter holding register (THR)

Reading the modem status register (MSR)

METHOD

line control register (LCR)

The system programmer controls the format of the asynchronous data communication exchange through the LCR. In addition, the programmer is able to retrieve, inspect, and modify the contents of the LCR; this eliminates the need for separate storage of the line characteristics in system memory. The contents of this register are summarized in Table 3 and described in the following bulleted list.

Bits 0 and 1: These two bits specify the number of bits in each transmitted or received serial character. These bits are encoded as shown in Table 6.

Table 6. Serial Character Word Length

Bit 1 Bit 0 Word Length

0 0 5 Bits 0 1 6 Bits 1 0 7 Bits 1 1 8 Bits

Bit 2: This bit specifies either one, one and one-half, or two stop bits in each transmitted character . When bit 2 is cleared, one stop bit is generated in the data. When bit 2 is set, the number of stop bits generated is dependent on the word length selected with bits 0 and 1. The receiver clocks the first stop bit only, regardless of the number of stop bits selected. The number of stop bits generated, in relation to word length and bit 2, is shown in Table 7.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

†

‡

line control register (LCR) (continued)

Table 7. Number of Stop Bits Generated

TL16C550A

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

Bit 2

0 Any word length 1 1 5 bits 1 1/2 1 6 bits 2 1 7 bits 2 1 8 bits 2

Bit 3: This bit is the parity enable bit. When bit 3 is set, a parity bit is generated in the transmitted data

Word Length Selected

by Bits 1 and 2

Number of Stop

Bits Generated

between the last data word bit and the first stop bit. In received data, when bit 3 is set, parity is checked. When bit 3 is cleared, no parity is generated or checked.

Bit 4: This bit is the even parity select bit. When parity is enabled (bit 3 is set) and bit 4 is set, even parity (an even number of logic 1’s in the data and parity bits) is selected. When parity is enabled and bit 4 is cleared, odd parity (an odd number of logic 1s) is selected.

Bit 5: This is the stick parity bit. When bits 3, 4, and 5 are set, the parity bit is transmitted and checked as cleared. When bits 3 and 5 are set and bit 4 is cleared, the parity bit is transmitted and checked as set. When bit 5 is cleared, stick parity is disabled.

Bit 6: This bit is the break control bit. Bit 6 is set to force a break condition, i.e., a condition where the serial output (SOUT) terminal is forced to the spacing (low) state. When bit 6 is cleared, the break condition is disabled. The break condition has no affect on the transmitter logic; it only affects the serial output.

Bit 7: This bit is the divisor latch access bit (DLAB). Bit 7 must be set to access the divisor latches of the baud generator during a read or write. Bit 7 must be cleared during a read or write to access the receiver buffer, the THR, or the IER.

line status register (LSR)

†

The LSR provides information to the CPU concerning the status of data transfers. The contents of this register are described in the following bulleted list and summarized in Table 3.

Bit 0: This bit is the data ready (DR) indicator for the receiver. Bit 0 is set whenever a complete incoming character has been received and transferred into the RBR or the FIFO and is cleared by reading all of the data in the RBR or the FIFO.

Bit 1‡: This bit is the overrun error (OE) indicator. When bit 1 is set, it indicates that before the character in the RBR was read, it was overwritten by the next character transferred into the register. The OE indicator is cleared every time the CPU reads the contents of the LSR. If the FIFO mode data continues to fill the FIFO beyond the trigger level, an overrun error occurs only after the FIFO is full and the next character has been completely received in the shift register. OE is indicated to the CPU as soon as it happens. The character in the shift register is overwritten but is not transferred to the FIFO.

The line status register is intended for read operations only; writing to this register is not recommended outside of a factory testing environmen Bits 1 through 4 are the error conditions that produce a receiver line status Interrupt.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C550A

†

‡

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

PRINCIPLES OF OPERATION

line status register (LSR)

Bit 2‡.: This bit is the parity error (PE) indicator . When bit 2 is set, it indicates that the parity of the received data character does not match the parity selected in the LCR (bit 4). The PE bit is cleared every time the CPU reads the contents of the LSR. In the FIFO mode, this error is associated with the particular character in the FIFO to which it applies. This error is revealed to the CPU when its associated character is at the top of the FIFO.

Bit 3‡: This bit is the framing error (FE) indicator . When bit 3 is set, it indicates that the received character did not have a valid (set) stop bit. The FE bit is cleared every time the CPU reads the contents of the LSR. In the FIFO mode, this error is associated with the particular character in the FIFO to which it applies. This error is revealed to the CPU when its associated character is at the top of the FIFO. The ACE tries to resynchronize after a framing error. To accomplish this, it is assumed that the framing error is due to the next start bit. The ACE then samples this start bit twice and then accepts the input data.

Bit 4‡: This bit is the break interrupt (BI) indicator . When bit 4 is set, it indicates that the received data input was held clear for longer than a full-word transmission time. A full-word transmission time is defined as the total time of the start, data, parity , and stop bits. The BI bit is cleared every time the CPU reads the contents of the LSR. In the FIFO mode, this error is associated with the particular character in the FIFO to which it applies. This error is revealed to the CPU when its associated character is at the top of the FIFO. When break occurs, only the 0 character is loaded into the FIFO. The next character transfer is enabled after SIN goes to the marking state and receives the next valid start bit.

Bit 5: This bit is the THRE indicator. Bit 5 is set when the THR is empty, indicating that the ACE is ready to accept a new character. If the THRE interrupt is enabled when the THRE bit is set, then an interrupt is generated. THRE is set when the contents of the THR are transferred to the transmitted shift register. This bit is cleared concurrent with the loading of the THR by the CPU. In the FIFO mode, this bit is set when the transmit FIFO is empty; it is cleared when at least 1 byte is written to the transmit FIFO.

†

(continued)

Bit 6: This bit is the transmitter empty (TEMT) indicator. Bit 6 is set when the THR and the TSR are both empty. When either the THR or the TSR contains a data character, the TEMT bit is cleared. In the FIFO mode, this bit is set when the transmitter FIFO and shift register are both empty.

Bit 7: In the TL16C550A, this bit is always cleared. In the TL16C450 mode, this bit is cleared. In the FIFO mode, LSR7 is set when there is at least one parity , framing, or break error in the FIFO. It is cleared when the microprocessor reads the LSR and there are no subsequent errors in the FIFO.

modem control register (MCR)

The MCR is an 8-bit register that controls an interface with a modem, data set, or peripheral device that is emulating a modem. The contents of this register are summarized in T able 3 and are described in the following bulleted list.

Bit 0: This bit (DTR) controls the data terminal ready (DTR) output. Setting bit 0 forces the DTR output to its low state. When bit 0 is cleared, DTR

Bit 1: This bit (RTS) controls the request to send (R TS) output in a manner identical to bit 0’ s control over the DTR

Bit 2: This bit (OUT1) controls the output 1 (OUT1) signal, a user-designated output signal, in a manner identical to bit 0’s control over the DTR

output.

goes high.

output.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

modem control register (MCR) (continued)

Bit 3: This bit (OUT2) controls the output 2 (OUT2) signal, a user-designated output signal, in a manner identical to bit 0’s control over the DTR

Bit 4: This bit provides a local loopback feature for diagnostic testing of the ACE. When bit 4 is set, the following occurs:

1. The SOUT is set high.

2. The SIN is disconnected.

3. The output of the TSR is looped back into the RSR input.

4. The four modem control inputs (CTS

5. The four modem control outputs (DTR modem control inputs.

6. The four modem control output terminals are forced to their inactive states (high).

In the diagnostic mode, data that is transmitted is immediately received. This allows the processor to verify the transmit and receive data paths to the ACE. The receiver and transmitter interrupts are fully operational. The modem control interrupts are also operational but the modem control interrupt’s sources are now the lower four bits of the MCR instead of the four modem control inputs. All interrupts are still controlled by the IER.

output.

TL16C550A

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

, DSR, DCD, and RI) are disconnected.

, RTS, OUT1, and OUT2) are internally connected to the four

Bit 5 – 7: These bits are permanently cleared.

modem status register (MSR)

The MSR is an 8-bit register that provides information about the current state of the control lines from the modem, data set, or peripheral device to the CPU. Additionally, four bits of this register provide change information; when a control input from the modem changes state, the appropriate bit is set. All four bits are cleared when the CPU reads the MSR. The contents of this register are summarized in Table 3 and are described in the following bulleted list.

Bit 0: This bit is the change in clear to send (∆CTS) indicator . Bit 0 indicates that the CTS input has changed states since the last time it was read by the CPU . When this bit is set and the modem status interrupt is enabled, a modem status interrupt is generated.

Bit 1: This bit is the change in data set ready (∆DSR) indicator. Bit 1 indicates that the DSR input has changed states since the last time it was read by the CPU. When this bit is set and the modem status interrupt is enabled, a modem status interrupt is generated.

Bit 2: This bit is the trailing edge of ring indicator (TERI) detector . Bit 2 indicates that the RI input to the chip has changed from a low to a high state. When this bit is set and the modem status interrupt is enabled, a modem status interrupt is generated.

Bit 3: This bit is the change in data carrier detect (∆DCD) indicator. Bit 3 indicates that the DCD input to the chip has changed states since the last time it was read by the CPU. When this bit is set and the modem status interrupt is enabled, a modem status interrupt is generated.

Bit 4: This bit is the compliment of the clear to send (CTS) input. When bit 4 (loop) of the MCR is set, bit 4 is equivalent to the MCR bit 1 (RTS).

Bit 5: This bit is the compliment of the data set ready (DSR) input. When bit 4 (loop) of the MCR is set, bit 5 is equivalent to the MCR bit 1 (DTR).

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C550A ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

PRINCIPLES OF OPERATION

modem status register (MSR) (continued)

Bit 6: This bit is the compliment of the ring indicator (RI) input. When bit 4 (loop) of the MCR is set, bit 6 is equivalent to the MCR bit 2 (OUT1).

Bit 7: This bit is the compliment of the data carrier detect (DCD) input. When bit 4 (loop) of the MCR is set, bit 7 is equivalent to the MCR bit 3 (OUT2).

programmable baud generator

The ACE contains a programmable baud generator that takes a clock input in the range between dc and 8 MHz

and divides it by a divisor in the range between 1 and (2

–1). The output frequency of the baud generator is

16× the baud rate. The formula for the divisor is:

divisor # = XIN frequency input ÷ (desired baud rate × 16)

Two 8-bit registers, called divisor latches, store the divisor in a 16-bit binary format. These divisor latches must be loaded during initialization of the ACE in order to ensure desired operation of the baud generator. When either of the divisor latches is loaded, a 16-bit baud counter is also loaded to prevent long counts on initial load.

Tables 8 and 9, which follow, illustrate the use of the baud generator with crystal frequencies of 1.8432 MHz and 3.072 MHz, respectively For baud rates of 38.4 kbit/s and below, the error obtained is very small. The accuracy of the selected baud rate is dependent on the selected crystal frequency.

Refer to Figure 16 for examples of typical clock circuits.

Table 8. Baud Rates Using a 1.8432-MHz Crystal

DESIRED

BAUD RATE

50 2304 75 1536

110 1047 0.026

134.5 857 0.058 150 768 300 384 600 192

1200 96 1800 64 2000 58 0.69 2400 48 3600 32 4800 24 7200 16

9600 12 19200 6 38400 3 56000 2 2.86

DIVISOR USED TO GENERATE

16× CLOCK

PERCENT ERROR

DIFFERENCE BETWEEN

DESIRED AND ACTUAL

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

programmable baud generator (continued)

Table 9. Baud Rates Using a 3.072-MHz Crystal

TL16C550A

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

External

Clock

Driver

XIN

DESIRED

BAUD RATE

50 3840 75 2560

110 1745 0.026

134.5 1428 0.034 150 1280 300 640 600 320

1200 160 1800 107 0.312 2000 96 2400 80 3600 53 0.628 4800 40 7200 27 1.23

9600 20 19200 10 38400 5

DIVISOR USED TO GENERATE

16× CLOCK

PERCENT ERROR

DIFFERENCE BETWEEN

DESIRED AND ACTUAL

XIN

Optional

Clock

Output

Optional Driver

XOUT

Crystal

Oscillator Clock to Baud Generator Logic

TYPICAL CRYSTAL OSCILLATOR NETWORK

CRYSTAL

3.1 MHz 1 MΩ 1.5 kΩ 10–30 pF 40–60 pF

1.8 MHz 1 MΩ 1.5 kΩ 10–30 pF 40–60 pF

RX2 C1 C2

RX2

XOUT

Figure 16. Typical Clock Circuits

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Oscillator Clock to Baud Generator Logic

TL16C550A ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

receiver buffer register (RBR)

The ACE receiver section consists of a receiver shift register (RSR) and a RBR. The RBR is actually a 16-byte FIFO. Timing is supplied by the 16× receiver clock (RCLK). Receiver section control is a function of the ACE line control register.

The ACEs RSR receives serial data from the SIN terminal. The RSR then deserializes the data and moves it into the RBR FIFO. In the TL16C450 mode, when a character is placed in the RBR and the received data available interrupt is enabled, an interrupt is generated. This interrupt is cleared when the data is read out of the RBR. in the FIFO mode, the interrupts are generated based on the control setup in the FIFO control register.

scratch register

The scratch register is an 8-bit register that is intended for the programmer’s use as a scratchpad in the sense that it temporarily holds the programmer’s data without affecting any other ACE operation.

transmitter holding register (THR)

The ACE transmitter section consists of a THR and a transmitter shift register (TSR). The THR is actually a 16-byte FIFO. Timing is suppled by the baud out (BAUDOUT function of the ACE line control register.

) clock signal. Transmitter section control is a

The ACE THR receives data off the internal data bus and, when the shift register is idle, moves it into the TSR. The TSR serializes the data and outputs it at the serial output (SOUT). In the TL16C450 mode, when the THR is empty and the transmitter holding register empty (THRE) interrupt is enabled, an interrupt is generated. This interrupt is cleared when a character is loaded into the register. In the FIFO mode, the interrupts are generated based on the control setup in the FIFO control register.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

T exas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current and complete.

TI warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (“Critical Applications”).

TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.

Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI products in such applications requires the written approval of an appropriate TI officer . Questions concerning potential risk applications should be directed to TI through a local SC sales office.

In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards should be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does TI warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used.

TEXAS INSTRUMENTS TL16C550A Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual