Texas Instruments TL16C450N, TL16C450FNR, TL16C450FN Datasheet

TL16C450

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS037B – MARCH 1988 – REVISED MARCH 1996

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Programmable Baud Rate Generator Allows
Division of Any Input Reference Clock by 1
to (2

16

–1) and Generates an Internal 16×

Clock

D

Full Double Buffering Eliminates the Need
for Precise Synchronization

D

Standard Asynchronous Communication
Bits (Start, Stop, and Parity) Added or
Deleted to or From the Serial Data Stream

D

Independent Receiver Clock Input

D

Transmit, Receive, Line Status, and Data
Set Interrupts Independently Controlled

D

Fully Programmable Serial Interface
Characteristics:
– 5-, 6-, 7-, or 8-Bit Characters
– Even-, Odd-, or No-Parity Bit Generation

and Detection
– 1-, 1 1/2-, or 2-Stop Bit Generation
– Baud Generation (dc to 256 Kbit/s)

D

False Start Bit Detection

D

Complete Status Reporting Capabilities

D

3-State TTL Drive Capabilities for
Bidirectional Data Bus and Control Bus

D

Line Break Generation and Detection

D

Internal Diagnostic Capabilities:
– Loopback Controls for Communications

Link Fault Isolation
– Break, Parity , Overrun, Framing Error

Simulation

D

Fully Prioritized Interrupt System Controls

D

Modem Control Functions (CTS, RTS, DSR,
DTR

, RI, and DCD)

D

Easily Interfaces to Most Popular
Microprocessors

D

Faster Plug-In Replacement for National
Semiconductor NS16C450

description

The TL16C450 is a CMOS version of an asynchronous communications element (ACE). It typically functions
in a microcomputer system as a serial input/output interface.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

D0
D1
D2
D3
D4
D5
D6
D7

RCLK

SIN

SOUT

CS0
CS1
CS2

BAUDOUT

XTAL1

XTAL2
DOSTR
DOSTR

V

SS

V

CC

RI
DCD
DSR
CTS
MR
OUT1
DTR
RTS
OUT2
INTRPT
NC
A0
A1
A2
ADS
CSOUT
DDIS
DISTR
DISTR

N PACKAGE
(TOP VIEW)

MR
OUT1
DTR
RTS
OUT2
NC
INTRP

T

NC
A0
A1
A2

39
38
37
36
35
34
33
32
31
30
29

1819

7
8
9
10
11
12
13
14
15
16
17

D5
D6
D7

RCLK

SIN

NC

SOUT

CS0
CS1
CS2

AUDOUT

20 21 22 23

FN PACKAGE

(TOP VIEW)

RI

DCD

DSR

CTS

54 321644

D4D3D2D1D0

NC

DISTR

DDIS

CSOUT

ADS

XTAL1

XTAL2

DOSTR

DOSTR

NC

DISTR

42 41 4043

24 25 26 27 28

C – No internal connection

V

CC

V

SS

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Copyright  1996, Texas Instruments Incorporated

TL16C450
ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS037B – MARCH 1988 – REVISED MARCH 1996

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description (continued)

The TL16C450 performs serial-to-parallel conversion on data received from a peripheral device or modem and
parallel-to-serial conversion on data received from its CPU. The CPU can read and report on the status of the

ACE at any point in the ACE’s operation. Reported status information includes the type of transfer operation
in progress, the status of the operation, and any error conditions encountered.

The TL16C450 ACE includes a programmable, on-board, baud rate generator. This generator is capable of
dividing a reference clock input by divisors from 1 to (2

16

–1) and producing a 16×clock for driving the internal
transmitter logic. Provisions are included to use this 16× clock to drive the receiver logic. Also included in the
ACE is a complete modem control capability and a processor interrupt system that may be software tailored
to the user’s requirements to minimize the computing required to handle the communications link.

TL16C450

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS037B – MARCH 1988 – REVISED MARCH 1996

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

block diagram

Receiver

Buffer

Register

Line

Control

Register

Divisor

Latch (LS)

32
36
33
37
38
39
34
31

11

15

9

10

28
27
26

12
13
14
25
35
22
21
19
18
23
24
16
17

1–8

30

A0
A1
A2

CS0
CS1
CS2

ADS

MR
DISTR
DISTR

DOSTR
DOSTR

CSOUT

XTAL1
XTAL2

D7–D0

DDIS

RTS
CTS
DTR
DSR
DCD
RI
OUT1
OUT2

SOUT

BAUDOUT

RCLK

SIN

INTRPT

V

CC

V

SS

40
20

Divisor

Latch (MS)

Line

Status

Register

Transmitter

Holding

Register

Modem
Control

Register

Modem

Status

Register

Interrupt

Enable

Register

Interrupt

I/O

Register

Interrupt

Control

Logic

Baud

Generator

Receiver

Shift

Register

Receiver

Timing and

Control

Data

Bus

Buffer

Internal

Data Bus

Transmitter
Timing and

Control

Transmitter

Shift

Register

Modem
Control

Logic

Power

Supply

Select

and

Control

Logic

Terminal numbers shown are for the N package.

TL16C450
ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS037B – MARCH 1988 – REVISED MARCH 1996

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NAME NO.

†

I/O

DESCRIPTION

A0
A1
A2

28
27
26

I Register select. A0, A1, and A2 are three inputs used during read and write operations to select the ACE register

to read from or write to. Refer to Table 1 for register addresses, also refer to the address strobe (ADS

) signal

description.

ADS

25 I

Address strobe. When ADS is active (low), the register select signals (A0, A1, and A2) and chip select signals
(CS0, CS1, CS2

) drive the internal select logic directly; when high, the register select and chip select signals are

held in the state they were in when the low-to-high transition of ADS

occurred.

BAUDOUT

15 O

Baud out. BAUDOUT is a16× clock signal for the transmitter section of the ACE. The clock rate is established
by the reference oscillator frequency divided by a divisor specified by the baud generator divisor latches.
BAUDOUT

may also be used for the receiver section by tying this output to the RCLK input.

CS0
CS1
CS2

12
13
14

I

Chip select. When CSx is active (high, high, and low respectively), the ACE is selected. Refer to the ADS signal
description.

CSOUT 24 O Chip select out. When CSOUT is high, it indicates that the ACE has been selected by the chip select inputs (CS0,

CS1, and CS2

). CSOUT is low when the chip is deselected.

CTS

36 I

Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of the modem
status register. Bit 0 (DCTS) of the modem status register indicates that this signal has changed states since the
last read from the modem status register. If the modem status interrupt is enabled when CTS

changes state, an

interrupt is generated.

D0 – D7 1 – 8 I/O Data bus. D0 – D7 are 3-state data lines that provide a bidirectional path for data, control, and status information

between the ACE and the CPU.

DCD

38 I

Data carrier detect. DCD is a modem status signal. Its condition can be checked by reading bit 7 (DCD) of the
modem status register. Bit 3 (DDCD) of the modem status register indicates that this signal has changed states
since the last read from the modem status register. If the modem status interrupt is enabled when the DCD
changes state, an interrupt is generated.

DDIS 23 O Driver disable. DDIS is active (high) when the CPU is not reading data. When active, this output can disable an

external transceiver.

DISTR
DISTR

22
21

I

Data input strobes. When either DISTR or DISTR is active (high or low respectively) while the ACE is selected,
the CPU is allowed to read status information or data from a selected ACE register. Only one of these inputs is
required for the transfer of data during a read operation. The other input should be tied in its inactive state (i.e.,
DISTR tied low or DISTR

tied high).

DOSTR
DOSTR

19
18

I

Data output strobes. When either DOSTR or DOSTR is active (high or low respectively), while the ACE is
selected, the CPU is allowed to write control words or data into a selected ACE register. Only one of these inputs
is required to transfer data during a write operation. The other input should be tied in its inactive state (i.e., DOSTR
tied low or DOSTR

tied high).

DSR

37 I

Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of the modem
status register. Bit 1 (DDSR) of the modem status register indicates that this signal has changed state since the
last read from the modem status register. If the modem status interrupt is enabled when the DSR

changes state,

an interrupt is generated.

DTR

33 O

Data terminal ready. When active (low), DTR informs a modem or data set that the ACE is ready to establish
communication. DTR

is placed in the active state by setting the DTR bit of the modem control register to a high

level. DTR

is placed in the inactive state either as a result of a master reset or during loop mode operation or

clearing bit 0 (DTR) of the modem control register.

INTRPT 30 O Interrupt. When active (high), INTRPT informs the CPU that the ACE has an interrupt to be serviced. The four

conditions that cause an interrupt are: a receiver error, received data is available, the transmitter holding register
is empty, or an enabled modem status interrupt. The INTRPT output is reset (inactivated) either when the interrupt
is serviced or as a result of a master reset.

MR 35 I Master reset. When active (high), MR clears most ACE registers and sets the state of various output signals.

Refer to Table 2 for ACE reset functions.

†

Terminal numbers shown are for the N package.

TL16C450

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS037B – MARCH 1988 – REVISED MARCH 1996

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions (continued)

TERMINAL

NAME NO.

†

I/O

DESCRIPTION

OUT1
OUT2

34
31

O

Outputs 1 and 2. OUT1 and OUT2 are user-designated output terminals that are set to their active states by
setting their respective modem control register bits (OUT1 and OUT2) high. OUT1

and OUT2 are set to their
inactive (high) states as a result of master reset or during loop mode operations or by clearing bit 2 (OUT1) or
bit 3 (OUT2) of the MCR.

RCLK 9 I Receiver clock. RCLK is the 16× baud rate clock for the receiver section of the ACE.
RI

39 I

Ring indicator. RI is a modem status signal. Its condition can be checked by reading bit 6 (RI) of the modem status
register. Bit 2 (TERI) of the modem status register indicates that the RI

input has transitioned from a low to a high
state since the last read from the modem status register. If the modem status interrupt is enabled when this
transition occurs, an interrupt is generated.

RTS

32 O

Request to send. When active, RTS informs the modem or data set that the ACE is ready to transmit data. RTS
is set to its active state by setting the RTS modem control register bit and is set to its inactive (high) state either
as a result of a master reset or during loop mode operations or by clearing bit 1 (RTS) of the MCR.

SIN 10 I Serial input. SIN is the serial data input from a connected communications device.
SOUT 11 O Serial output. SOUT is the composite serial data output to a connected communication device. SOUT is set to

the marking (set) state as a result of MR.

V

CC

40 5-V supply voltage

V

SS

20 Supply common

XTAL1
XTAL2

1617I/O External clock. XTAL1 and XTAL2 connect the ACE to the main timing reference (clock or crystal).

†

Terminal numbers shown are for the N package.

absolute maximum ratings over free-air temperature range (unless otherwise noted)

†

Supply voltage range, V

CC

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range at any input, V

I

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, V

O

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total power dissipation at (or below) 70°C free-air temperature: FN package 1100 mW. . . . . . .

N package 800 mW. . . . . . . . .

Operating free-air temperature range, T

A

0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Case temperature for 10 seconds, T

C

: FN package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package 260°C. . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to VSS.

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage, V

CC

4.75 5 5.25 V

High-level input voltage, V

IH

2 V

CC

V

Low-level input voltage, V

IL

–0.5 0.8 V

Operating free-air temperature, T

A

0 70 °C

TL16C450
ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS037B – MARCH 1988 – REVISED MARCH 1996

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

V

OH

‡

HIgh-level output voltage IOH = –1 mA 2.4 V

V

OL

‡

Low-level output voltage IOL = 1.6 mA 0.4 V

p

V

= 5.25 V , V

= 0,

I

Ikg

Input leakage current

CC

,

SS

,

VI = 0 to 5.25 V, All other terminals floating

±10µA

p

p

VCC = 5.25 V , VSS = 0,

IOZHigh-impedance output current

V

O

= 0 V to 5.25 V,

Chip selected, write mode,or chip deselected

±20µA

=

=

°

pp

V

CC

= 5.25 V,

T

A

=

25 C

,

SIN, DSR, DCD, CTS, and RI at 2 V,

ICCSupply current

,,,, ,

All other inputs at 0.8 V , Baud rate = 50 kbits/s,

10

mA

XTAL1 at 4 MHz, No load on outputs

C

XTAL1

Clock input capacitance 15 20 pF

C

XTAL2

Clock output capacitance

VCC = 0, VSS = 0,

°

20 30 pF

C

i

Input capacitance

f

= 1

MHz

,

T

A

=

25°C

,

All other terminals

g

rounded

6 10 pF

C

o

Output capacitance

All other terminals grounded

10 20 pF

†

All typical values are at VCC = 5 V, TA = 25°C.

‡

These parameters apply for all outputs except XTAL2.

system timing requirements over recommended ranges of supply voltage and operating free-air
temperature

PARAMETER FIGURE MIN MAX UNIT

t

cR

Cycle time, read (tw7 + td8 + td9) 175 ns

t

cW

Cycle time, write (tw6 + td5 + td6) 175 ns

t

w5

Pulse duration, ADS low 2,3 15 ns

t

w6

Pulse duration, write strobe 2 80 ns

t

w7

Pulse duration, read strobe 3 80 ns

t

wMR

Pulse duration, master reset 1000 ns

t

su1

Setup time, address valid before ADS↑ 2,3 15 ns

t

su2

Setup time, CS valid before ADS↑ 2,3 15 ns

t

su3

Setup time, data valid before WR1↓ or WR2↑ 2 15 ns

t

h1

Hold time, address low after ADS↑ 2,3 0 ns

t

h2

Hold time, CS valid after ADS↑ 2,3 0 ns

t

h3

Hold time, CS valid after WR1↑ or WR2↓ 2 20 ns

t

h4

§

Hold time, address valid after WR1↑ or WR2↓ 2 20 ns

t

h5

Hold time, data valid after WR1↑ or WR2↓ 2 15 ns

t

h6

Hold time, CS valid after RD1↑ or RD2↓

3 20 ns

t

h7

§

Hold time, address valid after RD1↑ or RD2↓ 3 20 ns

t

d4

§

Delay time, CS valid before WR1↓ or WR2↑ 2 15 ns

t

d5

§

Delay time, address valid before WR1↓ or WR2↑ 2 15 ns

t

d6

Delay time, write cycle, WR1↑ or WR2↓ to ADS↓ 2 80 ns

t

d7

§

Delay time, CS valid to RD1↓ or RD2↑ 3 15 ns

t

d8

§

Delay time, address valid to RD1↓ or RD2↑ 3 15 ns

t

d9

Delay time, read cycle, RD1↑ or RD2↓ to ADS↓ 3 80 ns

§

Only applies when ADS is low.

TL16C450

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS037B – MARCH 1988 – REVISED MARCH 1996

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

system switching characteristics over recommended ranges of supply voltage and operating
free-air temperature

PARAMETER FIGURE TEST CONDITIONS MIN MAX UNIT

t

w1

Pulse duration, clock high 1 f = 9 MHz maximum 50 ns

t

w2

Pulse duration, clock low 1 f = 9 MHz maximum 50 ns

t

d3

Delay time, select to CS output 2,3

†

CL = 100 pF 70 ns

t

d10

Delay time, RD1↓ or RD2↑ to data valid 3 CL = 100 pF 60 ns

t

d11

Delay time, RD1↑ or RD2↓ to floating data 3 CL = 100 pF 0 60 ns

t

dis(R)

Disable time, RD1↓↑ or RD2↑↓ to DDIS↑↓ 3 CL = 100 pF 60 ns

†

Only applies when ADS is low.

baud generator switching characteristics over recommended ranges of supply voltage and
operating free-air temperature

PARAMETER FIGURE TEST CONDITIONS MIN MAX UNIT

f = 6.25 MHz, CLK ÷ 1,

t

w3

Pul

se duration,

BAUDOUT l

ow

1

, ,

CL = 100 pF

80

ns

f = 6.25 MHz, CLK ÷ 1,

t

w4

Pul

se duration,

BAUDOUT high

1

, ,

CL = 100 pF

80

ns

t

d1

Delay time, XIN↑ to BAUDOUT↑ 1 CL = 100 pF 125 ns

t

d2

Delay time, XIN↑↓ to BAUDOUT↓ 1 CL = 100 pF 125 ns

receiver switching characteristics over recommended ranges of supply voltage and operating
free-air temperature

PARAMETER FIGURE TEST CONDITIONS MIN MAX UNIT

t

d12

Delay time, RCLK to sample clock 4 100 ns
Delay time, stop to set RCV error interrupt or read

p

p

RCLK

t

d13

RDR to LSI interrupt or stop to

RXRDY

↓

411

cycles

t

d14

Delay time, read RBR/LSR to reset interrupt 4 CL = 100 pF 140 ns

transmitter switching characteristics over recommended ranges of supply voltage and operating
free-air temperature

PARAMETER FIGURE TEST CONDITIONS MIN MAX UNIT

baudout

t

d15

Delay time, INTRPT to transmit start

5824

cycles

p

baudout

t

d16

Delay time, start to interrupt

588

cycles

t

d17

Delay time, WR THR to reset interrupt 5 CL = 100 pF 140 ns

p

baudout

t

d18

Delay time, initial write to interrupt (THRE)

51632

cycles

t

d19

Delay time, read IIR to reset interrupt (THRE) 5 CL = 100 pF 140 ns

TL16C450
ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS037B – MARCH 1988 – REVISED MARCH 1996

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

modem control switching characteristics over recommended ranges of supply voltage and
operating free-air temperature

PARAMETER FIGURE TEST CONDITIONS MIN MAX UNIT

t

d20

Delay time, WR MCR to output 6 CL = 100 pF 100 ns

t

d21

Delay time, modem interrupt to set interrupt 6 CL = 100 pF 170 ns

t

d22

Delay time, RD MSR to reset interrupt 6 CL = 100 pF 140 ns

PARAMETER MEASUREMENT INFORMATION

(N-2) XTAL1

Cycles

2XTAL1

Cycles

t

w1

t

w2

2 V

0.8 V

N

t

d2

t

d1

t

d1

t

d2

t

w3

t

w4

RCLK

(9 MHz Max)

XTAL1

BAUDOUT

(1/1)

BAUDOUT

(1/2)

BAUDOUT

(1/3)

BAUDOUT

(1/N)

(N>3)

90%

90%

10%

Figure 1. Baud Generator Timing Waveforms