TEXAS INSTRUMENTS TL16C450 Technical data

T

查询TL16C450供应商

TL16C450

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS037B – MARCH 1988 – REVISED MARCH 1996

D

Programmable Baud Rate Generator Allows
Division of Any Input Reference Clock by 1

16

to (2

–1) and Generates an Internal 16×

Clock

D

Full Double Buffering Eliminates the Need
for Precise Synchronization

D

Standard Asynchronous Communication
Bits (Start, Stop, and Parity) Added or
Deleted to or From the Serial Data Stream

D

Independent Receiver Clock Input

D

Transmit, Receive, Line Status, and Data
Set Interrupts Independently Controlled

D

Fully Programmable Serial Interface
Characteristics:
– 5-, 6-, 7-, or 8-Bit Characters
– Even-, Odd-, or No-Parity Bit Generation

and Detection
– 1-, 1 1/2-, or 2-Stop Bit Generation
– Baud Generation (dc to 256 Kbit/s)

D

False Start Bit Detection

D0
D1
D2
D3
D4
D5
D6
D7

RCLK

SIN

SOUT

CS0
CS1
CS2

BAUDOUT

XT AL1

XT AL2
DOSTR
DOSTR

V

SS

N PACKAGE
(TOP VIEW)

1

40

2

39

3

38

4

37

5

36

6

35

7

34

8

33

9

32

10

31

11

30

12

29

13

28

14

27

15

26

16

25

17

24

18

23

19

22

20

21

V

CC

RI
DCD
DSR
CTS
MR
OUT1
DTR
RTS
OUT2
INTRPT
NC
A0
A1
A2
ADS
CSOUT
DDIS
DISTR
DISTR

D

Complete Status Reporting Capabilities

D

3-State TTL Drive Capabilities for

FN PACKAGE

(TOP VIEW)

Bidirectional Data Bus and Control Bus

CC

RI

DCD

42 41 4043

DDIS

DISTR

DSR

CSOUT

D

Line Break Generation and Detection

D

Internal Diagnostic Capabilities:
– Loopback Controls for Communications

Link Fault Isolation

– Break, Parity, Overrun, Framing Error

Simulation

D

Fully Prioritized Interrupt System Controls

D

Modem Control Functions (CTS, RTS, DSR,

, RI, and DCD)

DTR

D

Easily Interfaces to Most Popular
Microprocessors

D

Faster Plug-In Replacement for National
Semiconductor NS16C450

description

The TL16C450 is a CMOS version of an asynchronous communications element (ACE). It typically functions

D5
D6
D7

RCLK

SIN

NC

SOUT

CS0
CS1
CS2

AUDOUT

C – No internal connection

D4D3D2D1D0

54 321644

7
8
9
10
11
12
13
14
15
16
17

20 21 22 23

1819

XT AL1

XT AL2

DOSTR

SS

V

DOSTR

NC

V

24 25 26 27 28

NC

DISTR

in a microcomputer system as a serial input/output interface.

CTS

39

MR

38

OUT1

37

DTR

36

RTS

35

OUT2

34

NC

33

INTRP

32

NC

31

A0

30

A1

29

A2

ADS

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1996, Texas Instruments Incorporated

1

TL16C450
ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS037B – MARCH 1988 – REVISED MARCH 1996

description (continued)

The TL16C450 performs serial-to-parallel conversion on data received from a peripheral device or modem and
parallel-to-serial conversion on data received from its CPU. The CPU can read and report on the status of the

ACE at any point in the ACE’s operation. Reported status information includes the type of transfer operation
in progress, the status of the operation, and any error conditions encountered.

The TL16C450 ACE includes a programmable, on-board, baud rate generator. This generator is capable of
dividing a reference clock input by divisors from 1 to (2
transmitter logic. Provisions are included to use this 16× clock to drive the receiver logic. Also included in the
ACE is a complete modem control capability and a processor interrupt system that may be software tailored
to the user’s requirements to minimize the computing required to handle the communications link.

16

–1) and producing a 16×clock for driving the internal

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

block diagram

D7–D0

1–8

Data

Bus

Buffer

Internal

Data Bus

Receiver

Buffer

Register

TL16C450

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS037B – MARCH 1988 – REVISED MARCH 1996

Receiver

Shift

Register

10

SIN

A0
A1
A2

CS0
CS1
CS2

ADS

MR
DISTR
DISTR

DOSTR
DOSTR

DDIS

CSOUT

XTAL1
XTAL2

V

CC

V

SS

28
27
26

12
13
14
25
35
22
21
19
18
23
24

16

17

40
20

Select

and

Control

Logic

Power

Supply

Line

Control

Register

Divisor

Latch (LS)

Divisor

Latch (MS)

Line

Status

Register

Transmitter

Holding

Register

Modem
Control

Register

Modem

Status

Register

Interrupt

Enable

Register

Interrupt

I/O

Register

Baud

Generator

Interrupt

Control

Logic

Receiver

Timing and

Control

Transmitter
Timing and

Control

Transmitter

Shift

Register

Modem
Control

Logic

30

9

15

11

32
36
33
37
38
39
34
31

RCLK

BAUDOUT

SOUT

RTS
CTS
DTR
DSR
DCD
RI
OUT1
OUT2

INTRPT

Terminal numbers shown are for the N package.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

TL16C450

I/O

DESCRIPTION

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS037B – MARCH 1988 – REVISED MARCH 1996

Terminal Functions

TERMINAL

NAME NO.

A0
A1
A2

ADS

BAUDOUT

CS0
CS1
CS2

CSOUT 24 O Chip select out. When CSOUT is high, it indicates that the ACE has been selected by the chip select inputs (CS0,

CTS

D0 – D7 1 – 8 I/O Data bus. D0 – D7 are 3-state data lines that provide a bidirectional path for data, control, and status information

DCD

DDIS 23 O Driver disable. DDIS is active (high) when the CPU is not reading data. When active, this output can disable an

DISTR
DISTR

DOSTR
DOSTR

DSR

DTR

INTRPT 30 O Interrupt. When active (high), INTRPT informs the CPU that the ACE has an interrupt to be serviced. The four

MR 35 I Master reset. When active (high), MR clears most ACE registers and sets the state of various output signals.

†

Terminal numbers shown are for the N package.

†

28
27
26

25 I

15 O

12
13
14

36 I

38 I

22
21

19
18

37 I

33 O

I Register select. A0, A1, and A2 are three inputs used during read and write operations to select the ACE register

to read from or write to. Refer to Table 1 for register addresses, also refer to the address strobe (ADS
description.

Address strobe. When ADS is active (low), the register select signals (A0, A1, and A2) and chip select signals
(CS0, CS1, CS2
held in the state they were in when the low-to-high transition of ADS

Baud out. BAUDOUT is a16× clock signal for the transmitter section of the ACE. The clock rate is established
by the reference oscillator frequency divided by a divisor specified by the baud generator divisor latches.
BAUDOUT

I

Chip select. When CSx is active (high, high, and low respectively), the ACE is selected. Refer to the ADS signal
description.

CS1, and CS2
Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of the modem

status register. Bit 0 (DCTS) of the modem status register indicates that this signal has changed states since the
last read from the modem status register. If the modem status interrupt is enabled when CTS
interrupt is generated.

between the ACE and the CPU.
Data carrier detect. DCD is a modem status signal. Its condition can be checked by reading bit 7 (DCD) of the

modem status register. Bit 3 (DDCD) of the modem status register indicates that this signal has changed states
since the last read from the modem status register. If the modem status interrupt is enabled when the DCD
changes state, an interrupt is generated.

external transceiver.

I

Data input strobes. When either DISTR or DISTR is active (high or low respectively) while the ACE is selected,
the CPU is allowed to read status information or data from a selected ACE register. Only one of these inputs is
required for the transfer of data during a read operation. The other input should be tied in its inactive state (i.e.,
DISTR tied low or DISTR

I

Data output strobes. When either DOSTR or DOSTR is active (high or low respectively), while the ACE is
selected, the CPU is allowed to write control words or data into a selected ACE register. Only one of these inputs
is required to transfer data during a write operation. The other input should be tied in its inactive state (i.e., DOSTR
tied low or DOSTR

Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of the modem
status register. Bit 1 (DDSR) of the modem status register indicates that this signal has changed state since the
last read from the modem status register. If the modem status interrupt is enabled when the DSR
an interrupt is generated.

Data terminal ready. When active (low), DTR informs a modem or data set that the ACE is ready to establish
communication. DTR
level. DTR
clearing bit 0 (DTR) of the modem control register.

conditions that cause an interrupt are: a receiver error, received data is available, the transmitter holding register
is empty, or an enabled modem status interrupt. The INTRPT output is reset (inactivated) either when the interrupt
is serviced or as a result of a master reset.

Refer to Table 2 for ACE reset functions.

) drive the internal select logic directly; when high, the register select and chip select signals are

occurred.

may also be used for the receiver section by tying this output to the RCLK input.

). CSOUT is low when the chip is deselected.

changes state, an

tied high).

tied high).

is placed in the active state by setting the DTR bit of the modem control register to a high

is placed in the inactive state either as a result of a master reset or during loop mode operation or

) signal

changes state,

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

I/O

DESCRIPTION

TL16C450

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS037B – MARCH 1988 – REVISED MARCH 1996

Terminal Functions (continued)

TERMINAL

NAME NO.

OUT1
OUT2

RCLK 9 I Receiver clock. RCLK is the 16× baud rate clock for the receiver section of the ACE.
RI

RTS

SIN 10 I Serial input. SIN is the serial data input from a connected communications device.
SOUT 11 O Serial output. SOUT is the composite serial data output to a connected communication device. SOUT is set to

V

CC

V

SS
XTAL1
XTAL2

†

Terminal numbers shown are for the N package.

†

34
31

39 I

32 O

40 5-V supply voltage
20 Supply common
1617I/O External clock. XTAL1 and XTAL2 connect the ACE to the main timing reference (clock or crystal).

O

Outputs 1 and 2. OUT1 and OUT2 are user-designated output terminals that are set to their active states by
setting their respective modem control register bits (OUT1 and OUT2) high. OUT1
inactive (high) states as a result of master reset or during loop mode operations or by clearing bit 2 (OUT1) or
bit 3 (OUT2) of the MCR.

Ring indicator. RI is a modem status signal. Its condition can be checked by reading bit 6 (RI) of the modem status
register. Bit 2 (TERI) of the modem status register indicates that the RI
state since the last read from the modem status register. If the modem status interrupt is enabled when this
transition occurs, an interrupt is generated.

Request to send. When active, RTS informs the modem or data set that the ACE is ready to transmit data. RTS
is set to its active state by setting the RTS modem control register bit and is set to its inactive (high) state either
as a result of a master reset or during loop mode operations or by clearing bit 1 (RTS) of the MCR.

the marking (set) state as a result of MR.

input has transitioned from a low to a high

and OUT2 are set to their

absolute maximum ratings over free-air temperature range (unless otherwise noted)

Supply voltage range, V
Input voltage range at any input, V
Output voltage range, V

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

†

Continuous total power dissipation at (or below) 70°C free-air temperature: FN package 1100 mW. . . . . . .

N package 800 mW. . . . . . . . .

Operating free-air temperature range, T
Storage temperature range, T

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

Case temperature for 10 seconds, T

0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A

: FN package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package 260°C. . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to VSS.

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage, V
High-level input voltage, V
Low-level input voltage, V
Operating free-air temperature, T

CC

IH

IL

A

4.75 5 5.25 V
2 V

–0.5 0.8 V

0 70 °C

CC

V

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

TL16C450

I

Input leakage current

CC

,

SS

,

±10µA

IOZHigh-impedance output current

V

O

±20µA

V

CC

T

A

25 C

ICCSupply current

,,,, ,

10

mA

f

MHz

T

A

25°C

g

All other terminals grounded

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS037B – MARCH 1988 – REVISED MARCH 1996

electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

‡

V

OH

V

OL

Ikg

C

XTAL1

C

XTAL2

C

i

C

o

†

All typical values are at VCC = 5 V, TA = 25°C.

‡

These parameters apply for all outputs except XTAL2.

HIgh-level output voltage IOH = –1 mA 2.4 V

‡

Low-level output voltage IOL = 1.6 mA 0.4 V

V

p

p

pp

Clock input capacitance 15 20 pF
Clock output capacitance
Input capacitance
Output capacitance

p

= 5.25 V, V

VI = 0 to 5.25 V, All other terminals floating
VCC = 5.25 V, VSS = 0,

= 0 V to 5.25 V,

Chip selected, write mode,or chip deselected

=

= 5.25 V,
SIN, DSR, DCD, CTS, and RI at 2 V,
All other inputs at 0.8 V , Baud rate = 50 kbits/s,
XTAL1 at 4 MHz, No load on outputs

VCC = 0, VSS = 0,

= 1

All other terminals

,

rounded

=

=

=

= 0,

°

,

,

°

20 30 pF

6 10 pF

10 20 pF

system timing requirements over recommended ranges of supply voltage and operating free-air
temperature

PARAMETER FIGURE MIN MAX UNIT

t

cR

t

cW

t

w5

t

w6

t

w7

t

wMR

t

su1

t

su2

t

su3

t

h1

t

h2

t

h3

t

h4

t

h5

t

h6

t

h7

t

d4

t

d5

t

d6

t

d7

t

d8

t

d9

§

Only applies when ADS is low.

Cycle time, read (tw7 + td8 + td9) 175 ns
Cycle time, write (tw6 + td5 + td6) 175 ns
Pulse duration, ADS low 2,3 15 ns
Pulse duration, write strobe 2 80 ns
Pulse duration, read strobe 3 80 ns
Pulse duration, master reset 1000 ns
Setup time, address valid before ADS↑ 2,3 15 ns
Setup time, CS valid before ADS↑ 2,3 15 ns
Setup time, data valid before WR1↓ or WR2↑ 2 15 ns
Hold time, address low after ADS↑ 2,3 0 ns
Hold time, CS valid after ADS↑ 2,3 0 ns
Hold time, CS valid after WR1↑ or WR2↓ 2 20 ns

§

Hold time, address valid after WR1↑ or WR2↓ 2 20 ns
Hold time, data valid after WR1↑ or WR2↓ 2 15 ns
Hold time, CS valid after RD1↑ or RD2↓

§

Hold time, address valid after RD1↑ or RD2↓ 3 20 ns

§

Delay time, CS valid before WR1↓ or WR2↑ 2 15 ns

§

Delay time, address valid before WR1↓ or WR2↑ 2 15 ns
Delay time, write cycle, WR1↑ or WR2↓ to ADS↓ 2 80 ns

§

Delay time, CS valid to RD1↓ or RD2↑ 3 15 ns

§

Delay time, address valid to RD1↓ or RD2↑ 3 15 ns
Delay time, read cycle, RD1↑ or RD2↓ to ADS↓ 3 80 ns

3 20 ns

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

t

Pul

BAUDOUT l

1

, ,

80

ns

t

Pul

BAUDOUT high

1

, ,

80

ns

t

RDR to LSI interrupt or stop to

411

t

Delay time, INTRPT to transmit start

5824

t

Delay time, start to interrupt

588

t

Delay time, initial write to interrupt (THRE)

51632

TL16C450

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS037B – MARCH 1988 – REVISED MARCH 1996

system switching characteristics over recommended ranges of supply voltage and operating
free-air temperature

PARAMETER FIGURE TEST CONDITIONS MIN MAX UNIT

t

w1

t

w2

t

d3

t

d10

t

d11

t

dis(R)

†

Only applies when ADS is low.

baud generator switching characteristics over recommended ranges of supply voltage and
operating free-air temperature

w3

w4

t

d1

t

d2

Pulse duration, clock high 1 f = 9 MHz maximum 50 ns
Pulse duration, clock low 1 f = 9 MHz maximum 50 ns
Delay time, select to CS output 2,3
Delay time, RD1↓ or RD2↑ to data valid 3 CL = 100 pF 60 ns
Delay time, RD1↑ or RD2↓ to floating data 3 CL = 100 pF 0 60 ns
Disable time, RD1↓↑ or RD2↑↓ to DDIS↑↓ 3 CL = 100 pF 60 ns

PARAMETER FIGURE TEST CONDITIONS MIN MAX UNIT

se duration,

se duration,

Delay time, XIN↑ to BAUDOUT↑ 1 CL = 100 pF 125 ns
Delay time, XIN↑↓ to BAUDOUT↓ 1 CL = 100 pF 125 ns

ow

†

CL = 100 pF 70 ns

f = 6.25 MHz, CLK ÷ 1,
CL = 100 pF

f = 6.25 MHz, CLK ÷ 1,
CL = 100 pF

receiver switching characteristics over recommended ranges of supply voltage and operating
free-air temperature

PARAMETER FIGURE TEST CONDITIONS MIN MAX UNIT

t

d12

d13

t

d14

Delay time, RCLK to sample clock 4 100 ns
Delay time, stop to set RCV error interrupt or read

p

↓

RXRDY
Delay time, read RBR/LSR to reset interrupt 4 CL = 100 pF 140 ns

p

RCLK
cycles

transmitter switching characteristics over recommended ranges of supply voltage and operating
free-air temperature

PARAMETER FIGURE TEST CONDITIONS MIN MAX UNIT

d15

d16

t

d17

d18

t

d19

p

Delay time, WR THR to reset interrupt 5 CL = 100 pF 140 ns

p

Delay time, read IIR to reset interrupt (THRE) 5 CL = 100 pF 140 ns

baudout

cycles

baudout

cycles

baudout

cycles

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7

TL16C450
ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS037B – MARCH 1988 – REVISED MARCH 1996

modem control switching characteristics over recommended ranges of supply voltage and
operating free-air temperature

PARAMETER FIGURE TEST CONDITIONS MIN MAX UNIT

t

d20

t

d21

t

d22

Delay time, WR MCR to output 6 CL = 100 pF 100 ns
Delay time, modem interrupt to set interrupt 6 CL = 100 pF 170 ns
Delay time, RD MSR to reset interrupt 6 CL = 100 pF 140 ns

PARAMETER MEASUREMENT INFORMATION

t

w1

RCLK

(9 MHz Max)

XTAL1

BAUDOUT

(1/1)

BAUDOUT

(1/2)

BAUDOUT

(1/3)

BAUDOUT

(1/N)

(N>3)

90%

t

w3

90%

t

d1

t

d1

2 V

10%

2XTAL1

Cycles

0.8 V
t

w2

N

t

d2

t

d2

t

w4

(N-2) XTAL1

Cycles

Figure 1. Baud Generator Timing Waveforms

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265