TEXAS INSTRUMENTS TL16C450 Technical data

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TL16C450

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS037B – MARCH 1988 – REVISED MARCH 1996

Programmable Baud Rate Generator Allows Division of Any Input Reference Clock by 1

to (2

–1) and Generates an Internal 16×

Clock

Full Double Buffering Eliminates the Need for Precise Synchronization

Standard Asynchronous Communication Bits (Start, Stop, and Parity) Added or Deleted to or From the Serial Data Stream

Independent Receiver Clock Input

Transmit, Receive, Line Status, and Data Set Interrupts Independently Controlled

Fully Programmable Serial Interface Characteristics: – 5-, 6-, 7-, or 8-Bit Characters – Even-, Odd-, or No-Parity Bit Generation

and Detection – 1-, 1 1/2-, or 2-Stop Bit Generation – Baud Generation (dc to 256 Kbit/s)

False Start Bit Detection

D0 D1 D2 D3 D4 D5 D6 D7

RCLK

SIN

SOUT

CS0 CS1 CS2

BAUDOUT

XT AL1

XT AL2 DOSTR DOSTR

N PACKAGE (TOP VIEW)

RI DCD DSR CTS MR OUT1 DTR RTS OUT2 INTRPT NC A0 A1 A2 ADS CSOUT DDIS DISTR DISTR

Complete Status Reporting Capabilities

3-State TTL Drive Capabilities for

FN PACKAGE

(TOP VIEW)

Bidirectional Data Bus and Control Bus

DCD

42 41 4043

DDIS

DISTR

DSR

CSOUT

Line Break Generation and Detection

Internal Diagnostic Capabilities: – Loopback Controls for Communications

Link Fault Isolation

– Break, Parity, Overrun, Framing Error

Simulation

Fully Prioritized Interrupt System Controls

Modem Control Functions (CTS, RTS, DSR,

, RI, and DCD)

DTR

Easily Interfaces to Most Popular Microprocessors

Faster Plug-In Replacement for National Semiconductor NS16C450

description

The TL16C450 is a CMOS version of an asynchronous communications element (ACE). It typically functions

D5 D6 D7

RCLK

SIN

SOUT

CS0 CS1 CS2

AUDOUT

C – No internal connection

D4D3D2D1D0

54 321644

7 8 9 10 11 12 13 14 15 16 17

20 21 22 23

1819

XT AL1

XT AL2

DOSTR

24 25 26 27 28

DISTR

in a microcomputer system as a serial input/output interface.

CTS

OUT1

DTR

RTS

OUT2

INTRP

ADS

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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TL16C450 ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS037B – MARCH 1988 – REVISED MARCH 1996

description (continued)

The TL16C450 performs serial-to-parallel conversion on data received from a peripheral device or modem and parallel-to-serial conversion on data received from its CPU. The CPU can read and report on the status of the

ACE at any point in the ACE’s operation. Reported status information includes the type of transfer operation in progress, the status of the operation, and any error conditions encountered.

The TL16C450 ACE includes a programmable, on-board, baud rate generator. This generator is capable of dividing a reference clock input by divisors from 1 to (2 transmitter logic. Provisions are included to use this 16× clock to drive the receiver logic. Also included in the ACE is a complete modem control capability and a processor interrupt system that may be software tailored to the user’s requirements to minimize the computing required to handle the communications link.

–1) and producing a 16×clock for driving the internal

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block diagram

D7–D0

1–8

Data

Bus

Buffer

Internal

Data Bus

Receiver

Buffer

TL16C450

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS037B – MARCH 1988 – REVISED MARCH 1996

Receiver

Shift

SIN

A0 A1 A2

CS0 CS1 CS2

ADS

MR DISTR DISTR

DOSTR DOSTR

DDIS

CSOUT

XTAL1 XTAL2

28 27 26

12 13 14 25 35 22 21 19 18 23 24

40 20

Select

and

Control

Logic

Power

Supply

Line

Control

Divisor

Latch (LS)

Divisor

Latch (MS)

Line

Status

Transmitter

Holding

Modem Control

Modem

Status

Interrupt

Enable

Interrupt

I/O

Baud

Generator

Interrupt

Control

Logic

Receiver

Timing and

Control

Transmitter Timing and

Control

Transmitter

Shift

Modem Control

Logic

32 36 33 37 38 39 34 31

RCLK

BAUDOUT

SOUT

RTS CTS DTR DSR DCD RI OUT1 OUT2

INTRPT

Terminal numbers shown are for the N package.

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TL16C450

I/O

DESCRIPTION

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS037B – MARCH 1988 – REVISED MARCH 1996

Terminal Functions

TERMINAL

NAME NO.

A0 A1 A2

ADS

BAUDOUT

CS0 CS1 CS2

CSOUT 24 O Chip select out. When CSOUT is high, it indicates that the ACE has been selected by the chip select inputs (CS0,

CTS

D0 – D7 1 – 8 I/O Data bus. D0 – D7 are 3-state data lines that provide a bidirectional path for data, control, and status information

DCD

DDIS 23 O Driver disable. DDIS is active (high) when the CPU is not reading data. When active, this output can disable an

DISTR DISTR

DOSTR DOSTR

DSR

DTR

INTRPT 30 O Interrupt. When active (high), INTRPT informs the CPU that the ACE has an interrupt to be serviced. The four

MR 35 I Master reset. When active (high), MR clears most ACE registers and sets the state of various output signals.

†

Terminal numbers shown are for the N package.

†

28 27 26

25 I

15 O

12 13 14

36 I

38 I

22 21

19 18

37 I

33 O

I Register select. A0, A1, and A2 are three inputs used during read and write operations to select the ACE register

to read from or write to. Refer to Table 1 for register addresses, also refer to the address strobe (ADS description.

Address strobe. When ADS is active (low), the register select signals (A0, A1, and A2) and chip select signals (CS0, CS1, CS2 held in the state they were in when the low-to-high transition of ADS

Baud out. BAUDOUT is a16× clock signal for the transmitter section of the ACE. The clock rate is established by the reference oscillator frequency divided by a divisor specified by the baud generator divisor latches. BAUDOUT

Chip select. When CSx is active (high, high, and low respectively), the ACE is selected. Refer to the ADS signal description.

CS1, and CS2 Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of the modem

status register. Bit 0 (DCTS) of the modem status register indicates that this signal has changed states since the last read from the modem status register. If the modem status interrupt is enabled when CTS interrupt is generated.

between the ACE and the CPU. Data carrier detect. DCD is a modem status signal. Its condition can be checked by reading bit 7 (DCD) of the

modem status register. Bit 3 (DDCD) of the modem status register indicates that this signal has changed states since the last read from the modem status register. If the modem status interrupt is enabled when the DCD changes state, an interrupt is generated.

external transceiver.

Data input strobes. When either DISTR or DISTR is active (high or low respectively) while the ACE is selected, the CPU is allowed to read status information or data from a selected ACE register. Only one of these inputs is required for the transfer of data during a read operation. The other input should be tied in its inactive state (i.e., DISTR tied low or DISTR

Data output strobes. When either DOSTR or DOSTR is active (high or low respectively), while the ACE is selected, the CPU is allowed to write control words or data into a selected ACE register. Only one of these inputs is required to transfer data during a write operation. The other input should be tied in its inactive state (i.e., DOSTR tied low or DOSTR

Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of the modem status register. Bit 1 (DDSR) of the modem status register indicates that this signal has changed state since the last read from the modem status register. If the modem status interrupt is enabled when the DSR an interrupt is generated.

Data terminal ready. When active (low), DTR informs a modem or data set that the ACE is ready to establish communication. DTR level. DTR clearing bit 0 (DTR) of the modem control register.

conditions that cause an interrupt are: a receiver error, received data is available, the transmitter holding register is empty, or an enabled modem status interrupt. The INTRPT output is reset (inactivated) either when the interrupt is serviced or as a result of a master reset.

Refer to Table 2 for ACE reset functions.

) drive the internal select logic directly; when high, the register select and chip select signals are

occurred.

may also be used for the receiver section by tying this output to the RCLK input.

). CSOUT is low when the chip is deselected.

changes state, an

tied high).

is placed in the active state by setting the DTR bit of the modem control register to a high

is placed in the inactive state either as a result of a master reset or during loop mode operation or

) signal

changes state,

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I/O

DESCRIPTION

TL16C450

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS037B – MARCH 1988 – REVISED MARCH 1996

Terminal Functions (continued)

TERMINAL

NAME NO.

OUT1 OUT2

RCLK 9 I Receiver clock. RCLK is the 16× baud rate clock for the receiver section of the ACE. RI

RTS

SIN 10 I Serial input. SIN is the serial data input from a connected communications device. SOUT 11 O Serial output. SOUT is the composite serial data output to a connected communication device. SOUT is set to

SS XTAL1 XTAL2

†

Terminal numbers shown are for the N package.

†

34 31

39 I

32 O

40 5-V supply voltage 20 Supply common 1617I/O External clock. XTAL1 and XTAL2 connect the ACE to the main timing reference (clock or crystal).

Outputs 1 and 2. OUT1 and OUT2 are user-designated output terminals that are set to their active states by setting their respective modem control register bits (OUT1 and OUT2) high. OUT1 inactive (high) states as a result of master reset or during loop mode operations or by clearing bit 2 (OUT1) or bit 3 (OUT2) of the MCR.

Ring indicator. RI is a modem status signal. Its condition can be checked by reading bit 6 (RI) of the modem status register. Bit 2 (TERI) of the modem status register indicates that the RI state since the last read from the modem status register. If the modem status interrupt is enabled when this transition occurs, an interrupt is generated.

Request to send. When active, RTS informs the modem or data set that the ACE is ready to transmit data. RTS is set to its active state by setting the RTS modem control register bit and is set to its inactive (high) state either as a result of a master reset or during loop mode operations or by clearing bit 1 (RTS) of the MCR.

the marking (set) state as a result of MR.

input has transitioned from a low to a high

and OUT2 are set to their

absolute maximum ratings over free-air temperature range (unless otherwise noted)

Supply voltage range, V Input voltage range at any input, V Output voltage range, V

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Continuous total power dissipation at (or below) 70°C free-air temperature: FN package 1100 mW. . . . . . .

N package 800 mW. . . . . . . . .

Operating free-air temperature range, T Storage temperature range, T

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

Case temperature for 10 seconds, T

0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

: FN package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package 260°C. . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to VSS.

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage, V High-level input voltage, V Low-level input voltage, V Operating free-air temperature, T

4.75 5 5.25 V 2 V

–0.5 0.8 V

0 70 °C

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TL16C450

Input leakage current

±10µA

IOZHigh-impedance output current

±20µA

25 C

ICCSupply current

,,,, ,

MHz

25°C

All other terminals grounded

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS037B – MARCH 1988 – REVISED MARCH 1996

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

‡

Ikg

XTAL1

XTAL2

†

All typical values are at VCC = 5 V, TA = 25°C.

‡

These parameters apply for all outputs except XTAL2.

HIgh-level output voltage IOH = –1 mA 2.4 V

‡

Low-level output voltage IOL = 1.6 mA 0.4 V

Clock input capacitance 15 20 pF Clock output capacitance Input capacitance Output capacitance

= 5.25 V, V

VI = 0 to 5.25 V, All other terminals floating VCC = 5.25 V, VSS = 0,

= 0 V to 5.25 V,

Chip selected, write mode,or chip deselected

= 5.25 V, SIN, DSR, DCD, CTS, and RI at 2 V, All other inputs at 0.8 V , Baud rate = 50 kbits/s, XTAL1 at 4 MHz, No load on outputs

VCC = 0, VSS = 0,

= 1

All other terminals

rounded

= 0,

20 30 pF

6 10 pF

10 20 pF

system timing requirements over recommended ranges of supply voltage and operating free-air temperature

PARAMETER FIGURE MIN MAX UNIT

wMR

su1

su2

su3

Only applies when ADS is low.

Cycle time, read (tw7 + td8 + td9) 175 ns Cycle time, write (tw6 + td5 + td6) 175 ns Pulse duration, ADS low 2,3 15 ns Pulse duration, write strobe 2 80 ns Pulse duration, read strobe 3 80 ns Pulse duration, master reset 1000 ns Setup time, address valid before ADS↑ 2,3 15 ns Setup time, CS valid before ADS↑ 2,3 15 ns Setup time, data valid before WR1↓ or WR2↑ 2 15 ns Hold time, address low after ADS↑ 2,3 0 ns Hold time, CS valid after ADS↑ 2,3 0 ns Hold time, CS valid after WR1↑ or WR2↓ 2 20 ns

Hold time, address valid after WR1↑ or WR2↓ 2 20 ns Hold time, data valid after WR1↑ or WR2↓ 2 15 ns Hold time, CS valid after RD1↑ or RD2↓

Hold time, address valid after RD1↑ or RD2↓ 3 20 ns

Delay time, CS valid before WR1↓ or WR2↑ 2 15 ns

Delay time, address valid before WR1↓ or WR2↑ 2 15 ns Delay time, write cycle, WR1↑ or WR2↓ to ADS↓ 2 80 ns

Delay time, CS valid to RD1↓ or RD2↑ 3 15 ns

Delay time, address valid to RD1↓ or RD2↑ 3 15 ns Delay time, read cycle, RD1↑ or RD2↓ to ADS↓ 3 80 ns

3 20 ns

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Pul

BAUDOUT l

, ,

Pul

BAUDOUT high

, ,

RDR to LSI interrupt or stop to

411

Delay time, INTRPT to transmit start

5824

Delay time, start to interrupt

588

Delay time, initial write to interrupt (THRE)

51632

TL16C450

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS037B – MARCH 1988 – REVISED MARCH 1996

system switching characteristics over recommended ranges of supply voltage and operating free-air temperature

PARAMETER FIGURE TEST CONDITIONS MIN MAX UNIT

d10

d11

dis(R)

†

Only applies when ADS is low.

baud generator switching characteristics over recommended ranges of supply voltage and operating free-air temperature

Pulse duration, clock high 1 f = 9 MHz maximum 50 ns Pulse duration, clock low 1 f = 9 MHz maximum 50 ns Delay time, select to CS output 2,3 Delay time, RD1↓ or RD2↑ to data valid 3 CL = 100 pF 60 ns Delay time, RD1↑ or RD2↓ to floating data 3 CL = 100 pF 0 60 ns Disable time, RD1↓↑ or RD2↑↓ to DDIS↑↓ 3 CL = 100 pF 60 ns

PARAMETER FIGURE TEST CONDITIONS MIN MAX UNIT

se duration,

Delay time, XIN↑ to BAUDOUT↑ 1 CL = 100 pF 125 ns Delay time, XIN↑↓ to BAUDOUT↓ 1 CL = 100 pF 125 ns

†

CL = 100 pF 70 ns

f = 6.25 MHz, CLK ÷ 1, CL = 100 pF

receiver switching characteristics over recommended ranges of supply voltage and operating free-air temperature

PARAMETER FIGURE TEST CONDITIONS MIN MAX UNIT

d12

d13

d14

Delay time, RCLK to sample clock 4 100 ns Delay time, stop to set RCV error interrupt or read

↓

RXRDY Delay time, read RBR/LSR to reset interrupt 4 CL = 100 pF 140 ns

RCLK cycles

transmitter switching characteristics over recommended ranges of supply voltage and operating free-air temperature

PARAMETER FIGURE TEST CONDITIONS MIN MAX UNIT

d15

d16

d17

d18

d19

Delay time, WR THR to reset interrupt 5 CL = 100 pF 140 ns

Delay time, read IIR to reset interrupt (THRE) 5 CL = 100 pF 140 ns

baudout

cycles

baudout

cycles

baudout

cycles

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TL16C450 ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS037B – MARCH 1988 – REVISED MARCH 1996

modem control switching characteristics over recommended ranges of supply voltage and operating free-air temperature

PARAMETER FIGURE TEST CONDITIONS MIN MAX UNIT

d20

d21

d22

Delay time, WR MCR to output 6 CL = 100 pF 100 ns Delay time, modem interrupt to set interrupt 6 CL = 100 pF 170 ns Delay time, RD MSR to reset interrupt 6 CL = 100 pF 140 ns

PARAMETER MEASUREMENT INFORMATION

RCLK

(9 MHz Max)

XTAL1

BAUDOUT

(1/1)

BAUDOUT

(1/2)

BAUDOUT

(1/3)

BAUDOUT

(1/N)

(N>3)

90%

2 V

10%

2XTAL1

Cycles

0.8 V t

(N-2) XTAL1

Cycles

Figure 1. Baud Generator Timing Waveforms

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TL16C450

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS037B – MARCH 1988 – REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION

ADS

A0–A2

CS0, CS1, CS2

CSOUT

DOSTR,

DOSTR

D0–D7

†

Applicable only when ADS

10% 10%

90% 10% 10%

90% 90%

10%

is tied low.

su1

Valid

†

10%

†

90%90%

Valid Valid

su2

Valid

90% 90%

†

90% 90%

Active

10%

su3

Valid Data

Figure 2. Write Cycle Timing Waveforms

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TL16C450 ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS037B – MARCH 1988 – REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION

ADS

A0–A2

CS0, CS1, CS2

CSOUT

DISTR,

DISTR

10%10%

su1

90%

Valid Valid

10% 10%

90% 90%

10%

dis(R)

50%

su2

Valid

†

90% 90%

†

90%90%

Active

10%10%

Valid

†

10%

†

dis(R)

10%

†

DDIS

D0–D7

†

Applicable only when ADS

10% 10%

is tied low.

d10

90%

d11

Valid Data

Figure 3. Read Cycle Timing Waveforms

50%

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TL16C450

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS037B – MARCH 1988 – REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION

RCLK

SAMPLE

CLOCK

SIN

SAMPLE

CLOCK

INTRPT

(RDR/LSI)

DISTR, DISTR

(RD RBR/LSR)

SOUT

8 CLKs

Start Data Bits 5–8 Parity Stop

Figure 4. Receiver Timing Waveforms

Start Data Bits Parity Stop

10%

d12

90%

d14

90%

Active

50%

d13

10%

Start

INTRPT

(THRE)

DOSTR

(WR THR)

DISTR (RD IIR)

d17

10%

90% 90%90%

d15

50%

d18

d17

Figure 5. Transmitter Timing Waveforms

d16

90%90%

d19

90%

50%

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TL16C450 ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS037B – MARCH 1988 – REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION

DOSTR (WR MCR)

10% 10%

RTS

OUT 1, OUT 2

CTS

DISTR (RD MSR)

, DTR

, DSR, DCD

INTRPT

(MODEM)

d20

90% 90%

10%

d21

90%

50%

50% 50%

90%

Figure 6. Modem Control Timing Waveforms

d22

d20

d21

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TL16C450

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS037B – MARCH 1988 – REVISED MARCH 1996

APPLICATION INFORMATION

D7–D0

MEMR

or I/OR

MEMW or I/ON

INTR

RESET

C P U

B u

A1 A2

D7–D0 DISTR DOSTR INTRPT MR A0 A1 A2 ADS DOSTR DISTR CS2 CS1 CS0

TL16C450

(ACE)

SOUT

SIN RTS DTR DSR

DCD

CTS

XTAL1

XTAL2

BAUDOUT

RCLK

EIA 232-D

Drivers

and

Receivers

3.072 MHz

Microcomputer

System

Figure 8. Typical Interface for a High-Capacity Data Bus

Figure 7. Basic TL16C450 Configuration

Receiver

8-Bit

Bus Transceiver

Disable

Driver

Disable

DOSTR

TL16C450

Data BusData Bus

(ACE)

D7–D0

DDIS

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TL16C450 ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS037B – MARCH 1988 – REVISED MARCH 1996

APPLICATION INFORMATION

A16–A23 A16–A23

Address Decoder

CPU

ADS

RSI/ABT

AD0–AD15

PHI2PHI1

Buffer

AD0– AD7

CS0

CS1

CS2

ADS

A0–A2 D0–D7

TL16C450

BAUDOUT

XTAL1

XTAL2

RCLK

DTR

RTS

OUT1

OUT2

DCD

DSR

CTS

15 9

39 38

5 V

Alternate

Xtal Control

TCU

PHI2PHI1 RSTOADS

AD0–AD15

DISTR

DOSTR

DISTR

DOSTR

GND (V

SS)

INTRPT

CSOUT

20 40

5 V

CC)

SOUT

SIN

DDIS

Figure 9. Typical TL16C450 Connection to a CPU

EIA-232-D

Connector

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RESET STATE

Interrupt identification register

Master reset

g, ,

INTRPT (transmitter holding register empty)

TL16C450

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS037B – MARCH 1988 – REVISED MARCH 1996

PRINCIPLES OF OPERATION

Table 1. Register Selection

†

DLAB

0 L L L Receiver buffer (read), transmitter holding register (write) 0 L L H Interrupt enable X L H L Interrupt identification (read only) X L H H Line control X H L L Modem control X H L H Line status X H H L Modem status X H H H Scratch 1 L L L Divisor latch (LSB) 1 L L H Divisor latch (MSB)

†

The divisor latch access bit (DLAB) is the most significant bit of the line control register. The DLAB signal is controlled by writing to this bit location (see Table 3).

A2 A1 A0 REGISTER

Table 2. ACE Reset Functions

RESET

CONTROL

Interrupt enable register Master reset All bits low (0–3 forced and 4–7 permanent)

Line control register All bits low Modem control register Master reset All bits low Line status register Master reset Bits 5 and 6 are high, all other bits are low Modem status register Master reset Bits 0–3 are low, bits 4–7 are input signals SOUT Master reset High INTRPT (receiver error flag) Read LSR/MR Low INTRPT (received data available) Read RBR/MR Low

INTRPT (modem status changes) Read MSR/MR Low OUT2 RTS DTR OUT1 Scratch register Master reset No effect Divisor latch (LSB and MSB) register Master reset No effect Receiver buffer register Master reset No effect Transmitter holding register Master reset No effect

Read IIR/Write

THR/MR

Master reset High Master reset High Master reset High Master reset High

Bit 0 is high, bits 1 and 2 are low, and bits 3–7 are permanently low

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TL16C450

Bit

Int

Enable

Control

Scratch

Latch

(MSB)

IER

LCR

Enable

Word

ece ed “0” If

Dat

Data Bit 0*

Data Bit 0

Int

Select

Read

Bit 0

Bit 8

Pending

Bit 0

(DR)

(WLSO)

Enable

as e

Traili

EdgeRi

Indicator

(TERI)

Even

Data Bit 4

Int

to Send

Bit 4

Bit 12

(BI)

(CTS)

Transmitter

Data

Data Bit 5

Bit 5

Bit 13

Set

Break

Data

Data Bit 7

Access

Bit 7

Bit 15

(DCD)

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PRINCIPLES OF OPERATION

accessible registers

The system programmer, using the CPU, has access to and control over any of the ACE registers that are summarized in Table 3. These registers control ACE operations, receive data, and transmit data. Descriptions of these registers follow Table 3.

Table 3. Summary of Accessible Registers

O DLAB = 0 O DLAB = 0 1 DLAB = 0 2 3 4 5 6 7 O DLAB = 1

Receiver Transmitter

Buffer Holding

(Read (Write

Only) Only)

RBR THR IER IIR LCR MCR LSR MSR SCR DLL DLM

1 Data Bit 1 Data Bit 1

2 Data Bit 2 Data Bit 2

3 Data Bit 3 Data Bit 3

6 Data Bit 6 Data Bit 6 0 0

errup

Enable

Received

Data

Available

Interrupt

(ERBF)

Enable

Transmitter

Holding

Empty

Interrupt

(ETBE)

Enable

Receiver

Line Status

Interrupt

(ELSI)

Enable Delta

Modem

Status Interrupt (EDSSI) (DDCD)

*Bit 0 is the least significant bit. It is the first bit serially transmitted or received.

Interrupt

Ident.

(Read

Only)

“

”

errup

Interrupt

Bit (0)

Interrupt Number of Parity

ID Stop Bits

Bit (1) (STB) (PE)

eng

Word Delta

Length

Select

Bit 1

(WLS1) (DDSR)

Parity Framing

Enable

(PEN) (FE)

Even Parity Select (EPS)

Stick

Parity

Divisor

Latch

Bit

(DLAB)

Modem Line Modem Control Status Status

Data

Terminal

Ready (DTR)

Request Overrun

to Send Error

(RTS) (OE)

Out 1

Out 2

oop

Error

Break

errup

Transmitter Data

Holding

(THRE) (DSR)

Transmitter

Empty

(TEMT)

Divisor

Latch (LSB)

Delta

Clear to Send (DCTS)

Data

Set

Ready

Data

Carrier

Detect

Clear

Set

Ring

Indicator

(RI)

Carrier

Detect

Bit 1 Bit 1 Bit 9

Bit 2 Bit 2 Bit 10

Bit 3 Bit 3 Bit 11

Bit 6 Bit 6 Bit 14

DLAB

= 0

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PRINCIPLES OF OPERATION

interrupt enable register (IER)

The IER enables each of the four types of interrupts (refer to T able 4) and the INTRPT output signal in response to an interrupt generation. By clearing bits 0 – 3, the IER can also disable the interrupt system. The contents of this register are summarized in Table 3 and are described in the following bulleted list.

Bit 0: This bit, when set, enables the received data available interrupt.

Bit 1: This bit, when set, enables the THRE interrupt.

Bit 2: This bit, when set, enables the receiver line status interrupt.

Bit 3: This bit, when set, enables the modem status interrupt.

Bits 4 – 7: These bits in the IER are not used and are always cleared.

interrupt identification register (IIR)

The ACE has an on-chip interrupt generation and prioritization capability that permits a flexible interface with most microprocessors.

The ACE provides four prioritized levels of interrupts:

TL16C450

Priority 1–Receiver line status (highest priority)

Priority 2–Receiver data ready or receiver character time out

Priority 3–Transmitter holding register empty

Priority 4–Modem status (lowest priority)

When an interrupt is generated, the IIR indicates that an interrupt is pending and the type of interrupt in its three least significant bits (bits 0, 1, and 2). The contents of this register are summarized in Table 3 and described in Table 4.

Bit 0: This bit can be used either in a hardwire prioritized or polled interrupt system. When bit 0 is cleared, an interrupt is pending. When bit 0 is set, no interrupt is pending.

Bits 1 and 2: These two bits identify the highest priority interrupt pending as indicated in Table 4.

Bits 3 – 7: These bits in the IIR are not used and are always clear.

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TL16C450

INTERRUPT TYPE

INTERRUPT SOURCE

,y,

Readi

1002Received data available

Receiver data available

Reading the interru t

itt

ldi

itt

ldi

identification register (if

em ty

Reading the modem status

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS037B – MARCH 1988 – REVISED MARCH 1996

PRINCIPLES OF OPERATION

interrupt identification register (IIR) (continued)

Table 4. Interrupt Control Functions

INTERRUPT

IDENTIFICATION

BIT 2 BIT 1 BIT 0

0 0 1 None None None –

1 1 0 1 Receiver line status

0 1 0 3

PRIORITY

LEVEL

ransm

er ho

ng register

Overrun error, parity error, framing error or break interrupt

ransm

er ho

ng register

Reading the receiver buffer Buffer register

identification register (if source of interrupt) or writing into the transmitter holding register

INTERRUPT RESET

METHOD

ng the line status

Clear to send, data set

0 0 0 4 Modem status

ready, ring indicator, or data carrier detect

line control register (LCR)

The system programmer controls the format of the asynchronous data communication exchange through the LCR. In addition, the programmer is able to retrieve, inspect, and modify the contents of the LCR; this eliminates the need for separate storage of the line characteristics in system memory. The contents of this register are summarized in Table 3 and are described in the following bulleted list.

Bits 0 and 1: These two bits specify the number of bits in each transmitted or received serial character. These bits are encoded as shown in Table 5.

Table 5. Serial Character Word Length

Bit 1 Bit 0 Word Length

0 0 5 Bits 0 1 6 Bits 1 0 7 Bits 1 1 8 Bits

Bit 2: This bit specifies either one, one and one-half, or two stop bits in each transmitted character. When bit 2 is cleared, one stop bit is generated in the data. When bit 2 is set, the number of stop bits generated is dependent on the word length selected with bits 0 and 1. The receiver checks the first stop bit only, regardless of the number of stop bits selected. The number of stop bits generated, in relation to word length and bit 2, is shown in Table 6.

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Bit 2

PRINCIPLES OF OPERATION

line control register (LCR) (continued)

Table 6. Number of Stop Bits Generated

0 Any word length 1 1 5 bits 1 1/2 1 6 bits 2 1 7 bits 2 1 8 bits 2

Bit 3: This bit is the parity enable bit. When bit 3 is set, a parity bit is generated in transmitted data between the last data word bit and the first stop bit. In received data, if bit 3 is set, parity is checked. When bit 3 is cleared, no parity is generated or checked.

Bit 4: This bit is the even parity select bit. When parity is enabled (bit 3 is set) and bit 4 is set, even parity (an even number of logic 1s is in the data and parity bits) is selected. When parity is enabled (bit 3 is set) and bit 4 is clear, odd parity (an odd number of logic 1s) is selected.

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SLLS037B – MARCH 1988 – REVISED MARCH 1996

Word Length Selected Number of Stop

by Bits 1 and 2

Bits Generated

TL16C450

Bit 5: This is the stick parity bit. When bits 3, 4, and 5 are set, the parity bit is transmitted and checked as cleared. When bits 3 and 5 are set and bit 4 is cleared, the parity bit is transmitted and checked as set.

Bit 6: This bit is the break control bit. Bit 6 is set to force a break condition, i.e, a condition where the serial output terminal (SOUT) is forced to the spacing (cleared) state. When bit 6 is cleared, the break condition is disabled. The break condition has no affect on the transmitter logic, it only affects the serial output.

Bit 7: This bit is the divisor latch access bit (DLAB). Bit 7 must be set to access the divisor latches of the baud generator during a read or write. Bit 7 must be cleared during a read or write to access the receiver buffer, the THR, or the IER.

line status register (LSR)

The LSR provides information to the CPU concerning the status of data transfers. The contents of this register are summarized in Table 3 and are described in the following bulleted list.

Bit 0: This bit is the data ready (DR) indicator for the receiver. Bit 0 is set whenever a complete incoming character has been received and transferred into the RBR and is cleared by reading the RBR.

Bit 1‡: This bit is the overrun error (OE) indicator. When bit 1 is set, it indicates that before the character in the RBR was read, it was overwritten by the next character transferred into the register. The OE indicator is cleared every time the CPU reads the contents of the LSR.

Bit 2‡: This bit is the parity error (PE) indicator. When bit 2 is set, it indicates that the parity of the received data character does not match the parity selected in the LCR (bit 4). The PE bit is cleared every time the CPU reads the contents of the LSR.

Bit 3‡: This bit is the framing error (FE) indicator. When bit 3 is set, it indicates that the received character does not have a valid (set) stop bit. The FE bit is cleared every time the CPU reads the contents of the LSR.

†

Bit4‡: This bit is the break interrupt (BI) indicator. When bit 4 is set, it indicates that the received data input was held clear for longer than a full-word transmission time. A full-word transmission time is defined as the total time of the start, data, parity , and stop bits. The BI bit is cleared every time the CPU reads the contents of the LSR.

†

The line status register is intended for read operations only; writing to this register is not recommended outside of a factory testing environment.

‡

Bits 1 through 4 are the error conditions that produce a receiver line-status interrupt.

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TL16C450 ASYNCHRONOUS COMMUNICATIONS ELEMENT

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PRINCIPLES OF OPERATION

line status register (LSR)† (continued)

Bit 5: This bit is the THRE indicator. Bit 5 is set when the THR is empty, indicating that the ACE is ready to accept a new character. If the THRE interrupt is enabled when the THRE bit is set, then an interrupt is generated. THRE is set when the contents of the THR are transferred to the transmitted shift register. This bit is cleared concurrent with the loading of the THR by the CPU.

Bit 6: This bit is the transmitter empty (TEMT) indicator. Bit 6 is set when the THR and the transmitter shift register are both empty . When either the THR or the transmitter shift register contains a data character, the TEMT bit is cleared.

Bit 7: This bit is always clear.

modem control register (MCR)

The MCR is an 8-bit register that controls an interface with a modem, data set, or peripheral device that is emulating a modem. The contents of this register are summarized in T able 3 and are described in the following bulleted list.

Bit 0: This bit (DTR) controls the data terminal ready (DTR) output. Setting bit 0 forces the DTR output to its active state (low). When bit 0 is clear, DTR

goes high.

Bit 1: This bit (RTS) controls the request to send (RTS) output in a manner identical to bit 0’s control over the DTR

Bit 2: This bit (OUT1) controls the output 1 (OUT1) signal, a user designated output signal, in a manner identical to bit 0’s control over the DTR

Bit 3: This bit (OUT2) controls the output 2 (OUT2) signal, a user designated output signal, in a manner identical to bit 0’s control over the DTR

Bit 4: This bit provides a local loopback feature for diagnostic testing of the ACE. When bit 4 is set, the following occurs:

1. The SOUT is asserted high.

2. The SIN is disconnected.

3. The output of the transmitter shift register is looped back into the RSR input.

4. The four modem control inputs (CTS

5. The four modem control outputs (DTR

6. The four modem control output terminals are forced to their inactive states (high). In the diagnostic mode, data that is transmitted is immediately received. This allows the processor to verify

the transmit and receive data paths to the ACE. The receiver and transmitter interrupts are fully operational. The modem control interrupts are also operational but the modem control interrupt sources are now the lower four bits of the MCR instead of the four modem control inputs. All interrupts are still controlled by the IER.

Bits 5 through 7: These bits are clear.

output.

, DSR, DCD, and RI) are disconnected.

, RTS, OUT1, and OUT2) are internally connected to the four

modem control inputs.

†

The line status register is intended for read operations only; writing to this register is not recommended outside of a factory testing environment.

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PRINCIPLES OF OPERATION

modem status register (MSR)

The MSR is an 8-bit register that provides information about the current state of the control lines from the modem, data set, or peripheral device to the CPU. Additionally, four bits of this register provides change information; when a control input from the modem changes state the appropriate bit is set. All four bits are cleared when the CPU reads the MSR. The contents of this register are summarized in Table 3 and are described in the following bulleted list.

Bit 0: This bit is the delta clear to send (DCTS) indicator. Bit 0 indicates that the CTS input has changed states since the last time it was read by the CPU. When this bit is set and the modem status interrupt is enabled, a modem status interrupt is generated.

Bit 1: This bit is the delta data set ready (DDSR) indicator. Bit 1 indicates that the DSR input has changed states since the last time it was read by the CPU. When this bit is set and the modem status interrupt is enabled, a modem status interrupt is generated.

Bit 2: This bit is the trailing edge of ring indicator (TERI) detector. Bit 2 indicates that the RI input to the chip has changed from a low to a high state. When this bit is set and the modem status interrupt is enabled, a modem status interrupt is generated.

TL16C450

Bit 3: This bit is the delta data carrier detect (DDCD) indicator. Bit 3 indicates that the DCD input to the chip has changed state since the last time it was read by the CPU. When this bit is set and the modem status interrupt is enabled, a modem status interrupt is generated.

Bit 4: This bit is the complement of the clear to send (CTS) input. When bit 4 (loop) of the MCR is set, this bit is equivalent to the MCR bit 1 (RTS).

Bit 5: This bit is the complement of the data set ready (DSR) input. When bit 4 (loop) of the MCR is set, this bit is equivalent to the MCR bit 0 (DTR).

Bit 6: This bit is the complement of the ring indicator (RI) input. When bit 4 (loop) of the MCR is set, this bit is equivalent to the MCRs bit 2 (OUT1).

Bit 7: This bit is the complement of the data carrier detect (DCD) input. When bit 4 (loop) of the MCR is set, this bit is equivalent to the MCRs bit 3 (OUT2).

programmable baud generator

The ACE contains a programmable baud generator that takes a clock input in the range between dc and 9 MHz and divides it by a divisor in the range between 1 and (2 sixteen times (16×) the baud rate. The formula for the divisor is:

divisor # = XTAL1 frequency input B (desired baud rate × 16)

Two 8-bit registers, called divisor latches, store the divisor in a 16-bit binary format. These divisor latches must be loaded during initialization of the ACE in order to ensure desired operation of the baud generator. When either of the divisor latches is loaded, a 16-bit baud counter is also loaded to prevent long counts on initial load.

T ables 7 and 8 illustrate the use of the baud generator with crystal frequencies of 1.8432 MHz and 3.072 MHz, respectively . For baud rates of 38.4 kilobits per second and below, the error obtained is very small. The accuracy of the selected baud rate is dependent on the selected crystal frequency.

–1). The output frequency of the baud generator is

Refer to Figure 10 for examples of typical clock circuits.

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TL16C450

DESIRED

DIVISOR USED

PERCENT ERROR

BAUD RATE

DESIRED

DIVISOR USED

PERCENT ERROR

BAUD RATE

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SLLS037B – MARCH 1988 – REVISED MARCH 1996

PRINCIPLES OF OPERATION

Table 7. Baud Rates Using a 1.8432-MHz Crystal

TO GENERATE

16× CLOCK DESIRED AND ACTUAL

50 2304 75 1536

110 1047 0.026

134.5 857 0.058 150 768 300 384 600 192

1200 96 1800 64 2000 58 0.69 2400 48 3600 32 4800 24 7200 16

9600 12 19200 6 38400 3 56000 2 2.86

DIFFERENCE BETWEEN

Table 8. Baud Rates Using a 3.072-MHz Crystal

DIVISOR USED PERCENT ERROR TO GENERATE

16× CLOCK DESIRED AND ACTUAL

50 3840 75 2560

110 1745 0.026

134.5 1428 0.034 150 1280 300 640 600 320

1200 160 1800 107 0.312 2000 96 2400 80 3600 53 0.628 4800 40 7200 27 1.23

9600 20 19200 10 38400 5

DIFFERENCE BETWEEN

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TL16C450

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS037B – MARCH 1988 – REVISED MARCH 1996

PRINCIPLES OF OPERATION

Driver

External

Clock

Optional

Clock

Output

XTAL1

Optional

XTAL2

Oscillator Clock to Baud Generator Logic

XTAL1

Crystal

RX2

XTAL2

TYPICAL CRYSTAL OSCILLATOR NETWORK

CRYSTAL

3.1 MHz 1 MΩ 1.5 kΩ 10–30 pF 40–60 pF

1.8 MHz 1 MΩ 1.5 kΩ 10–30 pF 40–60 pF

RX2 C1 C2

Oscillator Clock to Baud Generator Logic

Figure 10. Typical Clock Circuits

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TL16C450 ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS037B – MARCH 1988 – REVISED MARCH 1996

PRINCIPLES OF OPERATION

receiver buffer register (RBR)

The ACE receiver section consists of a receiver shift register and a RBR. Timing is supplied by the 16×receiver clock (RCLK). Receiver section control is a function of the ACE line control register.

The ACE receiver shift register receives serial data from the serial input (SIN) terminal. The receiver shift register then converts the data to a parallel form and loads it into the RBR. When a character is placed in the RBR and the received data available interrupt is enabled, an interrupt is generated. This interrupt is cleared when the data is read out of the RBR.

scratch register

The scratch register is an 8-bit register that is intended for programmer use as a scratchpad, in the sense that it temporarily holds programmer data without affecting any other ACE operation.

transmitter holding register (THR)

The ACE transmitter section consists of a THR and a transmitter shift register. Timing is supplied by the baud out (BAUDOUT

The ACE THR receives data from the internal data bus and, when the shift register is idle, moves it into the transmitter shift register. The transmitter shift register serializes the data and outputs it at the serial output (SOUT). If the THR is empty and the transmitter holding register empty (THRE) interrupt is enabled, an interrupt is generated. This interrupt is cleared when a character is loaded into the register.

) clock signal. Transmitter section control is a function of the ACE line control register.

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IMPORTANT NOTICE

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In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards should be provided by the customer to minimize inherent or procedural hazards.

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TEXAS INSTRUMENTS TL16C450 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual