TEXAS INSTRUMENTS THS3201 Technical data

Low-Noise, Low-Distortion, Wideband Application Circuit

NONINVERTING SMALL SIGNAL

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

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SLOS416A − JUNE 2003 − REVISED JANUARY 2004

FEATURES

D Unity Gain Bandwidth: 1.8 GHz D High Slew Rate: 10500 V/µs D Distortion at 100 MHz: (G = 10 V/V,

RL = 100 Ω, 2-VPP envelope)

− IMD3: −80 dBc

− OIP3: 41 dBm

D Noise Figure : 11 dB (G = 10 V/V,

RG = 28 Ω, RF = 255 Ω)

D Input Referred Noise (f > 10 MHz)

− Voltage Noise: 1.65 nV/√Hz

− Noninverting Current Noise: 13.4 pA/√Hz

− Inverting Current Noise: 20 pA/√Hz

D Output Current: +115/−100 mA D Power Supply Voltage Range: ±3.3 V to ±7.5 V

APPLICATIONS

D Arbitrary Waveform Driver D High-Resolution, High-Sampling Rate ADC

Drivers

D High-Resolution, High-Sampling Rate DAC

Output Buffers

D If Amplification for Wireless Communications

Applciations

D Broadcast Video and HDTV Line Drivers

DESCRIPTION

The THS3201 is a wide-band, high-speed current-feedback amplifier, designed to operate over a wide supply range of ±3.3 V to ±7.5 V for todays high performance applications.

The wide supply range combined with distortion as low as

−74 dBc at 10 MHz, plus an extremely high slew rate of 10500 V/µs makes the THS3201 ideally suited for arbitrary waveform driver applications. The distortion performance also enables driving high-resolution and high-sampling rate ADCs. Moreover, the gain of +2 bandwidth of 850 MHz, combined with a 0.1 dB flatness of 380 MHz makes the THS3201 ideal for broadcast video and HDTV applications. The THS3201 also offers excellent performance for IF amplification in wireless communications systems by having IMD

−80 dBc, OIP

of 41 dBm, and a noise figure of 1 1 dB, all at

100 MHz with a gain +10 V/V, while driving a 2-V envelope into a 100-Ω load.

The THS3201 is offered in a 5-pin SOT−23, 8-pin SOIC, and an 8-pin MSOP with PowerPAD packages.

RELATED DEVICES AND DESCRIPTIONS

THS3202 ±7.5-V 2-GHz Dual Low Distortion CFB Amplifier THS3001 ±15-V 420-MHz Low Distortion CFB Amplifier THS3061/2 ±15-V 300-MHz Low Distortion CFB Amplifier THS3122 ±15-V Dual CFB Amplifier With 350 mA Drive THS4271 ±7.5-V 1.4-GHz Low Distortion VFB Amplifier

performance of

FREQUENCY RESPONSE

50 Ω Source

50 Ω

NOTE:Power supply decoupling capacitors not shown

semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments Incorporated.

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49.9 Ω

768 Ω

+7.5 V

THS3201

−7.5 V

768 Ω

49.9 Ω

50 Ω

Gain = 2.

Noninverting Gain − dB

RL = 100 Ω, VO = 0.2 VPP.

VS = ±7.5 V

100 k 1 M 10 M 100 M 1 G 10 G

RF = 768 Ω

f − Frequency − Hz



ESD ratings:

PACKAGE

(1)

PACKAGE

(°C/W)

Supply voltage

OUTLINE

−40°C to 85°C

BEO

BEN

BGP

SLOS416A − JUNE 2003 − REVISED JANUARY 2004

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ABSOLUTE MAXIMUM RATINGS

over operat i n g f ree-air temperature range unless otherwise noted

UNIT

Supply voltage, V Input voltage, V Output current, IO Differential input voltage, V Continuous power dissipation See Dissipation Rating Table Maximum junction temperature, T Maximum junction temperature, continuous

operation, long term reliability T Operating free-air temperature range, T Storage temperature range, T Lead temperature

1,6 mm (1/16 inch) from case for 10 seconds

(2)

(3)

(4)

stg

HBM 3000 V

ESD ratings:

CDM 1500 V MM 100 V

(1)

Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.

(2)

The THS3201 may incorporate a PowerPAD on the underside of the chip. This acts as a heat sink and must be connected to a thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature which could permanently damage the device. See TI technical briefs SLMA002 and SLMA004 for more information about utilizing the PowerPAD thermally enhanced package.

(3)

The absolute maximum temperature under any condition is limited by the constraints of the silicon process.

(4)

The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may result in reduced reliability and/or lifetime of the device.

16.5 V

±V

175 mA

±3 V

150°C 125°C

−40°C to 85°C

−65°C to 150°C 300°C

(1)

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe

proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to

complete device failure. Precision integrated circuits may be more susceptible t o damage because very small parametric changes could cause the device not to meet its published specifications.

PACKAGE DISSIPATION RATINGS

JCθJA

POWER RATING

(TJ = 125°C)

TA ≤ 25°C TA = 85°C

DBV (5) 55 255.4 391 mW 156 mW

D (8) 38.3 97.5 1.02 W 410 mW

DGN (8) 4.7 58.4 1.71 W 685 mW

DGK (8 pin) 54.2 260 385 mW 154 mW

(1)

This data was taken using the JEDEC standard High-K test PCB.

(2)

Power rating is determined with a junction temperature of 125°C. This is the point where distortion starts to substantially increase. Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C for best performance and long term reliability.

(2)

RECOMMENDED OPERATING CONDITIONS

MIN MAX UNIT

Dual supply ±3.3 ±7.5 Single supply 6.6 15

Operating free-air temperature, T

−40 85 °C

PACKAGE/ORDERING INFORMATION

PIN ASSIGNMENTS

NOTE:If a PowerPAD is used, it is electrically isolated from the active circuitry.

PACKAGED DEVICES

TEMPERATURE

PLASTIC SMALL

OUTLINE

(1)

(D)

(DBV) SYM (DGN) SYM (DGK) SYM

SOT-23

(2)

THS3201D THS3201DBVT

THS3201DR THS3201DBVR

(1)

Available in tape and reel. The R suffix standard quantity is 2500 (e.g. THS3201DGNR).

(2)

Available in tape and reel. The R suffix standard quantity is 3000. The T suf fix standard quantity is 250 (e.g. THS3201DBVT).

SOT−23TOP VIEW

OUT

S−

IN+

S+

IN−

PLASTIC MSOP

THS3201DGN

THS3201DGNR

TOP VIEW

POWERPAD

IN−

IN+

S−

(1)

PLASTIC MSOP

THS3201DGK

THS3201DGKR

1 2 3 4

8 7

6 5

S+

OUT−

NC = No Internal Connection

(1)

D, DGN, DGK

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PARAMETER

TEST CONDITIONS

Small-signal bandwidth, −3 dB

Typ

(VO = 200 mVPP)

MHz

Slew rate (25% to 75% level)

V/µs

Typ

2nd harmonic

dBc

Typ

3rd harmonic

dBc

Typ

f = 200 kHz,

Differential gain G = +2, R

= 150 Ω,

G = +2, RL = 150 Ω

Differential phase

RF = 768

SLOS416A − JUNE 2003 − REVISED JANUARY 2004

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ELECTRICAL CHARACTERISTICS

VS = ±7.5 V: Rf = 768 Ω, RL = 100 Ω, and G = +2 unless otherwise noted

THS3201

TYP OVER TEMPERATURE

25°C 25°C

AC PERFORMANCE

G = +1, RF= 1.2 kΩ 1.8 GHz G = +2, RF = 768 Ω 850

(VO = 200 mVPP)

Bandwidth for 0.1 dB flatness Large-signal bandwidth G = +2, VO = 2 V

Rise and fall time G = +2, VO = 4-V step, RF = 768 Ω 0.6 ns Typ Settling time to 0.1% G = −2, VO = 2-V step 20

0.01% G = −2, VO = 2-V step 60 Harmonic distortion G = +5, f = 10 MHz, VO = 2 V

Third-order intermodulation distortion (IMD3)

Third-order output intercept point (OIP3)

Noise figure Input voltage noise f > 10 MHz 1.65 nV/√Hz Typ

Input current noise (noninverting) f > 10 MHz 13.4 pA/√Hz Typ Input current noise (inverting) f > 10 MHz 20 pA/√Hz Typ

G = +5, RF = 619 Ω 565 G = +10, RF = 487 Ω 520 G = +2, VO = 200 mV

RF = 768 Ω

G = +1, VO = 5-V step 6200 G = +2, VO = 10-V step 10500

RL = 100 Ω −75 RL = 500 Ω −77 RL = 100 Ω −91 RL = 500 Ω −93

G = +10, fc = 100 MHz,

∆

O(envelope)

G = +10, fc = 100 MHz, RF = 255 Ω, RG = 28

RF = 768 Ω

pp,

= 715 Ω 880 MHz Typ

pp, RF

= 2 V

pp 41 dBm Typ

NTSC 0.008% Typ

PAL 0.004% Typ

NTSC 0.007° Typ

PAL 0.011° Typ

380 MHz Typ

−80 dBc Typ

11 dB Typ

0°C to

70°C

−40°C

to 85°C

UNITS

MHz

MIN/TYP/

MAX

DC PERFORMANCE

Open-loop transimpedance gain VO = ±1 V, RL = 1 kΩ 300 200 140 120 kΩ Min Input offset voltage VCM = 0 V ±0.7 ±3 ±3.8 ±4 mV Max Average offset voltage drift VCM = 0 V ±10 ±13 µV/°C Typ Input bias current (inverting) VCM = 0 V ±13 ±60 ±80 ±85 µA Max Average bias current drift (−) VCM = 0 V ±300 ±400 nA/°C Typ Input bias current (noninverting) VCM = 0 V ±14 ±35 ±45 ±50 µA Max Average bias current drift (+) VCM = 0 V ±300 ±400 nA/°C Typ



PARAMETER

TEST CONDITIONS

Input resistance

Voltage output swing

Min

SLOS416A − JUNE 2003 − REVISED JANUARY 2004

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ELECTRICAL CHARACTERISTICS

VS = ±7.5 V: Rf = 768 Ω, RL = 100 Ω, and G = +2 unless otherwise noted

THS3201

TYP OVER TEMPERATURE

25°C 25°C

INPUT

Common-mode input range ±5.1 ±5 ±5 ±5 V Min Common-mode rejection ratio VCM = ±3.75 V 71 60 58 58 dB Min Inverting input impedance, Z

Input capacitance Noninverting 1 pF Typ

OUTPUT

Current output, sourcing RL = 20 Ω 115 105 100 100 mA Min Current output, sinking RL = 20 Ω 100 85 80 80 mA Min Closed-loop output impedance G = +1, f = 1 MHz 0.01 Ω Typ

Open loop 16 Ω Typ Noninverting 780 kΩ Typ Inverting 11 Ω Typ

RL = 1 kΩ ±6 ±5.9 ±5.8 ±5.8 RL = 100 Ω ±5.8 ±5.7 ±5.5 ±5.5

0°C to

70°C

−40°C

to 85°C

UNITS

MIN/TYP/

MAX

POWER SUPPLY

Minimum operating voltage Absolute minimum ±3.3 ±3.3 ±3.3 V Min Maximum operating voltage Absolute maximum ±8.25 ±8.25 ±8.25 V Max Maximum quiescent current 14 18 21 21 mA Max Power supply rejection (+PSRR) VS+ = 7 V to 8 V 69 63 60 60 dB Min Power supply rejection (−PSRR) VS− = −7 V to –8 V 65 58 55 55 dB Min

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PARAMETER

TEST CONDITIONS

Small-signal bandwidth, −3dB

Typ

(VO = 200 mVPP)

MHz

Slew rate (25% to 75% level)

V/µs

Typ

2nd harmonic

dBc

Typ

3rd harmonic

dBc

Typ

f = 200 kHz,

Differential gain G = +2, R

= 150 Ω,

G = +2, RL = 150 Ω,

Differential phase

RF= 768

SLOS416A − JUNE 2003 − REVISED JANUARY 2004



ELECTRICAL CHARACTERISTICS

VS = ±5 V: Rf = 715 Ω, RL = 100 Ω, and G = +2 unless otherwise noted

THS3201

TYP OVER TEMPERATURE

25°C 25°C

AC PERFORMANCE

G = +1, RF= 1.2 kΩ 1.3 GHz G = +2, RF = 715 Ω 725

(VO = 200 mVPP)

Bandwidth for 0.1 dB flatness Large-signal bandwidth G = +2, VO = 2 Vpp, RF= 715 Ω 900 MHz Typ

Rise and fall time Settling time to 0.1% G = −2, VO = 2-V step 20 ns Typ

0.01% G = −2, VO = 2-V step 60 ns Typ Harmonic distortion G = +5, f = 10 MHz, VO = 2 V

Third-order intermodulation distortion (IMD3)

Third-order output intercept point (OIP3)

Noise figure Input voltage noise f > 10 MHz 1.65 nV/√Hz Typ

Input current noise (noninverting) f > 10 MHz 13.4 pA/√Hz Typ Input current noise (inverting) f > 10 MHz 20 pA/√Hz Typ

G = +5, RF = 576 Ω 540 G = +10, RF = 464 Ω 480 G = +2, VO = 200 mV

RF= 715 Ω

G = +1, VO = 5-V step 5200 G = +2, VO = 5-V step 5200 G = +2, VO = 4-V step,

RF= 715 Ω

RL = 100 Ω −68 RL = 500 Ω −70 RL = 100 Ω −72 RL = 500 kΩ −74

G = +10, fc = 100 MHz,

∆

O(envelope)

G = +10, fc = 100 MHz, RF = 255 Ω, RG = 28

RF= 768 Ω

pp,

= 2 V

pp 33.5 dBm Typ

NTSC 0.006% Typ

PAL 0.004% Typ

NTSC 0.03° Typ

PAL 0.04° Typ

170 MHz Typ

0.7 ns Typ

−65 dBc Typ

11 dB Typ

0°C to

70°C

−40°C

to 85°C

UNITS

MHz

MIN/TYP/

MAX

DC PERFORMANCE

Open-loop transimpedance gain VO = +1 V , RL = 1 kΩ 300 200 140 120 kΩ Min Input offset voltage VCM =0 V ±0.7 ±3 ±3.8 ±4 mV Max Average offset voltage drift VCM = 0 V ±10 ±13 µV/°C Typ Input bias current (inverting) VCM = 0 V ±13 ±60 ±80 ±85 µA Max Average bias current drift (−) VCM = 0 V ±300 ±400 nA/°C Typ Input bias current (noninverting) VCM = 0 V ±14 ±35 ±45 ±50 µA Max Average bias current drift (+) VCM = 0 V ±300 ±400 nA/°C Typ



PARAMETER

TEST CONDITIONS

Input resistance

Voltage output swing

Min

SLOS416A − JUNE 2003 − REVISED JANUARY 2004

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ELECTRICAL CHARACTERISTICS continued

VS = ±5 V: Rf = 715 Ω, RL = 100 Ω, and G = +2 unless otherwise noted

THS3201

TYP OVER TEMPERATURE

25°C 25°C

INPUT

Common-mode input range ±2.6 ±2.5 ±2.5 ±2.5 V Min Common-mode rejection ratio VCM = ±2.5 V 71 60 58 58 dB Min Inverting input impedance, Z

Input capacitance Noninverting 1 pF Typ

OUTPUT

Current output, sourcing RL = 20 Ω 115 105 100 100 mA Min Current output, sinking RL = 20 Ω 100 85 80 80 mA Min Closed-loop output impedance G = +1, f = 1 MHz 0.01 Ω Typ

Open loop 17.5 Ω Typ Noninverting 780 kΩ Typ Inverting 11 Ω Typ

RL = 1 kΩ ±3.65 ±3.5 ±3.45 ±3.4 RL = 100 Ω ±3.45 ±3.33 ±3.25 ±3.2

0°C to

70°C

−40°C

to 85°C

UNITS

MIN/TYP/

MAX

POWER SUPPLY

Minimum operating voltage Absolute minimum ±3.3 ±3.3 ±3.3 V Min Maximum operating voltage Absolute maximum ±8.25 ±8.25 ±8.25 V Max Maximum quiescent current 14 16.8 19 20 mA Max Power supply rejection (+PSRR) VS+ = 4.5 V to 5.5 V 69 63 60 60 dB Min Power supply rejection (−PSRR) VS− = −4.5 V to –5.5 V 65 58 55 55 dB Min

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SLOS416A − JUNE 2003 − REVISED JANUARY 2004

TYPICAL CHARACTERISTICS

Table of Graphs (V

Noninverting small signal frequency response 1, 2 Inverting small signal frequency response 3 Noninverting large signal frequency response 4 Inverting large signal frequency response 5

0.1 dB gain flatness frequency response 6 Capacitive load frequency response 7 Recommended switching resistance vs Capacitive Load 8 2nd harmonic distortion vs Frequency 9 3rd harmonic distortion vs Frequency 10 Harmonic distortion vs Output voltage swing 11, 12 Third-order intermodulation distortion (IMD3) vs Frequency 13 Third-order output intercept point (OIP3) vs Frequency 14 S − Parameter vs Frequency 15, 16 Input voltage and current noise vs Frequency 17 Noise figure vs Frequency 18 Transimpedance vs Frequency 19 Input offset voltage vs Case Temperature 20 Input bias and offset current vs Case Temperature 21 Slew rate vs Output voltage step 22, 23 Settling time 24, 25 Quiescent current vs Supply voltage 26 Output voltage vs Load resistance 27 Rejection ratio vs Frequency 28 Noninverting small signal transient response 29 Inverting large signal transient response 30 Overdrive recovery time 31 Differential gain vs Number of loads 32 Differential phase vs Number of loads 33 Closed-loop output impedance vs Frequency 34

= ±7.5 V)

FIGURE

Table of Graphs (VS = ±5 V)

FIGURE

Noninverting small signal frequency response 35 Inverting small signal frequency response 36

2nd harmonic distortion vs Frequency 38 3rd harmonic distortion vs Frequency 39 Harmonic distortion vs Output voltage swing 40, 41 Third-order intermodulation distortion (IMD3) vs Frequency 42 Third-order output intercept point (OIP3) vs Frequency 43 S − Parameter vs Frequency 44, 45 Slew rate vs Output voltage step 46 Noninverting small signal transient response 47 Inverting large signal transient response 48 Overdrive recovery time 49



SLOS416A − JUNE 2003 − REVISED JANUARY 2004

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VS = ±7.5 V Graphs

NONINVERTING SMALL SIGNAL

FREQUENCY RESPONSE

Gain = 2.

Noninverting Gain − dB

RL = 100 Ω, VO = 0.2 VPP.

VS = ±7.5 V

100 k 1 M 10 M 100 M 1 G 10 G

RF = 619 Ω

RF = 768 Ω

RF = 1 kΩ

f − Frequency − Hz

Figure 1

INVERTING LARGE SIGNAL

FREQUENCY RESPONSE

Inverting Gain − dB

G =−5, RF = 576 Ω

G = 2, RF = 715 Ω

RL = 100 Ω, VO = 2 VPP.

VS = ±7.5 V

100 k 1 M 10 M 100 M 1 G

f − Frequency − Hz

Figure 4

NONINVERTING SMALL SIGNAL

FREQUENCY RESPONSE

24 22 20 18 16 14 12 10

8 6

Noninverting Gain − dB

4 2 0

−2

−4 100 k 1 M 10 M 100 M 1 G 10 G

G = 10, RF = 487 Ω

G = 5, RF = 619 Ω

RL = 100 Ω, VO = 0.2 VPP. VS = ±7.5 V

G = 2, RF = 768 Ω

G =1, RF = 1.2 kΩ

f − Frequency − Hz

Figure 2

INVERTING LARGE SIGNAL

FREQUENCY RESPONSE

16 14 12 10

8 6 4

Inverting Gain − dB

2 0

−2

−4

G =−5, RF = 549 Ω

RL = 100 Ω, VO = 2 VPP. VS = ±7.5 V

G = −1, RF = 576 Ω

100 k 1 M 10 M 100 M 1 G

f − Frequency − Hz

Figure 5

INVERTING SMALL SIGNAL

FREQUENCY RESPONSE

24 22

20 18 16 14 12 10

8 6 4

Noninverting Gain − dB

2 0

−2

−4 100 k 1 M 10 M 100 M 1 G 10 G

G = −10, RF = 499 Ω

G = −5, RF = 549 Ω

RL = 100 Ω, VO = 0.2 VPP. VS = ±7.5 V

G = −2, RF = 576 Ω

G = −1, RF = 619 Ω

f − Frequency − Hz

Figure 3

0.1 dB GAIN FLATNESS

FREQUENCY RESPONSE

6.4 Gain = 2,

6.3

RF = 768 Ω, RL = 100 Ω,

6.2

VO = 0.2 VPP, VS = ±7.5 V

6.1

5.9

Noninverting Gain − dB

5.8

5.7

5.6

100 k 10 M 100 M 1 G 10 G

1 M

f − Frequency − Hz

Figure 6

Gain − dB

CAPACITIVE LOAD

FREQUENCY RESPONSE

= 30 Ω, CL = 22 pF

14 12 10

−2

(ISO)

= 20 Ω,

(ISO)

CL = 50 pF

Gain = 5 RF = 619 Ω

RL = 100 Ω VS = ±7.5 V

6 4

= 15 Ω,

(ISO)

CL = 100 pF

= 20 Ω,

(ISO)

CL = 47 pF

0 100 200 300 400 500

f − Frequency − MHz

Figure 7

RECOMMENDED R

Ω

−

ISO

Recommended

CAPACTIVE LOAD

Gain = 5, RF = 619 Ω RL = 100 Ω, VS = ±7.5 V

ISO

10 100

CL − Capacitive Load − pF

Figure 8

ISO

2nd HARMONIC DISTORTION

FREQUENCY

−40 VO = 2 VPP, RL = 100 Ω,

−50 VS = ±7.5 V

G = 1, RF = 1.2 kΩ

−60

−70

−80

−90

2nd Harmonic Distortion − dBc

−100 1 10 100

f − Frequency − MHz

G = 5, RF = 619 Ω

G = 2, RF = 768 Ω

Figure 9

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SLOS416A − JUNE 2003 − REVISED JANUARY 2004

3rd HARMONIC DISTORTION

−40

−50

−60

−70

−80

−90

3rd Harmonic Distortion − dBc

−100 1

FREQUENCY

VO = 2 VPP, RL = 100 Ω, VS = ±7.5 V

G = 1, RF = 1.2 kΩ

G = 2, RF = 768 Ω

f − Frequency − MHz

G = 5, RF = 619 Ω 10 100

Figure 10

THIRD-ORDER INTERMODULATION

DISTORTION

−60

−65

−70

−75

−80

−85

−90

−95

−100

Third-Order Intermodulation Distortion − dBc

10 100 200

FREQUENCY

RL = 100 Ω VO = 2VPP Envelope VS = ±7.5 V 200 kHz Tone Spacing

G = 2, RF = 768 Ω

G = 5, RF = 619 Ω

f − Frequency − MHz

G = 10, RF = 487 Ω

Figure 13

HARMONIC DISTORTION

OUTPUT VOLTAGE SWING

−60 Gain = 5 RF = 619 Ω

−65 f = 8 MHz

−70

VS = ±7.5 V

HD2, RL = 100 Ω

−75

−80

−85

−90

Harmonic Distortion − dBc

−95

−100 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

VO − Output Voltage Swing − ± V

HD2, RL = 499 Ω

HD3, RL = 100 Ω

HD3, RL = 499 Ω

Figure 11

THIRD-ORDER OUTPUT

INTERCEPT POINT

FREQUENCY

G = 5, RF = 619 Ω

Third-Order Output Intersept Point − dBm

VO = 2 VPP Envelope RL = 100 Ω VS = ±7.5 V 200 kHz Tone Spacing

G = 10, RF = 487 Ω

G = 2, RF = 768 Ω

20 40 60 80 1000

f − Frequency − MHz

Figure 14

HARMONIC DISTORTION

OUTPUT VOLTAGE SWING

−50

−55

−60

−65

−70

−75

−80

−85

Harmonic Distortion − dBc

−90

−95

−100 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

HD2

RL = 100 Ω

RL = 499 Ω

VO − Output Voltage Swing − ± V

HD2, RL = 499 Ω

HD3,

HD3, RL = 100 Ω

Gain = 5, RF = 619 Ω f = 32 MHz, VS = ±7.5 V

Figure 12

S − PARAMETER

FREQUENCY

VS = ±7.5 V Gain = +10 C = 0 pF

−20

S22

−40

−60

S−Parameter − dB

−80

−100 1 M 10 M 100 M 10

f − Frequency − Hz

50 Ω Source

S11

Figure 15

−

50 Ω

1 G

S12

50 Ω

S − PARAMETER

FREQUENCY

VS = ±7.5 V Gain = +10 C = 3.3 pF

−20

S22

−40

−60 S11

S−Parameter − dB

−80

−100 1 M 10 M 100 M 10 G

f − Frequency − Hz

50 Ω Source

−

50 Ω

1 G

Figure 16

INPUT VOLTAGE

AND CURRENT NOISE

pA Hz

S12

50 Ω

35 30

Input Current Noise Density −

−

100 k 1 M 10 M 100 M

FREQUENCY

VS = ±7.5 V and ±5 V TA = 25°C

Inverting Noise Current

Noninverting Current Noise

f − Frequency − Hz

nV/

3.5

2.5

1.5

0.5

Voltage Noise Density −

− n

Figure 17

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SLOS416A − JUNE 2003 − REVISED JANUARY 2004

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NOISE FIGURE

Noise Figure − dB

0 50 100 150 200 250 300 350 400

FREQUENCY

Gain = +10 RG = 28 Ω RF = 255 Ω VS = ±7.5 V & ±5 V

f − Frequency − MHz

Figure 18

INPUT BIAS AND OFFSET CURRENT

CASE TEMPERATURE

VS = ±7.5 V

Aµ

− Input Bias Currents − IB

11 10

−40−30−20−10 0 10 20 30 40 50 60 70 80 90

TC − Case Temperature − °C

IIB−

IIB+

Figure 21

120

100

Transimpedance Gain −dBΩ

100 k 10 M 1 G100 M1 M

8000

7000

Aµ

sµ

6000

5000

4000 3000

SR − Slew Rate −

2000

− Input Offset Currents −

1000

TRANSIMPEDANCE

FREQUENCY

VS = ±5 and ±7.5V

10 Ω

+ _

Gain W +

f − Frequency − Hz

Figure 19

SLEW RATE

OUTPUT VOLTAGE

Gain = 1 RL = 100 Ω RF = 1.2 kΩ VS = ±7.5 V

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

VO − Output Voltage − V

Rise

Fall

Figure 22

INPUT OFFSET VOLTAGE

CASE TEMPERATURE

2.5

1.5

− Input Offset Voltage − mV

0.5

VS = ±7.5 V

VS = ±5 V

−40−30−20−10 0 10 20 30 40 50 60 70 80 90

TC − Case Temperature − °C

Figure 20

SLEW RATE

OUTPUT VOLTAGE

11000

Gain = 2

10000

RL = 100 Ω

9000

sµ

SR − Slew Rate −

RF = 768 Ω VS = ±7.5 V

8000 7000 6000 5000

4000 3000 2000

1000

012345678910

VO − Output Voltage − V

Rise

Fall

Figure 23

QUIESCENT CURRENT

1.5

0.5

−0.5

− Output Voltage − V O

−1

−1.5

SETTLING TIME

Rising Edge

Gain = −2 RL = 100 Ω RF = 576 Ω f= 1 MHz VS = ±7.5 V

Falling Edge

0246810

t − Time − ns

2.5 2

1.5 1

0.5 0

−0.5

−1

− Output Voltage − V O

−1.5

−2

−2.5

−3

Figure 24

SETTLING TIME

Rising Edge

Gain = −2 RL = 100 Ω RF = 576 Ω f= 1 MHz VS = ±7.5 V

Falling Edge

0 2.5 7.5 12.5

510

t − Time − ns

Figure 25

20 18 16 14 12 10

8 6

Quiescent Current − mA

4 2 0

SUPPLY VOL TAGE

TA = 85°C

TA = 25°C

TA = −40°C

2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5

VS − Supply Voltage − ±V

Figure 26

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SLOS416A − JUNE 2003 − REVISED JANUARY 2004

OUTPUT VOLTAGE

LOAD RESISTANCE

7 6 5 4 3 2 1 0

−1

−2

− Output Voltage − V

−3

−4

−5

−6

−7 10 100 1000

RL − Load Resistance − Ω

VS = ±7.5 V TA = −40 to 85°C

Figure 27

INVERTING LARGE-SIGNAL

TRANSIENT RESPONSE

6 5 4 3 2 1 0

−1

−2

− Output Voltage − V O

−3

−4

−5

−6

Gain = −5 RL = 100 Ω RF = 549 Ω VS = ±7.5 V

Input

Output

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

t − Time − µs

Figure 30

REJECTION RATIO

FREQUENCY

PSRR+

Rejection Ratios − dB

100 k 1 M 10 M 100 M

CMRR

f − Frequency − Hz

VS = ±7.5 V

Figure 28

OVERDRIVE RECOVERY TIME

8 6 4 2

−2

− Output Voltage − V

−4

−6

−8

−10 0 0.2 0.4 0.6 0.8 1

t − Time − µs

G = 2, RF = 768 Ω, VS = ±7.5 V

Figure 31

5 4 3 2 1 0

−1

− Input Voltage − VV

−2

−3

−4

−5

NONINVERTING SMALL-SIGNAL

TRANSIENT RESPONSE

0.3

0.2

0.1

− Output Voltage − V

−0.1

−0.2

−0.3

Output

Input

Gain = 2 RL = 100 Ω RF = 715 Ω VS = ±7.5 V

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

t − Time − µs

Figure 29

DIFFERENTIAL GAIN

0.030

0.025

0.020

0.015

0.010

Differential Gain − %

0.005

NUMBER OF LOADS

Gain = 2 RF = 768 Ω VS = ±7.5 V 40 IRE − NTSC and Pal Worst Case ±100 IRE Ramp

012345678

Number of Loads − 150 Ω

Figure 32

PAL

NTSC

DIFFERENTIAL PHASE

0.040

0.035

0.030

0.025

0.020

0.015

Differential Phase −

0.010

0.005

NUMBER OF LOADS

Gain = 2 RF = 768 kΩ VS = ±7.5 V 40 IRE − NTSC and Pal Worst Case ±100 IRE Ramp

PAL

NTSC

012345678

Number of Loads − 150 Ω

Figure 33

CLOSED-LOOP OUTPUT IMPEDANCE

Gain = 2 RF = 715 Ω RL = 100 Ω VS = ±7.5 V

f − Frequency − Hz

FREQUENCY

1000

Ω

100

0.1

0.01

Closed-Loop Output Impedance −

0.001 100 k 1 M 10 M 1 M 1 G

Figure 34



THIRD-ORDER INTERMODULATION

SLOS416A − JUNE 2003 − REVISED JANUARY 2004

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VS = ±5 V Graphs

NONINVERTING SMALL SIGNAL

FREQUENCY RESPONSE

24 22 20 18

16 14 12 10

8 6

Noninverting Gain − dB

4 2 0

−2

−4 100 k 1 M 10 M 100 M 1 G 10 G

G = 10, RF = 464 Ω

G = 5, RF = 576 Ω

RL = 100 Ω, VO = 0.2 VPP. VS = ±5 V

G = 2, RF = 715 Ω

G =1, RF = 1.2 kΩ

f − Frequency − Hz

Figure 35

2nd HARMONIC DISTORTION

−40

−50

−60

−70

−80

−90

2nd Harmonic Distortion − dBc

−100 1 10 100

FREQUENCY

VO = 2 VPP, RL = 100 Ω, VS = ±5 V

G = 1, RF = 1.2 kΩ

G = 2, RF = 715 Ω

f − Frequency − MHz

G = 5, RF = 576 Ω

Figure 38

INVERTING SMALL SIGNAL

FREQUENCY RESPONSE

24 22 20 18 16 14 12 10

8 6

Inverting Gain − dB

4 2

−2

−4 100 k 1 M 10 M 100 M 1 G 10 G

G = −10, RF = 499 Ω

G = −5, RF = 549 Ω

RL = 100 Ω, VO = 0.2 VPP. VS = ±5 V

G = −2, RF = 576 Ω

G =−1, RF = 576 Ω

f − Frequency − Hz

Figure 36

3rd HARMONIC DISTORTION

−40

−50

−60

−70

−80

−90

3rd Harmonic Distortion − dBc

−100 1 10 100

FREQUENCY

VO = 2 VPP, RL = 100 Ω, VS = ±5 V

G = 1, RF = 1.2 kΩ

G = 5, RF = 576 Ω

f − Frequency − MHz

G = 2, RF = 715 Ω

Figure 39

0.1 dB GAIN FLATNESS

FREQUENCY RESPONSE

6.4 Gain = 2,

RF = 715 Ω,

6.3 RL = 100 Ω,

6.2

VO = 0.2 VPP, VS = ±5 V

6.1

5.9

5.8

Noninverting Gain − dB

5.7

5.6

100 k 1 M 10 M 100 M 1 G 10 G

f − Frequency − Hz

Figure 37

HARMONIC DISTORTION

OUTPUT VOLTAGE SWING

−50

−55

−60

−65

−70

−75

−80

−85

Harmonic Distortion − dBc

−90

−95

−100 0

HD2, RL = 499 Ω

HD2, RL = 100 Ω

HD3, RL = 499 Ω

HD3, RL = 100 Ω

Gain = 5 RF = 576 Ω f = 8 MHz VS = ±5 V

0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

VO − Output Voltage Swing − ± V

Figure 40

HARMONIC DISTORTION

OUTPUT VOLTAGE SWING

−40

−45

−50

−55

−60

−65

−70

−75

−80

−85

Harmonic Distortion − dBc

−90

−95

−100 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

HD2, RL = 499 Ω

HD2, RL = 100 Ω

HD3, RL = 100 Ω

HD3, RL = 499 Ω

VO − Output Voltage Swing − ± V

Figure 41

Gain = 5 RF = 576 Ω f = 32 MHz VS = ±5 V

DISTORTION

−40

−45

−50

−55

−60

−65

−70

−75

−80

−85

−90

Third-Order Intermodulation Distortion − dBc

10 100 200

FREQUENCY

RL = 100 Ω VO = 2VPP Envelope VS = ±5 V 200 kHz Tone Spacing

G = 2, RF = 715 Ω

G = 10, RF = 464 Ω

f − Frequency − MHz

G = 5, RF = 576 Ω

Figure 42

THIRD-ORDER OUTPUT

INTERCEPT POINT

VO = 2 VPP Envelope RL = 100 Ω VS = ±5 V

200 kHz Tone Spacing

Third-Order Output Intersept Point − dBm

FREQUENCY

G = 10, RF = 464 Ω

G = 2, RF = 715 Ω

G = 5, RF = 576 Ω

20 40 60 80 10

f − Frequency − MHz

Figure 43

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S−Parameter − dB

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SLOS416A − JUNE 2003 − REVISED JANUARY 2004

S − PARAMETER

FREQUENCY

VS = ±5 V Gain = +10 C = 0 pF

−20

S22

−40

−60

S11

S−Parameter − dB

−80

−100 1 M 10 M 100 M 10 G

f − Frequency − Hz

50 Ω Source

−

50 Ω

1 G

Figure 44

NONINVERTING SMALL-SIGNAL

TRANSIENT RESPONSE

0.3

0.2

0.1

−0.1

− Output Voltage − V O

−0.2

−0.3

Output

Input

Gain = 2 RL = 100 Ω RF = 715 Ω VS = ±5 V

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

t − Time − µs

S − PARAMETER

FREQUENCY

VS = ±5 V Gain = +10

−20

C = 3.3 pF

−40

S22

S12

−60

50 Ω

S11

−80

50 Ω

−100 1 M 10 M 100 M 10 G

Source

f − Frequency − Hz

S12

−

50 Ω

1 G

50 Ω

6000

Gain = 2 RL = 100 Ω

5000

RF = 715 Ω

sµ

VS = ±5 V

4000

3000

2000

SR − Slew Rate −

1000

012345

Figure 45

SLEW RATE

OUTPUT VOLTAGE

Rise

Fall

VO − Output Voltage − V

Figure 46

INVERTING LARGE-SIGNAL

TRANSIENT RESPONSE

2.5 2

1.5 1

0.5 0

−0.5

−1

− Output Voltage − V O

−1.5

−2

−2.5

−3

Gain = −5 RL = 100 Ω RF = 549 Ω VS = ±5 V

Input

Output

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

t − Time −µs

OVERDRIVE RECOVERY TIME

G = 2,

−2

− Output Voltage − V O

−4

−6 0 0.2 0.4 0.6 0.8 1

t − Time − µs

RF = 715 Ω, VS = ±5 V

−1

− Input Voltage − VV

−2

−3

Figure 47

Figure 48

Figure 49

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SLOS416A − JUNE 2003 − REVISED JANUARY 2004

APPLICATION INFORMATION

WIDEBAND, NONINVERTING OPERATION

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Table 1. Recommended Resistor Values for

Optimum Frequency Response

The THS3201 is a unity gain stable 1.8-GHz current-feedback operational amplifiers, designed to operate from a ±3.3-V to ±7.5-V power supply.

Figure 50 shows the THS3201 in a noninverting gain of 2V/V configuration typically used to generate the performance curves. Most of the curves were characterized using signal sources with 50-Ω source impedance, and with measurement equipment presenting a 50-Ω load impedance. The 49.9-Ω shunt resistor at the V

terminal in Figure 50 matches the source impedance of

the test generator.

7.5 V +V

50 Ω Source

49.9 Ω

768 Ω

THS3201

−7.5 V

100 pF

768 Ω

100 pF

−V

0.1 µF 6.8 µF

49.9 Ω

50 Ω

0.1 µF 6.8 µF +

THS3201 RF for AC When R

Gain (V/V)

−2 ±7.5 and ±5 287 576

−5 ±7.5 and ±5 110 549

−10 ±7.5 and ±5 49.9 499

Supply Voltage

(V)

±7.5 — 1.2 k

±5 — 1.2 k

±7.5 768 768

±5 715 715

±7.5 154.9 619

±5 143 576

±7.5 54.9 487

±5 51.1 464

±7.5 619 619

±5 576 576

= 100 Ω

load

RG (Ω) RF (Ω)

WIDEBAND, INVERTING GAIN OPERATION

Figure 51 shows the THS3201 is a typical inverting gain configuration where the input and output impedances and signal gain from Figure 50 are retained in an inverting circuit configuration.

7.5 V

100 pF

0.1 µF 6.8 µF

Figure 50. Wideband, Noninverting Gain

Configuration

Unlike voltage-feedback amplifiers, current-feedback amplifiers are highly dependent on the feedback resistor R

for maximum performance and stability . Table 1 shows

the optimal gain setting resistors R

and RG at different

gains to give maximum bandwidth with minimal peaking in the frequency response. Higher bandwidths can be achieved, at the expense of added peaking in the frequency response, by using even lower values for R Conversely, increasing R

decreases the bandwidth, but

stability is improved.

THS3201

50 Ω Source

287 Ω

60.4 Ω

−7.5 V

576 Ω

100 pF

−V

49.9 Ω

50 Ω

0.1 µF 6.8 µF +

Figure 51. Wideband, Inverting Gain

Configuration

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SINGLE SUPPLY OPERATION

The THS3201 has the capability to operate from a single supply voltage ranging from 6.6V to 15V. When operating from a single power supply, care must be taken to ensure the input signal and amplifier is biased appropriately to allow for the maximum output voltage swing. The circuits shown in Figure 52 demonstrate methods to configure an amplifier in a manner conducive for single supply operation

50 Ω Source

60.4 Ω

49.9 Ω

768 Ω

THS3201

768 Ω

576 Ω

THS3201

287 Ω

49.9 Ω

50 Ω

49.9 Ω

50 Ω

Ω

THS3201

75 Ω

±7.5 V

−

±7.5 V

Ω

75-Ω Transmission Line

75 Ω

n Lines

75 Ω

O(1

O(n

Figure 53. Video Distribution Amplifier

Application

ADC DRIVER APPLICATION

The THS3201 can be used as a high-performance ADC driver in applications like radio receiver IF stages, and test and measurement devices. All high-performance ADCs have differential inputs. The THS3201 can be used in conjunction with a transformer as a drive amplifier in these applications. Figure 54 and Figure 55 show two different approaches.

In Figure 54, a transformer is used after the amplifier to convert the signal to differential. The advantage of this approach is fewer components are required. R are required for impedance matching the transformer.

OUT

and R

Figure 52. DC-Coupled Single Supply Operation

VIDEO AND HDTV DRIVERS

The exceptional bandwidth and slew rate of the THS3201 matches the demands for professional video and HDTV. Most commercial HDTV standards requires a video passband of 30-MHz. To ensure high signal quality with minimal degradation of performance, a 0.1-dB gain flatness should be at least 7x the passband frequency to minimize group delay variations—requiring 210-MHz

0.1-dB frequency flatness from the amplifier. High slew rates ensures there is minimal distortion of the video signal. Component video and RGB video signals require fast transition times and fast settling times to keep a high signal quality. The THS8135, for example, is a 240 MSPS video DAC and has a transition time approaching 4-ns. The THS3201 is a perfect candidate for interfacing the output of such high-performance video components.

S+

0.1 µF

THS3201

0.1 µF

1:n

OUT

S−

24.9 Ω

47pF

ADC

0.1 µF

Figure 54. Differential ADC Driver Circuit 1

In Figure 55, a transformer is used before two amplifiers to convert the signal to differential. The two amplifiers then amplify the differential signal. The advantage to this approach is each amplifier is required to drive half the voltage as before. R

is used to impedance match the

transformer.

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SLOS416A − JUNE 2003 − REVISED JANUARY 2004

S+

0.1 µF

1:n

THS3201

24.9 Ω

47pF

24.9 Ω

47pF

ADC

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Placing this pole at about 10x the highest frequency of interest insures it has no impact on the signal. Since the resistor is typically a small value, it is very bad practice to place the pole at (or very near) frequencies of interest. At the pole frequency, the amplifiers sees a load with a magnitude of:

2ǸxR

If R is only 10 Ω, the amplifier is very heavily loaded above the pole frequency, and generates excessive distortion.

0.1 µF

S−

Figure 55. Differential ADC Driver Circuit 2

It is almost universally recommended to use a resistor and capacitor between the op amp’s output and the ADC’s input as shown in both Figures.

This resistor-capacitor (RC) combination has multiple functions:

D The capacitor is a local charge reservoir for ADC D The resistor isolates the amplifier from the ADC D In conjunction, they form a low-pass noise filter

During the sampling phase, current is required to charge the ADC’s input sampling capacitors. By placing external capacitors directly at the input pins, most of the current is drawn from them. They are seen as a very low impedance source. They can be thought of as serving much the same purpose as a power supply bypass capacitor; to supply transient current, with the amplifier then providing the bulk charge.

Typically, a low-value capacitor in the range of 10 pF to 100 pF provides the required transient charge reservoir.

The capacitance and the switching action of the ADC is one of the worst loading scenarios that a high-speed amplifier encounters. The resistor provides a simple means of isolating the associated phase shift from the feedback network and maintaining the phase margin of the amplifier.

DAC DRIVER APPLICATION

The THS3201 can be used as a high-performance DAC output driver in applications like radio transmitter stages, and arbitrary waveform generators. All high-performance DACs have differential current outputs. Two THS3201s can be used as a differential drive amplifier in these applications as shown in Figure 56.

on the DAC output is used to convert the output

current to voltage. The 24.9-Ω resistor and 47-pF capacitor between each DAC output and the op amp input is used to reduce the images generated at multiples of the sampling rate. The values shown form a pole a 136 MHz. R

sets the output impedance of each amplifier.

OUT

S+

0.1 µF

DAC

IOUT1

IOUT2

24.9 Ω

47pF

0.1 µF

THS3201

0.1 µF

THS3201

S−

OUT

OUT1

OUT

OUT2

Typically , a low value resistor in the range of 10 Ω to 100 Ω provides the required isolation. Together, the R and C form a real pole in the s-plane located at the frequency:

2pRC

Figure 56. Differential DAC Driver Circuit

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SLOS416A − JUNE 2003 − REVISED JANUARY 2004

POWER SUPPLY

The performance of the THS3201 is dependent upon the power supply. Slew rate, bandwidth, and distortion are graphed against the power supply to highlight this dependence. As the power supply is increased from ±5 V to ±7.5 V, the slew rate increases, the bandwidth increases, and the distortion improves.

11000 10000

9000 8000

µs

7000 6000 5000 4000

Slew Rate − V/

3000 2000

1000

01234 5678

Figure 57. Slew Rate vs Output Voltage Step

−45

−50

−55

−60

−65

−70

−75

−80

−85

2nd Harmonic Distortion − dBc

−90

−95 1

Rise VS = ± 7.5 V RF = 768 Ω

Rise VS = ± 5 V RF = 715 Ω

Fall VS = ± 5 V RF = 715 Ω

VO − Output Voltage Step − V

VS = ± 5 V RF = 715 Ω

VS = ± 7.5 V RF = 768 Ω

Gain = +2 RL = 100 Ω VO = 2 V

10 100

f − Frequency − MHz

Fall VS = ± 7.5 V RF = 768 Ω

Gain = +2 RL = 100 Ω

910

Gain = +2

−55

RL = 100 Ω VO = 2 V

−60

−65

−70

−75

−80

−85

−90

3 rd Harmonic Distortion − dBc

−95

−100 1

VS = ± 5 V RF = 715 Ω

f − Frequency − MHz

VS = ± 7.5 V RF = 768 Ω

10 100

igure 59. 3rd Harmonic Distortion vs Frequenc

5 4

VS = ± 5 V

RF = 715 Ω

Noninverting Gain − dB

Gain = +2

RL = 100 Ω VO = 2 V

10 100 1 k 10 k

f − Frequency − Hz

VS = ± 7.5 V RF = 768 Ω

Figure 60. Noninverting Small Signal

Frequency Response

Figure 58. 2nd Harmonic Distortion vs Frequency

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PRINTED-CIRCUIT BOARD LAYOUT TECHNIQUES FOR OPTIMAL PERFORMANCE

Achieving optimum performance with high frequency amplifier-like devices in the THS3201 requires careful attention to board layout parasitic and external component types.

Recommendations that optimize performance include:

D Minimize parasitic capacitance to any ac ground for all

of the signal I/O pins. Parasitic capacitance on the output and input pins can cause instability. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board.

D Minimize the distance (< 0.25”) from the power supply

pins to high frequency 0.1-µF and 100 pF decoupling capacitors. At the device pins, the ground and power plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power supply connections should always be decoupled with these capacitors. Larger (6.8 µF or more) tantalum decoupling capacitors, effective at lower frequency, should also be used on the main supply pins. These may be placed somewhat farther from the device and may be shared among several devices in the same area of the PC board. The primary goal is to minimize the impedance seen in the differential-current return paths. For d r i v i n g dif ferential loads with the THS3201, adding a capacitor between the power supply pins improves 2nd order harmonic distortion performance. This also minimizes the current loop formed by the differential drive.

D Careful selection and placement of external

components preserve the high frequency performance of the THS3201. Resistors should be a very low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Again, keep their leads and PC board trace length as short as possible. Never use wirebound type resistors in a high frequency application. Since the output pin and inverting input pins are the most sensitive to parasitic capacitance, always position the feedback and series output resistors, if any, as close as possible to the inverting input pins and output pins. Other network components, such as input termination resistors, should be placed close to the gain-setting resistors. Even with a low parasitic capacitance shunting the external resistors, excessively high resistor values can create significant time constants that can degrade performance. Good axial metal-film or surface-mount

resistors have approximately 0.2 pF in shunt with the resistor. For resistor values > 2.0 kΩ, this parasitic capacitance can add a pole and/or a zero that can effect circuit operation. Keep resistor values as low as possible, consistent with load driving considerations.

D Connections to other wideband devices on the board

may be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50 mils to 100 mils) should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and determine if isolation resistors on the outputs are necessary. Low parasitic capacitive loads (< 4 pF) may not need an R since the THS3201 is nominally compensated to operate with a 2-pF parasitic load. Higher parasitic capacitive loads without an RS are allowed as the signal gain increases (increasing the unloaded phase margin). If a l o n g t r a c e i s r e q u i r e d , a n d t h e 6 - d B s i g n a l loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques).

A 50-Ω environment is not necessary onboard, and in fact, a higher impedance environment improves distortion as shown in the distortion versus load plots. With a characteristic board trace impedance based o n board material and trace dimensions, a matching series resistor into the trace from the output of the THS3201 is used as well as a terminating shunt resistor at the input of the destination device.

Remember also that the terminating impedance is t h e parallel combination of the shunt resistor and the input impedance of the destination device: this total effective impedance should be set to match the trace impedance. If the 6-dB attenuation of a doubly terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case. This does not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, there is some signal attenuation due to the voltage divider formed by the series output into the terminating impedance.

D Socketing a high speed part like the THS3201 is not

recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the THS3201 parts directly onto the board.

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SLOS416A − JUNE 2003 − REVISED JANUARY 2004

PowerPAD DESIGN CONSIDERATIONS

The THS3201 is available in a thermally-enhanced PowerPAD family of packages. These packages are constructed using a downset leadframe upon which the die is mounted [see Figure 61(a) and Figure 61(b)]. This arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see Figure 61(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance can be achieved by providing a good thermal path away from the thermal pad.

The PowerPAD package allows for both assembly and thermal management in one manufacturing operation. During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be soldered to a copper area underneath the package. Through the use of thermal paths within this copper area, heat can be conducted away from the package into either a ground plane or other heat dissipating device.

The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of surface mount with the, heretofore, awkward mechanical methods of heatsinking.

DIE

Side View (a)

DIE

End View (b)

Thermal

Pad

Bottom View (c)

Although there are many ways to properly heatsink the PowerPAD package, the following steps illustrate the recommended approach.

0.205

0.060

Pin 1

0.030

0.075 0.025

0.010 vias

0.013

0.035

Top View

0.017

0.09

0.040

Figure 62. DGN PowerPAD PCB Etch and Via

Pattern

Figure 61. Views of Thermally Enhanced Package

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SLOS416A − JUNE 2003 − REVISED JANUARY 2004

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PowerPAD PCB LAYOUT CONSIDERATIONS

1. Prepare the PCB with a top side etch pattern as shown in Figure 62. There should be etch for the leads as well as etch for the thermal pad.

2. Place five holes in the area of the thermal pad. These holes should be 10 mils in diameter. Keep them small so that solder wicking through the holes is not a problem during reflow.

3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps dissipate the heat generated by the THS3201 IC. These additional vias may be larger than the 10-mil diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad area to be soldered so that wicking is not a problem.

4. Connect all holes to the internal ground plane.

5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the holes under the THS3201 PowerPAD package should make their connection to the internal ground plane with a complete connection around the entire circumference of the plated-through hole.

6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five holes exposed. The bottom-side solder mask should cover the five holes of the thermal pad area. This

prevents solder from being pulled away from the thermal pad area during the reflow process.

7. Apply solder paste to the exposed thermal pad area and all of the IC terminals.

8. With these preparatory steps in place, the IC is simply placed in position and run through the solder reflow operation as any standard surface-mount component. This results in a part that is properly installed.

POWER DISSIPATION AND THERMAL CONSIDERATIONS

To maintain maximum output capabilities, the THS3201 does not incorporate automatic thermal shutoff protection. The designer must take care to ensure that the design does not violate the absolute maximum junction temperature of the device. Failure may result if the absolute maximum junction temperature of 150°C is exceeded. For best performance, design for a maximum junction temperature of 125°C. Between 125°C and 150°C, damage does not occur, but the performance of the amplifier begins to degrade.

The thermal characteristics of the device are dictated by the package and the PC board. Maximum power dissipation for a given package can be calculated using the following formula.

max

Dmax

where: P

is the maximum power dissipation in the

Dmax

amplifier (W). T

is the absolute maximum junction

max

temperature (°C). TA is the ambient temperature (°C).

= θJC + θ

is the thermal coefficient from the silicon

junctions to the case (°C/W).

is the thermal coefficient from the case to

ambient air (°C/W).

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SLOS416A − JUNE 2003 − REVISED JANUARY 2004

For systems where heat dissipation is more critical, the THS3201 i s o f fered in an 8-pin MSOP with PowerPAD and the THS3201 is available in the SOIC−8 PowerPAD package offering even better thermal performance. The thermal coefficient for the PowerPAD packages are substantially improved over the traditional SOIC. Maximum power dissipation levels are depicted in the graph for the available packages. The data for the PowerP AD packages assume a board layout that follows the PowerPAD layout guidelines referenced above and detailed in the PowerPAD application note number SLMA002. The following graph also illustrates the effect of not soldering the PowerPAD to a PCB. The thermal impedance increases substantially which may cause serious heat and performance issues. Be sure to always solder the PowerPAD to the PCB for optimum performance.

4.0

3.5

3.0

2.5

2.0

1.5

1.0

− Maximum Power Dissipation − W

0.5

Results are With No Air Flow and PCB Size = 3”x3”

θJA = 158°C/W

0.0

−40 −20 0 20 40 60 80 100

TA − Free-Air Temperature − °C

θJA = 58.4°C/W

θJA = 58.4°C/W for 8-Pin MSOP w/PowerPad (DGN) θJA = 98°C/W for 8-Pin SOIC High Test PCB (D) θJA = 158°C/W for 8-Pin MSOP w/PowerPad w/o Solder

TJ = 125°C

θJA = 98°C/W

quantify because the signal pattern is inconsistent, but an estimate of the RMS power dissipation can provide visibility into a possible problem.

DESIGN TOOLS

Evaluation Fixture, Spice Models, and Applications Support

Texas Instruments is committed to providing its customers with the highest quality of applications support. To support this goal an evaluation board has been developed for the THS3201 operational amplifier. The board is easy to use, allowing for straightforward evaluation of the device. The evaluation board can be ordered through the Texas Instruments web site, www.ti.com, or through your local Texas Instruments sales representative. The schematic diagram, board layers, and bill of materials of the evaluation boards are provided below.

J9*

C8*

Not Populate

Vout

Vs+

Vin

−

0 Ω

Vin+

49.9 Ω

*Does Not Apply to the THS3201

768 Ω

2 3

7418

_ +

Vs−

768 Ω

C7*

GND

49.9 Ω

J8*

Ref

TP1

Figure 63. Maximum Power Dissipation vs

Ambient Temperature

When determining whether or not the device satisfies the maximum power dissipation requirement, it is important to not only consider quiescent power dissipation, but also dynamic power dissipation. Often times, this is difficult to

VS−

22 µF

FB1

C6 C5

0.1 µF

VS−

100 pF

VS+

100 pF 0.1 µF

FB2

VS+

Figure 64. THS3201 EVM Circuit Configuration

22 µ

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SLOS416A − JUNE 2003 − REVISED JANUARY 2004

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Figure 65. THS3201 EVM Board Layout (Top

Layer)

Figure 67. THS3201 EVM Board Layout (Third

Layer, Power)

Figure 66. THS3201 EVM Board Layout (Second

Layer, Ground)

Figure 68. THS3201 EVM Board Layout (Bottom

Layer)

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SLOS416A − JUNE 2003 − REVISED JANUARY 2004

Table 2. Bill of Materials

THS3201DGN E V M

Item Description

1 Bead, ferrite, 3 A, 80 Ω 1206 FB1, FB2 2 (Steward) HI1206N800R−00 2 Cap, 22 µF , tanatalum, 25V, 10% D C1, C2 2 (AVX) TAJD226K025R 3 Cap, 100 pF, ceramic, 5%, 150V AQ12 C4, C5 2 (AVX) AQ12EM101JAJME 4 Cap, 0.1 µF, ceramic, X7R, 50V 0805 C3, C6 2 (A VX) 08055C104KAT2A 6 Open 0805 R7 1 7 Resistor, 49.9 Ω, 1/8W, 1% 0805 R6 1 (Phycomp) 9C08052A49R9FKHFT

9 Resistor, 768 Ω, 1/8W, 1% 0805 R3, R5 2 (Phycomp) 9C08052A7680FKHFT 10 Open 1206 C7, C8 2 11 Resistor, 0 Ω, 1/4W, 1% 1206 R2 1 (KOA) RK73Z2BLTD 12 Resistor, 49.9 Ω, 1/4W, 1% 1206 R4 1 (Phycomp) 9C12063A49R9FKRFT 13 Test point, black TP1 1 (Keystone) 5001 14 Open J8, J9 2 15 Jack, Banana Recptance, 0.25” dia. hole J5, J6, J7 3 (HH Smith) 101 16 Connector, edge, SMA PCB jack J1, J2, J4 3 (Johnson) 142−0701−801 17 Standoff, 4−40 hex, 0.625” length 4 (Keystone) 1804 18 Screw, Phillips, 4−40, .250” 4 SHR−0440−016−SN 19 IC, THS3201 U1 1 (TI) THS3201DGN 20 Board, printed circuit 1 (TI) Edge # 6447972 Rev.A

NOTE:The components shown in the BOM were used in test by TI.

SMD

Size

Ref Des

PCB

Quantity

Manufacturer’s Part Numb e r

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Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for video and RF-amplifier circuits where parasitic capacitance and inductance ca n h a v e a major ef fect o n circuit performance. A SPICE model for the THS3201 is available through either the Texas Instruments web site (www.ti.com) or as one model on a disk from the Texas Instruments Product Information Center (1–800–548–6132). The PIC is also available for design assistance and detailed product information at this number. These models do a good job of predicting small-signal ac and transient performance under a wide variety of operating conditions. They are not intended to model the distortion characteristics of the amplifier, nor do they attempt to distinguish between the package types in their small-signal ac performance. Detailed information about what is and is not modeled is contained in the model file itself.

ADDITIONAL REFERENCE MATERIAL

PowerPAD Made Easy, application brief (SLMA004) PowerPAD Thermally Enhanced Package, technical brief

(SLMA002) Voltage Feedback vs. Current Feedback amplifiers,

(SLVA051) Current Feedback Analysis and Compensation

(SLOA021) Current Feedback Amplifiers: Review, Stability, and

Application (SBOA081) Effect of parasitic capacitance in op amp circuits

(SLOA013)

PACKAGE OPTION ADDENDUM

www.ti.com

11-Feb-2005

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package

Drawing

Pins Package

Qty

Eco Plan

THS3201D ACTIVE SOIC D 8 75 Pb-Free

THS3201DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS &

no Sb/Br)

THS3201DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS &

no Sb/Br)

THS3201DGK ACTIVE MSOP DGK 8 100 Green (RoHS &

no Sb/Br)

THS3201DGKR ACTIVE MSOP DGK 8 2500 Green (RoHS &

no Sb/Br)

THS3201DGN ACTIVE MSOP-

Power

DGN 8 80 Green (RoHS &

no Sb/Br)

PAD

THS3201DGNR ACTIVE MSOP-

Power

DGN 8 2500 Green (RoHS &

no Sb/Br)

PAD

THS3201DR ACTIVE SOIC D 8 2500 Pb-Free

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(RoHS)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-2-260C-1YEAR/

Level-1-220C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-2-260C-1YEAR/

Level-1-220C-UNLIM

(3)

(2)

Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional

product content details.

None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight.

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder

temperature.

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TEXAS INSTRUMENTS THS3201 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual