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Copyright 2000, Texas Instruments Incorporated
How to Use This Manual
This document contains the following chapters:
Chapter 1 –Introduction to the MSP53C391 and MSP53C392 Speech
Chapter 2 –MSP53C391 Hardware Description
Chapter 3 –MSP53C392 Hardware Description
Chapter 4 –MSP53C391 and MSP53C392 Software Description
Appendix A –Editing Tools and Data Preparation
Preface
Read This First
Synthesizers
Appendix B –FM Synthesis
Appendix C –Listing of FMequM2.inc
Appendix D –MSP53C391/392 Timing Considerations
Appendix E –Listing of FM2INTR1.inc
Appendix F –MSP53C391 and MSP53C392 Data Sheet
Related Documentation From Texas Instruments
MSP50x3x Mixed-Signal Processor User’s Guide
(Literature Number SLOU006B)
Read This First
iii
iv
Contents
Contents
1Introduction to the MSP53C391 and MSP53C392 Speech Synthesizers1-1. . . . . . . . . . . . . .
MSP53C391 and MSP53C392 are standard slave synthesizers from Texas
Instruments that accept compressed speech data from another microprocessor and produce speech with that data. This allows the MSP53C391 and
MSP53C392 to be used with a master microprocessor in the various speech
products including electronic learning aids, games, and toys.
The TI MSP53C391 and MSP53C392 support several different speech synthesis algorithms to permit tradeoffs to meet the different price performance
requirements of different markets. They also incorporate a two-channel FM
synthesis routine for music generation.
Both the MSP53C391 and MSP53C392 are special programs that run on the
MSP50C3x device. For more information about the MSP50C3x, please refer
to the
MSP50x3x User’s Guide
(literature number: SLOU006B)
1.2Features
Wide ranges of algorithms are incorporated in one chip. This allows the
user to choose from a low bit rate to high-quality synthesizing routines for
their application. Algorithms included are:
Software selectable 8-kHz or 10-kHz speech sample rate
Three different interface options to support different pin count require-
ments
32-Ω speaker direct drive capability
Internally generated clock requires no external components
Maximum 10-µA standby current in sleep mode
Digital volume control
Built-in, two general-purpose output pins for MSP53C391 pin expansion
1-2
1.3MSP53C391 and MSP53C392 Comparison
The MSP53C391 is optimized to support a 4-bit wide data transfer protocol.
The MSP53C392 is optimized to support an 8-bit wide data transfer protocol.
The use of the 4-bit wide protocol in the MSP53C391 frees up some I/O pins
that can be used for other purposes. These pins (EOS and BUSY) can be used
to simplify the interface by minimizing the need to periodically poll the
MSP53C391 for its current status.
The use of the 8-bit wide protocol in the MSP53C392 provides a more efficient
data transfer.
A detailed comparison of the two devices is listed in Table 1–1.
Table 1–1. MSP53C391 and MSP53C392 Comparison
Number of Data Lines4 bit8 bit
Number of Control Lines2 (Strobe & R/W)2 (Strobe & R/W)
Data RequestSupportedN/A
Separate EOS Line for Detecting
End-of-Speech
Pin ExpansionTwo expansion pinsN/A
MSP53C391 and MSP53C392 Comparison
MSP53C391MSP53C392
SupportedN/A
Introduction to the MSP53C391 and MSP53C392 Speech Synthesizers
1-3
Pin Assignments and Description
I/O
DESCRIPTION
1.4Pin Assignments and Description
Figure 1–1 shows the pin assignments for the MSP53C391. Table 1–2 provides pin functional descriptions. Figure 1–2 shows the pin assignments for
the MSP53C392. Table 1–3 shows the pin functional descriptions.
Figure 1–1. MSP53C391 Pin Assignments
MSP53C391
N PACKAGE
(TOP VIEW)
DATA2/EOS
DATA1
DATA0
OUT2
OUT1
EOS
R/W
OSC IN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DATA3/BUSY
STROB
IRQ
DAC+
DAC–
V
DD
V
SS
INIT
Table 1–2. MSP53C391 Terminal Functions
PIN
NAMENO.
DAC+13OD/A output. This output pulses high for positive output values. It remains low
when negative values are output.
DAC–12OD/A output. This output pulses high for negative output values. It remains
low when positive values are output.
DATA 0–33,2,1,16I/OData lines
EOS6OEnd of speech signal. Output high when end of speech is reached.
INIT9IInitialize input. When INIT goes low , the clock stops, the MSP53C391 goes into
low-power mode, the program counter is set to zero, and the contents of the
RAM are retained. An INIT
IRQ14ONegative-edge trigger interrupt request line. Connect to the external inter-
rupt of the master MCU for interrupt mode operation.
OUT 1–25,4OGeneral-purpose output ports used for pin expansion
OSC IN8IThis signal should be connected to VSS.
R/W7IRead/write select signal. Set high for read operations or cleared low for
write operations by the master processor.
STROB15IStrobe signal for read and write operations. Pulsed low for read or write
operations
V
DD
V
SS
11–5-V nominal supply voltage
10–Ground pin
pulse of 1 µs is sufficient to reset the processor.
1-4
Figure 1–2. MSP53C392 Pin Assignments
I/O
DESCRIPTION
MSP53C392
N PACKAGE
(TOP VIEW)
Pin Assignments and Description
DATA6/EOS
DATA5
DATA4
DATA3
DATA2
DATA1
R/W
OSC IN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DATA7/BUSY
STROB
DATA0
DAC+
DAC–
V
DD
V
SS
INIT
Table 1–3. MSP53C392 Terminal Functions
PIN
NAMENO.
DAC+13OD/A output. This output pulses high for positive output values. It remains
low when negative values are output.
DAC–12OD/A output. This output pulses high for negative output values. It remains
low when positive values are output.
DATA 0–714,6,5,4,
3,2,1,16
INIT9IInitialize input. When INIT goes low, the clock stops, the MSP53C392 goes
OSC IN8IThis signal should be connected to Vss.
R/W7IRead/write signal
STROB15IStrobe signal for read/write
V
DD
V
SS
11–5-V nominal supply voltage
10–Ground pin
I/OData lines
into low-power mode, the program counter is set to zero, and the contents of
the RAM are retained. An INIT
pulse of 1 µs is sufficient to reset the processor .
Introduction to the MSP53C391 and MSP53C392 Speech Synthesizers
1-5
D/A Information
1.5D/A Information
Two-Pin Push Pull (Option 1) is selected in MSP53C391 and MSP53C392 that
can directly drive a 32-Ω speaker . Please refer to the
Processor Users Guide
on the D/A and amplifier circuit.
1.6Algorithms Supported
LPC:D6 and 5220 format. Data rates 1.5 to 3 kbps at an 8-kHz sample
MELP: Data rates range form 2kbps ~ 3.5 kbps at an 8-kHz sample rate
CELP: Data rates can be selected form 4.2 kbps ~ 10.7kbps at an 8-kHz
sample rate
MSP50x3x Mixed Signal
(literature number: SPSU006B) for more information
rate
PCM:8 bit. Data rates is 64 kbps for 8 kHz sampling
FM: Frequency modulation for two-channel musical instrument
The MSP53C391 accepts data from the master microprocessor across four
data lines. The transfer of data is controlled by two control lines (R/W and
STROB). The data is loaded to an internal buffer and the synthesis process
reads the data from the internal buffer as needed. The MSP53C391 signals
that it is
condition that would prevent the MSP53C391 from accepting new data. This
signal is communicated to the master microprocessor using either the IRQ
BUSY signals.
Depending on the number of available pins on the master microprocessor,
three different connection options are provided to connect the master microprocessor to the MSP53C391. Whichever method is used, two operations
must be accomplished: 1) Determining if the MSP53C391 is ready to accept
new data, and if it is ready, 2) writing new data to the MSP53C391.
Two control lines are provided to enable the master microprocessor to accomplish these two tasks, STROB
not
ready to accept data when the buffer is full, or there is some other
or
and R/W.
The R/W line determines whether a read or a write operation is done to the
MSP53C391 when the STROB
is pulsed low. If the R/W is high, then a read
from the MSP53C391 is done when the STROB is pulsed low. If the R/W is low ,
then data is written to the MSP53C391 when the STROB is pulsed low.
Two signals are provided to determine if the MSP53C391 is ready or not ready
to accept new data. The BUSY
signal shares the same pin as the DA TA3 signal. During a read operation, this signal goes high to signal that the
MSP53C391 is ready for a write operation. If this signal is low during a read
operation, then the MSP53C391 is
An alternative to polling the BUSY
not
ready for a write operation.
signal is provided by the IRQ signal. This
signal goes from high to low when the MSP53C391 is ready for a write operation.
The EOS signal indicates whether or not the end-of-speech has been reached
by the synthesis process. It is set high by the MSP53C391 when the stop code
in the data stream is reached. This signal is provided on two pins. It can be read
directly on pin 6 (EOS), or during a read operation on pin 1 (DATA2/EOS).
Three methods are provided for interfacing the MSP53C391 to various microprocessors. This allows the designer to make trade-offs between the number
of device pins being used and the algorithm complexity for the interface to the
master microprocessor.
2-2
2.2Signal Description
Table 2–1. MSP53C391 Signal Description
Signal Description
Pin
NameNo.
DAC+
DAC–
DATA3/BUSY16BUSY signal can be obtained on DATA 3 during read operation. A high signal
DATA2/EOS1The EOS signal can be obtained on the DATA2 pin during a read operation. This
STROB15This is an active low strobe signal for the reading and writing operation from the
R/W7Read/write signal from master microprocessor. A high signal for a read operation
IRQ14When the data latched into the MSP53C391 is read and the MSP53C391 device is
EOS6This is an active high output signal that is asserted when end-of-speech is
OUT1–25,4General-purpose output port that can be controlled by the master microprocessor.
DATA 0–33,2,1,16 4-bit bidirectional data line
INIT9Reset signal. A low pulse to reset the chip. It can also be used to stop the
12
13
PDM-style DAC used for speech output.
indicates that the MSP53C391 is
indicates that the MSP53C391 is busy and the master should not write any
command or data to MSP53C391.
signal is normally low, but goes high when the end-of-speech code is reached in
the data stream.
master microprocessor. The data to be read is available when the strobe is active
(low) for the read operation. The data on the data line is latched into the
MSP53C391 on the raising edge of the strobe signal for the write operation.
and a low signal for a write operation.
ready to accept more data, a negative edge interrupt signal is generated to
interrupt the master. For proper operation of the interrupt function, a negative edge
triggered external interrupt input pin is required on the master microprocessor.
reached. It indicates that the speech synthesis process is finished. When a high is
detected on the EOS line by the master microprocessor, dummy bytes are written
to the MSP53C391 to reset the EOS. The next transfer can then be initiated after
the EOS was de-asserted. EOS also appears on the DATA2 pin during a read
operation for adopting different interfacing methods.
MSP53C391 operation during speech synthesis. Following the rising edge of the
pulse, a delay of up to 5 ms will be required to permit the MSP53C391 to com-
INIT
pletely initialize its internal condition.
Description
not
busy and ready to accept data. A low signal
MSP53C391 Hardware Description
2-3
Master Microprocessor Interface Description
2.3Master Microprocessor Interface Description
2.3.1Method 1: Polling
This method is used when it is important to minimize the total number of interface pins between the master microprocessor and the MSP53C391. A total of
three control lines and 4 data lines are required for this method. The two status
bits can be read from the MSP53C391 by manipulating the R/W
lines and reading the data lines.
:Read/write signal
DATA 0–3: 4-bit data line
BUSY
is ready to accept data.
EOS:End-of-speech data. A high signal indicates end-of-speech. Two bytes of dummy data writen resets
the EOS to low .
INIT
:Active low reset signal. The master microprocessor should issue a reset signal to MSP53C391 after
B. When not being used, the EOS and IRQ pins should be left unconnected.
MASTER
15
Output Port
Output Port
9
Output Port
16
I/O Port
I/O Port
I/O Port
I/O Port
14
:Active low strobe signal
:Active low busy signal form MSP53C391. A high signal indicates that the MSP53C391 is not busy and
power up to properly initialize the MSP53C391 device.
STROB
7
R/W
INIT
DATA3/BUSY
1
DATA2/EOS
2
DATA1
3
DATA0
6
EOS
IRQ
MSP53C391
13
12
DAC+
DAC–
TO SPEAKER OR
AMPLIFIER/FILTER
2-4
Read Operation
Master Microprocessor Interface Description
1)The master microprocessor sets R/W high to indicate a read operation.
2)The master microprocessor sets STROB to low and reads the state of
BUSY and EOS.
3)The master microprocessor sets STROB
If the BUSY signal was high in step 2, the MSP53C391 is
high.
not
busy and is
ready to accept a write operation. If the BUSY signal was low in step 2, the
MSP53C391 is
not
ready to accept a write operation and the read operation
should be repeated until BUSY is asserted high.
If EOS was high in step 2, the synthesis process has reached the end of the
speech data stream. In this case, the master microprocessor should stop trying to send data and reset the MSP53C391 to allow it to accept additional commands or synthesis data.
The frequency of the polling operation should be optimized to the data rate of
the algorithm being used to synthesize speech. If the polling operation is too
frequent, the MSP53C391 spends too much time servicing the polling operation and the quality of the synthetic speech may be affected. If the polling operation is too infrequent, the internal buffer may run out of data and the synthesis process can become corrupted. Normally , a polling frequency of four times
the bit rates of the speech data provides optimal transfer characteristics.
Example:
For 6.2 kbps CELP the frequency of polling would be
Write Operation
6.2
4
n
n = the number of bits transfered at a time
1)The master processor should determine that the MSP53C391 is ready to
accept data by reading the BUSY signal as described previously.
2)The master microprocessor clears R/W low to indicate a write operation
3)The master microprocessor presents valid data to the four data pins
(DATA0 – DATA3).
4)The master microprocessor pulses the STROB signal low and then high
to latch the data to the MSP53C391 input data latch.
5)The master microprocessor should do a read operation to determine that
the MSP53C391 is ready to accept additional data before attempting to
write more data.
MSP53C391 Hardware Description
2-5
Master Microprocessor Interface Description
If the EOS signal is asserted high during the read operation, the end-of-speech
has been reached and a reset operation should be performed prior to sending
new commands or speech data. The reset can be done in one of two ways:
Pulsing the INIT pin low and then waiting for the MSP53C391 to re-initialize
itself or by writing two dummy bytes as described in the following.
RESET Operation
1)Perform a read operation to determine that both the EOS and BUSY signals are high.
2)If both the EOS and BUSY signals are high, write 2 bytes of dummy data
to the MSP53C391 by repeating the write operation four times as described previously.
2.3.2Method 2: Interrupt 1
In this method, the IRQ pin of the MSP53C391 is connected to an external interrupt input pin of the master microprocessor. When the MSP53C391 is
busy and is ready to accept data, the IRQ signal goes low and provides a negative edge to trigger an interrupt in the master processor. This minimizes the
need to constantly poll the MSP53C391 while waiting for it to become ready
to accept new data.
: Negative edge interrupt to master microprocessor when MSP53C391 is not busy and ready to accept data.
14
IRQ
6
EOS
Read Operation
Master Microprocessor Interface Description
1)The master microprocessor sets R/W high to indicate a read operation.
2)The master microprocessor sets STROB to low and reads the state of
BUSY and EOS.
3)The master microprocessor sets STROB high.
The EOS is used to signal that the end-of-speech has been reached. In this
case, the master microprocessor should stop trying to send data and act to reset the MSP53C391 so as to prepare it to accept additional commands or synthesis data.
In this method, the BUSY signal is not normally used. Instead, the IRQ signal
is used to signal the need for new speech data. It pulses low then high to produce a negative edge signal to the master microprocessor when the
MSP53C391 becomes ready to accept a new write operation. It will remain low
until a new nibble is written. The master microprocessor should immediately
initiate a write operation when the IRQ
signal goes low. If the master microprocessor delays for too long a time before writing new data, it is possible that the
buffer will empty and the synthesis process will be interrupted or the quality of
speech will be degraded.
Write Operation
1)The master microprocessor should clear all pending interrupts and enable
the external interrupt.
2)The master microprocessor writes the first nibble of data by presenting
valid data on DA TA0 – DA TA3, setting R/W low to indicate a write operation
and pulsing STROB low and high to latch the data into the MSP53C391
input latch.
Subsequent data is written following the falling edge of the IRQ signal.
3)The master microprocessor waits for a falling edge on the IRQ signal.
4)Master microprocessor sets R/W high and pulses the STROB to read the
EOS signal.
5)The master microprocessor clears R/W low to indicate a write operation
6)The master microprocessor presents valid data (first nibble of the dummy
data if EOS is high or nibble of speech data if EOS is low) to the four data
pins (DATA0 – DATA3).
MSP53C391 Hardware Description
2-7
Master Microprocessor Interface Description
7)The master microprocessor pulses the STROB signal low and then high
to latch the data to the MSP53C391 input data latch.
8)A read operation should be performed just before each write operation to
ensure that the end-of-speech has not been reached.
If the EOS signal is asserted high during the read operation, the end-of-speech
has been reached and a reset operation should be performed prior to sending
new commands or speech data. The reset can be done in one of two ways:
Pulsing the INIT
itself or by writing two dummy bytes as described the following.
RESET Operation
1)Perform a read operation to determine that the EOS signal is high.
2)If the EOS signal is high, write 2 bytes of dummy data to the MSP53C391
by repeating the write operation four times as described previously.
pin low and then waiting for the MSP53C391 to re-initialize
2.3.3Method 3: Interrupt 2
This method is similar to method 2. The only difference is performing the read
operation is not necessary because the EOS and IRQ
reads.
1)The master microprocessor should clear all pending interrupts and enable
the external interrupt.
2)The master microprocessor writes the first nibble of data by presenting
valid data on DA TA0 – DA TA3, tying R/W to ground indicates a write operation and pulsing STROB low and high to latch the data into the
MSP53C391 input latch.
Subsequent data is written following the falling edge of the IRQ signal.
3)The master microprocessor waits for a falling edge on the IRQ signal.
4)The master microprocessor checks the EOS signal to verify that the endof-speech has not been reached. If the EOS is high, the end-of-speech
has been reached and the master microprocessor should stop trying to
send data and should reset the MSP53C391 as described in the following.
If the EOS is low, the end-of-speech has not been reached and the write
operation should continue with step 5.
5)Tie R/W
to ground indicates a write operation
6)The master microprocessor presents valid data to the four data pins
(DATA0 – DATA3).
7)The master microprocessor pulses the STROB signal low and then high
to latch the data to the MSP53C391 input data latch.
If the EOS signal is asserted high in step 4 (shown previously), the end-ofspeech has been reached and a reset operation should be performed prior to
sending new commands or speech data. The reset can be done in one of two
ways: Pulsing the INIT
pin low and then waiting for the MSP53C391 to re-ini-
tialize itself or by writing two dummy bytes to the MSP53C391.
MSP53C391 Hardware Description
2-9
Master Microprocessor Interface Timing
2.4Master Microprocessor Interface Timing
2.4.1Timing Method 1: Polling
Data Transfer
STROB
R/W
DATA0 – 3
DATA3/BUSY
DATA2/EOS
NOTE A: State A: Polling the status by reading the BUSY
State B: Write operation
AAAAABAA
End-of-Speech
STROB
R/W
DATA0 – 3
DATA3/BUSY
DATA2/EOS
NOTE A: State A: EOS detected by reading DATA 2/EOS
State B: Dummy write. A 4-nibble dummy write resets the EOS for the next transfer.
State C: Wait until the part is ready to accept dummy data (BUSY
State D: Check to see if the device is busy or not.
ABDBDCDBB
and EOS
high).
2-10
2.4.2Timing Method 2: Interrupt 1
Data Transfer
Master Microprocessor Interface Timing
STROB
R/W
DATA0 – 3
DATA2/EOS
IRQ
NOTE A: State A: Read the EOS state
State B: Write operation
AABB
End-of-Speech
STROB
R/W
DATA0 – 3
DATA2/EOS
IRQ
NOTE A: State A: EOS detected by read DATA2/EOS
State B: Dummy write. A 4-byte dummy write resets the EOS for the next transfer.
ABBBB
MSP53C391 Hardware Description
2-11
Master Microprocessor Interface Timing
2.4.3Timing Method 3: Interrupt 2
Data Transfer
STROB
R/W
DATA0 – 3
EOS
IRQ
NOTE A: State A: Write operation
End-of-Speech
A
STROB
R/W
DATA0 – 3
EOS
IRQ
NOTE A: State A: EOS detected by read on pin 6
State B: Dummy write. A 4-nibble dummy write resets the EOS for the next transfer.
BBB B
AA
2-12
2.5MSP53C391 Device Initialization
For proper operation, the MSP53C391 device should be initialized by sending
the following command sequence of bytes:
F,F,F,F,0,A,0,1,0,0,F,F ,F,F,F,F
Following this command sequence, the normal command sequence options
are available as described in Section 4.2 and onwards.
The function of this sequence is to properly initialize the synthesis engine by
speaking a short selection of LPC prior to speaking selections using other synthesis algorithms.
This initialization needs to be performed:
1)After you apply power to the device, or
2)When you reset the part by toggling the INIT pin.
The MSP53C392 accepts data from the master microprocessor across the
eight data lines. The transfer of data is controlled by two control lines (R/W and
STROB). The data is loaded to an internal buffer and the synthesis process
reads the data from the internal buffer as needed. The MSP53C392 signals
that it is
condition that would prevent the MSP53C392 from accepting new data. This
signal is communicated to the master microprocessor using BUSY
The MSP53C392 accepts data across an 8-bit wide data connection that is
controlled using two control lines (R/W
accomplished: 1) Determining if the MSP53C392 is ready to accept new data,
and if it is ready, 2) writing new data to the MSP53C392.
Two control lines are provided to enable the master microprocessor to accomplish these two tasks, STROB and R/W .
not
ready to accept data when the buffer is full, or there is some other
signal.
and STROB). Two operations must be
The R/W line determines whether a read or a write operation is done to the
MSP53C392 when the STROB is pulsed low. If the R/W is high, than a read
from the MSP53C392 is done when the STROB is pulsed low. If the R/W is low ,
then data is written to the MSP53C392 when the STROB
is pulsed low.
The BUSY signal shares the same pin as the DA T A7 signal. During a read operation, this signal goes high to signal that the MSP53C392 is ready for a write
operation. If this signal is low during a read operation, then the MSP53C392
is
not
ready for a write operation.
The EOS signal shares the same pin as the DA TA6 signal. During a read operation, this signal normally goes low, but goes high to signal that the
MSP53C392 has encountered an end-of-speech code in the data stream.
A negative going pulse on the INIT line can be used to reset the device. An INIT
pulse of 1 µs is enough to reset the device. Following the rising edge of the INIT
pulse, a delay of up to 5 ms will be required to permit the MSP53C391 and
MSP53C392 to completely initialize its internal condition.
3-2
3.2Signal Description
Table 3–1. MSP53C392 Signal Description
Signal Description
Pin
NameNo.
DAC+
DAC–
DATA7/BUSY 16The BUSY signal can be obtained on DATA 7 during a read operation. A high
DATA6 / EOS1The EOS signal can be obtained on DATA 6 during a read operation. This is an
R/W7Read/write signal from master microprocessor. A high signal for a read operation
STROB15This is an active low strobe signal for the reading and writing operation form
DATA 0–714,6,5,4
INIT9Reset signal. A low pulse to reset the chip. It can also be used to stop the
12
13
3,2,1,16
PDM-style DAC used for speech output.
signal indicates that the MSP53C392 is
low signal indicates that the MSP53C392 is BUSY and master should not write
any command or data to MSP53C392.
active high signal that is asserted when end-of-speech is reached. It indicates
that the speech synthesis is finished. When a high is detected on EOS by the
master microprocessor, the MSP53C392 should be reset.
and a low signal for a write operation.
master microprocessor. The data to be read is available when the strobe is
active (low) for the read operation. The data on the data line is latched into the
MSP53C392 on the rising edge of the strobe signal for the write operation.
8-bit bidirectional data line
MSP53C392 operation during speech synthesis. Following the rising edge of the
pulse, a delay of up to 5 ms will be required to permit the MSP53C392 to
INIT
completely initialize its internal condition.
Description
not
BUSY and ready to accept data. A
MSP53C392 Hardware Description
3-3
Master Microprocessor Interface Description
3.3Master Microprocessor Interface Description
3.3.1Method 1: Polling
Three control lines and eight I/O data lines are used in this interface. Data is
written to the MSP53C392 device and the status can be read back. Two status
bits (BUSY
that the MSP53C392 is busy and signal the end-of-speech has been reached.
The interfacing diagram is shown in Figure 3–1:
and EOS) can be read back by the master microprocessor to signal
MASTER
MICROPROCESSOR
Output Port
Output Port
Output Port
I/O Port
I/O Port
I/O Port
I/O Port
I/O Port
I/O Port
I/O Port
I/O Port
15
7
9
16
1
2
3
4
5
6
14
MSP53C392
STROB
R/W
INIT
DATA7/BUSY
DATA6/EOS
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
13
12
DAC+
DAC–
TO SPEAKER OR
AMPLIFIER/FILTER
NOTE A: STROB
R/W
DATA 0–7: 8-bit data line
BUSY
is ready to accept data.
EOS:End-of-speech data. A high signal indicates end-of-speech. Two bytes of dummy data written resets
INIT
3-4
:Active low strobe signal
:Read/write signal
:Active low busy signal form MSP53C392. A high signal indicates that the MSP53C392 is not busy and
the EOS to low.
:Active low reset signal. The master microprocessor should issue a reset signal to MSP53C392 after
power up to properly initialize the MSP53C392 device.
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