Texas Instruments MSP50C6xx User Manual
MSP50C6xx Mixed-Signal Processor
User’s Guide
Mixed Signal Products
SPSU014A
Printed on Recycled Paper
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products
or to discontinue any product or service without notice, and advise customers to obtain the latest
version of relevant information to verify , before placing orders, that information being relied on
is current and complete. All products are sold subject to the terms and conditions of sale supplied
at the time of order acknowledgment, including those pertaining to warranty , patent infringement,
and limitation of liability .
TI warrants performance of its semiconductor products to the specifications applicable at the
time of sale in accordance with TI’s standard warranty. Testing and other quality control
techniques are utilized to the extent TI deems necessary to support this warranty . Specific testing
of all parameters of each device is not necessarily performed, except those mandated by
government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and
operating safeguards must be provided by the customer to minimize inherent or procedural
hazards.
TI assumes no liability for applications assistance or customer product design. TI does not
warrant or represent that any license, either express or implied, is granted under any patent right,
copyright, mask work right, or other intellectual property right of TI covering or relating to any
combination, machine, or process in which such semiconductor products or services might be
or are used. TI’s publication of information regarding any third party’s products or services does
not constitute TI’s approval, warranty or endorsement thereof.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2001, Texas Instruments Incorporated
About This Manual
This user’s guide gives information for the MSP50C6xx mixed-signal proces-
sor. This information includes a functional overview, a detailed architectural
description, device peripheral functional description, assembly language
instruction listing, code development tools, applications, customer information, and electrical characteristics (in data sheet).
How to Use This Manual
This document contains the following chapters:
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Preface
Read This First
Chapter 1 –Introduction to the MSP50C6xx
Chapter 2 –MSP50C6xx Architecture
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Notational Conventions
This document uses the following conventions.
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Chapter 3 –Peripheral Functions
Chapter 4 –Assembly Language Instructions
Chapter 5 –Code Development Tools
Chapter 6 –Applications
Chapter 7 –Customer Information
Appendix A –Additional Information
Program listings, program examples, and interactive displays are shown
in a special typeface similar to a typewriter’s. Examples use a bold
version of the special typeface for emphasis; interactive displays use a
bold version of the special typeface to distinguish commands that you
enter from items that the system displays (such as prompts, command
output, error messages, etc.).
iiiRead This First
Notational Conventions
Here is a sample program listing:
0011 0005 0001 .field 1, 2
0012 0005 0003 .field 3, 4
0013 0005 0006 .field 6, 3
0014 0006 .even
Here is an example of a system prompt and a command that you might
enter:
C: csr –a /user/ti/simuboard/utilities
-
In syntax descriptions, the instruction, command, or directive is in a bold
typeface font and parameters are in an italic typeface. Portions of a syntax
that are in bold should be entered as shown; portions of a syntax that are
in italics describe the type of information that should be entered. Here is
an example of a directive syntax:
.asect ”section name”, address
.asect is the directive. This directive has two parameters, indicated by sec-
tion name and address. When you use .asect, the first parameter must be
an actual section name, enclosed in double quotes; the second parameter
must be an address.
-
Square brackets ( [ and ] ) identify an optional parameter. If you use an
optional parameter, you specify the information within the brackets; you
don’t enter the brackets themselves. Here’s an example of an instruction
that has an optional parameter:
LALK 16–bit constant [, shift]
The LALK instruction has two parameters. The first parameter, 16-bit constant, is required. The second parameter, shift, is optional. As this syntax
shows, if you use the optional second parameter, you must precede it with
a comma.
Square brackets are also used as part of the pathname specification for
VMS pathnames; in this case, the brackets are actually part of the pathname (they are not optional).
iv
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Braces ( { and } ) indicate a list. The symbol | (read as or) separates items
within the list. Here’s an example of a list:
{ * | *+ | *– }
This provides three choices: *, *+, or *–.
Unless the list is enclosed in square brackets, you must choose one item
from the list.
-
Some directives can have a varying number of parameters. For example,
the .byte directive can have up to 100 parameters. The syntax for this directive is:
.byte value1 [, ... , valuen]
This syntax shows that .byte must have at least one value parameter, but
you have the option of supplying additional value parameters, separated
by commas.
Information About Cautions and Warnings
This book may contain cautions and warnings.
This is an example of a caution statement.
A caution statement describes a situation that could potentially
damage your software or equipment.
This is an example of a warning statement.
Information About Cautions and Warnings
A warning statement describes a situation that could potentially
cause harm to you
The information in a caution or a warning is provided for your protection.
Please read each caution and warning carefully.
.
Trademarks
Intel, i486, and Pentium are trademarks of Intel Corporation.
Microsoft, Windows, Windows 95, and Windows 98 are registered trademarks of Microsoft Corporation.
vRead This First
vi
Contents
Contents
1 Introduction to the MSP50C6xx 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Features of the MSP50C6xx 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Applications 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Development Device: MSP50P614 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Functional Description for the MSP50C614 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 MSP50C601, MSP50C604, and MSP50C605 1-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 MSP50C6xx Architecture 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Architecture Overview 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Computation Unit 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.1 Multiplier 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.2 Arithmetic Logic Unit 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Data Memory Address Unit 2-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.1 RAM Configuration 2-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.2 Data Memory Addressing Modes 2-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Program Counter Unit 2-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 Bit Logic Unit 2-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6 Memory Organization: RAM and ROM 2-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.1 Memory Map 2-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.2 Peripheral Communications (Ports) 2-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.3 Interrupt Vectors 2-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.4 ROM Code Security 2-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.5 Macro Call Vectors 2-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7 Interrupt Logic 2-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8 Clock Control 2-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8.1 Oscillator Options 2-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8.2 PLL Performance 2-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8.3 Clock Speed Control Register 2-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8.4 RTO Oscillator Trim Adjustment 2-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.9 Timer Registers 2-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.10 Reduced Power Modes 2-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.11 Execution Timing 2-40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Contents
3 Peripheral Functions 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 I/O 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.1 General-Purpose I/O Ports 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.2 Dedicated Input Port F 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.3 Dedicated Output Port G 3-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.4 Branch on D Port 3-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.5 Internal and External Interrupts 3-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Digital-to-Analog Converter (DAC) 3-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.1 Pulse-Density Modulation Rate 3-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.2 DAC Control and Data Registers 3-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.3 PDM Clock Divider 3-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Comparator 3-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 Interrupt/General Control Register 3-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 Hardware Initialization States 3-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Assembly Language Instructions 4-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 Introduction 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 System Registers 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.1 Multiplier Register (MR) 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.2 Shift Value Register (SV) 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.3 Data Pointer Register (DP) 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.4 Program Counter (PC) 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.5 Top of Stack, (TOS) 4-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.6 Product High Register (PH) 4-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.7 Product Low Register (PL) 4-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.8 Accumulators (AC0–AC31) 4-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.9 Accumulator Pointers (AP0–AP3) 4-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.10 Indirect Register (R0–R7) 4-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.11 String Register (STR) 4-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.12 Status Register (STAT) 4-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 Instruction Syntax and Addressing Modes 4-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.1 MSP50P614/MSP50C614 Instruction Syntax 4-8. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.2 Addressing Modes 4-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.3 Immediate Addressing 4-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.4 Direct Addressing 4-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.5 Indirect Addressing 4-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.6 Relative Addressing 4-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.7 Flag Addressing 4-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.8 Tag/Flag Bits 4-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Contents
4.4 Instruction Classification 4-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.2 Class 2 Instructions: Accumulator and Constant Reference 4-28. . . . . . . . . . . . . .
4.4.3 Class 3 Instruction: Accumulator Reference 4-30. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.4 Class 4 Instructions: Address Register and Memory Reference 4-34. . . . . . . . . . .
4.4.5 Class 5 Instructions: Memory Reference 4-36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.6 Class 6 Instructions: Port and Memory Reference 4-38. . . . . . . . . . . . . . . . . . . . . .
4.4.7 Class 7 Instructions: Program Control 4-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.8 Class 8 Instructions: Logic and Bit 4-41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.9 Class 9 Instructions: Miscellaneous 4-42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5 Bit, Byte, Word and String Addressing 4-44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6 MSP50P614/MSP50C614 Computational Modes 4-49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7 Hardware Loop Instructions 4-53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8 String Instructions 4-55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.9 Lookup Instructions 4-57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.10 Input/Output Instructions 4-59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.11 Special Filter Instructions 4-59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.12 Conditionals 4-69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.13 Legend 4-70. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.14 Individual Instruction Descriptions 4-74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.15 Instruction Set Encoding 4-189. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.16 Instruction Set Summary 4-198. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Code Development Tools 5-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 Introduction 5-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2 MSP50C6xx Development Tools Guidelines 5-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.1 Categories of MSP50Cxx Development Tools 5-4. . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.2 Tools Definitions 5-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.3 Documentation 5-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3 MSP50C6xx Code Development Tools 5-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.1 System Requirements 5-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.2 Hardware Tools Setup 5-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4 Assembler 5-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.1 Assembler Directives 5-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5 C–– Compiler 5-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.1 Foreword 5-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.2 Variable Types 5-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.3 External References 5-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.4 C– – Directives 5-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.5 Include Files 5-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.6 Function Prototypes and Declarations 5-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.7 Initializations 5-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.8 RAM Usage 5-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.9 String Functions 5-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.10 Constant Functions 5-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ixContents
Contents
5.6 Implementation Details 5-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6.1 Comparisons 5-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6.2 Division 5-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6.3 Function Calls 5-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6.4 Programming Example 5-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6.5 Programming Example, C –– With Assembly Routines 5-29. . . . . . . . . . . . . . . . . .
5.7 C– – Efficiency 5-37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7.1 Real Time Clock Example 5-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.8 Beware of Stack Corruption 5-57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.9 Reported Bugs With Code Development Tool 5-58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 Applications 6-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1 Application Circuits 6-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2 Initializing the MSP50C6xx 6-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.1 File init.asm 6-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3 TI-T ALKS Example Code 6-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4 RAM Overlay 6-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.1 RAM Usage 6-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.2 RAM Overlay 6-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.3 Adding Customer Variables 6-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.4 Common Problems 6-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7 Customer Information 7-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1 Mechanical Information 7-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.1 Die Bond-Out Coordinates 7-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.2 Package Information 7-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2 Customer Information Fields in the ROM 7-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3 Speech Development Cycle 7-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.4 Device Production Sequence 7-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5 Ordering Information 7-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.6 New Product Release Forms (NPRF) 7-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A Additional Information A-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.1 Additional Information A-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
x
Figures
Figures
1–1 Functional Block Diagram for the MSP50C614/MSP50P614 1-5. . . . . . . . . . . . . . . . . . . . . . . .
1–2 Oscillator and PLL Connection 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–3 RESET Circuit 1-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–1 MSP50C6xx Core Processor Block Diagram 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–2 Computational Unit Block Diagram 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–3 Overview of the Multiplier Unit Operation 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–4 Overview of the Arithmetic Logic Unit 2-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–5 Overview of the Accumulators 2-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–6 Data Memory Address Unit 2-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–7 C6xx Memory Map (not drawn to scale) 2-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–8 Interrupt Initialization Sequence 2-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–9 PLL Performance 2-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–10 Instruction Execution and Timing 2-40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–1 PDM Clock Divider 3-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–2 Relationship Between Comparator/Interrupt Activity and the TIMER1 Control 3-16. . . . . . . .
4–1 Top of Stack (TOS) Register Operation 4-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–2 Relative Flag Addressing 4-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–3 Data Memory Organization and Addressing 4-45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–4 Data Memory Example 4-47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–5 FIR Filter Structure 4-59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–6 Setup and Execution of MSP50P614/MSP50C614 Filter Instructions, N+1 Taps 4-67. . . . . .
4–7 Filter Instruction and Circular Buffering for N+1 Tap Filter 4-68. . . . . . . . . . . . . . . . . . . . . . . . . .
4–8 Valid Moves/Transfer in MSP50P614/MSP50C614 Instruction Set 4-132. . . . . . . . . . . . . . . . .
5–1 10-Pin IDC Connector (top view looking at the board) 5-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–2 Hardware Tools Setup 5-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–1 Minimum Circuit Configuration for the C614/P614 Using a
6–2 Minimum Circuit Configuration for the C614/P614 Using a
7–1 100-Pin QFP Mechanical Information 7-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–2 64-Pin QFP Mechanical Information 7-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–3 120-Pin, Grid Array Package for the Development Device, MSP50P614 7-9. . . . . . . . . . . . . .
7–4 Bottom View of 120-Pin PGA Package of the MSP50P614 7-10. . . . . . . . . . . . . . . . . . . . . . . .
7–5 Speech Development Cycle 7-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Resistor-Trimmed Oscillator 6-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Crystal-Referenced Oscillator 6-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Tables
Tables
2–1 Signed and Unsigned Integer Representation 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–2 Summary of MSP50C614’s Peripheral Communications Ports 2-17. . . . . . . . . . . . . . . . . . . . .
2–3 Programmable Bits Needed to Control Reduced Power Modes 2-36. . . . . . . . . . . . . . . . . . . . .
2–4 Status of Circuitry When in Reduced Power Modes (Refer to Table 2–3) 2-37. . . . . . . . . . . .
2–5 How to Wake Up from Reduced Power Modes (Refer to Table 2–3 and Table 2–4) 2-38. . . .
2–6 Destination of Program Counter on Wake-Up Under Various Conditions 2-39. . . . . . . . . . . . .
3–1 Interrupts 3-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–2 State of the Status Register (17 bit) after RESET Low-to-High
4–1 Status Register (STAT) 4-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–2 Addressing Mode Encoding 4-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–3 Rx Bit Description 4-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–4 Addressing Mode Bits and {adrs} Field Description 4-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–5 MSP50P614/MSP50C614 Addressing Modes Summary 4-11. . . . . . . . . . . . . . . . . . . . . . . . . .
4–6 Auto Increment and Auto Decrement Modes 4-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–7 Flag Addressing Field {flagadrs} for Certain Flag Instructions (Class 8a) 4-12. . . . . . . . . . . . .
4–8 Initial Processor State for the Examples Before Execution of Instruction 4-13. . . . . . . . . . . . .
4–9 Indirect Addressing Syntax 4-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–10 Symbols and Explanation 4-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–1 1 Instruction Classification 4-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–12 Classes and Opcode Definition 4-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–13 Class 1 Instruction Encoding 4-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–14 Class 1a Instruction Description 4-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–15 Class 1b Instruction Description 4-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–16 Class 2 Instruction Encoding 4-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–17 Class 2a Instruction Description 4-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–18 Class 2b Instruction Description 4-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–19 Class 3 Instruction Encoding 4-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–20 Class 3 Instruction Description 4-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–21 Class 4a Instruction Encoding 4-34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–22 Class 4a Instruction Description 4-35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–23 Class 4b Instruction Description 4-35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–24 Class 4c Instruction Description 4-35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–25 Class 4d Instruction Description 4-35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–26 Class 5 Instruction Encoding 4-36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–27 Class 5 Instruction Description 4-36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(Bits 5 through 16 are left uninitialized) 3-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
xii
Tables
4–28 Class 6a Instruction Encoding 4-38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–29 Class 6a Instruction Description 4-38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–30 Class 6b Instruction Description 4-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–31 Class 7 Instruction Encoding and Description 4-40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–32 Class 8a Instruction Encoding 4-41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–33 Class 8a Instruction Description 4-42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–34 Class 8b Instruction Description 4-42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–35 Class 9a Instruction Encoding 4-43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–36 Class 9a Instruction Description 4-43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–37 Class 9b Instruction Description 4-43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–38 Class 9c Instruction Description 4-44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–39 Class 9d Instruction Description 4-44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–40 Data Memory Address and Data Relationship 4-46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–41 MSP50P614/MSP50C614 Computational Modes 4-50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–42 Hardware Loops in MSP50P614/MSP50C614 4-54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–43 Initial Processor State for String Instructions 4-55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–44 Lookup Instructions 4-57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–45 Auto Increment and Decrement 4-73. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–46 Addressing Mode Bits and adrs Field Description 4-73. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–47 Flag Addressing Syntax and BIts 4-73. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–48 Names for cc 4-88. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–1 String Functions 5-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–1 Signal and Pad Descriptions for the MSP50C614 7-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–2 Signal and Pad Descriptions for the MSP50C605 7-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–3 Signal and Pad Descriptions for the MSP50C601 7-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–4 Signal and Pad Descriptions for the MSP50C604 7-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
xiiiContents
xiv
Chapter 1
Introduction to the MSP50C6xx
The MSP50C6xx is a low cost, mixed signal controller, that combines a speech
synthesizer, general-purpose input/output (I/O), onboard ROM, and direct
speaker-drive in a single package. The computational unit utilizes a powerful
new DSP which gives the MSP50C6xx unprecedented speed and
computational flexibility compared with previous devices of its type. The
MSP50C6xx supports a variety of speech and audio coding algorithms,
providing a range of options with respect to speech duration and sound quality.
Topic Page
1.1 Features of the MSP50C6xx 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Applications 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Development Device: MSP50P614 1–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Functional Description for the MSP50C614 1–5. . . . . . . . . . . . . . . . . . . . . .
1.5 MSP50C601, MSP50C604, and MSP50C605 1–9. . . . . . . . . . . . . . . . . . . . .
1-1
Features of the MSP50C6xx
1.1 Features of the MSP50C6xx
-
Advanced, integrated speech synthesizer for high quality sound
-
Operates up to 12.32 MHz (performs up to 12.32 MIPS)
-
Very low-power operation, ideal for hand-held devices
-
Low voltage operation, sustainable by three batteries
-
Reduced power stand-by modes, less than 10 µA in deep-sleep mode
-
Supports high-quality synthesis algorithms such as MELP, CELP, LPC,
and ADPCM
-
Contains 32K words onboard ROM (2K words reserved)
-
Up to 2.36 Mbits of internal data ROM for speech storage
-
640 words RAM
-
Up to 64 input/output pins
-
Direct speaker driver, 32 Ω
-
One-bit comparator with edge-detection interrupt service
-
Resistor-trimmed oscillator or 32.768-kHz crystal reference oscillator
-
Serial scan port for in-circuit emulation and diagnostics
-
The MSP50C6xx is sold in die form or QFP package. An emulator device,
MSP50P614 is sold in a ceramic package for development.
-
The MSP50P614 devices operate from 4.0 Vdc to 6.0 Vdc, and
the MSP50C6xx devices operate from 3.0 Vdc to 5.2 Vdc
1-2
1.2 Applications
Applications
Due to its low cost, low-power consumption, and high programmability, the
MSP50C6xx is suitable for a wide variety of applications incorporating flexible
I/O and high-quality speech:
-
Consumer
-
Education
Toys and Games Electronic Learning Aids
Appliances Talking Dictionaries
Talking Clocks Language Translators
Navigation Aids Talking Books
-
Industrial
-
Medical
Warning Systems Controls Aids for the Handicapped
-
Telecom
-
Security
Answering Machines Security Systems
Voice Mail Systems Home Monitors
1-3Introduction to the MSP50C6xx
Development Device: MSP50P614
1.3 Development Device: MSP50P614
The MSP50P614 is an EPROM based version of the MSP50C614, and is
available in a 120-pin windowed ceramic pin grid array. This EPROM based
version of the device is only available in limited quantities to support software
development. Since the MSP50P614 program memory is EPROM, each
person doing software development should have several of these PGA
packaged devices.
The MSP50P614 is also used to emulate the MSP50C601, MSP50C604, and
MSP50C605 with the addition of external logic.
The MSP50C6xx code development software (EMUC6xx) supports non-realtime debugging by scanning the code sequence through the MSP50C6xx/
MSP50P614 scanport without programming the EPROM. However, the rate
of code execution is limited by the speed of the PC parallel port. Any
MSP50C6xx/MSP50P614 can be used in this debugging mode.
The MSP50P614 EPROM must be programmed to debug the code in real
time. The EMUC6xx software is used to program the EPROM, set a breakpoint, and evaluate the internal registers after the breakpoint is reached. If a
change is made to the code, the code will need to be updated and programmed
into another device while erasing previous devices. This cycle of programming, debugging, and erasing typically requires 10–15 devices to be in the
eraser at any one time, so 15–20 devices may be required to operate efficiently . The windowed PGA version of the MSP50P614 is required for this debugging mode.
Note:
The MSP50P614 operates with a voltage range of 4 V to 6 V. However, the
MSP50C6xx devices operate at a different voltage range (3 V to 5.2 V).
Please refer to the data sheet for specific device information.
1-4
Functional Description for the MSP50C614
1.4 Functional Description for the MSP50C614
The MSP50C614 device consists of a micro-DSP core, embedded program
and data memory , and a self-contained clock generation system. General-purpose periphery is comprised of 64 bits of flexible I/O. The block diagram appearing in Figure 1–1 gives an overview of the MSP50C614/MSP50P614
functionality.
Figure 1–1. Functional Block Diagram for the MSP50C614/MSP50P614
SCANIN
SCANOUT
SCANCLK
SYNC
TEST
PGMPULSE
DACP
DACM
RESET
OSCIN
OSCOUT
PLL
Scan Interface
Break Point
Emulation
OTP Program
Serial Comm.
(C6xx only)
(P614 only)
DAC 0x30
32 Ohm PDM
Initialization
Logic
OSC Reference
Resistor
Trimmed
32 kHz nominal
or
or
Crystal
Referenced
32.768 kHz
PLL Filter
V
V
Power (P614 only)
(EP)ROM 32k x (16 + 1) bit
Test-Area
(reserved)
User ROM 0x0800 to
INT vectors 0x7FF0 to
Core
Instr. Decoder
PCU Prog. Counter Unit
CU Computational Unit
TIMER1 PRD1
TIMER2
Clock Control
Gen. Control
Interrupt Processor
DMAU
RAM 640 x 17 bit
(data)
DDVPP
SS
55
0x0000 to
0x3A
PRD2
0x3E
FLAG
0x39
Data Mem. Addr.
0x07FF
0x7FEF
0x7FFF
TIM1
0x3B
TIM2
0x3F
0x3D
0x38
MASK
0x38
0x000 to
0x027F
A port I/O
Data 0x00
Control 0x04
B port I/O
Data 0x08
Control 0x0C
C port I/O
Data 0x10
Control 0x14
Comparator
1 bit: PD5 vs PD
D port I/O
Data 0x18
Control 0x1C
E port I/O
Data 0x20
Control 0x24
F port INPUT
Data 0x28
G port OUTPUT
Data 0x2C
4
+ –
PA0–7
8
PB0–7
8
PC0–7
8
PD0–7
8
PE0–7
8
PF0–7
8
PG0–15
16
1-5Introduction to the MSP50C6xx
Functional Description for the MSP50C614
The core processor is a general-purpose 16 bit micro-controller with DSP
capability. The basic core block includes a computational unit (CU), data
address unit, program address unit, two timers, eight level interrupt processor,
and several system and control registers. The core processor provides
break-point capability to the MSP50C6xx code development software
(EMUC6xx).
The processor is a Harvard type for efficient DSP algorithm execution. It requires separate program and data memory blocks to permit simultaneous access. The ROM has a protection scheme to prevent third-party pirating. It is
configured in 32K 17-bit words.
The total ROM space is divided into two areas: 1) The lower 2K words are reserved by T exas Instruments for a built-in self-test, 2) the upper 30K is for user
program/data.
The data memory is internal static RAM. The RAM is configured in 640 17-bit
words. Both memories are designed to consume minimum power at a given
system clock and algorithm acquisition frequency.
A flexible clock generation system is included that enables the software to
control the clock over a wide frequency range. The implementation uses a
phase-locked loop (PLL) circuit to generate the processor clock. The
Processor clock is programmable in 65.536-kHz steps between 64 kHz and
12.32 MHz. The PLL reference clock is also selectable; either a
resistor-trimmed oscillator or a crystal-referenced oscillator may be used.
Internal and peripheral clock sources are controlled separately to provide
different levels of power management (see Figure 1–2).
1-6
Figure 1–2. Oscillator and PLL Connection
a) Crystal Reference Oscillator Connections
OSCIN OSCOUT PLL
10 Mن
32.768 kHz†
Functional Description for the MSP50C614
MSP50P614
MSP50C6xx
10 Mن
†
Keep these components as close as possible to the OSCIN, OSC
22 pF†
b) Resistor Trim Oscillator Connections
MSP50C6xx
MSP50P614
OSCIN OSCOUT PLL
R
(RTO)
†
Keep these components as close as possible to the OSCIN, OSC
470 kΩ 1%†
=
The peripheral consists of five 8-bit wide general-purpose I/O ports, one 8-bit
wide dedicated input port, and one 16-bit wide dedicated output port. The
general-purpose I/O ports are bit-wise programmable as either
high-impedance inputs or as totem-pole outputs. They are controlled via
addressable I/O registers. The input-only port has a programmable pullup
option (100-kΩ minimum resistance) and a dedicated service interrupt. These
features make the input port especially useful as a key-scan interface.
22 pF†
, and PLL pins.
OUT
, and PLL pins.
OUT
C
(PLL)
C
= 3300 pF†
(PLL)
= 3300 pF†
A simple one-bit comparator is also included in the periphery . The comparator
is enabled by a control register, and its input pins are shared with two pins in
one of the general-purpose I/O ports.
1-7Introduction to the MSP50C6xx
Functional Description for the MSP50C614
Rounding out the MSP50C6xx periphery is a built in pulse-density-modulated
(PDM) digital-to-analog converter (DAC) with direct speaker-drive capability.
Typical connections to implement reset functionality are shown in Figure 1–3.
An external reset circuit is required to hold the reset pin low until the
MSP50C6xx power supply has stabilized in the specified voltage range. In
some cases, a simple reset circuit (as shown in Figure 1–3) can be used for
this purpose. However, this simple circuit may not be suitable for all applications. For example, if the power supply has an unpredictable rise time or has
intermittent voltage sags, the device may not initialize properly . The diode and
the switch shown in Figure 1–3 may be optional for some applications. The
diode provides a lower impedance path for the capacitor to discharge when
power is removed. This make the circuit more reliable when power is removed
and quickly reapplied.
Figure 1–3. RESET Circuit
(MSP50P614 only)
V
PP
V
DD
100 kΩ
†
Inside the
MSP50P614
MSP50C6xx
†
If it is necessary to use the software development tools to control the MSP50P614 in an application board, the 1 kΩ resistor is
needed to allow the development tool to over drive the RESET circuit on the application board.
‡
This Diode can be omitted (shorted) if the application does not require use of the scanport interface. See Section 7.1 regarding
scan port bond out.
RESET
V
SS
1 kΩ
1 µF
(20%)
To Pin 2 of optional (scan port) connector
IN914
To Pin 1 of Optional (Scanport)
Connector
‡
5 V
IN914
Reset
Switch
†
Note:
This simple circuit may not be suitable for all applications. For example, if the
power supply has an unpredictable rise time or has intermittent voltage sags,
the device may not initialize properly.
1-8
MSP50C601, MSP50C604, and MSP50C605
1.5 MSP50C601, MSP50C604, and MSP50C605
Related products, the MSP50C601, MSP50C604, and MSP50C605 use the
MSP50C6xx core. The MSP50C601 has a 128K byte data ROM built into the
chip and 32 I/O port pins. The MSP50C605 has a 224K byte data ROM built
into the chip and 32 I/O port pins. The MSP50C604 has a 64K byte data ROM
built into the chip and 16 I/O port pins. The MSP50C601 can provide up to 24
minutes, the MSP50C605 can provide up to 37 minutes, and the MSP50C604
can provide up to 6.5 minutes of uninterrupted speech. The MSP50C604 is designed to support slave operation with an external host microcontroller. In this
mode the MSP50C604 can be programmed with a code that communicates
with the host via a command set. This command set can be designed to support LPC, CELP , MELP, and ADPCM coders by selecting the appropriate command. The MSP50C604 can also be used stand-alone in master mode. The
MSP50C601, MSP50C604, and MSP50C605 use the MSP50P614 as the development version device.
1-9Introduction to the MSP50C6xx
1-10
Chapter 2
MSP50C6xx Architecture
A detailed description of the MSP50C6xx architecture is included in this chapter. After reading this chapter , the reader will have in-depth knowledge of internal blocks, memory organization, interrupt system, timers, clock control mechanism, and various low power modes.
Topic Page
2.1 Architecture Overview 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Computation Unit 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Data Memory Address Unit 2–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Program Counter Unit 2–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 Bit Logic Unit 2–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6 Memory Organization: RAM and ROM 2–15. . . . . . . . . . . . . . . . . . . . . . . .
2.7 Interrupt Logic 2–22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8 Clock Control 2–26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.9 Timer Registers 2–31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.10 Reduced Power Modes 2–33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.11 Execution Timing 2–40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-1
2.1 Architecture Overview
The core processor in the C6xx is a medium performance mixed signal processor with enhanced microcontroller features and a limited DSP instruction set.
In addition to its basic multiply/accumulate structure for DSP routines, the core
provides for a very efficient handling of string and bit manipulation. A unique
accumulator-register file provides additional scratch pad memory and minimizes memory thrashing for many operations. Five different addressing
modes and many short direct references provide enhanced execution and
code efficiency.
The basic elements of the C6xx core are shown in Figure 2–1. In addition to
the main computational units, the core’s auxiliary functions include two timers,
an eight-level interrupt processor, a clock generation circuit, a serial scan-port
interface, and a general control register.
2-2
Figure 2–1. MSP50C6xx Core Processor Block Diagram
Interrupt Inputs
Interrupt Flag Register (IFR)†
Multiplier (MR)† Shift Value (SV)†
17 x 17 Multiplier
Product High (PH)†
MUX
16 bit ALU
32 Accumulators (AC0–AC31)†
Control Register (CTRL)†
Interrupt Processor
Serial Interface Register†
Oscillator Register†
Timer Period (PRD1 and PRD2)†
Timer Register (TIM1 and TIM2)†
AP0–AP3†
Accumulator Pointer
Peripheral
Interface
Serial
Interface
VCO
Frequency
Divider
Instruction
Decoder
+1
Column Exchange
Stack (R7)
Page (R6)
Index (R5)
Loop (R4)
R3
R2
R1
R0
MUX
Arithmetic Unit
MUX
Data Memory
640 x 17 bit
†
Indicates internal programmable registers.
Incrementor
Top Of Stack (TOS)†
Program Counter (PC)†
Protection Register (PR)†
Data Pointer (DP)†
MUX
String Register†
MUX
Repeat Counter†
Status Register (STAT)†
Flag Register†
Test Code
2k x 17 bit
Program Memory
30k x 17 bit
Macro Calls
Vectors
2-3MSP50C6xx Architecture
Figure 2–2. Computational Unit Block Diagram
16
16
16
16
16
16
5
Internal Databus – 16 bit
Shift Value (SV)
Multiplier Register (MR)
17 bit x 17 bit
Multiplexer
Product High (PH)
Accumulators
AP0
AP1
AP2
AP3
16
16
(Product Low, PL)
16 LSB
16 MSB
16
0
0
16
AB
ALU
16
Read/Write
AC0
AC1
AC2
AC3
AC4
5
AC5
AC6
AC7
AC8
AC9
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC25
AC26
AC27
AC28
AC29
AC30
AC31
16
16
2-4
2.2 Computation Unit
The computational unit (CU) is comprised of a (17-bit by 17-bit) Booth’s
algorithm multiplier and a 16-bit arithmetic logic unit (ALU). The block diagram
of the CU is shown in Figure 2–2. The multiplier block is served by 4 system
registers: a 16-bit multiplier register (MR), a 16-bit write-only multiplicand
register, a 16-bit high word product register (PH), and a 4-bit shift value register
(SV). The output of the ALU is stored in one 16-bit accumulator from among
the 32 which compose the accumulator-register block. The accumulator
register block can supply either one operand to the ALU (addressed
accumulator register or its offset register) or two operands to the ALU (both the
addressed register and its offset).
2.2.1 Multiplier
The multiplier executes a 17-bit by 17-bit 2s complement multiply and
multiply-accumulate in a single instruction cycle. The sign bit within each
operand is bit 16, and its value extends from bit 0 (LSB) to bit 15 (MSB). The
sign bit for either operand (multiplier or multiplicand) can assume a positive
value (zero) or a value equal to the MSB (bit 15). In assuming zero, the extra
bit supports unsigned multiplication. In assuming the value of bit 15, the extra
bit supports signed multiplication. Table 2–1 shows the greater magnitude
achievable when using unsigned multiplication (65535 as opposed to 32767).
Computation Unit
Table 2–1. Signed and Unsigned Integer Representation
Unsigned Signed
Decimal Hex Decimal Hex
65535 0xFFFF −1 0xFFFF
32768 0x8000 −32768
32767 0x7FFF 32767
0
During multiplication, the lower word (LSB) of the resulting product, product
low, is multiplexed to the ALU. Product low is either loaded to or arithmetically
combined with an accumulator register. These steps are performed within the
same instruction cycle. Refer to Figure 2–3 for an overview of this operation.
At the end of the current execution cycle, the upper word (MSB) of the product
is latched into the product high register (PH).
0x0000 0 0x0000
0x8000
0x7FFF
2-5MSP50C6xx Architecture
Computation Unit
The multiplicand source can be either data memory, an accumulator, or an
accumulator offset. The multiplier source can be either the 16-bit multiplier
register (MR) or the 4-bit shift value (SV) register. For all multiply operations,
the MR register stores the multiplier operand. For barrel shift instructions, the
multiplier operand is a 4-to-16-bit value that is decoded from the 4-bit shift
value register (SV).
As an example of a barrel shift operation, a coded value of 0x7 in the SV
register results in a multiplier operand of 0000000010000000 (1 at bit 7). This
causes a left-shift 7-times on the 16 bit multiplicand. The output result is 32-bit.
On the other hand, if the status bit FM (multiplier shift mode) is SET, then the
multiplier operand (0000000010000000) is left-shifted once to form a 17
significant-bit operand (00000000100000000). This mode is included to avoid
a divide-by-2 of the product, when interpreting the input operands as signed
binary fractions. The multiplier shift mode status bit is located in the status
register (STAT).
All three multiplier registers (PH, SV, and MR) can be loaded from data
memory and stored to data memory . In addition, data can be transferred from
an accumulator register to the PH, or vice versa. Both long and short constants
can be directly loaded to the MR from program memory.
The multiplicand is latched in a write-only register from the internal data bus.
The value is not accessible by memory or other system registers.
2-6
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