The LM3489 is a high efficiency PFET switching
regulator controller that can be used to quickly and
easily develop a small, cost effective, switching buck
regulator for a wide range of applications. The
hysteretic control architecture provides for simple
design without any control loop stability concerns
using a wide variety of external components. The
PFET architecture also allows for low component
count as well as ultra-low dropout, 100% duty cycle
operation. Another benefit is high efficiency operation
at light loads without an increase in output ripple. A
dedicated Enable Pin provides a shutdown mode
drawingonly7µA.LeavingtheEnablePin
unconnected defaults to on.
Current limit protection can be implemented by
measuring the voltage across the PFET’s R
thus eliminating the need for a sense resistor. A
sense resistor may be used to improve current limit
accuracy if desired. The cycle-by-cycle current limit
can be adjusted with a single resistor, ensuring safe
operation over a range of output currents.
DS(ON)
,
TYPICAL APPLICATION CIRCUIT
1
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PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Figure 1. Top View
8-Lead Plastic VSSOP-8
Package Number (DGK)
PIN DESCRIPTIONS
PinNameDescription
No.
1ISENSEThe current sense input pin. This pin should be connected to the PFET drain terminal directly or through a series
resistor up to 600 ohm for 28V>Vin>35V.
2GNDSignal ground.
3ENEnable pin. Connect EN pin to ground to shutdown the part or float to enable operation (Internally pulled high).
This pin can also be used to perform UVLO function.
4FBThe feedback input. Connect the FB to a resistor voltage divider between the output and GND for an adjustable
output voltage.
5ADJCurrent limit threshold adjustment. Connected to an internal 5.5µA current source. A resistor is connected
between this pin and VIN. The voltage across this resistor is compared with the ISENSE pin voltage to determine
if an over-current condition has occurred.
6PGNDPower ground.
7PGATEGate Drive output for the external PFET. PGATE swings between VIN and VIN-5V.
8VINPower supply input pin.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
(1)
VIN Voltage−0.3V to 36V
PGATE Voltage−0.3V to 36V
FB Voltage−0.3V to 5V
ISENSE Voltage
−1.0V to 36V
-1V (<100ns)
ADJ Voltage−0.3V to 36V
EN Voltage
(2)
−0.3V to 6V
Maximum Junction Temperature150°C
Power Dissipation, TA= 25°C
ESD SusceptibilityHuman Body Model
(3)
(4)
417mW
2kV
Lead TemperatureVapor Phase (60 sec.)215°C
Infrared (15 sec.)220°C
Storage Temperature−65°C to 150°C
(1) Absolute maximum ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the
device is intended to be functional, but device parameter specifications may not be ensured. For specifications and test conditions, see
the Electrical Characteristics.
(2) This pin is internally pulled high and clamped at 8V typical. The absolute maximum and operating maximum rating specifies the input
level allowed for an external voltage source applied to this pin without triggering the internal clamp with margin.
(3) The maximum allowable power dissipation is a function of the maximum junction temperature, T
resistance, θJA= 240°C/W, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is
calculated using: P
(4) The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin. The machine model is a 200pF
D_MAX
= (T
- TA)/θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature.
J_MAX
, the junction-to-ambient thermal
J_MAX
capacitor discharged directly into each pin. MIL-STD-883 3015.7
Operating Ratings
(1)
Supply Voltage Range (VIN)4.5V to 35V
EN Voltage (maximum)
(2)
5.5V
Operating Junction Temperature (TJ)−40°C to +125°C
(1) Absolute maximum ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the
device is intended to be functional, but device parameter specifications may not be ensured. For specifications and test conditions, see
the Electrical Characteristics.
(2) This pin is internally pulled high and clamped at 8V typical. The absolute maximum and operating maximum rating specifies the input
level allowed for an external voltage source applied to this pin without triggering the internal clamp with margin.
Specifications in Standard type face are for TJ= 25°C, and in bold type face apply over the full Operating Temperature
Range (TJ= −40°C to +125°C). Unless otherwise specified, VIN= 12V, V
= VIN− 1V, and V
ISNS
= VIN− 1.1V. Datasheet
ADJ
min/max specification limits are specified by design, test, or statistical analysis.
Current limit comparator offsetVFB= 1.0V-200+20mV
Current limit ADJ current sourceVFB= 1.5V3.05.57.0µA
Current limit one shot off timeV
= 11.5V6914µs
ADJ
V
= 11.0V
ISNS
VFB= 1.0V
Driver resistanceSource5.5Ω
I
SOURCE
= 100mA
Sink8.5
I
= 100mA
SINK
Driver Output currentSource0.44A
VIN= 7V, PGATE = 3.5V
Sink0.1
VIN = 7V, PGATE = 3.5V
FB pin Bias CurrentVFB= 1.0V300750nA
Minimum on time in normalV
operationC
Minimum on time in current limitV
Feedback Voltage Line Regulation4.5 ≤ VIN≤ 35V0.01%/V
IN
= V
ISNS
ADJ
on OUT = 1000pF
load
= V
ISNS
VFB= 1.0V
C
ADJ
on OUT = 1000pF
load
+ 0.1V100ns
(5)
- 0.1V200ns
(5)
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(1) All limits are specified at room temperature (standard type face) and at temperature extremes (bold type face). All room temperature
limits are 100% tested. All limits at temperature extremes are specified via correlation using standard Statistical Quality Control (SQC)
methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).
(2) Typical numbers are at 25°C and represent the most likely norm.
(3) The VFBis the trip voltage at the FB pin when PGATE switches from high to low.
(4) Bias current flows out from the FB pin.
(5) A 1000pF capacitor is connected between VINand PGATE.