INPUT VOLTAGE (V)
EFFICIENCY (%)
100
95
90
85
80
75
40 45 50 55 60 65 70 75
1 Introduction
This evaluation board showcases the LM3409HV PFET controller for a buck current regulator. It is
designed to drive 12 LEDs (VO= 42V) at a maximum average LED current (I
voltage (V = 48V). The switching frequency (fSW= 400 kHz) is targeted for the nominal operating point,
however f
However, if the input voltage drops below the regulated LED string voltage, the converter goes into
dropout and VO= VINideally.
The PCB is made using 4 layers of 2 oz. copper with FR4 dieletric. The evaluation board showcases all
features of the LM3409HV including analog dimming using the IADJ pin and internal PWM dimming using
the EN pin. High frequency external parallel FET shunt PWM dimming can also be evaluated. The board
has a header (J1) with a removable jumper, which is used to select the PWM dimming method.
The evaluation board has a right angle connector (J2) which can mate with an external LED load board
allowing for the LEDs to be mounted close to the driver. This reduces potential ringing when there is no
output capacitor. Alternatively, the LED+ and LED- turrets can be used to connect the LED load.
This board can be easily modified to demonstrate other operating points as shown in Section 9. The
Design Procedure section of the LM3409/3409HV/3409Q/3409QHV PFET Buck Controller for High
Power LED Drivers (SNVS602) data sheet can be used to design for any set of specifications.
SWIN
User's Guide
SNVA390D–May 2009–Revised May 2013
AN-1953 LM3409HV Evaluation Board
= 1.5A) from a DC input
LED
varies across the entire operating range. The circuit can accept an input voltage of 6V-75V.
Figure 1. Efficiency with 12 Series LEDS AT 1.5A
Since the board contains a buck regulator designed for 48V input, the efficiency is very high at input
voltages near or less than 48V. The switching frequency increases as input voltage increases, yielding
lower efficiency at higher input voltages. Note that increasing the off-time resistor (R6) will increase the
efficiency at high input voltage.
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Copyright © 2009–2013, Texas Instruments Incorporated
IADJ
EN
CSN
LM3409HV
UVLO
V
IN
VCC
COFF
GND
CSP
C4
R6
PGATE
C7
R8
R7
DAP
VIN
LED+
R9
1
2
3
4
5 6
7
8
9
10
PWM2
C1
C2
5V
R4
C9
R3
R2
R1
D1
L1
Q3Q2
C3
C5
GND2
LED-
GND
VADJ
R10
C6
R11
C8
R5
D2
1
2
3
5
6
7
14
13
12
10
9
8
J2
J1
1
3
EN
Q1
U1
Schematic
2 Schematic
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3 Pin Descriptions
Pin(s) Name Description Application Information
1 UVLO Input under-voltage lockout Connect to a resistor divider from VINand GND. Turn-on threshold is
2 IADJ Analog LED current adjust Apply a voltage between 0 - 1.24V, connect a resistor to GND, or leave
3 EN Logic level enable / Apply a voltage >1.74V to enable device, a PWM signal to dim, or a
4 COFF Off-time programming Connect resistor to VO, and capacitor to GND to set the off-time.
5 GND Ground Connect to the system ground.
6 PGATE Gate drive Connect to the gate of the external PFET.
7 CSN Negative current sense Connect to the negative side of the sense resistor.
8 CSP Positive current sense Connect to the positive side of the sense resistor (VIN).
9 VCC VIN- referenced Connect at least a 1µF ceramic capacitor to VIN. The regulator provides
10 VIN Input voltage Connect to the input voltage.
DAP DAP Thermal pad on bottom of IC Connect to pin 5 (GND). Place 4-6 vias from DAP to bottom GND plane.
PWM dimming voltage <0.5V for low power shutdown.
linear regulator output power for the PFET drive.
1.24V and hysteresis for turn-off is provided by a 22µA current source.
open to set the current sense threshold voltage.
2
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4 Bill of Materials
Qty Part ID Part Value Manufacturer Part Number
1 U1 Buck controller TI LM3409HV
2 C1, C2 2.2µF X7R 10% 100V MURATA GRM43ER72A225KA01L
1 C3 0.1µF X7R 10% 100V MURATA GRM188R72A104KA35D
1 C4 1.0µF X7R 10% 16V TDK C1608X7R1C105K
1 C5 0.1µF X7R 10% 50V MURATA GRM319R71H104KA01D
1 C6 0.1µF X7R 10% 50V MURATA GCM188R71H104KA57D
1 C7 470pF X7R 10% 50V TDK C1608X7R1H471K
3 C8, D2, R11 No Load
1 C9 2200pF X7R 10% 50V MURATA GRM188R71H222KA01D
1 Q1 PMOS 100V 3.8A ZETEX ZXMP10A18KTC
1 Q2 CMOS 30V 2A FAIRCHILD FDC6333C
1 Q3 NMOS 100V 7.5A FAIRCHILD FDS3672
1 D1 Schottky 100V 3A VISHAY SS3H10-E3/57T
1 L1 33 µH 20% 3.2A TDK SLF12575T-330M3R2
2 R1, R2 1Ω 1% VISHAY CRCW06031R00FNEA
1 R3 10kΩ 1% VISHAY CRCW060310K0FKEA
1 R4 100Ω 1% VISHAY CRCW0603100RFKEA
1 R5 0Ω 1% VISHAY CRCW06030000Z0EA
1 R6 16.5kΩ 1% VISHAY CRCW060316K5FKEA
1 R7 6.98kΩ 1% VISHAY CRCW06036K98FKEA
1 R8 49.9kΩ 1% VISHAY CRCW060349K9FKEA
1 R9 0.15Ω 1% 1W VISHAY WSL2512R1500FEA
1 R10 1kΩ 1% VISHAY CRCW06031K00FKEA
1 J1 3 pin header MOLEX 22-28-4033
1 J2 2x7 pin RA shrouded SAMTEC TSSH-107-01-S-D-RA
2 VIN, GND banana jack KEYSTONE 575-8
7 EN, Vadj, +5V, GND2, PWM2, turret KEYSTONE 1502-2
LED+, LED-
Bill of Materials
Table 1. Bill of Materials
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Copyright © 2009–2013, Texas Instruments Incorporated
PCB Layout
5 PCB Layout
The two inner planes are GND and VIN.
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Figure 2. Top Layer
4
AN-1953 LM3409HV Evaluation Board SNVA390D–May 2009–Revised May 2013
Figure 3. Bottom Layer
Copyright © 2009–2013, Texas Instruments Incorporated
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=
pF470C7
:
=
k5.16R6
t
OFF
fSW= =
ns242
=
kHz404
1
-
¸
¹
·
¨
©
§
V4897.0 x
V42
¸
¸
¹
·
¨
¨
©
§
V
O
VINxK
1
-
1lnk5.16pF490t
OFF
-x:x
-
=
¨
¨
©
§
ns242
=
¸
¸
¹
·
V24.1
V42
(C7+20pF)t
OFF
-
=
x R6 x11ln -
¸
¸
¹
·
¨
¨
©
§
V
O
V24.
=
R6
--
1
¸
¸
¹
·
¨
¨
©
§
V
O
xK V
IN
=
R6
:=k7.
16
x lnpF490 xkHz400
¨
©
§
-
1
V42
¸
¹
·
V24.1
--
1
¨
©
§
¸
¹
·
V42
x V4897.0
-
xx 1lnf(C7 + 20 pF)
SW
¸
¸
¹
·
¨
¨
©
§
V
O
V24.1
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6 Design Procedure
6.1 Specifications
Design Procedure
VIN= 48V; V
IN-MAX
= 75V
VO= 42V
fSW= 400kHz
I
= 1.5A
LED
Δi
Δv
V
LED-PP
IN-PP
TURN-ON
= Δi
L-PP
= 1.44V
= 10V; V
= 300mA
= 1.1V
HYS
η = 0.97
6.2 Nominal Switching Frequency
Assume C7 = 470pF and η = 0.97. Solve for R6:
The closest 1% tolerance resistor is 16.5 kΩ therefore the actual t
and target fSWare:
OFF
(1)
The chosen components from step 1 are:
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(2)
(3)
(4)
5
Copyright © 2009–2013, Texas Instruments Incorporated
F2.2C2C1 P
==
F1.0
C3
P
=
I
RMSIN-
kHz404A5.1 xx
=
mA446
=
ns242s32.2 xP
tt
OFFON
xfII
SWLEDRMSIN
xx
=
-
1.75C
MININ
=
x
=
-
F07.4 PC
IN
C
MININ=-
= =
F32.2 P
V44.1
A5.1 x s23.2 P
v
PPIN'-
tI
ONLED
x
1
t
ON
=
1
t
OFF
=
- - ns242
=
s23.2 P
kHz404
f
SW
=
R9
:15.0
I
LED
=
2
308
-
A5.1
=
15.05 :x
V24.1
I
LED
=
R95x
-
2
i
PPL'-
V
ADJ
mA
=
R9
V
ADJ
x-I5
MAXL
= =
:15.0
V24.1
x5 A65.1
II
LEDMAXL
+
=
-
2
A1.5
+
=
A65.1
=
2
i
PPL'-
308mA
H33L1 P
=
= =
H33P
308
=
242nsV42 x
L1
tV
OFFO
x
i
PPL'-
mA
=
H9.33 P
=
L1
=
i
PPL'-
tV
OFFO
x
ns242V42 x
mA300
Design Procedure
6.3 Inductor Ripple Current
Solve for L1:
The closest standard inductor value is 33 µH therefore the actual Δi
The chosen component from step 2 is:
6.4 Average LED Current
L-PP
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(5)
is:
(6)
(7)
DetermineI
Assume V
:
L-MAX
= 1.24V and solve for R9:
ADJ
The closest 1% tolerance resistor is 0.15 Ω therefore the I
The chosen component from step 3 is:
6.5 Output Capacitance
No output capacitance is necessary.
6.6 Input Capacitance
Determine tON:
Solve for C
IN-MIN
:
LED
(8)
(9)
is:
(10)
(11)
(12)
Choose CIN:
DetermineI
IN-RMS
:
The chosen components from step 5 are:
6
AN-1953 LM3409HV Evaluation Board SNVA390D–May 2009–Revised May 2013
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(13)
(14)
(15)
(16)
(17)
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=
V1.10
k98.6 :
( )k9.49k98.6V24.1 :+:x
V
ONTURN=-
V
ONTURN=-
V24.1 ( )R8R7+x
R7
=
:
=
k06.7
:
x
k9.49V24.1
- V24.1V10
=
R7
x
R8V24.1
--V24.1V
ONTURN
1k9.49A22R8V
HYS
x:
=
Px
=
V1.A22
=
P
==
V
R8
HYS
=
:k50
PA22PA22
V1.1
SMC,V100,A3D1o
mA147V
D
x=x mV750 = mW110IPDD=
( )
1ID1I
LEDD
-
=
x-
=
¨
¨
©
§
I
LED
x
¸
¸
¹
·
VINKx
V
O
mA147A5.1=x
¸
¸
¹
·
V42
1ID-
=
¨
¨
©
§
97.0V48 x
VV
MAXINMAXD
==
--
V75
Q1o 3.8 DPAK,V100,A
mW387m190A43.1RIP
2
DSON
2
RMSTT
=:
x
=
x
=
-
11.5A x
+
xx
=
¨
¨
©
§
V42
12
1
97.0V48 x
I
RMST-
2
¸
¸
¹
·
¸
¸
¹
·
¨
¨
©
§
308mA
1.5A
1.43A
=
I
RMST-
I
LED
x
=
1D
2
x
+
x
¸
¸
¸
¹
·
¸
¸
¹
·
¨
¨
©
§
¨
¨
¨
©
§
12
1
i
L-PP
'
I
LED
I
RMST-
=
A35.1
=
A5.1V42 x
97.0V48 x
IDI
LEDT
=
x
=
VINKx
IV
LEDO
x
V75VV
MAXINMAXT
==
--
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6.7 P-Channel MOSFET
Determine minimum Q1 voltage rating and current rating:
A 100V 3.8A PFET is chosen with R
The chosen component from step 6 is:
6.8 Recirculating Diode
Determine minimum D1 voltage rating and current rating:
= 190mΩ and Qg= 20nC. Determine I
DS-ON
T-RMS
Design Procedure
(18)
(19)
and PT:
(20)
(21)
(22)
A 100V 3A diode is chosen with VD= 750mV. Determine PD:
The chosen component from step 7 is:
6.9 Input Under-Voltage Lockout (UVLO)
Solve for R8:
The closest 1% tolerance resistor is 49.9 kΩ so V
Solve for R7:
The closest 1% tolerance resistor is 6.98 kΩ so V
is:
HYS
TURN-ON
(23)
(24)
(25)
(26)
(27)
(28)
(29)
is:
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(30)
7
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9R
2
I
LED
x
+
¸
¹
·
¨
©
§
Âi
L-PP
A1 é
=
A1 é
I
LED
+
¨
©
§
150 m:
2
308 mA
x
¸
¹
·
R
EXT
=
R10
!
796:
1
==
F0.12 kHz2S xx é
1
6Cf2SCxx
:
=
:
=
k9.49R8
k98.6R7
Design Procedure
The chosen components from step 8 are:
6.10 IADJ Connection Method
The IADJ pin controls the high-side current sense threshold in three ways outlined in the datasheet. The
LM3409HV evaluation board allows for all three methods to be evaluated using C6, R10, and the VADJ
terminal.
Method #1: If the VADJ terminal is not connected to the power supply, then the internal Zener diode
biases the pin to 1.24V and the current sense threshold is nominally 248mV.
Method #2: Applying an external voltage to the VADJ terminal between 0 and 1.24V linearly scales the
current sense threshold between 0 and 248mV nominally. It can be necessary to have an RC filter when
using an external power supply in order to remove any high frequency noise or oscillations created by the
power supply and the connecting cables. The filter is chosen by assuming a standard value of C6 = 0.1µF
and solving for a cut-off frequency fC< 2kHz:
Since an exact fCis not critical, a standard value of 1kΩ is used. Section 8 shows a typical LED current
waveform when analog dimming using an external voltage source.
Method #3: (This method requires modification of the received evaluation board). The internal 5µA current
source can be used to bias the voltage across an external resistor to ground (R
evaluation board. The resistor is sized knowing the desired average LED current I
which is default using method #1):
) across C6 on the
EXT
(must be < 1.5A
LED
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(31)
(32)
(33)
8
AN-1953 LM3409HV Evaluation Board SNVA390D–May 2009–Revised May 2013
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NMOS8,SOIC100V,7.5A,Q3
CMOS6,SOT30V, 20A,Q2
100:R4
R3
1:R2R1
2.2 nFC9
F0.1C6
-o
-o
=
=
==
=
= #
10 k:
==
t
R4
C
=
:100
nF2.2
ns220
C9
1
2
3
1
2
1: No PWM, EN = V
IN
2: External PWM, EN coupled
3: Internal PWM, using EN
3
J1
:
=
P
=
k1R10
F1.0C6
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The chosen components from step 9 are:
6.11 PWM Dimming Method
The LM3409HV evaluation board allows for PWM dimming to be evaluated as follows:
Method #1: If no PWM dimming is desired, a jumper should be placed in position 1 (shorts pins 1 and 2)
on header J1. This shorts VIN and EN which ensures the controller is always enabled if an input voltage
greater than 1.74V is applied.
Method #2: External parallel FET shunt dimming can be evaluated by placing the jumper in position 2
(shorts pins 2 and 3) on header J1. This connects the capacitive coupling circuit to the EN pin as
suggested in the datasheet. The resistor (R4) can be solved for assuming a standard capacitor value C9 =
2.2nF and a desired time constant (tC= 220ns < t
) as follows:
OFF
Design Procedure
(34)
(35)
The external shunt FET dimming circuit shown below is designed using an N-channel MosFET (Q3), a
CMOS FET (Q2), two gate current limiting resistors (R1 and R2), a pull-up resistor (R3), and a bypass
capacitor (C5). With an external 5V power supply attached to the 5V terminal and an external PWM signal
attached to the PWM2 terminal, the shunt dimming circuit is complete. Q3 is the shunt dimFET which
conducts the LED current when turned on and blocks the LED voltage when turned off. Q3 needs to be
fast and rated for VOand I
. For design flexibility, a fast 100V, 7.5A NFET is chosen. Q2 is necessary to
LED
invert the PWM signal so it properly translates the duty cycle to the shunt dimming FET. Q2 also needs to
be fast and rated for 5V and fairly small current, therefore a 30V, 2A fast CMOS FET was chosen. R1 and
R2 are 1Ω resistors to slow down the rising edge of the FETs slightly to prevent the gate from ringing. R3
is a 10kΩ pull-up resistor to ensure the CMOS gate is pulled all the way to 5V if a sub-5V PWM signal is
applied to PWM2. The bypass capacitor (C5) for the 5V power supply is chosen to be 0.1µF. See
Section 7 for an improvement that can be made to this circuit.
Method #3: Internal PWM dimming using the EN pin can be evaluated by removing the jumper from
header J1. An external PWM signal can then be applied to the EN terminal to provide PWM dimming.
Section 8 shows typical LED current waveforms during both types of PWM dimming.
The chosen components from step 10 are:
6.12 Bypass Capacitor
The internal regulator requires at least 1µF of ceramic capacitance with a voltage rating of 16V.
The chosen component from step 11 is:
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(36)
9
R
L
OFF2
<
I
V
LED
O
x
0.1
x
C7x
LED+
5V
R4
C9
R3
R2
R1
Q3Q2
C5
GND2
LED-
EN
LM3409/09HV
I
LED
P
=
F0.1C4
Shunt FET Circuit Modification
Figure 4. External shunt FET dimming circuit with EN pin coupling
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(37)
7 Shunt FET Circuit Modification
When the shunt FET (Q3) is on, the LM3409 is driving current into a short, therefore a maximum off-time
(typical 300 µs) occurs followed by a minimum on-time. Maximum off-time followed by minimum on-time
continues until Q3 is turned off. At low dimming frequencies and depending on the duty cycle, the inductor
current may be at a very low level when the Q3 turns off. This will eliminate the benefits of using the shunt
FET over the EN pin because the inductor will have to slew the current back to the nominal value
anyways.
A simple modification to the external parallel FET dimming circuit will keep the inductor current close to its
nominal value when Q3 is turned off. This modification will ensure that the rise time of the LED current is
only limited by the turn-off time of the shunt FET as desired. The following circuit additions allow for two
different off-times to occur. When Q3 is off, the standard off-timer referenced from VOis set. However
when the Q3 is on, a second off-timer referenced to the gate signal of the Q3 is enabled and a controlled
(non-maximum) off-time is set.
This modification includes 2 extra diodes (i.e. BAT54H) and one resistor (R
shunt FET PWM dimming below 10 kHz or so. In general, this second off-timer should be set to allow the
inductor current to fall no more than 10% of its nominal value. A simple approximation can be used to find
R
:
OFF2
) and is only relevant when
OFF2
(38)
10
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IADJ
EN
CSN
LM3409HV
UVLO
V
IN
VCC
COFF
GND
CSP
C4
R6
PGATE
C7
R8
R7
DAP
VIN
LED+
R9
1
2
3
4
5 6
7
8
9
10
PWM2
C1
C2
5V
R4
C9
R3
R2
R1
D1
L1
Q3Q2
C3
C5
GND2
LED-
GND
VADJ
R10
C6
R11
C8
R5
D2
1
2
3
5
6
7
14
13
12
10
9
8
J2
J1
1
3
EN
Q1
U1
Two Off-timers
for
Shunt FET dimming
R
OFF2
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Shunt FET Circuit Modification
Figure 5. Multiple off-timers for shunt FET dimming circuit
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11
I
LED
(A)
V
PWM2
(V)
14
12
10
8
6
4
2
0
-2
2.0
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
I
LED
2 és/DIV
V
PWM2
I
LED
(A)
V
PWM2
(V)
7
6
5
4
3
2
1
0
-1
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0.0
-0.4
I
LED
200 ns/DIV
V
PWM2
I
LED
(A)
V
EN
(V)
14
12
10
8
6
4
2
0
-2
2.0
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
I
LED
10 és/DIV
V
EN
I
LED
(A)
V
EN
(V)
7
6
5
4
3
2
1
0
-1
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0.0
-0.4
I
LED
2 és/DIV
3.5 és
V
EN
Typical Waveforms
8 Typical Waveforms
TA= +25°C, VIN= 48V and VO= 42V.
Figure 6. 20kHz 50% EN pin PWM dimming Figure 7. 20kHz 50% EN pin PWM dimming (rising
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edge)
Figure 8. 100kHz 50% External FET PWM dimming Figure 9. 100kHz 50% External FET PWM dimming
12
AN-1953 LM3409HV Evaluation Board SNVA390D–May 2009–Revised May 2013
Copyright © 2009–2013, Texas Instruments Incorporated
(rising edge)
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I
LED
(A)
V
SW
(V)
140
120
100
80
60
40
20
0
-20
I
LED
200 ns/DIV
0.0
V
SW
0.1
0.2
I
LED
(A)
V
SW
(V)
140
120
100
80
60
40
20
0
-20
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
I
LED
400 ns/DIV
V
SW
www.ti.com
Alternate Designs
Figure 10. Analog dimming minimum (V
9 Alternate Designs
Alternate designs with the LM3409HV evaluation board are possible with very few changes to the existing
hardware. The evaluation board FETs and diodes are already rated higher than necessary for design
flexibility. The input UVLO can remain the same and the input capacitance is sufficient for most designs,
though the input voltage ripple will change. Other designs can evaluated by changing R6, R9, L1, and C8.
The table below gives the main specifications for five different designs and the corresponding values for
R6, R9, L1 and C8. The RMS current rating of L1 should be at least 50% higher than the specified I
Designs 3 and 5 are optimized for best analog dimming range, while designs 1, 2, and 4 are optimized for
best PWM dimming range. These are just examples, however any combination of specifications can be
achieved by following the Design Procedure in the LM3409/3409HV/3409Q/3409QHV PFET Buck
Controller for High Power LED Drivers (SNVS602 data sheet.
Specification / Design 1 Design 2 Design 3 Design 4 Design 5
Component
Dimming Method PWM PWM Analog PWM Analog
V
IN
V
O
f
SW
I
LED
Δi
LED
R6 15.4 kΩ 25.5 kΩ 46.4 kΩ 24.9 kΩ 95.3 kΩ
R9 0.2Ω 0.3Ω 0.12Ω 0.07Ω 0.15Ω
L1 22 µH 68 µH 150 µH 15 µH 330 µH
C8 None None 2.2 µF None 2.2 µF
24V 36V 48V 65V 75V
14V 24V 35V 56V 42V
500 kHz 450 kHz 300 kHz 350 kHz 300 kHz
1A 700 mA 2A 3A 1.5A
450 mA 250 mA 70 mA 1A 80 mA
= 0V) Figure 11. Analog dimming maximum (V
ADJ
Table 2. Alternate Designs
ADJ
open)
LED
.
SNVA390D–May 2009–Revised May 2013 AN-1953 LM3409HV Evaluation Board
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