INPUT VOLTAGE (V)
EFFICIENCY (%)
100
95
90
85
80
75
40 45 50 55 60 65 70 75
1 Introduction
This evaluation board showcases the LM3409HV PFET controller for a buck current regulator. It is
designed to drive 12 LEDs (VO= 42V) at a maximum average LED current (I
voltage (V = 48V). The switching frequency (fSW= 400 kHz) is targeted for the nominal operating point,
however f
However, if the input voltage drops below the regulated LED string voltage, the converter goes into
dropout and VO= VINideally.
The PCB is made using 4 layers of 2 oz. copper with FR4 dieletric. The evaluation board showcases all
features of the LM3409HV including analog dimming using the IADJ pin and internal PWM dimming using
the EN pin. High frequency external parallel FET shunt PWM dimming can also be evaluated. The board
has a header (J1) with a removable jumper, which is used to select the PWM dimming method.
The evaluation board has a right angle connector (J2) which can mate with an external LED load board
allowing for the LEDs to be mounted close to the driver. This reduces potential ringing when there is no
output capacitor. Alternatively, the LED+ and LED- turrets can be used to connect the LED load.
This board can be easily modified to demonstrate other operating points as shown in Section 9. The
Design Procedure section of the LM3409/3409HV/3409Q/3409QHV PFET Buck Controller for High
Power LED Drivers (SNVS602) data sheet can be used to design for any set of specifications.
SWIN
User's Guide
SNVA390D–May 2009–Revised May 2013
AN-1953 LM3409HV Evaluation Board
= 1.5A) from a DC input
LED
varies across the entire operating range. The circuit can accept an input voltage of 6V-75V.
Figure 1. Efficiency with 12 Series LEDS AT 1.5A
Since the board contains a buck regulator designed for 48V input, the efficiency is very high at input
voltages near or less than 48V. The switching frequency increases as input voltage increases, yielding
lower efficiency at higher input voltages. Note that increasing the off-time resistor (R6) will increase the
efficiency at high input voltage.
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IADJ
EN
CSN
LM3409HV
UVLO
V
IN
VCC
COFF
GND
CSP
C4
R6
PGATE
C7
R8
R7
DAP
VIN
LED+
R9
1
2
3
4
5 6
7
8
9
10
PWM2
C1
C2
5V
R4
C9
R3
R2
R1
D1
L1
Q3Q2
C3
C5
GND2
LED-
GND
VADJ
R10
C6
R11
C8
R5
D2
1
2
3
5
6
7
14
13
12
10
9
8
J2
J1
1
3
EN
Q1
U1
Schematic
2 Schematic
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3 Pin Descriptions
Pin(s) Name Description Application Information
1 UVLO Input under-voltage lockout Connect to a resistor divider from VINand GND. Turn-on threshold is
2 IADJ Analog LED current adjust Apply a voltage between 0 - 1.24V, connect a resistor to GND, or leave
3 EN Logic level enable / Apply a voltage >1.74V to enable device, a PWM signal to dim, or a
4 COFF Off-time programming Connect resistor to VO, and capacitor to GND to set the off-time.
5 GND Ground Connect to the system ground.
6 PGATE Gate drive Connect to the gate of the external PFET.
7 CSN Negative current sense Connect to the negative side of the sense resistor.
8 CSP Positive current sense Connect to the positive side of the sense resistor (VIN).
9 VCC VIN- referenced Connect at least a 1µF ceramic capacitor to VIN. The regulator provides
10 VIN Input voltage Connect to the input voltage.
DAP DAP Thermal pad on bottom of IC Connect to pin 5 (GND). Place 4-6 vias from DAP to bottom GND plane.
PWM dimming voltage <0.5V for low power shutdown.
linear regulator output power for the PFET drive.
1.24V and hysteresis for turn-off is provided by a 22µA current source.
open to set the current sense threshold voltage.
2
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4 Bill of Materials
Qty Part ID Part Value Manufacturer Part Number
1 U1 Buck controller TI LM3409HV
2 C1, C2 2.2µF X7R 10% 100V MURATA GRM43ER72A225KA01L
1 C3 0.1µF X7R 10% 100V MURATA GRM188R72A104KA35D
1 C4 1.0µF X7R 10% 16V TDK C1608X7R1C105K
1 C5 0.1µF X7R 10% 50V MURATA GRM319R71H104KA01D
1 C6 0.1µF X7R 10% 50V MURATA GCM188R71H104KA57D
1 C7 470pF X7R 10% 50V TDK C1608X7R1H471K
3 C8, D2, R11 No Load
1 C9 2200pF X7R 10% 50V MURATA GRM188R71H222KA01D
1 Q1 PMOS 100V 3.8A ZETEX ZXMP10A18KTC
1 Q2 CMOS 30V 2A FAIRCHILD FDC6333C
1 Q3 NMOS 100V 7.5A FAIRCHILD FDS3672
1 D1 Schottky 100V 3A VISHAY SS3H10-E3/57T
1 L1 33 µH 20% 3.2A TDK SLF12575T-330M3R2
2 R1, R2 1Ω 1% VISHAY CRCW06031R00FNEA
1 R3 10kΩ 1% VISHAY CRCW060310K0FKEA
1 R4 100Ω 1% VISHAY CRCW0603100RFKEA
1 R5 0Ω 1% VISHAY CRCW06030000Z0EA
1 R6 16.5kΩ 1% VISHAY CRCW060316K5FKEA
1 R7 6.98kΩ 1% VISHAY CRCW06036K98FKEA
1 R8 49.9kΩ 1% VISHAY CRCW060349K9FKEA
1 R9 0.15Ω 1% 1W VISHAY WSL2512R1500FEA
1 R10 1kΩ 1% VISHAY CRCW06031K00FKEA
1 J1 3 pin header MOLEX 22-28-4033
1 J2 2x7 pin RA shrouded SAMTEC TSSH-107-01-S-D-RA
2 VIN, GND banana jack KEYSTONE 575-8
7 EN, Vadj, +5V, GND2, PWM2, turret KEYSTONE 1502-2
LED+, LED-
Bill of Materials
Table 1. Bill of Materials
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PCB Layout
5 PCB Layout
The two inner planes are GND and VIN.
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Figure 2. Top Layer
4
AN-1953 LM3409HV Evaluation Board SNVA390D–May 2009–Revised May 2013
Figure 3. Bottom Layer
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=
pF470C7
:
=
k5.16R6
t
OFF
fSW= =
ns242
=
kHz404
1
-
¸
¹
·
¨
©
§
V4897.0 x
V42
¸
¸
¹
·
¨
¨
©
§
V
O
VINxK
1
-
1lnk5.16pF490t
OFF
-x:x
-
=
¨
¨
©
§
ns242
=
¸
¸
¹
·
V24.1
V42
(C7+20pF)t
OFF
-
=
x R6 x11ln -
¸
¸
¹
·
¨
¨
©
§
V
O
V24.
=
R6
--
1
¸
¸
¹
·
¨
¨
©
§
V
O
xK V
IN
=
R6
:=k7.
16
x lnpF490 xkHz400
¨
©
§
-
1
V42
¸
¹
·
V24.1
--
1
¨
©
§
¸
¹
·
V42
x V4897.0
-
xx 1lnf(C7 + 20 pF)
SW
¸
¸
¹
·
¨
¨
©
§
V
O
V24.1
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6 Design Procedure
6.1 Specifications
Design Procedure
VIN= 48V; V
IN-MAX
= 75V
VO= 42V
fSW= 400kHz
I
= 1.5A
LED
Δi
Δv
V
LED-PP
IN-PP
TURN-ON
= Δi
L-PP
= 1.44V
= 10V; V
= 300mA
= 1.1V
HYS
η = 0.97
6.2 Nominal Switching Frequency
Assume C7 = 470pF and η = 0.97. Solve for R6:
The closest 1% tolerance resistor is 16.5 kΩ therefore the actual t
and target fSWare:
OFF
(1)
The chosen components from step 1 are:
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(2)
(3)
(4)
5
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