Texas Instruments JM38510-33701BFA, JM38510-33701B2A, JM38510-33701BEA, SN54F138J, SN74F138D Datasheet
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SN54F138, SN74F138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SDFS051B – MARCH 1987 – REVISED JUL Y 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Designed Specifically for High-Speed
Memory Decoders and Data Transmission
Systems
D
Incorporates Three Enable Inputs to
Simplify Cascading and/or Data Reception
D
Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and Ceramic
300-mil DIPs
description
The ′F138 is designed to be used in
high-performance memory-decoding or datarouting applications requiring very short
propagation delay times. In high-performance
memory systems, these decoders can be used to
minimize the effects of system decoding. When
employed with high-speed memories utilizing a
fast enable circuit, the delay times of this decoder
and the enable time of the memory are usually
less than the typical access time of the memory.
This means that the effective system delay
introduced by the decoder is negligible.
The conditions at the binary-select inputs and the
three enable inputs select one of eight output
lines. Two active-low and one active-high enable
inputs reduce the need for external gates or
inverters when expanding. A 24-line decoder can
be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can
be used as a data input for demultiplexing applications.
The SN54F138 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74F138 is characterized for operation from 0°C to 70°C.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN54F138 ...J PACKAGE
SN74F138 ...D OR N PACKAGE
(TOP VIEW)
SN54F138 . . . FK PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
Y1
Y2
NC
Y3
Y4
C
G
2A
NC
G
2B
G1
BANC
Y6
Y5
V
Y0
Y7
GND
NC
CC
NC – No internal connection
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A
B
C
G
2A
G
2B
G1
Y7
GND
V
CC
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54F138, SN74F138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SDFS051B – MARCH 1987 – REVISED JUL Y 1996
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
ENABLE INPUTS
SELECT INPUTS OUTPUTS
G1 G2A G2B C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
X H X X X X H H H H H H H H
X XHXXXHHHHHHHH
LXXXXXHHHHHHHH
HLLLLLLHHHHHHH
HLLLLHHLHHHHHH
HLLLHLHHLHHHHH
HLLLHHHHHLHHHH
HLLHLLHHHHLHHH
HLLHLHHHHHHLHH
HLLHHLHHHHHHLH
HL LHHHHHHHHHHL
logic symbols (alternatives)
†
BIN/OCT
1
1
A
2
2
B
4
3
C
4
5
6
G1
Y0
15
0
&
EN
Y1
14
1
Y2
13
2
Y3
12
3
Y4
11
4
Y5
10
5
Y6
9
6
Y7
7
7
DMUX
0
1
A
2
B
2
3
C
4
5
6
G1
Y0
15
0
&
Y1
14
1
Y2
13
2
Y3
12
3
Y4
11
4
Y5
10
5
Y6
9
6
Y7
7
7
G
7
0
G
2A
G
2B
G
2A
G
2B
†
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
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