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EV2012
Datasheet
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Texas Instruments EV2012, BQ2012SN-D107TR, BQ2012SN-D107 Datasheet

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1
Features
➤
Conservative and repeatable measurement of available charge in rechargeable batteries
➤
Charge control output
➤
Designed for battery pack inte
gration
-
120µA typical standby current (self-discharge estimation mode)
-
Small size enables imple­mentations in as little as
1
2
square inch of PCB
➤ Integrate within a system or as a
stand-alone device
-
Display capacity via single­wire serial communication port or direct drive of LEDs
➤ Measurements compensated for
current and temperature
➤ Self-discharge compensation us-
ing internal temperature sensor
➤
16-pin narrow SOIC
General Description
The bq2012 Gas Gauge IC is in
Self-discharge of NiMH and NiCd batteries is estimated based on an internal timer and temperature sen
The bq2012 includes a charge con­trol output that, when used with other full-charge safety termination methods, can provide a cost-effective
means of controlling charge based on the battery's charge state.
Nominal available charge may be di
The bq2012 supports a simple single-line bidirectional serial link to an external processor (common ground). The bq2012 outputs battery information in response to external commands over the serial link.
Internal registers include available charge, temperature, capacity, battery ID, battery status, and programming pin settings. To support subassembly testing, the outputs may also be con­trolled. The external processor may also overwrite some of the bq2012 gas gauge data registers.
The bq2012 may operate directly from three or four cells. With the REF output and an external transis­tor, a simple, inexpensive regulator can be built to provide V
CC
across a
greater number of cells.
LCOM LED common output
SEG
1
/PROG1LED segment 1/
program 1 input
SEG
2
/PROG2LED segment 2/
program 2 input
SEG
3
/PROG3LED segment 3/
program 3 input
SEG
4
/PROG4LED segment 4/
program 4 input
SEG
5
/PROG5LED segment 5/
program 5 input
SEG
6
/PROG6LED segment 6/
program 6 input
1
PN201201.eps
16-Pin Narrow SOIC
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
LCOM
SEG1/PROG
1
SEG2/PROG
2
SEG3/PROG
3
SEG4/PROG
4
SEG5/PROG
5
SEG6/PROG
6
V
SS
V
CC
REF
CHG
DQ
EMPTY
SB
DISP
SR
REF Voltage reference output
CHG
Charge control output
DQ Serial communications
input/output
EMPTY Empty battery indicator
output
SB Battery sense input
DISP
Display control input
SR Sense resistor input
V
CC
3.0–6.5V
V
SS
System ground
Pin Connections Pin Names
bq2012
Gas Gauge IC With
Slow-Charge Control
9/96 B
Pin Descriptions
LCOM
LED common output
Open-drain output switches V
CC
to source
current for the LEDs. The switch is off dur
SEG
1
–
SEG
6
LED display segment outputs (dual func
1
–PROG6)
Each output may activate an LED to sink the current sourced from LCOM.
PROG
1
–
PROG
2
Programmed full count selection inputs (dual function with SEG
1
–SEG2)
These three-level input pins define the pro
PROG
3
–
PROG
4
Gas gauge rate selection inputs (dual function with SEG
3
–SEG4)
These three-level input pins define the scale factor described in Table 2.
PROG
5
Self-discharge rate selection (dual func­tion with SEG
5
)
This three-level input pin defines the selfdis­charge compensation rate shown in Table 1.
PROG
6
Display mode selection (dual function with SEG
6
)
This three-level pin defines the display op
CHG
Charge control output
This open-drain output becomes active low when charging is allowed. Valid charging conditions are described in the Charge Con
SR
Sense resistor input
The voltage drop (V
SR
) across the sense re
sistor R
S
is monitored and integrated over
time to interpret charge and discharge activ
SR<VSS
indicates dis
SR>VSS
indicates charge. The
effective voltage drop (V
SRO
) as seen by the
bq2012 is V
SR+VOS
(see Table 5).
DISP
Display control input
DISP
high disables the LED display. DISP tied to VCCallows PROGXto connect directly to V
CC
or VSSinstead of through a pull-up or
pull-down resistor. DISP
floating allows the LED display to be active during a valid charge or during discharge if the NAC regis
ter is updated at a rate equivalent to V
SRO
≤
-4mV. DISP
low activates the display. See
Table 1.
SB
Secondary battery input
This input monitors the single-cell voltage potential through a high-impedance resis­tive divider network for end-of-discharge voltage (EDV) thresholds, maximum charge voltage (MCV), and battery removed.
EMPTY
Battery empty output
This open-drain output becomes high­impedance on detection of a valid end-of­discharge voltage (V
EDVF
) and is low following
the next application of a valid charge.
DQ
Serial I/O pin
This is an open-drain bidirectional pin.
REF
Voltage reference output for regulator
REF provides a voltage reference output for an optional micro-regulator.
V
CC
Supply voltage input
V
SS
Ground
2
bq2012
Functional Description
General Operation
The bq2012 determines battery capacity by monitoring the amount of charge input to or removed from a re
Figure 1 shows a typical battery pack application of the bq2012 using the LED display capability as a charge­state indicator. The bq2012 can be configured to display capacity in either a relative or an absolute display mode. The relative display mode uses the last measured dis
charge capacity of the battery as the battery “full” refer
The bq2012 monitors the charge and discharge currents as a voltage across a sense resistor (see R
S
in Figure 1). A filter between the negative battery terminal and the SR pin may be required if the rate of change of the bat
tery current is too great.
3
bq2012
FG201201.eps
SEG6/PROG
6
SEG5/PROG
5
SEG4/PROG
4
SEG3/PROG
3
SEG2/PROG
2
SEG1/PROG
1
SR
DISP
SB
V
CC
REF
bq2012
Gas Gauge IC
LCOM
V
SS
EMPTY
DQ
V
CC
C1
0.1 F
Q1 ZVNL110A
R
1
R
S
RB
1
RB
2
Load
Charger
Indicates optional.
Directly connect to VCC across 3 or 4 cells (3 to 4.8V nominal,should not exceed 6.5V) with a resistor and a Zener diode to limit voltage during charge. Otherwise, R1, C1, and Q1 are needed for regulation of >4 cells. The value of R1 depends on the number of cells.
Programming resistors (6 max.) and ESD-protection diodes are not shown.
R-C on SR may be required (application-specific), where the R should not exceed 100k.
V
CC
CHG
1M
Figure 1. Battery Pack Application Diagram—LED Display
Voltage Thresholds
In conjunction with monitoring VSRfor charge/discharge currents, the bq2012 monitors the single-cell battery po
tential through the SB pin. The single-cell voltage po
RB RB
N
1
2
1=−
where N is the number of cells, RB
1
is connected to the
positive battery terminal, and RB
2
is connected to the
negative battery terminal. The single-cell battery volt
Two EDV thresholds for the bq2012 are fixed at:
EDV1 (early warning) = 1.05V
EDVF (empty) = 0.95V
If V
SB
is below either of the two EDV thresholds, the as­sociated flag is latched and remains latched, independ­ent of V
SB
, until the next valid charge.
During discharge and charge, the bq2012 monitors V
SR
for various thresholds. These thresholds are used to compensate the charge and discharge rates. Refer to the count compensation section for details. EDV monitoring is disabled if V
SR
≤
-250mV typical and resumes
1
2
sec-
ond after V
SR
> -250mV.
EMPTY Output
The EMPTY output switches to high impedance when V
SB<VEDF
and remains latched until a valid charge oc
curs. The bq2012 also monitors V
SB
relative to V
MCV
,
2.25V. V
SB
falling from above V
MCV
resets the device.
Reset
The bq2012 recognizes a valid battery whenever VSBis greater than 0.1V typical. V
SB
rising from below 0.25V or falling from above 2.25V resets the device. Reset can also be accomplished with a command over the serial port as described in the Register Reset section.
Temperature
The bq2012 internally determines the temperature in 10°C steps centered from -35°C to +85°C. The tempera
available over the serial port in 10°C increments as shown below:
Layout Considerations
The bq2012 measures the voltage differential between the SR and V
SS
pins. VOS(the offset voltage at the SR pin) is greatly affected by PC board layout. For optimal results, the PC board layout should follow the strict rule of a single-point ground return. Sharing high-current ground with small signal ground causes undesirable noise on the small signal nodes. Additionally:
■
The capacitors (SB and VCC) should be placed as close as possible to the SB and V
CC
pins, respectively,
and their paths to V
SS
should be as short as possible. A high-quality ceramic capacitor of 0.1µf is recommended for V
CC
.
■
The sense resistor (RS) should be as close as possible to the bq2012.
■
The R-C on the SR pin should be located as close as possible to the SR pin. The maximum R should not exceed 100K.
4
bq2012
TMPGG (hex) Temperature Range
0x < -30°C
1x -30°C to -20°C
2x -20°C to -10°C
3x -10°C to 0°C
4x 0°C to 10°C
5x 10°C to 20°C
6x 20°C to 30°C
7x 30°C to 40°C
8x 40°C to 50°C
9x 50°C to 60°C
Ax 60°C to 70°C
Bx 70°C to 80°C
Cx > 80°C
Gas Gauge Operation
The operational overview diagram in Figure 2 illustrates the operation of the bq2012. The bq2012 accumulates a measure of charge and discharge currents, as well as an estimation of self-discharge. Charge and discharge cur
The main counter, Nominal Available Charge (NAC), represents the available battery capacity at any given time. Battery charging increments the NAC register, while battery discharging and self-discharge decrement the NAC register and increment the DCR (Discharge Count Register).
The Discharge Count Register (DCR) is used to update the Last Measured Discharge (LMD) register only if a complete battery discharge from full to empty occurs without any partial battery charges. Therefore, the bq2012 adapts its capacity determination based on the actual conditions of discharge.
The battery’s initial capacity is equal to the programmed full count (PFC) shown in Table 2. Until LMD is up­dated, NAC counts up to but not beyond this threshold during subsequent charges. This approach allows the gas gauge to be charger-independent and compatible with any type of charge regime.
1. Last Measured Discharge (LMD) or learned battery capacity:
LMD is the last measured discharge capacity of the battery. On initialization (application of V
CC
or bat
2. Programmed Full Count (PFC) or initial bat
The initial LMD and gas gauge rate values are pro
1
–PROG4. The PFC also
provides the 100% reference for the absolute dis
Battery capacity (mAh)*sense resistor (Ω) =
PFC (mVh)
Selecting a PFC slightly less than the rated capac­ity for absolute mode provides capacity above the full reference for much of the battery’s life.
5
bq2012
FG201002.eps
Rate and
Temperature
Compensation
Temperature
Compensation
Charge Current
Discharge
Current
Self-Discharge
Timer
Temperature
Translation
Nominal
Available
Charge
(NAC)
Last
Measured
Discharged
(LMD)
Discharge
Count
Register
(DCR)
<
Qualified Transfer
+
Rate and
Temperature
Compensation
Rate and
Temperature
Compensation
Temperature Step, Other Data
+
--
+
Inputs
Main Counters
and Capacity
Reference (LMD)
Outputs
Serial
Port
Chip-Controlled
Available Charge
LED Display
Figure 2. Operational Overview
Example: Selecting a PFC Value
Given:
Sense resistor = 0.1
Ω
Number of cells = 6 Capacity = 2200mAh, NiCd battery Current range = 50mA to 2A Absolute display mode Serial port only Self-discharge =
C
64
Voltage drop over sense resistor = 5mV to 200mV
Therefore:
2200mAh*0.1Ω= 220mVh
Select:
PFC = 33792 counts or 211mVh PROG
1
= float
PROG
2
= float
PROG
3
= float
PROG
4
= low
PROG
5
= float
PROG
6
= float
The initial full battery capacity is 211mVh (2110mAh) until the bq2012 “learns” a new capac
6
bq2012
PROG
x
Programmed
Full
Count
(PFC)
PROG
4
= L PROG4= Z
Units
1 2 PROG
3
= H PROG3= Z PROG3= L PROG3= H PROG3= Z PROG3= L
-- -
Scale =
1/80
Scale =
1/160
Scale =
1/320
Scale =
1/640
Scale =
1/1280
Scale =
1/2560
mVh/ count
H H 49152 614 307 154 76.8 38.4 19.2 mVh
H Z 45056 563 282 141 70.4 35.2 17.6 mVh
H L 40960 512 256 128 64.0 32.0 16.0 mVh
Z H 36864 461 230 115 57.6 28.8 14.4 mVh
Z Z 33792 422 211 106 53.0 26.4 13.2 mVh
Z L 30720 384 192 96.0 48.0 24.0 12.0 mVh
L H 27648 346 173 86.4 43.2 21.6 10.8 mVh
L Z 25600 320 160 80.0 40.0 20.0 10.0 mVh
L L 22528 282 141 70.4 35.2 17.6 8.8 mVh
V
SR
is equivalent to 2
counts/sec. (nom.)
90 45 22.5 11.25 5.56 2.8 mV
Table 2. bq2012 Programmed Full Count mVh Selections
Pin
Connection
PROG
5
Self-Discharge Rate
PROG
6
Display Mode
DISP
Display State
H Self-discharge disabled NAC = PFC on reset LED disabled
Z
NAC
64
Absolute
LED enabled on discharge when
V
SRO
< -4mV or during a valid charge
L
NAC
47
Relative LED on
Note: PROG5and PROG6states are independent.
Table 1. bq2012 Programming
3. Nominal Available Charge (NAC):
NAC counts up during charge to a maximum value of LMD and down during discharge and self-discharge to 0. NAC is reset to 0 on initializa
tion (PROG
6
= Z or low) and on reaching EDV1. NAC
is set to PFC on initialization if PROG
6
= high. To prevent overstatement of charge during periods of overcharge, NAC stops incrementing when NAC = LMD.
4. Discharge Count Register (DCR):
The DCR counts up during discharge independent of NAC and could continue increasing after NAC has decremented to 0. DCR stops counting when EDV1 is reached. Prior to NAC = 0 (empty battery), both discharge and self-discharge increment the DCR. After NAC = 0, only discharge increments the DCR. The DCR resets to 0 when NAC = LMD. The DCR does not roll over but stops counting when it reaches FFFFh.
The DCR value becomes the new LMD value on the first charge after a valid discharge to V
EDV1
if:
No valid charge initiations (charges greater than 256 NAC counts; where V
SRO>VSRQ
) occurred dur­ing the period between NAC = LMD and EDV1 de­tected.
The self-discharge count is not more than 4096 counts (8% to 18% of PFC, specific percentage threshold determined by PFC).
The temperature is ≥ 0°C when the EDV1 level is reached during discharge.
The valid discharge flag (VDQ) indicates whether the present discharge is valid for LMD update.
Charge Counting
Charge activity is detected based on a positive voltage on the V
SR
input. If charge activity is detected, the
bq2012 increments NAC at a rate proportional to V
SRO
(VSR+VOS) and, if enabled, activates the LED display if the rate is equivalent to V
SRO
> 4mV. Charge actions in
The bq2012 determines charge activity sustained at a continuous rate equivalent to V
SRO>VSRQ
. A valid charge equates to sustained charge activity greater than 256 NAC counts. Once a valid charge is detected, charge counting continues until V
SRO
falls below V
SRQ.VSRQ
is a programmable threshold as described in the Digital Magnitude Filter section. The default value for V
SRQ
is 375µV.
Charge Control
Charge control is provided by the CHG output. This output is asserted continuously when:
NAC < 0.94*LMD and
0.95V < V
SB
< 2.25V and 0°C < Temp < 50°C and BRM=0
This output is asserted at a
1
16
duty cycle (low for 0.5 sec and high for 7.5 sec) when the above conditions are not met and:
NAC < LMD and
0.95V < V
SB
< 2.25V and Temp < 50°C and BRM=0
This output is also asserted at a
1
16
duty cycle (low for 0.5 sec
and high for 7.5 sec) for a 2-hour top-off period after:
NAC = LMD and Temp < 50°C and
0.95V < V
SB
< 2.25V and BRM=0
This output is inactive when:
NAC = LMD (after a 2-hour top-off period) or Temp > 50°C or V
SB
< 0.95V or
V
SB
> 2.25V or
BRM=1
The top-off timer (2 hours) is reset to allow another top­off after the battery is discharged to 0.8*LMD (PROG
6
=L)or0.8*PFC (PROG6=ZorH).
Caution: The charge control output (CHG
) should be used with other forms of charge termination such as∆T/∆t and -∆V.
If charge terminates due to maximum temperature, the battery temperature must fall typically 10°C below 50°C before the charge output becomes active again.
Discharge Counting
All discharge counts where V
SRO<VSRD
cause the NAC
register to decrement and the DCR to increment. Ex
SRO
< -4mV activates the display, if en
SRO
rises
above -4mV. V
SRD
is a programmable threshold as described in the Digital Magnitude Filter section. The default value for V
SRD
is -300µV.
7
bq2012
Self-Discharge Estimation
The bq2012 continuously decrements NAC and increments DCR for self-discharge based on time and temperature. The self-discharge count rate is programmed to be a nomi
nal
1
64
*
NAC or
1
47
*
NAC per day or disabled as selected
by PROG
5
. This is the rate for a battery whose tempera
Count Compensations
The bq2012 determines fast charge when the NAC up
Charge Compensation
Two charge efficiency compensation factors are used for trickle charge and fast charge. Fast charge is defined as a rate of charge resulting in≥2 NAC counts/sec (≥0.15C to 0.32C depending on PFC selections; see Table 2). The compensation defaults to the fast charge factor until the actual charge rate is determined.
Temperature adapts the charge rate compensation factors over three ranges between nominal, warm, and hot tem­peratures. The compensation factors are shown below.
Discharge Compensation
Corrections for the rate of discharge are made by adjusting an internal discharge compensation factor. The discharge factor is based on the dynamically measured V
SR
. The
compensation factors during discharge are:
Temperature compensation during discharge also takes place. At lower temperatures, the compensation factor increases by
0.05 for each 10°C temperature range below 10°C.
Compensation factor = 1.0 + (0.05*N)
Where N = Number of 10°C steps below 10°C and
-150mV < V
SR
<0.
For example:
T > 10°C : Nominal compensation,N = 0
0°C<T<10°C: N = 1 (i.e., 1.0 becomes 1.05)
-10°C<T<0°C:N=2(i.e., 1.0 becomes 1.10)
-20°C<T<-10°C: N = 3 (i.e., 1.0 becomes 1.15)
-20°C<T<-30°C: N = 4 (i.e., 1.0 becomes 1.20)
Self-Discharge Compensation
The self-discharge compensation is programmed for a nominal rate of
1
64
*
NAC or
1
47
*
NAC per day. This is the rate for a battery within the 20–30°C temperature range (TMPGG = 6x). This rate varies across 8 ranges from <10°C to >70°C, doubling with each higher tem
perature step (10°C). See Table 3.
Digital Magnitude Filter
The bq2012 has a programmable digital filter to eliminate charge and discharge counting below a set threshold. The de
fault setting is -0.30mV for V
SRD
and +0.38mV for V
SRQ
. The proper digital filter setting can be calculated using the following equation. Table 4 shows typical digital filter settings.
V
SRD
(mV) = -45 / DMF
V
SRQ
(mV) = -1.25*V
SRD
8
bq2012
Temperature
Step
Typical Rate
PROG
5
= Z PROG5= L
< 10°C
NAC
256
NAC
188
10–20°C
NAC
128
NAC
94
20–30°C
NAC
64
NAC
47
30–40°C
NAC
32
NAC
23 5.
40–50°C
NAC
16
NAC
11 8.
50–60°C
NAC
8
NAC
588.
Table 3. Self-Discharge Compensation
Charge
Temperature
Trickle Charge Compensation
Fast Charge
Compensation
<30°C 0.80 0.95
30– 40°C 0.75 0.90
> 40°C 0.65 0.80
Approximate
V
SR
Threshold
Discharge
Compensation
Factor Efficiency
V
SR
> -150 mV 1.00 100%
V
SR
< -150 mV 1.05 95%
DMF
DMF Hex.
V
SRD
(mV)
V
SRQ
(mV)
75 4B -0.60 0.75
100 64 -0.45 0.56
150 (default) 96 -0.30 0.38
175 AF -0.26 0.32 200 C8 -0.23 0.28
Table 4. Typical Digital Filter Settings
Error Summary
Capacity Inaccurate
The LMD is susceptible to error on initialization or if no updates occur. On initialization, the LMD value in
A Capacity Inaccurate counter (CPI) is maintained and incremented each time a valid charge occurs (qualified by NAC; see the CPI register description) and is reset whenever LMD is updated from the DCR. The counter does not wrap around but stops counting at 255. The ca
Current-Sensing Error
Table 5 illustrates the current-sensing error as a func­tion of V
SR
. A digital filter eliminates charge and dis-
charge counts to the NAC register when V
SRO(VSR
+
V
OS
) is between V
SRQ
and V
SRD
.
Communicating With the bq2012
The bq2012 includes a simple single-pin (DQ plus re­turn) serial data interface. A host processor uses the in­terface to access various bq2012 registers. Battery char
The interface uses a command-based protocol, where the host processor sends a command byte to the bq2012. The command directs the bq2012 to either store the next eight bits of data received to a register specified by the command byte or output the eight bits of data specified by the command byte.
The communication protocol is asynchronous return-to­one. Command and data bytes consist of a stream of eight bits that have a maximum transmission rate of 333 bits/sec. The least-significant bit of a command or data byte is transmitted first. The protocol is simple enough that it can be implemented by most host processors using either polled or interrupt processing. Data input from the bq2012 may be sampled using the pulse-width capture timers available on some microcontrollers.
Communication is normally initiated by the host proces
B
or greater. The DQ pin should then be returned to its normal ready-high logic state for a time, t
BR
. The bq2012 is now ready to receive
a command from the host processor.
The return-to-one data bit frame consists of three dis
STRH,B
. The next section is the actual data transmission, where the data should be valid by a period, t
DSU
, after the negative edge used to start communication. The data should be held for a period, t
DV
, to allow the host or bq2012 to
sample the data bit.
The final section is used to stop the transmission by return­ing the DQ pin to a logic-high state by at least a period, t
SSU
, after the negative edge used to start communication.
The final logic-high state should be held until a period, t
SV
,to allow time to ensure that the bit transmission was stopped properly. The timings for data and break communication are given in the serial communication timing specification and illustration sections.
Communication with the bq2012 is always performed with the least-significant bit being transmitted first. Figure 3 shows an example of a communication se
quence to read the bq2012 NAC register.
bq2012 Registers
The bq2012 command and status registers are listed in Table 6 and described in the following sections.
9
bq2012
Symbol Parameter Typical Maximum Units Notes
INL
Integrated non-linearity error
±
2
±
4
%
Add 0.1% per °C above or below 25°C and 1% per volt above or below 4.25V.
INR
Integrated non­repeatability error
±
1
±
2
%
Measurement repeatability given similar operating conditions.
Table 5. Current-Sensing Error as a Function of V
SR
10
bq2012
Symbol
Register
Name
Loc.
(hex)
Read/
Write
Control Field
7(MSB) 6543210(LSB)
CMDR
Command register
00h Write W/R
AD6 AD5 AD4 AD3 AD2 AD1 AD0
FLGS1
Primary status flags register
01h Read CHGS BRP BRM CI VDQ CHG
EDV1 EDVF
TMPGG
Temperature and gas gauge register
02h Read TMP3 TMP2 TMP1 TMP0 GG3 GG2 GG1 GG0
NACH
Nominal available charge high byte register
03h R/W NACH7 NACH6 NACH5 NACH4 NACH3 NACH2 NACH1 NACH0
NACL
Nominal available charge low byte register
17h Read NACL7 NACL6 NACL5 NACL4 NACL3 NACL2 NACL1 NACL0
BATID
Battery identification register
04h R/W BATID7 BATID6 BATID5 BATID4 BATID3 BATID2 BATID1 BATID0
LMD
Last meas­ured dis­charge regis­ter
05h R/W LMD7 LMD6 LMD5 LMD4 LMD3 LMD2 LMD1 LMD0
FLGS2
Secondary status flags register
06h Read CR DR2 DR1 DR0 n/u n/u n/u OVLD
PPD
Program pin pull-down register
07h Read n/u n/u PPD6 PPD5 PPD4 PPD3 PPD2 PPD1
PPU
Program pin pull-up regis
ter
08h Read n/u n/u PPU6 PPU5 PPU4 PPU3 PPU2 PPU1
CPI
Capacity inaccurate count register
09h Read CPI7 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 CPI0
DMF
Digital mag
0ah R/W DMF7 DMF6 DMF5 DMF4 DMF3 DMF2 DMF1 DMF0
RST Reset register 39h Write RST 0000000
Note: n/u = not used
Table 6. bq2012 Command and Status Registers
Command Register (CMDR)
The write-only CMDR register is accessed when eight valid command bits have been received by the bq2012. The CMDR register contains two fields:
■
W/R bit
■
Command address
The W/R
bit of the command register is used to select
whether the received command is for a read or a write function.
The W/R
values are:
Where W/R
is:
0 The bq2012 outputs the requested register
contents specified by the address portion of CMDR.
1 The following eight bits should be written
to the register specified by the address por
tion of CMDR.
The lower seven-bit field of CMDR contains the address portion of the register to be accessed. Attempts to write to invalid addresses are ignored.
Primary Status Flags Register (FLGS1)
The read-only FLGS1 register (address=01h) contains the primary bq2012 flags.
The charge status flag (CHGS) is asserted when a valid charge rate is detected. Charge rate is deemed valid when V
SRO>VSRQ
.AV
SRO
of less than V
SRQ
or
discharge activity clears CHGS.
The CHGS values are:
Where CHGS is:
0 Either discharge activity detected or V
SRO
<
V
SRQ
1V
SRO>VSRQ
The battery replaced flag (BRP) is asserted whenever the potential on the SB pin (relative to V
SS
), VSB, falls from above the maximum cell voltage, MCV (2.25V), or rises above 0.1V. The BRP flag is also set when the bq2012 is reset (see the RST register description). BRP is reset when either a valid charge action increments NAC to be equal to LMD, or a valid charge action is de
The BRP values are:
Where BRP is:
0 Battery is charged until NAC = LMD or dis
charged until the EDV1 flag is asserted
1V
SB
dropping from above MCV, VSBrising from below 0.1V, or a serial port initiated reset has occurred
11
bq2012
FLGS1 Bits
7654 3 2 1 0
CHGS - -- - - - -
FLGS1 Bits
7654 3 2 1 0
- BRP - - - - - -
CMDR Bits
765 4 3 2 1 0
- AD6 AD5 AD4 AD3 AD2 AD1
AD0
(LSB)
CMDR Bits
7654 3 2 1 0
W/R
- -- - - - -
TD201201.eps
DQ
Break 0 0 0 0 0 0 1 0 1 0 0 1
Written by Host to bq2012
CMDR = 03h
Received by Host to bq2012
NAC = 65h
LSB MSB LSB MSB
1110
Figure 3. Typical Communication With the bq2012
The battery removed flag (BRM) is asserted whenever the potential on the SB pin (relative to V
SS
) rises above MCV or falls below 0.1V. The BRM flag is asserted until the condition causing BRM is removed.
The BRM values are:
Where BRM is:
0 0.1V < V
SB
< 2.25V
1 0.1 V > V
SB
or VSB> 2.25V
The capacity inaccurate flag (CI) is used to warn the user that the battery has been charged a substantial number of times since LMD has been updated. The CI flag is asserted on the 64th charge after the last LMD update or when the bq2012 is reset. The flag is cleared after an LMD update.
The CI values are:
Where CI is:
0 When LMD is updated with a valid full dis-
charge
1 After the 64th valid charge action with no
LMD updates
The valid discharge flag (VDQ) is asserted when the bq2012 is discharged from NAC = LMD. The flag re
■
The self-discharge count register (SDCR) has exceeded the maximum acceptable value (4096 counts) for an LMD update.
■
A valid charge action sustained at V
SRO>VSRQ
for at
least 256 NAC counts.
■
The EDV1 flag was set at a temperature below 0°C
The VDQ values are:
Where VDQ is:
0 SDCR≥4096, subsequent valid charge ac
1 On first discharge after NAC = LMD
The charge control flag, CHG
, is asserted whenever
the CHG
pin is asserted (see the charge control section
on page 7 for a description of the CHG
pin function).
The CHG
values are:
Where CHG
is:
0 When the CHG
pin is asserted active low, signifying that the bq2012 is in a state to allow charge activity.
1 When the CHG
pin is high-impedance, sig­nifying that no charge activity should take place.
The first end-of-discharge warning flag (EDV1) warns the user that the battery is almost empty. The first segment pin, SEG
1
, is modulated at a 4Hz rate if the display is enabled once EDV1 is asserted, which should warn the user that loss of battery power is immi­nent. The EDV1 flag is latched until a valid charge has been detected.
The EDV1 values are:
Where EDV1 is:
0 Valid charge action detected, V
SB
≥
1.05V
1V
SB
< 1.05V providing that OVLD=0 (see
FLGS2 register description)
The final end-of-discharge warning flag (EDVF) flag is used to warn that battery power is at a failure condi
12
bq2012
FLGS1 Bits
7654 3 2 1 0
- - - - - CHG
--
FLGS1 Bits
7654 3 2 1 0
- - - - VDQ - - -
FLGS1 Bits
7654 3 2 1 0
- - - - - - EDV1 -
FLGS1 Bits
7654 3 2 1 0
---CI- - - -
FLGS1 Bits
7654 3 2 1 0
- - BRM - - - - -
The EDVF values are:
Where EDVF is:
0 Valid charge action detected, V
SB
≥
0.95V
1V
SB
< 0.95V providing that OVLD=0 (see
FLGS2 register description)
Temperature and Gas Gauge Register (TMPGG)
The read-only TMPGG register (address=02h) contains two data fields. The first field contains the battery tem
The bq2012 contains an internal temperature sensor. The temperature is used to set charge and discharge ef­ficiency factors as well as to adjust the self-discharge co­efficient.
The temperature register contents may be translated as shown in Table 7.
The bq2012 calculates the available charge as a function of NAC, temperature, and a full reference, either LMD or PFC. The results of the calculation are available via the display port or the gas gauge field of the TMPGG register. The register is used to give available capacity in
1
16
increments from 0 to
15
16
.
The gas gauge display and the gas gauge portion of the TMPGG register are adjusted for cold temperature de
The adjustment between > 0°C and -20°C<T<0°Chas a 10°C hysteresis.
Nominal Available Charge Registers (NACH/NACL)
The read/write NACH high-byte register (address=03h) and the read-only NACL low-byte register (address=17h) are the main gas gauging register for the bq2012. The NAC registers are incremented during charge actions and decremented during discharge and self-discharge actions. The correction factors for charge/discharge efficiency are applied automatically to NAC.
On reset, if PROG
6
= Z or low, NACH and NACL are
cleared to 0; if PROG
6
= high, NACH = PFC and NACL = 0. When the bq2012 detects a valid EDV1, NACH and NACL are reset to 0. Writing to the NAC registers affects
the available charge counts and, therefore, affects the bq2012 gas gauge operation. Do not write the NAC regis
ters to a value greater than LMD.
Battery Identification Register (BATID)
The read/write BATID register (address=04h) is avail
able for use by the system to determine the type of bat
CC
is greater than 2V. The contents of BATID have no
effect on the operation of the bq2012. There is no de
Last Measured Discharge Register (LMD)
LMD is a read/write register (address=05h) that the bq2012 uses as a measured full reference. The bq2012 adjusts LMD based on the measured discharge capacity
13
bq2012
Temperature Available Capacity Calculation
> 0°C NAC / “Full Reference”
-20°C < T < 0°C 0.75*NAC / “Full Reference”
< -20°C 0.5*NAC / “Full Reference”
TMP3 TMP2 TMP1 TMP0 Temperature
0000 T < -30°C
0001-30°C < T < -20°C
0010-20°C < T < -10°C
0011-10°C < T < 0°C
01000°C < T < 10°C
010110°C < T < 20°C
011020°C < T < 30°C
011130°C < T < 40°C
100040°C < T < 50°C
100150°C < T < 60°C
101060°C < T < 70°C
101170°C < T < 80°C
1100 T > 80°C
Table 7. Temperature Register Translation
TMPGG Temperature Bits
7 6 5 4 3210
TMP3 TMP2 TMP1 TMP0 - - -
TMPGG Gas Gauge Bits
7654 3 2 1 0
- - - - GG3 GG2 GG1 GG0
FLGS1 Bits
7654 3 2 1 0
- - - - - - - EDVF
of the battery from full to empty. In this way the bq2012 updates the capacity of the battery. LMD is set to PFC during a bq2012 reset.
Secondary Status Flags Register (FLGS2)
The read-only FLGS2 register (address=06h) contains the secondary bq2012 flags.
The charge rate flag (CR) is used to denote the fast charge regime. Fast charge is assumed whenever a charge action is initiated. The CR flag remains asserted if the charge rate does not fall below 2 counts/sec.
The CR values are:
Where CR is:
0 When charge rate falls below 2 counts/sec
1 When charge rate is above 2 counts/sec
The fast charge regime efficiency factors are used when CR = 1. When CR = 0, the trickle charge efficiency fac­tors are used. The time to change CR varies due to the user-selectable count rates.
The discharge rate flags, DR2–0, are bits 6–4.
They are used to determine the current discharge re
gime as follows:
The overload flag (OVLD) is asserted when a discharge overload is detected, V
SR
< -250mV. OVLD remains as
SR
> -250mV. The overload condition is used to stop sampling of the battery terminal characteristics for end-of-discharge determination. Sampling is re-enabled
0.5 secs after the overload condition is removed.
DR2–0 and OVLD are set based on the measurement of the voltage at the SR pin relative to V
SS
. The rate at which
this measurement is made varies with device activity.
Program Pin Pull-Down Register (PPD)
The read-only PPD register (address=07h) contains some of the programming pin information for the bq2012. The seg
ment drivers, SEG
1–6
, have a corresponding PPD register
location, PPD
1–6
. A given location is set if a pull-down re
1
and SEG4have pull-down
resistors, the contents of PPD are xx001001.
Program Pin Pull-Up Register (PPU)
The read-only PPU register (address=08h) contains the rest of the programming pin information for the bq2012. The segment drivers, SEG
1–6
, have a corre
1–6
. A given loca
3
and
SEG
6
have pull-up resistors, the contents of PPU are
xx100100.
Capacity Inaccurate Count Register (CPI)
The read-only CPI register (address=09h) is used to in
The CPI register is incremented every time a valid charge is detected if NAC < 0.94*LMD. When NAC
≥
0.94*LMD, the CPI register increments on the first valid charge; CPI does not increment again for a valid charge until NAC is discharged below 0.94*LMD. This prevents continuous trickle charging from incrementing CPI if self-discharge decrements NAC. The CPI register increments to 255 without rolling over. When the con
14
bq2012
FLGS2 Bits
7654 3 2 1 0
- - - - - - - OVLD
PPD/PPU Bits
87654321
- - PPU
6
PPU5PPU4PPU3PPU2PPU
1
- - PPD6PPD5PPD4PPD3PPD2PPD
1
FLGS2 Bits
7654 3 2 1 0
CR - - - - - - -
FLGS2 Bits
7 6 5 4 3210
- DR2 DR1 DR0 - - -
DR2 DR1 DR0 VSR(V)
000 V
SR
> -150mV
001 V
SR
< -150mV
Digital Magnitude Filter (DMF)
The read-write DMF register (address = 0ah) provides the system with a means to change the default settings of the digital magnitude filter. By writing different val
ues into this register, the limits of V
SRD
and V
SRQ
can be
adjusted.
Note: Care should be taken when writing to this regis
ter. A V
SRD
and V
SRQ
below the specified VOSmay ad
Reset Register (RST)
The reset register (address=39h) provides the means to perform a software-controlled reset of the device. By writing the RST register contents from 00h to 80h, a bq2012 reset is performed. Setting any bit other than the
most-significant bit of the RST register is not allowed, and results in improper operation of the bq2012.
Resetting the bq2012 sets the following:
■
LMD = PFC
■
CPI, VDQ, NACH, and NACL = 0
■
CI and BRP = 1
Note: NACH = PFC when PROG
6
=H.
Display
The bq2012 can directly display capacity information us­ing low-power LEDs. If LEDs are used, the program pins should be resistively tied to V
CC
or VSSfor a pro
The bq2012 displays the battery charge state in either absolute or relative mode. In relative mode, the battery charge is represented as a percentage of the LMD. Each LED segment represents 20% of the LMD. The sixth segment is not used.
In absolute mode, each segment represents a fixed amount of charge, based on the initial PFC. In absolute mode, each segment represents 20% of the PFC, with the sixth segment representing “overfull” (charge above the PFC). As the battery wears out over time, it is pos
The capacity display is also adjusted for the present bat
When DISP
is tied to VCC, the SEG
1–6
outputs are inac
is left floating, the display becomes ac
SRO
< -4mV or V
SRO>VSRQ
. When
pulled low, the segment outputs become active immedi
allows the display to re
The segment outputs are modulated as two banks of three, with segments 1, 3, and 5 alternating with seg­ments 2, 4, and 6. The segment outputs are modulated at approximately 100Hz with each segment bank active for 30% of the period.
SEG
1
blinks at a 4Hz rate whenever VSBhas been de-
tected to be below V
EDV1
(EDV1 = 1), indicating a low-
battery condition. V
SB
below V
EDVF
(EDVF = 1) disables
the display output.
Microregulator
The bq2012 can operate directly from three or four cells. To facilitate the power supply requirements of the bq2012, an REF output is provided to regulate an exter
15
bq2012
16
bq2012
Absolute Maximum Ratings
Symbol Parameter Minimum Maximum Unit Notes
V
CC
Relative to V
SS
-0.3 7.0 V
All other pins Relative to V
SS
-0.3 7.0 V
REF Relative to V
SS
-0.3 8.5 V Current limited by R1 (see Figure 1)
V
SR
Relative to V
SS
-0.3 7.0 V
Minimum 100Ωseries resistor should be used to protect SR in case of a shorted battery (see the bq2012 appli
cation note for details).
T
OPR
Operating tempera
ture
0 70 °C Commercial
-40 85 °C Industrial
Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional opera
tion should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Expo
sure to conditions beyond the operational limits for extended periods of time may affect device reliability.
DC Voltage Thresholds (T
A
= T
OPR
; V = 3.0 to 6.5V)
Symbol Parameter Minimum Typical Maximum Unit Notes
V
EDVF
Final empty warning 0.93 0.95 0.97 V SB
V
EDV1
First empty warning 1.03 1.05 1.07 V SB
V
SR1
Discharge compensation threshold -120 -150 -180 mV
SR, V
SR
+ VOS(see
note 2)
V
ORD
Overload threshold -230 -250 -280 mV SR, VSR+ V
OS
V
SRO
SR sense range -300 - +2000 mV SR, VSR+ V
OS
V
SRQ
Valid charge 375 - -
µ
VVSR+VOS(see note 1)
V
SRD
Valid discharge - - -300
µ
VVSR+VOS(see note 1)
V
MCV
Maximum single-cell voltage 2.20 2.25 2.30 V SB
V
BR
Battery removed/replaced
- 0.1 0.25 V SB pulled low
2.20 2.25 2.30 V SB pulled high
Notes: 1. Default value; value set in DMF register. VOSis affected by PC board layout. Proper layout
guidelines should be followed for optimal performance. See “LayoutConsiderations.”
2. Proper threshold measurements require V
CC
to be more than 1.5V greater than the desired signal
value.
17
bq2012
DC Electrical Characteristics (T
A
=T
OPR
Symbol Parameter Minimum Typical Maximum Unit Notes
V
CC
Supply voltage 3.0 4.25 6.5 V
V
CC
excursion from < 2.0V to
≥
3.0V initializes the unit.
V
OS
Offset referred to V
SR
±50
±150
µV
DISP
=V
CC
V
REF
Reference at 25°C 5.7 6.0 6.3 V I
REF
= 5µA
Reference at -40°C to +85°C 4.5 - 7.5 V I
REF
= 5µA
R
REF
Reference input impedance 2.0 5.0 - MΩV
REF
= 3V
I
CC
Normal operation
- 90 135
µ
AV
CC
= 3.0V
- 120 180
µ
AV
CC
= 4.25V
- 170 250
µ
AV
CC
= 6.5V
V
SB
Battery input - - 2.4 V
R
SBmax
SB input impedance 10 - - MΩ0 < VSB<V
CC
I
DISP
DISP input leakage - - 5
µ
AV
DISP=VSS
I
LCOM
LCOM input leakage -0.2 - 0.2
µ
A DISP =V
CC
R
DQ
Internal pulldown 500 - - K
Ω
V
SR
Sense resistor input -0.3 - 2.0 V
V
SR<VSS
= discharge;
V
SR>VSS
= charge
R
SR
SR input impedance 10 - - MΩ-200mV < VSR<V
CC
V
IH
Logic input high VCC- 0.2 - - V PROG1–PROG
6
V
IL
Logic input low - - VSS+ 0.2 V PROG1–PROG
6
V
IZ
Logic input Z float - float V PROG1–PROG
6
V
OLSL
SEGXoutput low, low V
CC
- 0.1 - V
V
CC
= 3V, I
OLS
≤
1.75mA
SEG
1
–SEG
6
V
OLSH
SEGXoutput low, high V
CC
- 0.4 - V
V
CC
= 6.5V, I
OLS
≤
11.0mA
SEG
1
–SEG
6
V
OHLCL
LCOM output high, low V
CC
VCC- 0.3 - - V VCC= 3V, I
OHLCOM
= -5.25mA
V
OHLCH
LCOM output high, high V
CC
VCC- 0.6 - - V VCC= 6.5V, I
OHLCOM
= -33.0mA
I
IH
PROG
1-6
input high current - 1.2 -
µ
AV
PROG=VCC
/2
I
IL
PROG
1-6
input low current - 1.2 -
µ
AV
PROG=VCC
/2
I
OHLCOM
LCOM source current -33 - - mA At V
OHLCH=VCC
- 0.6V
I
OLS
SEGXsink current - - 11.0 mA At V
OLSH
= 0.4V
I
OL
Open-drain sink current - - 5.0 mA
At V
OL=VSS
+ 0.3V
DQ, EMPTY, CHG
V
OL
Open-drain output low - - 0.5 V I
OL
≤
5mA, DQ, EMPTY
V
IHDQ
DQ input high 2.5 - - V DQ
V
ILDQ
DQ input low - - 0.8 V DQ
R
PROG
Soft pull-up or pull-down resis
tor value (for programming)
- - 200
K
Ω
PROG
1
–PROG
6
R
FLOAT
Float state external impedance - 5 - MΩPROG1–PROG
6
Note: All voltages relative to VSS.
18
bq2012
Serial Communication Timing Specification
Symbol Parameter Minimum Typical Maximum Unit Notes
t
CYCH
Cycle time, host to bq2012 3 - - ms See note
t
CYCB
Cycle time, bq2012 to host 3 - 6 ms
t
STRH
Start hold, host to bq2012 5 - - ns
t
STRB
Start hold, bq2012 to host 500 - -
µ
s
t
DSU
Data setup - - 750
µ
s
t
DH
Data hold 750 - -
µ
s
t
DV
Data valid 1.50 - - ms
t
SSU
Stop setup - - 2.25 ms
t
SH
Stop hold 700 - -
µ
s
t
SV
Stop valid 2.95 - - ms
t
B
Break 3 - - ms
t
BR
Break recovery 1 - - ms
Note: The open-drain DQ pin should be pulled to at least VCCby the host system for proper DQ operation.
DQ may be left floating if the serial interface is not used.
TD201002.eps
DQ
(R/W "1")
t
STRH
t
STRB
t
DSU
t
DH
t
DV
t
SV
t
SSU
t
SH
t
CYCH, tCYCB, tB
t
BR
DQ
(R/W "0")
DQ
(BREAK)
Serial Communication Timing Illustration
19
16-Pin SOIC Narrow (SN)
A
A1
.004
C
B
e
D
E
H
L
16-Pin SN(0.150" SOIC
)
Dimension
Inches Millimeters
Min. Max. Min. Max.
A 0.060 0.070 1.52 1.78
A1 0.004 0.010 0.10 0.25
B 0.013 0.020 0.33 0.51
C 0.007 0.010 0.18 0.25
D 0.385 0.400 9.78 10.16
E 0.150 0.160 3.81 4.06
e 0.045 0.055 1.14 1.40
H 0.225 0.245 5.72 6.22
L 0.015 0.035 0.38 0.89
bq2012
Data Sheet Revision History
Change No. Page No. Description Nature of Change
1 7 Addition to Table 2 Added bottom row
Note: Change 1 = Sept. 1996 B changes from July 1994.
bq2012
Package Option:
SN = 16-pin narrow SOIC
Device:
bq2012 Gas Gauge IC
Temperature Range:
blank = Commercial (0 to +70°C) N = Industrial (-40 to +85°C)*
Ordering Information
* Contact factory for availability.
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICA TIONS IS UNDERSTOOD T O BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
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